STM32F2: Add timer support.

Standard series peripheral support patch, containing STM32F2 series
timer.h and timer.c.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

3 files changed, 356 insertions, 0 deletions

diff --git a/libmaple/stm32f2/include/series/timer.h b/libmaple/stm32f2/include/series/timer.h
new file mode 100644
index 0000000..cf7cc15
--- /dev/null
+++ b/libmaple/stm32f2/include/series/timer.h
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011,2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   stm32f2/include/series/timer.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  STM32F2 timer sub-header.
+ */
+
+#ifndef _LIBMAPLE_STM32F2_TIMER_H_
+#define _LIBMAPLE_STM32F2_TIMER_H_
+
+#include <libmaple/libmaple_types.h>
+
+/*
+ * Register maps and base pointers
+ */
+
+/**
+ * @brief STM32F2 general purpose timer register map type
+ *
+ * Note that not all general purpose timers have all of these
+ * registers. Consult your chip's reference manual for the details.
+ */
+typedef struct timer_gen_reg_map {
+    __io uint32 CR1;            /**< Control register 1 */
+    __io uint32 CR2;            /**< Control register 2 */
+    __io uint32 SMCR;           /**< Slave mode control register */
+    __io uint32 DIER;           /**< DMA/Interrupt enable register */
+    __io uint32 SR;             /**< Status register */
+    __io uint32 EGR;            /**< Event generation register  */
+    __io uint32 CCMR1;          /**< Capture/compare mode register 1 */
+    __io uint32 CCMR2;          /**< Capture/compare mode register 2 */
+    __io uint32 CCER;           /**< Capture/compare enable register */
+    __io uint32 CNT;            /**< Counter */
+    __io uint32 PSC;            /**< Prescaler */
+    __io uint32 ARR;            /**< Auto-reload register */
+    const uint32 RESERVED1;     /**< Reserved */
+    __io uint32 CCR1;           /**< Capture/compare register 1 */
+    __io uint32 CCR2;           /**< Capture/compare register 2 */
+    __io uint32 CCR3;           /**< Capture/compare register 3 */
+    __io uint32 CCR4;           /**< Capture/compare register 4 */
+    const uint32 RESERVED2;     /**< Reserved */
+    __io uint32 DCR;            /**< DMA control register */
+    __io uint32 DMAR;           /**< DMA address for full transfer */
+    __io uint32 OR;             /**< Option register. */
+} timer_gen_reg_map;
+
+struct timer_adv_reg_map;
+struct timer_gen_reg_map;
+struct timer_bas_reg_map;
+
+/** Timer 1 register map base pointer */
+#define TIMER1_BASE                     ((struct timer_adv_reg_map*)0x40010000)
+/** Timer 2 register map base pointer */
+#define TIMER2_BASE                     ((struct timer_gen_reg_map*)0x40000000)
+/** Timer 3 register map base pointer */
+#define TIMER3_BASE                     ((struct timer_gen_reg_map*)0x40000400)
+/** Timer 4 register map base pointer */
+#define TIMER4_BASE                     ((struct timer_gen_reg_map*)0x40000800)
+/** Timer 5 register map base pointer */
+#define TIMER5_BASE                     ((struct timer_gen_reg_map*)0x40000C00)
+/** Timer 6 register map base pointer */
+#define TIMER6_BASE                     ((struct timer_bas_reg_map*)0x40001000)
+/** Timer 7 register map base pointer */
+#define TIMER7_BASE                     ((struct timer_bas_reg_map*)0x40001400)
+/** Timer 8 register map base pointer */
+#define TIMER8_BASE                     ((struct timer_adv_reg_map*)0x40010400)
+/** Timer 9 register map base pointer */
+#define TIMER9_BASE                     ((struct timer_gen_reg_map*)0x40014000)
+/** Timer 10 register map base pointer */
+#define TIMER10_BASE                    ((struct timer_gen_reg_map*)0x40014400)
+/** Timer 11 register map base pointer */
+#define TIMER11_BASE                    ((struct timer_gen_reg_map*)0x40014800)
+/** Timer 12 register map base pointer */
+#define TIMER12_BASE                    ((struct timer_gen_reg_map*)0x40001800)
+/** Timer 13 register map base pointer */
+#define TIMER13_BASE                    ((struct timer_gen_reg_map*)0x40001C00)
+/** Timer 14 register map base pointer */
+#define TIMER14_BASE                    ((struct timer_gen_reg_map*)0x40002000)
+
+/*
+ * Register bit definitions
+ */
+
+/* TIM2 option register */
+
+/** Timer 2 option register internal trigger 1 remap */
+#define TIMER2_OR_ITR1_RMP              (0x3 << 10)
+/** Timer 2 OR internal trigger 1: TIM8_TRGOUT */
+#define TIMER2_OR_ITR1_RMP_TIM8_TRGOUT  (0x0 << 10)
+/** Timer 2 OR internal trigger 1: Ethernet PTP trigger output */
+#define TIMER2_OR_ITR1_RMP_PTP_TRGOUT   (0x1 << 10)
+/** Timer 2 OR internal trigger 1: USB OTG full speed start of frame */
+#define TIMER2_OR_ITR1_RMP_OTG_FS_SOF   (0x2 << 10)
+/** Timer 2 OR internal trigger 1: USB OTG high speed start of frame */
+#define TIMER2_OR_ITR1_RMP_OTG_HS_SOF   (0x3 << 10)
+
+/* TIM5 option register */
+
+/**
+ * Timer 5 option register input 4 remap.
+ *
+ * These bits control whether TIM5_CH4 is connected to a GPIO or a
+ * clock. Connecting to a GPIO is the normal mode, useful for e.g. PWM
+ * generation or input pulse duration measurement. Connecting to a
+ * clock is useful for calibrating that clock.
+ */
+#define TIMER5_OR_TI4_RMP               (0x3 << 6)
+/**
+ * Timer 5 OR input 4: Timer 5 channel 4 connected to GPIO. */
+#define TIMER5_OR_TI4_RMP_GPIO          (0x0 << 6)
+/**
+ * Timer 5 OR input 4: low speed internal clock (LSI) is connected to
+ * TIM5_CH4. */
+#define TIMER5_OR_TI4_RMP_LSI           (0x1 << 6)
+/**
+ * Timer 5 OR input 4: low speed external clock (LSE) is connected to
+ * TIM5_CH4. */
+#define TIMER5_OR_TI4_RMP_LSE           (0x2 << 6)
+/**
+ * Timer 5 OR input 4: real time clock (RTC) output is connected to
+ * TIM5_CH4. */
+#define TIMER5_OR_TI4_RMP_RTC           (0x3 << 6)
+
+/*
+ * Device pointers
+ */
+
+struct timer_dev;
+
+extern struct timer_dev *TIMER1;
+extern struct timer_dev *TIMER2;
+extern struct timer_dev *TIMER3;
+extern struct timer_dev *TIMER4;
+extern struct timer_dev *TIMER5;
+extern struct timer_dev *TIMER6;
+extern struct timer_dev *TIMER7;
+extern struct timer_dev *TIMER8;
+extern struct timer_dev *TIMER9;
+extern struct timer_dev *TIMER10;
+extern struct timer_dev *TIMER11;
+extern struct timer_dev *TIMER12;
+extern struct timer_dev *TIMER13;
+extern struct timer_dev *TIMER14;
+
+#endif
diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk
index 5951b94..c98f5b9 100644
--- a/libmaple/stm32f2/rules.mk
+++ b/libmaple/stm32f2/rules.mk
@@ -15,6 +15,7 @@ cSRCS_$(d) := adc.c
 cSRCS_$(d) += fsmc.c
 cSRCS_$(d) += gpio.c
 cSRCS_$(d) += rcc.c
+cSRCS_$(d) += timer.c
 cSRCS_$(d) += usart.c
 
 sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%)
diff --git a/libmaple/stm32f2/timer.c b/libmaple/stm32f2/timer.c
new file mode 100644
index 0000000..eed7810
--- /dev/null
+++ b/libmaple/stm32f2/timer.c
@@ -0,0 +1,185 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   libmaple/stm32f2/timer.c
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  STM32F2 timer support.
+ */
+
+#include <libmaple/timer.h>
+#include "timer_private.h"
+
+/*
+ * Devices
+ *
+ * Defer to the timer_private API for declaring these.
+ */
+
+static DECLARE_ADVANCED_TIMER(timer1, 1);
+static DECLARE_GENERAL_TIMER(timer2, 2);
+static DECLARE_GENERAL_TIMER(timer3, 3);
+static DECLARE_GENERAL_TIMER(timer4, 4);
+static DECLARE_GENERAL_TIMER(timer5, 5);
+static DECLARE_BASIC_TIMER(timer6, 6);
+static DECLARE_BASIC_TIMER(timer7, 7);
+static DECLARE_ADVANCED_TIMER(timer8, 8);
+/* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */
+static DECLARE_RESTRICTED_GENERAL_TIMER(timer9, 9, TIMER_DIER_TIE_BIT);
+/* TIM10 has UIE, CC1IE. */
+static DECLARE_RESTRICTED_GENERAL_TIMER(timer10, 10, TIMER_DIER_CC1IE_BIT);
+/* TIM11 has UIE, CC1IE. */
+static DECLARE_RESTRICTED_GENERAL_TIMER(timer11, 11, TIMER_DIER_CC1IE_BIT);
+/* TIM12 has UIE, CC1IE, CC2IE, TIE. */
+static DECLARE_RESTRICTED_GENERAL_TIMER(timer12, 12, TIMER_DIER_TIE_BIT);
+/* TIM13 has UIE, CC1IE. */
+static DECLARE_RESTRICTED_GENERAL_TIMER(timer13, 13, TIMER_DIER_CC1IE_BIT);
+/* TIM14 has UIE, CC1IE. */
+static DECLARE_RESTRICTED_GENERAL_TIMER(timer14, 14, TIMER_DIER_CC1IE_BIT);
+
+/** Timer 1 device (advanced) */
+timer_dev *TIMER1 = &timer1;
+/** Timer 2 device (general-purpose) */
+timer_dev *TIMER2 = &timer2;
+/** Timer 3 device (general-purpose) */
+timer_dev *TIMER3 = &timer3;
+/** Timer 4 device (general-purpose) */
+timer_dev *TIMER4 = &timer4;
+/** Timer 5 device (general-purpose) */
+timer_dev *TIMER5 = &timer5;
+/** Timer 6 device (basic) */
+timer_dev *TIMER6 = &timer6;
+/** Timer 7 device (basic) */
+timer_dev *TIMER7 = &timer7;
+/** Timer 8 device (advanced) */
+timer_dev *TIMER8 = &timer8;
+/** Timer 9 device (general-purpose) */
+timer_dev *TIMER9 = &timer9;
+/** Timer 10 device (general-purpose) */
+timer_dev *TIMER10 = &timer10;
+/** Timer 11 device (general-purpose) */
+timer_dev *TIMER11 = &timer11;
+/** Timer 12 device (general-purpose) */
+timer_dev *TIMER12 = &timer12;
+/** Timer 13 device (general-purpose) */
+timer_dev *TIMER13 = &timer13;
+/** Timer 14 device (general-purpose) */
+timer_dev *TIMER14 = &timer14;
+
+/*
+ * Routines
+ */
+
+/**
+ * @brief Call a function on timer devices.
+ * @param fn Function to call on each timer device.
+ */
+void timer_foreach(void (*fn)(timer_dev*)) {
+    fn(TIMER1);
+    fn(TIMER2);
+    fn(TIMER3);
+    fn(TIMER4);
+    fn(TIMER5);
+    fn(TIMER6);
+    fn(TIMER7);
+    fn(TIMER8);
+    fn(TIMER9);
+    fn(TIMER10);
+    fn(TIMER11);
+    fn(TIMER12);
+    fn(TIMER13);
+    fn(TIMER14);
+}
+
+/*
+ * IRQ handlers
+ *
+ * Defer to the timer_private dispatch API.
+ */
+
+void __irq_tim1_brk_tim9(void) {
+    dispatch_adv_brk(TIMER1);
+    dispatch_tim_9_12(TIMER9);
+}
+
+void __irq_tim1_up_tim10(void) {
+    dispatch_adv_up(TIMER1);
+    dispatch_tim_10_11_13_14(TIMER10);
+}
+
+void __irq_tim1_trg_com_tim11(void) {
+    dispatch_adv_trg_com(TIMER1);
+    dispatch_tim_10_11_13_14(TIMER11);
+}
+
+void __irq_tim1_cc(void) {
+    dispatch_adv_cc(TIMER1);
+}
+
+void __irq_tim2(void) {
+    dispatch_general(TIMER2);
+}
+
+void __irq_tim3(void) {
+    dispatch_general(TIMER3);
+}
+
+void __irq_tim4(void) {
+    dispatch_general(TIMER4);
+}
+
+void __irq_tim5(void) {
+    dispatch_general(TIMER5);
+}
+
+/* FIXME: this is also the DAC DMA underrun interrupt, so it needs a
+ * different name (and to be supported?). */
+void __irq_tim6(void) {
+    dispatch_basic(TIMER6);
+}
+
+void __irq_tim7(void) {
+    dispatch_basic(TIMER7);
+}
+
+void __irq_tim8_brk_tim12(void) {
+    dispatch_adv_brk(TIMER8);
+    dispatch_tim_9_12(TIMER12);
+}
+
+void __irq_tim8_up_tim13(void) {
+    dispatch_adv_up(TIMER8);
+    dispatch_tim_10_11_13_14(TIMER13);
+}
+
+void __irq_tim8_trg_com_tim14(void) {
+    dispatch_adv_trg_com(TIMER8);
+    dispatch_tim_10_11_13_14(TIMER14);
+}
+
+void __irq_tim8_cc(void) {
+    dispatch_adv_cc(TIMER8);
+}