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| author | Andrew J Meyer <ajm@leaflabs.com> | 2013-03-06 18:47:43 -0500 |
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| committer | Andrew J Meyer <ajm@leaflabs.com> | 2013-03-06 18:47:43 -0500 |
| commit | 0754c0f771c51d48107c5c96d79a512ce56cce0a (patch) | |
| tree | d444913b56cc430f6c4b6050af6226e669919438 /synth_project/project.ucf | |
| parent | 25e9b58c4a438292e9d07151c0f2ce73d1ed64f8 (diff) | |
| download | fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.tar.gz fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.zip | |
added the base files
Diffstat (limited to 'synth_project/project.ucf')
| -rwxr-xr-x | synth_project/project.ucf | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/synth_project/project.ucf b/synth_project/project.ucf new file mode 100755 index 0000000..322c05a --- /dev/null +++ b/synth_project/project.ucf @@ -0,0 +1,21 @@ +NET "PUSH_BUTTON_RESET_RAW" LOC = F3; + +#100MHz clock +NET "SYSTEMCLOCK" LOC = K21; + +NET "Switch_input_0" LOC = C18; +NET "Switch_input_1" LOC = Y6; +NET "Switch_input_2" LOC = W6; +NET "Switch_input_3" LOC = E4; + +NET "LED_output_1" LOC = D17; +NET "LED_output_2" LOC = AB4; +NET "LED_output_4" LOC = D21; +NET "LED_output_5" LOC = W15; + +# Defines the external differential clock to be 150 MHz with 50% duty +# cycle. + +NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK"; +TIMESPEC TS__SYSTEMCLOCK = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50 % PRIORITY 2; + |