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BUG: synth still seems to continue even if first build (verilog compile) fails
For bitfile/mcs targets, add an echo that they are being created (slow).
requests from AJ:
anything related to not rebuilding all the coregen when not necessary.
e.g. want a make clean equivalent to removing the build dir but not the
cores. This should actually be the default behavior, with different
operator for nixing the cores.
not auto rebuilding the cores when switching branches/commits if not
strictly necessary. Because git touches all the files, this may be
difficult.
make isim/simulate will run to completion even if there were errors on
the build.
In the case of make isim, isim will load and run the previously valid
simulation. Unless you happen to see the error go by in the build log,
you will unknowingly be simulating your previous build, whereas your
current build failed to compile.
The solution is to have make simulate begin by deleting the previous
simulation executable, so that it must successfully create a new one
before loading isim.
--- later...
effort levels seem high by default:
Overall effort level (-ol): High
Router effort level (-rl): High
-> 'make quicksynth' ?
add support for post-synthesis simulation
autoimpact (needs testing)
impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing)
Add linting to tests (aka, tb/*_tb.v)
'lint' should use vfiles, not -I./hdl
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