index
:
basic-hdl-template
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
*
minor cleanup of lint target
bryan newbold
2013-11-12
1
-1
/
+1
*
fold BUGS into TODO.template
bryan newbold
2013-11-12
2
-2
/
+2
*
initial VHDL support
bryan newbold
2013-11-12
2
-4
/
+19
*
add old TODO requests from AJ
bryan newbold
2013-10-29
1
-0
/
+25
*
need to specify .pcf file to bitgen for some cases
bryan newbold
2013-10-21
1
-1
/
+1
*
commit TODO list
bryan newbold
2013-10-09
1
-0
/
+18
*
fix up minor xula2 typos
bryan newbold
2013-10-09
2
-2
/
+1
*
refactor project -> exampleproj
bryan newbold
2013-10-09
4
-367
/
+1
*
partially fix bug where synthesis continues after .ngc failure
bryan newbold
2013-10-09
1
-0
/
+2
*
clean up main_xula2 a bit
bryan newbold
2013-10-09
1
-3
/
+6
*
move around device-specific Makefile includes for easier target swapping
bryan newbold
2013-10-09
1
-2
/
+5
*
spruce up sp605 build target
bryan newbold
2013-10-09
3
-30
/
+527
*
basic rot13 UART demo working
bryan newbold
2013-10-08
3
-0
/
+239
*
clean up test stuff
bryan newbold
2013-10-08
9
-112
/
+189
*
working xula2 sim/syn/prog system
bryan newbold
2013-10-08
11
-18
/
+289
*
don't have outputs depend on makefiles
bryan newbold
2013-10-08
1
-3
/
+3
*
linting: ignore module/filename equivalence
bryan newbold
2013-10-06
1
-1
/
+1
*
add test/ and isim/ system
bryan newbold
2013-10-06
10
-63
/
+214
*
fix old tb/tb.v
bryan newbold
2013-10-04
1
-15
/
+6
*
add concept of 'board' for seperate ucfs and top level modules
bryan newbold
2013-10-04
5
-24
/
+34
*
add autoimpact target (pre-select bitfile)
bryan newbold
2013-10-04
1
-0
/
+3
*
generic timingan target
bryan newbold
2013-10-04
1
-0
/
+3
*
backport improvements from SNG project
bryan newbold
2013-10-04
2
-3
/
+8
*
changed build-commits to have one argument
Andrew J Meyer
2013-08-19
1
-3
/
+9
*
added build commits script
Andrew J Meyer
2013-08-19
1
-0
/
+31
*
typo: pre-par .ncd file for partial_timing analysis
bryan newbold
2013-06-27
1
-1
/
+1
*
parameterize unconstrained timing analysis
bryan newbold
2013-06-27
1
-2
/
+3
*
commit an .xco as an example of stripped project metadata
bryan newbold
2013-06-27
1
-0
/
+76
*
a better minimalist project, including a timing constraint
bryan newbold
2013-06-27
2
-31
/
+39
*
fix bugs with trce and par
bryan newbold
2013-06-27
1
-4
/
+4
*
break out synth_effort as a variable
bryan newbold
2013-06-27
1
-2
/
+3
*
fix potential problem with old etwr target
bryan newbold
2013-06-27
1
-1
/
+1
*
add planahead, fpga_editor, and timing targets
bryan newbold
2013-06-27
1
-13
/
+31
*
very minor style tweaks from downstream repos
bryan newbold
2013-06-19
3
-2
/
+3
*
don't re-coregen after every little Makefile tweak
bryan newbold
2013-06-19
2
-1
/
+4
*
proper Makefile syntax; device-specific; mcs bitwidth
bryan newbold
2013-06-19
3
-16
/
+32
*
be more explicit about listing .v files
bryan newbold
2013-06-06
1
-0
/
+3
*
BUGS
bryan newbold
2013-06-05
1
-0
/
+1
*
add 'make lint' verilog-build command; requires verilator
bryan newbold
2013-06-05
1
-1
/
+4
*
README: fix typo.
Marti Bolivar
2013-04-26
1
-1
/
+1
*
update README, comments, .xise project file
bryan newbold
2013-04-26
3
-12
/
+56
*
update with bnewbold's changes
bryan newbold
2013-03-27
3
-76
/
+68
*
initial colorization stuff
bryan newbold
2013-03-27
2
-1
/
+105
*
compile in multiple tb-modules (this might slow things down for you)
bryan newbold
2013-03-21
1
-2
/
+6
*
add .ucf file reference
bryan newbold
2013-03-21
1
-1
/
+1
*
isim in the background; hackisly fix deps
bryan newbold
2013-03-20
1
-4
/
+4
*
fix 'main' in tb.v
bryan newbold
2013-03-20
1
-1
/
+1
*
fixes to simulate
bryan newbold
2013-03-20
1
-8
/
+6
*
Corrects comments (clock is 200MHz, not 100MHz) and removed incorrect clock t...
jesstherobot
2013-03-20
1
-7
/
+1
*
'main', not 'project' top module by default
bryan newbold
2013-03-14
2
-3
/
+3
[next]