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authorbryan newbold <bnewbold@leaflabs.com>2013-10-09 00:31:49 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-10-09 00:31:49 -0400
commit078932696fc9f8ec97e6efddea3019f4cb0669a9 (patch)
tree0f8be76c5b6e5a905eafeebf69cca3d599371a2a
parent58a4d81047891bf2bcfaa141f81b4ea34f0c3594 (diff)
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commit TODO list
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+
+switch to .EXPORT_ALL_VARIABLES and/or .ONESHELL (as a refactor/cleanup)?
+ or is that too gmake specific...
+
+BUG: synth still seems to continue even if first build (verilog compile)
+ fails
+
+add .PRECIOUS for intermediate files we don't want to get deleted
+
+for fpga_editor:
+ DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file>
+
+effort levels seem high by default:
+ Overall effort level (-ol): High
+ Router effort level (-rl): High
+
+impact:
+ impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing)