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authorbryan newbold <bnewbold@leaflabs.com>2013-11-13 12:46:10 -0500
committerbryan newbold <bnewbold@leaflabs.com>2013-11-13 12:46:10 -0500
commitcf6d724d536a77280e122a1dd3c03b2b8aa3b3c5 (patch)
tree47b4f462af88b35cd9e86bd2012b4dc968c547ea /contrib
parentc1c89f3cbc619b6b5ff000cdfcef743fca6900ea (diff)
downloadbasic-hdl-template-cf6d724d536a77280e122a1dd3c03b2b8aa3b3c5.tar.gz
basic-hdl-template-cf6d724d536a77280e122a1dd3c03b2b8aa3b3c5.zip
update TODO list
Diffstat (limited to 'contrib')
-rw-r--r--contrib/TODO33
1 files changed, 2 insertions, 31 deletions
diff --git a/contrib/TODO b/contrib/TODO
index 9c10050..e7f26c2 100644
--- a/contrib/TODO
+++ b/contrib/TODO
@@ -1,36 +1,7 @@
-rename repo...
- hdl-build
- basic-hdl-project
+rename repo "basic-hdl-project"
-cleanup simple_uart.v
-
-BUG: synth still seems to continue even if first build (verilog compile) fails
-
-requests from AJ:
- anything related to not rebuilding all the coregen when not necessary.
-
- e.g. want a make clean equivalent to removing the build dir but not the
- cores. This should actually be the default behavior, with different
- operator for nixing the cores.
-
- not auto rebuilding the cores when switching branches/commits if not
- strictly necessary. Because git touches all the files, this may be
- difficult.
-
- make isim/simulate will run to completion even if there were errors on
- the build.
-
- In the case of make isim, isim will load and run the previously valid
- simulation. Unless you happen to see the error go by in the build log,
- you will unknowingly be simulating your previous build, whereas your
- current build failed to compile.
-
- The solution is to have make simulate begin by deleting the previous
- simulation executable, so that it must successfully create a new one
- before loading isim.
-
---- later...
+cleanup simple_uart.v (remove warnings)
effort levels seem high by default:
Overall effort level (-ol): High