Part 3 of refactoring template files into ./contrib

Docs!

3 files changed, 70 insertions, 0 deletions

diff --git a/contrib/HOWTO.coregen b/contrib/HOWTO.coregen
new file mode 100644
index 0000000..d679d23
--- /dev/null
+++ b/contrib/HOWTO.coregen
@@ -0,0 +1,13 @@
+
+== HOWTO Coregen =============================================================
+
+Run `make coregen` and use the GUI to generate a core.
+
+Depending on the output, copy .v files to hdl/ and/or .xco files to cores/.
+update the Makefile.
+
+For any .xco files, strip the "Project Options" section and the final CRC line.
+
+After making any changes to the target chipset (eg, by modifying Makefile),
+you'll need to do a 'make clean' to ensure that the coregen logic is
+resynthesized correctly.
diff --git a/contrib/README.tb_test b/contrib/HOWTO.testbench
index 3be00d6..3be00d6 100644
--- a/contrib/README.tb_test
+++ b/contrib/HOWTO.testbench
diff --git a/contrib/QUICK_START.txt b/contrib/QUICK_START.txt
new file mode 100644
index 0000000..852f11c
--- /dev/null
+++ b/contrib/QUICK_START.txt
@@ -0,0 +1,57 @@
+#!/usr/bin/env sh
+
+# Note: you can either follow the directions in this file, or just run it like:
+#
+#   sh ./contrib/QUICK_START.txt
+#
+# Make sure we are where we think we are; eg don't run this from the ./contrib
+# folder. Also, fail hard.
+set -e
+test -f ./contrib/QUICK_START.txt
+
+###############################################################################
+############## The Verilog Build Project Template Quick Start! ################
+###############################################################################
+
+# Move Makefile.example to Makefile and edit it. At least set a project name
+# and chose a board.
+# If you are using a board for which there does not (yet) exist a template in
+# ./contrib, you'll need to create a ./<boardname>.ucf file, and possibly also
+# ./<boardname>.opt and ./<boardname>.bitconf files as well.
+
+  git mv Makefile.example Makefile
+  $EDITOR Makefile
+
+# Edit the README file with project-specific info; include a snazzy title by
+# default if possible.
+
+  if [ -x /usr/bin/figlet ]; then
+      echo "Enter the project title (up to ~32 char), then press enter, then Ctrl-D"
+      figlet > README.new && cat README >> README.new && mv README.new README
+  fi
+  $EDITOR README
+
+# Edit the COPYING file with license information
+
+  $EDITOR COPYING
+
+# Change the 'origin' git remote to point to a new remote repository. Don't
+# accidentially push to the 'verilog-build' template repo!
+
+  $EDITOR .git/config
+
+# Add any hdl files to git
+
+  git add hdl/*.v hdl/*.vhd tb/*.v 2> /dev/null || true
+
+# Add any project-specific files to git (if there are any)
+
+  git add *.opt *.bmm *.ucf 2> /dev/null || true
+
+# Commit all that!
+
+  git commit -e -m "Starting new project using verilog-build template"
+
+echo "Alright, good to go."
+echo
+echo "NOTE: If you didn't get a chance to add any files you wanted in the initial commit, you can still add them now (with 'git add') and then update the most recent commit with 'git commit --amend'."