aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorbryan newbold <bnewbold@leaflabs.com>2014-03-25 11:51:46 -0400
committerbryan newbold <bnewbold@leaflabs.com>2014-03-25 12:00:08 -0400
commite3ef6c1adb03c9aceb0e8a4e0cae497e16ba9b40 (patch)
tree7ba99f70e51895aa11e64cfac20e7956e90eb9bc
parentc87a900a056c566bf5fb85daaec2f74e4efe4a0f (diff)
downloadbasic-hdl-template-e3ef6c1adb03c9aceb0e8a4e0cae497e16ba9b40.zip
basic-hdl-template-e3ef6c1adb03c9aceb0e8a4e0cae497e16ba9b40.tar.gz
verilog indentation style cleanup
-rw-r--r--hdl/main_sp605.v90
-rw-r--r--hdl/main_xula2.v98
-rw-r--r--hdl/rot13.v38
3 files changed, 113 insertions, 113 deletions
diff --git a/hdl/main_sp605.v b/hdl/main_sp605.v
index a5e25b3..3dedfcd 100644
--- a/hdl/main_sp605.v
+++ b/hdl/main_sp605.v
@@ -36,59 +36,59 @@ module main (
); // don't forget to remove trailing comma!
- wire reset;
- assign reset = reset_button;
- wire clock_25mhz;
- assign clock_25mhz = user_clock;
+wire reset;
+assign reset = reset_button;
+wire clock_25mhz;
+assign clock_25mhz = user_clock;
- reg [23:0] throb_counter = 0;
- reg throb_led = 0;
- assign gpio_led[0] = throb_led;
+reg [23:0] throb_counter = 0;
+reg throb_led = 0;
+assign gpio_led[0] = throb_led;
- wire [7:0] rx_byte;
- wire [7:0] tx_byte;
- wire uart_flag;
- assign gpio_led[1] = uart_flag;
- simple_uart #(
- .CLOCK_DIVIDE(651) // for (non-standard) 25MHz clock
- ) simple_uart_inst (
- .clk(clock_25mhz),
- .rst(reset),
- .rx(uart_rx),
- .tx(uart_tx),
- .transmit(uart_flag),
- .tx_byte(tx_byte),
- .received(uart_flag),
- .rx_byte(rx_byte),
- .is_receiving(),
- .is_transmitting(),
- .recv_error()
- );
+wire [7:0] rx_byte;
+wire [7:0] tx_byte;
+wire uart_flag;
+assign gpio_led[1] = uart_flag;
+simple_uart #(
+ .CLOCK_DIVIDE(651) // for (non-standard) 25MHz clock
+) simple_uart_inst (
+ .clk(clock_25mhz),
+ .rst(reset),
+ .rx(uart_rx),
+ .tx(uart_tx),
+ .transmit(uart_flag),
+ .tx_byte(tx_byte),
+ .received(uart_flag),
+ .rx_byte(rx_byte),
+ .is_receiving(),
+ .is_transmitting(),
+ .recv_error()
+);
- rot13 rot13_inst (
- .clock(clock_25mhz),
- .reset(reset),
- .in_char(rx_byte),
- .out_char(tx_byte)
- );
+rot13 rot13_inst (
+ .clock(clock_25mhz),
+ .reset(reset),
+ .in_char(rx_byte),
+ .out_char(tx_byte)
+);
- always @(posedge clock_25mhz) begin
- if (reset) begin
- throb_counter <= 0;
- throb_led <= 0;
+always @(posedge clock_25mhz) begin
+ if (reset) begin
+ throb_counter <= 0;
+ throb_led <= 0;
+ end else begin
+ if (throb_counter >= 24'd12_500_000) begin
+ throb_led <= !throb_led;
+ throb_counter <= 24'd0;
end else begin
- if (throb_counter >= 24'd12_500_000) begin
- throb_led <= !throb_led;
- throb_counter <= 24'd0;
- end else begin
- throb_counter <= throb_counter + 24'd1;
- end
+ throb_counter <= throb_counter + 24'd1;
end
end
+end
- // Tie off extra signals
- assign gpio_led[3:2] = 0;
- assign gpio_header = gpio_switch;
+// Tie off extra signals
+assign gpio_led[3:2] = 0;
+assign gpio_header = gpio_switch;
endmodule
diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v
index 3eba7c9..9d22c09 100644
--- a/hdl/main_xula2.v
+++ b/hdl/main_xula2.v
@@ -25,63 +25,63 @@ module main (
output wire flash_miso
);
- wire reset = chan[0];
- wire uart_rx = chan[17];
- wire uart_tx = chan[18];
+wire reset = chan[0];
+wire uart_rx = chan[17];
+wire uart_tx = chan[18];
- reg [22:0] throb_counter = 0;
- reg throb_led = 0;
- assign chan[10] = throb_led;
+reg [22:0] throb_counter = 0;
+reg throb_led = 0;
+assign chan[10] = throb_led;
- wire [7:0] rx_byte;
- wire [7:0] tx_byte;
- wire uart_flag;
- simple_uart #(
- .CLOCK_DIVIDE(313) // for 12MHz clock
- ) simple_uart_inst (
- .clk(clock_12mhz),
- .rst(reset),
- .rx(chan[17]),
- .tx(chan[18]),
- .transmit(uart_flag),
- .tx_byte(tx_byte),
- .received(uart_flag),
- .rx_byte(rx_byte),
- .is_receiving(),
- .is_transmitting(),
- .recv_error()
- );
+wire [7:0] rx_byte;
+wire [7:0] tx_byte;
+wire uart_flag;
+simple_uart #(
+ .CLOCK_DIVIDE(313) // for 12MHz clock
+) simple_uart_inst (
+ .clk(clock_12mhz),
+ .rst(reset),
+ .rx(chan[17]),
+ .tx(chan[18]),
+ .transmit(uart_flag),
+ .tx_byte(tx_byte),
+ .received(uart_flag),
+ .rx_byte(rx_byte),
+ .is_receiving(),
+ .is_transmitting(),
+ .recv_error()
+ );
- rot13 rot13_inst (
- .clock(clock_12mhz),
- .reset(reset),
- .in_char(rx_byte),
- .out_char(tx_byte)
- );
+rot13 rot13_inst (
+ .clock(clock_12mhz),
+ .reset(reset),
+ .in_char(rx_byte),
+ .out_char(tx_byte)
+ );
- always @(posedge clock_12mhz) begin
- if (reset) begin
- throb_counter <= 0;
- throb_led <= 0;
+always @(posedge clock_12mhz) begin
+ if (reset) begin
+ throb_counter <= 0;
+ throb_led <= 0;
+ end else begin
+ if (throb_counter >= 23'd06_000_000) begin
+ throb_led <= !throb_led;
+ throb_counter <= 23'd0;
end else begin
- if (throb_counter >= 23'd06_000_000) begin
- throb_led <= !throb_led;
- throb_counter <= 23'd0;
- end else begin
- throb_counter <= throb_counter + 23'd1;
- end
+ throb_counter <= throb_counter + 23'd1;
end
end
+end
- // Tie off unused outputs
- assign microsd_cs = 1'bZ;
- assign flash_cs = 1'bZ;
- assign flash_sclk = 1'bZ;
- assign flash_mosi = 1'bZ;
- assign flash_miso = 1'bZ;
+// Tie off unused outputs
+assign microsd_cs = 1'bZ;
+assign flash_cs = 1'bZ;
+assign flash_sclk = 1'bZ;
+assign flash_mosi = 1'bZ;
+assign flash_miso = 1'bZ;
- // Squelch unused input warnings
- (* KEEP="TRUE" *) wire dummy;
- assign dummy =& {chan[31:0], chan_clk};
+// Squelch unused input warnings
+(* KEEP="TRUE" *) wire dummy;
+assign dummy =& {chan[31:0], chan_clk};
endmodule
diff --git a/hdl/rot13.v b/hdl/rot13.v
index d394407..6c9b9d9 100644
--- a/hdl/rot13.v
+++ b/hdl/rot13.v
@@ -20,27 +20,27 @@ module rot13 (
output reg [7:0] out_char = 8'd0
);
- always @(posedge clock) begin
- if (reset) begin
- out_char <= 8'd0;
+always @(posedge clock) begin
+ if (reset) begin
+ out_char <= 8'd0;
+ end else begin
+ if (in_char >= 8'd97 && in_char < 8'd110) begin
+ // 'a' through 'm'
+ out_char <= in_char + 8'd13;
+ end else if (in_char >= 8'd110 && in_char < 8'd123) begin
+ // 'n' through 'z'
+ out_char <= in_char - 8'd13;
+ end else if (in_char >= 8'd65 && in_char < 8'd78) begin
+ // 'A' through 'M'
+ out_char <= in_char + 8'd13;
+ end else if (in_char >= 8'd78 && in_char < 8'd91) begin
+ // 'N' through 'Z'
+ out_char <= in_char - 8'd13;
end else begin
- if (in_char >= 8'd97 && in_char < 8'd110) begin
- // 'a' through 'm'
- out_char <= in_char + 8'd13;
- end else if (in_char >= 8'd110 && in_char < 8'd123) begin
- // 'n' through 'z'
- out_char <= in_char - 8'd13;
- end else if (in_char >= 8'd65 && in_char < 8'd78) begin
- // 'A' through 'M'
- out_char <= in_char + 8'd13;
- end else if (in_char >= 8'd78 && in_char < 8'd91) begin
- // 'N' through 'Z'
- out_char <= in_char - 8'd13;
- end else begin
- // all other characters
- out_char <= in_char;
- end
+ // all other characters
+ out_char <= in_char;
end
end
+end
endmodule