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authorbryan newbold <bnewbold@leaflabs.com>2013-11-13 12:19:15 -0500
committerbryan newbold <bnewbold@leaflabs.com>2013-11-13 12:19:15 -0500
commitc66f054b25d29612393055090953758d0c18b7d6 (patch)
treeeed67b397bb03f2f03026905ddab9389608f2060
parentdd227d103448274e1142119c0c9f657dcfc2ad18 (diff)
downloadbasic-hdl-template-c66f054b25d29612393055090953758d0c18b7d6.zip
basic-hdl-template-c66f054b25d29612393055090953758d0c18b7d6.tar.gz
clean up simulation targets
Proper prereqs for simulation/test targets. This commit should fix old "iSim runs with old files even if there was a bug" errors.
-rw-r--r--README2
-rw-r--r--contrib/README7
-rw-r--r--contrib/xilinx.mk44
3 files changed, 26 insertions, 27 deletions
diff --git a/README b/README
index ff2aad0..f520ebb 100644
--- a/README
+++ b/README
@@ -86,7 +86,7 @@ first time, be sure to save and rename the configuration appropriately.
After editing any HDL files (either the testbench itself or files in ./hdl/),
instead of restarting isim you can simply run the following command and then
-hit the "Reload" button in the isim GUI:
+hit the "Re-launch" button in the isim GUI:
make resim/<testbench>_tb
diff --git a/contrib/README b/contrib/README
index d145490..05ece66 100644
--- a/contrib/README
+++ b/contrib/README
@@ -29,9 +29,10 @@ make clean - cleans all sim and synth files, incl. coregen'd
make untouchcores - reset timestamps on .xco files to last change
-make isim/<name>_tb - compiles sim files, then launches simulator GUI
-make resim/<name>_tb - recompiles sim files w/o launching GUI
-make test/<name>_tb - runs a single unit test
+make isim/<name>_tb - compiles sim files, then launches simulator GUI
+make isimcli/<name>_tb - compiles sim files, then launches simulator CLI
+make resim/<name>_tb - recompiles sim files w/o launching GUI
+make test/<name>_tb - runs a single unit test
make par_timingan - launches timing GUI with most recent build results
make par_fpga_editor - launches FPGA visualizer GUI for last build (slow!)
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index 2d5c0a5..f946ad3 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -43,12 +43,12 @@
# NOTE: DO NOT edit this file to change settings; instead edit Makefile
# These dot-targets must come first in the file
-.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen \
+.PHONY: default xilinx_cores clean twr_map twr_par ise isim coregen \
impact ldimpact lint planahead partial_fpga_editor final_fpga_editor \
partial_timing final_timing tests all bit mcs
# "PRECIOUS" files will not be deleted by make as casually
-.PRECIOUS: tb/%.isim
+.PRECIOUS: tb/%.isim tb/isim/unenclib/%.sdb
# Setup default targets
default: bitfiles
@@ -204,13 +204,14 @@ build/$(project).ngd: build/$(project).ngc $(ucf_file) $(bmm_file)
ngdbuild $(intstyle) $(project).ngc -bm ../$(bmm_file) \
-sd ../cores -uc ../$(ucf_file) -aul $(colorize)"
-build/$(project).ngc: $(verilog_files) $(vhdl_files) $(local_corengcs) build/$(project).scr build/$(project).prj
- @#TODO: The below line is ugly
+build/$(project).ngc: $(verilog_files) $(vhdl_files) $(local_corengcs) build/$(project).scr build/$(project).prj
+ @echo "HACK: Forcing re-build of .scr configuration file..."
@bash -c "rm build/$(project).scr; make build/$(project).scr"
+ # XST does not fail on error (!), so deleting the .ngc before building
+ @rm -f $@
@bash -c "$(xil_env); \
xst $(intstyle) -ifn $(project).scr $(colorize)"
- @# Need to check for success manually? TODO: doesn't work if pre-existed
- @if [ ! -f build/$(project).ngc ]; then false; fi
+ @if [ ! -f $@ ]; then false; fi
build/$(project).prj: $(verilog_files) $(vhdl_files)
@for src in $(verilog_files); do echo "verilog work ../$$src" >> $(project).tmpprj; done
@@ -258,29 +259,22 @@ tb/simulate_isim.prj: $(tbfiles) $(verilog_files) $(vhdl_files) $(enc_vhdl_files
done
@echo "verilog unenclib $(iseenv)/ISE/verilog/src/glbl.v" >> $@
-tb/isim.compiled: tb/simulate_isim.prj $(tbfiles) $(verilog_files) $(vhdl_files)
- @bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj $(colorize)"
- @touch tb/isim.compiled
-
-tb/simulate_isim: tb/isim.compiled
+tb/isim/unenclib/%.sdb: tb/simulate_isim.prj $(tbfiles) $(verilog_files) $(vhdl_files)
+ @rm -f $@
@bash -c "$(sim_env); \
cd ../tb/; \
- fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver \
- -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim \
- $(tbmods) unenclib.glbl $(colorize)"
-
-simulate: tb/simulate_isim
-
-isim_cli: simulate
- @bash -c "$(sim_env); cd ../tb/; ./simulate_isim"
+ vlogcomp -prj simulate_isim.prj $(colorize)"
+ @if [ ! -f $@ ]; then false; fi
-tb/%.isim: tb/%.v tb/isim.compiled
+tb/%.isim: tb/%.v tb/isim/unenclib/%.sdb
+ @rm -f $@
@uut=`basename $< .v`; \
bash -c "$(sim_env); \
cd ../tb/; \
fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver \
-lib unimacro_ver -lib iplib=./iplib -lib unenclib -o $$uut.isim \
unenclib.$$uut unenclib.glbl $(colorize)"
+ @if [ ! -f $@ ]; then false; fi
isim/%: tb/%.isim tb/simulate_isim.prj
@uut=`basename $@`; \
@@ -288,6 +282,12 @@ isim/%: tb/%.isim tb/simulate_isim.prj
cd ../tb; \
./$$uut.isim -gui -view $$uut.wcfg &"
+isimcli/%: tb/%.isim tb/simulate_isim.prj
+ @uut=`basename $@`; \
+ bash -c "$(sim_env); \
+ cd ../tb; \
+ ./$$uut.isim"
+
resim/%: tb/%.isim tb/simulate_isim.prj
@true
@@ -303,7 +303,7 @@ tests: $(alltests)
isim: simulate
@bash -c "$(sim_env); \
cd ../tb/; \
- ./simulate_isim -gui -view signals.wcfg &"
+ isimgui &"
coregen: $(coregen_work_dir)/$(project).cgp
@bash -c "$(xil_env); \
@@ -386,13 +386,11 @@ clean_ise:
rm -rf iseconfig
clean_sim:
- rm -f tb/simulate_isim
rm -f tb/*.log
rm -f tb/*.cmd
rm -f tb/*.xmsgs
rm -f tb/*.prj
rm -f tb/*.isim
- rm -f tb/isim.compiled
rm -rf tb/isim
clean_synth: