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authorbryan newbold <bnewbold@leaflabs.com>2013-11-12 12:54:30 -0500
committerbryan newbold <bnewbold@leaflabs.com>2013-11-12 12:54:30 -0500
commit92ed49e97997d769f41f42260e56a41f8391559d (patch)
treeedfa72346aea5ebbbbcd550d52ae8f299cf12e5c
parent79815d744079daadb5a3808b03ed4d45ffa76365 (diff)
downloadbasic-hdl-template-92ed49e97997d769f41f42260e56a41f8391559d.zip
basic-hdl-template-92ed49e97997d769f41f42260e56a41f8391559d.tar.gz
Part 1 of refactoring template files into ./contrib
BROKEN without later parts (documentation and Makefile updates) This commit moves and deletes a lot of Xula2 and SP605 files around. It also includes a large cleanup of xilinx.mk
-rw-r--r--contrib/README.tb_test (renamed from README.tb_test)0
-rw-r--r--contrib/TODO.template (renamed from TODO.template)0
-rw-r--r--contrib/default.opt (renamed from exampleproj.opt)0
-rw-r--r--contrib/empty.bmm (renamed from exampleproj.bmm)0
-rw-r--r--contrib/sp605/sp605.bitconf (renamed from sp605.bitconf)0
-rw-r--r--contrib/sp605/sp605.mk12
-rw-r--r--contrib/sp605/sp605.ucf (renamed from sp605.ucf)0
-rw-r--r--contrib/xilinx.mk213
-rw-r--r--contrib/xula2.mk9
-rw-r--r--contrib/xula2/README.xula2 (renamed from README.xula2)0
-rw-r--r--contrib/xula2/xula2.bitconf (renamed from xula2.bitconf)0
-rw-r--r--contrib/xula2/xula2.mk24
-rw-r--r--contrib/xula2/xula2.ucf (renamed from xula2.ucf)0
-rw-r--r--sp605.bmm1
-rw-r--r--xula2.bmm1
15 files changed, 173 insertions, 87 deletions
diff --git a/README.tb_test b/contrib/README.tb_test
index 3be00d6..3be00d6 100644
--- a/README.tb_test
+++ b/contrib/README.tb_test
diff --git a/TODO.template b/contrib/TODO.template
index cc47521..cc47521 100644
--- a/TODO.template
+++ b/contrib/TODO.template
diff --git a/exampleproj.opt b/contrib/default.opt
index 7fe9d8b..7fe9d8b 100644
--- a/exampleproj.opt
+++ b/contrib/default.opt
diff --git a/exampleproj.bmm b/contrib/empty.bmm
index c915ec8..c915ec8 100644
--- a/exampleproj.bmm
+++ b/contrib/empty.bmm
diff --git a/sp605.bitconf b/contrib/sp605/sp605.bitconf
index 2a339b6..2a339b6 100644
--- a/sp605.bitconf
+++ b/contrib/sp605/sp605.bitconf
diff --git a/contrib/sp605/sp605.mk b/contrib/sp605/sp605.mk
new file mode 100644
index 0000000..857417b
--- /dev/null
+++ b/contrib/sp605/sp605.mk
@@ -0,0 +1,12 @@
+# Configuration variables and build targets for the Xilinx Spartan6 SP605 Dev
+# Board
+
+board := sp605
+family := spartan6
+device := xc6slx45t
+speedgrade := -3
+device_package := fgg484
+bitconf_file := ./contrib/sp605/sp605.bitconf
+ucf_file := ./contrib/sp605/sp605.ucf
+opt_file := ./contrib/default.opt
+mcs_datawidth := 16
diff --git a/sp605.ucf b/contrib/sp605/sp605.ucf
index 9ad7857..9ad7857 100644
--- a/sp605.ucf
+++ b/contrib/sp605/sp605.ucf
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index ec7af12..3c26ed5 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -2,86 +2,103 @@
#
# The top level module should define the variables below then include
# this file. The files listed should be in the same directory as the
-# Makefile.
-#
-# TODO: update these listings
+# root Makefile.
#
# variable description
# ---------- -------------
# board board target short-name
-# project project name (top level module should match this name)
+# project project name
# top_module top level module of the project
# libdir path to library directory
# libs library modules used
-# verilog_files all local .v files
-# vhdl_files all local .vhd files
-# end_vhdl_files all local encrypted .vhd files
-# xilinx_cores all local .xco files
-# vendor vendor of FPGA (xilinx, altera, etc.)
+# vendor vendor of FPGA (xilinx, lattice, altera, etc.)
# family FPGA device family (spartan3e)
# part FPGA part name (xc4vfx12-10-sf363)
# flashsize size of flash for mcs file (16384)
-# optfile (optional) xst extra opttions file to put in .scr
+# vgenerics verilog parameters to be passed into top-level module
# map_opts (optional) options to give to map
# par_opts (optional) options to give to par
# intstyle (optional) intstyle option to all tools
#
-# files description
-# ---------- ------------
-# $(board).ucf ucf file
+# files description
+# ---------- ------------
+# opt_file xst extra opttions file to put in .scr
+# ucf_file .ucf file specifying FPGA constraints
+# bitconf_file bitfile generation flags
+# bmm_file BRAM default memory
+# verilog_files all local non-testbench .v files
+# vhdl_files all local .vhd files
+# tbfile all local .v testbench files
+# end_vhdl_files all local encrypted .vhd files
+# xilinx_cores all local .xco files
#
# Library modules should have a modules.mk in their root directory,
# namely $(libdir)/<libname>/module.mk, that simply adds to the verilog_files
# and xilinx_cores variable.
#
-# all the .xco files listed in xilinx_cores will be generated with core, with
+# All the .xco files listed in xilinx_cores will be generated with core, with
# the resulting .v and .ngc files placed back in the same directory as
# the .xco file.
#
-# TODO: .xco files are device dependant, should use a template based system
-#
# NOTE: DO NOT edit this file to change settings; instead edit Makefile
+# This file only works with Xilinx stuff
+vendor = xilinx
+
+# Defaults; these should all be overriden though
+hostbits ?= 64
+iseenv ?= /opt/Xilinx/14.3/ISE_DS
+opt_file ?= ./contrib/default.opt
vgenerics ?=
+extra_prj ?=
+verilog_files ?=
+vhdl_files ?=
+tbfiles ?=
+enc_vhdl_files ?=
+
+# Low-level Tunables (override in top-level Makefile)
+synth_effort ?= high
unconst_timing ?= -u 50
const_timing_limit ?= 50
-synth_effort ?= high
-coregen_work_dir ?= ./coregen-tmp
+flashsize ?= 8192
+mcs_datawidth ?= 8
map_opts ?= -timing -ol $(synth_effort) -detail -pr b -register_duplication -w
par_opts ?= -ol $(synth_effort)
-hostbits = 64
-iseenv= /opt/Xilinx/14.3/ISE_DS
+intstyle ?= -intstyle xflow
+multithreading ?= -mt 4
+
+# Build Environment
iseenvfile?= $(iseenv)/settings$(hostbits).sh
xil_env ?= mkdir -p build/; cd ./build; source $(iseenvfile) > /dev/null
sim_env ?= cd ./tb; source $(iseenvfile) > /dev/null
-flashsize ?= 8192
-mcs_datawidth ?= 16
-extra_prj ?=
-end_vhdl_files ?=
-
+coregen_work_dir ?= ./coregen-tmp
PWD := $(shell pwd)
-intstyle ?= -intstyle xflow
+
+# The following are used to color-code console build output
colorize ?= 2>&1 | python $(PWD)/contrib/colorize.py red ERROR: yellow WARNING: green \"Number of error messages: 0\" green \"Number of error messages:\t0\" green \"Number of errors: 0\"
colorizetest ?= 2>&1 | python $(PWD)/contrib/colorize.py red FAIL green PASS
-multithreading ?= -mt 4
-
+# Library stuff (TODO: untested)
libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
mkfiles = Makefile $(libmks) contrib/xilinx.mk
include $(libmks)
-# default is a single file
-tbfiles ?= ./tb/tb.v
-testfiles ?=
-
+# Setup coregen'd includes
corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
verilog_files += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
-tbfiles += $(foreach tfile,$(testfiles),$(tfile))
tbmods = $(foreach tbm,$(tbfiles),unenclib.`basename $(tbm) .v`)
+define cp_template
+$(2): $(1)
+ cp $(1) $(2)
+endef
+$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
-.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen impact ldimpact lint planahead partial_fpga_editor final_fpga_editor partial_timing final_timing tests
+.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen \
+ impact ldimpact lint planahead partial_fpga_editor final_fpga_editor \
+ partial_timing final_timing tests
+# "PRECIOUS" files will not be deleted by make as casually
.PRECIOUS: tb/%.isim
default: build/$(project).bit build/$(project).mcs
@@ -89,12 +106,6 @@ xilinx_cores: $(corengcs)
twr_map: build/$(project)_post_map.twr
twr_par: build/$(project)_post_par.twr
-define cp_template
-$(2): $(1)
- cp $(1) $(2)
-endef
-$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
-
$(coregen_work_dir)/$(project).cgp: contrib/template.cgp
@if [ -d $(coregen_work_dir) ]; then \
rm -rf $(coregen_work_dir)/*; \
@@ -111,7 +122,9 @@ $(coregen_work_dir)/$(project).cgp: contrib/template.cgp
%.ngc %.v: %.xco $(coregen_work_dir)/$(project).cgp
@echo "=== rebuilding $@"
- @bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -b ../$< -p $(project).cgp;"
+ @bash -c "$(xil_env); \
+ cd ../$(coregen_work_dir); \
+ coregen -b ../$< -p $(project).cgp;"
@xcodir=`dirname $<`; \
basename=`basename $< .xco`; \
echo $(coregen_work_dir)/$$basename.v; \
@@ -127,15 +140,22 @@ date = $(shell date +%F-%H-%M)
programming_files: build/$(project).bit build/$(project).mcs
@mkdir -p $@/$(date)
@mkdir -p $@/latest
- @for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
- @bash -c "$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr"
+ @for x in .bit .mcs .cfi _bd.bmm; do \
+ cp $(project)$$x $@/$(date)/$(project)$$x; \
+ cp $(project)$$x $@/latest/$(project)$$x; \
+ done
+ @bash -c "$(xil_env); \
+ xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr"
build/$(project).mcs: build/$(project).bit
- @bash -c "$(xil_env); promgen -w -data_width $(mcs_datawidth) -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit"
+ @bash -c "$(xil_env); \
+ promgen -w -data_width $(mcs_datawidth) -s $(flashsize) -p mcs -o $(project).mcs \
+ -u 0 $(project).bit"
-build/$(project).bit: build/$(project)_par.ncd build/$(project)_post_par.twr $(board).bitconf
+build/$(project).bit: build/$(project)_par.ncd build/$(project)_post_par.twr $(bitconf_file)
@bash -c "$(xil_env); \
- bitgen $(intstyle) -f ../$(board).bitconf -w $(project)_par.ncd $(project).bit $(project).pcf"
+ bitgen $(intstyle) -f ../$(bitconf_file) -w $(project)_par.ncd $(project).bit \
+ $(project).pcf"
build/$(project)_par.ncd: build/$(project).ncd build/$(project)_post_map.twr
@@ -154,16 +174,19 @@ build/$(project).ncd: build/$(project).ngd
smartguide=""; \
fi; \
bash -c "$(xil_env); \
- map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)"
+ map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)"
-build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm
+build/$(project).ngd: build/$(project).ngc $(ucf_file) $(bmm_file)
@bash -c "$(xil_env); \
- ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)"
+ ngdbuild $(intstyle) $(project).ngc -bm ../$(bmm_file) \
+ -sd ../cores -uc ../$(ucf_file) -aul $(colorize)"
build/$(project).ngc: $(verilog_files) $(vhdl_files) $(local_corengcs) build/$(project).scr build/$(project).prj
+ @#TODO: The below line is ugly
@bash -c "rm build/$(project).scr; make build/$(project).scr"
- @bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr $(colorize)"
- @# need to check for success manually; TODO: doesn't work if pre-existed
+ @bash -c "$(xil_env); \
+ xst $(intstyle) -ifn $(project).scr $(colorize)"
+ @# Need to check for success manually? TODO: doesn't work if pre-existed
@if [ ! -f build/$(project).ngc ]; then false; fi
build/$(project).prj: $(verilog_files) $(vhdl_files)
@@ -173,25 +196,27 @@ build/$(project).prj: $(verilog_files) $(vhdl_files)
@sort -u $(project).tmpprj > $@
@rm -f $(project).tmpprj
-optfile += $(wildcard $(project).opt)
-top_module ?= $(project)
-build/$(project).scr: $(optfile) ./$(project).opt
- mkdir -p build
+build/$(project).scr: $(opt_file)
+ @mkdir -p build
@echo "run" > $@
@echo "-p $(part)" >> $@
@echo "-top $(top_module)" >> $@
@echo "-ifn $(project).prj" >> $@
@echo "-ofn $(project).ngc" >> $@
@echo '-generics {$(vgenerics)}' >> $@
- @cat $(optfile) >> $@
+ @cat $(opt_file) >> $@
cp $@ build/$(project).xst
build/$(project)_post_map.twr: build/$(project).ncd
- @bash -c "$(xil_env); trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) $(project).ncd $(project).pcf -o $(project)_post_map.twr $(colorize)"
+ @bash -c "$(xil_env); \
+ trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) \
+ $(project).ncd $(project).pcf -o $(project)_post_map.twr $(colorize)"
@echo "Read $@ for timing analysis details"
build/$(project)_post_par.twr: build/$(project)_par.ncd
- @bash -c "$(xil_env); trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) $(project)_par.ncd $(project).pcf -o $(project)_post_par.twr $(colorize)"
+ @bash -c "$(xil_env); \
+ trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) \
+ $(project)_par.ncd $(project).pcf -o $(project)_post_par.twr $(colorize)"
@echo "See $@ for timing analysis details"
tb/simulate_isim.prj: $(tbfiles) $(verilog_files) $(vhdl_files) $(enc_vhdl_files)
@@ -215,7 +240,11 @@ tb/isim.compiled: tb/simulate_isim.prj $(tbfiles) $(verilog_files) $(vhdl_files)
@touch tb/isim.compiled
tb/simulate_isim: tb/isim.compiled
- @bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim $(tbmods) unenclib.glbl $(colorize)"
+ @bash -c "$(sim_env); \
+ cd ../tb/; \
+ fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver \
+ -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim \
+ $(tbmods) unenclib.glbl $(colorize)"
simulate: tb/simulate_isim
@@ -224,11 +253,17 @@ isim_cli: simulate
tb/%.isim: tb/%.v tb/isim.compiled
@uut=`basename $< .v`; \
- bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o $$uut.isim unenclib.$$uut unenclib.glbl $(colorize)"
+ bash -c "$(sim_env); \
+ cd ../tb/; \
+ fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver \
+ -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o $$uut.isim \
+ unenclib.$$uut unenclib.glbl $(colorize)"
isim/%: tb/%.isim tb/simulate_isim.prj
@uut=`basename $@`; \
- bash -c "$(sim_env); cd ../tb; ./$$uut.isim -gui -view $$uut.wcfg &"
+ bash -c "$(sim_env); \
+ cd ../tb; \
+ ./$$uut.isim -gui -view $$uut.wcfg &"
resim/%: tb/%.isim tb/simulate_isim.prj
@true
@@ -236,24 +271,36 @@ resim/%: tb/%.isim tb/simulate_isim.prj
test/%: tb/%.isim tb/simulate_isim.prj
@echo "run all" > ./tb/test.tcl
@uut=`basename $@`; \
- bash -c "$(sim_env); cd ../tb/; ./$$uut.isim -tclbatch test.tcl $(colorizetest)"
+ bash -c "$(sim_env); \
+ cd ../tb/; \
+ ./$$uut.isim -tclbatch test.tcl $(colorizetest)"
tests: $(alltests)
isim: simulate
- @bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg &"
+ @bash -c "$(sim_env); \
+ cd ../tb/; \
+ ./simulate_isim -gui -view signals.wcfg &"
coregen: $(coregen_work_dir)/$(project).cgp
- @bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -p $(project).cgp &"
+ @bash -c "$(xil_env); \
+ cd ../$(coregen_work_dir); \
+ coregen -p $(project).cgp &"
impact:
- @bash -c "$(xil_env); cd ../build; impact &"
+ @bash -c "$(xil_env); \
+ cd ../build; \
+ impact &"
ldimpact:
- @bash -c "$(xil_env); cd ../build; LD_PRELOAD=/usr/local/lib/libusb-driver.so impact &"
+ @bash -c "$(xil_env); \
+ cd ../build; \
+ LD_PRELOAD=/usr/local/lib/libusb-driver.so impact &"
autoimpact:
- @bash -c "$(xil_env); cd ../build; impact -mode bscan -b build/$(project).bit -port auto -autoassign &"
+ @bash -c "$(xil_env); \
+ cd ../build; \
+ impact -mode bscan -b build/$(project).bit -port auto -autoassign &"
ise:
@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@@ -261,29 +308,43 @@ ise:
@echo "! (see README) !"
@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@mkdir -p build
- @bash -c "$(xil_env); cd ..; XIL_MAP_LOCWARN=0 ise $(project).xise &"
+ @bash -c "$(xil_env); \
+ cd ..; \
+ XIL_MAP_LOCWARN=0 ise $(project).xise &"
planahead:
- @bash -c "$(xil_env); cd ..; planAhead &"
+ @bash -c "$(xil_env); \
+ cd ..; \
+ planAhead &"
+
+# DISPLAY variable (X Windows) should be inherited from environment
+DISPLAY ?= :0
-# TODO: DISPLAY = `echo $DISPLAY |sed s/'\.0'//`
partial_fpga_editor: build/$(project).ncd
@echo "Starting fpga_editor in the background (can take a minute or two)..."
- @bash -c "$(xil_env); DISPLAY=:0 fpga_editor $(project).ncd &"
+ @echo "IGNORE the RPC errors below."
+ @echo
+ @bash -c "$(xil_env); \
+ DISPLAY=`echo $(DISPLAY) | sed s/'\.0'//` fpga_editor $(project).ncd &"
-# TODO: DISPLAY = `echo $DISPLAY |sed s/'\.0'//`
final_fpga_editor: build/$(project)_par.ncd
@echo "Starting fpga_editor in the background (can take a minute or two)..."
- @bash -c "$(xil_env); DISPLAY=:0 fpga_editor $(project)_par.ncd &"
+ @echo "IGNORE the RPC errors below."
+ @echo
+ @bash -c "$(xil_env); \
+ DISPLAY=`echo $(DISPLAY) | sed s/'\.0'//` fpga_editor $(project)_par.ncd &"
timingan:
- @bash -c "$(xil_env); timingan &"
+ @bash -c "$(xil_env); \
+ timingan &"
partial_timing: build/$(project)_post_map.twr
- @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &"
+ @bash -c "$(xil_env); \
+ timingan -ucf ../$(ucf_file) $(project).ncd $(project).pcf $(project)_post_map.twx &"
final_timing: build/$(project)_post_par.twr
- @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &"
+ @bash -c "$(xil_env); \
+ timingan -ucf ../$(ucf_file) $(project)_par.ncd $(project).pcf $(project)_post_par.twx &"
lint:
verilator --lint-only -I./hdl -I./cores -Wall -Wno-DECLFILENAME hdl/$(top_module)_$(board) || true
diff --git a/contrib/xula2.mk b/contrib/xula2.mk
deleted file mode 100644
index 9c06b3b..0000000
--- a/contrib/xula2.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-# xula2 device-specific make targets
-
-.PHONY: prog
-
-prog: build/$(project).bit
- @xsload.py --fpga build/$(project).bit
-
-prog_flash: build/$(project).bit
- @xsload.py --flash build/$(project).bit
diff --git a/README.xula2 b/contrib/xula2/README.xula2
index 3ca7d50..3ca7d50 100644
--- a/README.xula2
+++ b/contrib/xula2/README.xula2
diff --git a/xula2.bitconf b/contrib/xula2/xula2.bitconf
index 599289d..599289d 100644
--- a/xula2.bitconf
+++ b/contrib/xula2/xula2.bitconf
diff --git a/contrib/xula2/xula2.mk b/contrib/xula2/xula2.mk
new file mode 100644
index 0000000..681fe38
--- /dev/null
+++ b/contrib/xula2/xula2.mk
@@ -0,0 +1,24 @@
+# xula2 device-specific configuration variables and make targets
+
+.PHONY: prog prog_flash
+
+board := xula2
+family := spartan6
+device := XC6SLX25
+speedgrade := -2
+device_package := ftg256
+bitconf_file := ./contrib/xula2/xula2.bitconf
+ucf_file := ./contrib/xula2/xula2.ucf
+opt_file := ./contrib/default.opt
+
+# This target uploads directly to the FPGA; volatile
+prog: build/$(project).bit
+ # First ensure that xsload.py is installed
+ @xsload.py --version
+ @xsload.py --fpga build/$(project).bit
+
+# This target uploads to the SPI flash on board; non-volatile
+prog_flash: build/$(project).bit
+ # First ensure that xsload.py is installed
+ @xsload.py --version
+ @xsload.py --flash build/$(project).bit
diff --git a/xula2.ucf b/contrib/xula2/xula2.ucf
index ae04f81..ae04f81 100644
--- a/xula2.ucf
+++ b/contrib/xula2/xula2.ucf
diff --git a/sp605.bmm b/sp605.bmm
deleted file mode 100644
index c915ec8..0000000
--- a/sp605.bmm
+++ /dev/null
@@ -1 +0,0 @@
-// Empty file; this is a "Block Ram Memory Map"
diff --git a/xula2.bmm b/xula2.bmm
deleted file mode 100644
index c915ec8..0000000
--- a/xula2.bmm
+++ /dev/null
@@ -1 +0,0 @@
-// Empty file; this is a "Block Ram Memory Map"