commit day's work

5 files changed, 223 insertions, 12 deletions

diff --git a/templates/headers.h.tmpl b/templates/headers.h.tmpl
new file mode 100644
index 0000000..ad6a0f7
--- /dev/null
+++ b/templates/headers.h.tmpl
@@ -0,0 +1,20 @@
+#ifndef {{ name.upper() }}_MAP_H
+#define {{ name.upper() }}_MAP_H
+
+/* {{ name }} Memory Map Structs */
+
+/* WARNING: Currently assumes perfect packing */
+
+{% for sec_name, values in sections.iteritems() %}
+typedef struct {
+{% for val in values %}
+    {{ val.ctype() }} {{ val.slug }};
+{% endfor %}
+} {{ name }}_{{ sec_name }}_map;
+#define {{ name }}_{{ sec_name }}_offset    {{ values[0].addr_pp() }}
+/* Usage (?)
+ *      void *uint32_t {{ name }}_{{ sec_name }}_map...
+ */
+{% endfor %}
+
+#endif
diff --git a/templates/minimal.html.tmpl b/templates/minimal.html.tmpl
index 98042ee..21530b1 100644
--- a/templates/minimal.html.tmpl
+++ b/templates/minimal.html.tmpl
@@ -24,17 +24,17 @@ Last updated [{{ now }}] by {{ whoami }}
 {% for sec_name, sec_values in sections.iteritems() %}
 <a name="{{sec_name}}"><h2>{{ sec_name }}</h2></a>
 <table>
-  <tr><th>Memory Address
-      <th>Bits
-      <th>Mode
-      <th>Shortname
-      <th>What
+  <tr><th>Memory Address</th>
+      <th>Bits</th>
+      <th>Mode</th>
+      <th>Shortname</th>
+      <th>What</th></tr>
 {% for val in sec_values %}
-  <tr><td>{{ val.addr_pp() }}
-      <td>{{ val.bits }}
-      <td>{{ val.mode }}
-      <td>{{ val.slug }}
-      <td>{{ val.description }}
+  <tr><td><pre>{{ val.addr_pp() }}</pre></td>
+      <td><pre>{{ val.bits }}</pre></td>
+      <td><pre>{{ val.mode }}</pre></td>
+      <td>{{ val.slug }}</td>
+      <td>{{ val.description }}</td></tr>
 {% endfor %}
 </table>{% endfor %}
 
diff --git a/templates/minimal.rst.tmpl b/templates/minimal.rst.tmpl
index 0ad74df..167aa14 100644
--- a/templates/minimal.rst.tmpl
+++ b/templates/minimal.rst.tmpl
@@ -3,6 +3,7 @@
 =========================================================================
 
 {% for sec_name, sec_values in sections.iteritems() %}
+
 {{sec_name}}
 ---------------------------------------------------------
 
@@ -14,10 +15,14 @@
        - Bits
        - Mode
        - Shortname
-       - What      {% for val in sec_values %}
+       - What
+   {% for val in sec_values %}
    *   - ``{{ val.addr_pp() }}``
        - {{ val.bits }}
        - ``{{ val.mode }}``
        - {{ val.slug }}
-       - {{ val.description }}     {% endfor %}
+       - {{ val.description }}
+   {% endfor %}
+
 {% endfor %}
+
diff --git a/templates/partial_axi_lite_slave.v.tmpl b/templates/partial_axi_lite_slave.v.tmpl
new file mode 100644
index 0000000..042dc11
--- /dev/null
+++ b/templates/partial_axi_lite_slave.v.tmpl
@@ -0,0 +1,141 @@
+
+// Generate-time parameters:
+//    AXI_DATA_WIDTH = {{AXI_DATA_WIDTH}}
+//    AXI_ADDR_WIDTH = {{AXI_ADDR_WIDTH}}
+//    AXI_ADDR_MSB = {{AXI_ADDR_MSB}}
+//    AXI_ADDR_LSB = {{AXI_ADDR_LSB}}
+
+module axi_lite_slave_{{name}} (
+    //// AXI I/O Signals
+    input wire axi_anreset,
+    input wire [{{AXI_ADDR_WIDTH-1}}:0] axi_awaddr,
+    input wire axi_awvalid,
+    output wire s_axi_awready,
+    input wire [{{AXI_DATA_WIDTH-1}}:0] s_axi_wdata,
+    input wire [{{AXI_DATA_WIDTH/8-1}}:0] s_axi_wstrb,
+    input wire s_axi_wvalid,
+    output wire s_axi_wready,
+    output wire [1:0] s_axi_bresp,
+    output wire s_axi_bvalid,
+    input wire s_axi_bready,
+    input wire [{{AXI_ADDR_WIDTH-1}}:0] s_axi_araddr,
+    input wire s_axi_arvalid,
+    output wire s_axi_arready,
+    output wire [{{AXI_DATA_WIDTH-1}}:0] s_axi_rdata,
+    output wire [1:0] s_axi_rresp,
+    output wire s_axi_rvalid,
+    input wire s_axi_rready,
+{% if registers|length > 0 %}
+    //// {{ name }} register values
+{% for reg in registers %}
+    {%+ if reg.write %}output reg{% else %}input wire{% endif %} {{ reg.pphdlwidth() }}{{ reg.slug }},
+{% endfor %}
+{% endif %}
+    // axi_clock is last to ensure no trailing comma
+    input wire axi_clock
+);
+
+{% if parameters|length > 0 %}//// Static Memory Map Values{% endif %}
+
+{% for param in parameters %}
+parameter {{ param.ppslug() }} = {{ param.ppdefault() }};
+{% endfor %}
+
+//// Register Default Parameters
+{% for reg in registers %}
+parameter DEFAULT_{{ reg.slug.upper() }} = {{ reg.ppdefault() }};
+{% endfor %}
+
+//// Memory Mapped Register Initialization
+initial begin
+{% for reg in registers %}
+{% if reg.write %}
+    {{ reg.slug }} = DEFAULT_{{ reg.slug.upper() }};
+{% endif %}
+{% endfor %}
+end
+
+//// AXI Internals
+// TODO:
+wire slv_reg_wren;
+wire slv_reg_rden;
+reg [{{AXI_DATA_WIDTH-1}}:0] reg_data_out;
+reg [{{AXI_DATA_WIDTH-1}}:0] axi_wdata;
+reg [{{AXI_DATA_WIDTH-1}}:0] axi_rdata;
+reg [{{AXI_DATA_WIDTH-1}}:0] axi_araddr;
+
+{# this would be for duplicated sections
+genvar k;
+generate
+for (k = 1; k < 8; k = k + 1) begin: kblock
+    initial begin
+        afg_wavetable_select[k] <= 0;
+    end
+end
+endgenerate
+#}
+
+// This block handles writes
+always @(posedge axi_clock) begin
+    if (axi_anreset == 1'b0) begin
+{% for reg in registers %}
+{% if reg.write %}
+        {{ reg.slug }} <= DEFAULT_{{ reg.slug.upper() }};
+{% endif %}
+{% endfor %}
+    end else begin
+        if (slv_reg_wren) begin
+            casex (axi_awaddr[{{AXI_ADDR_MSB-1}}:{{AXI_ADDR_LSB}}])
+{% for reg in registers %}
+{% if reg.write %}
+{% for word in reg.word_list() %}
+            14'd{{ word[0] }}: begin
+                {{ reg.slug }}{{ word[2] }} <= axi_wdata{{ word[2] }};
+            end
+{% endfor %}
+{% endif %}
+{% endfor %}
+            default: begin
+                // pass
+            end
+          endcase
+        end else begin
+            // TODO: doorbells
+        end
+    end
+end
+
+// This block handles reads
+always @(posedge axi_clock) begin
+    if (axi_anreset == 1'b0) begin
+        reg_data_out <= 0;
+    end else if (slv_reg_rden) begin
+        // Read address mux
+        casex ( axi_araddr[{{AXI_ADDR_MSB-1}}:{{AXI_ADDR_LSB}}] )
+{% for reg in registers %}
+{% if reg.read %}
+{% for word in reg.word_list() %}
+        14'd{{ word[0] }}: begin
+            reg_data_out[31:0] <= {{ word[1] }};
+        end
+{% endfor %}
+{% endif %}
+{% endfor %}
+        default: begin
+            // pass
+        end
+        endcase
+    end
+end
+
+{# this would be for MEMORY blocks
+always @(posedge axi_clock) begin
+    if (slv_reg_wren) begin
+        memory_addr <= axi_awaddr[13:2];
+    end else begin
+        wavetables_addr <= axi_araddr[13:2];
+    end
+end
+#}
+
+endmodule
diff --git a/templates/stub.v.tmpl b/templates/stub.v.tmpl
new file mode 100644
index 0000000..9363240
--- /dev/null
+++ b/templates/stub.v.tmpl
@@ -0,0 +1,45 @@
+{% if settings.stub_nets %}
+    {% for reg in registers %}
+    {% if reg.write %}
+    wire {{ reg.pphdlwidth() }}{{ reg.slug }};
+    {% else %}
+    reg {{ reg.pphdlwidth() }}{{ reg.slug }} = {{ reg.ppdefault() }};
+    {% endif %}
+    {% endfor %}
+    {%+ if parameters|length > 0 %}//// Static Memory Map Values{% endif %}
+    {% for param in parameters %}
+    parameter {{ param.ppslug() }} = {{ param.ppdefault() }};
+    {% endfor %}
+{% endif %}
+    axi_lite_slave_afg {% if parameters|length > 0 %}#(
+{%+ for param in parameters %}
+        .{{ param.ppslug() }}({{ param.ppslug() if settings.stub_axi_nets }}){% if not loop.last %},{% endif %}
+
+{% endfor %}
+    ){%endif%} axi_lite_slave_afg_i (
+        //// AXI I/O Signals
+        // NB: axi_clock comes at end
+        .axi_anreset({% if settings.stub_axi_nets %}axi_aresetn{% endif %}),
+        .axi_araddr({% if settings.stub_axi_nets %}axi_slave1_araddr[15:0]{% endif %}),
+        .axi_arready({% if settings.stub_axi_nets %}axi_slave1_arready{% endif %}),
+        .axi_arvalid({% if settings.stub_axi_nets %}axi_slave1_arvalid{% endif %}),
+        .axi_awaddr({% if settings.stub_axi_nets %}axi_slave1_awaddr[15:0]{% endif %}),
+        .axi_awready({% if settings.stub_axi_nets %}axi_slave1_awready{% endif %}),
+        .axi_awvalid({% if settings.stub_axi_nets %}axi_slave1_awvalid{% endif %}),
+        .axi_bready({% if settings.stub_axi_nets %}axi_slave1_bready{% endif %}),
+        .axi_bresp({% if settings.stub_axi_nets %}axi_slave1_bresp{% endif %}),
+        .axi_bvalid({% if settings.stub_axi_nets %}axi_slave1_bvalid{% endif %}),
+        .axi_rdata({% if settings.stub_axi_nets %}axi_slave1_rdata{% endif %}),
+        .axi_rready({% if settings.stub_axi_nets %}axi_slave1_rready{% endif %}),
+        .axi_rresp({% if settings.stub_axi_nets %}axi_slave1_rresp{% endif %}),
+        .axi_rvalid({% if settings.stub_axi_nets %}axi_slave1_rvalid{% endif %}),
+        .axi_wdata({% if settings.stub_axi_nets %}axi_slave1_wdata{% endif %}),
+        .axi_wready({% if settings.stub_axi_nets %}axi_slave1_wready{% endif %}),
+        .axi_wstrb({% if settings.stub_axi_nets %}axi_slave1_wstrb{% endif %}),
+        .axi_wvalid({% if settings.stub_axi_nets %}axi_slave1_wvalid{% endif %}),
+        //// Memory Map
+        {% for reg in registers %}
+        .{{ reg.slug }}({{ reg.slug if settings.stub_nets }}),
+        {% endfor %}
+        .axi_clock({% if settings.stub_axi_nets %}axi_aclk{% endif %}) // axi_clock is last to ensure no trailing comma
+        );