diff options
Diffstat (limited to 'xilinx_data')
-rw-r--r-- | xilinx_data/spartan3a.csv | 29 | ||||
-rw-r--r-- | xilinx_data/spartan3a_shared.csv | 0 | ||||
-rw-r--r-- | xilinx_data/virtex6.csv | 36 | ||||
-rw-r--r-- | xilinx_data/virtex6_shared.csv | 0 | ||||
-rw-r--r-- | xilinx_data/virtex7.csv | 35 | ||||
-rw-r--r-- | xilinx_data/virtex7_shared.csv | 2 |
6 files changed, 102 insertions, 0 deletions
diff --git a/xilinx_data/spartan3a.csv b/xilinx_data/spartan3a.csv new file mode 100644 index 0000000..aa8c0ac --- /dev/null +++ b/xilinx_data/spartan3a.csv @@ -0,0 +1,29 @@ +Part Number,XC3S50A,XC3S50AN,XC3S200A,XC3S200AN,XC3S400A,XC3S400AN,XC3S700A,XC3S700AN,XC3S1400A,XC3S1400AN,XC3SD1800A,XC3SD3400A +System Gates,50K,,200K,,400K,,700K,,1400K,,1800K,3400K +Logic Cells,1584,,4032,,8064,,13248,,25344,,37440,53712 +CLBs,176,,448,,896,,1472,,2816,,4160,5968 +Slices,704,,1792,,3584,,5888,,11264,,16640,23872 +Distributed RAM Bits,11K,,28K,,56K,,92K,,176K,,260K,373K +Block RAM Bits,54K,,288K,,360K,,360K,,576K,,1512K,2268K +In-System Flash Bits,1M,,4M,,4M,,8M,,16M,,n/a,n/a +Dedicated Multipliers,3,,16,,20,,20,,32,,n/a,n/a +DSP48As,n/a,,n/a,,n/a,,n/a,,n/a,,84,126 +DCMs,2,,4,,4,,8,,8,,8,8 +Maximum User I/O,144,,248,,311,,372,,502,,519,469 +###,Available I/O Pins,,,,,,,,,,, +VQ100,68,68,68,68, , , , , , , , +VQG100,68,68,68,68, , , , , , , , +TQ144,108,108, , , , , , , , , , +TQG144,108,108, , , , , , , , , , +FT256,144,144,195,195,195,195,161,161,161,161, , +FTG256,144,144,195,195,195,195,161,161,161,161, , +FG320, ,,248,248,251,251, , , , , , +FGG320, ,,248,248,251,251, , , , , , +FG400, ,, ,,311,311,311,311, , , , +FGG400, ,, ,,311,311,311,311, , , , +CS484, ,, ,, ,, , , , ,309,309 +CSG484, ,, ,, ,, , , , ,309,309 +FG484, ,, ,, ,,372,372,375,375, , +FGG484, ,, ,, ,,372,372,375,375, , +FG676, ,, ,, ,, ,,502,502,519,469 +FGG676, ,, ,, ,, ,,502,502,519,469 diff --git a/xilinx_data/spartan3a_shared.csv b/xilinx_data/spartan3a_shared.csv new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/xilinx_data/spartan3a_shared.csv diff --git a/xilinx_data/virtex6.csv b/xilinx_data/virtex6.csv new file mode 100644 index 0000000..e4a2496 --- /dev/null +++ b/xilinx_data/virtex6.csv @@ -0,0 +1,36 @@ +Part Number,XC6VLX75T,XC6VLX130T,XC6VLX195T,XC6VLX240T,XC6VLX365T,XC6VLX550T,XC6VLX760,XC6VSX315T,XC6VSX475T,XC6VHX250T,XC6VHX255T,XC6VHX380T,XC6VHX565T, +Cost Reduction Part,XCE6VLX75T,XCE6VLX130T,XCE6VLX195T,XCE6VLX240T,XCE6VLX365T,XCE6VLX550T,XCE6VLX760,XCE6VSX315T,XCE6VSX475T,XCE6VHX250T,XCE6VHX255T,XCE6VHX380T,XCE6VHX565T, +Slices,11640,20000,31200,37680,56880,85920,118560,49200,74400,39360,39600,59760,88560, +Logic Cells,74496,128000,199680,241152,364032,549888,758784,314880,476160,251904,253440,382464,566784, +CLB Flip-Flops,93120,160000,249600,455040,687360,948480,393600,595200,314880,478080,708480,,, +Max Distributed RAM (Kb),1045,1740,3040,3650,4130,6200,8280,5090,7640,3040,3050,4570,6370, +Block RAM/FIFO w/ ECC (36 Kbit),156,264,344,416,416,632,720,704,64,504,516,768,912, +Total Block RAM (Kbit),5616,9504,12384,14976,14976,22752,25920,25344,38304,18144,18576,27648,32832, +Mixed-Mode Clock Managers (MMCM),6,10,10,12,12,18,18,12,18,12,12,18,18, +Max Single-Ended I/O Pins,360,600,600,720,720,1200,1200,720,840,320,480,720,720, +Max Differential I/O Pairs,180,300,300,360,360,600,600,360,420,160,240,360,360, +Total I/O Banks,9,15,15,18,18,30,30,18,21,8,12,18,18, +DSP48E1 Slices,288,480,640,768,576,864,864,1344,2016,576,576,864,864, +PCI Express Blocks,1,2,2,2,2,2,0,2,2,4,2,4,4, +10/100/1000 Ethernet MAC Blocks,4,4,4,4,4,4,0,4,4,4,2,4,4, +GTX Transceivers,12,20,20,24,24,36,0,24,36,48,24,48,48, +GTH Transceivers,0,0,0,0,0,0,0,0,0,0,24,24,24, +###, Pins (GTX, GTH) GTX (GTH) Pins,,,,,,,,,,,, +FF484,"240 (8, 0)","240 (8, 0)", , , , , , , , , , , , +FFG484,"240 (8, 0)","240 (8, 0)", , , , , , , , , , , , +FF784,"360 (12, 0)","400 (12, 0)","400 (12, 0)","400 (12, 0)",, , , , , , , , , +FFG784,"360 (12, 0)","400 (12, 0)","400 (12, 0)","400 (12, 0)",, , , , , , , , , +FF1156, ,"600 (20, 0)","600 (20, 0)","600 (20, 0)","600 (20, 0)", , ,"600 (20, 0)","600 (20, 0)", , , , , +FFG1156, ,"600 (20, 0)","600 (20, 0)","600 (20, 0)","600 (20, 0)", , ,"600 (20, 0)","600 (20, 0)", , , , , +FF1759, , , ,"720 (24, 0)","720 (24, 0)","840 (36, 0)", ,"720 (24, 0)","840 (36, 0)", , , , , +FFG1759, , , ,"720 (24, 0)","720 (24, 0)","840 (36, 0)", ,"720 (24, 0)","840 (36, 0)", , , , , +FF1760, , , , , ,"1200 (0, 0)","1200 (0, 0)", , , , , , , +FFG1760, , , , , ,"1200 (0, 0)","1200 (0, 0)", , , , , , , +FF1154, , , , , , , , , ,"320 (48, 0)", ,"320 (48, 0)", , +FFG1154, , , , , , , , , ,"320 (48, 0)", ,"320 (48, 0)", , +FF1155, , , , , , , , , , ,"440 (24, 12)","440 (24, 12)", , +FFG1155, , , , , , , , , , ,"440 (24, 12)","440 (24, 12)", , +FF1923, , , , , , , , , , ,"480 (24, 24)","720 (40, 24)","720 (40, 24)", +FFG1923, , , , , , , , , , ,"480 (24, 24)","720 (40, 24)","720 (40, 24) ", +FF1924, , , , , , ,,,, ,,"640 (48, 24)","640 (40, 24)", +FFG1924, , , , , , ,,,, ,,"640 (48, 24)","640 (40, 24)", diff --git a/xilinx_data/virtex6_shared.csv b/xilinx_data/virtex6_shared.csv new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/xilinx_data/virtex6_shared.csv diff --git a/xilinx_data/virtex7.csv b/xilinx_data/virtex7.csv new file mode 100644 index 0000000..d7ddcd3 --- /dev/null +++ b/xilinx_data/virtex7.csv @@ -0,0 +1,35 @@ +Part Number,XC7V585T,XC7V2000T,XC7VX330T,XC7VX415T,XC7VX485T,XC7VX550T,XC7VX690T,XC7VX980T,XC7VX1140T,XC7VH580T,XC7VH870T +Cost Reduction Part,XCE7V585T,n/a,XCE7VX330T,XCE7VX415T,XCE7VX485T,XCE7VX550T,XCE7VX690T,XCE7VX980T,n/a,n/a,n/a +Slices,91050,305400,51000,64400,75900,86600,108300,153000,178000,90700,136900 +Logic Cells,582720,1954560,326400,412160,485760,554240,693120,979200,1139200,580480,876160 +CLB Flip-Flops,728400,2443200,408000,515200,607200,692800,866400,1224000,1424000,725600,1095200 +Max Distributed RAM (Kbit),6938,21550,4388,6525,8175,8725,10888,13838,17700,8850,13275 +Block Ram/FIFO w/ ECC (36 Kbit each),795,1292,750,880,1030,1180,1470,1500,1880,940,1410 +Total Block RAM (Kbit),28620,46512,27000,31680,37080,42480,52920,54000,67680,33840,50760 +Clock Management Tiles (1 MMCM + 1 PLL),18,24,14,12,14,20,20,18,24,12,18 +Max Single-Ended I/O Pins,850,1200,700,600,700,600,1000,880,1100,600,650 +Max Differential I/O Pairs,408,576,336,288,336,288,480,432,528,288,312 +Total I/O Banks,17,24,14,12,14,16,20,18,22,12,13 +DSP48E1 Slices,1260,2160,1120,2160,2800,2880,3600,3600,3360,1680,2520 +PCI Express Gen2,3,4,n/a,n/a,4,n/a,n/a,n/a,n/a,n/a,n/a +PCI Express Gen3,n/a,n/a,2,2,n/a,2,3,3,4,2,3 +GTX 12.5 Gb/s Transceivers,36,36,0,0,56,0,0,0,0,0,0 +GTH 13.1 Gb/s Transceivers,0,0,28,48,0,80,80,72,96,48,72 +GTZ 28.05 Gb/s Transceivers,0,0,0,0,0,0,0,0,0,8,16 +SLRs,n/a,4,n/a,n/a,n/a,n/a,n/a,n/a,4,2,3 +####,"HR, HP (GTX, GTH)",,,,,,,,,, +FFG1157,"0, 600 (20, 0)", ,"0, 600 (0, 20)","0, 600 (0, 20)","0, 600 (20, 0)", ,"0, 600 (0, 20)", , ,, +FFG1761,"100, 750 (36, 0)", ,"50, 650 (0, 28)", ,"0, 700 (28, 0)", ,"0, 850 (0, 36)", , ,, +FHG1761, ,"0, 850 (36, 0)", , , , , , , ,, +FLG1925, ,"0, 1200 (16, 0)", , , , , , , ,, +FFG1158, , , ,"0, 350 (0, 48)","0, 350 (48, 0)","0, 350 (0, 48)","0, 350 (0, 48)", , ,, +FFG1926, , , , , , ,"0, 720 (0, 64)","0, 720 (0, 64)", ,, +FLG1926, , , , , , , , ,"0, 720 (0, 64)",, +FFG1927, , , ,"0, 600 (0, 48)","0, 600 (56, 0)","0, 600 (0, 80)","0, 600 (0, 80)", , ,, +FFG1928, , , , , , , ,"0, 480 (0, 72)", ,, +FLG1928, , , , , , , , ,"0, 480 (0, 96)",, +FFG1930, , , , ,"0, 700 (0, 24)", ,"0, 1000 (0, 24)","0, 900 (0, 24)", ,, +FLG1930, , , ,,,, ,,"0, 1100 (0, 24)",, +HCG1155,,,,,,,,,,"0, 400 (34 GTH, 8 GTZ)", +HCG1931,,,,,,,,,,"0, 600 (48 GTH, 8 GTZ)","0, 650 (48 GTH, 8 GTZ)" +HCG1932,,,,,,,,,,"0, 300 (48 GTH, 8 GTZ)","0, 300 (72 GTH, 16 GTZ)" diff --git a/xilinx_data/virtex7_shared.csv b/xilinx_data/virtex7_shared.csv new file mode 100644 index 0000000..b42639d --- /dev/null +++ b/xilinx_data/virtex7_shared.csv @@ -0,0 +1,2 @@ +AMS / XADC Blocks,1 +Configuration AES / HMAC Blocks,1 |