diff options
| -rw-r--r-- | xilinx_data/spartan6.csv | 25 | ||||
| -rw-r--r-- | xilinx_data/spartan6_shared.csv | 3 | ||||
| -rw-r--r-- | xilinx_data/zynq7000.csv | 25 | ||||
| -rw-r--r-- | xilinx_data/zynq7000_shared.csv | 3 |
4 files changed, 56 insertions, 0 deletions
diff --git a/xilinx_data/spartan6.csv b/xilinx_data/spartan6.csv new file mode 100644 index 0000000..bddbd43 --- /dev/null +++ b/xilinx_data/spartan6.csv @@ -0,0 +1,25 @@ +Part Prefix,XC6SLX4,XC6SLX9,XC6SLX16,XC6SLX25,XC6SLX45,XC6SLX75,XC6SLX100,XC6SLX150,XC6SLX25T,XC6SLX45T,XC6SLX75T,XC6SLX100T,XC6SLX150T +Slices,600,1430,2278,3758,6822,11662,15822,23038,3758,6822,11662,15822,23038 +Logic Cells,3840,9152,14579,24051,43661,74637,101261,147443,24051,43661,74637,101261,147443 +CLB Flip-Flops,4800,11440,18224,30064,54576,93296,126576,184304,30064,54576,93296,126576,184304 +Maximum Distributed RAM (Kb),75,90,136,229,401,692,976,1355,229,401,692,976,1355 +Black RAM (18 Kb each),12,32,32,52,116,172,268,268,52,116,172,268,268 +Total Block RAM (Kb),216,576,576,936,2088,3096,4824,4824,936,2088,3096,4824,4824 +Clock Management Tiles (CMT),2,2,2,2,4,6,6,6,2,4,6,6,6 +Maximum Single-Ended Pins,132,200,232,266,358,408,480,576,250,296,348,498,540 +Maximum Differential Pairs,66,100,116,133,179,204,240,288,125,148,174,249,270 +DSP48A Slices,8,16,32,38,58,132,180,180,38,58,132,180,180 +Endpoint Block for PCI Express,n/a,n/a,n/a,n/a,n/a,n/a,n/a,n/a,1,1,1,1,1 +Memory Controller Blocks,0,2,2,2,2,4,4,4,2,2,4,4,4 +GTP Low Power Transceivers,n/a,n/a,n/a,n/a,n/a,n/a,n/a,n/a,2,4,8,8,8 +Configuration Memory (Mb),2.7,2.7,3.7,6.4,11.9,19.6,26.5,33.8,6.4,11.9,19.6,26.5,33.8 +###,,,,,,,,,,,,, +CPG196,106,106,106,,,,,,,,,, +TQG144,102,102,,,,,,,,,,, +CSG225,132,160,160,,,,,,,,,, +CSG324,,200,232,226,218,,,,190,190,,, +CSG484,,,,,320,328,338,338,,296,292,296,296 +FTG256,,186,186,186,,,,,,,,, +FGG484,,,,,316,280,326,338,250,296,268,296,296 +FGG676,,,,,358,408,480,498,,,348,376,396 +FGG900,,,,,,,,576,,,,498,540 diff --git a/xilinx_data/spartan6_shared.csv b/xilinx_data/spartan6_shared.csv new file mode 100644 index 0000000..7a6cacc --- /dev/null +++ b/xilinx_data/spartan6_shared.csv @@ -0,0 +1,3 @@ +Widgets,123 +Whatchamecallems,Gazmo +Yub Yubs,3840 diff --git a/xilinx_data/zynq7000.csv b/xilinx_data/zynq7000.csv new file mode 100644 index 0000000..3b4133b --- /dev/null +++ b/xilinx_data/zynq7000.csv @@ -0,0 +1,25 @@ +Device Number,Z-7010,,Z-7020,,Z-7030,,,Z-7045,,,Z-7100, +Part Number Prefix,XC7Z010,,XC7Z020,,XC7Z030,,,XC7Z045,,,XC7Z100, +Max Processor Frequency,800 MHz,,800 MHz,,1 Ghz,,,1 Ghz,,,1 Ghz, +Xilinx FPGA Equivalent,Artix7,,Artix7,,Kintex7,,,Kintex7,,,Kintex7, +Look-Up Tables (LUTs),17600,,53200,,78600,,,218600,,,277400, +Flip-Flops,35200,,106400,,157200,,,437200,,,554800, +BRAM (# 36Kb Blocks),240 KB (60),,560 KB (140),,1060 KB (265),,,2180 KB (545),,,3020 KB (755), +DSP Slices (18x MACCs),80,,220,,400,,,900,,,2020, +Peak DSP Performance (Symmetric FIR),100 GMACs,,276 GMACs,,593 GMACs,,,1334 GMACs,,,2622 GMACs, +PCI Express,n/a,,n/a,,Gen2 x4,,,Gen2 x8,,,Gen2 x8, +Package,CLG225,CLG400,CLG400,CLG484,FBG484,FBG676,FFG676,FBG676,FFG676,FFG900,FFG900,FFG1156 +SoC I/O pins (excld. DDR),32,54,54,54,54,54,54,54,54,54,54,54 +SelectIO Pins,54,100,125,200,100,100,100,100,100,212,212,250 +High-Speed SelectIO Pins,n/a,n/a,n/a,n/a,63,150,150,150,150,150,150,150 +Serial Transceivers (GTP),n/a,n/a,n/a,n/a,4,4,4,8,8,16,16,16 +Max Transceiver Speed,n/a,n/a,n/a,n/a,6.6 Gb/s,6.6 Gb/s,12.5 Gb/s,6.6 Gb/s,12.5 Gb/s,12.5 Gb/s,10.3 Gb/s,10.3 Gb/s +###,,,,,,,,,,,, +CLG225,54/0,,,,,,,,,,, +CLG400,,100/0,125/0,,,,,,,,, +CLG484,,,,200/0,,,,,,,, +FBG484,,,,,100/63,,,,,,, +FBG676,,,,,,100/150,,100/150,,,, +FFG676,,,,,,,100/150,,100/150,,, +FFG900,,,,,,,,,,212/150,212/150, +FFG1156,,,,,,,,,,,,250/150 diff --git a/xilinx_data/zynq7000_shared.csv b/xilinx_data/zynq7000_shared.csv new file mode 100644 index 0000000..7a6cacc --- /dev/null +++ b/xilinx_data/zynq7000_shared.csv @@ -0,0 +1,3 @@ +Widgets,123 +Whatchamecallems,Gazmo +Yub Yubs,3840 |