From 0c921d542eb4359791cffd1737bf45184f6ae352 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Tue, 12 Jun 2012 10:23:39 +0200 Subject: [PATCH 2/8] MIPS: BCM63XX: Add flash type detection On BCM6358 and BCM6368 the attached flash type is exposed through a bootstrapping register. Use it for auto detecting the flash type on those and default to parallel flash for earlier SoCs. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: Maxime Bizon Cc: Florian Fainelli Cc: Kevin Cernekee Patchwork: https://patchwork.linux-mips.org/patch/3954/ Reviewed-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/dev-flash.c | 60 ++++++++++++++++++-- .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 6 ++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 9 +++ 3 files changed, 69 insertions(+), 6 deletions(-) --- a/arch/mips/bcm63xx/dev-flash.c +++ b/arch/mips/bcm63xx/dev-flash.c @@ -7,6 +7,7 @@ * * Copyright (C) 2008 Maxime Bizon * Copyright (C) 2008 Florian Fainelli + * Copyright (C) 2012 Jonas Gorski */ #include @@ -54,16 +55,63 @@ static struct platform_device mtd_dev = }, }; -int __init bcm63xx_flash_register(void) +static int __init bcm63xx_detect_flash_type(void) { u32 val; - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + switch (bcm63xx_get_cpu_id()) { + case BCM6338_CPU_ID: + case BCM6345_CPU_ID: + case BCM6348_CPU_ID: + /* no way to auto detect so assume parallel */ + return BCM63XX_FLASH_TYPE_PARALLEL; + case BCM6358_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); + if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) + return BCM63XX_FLASH_TYPE_PARALLEL; + else + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6368_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { + case STRAPBUS_6368_BOOT_SEL_NAND: + return BCM63XX_FLASH_TYPE_NAND; + case STRAPBUS_6368_BOOT_SEL_SERIAL: + return BCM63XX_FLASH_TYPE_SERIAL; + case STRAPBUS_6368_BOOT_SEL_PARALLEL: + return BCM63XX_FLASH_TYPE_PARALLEL; + } + default: + return -EINVAL; + } +} + +int __init bcm63xx_flash_register(void) +{ + int flash_type; + u32 val; - mtd_resources[0].start = val; - mtd_resources[0].end = 0x1FFFFFFF; + flash_type = bcm63xx_detect_flash_type(); - return platform_device_register(&mtd_dev); + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: + pr_warn("unsupported serial flash detected\n"); + return -ENODEV; + case BCM63XX_FLASH_TYPE_NAND: + pr_warn("unsupported NAND flash detected\n"); + return -ENODEV; + default: + pr_err("flash detection failed for BCM%x: %d\n", + bcm63xx_get_cpu_id(), flash_type); + return -ENODEV; + } } --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h @@ -1,6 +1,12 @@ #ifndef __BCM63XX_FLASH_H #define __BCM63XX_FLASH_H +enum { + BCM63XX_FLASH_TYPE_PARALLEL, + BCM63XX_FLASH_TYPE_SERIAL, + BCM63XX_FLASH_TYPE_NAND, +}; + int __init bcm63xx_flash_register(void); #endif /* __BCM63XX_FLASH_H */ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -507,6 +507,15 @@ #define GPIO_BASEMODE_6368_MASK 0x7 /* those bits must be kept as read in gpio basemode register*/ +#define GPIO_STRAPBUS_REG 0x40 +#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) +#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) +#define STRAPBUS_6368_BOOT_SEL_MASK 0x3 +#define STRAPBUS_6368_BOOT_SEL_NAND 0 +#define STRAPBUS_6368_BOOT_SEL_SERIAL 1 +#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 + + /************************************************************************* * _REG relative to RSET_ENET *************************************************************************/