From fc22669ed039ff4e2fc68931d80a672c614e76e0 Mon Sep 17 00:00:00 2001 From: juhosg Date: Sun, 25 Nov 2012 16:22:50 +0000 Subject: AA: ramips: set clk_is_20mhz for rt2x00 on RT3352/RT5350 Backport of r34270. Signed-off-by: Daniel Golle Signed-off-by: Gabor Juhos git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@34363 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target/linux/ramips/files/arch/mips/include') diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 949232dbd..943facb6d 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -111,6 +111,8 @@ #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 +#define RT3352_SYSCFG0_XTAL_SEL BIT(20) + #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) -- cgit v1.2.3