diff options
Diffstat (limited to 'target/linux/xburst/patches-3.3/0004-NAND-Add-support-for-subpage-reads-for-NAND_ECC_HW_O.patch')
| -rw-r--r-- | target/linux/xburst/patches-3.3/0004-NAND-Add-support-for-subpage-reads-for-NAND_ECC_HW_O.patch | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/target/linux/xburst/patches-3.3/0004-NAND-Add-support-for-subpage-reads-for-NAND_ECC_HW_O.patch b/target/linux/xburst/patches-3.3/0004-NAND-Add-support-for-subpage-reads-for-NAND_ECC_HW_O.patch new file mode 100644 index 000000000..477d3723e --- /dev/null +++ b/target/linux/xburst/patches-3.3/0004-NAND-Add-support-for-subpage-reads-for-NAND_ECC_HW_O.patch @@ -0,0 +1,144 @@ +From 297d8a7bdfb755778d4189ca2861dd2a6125e972 Mon Sep 17 00:00:00 2001 +From: Lars-Peter Clausen <lars@metafoo.de> +Date: Tue, 15 Mar 2011 12:33:41 +0100 +Subject: [PATCH 04/21] NAND: Add support for subpage reads for + NAND_ECC_HW_OOB_FIRST + +--- + drivers/mtd/nand/nand_base.c | 78 ++++++++++++++++++++++++++++++++++++++++-- + include/linux/mtd/nand.h | 8 ++-- + 2 files changed, 79 insertions(+), 7 deletions(-) + +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -1143,7 +1143,7 @@ static int nand_read_page_swecc(struct m + * @bufpoi: buffer to store read data + */ + static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, +- uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) ++ uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, int page) + { + int start_step, end_step, num_steps; + uint32_t *eccpos = chip->ecc.layout->eccpos; +@@ -1324,6 +1324,75 @@ static int nand_read_page_hwecc_oob_firs + } + + /** ++ * nand_read_subpage_hwecc_oob_first - [REPLACABLE] hw ecc based sub-page read function ++ * @mtd: mtd info structure ++ * @chip: nand chip info structure ++ * @data_offs: offset of requested data within the page ++ * @readlen: data length ++ * @bufpoi: buffer to store read data ++ * @page: page number to read ++ * ++ * Hardware ECC for large page chips, require OOB to be read first. ++ * For this ECC mode, the write_page method is re-used from ECC_HW. ++ * These methods read/write ECC from the OOB area, unlike the ++ * ECC_HW_SYNDROME support with multiple ECC steps, follows the ++ * "infix ECC" scheme and reads/writes ECC from the data area, by ++ * overwriting the NAND manufacturer bad block markings. ++ */ ++static int nand_read_subpage_hwecc_oob_first(struct mtd_info *mtd, struct nand_chip *chip, ++ uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, int page) ++{ ++ int start_step, end_step, num_steps; ++ uint32_t *eccpos = chip->ecc.layout->eccpos; ++ uint8_t *p; ++ int data_col_addr; ++ int eccsize = chip->ecc.size; ++ int eccbytes = chip->ecc.bytes; ++ uint8_t *ecc_code = chip->buffers->ecccode; ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ int i; ++ ++ /* Column address wihin the page aligned to ECC size */ ++ start_step = data_offs / chip->ecc.size; ++ end_step = (data_offs + readlen - 1) / chip->ecc.size; ++ num_steps = end_step - start_step + 1; ++ ++ data_col_addr = start_step * chip->ecc.size; ++ ++ /* Read the OOB area first */ ++ if (mtd->writesize > 512) { ++ chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); ++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); ++ } else { ++ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); ++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); ++ chip->cmdfunc(mtd, NAND_CMD_READ0, data_col_addr, page); ++ } ++ ++ for (i = 0; i < chip->ecc.total; i++) ++ ecc_code[i] = chip->oob_poi[eccpos[i]]; ++ ++ p = bufpoi + data_col_addr; ++ ++ for (i = eccbytes * start_step; num_steps; num_steps--, i += eccbytes, p += eccsize) { ++ int stat; ++ ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, p, eccsize); ++ chip->ecc.calculate(mtd, p, &ecc_calc[i]); ++ ++ stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); ++ if (stat < 0) ++ mtd->ecc_stats.failed++; ++ else ++ mtd->ecc_stats.corrected += stat; ++ } ++ ++ return 0; ++} ++ ++/** + * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read + * @mtd: mtd info structure + * @chip: nand chip info structure +@@ -1482,7 +1551,7 @@ static int nand_do_read_ops(struct mtd_i + bufpoi, page); + else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) + ret = chip->ecc.read_subpage(mtd, chip, +- col, bytes, bufpoi); ++ col, bytes, bufpoi, page); + else + ret = chip->ecc.read_page(mtd, chip, bufpoi, + page); +@@ -3293,8 +3362,11 @@ int nand_scan_tail(struct mtd_info *mtd) + "hardware ECC not possible\n"); + BUG(); + } +- if (!chip->ecc.read_page) ++ if (!chip->ecc.read_page) { + chip->ecc.read_page = nand_read_page_hwecc_oob_first; ++ if (!chip->ecc.read_subpage) ++ chip->ecc.read_subpage = nand_read_subpage_hwecc_oob_first; ++ } + + case NAND_ECC_HW: + /* Use standard hwecc read page function? */ +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -211,9 +211,9 @@ typedef enum { + #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) + #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) + #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) +-/* Large page NAND with SOFT_ECC should support subpage reads */ +-#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ +- && (chip->page_shift > 9)) ++/* Large page NAND with read_subpage set should support subpage reads */ ++#define NAND_SUBPAGE_READ(chip) (((chip)->ecc.read_subpage) \ ++ && ((chip)->page_shift > 9)) + + /* Mask to zero out the chip options, which come from the id table */ + #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) +@@ -367,7 +367,7 @@ struct nand_ecc_ctrl { + int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page); + int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, +- uint32_t offs, uint32_t len, uint8_t *buf); ++ uint32_t offs, uint32_t len, uint8_t *buf, int page); + void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf); + int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |