diff options
Diffstat (limited to 'target/linux/ar71xx')
316 files changed, 41785 insertions, 0 deletions
diff --git a/target/linux/ar71xx/Makefile b/target/linux/ar71xx/Makefile new file mode 100644 index 000000000..f86399381 --- /dev/null +++ b/target/linux/ar71xx/Makefile @@ -0,0 +1,29 @@ +# +# Copyright (C) 2008-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +BOARD:=ar71xx +BOARDNAME:=Atheros AR7xxx/AR9xxx +FEATURES:=squashfs jffs2 targz +CFLAGS:=-Os -pipe -mips32r2 -mtune=mips32r2 -fno-caller-saves +SUBTARGETS:=generic nand + +LINUX_VERSION:=3.3.8 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += \ + kmod-leds-gpio kmod-gpio-button-hotplug kmod-wdt-ath79 swconfig \ + kmod-ledtrig-default-on kmod-ledtrig-timer kmod-ledtrig-netdev \ + kmod-ath9k wpad-mini uboot-envtools + +define Target/Description + Build firmware images for Atheros AR7xxx/AR9xxx based boards. +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/ar71xx/base-files.mk b/target/linux/ar71xx/base-files.mk new file mode 100644 index 000000000..d6682bd38 --- /dev/null +++ b/target/linux/ar71xx/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/ar71xx/base-files/etc/defconfig/wndr3700/network b/target/linux/ar71xx/base-files/etc/defconfig/wndr3700/network new file mode 100644 index 000000000..69d7dc712 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/defconfig/wndr3700/network @@ -0,0 +1,69 @@ +config interface loopback + option ifname lo + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + +config interface lan + option ifname eth0.1 + option type bridge + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + +config interface wan + option ifname eth1 + option proto dhcp + +config switch + option name rtl8366s + option reset 1 + option enable_vlan 1 + # Blinkrate: 0=43ms; 1=84ms; 2=120ms; 3=170ms; 4=340ms; 5=670ms + option blinkrate 2 + +config switch_vlan + option device rtl8366s + option vlan 1 + option ports "0 1 2 3 5t" + +config switch_port + # Port 1 controls the GREEN configuration of LEDs for + # the switch and the section does not correspond to a real + # switch port. + # + # 0=LED off; 1=Collision/FDX; 2=Link/activity; 3=1000 Mb/s; + # 4=100 Mb/s; 5=10 Mb/s; 6=1000 Mb/s+activity; 7=100 Mb/s+activity; + # 8=10 Mb/s+activity; 9=10/100 Mb/s+activity; 10: Fiber; + # 11: Fault; 12: Link/activity(tx); 13: Link/activity(rx); + # 14: Link (master); 15: separate register + + option device rtl8366s + option port 1 + option led 6 + +config switch_port + # Port 2 controls the ORANGE configuration of LEDs for + # the switch and the section does not correspond to a real + # switch port. + # + # See the key above for switch port 1 for the meaning of the + # 'led' setting below. + + option device rtl8366s + option port 2 + option led 9 + +config switch_port + # Port 5 controls the configuration of the WAN LED and the + # section does not correspond to a real switch port. + # + # To toggle the use of green or orange LEDs for the WAN port, + # see the LED setting for wndr3700:green:wan in /etc/config/system. + # + # See the key above for switch port 1 for the meaning of the + # 'led' setting below. + + option device rtl8366s + option port 5 + option led 2 diff --git a/target/linux/ar71xx/base-files/etc/diag.sh b/target/linux/ar71xx/base-files/etc/diag.sh new file mode 100755 index 000000000..c3f97345c --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/diag.sh @@ -0,0 +1,196 @@ +#!/bin/sh +# +# Copyright (C) 2009 OpenWrt.org +# +# + +. /lib/ar71xx.sh + +status_led="" + +led_set_attr() { + [ -f "/sys/class/leds/$1/$2" ] && echo "$3" > "/sys/class/leds/$1/$2" +} + +status_led_set_timer() { + led_set_attr $status_led "trigger" "timer" + led_set_attr $status_led "delay_on" "$1" + led_set_attr $status_led "delay_off" "$2" +} + +status_led_on() { + led_set_attr $status_led "trigger" "none" + led_set_attr $status_led "brightness" 255 +} + +status_led_off() { + led_set_attr $status_led "trigger" "none" + led_set_attr $status_led "brightness" 0 +} + +get_status_led() { + case $(ar71xx_board_name) in + alfa-nx) + status_led="alfa:green:led_8" + ;; + all0305) + status_led="eap7660d:green:ds4" + ;; + ap136) + status_led="ap136:green:status" + ;; + ap81) + status_led="ap81:green:status" + ;; + ap83) + status_led="ap83:green:power" + ;; + ap96) + status_led="ap96:green:led2" + ;; + aw-nr580) + status_led="aw-nr580:green:ready" + ;; + bullet-m | rocket-m | nano-m | nanostation-m) + status_led="ubnt:green:link4" + ;; + db120) + status_led="db120:green:status" + ;; + dir-600-a1 |\ + dir-615-e4) + status_led="d-link:green:power" + ;; + dir-615-c1) + status_led="d-link:green:status" + ;; + dir-825-b1) + status_led="d-link:orange:power" + ;; + eap7660d) + status_led="eap7660d:green:ds4" + ;; + hornet-ub) + status_led="alfa:blue:wps" + ;; + ja76pf | \ + ja76pf2) + status_led="jjplus:green:led1" + ;; + ls-sr71) + status_led="ubnt:green:d22" + ;; + mzk-w04nu | \ + mzk-w300nh) + status_led="planex:green:status" + ;; + nbg460n_550n_550nh) + status_led="nbg460n:green:power" + ;; + om2p | \ + om2p-lc) + status_led="om2p:blue:power" + ;; + pb44) + status_led="pb44:amber:jump1" + ;; + rb-411 | rb-411u | rb-433 | rb-433u | rb-450 | rb-450g | rb-493) + status_led="rb4xx:yellow:user" + ;; + rb-750) + status_led="rb750:green:act" + ;; + routerstation | routerstation-pro) + status_led="ubnt:green:rf" + ;; + rw2458n) + status_led="rw2458n:green:d3" + ;; + tew-632brp) + status_led="tew-632brp:green:status" + ;; + tew-673gru) + status_led="trendnet:blue:wps" + ;; + tew-712br) + status_led="trendnet:green:power" + ;; + tl-mr3020) + status_led="tp-link:green:wps" + ;; + tl-mr3220 | \ + tl-mr3420 | \ + tl-wa901nd | \ + tl-wa901nd-v2 | \ + tl-wr1041n-v2 | \ + tl-wr1043nd | \ + tl-wr741nd | \ + tl-wr741nd-v4 | \ + tl-wr841n-v1 | \ + tl-wr841n-v7 | \ + tl-wr841n-v8 | \ + tl-wr941nd) + status_led="tp-link:green:system" + ;; + tl-wdr4300 | \ + tl-wr703n) + status_led="tp-link:blue:system" + ;; + tl-wr2543n) + status_led="tp-link:green:wps" + ;; + unifi) + status_led="ubnt:green:dome" + ;; + whr-g301n | \ + whr-hp-g300n | \ + whr-hp-gn | \ + wzr-hp-g300nh) + status_led="buffalo:green:router" + ;; + wlae-ag300n) + status_led="buffalo:green:status" + ;; + wzr-hp-ag300h | \ + wzr-hp-g300nh2) + status_led="buffalo:red:diag" + ;; + wndr3700) + status_led="wndr3700:green:power" + ;; + wnr2000) + status_led="wnr2000:green:power" + ;; + wp543) + status_led="wp543:green:diag" + ;; + wrt400n) + status_led="wrt400n:blue:wps" + ;; + wrt160nl) + status_led="wrt160nl:blue:wps" + ;; + zcn-1523h-2 | zcn-1523h-5) + status_led="zcn-1523h:amber:init" + ;; + esac; +} + +set_state() { + get_status_led + + case "$1" in + preinit) + insmod leds-gpio + insmod ledtrig-default-on + insmod ledtrig-timer + status_led_set_timer 200 200 + ;; + failsafe) + status_led_set_timer 50 50 + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix b/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix new file mode 100644 index 000000000..102415009 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix @@ -0,0 +1,51 @@ +#!/bin/sh + +# For AR9220 and AR9223, GPIO JTAG must explicit be disabled +# before LEDs start working. Do this when wifi device is +# detected. + +# +# $DEVPATH is not valid for some boards (including WZR-HP-AG300H). +# Manipulate the $DEVPATH to reach the corresponding phyN. +# + +devdir=`dirname $DEVPATH` +devdir=`dirname $devdir` +phydir=/sys$devdir/ieee80211 +phyname=`cat $phydir/phy*/name` + +if [ -z $phyname -o $ACTION != "add" ]; then exit 0; fi + +# +# ar922x_disable_gpio_jtag(): +# +# Emulate +# REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); +# for AR9220 and AR9223. +# + +ar922x_disable_gpio_jtag() +{ + local regidx=0x4054 + + [ -f /sys/kernel/debug/ieee80211/$1/ath9k/regidx ] && { + echo $regidx > /sys/kernel/debug/ieee80211/$1/ath9k/regidx + regval=`cat /sys/kernel/debug/ieee80211/$1/ath9k/regval` + regval=$((regval | 0x20000)) + echo regval $regval + echo $regval > /sys/kernel/debug/ieee80211/$1/ath9k/regval + } +} + +if [ $phyname -a $ACTION = "add" ]; then + + . /lib/ar71xx.sh + + case $(ar71xx_board_name) in + wzr-hp-ag300h) + ar922x_disable_gpio_jtag $phyname + ;; + esac; +fi + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/init.d/defconfig b/target/linux/ar71xx/base-files/etc/init.d/defconfig new file mode 100755 index 000000000..364fa4a6a --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/init.d/defconfig @@ -0,0 +1,20 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (C) 2009 OpenWrt.org +# + +START=05 + +start() { + . /lib/ar71xx.sh + + local board=$(ar71xx_board_name) + + [ ! -d /etc/defconfig/$board ] && return 0 + + for f in $( ls /etc/defconfig/$board ); do + if [ ! -e /etc/config/$f ]; then + cp /etc/defconfig/$board/$f /etc/config/ + fi + done +} diff --git a/target/linux/ar71xx/base-files/etc/inittab b/target/linux/ar71xx/base-files/etc/inittab new file mode 100644 index 000000000..17f829f6d --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/inittab @@ -0,0 +1,2 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/inittab-console-fixup b/target/linux/ar71xx/base-files/etc/uci-defaults/inittab-console-fixup new file mode 100755 index 000000000..4098b37a7 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/inittab-console-fixup @@ -0,0 +1,27 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +enable_console_login() { + local cons=$1 + local initline="$cons::askfirst:/bin/ash --login" + + grep -qs "^$initline" /etc/inittab || { + echo "$initline" >> /etc/inittab + sync + kill -HUP 1 + } +} + +inittab_console_fixup() { + for cons in ttyS0 ttyATH0; do + grep -qs "console=$cons" /proc/cmdline && { + enable_console_login $cons + } + done +} + +inittab_console_fixup + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/leds b/target/linux/ar71xx/base-files/etc/uci-defaults/leds new file mode 100755 index 000000000..cb4b68299 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/leds @@ -0,0 +1,209 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +alfa-nx) + ucidef_set_led_netdev "wan" "WAN" "alfa:green:led_2" "eth0" + ucidef_set_led_netdev "lan" "LAN" "alfa:green:led_3" "eth1" + ;; + +all0258n) + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "all0258n:red:rssilow" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "all0258n:yellow:rssimedium" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "all0258n:green:rssihigh" "wlan0" "70" "100" "-69" "8" + ;; + +all0315n) + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "all0315n:red:rssilow" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "all0315n:yellow:rssimedium" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "all0315n:green:rssihigh" "wlan0" "70" "100" "-69" "8" + ;; + +ap113) + ucidef_set_led_usbdev "usb" "USB" "ap113:green:usb" "1-1" + ;; + +db120) + ucidef_set_led_usbdev "usb" "USB" "db120:green:usb" "1-1" + ;; + +rb750) + ucidef_set_led_default "act" "act" "rb750:green:act" "1" + ucidef_set_led_netdev "port1" "port1" "rb750:green:port1" "eth1" + ucidef_set_led_switch "port2" "port2" "rb750:green:port2" "switch0" "0x10" + ucidef_set_led_switch "port3" "port3" "rb750:green:port3" "switch0" "0x08" + ucidef_set_led_switch "port4" "port4" "rb750:green:port4" "switch0" "0x04" + ucidef_set_led_switch "port5" "port5" "rb750:green:port5" "switch0" "0x02" + ;; + +dir-600-a1|\ +dir-615-e4) + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "d-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "d-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "d-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "d-link:green:lan4" "switch0" "0x10" + ;; + +dir-825-b1) + ucidef_set_led_usbdev "usb" "USB" "d-link:blue:usb" "1-1" + ;; + +hornet-ub) + ucidef_set_led_netdev "lan" "LAN" "alfa:blue:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "alfa:blue:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "alfa:blue:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "alfa:blue:usb" "1-1" + ;; + +mzk-w04u) + ucidef_set_led_usbdev "usb" "USB" "planex:green:usb" "1-1" + ;; + +mzk-w300nh) + ucidef_set_led_wlan "wlan" "WLAN" "planex:green:wlan" "phy0tpt" + ;; + +nbg460n_550n_550nh) + ucidef_set_led_wlan "wlan" "WLAN" "nbg460n:green:wlan" "phy0tpt" + ;; + +om2p | \ +om2p-lc) + ucidef_set_led_netdev "port1" "port1" "om2p:blue:wan" "eth0" + ucidef_set_led_netdev "port2" "port2" "om2p:blue:lan" "eth1" + ;; + +tew-712br) + ucidef_set_led_netdev "wan" "WAN" "trendnet:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "trendnet:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "trendnet:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "trendnet:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "trendnet:green:lan4" "switch0" "0x10" + ucidef_set_led_wlan "wlan" "WLAN" "trendnet:green:wlan" "phy0tpt" + ;; + +tl-mr11u | \ +tl-mr3020 | \ +tl-mr3040) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ;; + +tl-mr3220 | \ +tl-mr3420 ) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-wa901nd) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ;; + +tl-wa901nd-v2) + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wdr4300) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1.1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "1-1.2" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy0tpt" + ;; + +tl-wr741nd) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x10" + ;; + +tl-wr741nd-v4) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr841n-v8) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr941nd | \ +tl-wr1041n-v2) + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr1043nd) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr2543n) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ;; + +wrt160nl) + ucidef_set_led_wlan "wlan" "WLAN" "wrt160nl:blue:wlan" "phy0tpt" + ;; + +wndr3700) + ucidef_set_led_default "wan" "WAN LED (green)" "wndr3700:green:wan" "0" + ucidef_set_led_usbdev "usb" "USB" "wndr3700:green:usb" "1-1" + ;; + +whr-g301n |\ +whr-hp-g300n |\ +whr-hp-gn) + ucidef_set_led_netdev "wan" "WAN" "buffalo:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "buffalo:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "buffalo:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "buffalo:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "buffalo:green:lan4" "switch0" "0x10" + ;; + +wlae-ag300n) + ucidef_set_led_netdev "wireless" "WIRELESS" "buffalo:green:wireless" "wlan0" + ;; + +wzr-hp-ag300h) + ucidef_set_led_default "diag" "DIAG" "buffalo:red:diag" "0" + ucidef_set_led_netdev "router" "ROUTER" "buffalo:green:router" "eth1" + ucidef_set_led_usbdev "usb" "USB" "buffalo:green:usb" "1-1" + ;; + +wzr-hp-g300nh) + ucidef_set_led_wlan "wlan" "Wireless" "buffalo:green:wireless" "phy0tpt" + ucidef_set_led_netdev "router" "Router" "buffalo:green:router" "eth1" + ucidef_set_led_usbdev "usb" "USB" "buffalo:blue:usb" "1-1" + ;; + +zcn-1523h-2) + ucidef_set_led_netdev "lan1" "lan1" "zcn-1523h:green:lan1" "eth0" + ;; + +zcn-1523h-5) + ucidef_set_led_netdev "lan1" "lan1" "zcn-1523h:green:lan1" "eth0" + ucidef_set_led_netdev "lan2" "lan2" "zcn-1523h:green:lan2" "eth1" + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/network b/target/linux/ar71xx/base-files/etc/uci-defaults/network new file mode 100755 index 000000000..cd9e997d8 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/network @@ -0,0 +1,215 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +ucidef_set_interface_loopback + +board=$(ar71xx_board_name) + +case "$board" in +all0315n |\ +all0258n |\ +ja76pf2) + ucidef_set_interface_lan "eth0 eth1" + ;; + +db120 |\ +rb-2011l | \ +rb-2011uas-2hnd) + ucidef_set_interfaces_lan_wan "eth0.1 eth1" "eth0.2" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "eth0" "2" "0t 1" + ucidef_add_switch "eth1" "1" "1" + ucidef_add_switch_vlan "eth1" "1" "0 1 2 3 4 5" + ;; + +dir-825-b1|\ +tew-673gru) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "rtl8366s" "1" "1" + ucidef_add_switch_vlan "rtl8366s" "1" "0 1 2 3 5t" + ;; + +nbg460n_550n_550nh) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "rtl8366s" "1" "1" + ucidef_add_switch_vlan "rtl8366s" "0" "0 1 2 3 5" + ;; + +rb-433 |\ +rb-433u) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 5" + ;; + +rb-450) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "eth1" "1" "1" + ucidef_add_switch_vlan "eth1" "1" "0 1 2 3 5" + ;; + +rb-450g |\ +routerstation-pro) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +ap136 |\ +rb-750gl |\ +rb-751g |\ +wzr-hp-g450h) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +rb-493g) + ucidef_set_interfaces_lan_wan "eth0 eth1.1" "eth1.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch "switch1" "1" "1" + ucidef_add_switch_vlan "switch1" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch1" "2" "0t 5" + ;; + +wzr-hp-g300nh2 |\ +pb92 |\ +ap113) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0t 1 3 4 5" + ucidef_add_switch_vlan "eth0" "2" "0t 2" + ;; + +tl-wdr4300|\ +tl-wr1041n-v2) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "eth0" "2" "0t 1" + ;; + +tl-wr1043nd) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "rtl8366rb" "1" "1" + ucidef_add_switch_vlan "rtl8366rb" "1" "1 2 3 4 5t" + ucidef_add_switch_vlan "rtl8366rb" "2" "0 5t" + ;; + +tl-wr2543n) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 9t" + ucidef_add_switch_vlan "switch0" "2" "0 9t" + ;; + +tl-wr841n-v1|\ +tl-wr941nd) + ucidef_set_interface_raw "eth" "eth0" + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" + ;; + +tl-wr841n-v8) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +wrt160nl) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 1 2 3 4 5" + ;; + +wzr-hp-g300nh) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ;; + +all0305 |\ +aw-nr580 |\ +bullet-m |\ +eap7660d |\ +ew-dorin |\ +rb-411 |\ +tl-mr11u |\ +tl-mr3020 |\ +tl-mr3040 |\ +tl-wa901nd |\ +tl-wa901nd-v2 |\ +tl-wr703n |\ +wp543) + ucidef_set_interface_lan "eth0" + ;; + +alfa-ap96 |\ +alfa-nx |\ +ap83 |\ +jwap003 |\ +pb42 |\ +pb44 |\ +routerstation|\ +wpe72) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + +ap121 |\ +ap121-mini |\ +ap96 |\ +airrouter |\ +dir-600-a1 |\ +dir-615-c1 |\ +dir-615-e4 |\ +ja76pf |\ +rb-750 |\ +rb-751 |\ +tew-632brp |\ +tew-712br |\ +tl-mr3220 |\ +tl-mr3420 |\ +tl-wr741nd |\ +tl-wr741nd-v4 |\ +tl-wr841n-v7 |\ +whr-g301n |\ +whr-hp-g300n |\ +whr-hp-gn |\ +wzr-hp-ag300h) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 1 2 3 4" + ;; + +wzr-hp-g450h) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "eth0" "2" "0t 1" + ;; + +ew-dorin-router) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 2 3" + ;; + +*) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/vlan-migration b/target/linux/ar71xx/base-files/etc/uci-defaults/vlan-migration new file mode 100755 index 000000000..bea9493c8 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/vlan-migration @@ -0,0 +1,13 @@ +#!/bin/sh +# +# Copyright (C) 2010 OpenWrt.org +# + +local dev="$(uci -q get network.@switch_vlan[0].device)" +local vlan="$(uci -q get network.@switch_vlan[0].vlan)" + +if [ "$dev" = "rtl8366s" ] && [ "$vlan" = 0 ]; then + logger -t vlan-migration "VLAN 0 is invalid for RTL8366s, changing to 1" + uci set network.@switch_vlan[0].vlan=1 + uci commit network +fi diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/wrt160nl b/target/linux/ar71xx/base-files/etc/uci-defaults/wrt160nl new file mode 100755 index 000000000..dce28dde9 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/wrt160nl @@ -0,0 +1,16 @@ +#!/bin/sh +# +# Copyright (C) 2010 OpenWrt.org +# + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +wrt160nl_fixtrx() { + mtd -o 32 fixtrx firmware +} + +if [ "${board}" == "wrt160nl" ]; then + wrt160nl_fixtrx +fi diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh b/target/linux/ar71xx/base-files/lib/ar71xx.sh new file mode 100755 index 000000000..f3c32555f --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh @@ -0,0 +1,455 @@ +#!/bin/sh +# +# Copyright (C) 2009-2011 OpenWrt.org +# + +AR71XX_BOARD_NAME= +AR71XX_MODEL= + +ar71xx_get_mtd_offset_size_format() { + local mtd="$1" + local offset="$2" + local size="$3" + local format="$4" + local dev + + dev=$(find_mtd_part $mtd) + [ -z "$dev" ] && return + + dd if=$dev bs=1 skip=$offset count=$size 2>/dev/null | hexdump -v -e "1/1 \"$format\"" +} + +ar71xx_get_mtd_part_magic() { + local mtd="$1" + ar71xx_get_mtd_offset_size_format "$mtd" 0 4 %02x +} + +wndr3700_board_detect() { + local machine="$1" + local magic + local name + + name="wndr3700" + + magic="$(ar71xx_get_mtd_part_magic firmware)" + case $magic in + "33373030") + machine="NETGEAR WNDR3700" + ;; + "33373031") + local model + model=$(ar71xx_get_mtd_offset_size_format art 56 10 %c) + if [ -z "$model" ] || [ "$model" = $'\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff' ]; then + machine="NETGEAR WNDR3700v2" + elif [ -z "$model" ] || [ "$model" = $'\xff\xff\xff\xff\xff\xff\xff\xff\xffN' ]; then + machine="NETGEAR WNDRMAC" + else + machine="NETGEAR $model" + fi + ;; + esac + + AR71XX_BOARD_NAME="$name" + AR71XX_MODEL="$machine" +} + +tplink_get_hwid() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd if=$part bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_board_detect() { + local model="$1" + local hwid + local hwver + + hwid=$(tplink_get_hwid) + hwver=${hwid:6:2} + hwver="v${hwver#0}" + + case "$hwid" in + "070300"*) + model="TP-Link TL-WR703N" + ;; + "070100"*) + model="TP-Link TL-WA701N/ND" + ;; + "074000"*) + model="TP-Link TL-WR740N/ND" + ;; + "074100"*) + model="TP-Link TL-WR741N/ND" + ;; + "074300"*) + model="TP-Link TL-WR743N/ND" + ;; + "084100"*) + model="TP-Link TL-WR841N/ND" + ;; + "084200"*) + model="TP-Link TL-WR842N/ND" + ;; + "090100"*) + model="TP-Link TL-WA901N/ND" + ;; + "094100"*) + model="TP-Link TL-WR941N/ND" + ;; + "104100"*) + model="TP-Link TL-WR1041N/ND" + ;; + "104300"*) + model="TP-Link TL-WR1043N/ND" + ;; + "254300"*) + model="TP-Link TL-WR2543N/ND" + ;; + "110101"*) + model="TP-Link TL-MR11U" + ;; + "302000"*) + model="TP-Link TL-MR3020" + ;; + "304000"*) + model="TP-Link TL-MR3040" + ;; + "322000"*) + model="TP-Link TL-MR3220" + ;; + "342000"*) + model="TP-Link TL-MR3420" + ;; + "360000"*) + model="TP-Link TL-WDR3600" + ;; + "430000"*) + model="TP-Link TL-WDR4300" + ;; + "431000"*) + model="TP-Link TL-WDR4310" + ;; + *) + hwver="" + ;; + esac + + AR71XX_MODEL="$model $hwver" +} + +ar71xx_board_detect() { + local machine + local name + + machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo) + + case "$machine" in + *"AirRouter") + name="airrouter" + ;; + *"ALFA Network AP96") + name="alfa-ap96" + ;; + *"ALFA Network N2/N5") + name="alfa-nx" + ;; + *ALL0258N) + name="all0258n" + ;; + *ALL0305) + name="all0305" + ;; + *ALL0315N) + name="all0315n" + ;; + *AP113) + name="ap113" + ;; + *AP121) + name="ap121" + ;; + *AP121-MINI) + name="ap121-mini" + ;; + *"AP136 reference board") + name="ap136" + ;; + *AP81) + name="ap81" + ;; + *AP83) + name="ap83" + ;; + *"Atheros AP96") + name="ap96" + ;; + *AW-NR580) + name="aw-nr580" + ;; + *"DB120 reference board") + name="db120" + ;; + *"DIR-600 rev. A1") + name="dir-600-a1" + ;; + *"DIR-615 rev. E4") + name="dir-615-e4" + ;; + *"DIR-825 rev. B1") + name="dir-825-b1" + ;; + *EAP7660D) + name="eap7660d" + ;; + *JA76PF) + name="ja76pf" + ;; + *JA76PF2) + name="ja76pf2" + ;; + *"Bullet M") + name="bullet-m" + ;; + *"Nanostation M") + name="nanostation-m" + ;; + *JWAP003) + name="jwap003" + ;; + *"Hornet-UB") + name="hornet-ub" + ;; + *LS-SR71) + name="ls-sr71" + ;; + *MZK-W04NU) + name="mzk-w04nu" + ;; + *MZK-W300NH) + name="mzk-w300nh" + ;; + *"NBG460N/550N/550NH") + name="nbg460n_550n_550nh" + ;; + *OM2P) + name="om2p" + ;; + *"OM2P LC") + name="om2p-lc" + ;; + *PB42) + name="pb42" + ;; + *"PB44 reference board") + name="pb44" + ;; + *PB92) + name="pb92" + ;; + *"RouterBOARD 411/A/AH") + name="rb-411" + ;; + *"RouterBOARD 411U") + name="rb-411u" + ;; + *"RouterBOARD 433/AH") + name="rb-433" + ;; + *"RouterBOARD 433UAH") + name="rb-433u" + ;; + *"RouterBOARD 450") + name="rb-450" + ;; + *"RouterBOARD 450G") + name="rb-450g" + ;; + *"RouterBOARD 493/AH") + name="rb-493" + ;; + *"RouterBOARD 493G") + name="rb-493g" + ;; + *"RouterBOARD 750") + name="rb-750" + ;; + *"RouterBOARD 750GL") + name="rb-750gl" + ;; + *"RouterBOARD 751") + name="rb-751" + ;; + *"RouterBOARD 751G") + name="rb-751g" + ;; + *"RouterBOARD 2011L") + name="rb-2011l" + ;; + *"RouterBOARD 2011UAS-2HnD") + name="rb-2011uas-2hnd" + ;; + *"Rocket M") + name="rocket-m" + ;; + *RouterStation) + name="routerstation" + ;; + *"RouterStation Pro") + name="routerstation-pro" + ;; + *RW2458N) + name="rw2458n" + ;; + *TEW-632BRP) + name="tew-632brp" + ;; + *TEW-673GRU) + name="tew-673gru" + ;; + *TEW-712BR) + name="tew-712br" + ;; + *"TL-WR1041N v2") + name="tl-wr1041n-v2" + ;; + *TL-WR1043ND) + name="tl-wr1043nd" + ;; + *TL-WR2543N*) + name="tl-wr2543n" + ;; + *"DIR-615 rev. C1") + name="dir-615-c1" + ;; + *TL-MR3020) + name="tl-mr3020" + ;; + *TL-MR3040) + name="tl-mr3040" + ;; + *TL-MR3220) + name="tl-mr3220" + ;; + *TL-MR3420) + name="tl-mr3420" + ;; + *TL-WA901ND) + name="tl-wa901nd" + ;; + *"TL-WA901ND v2") + name="tl-wa901nd-v2" + ;; + *"TL-WDR3600/4300/4310") + name="tl-wdr4300" + ;; + *TL-WR741ND) + name="tl-wr741nd" + ;; + *"TL-WR741ND v4") + name="tl-wr741nd-v4" + ;; + *"TL-WR841N v1") + name="tl-wr841n-v1" + ;; + *"TL-WR841N/ND v7") + name="tl-wr841n-v7" + ;; + *"TL-WR841N/ND v8") + name="tl-wr841n-v8" + ;; + *TL-WR941ND) + name="tl-wr941nd" + ;; + *"TL-WR703N v1") + name="tl-wr703n" + ;; + *"TL-MR11U") + name="tl-mr11u" + ;; + *UniFi) + name="unifi" + ;; + *WHR-G301N) + name="whr-g301n" + ;; + *WHR-HP-GN) + name="whr-hp-gn" + ;; + *WLAE-AG300N) + name="wlae-ag300n" + ;; + *WP543) + name="wp543" + ;; + *WPE72) + name="wpe72" + ;; + *"WNDR3700/WNDR3800/WNDRMAC") + wndr3700_board_detect "$machine" + ;; + *WNR2000) + name="wnr2000" + ;; + *WRT160NL) + name="wrt160nl" + ;; + *WRT400N) + name="wrt400n" + ;; + *WZR-HP-AG300H) + name="wzr-hp-ag300h" + ;; + *WZR-HP-G300NH) + name="wzr-hp-g300nh" + ;; + *WZR-HP-G450H) + name="wzr-hp-g450h" + ;; + *WZR-HP-G300NH2) + name="wzr-hp-g300nh2" + ;; + *WHR-HP-G300N) + name="whr-hp-g300n" + ;; + *ZCN-1523H-2) + name="zcn-1523h-2" + ;; + *ZCN-1523H-5) + name="zcn-1523h-5" + ;; + *EmbWir-Dorin) + name="ew-dorin" + ;; + *EmbWir-Dorin-Router) + name="ew-dorin-router" + ;; + esac + + case "$machine" in + *TL-WR* | *TL-WA* | *TL-MR*) + tplink_board_detect "$machine" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$AR71XX_BOARD_NAME" ] && AR71XX_BOARD_NAME="$name" + [ -z "$AR71XX_MODEL" ] && AR71XX_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$AR71XX_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$AR71XX_MODEL" > /tmp/sysinfo/model +} + +ar71xx_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh b/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh new file mode 100644 index 000000000..ff5407a0d --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_ar71xx() { + . /lib/ar71xx.sh + + ar71xx_board_detect +} + +boot_hook_add preinit_main do_ar71xx diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_enable_reset_button_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_enable_reset_button_ar71xx new file mode 100644 index 000000000..317c8d15a --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_enable_reset_button_ar71xx @@ -0,0 +1,13 @@ +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + + +preinit_enable_reset_button() { + insmod gpio-button-hotplug +} + +boot_hook_add preinit_main preinit_enable_reset_button + diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx new file mode 100644 index 000000000..f8bb7b76c --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx @@ -0,0 +1,39 @@ +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + +fetch_mac_from_mtd() { + local mtd_part=$1 + local lan_env=$2 + local wan_env=$3 + local mtd mac + + mtd=$(grep $mtd_part /proc/mtd | cut -d: -f1) + [ -z $mtd ] && return + + mac=$(grep $lan_env /dev/$mtd | cut -d= -f2) + [ ! -z $mac ] && ifconfig eth0 hw ether $mac 2>/dev/null + + mac=$(grep $wan_env /dev/$mtd | cut -d= -f2) + [ ! -z $mac ] && ifconfig eth1 hw ether $mac 2>/dev/null +} + +preinit_set_mac_address() { + case $(ar71xx_board_name) in + tew-632brp) + fetch_mac_from_mtd config lan_mac wan_mac + ;; + dir-615-c1) + fetch_mac_from_mtd config lan_mac wan_mac + echo 1 > /sys/class/leds/dir-615-c1:green:wancpu/brightness + ;; + wrt160nl) + fetch_mac_from_mtd nvram lan_hwaddr wan_hwaddr + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address + diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx new file mode 100644 index 000000000..8611dce81 --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx @@ -0,0 +1,16 @@ +#!/bin/sh + +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + +set_preinit_iface() { + ifname=eth0 +} + +boot_hook_add preinit_main set_preinit_iface + + + diff --git a/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh b/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh new file mode 100644 index 000000000..9a375ff19 --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh @@ -0,0 +1,160 @@ +# The U-Boot loader of the some Allnet devices requires image sizes and +# checksums to be provided in the U-Boot environment. +# In case the check fails during boot, a failsafe-system is started to provide +# a minimal web-interface for flashing a new firmware. + +# make sure we got uboot-envtools and fw_env.config copied over to the ramfs +platform_add_ramfs_ubootenv() { + [ -e /usr/sbin/fw_printenv ] && install_bin /usr/sbin/fw_printenv /usr/sbin/fw_setenv + [ -e /etc/fw_env.config ] && install_file /etc/fw_env.config +} +append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv + +# determine size of the main firmware partition +platform_get_firmware_size() { + local dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + firmware) + printf "%d" "0x$size" + break + ;; + esac + done < /proc/mtd +} + +# get the first 4 bytes (magic) of a given file starting at offset in hex format +get_magic_long_at() { + dd if="$1" skip=$(( $CI_BLKSZ / 4 * $2 )) bs=4 count=1 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +get_filesize() { + wc -c "$1" | while read image_size _n ; do echo $image_size ; break; done +} + +# scan through the update image pages until matching a magic +platform_get_offset() { + offsetcount=0 + magiclong="x" + if [ -n "$3" ]; then + offsetcount=$3 + fi + while magiclong=$( get_magic_long_at "$1" "$offsetcount" ) && [ -n "$magiclong" ]; do + case "$magiclong" in + "2705"*) + # U-Boot image magic + if [ "$2" = "uImage" ]; then + echo $offsetcount + return + fi + ;; + "68737173"|"73717368") + # SquashFS + if [ "$2" = "rootfs" ]; then + echo $offsetcount + return + fi + ;; + "deadc0de"|"19852003") + # JFFS2 empty page + if [ "$2" = "rootfs-data" ]; then + echo $offsetcount + return + fi + ;; + esac + offsetcount=$(( $offsetcount + 1 )) + done +} + +platform_check_image_allnet() { + local fw_printenv=/usr/sbin/fw_printenv + [ ! -n "$fw_printenv" -o ! -x "$fw_printenv" ] && { + echo "Please install uboot-envtools!" + return 1 + } + + [ ! -r "/etc/fw_env.config" ] && { + echo "/etc/fw_env.config is missing" + return 1 + } + + local image_size=$( get_filesize "$1" ) + local firmware_size=$( platform_get_firmware_size ) + [ $image_size -ge $firmware_size ] && + { + echo "upgrade image is too big (${image_size}b > ${firmware_size}b)" + } + + local vmlinux_blockoffset=$( platform_get_offset "$1" uImage ) + [ -z $vmlinux_blockoffset ] && { + echo "vmlinux-uImage not found" + return 1 + } + + local rootfs_blockoffset=$( platform_get_offset "$1" rootfs "$vmlinux_blockoffset" ) + [ -z $rootfs_blockoffset ] && { + echo "missing rootfs" + return 1 + } + + local data_blockoffset=$( platform_get_offset "$1" rootfs-data "$rootfs_blockoffset" ) + [ -z $data_blockoffset ] && { + echo "rootfs doesn't have JFFS2 end marker" + return 1 + } + + return 0 +} + +platform_do_upgrade_allnet() { + local firmware_base_addr=$( printf "%d" "$1" ) + local vmlinux_blockoffset=$( platform_get_offset "$2" uImage ) + if [ ! -n "$vmlinux_blockoffset" ]; then + echo "can't determine uImage offset" + return 1 + fi + local rootfs_blockoffset=$( platform_get_offset "$2" rootfs $(( $vmlinux_blockoffset + 1 )) ) + local vmlinux_offset=$(( $vmlinux_blockoffset * $CI_BLKSZ )) + local vmlinux_addr=$(( $firmware_base_addr + $vmlinux_offset )) + local vmlinux_hexaddr=0x$( printf "%08x" "$vmlinux_addr" ) + if [ ! -n "$rootfs_blockoffset" ]; then + echo "can't determine rootfs offset" + return 1 + fi + local rootfs_offset=$(( $rootfs_blockoffset * $CI_BLKSZ )) + local rootfs_addr=$(( $firmware_base_addr + $rootfs_offset )) + local rootfs_hexaddr=0x$( printf "%08x" "$rootfs_addr" ) + local vmlinux_blockcount=$(( $rootfs_blockoffset - $vmlinux_blockoffset )) + local vmlinux_size=$(( $rootfs_offset - $vmlinux_offset )) + local vmlinux_hexsize=0x$( printf "%08x" "$vmlinux_size" ) + local data_blockoffset=$( platform_get_offset "$2" rootfs-data $(( $rootfs_blockoffset + 1 )) ) + if [ ! -n "$data_blockoffset" ]; then + echo "can't determine rootfs size" + return 1 + fi + local data_offset=$(( $data_blockoffset * $CI_BLKSZ )) + local rootfs_blockcount=$(( $data_blockoffset - $rootfs_blockoffset )) + local rootfs_size=$(( $data_offset - $rootfs_offset )) + local rootfs_hexsize=0x$( printf "%08x" "$rootfs_size" ) + + local rootfs_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$rootfs_blockoffset count=$rootfs_blockcount 2>/dev/null | md5sum -); rootfs_md5="${rootfs_md5%% *}" + local vmlinux_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$vmlinux_blockoffset count=$vmlinux_blockcount 2>/dev/null | md5sum -); vmlinux_md5="${vmlinux_md5%% *}" + # this needs a recent version of uboot-envtools! + cat >/tmp/fw_env_upgrade <<EOF +vmlinux_start_addr $vmlinux_hexaddr +vmlinux_size $vmlinux_hexsize +vmlinux_checksum $vmlinux_md5 +rootfs_start_addr $rootfs_hexaddr +rootfs_size $rootfs_hexsize +rootfs_checksum $rootfs_md5 +bootcmd bootm $vmlinux_hexaddr +EOF + fw_setenv -s /tmp/fw_env_upgrade || { + echo "failed to update U-Boot environment" + return 1 + } + shift + default_do_upgrade "$@" +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/dir825.sh b/target/linux/ar71xx/base-files/lib/upgrade/dir825.sh new file mode 100644 index 000000000..e16128a9c --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/dir825.sh @@ -0,0 +1,177 @@ +#!/bin/sh +# +# Copyright (C) 2012 OpenWrt.org +# + +. /lib/functions.sh +. /lib/ar71xx.sh + +get_mtd_part_size() { + local part_name=$1 + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + if [ "$name" = "$part_name" ]; then + echo $((0x$size)) + break + fi + done < /proc/mtd +} + +get_magic_at() { + local mtddev=$1 + local pos=$2 + dd bs=1 count=2 skip=$pos if=$mtddev 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +dir825b_is_caldata_valid() { + local mtddev=$1 + local magic + + magic=$(get_magic_at $mtddev 4096) + [ "$magic" != "a55a" ] && return 0 + + magic=$(get_magic_at $mtddev 20480) + [ "$magic" != "a55a" ] && return 0 + + return 1 +} + +dir825b_copy_caldata() { + local cal_src=$1 + local cal_dst=$2 + local mtd_src + local mtd_dst + local md5_src + local md5_dst + + mtd_src=$(find_mtd_part $cal_src) + [ -z "$mtd_src" ] && { + echo "no $cal_src partition found" + return 1 + } + + mtd_dst=$(find_mtd_part $cal_dst) + [ -z "$mtd_dst" ] && { + echo "no $cal_dst partition found" + return 1 + } + + dir825b_is_caldata_valid "$mtd_src" && { + echo "no valid calibration data found in $cal_src" + return 1 + } + + dir825b_is_caldata_valid "$mtd_dst" && { + echo "Copying calibration data from $cal_src to $cal_dst..." + dd if="$mtd_src" 2>/dev/null | mtd -q -q write - "$cal_dst" + } + + md5_src=$(md5sum "$mtd_src") && md5_src="${md5_src%% *}" + md5_dst=$(md5sum "$mtd_dst") && md5_dst="${md5_dst%% *}" + + [ "$md5_src" != "$md5_dst" ] && { + echo "calibration data mismatch $cal_src:$md5_src $cal_dst:$md5_dst" + return 1 + } + + return 0 +} + +dir825b_do_upgrade_combined() { + local fw_part=$1 + local fw_file=$2 + local fw_mtd=$(find_mtd_part $fw_part) + local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null) + local fw_blocks=$(($fw_length / 65536)) + + if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + sync + dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \ + mtd $append write - "$fw_part" + fi +} + +dir825b_check_image() { + local magic="$(get_magic_long "$1")" + local fw_mtd=$(find_mtd_part "firmware_orig") + + case "$magic" in + "27051956") + ;; + "43493030") + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=64k skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + local fw_len=$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local fw_part_len=$(get_mtd_part_size "firmware") + + if [ -z "$fw_mtd" ]; then + ask_bool 0 "Do you have a backup of the caldata partition?" || { + echo "Warning, please make sure that you have a backup of the caldata partition." + echo "Once you have that, use 'sysupgrade -i' for upgrading to the 'fat' firmware." + return 1 + } + fi + + if [ -z "$md5_img" -o -z "$md5_chk" ]; then + echo "Unable to get image checksums. Maybe you are using a streamed image?" + return 1 + fi + + if [ "$md5_img" != "$md5_chk" ]; then + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + + fw_len=$((0x$fw_len)) + fw_part_len=${fw_part_len:-0} + + if [ $fw_part_len -lt $fw_len ]; then + echo "The upgrade image is too big (size:$fw_len available:$fw_part_len)" + return 1 + fi + ;; + *) + echo "Unsupported image format." + return 1 + ;; + esac + + return 0 +} + +platform_do_upgrade_dir825b() { + local magic="$(get_magic_long "$1")" + local fw_mtd=$(find_mtd_part "firmware_orig") + + case "$magic" in + "27051956") + if [ -n "$fw_mtd" ]; then + # restore calibration data before downgrading to + # the normal image + dir825b_copy_caldata "caldata" "caldata_orig" || { + echo "unable to restore calibration data" + exit 1 + } + PART_NAME="firmware_orig" + else + PART_NAME="firmware" + fi + default_do_upgrade "$ARGV" + ;; + "43493030") + if [ -z "$fw_mtd" ]; then + # backup calibration data before upgrading to the + # fat image + dir825b_copy_caldata "caldata" "caldata_copy" || { + echo "unable to backup calibration data" + exit 1 + } + fi + dir825b_do_upgrade_combined "firmware" "$ARGV" + ;; + esac +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/om2p.sh b/target/linux/ar71xx/base-files/lib/upgrade/om2p.sh new file mode 100644 index 000000000..d9a8bbb7f --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/om2p.sh @@ -0,0 +1,169 @@ +# The U-Boot loader of the OM2P requires image sizes and checksums to be +# provided in the U-Boot environment. +# The OM2P comes with 2 main partitions - while one is active sysupgrade +# will flash the other. The boot order is changed to boot the newly +# flashed partition. If the new partition can't be booted due to upgrade +# failures the previously used partition is loaded. + +trim() +{ + echo $1 +} + +cfg_value_get() +{ + local cfg=$1 cfg_opt + local section=$2 our_section=0 + local param=$3 our_param= + + for cfg_opt in $cfg + do + [ "$cfg_opt" = "[$section]" ] && our_section=1 && continue + [ "$our_section" = "1" ] || continue + + our_param=$(echo ${cfg_opt%%=*}) + [ "$param" = "$our_param" ] && echo ${cfg_opt##*=} && break + done +} + +# make sure we got uboot-envtools and fw_env.config copied over to the ramfs +platform_add_ramfs_ubootenv() +{ + [ -e /usr/sbin/fw_printenv ] && install_bin /usr/sbin/fw_printenv /usr/sbin/fw_setenv + [ -e /etc/fw_env.config ] && install_file /etc/fw_env.config +} +append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv + +platform_check_image_om2p() +{ + local img_magic=$1 + local img_path=$2 + local fw_printenv=/usr/sbin/fw_printenv + local img_board_target= img_num_files= i=0 + local cfg_name= kernel_name= rootfs_name= + + case "$img_magic" in + # Combined Extended Image v1 + 43453031) + img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null)) + img_num_files=$(trim $(dd if="$img_path" bs=2 skip=18 count=1 2>/dev/null)) + ;; + *) + echo "Invalid image ($img_magic). Use combined extended images on this platform" + return 1 + ;; + esac + + case "$img_board_target" in + OM2P) + ;; + *) + echo "Invalid board target ($img_board_target). Use the correct image for this platform" + return 1 + ;; + esac + + [ $img_num_files -ne 3 ] && { + echo "Invalid number of embedded images ($img_num_files). Use the correct image for this platform" + return 1 + } + + cfg_name=$(trim $(dd if="$img_path" bs=2 skip=19 count=16 2>/dev/null)) + + [ "$cfg_name" != "fwupgrade.cfg" ] && { + echo "Invalid embedded config file ($cfg_name). Use the correct image for this platform" + return 1 + } + + kernel_name=$(trim $(dd if="$img_path" bs=2 skip=55 count=16 2>/dev/null)) + + [ "$kernel_name" != "kernel" ] && { + echo "Invalid embedded kernel file ($kernel_name). Use the correct image for this platform" + return 1 + } + + rootfs_name=$(trim $(dd if="$img_path" bs=2 skip=91 count=16 2>/dev/null)) + + [ "$rootfs_name" != "rootfs" ] && { + echo "Invalid embedded kernel file ($rootfs_name). Use the correct image for this platform" + return 1 + } + + [ ! -x "$fw_printenv" ] && { + echo "Please install uboot-envtools!" + return 1 + } + + [ ! -r "/etc/fw_env.config" ] && { + echo "/etc/fw_env.config is missing" + return 1 + } + + return 0 +} + +platform_do_upgrade_om2p() +{ + local img_path=$1 + local kernel_start_addr= kernel_size= kernel_md5= + local rootfs_size= rootfs_checksize= rootfs_md5= + local kernel_bsize= total_size=7340032 + local data_offset=$((64 * 1024)) block_size=$((256 * 1024)) offset= + local uboot_env_upgrade="/tmp/fw_env_upgrade" + local cfg_size= kernel_size= rootfs_size= + local append="" + + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + cfg_size=$(dd if="$img_path" bs=2 skip=35 count=4 2>/dev/null) + kernel_size=$(dd if="$img_path" bs=2 skip=71 count=4 2>/dev/null) + rootfs_size=$(dd if="$img_path" bs=2 skip=107 count=4 2>/dev/null) + + cfg_content=$(dd if="$img_path" bs=1 skip=$data_offset count=$(echo $((0x$cfg_size))) 2>/dev/null) + + kernel_md5=$(cfg_value_get "$cfg_content" "vmlinux" "md5sum") + rootfs_md5=$(cfg_value_get "$cfg_content" "rootfs" "md5sum") + rootfs_checksize=$(cfg_value_get "$cfg_content" "rootfs" "checksize") + + if [ "$((0x$kernel_size % $block_size))" = "0" ] + then + kernel_bsize=$(echo $((0x$kernel_size))) + else + kernel_bsize=$((0x$kernel_size + ($block_size - (0x$kernel_size % $block_size)))) + fi + + mtd -q erase inactive + + offset=$(echo $(($data_offset + 0x$cfg_size + 0x$kernel_size))) + dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$rootfs_size))) 2>&- | mtd -n -p $kernel_bsize $append write - "inactive" + + offset=$(echo $(($data_offset + 0x$cfg_size))) + dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$kernel_size))) 2>&- | mtd -n write - "inactive" + + rm $uboot_env_upgrade 2>&- + + if [ "$(grep 'mtd3:.*inactive' /proc/mtd)" ] + then + printf "kernel_size_1 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade + printf "rootfs_size_1 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade + printf "bootseq 1,2\n" >> $uboot_env_upgrade + kernel_start_addr=0x9f1c0000 + else + printf "kernel_size_2 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade + printf "rootfs_size_2 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade + printf "bootseq 2,1\n" >> $uboot_env_upgrade + kernel_start_addr=0x9f8c0000 + fi + + printf "vmlinux_start_addr %s\n" $kernel_start_addr >> $uboot_env_upgrade + printf "vmlinux_size 0x%s\n" $kernel_size >> $uboot_env_upgrade + printf "vmlinux_checksum %s\n" $kernel_md5 >> $uboot_env_upgrade + printf "rootfs_start_addr 0x%x\n" $(($kernel_start_addr + $kernel_bsize)) >> $uboot_env_upgrade + printf "rootfs_size %s\n" $rootfs_checksize >> $uboot_env_upgrade + printf "rootfs_checksum %s\n" $rootfs_md5 >> $uboot_env_upgrade + + fw_setenv -s $uboot_env_upgrade || { + echo "failed to update U-Boot environment" + return 1 + } +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh new file mode 100755 index 000000000..8ec958d79 --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,269 @@ +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/ar71xx.sh + +PART_NAME=firmware +RAMFS_COPY_DATA=/lib/ar71xx.sh + +CI_BLKSZ=65536 +CI_LDADR=0x80060000 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|vmlinux|kernel|linux|rootfs|filesystem) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|vmlinux|kernel|linux) + echo "$part" + break + ;; + esac + done +} + +platform_do_upgrade_combined() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt ${kern_blocks:-0} ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + ( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \ + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \ + mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions + fi +} + +tplink_get_image_hwid() { + get_image "$@" | dd bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +platform_check_image() { + local board=$(ar71xx_board_name) + local magic="$(get_magic_word "$1")" + local magic_long="$(get_magic_long "$1")" + + [ "$ARGC" -gt 1 ] && return 1 + + case "$board" in + all0315n | \ + all0258n ) + platform_check_image_allnet "$1" && return 0 + return 1 + ;; + alfa-ap96 | \ + alfa-nx | \ + ap113 | \ + ap121 | \ + ap121-mini | \ + ap136 | \ + ap96 | \ + db120 | \ + hornet-ub | \ + zcn-1523h-2 | \ + zcn-1523h-5) + [ "$magic_long" != "68737173" -a "$magic_long" != "19852003" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + ap81 | \ + ap83 | \ + dir-600-a1 | \ + dir-615-c1 | \ + dir-615-e4 | \ + ew-dorin | \ + ew-dorin-router | \ + mzk-w04nu | \ + mzk-w300nh | \ + tew-632brp | \ + tew-712br | \ + wrt400n | \ + airrouter | \ + bullet-m | \ + nanostation-m | \ + rocket-m | \ + rw2458n | \ + wzr-hp-g300nh2 | \ + wzr-hp-g300nh | \ + wzr-hp-g450h | \ + wzr-hp-ag300h | \ + whr-g301n | \ + whr-hp-g300n | \ + whr-hp-gn | \ + wlae-ag300n | \ + nbg460n_550n_550nh | \ + unifi ) + [ "$magic" != "2705" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + + dir-825-b1 | \ + tew-673gru) + dir825b_check_image "$1" && return 0 + ;; + + om2p | \ + om2p-lc) + platform_check_image_om2p "$magic_long" "$1" && return 0 + return 1 + ;; + tl-mr11u | \ + tl-mr3020 | \ + tl-mr3040 | \ + tl-mr3220 | \ + tl-mr3420 | \ + tl-wa901nd | \ + tl-wa901nd-v2 | \ + tl-wdr4300 | \ + tl-wr703n | \ + tl-wr741nd | \ + tl-wr741nd-v4 | \ + tl-wr841n-v1 | \ + tl-wr841n-v7 | \ + tl-wr841n-v8 | \ + tl-wr941nd | \ + tl-wr1041n-v2 | \ + tl-wr1043nd | \ + tl-wr2543n) + [ "$magic" != "0100" ] && { + echo "Invalid image type." + return 1 + } + + local hwid + local imageid + + hwid=$(tplink_get_hwid) + imageid=$(tplink_get_image_hwid "$1") + + [ "$hwid" != "$imageid" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hwid image:$imageid." + return 1 + } + + return 0 + ;; + wndr3700) + local hw_magic + + hw_magic="$(ar71xx_get_mtd_part_magic firmware)" + [ "$magic_long" != "$hw_magic" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hw_magic image:$magic_long." + return 1 + } + return 0 + ;; + wrt160nl) + [ "$magic" != "4e4c" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + routerstation | \ + routerstation-pro | \ + ls-sr71 | \ + pb42 | \ + pb44 | \ + all0305 | \ + eap7660d | \ + ja76pf | \ + ja76pf2) + [ "$magic" != "4349" ] && { + echo "Invalid image. Use *-sysupgrade.bin files on this board" + return 1 + } + + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + return 0 + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(ar71xx_board_name) + + case "$board" in + routerstation | \ + routerstation-pro | \ + ls-sr71 | \ + all0305 | \ + eap7660d | \ + pb42 | \ + pb44 | \ + ja76pf | \ + ja76pf2) + platform_do_upgrade_combined "$ARGV" + ;; + all0258n ) + platform_do_upgrade_allnet "0x9f050000" "$ARGV" + ;; + all0315n ) + platform_do_upgrade_allnet "0x9f080000" "$ARGV" + ;; + dir-825-b1 |\ + tew-673gru) + platform_do_upgrade_dir825b "$ARGV" + ;; + om2p | \ + om2p-lc) + platform_do_upgrade_om2p "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/ar71xx/base-files/sbin/wget2nand b/target/linux/ar71xx/base-files/sbin/wget2nand new file mode 100755 index 000000000..9cd6e7c40 --- /dev/null +++ b/target/linux/ar71xx/base-files/sbin/wget2nand @@ -0,0 +1,85 @@ +#!/bin/sh +# wget2nand +# This script can be used to download a TGZ file from your build system which +# contains the files to be installed on the NAND flash on your RB1xx card. +# The one parameter is the URL of the TGZ file to be downloaded. +# Licence GPL V2 +# Author david.goodenough@linkchoose.co.uk +# Based on cf2nand from RB532 support +. /etc/functions.sh + +wget2nand_dir=/tmp/wget2nand +mnt_kernel=$wget2nand_dir/mnt_kernel +mnt_rootfs=$wget2nand_dir/mnt_rootfs +src_rootfs=$wget2nand_dir/rootfs.tgz +src_kernel=$wget2nand_dir/kernel + +[ -d "$wget2nand_dir" ] && { + echo "$wget2nand_dir already exists" + exit 1 +} + +# need to find the wget server from the command line +url=$1 +[ -z "$url" ] && { + echo "No URL specified for image TGZ" + echo "Usage : $0 URL" + exit 1 +} + +url_kernel=$url/openwrt-ar71xx-nand-vmlinux.elf +url_rootfs=$url/openwrt-ar71xx-nand-rootfs.tar.gz + +mtd_kernel="$(find_mtd_part 'kernel')" +mtd_rootfs="$(find_mtd_part 'rootfs')" +[ -z "$mtd_kernel" -o -z "$mtd_rootfs" ] && { + echo "Cannot find NAND Flash partitions" + exit 1 +} + +mkdir "$wget2nand_dir" +wget $url_kernel -O "$src_kernel" || { + echo "Unable to download $url_kernel" + exit 1 +} + +wget $url_rootfs -O "$src_rootfs" || { + echo "Unable to download $url_rootfs" + exit 1 +} + +echo "Erasing filesystem..." +mtd erase kernel 2>/dev/null >/dev/null +mtd erase rootfs 2>/dev/null >/dev/null + +echo "Mounting $mtd_rootfs as new root and $mtd_kernel as kernel partition" + +mkdir "$mnt_kernel" +mkdir "$mnt_rootfs" +mount -t yaffs2 "$mtd_kernel" "$mnt_kernel" +mount -t yaffs2 "$mtd_rootfs" "$mnt_rootfs" + +echo "Copying kernel..." +cp $src_kernel $mnt_kernel/kernel || { + echo "Error occured while copying the kernel" + exit 1 +} +chmod +x $mnt_kernel/kernel + +echo "Preparing filesystem..." +( cd "$mnt_rootfs"; tar xvz -f "$src_rootfs" ) + +# make sure everything is written before we unmount the partitions +echo "chmod ugo+x /" > $mnt_rootfs/etc/uci-defaults/set_root_permission +sync +ls $mnt_kernel >/dev/null +ls $mnt_rootfs >/dev/null + +echo "Cleaning up..." +# unmount the partitions and remove the directories into which they were mounted +umount $mnt_kernel +umount $mnt_rootfs +rm -rf $wget2nand_dir + +# all done +echo "Image written, you can now reboot. Remember to change the boot source to Boot from Nand" diff --git a/target/linux/ar71xx/config-3.3 b/target/linux/ar71xx/config-3.3 new file mode 100644 index 000000000..ec12afdfd --- /dev/null +++ b/target/linux/ar71xx/config-3.3 @@ -0,0 +1,233 @@ +CONFIG_AG71XX=y +CONFIG_AG71XX_AR8216_SUPPORT=y +# CONFIG_AG71XX_DEBUG is not set +# CONFIG_AG71XX_DEBUG_FS is not set +CONFIG_AR8216_PHY=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ATH79=y +CONFIG_ATH79_DEV_AP9X_PCI=y +CONFIG_ATH79_DEV_DSA=y +CONFIG_ATH79_DEV_ETH=y +CONFIG_ATH79_DEV_GPIO_BUTTONS=y +CONFIG_ATH79_DEV_LEDS_GPIO=y +CONFIG_ATH79_DEV_M25P80=y +CONFIG_ATH79_DEV_NFC=y +CONFIG_ATH79_DEV_SPI=y +CONFIG_ATH79_DEV_USB=y +CONFIG_ATH79_DEV_WMAC=y +CONFIG_ATH79_MACH_ALFA_AP96=y +CONFIG_ATH79_MACH_ALFA_NX=y +CONFIG_ATH79_MACH_ALL0258N=y +CONFIG_ATH79_MACH_ALL0315N=y +CONFIG_ATH79_MACH_AP113=y +CONFIG_ATH79_MACH_AP121=y +CONFIG_ATH79_MACH_AP136=y +CONFIG_ATH79_MACH_AP81=y +CONFIG_ATH79_MACH_AP83=y +CONFIG_ATH79_MACH_AP96=y +CONFIG_ATH79_MACH_AW_NR580=y +CONFIG_ATH79_MACH_DB120=y +CONFIG_ATH79_MACH_DIR_600_A1=y +CONFIG_ATH79_MACH_DIR_615_C1=y +CONFIG_ATH79_MACH_DIR_825_B1=y +CONFIG_ATH79_MACH_EAP7660D=y +CONFIG_ATH79_MACH_EW_DORIN=y +CONFIG_ATH79_MACH_HORNET_UB=y +CONFIG_ATH79_MACH_JA76PF=y +CONFIG_ATH79_MACH_JWAP003=y +CONFIG_ATH79_MACH_MZK_W04NU=y +CONFIG_ATH79_MACH_MZK_W300NH=y +CONFIG_ATH79_MACH_NBG460N=y +CONFIG_ATH79_MACH_OM2P=y +CONFIG_ATH79_MACH_PB42=y +CONFIG_ATH79_MACH_PB44=y +CONFIG_ATH79_MACH_PB92=y +CONFIG_ATH79_MACH_RB2011=y +CONFIG_ATH79_MACH_RB4XX=y +CONFIG_ATH79_MACH_RB750=y +CONFIG_ATH79_MACH_RW2458N=y +CONFIG_ATH79_MACH_TEW_632BRP=y +CONFIG_ATH79_MACH_TEW_673GRU=y +CONFIG_ATH79_MACH_TEW_712BR=y +CONFIG_ATH79_MACH_TL_MR11U=y +CONFIG_ATH79_MACH_TL_MR3020=y +CONFIG_ATH79_MACH_TL_MR3X20=y +CONFIG_ATH79_MACH_TL_WA901ND=y +CONFIG_ATH79_MACH_TL_WA901ND_V2=y +CONFIG_ATH79_MACH_TL_WDR4300=y +CONFIG_ATH79_MACH_TL_WR1041N_V2=y +CONFIG_ATH79_MACH_TL_WR1043ND=y +CONFIG_ATH79_MACH_TL_WR2543N=y +CONFIG_ATH79_MACH_TL_WR703N=y +CONFIG_ATH79_MACH_TL_WR741ND=y +CONFIG_ATH79_MACH_TL_WR741ND_V4=y +CONFIG_ATH79_MACH_TL_WR841N_V1=y +CONFIG_ATH79_MACH_TL_WR841N_V8=y +CONFIG_ATH79_MACH_TL_WR941ND=y +CONFIG_ATH79_MACH_UBNT=y +CONFIG_ATH79_MACH_UBNT_XM=y +CONFIG_ATH79_MACH_WHR_HP_G300N=y +CONFIG_ATH79_MACH_WLAE_AG300N=y +CONFIG_ATH79_MACH_WNDR3700=y +CONFIG_ATH79_MACH_WNR2000=y +CONFIG_ATH79_MACH_WP543=y +CONFIG_ATH79_MACH_WPE72=y +CONFIG_ATH79_MACH_WRT160NL=y +CONFIG_ATH79_MACH_WRT400N=y +CONFIG_ATH79_MACH_WZR_HP_AG300H=y +CONFIG_ATH79_MACH_WZR_HP_G300NH=y +CONFIG_ATH79_MACH_WZR_HP_G300NH2=y +CONFIG_ATH79_MACH_WZR_HP_G450H=y +CONFIG_ATH79_MACH_ZCN_1523H=y +CONFIG_ATH79_NVRAM=y +CONFIG_ATH79_PCI_ATH9K_FIXUP=y +CONFIG_ATH79_ROUTERBOOT=y +# CONFIG_ATH79_WDT is not set +CONFIG_BCMA_POSSIBLE=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_NXP_74HC153=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_WORK=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_GPIO=y +CONFIG_IMAGE_CMDLINE_HACK=y +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_SOURCE="../../root" +CONFIG_IP17XX_PHY=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_FORCED_THREADING=y +# CONFIG_LEDS_RB750 is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_WNDR3700_USB is not set +# CONFIG_M25PXX_USE_FAST_READ is not set +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MICREL_PHY=y +CONFIG_MIPS=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MACHINE=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_MYLOADER_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_TPLINK_PARTS=y +CONFIG_MTD_WRT160NL_PARTS=y +CONFIG_MYLOADER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6060=y +CONFIG_NET_DSA_MV88E6063=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_AR724X=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_RLE_DECOMPRESS=y +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8366_SMI=y +CONFIG_RTL8367_PHY=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_AR933X=y +CONFIG_SERIAL_AR933X_CONSOLE=y +CONFIG_SERIAL_AR933X_NR_UARTS=2 +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SOC_AR71XX=y +CONFIG_SOC_AR724X=y +CONFIG_SOC_AR913X=y +CONFIG_SOC_AR933X=y +CONFIG_SOC_AR934X=y +CONFIG_SOC_QCA955X=y +CONFIG_SPI=y +CONFIG_SPI_AP83=y +CONFIG_SPI_ATH79=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_RB4XX is not set +# CONFIG_SPI_RB4XX_CPLD is not set +# CONFIG_SPI_VSC7385 is not set +CONFIG_SWCONFIG=y +CONFIG_SWCONFIG_LEDS=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_SUPPORT=y +CONFIG_XZ_DEC=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c new file mode 100644 index 000000000..c08e43808 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c @@ -0,0 +1,153 @@ +/* + * Atheros AP9X reference board PCI initialization + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/pci.h> +#include <linux/ath9k_platform.h> +#include <linux/delay.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-ap9x-pci.h" +#include "pci-ath9k-fixup.h" +#include "pci.h" + +static struct ath9k_platform_data ap9x_wmac0_data = { + .led_pin = -1, +}; +static struct ath9k_platform_data ap9x_wmac1_data = { + .led_pin = -1, +}; +static char ap9x_wmac0_mac[6]; +static char ap9x_wmac1_mac[6]; + +__init void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.led_pin = pin; + break; + case 1: + ap9x_wmac1_data.led_pin = pin; + break; + } +} + +__init struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac) +{ + switch (wmac) { + case 0: + return &ap9x_wmac0_data; + + case 1: + return &ap9x_wmac1_data; + } + + return NULL; +} + +__init void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.gpio_mask = mask; + ap9x_wmac0_data.gpio_val = val; + break; + case 1: + ap9x_wmac1_data.gpio_mask = mask; + ap9x_wmac1_data.gpio_val = val; + break; + } +} + +__init void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds, + int num_leds) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.leds = leds; + ap9x_wmac0_data.num_leds = num_leds; + break; + case 1: + ap9x_wmac1_data.leds = leds; + ap9x_wmac1_data.num_leds = num_leds; + break; + } +} + +static int ap91_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 0: + dev->dev.platform_data = &ap9x_wmac0_data; + break; + } + + return 0; +} + +__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr) +{ + if (cal_data) + memcpy(ap9x_wmac0_data.eeprom_data, cal_data, + sizeof(ap9x_wmac0_data.eeprom_data)); + + if (mac_addr) { + memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac)); + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac; + } + + ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init); + ath79_register_pci(); + + pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data); +} + +static int ap94_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 17: + dev->dev.platform_data = &ap9x_wmac0_data; + break; + + case 18: + dev->dev.platform_data = &ap9x_wmac1_data; + break; + } + + return 0; +} + +__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ + if (cal_data0) + memcpy(ap9x_wmac0_data.eeprom_data, cal_data0, + sizeof(ap9x_wmac0_data.eeprom_data)); + + if (cal_data1) + memcpy(ap9x_wmac1_data.eeprom_data, cal_data1, + sizeof(ap9x_wmac1_data.eeprom_data)); + + if (mac_addr0) { + memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac)); + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac; + } + + if (mac_addr1) { + memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac)); + ap9x_wmac1_data.macaddr = ap9x_wmac1_mac; + } + + ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init); + ath79_register_pci(); + + pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data); + pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h new file mode 100644 index 000000000..d56f7136b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h @@ -0,0 +1,46 @@ +/* + * Atheros AP9X reference board PCI initialization + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_AP9X_PCI_H +#define _ATH79_DEV_AP9X_PCI_H + +struct gpio_led; +struct ath9k_platform_data; + +#if defined(CONFIG_ATH79_DEV_AP9X_PCI) +void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin); +void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val); +void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds, + int num_leds); +struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac); + +void ap91_pci_init(u8 *cal_data, u8 *mac_addr); +void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1); + +#else +static inline void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) {} +static inline void ap9x_pci_setup_wmac_gpio(unsigned wmac, + u32 mask, u32 val) {} +static inline void ap9x_pci_setup_wmac_leds(unsigned wmac, + struct gpio_led *leds, + int num_leds) {} +static inline struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac) +{ + return NULL; +} + +static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) {} +static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) {} +#endif + +#endif /* _ATH79_DEV_AP9X_PCI_H */ + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c new file mode 100644 index 000000000..176414738 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c @@ -0,0 +1,36 @@ +/* + * Atheros AR71xx DSA switch device support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-dsa.h" + +static struct platform_device ar71xx_dsa_switch_device = { + .name = "dsa", + .id = 0, +}; + +void __init ath79_register_dsa(struct device *netdev, + struct device *miidev, + struct dsa_platform_data *d) +{ + int i; + + d->netdev = netdev; + for (i = 0; i < d->nr_chips; i++) + d->chip[i].mii_bus = miidev; + + ar71xx_dsa_switch_device.dev.platform_data = d; + platform_device_register(&ar71xx_dsa_switch_device); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h new file mode 100644 index 000000000..3730202e8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71xx DSA switch device support + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_DSA_H +#define _ATH79_DEV_DSA_H + +#include <net/dsa.h> + +void ath79_register_dsa(struct device *netdev, + struct device *miidev, + struct dsa_platform_data *d); + +#endif /* _ATH79_DEV_DSA_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c new file mode 100644 index 000000000..4487958bc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -0,0 +1,1029 @@ +/* + * Atheros AR71xx SoC platform devices + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/etherdevice.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/irq.h> + +#include "common.h" +#include "dev-eth.h" + +unsigned char ath79_mac_base[ETH_ALEN] __initdata; + +static struct resource ath79_mdio0_resources[] = { + { + .name = "mdio_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE0_BASE, + .end = AR71XX_GE0_BASE + 0x200 - 1, + } +}; + +static struct ag71xx_mdio_platform_data ath79_mdio0_data; + +struct platform_device ath79_mdio0_device = { + .name = "ag71xx-mdio", + .id = 0, + .resource = ath79_mdio0_resources, + .num_resources = ARRAY_SIZE(ath79_mdio0_resources), + .dev = { + .platform_data = &ath79_mdio0_data, + }, +}; + +static struct resource ath79_mdio1_resources[] = { + { + .name = "mdio_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE1_BASE, + .end = AR71XX_GE1_BASE + 0x200 - 1, + } +}; + +static struct ag71xx_mdio_platform_data ath79_mdio1_data; + +struct platform_device ath79_mdio1_device = { + .name = "ag71xx-mdio", + .id = 1, + .resource = ath79_mdio1_resources, + .num_resources = ARRAY_SIZE(ath79_mdio1_resources), + .dev = { + .platform_data = &ath79_mdio1_data, + }, +}; + +static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) +{ + void __iomem *base; + u32 t; + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + t = __raw_readl(base + cfg_reg); + t &= ~(3 << shift); + t |= (2 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + __raw_writel(pll_val, base + pll_reg); + + t |= (3 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + t &= ~(3 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", + (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); + + iounmap(base); +} + +static void __init ath79_mii_ctrl_set_if(unsigned int reg, + unsigned int mii_if) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); + + t = __raw_readl(base + reg); + t &= ~(AR71XX_MII_CTRL_IF_MASK); + t |= (mii_if & AR71XX_MII_CTRL_IF_MASK); + __raw_writel(t, base + reg); + + iounmap(base); +} + +static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed) +{ + void __iomem *base; + unsigned int mii_speed; + u32 t; + + switch (speed) { + case SPEED_10: + mii_speed = AR71XX_MII_CTRL_SPEED_10; + break; + case SPEED_100: + mii_speed = AR71XX_MII_CTRL_SPEED_100; + break; + case SPEED_1000: + mii_speed = AR71XX_MII_CTRL_SPEED_1000; + break; + default: + BUG(); + } + + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); + + t = __raw_readl(base + reg); + t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT); + t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT; + __raw_writel(t, base + reg); + + iounmap(base); +} + +static unsigned long ar934x_get_mdio_ref_clock(void) +{ + void __iomem *base; + unsigned long ret; + u32 t; + + base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + ret = 0; + t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) { + ret = 100 * 1000 * 1000; + } else { + struct clk *clk; + + clk = clk_get(NULL, "ref"); + if (!IS_ERR(clk)) + ret = clk_get_rate(clk); + } + + iounmap(base); + + return ret; +} + +void __init ath79_register_mdio(unsigned int id, u32 phy_mask) +{ + struct platform_device *mdio_dev; + struct ag71xx_mdio_platform_data *mdio_data; + unsigned int max_id; + + if (ath79_soc == ATH79_SOC_AR9341 || + ath79_soc == ATH79_SOC_AR9342 || + ath79_soc == ATH79_SOC_AR9344 || + ath79_soc == ATH79_SOC_QCA9558) + max_id = 1; + else + max_id = 0; + + if (id > max_id) { + printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id); + return; + } + + switch (ath79_soc) { + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + mdio_dev = &ath79_mdio1_device; + mdio_data = &ath79_mdio1_data; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: + if (id == 0) { + mdio_dev = &ath79_mdio0_device; + mdio_data = &ath79_mdio0_data; + } else { + mdio_dev = &ath79_mdio1_device; + mdio_data = &ath79_mdio1_data; + } + break; + + case ATH79_SOC_AR7242: + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, + AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000, + AR71XX_ETH0_PLL_SHIFT); + /* fall through */ + default: + mdio_dev = &ath79_mdio0_device; + mdio_data = &ath79_mdio0_data; + break; + } + + mdio_data->phy_mask = phy_mask; + + switch (ath79_soc) { + case ATH79_SOC_AR7240: + mdio_data->is_ar7240 = 1; + /* fall through */ + case ATH79_SOC_AR7241: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_AR9330: + mdio_data->is_ar9330 = 1; + /* fall through */ + case ATH79_SOC_AR9331: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + if (id == 1) { + mdio_data->builtin_switch = 1; + mdio_data->ref_clock = ar934x_get_mdio_ref_clock(); + mdio_data->mdio_clock = 6250000; + } + mdio_data->is_ar934x = 1; + break; + case ATH79_SOC_QCA9558: + if (id == 1) + mdio_data->builtin_switch = 1; + mdio_data->is_ar934x = 1; + break; + + default: + break; + } + + platform_device_register(mdio_dev); +} + +struct ath79_eth_pll_data ath79_eth0_pll_data; +struct ath79_eth_pll_data ath79_eth1_pll_data; + +static u32 ath79_get_eth_pll(unsigned int mac, int speed) +{ + struct ath79_eth_pll_data *pll_data; + u32 pll_val; + + switch (mac) { + case 0: + pll_data = &ath79_eth0_pll_data; + break; + case 1: + pll_data = &ath79_eth1_pll_data; + break; + default: + BUG(); + } + + switch (speed) { + case SPEED_10: + pll_val = pll_data->pll_10; + break; + case SPEED_100: + pll_val = pll_data->pll_100; + break; + case SPEED_1000: + pll_val = pll_data->pll_1000; + break; + default: + BUG(); + } + + return pll_val; +} + +static void ath79_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, + val, AR71XX_ETH0_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed); +} + +static void ath79_set_speed_ge1(int speed) +{ + u32 val = ath79_get_eth_pll(1, speed); + + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, + val, AR71XX_ETH1_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed); +} + +static void ar7242_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + void __iomem *base; + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK); + iounmap(base); +} + +static void ar91xx_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK, + val, AR913X_ETH0_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed); +} + +static void ar91xx_set_speed_ge1(int speed) +{ + u32 val = ath79_get_eth_pll(1, speed); + + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK, + val, AR913X_ETH1_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed); +} + +static void ar934x_set_speed_ge0(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG); + iounmap(base); +} + +static void ath79_set_speed_dummy(int speed) +{ +} + +static void ath79_ddr_no_flush(void) +{ +} + +static void ath79_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0); +} + +static void ath79_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1); +} + +static void ar724x_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0); +} + +static void ar724x_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1); +} + +static void ar91xx_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0); +} + +static void ar91xx_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1); +} + +static void ar933x_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0); +} + +static void ar933x_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1); +} + +static struct resource ath79_eth0_resources[] = { + { + .name = "mac_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE0_BASE, + .end = AR71XX_GE0_BASE + 0x200 - 1, + }, { + .name = "mac_irq", + .flags = IORESOURCE_IRQ, + .start = ATH79_CPU_IRQ_GE0, + .end = ATH79_CPU_IRQ_GE0, + }, +}; + +struct ag71xx_platform_data ath79_eth0_data = { + .reset_bit = AR71XX_RESET_GE0_MAC, +}; + +struct platform_device ath79_eth0_device = { + .name = "ag71xx", + .id = 0, + .resource = ath79_eth0_resources, + .num_resources = ARRAY_SIZE(ath79_eth0_resources), + .dev = { + .platform_data = &ath79_eth0_data, + }, +}; + +static struct resource ath79_eth1_resources[] = { + { + .name = "mac_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE1_BASE, + .end = AR71XX_GE1_BASE + 0x200 - 1, + }, { + .name = "mac_irq", + .flags = IORESOURCE_IRQ, + .start = ATH79_CPU_IRQ_GE1, + .end = ATH79_CPU_IRQ_GE1, + }, +}; + +struct ag71xx_platform_data ath79_eth1_data = { + .reset_bit = AR71XX_RESET_GE1_MAC, +}; + +struct platform_device ath79_eth1_device = { + .name = "ag71xx", + .id = 1, + .resource = ath79_eth1_resources, + .num_resources = ARRAY_SIZE(ath79_eth1_resources), + .dev = { + .platform_data = &ath79_eth1_data, + }, +}; + +struct ag71xx_switch_platform_data ath79_switch_data; + +#define AR71XX_PLL_VAL_1000 0x00110000 +#define AR71XX_PLL_VAL_100 0x00001099 +#define AR71XX_PLL_VAL_10 0x00991099 + +#define AR724X_PLL_VAL_1000 0x00110000 +#define AR724X_PLL_VAL_100 0x00001099 +#define AR724X_PLL_VAL_10 0x00991099 + +#define AR7242_PLL_VAL_1000 0x16000000 +#define AR7242_PLL_VAL_100 0x00000101 +#define AR7242_PLL_VAL_10 0x00001616 + +#define AR913X_PLL_VAL_1000 0x1a000000 +#define AR913X_PLL_VAL_100 0x13000a44 +#define AR913X_PLL_VAL_10 0x00441099 + +#define AR933X_PLL_VAL_1000 0x00110000 +#define AR933X_PLL_VAL_100 0x00001099 +#define AR933X_PLL_VAL_10 0x00991099 + +#define AR934X_PLL_VAL_1000 0x16000000 +#define AR934X_PLL_VAL_100 0x00000101 +#define AR934X_PLL_VAL_10 0x00001616 + +static void __init ath79_init_eth_pll_data(unsigned int id) +{ + struct ath79_eth_pll_data *pll_data; + u32 pll_10, pll_100, pll_1000; + + switch (id) { + case 0: + pll_data = &ath79_eth0_pll_data; + break; + case 1: + pll_data = &ath79_eth1_pll_data; + break; + default: + BUG(); + } + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + pll_10 = AR71XX_PLL_VAL_10; + pll_100 = AR71XX_PLL_VAL_100; + pll_1000 = AR71XX_PLL_VAL_1000; + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + pll_10 = AR724X_PLL_VAL_10; + pll_100 = AR724X_PLL_VAL_100; + pll_1000 = AR724X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR7242: + pll_10 = AR7242_PLL_VAL_10; + pll_100 = AR7242_PLL_VAL_100; + pll_1000 = AR7242_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + pll_10 = AR913X_PLL_VAL_10; + pll_100 = AR913X_PLL_VAL_100; + pll_1000 = AR913X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + pll_10 = AR933X_PLL_VAL_10; + pll_100 = AR933X_PLL_VAL_100; + pll_1000 = AR933X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: + pll_10 = AR934X_PLL_VAL_10; + pll_100 = AR934X_PLL_VAL_100; + pll_1000 = AR934X_PLL_VAL_1000; + break; + + default: + BUG(); + } + + if (!pll_data->pll_10) + pll_data->pll_10 = pll_10; + + if (!pll_data->pll_100) + pll_data->pll_100 = pll_100; + + if (!pll_data->pll_1000) + pll_data->pll_1000 = pll_1000; +} + +static int __init ath79_setup_phy_if_mode(unsigned int id, + struct ag71xx_platform_data *pdata) +{ + unsigned int mii_if; + + switch (id) { + case 0: + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + mii_if = AR71XX_MII0_CTRL_IF_MII; + break; + case PHY_INTERFACE_MODE_GMII: + mii_if = AR71XX_MII0_CTRL_IF_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + mii_if = AR71XX_MII0_CTRL_IF_RGMII; + break; + case PHY_INTERFACE_MODE_RMII: + mii_if = AR71XX_MII0_CTRL_IF_RMII; + break; + default: + return -EINVAL; + } + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if); + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; + break; + + case ATH79_SOC_AR7242: + /* FIXME */ + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RMII: + break; + default: + return -EINVAL; + } + break; + + default: + BUG(); + } + break; + case 1: + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_RMII: + mii_if = AR71XX_MII1_CTRL_IF_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + mii_if = AR71XX_MII1_CTRL_IF_RGMII; + break; + default: + return -EINVAL; + } + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if); + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; + break; + + case ATH79_SOC_AR7242: + /* FIXME */ + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + break; + default: + return -EINVAL; + } + break; + + default: + BUG(); + } + break; + } + + return 0; +} + +void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE); + + t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG); + t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP); + if (mac) + t |= AR933X_ETH_CFG_SW_PHY_SWAP; + if (mdio) + t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP; + __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static int ath79_eth_instance __initdata; +void __init ath79_register_eth(unsigned int id) +{ + struct platform_device *pdev; + struct ag71xx_platform_data *pdata; + int err; + + if (id > 1) { + printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); + return; + } + + ath79_init_eth_pll_data(id); + + if (id == 0) + pdev = &ath79_eth0_device; + else + pdev = &ath79_eth1_device; + + pdata = pdev->dev.platform_data; + + err = ath79_setup_phy_if_mode(id, pdata); + if (err) { + printk(KERN_ERR + "ar71xx: invalid PHY interface mode for GE%u\n", id); + return; + } + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + if (id == 0) { + pdata->ddr_flush = ath79_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->ddr_flush = ath79_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_ge1; + } + break; + + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + if (id == 0) { + pdata->ddr_flush = ath79_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->ddr_flush = ath79_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_ge1; + } + pdata->has_gbit = 1; + break; + + case ATH79_SOC_AR7242: + if (id == 0) { + pdata->reset_bit |= AR724X_RESET_GE0_MDIO | + AR71XX_RESET_GE0_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge0; + pdata->set_speed = ar7242_set_speed_ge0; + } else { + pdata->reset_bit |= AR724X_RESET_GE1_MDIO | + AR71XX_RESET_GE1_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + } + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR7241: + if (id == 0) + pdata->reset_bit |= AR724X_RESET_GE0_MDIO; + else + pdata->reset_bit |= AR724X_RESET_GE1_MDIO; + /* fall through */ + case ATH79_SOC_AR7240: + if (id == 0) { + pdata->reset_bit |= AR71XX_RESET_GE0_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit |= AR71XX_RESET_GE1_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + if (ath79_soc == ATH79_SOC_AR7240) + pdata->is_ar7240 = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR9130: + if (id == 0) { + pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->set_speed = ar91xx_set_speed_ge0; + } else { + pdata->ddr_flush = ar91xx_ddr_flush_ge1; + pdata->set_speed = ar91xx_set_speed_ge1; + } + pdata->is_ar91xx = 1; + break; + + case ATH79_SOC_AR9132: + if (id == 0) { + pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->set_speed = ar91xx_set_speed_ge0; + } else { + pdata->ddr_flush = ar91xx_ddr_flush_ge1; + pdata->set_speed = ar91xx_set_speed_ge1; + } + pdata->is_ar91xx = 1; + pdata->has_gbit = 1; + break; + + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->ddr_flush = ar933x_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->ddr_flush = ar933x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: + if (id == 0) { + pdata->reset_bit = AR934X_RESET_GE0_MAC | + AR934X_RESET_GE0_MDIO; + pdata->set_speed = ar934x_set_speed_ge0; + } else { + pdata->reset_bit = AR934X_RESET_GE1_MAC | + AR934X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->switch_data = &ath79_switch_data; + + /* reset the built-in switch */ + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH); + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + default: + BUG(); + } + + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + if (!pdata->has_gbit) { + printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", + id); + return; + } + /* fallthrough */ + default: + break; + } + + if (!is_valid_ether_addr(pdata->mac_addr)) { + random_ether_addr(pdata->mac_addr); + printk(KERN_DEBUG + "ar71xx: using random MAC address for eth%d\n", + ath79_eth_instance); + } + + if (pdata->mii_bus_dev == NULL) { + switch (ath79_soc) { + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9558: + if (id == 0) + pdata->mii_bus_dev = &ath79_mdio0_device.dev; + else + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + + default: + pdata->mii_bus_dev = &ath79_mdio0_device.dev; + break; + } + } + + /* Reset the device */ + ath79_device_reset_set(pdata->reset_bit); + mdelay(100); + + ath79_device_reset_clear(pdata->reset_bit); + mdelay(100); + + platform_device_register(pdev); + ath79_eth_instance++; +} + +void __init ath79_set_mac_base(unsigned char *mac) +{ + memcpy(ath79_mac_base, mac, ETH_ALEN); +} + +void __init ath79_parse_mac_addr(char *mac_str) +{ + u8 tmp[ETH_ALEN]; + int t; + + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); + + if (t != ETH_ALEN) + t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", + &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); + + if (t == ETH_ALEN) + ath79_set_mac_base(tmp); + else + printk(KERN_DEBUG "ar71xx: failed to parse mac address " + "\"%s\"\n", mac_str); +} + +static int __init ath79_ethaddr_setup(char *str) +{ + ath79_parse_mac_addr(str); + return 1; +} +__setup("ethaddr=", ath79_ethaddr_setup); + +static int __init ath79_kmac_setup(char *str) +{ + ath79_parse_mac_addr(str); + return 1; +} +__setup("kmac=", ath79_kmac_setup); + +void __init ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset) +{ + int t; + + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { + memset(dst, '\0', ETH_ALEN); + return; + } + + t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]); + t += offset; + + dst[0] = src[0]; + dst[1] = src[1]; + dst[2] = src[2]; + dst[3] = (t >> 16) & 0xff; + dst[4] = (t >> 8) & 0xff; + dst[5] = t & 0xff; +} + +void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src) +{ + int i; + + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { + memset(dst, '\0', ETH_ALEN); + return; + } + + for (i = 0; i < ETH_ALEN; i++) + dst[i] = src[i]; + dst[0] |= 0x02; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h new file mode 100644 index 000000000..d4f27d9cf --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h @@ -0,0 +1,48 @@ +/* + * Atheros AR71xx SoC device definitions + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_ETH_H +#define _ATH79_DEV_ETH_H + +#include <asm/mach-ath79/ag71xx_platform.h> + +struct platform_device; + +extern unsigned char ath79_mac_base[] __initdata; +void ath79_parse_mac_addr(char *mac_str); +void ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset); +void ath79_init_local_mac(unsigned char *dst, const unsigned char *src); + +struct ath79_eth_pll_data { + u32 pll_10; + u32 pll_100; + u32 pll_1000; +}; + +extern struct ath79_eth_pll_data ath79_eth0_pll_data; +extern struct ath79_eth_pll_data ath79_eth1_pll_data; + +extern struct ag71xx_platform_data ath79_eth0_data; +extern struct ag71xx_platform_data ath79_eth1_data; +extern struct platform_device ath79_eth0_device; +extern struct platform_device ath79_eth1_device; +void ath79_register_eth(unsigned int id); + +extern struct ag71xx_switch_platform_data ath79_switch_data; + +extern struct platform_device ath79_mdio0_device; +extern struct platform_device ath79_mdio1_device; +void ath79_register_mdio(unsigned int id, u32 phy_mask); + +void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio); + +#endif /* _ATH79_DEV_ETH_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c new file mode 100644 index 000000000..66115b1c4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/concat.h> + +#include "dev-spi.h" +#include "dev-m25p80.h" + +static struct ath79_spi_controller_data ath79_spi0_cdata = +{ + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, +}; + +static struct ath79_spi_controller_data ath79_spi1_cdata = +{ + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 1, +}; + +static struct spi_board_info ath79_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ath79_spi0_cdata, + }, + { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ath79_spi1_cdata, + } +}; + +static struct ath79_spi_platform_data ath79_spi_data; + +void __init ath79_register_m25p80(struct flash_platform_data *pdata) +{ + ath79_spi_data.bus_num = 0; + ath79_spi_data.num_chipselect = 1; + ath79_spi0_cdata.is_flash = true; + ath79_spi_info[0].platform_data = pdata; + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1); +} + +static struct flash_platform_data *multi_pdata; + +static struct mtd_info *concat_devs[2] = { NULL, NULL }; +static struct work_struct mtd_concat_work; + +static void mtd_concat_add_work(struct work_struct *work) +{ + struct mtd_info *mtd; + + mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash"); + + mtd_device_register(mtd, multi_pdata->parts, multi_pdata->nr_parts); +} + +static void mtd_concat_add(struct mtd_info *mtd) +{ + static bool registered = false; + + if (registered) + return; + + if (!strcmp(mtd->name, "spi0.0")) + concat_devs[0] = mtd; + else if (!strcmp(mtd->name, "spi0.1")) + concat_devs[1] = mtd; + else + return; + + if (!concat_devs[0] || !concat_devs[1]) + return; + + registered = true; + INIT_WORK(&mtd_concat_work, mtd_concat_add_work); + schedule_work(&mtd_concat_work); +} + +static void mtd_concat_remove(struct mtd_info *mtd) +{ +} + +static void add_mtd_concat_notifier(void) +{ + static struct mtd_notifier not = { + .add = mtd_concat_add, + .remove = mtd_concat_remove, + }; + + register_mtd_user(¬); +} + + +void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata) +{ + multi_pdata = pdata; + add_mtd_concat_notifier(); + ath79_spi_data.bus_num = 0; + ath79_spi_data.num_chipselect = 2; + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 2); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h new file mode 100644 index 000000000..637b41a7d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_M25P80_H +#define _ATH79_DEV_M25P80_H + +#include <linux/spi/flash.h> + +void ath79_register_m25p80(struct flash_platform_data *pdata) __init; +void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init; + +#endif /* _ATH79_DEV_M25P80_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c new file mode 100644 index 000000000..f330395fe --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c @@ -0,0 +1,95 @@ +/* + * Atheros AR934X SoCs built-in NAND flash controller support + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/dma-mapping.h> +#include <linux/etherdevice.h> +#include <linux/platform_device.h> +#include <linux/platform/ar934x_nfc.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "dev-nfc.h" + +static struct resource ath79_nfc_resources[2]; +static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32); +static struct ar934x_nfc_platform_data ath79_nfc_data; + +static struct platform_device ath79_nfc_device = { + .name = AR934X_NFC_DRIVER_NAME, + .id = -1, + .resource = ath79_nfc_resources, + .num_resources = ARRAY_SIZE(ath79_nfc_resources), + .dev = { + .dma_mask = &ar934x_nfc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_nfc_data, + }, +}; + +static void ar934x_nfc_hw_reset(bool active) +{ + if (active) { + ath79_device_reset_set(AR934X_RESET_NANDF); + udelay(100); + + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG); + udelay(250); + } else { + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG); + udelay(250); + + ath79_device_reset_clear(AR934X_RESET_NANDF); + udelay(100); + } +} + +static void ar934x_nfc_setup(void) +{ + ath79_nfc_resources[0].start = AR934X_NFC_BASE; + ath79_nfc_resources[0].end = AR934X_NFC_BASE + AR934X_NFC_SIZE - 1; + ath79_nfc_resources[0].flags = IORESOURCE_MEM; + + ath79_nfc_resources[1].start = ATH79_MISC_IRQ(21); + ath79_nfc_resources[1].end = ATH79_MISC_IRQ(21); + ath79_nfc_resources[1].flags = IORESOURCE_IRQ; + + ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset; + + platform_device_register(&ath79_nfc_device); +} + +void __init ath79_nfc_set_select_chip(void (*f)(int chip_no)) +{ + ath79_nfc_data.select_chip = f; +} + +void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) +{ + ath79_nfc_data.scan_fixup = f; +} + +void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts) +{ + ath79_nfc_data.parts = parts; + ath79_nfc_data.nr_parts = nr_parts; +} + +void __init ath79_register_nfc(void) +{ + if (soc_is_ar934x()) + ar934x_nfc_setup(); + else + BUG(); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h new file mode 100644 index 000000000..1fc4b807b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h @@ -0,0 +1,27 @@ +/* + * Atheros AR934X SoCs built-in NAND Flash Controller support + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_NFC_H +#define _ATH79_DEV_NFC_H + +#ifdef CONFIG_ATH79_DEV_NFC +void ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts); +void ath79_nfc_set_select_chip(void (*f)(int chip_no)); +void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)); +void ath79_register_nfc(void); +#else +static inline void ath79_nfc_set_parts(struct mtd_partition *parts, + int nr_parts) {} +static inline void ath79_nfc_set_select_chip(void (*f)(int chip_no)) {} +static inline void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) {} +static inline void ath79_register_nfc(void) {} +#endif + +#endif /* _ATH79_DEV_NFC_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c new file mode 100644 index 000000000..15abb081f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c @@ -0,0 +1,154 @@ +/* + * ALFA Network AP96 board support + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/spi/spi.h> +#include <linux/spi/mmc_spi.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define ALFA_AP96_GPIO_PCIE_RESET 2 +#define ALFA_AP96_GPIO_SIM_DETECT 3 +#define ALFA_AP96_GPIO_MICROSD_CD 4 +#define ALFA_AP96_GPIO_PCIE_W_DISABLE 5 + +#define ALFA_AP96_GPIO_BUTTON_RESET 11 + +#define ALFA_AP96_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP96_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALFA_AP96_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static int alfa_ap96_mmc_get_cd(struct device *dev) +{ + return !gpio_get_value(ALFA_AP96_GPIO_MICROSD_CD); +} + +static struct mmc_spi_platform_data alfa_ap96_mmc_data = { + .get_cd = alfa_ap96_mmc_get_cd, + .caps = MMC_CAP_NEEDS_POLL, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct ath79_spi_controller_data ap96_spi0_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, + .is_flash = true, +}; + +static struct ath79_spi_controller_data ap96_spi1_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 1, +}; + +static struct ath79_spi_controller_data ap96_spi2_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 2, +}; + +static struct spi_board_info alfa_ap96_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ap96_spi0_cdata + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "mmc_spi", + .platform_data = &alfa_ap96_mmc_data, + .controller_data = &ap96_spi1_cdata + }, { + .bus_num = 0, + .chip_select = 2, + .max_speed_hz = 6250000, + .modalias = "rtc-pcf2123", + .controller_data = &ap96_spi2_cdata + }, +}; + +static struct ath79_spi_platform_data alfa_ap96_spi_data = { + .bus_num = 0, + .num_chipselect = 3, +}; + +static void __init alfa_ap96_gpio_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD"); + gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD); + gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset"); + gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1); + gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable"); + gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1); +} + +#define ALFA_AP96_WAN_PHYMASK BIT(4) +#define ALFA_AP96_LAN_PHYMASK BIT(5) +#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK) + +static void __init alfa_ap96_init(void) +{ + alfa_ap96_gpio_setup(); + + ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK; + ath79_eth1_pll_data.pll_1000 = 0x110000; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK; + ath79_eth1_pll_data.pll_1000 = 0x110000; + + ath79_register_eth(1); + + ath79_register_pci(); + ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info, + ARRAY_SIZE(alfa_ap96_spi_info)); + + ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL, + ARRAY_SIZE(alfa_ap96_gpio_keys), + alfa_ap96_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96", + alfa_ap96_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c new file mode 100644 index 000000000..a515f4f54 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c @@ -0,0 +1,113 @@ +/* + * ALFA Network N2/N5 board support + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define ALFA_NX_GPIO_LED_2 17 +#define ALFA_NX_GPIO_LED_3 16 +#define ALFA_NX_GPIO_LED_5 12 +#define ALFA_NX_GPIO_LED_6 8 +#define ALFA_NX_GPIO_LED_7 6 +#define ALFA_NX_GPIO_LED_8 7 + +#define ALFA_NX_GPIO_BTN_RESET 11 + +#define ALFA_NX_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL) + +#define ALFA_NX_MAC0_OFFSET 0 +#define ALFA_NX_MAC1_OFFSET 6 +#define ALFA_NX_CALDATA_OFFSET 0x1000 + +static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALFA_NX_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct gpio_led alfa_nx_leds_gpio[] __initdata = { + { + .name = "alfa:green:led_2", + .gpio = ALFA_NX_GPIO_LED_2, + .active_low = 1, + }, { + .name = "alfa:green:led_3", + .gpio = ALFA_NX_GPIO_LED_3, + .active_low = 1, + }, { + .name = "alfa:red:led_5", + .gpio = ALFA_NX_GPIO_LED_5, + .active_low = 1, + }, { + .name = "alfa:amber:led_6", + .gpio = ALFA_NX_GPIO_LED_6, + .active_low = 1, + }, { + .name = "alfa:green:led_7", + .gpio = ALFA_NX_GPIO_LED_7, + .active_low = 1, + }, { + .name = "alfa:green:led_8", + .gpio = ALFA_NX_GPIO_LED_8, + .active_low = 1, + } +}; + +static void __init alfa_nx_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio), + alfa_nx_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(alfa_nx_gpio_keys), + alfa_nx_gpio_keys); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + ALFA_NX_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, + art + ALFA_NX_MAC1_OFFSET, 0); + + /* WAN port */ + ath79_register_eth(0); + /* LAN port */ + ath79_register_eth(1); + + ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5", + alfa_nx_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c new file mode 100644 index 000000000..2495bcba7 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c @@ -0,0 +1,88 @@ +/* + * Allnet ALL0258N support + * + * Copyright (C) 2011 Daniel Golle <dgolle@allnet.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +/* found via /sys/gpio/... try and error */ +#define ALL0258N_GPIO_BTN_RESET 1 +#define ALL0258N_GPIO_LED_RSSIHIGH 13 +#define ALL0258N_GPIO_LED_RSSIMEDIUM 15 +#define ALL0258N_GPIO_LED_RSSILOW 14 + +/* defaults taken from others machs */ +#define ALL0258N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL) + +/* showed up in the original firmware's bootlog */ +#define ALL0258N_SEC_PHYMASK BIT(3) + +static struct gpio_led all0258n_leds_gpio[] __initdata = { + { + .name = "all0258n:green:rssihigh", + .gpio = ALL0258N_GPIO_LED_RSSIHIGH, + .active_low = 1, + }, { + .name = "all0258n:yellow:rssimedium", + .gpio = ALL0258N_GPIO_LED_RSSIMEDIUM, + .active_low = 1, + }, { + .name = "all0258n:red:rssilow", + .gpio = ALL0258N_GPIO_LED_RSSILOW, + .active_low = 1, + } +}; + +static struct gpio_keys_button all0258n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0258N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init all0258n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1f7f1000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio), + all0258n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0258n_gpio_keys), + all0258n_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK; + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N", + all0258n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c new file mode 100644 index 000000000..387ee7f9e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c @@ -0,0 +1,85 @@ +/* + * Allnet ALL0315N support + * + * Copyright (C) 2012 Daniel Golle <dgolle@allnet.de> + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" +#include "pci.h" + +#define ALL0315N_GPIO_BTN_RESET 0 +#define ALL0315N_GPIO_LED_RSSIHIGH 14 +#define ALL0315N_GPIO_LED_RSSIMEDIUM 15 +#define ALL0315N_GPIO_LED_RSSILOW 16 + +#define ALL0315N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALL0315N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0315N_KEYS_POLL_INTERVAL) + +static struct gpio_led all0315n_leds_gpio[] __initdata = { + { + .name = "all0315n:green:rssihigh", + .gpio = ALL0315N_GPIO_LED_RSSIHIGH, + .active_low = 1, + }, { + .name = "all0315n:yellow:rssimedium", + .gpio = ALL0315N_GPIO_LED_RSSIMEDIUM, + .active_low = 1, + }, { + .name = "all0315n:red:rssilow", + .gpio = ALL0315N_GPIO_LED_RSSILOW, + .active_low = 1, + } +}; + +static struct gpio_keys_button all0315n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0315N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0315N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init all0315n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffc0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1ffc1000); + + ath79_register_m25p80(NULL); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0315n_leds_gpio), + all0315n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALL0315N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0315n_gpio_keys), + all0315n_gpio_keys); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap91_pci_init(ee, NULL); +} + +MIPS_MACHINE(ATH79_MACH_ALL0315N, "ALL0315N", "Allnet ALL0315N", + all0315n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c new file mode 100644 index 000000000..9b38faa47 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c @@ -0,0 +1,84 @@ +/* + * Atheros AP113 board support + * + * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "pci.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define AP113_GPIO_LED_USB 0 +#define AP113_GPIO_LED_STATUS 1 +#define AP113_GPIO_LED_ST 11 + +#define AP113_GPIO_BTN_JUMPSTART 12 + +#define AP113_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP113_KEYS_DEBOUNCE_INTERVAL (3 * AP113_KEYS_POLL_INTERVAL) + +static struct gpio_led ap113_leds_gpio[] __initdata = { + { + .name = "ap113:green:usb", + .gpio = AP113_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "ap113:green:status", + .gpio = AP113_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "ap113:green:st", + .gpio = AP113_GPIO_LED_ST, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap113_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP113_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP113_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, +}; + +static void __init ap113_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + ath79_register_gpio_keys_polled(-1, AP113_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap113_gpio_keys), + ap113_gpio_keys); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap113_leds_gpio), + ap113_leds_gpio); + + ath79_register_pci(); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_AP113, "AP113", "Atheros AP113", + ap113_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c new file mode 100644 index 000000000..8519a9d9a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c @@ -0,0 +1,275 @@ +/* + * Atheros AP83 board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/spi/vsc7385.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP83_GPIO_LED_WLAN 6 +#define AP83_GPIO_LED_POWER 14 +#define AP83_GPIO_LED_JUMPSTART 15 +#define AP83_GPIO_BTN_JUMPSTART 12 +#define AP83_GPIO_BTN_RESET 21 + +#define AP83_050_GPIO_VSC7385_CS 1 +#define AP83_050_GPIO_VSC7385_MISO 3 +#define AP83_050_GPIO_VSC7385_MOSI 16 +#define AP83_050_GPIO_VSC7385_SCK 17 + +#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) + +static struct mtd_partition ap83_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x040000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x060000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x1a0000, + .size = 0x650000, + }, { + .name = "art", + .offset = 0x7f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x060000, + .size = 0x790000, + } +}; + +static struct physmap_flash_data ap83_flash_data = { + .width = 2, + .parts = ap83_flash_partitions, + .nr_parts = ARRAY_SIZE(ap83_flash_partitions), +}; + +static struct resource ap83_flash_resources[] = { + [0] = { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ap83_flash_device = { + .name = "ar91xx-flash", + .id = -1, + .resource = ap83_flash_resources, + .num_resources = ARRAY_SIZE(ap83_flash_resources), + .dev = { + .platform_data = &ap83_flash_data, + } +}; + +static struct gpio_led ap83_leds_gpio[] __initdata = { + { + .name = "ap83:green:jumpstart", + .gpio = AP83_GPIO_LED_JUMPSTART, + .active_low = 0, + }, { + .name = "ap83:green:power", + .gpio = AP83_GPIO_LED_POWER, + .active_low = 0, + }, { + .name = "ap83:green:wlan", + .gpio = AP83_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ap83_gpio_keys[] __initdata = { + { + .desc = "soft_reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP83_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "jumpstart", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP83_GPIO_BTN_JUMPSTART, + .active_low = 1, + } +}; + +static struct resource ap83_040_spi_resources[] = { + [0] = { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ap83_040_spi_device = { + .name = "ap83-spi", + .id = 0, + .resource = ap83_040_spi_resources, + .num_resources = ARRAY_SIZE(ap83_040_spi_resources), +}; + +static struct spi_gpio_platform_data ap83_050_spi_data = { + .miso = AP83_050_GPIO_VSC7385_MISO, + .mosi = AP83_050_GPIO_VSC7385_MOSI, + .sck = AP83_050_GPIO_VSC7385_SCK, + .num_chipselect = 1, +}; + +static struct platform_device ap83_050_spi_device = { + .name = "spi_gpio", + .id = 0, + .dev = { + .platform_data = &ap83_050_spi_data, + } +}; + +static void ap83_vsc7385_reset(void) +{ + ath79_device_reset_set(AR71XX_RESET_GE1_PHY); + udelay(10); + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); + mdelay(50); +} + +static struct vsc7385_platform_data ap83_vsc7385_data = { + .reset = ap83_vsc7385_reset, + .ucode_name = "vsc7385_ucode_ap83.bin", + .mac_cfg = { + .tx_ipg = 6, + .bit2 = 0, + .clk_sel = 3, + }, +}; + +static struct spi_board_info ap83_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "spi-vsc7385", + .platform_data = &ap83_vsc7385_data, + .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, + } +}; + +static void __init ap83_generic_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0xfffffffe); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = 0x1; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_eth1_pll_data.pll_1000 = 0x1f000000; + + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), + ap83_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap83_gpio_keys), + ap83_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(eeprom, NULL); + + platform_device_register(&ap83_flash_device); + + spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); +} + +static void ap83_040_flash_lock(struct platform_device *pdev) +{ + ath79_flash_acquire(); +} + +static void ap83_040_flash_unlock(struct platform_device *pdev) +{ + ath79_flash_release(); +} + +static void __init ap83_040_setup(void) +{ + ap83_flash_data.lock = ap83_040_flash_lock; + ap83_flash_data.unlock = ap83_040_flash_unlock; + ap83_generic_setup(); + platform_device_register(&ap83_040_spi_device); +} + +static void __init ap83_050_setup(void) +{ + ap83_generic_setup(); + platform_device_register(&ap83_050_spi_device); +} + +static void __init ap83_setup(void) +{ + u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); + unsigned int board_version; + + board_version = (unsigned int)(board_id[0] - '0'); + board_version += ((unsigned int)(board_id[1] - '0')) * 10; + + switch (board_version) { + case 40: + ap83_040_setup(); + break; + case 50: + ap83_050_setup(); + break; + default: + printk(KERN_WARNING "AP83-%03u board is not yet supported\n", + board_version); + } +} + +MIPS_MACHINE(ATH79_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c new file mode 100644 index 000000000..35120d3e2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c @@ -0,0 +1,142 @@ +/* + * Atheros AP96 board support + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define AP96_GPIO_LED_12_GREEN 0 +#define AP96_GPIO_LED_3_GREEN 1 +#define AP96_GPIO_LED_2_GREEN 2 +#define AP96_GPIO_LED_WPS_GREEN 4 +#define AP96_GPIO_LED_5_GREEN 5 +#define AP96_GPIO_LED_4_ORANGE 6 + +/* Reset button - next to the power connector */ +#define AP96_GPIO_BTN_RESET 3 +/* WPS button - next to a led on right */ +#define AP96_GPIO_BTN_WPS 8 + +#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL) + +#define AP96_WMAC0_MAC_OFFSET 0x120c +#define AP96_WMAC1_MAC_OFFSET 0x520c +#define AP96_CALDATA0_OFFSET 0x1000 +#define AP96_CALDATA1_OFFSET 0x5000 + +/* + * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12 + * below (from left to right on the board). Led 1 seems to be on whenever the + * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange; + * others are green. + * + * In addition, there is one led next to a button on the right side for WPS. + */ +static struct gpio_led ap96_leds_gpio[] __initdata = { + { + .name = "ap96:green:led2", + .gpio = AP96_GPIO_LED_2_GREEN, + .active_low = 1, + }, { + .name = "ap96:green:led3", + .gpio = AP96_GPIO_LED_3_GREEN, + .active_low = 1, + }, { + .name = "ap96:orange:led4", + .gpio = AP96_GPIO_LED_4_ORANGE, + .active_low = 1, + }, { + .name = "ap96:green:led5", + .gpio = AP96_GPIO_LED_5_GREEN, + .active_low = 1, + }, { + .name = "ap96:green:led12", + .gpio = AP96_GPIO_LED_12_GREEN, + .active_low = 1, + }, { /* next to a button on right */ + .name = "ap96:green:wps", + .gpio = AP96_GPIO_LED_WPS_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap96_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP96_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP96_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +#define AP96_WAN_PHYMASK 0x10 +#define AP96_LAN_PHYMASK 0x0f + +static void __init ap96_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK; + + ath79_eth1_pll_data.pll_1000 = 0x1f000000; + + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio), + ap96_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap96_gpio_keys), + ap96_gpio_keys); + + ap94_pci_init(art + AP96_CALDATA0_OFFSET, + art + AP96_WMAC0_MAC_OFFSET, + art + AP96_CALDATA1_OFFSET, + art + AP96_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c new file mode 100644 index 000000000..281129b78 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c @@ -0,0 +1,107 @@ +/* + * AzureWave AW-NR580 board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" +#include "pci.h" + +#define AW_NR580_GPIO_LED_READY_RED 0 +#define AW_NR580_GPIO_LED_WLAN 1 +#define AW_NR580_GPIO_LED_READY_GREEN 2 +#define AW_NR580_GPIO_LED_WPS_GREEN 4 +#define AW_NR580_GPIO_LED_WPS_AMBER 5 + +#define AW_NR580_GPIO_BTN_WPS 3 +#define AW_NR580_GPIO_BTN_RESET 11 + +#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL) + +static struct gpio_led aw_nr580_leds_gpio[] __initdata = { + { + .name = "aw-nr580:red:ready", + .gpio = AW_NR580_GPIO_LED_READY_RED, + .active_low = 0, + }, { + .name = "aw-nr580:green:ready", + .gpio = AW_NR580_GPIO_LED_READY_GREEN, + .active_low = 0, + }, { + .name = "aw-nr580:green:wps", + .gpio = AW_NR580_GPIO_LED_WPS_GREEN, + .active_low = 0, + }, { + .name = "aw-nr580:amber:wps", + .gpio = AW_NR580_GPIO_LED_WPS_AMBER, + .active_low = 0, + }, { + .name = "aw-nr580:green:wlan", + .gpio = AW_NR580_GPIO_LED_WLAN, + .active_low = 0, + } +}; + +static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, + .gpio = AW_NR580_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, + .gpio = AW_NR580_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static const char *aw_nr580_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data aw_nr580_flash_data = { + .part_probes = aw_nr580_part_probes, +}; + +static void __init aw_nr580_setup(void) +{ + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_register_pci(); + + ath79_register_m25p80(&aw_nr580_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), + aw_nr580_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL, + ARRAY_SIZE(aw_nr580_gpio_keys), + aw_nr580_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", + aw_nr580_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c new file mode 100644 index 000000000..c0fa9008c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c @@ -0,0 +1,151 @@ +/* + * D-Link DIR-600 rev. A1 board support + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "nvram.h" + +#define DIR_600_A1_GPIO_LED_WPS 0 +#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 +#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 +#define DIR_600_A1_GPIO_LED_LAN1 13 +#define DIR_600_A1_GPIO_LED_LAN2 14 +#define DIR_600_A1_GPIO_LED_LAN3 15 +#define DIR_600_A1_GPIO_LED_LAN4 16 +#define DIR_600_A1_GPIO_LED_WAN_AMBER 7 +#define DIR_600_A1_GPIO_LED_WAN_GREEN 17 + +#define DIR_600_A1_GPIO_BTN_RESET 8 +#define DIR_600_A1_GPIO_BTN_WPS 12 + +#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL) + +#define DIR_600_A1_NVRAM_ADDR 0x1f030000 +#define DIR_600_A1_NVRAM_SIZE 0x10000 + +static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, + }, { + .name = "d-link:amber:power", + .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_600_A1_GPIO_LED_WAN_AMBER, + }, { + .name = "d-link:green:wan", + .gpio = DIR_600_A1_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:green:lan1", + .gpio = DIR_600_A1_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "d-link:green:lan2", + .gpio = DIR_600_A1_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "d-link:green:lan3", + .gpio = DIR_600_A1_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "d-link:green:lan4", + .gpio = DIR_600_A1_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_600_A1_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_600_A1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_600_A1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_600_a1_setup(void) +{ + const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac_buff[6]; + u8 *mac = NULL; + + if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, + "lan_mac=", mac_buff) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1); + mac = mac_buff; + } + + ath79_register_m25p80(NULL); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), + dir_600_a1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_600_a1_gpio_keys), + dir_600_a1_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", + dir_600_a1_setup); + +static void __init dir_615_e4_setup(void) +{ + dir_600_a1_setup(); + ap9x_pci_setup_wmac_led_pin(0, 1); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4", + dir_615_e4_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c new file mode 100644 index 000000000..425be301e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c @@ -0,0 +1,133 @@ +/* + * D-Link DIR-615 rev C1 board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ +#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ +#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ +#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ +#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ +#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ +#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ + +/* buttons may need refinement */ + +#define DIR_615C1_GPIO_BTN_WPS 12 +#define DIR_615C1_GPIO_BTN_RESET 21 + +#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL) + +#define DIR_615C1_CONFIG_ADDR 0x1f020000 +#define DIR_615C1_CONFIG_SIZE 0x10000 + +static struct gpio_led dir_615c1_leds_gpio[] __initdata = { + { + .name = "d-link:orange:status", + .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, { + .name = "d-link:green:wan", + .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, + .active_low = 1, + }, { + .name = "d-link:green:wancpu", + .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, + .active_low = 1, + }, { + .name = "d-link:green:wlan", + .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, + .active_low = 1, + }, { + .name = "d-link:green:status", + .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, + .active_low = 1, + }, { + .name = "d-link:orange:wan", + .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, + .active_low = 1, + } + +}; + +static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615C1_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615C1_GPIO_BTN_WPS, + } +}; + +#define DIR_615C1_LAN_PHYMASK BIT(0) +#define DIR_615C1_WAN_PHYMASK BIT(4) +#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ + DIR_615C1_WAN_PHYMASK)) + +static void __init dir_615c1_setup(void) +{ + const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + u8 *wlan_mac = NULL; + + if (ath79_nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, + "lan_mac=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + wlan_mac = mac; + } + + ath79_register_mdio(0, DIR_615C1_MDIO_MASK); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), + dir_615c1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_615c1_gpio_keys), + dir_615c1_gpio_keys); + + ath79_register_wmac(eeprom, wlan_mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", + dir_615c1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c new file mode 100644 index 000000000..476cbd98e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c @@ -0,0 +1,200 @@ +/* + * D-Link DIR-825 rev. B1 board support + * + * Copyright (C) 2009-2011 Lukas Kuna, Evkanet, s.r.o. + * + * based on mach-wndr3700.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/rtl8366.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define DIR825B1_GPIO_LED_BLUE_USB 0 +#define DIR825B1_GPIO_LED_ORANGE_POWER 1 +#define DIR825B1_GPIO_LED_BLUE_POWER 2 +#define DIR825B1_GPIO_LED_BLUE_WPS 4 +#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 +#define DIR825B1_GPIO_LED_BLUE_PLANET 11 + +#define DIR825B1_GPIO_BTN_RESET 3 +#define DIR825B1_GPIO_BTN_WPS 8 + +#define DIR825B1_GPIO_RTL8366_SDA 5 +#define DIR825B1_GPIO_RTL8366_SCK 7 + +#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL) + +#define DIR825B1_CAL0_OFFSET 0x1000 +#define DIR825B1_CAL1_OFFSET 0x5000 +#define DIR825B1_MAC0_OFFSET 0xffa0 +#define DIR825B1_MAC1_OFFSET 0xffb4 + +#define DIR825B1_CAL_LOCATION_0 0x1f660000 +#define DIR825B1_CAL_LOCATION_1 0x1f7f0000 + +static struct gpio_led dir825b1_leds_gpio[] __initdata = { + { + .name = "d-link:blue:usb", + .gpio = DIR825B1_GPIO_LED_BLUE_USB, + .active_low = 1, + }, { + .name = "d-link:orange:power", + .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, + .active_low = 1, + }, { + .name = "d-link:blue:power", + .gpio = DIR825B1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR825B1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, { + .name = "d-link:orange:planet", + .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, + .active_low = 1, + }, { + .name = "d-link:blue:planet", + .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825B1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825B1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = { + { .reg = 0x06, .val = 0x0108 }, +}; + +static struct rtl8366_platform_data dir825b1_rtl8366s_data = { + .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, + .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, + .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals), + .initvals = dir825b1_rtl8366s_initvals, +}; + +static struct platform_device dir825b1_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &dir825b1_rtl8366s_data, + } +}; + +static void dir825b1_read_ascii_mac(u8 *dest, u8 *src) +{ + int ret; + + ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &dest[0], &dest[1], &dest[2], + &dest[3], &dest[4], &dest[5]); + + if (ret != ETH_ALEN) + memset(dest, 0, ETH_ALEN); +} + +static bool __init dir825b1_is_caldata_valid(u8 *p) +{ + u16 *magic0, *magic1; + + magic0 = (u16 *)(p + DIR825B1_CAL0_OFFSET); + magic1 = (u16 *)(p + DIR825B1_CAL1_OFFSET); + + return (*magic0 == 0xa55a && *magic1 == 0xa55a); +} + +static void __init dir825b1_wlan_init(void) +{ + u8 *caldata; + u8 mac1[ETH_ALEN], mac2[ETH_ALEN]; + + caldata = (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0); + if (!dir825b1_is_caldata_valid(caldata)) { + caldata = (u8 *)KSEG1ADDR(DIR825B1_CAL_LOCATION_1); + if (!dir825b1_is_caldata_valid(caldata)) { + pr_err("no calibration data found\n"); + return; + } + } + + dir825b1_read_ascii_mac(mac1, caldata + DIR825B1_MAC0_OFFSET); + dir825b1_read_ascii_mac(mac2, caldata + DIR825B1_MAC1_OFFSET); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(caldata + DIR825B1_CAL0_OFFSET, mac1, + caldata + DIR825B1_CAL1_OFFSET, mac2); +} + +static void __init dir825b1_setup(void) +{ + dir825b1_wlan_init(); + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x11110000; + + ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + ath79_eth1_pll_data.pll_1000 = 0x11110000; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), + dir825b1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir825b1_gpio_keys), + dir825b1_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&dir825b1_rtl8366s_device); +} + +MIPS_MACHINE(ATH79_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", + dir825b1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c new file mode 100644 index 000000000..787e6275d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c @@ -0,0 +1,181 @@ +/* + * Senao EAP7660D board support + * + * Copyright (C) 2010 Daniel Golle <daniel.golle@gmail.com> + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/pci.h> +#include <linux/ath5k_platform.h> +#include <linux/delay.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL) + +#define EAP7660D_GPIO_DS4 7 +#define EAP7660D_GPIO_DS5 2 +#define EAP7660D_GPIO_DS7 0 +#define EAP7660D_GPIO_DS8 4 +#define EAP7660D_GPIO_SW1 3 +#define EAP7660D_GPIO_SW3 8 +#define EAP7660D_PHYMASK BIT(20) +#define EAP7660D_BOARDCONFIG 0x1F7F0000 +#define EAP7660D_GBIC_MAC_OFFSET 0x1000 +#define EAP7660D_WMAC0_MAC_OFFSET 0x1010 +#define EAP7660D_WMAC1_MAC_OFFSET 0x1016 +#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000 +#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000 + +#ifdef CONFIG_PCI +static struct ath5k_platform_data eap7660d_wmac0_data; +static struct ath5k_platform_data eap7660d_wmac1_data; +static char eap7660d_wmac0_mac[6]; +static char eap7660d_wmac1_mac[6]; +static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; +static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; + +static int eap7660d_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 17: + dev->dev.platform_data = &eap7660d_wmac0_data; + break; + + case 18: + dev->dev.platform_data = &eap7660d_wmac1_data; + break; + } + + return 0; +} + +void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ + if (cal_data0 && *cal_data0 == 0xa55a) { + memcpy(eap7660d_wmac0_eeprom, cal_data0, + ATH5K_PLAT_EEP_MAX_WORDS); + eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom; + } + + if (cal_data1 && *cal_data1 == 0xa55a) { + memcpy(eap7660d_wmac1_eeprom, cal_data1, + ATH5K_PLAT_EEP_MAX_WORDS); + eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom; + } + + if (mac_addr0) { + memcpy(eap7660d_wmac0_mac, mac_addr0, + sizeof(eap7660d_wmac0_mac)); + eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac; + } + + if (mac_addr1) { + memcpy(eap7660d_wmac1_mac, mac_addr1, + sizeof(eap7660d_wmac1_mac)); + eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac; + } + + ath79_pci_set_plat_dev_init(eap7660d_pci_plat_dev_init); + ath79_register_pci(); +} +#else +static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ +} +#endif /* CONFIG_PCI */ + +static struct gpio_led eap7660d_leds_gpio[] __initdata = { + { + .name = "eap7660d:green:ds8", + .gpio = EAP7660D_GPIO_DS8, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds5", + .gpio = EAP7660D_GPIO_DS5, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds7", + .gpio = EAP7660D_GPIO_DS7, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds4", + .gpio = EAP7660D_GPIO_DS4, + .active_low = 0, + } +}; + +static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP7660D_GPIO_SW1, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP7660D_GPIO_SW3, + .active_low = 1, + } +}; + +static const char *eap7660d_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data eap7660d_flash_data = { + .part_probes = eap7660d_part_probes, +}; + +static void __init eap7660d_setup(void) +{ + u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG); + + ath79_register_mdio(0, ~EAP7660D_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, + boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = EAP7660D_PHYMASK; + ath79_register_eth(0); + ath79_register_m25p80(&eap7660d_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio), + eap7660d_leds_gpio); + ath79_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL, + ARRAY_SIZE(eap7660d_gpio_keys), + eap7660d_gpio_keys); + eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET, + boardconfig + EAP7660D_WMAC0_MAC_OFFSET, + boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET, + boardconfig + EAP7660D_WMAC1_MAC_OFFSET); +}; + +MIPS_MACHINE(ATH79_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D", + eap7660d_setup); + +MIPS_MACHINE(ATH79_MACH_ALL0305, "ALL0305", "Allnet ALL0305", + eap7660d_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c new file mode 100644 index 000000000..47ed51b5d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c @@ -0,0 +1,144 @@ +/* + * EW Dorin board support + * (based on Atheros Ref. Design AP121) + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2012 Embedded Wireless GmbH www.80211.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DORIN_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DORIN_KEYS_DEBOUNCE_INTERVAL (3 * DORIN_KEYS_POLL_INTERVAL) + +#define DORIN_CALDATA_OFFSET 0x1000 +#define DORIN_WMAC_MAC_OFFSET 0x1002 + +#define DORIN_GPIO_LED_21 21 +#define DORIN_GPIO_LED_22 22 + +#define DORIN_GPIO_BTN_JUMPSTART 11 +#define DORIN_GPIO_BTN_RESET 6 + +static struct gpio_led dorin_leds_gpio[] __initdata = { + { + .name = "dorin:green:led21", + .gpio = DORIN_GPIO_LED_21, + .active_low = 1, + }, + { + .name = "dorin:green:led22", + .gpio = DORIN_GPIO_LED_22, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dorin_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL, + .gpio = DORIN_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL, + .gpio = DORIN_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init ew_dorin_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + static u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + if (ar93xx_wmac_read_mac_address(mac)) { + ath79_register_wmac(NULL, NULL); + } else { + ath79_register_wmac(art + DORIN_CALDATA_OFFSET, + art + DORIN_WMAC_MAC_OFFSET); + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac)); + } + + mac[3] |= 0x40; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio), + dorin_leds_gpio); + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dorin_gpio_keys), + dorin_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_EW_DORIN, "EW-DORIN", "EmbWir-Dorin", + ew_dorin_setup); + + +static void __init ew_dorin_router_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + static u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + if (ar93xx_wmac_read_mac_address(mac)) { + ath79_register_wmac(NULL, NULL); + } else { + ath79_register_wmac(art + DORIN_CALDATA_OFFSET, + art + DORIN_WMAC_MAC_OFFSET); + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac)); + } + + mac[3] |= 0x40; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + mac[3] &= 0x3F; + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio), + dorin_leds_gpio); + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dorin_gpio_keys), + dorin_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_EW_DORIN_ROUTER, "EW-DORIN-ROUTER", + "EmbWir-Dorin-Router", ew_dorin_router_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c new file mode 100644 index 000000000..f8870e711 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c @@ -0,0 +1,136 @@ +/* + * ALFA NETWORKS Hornet-UB board support + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define HORNET_UB_GPIO_LED_WLAN 0 +#define HORNET_UB_GPIO_LED_USB 1 +#define HORNET_UB_GPIO_LED_LAN 13 +#define HORNET_UB_GPIO_LED_WAN 17 +#define HORNET_UB_GPIO_LED_WPS 27 + +#define HORNET_UB_GPIO_BTN_RESET 11 +#define HORNET_UB_GPIO_BTN_WPS 12 + +#define HORNET_UB_GPIO_USB_POWER 26 + +#define HORNET_UB_KEYS_POLL_INTERVAL 20 /* msecs */ +#define HORNET_UB_KEYS_DEBOUNCE_INTERVAL (3 * HORNET_UB_KEYS_POLL_INTERVAL) + +#define HORNET_UB_MAC0_OFFSET 0x0000 +#define HORNET_UB_MAC1_OFFSET 0x0006 +#define HORNET_UB_CALDATA_OFFSET 0x1000 + +static struct gpio_led hornet_ub_leds_gpio[] __initdata = { + { + .name = "alfa:blue:lan", + .gpio = HORNET_UB_GPIO_LED_LAN, + .active_low = 0, + }, + { + .name = "alfa:blue:usb", + .gpio = HORNET_UB_GPIO_LED_USB, + .active_low = 0, + }, + { + .name = "alfa:blue:wan", + .gpio = HORNET_UB_GPIO_LED_WAN, + .active_low = 1, + }, + { + .name = "alfa:blue:wlan", + .gpio = HORNET_UB_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "alfa:blue:wps", + .gpio = HORNET_UB_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button hornet_ub_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL, + .gpio = HORNET_UB_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL, + .gpio = HORNET_UB_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init hornet_ub_gpio_setup(void) +{ + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + ath79_set_usb_power_gpio(HORNET_UB_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "USB power"); +} + +static void __init hornet_ub_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + hornet_ub_gpio_setup(); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio), + hornet_ub_leds_gpio); + ath79_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL, + ARRAY_SIZE(hornet_ub_gpio_keys), + hornet_ub_gpio_keys); + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + HORNET_UB_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, + art + HORNET_UB_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_HORNET_UB, "HORNET-UB", "ALFA NETWORKS Hornet-UB", + hornet_ub_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c new file mode 100644 index 000000000..d1fe0f8a2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c @@ -0,0 +1,190 @@ +/* + * jjPlus JA76PF board support + */ + +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */ +#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL) + +#define JA76PF_GPIO_I2C_SCL 0 +#define JA76PF_GPIO_I2C_SDA 1 +#define JA76PF_GPIO_LED_1 5 +#define JA76PF_GPIO_LED_2 4 +#define JA76PF_GPIO_LED_3 3 +#define JA76PF_GPIO_BTN_RESET 11 + +static struct gpio_led ja76pf_leds_gpio[] __initdata = { + { + .name = "jjplus:green:led1", + .gpio = JA76PF_GPIO_LED_1, + .active_low = 1, + }, { + .name = "jjplus:green:led2", + .gpio = JA76PF_GPIO_LED_2, + .active_low = 1, + }, { + .name = "jjplus:green:led3", + .gpio = JA76PF_GPIO_LED_3, + .active_low = 1, + } +}; + +static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = { + .sda_pin = JA76PF_GPIO_I2C_SDA, + .scl_pin = JA76PF_GPIO_I2C_SCL, +}; + +static struct platform_device ja76pf_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &ja76pf_i2c_gpio_data, + } +}; + +static const char *ja76pf_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data ja76pf_flash_data = { + .part_probes = ja76pf_part_probes, +}; + +#define JA76PF_WAN_PHYMASK (1 << 4) +#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3)) +#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK) + +static void __init ja76pf_init(void) +{ + ath79_register_m25p80(&ja76pf_flash_data); + + ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + platform_device_register(&ja76pf_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio), + ja76pf_leds_gpio); + + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ja76pf_gpio_keys), + ja76pf_gpio_keys); + + ath79_register_usb(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init); + +#define JA76PF2_GPIO_LED_D2 5 +#define JA76PF2_GPIO_LED_D3 4 +#define JA76PF2_GPIO_LED_D4 3 +#define JA76PF2_GPIO_BTN_RESET 7 +#define JA76PF2_GPIO_BTN_WPS 8 + +static struct gpio_led ja76pf2_leds_gpio[] __initdata = { + { + .name = "jjplus:green:led1", + .gpio = JA76PF2_GPIO_LED_D2, + .active_low = 1, + }, { + .name = "jjplus:green:led2", + .gpio = JA76PF2_GPIO_LED_D3, + .active_low = 0, + }, { + .name = "jjplus:green:led3", + .gpio = JA76PF2_GPIO_LED_D4, + .active_low = 0, + } +}; + +static struct gpio_keys_button ja76pf2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF2_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +#define JA76PF2_LAN_PHYMASK BIT(0) +#define JA76PF2_WAN_PHYMASK BIT(4) +#define JA76PF2_MDIO_PHYMASK (JA76PF2_LAN_PHYMASK | JA76PF2_WAN_PHYMASK) + +static void __init ja76pf2_init(void) +{ + ath79_register_m25p80(&ja76pf_flash_data); + + ath79_register_mdio(0, ~JA76PF2_MDIO_PHYMASK); + + /* MAC0 is connected to the CPU port of the AR8316 switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + /* MAC1 is connected to the PHY4 of the AR8316 switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf2_leds_gpio), + ja76pf2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ja76pf2_gpio_keys), + ja76pf2_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JA76PF2, "JA76PF2", "jjPlus JA76PF2", ja76pf2_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c new file mode 100644 index 000000000..a3c93ccd9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c @@ -0,0 +1,95 @@ +/* + * jjPlus JWAP003 board support + * + */ + +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */ +#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL) + +#define JWAP003_GPIO_WPS 11 +#define JWAP003_GPIO_I2C_SCL 0 +#define JWAP003_GPIO_I2C_SDA 1 + +static struct gpio_keys_button jwap003_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL, + .gpio = JWAP003_GPIO_WPS, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = { + .sda_pin = JWAP003_GPIO_I2C_SDA, + .scl_pin = JWAP003_GPIO_I2C_SCL, +}; + +static struct platform_device jwap003_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &jwap003_i2c_gpio_data, + } +}; + +static const char *jwap003_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data jwap003_flash_data = { + .part_probes = jwap003_part_probes, +}; + +#define JWAP003_WAN_PHYMASK BIT(0) +#define JWAP003_LAN_PHYMASK BIT(4) + +static void __init jwap003_init(void) +{ + ath79_register_m25p80(&jwap003_flash_data); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = JWAP003_WAN_PHYMASK; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = JWAP003_LAN_PHYMASK; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + platform_device_register(&jwap003_i2c_gpio_device); + + ath79_register_usb(); + + ath79_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL, + ARRAY_SIZE(jwap003_gpio_keys), + jwap003_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c new file mode 100644 index 000000000..c2460ce33 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c @@ -0,0 +1,124 @@ +/* + * Planex MZK-W04NU board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MZK_W04NU_GPIO_LED_USB 0 +#define MZK_W04NU_GPIO_LED_STATUS 1 +#define MZK_W04NU_GPIO_LED_WPS 3 +#define MZK_W04NU_GPIO_LED_WLAN 6 +#define MZK_W04NU_GPIO_LED_AP 15 +#define MZK_W04NU_GPIO_LED_ROUTER 16 + +#define MZK_W04NU_GPIO_BTN_APROUTER 5 +#define MZK_W04NU_GPIO_BTN_WPS 12 +#define MZK_W04NU_GPIO_BTN_RESET 21 + +#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL) + +static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { + { + .name = "planex:green:status", + .gpio = MZK_W04NU_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "planex:blue:wps", + .gpio = MZK_W04NU_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "planex:green:wlan", + .gpio = MZK_W04NU_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "planex:green:usb", + .gpio = MZK_W04NU_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "planex:green:ap", + .gpio = MZK_W04NU_GPIO_LED_AP, + .active_low = 1, + }, { + .name = "planex:green:router", + .gpio = MZK_W04NU_GPIO_LED_ROUTER, + .active_low = 1, + } +}; + +static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "aprouter", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_APROUTER, + .active_low = 0, + } +}; + +#define MZK_W04NU_WAN_PHYMASK BIT(4) +#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) + +static void __init mzk_w04nu_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, MZK_W04NU_MDIO_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), + mzk_w04nu_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzk_w04nu_gpio_keys), + mzk_w04nu_gpio_keys); + ath79_register_usb(); + + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", + mzk_w04nu_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c new file mode 100644 index 000000000..8c4036528 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c @@ -0,0 +1,115 @@ +/* + * Planex MZK-W300NH board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MZK_W300NH_GPIO_LED_STATUS 1 +#define MZK_W300NH_GPIO_LED_WPS 3 +#define MZK_W300NH_GPIO_LED_WLAN 6 +#define MZK_W300NH_GPIO_LED_AP_GREEN 15 +#define MZK_W300NH_GPIO_LED_AP_AMBER 16 + +#define MZK_W300NH_GPIO_BTN_APROUTER 5 +#define MZK_W300NH_GPIO_BTN_WPS 12 +#define MZK_W300NH_GPIO_BTN_RESET 21 + +#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL) + +static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { + { + .name = "planex:green:status", + .gpio = MZK_W300NH_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "planex:blue:wps", + .gpio = MZK_W300NH_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "planex:green:wlan", + .gpio = MZK_W300NH_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "planex:green:aprouter", + .gpio = MZK_W300NH_GPIO_LED_AP_GREEN, + }, { + .name = "planex:amber:aprouter", + .gpio = MZK_W300NH_GPIO_LED_AP_AMBER, + } +}; + +static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "aprouter", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_APROUTER, + .active_low = 0, + } +}; + +#define MZK_W300NH_WAN_PHYMASK BIT(4) +#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) + +static void __init mzk_w300nh_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, MZK_W300NH_MDIO_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), + mzk_w300nh_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzk_w300nh_gpio_keys), + mzk_w300nh_gpio_keys); + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", + mzk_w300nh_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c new file mode 100644 index 000000000..8aa7331d4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c @@ -0,0 +1,220 @@ +/* + * Zyxel NBG 460N/550N/550NH board support + * + * Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com> + * + * based on mach-tl-wr1043nd.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/i2c-algo-bit.h> +#include <linux/i2c-gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/rtl8366.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* LEDs */ +#define NBG460N_GPIO_LED_WPS 3 +#define NBG460N_GPIO_LED_WAN 6 +#define NBG460N_GPIO_LED_POWER 14 +#define NBG460N_GPIO_LED_WLAN 15 + +/* Buttons */ +#define NBG460N_GPIO_BTN_WPS 12 +#define NBG460N_GPIO_BTN_RESET 21 + +#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL) + +/* RTC chip PCF8563 I2C interface */ +#define NBG460N_GPIO_PCF8563_SDA 8 +#define NBG460N_GPIO_PCF8563_SCK 7 + +/* Switch configuration I2C interface */ +#define NBG460N_GPIO_RTL8366_SDA 16 +#define NBG460N_GPIO_RTL8366_SCK 18 + +static struct mtd_partition nbg460n_partitions[] = { + { + .name = "Bootbase", + .offset = 0, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "U-Boot Config", + .offset = 0x010000, + .size = 0x030000, + }, { + .name = "U-Boot", + .offset = 0x040000, + .size = 0x030000, + }, { + .name = "linux", + .offset = 0x070000, + .size = 0x0e0000, + }, { + .name = "rootfs", + .offset = 0x150000, + .size = 0x2a0000, + }, { + .name = "CalibData", + .offset = 0x3f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x070000, + .size = 0x380000, + } +}; + +static struct flash_platform_data nbg460n_flash_data = { + .parts = nbg460n_partitions, + .nr_parts = ARRAY_SIZE(nbg460n_partitions), +}; + +static struct gpio_led nbg460n_leds_gpio[] __initdata = { + { + .name = "nbg460n:green:power", + .gpio = NBG460N_GPIO_LED_POWER, + .active_low = 0, + .default_trigger = "default-on", + }, { + .name = "nbg460n:green:wps", + .gpio = NBG460N_GPIO_LED_WPS, + .active_low = 0, + }, { + .name = "nbg460n:green:wlan", + .gpio = NBG460N_GPIO_LED_WLAN, + .active_low = 0, + }, { + /* Not really for controlling the LED, + when set low the LED blinks uncontrollable */ + .name = "nbg460n:green:wan", + .gpio = NBG460N_GPIO_LED_WAN, + .active_low = 0, + } +}; + +static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG460N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG460N_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { + .sda_pin = NBG460N_GPIO_PCF8563_SDA, + .scl_pin = NBG460N_GPIO_PCF8563_SCK, + .udelay = 10, +}; + +static struct platform_device nbg460n_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .num_resources = 0, + .resource = NULL, + .dev = { + .platform_data = &nbg460n_i2c_device_platdata, + }, +}; + +static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static void __devinit nbg460n_i2c_init(void) +{ + /* The gpio interface */ + platform_device_register(&nbg460n_i2c_device); + /* I2C devices */ + i2c_register_board_info(0, nbg460n_i2c_devs, + ARRAY_SIZE(nbg460n_i2c_devs)); +} + + +static struct rtl8366_platform_data nbg460n_rtl8366s_data = { + .gpio_sda = NBG460N_GPIO_RTL8366_SDA, + .gpio_sck = NBG460N_GPIO_RTL8366_SCK, +}; + +static struct platform_device nbg460n_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &nbg460n_rtl8366s_data, + } +}; + +static void __init nbg460n_setup(void) +{ + /* end of bootloader sector contains mac address */ + u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); + /* last sector contains wlan calib data */ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + /* LAN Port */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + /* WAN Port */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + ath79_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + /* register the switch phy */ + platform_device_register(&nbg460n_rtl8366s_device); + + /* register flash */ + ath79_register_m25p80(&nbg460n_flash_data); + + ath79_register_wmac(eeprom, mac); + + /* register RTC chip */ + nbg460n_i2c_init(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), + nbg460n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nbg460n_gpio_keys), + nbg460n_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", + nbg460n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c new file mode 100644 index 000000000..faeb49a51 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c @@ -0,0 +1,176 @@ +/* + * OpenMesh OM2P support + * + * Copyright (C) 2011 Marek Lindner <marek@open-mesh.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OM2P_GPIO_LED_POWER 0 +#define OM2P_GPIO_LED_GREEN 13 +#define OM2P_GPIO_LED_RED 14 +#define OM2P_GPIO_LED_YELLOW 15 +#define OM2P_GPIO_LED_LAN 16 +#define OM2P_GPIO_LED_WAN 17 +#define OM2P_GPIO_BTN_RESET 11 + +#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL) + +#define OM2P_WAN_PHYMASK BIT(4) + +#define OM2P_LC_GPIO_LED_POWER 1 +#define OM2P_LC_GPIO_LED_GREEN 15 +#define OM2P_LC_GPIO_LED_RED 16 +#define OM2P_LC_GPIO_LED_YELLOW 0 +#define OM2P_LC_GPIO_LED_LAN 13 +#define OM2P_LC_GPIO_LED_WAN 17 +#define OM2P_LC_GPIO_BTN_RESET 12 + +static struct flash_platform_data om2p_flash_data = { + .type = "s25sl12800", + .name = "ar7240-nor0", +}; + +static struct gpio_led om2p_leds_gpio[] __initdata = { + { + .name = "om2p:blue:power", + .gpio = OM2P_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om2p:red:wifi", + .gpio = OM2P_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om2p:yellow:wifi", + .gpio = OM2P_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om2p:green:wifi", + .gpio = OM2P_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "om2p:blue:lan", + .gpio = OM2P_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "om2p:blue:wan", + .gpio = OM2P_GPIO_LED_WAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button om2p_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL, + .gpio = OM2P_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init om2p_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(&om2p_flash_data); + + ath79_register_mdio(0, ~OM2P_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_OM2P, "OM2P", "OpenMesh OM2P", om2p_setup); + + +static struct flash_platform_data om2p_lc_flash_data = { + .type = "s25sl12800", +}; + +static void __init om2p_lc_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000); + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + ath79_register_m25p80(&om2p_lc_flash_data); + + om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER; + om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED; + om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW; + om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN; + om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN; + om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN; + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + + om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET; + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); + + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, mac2, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(art, NULL); +} + +MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c new file mode 100644 index 000000000..3a350e90a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c @@ -0,0 +1,83 @@ +/* + * Atheros PB42 board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) + +#define PB42_GPIO_BTN_SW4 8 +#define PB42_GPIO_BTN_SW5 3 + +static struct gpio_keys_button pb42_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB42_GPIO_BTN_SW4, + .active_low = 1, + }, { + .desc = "sw5", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB42_GPIO_BTN_SW5, + .active_low = 1, + } +}; + +static const char *pb42_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data pb42_flash_data = { + .part_probes = pb42_part_probes, +}; + +#define PB42_WAN_PHYMASK BIT(20) +#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) +#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) + +static void __init pb42_init(void) +{ + ath79_register_m25p80(&pb42_flash_data); + + ath79_register_mdio(0, ~PB42_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb42_gpio_keys), + pb42_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c new file mode 100644 index 000000000..76715a517 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c @@ -0,0 +1,70 @@ +/* + * Atheros PB92 board support + * + * Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org> + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL) + +#define PB92_GPIO_BTN_SW4 8 +#define PB92_GPIO_BTN_SW5 3 + +static struct gpio_keys_button pb92_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB92_GPIO_BTN_SW4, + .active_low = 1, + }, { + .desc = "sw5", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB92_GPIO_BTN_SW5, + .active_low = 1, + } +}; + +static void __init pb92_init(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + ath79_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb92_gpio_keys), + pb92_gpio_keys); + + ath79_register_usb(); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_PB92, "PB92", "Atheros PB92", pb92_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c new file mode 100644 index 000000000..ecdd7ea2e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c @@ -0,0 +1,271 @@ +/* + * MikroTik RouterBOARD 2011 support + * + * Copyright (C) 2012 Stijn Tintel <stijn@linux-ipv6.be> + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb2011: " fmt + +#include <linux/phy.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/ath9k_platform.h> +#include <linux/ar8216_platform.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/rle.h> +#include <linux/routerboot.h> +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "routerboot.h" + +#define RB2011_GPIO_NAND_NCE 14 + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_SIZE 0xb000 +#define RB_HARD_CFG_OFFSET 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x2000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +#define RB_ART_SIZE 0x10000 + +static struct mtd_partition rb2011_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .size = RB_ROUTERBOOT_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .offset = RB_HARD_CFG_OFFSET, + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .offset = RB_SOFT_CFG_OFFSET, + .size = RB_SOFT_CFG_SIZE, + } +}; + +static struct mtd_partition rb2011_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data rb2011_spi_flash_data = { + .parts = rb2011_spi_partitions, + .nr_parts = ARRAY_SIZE(rb2011_spi_partitions), +}; + +static struct ar8327_pad_cfg rb2011_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data rb2011_ar8327_data = { + .pad0_cfg = &rb2011_ar8327_pad0_cfg, + .cpuport_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info rb2011_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb2011_ar8327_data, + }, +}; + +static void __init rb2011_gmac_setup(void) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); + t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE; + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init rb2011_wlan_init(void) +{ + u8 *hard_cfg = (u8 *) KSEG1ADDR(0x1f000000 + RB_HARD_CFG_OFFSET); + u16 tag_len; + u8 *tag; + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + int err; + + err = routerboot_find_tag(hard_cfg, RB_HARD_CFG_SIZE, RB_ID_WLAN_DATA, + &tag, &tag_len); + if (err) { + pr_err("no calibration data found\n"); + return; + } + + art_buf = kmalloc(RB_ART_SIZE, GFP_KERNEL); + if (art_buf == NULL) { + pr_err("no memory for calibration data\n"); + return; + } + + err = rle_decode((char *) tag, tag_len, art_buf, RB_ART_SIZE, + NULL, NULL); + if (err) { + pr_err("unable to decode calibration data\n"); + goto free; + } + + ath79_init_mac(wlan_mac, ath79_mac_base, 11); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + +free: + kfree(art_buf); +} + +static void rb2011_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB2011_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB2011_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb2011_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb2011_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb2011_nand_ecclayout; + } + + return 0; +} + +static void __init rb2011_nand_init(void) +{ + ath79_nfc_set_scan_fixup(rb2011_nand_scan_fixup); + ath79_nfc_set_parts(rb2011_nand_partitions, + ARRAY_SIZE(rb2011_nand_partitions)); + ath79_nfc_set_select_chip(rb2011_nand_select_chip); + ath79_register_nfc(); +} + +static void __init rb2011_gpio_init(void) +{ + gpio_request_one(RB2011_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); +} + +static void __init rb2011_setup(void) +{ + rb2011_gpio_init(); + + ath79_register_m25p80(&rb2011_spi_flash_data); + rb2011_nand_init(); + + rb2011_gmac_setup(); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb2011_mdio0_info, + ARRAY_SIZE(rb2011_mdio0_info)); + + /* GMAC0 is connected to an ar8327 switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_RB_2011L, "2011L", "MikroTik RouterBOARD 2011L", + rb2011_setup); + +static void __init rb2011g_setup(void) +{ + rb2011_setup(); + rb2011_wlan_init(); +} + +MIPS_MACHINE(ATH79_MACH_RB_2011G, "2011G", "MikroTik RouterBOARD 2011UAS-2HnD", + rb2011g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c new file mode 100644 index 000000000..1604a5c56 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c @@ -0,0 +1,405 @@ +/* + * MikroTik RouterBOARD 4xx series support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/mdio-gpio.h> +#include <linux/mmc/host.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/spi/mmc_spi.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/rb4xx_cpld.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define RB4XX_GPIO_USER_LED 4 +#define RB4XX_GPIO_RESET_SWITCH 7 + +#define RB4XX_GPIO_CPLD_BASE 32 +#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1) +#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2) +#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3) +#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4) +#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5) + +#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL) + +static struct gpio_led rb4xx_leds_gpio[] __initdata = { + { + .name = "rb4xx:yellow:user", + .gpio = RB4XX_GPIO_USER_LED, + .active_low = 0, + }, { + .name = "rb4xx:green:led1", + .gpio = RB4XX_GPIO_CPLD_LED1, + .active_low = 1, + }, { + .name = "rb4xx:green:led2", + .gpio = RB4XX_GPIO_CPLD_LED2, + .active_low = 1, + }, { + .name = "rb4xx:green:led3", + .gpio = RB4XX_GPIO_CPLD_LED3, + .active_low = 1, + }, { + .name = "rb4xx:green:led4", + .gpio = RB4XX_GPIO_CPLD_LED4, + .active_low = 1, + }, { + .name = "rb4xx:green:led5", + .gpio = RB4XX_GPIO_CPLD_LED5, + .active_low = 0, + }, +}; + +static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = { + { + .desc = "reset_switch", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL, + .gpio = RB4XX_GPIO_RESET_SWITCH, + .active_low = 1, + } +}; + +static struct platform_device rb4xx_nand_device = { + .name = "rb4xx-nand", + .id = -1, +}; + +static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = { + { + .slot = 17, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 18, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 18, + .pin = 2, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + } +}; + +static struct mtd_partition rb4xx_partitions[] = { + { + .name = "routerboot", + .offset = 0, + .size = 0x0b000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .offset = 0x0b000, + .size = 0x01000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = 0x0d000, + .size = 0x02000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .offset = 0x0f000, + .size = 0x01000, + } +}; + +static struct flash_platform_data rb4xx_flash_data = { + .type = "pm25lv512", + .parts = rb4xx_partitions, + .nr_parts = ARRAY_SIZE(rb4xx_partitions), +}; + +static struct rb4xx_cpld_platform_data rb4xx_cpld_data = { + .gpio_base = RB4XX_GPIO_CPLD_BASE, +}; + +static struct mmc_spi_platform_data rb4xx_mmc_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct spi_board_info rb4xx_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .platform_data = &rb4xx_flash_data, + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "spi-rb4xx-cpld", + .platform_data = &rb4xx_cpld_data, + } +}; + +static struct spi_board_info rb4xx_microsd_info[] = { + { + .bus_num = 0, + .chip_select = 2, + .max_speed_hz = 25000000, + .modalias = "mmc_spi", + .platform_data = &rb4xx_mmc_data, + } +}; + + +static struct resource rb4xx_spi_resources[] = { + { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rb4xx_spi_device = { + .name = "rb4xx-spi", + .id = -1, + .resource = rb4xx_spi_resources, + .num_resources = ARRAY_SIZE(rb4xx_spi_resources), +}; + +static void __init rb4xx_generic_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), + rb4xx_leds_gpio); + + ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rb4xx_gpio_keys), + rb4xx_gpio_keys); + + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); + platform_device_register(&rb4xx_spi_device); + platform_device_register(&rb4xx_nand_device); +} + +static void __init rb411_setup(void) +{ + rb4xx_generic_setup(); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, 0xfffffffc); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x00000003; + + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", + rb411_setup); + +static void __init rb411u_setup(void) +{ + rb411_setup(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", + rb411u_setup); + +#define RB433_LAN_PHYMASK BIT(0) +#define RB433_WAN_PHYMASK BIT(4) +#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK) + +static void __init rb433_setup(void) +{ + rb4xx_generic_setup(); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", + rb433_setup); + +static void __init rb433u_setup(void) +{ + rb433_setup(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", + rb433u_setup); + +#define RB450_LAN_PHYMASK BIT(0) +#define RB450_WAN_PHYMASK BIT(4) +#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK) + +static void __init rb450_generic_setup(int gige) +{ + rb4xx_generic_setup(); + ath79_register_mdio(0, ~RB450_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = (gige) ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = (gige) ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); +} + +static void __init rb450_setup(void) +{ + rb450_generic_setup(0); +} + +MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450", + rb450_setup); + +static void __init rb450g_setup(void) +{ + rb450_generic_setup(1); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); +} + +MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", + rb450g_setup); + +static void __init rb493_setup(void) +{ + rb4xx_generic_setup(); + + ath79_register_mdio(0, 0x3fffff00); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x00000001; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", + rb493_setup); + +#define RB493G_GPIO_MDIO_MDC 7 +#define RB493G_GPIO_MDIO_DATA 8 + +#define RB493G_MDIO_PHYMASK BIT(0) + +static struct mdio_gpio_platform_data rb493g_mdio_data = { + .mdc = RB493G_GPIO_MDIO_MDC, + .mdio = RB493G_GPIO_MDIO_DATA, + + .phy_mask = ~RB493G_MDIO_PHYMASK, +}; + +static struct platform_device rb493g_mdio_device = { + .name = "mdio-gpio", + .id = -1, + .dev = { + .platform_data = &rb493g_mdio_data, + }, +}; + +static void __init rb493g_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), + rb4xx_leds_gpio); + + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); + platform_device_register(&rb4xx_spi_device); + platform_device_register(&rb4xx_nand_device); + + ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev; + ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + platform_device_register(&rb493g_mdio_device); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G", + rb493g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c new file mode 100644 index 000000000..bee8bdf9c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c @@ -0,0 +1,337 @@ +/* + * MikroTik RouterBOARD 750/750GL support + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/export.h> +#include <linux/pci.h> +#include <linux/ath9k_platform.h> +#include <linux/platform_device.h> +#include <linux/phy.h> +#include <linux/ar8216_platform.h> +#include <linux/rle.h> +#include <linux/routerboot.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/irq.h> +#include <asm/mach-ath79/mach-rb750.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-usb.h" +#include "dev-eth.h" +#include "machtypes.h" +#include "routerboot.h" + +static struct rb750_led_data rb750_leds[] = { + { + .name = "rb750:green:act", + .mask = RB750_LED_ACT, + .active_low = 1, + }, { + .name = "rb750:green:port1", + .mask = RB750_LED_PORT5, + .active_low = 1, + }, { + .name = "rb750:green:port2", + .mask = RB750_LED_PORT4, + .active_low = 1, + }, { + .name = "rb750:green:port3", + .mask = RB750_LED_PORT3, + .active_low = 1, + }, { + .name = "rb750:green:port4", + .mask = RB750_LED_PORT2, + .active_low = 1, + }, { + .name = "rb750:green:port5", + .mask = RB750_LED_PORT1, + .active_low = 1, + } +}; + +static struct rb750_led_data rb750gr3_leds[] = { + { + .name = "rb750:green:act", + .mask = RB7XX_LED_ACT, + .active_low = 1, + }, +}; + +static struct rb750_led_platform_data rb750_leds_data; +static struct platform_device rb750_leds_device = { + .name = "leds-rb750", + .dev = { + .platform_data = &rb750_leds_data, + } +}; + +static struct rb7xx_nand_platform_data rb750_nand_data; +static struct platform_device rb750_nand_device = { + .name = "rb750-nand", + .id = -1, + .dev = { + .platform_data = &rb750_nand_data, + } +}; + +static void rb750_latch_change(u32 mask_clr, u32 mask_set) +{ + static DEFINE_SPINLOCK(lock); + static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; + static u32 latch_oe; + static u32 latch_clr; + unsigned long flags; + u32 t; + + spin_lock_irqsave(&lock, flags); + + if ((mask_clr & BIT(31)) != 0 && + (latch_set & RB750_LVC573_LE) == 0) { + goto unlock; + } + + latch_set = (latch_set | mask_set) & ~mask_clr; + latch_clr = (latch_clr | mask_clr) & ~mask_set; + + if (latch_oe == 0) + latch_oe = __raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_OE); + + if (likely(latch_set & RB750_LVC573_LE)) { + void __iomem *base = ath79_gpio_base; + + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= mask_clr | latch_oe | mask_set; + + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + __raw_writel(latch_clr, base + AR71XX_GPIO_REG_CLEAR); + __raw_writel(latch_set, base + AR71XX_GPIO_REG_SET); + } else if (mask_clr & RB750_LVC573_LE) { + void __iomem *base = ath79_gpio_base; + + latch_oe = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(RB750_LVC573_LE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + } + +unlock: + spin_unlock_irqrestore(&lock, flags); +} + +static void rb750_nand_enable_pins(void) +{ + rb750_latch_change(RB750_LVC573_LE, 0); + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_SPI_EN); +} + +static void rb750_nand_disable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, + AR724X_GPIO_FUNC_JTAG_DISABLE); + rb750_latch_change(0, RB750_LVC573_LE); +} + +static void __init rb750_setup(void) +{ + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + rb750_leds_data.num_leds = ARRAY_SIZE(rb750_leds); + rb750_leds_data.leds = rb750_leds; + rb750_leds_data.latch_change = rb750_latch_change; + platform_device_register(&rb750_leds_device); + + rb750_nand_data.nce_line = RB750_NAND_NCE; + rb750_nand_data.enable_pins = rb750_nand_enable_pins; + rb750_nand_data.disable_pins = rb750_nand_disable_pins; + rb750_nand_data.latch_change = rb750_latch_change; + platform_device_register(&rb750_nand_device); +} + +MIPS_MACHINE(ATH79_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", + rb750_setup); + +static struct ar8327_pad_cfg rb750gr3_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data rb750gr3_ar8327_data = { + .pad0_cfg = &rb750gr3_ar8327_pad0_cfg, + .cpuport_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_100, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info rb750g3_mdio_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb750gr3_ar8327_data, + }, +}; + +static void rb750gr3_nand_enable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_SPI_EN | + AR724X_GPIO_FUNC_SPI_CS_EN2); +} + +static void rb750gr3_nand_disable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN | + AR724X_GPIO_FUNC_SPI_CS_EN2, + AR724X_GPIO_FUNC_JTAG_DISABLE); +} + +static void rb750gr3_latch_change(u32 mask_clr, u32 mask_set) +{ + static DEFINE_SPINLOCK(lock); + static u32 latch_set = RB7XX_LED_ACT; + static u32 latch_clr; + void __iomem *base = ath79_gpio_base; + unsigned long flags; + u32 t; + + spin_lock_irqsave(&lock, flags); + + latch_set = (latch_set | mask_set) & ~mask_clr; + latch_clr = (latch_clr | mask_clr) & ~mask_set; + + mask_set = latch_set & (RB7XX_USB_POWERON | RB7XX_MONITOR); + mask_clr = latch_clr & (RB7XX_USB_POWERON | RB7XX_MONITOR); + + if ((latch_set ^ RB7XX_LED_ACT) & RB7XX_LED_ACT) { + /* enable output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= RB7XX_LED_ACT; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + + mask_clr |= RB7XX_LED_ACT; + } else { + /* disable output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t &= ~RB7XX_LED_ACT; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + } + + __raw_writel(mask_set, base + AR71XX_GPIO_REG_SET); + __raw_writel(mask_clr, base + AR71XX_GPIO_REG_CLEAR); + + spin_unlock_irqrestore(&lock, flags); +} + +static void __init rb750gr3_setup(void) +{ + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(rb750g3_mdio_info, + ARRAY_SIZE(rb750g3_mdio_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + rb750_leds_data.num_leds = ARRAY_SIZE(rb750gr3_leds); + rb750_leds_data.leds = rb750gr3_leds; + rb750_leds_data.latch_change = rb750gr3_latch_change; + platform_device_register(&rb750_leds_device); + + rb750_nand_data.nce_line = RB7XX_NAND_NCE; + rb750_nand_data.enable_pins = rb750gr3_nand_enable_pins; + rb750_nand_data.disable_pins = rb750gr3_nand_disable_pins; + rb750_nand_data.latch_change = rb750gr3_latch_change; + platform_device_register(&rb750_nand_device); +} + +MIPS_MACHINE(ATH79_MACH_RB_750G_R3, "750Gr3", "MikroTik RouterBOARD 750GL", + rb750gr3_setup); + +#define RB751_HARDCONFIG 0x1f00b000 +#define RB751_HARDCONFIG_SIZE 0x1000 +#define RB751_MAC_ADDRESS_OFFSET 0xE80 + +static void __init rb751_wlan_setup(void) +{ + u8 *hardconfig = (u8 *) KSEG1ADDR(RB751_HARDCONFIG); + struct ath9k_platform_data *wmac_data; + u16 tag_len; + u8 *tag; + int err; + + wmac_data = ap9x_pci_get_wmac_data(0); + if (!wmac_data) { + pr_err("rb75x: unable to get address of wlan data\n"); + return; + } + + ap9x_pci_setup_wmac_led_pin(0, 9); + + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE, + RB_ID_WLAN_DATA, &tag, &tag_len); + if (err) { + pr_err("rb75x: no calibration data found\n"); + return; + } + + err = rle_decode(tag, tag_len, (unsigned char *) wmac_data->eeprom_data, + sizeof(wmac_data->eeprom_data), NULL, NULL); + if (err) { + pr_err("rb75x: unable to decode wlan eeprom data\n"); + return; + } + + ap91_pci_init(NULL, hardconfig + RB751_MAC_ADDRESS_OFFSET); +} + +static void __init rb751_setup(void) +{ + rb750_setup(); + ath79_register_usb(); + rb751_wlan_setup(); +} + +MIPS_MACHINE(ATH79_MACH_RB_751, "751", "MikroTik RouterBOARD 751", + rb751_setup); + +static void __init rb751g_setup(void) +{ + rb750gr3_setup(); + ath79_register_usb(); + rb751_wlan_setup(); +} + +MIPS_MACHINE(ATH79_MACH_RB_751G, "751g", "MikroTik RouterBOARD 751G", + rb751g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c new file mode 100644 index 000000000..28d9de4f3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c @@ -0,0 +1,100 @@ +/* + * Redwave RW2458N support + * + * Copyright (C) 2011-2012 Cezary Jackiewicz <cezary@eko.one.pl> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define RW2458N_GPIO_LED_D3 1 +#define RW2458N_GPIO_LED_D4 0 +#define RW2458N_GPIO_LED_D5 11 +#define RW2458N_GPIO_LED_D6 7 +#define RW2458N_GPIO_BTN_RESET 12 + +#define RW2458N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RW2458N_KEYS_DEBOUNCE_INTERVAL (3 * RW2458N_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button rw2458n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RW2458N_KEYS_DEBOUNCE_INTERVAL, + .gpio = RW2458N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define RW2458N_WAN_PHYMASK BIT(4) + +static struct gpio_led rw2458n_leds_gpio[] __initdata = { + { + .name = "rw2458n:green:d3", + .gpio = RW2458N_GPIO_LED_D3, + .active_low = 1, + }, { + .name = "rw2458n:green:d4", + .gpio = RW2458N_GPIO_LED_D4, + .active_low = 1, + }, { + .name = "rw2458n:green:d5", + .gpio = RW2458N_GPIO_LED_D5, + .active_low = 1, + }, { + .name = "rw2458n:green:d6", + .gpio = RW2458N_GPIO_LED_D6, + .active_low = 1, + } +}; + +static const char *rw2458n_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data rw2458n_flash_data = { + .part_probes = rw2458n_part_probes, +}; + +static void __init rw2458n_setup(void) +{ + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&rw2458n_flash_data); + + ath79_register_mdio(0, ~RW2458N_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rw2458n_leds_gpio), + rw2458n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, RW2458N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rw2458n_gpio_keys), + rw2458n_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RW2458N, "RW2458N", "Redwave RW2458N", + rw2458n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c new file mode 100644 index 000000000..b76d4a7a0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c @@ -0,0 +1,109 @@ +/* + * TrendNET TEW-632BRP board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define TEW_632BRP_GPIO_LED_STATUS 1 +#define TEW_632BRP_GPIO_LED_WPS 3 +#define TEW_632BRP_GPIO_LED_WLAN 6 +#define TEW_632BRP_GPIO_BTN_WPS 12 +#define TEW_632BRP_GPIO_BTN_RESET 21 + +#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL) + +#define TEW_632BRP_CONFIG_ADDR 0x1f020000 +#define TEW_632BRP_CONFIG_SIZE 0x10000 + +static struct gpio_led tew_632brp_leds_gpio[] __initdata = { + { + .name = "tew-632brp:green:status", + .gpio = TEW_632BRP_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "tew-632brp:blue:wps", + .gpio = TEW_632BRP_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "tew-632brp:green:wlan", + .gpio = TEW_632BRP_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_632BRP_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_632BRP_GPIO_BTN_WPS, + } +}; + +#define TEW_632BRP_LAN_PHYMASK BIT(0) +#define TEW_632BRP_WAN_PHYMASK BIT(4) +#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ + TEW_632BRP_WAN_PHYMASK)) + +static void __init tew_632brp_setup(void) +{ + const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + u8 *wlan_mac = NULL; + + if (ath79_nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, + "lan_mac=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + wlan_mac = mac; + } + + ath79_register_mdio(0, TEW_632BRP_MDIO_MASK); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), + tew_632brp_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_632brp_gpio_keys), + tew_632brp_gpio_keys); + + ath79_register_wmac(eeprom, wlan_mac); +} + +MIPS_MACHINE(ATH79_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", + tew_632brp_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c new file mode 100644 index 000000000..207384f99 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c @@ -0,0 +1,210 @@ +/* + * TRENDnet TEW-673GRU board support + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/rtl8366.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TEW673GRU_GPIO_LCD_SCK 0 +#define TEW673GRU_GPIO_LCD_MOSI 1 +#define TEW673GRU_GPIO_LCD_MISO 2 +#define TEW673GRU_GPIO_LCD_CS 6 + +#define TEW673GRU_GPIO_LED_WPS 9 + +#define TEW673GRU_GPIO_BTN_RESET 3 +#define TEW673GRU_GPIO_BTN_WPS 8 + +#define TEW673GRU_GPIO_RTL8366_SDA 5 +#define TEW673GRU_GPIO_RTL8366_SCK 7 + +#define TEW673GRU_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW673GRU_KEYS_DEBOUNCE_INTERVAL (3 * TEW673GRU_KEYS_POLL_INTERVAL) + +#define TEW673GRU_CAL0_OFFSET 0x1000 +#define TEW673GRU_CAL1_OFFSET 0x5000 +#define TEW673GRU_MAC0_OFFSET 0xffa0 +#define TEW673GRU_MAC1_OFFSET 0xffb4 + +#define TEW673GRU_CAL_LOCATION_0 0x1f660000 +#define TEW673GRU_CAL_LOCATION_1 0x1f7f0000 + +static struct gpio_led tew673gru_leds_gpio[] __initdata = { + { + .name = "trendnet:blue:wps", + .gpio = TEW673GRU_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button tew673gru_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW673GRU_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW673GRU_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_initval tew673gru_rtl8366s_initvals[] = { + { .reg = 0x06, .val = 0x0108 }, +}; + +static struct rtl8366_platform_data tew673gru_rtl8366s_data = { + .gpio_sda = TEW673GRU_GPIO_RTL8366_SDA, + .gpio_sck = TEW673GRU_GPIO_RTL8366_SCK, + .num_initvals = ARRAY_SIZE(tew673gru_rtl8366s_initvals), + .initvals = tew673gru_rtl8366s_initvals, +}; + +static struct platform_device tew673gru_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tew673gru_rtl8366s_data, + } +}; + +static struct spi_board_info tew673gru_spi_info[] = { + { + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 400000, + .modalias = "spidev", + .mode = SPI_MODE_2, + .controller_data = (void *) TEW673GRU_GPIO_LCD_CS, + }, +}; + +static struct spi_gpio_platform_data tew673gru_spi_data = { + .sck = TEW673GRU_GPIO_LCD_SCK, + .miso = TEW673GRU_GPIO_LCD_MISO, + .mosi = TEW673GRU_GPIO_LCD_MOSI, + .num_chipselect = 1, +}; + +static struct platform_device tew673gru_spi_device = { + .name = "spi_gpio", + .id = 1, + .dev = { + .platform_data = &tew673gru_spi_data, + }, +}; + +static void tew673gru_read_ascii_mac(u8 *dest, u8 *src) +{ + int ret; + + ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &dest[0], &dest[1], &dest[2], + &dest[3], &dest[4], &dest[5]); + + if (ret != ETH_ALEN) + memset(dest, 0, ETH_ALEN); +} + +static bool __init tew673gru_is_caldata_valid(u8 *p) +{ + u16 *magic0, *magic1; + + magic0 = (u16 *)(p + TEW673GRU_CAL0_OFFSET); + magic1 = (u16 *)(p + TEW673GRU_CAL1_OFFSET); + + return (*magic0 == 0xa55a && *magic1 == 0xa55a); +} + +static void __init tew673gru_wlan_init(void) +{ + u8 mac1[ETH_ALEN], mac2[ETH_ALEN]; + u8 *caldata; + + caldata = (u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_0); + if (!tew673gru_is_caldata_valid(caldata)) { + caldata = (u8 *)KSEG1ADDR(TEW673GRU_CAL_LOCATION_1); + if (!tew673gru_is_caldata_valid(caldata)) { + pr_err("no calibration data found\n"); + return; + } + } + + tew673gru_read_ascii_mac(mac1, caldata + TEW673GRU_MAC0_OFFSET); + tew673gru_read_ascii_mac(mac2, caldata + TEW673GRU_MAC1_OFFSET); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(caldata + TEW673GRU_CAL0_OFFSET, mac1, + caldata + TEW673GRU_CAL1_OFFSET, mac2); +} + +static void __init tew673gru_setup(void) +{ + tew673gru_wlan_init(); + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x11110000; + + ath79_eth1_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + ath79_eth1_pll_data.pll_1000 = 0x11110000; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew673gru_leds_gpio), + tew673gru_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TEW673GRU_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew673gru_gpio_keys), + tew673gru_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&tew673gru_rtl8366s_device); + + spi_register_board_info(tew673gru_spi_info, + ARRAY_SIZE(tew673gru_spi_info)); + platform_device_register(&tew673gru_spi_device); +} + +MIPS_MACHINE(ATH79_MACH_TEW_673GRU, "TEW-673GRU", "TRENDnet TEW-673GRU", + tew673gru_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c new file mode 100644 index 000000000..b0bc51bfe --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c @@ -0,0 +1,163 @@ +/* + * TRENDnet TEW-712BR board support + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TEW_712BR_GPIO_BTN_WPS 11 +#define TEW_712BR_GPIO_BTN_RESET 12 + +#define TEW_712BR_GPIO_LED_LAN1 13 +#define TEW_712BR_GPIO_LED_LAN2 14 +#define TEW_712BR_GPIO_LED_LAN3 15 +#define TEW_712BR_GPIO_LED_LAN4 16 +#define TEW_712BR_GPIO_LED_POWER_GREEN 20 +#define TEW_712BR_GPIO_LED_POWER_ORANGE 27 +#define TEW_712BR_GPIO_LED_WAN_GREEN 17 +#define TEW_712BR_GPIO_LED_WAN_ORANGE 23 +#define TEW_712BR_GPIO_LED_WLAN 0 +#define TEW_712BR_GPIO_LED_WPS 26 + +#define TEW_712BR_GPIO_WAN_LED_ENABLE 1 + +#define TEW_712BR_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_712BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_712BR_KEYS_POLL_INTERVAL) + +#define TEW_712BR_ART_ADDRESS 0x1f010000 +#define TEW_712BR_CALDATA_OFFSET 0x1000 +#define TEW_712BR_LAN_MAC_ADDRESS 0x1f020004 +#define TEW_712BR_WAN_MAC_ADDRESS 0x1f020016 + +static struct gpio_led tew_712br_leds_gpio[] __initdata = { + { + .name = "trendnet:green:lan1", + .gpio = TEW_712BR_GPIO_LED_LAN1, + .active_low = 0, + }, { + .name = "trendnet:green:lan2", + .gpio = TEW_712BR_GPIO_LED_LAN2, + .active_low = 0, + }, { + .name = "trendnet:green:lan3", + .gpio = TEW_712BR_GPIO_LED_LAN3, + .active_low = 0, + }, { + .name = "trendnet:green:lan4", + .gpio = TEW_712BR_GPIO_LED_LAN4, + .active_low = 0, + }, { + .name = "trendnet:blue:wps", + .gpio = TEW_712BR_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "trendnet:green:power", + .gpio = TEW_712BR_GPIO_LED_POWER_GREEN, + .active_low = 0, + }, { + .name = "trendnet:orange:power", + .gpio = TEW_712BR_GPIO_LED_POWER_ORANGE, + .active_low = 0, + }, { + .name = "trendnet:green:wan", + .gpio = TEW_712BR_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "trendnet:orange:wan", + .gpio = TEW_712BR_GPIO_LED_WAN_ORANGE, + .active_low = 0, + }, { + .name = "trendnet:green:wlan", + .gpio = TEW_712BR_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tew_712br_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_712BR_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_712BR_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init tew_712br_read_ascii_mac(u8 *dest, unsigned int src_addr) +{ + int ret; + u8 *src = (u8 *)KSEG1ADDR(src_addr); + + ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &dest[0], &dest[1], &dest[2], + &dest[3], &dest[4], &dest[5]); + + if (ret != ETH_ALEN) + memset(dest, 0, ETH_ALEN); +} + +static void __init tew_712br_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TEW_712BR_ART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + gpio_request_one(TEW_712BR_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_712br_leds_gpio), + tew_712br_leds_gpio); + + ath79_register_gpio_keys_polled(1, TEW_712BR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_712br_gpio_keys), + tew_712br_gpio_keys); + + ath79_register_m25p80(NULL); + + tew_712br_read_ascii_mac(lan_mac, TEW_712BR_LAN_MAC_ADDRESS); + tew_712br_read_ascii_mac(wan_mac, TEW_712BR_WAN_MAC_ADDRESS); + + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + TEW_712BR_CALDATA_OFFSET, wan_mac); +} + +MIPS_MACHINE(ATH79_MACH_TEW_712BR, "TEW-712BR", + "TRENDnet TEW-712BR", tew_712br_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c new file mode 100644 index 000000000..6b2820711 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c @@ -0,0 +1,130 @@ +/* + * TP-LINK TL-MR11U/TL-MR3040 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR11U_GPIO_LED_3G 27 +#define TL_MR11U_GPIO_LED_WLAN 26 +#define TL_MR11U_GPIO_LED_LAN 17 + +#define TL_MR11U_GPIO_BTN_WPS 20 +#define TL_MR11U_GPIO_BTN_RESET 11 + +#define TL_MR11U_GPIO_USB_POWER 8 +#define TL_MR3040_GPIO_USB_POWER 18 + +#define TL_MR11U_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR11U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR11U_KEYS_POLL_INTERVAL) + +static const char *tl_mr11u_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr11u_flash_data = { + .part_probes = tl_mr11u_part_probes, +}; + +static struct gpio_led tl_mr11u_leds_gpio[] __initdata = { + { + .name = "tp-link:green:3g", + .gpio = TL_MR11U_GPIO_LED_3G, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_MR11U_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "tp-link:green:lan", + .gpio = TL_MR11U_GPIO_LED_LAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_mr11u_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_WPS, + .active_low = 0, + }, +}; + +static void __init common_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_setup_ar933x_phy4_switch(false, true); + + ath79_register_m25p80(&tl_mr11u_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio), + tl_mr11u_leds_gpio); + + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_mr11u_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr11u_gpio_keys), + tl_mr11u_gpio_keys); + ath79_set_usb_power_gpio(TL_MR11U_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR11U, "TL-MR11U", "TP-LINK TL-MR11U", + tl_mr11u_setup); + +static void __init tl_mr3040_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + 1, tl_mr11u_gpio_keys); + ath79_set_usb_power_gpio(TL_MR3040_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3040, "TL-MR3040", "TP-LINK TL-MR3040", + tl_mr3040_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c new file mode 100644 index 000000000..8f37d7a87 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c @@ -0,0 +1,125 @@ +/* + * TP-LINK TL-MR3020 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR3020_GPIO_LED_3G 27 +#define TL_MR3020_GPIO_LED_WLAN 0 +#define TL_MR3020_GPIO_LED_LAN 17 +#define TL_MR3020_GPIO_LED_WPS 26 + +#define TL_MR3020_GPIO_BTN_WPS 11 +#define TL_MR3020_GPIO_BTN_SW1 18 +#define TL_MR3020_GPIO_BTN_SW2 20 + +#define TL_MR3020_GPIO_USB_POWER 8 + +#define TL_MR3020_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR3020_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3020_KEYS_POLL_INTERVAL) + +static const char *tl_mr3020_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr3020_flash_data = { + .part_probes = tl_mr3020_part_probes, +}; + +static struct gpio_led tl_mr3020_leds_gpio[] __initdata = { + { + .name = "tp-link:green:3g", + .gpio = TL_MR3020_GPIO_LED_3G, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_MR3020_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "tp-link:green:lan", + .gpio = TL_MR3020_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "tp-link:green:wps", + .gpio = TL_MR3020_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_mr3020_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init tl_mr3020_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_setup_ar933x_phy4_switch(false, true); + + ath79_register_m25p80(&tl_mr3020_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio), + tl_mr3020_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3020_gpio_keys), + tl_mr3020_gpio_keys); + + ath79_set_usb_power_gpio(TL_MR3020_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_eth0_data.phy_mask = BIT(0); + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3020, "TL-MR3020", "TP-LINK TL-MR3020", + tl_mr3020_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c new file mode 100644 index 000000000..b35f09f8a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c @@ -0,0 +1,146 @@ +/* + * TP-LINK TL-MR3220/3420 board support + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TL_MR3X20_GPIO_LED_QSS 0 +#define TL_MR3X20_GPIO_LED_SYSTEM 1 +#define TL_MR3X20_GPIO_LED_3G 8 + +#define TL_MR3X20_GPIO_BTN_RESET 11 +#define TL_MR3X20_GPIO_BTN_QSS 12 + +#define TL_MR3X20_GPIO_USB_POWER 6 + +#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL) + +static const char *tl_mr3x20_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr3x20_flash_data = { + .part_probes = tl_mr3x20_part_probes, +}; + +static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_MR3X20_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_MR3X20_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:3g", + .gpio = TL_MR3X20_GPIO_LED_3G, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3X20_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3X20_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_ap99_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_mr3x20_flash_data); + + ath79_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3x20_gpio_keys), + tl_mr3x20_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + /* WAN port */ + ath79_register_eth(0); + + ap91_pci_init(ee, mac); +} + +static void __init tl_mr3x20_usb_setup(void) +{ + /* enable power for the USB port */ + ath79_set_usb_power_gpio(TL_MR3X20_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "USB power"); + ath79_register_usb(); +} + +static void __init tl_mr3220_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 1); + tl_mr3x20_usb_setup(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220", + tl_mr3220_setup); + +static void __init tl_mr3420_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); + tl_mr3x20_usb_setup(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420", + tl_mr3420_setup); + +static void __init tl_wr841n_v7_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio) - 1, + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V7, "TL-WR841N-v7", + "TP-LINK TL-WR841N/ND v7", tl_wr841n_v7_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c new file mode 100644 index 000000000..b4fb2a9f9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c @@ -0,0 +1,104 @@ +/* + * TP-LINK TL-WA901N/ND v2 board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2010 Pieter Hollants <pieter@hollants.com> + * Copyright (C) 2011 Jonathan Bennett <jbscience87@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA901ND_V2_GPIO_LED_QSS 4 +#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2 +#define TL_WA901ND_V2_GPIO_LED_WLAN 9 + +#define TL_WA901ND_V2_GPIO_BTN_RESET 3 +#define TL_WA901ND_V2_GPIO_BTN_QSS 7 + +#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \ + (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL) + +static const char *tl_wa901nd_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa901nd_v2_flash_data = { + .part_probes = tl_wa901nd_v2_part_probes, +}; + +static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA901ND_V2_GPIO_LED_QSS, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA901ND_V2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_V2_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_V2_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wa901nd_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x00001000; + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC | + AR71XX_RESET_GE0_PHY; + ath79_register_eth(0); + + ath79_register_m25p80(&tl_wa901nd_v2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio), + tl_wa901nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa901nd_v2_gpio_keys), + tl_wa901nd_v2_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V2, "TL-WA901ND-v2", + "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c new file mode 100644 index 000000000..2f4e0c047 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c @@ -0,0 +1,109 @@ +/* + * TP-LINK TL-WA901N/ND v1 board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2010 Pieter Hollants <pieter@hollants.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define TL_WA901ND_GPIO_LED_QSS 0 +#define TL_WA901ND_GPIO_LED_SYSTEM 1 +#define TL_WA901ND_GPIO_LED_LAN 13 + +#define TL_WA901ND_GPIO_BTN_RESET 11 +#define TL_WA901ND_GPIO_BTN_QSS 12 + +#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL) + +static const char *tl_wa901nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa901nd_flash_data = { + .part_probes = tl_wa901nd_part_probes, +}; + +static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA901ND_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA901ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA901ND_GPIO_LED_QSS, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wa901nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + /* + * ath79_eth0 would be the WAN port, but is not connected on + * the TL-WA901ND. ath79_eth1 connects to the internal switch chip, + * however we have a single LAN port only. + */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + + ath79_register_m25p80(&tl_wa901nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio), + tl_wa901nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa901nd_gpio_keys), + tl_wa901nd_gpio_keys); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND", + tl_wa901nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c new file mode 100644 index 000000000..331de5680 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c @@ -0,0 +1,204 @@ +/* + * TP-LINK TL-WDR4300 board support + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/pci.h> +#include <linux/phy.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/ath9k_platform.h> +#include <linux/ar8216_platform.h> + +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR4300_GPIO_LED_USB1 11 +#define WDR4300_GPIO_LED_USB2 12 +#define WDR4300_GPIO_LED_WLAN2G 13 +#define WDR4300_GPIO_LED_SYSTEM 14 +#define WDR4300_GPIO_LED_QSS 15 + +#define WDR4300_GPIO_BTN_WPS 16 +#define WDR4300_GPIO_BTN_RFKILL 17 + +#define WDR4300_GPIO_USB1_POWER 22 +#define WDR4300_GPIO_USB2_POWER 21 + +#define WDR4300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WDR4300_KEYS_POLL_INTERVAL) + +#define WDR4300_MAC0_OFFSET 0 +#define WDR4300_MAC1_OFFSET 6 +#define WDR4300_WMAC_CALDATA_OFFSET 0x1000 +#define WDR4300_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr4300_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr4300_flash_data = { + .part_probes = wdr4300_part_probes, +}; + +static struct gpio_led wdr4300_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:qss", + .gpio = WDR4300_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:blue:system", + .gpio = WDR4300_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:usb1", + .gpio = WDR4300_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "tp-link:green:usb2", + .gpio = WDR4300_GPIO_LED_USB2, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan2g", + .gpio = WDR4300_GPIO_LED_WLAN2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr4300_gpio_keys[] __initdata = { + { + .desc = "QSS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR4300_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR4300_GPIO_BTN_RFKILL, + }, +}; + +static struct ar8327_pad_cfg wdr4300_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wdr4300_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data wdr4300_ar8327_data = { + .pad0_cfg = &wdr4300_ar8327_pad0_cfg, + .cpuport_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wdr4300_ar8327_led_cfg, +}; + +static struct mdio_board_info wdr4300_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wdr4300_ar8327_data, + }, +}; + +static void __init wdr4300_gmac_setup(void) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); + t |= AR934X_ETH_CFG_RGMII_GMAC0; + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init wdr4300_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr4300_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio), + wdr4300_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr4300_gpio_keys), + wdr4300_gpio_keys); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 0); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac); + + wdr4300_gmac_setup(); + + mdiobus_register_board_info(wdr4300_mdio0_info, + ARRAY_SIZE(wdr4300_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_set_usb_power_gpio(WDR4300_GPIO_USB1_POWER, GPIOF_OUT_INIT_HIGH, + "USB1 power"); + ath79_set_usb_power_gpio(WDR4300_GPIO_USB2_POWER, GPIOF_OUT_INIT_HIGH, + "USB2 power"); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR4300, "TL-WDR4300", + "TP-LINK TL-WDR3600/4300/4310", + wdr4300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c new file mode 100644 index 000000000..ed5b2b0e6 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c @@ -0,0 +1,154 @@ +/* + * TP-LINK TL-WR1041 v2 board support + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2011-2012 Anan Huang <axishero@foxmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/pci.h> +#include <linux/phy.h> +#include <linux/platform_device.h> +#include <linux/ath9k_platform.h> +#include <linux/ar8216_platform.h> + +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1041NV2_GPIO_BTN_RESET 14 +#define TL_WR1041NV2_GPIO_LED_WPS 13 +#define TL_WR1041NV2_GPIO_LED_WLAN 11 + +#define TL_WR1041NV2_GPIO_LED_SYSTEM 12 + +#define TL_WR1041NV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1041NV2_KEYS_POLL_INTERVAL) + +#define TL_WR1041NV2_PCIE_CALDATA_OFFSET 0x5000 + +static const char *tl_wr1041nv2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr1041nv2_flash_data = { + .part_probes = tl_wr1041nv2_part_probes, +}; + +static struct gpio_led tl_wr1041nv2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR1041NV2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR1041NV2_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR1041NV2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr1041nv2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1041NV2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data db120_ar8327_data = { + .pad0_cfg = &db120_ar8327_pad0_cfg, + .cpuport_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info db120_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &db120_ar8327_data, + }, +}; + +static void __init db120_gmac_setup(void) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); + t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE; + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init tl_wr1041nv2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr1041nv2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1041nv2_leds_gpio), + tl_wr1041nv2_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR1041NV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1041nv2_gpio_keys), + tl_wr1041nv2_gpio_keys); + ath79_register_wmac(ee, mac); + + db120_gmac_setup(); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + mdiobus_register_board_info(db120_mdio0_info, + ARRAY_SIZE(db120_mdio0_info)); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1041N_V2, "TL-WR1041N-v2", + "TP-LINK TL-WR1041N v2", tl_wr1041nv2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c new file mode 100644 index 000000000..61aeb52d0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c @@ -0,0 +1,141 @@ +/* + * TP-LINK TL-WR1043N/ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/rtl8366.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1043ND_GPIO_LED_USB 1 +#define TL_WR1043ND_GPIO_LED_SYSTEM 2 +#define TL_WR1043ND_GPIO_LED_QSS 5 +#define TL_WR1043ND_GPIO_LED_WLAN 9 + +#define TL_WR1043ND_GPIO_BTN_RESET 3 +#define TL_WR1043ND_GPIO_BTN_QSS 7 + +#define TL_WR1043ND_GPIO_RTL8366_SDA 18 +#define TL_WR1043ND_GPIO_RTL8366_SCK 19 + +#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr1043nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr1043nd_flash_data = { + .part_probes = tl_wr1043nd_part_probes, +}; + +static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:usb", + .gpio = TL_WR1043ND_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR1043ND_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR1043ND_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void tl_wr1043nd_rtl8366rb_hw_reset(bool active) +{ + if (active) + ath79_device_reset_set(AR71XX_RESET_GE0_PHY); + else + ath79_device_reset_clear(AR71XX_RESET_GE0_PHY); +} + +static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = { + .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, + .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, + .hw_reset = tl_wr1043nd_rtl8366rb_hw_reset, +}; + +static struct platform_device tl_wr1043nd_rtl8366rb_device = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tl_wr1043nd_rtl8366rb_data, + } +}; + +static void __init tl_wr1043nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + tl_wr1043nd_rtl8366rb_hw_reset(true); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x1a000000; + + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_register_m25p80(&tl_wr1043nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), + tl_wr1043nd_leds_gpio); + + platform_device_register(&tl_wr1043nd_rtl8366rb_device); + + ath79_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1043nd_gpio_keys), + tl_wr1043nd_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", + tl_wr1043nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c new file mode 100644 index 000000000..8f6db5eda --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c @@ -0,0 +1,156 @@ +/* + * TP-LINK TL-WR2543N/ND board support + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/rtl8367.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TL_WR2543N_GPIO_LED_WPS 0 +#define TL_WR2543N_GPIO_LED_USB 8 + +/* The WLAN LEDs use GPIOs on the discrete AR9380 wmac */ +#define TL_WR2543N_GPIO_WMAC_LED_WLAN2G 0 +#define TL_WR2543N_GPIO_WMAC_LED_WLAN5G 1 + +#define TL_WR2543N_GPIO_BTN_RESET 11 +#define TL_WR2543N_GPIO_BTN_WPS 12 + +#define TL_WR2543N_GPIO_RTL8367_SDA 1 +#define TL_WR2543N_GPIO_RTL8367_SCK 6 + +#define TL_WR2543N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR2543N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR2543N_KEYS_POLL_INTERVAL) + +static const char *tl_wr2543n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr2543n_flash_data = { + .part_probes = tl_wr2543n_part_probes, +}; + +static struct gpio_led tl_wr2543n_leds_gpio[] __initdata = { + { + .name = "tp-link:green:usb", + .gpio = TL_WR2543N_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR2543N_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_led tl_wr2543n_wmac_leds_gpio[] = { + { + .name = "tp-link:green:wlan5g", + .gpio = TL_WR2543N_GPIO_WMAC_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr2543n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR2543N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR2543N_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8367_extif_config tl_wr2543n_rtl8367_extif0_cfg = { + .mode = RTL8367_EXTIF_MODE_RGMII, + .txdelay = 1, + .rxdelay = 0, + .ability = { + .force_mode = 1, + .txpause = 1, + .rxpause = 1, + .link = 1, + .duplex = 1, + .speed = RTL8367_PORT_SPEED_1000, + }, +}; + +static struct rtl8367_platform_data tl_wr2543n_rtl8367_data = { + .gpio_sda = TL_WR2543N_GPIO_RTL8367_SDA, + .gpio_sck = TL_WR2543N_GPIO_RTL8367_SCK, + .extif0_cfg = &tl_wr2543n_rtl8367_extif0_cfg, +}; + +static struct platform_device tl_wr2543n_rtl8367_device = { + .name = RTL8367_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tl_wr2543n_rtl8367_data, + } +}; + +static void __init tl_wr2543n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr2543n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr2543n_leds_gpio), + tl_wr2543n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR2543N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr2543n_gpio_keys), + tl_wr2543n_gpio_keys); + ath79_register_usb(); + + /* + * The ath9k driver uses this pin for its default led device, which is + * named ath9k-phy0, and reflects activity on either the 2 GHz or 5 GHz + * bands. This pin is connected to the WR2543's 2GHz WLAN LED. + */ + ap9x_pci_setup_wmac_led_pin(0, TL_WR2543N_GPIO_WMAC_LED_WLAN2G); + + /* + * We also have the driver set up an led device for the WR2543's + * separate 5 GHz WLAN LED in case the user wants it. + */ + ap9x_pci_setup_wmac_leds(0, tl_wr2543n_wmac_leds_gpio, + ARRAY_SIZE(tl_wr2543n_wmac_leds_gpio)); + ap91_pci_init(eeprom, mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_eth0_data.mii_bus_dev = &tl_wr2543n_rtl8367_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x1a000000; + + ath79_register_eth(0); + + platform_device_register(&tl_wr2543n_rtl8367_device); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR2543N, "TL-WR2543N", "TP-LINK TL-WR2543N/ND", + tl_wr2543n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c new file mode 100644 index 000000000..f60f96245 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c @@ -0,0 +1,85 @@ +/* + * TP-LINK TL-WR703N board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR703N_GPIO_LED_SYSTEM 27 +#define TL_WR703N_GPIO_BTN_RESET 11 + +#define TL_WR703N_GPIO_USB_POWER 8 + +#define TL_WR703N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR703N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR703N_KEYS_POLL_INTERVAL) + +static const char *tl_wr703n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr703n_flash_data = { + .part_probes = tl_wr703n_part_probes, +}; + +static struct gpio_led tl_wr703n_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_WR703N_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr703n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR703N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR703N_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init tl_wr703n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr703n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio), + tl_wr703n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr703n_gpio_keys), + tl_wr703n_gpio_keys); + + ath79_set_usb_power_gpio(TL_WR703N_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR703N, "TL-WR703N", "TP-LINK TL-WR703N v1", + tl_wr703n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c new file mode 100644 index 000000000..0d758913f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c @@ -0,0 +1,135 @@ +/* + * TP-LINK TL-WR741ND v4 board support + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR741NDV4_GPIO_BTN_RESET 11 +#define TL_WR741NDV4_GPIO_BTN_WPS 26 + +#define TL_WR741NDV4_GPIO_LED_WLAN 0 +#define TL_WR741NDV4_GPIO_LED_QSS 1 +#define TL_WR741NDV4_GPIO_LED_WAN 13 +#define TL_WR741NDV4_GPIO_LED_LAN1 14 +#define TL_WR741NDV4_GPIO_LED_LAN2 15 +#define TL_WR741NDV4_GPIO_LED_LAN3 16 +#define TL_WR741NDV4_GPIO_LED_LAN4 17 + +#define TL_WR741NDV4_GPIO_LED_SYSTEM 27 + +#define TL_WR741NDV4_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741NDV4_KEYS_POLL_INTERVAL) + +static const char *tl_wr741ndv4_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr741ndv4_flash_data = { + .part_probes = tl_wr741ndv4_part_probes, +}; + +static struct gpio_led tl_wr741ndv4_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR741NDV4_GPIO_LED_LAN1, + .active_low = 0, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR741NDV4_GPIO_LED_LAN2, + .active_low = 0, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR741NDV4_GPIO_LED_LAN3, + .active_low = 0, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR741NDV4_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR741NDV4_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR741NDV4_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR741NDV4_GPIO_LED_WAN, + .active_low = 0, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR741NDV4_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_wr741ndv4_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741NDV4_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741NDV4_GPIO_BTN_WPS, + .active_low = 0, + } +}; + +static void __init tl_wr741ndv4_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio), + tl_wr741ndv4_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr741ndv4_gpio_keys), + tl_wr741ndv4_gpio_keys); + + ath79_register_m25p80(&tl_wr741ndv4_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR741ND_V4, "TL-WR741ND-v4", + "TP-LINK TL-WR741ND v4", tl_wr741ndv4_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c new file mode 100644 index 000000000..5931654bb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c @@ -0,0 +1,130 @@ +/* + * TP-LINK TL-WR741ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define TL_WR741ND_GPIO_LED_QSS 0 +#define TL_WR741ND_GPIO_LED_SYSTEM 1 +#define TL_WR741ND_GPIO_LED_LAN1 13 +#define TL_WR741ND_GPIO_LED_LAN2 14 +#define TL_WR741ND_GPIO_LED_LAN3 15 +#define TL_WR741ND_GPIO_LED_LAN4 16 +#define TL_WR741ND_GPIO_LED_WAN 17 + +#define TL_WR741ND_GPIO_BTN_RESET 11 +#define TL_WR741ND_GPIO_BTN_QSS 12 + +#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr741nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr741nd_flash_data = { + .part_probes = tl_wr741nd_part_probes, +}; + +static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR741ND_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR741ND_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR741ND_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR741ND_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR741ND_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR741ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR741ND_GPIO_LED_WAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wr741nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr741nd_flash_data); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), + tl_wr741nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr741nd_gpio_keys), + tl_wr741nd_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap91_pci_init(ee, mac); +} +MIPS_MACHINE(ATH79_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", + tl_wr741nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c new file mode 100644 index 000000000..db4d1052a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c @@ -0,0 +1,159 @@ +/* + * TP-LINK TL-WR841N/ND v8 board support + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR841NV8_GPIO_LED_WLAN 13 +#define TL_WR841NV8_GPIO_LED_QSS 15 +#define TL_WR841NV8_GPIO_LED_WAN 18 +#define TL_WR841NV8_GPIO_LED_LAN1 19 +#define TL_WR841NV8_GPIO_LED_LAN2 20 +#define TL_WR841NV8_GPIO_LED_LAN3 21 +#define TL_WR841NV8_GPIO_LED_LAN4 12 +#define TL_WR841NV8_GPIO_LED_SYSTEM 14 + +#define TL_WR841NV8_GPIO_BTN_RESET 17 +#define TL_WR841NV8_GPIO_SW_RFKILL 16 + +#define TL_WR841NV8_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV8_KEYS_POLL_INTERVAL) + +static const char *tl_wr841n_v8_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr841n_v8_flash_data = { + .part_probes = tl_wr841n_v8_part_probes, +}; + +static struct gpio_led tl_wr841n_v8_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR841NV8_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR841NV8_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR841NV8_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR841NV8_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841NV8_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR841NV8_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR841NV8_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR841NV8_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr841n_v8_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static void __init tl_wr841n_v8_gmac_setup(void) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + t |= AR934X_ETH_CFG_SW_PHY_SWAP; + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init tl_wr841n_v8_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio), + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); + + ath79_register_m25p80(&tl_wr841n_v8_flash_data); + + tl_wr841n_v8_gmac_setup(); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V8, "TL-WR841N-v8", "TP-LINK TL-WR841N/ND v8", + tl_wr841n_v8_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c new file mode 100644 index 000000000..11f853f05 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c @@ -0,0 +1,140 @@ +/* + * TP-LINK TL-WR841N/ND v1 board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 +#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 +#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 + +#define TL_WR841ND_V1_GPIO_BTN_RESET 3 +#define TL_WR841ND_V1_GPIO_BTN_QSS 7 + +#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \ + (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL) + +static struct mtd_partition tl_wr841n_v1_partitions[] = { + { + .name = "redboot", + .offset = 0, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x020000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x160000, + .size = 0x280000, + }, { + .name = "config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x020000, + .size = 0x3c0000, + } +}; + +static struct flash_platform_data tl_wr841n_v1_flash_data = { + .parts = tl_wr841n_v1_partitions, + .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), +}; + +static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:red:qss", + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, + } +}; + +static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { + .port_names[0] = "wan", + .port_names[1] = "lan1", + .port_names[2] = "lan2", + .port_names[3] = "lan3", + .port_names[4] = "lan4", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data tl_wr841n_v1_dsa_data = { + .nr_chips = 1, + .chip = &tl_wr841n_v1_dsa_chip, +}; + +static void __init tl_wr841n_v1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev, + &tl_wr841n_v1_dsa_data); + + ath79_register_m25p80(&tl_wr841n_v1_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), + tl_wr841n_v1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v1_gpio_keys), + tl_wr841n_v1_gpio_keys); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", + tl_wr841n_v1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c new file mode 100644 index 000000000..1ddeec730 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c @@ -0,0 +1,121 @@ +/* + * TP-LINK TL-WR941ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR941ND_GPIO_LED_SYSTEM 2 +#define TL_WR941ND_GPIO_LED_QSS_RED 4 +#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 +#define TL_WR941ND_GPIO_LED_WLAN 9 + +#define TL_WR941ND_GPIO_BTN_RESET 3 +#define TL_WR941ND_GPIO_BTN_QSS 7 + +#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr941nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr941nd_flash_data = { + .part_probes = tl_wr941nd_part_probes, +}; + +static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR941ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:red:qss", + .gpio = TL_WR941ND_GPIO_LED_QSS_RED, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR941ND_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR941ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR941ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static struct dsa_chip_data tl_wr941nd_dsa_chip = { + .port_names[0] = "wan", + .port_names[1] = "lan1", + .port_names[2] = "lan2", + .port_names[3] = "lan3", + .port_names[4] = "lan4", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data tl_wr941nd_dsa_data = { + .nr_chips = 1, + .chip = &tl_wr941nd_dsa_chip, +}; + +static void __init tl_wr941nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev, + &tl_wr941nd_dsa_data); + + ath79_register_m25p80(&tl_wr941nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), + tl_wr941nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr941nd_gpio_keys), + tl_wr941nd_gpio_keys); + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", + tl_wr941nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c new file mode 100644 index 000000000..e49ac23fd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c @@ -0,0 +1,205 @@ +/* + * Ubiquiti RouterStation support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * Copyright (C) 2008 Ubiquiti <support@ubnt.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define UBNT_RS_GPIO_LED_RF 2 +#define UBNT_RS_GPIO_SW4 8 + +#define UBNT_LS_SR71_GPIO_LED_D25 0 +#define UBNT_LS_SR71_GPIO_LED_D26 1 +#define UBNT_LS_SR71_GPIO_LED_D24 2 +#define UBNT_LS_SR71_GPIO_LED_D23 4 +#define UBNT_LS_SR71_GPIO_LED_D22 5 +#define UBNT_LS_SR71_GPIO_LED_D27 6 +#define UBNT_LS_SR71_GPIO_LED_D28 7 + +#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */ +#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL) + +static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { + { + .name = "ubnt:green:rf", + .gpio = UBNT_RS_GPIO_LED_RF, + .active_low = 0, + } +}; + +static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { + { + .name = "ubnt:green:d22", + .gpio = UBNT_LS_SR71_GPIO_LED_D22, + .active_low = 0, + }, { + .name = "ubnt:green:d23", + .gpio = UBNT_LS_SR71_GPIO_LED_D23, + .active_low = 0, + }, { + .name = "ubnt:green:d24", + .gpio = UBNT_LS_SR71_GPIO_LED_D24, + .active_low = 0, + }, { + .name = "ubnt:red:d25", + .gpio = UBNT_LS_SR71_GPIO_LED_D25, + .active_low = 0, + }, { + .name = "ubnt:red:d26", + .gpio = UBNT_LS_SR71_GPIO_LED_D26, + .active_low = 0, + }, { + .name = "ubnt:green:d27", + .gpio = UBNT_LS_SR71_GPIO_LED_D27, + .active_low = 0, + }, { + .name = "ubnt:green:d28", + .gpio = UBNT_LS_SR71_GPIO_LED_D28, + .active_low = 0, + } +}; + +static struct gpio_keys_button ubnt_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, + .gpio = UBNT_RS_GPIO_SW4, + .active_low = 1, + } +}; + +static const char *ubnt_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data ubnt_flash_data = { + .part_probes = ubnt_part_probes, +}; + +static void __init ubnt_generic_setup(void) +{ + ath79_register_m25p80(&ubnt_flash_data); + + ath79_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_gpio_keys), + ubnt_gpio_keys); + ath79_register_pci(); +} + +#define UBNT_RS_WAN_PHYMASK BIT(20) +#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) + +static void __init ubnt_rs_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; + + /* + * There is Secondary MAC address duplicate problem with some + * UBNT HW batches. Do not increase Secondary MAC address by 1 + * but do workaround with 'Locally Administrated' bit. + */ + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), + ubnt_rs_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", + ubnt_rs_setup); + +#define UBNT_RSPRO_WAN_PHYMASK BIT(4) +#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +static void __init ubnt_rspro_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~(UBNT_RSPRO_WAN_PHYMASK | + UBNT_RSPRO_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; + + /* + * There is Secondary MAC address duplicate problem with some + * UBNT HW batches. Do not increase Secondary MAC address by 1 + * but do workaround with 'Locally Administrated' bit. + */ + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), + ubnt_rs_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", + ubnt_rspro_setup); + +static void __init ubnt_lsx_setup(void) +{ + ubnt_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); + +#define UBNT_LSSR71_PHY_MASK BIT(1) + +static void __init ubnt_lssr71_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~UBNT_LSSR71_PHY_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; + + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), + ubnt_ls_sr71_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", + ubnt_lssr71_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c new file mode 100644 index 000000000..48f49ad0f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c @@ -0,0 +1,155 @@ +/* + * Buffalo WHR-HP-G300N board support + * + * based on ... + * + * TP-LINK TL-WR741ND board support + * + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WHRHPG300N_GPIO_LED_SECURITY 0 +#define WHRHPG300N_GPIO_LED_DIAG 1 +#define WHRHPG300N_GPIO_LED_ROUTER 6 + +#define WHRHPG300N_GPIO_BTN_ROUTER_ON 7 +#define WHRHPG300N_GPIO_BTN_ROUTER_AUTO 8 +#define WHRHPG300N_GPIO_BTN_RESET 11 +#define WHRHPG300N_GPIO_BTN_AOSS 12 +#define WHRHPG300N_GPIO_LED_LAN1 13 +#define WHRHPG300N_GPIO_LED_LAN2 14 +#define WHRHPG300N_GPIO_LED_LAN3 15 +#define WHRHPG300N_GPIO_LED_LAN4 16 +#define WHRHPG300N_GPIO_LED_WAN 17 + +#define WHRHPG300N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WHRHPG300N_KEYS_DEBOUNCE_INTERVAL (3 * WHRHPG300N_KEYS_POLL_INTERVAL) + +#define WHRHPG300N_MAC_OFFSET 0x20c + +static struct gpio_led whrhpg300n_leds_gpio[] __initdata = { + { + .name = "buffalo:orange:security", + .gpio = WHRHPG300N_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "buffalo:red:diag", + .gpio = WHRHPG300N_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "buffalo:green:router", + .gpio = WHRHPG300N_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "buffalo:green:wan", + .gpio = WHRHPG300N_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "buffalo:green:lan1", + .gpio = WHRHPG300N_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "buffalo:green:lan2", + .gpio = WHRHPG300N_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "buffalo:green:lan3", + .gpio = WHRHPG300N_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "buffalo:green:lan4", + .gpio = WHRHPG300N_GPIO_LED_LAN4, + .active_low = 1, + } +}; + +static struct gpio_keys_button whrhpg300n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHRHPG300N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "aoss/wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .gpio = WHRHPG300N_GPIO_BTN_AOSS, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_2, + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_ON, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_3, + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_AUTO, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + } +}; + +static void __init whrhpg300n_setup(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac = (u8 *) KSEG1ADDR(ee + WHRHPG300N_MAC_OFFSET); + + ath79_register_m25p80(NULL); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(whrhpg300n_leds_gpio), + whrhpg300n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WHRHPG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(whrhpg300n_gpio_keys), + whrhpg300n_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + /* WAN port */ + ath79_register_eth(0); + + ap9x_pci_setup_wmac_led_pin(0, 1); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_WHR_HP_G300N, "WHR-HP-G300N", "Buffalo WHR-HP-G300N", + whrhpg300n_setup); + +MIPS_MACHINE(ATH79_MACH_WHR_G301N, "WHR-G301N", "Buffalo WHR-G301N", + whrhpg300n_setup); + +MIPS_MACHINE(ATH79_MACH_WHR_HP_GN, "WHR-HP-GN", "Buffalo WHR-HP-GN", + whrhpg300n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c new file mode 100644 index 000000000..11006fd1b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c @@ -0,0 +1,114 @@ +/* + * Buffalo WLAE-AG300N board support + */ + +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WLAEAG300N_MAC_OFFSET 0x20c +#define WLAEAG300N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WLAEAG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLAEAG300N_KEYS_POLL_INTERVAL) + + +static struct gpio_led wlaeag300n_leds_gpio[] __initdata = { + /* + * Note: Writing 1 into GPIO 13 will power down the device. + */ + { + .name = "buffalo:green:wireless", + .gpio = 14, + .active_low = 1, + }, { + .name = "buffalo:red:wireless", + .gpio = 15, + .active_low = 1, + }, { + .name = "buffalo:green:status", + .gpio = 16, + .active_low = 1, + }, { + .name = "buffalo:red:status", + .gpio = 17, + .active_low = 1, + } +}; + + +static struct gpio_keys_button wlaeag300n_gpio_keys[] __initdata = { + { + .desc = "function", + .type = EV_KEY, + .code = KEY_MODE, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 0, + .active_low = 1, + }, { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "power", + .type = EV_KEY, + .code = KEY_POWER, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 1, + } +}; + +static void __init wlaeag300n_setup(void) +{ + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac1 = eeprom1 + WLAEAG300N_MAC_OFFSET; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 1); + + ath79_register_mdio(0, ~(BIT(0) | BIT(4))); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlaeag300n_leds_gpio), + wlaeag300n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WLAEAG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wlaeag300n_gpio_keys), + wlaeag300n_gpio_keys); + + ath79_register_m25p80(NULL); + + ap91_pci_init(eeprom1, mac1); +} + +MIPS_MACHINE(ATH79_MACH_WLAE_AG300N, "WLAE-AG300N", + "Buffalo WLAE-AG300N", wlaeag300n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c new file mode 100644 index 000000000..fccf1c663 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c @@ -0,0 +1,172 @@ +/* + * Netgear WNDR3700 board support + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/delay.h> +#include <linux/rtl8366.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WNDR3700_GPIO_LED_WPS_ORANGE 0 +#define WNDR3700_GPIO_LED_POWER_ORANGE 1 +#define WNDR3700_GPIO_LED_POWER_GREEN 2 +#define WNDR3700_GPIO_LED_WPS_GREEN 4 +#define WNDR3700_GPIO_LED_WAN_GREEN 6 + +#define WNDR3700_GPIO_BTN_WPS 3 +#define WNDR3700_GPIO_BTN_RESET 8 +#define WNDR3700_GPIO_BTN_WIFI 11 + +#define WNDR3700_GPIO_RTL8366_SDA 5 +#define WNDR3700_GPIO_RTL8366_SCK 7 + +#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL) + +#define WNDR3700_ETH0_MAC_OFFSET 0 +#define WNDR3700_ETH1_MAC_OFFSET 0x6 + +#define WNDR3700_WMAC0_MAC_OFFSET 0 +#define WNDR3700_WMAC1_MAC_OFFSET 0xc +#define WNDR3700_CALDATA0_OFFSET 0x1000 +#define WNDR3700_CALDATA1_OFFSET 0x5000 + +static struct gpio_led wndr3700_leds_gpio[] __initdata = { + { + .name = "wndr3700:green:power", + .gpio = WNDR3700_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "wndr3700:orange:power", + .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "wndr3700:green:wps", + .gpio = WNDR3700_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, { + .name = "wndr3700:orange:wps", + .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, + .active_low = 1, + }, { + .name = "wndr3700:green:wan", + .gpio = WNDR3700_GPIO_LED_WAN_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_WIFI, + .active_low = 1, + } +}; + +static struct rtl8366_platform_data wndr3700_rtl8366s_data = { + .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, + .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, +}; + +static struct platform_device wndr3700_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wndr3700_rtl8366s_data, + } +}; + +static void __init wndr3700_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* + * The eth0 and wmac0 interfaces share the same MAC address which + * can lead to problems if operated unbridged. Set the locally + * administered bit on the eth0 MAC to make it unique. + */ + ath79_init_local_mac(ath79_eth0_data.mac_addr, + art + WNDR3700_ETH0_MAC_OFFSET); + ath79_eth0_pll_data.pll_1000 = 0x11110000; + ath79_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + WNDR3700_ETH1_MAC_OFFSET, 0); + ath79_eth1_pll_data.pll_1000 = 0x11110000; + ath79_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), + wndr3700_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndr3700_gpio_keys), + wndr3700_gpio_keys); + + platform_device_register(&wndr3700_rtl8366s_device); + platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */ + ap9x_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6)); + + /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */ + ap9x_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6)); + + ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, + art + WNDR3700_WMAC0_MAC_OFFSET, + art + WNDR3700_CALDATA1_OFFSET, + art + WNDR3700_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_WNDR3700, "WNDR3700", + "NETGEAR WNDR3700/WNDR3800/WNDRMAC", + wndr3700_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c new file mode 100644 index 000000000..bd86db386 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c @@ -0,0 +1,145 @@ +/* + * NETGEAR WNR2000 board support + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * Copyright (C) 2008-2009 Andy Boyett <agb@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WNR2000_GPIO_LED_PWR_GREEN 14 +#define WNR2000_GPIO_LED_PWR_AMBER 7 +#define WNR2000_GPIO_LED_WPS 4 +#define WNR2000_GPIO_LED_WLAN 6 +#define WNR2000_GPIO_BTN_RESET 21 +#define WNR2000_GPIO_BTN_WPS 8 + +#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL) + +static struct mtd_partition wnr2000_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x040000, + .size = 0x010000, + }, { + .name = "rootfs", + .offset = 0x050000, + .size = 0x240000, + }, { + .name = "user-config", + .offset = 0x290000, + .size = 0x010000, + }, { + .name = "uImage", + .offset = 0x2a0000, + .size = 0x120000, + }, { + .name = "language_table", + .offset = 0x3c0000, + .size = 0x020000, + }, { + .name = "rootfs_checksum", + .offset = 0x3e0000, + .size = 0x010000, + }, { + .name = "art", + .offset = 0x3f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wnr2000_flash_data = { + .parts = wnr2000_partitions, + .nr_parts = ARRAY_SIZE(wnr2000_partitions), +}; + +static struct gpio_led wnr2000_leds_gpio[] __initdata = { + { + .name = "wnr2000:green:power", + .gpio = WNR2000_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "wnr2000:amber:power", + .gpio = WNR2000_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, { + .name = "wnr2000:green:wps", + .gpio = WNR2000_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "wnr2000:blue:wlan", + .gpio = WNR2000_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000_GPIO_BTN_WPS, + } +}; + +static void __init wnr2000_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wnr2000_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), + wnr2000_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000_gpio_keys), + wnr2000_gpio_keys); + + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c new file mode 100644 index 000000000..148cd7c7f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c @@ -0,0 +1,107 @@ +/* + * Compex WP543/WPJ543 board support + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define WP543_GPIO_SW6 2 +#define WP543_GPIO_LED_1 3 +#define WP543_GPIO_LED_2 4 +#define WP543_GPIO_LED_WLAN 5 +#define WP543_GPIO_LED_CONN 6 +#define WP543_GPIO_LED_DIAG 7 +#define WP543_GPIO_SW4 8 + +#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL) + +static struct gpio_led wp543_leds_gpio[] __initdata = { + { + .name = "wp543:green:led1", + .gpio = WP543_GPIO_LED_1, + .active_low = 1, + }, { + .name = "wp543:green:led2", + .gpio = WP543_GPIO_LED_2, + .active_low = 1, + }, { + .name = "wp543:green:wlan", + .gpio = WP543_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "wp543:green:conn", + .gpio = WP543_GPIO_LED_CONN, + .active_low = 1, + }, { + .name = "wp543:green:diag", + .gpio = WP543_GPIO_LED_DIAG, + .active_low = 1, + } +}; + +static struct gpio_keys_button wp543_gpio_keys[] __initdata = { + { + .desc = "sw6", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, + .gpio = WP543_GPIO_SW6, + }, { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, + .gpio = WP543_GPIO_SW4, + } +}; + +static const char *wp543_part_probes[] = { + "MyLoader", + NULL, +}; + +static struct flash_platform_data wp543_flash_data = { + .part_probes = wp543_part_probes, +}; + +static void __init wp543_setup(void) +{ + ath79_register_m25p80(&wp543_flash_data); + + ath79_register_mdio(0, 0xfffffff0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x0f; + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC | + AR71XX_RESET_GE0_PHY; + ath79_register_eth(0); + + ath79_register_usb(); + ath79_register_pci(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), + wp543_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wp543_gpio_keys), + wp543_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WP543, "WP543", "Compex WP543", wp543_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c new file mode 100644 index 000000000..114d6233c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c @@ -0,0 +1,96 @@ +/* + * Compex WPE72 board support + * + * Copyright (C) 2012 Johnathan Boyce<jon.boyce@globalreach.eu.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include<asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define WPE72_GPIO_RESET 12 +#define WPE72_GPIO_LED_DIAG 13 +#define WPE72_GPIO_LED_1 14 +#define WPE72_GPIO_LED_2 15 +#define WPE72_GPIO_LED_3 16 +#define WPE72_GPIO_LED_4 17 + +#define WPE72_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPE72_KEYS_DEBOUNCE_INTERVAL (3 * WPE72_KEYS_POLL_INTERVAL) + +static struct gpio_led wpe72_leds_gpio[] __initdata = { + { + .name = "wpe72:green:led1", + .gpio = WPE72_GPIO_LED_1, + .active_low = 1, + }, { + .name = "wpe72:green:led2", + .gpio = WPE72_GPIO_LED_2, + .active_low = 1, + }, { + .name = "wpe72:green:led3", + .gpio = WPE72_GPIO_LED_3, + .active_low = 1, + }, { + .name = "wpe72:green:led4", + .gpio = WPE72_GPIO_LED_4, + .active_low = 1, + }, { + .name = "wpe72:green:diag", + .gpio = WPE72_GPIO_LED_DIAG, + .active_low = 1, + } +}; + +static struct gpio_keys_button wpe72_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPE72_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPE72_GPIO_RESET, + } +}; + +static const char *wpe72_part_probes[] = { + "MyLoader", + NULL, +}; + +static struct flash_platform_data wpe72_flash_data = { + .part_probes = wpe72_part_probes, +}; + +static void __init wpe72_setup(void) +{ + ath79_register_m25p80(&wpe72_flash_data); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_pci(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpe72_leds_gpio), + wpe72_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WPE72_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpe72_gpio_keys), + wpe72_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WPE72, "WPE72", "Compex WPE72", wpe72_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c new file mode 100644 index 000000000..21aefe00a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c @@ -0,0 +1,126 @@ +/* + * Linksys WRT160NL board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "nvram.h" +#include "machtypes.h" + +#define WRT160NL_GPIO_LED_POWER 14 +#define WRT160NL_GPIO_LED_WPS_AMBER 9 +#define WRT160NL_GPIO_LED_WPS_BLUE 8 +#define WRT160NL_GPIO_LED_WLAN 6 + +#define WRT160NL_GPIO_BTN_WPS 7 +#define WRT160NL_GPIO_BTN_RESET 21 + +#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL) + +#define WRT160NL_NVRAM_ADDR 0x1f7e0000 +#define WRT160NL_NVRAM_SIZE 0x10000 + +static const char *wrt160nl_part_probes[] = { + "wrt160nl", + NULL, +}; + +static struct flash_platform_data wrt160nl_flash_data = { + .part_probes = wrt160nl_part_probes, +}; + +static struct gpio_led wrt160nl_leds_gpio[] __initdata = { + { + .name = "wrt160nl:blue:power", + .gpio = WRT160NL_GPIO_LED_POWER, + .active_low = 1, + .default_trigger = "default-on", + }, { + .name = "wrt160nl:amber:wps", + .gpio = WRT160NL_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, { + .name = "wrt160nl:blue:wps", + .gpio = WRT160NL_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, { + .name = "wrt160nl:blue:wlan", + .gpio = WRT160NL_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRT160NL_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRT160NL_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init wrt160nl_setup(void) +{ + const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, + "lan_hwaddr=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + } + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = 0x01; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wrt160nl_flash_data); + + ath79_register_usb(); + + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, + "wl0_hwaddr=", mac) == 0) + ath79_register_wmac(eeprom, mac); + else + ath79_register_wmac(eeprom, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), + wrt160nl_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrt160nl_gpio_keys), + wrt160nl_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", + wrt160nl_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c new file mode 100644 index 000000000..6c4c1cb0d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c @@ -0,0 +1,161 @@ +/* + * Linksys WRT400N board support + * + * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WRT400N_GPIO_LED_POWER 1 +#define WRT400N_GPIO_LED_WPS_BLUE 4 +#define WRT400N_GPIO_LED_WPS_AMBER 5 +#define WRT400N_GPIO_LED_WLAN 6 + +#define WRT400N_GPIO_BTN_RESET 8 +#define WRT400N_GPIO_BTN_WLSEC 3 + +#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) + +#define WRT400N_MAC_ADDR_OFFSET 0x120c +#define WRT400N_CALDATA0_OFFSET 0x1000 +#define WRT400N_CALDATA1_OFFSET 0x5000 + +static struct mtd_partition wrt400n_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = 0x030000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "env", + .offset = 0x030000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "linux", + .offset = 0x040000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x180000, + .size = 0x630000, + }, { + .name = "nvram", + .offset = 0x7b0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "factory", + .offset = 0x7c0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "language", + .offset = 0x7d0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "caldata", + .offset = 0x7f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x040000, + .size = 0x770000, + } +}; + +static struct flash_platform_data wrt400n_flash_data = { + .parts = wrt400n_partitions, + .nr_parts = ARRAY_SIZE(wrt400n_partitions), +}; + +static struct gpio_led wrt400n_leds_gpio[] __initdata = { + { + .name = "wrt400n:blue:wps", + .gpio = WRT400N_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, { + .name = "wrt400n:amber:wps", + .gpio = WRT400N_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, { + .name = "wrt400n:blue:wlan", + .gpio = WRT400N_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "wrt400n:blue:power", + .gpio = WRT400N_GPIO_LED_POWER, + .active_low = 0, + .default_trigger = "default-on", + } +}; + +static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, + .gpio = WRT400N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wlsec", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, + .gpio = WRT400N_GPIO_BTN_WLSEC, + .active_low = 1, + } +}; + +static void __init wrt400n_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wrt400n_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), + wrt400n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrt400n_gpio_keys), + wrt400n_gpio_keys); + + ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, + art + WRT400N_CALDATA1_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c new file mode 100644 index 000000000..868514c95 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c @@ -0,0 +1,213 @@ +/* + * Buffalo WZR-HP-AG300H board support + * + * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPAG300H_MAC_OFFSET 0x20c +#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpag300h_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x0060000, + .size = 0x0100000, + }, { + .name = "rootfs", + .offset = 0x0160000, + .size = 0x1e90000, + }, { + .name = "user_property", + .offset = 0x1ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f90000, + } +}; + +static struct flash_platform_data wzrhpag300h_flash_data = { + .parts = wzrhpag300h_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpag300h_flash_partitions), +}; + +static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 1, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpag300h_wmac0_leds_gpio[] = { + { + .name = "buffalo:amber:band2g", + .gpio = 1, + .active_low = 1, + }, + { + .name = "buffalo:green:usb", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:green:band2g", + .gpio = 5, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpag300h_wmac1_leds_gpio[] = { + { + .name = "buffalo:green:band5g", + .gpio = 1, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine", + .gpio = 4, + .active_low = 1, + }, + { + .name = "buffalo:amber:band5g", + .gpio = 5, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 3, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 5, + .active_low = 1, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 6, + .active_low = 1, + }, { + .desc = "router_off", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 1, + }, { + .desc = "movie_engine", + .type = EV_KEY, + .code = BTN_7, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 1, + } +}; + +static void __init wzrhpag300h_setup(void) +{ + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000); + u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000); + u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET; + u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1); + + ath79_register_mdio(0, ~(BIT(0) | BIT(4))); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_set_usb_power_gpio(2, GPIOF_OUT_INIT_HIGH, "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio), + wzrhpag300h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpag300h_gpio_keys), + wzrhpag300h_gpio_keys); + + ath79_register_m25p80_multi(&wzrhpag300h_flash_data); + + ap94_pci_init(eeprom1, mac1, eeprom2, mac2); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio, + ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio)); + ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio, + ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio)); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_AG300H, "WZR-HP-AG300H", + "Buffalo WZR-HP-AG300H", wzrhpag300h_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c new file mode 100644 index 000000000..94f352ace --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c @@ -0,0 +1,287 @@ +/* + * Buffalo WZR-HP-G300NH board support + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/nxp_74hc153.h> +#include <linux/rtl8366.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WZRHPG300NH_GPIO_LED_USB 0 +#define WZRHPG300NH_GPIO_LED_DIAG 1 +#define WZRHPG300NH_GPIO_LED_WIRELESS 6 +#define WZRHPG300NH_GPIO_LED_SECURITY 17 +#define WZRHPG300NH_GPIO_LED_ROUTER 18 + +#define WZRHPG300NH_GPIO_RTL8366_SDA 19 +#define WZRHPG300NH_GPIO_RTL8366_SCK 20 + +#define WZRHPG300NH_GPIO_74HC153_S0 9 +#define WZRHPG300NH_GPIO_74HC153_S1 11 +#define WZRHPG300NH_GPIO_74HC153_1Y 12 +#define WZRHPG300NH_GPIO_74HC153_2Y 14 + +#define WZRHPG300NH_GPIO_EXP_BASE 32 +#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) +#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) +#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) +#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) +#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) +#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) +#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) + +#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL) + +#define WZRHPG300NH_MAC_OFFSET 0x20c + +static struct mtd_partition wzrhpg300nh_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x0060000, + .size = 0x0100000, + }, { + .name = "rootfs", + .offset = 0x0160000, + .size = 0x1e60000, + }, { + .name = "user_property", + .offset = 0x1fc0000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x1fe0000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f60000, + } +}; + +static struct physmap_flash_data wzrhpg300nh_flash_data = { + .width = 2, + .parts = wzrhpg300nh_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), +}; + +#define WZRHPG300NH_FLASH_BASE 0x1e000000 +#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) + +static struct resource wzrhpg300nh_flash_resources[] = { + [0] = { + .start = WZRHPG300NH_FLASH_BASE, + .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device wzrhpg300nh_flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = wzrhpg300nh_flash_resources, + .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), + .dev = { + .platform_data = &wzrhpg300nh_flash_data, + } +}; + +static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { + { + .name = "buffalo:orange:security", + .gpio = WZRHPG300NH_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "buffalo:green:wireless", + .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, + .active_low = 1, + }, { + .name = "buffalo:green:router", + .gpio = WZRHPG300NH_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "buffalo:red:diag", + .gpio = WZRHPG300NH_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "buffalo:blue:usb", + .gpio = WZRHPG300NH_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_AOSS, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_USB, + .active_low = 1, + }, { + .desc = "qos_on", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, + .active_low = 0, + }, { + .desc = "qos_off", + .type = EV_KEY, + .code = BTN_4, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, + .active_low = 0, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, + .active_low = 0, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, + .active_low = 0, + } +}; + +static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { + .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, + .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, + .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, + .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, + .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, +}; + +static struct platform_device wzrhpg300nh_74hc153_device = { + .name = NXP_74HC153_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_74hc153_data, + } +}; + +static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = { + .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, + .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, +}; + +static struct platform_device wzrhpg300nh_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_rtl8366_data, + } +}; + +static struct platform_device wzrhpg300nh_rtl8366rb_device = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_rtl8366_data, + } +}; + +static void __init wzrhpg300nh_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET; + bool hasrtl8366rb = false; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB) + hasrtl8366rb = true; + + if (hasrtl8366rb) { + ath79_eth0_pll_data.pll_1000 = 0x1f000000; + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; + ath79_eth1_pll_data.pll_1000 = 0x100; + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; + } else { + ath79_eth0_pll_data.pll_1000 = 0x1e000100; + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; + ath79_eth1_pll_data.pll_1000 = 0x1e000100; + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; + } + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_wmac(eeprom, NULL); + + platform_device_register(&wzrhpg300nh_74hc153_device); + platform_device_register(&wzrhpg300nh_flash_device); + + if (hasrtl8366rb) + platform_device_register(&wzrhpg300nh_rtl8366rb_device); + else + platform_device_register(&wzrhpg300nh_rtl8366s_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), + wzrhpg300nh_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg300nh_gpio_keys), + wzrhpg300nh_gpio_keys); + +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", + "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c new file mode 100644 index 000000000..6c850cee5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c @@ -0,0 +1,177 @@ +/* + * Buffalo WZR-HP-G300NH2 board support + * + * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org> + * Copyright (C) 2011 Mark Deneen <mdeneen@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPG300NH2_MAC_OFFSET 0x20c +#define WZRHPG300NH2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH2_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpg300nh2_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x0060000, + .size = 0x0100000, + }, { + .name = "rootfs", + .offset = 0x0160000, + .size = 0x1e90000, + }, { + .name = "user_property", + .offset = 0x1ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f90000, + } +}; + +static struct flash_platform_data wzrhpg300nh2_flash_data = { + .parts = wzrhpg300nh2_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg300nh2_flash_partitions), +}; + +static struct gpio_led wzrhpg300nh2_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 16, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpg300nh2_wmac_leds_gpio[] = { + { + .name = "buffalo:blue:usb", + .gpio = 4, + .active_low = 1, + }, + { + .name = "buffalo:orange:security", + .gpio = 6, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 7, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine_on", + .gpio = 8, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine_off", + .gpio = 9, + .active_low = 1, + }, +}; + +/* The AOSS button is wmac gpio 12 */ +static struct gpio_keys_button wzrhpg300nh2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 1, + }, { + .desc = "qos", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 0, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 0, + }, +}; + +static void __init wzrhpg300nh2_setup(void) +{ + + u8 *eeprom = (u8 *) KSEG1ADDR(0x1f051000); + u8 *mac0 = eeprom + WZRHPG300NH2_MAC_OFFSET; + /* There is an eth1 but it is not connected to the switch */ + + ath79_register_m25p80_multi(&wzrhpg300nh2_flash_data); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_register_mdio(0, ~(BIT(0))); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + /* gpio13 is usb power. Turn it on. */ + ath79_set_usb_power_gpio(13, GPIOF_OUT_INIT_HIGH, "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh2_leds_gpio), + wzrhpg300nh2_leds_gpio); + ath79_register_gpio_keys_polled(-1, WZRHPG300NH2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg300nh2_gpio_keys), + wzrhpg300nh2_gpio_keys); + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_leds(0, wzrhpg300nh2_wmac_leds_gpio, + ARRAY_SIZE(wzrhpg300nh2_wmac_leds_gpio)); + + ap91_pci_init(eeprom, mac0); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH2, "WZR-HP-G300NH2", + "Buffalo WZR-HP-G300NH2", wzrhpg300nh2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c new file mode 100644 index 000000000..b5292db54 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c @@ -0,0 +1,169 @@ +/* + * Buffalo WZR-HP-G450G board support + * + * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org> + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-ath79/ath79.h> + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPG450H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG450H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG450H_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpg450h_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + }, { + .name = "ART", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uImage", + .offset = 0x0060000, + .size = 0x0100000, + }, { + .name = "rootfs", + .offset = 0x0160000, + .size = 0x1e80000, + }, { + .name = "user_property", + .offset = 0x1fe0000, + .size = 0x0020000, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f80000, + } +}; + +static struct flash_platform_data wzrhpg450h_flash_data = { + .parts = wzrhpg450h_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions), +}; + +static struct gpio_led wzrhpg450h_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 14, + .active_low = 1, + }, + { + .name = "buffalo:orange:security", + .gpio = 13, + .active_low = 1, + }, +}; + + +static struct gpio_led wzrhpg450h_wmac_leds_gpio[] = { + { + .name = "buffalo:blue:movie_engine", + .gpio = 13, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 14, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzrhpg450h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 6, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 1, + }, { + .desc = "movie_engine", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 0, + }, { + .desc = "router_off", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 0, + } +}; + + +static void __init wzrhpg450h_init(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1f051000); + u8 *mac = (u8 *) ee + 2; + + ath79_register_m25p80_multi(&wzrhpg450h_flash_data); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg450h_leds_gpio), + wzrhpg450h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPG450H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg450h_gpio_keys), + wzrhpg450h_gpio_keys); + + ath79_register_eth(0); + + ath79_set_usb_power_gpio(16, GPIOF_OUT_INIT_HIGH, "USB power"); + ath79_register_usb(); + + ap91_pci_init(ee, NULL); + ap9x_pci_setup_wmac_led_pin(0, 15); + ap9x_pci_setup_wmac_leds(0, wzrhpg450h_wmac_leds_gpio, + ARRAY_SIZE(wzrhpg450h_wmac_leds_gpio)); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G450H, "WZR-HP-G450H", "Buffalo WZR-HP-G450H", + wzrhpg450h_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c new file mode 100644 index 000000000..3a6fe21ed --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c @@ -0,0 +1,157 @@ +/* + * Zcomax ZCN-1523H-2-8/5-16 board support + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" + +#define ZCN_1523H_GPIO_BTN_RESET 0 +#define ZCN_1523H_GPIO_LED_INIT 11 +#define ZCN_1523H_GPIO_LED_LAN1 17 + +#define ZCN_1523H_2_GPIO_LED_WEAK 13 +#define ZCN_1523H_2_GPIO_LED_MEDIUM 14 +#define ZCN_1523H_2_GPIO_LED_STRONG 15 + +#define ZCN_1523H_5_GPIO_LED_UNKNOWN 1 +#define ZCN_1523H_5_GPIO_LED_LAN2 13 +#define ZCN_1523H_5_GPIO_LED_WEAK 14 +#define ZCN_1523H_5_GPIO_LED_MEDIUM 15 +#define ZCN_1523H_5_GPIO_LED_STRONG 16 + +#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL, + .gpio = ZCN_1523H_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:amber:init", + .gpio = ZCN_1523H_GPIO_LED_INIT, + .active_low = 1, + }, { + .name = "zcn-1523h:green:lan1", + .gpio = ZCN_1523H_GPIO_LED_LAN1, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:red:weak", + .gpio = ZCN_1523H_2_GPIO_LED_WEAK, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:medium", + .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM, + .active_low = 1, + }, { + .name = "zcn-1523h:green:strong", + .gpio = ZCN_1523H_2_GPIO_LED_STRONG, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:red:weak", + .gpio = ZCN_1523H_5_GPIO_LED_WEAK, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:medium", + .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM, + .active_low = 1, + }, { + .name = "zcn-1523h:green:strong", + .gpio = ZCN_1523H_5_GPIO_LED_STRONG, + .active_low = 1, + }, { + .name = "zcn-1523h:green:lan2", + .gpio = ZCN_1523H_5_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:unknown", + .gpio = ZCN_1523H_5_GPIO_LED_UNKNOWN, + } +}; + +static void __init zcn_1523h_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio), + zcn_1523h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(zcn_1523h_gpio_keys), + zcn_1523h_gpio_keys); + + ap91_pci_init(ee, mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN1 port */ + ath79_register_eth(0); +} + +static void __init zcn_1523h_2_setup(void) +{ + zcn_1523h_generic_setup(); + ap9x_pci_setup_wmac_gpio(0, BIT(9), 0); + + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio), + zcn_1523h_2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2", + zcn_1523h_2_setup); + +static void __init zcn_1523h_5_setup(void) +{ + zcn_1523h_generic_setup(); + ap9x_pci_setup_wmac_gpio(0, BIT(8), 0); + + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio), + zcn_1523h_5_leds_gpio); + + /* LAN2 port */ + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5", + zcn_1523h_5_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/nvram.c b/target/linux/ar71xx/files/arch/mips/ath79/nvram.c new file mode 100644 index 000000000..43911b8ac --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/nvram.c @@ -0,0 +1,75 @@ +/* + * Atheros AR71xx minimal nvram support + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/vmalloc.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/string.h> + +#include "nvram.h" + +char *ath79_nvram_find_var(const char *name, const char *buf, unsigned buf_len) +{ + unsigned len = strlen(name); + char *cur, *last; + + if (buf_len == 0 || len == 0) + return NULL; + + if (buf_len < len) + return NULL; + + if (len == 1) + return memchr(buf, (int) *name, buf_len); + + last = (char *) buf + buf_len - len; + for (cur = (char *) buf; cur <= last; cur++) + if (cur[0] == name[0] && memcmp(cur, name, len) == 0) + return cur + len; + + return NULL; +} + +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, + const char *name, char *mac) +{ + char *buf; + char *mac_str; + int ret; + int t; + + buf = vmalloc(nvram_len); + if (!buf) + return -ENOMEM; + + memcpy(buf, nvram, nvram_len); + buf[nvram_len - 1] = '\0'; + + mac_str = ath79_nvram_find_var(name, buf, nvram_len); + if (!mac_str) { + ret = -EINVAL; + goto free; + } + + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != 6) { + ret = -EINVAL; + goto free; + } + + ret = 0; + +free: + vfree(buf); + return ret; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/nvram.h b/target/linux/ar71xx/files/arch/mips/ath79/nvram.h new file mode 100644 index 000000000..75151d4a3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/nvram.h @@ -0,0 +1,19 @@ +/* + * Atheros AR71xx minimal nvram support + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_NVRAM_H +#define _ATH79_NVRAM_H + +char *ath79_nvram_find_var(const char *name, const char *buf, + unsigned buf_len); +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, + const char *name, char *mac); + +#endif /* _ATH79_NVRAM_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c new file mode 100644 index 000000000..fcca1d2ea --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c @@ -0,0 +1,123 @@ +/* + * Atheros AP94 reference board PCI initialization + * + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/pci.h> +#include <linux/delay.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +struct ath9k_fixup { + u16 *cal_data; + unsigned slot; +}; + +static int ath9k_num_fixups; +static struct ath9k_fixup ath9k_fixups[2]; + +static void ath9k_pci_fixup(struct pci_dev *dev) +{ + void __iomem *mem; + u16 *cal_data = NULL; + u16 cmd; + u32 bar0; + u32 val; + unsigned i; + + for (i = 0; i < ath9k_num_fixups; i++) { + if (ath9k_fixups[i].cal_data == NULL) + continue; + + if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) + continue; + + cal_data = ath9k_fixups[i].cal_data; + break; + } + + if (cal_data == NULL) + return; + + if (*cal_data != 0xa55a) { + pr_err("pci %s: invalid calibration data\n", pci_name(dev)); + return; + } + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + + mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + + switch (ath79_soc) { + case ATH79_SOC_AR7161: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + AR71XX_PCI_MEM_BASE); + break; + case ATH79_SOC_AR7240: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR7242: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); + break; + + default: + BUG(); + } + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); + + /* set pointer to first reg address */ + cal_data += 3; + while (*cal_data != 0xffff) { + u32 reg; + reg = *cal_data++; + val = *cal_data++; + val |= (*cal_data++) << 16; + + __raw_writel(val, mem + reg); + udelay(100); + } + + pci_read_config_dword(dev, PCI_VENDOR_ID, &val); + dev->vendor = val & 0xffff; + dev->device = (val >> 16) & 0xffff; + + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); + dev->revision = val & 0xff; + dev->class = val >> 8; /* upper 3 bytes */ + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + + iounmap(mem); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + +void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) +{ + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; + ath9k_fixups[ath9k_num_fixups].cal_data = cal_data; + ath9k_num_fixups++; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h new file mode 100644 index 000000000..5794941f0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h @@ -0,0 +1,6 @@ +#ifndef _PCI_ATH9K_FIXUP +#define _PCI_ATH9K_FIXUP + +void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init; + +#endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c new file mode 100644 index 000000000..3c6f9aaeb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c @@ -0,0 +1,100 @@ +/* + * RouterBoot helper routines + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/routerboot.h> + +#include "routerboot.h" + +static u32 get_u32(void *buf) +{ + u8 *p = buf; + + return ((u32) p[3] + ((u32) p[2] << 8) + ((u32) p[1] << 16) + + ((u32) p[0] << 24)); +} + +static u16 get_u16(void *buf) +{ + u8 *p = buf; + + return (u16) p[1] + ((u16) p[0] << 8); +} + +__init int +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len) +{ + uint32_t magic; + int ret; + + if (buflen < 4) + return -EINVAL; + + magic = get_u32(buf); + switch (magic) { + case RB_MAGIC_HARD: + /* skip magic value */ + buf += 4; + buflen -= 4; + break; + + case RB_MAGIC_SOFT: + if (buflen < 8) + return -EINVAL; + + /* skip magic and CRC value */ + buf += 8; + buflen -= 8; + + break; + + default: + return -EINVAL; + } + + ret = -ENOENT; + while (buflen > 2) { + u16 id; + u16 len; + + len = get_u16(buf); + buf += 2; + buflen -= 2; + + if (buflen < 2) + break; + + id = get_u16(buf); + buf += 2; + buflen -= 2; + + if (id == RB_ID_TERMINATOR) + break; + + if (buflen < len) + break; + + if (id == tag_id) { + if (tag_len) + *tag_len = len; + if (tag_data) + *tag_data = buf; + ret = 0; + break; + } + + buf += len; + buflen -= len; + } + + return ret; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h new file mode 100644 index 000000000..9a4dde59e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h @@ -0,0 +1,26 @@ +/* + * RouterBoot definitions + * + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_ROUTERBOOT_H_ +#define _ATH79_ROUTERBOOT_H_ + +#ifdef CONFIG_ATH79_ROUTERBOOT +int routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len); +#else +static inline int +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len) +{ + return -ENOENT; +} +#endif + +#endif /* _ATH79_ROUTERBOOT_H_ */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h b/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h new file mode 100644 index 000000000..8a99d566d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h @@ -0,0 +1,34 @@ +/* + * Compex's MyLoader specific definitions + * + * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ASM_MIPS_FW_MYLOADER_H +#define _ASM_MIPS_FW_MYLOADER_H + +#include <linux/myloader.h> + +struct myloader_info { + uint32_t vid; + uint32_t did; + uint32_t svid; + uint32_t sdid; + uint8_t macs[MYLO_ETHADDR_COUNT][6]; +}; + +#ifdef CONFIG_MYLOADER +extern struct myloader_info *myloader_get_info(void) __init; +#else +static inline struct myloader_info *myloader_get_info(void) +{ + return NULL; +} +#endif /* CONFIG_MYLOADER */ + +#endif /* _ASM_MIPS_FW_MYLOADER_H */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h new file mode 100644 index 000000000..656a6ef86 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h @@ -0,0 +1,60 @@ +/* + * Atheros AR71xx SoC specific platform data definitions + * + * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_PLATFORM_H +#define __ASM_MACH_ATH79_PLATFORM_H + +#include <linux/if_ether.h> +#include <linux/skbuff.h> +#include <linux/phy.h> +#include <linux/spi/spi.h> + +struct ag71xx_switch_platform_data { + u8 phy4_mii_en:1; + u8 phy_poll_mask; +}; + +struct ag71xx_platform_data { + phy_interface_t phy_if_mode; + u32 phy_mask; + int speed; + int duplex; + u32 reset_bit; + u8 mac_addr[ETH_ALEN]; + struct device *mii_bus_dev; + + u8 has_gbit:1; + u8 is_ar91xx:1; + u8 is_ar7240:1; + u8 is_ar724x:1; + u8 has_ar8216:1; + + struct ag71xx_switch_platform_data *switch_data; + + void (*ddr_flush)(void); + void (*set_speed)(int speed); + + u32 fifo_cfg1; + u32 fifo_cfg2; + u32 fifo_cfg3; +}; + +struct ag71xx_mdio_platform_data { + u32 phy_mask; + u8 builtin_switch:1; + u8 is_ar7240:1; + u8 is_ar9330:1; + u8 is_ar934x:1; + unsigned long mdio_clock; + unsigned long ref_clock; +}; + +#endif /* __ASM_MACH_ATH79_PLATFORM_H */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h new file mode 100644 index 000000000..50d5a2097 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h @@ -0,0 +1,84 @@ +/* + * MikroTik RouterBOARD 750 definitions + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef _MACH_RB750_H +#define _MACH_RB750_H + +#include <linux/bitops.h> + +#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ +#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ +#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ +#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ +#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ +#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ +#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ +#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ +#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ +#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ +#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ +#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ +#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ +#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ +#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ + +#define RB750_GPIO_BTN_RESET 1 +#define RB750_GPIO_SPI_CS0 2 +#define RB750_GPIO_LED_ACT 12 +#define RB750_GPIO_LED_PORT1 13 +#define RB750_GPIO_LED_PORT2 14 +#define RB750_GPIO_LED_PORT3 15 +#define RB750_GPIO_LED_PORT4 16 +#define RB750_GPIO_LED_PORT5 17 + +#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) +#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) +#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) +#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) +#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) +#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) +#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) + +#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) + +#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ + RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) + +#define RB7XX_GPIO_NAND_NCE 0 +#define RB7XX_GPIO_MON 9 +#define RB7XX_GPIO_LED_ACT 11 +#define RB7XX_GPIO_USB_POWERON 13 + +#define RB7XX_NAND_NCE BIT(RB7XX_GPIO_NAND_NCE) +#define RB7XX_LED_ACT BIT(RB7XX_GPIO_LED_ACT) +#define RB7XX_MONITOR BIT(RB7XX_GPIO_MON) +#define RB7XX_USB_POWERON BIT(RB7XX_GPIO_USB_POWERON) + +struct rb750_led_data { + char *name; + char *default_trigger; + u32 mask; + int active_low; +}; + +struct rb750_led_platform_data { + int num_leds; + struct rb750_led_data *leds; + void (*latch_change)(u32 clear, u32 set); +}; + +struct rb7xx_nand_platform_data { + u32 nce_line; + + void (*enable_pins)(void); + void (*disable_pins)(void); + void (*latch_change)(u32, u32); +}; + +#endif /* _MACH_RB750_H */
\ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h new file mode 100644 index 000000000..5b17e94b6 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h @@ -0,0 +1,48 @@ +/* + * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define CPLD_GPIO_nLED1 0 +#define CPLD_GPIO_nLED2 1 +#define CPLD_GPIO_nLED3 2 +#define CPLD_GPIO_nLED4 3 +#define CPLD_GPIO_FAN 4 +#define CPLD_GPIO_ALE 5 +#define CPLD_GPIO_CLE 6 +#define CPLD_GPIO_nCE 7 +#define CPLD_GPIO_nLED5 8 + +#define CPLD_NUM_GPIOS 9 + +#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) +#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) +#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) +#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) +#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) +#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) +#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) +#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) +#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) + +struct rb4xx_cpld_platform_data { + unsigned gpio_base; +}; + +extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); +extern int rb4xx_cpld_read(unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_read_from(unsigned addr, + unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); diff --git a/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c new file mode 100644 index 000000000..a5fec5ca7 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c @@ -0,0 +1,247 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer GPIO driver + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/nxp_74hc153.h> + +#define NXP_74HC153_NUM_GPIOS 8 +#define NXP_74HC153_S0_MASK 0x1 +#define NXP_74HC153_S1_MASK 0x2 +#define NXP_74HC153_BANK_MASK 0x4 + +struct nxp_74hc153_chip { + struct device *parent; + struct gpio_chip gpio_chip; + struct mutex lock; +}; + +static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) +{ + return container_of(gc, struct nxp_74hc153_chip, gpio_chip); +} + +static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) +{ + return 0; +} + +static int nxp_74hc153_direction_output(struct gpio_chip *gc, + unsigned offset, int val) +{ + return -EINVAL; +} + +static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) +{ + struct nxp_74hc153_chip *nxp; + struct nxp_74hc153_platform_data *pdata; + unsigned s0; + unsigned s1; + unsigned pin; + int ret; + + nxp = gpio_to_nxp(gc); + pdata = nxp->parent->platform_data; + + s0 = !!(offset & NXP_74HC153_S0_MASK); + s1 = !!(offset & NXP_74HC153_S1_MASK); + pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y + : pdata->gpio_pin_1y; + + mutex_lock(&nxp->lock); + gpio_set_value(pdata->gpio_pin_s0, s0); + gpio_set_value(pdata->gpio_pin_s1, s1); + ret = gpio_get_value(pin); + mutex_unlock(&nxp->lock); + + return ret; +} + +static void nxp_74hc153_set_value(struct gpio_chip *gc, + unsigned offset, int val) +{ + /* not supported */ +} + +static int __devinit nxp_74hc153_probe(struct platform_device *pdev) +{ + struct nxp_74hc153_platform_data *pdata; + struct nxp_74hc153_chip *nxp; + struct gpio_chip *gc; + int err; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { + dev_dbg(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); + if (nxp == NULL) { + dev_err(&pdev->dev, "no memory for private data\n"); + return -ENOMEM; + } + + err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_s0, err); + goto err_free_nxp; + } + + err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_s1, err); + goto err_free_s0; + } + + err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_1y, err); + goto err_free_s1; + } + + err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_2y, err); + goto err_free_1y; + } + + err = gpio_direction_output(pdata->gpio_pin_s0, 0); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_s0, err); + goto err_free_2y; + } + + err = gpio_direction_output(pdata->gpio_pin_s1, 0); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_s1, err); + goto err_free_2y; + } + + err = gpio_direction_input(pdata->gpio_pin_1y); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_1y, err); + goto err_free_2y; + } + + err = gpio_direction_input(pdata->gpio_pin_2y); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_2y, err); + goto err_free_2y; + } + + nxp->parent = &pdev->dev; + mutex_init(&nxp->lock); + + gc = &nxp->gpio_chip; + + gc->direction_input = nxp_74hc153_direction_input; + gc->direction_output = nxp_74hc153_direction_output; + gc->get = nxp_74hc153_get_value; + gc->set = nxp_74hc153_set_value; + gc->can_sleep = 1; + + gc->base = pdata->gpio_base; + gc->ngpio = NXP_74HC153_NUM_GPIOS; + gc->label = dev_name(nxp->parent); + gc->dev = nxp->parent; + gc->owner = THIS_MODULE; + + err = gpiochip_add(&nxp->gpio_chip); + if (err) { + dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); + goto err_free_2y; + } + + platform_set_drvdata(pdev, nxp); + return 0; + +err_free_2y: + gpio_free(pdata->gpio_pin_2y); +err_free_1y: + gpio_free(pdata->gpio_pin_1y); +err_free_s1: + gpio_free(pdata->gpio_pin_s1); +err_free_s0: + gpio_free(pdata->gpio_pin_s0); +err_free_nxp: + kfree(nxp); + return err; +} + +static int nxp_74hc153_remove(struct platform_device *pdev) +{ + struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); + struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; + + if (nxp) { + int err; + + err = gpiochip_remove(&nxp->gpio_chip); + if (err) { + dev_err(&pdev->dev, + "unable to remove gpio chip, err=%d\n", + err); + return err; + } + + gpio_free(pdata->gpio_pin_2y); + gpio_free(pdata->gpio_pin_1y); + gpio_free(pdata->gpio_pin_s1); + gpio_free(pdata->gpio_pin_s0); + + kfree(nxp); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver nxp_74hc153_driver = { + .probe = nxp_74hc153_probe, + .remove = __devexit_p(nxp_74hc153_remove), + .driver = { + .name = NXP_74HC153_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init nxp_74hc153_init(void) +{ + return platform_driver_register(&nxp_74hc153_driver); +} +subsys_initcall(nxp_74hc153_init); + +static void __exit nxp_74hc153_exit(void) +{ + platform_driver_unregister(&nxp_74hc153_driver); +} +module_exit(nxp_74hc153_exit); + +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/leds/leds-rb750.c b/target/linux/ar71xx/files/drivers/leds/leds-rb750.c new file mode 100644 index 000000000..483e4fc96 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/leds/leds-rb750.c @@ -0,0 +1,144 @@ +/* + * LED driver for the RouterBOARD 750 + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/slab.h> + +#include <asm/mach-ath79/mach-rb750.h> + +#define DRV_NAME "leds-rb750" + +struct rb750_led_dev { + struct led_classdev cdev; + u32 mask; + int active_low; + void (*latch_change)(u32 clear, u32 set); +}; + +struct rb750_led_drvdata { + struct rb750_led_dev *led_devs; + int num_leds; +}; + +static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) +{ + return (struct rb750_led_dev *)container_of(led_cdev, + struct rb750_led_dev, cdev); +} + +static void rb750_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct rb750_led_dev *rbled = to_rbled(led_cdev); + int level; + + level = (value == LED_OFF) ? 0 : 1; + level ^= rbled->active_low; + + if (level) + rbled->latch_change(0, rbled->mask); + else + rbled->latch_change(rbled->mask, 0); +} + +static int __devinit rb750_led_probe(struct platform_device *pdev) +{ + struct rb750_led_platform_data *pdata; + struct rb750_led_drvdata *drvdata; + int ret = 0; + int i; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + + sizeof(struct rb750_led_dev) * pdata->num_leds, + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->num_leds = pdata->num_leds; + drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; + + for (i = 0; i < drvdata->num_leds; i++) { + struct rb750_led_dev *rbled = &drvdata->led_devs[i]; + struct rb750_led_data *led_data = &pdata->leds[i]; + + rbled->cdev.name = led_data->name; + rbled->cdev.default_trigger = led_data->default_trigger; + rbled->cdev.brightness_set = rb750_led_brightness_set; + rbled->cdev.brightness = LED_OFF; + + rbled->mask = led_data->mask; + rbled->active_low = !!led_data->active_low; + rbled->latch_change = pdata->latch_change; + + ret = led_classdev_register(&pdev->dev, &rbled->cdev); + if (ret) + goto err; + } + + platform_set_drvdata(pdev, drvdata); + return 0; + +err: + for (i = i - 1; i >= 0; i--) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return ret; +} + +static int __devexit rb750_led_remove(struct platform_device *pdev) +{ + struct rb750_led_drvdata *drvdata; + int i; + + drvdata = platform_get_drvdata(pdev); + for (i = 0; i < drvdata->num_leds; i++) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return 0; +} + +static struct platform_driver rb750_led_driver = { + .probe = rb750_led_probe, + .remove = __devexit_p(rb750_led_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:leds-rb750"); + +static int __init rb750_led_init(void) +{ + return platform_driver_register(&rb750_led_driver); +} + +static void __exit rb750_led_exit(void) +{ + platform_driver_unregister(&rb750_led_driver); +} + +module_init(rb750_led_init); +module_exit(rb750_led_exit); + +MODULE_DESCRIPTION(DRV_NAME); +MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c b/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c new file mode 100644 index 000000000..42f5b70bd --- /dev/null +++ b/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c @@ -0,0 +1,76 @@ +/* + * USB LED driver for the NETGEAR WNDR3700 + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/leds.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#define DRIVER_NAME "wndr3700-led-usb" + +static void wndr3700_usb_led_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + if (brightness) + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); + else + ath79_device_reset_set(AR71XX_RESET_GE1_PHY); +} + +static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) +{ + return ath79_device_reset_get(AR71XX_RESET_GE1_PHY) ? LED_OFF : LED_FULL; +} + +static struct led_classdev wndr3700_usb_led = { + .name = "wndr3700:green:usb", + .brightness_set = wndr3700_usb_led_set, + .brightness_get = wndr3700_usb_led_get, +}; + +static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) +{ + return led_classdev_register(&pdev->dev, &wndr3700_usb_led); +} + +static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&wndr3700_usb_led); + return 0; +} + +static struct platform_driver wndr3700_usb_led_driver = { + .probe = wndr3700_usb_led_probe, + .remove = __devexit_p(wndr3700_usb_led_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init wndr3700_usb_led_init(void) +{ + return platform_driver_register(&wndr3700_usb_led_driver); +} + +static void __exit wndr3700_usb_led_exit(void) +{ + platform_driver_unregister(&wndr3700_usb_led_driver); +} + +module_init(wndr3700_usb_led_init); +module_exit(wndr3700_usb_led_exit); + +MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c new file mode 100644 index 000000000..9bc9b125f --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c @@ -0,0 +1,1151 @@ +/* + * Driver for the built-in NAND controller of the Atheros AR934x SoCs + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/dma-mapping.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/slab.h> + +#include <linux/platform/ar934x_nfc.h> + +#define AR934X_NFC_REG_CMD 0x00 +#define AR934X_NFC_REG_CTRL 0x04 +#define AR934X_NFC_REG_STATUS 0x08 +#define AR934X_NFC_REG_INT_MASK 0x0c +#define AR934X_NFC_REG_INT_STATUS 0x10 +#define AR934X_NFC_REG_ECC_CTRL 0x14 +#define AR934X_NFC_REG_ECC_OFFSET 0x18 +#define AR934X_NFC_REG_ADDR0_0 0x1c +#define AR934X_NFC_REG_ADDR0_1 0x24 +#define AR934X_NFC_REG_ADDR1_0 0x20 +#define AR934X_NFC_REG_ADDR1_1 0x28 +#define AR934X_NFC_REG_SPARE_SIZE 0x30 +#define AR934X_NFC_REG_PROTECT 0x38 +#define AR934X_NFC_REG_LOOKUP_EN 0x40 +#define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4) +#define AR934X_NFC_REG_DMA_ADDR 0x64 +#define AR934X_NFC_REG_DMA_COUNT 0x68 +#define AR934X_NFC_REG_DMA_CTRL 0x6c +#define AR934X_NFC_REG_MEM_CTRL 0x80 +#define AR934X_NFC_REG_DATA_SIZE 0x84 +#define AR934X_NFC_REG_READ_STATUS 0x88 +#define AR934X_NFC_REG_TIME_SEQ 0x8c +#define AR934X_NFC_REG_TIMINGS_ASYN 0x90 +#define AR934X_NFC_REG_TIMINGS_SYN 0x94 +#define AR934X_NFC_REG_FIFO_DATA 0x98 +#define AR934X_NFC_REG_TIME_MODE 0x9c +#define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0 +#define AR934X_NFC_REG_FIFO_INIT 0xb0 +#define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4 + +#define AR934X_NFC_CMD_CMD_SEQ_S 0 +#define AR934X_NFC_CMD_CMD_SEQ_M 0x3f +#define AR934X_NFC_CMD_SEQ_1C 0x00 +#define AR934X_NFC_CMD_SEQ_ERASE 0x0e +#define AR934X_NFC_CMD_SEQ_12 0x0c +#define AR934X_NFC_CMD_SEQ_1C1AXR 0x21 +#define AR934X_NFC_CMD_SEQ_S 0x24 +#define AR934X_NFC_CMD_SEQ_1C3AXR 0x27 +#define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a +#define AR934X_NFC_CMD_SEQ_18 0x32 +#define AR934X_NFC_CMD_INPUT_SEL_SIU 0 +#define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6) +#define AR934X_NFC_CMD_ADDR_SEL_0 0 +#define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7) +#define AR934X_NFC_CMD_CMD0_S 8 +#define AR934X_NFC_CMD_CMD0_M 0xff +#define AR934X_NFC_CMD_CMD1_S 16 +#define AR934X_NFC_CMD_CMD1_M 0xff +#define AR934X_NFC_CMD_CMD2_S 24 +#define AR934X_NFC_CMD_CMD2_M 0xff + +#define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7 +#define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0 +#define AR934X_NFC_CTRL_SPARE_EN BIT(3) +#define AR934X_NFC_CTRL_INT_EN BIT(4) +#define AR934X_NFC_CTRL_ECC_EN BIT(5) +#define AR934X_NFC_CTRL_BLOCK_SIZE_S 6 +#define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3 +#define AR934X_NFC_CTRL_BLOCK_SIZE_32 0 +#define AR934X_NFC_CTRL_BLOCK_SIZE_64 1 +#define AR934X_NFC_CTRL_BLOCK_SIZE_128 2 +#define AR934X_NFC_CTRL_BLOCK_SIZE_256 3 +#define AR934X_NFC_CTRL_PAGE_SIZE_S 8 +#define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7 +#define AR934X_NFC_CTRL_PAGE_SIZE_256 0 +#define AR934X_NFC_CTRL_PAGE_SIZE_512 1 +#define AR934X_NFC_CTRL_PAGE_SIZE_1024 2 +#define AR934X_NFC_CTRL_PAGE_SIZE_2048 3 +#define AR934X_NFC_CTRL_PAGE_SIZE_4096 4 +#define AR934X_NFC_CTRL_PAGE_SIZE_8192 5 +#define AR934X_NFC_CTRL_PAGE_SIZE_16384 6 +#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11) +#define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0 +#define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12) +#define AR934X_NFC_CTRL_LOOKUP_EN BIT(13) +#define AR934X_NFC_CTRL_PROT_EN BIT(14) +#define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0 +#define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15) +#define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16) +#define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17) +#define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7 +#define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18 +#define AR934X_NFC_CTRL_SMALL_PAGE BIT(21) + +#define AR934X_NFC_DMA_CTRL_DMA_START BIT(7) +#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0 +#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6) +#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5) +#define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5 +#define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1) +#define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0) + +#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x)) +#define AR934X_NFC_INT_CMD_END BIT(1) + +/* default timing values */ +#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff +#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22 +#define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf + +#define AR934X_NFC_ID_BUF_SIZE 8 +#define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */ +#define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */ +#define AR934X_NFC_DONE_TIMEOUT 1000 +#define AR934X_NFC_DMA_RETRIES 20 + +#define AR934X_NFC_USE_IRQ true +#define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0) + +#define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043 + +#undef AR934X_NFC_DEBUG_DATA +#undef AR934X_NFC_DEBUG + +struct ar934x_nfc; + +static inline __attribute__ ((format (printf, 2, 3))) +void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...) +{ +} + +#ifdef AR934X_NFC_DEBUG +#define nfc_dbg(_nfc, fmt, ...) \ + dev_info((_nfc)->parent, fmt, ##__VA_ARGS__) +#else +#define nfc_dbg(_nfc, fmt, ...) \ + _nfc_dbg((_nfc), fmt, ##__VA_ARGS__) +#endif /* AR934X_NFC_DEBUG */ + +#ifdef AR934X_NFC_DEBUG_DATA +static void +nfc_debug_data(const char *label, void *data, int len) +{ + print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1, + data, len, 0); +} +#else +static inline void +nfc_debug_data(const char *label, void *data, int len) {} +#endif /* AR934X_NFC_DEBUG_DATA */ + +struct ar934x_nfc { + struct mtd_info mtd; + struct nand_chip nand_chip; + struct device *parent; + void __iomem *base; + void (*select_chip)(int chip_no); + int irq; + wait_queue_head_t irq_waitq; + + bool spurious_irq_expected; + u32 irq_status; + + u32 ctrl_reg; + bool small_page; + unsigned int addr_count0; + unsigned int addr_count1; + + u8 *buf; + dma_addr_t buf_dma; + unsigned int buf_size; + int buf_index; + + int erase1_page_addr; + + int rndout_page_addr; + int rndout_read_cmd; + + int seqin_page_addr; + int seqin_column; + int seqin_read_cmd; +}; + +static void ar934x_nfc_restart(struct ar934x_nfc *nfc); + +static inline void +ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val) +{ + __raw_writel(val, nfc->base + reg); +} + +static inline u32 +ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg) +{ + return __raw_readl(nfc->base + reg); +} + +static inline struct ar934x_nfc_platform_data * +ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc) +{ + return nfc->parent->platform_data; +} + +static inline struct +ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd) +{ + return container_of(mtd, struct ar934x_nfc, mtd); +} + +static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc) +{ + return AR934X_NFC_USE_IRQ; +} + +static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg) +{ + wmb(); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD); +} + +static bool +__ar934x_nfc_dev_ready(struct ar934x_nfc *nfc) +{ + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS); + return (status & 0xff) == 0xff; +} + +static inline bool +__ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc) +{ + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL); + return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0; +} + +static int +ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc) +{ + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT); + do { + if (__ar934x_nfc_dev_ready(nfc)) + return 0; + } while time_before(jiffies, timeout); + + nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n", + ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS), + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS)); + return -ETIMEDOUT; +} + +static int +ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc) +{ + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT); + do { + if (__ar934x_nfc_is_dma_ready(nfc)) + return 0; + } while time_before(jiffies, timeout); + + nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n", + ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL)); + return -ETIMEDOUT; +} + +static int +ar934x_nfc_wait_irq(struct ar934x_nfc *nfc) +{ + long timeout; + int ret; + + timeout = wait_event_timeout(nfc->irq_waitq, + (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0, + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT)); + + ret = 0; + if (!timeout) { + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + nfc_dbg(nfc, + "timeout waiting for interrupt, status:%08x\n", + nfc->irq_status); + ret = -ETIMEDOUT; + } + + nfc->irq_status = 0; + return ret; +} + +static int +ar934x_nfc_wait_done(struct ar934x_nfc *nfc) +{ + int ret; + + if (ar934x_nfc_use_irq(nfc)) + ret = ar934x_nfc_wait_irq(nfc); + else + ret = ar934x_nfc_wait_dev_ready(nfc); + + if (ret) + return ret; + + return ar934x_nfc_wait_dma_ready(nfc); +} + +static int +ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size) +{ + nfc->buf = dma_alloc_coherent(nfc->parent, size, + &nfc->buf_dma, GFP_KERNEL); + if (nfc->buf == NULL) { + dev_err(nfc->parent, "no memory for DMA buffer\n"); + return -ENOMEM; + } + + nfc->buf_size = size; + nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size); + + return 0; +} + +static void +ar934x_nfc_free_buf(struct ar934x_nfc *nfc) +{ + dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma); +} + +static void +ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr, + u32 *addr0, u32 *addr1) +{ + u32 a0, a1; + + a0 = 0; + a1 = 0; + + if (column == -1) { + /* ERASE1 */ + a0 = (page_addr & 0xffff) << 16; + a1 = (page_addr >> 16) & 0xf; + } else if (page_addr != -1) { + /* SEQIN, READ0, etc.. */ + + /* TODO: handle 16bit bus width */ + if (nfc->small_page) { + a0 = column & 0xff; + a0 |= (page_addr & 0xff) << 8; + a0 |= ((page_addr >> 8) & 0xff) << 16; + a0 |= ((page_addr >> 16) & 0xff) << 24; + } else { + a0 = column & 0x0FFF; + a0 |= (page_addr & 0xffff) << 16; + + if (nfc->addr_count0 > 4) + a1 = (page_addr >> 16) & 0xf; + } + } + + *addr0 = a0; + *addr1 = a1; +} + +static void +ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command) +{ + u32 cmd_reg; + + cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 | + AR934X_NFC_CMD_SEQ_1C; + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); +} + +static void +ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr, + int len, u32 cmd_reg, u32 ctrl_reg, bool write) +{ + u32 addr0, addr1; + u32 dma_ctrl; + int dir; + int err; + int retries = 0; + + WARN_ON(len & 3); + + if (WARN_ON(len > nfc->buf_size)) + dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size); + + if (write) { + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE; + dir = DMA_TO_DEVICE; + } else { + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ; + dir = DMA_FROM_DEVICE; + } + + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1); + + dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START | + (AR934X_NFC_DMA_CTRL_DMA_BURST_3 << + AR934X_NFC_DMA_CTRL_DMA_BURST_S); + + cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0; + ctrl_reg |= AR934X_NFC_CTRL_INT_EN; + + nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n", + (write) ? "write" : "read", + addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg); + +retry: + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl); + + if (ar934x_nfc_use_irq(nfc)) { + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK); + } + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + err = ar934x_nfc_wait_done(nfc); + if (err) { + dev_dbg(nfc->parent, "%s operation stuck at page %d\n", + (write) ? "write" : "read", page_addr); + + ar934x_nfc_restart(nfc); + if (retries++ < AR934X_NFC_DMA_RETRIES) + goto retry; + + dev_err(nfc->parent, "%s operation failed on page %d\n", + (write) ? "write" : "read", page_addr); + } +} + +static void +ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command) +{ + u32 cmd_reg; + + nfc_dbg(nfc, "readid, cmd:%02x\n", command); + + cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR; + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, cmd_reg, + nfc->ctrl_reg, false); + + nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE); +} + +static void +ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr, int len) +{ + u32 cmd_reg; + + nfc_dbg(nfc, "read, column=%d page=%d len=%d\n", + column, page_addr, len); + + cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + if (nfc->small_page) { + cmd_reg |= AR934X_NFC_CMD_SEQ_18; + } else { + cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR; + } + + ar934x_nfc_do_rw_command(nfc, column, page_addr, len, + cmd_reg, nfc->ctrl_reg, false); + + nfc_debug_data("[data] ", nfc->buf, len); +} + +static void +ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr) +{ + u32 addr0, addr1; + u32 ctrl_reg; + u32 cmd_reg; + + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1); + + ctrl_reg = nfc->ctrl_reg; + if (nfc->small_page) { + /* override number of address cycles for the erase command */ + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M << + AR934X_NFC_CTRL_ADDR_CYCLE0_S); + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M << + AR934X_NFC_CTRL_ADDR_CYCLE1_S); + ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE); + ctrl_reg |= (nfc->addr_count0 + 1) << + AR934X_NFC_CTRL_ADDR_CYCLE0_S; + } + + cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE; + + nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n", + page_addr, addr0, addr1, cmd_reg, ctrl_reg); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); +} + +static void +ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr, int len) +{ + u32 cmd_reg; + + nfc_dbg(nfc, "write, column=%d page=%d len=%d\n", + column, page_addr, len); + + nfc_debug_data("[data] ", nfc->buf, len); + + cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_12; + + ar934x_nfc_do_rw_command(nfc, column, page_addr, len, + cmd_reg, nfc->ctrl_reg, true); +} + +static void +ar934x_nfc_read_status(struct ar934x_nfc *nfc) +{ + u32 cmd_reg; + u32 status; + + cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_S; + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS); + + nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n", + cmd_reg, (status & 0xff)); + + nfc->buf[0 ^ 3] = status; +} + +static void +ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, + int page_addr) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + if (command != NAND_CMD_PAGEPROG) + nfc->buf_index = 0; + + switch (command) { + case NAND_CMD_RESET: + ar934x_nfc_send_cmd(nfc, command); + break; + + case NAND_CMD_READID: + ar934x_nfc_send_readid(nfc, command); + break; + + case NAND_CMD_READ0: + case NAND_CMD_READ1: + if (nfc->small_page) { + ar934x_nfc_send_read(nfc, command, column, page_addr, + mtd->writesize + mtd->oobsize); + } else { + ar934x_nfc_send_read(nfc, command, 0, page_addr, + mtd->writesize + mtd->oobsize); + nfc->buf_index = column; + nfc->rndout_page_addr = page_addr; + nfc->rndout_read_cmd = command; + } + break; + + case NAND_CMD_READOOB: + if (nfc->small_page) + ar934x_nfc_send_read(nfc, NAND_CMD_READOOB, + column, page_addr, + mtd->oobsize); + else + ar934x_nfc_send_read(nfc, NAND_CMD_READ0, + mtd->writesize, page_addr, + mtd->oobsize); + break; + + case NAND_CMD_RNDOUT: + if (WARN_ON(nfc->small_page)) + break; + + /* emulate subpage read */ + ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0, + nfc->rndout_page_addr, + mtd->writesize + mtd->oobsize); + nfc->buf_index = column; + break; + + case NAND_CMD_ERASE1: + nfc->erase1_page_addr = page_addr; + break; + + case NAND_CMD_ERASE2: + ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr); + break; + + case NAND_CMD_STATUS: + ar934x_nfc_read_status(nfc); + break; + + case NAND_CMD_SEQIN: + if (nfc->small_page) { + /* output read command */ + if (column >= mtd->writesize) { + column -= mtd->writesize; + nfc->seqin_read_cmd = NAND_CMD_READOOB; + } else if (column < 256) { + nfc->seqin_read_cmd = NAND_CMD_READ0; + } else { + column -= 256; + nfc->seqin_read_cmd = NAND_CMD_READ1; + } + } else { + nfc->seqin_read_cmd = NAND_CMD_READ0; + } + nfc->seqin_column = column; + nfc->seqin_page_addr = page_addr; + break; + + case NAND_CMD_PAGEPROG: + if (nfc->small_page) + ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd); + + ar934x_nfc_send_write(nfc, command, nfc->seqin_column, + nfc->seqin_page_addr, + nfc->buf_index); + break; + + default: + dev_err(nfc->parent, + "unsupported command: %x, column:%d page_addr=%d\n", + command, column, page_addr); + break; + } +} + +static int +ar934x_nfc_dev_ready(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + return __ar934x_nfc_dev_ready(nfc); +} + +static void +ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + if (nfc->select_chip) + nfc->select_chip(chip_no); +} + +static u8 +ar934x_nfc_read_byte(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + unsigned int buf_index; + u8 data; + + WARN_ON(nfc->buf_index >= nfc->buf_size); + + buf_index = nfc->buf_index ^ 3; + data = nfc->buf[buf_index]; + nfc->buf_index++; + + return data; +} + +static void +ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int i; + + WARN_ON(nfc->buf_index + len > nfc->buf_size); + + for (i = 0; i < len; i++) { + nfc->buf[nfc->buf_index ^ 3] = buf[i]; + nfc->buf_index++; + } +} + +static void +ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int buf_index; + int i; + + WARN_ON(nfc->buf_index + len > nfc->buf_size); + + buf_index = nfc->buf_index; + + for (i = 0; i < len; i++) { + buf[i] = nfc->buf[buf_index ^ 3]; + buf_index++; + } + + nfc->buf_index = buf_index; +} + +static int +ar934x_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (buf[i] != ar934x_nfc_read_byte(mtd)) + return -EFAULT; + + return 0; +} + +static void +ar934x_nfc_hw_init(struct ar934x_nfc *nfc) +{ + struct ar934x_nfc_platform_data *pdata; + + pdata = ar934x_nfc_get_platform_data(nfc); + if (pdata->hw_reset) { + pdata->hw_reset(true); + pdata->hw_reset(false); + } + + /* + * setup timings + * TODO: make it configurable via platform data + */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ, + AR934X_NFC_TIME_SEQ_DEFAULT); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN, + AR934X_NFC_TIMINGS_ASYN_DEFAULT); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN, + AR934X_NFC_TIMINGS_SYN_DEFAULT); + + /* disable WP on all chips, and select chip 0 */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0); + + /* initialize Control register */ + nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN; + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + if (nfc->small_page) { + /* Setup generic sequence register for small page reads. */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL, + AR934X_NFC_GENSEQ_SMALL_PAGE_READ); + } +} + +static void +ar934x_nfc_restart(struct ar934x_nfc *nfc) +{ + u32 ctrl_reg; + + if (nfc->select_chip) + nfc->select_chip(-1); + + ctrl_reg = nfc->ctrl_reg; + ar934x_nfc_hw_init(nfc); + nfc->ctrl_reg = ctrl_reg; + + if (nfc->select_chip) + nfc->select_chip(0); + + ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET); +} + +static irqreturn_t +ar934x_nfc_irq_handler(int irq, void *data) +{ + struct ar934x_nfc *nfc = data; + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK); + if (status) { + nfc_dbg(nfc, "got IRQ, status:%08x\n", status); + + nfc->irq_status = status; + nfc->spurious_irq_expected = true; + wake_up(&nfc->irq_waitq); + } else { + if (nfc->spurious_irq_expected) { + nfc->spurious_irq_expected = false; + } else { + dev_warn(nfc->parent, "spurious interrupt\n"); + } + } + + return IRQ_HANDLED; +} + +static int __devinit +ar934x_nfc_init_tail(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + struct nand_chip *chip = &nfc->nand_chip; + u32 ctrl; + u32 t; + int err; + + switch (mtd->oobsize) { + case 16: + case 64: + case 128: + ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize); + break; + + default: + dev_err(nfc->parent, "unsupported OOB size: %d bytes\n", + mtd->oobsize); + return -ENXIO; + } + + ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN; + + switch (mtd->erasesize / mtd->writesize) { + case 32: + t = AR934X_NFC_CTRL_BLOCK_SIZE_32; + break; + + case 64: + t = AR934X_NFC_CTRL_BLOCK_SIZE_64; + break; + + case 128: + t = AR934X_NFC_CTRL_BLOCK_SIZE_128; + break; + + case 256: + t = AR934X_NFC_CTRL_BLOCK_SIZE_256; + break; + + default: + dev_err(nfc->parent, "unsupported block size: %u\n", + mtd->erasesize / mtd->writesize); + return -ENXIO; + } + + ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S; + + switch (mtd->writesize) { + case 256: + nfc->small_page = 1; + t = AR934X_NFC_CTRL_PAGE_SIZE_256; + break; + + case 512: + nfc->small_page = 1; + t = AR934X_NFC_CTRL_PAGE_SIZE_512; + break; + + case 1024: + t = AR934X_NFC_CTRL_PAGE_SIZE_1024; + break; + + case 2048: + t = AR934X_NFC_CTRL_PAGE_SIZE_2048; + break; + + case 4096: + t = AR934X_NFC_CTRL_PAGE_SIZE_4096; + break; + + case 8192: + t = AR934X_NFC_CTRL_PAGE_SIZE_8192; + break; + + case 16384: + t = AR934X_NFC_CTRL_PAGE_SIZE_16384; + break; + + default: + dev_err(nfc->parent, "unsupported write size: %d bytes\n", + mtd->writesize); + return -ENXIO; + } + + ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S; + + if (nfc->small_page) { + ctrl |= AR934X_NFC_CTRL_SMALL_PAGE; + + if (chip->chipsize > (32 << 20)) { + nfc->addr_count0 = 4; + nfc->addr_count1 = 3; + } else if (chip->chipsize > (2 << 16)) { + nfc->addr_count0 = 3; + nfc->addr_count1 = 2; + } else { + nfc->addr_count0 = 2; + nfc->addr_count1 = 1; + } + } else { + if (chip->chipsize > (128 << 20)) { + nfc->addr_count0 = 5; + nfc->addr_count1 = 3; + } else if (chip->chipsize > (8 << 16)) { + nfc->addr_count0 = 4; + nfc->addr_count1 = 2; + } else { + nfc->addr_count0 = 3; + nfc->addr_count1 = 1; + } + } + + ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S; + ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S; + + nfc->ctrl_reg = ctrl; + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_free_buf(nfc); + err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize); + + return err; +} + +static int __devinit +ar934x_nfc_probe(struct platform_device *pdev) +{ + static const char *part_probes[] = { "cmdlinepart", NULL, }; + struct ar934x_nfc_platform_data *pdata; + struct ar934x_nfc *nfc; + struct resource *res; + struct mtd_info *mtd; + struct nand_chip *nand; + struct mtd_part_parser_data ppdata; + int ret; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { + dev_err(&pdev->dev, "no platform data defined\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get I/O memory\n"); + return -EINVAL; + } + + nfc = kzalloc(sizeof(struct ar934x_nfc), GFP_KERNEL); + if (!nfc) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + return -ENOMEM; + } + + nfc->base = ioremap(res->start, resource_size(res)); + if (nfc->base == NULL) { + dev_err(&pdev->dev, "failed to remap I/O memory\n"); + ret = -ENXIO; + goto err_free_nand; + } + + nfc->irq = platform_get_irq(pdev, 0); + if (nfc->irq < 0) { + dev_err(&pdev->dev, "no IRQ resource specified\n"); + ret = -EINVAL; + goto err_unmap; + } + + init_waitqueue_head(&nfc->irq_waitq); + ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED, + dev_name(&pdev->dev), nfc); + if (ret) { + dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret); + goto err_unmap; + } + + nfc->parent = &pdev->dev; + nfc->select_chip = pdata->select_chip; + + nand = &nfc->nand_chip; + mtd = &nfc->mtd; + + mtd->priv = nand; + mtd->owner = THIS_MODULE; + if (pdata->name) + mtd->name = pdata->name; + else + mtd->name = dev_name(&pdev->dev); + + nand->options = NAND_NO_AUTOINCR; + nand->chip_delay = 25; + nand->ecc.mode = NAND_ECC_SOFT; + + nand->dev_ready = ar934x_nfc_dev_ready; + nand->cmdfunc = ar934x_nfc_cmdfunc; + nand->read_byte = ar934x_nfc_read_byte; + nand->write_buf = ar934x_nfc_write_buf; + nand->read_buf = ar934x_nfc_read_buf; + nand->verify_buf = ar934x_nfc_verify_buf; + nand->select_chip = ar934x_nfc_select_chip; + + ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE); + if (ret) + goto err_free_irq; + + platform_set_drvdata(pdev, nfc); + + ar934x_nfc_hw_init(nfc); + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret); + goto err_free_buf; + } + + ret = ar934x_nfc_init_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "init tail failed, err:%d\n", ret); + goto err_free_buf; + } + + if (pdata->scan_fixup) { + ret = pdata->scan_fixup(mtd); + if (ret) + goto err_free_buf; + } + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret); + goto err_free_buf; + } + + memset(&ppdata, '\0', sizeof(ppdata)); + ret = mtd_device_parse_register(mtd, part_probes, &ppdata, + pdata->parts, pdata->nr_parts); + if (ret) { + dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret); + goto err_free_buf; + } + + return 0; + +err_free_buf: + ar934x_nfc_free_buf(nfc); +err_free_irq: + free_irq(nfc->irq, nfc); +err_unmap: + iounmap(nfc->base); +err_free_nand: + kfree(nfc); + platform_set_drvdata(pdev, NULL); + return ret; +} + +static int __devexit +ar934x_nfc_remove(struct platform_device *pdev) +{ + struct ar934x_nfc *nfc; + + nfc = platform_get_drvdata(pdev); + if (nfc) { + nand_release(&nfc->mtd); + ar934x_nfc_free_buf(nfc); + free_irq(nfc->irq, nfc); + iounmap(nfc->base); + kfree(nfc); + } + + return 0; +} + +static struct platform_driver ar934x_nfc_driver = { + .probe = ar934x_nfc_probe, + .remove = __devexit_p(ar934x_nfc_remove), + .driver = { + .name = AR934X_NFC_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ar934x_nfc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver"); +MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c new file mode 100644 index 000000000..1cb8f8240 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c @@ -0,0 +1,309 @@ +/* + * NAND flash driver for the MikroTik RouterBoard 4xx series + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This file was based on the driver for Linux 2.6.22 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/slab.h> + +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/rb4xx_cpld.h> + +#define DRV_NAME "rb4xx-nand" +#define DRV_VERSION "0.2.0" +#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" + +#define RB4XX_NAND_GPIO_READY 5 +#define RB4XX_NAND_GPIO_ALE 37 +#define RB4XX_NAND_GPIO_CLE 38 +#define RB4XX_NAND_GPIO_NCE 39 + +struct rb4xx_nand_info { + struct nand_chip chip; + struct mtd_info mtd; +}; + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb4xx_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb4xx_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (6 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static int rb4xx_nand_dev_ready(struct mtd_info *mtd) +{ + return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY); +} + +static void rb4xx_nand_write_cmd(unsigned char cmd) +{ + unsigned char data = cmd; + int err; + + err = rb4xx_cpld_write(&data, 1); + if (err) + pr_err("rb4xx_nand: write cmd failed, err=%d\n", err); +} + +static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE, + (ctrl & NAND_CLE) ? 1 : 0); + gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE, + (ctrl & NAND_ALE) ? 1 : 0); + gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE, + (ctrl & NAND_NCE) ? 0 : 1); + } + + if (cmd != NAND_CMD_NONE) + rb4xx_nand_write_cmd(cmd); +} + +static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd) +{ + unsigned char data = 0; + int err; + + err = rb4xx_cpld_read(&data, NULL, 1); + if (err) { + pr_err("rb4xx_nand: read data failed, err=%d\n", err); + data = 0xff; + } + + return data; +} + +static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf, + int len) +{ + int err; + + err = rb4xx_cpld_write(buf, len); + if (err) + pr_err("rb4xx_nand: write buf failed, err=%d\n", err); +} + +static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, + int len) +{ + int err; + + err = rb4xx_cpld_read(buf, NULL, len); + if (err) + pr_err("rb4xx_nand: read buf failed, err=%d\n", err); +} + +static int __devinit rb4xx_nand_probe(struct platform_device *pdev) +{ + struct rb4xx_nand_info *info; + int ret; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + + ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_READY); + goto err; + } + + ret = gpio_direction_input(RB4XX_NAND_GPIO_READY); + if (ret) { + dev_err(&pdev->dev, "unable to set input mode on gpio %d\n", + RB4XX_NAND_GPIO_READY); + goto err_free_gpio_ready; + } + + ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_ready; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_ale; + } + + ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_CLE); + goto err_free_gpio_ale; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_CLE); + goto err_free_gpio_cle; + } + + ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_NCE); + goto err_free_gpio_cle; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_nce; + } + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n"); + ret = -ENOMEM; + goto err_free_gpio_nce; + } + + info->chip.priv = &info; + info->mtd.priv = &info->chip; + info->mtd.owner = THIS_MODULE; + + info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; + info->chip.dev_ready = rb4xx_nand_dev_ready; + info->chip.read_byte = rb4xx_nand_read_byte; + info->chip.write_buf = rb4xx_nand_write_buf; + info->chip.read_buf = rb4xx_nand_read_buf; +#if 0 + info->chip.verify_buf = rb4xx_nand_verify_buf; +#endif + + info->chip.chip_delay = 25; + info->chip.ecc.mode = NAND_ECC_SOFT; + info->chip.options |= NAND_NO_AUTOINCR; + + platform_set_drvdata(pdev, info); + + ret = nand_scan_ident(&info->mtd, 1, NULL); + if (ret) { + ret = -ENXIO; + goto err_free_info; + } + + if (info->mtd.writesize == 512) + info->chip.ecc.layout = &rb4xx_nand_ecclayout; + + ret = nand_scan_tail(&info->mtd); + if (ret) { + return -ENXIO; + goto err_set_drvdata; + } + + mtd_device_register(&info->mtd, rb4xx_nand_partitions, + ARRAY_SIZE(rb4xx_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&info->mtd); +err_set_drvdata: + platform_set_drvdata(pdev, NULL); +err_free_info: + kfree(info); +err_free_gpio_nce: + gpio_free(RB4XX_NAND_GPIO_NCE); +err_free_gpio_cle: + gpio_free(RB4XX_NAND_GPIO_CLE); +err_free_gpio_ale: + gpio_free(RB4XX_NAND_GPIO_ALE); +err_free_gpio_ready: + gpio_free(RB4XX_NAND_GPIO_READY); +err: + return ret; +} + +static int __devexit rb4xx_nand_remove(struct platform_device *pdev) +{ + struct rb4xx_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); + kfree(info); + gpio_free(RB4XX_NAND_GPIO_NCE); + gpio_free(RB4XX_NAND_GPIO_CLE); + gpio_free(RB4XX_NAND_GPIO_ALE); + gpio_free(RB4XX_NAND_GPIO_READY); + + return 0; +} + +static struct platform_driver rb4xx_nand_driver = { + .probe = rb4xx_nand_probe, + .remove = __devexit_p(rb4xx_nand_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb4xx_nand_init(void) +{ + return platform_driver_register(&rb4xx_nand_driver); +} + +static void __exit rb4xx_nand_exit(void) +{ + platform_driver_unregister(&rb4xx_nand_driver); +} + +module_init(rb4xx_nand_init); +module_exit(rb4xx_nand_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c new file mode 100644 index 000000000..251e18220 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c @@ -0,0 +1,367 @@ +/* + * NAND flash driver for the MikroTik RouterBOARD 750 + * + * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/mach-rb750.h> + +#define DRV_NAME "rb750-nand" +#define DRV_VERSION "0.1.0" +#define DRV_DESC "NAND flash driver for the RouterBOARD 750" + +#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) +#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) +#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) +#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) +#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) +#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) + +#define RB750_NAND_DATA_SHIFT 1 +#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) +#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) +#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ + RB750_NAND_NRE | RB750_NAND_NWE) + +struct rb750_nand_info { + struct nand_chip chip; + struct mtd_info mtd; + struct rb7xx_nand_platform_data *pdata; +}; + +static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) +{ + return container_of(mtd, struct rb750_nand_info, mtd); +} + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb750_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb750_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void rb750_nand_write(const u8 *buf, unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 out; + u32 t; + unsigned i; + + /* set data lines to output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); + + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); + out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); + for (i = 0; i != len; i++) { + u32 data; + + data = buf[i]; + data <<= RB750_NAND_DATA_SHIFT; + data |= out; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + + __raw_writel(data | RB750_NAND_NWE, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + /* set data lines to input mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OE); +} + +static int rb750_nand_read_verify(u8 *read_buf, unsigned len, + const u8 *verify_buf) +{ + void __iomem *base = ath79_gpio_base; + unsigned i; + + for (i = 0; i < len; i++) { + u8 data; + + /* activate RE line */ + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + + /* read input lines */ + data = __raw_readl(base + AR71XX_GPIO_REG_IN) >> + RB750_NAND_DATA_SHIFT; + + /* deactivate RE line */ + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_SET); + + if (read_buf) + read_buf[i] = data; + else if (verify_buf && verify_buf[i] != data) + return -EFAULT; + } + + return 0; +} + +static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct rb750_nand_info *rbinfo = mtd_to_rbinfo(mtd); + void __iomem *base = ath79_gpio_base; + u32 t; + + if (chip >= 0) { + rbinfo->pdata->enable_pins(); + + /* set input mode for data lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_INPUT_BITS, + base + AR71XX_GPIO_REG_OE); + + /* deactivate RE and WE lines */ + __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, + base + AR71XX_GPIO_REG_SET); + /* flush write */ + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); + + /* activate CE line */ + __raw_writel(rbinfo->pdata->nce_line, + base + AR71XX_GPIO_REG_CLEAR); + } else { + /* deactivate CE line */ + __raw_writel(rbinfo->pdata->nce_line, + base + AR71XX_GPIO_REG_SET); + /* flush write */ + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); + + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY, + base + AR71XX_GPIO_REG_OE); + + rbinfo->pdata->disable_pins(); + } +} + +static int rb750_nand_dev_ready(struct mtd_info *mtd) +{ + void __iomem *base = ath79_gpio_base; + + return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY); +} + +static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *base = ath79_gpio_base; + u32 t; + + t = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); + t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; + t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; + + __raw_writel(t, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + if (cmd != NAND_CMD_NONE) { + u8 t = cmd; + rb750_nand_write(&t, 1); + } +} + +static u8 rb750_nand_read_byte(struct mtd_info *mtd) +{ + u8 data = 0; + rb750_nand_read_verify(&data, 1, NULL); + return data; +} + +static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + rb750_nand_read_verify(buf, len, NULL); +} + +static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + rb750_nand_write(buf, len); +} + +static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + return rb750_nand_read_verify(NULL, len, buf); +} + +static void __init rb750_nand_gpio_init(struct rb750_nand_info *info) +{ + void __iomem *base = ath79_gpio_base; + u32 out; + u32 t; + + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* setup output levels */ + __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, + base + AR71XX_GPIO_REG_SET); + + __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, + base + AR71XX_GPIO_REG_CLEAR); + + /* setup input lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~(RB750_NAND_INPUT_BITS), base + AR71XX_GPIO_REG_OE); + + /* setup output lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= RB750_NAND_OUTPUT_BITS; + t |= info->pdata->nce_line; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + + info->pdata->latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); +} + +static int __devinit rb750_nand_probe(struct platform_device *pdev) +{ + struct rb750_nand_info *info; + struct rb7xx_nand_platform_data *pdata; + int ret; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->chip.priv = &info; + info->mtd.priv = &info->chip; + info->mtd.owner = THIS_MODULE; + + info->chip.select_chip = rb750_nand_select_chip; + info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; + info->chip.dev_ready = rb750_nand_dev_ready; + info->chip.read_byte = rb750_nand_read_byte; + info->chip.write_buf = rb750_nand_write_buf; + info->chip.read_buf = rb750_nand_read_buf; + info->chip.verify_buf = rb750_nand_verify_buf; + + info->chip.chip_delay = 25; + info->chip.ecc.mode = NAND_ECC_SOFT; + info->chip.options |= NAND_NO_AUTOINCR; + + info->pdata = pdata; + + platform_set_drvdata(pdev, info); + + rb750_nand_gpio_init(info); + + ret = nand_scan_ident(&info->mtd, 1, NULL); + if (ret) { + ret = -ENXIO; + goto err_free_info; + } + + if (info->mtd.writesize == 512) + info->chip.ecc.layout = &rb750_nand_ecclayout; + + ret = nand_scan_tail(&info->mtd); + if (ret) { + return -ENXIO; + goto err_set_drvdata; + } + + ret = mtd_device_register(&info->mtd, rb750_nand_partitions, + ARRAY_SIZE(rb750_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&info->mtd); +err_set_drvdata: + platform_set_drvdata(pdev, NULL); +err_free_info: + kfree(info); + return ret; +} + +static int __devexit rb750_nand_remove(struct platform_device *pdev) +{ + struct rb750_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); + kfree(info); + + return 0; +} + +static struct platform_driver rb750_nand_driver = { + .probe = rb750_nand_probe, + .remove = __devexit_p(rb750_nand_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb750_nand_init(void) +{ + return platform_driver_register(&rb750_nand_driver); +} + +static void __exit rb750_nand_exit(void) +{ + platform_driver_unregister(&rb750_nand_driver); +} + +module_init(rb750_nand_init); +module_exit(rb750_nand_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c new file mode 100644 index 000000000..674df6602 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/magic.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#define TPLINK_NUM_PARTS 5 +#define TPLINK_HEADER_V1 0x01000000 +#define MD5SUM_LEN 16 + +#define TPLINK_ART_LEN 0x10000 +#define TPLINK_KERNEL_OFFS 0x20000 + +struct tplink_fw_header { + uint32_t version; /* header version */ + char vendor_name[24]; + char fw_version[36]; + uint32_t hw_id; /* hardware id */ + uint32_t hw_rev; /* hardware revision */ + uint32_t unk1; + uint8_t md5sum1[MD5SUM_LEN]; + uint32_t unk2; + uint8_t md5sum2[MD5SUM_LEN]; + uint32_t unk3; + uint32_t kernel_la; /* kernel load address */ + uint32_t kernel_ep; /* kernel entry point */ + uint32_t fw_length; /* total length of the firmware */ + uint32_t kernel_ofs; /* kernel data offset */ + uint32_t kernel_len; /* kernel data length */ + uint32_t rootfs_ofs; /* rootfs data offset */ + uint32_t rootfs_len; /* rootfs data length */ + uint32_t boot_ofs; /* bootloader data offset */ + uint32_t boot_len; /* bootloader data length */ + uint8_t pad[360]; +} __attribute__ ((packed)); + +static struct tplink_fw_header * +tplink_read_header(struct mtd_info *mtd, size_t offset) +{ + struct tplink_fw_header *header; + size_t header_len; + size_t retlen; + int ret; + u32 t; + + header = vmalloc(sizeof(*header)); + if (!header) + goto err; + + header_len = sizeof(struct tplink_fw_header); + ret = mtd->read(mtd, offset, header_len, &retlen, + (unsigned char *) header); + if (ret) + goto err_free_header; + + if (retlen != header_len) + goto err_free_header; + + /* sanity checks */ + t = be32_to_cpu(header->version); + if (t != TPLINK_HEADER_V1) + goto err_free_header; + + t = be32_to_cpu(header->kernel_ofs); + if (t != header_len) + goto err_free_header; + + return header; + +err_free_header: + vfree(header); +err: + return NULL; +} + +static int tplink_check_rootfs_magic(struct mtd_info *mtd, size_t offset) +{ + u32 magic; + size_t retlen; + int ret; + + ret = mtd->read(mtd, offset, sizeof(magic), &retlen, + (unsigned char *) &magic); + if (ret) + return ret; + + if (retlen != sizeof(magic)) + return -EIO; + + if (le32_to_cpu(magic) != SQUASHFS_MAGIC && + magic != 0x19852003) + return -EINVAL; + + return 0; +} + +static int tplink_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct mtd_partition *parts; + struct tplink_fw_header *header; + int nr_parts; + size_t offset; + size_t art_offset; + size_t rootfs_offset; + size_t squashfs_offset; + int ret; + + nr_parts = TPLINK_NUM_PARTS; + parts = kzalloc(nr_parts * sizeof(struct mtd_partition), GFP_KERNEL); + if (!parts) { + ret = -ENOMEM; + goto err; + } + + offset = TPLINK_KERNEL_OFFS; + + header = tplink_read_header(master, offset); + if (!header) { + pr_notice("%s: no TP-Link header found\n", master->name); + ret = -ENODEV; + goto err_free_parts; + } + + squashfs_offset = offset + sizeof(struct tplink_fw_header) + + be32_to_cpu(header->kernel_len); + + ret = tplink_check_rootfs_magic(master, squashfs_offset); + if (ret == 0) + rootfs_offset = squashfs_offset; + else + rootfs_offset = offset + be32_to_cpu(header->rootfs_ofs); + + art_offset = master->size - TPLINK_ART_LEN; + + parts[0].name = "u-boot"; + parts[0].offset = 0; + parts[0].size = offset; + parts[0].mask_flags = MTD_WRITEABLE; + + parts[1].name = "kernel"; + parts[1].offset = offset; + parts[1].size = rootfs_offset - offset; + + parts[2].name = "rootfs"; + parts[2].offset = rootfs_offset; + parts[2].size = art_offset - rootfs_offset; + + parts[3].name = "art"; + parts[3].offset = art_offset; + parts[3].size = TPLINK_ART_LEN; + parts[3].mask_flags = MTD_WRITEABLE; + + parts[4].name = "firmware"; + parts[4].offset = offset; + parts[4].size = art_offset - offset; + + vfree(header); + + *pparts = parts; + return nr_parts; + +err_free_parts: + kfree(parts); +err: + *pparts = NULL; + return ret; +} + +static struct mtd_part_parser tplink_parser = { + .owner = THIS_MODULE, + .parse_fn = tplink_parse_partitions, + .name = "tp-link", +}; + +static int __init tplink_parser_init(void) +{ + return register_mtd_parser(&tplink_parser); +} + +module_init(tplink_parser_init); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); diff --git a/target/linux/ar71xx/files/drivers/mtd/wrt160nl_part.c b/target/linux/ar71xx/files/drivers/mtd/wrt160nl_part.c new file mode 100644 index 000000000..72927f6f2 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/wrt160nl_part.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2009 Christian Daniel <cd@maintech.de> + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * TRX flash partition table. + * Based on ar7 map by Felix Fietkau <nbd@openwrt.org> + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +struct cybertan_header { + char magic[4]; + u8 res1[4]; + char fw_date[3]; + char fw_ver[3]; + char id[4]; + char hw_ver; + char unused; + u8 flags[2]; + u8 res2[10]; +}; + +#define TRX_PARTS 6 +#define TRX_MAGIC 0x30524448 +#define TRX_MAX_OFFSET 3 + +struct trx_header { + uint32_t magic; /* "HDR0" */ + uint32_t len; /* Length of file including header */ + uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ + uint32_t flag_version; /* 0:15 flags, 16:31 version */ + uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ +}; + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +struct uimage_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data» Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +}; + +struct wrt160nl_header { + struct cybertan_header cybertan; + struct trx_header trx; + struct uimage_header uimage; +} __attribute__ ((packed)); + +#define WRT160NL_UBOOT_LEN 0x40000 +#define WRT160NL_ART_LEN 0x10000 +#define WRT160NL_NVRAM_LEN 0x10000 + +static int wrt160nl_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct wrt160nl_header *header; + struct trx_header *theader; + struct uimage_header *uheader; + struct mtd_partition *trx_parts; + size_t retlen; + unsigned int kernel_len; + unsigned int uboot_len; + unsigned int nvram_len; + unsigned int art_len; + int ret; + + uboot_len = max_t(unsigned int, master->erasesize, WRT160NL_UBOOT_LEN); + nvram_len = max_t(unsigned int, master->erasesize, WRT160NL_NVRAM_LEN); + art_len = max_t(unsigned int, master->erasesize, WRT160NL_ART_LEN); + + trx_parts = kzalloc(TRX_PARTS * sizeof(struct mtd_partition), + GFP_KERNEL); + if (!trx_parts) { + ret = -ENOMEM; + goto out; + } + + header = vmalloc(sizeof(*header)); + if (!header) { + return -ENOMEM; + goto free_parts; + } + + ret = master->read(master, uboot_len, sizeof(*header), + &retlen, (void *) header); + if (ret) + goto free_hdr; + + if (retlen != sizeof(*header)) { + ret = -EIO; + goto free_hdr; + } + + if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { + printk(KERN_NOTICE "%s: no WRT160NL signature found\n", + master->name); + goto free_hdr; + } + + theader = &header->trx; + if (le32_to_cpu(theader->magic) != TRX_MAGIC) { + printk(KERN_NOTICE "%s: no TRX header found\n", master->name); + goto free_hdr; + } + + uheader = &header->uimage; + if (uheader->ih_magic != IH_MAGIC) { + printk(KERN_NOTICE "%s: no uImage found\n", master->name); + goto free_hdr; + } + + kernel_len = le32_to_cpu(theader->offsets[1]) + + sizeof(struct cybertan_header); + + trx_parts[0].name = "u-boot"; + trx_parts[0].offset = 0; + trx_parts[0].size = uboot_len; + trx_parts[0].mask_flags = MTD_WRITEABLE; + + trx_parts[1].name = "kernel"; + trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; + trx_parts[1].size = kernel_len; + trx_parts[1].mask_flags = 0; + + trx_parts[2].name = "rootfs"; + trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; + trx_parts[2].size = master->size - uboot_len - nvram_len - art_len - + trx_parts[1].size; + trx_parts[2].mask_flags = 0; + + trx_parts[3].name = "nvram"; + trx_parts[3].offset = master->size - nvram_len - art_len; + trx_parts[3].size = nvram_len; + trx_parts[3].mask_flags = MTD_WRITEABLE; + + trx_parts[4].name = "art"; + trx_parts[4].offset = master->size - art_len; + trx_parts[4].size = art_len; + trx_parts[4].mask_flags = MTD_WRITEABLE; + + trx_parts[5].name = "firmware"; + trx_parts[5].offset = uboot_len; + trx_parts[5].size = master->size - uboot_len - nvram_len - art_len; + trx_parts[5].mask_flags = 0; + + vfree(header); + + *pparts = trx_parts; + return TRX_PARTS; + +free_hdr: + vfree(header); +free_parts: + kfree(trx_parts); +out: + return ret; +} + +static struct mtd_part_parser wrt160nl_parser = { + .owner = THIS_MODULE, + .parse_fn = wrt160nl_parse_partitions, + .name = "wrt160nl", +}; + +static int __init wrt160nl_parser_init(void) +{ + return register_mtd_parser(&wrt160nl_parser); +} + +module_init(wrt160nl_parser_init); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Christian Daniel <cd@maintech.de>"); diff --git a/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c new file mode 100644 index 000000000..b41eb5481 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c @@ -0,0 +1,294 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips + * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This driver was base on: net/dsa/mv88e6060.c + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips + * Copyright (c) 2008-2009 Marvell Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/list.h> +#include <linux/netdevice.h> +#include <linux/phy.h> +#include <net/dsa.h> + +#define REG_BASE 0x10 +#define REG_PHY(p) (REG_BASE + (p)) +#define REG_PORT(p) (REG_BASE + 8 + (p)) +#define REG_GLOBAL (REG_BASE + 0x0f) +#define NUM_PORTS 7 + +static int reg_read(struct dsa_switch *ds, int addr, int reg) +{ + return mdiobus_read(ds->master_mii_bus, addr, reg); +} + +#define REG_READ(addr, reg) \ + ({ \ + int __ret; \ + \ + __ret = reg_read(ds, addr, reg); \ + if (__ret < 0) \ + return __ret; \ + __ret; \ + }) + + +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) +{ + return mdiobus_write(ds->master_mii_bus, addr, reg, val); +} + +#define REG_WRITE(addr, reg, val) \ + ({ \ + int __ret; \ + \ + __ret = reg_write(ds, addr, reg, val); \ + if (__ret < 0) \ + return __ret; \ + }) + +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) +{ + int ret; + + ret = mdiobus_read(bus, REG_PORT(0), 0x03); + if (ret >= 0) { + ret &= 0xfff0; + if (ret == 0x1530) + return "Marvell 88E6063"; + } + + return NULL; +} + +static int mv88e6063_switch_reset(struct dsa_switch *ds) +{ + int i; + int ret; + + /* + * Set all ports to the disabled state. + */ + for (i = 0; i < NUM_PORTS; i++) { + ret = REG_READ(REG_PORT(i), 0x04); + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); + } + + /* + * Wait for transmit queues to drain. + */ + msleep(2); + + /* + * Reset the switch. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); + + /* + * Wait up to one second for reset to complete. + */ + for (i = 0; i < 1000; i++) { + ret = REG_READ(REG_GLOBAL, 0x00); + if ((ret & 0x8000) == 0x0000) + break; + + msleep(1); + } + if (i == 1000) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6063_setup_global(struct dsa_switch *ds) +{ + /* + * Disable discarding of frames with excessive collisions, + * set the maximum frame size to 1536 bytes, and mask all + * interrupt sources. + */ + REG_WRITE(REG_GLOBAL, 0x04, 0x0800); + + /* + * Enable automatic address learning, set the address + * database size to 1024 entries, and set the default aging + * time to 5 minutes. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); + + return 0; +} + +static int mv88e6063_setup_port(struct dsa_switch *ds, int p) +{ + int addr = REG_PORT(p); + + /* + * Do not force flow control, disable Ingress and Egress + * Header tagging, disable VLAN tunneling, and set the port + * state to Forwarding. Additionally, if this is the CPU + * port, enable Ingress and Egress Trailer tagging mode. + */ + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); + + /* + * Port based VLAN map: give each port its own address + * database, allow the CPU port to talk to each of the 'real' + * ports, and allow each of the 'real' ports to only talk to + * the CPU port. + */ + REG_WRITE(addr, 0x06, + ((p & 0xf) << 12) | + (dsa_is_cpu_port(ds, p) ? + ds->phys_port_mask : + (1 << ds->dst->cpu_port))); + + /* + * Port Association Vector: when learning source addresses + * of packets, add the address to the address database using + * a port bitmap that has only the bit for this port set and + * the other bits clear. + */ + REG_WRITE(addr, 0x0b, 1 << p); + + return 0; +} + +static int mv88e6063_setup(struct dsa_switch *ds) +{ + int i; + int ret; + + ret = mv88e6063_switch_reset(ds); + if (ret < 0) + return ret; + + /* @@@ initialise atu */ + + ret = mv88e6063_setup_global(ds); + if (ret < 0) + return ret; + + for (i = 0; i < NUM_PORTS; i++) { + ret = mv88e6063_setup_port(ds, i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) +{ + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); + + return 0; +} + +static int mv88e6063_port_to_phy_addr(int port) +{ + if (port >= 0 && port <= NUM_PORTS) + return REG_PHY(port); + return -1; +} + +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_read(ds, addr, regnum); +} + +static int +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_write(ds, addr, regnum, val); +} + +static void mv88e6063_poll_link(struct dsa_switch *ds) +{ + int i; + + for (i = 0; i < DSA_MAX_PORTS; i++) { + struct net_device *dev; + int uninitialized_var(port_status); + int link; + int speed; + int duplex; + int fc; + + dev = ds->ports[i]; + if (dev == NULL) + continue; + + link = 0; + if (dev->flags & IFF_UP) { + port_status = reg_read(ds, REG_PORT(i), 0x00); + if (port_status < 0) + continue; + + link = !!(port_status & 0x1000); + } + + if (!link) { + if (netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + continue; + } + + speed = (port_status & 0x0100) ? 100 : 10; + duplex = (port_status & 0x0200) ? 1 : 0; + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; + + if (!netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " + "flow control %sabled\n", dev->name, + speed, duplex ? "full" : "half", + fc ? "en" : "dis"); + netif_carrier_on(dev); + } + } +} + +static struct dsa_switch_driver mv88e6063_switch_driver = { + .tag_protocol = htons(ETH_P_TRAILER), + .probe = mv88e6063_probe, + .setup = mv88e6063_setup, + .set_addr = mv88e6063_set_addr, + .phy_read = mv88e6063_phy_read, + .phy_write = mv88e6063_phy_write, + .poll_link = mv88e6063_poll_link, +}; + +static int __init mv88e6063_init(void) +{ + register_switch_driver(&mv88e6063_switch_driver); + return 0; +} +module_init(mv88e6063_init); + +static void __exit mv88e6063_cleanup(void) +{ + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig new file mode 100644 index 000000000..42d544f73 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig @@ -0,0 +1,33 @@ +config AG71XX + tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support" + depends on ATH79 + select PHYLIB + help + If you wish to compile a kernel for AR7XXX/91XXX and enable + ethernet support, then you should always answer Y to this. + +if AG71XX + +config AG71XX_DEBUG + bool "Atheros AR71xx built-in ethernet driver debugging" + default n + help + Atheros AR71xx built-in ethernet driver debugging messages. + +config AG71XX_DEBUG_FS + bool "Atheros AR71xx built-in ethernet driver debugfs support" + depends on DEBUG_FS + default n + help + Say Y, if you need access to various statistics provided by + the ag71xx driver. + +config AG71XX_AR8216_SUPPORT + bool "special support for the Atheros AR8216 switch" + default n + default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU + help + Say 'y' here if you want to enable special support for the + Atheros AR8216 switch found on some boards. + +endif diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile new file mode 100644 index 000000000..b3ec4084c --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the Atheros AR71xx built-in ethernet macs +# + +ag71xx-y += ag71xx_main.o +ag71xx-y += ag71xx_ethtool.o +ag71xx-y += ag71xx_phy.o +ag71xx-y += ag71xx_mdio.o +ag71xx-y += ag71xx_ar7240.o + +ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o +ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o + +obj-$(CONFIG_AG71XX) += ag71xx.o + diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h new file mode 100644 index 000000000..b9d95adaf --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h @@ -0,0 +1,477 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __AG71XX_H +#define __AG71XX_H + +#include <linux/kernel.h> +#include <linux/version.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/random.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/ethtool.h> +#include <linux/etherdevice.h> +#include <linux/if_vlan.h> +#include <linux/phy.h> +#include <linux/skbuff.h> +#include <linux/dma-mapping.h> +#include <linux/workqueue.h> + +#include <linux/bitops.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ag71xx_platform.h> + +#define AG71XX_DRV_NAME "ag71xx" +#define AG71XX_DRV_VERSION "0.5.35" + +#define AG71XX_NAPI_WEIGHT 64 +#define AG71XX_OOM_REFILL (1 + HZ/10) + +#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) +#define AG71XX_INT_TX (AG71XX_INT_TX_PS) +#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) + +#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) +#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) + +#define AG71XX_TX_MTU_LEN 1540 +#define AG71XX_RX_PKT_SIZE \ + (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) +#define AG71XX_RX_BUF_SIZE (AG71XX_RX_PKT_SIZE + NET_SKB_PAD + NET_IP_ALIGN) + +#define AG71XX_TX_RING_SIZE_DEFAULT 64 +#define AG71XX_RX_RING_SIZE_DEFAULT 128 + +#define AG71XX_TX_RING_SIZE_MAX 256 +#define AG71XX_RX_RING_SIZE_MAX 256 + +#ifdef CONFIG_AG71XX_DEBUG +#define DBG(fmt, args...) pr_debug(fmt, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#define ag71xx_assert(_cond) \ +do { \ + if (_cond) \ + break; \ + printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ + BUG(); \ +} while (0) + +struct ag71xx_desc { + u32 data; + u32 ctrl; +#define DESC_EMPTY BIT(31) +#define DESC_MORE BIT(24) +#define DESC_PKTLEN_M 0xfff + u32 next; + u32 pad; +} __attribute__((aligned(4))); + +struct ag71xx_buf { + union { + struct sk_buff *skb; + void *rx_buf; + }; + struct ag71xx_desc *desc; + dma_addr_t dma_addr; + unsigned long timestamp; +}; + +struct ag71xx_ring { + struct ag71xx_buf *buf; + u8 *descs_cpu; + dma_addr_t descs_dma; + unsigned int desc_size; + unsigned int curr; + unsigned int dirty; + unsigned int size; +}; + +struct ag71xx_mdio { + struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + void __iomem *mdio_base; + struct ag71xx_mdio_platform_data *pdata; +}; + +struct ag71xx_int_stats { + unsigned long rx_pr; + unsigned long rx_be; + unsigned long rx_of; + unsigned long tx_ps; + unsigned long tx_be; + unsigned long tx_ur; + unsigned long total; +}; + +struct ag71xx_napi_stats { + unsigned long napi_calls; + unsigned long rx_count; + unsigned long rx_packets; + unsigned long rx_packets_max; + unsigned long tx_count; + unsigned long tx_packets; + unsigned long tx_packets_max; + + unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; + unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; +}; + +struct ag71xx_debug { + struct dentry *debugfs_dir; + + struct ag71xx_int_stats int_stats; + struct ag71xx_napi_stats napi_stats; +}; + +struct ag71xx { + void __iomem *mac_base; + + spinlock_t lock; + struct platform_device *pdev; + struct net_device *dev; + struct napi_struct napi; + u32 msg_enable; + + struct ag71xx_desc *stop_desc; + dma_addr_t stop_desc_dma; + + struct ag71xx_ring rx_ring; + struct ag71xx_ring tx_ring; + + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + void *phy_priv; + + unsigned int link; + unsigned int speed; + int duplex; + + struct work_struct restart_work; + struct delayed_work link_work; + struct timer_list oom_timer; + +#ifdef CONFIG_AG71XX_DEBUG_FS + struct ag71xx_debug debug; +#endif +}; + +extern struct ethtool_ops ag71xx_ethtool_ops; +void ag71xx_link_adjust(struct ag71xx *ag); + +int ag71xx_mdio_driver_init(void) __init; +void ag71xx_mdio_driver_exit(void); + +int ag71xx_phy_connect(struct ag71xx *ag); +void ag71xx_phy_disconnect(struct ag71xx *ag); +void ag71xx_phy_start(struct ag71xx *ag); +void ag71xx_phy_stop(struct ag71xx *ag); + +static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) +{ + return ag->pdev->dev.platform_data; +} + +static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) +{ + return (desc->ctrl & DESC_EMPTY) != 0; +} + +static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) +{ + return desc->ctrl & DESC_PKTLEN_M; +} + +/* Register offsets */ +#define AG71XX_REG_MAC_CFG1 0x0000 +#define AG71XX_REG_MAC_CFG2 0x0004 +#define AG71XX_REG_MAC_IPG 0x0008 +#define AG71XX_REG_MAC_HDX 0x000c +#define AG71XX_REG_MAC_MFL 0x0010 +#define AG71XX_REG_MII_CFG 0x0020 +#define AG71XX_REG_MII_CMD 0x0024 +#define AG71XX_REG_MII_ADDR 0x0028 +#define AG71XX_REG_MII_CTRL 0x002c +#define AG71XX_REG_MII_STATUS 0x0030 +#define AG71XX_REG_MII_IND 0x0034 +#define AG71XX_REG_MAC_IFCTL 0x0038 +#define AG71XX_REG_MAC_ADDR1 0x0040 +#define AG71XX_REG_MAC_ADDR2 0x0044 +#define AG71XX_REG_FIFO_CFG0 0x0048 +#define AG71XX_REG_FIFO_CFG1 0x004c +#define AG71XX_REG_FIFO_CFG2 0x0050 +#define AG71XX_REG_FIFO_CFG3 0x0054 +#define AG71XX_REG_FIFO_CFG4 0x0058 +#define AG71XX_REG_FIFO_CFG5 0x005c +#define AG71XX_REG_FIFO_RAM0 0x0060 +#define AG71XX_REG_FIFO_RAM1 0x0064 +#define AG71XX_REG_FIFO_RAM2 0x0068 +#define AG71XX_REG_FIFO_RAM3 0x006c +#define AG71XX_REG_FIFO_RAM4 0x0070 +#define AG71XX_REG_FIFO_RAM5 0x0074 +#define AG71XX_REG_FIFO_RAM6 0x0078 +#define AG71XX_REG_FIFO_RAM7 0x007c + +#define AG71XX_REG_TX_CTRL 0x0180 +#define AG71XX_REG_TX_DESC 0x0184 +#define AG71XX_REG_TX_STATUS 0x0188 +#define AG71XX_REG_RX_CTRL 0x018c +#define AG71XX_REG_RX_DESC 0x0190 +#define AG71XX_REG_RX_STATUS 0x0194 +#define AG71XX_REG_INT_ENABLE 0x0198 +#define AG71XX_REG_INT_STATUS 0x019c + +#define AG71XX_REG_FIFO_DEPTH 0x01a8 +#define AG71XX_REG_RX_SM 0x01b0 +#define AG71XX_REG_TX_SM 0x01b4 + +#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ +#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ +#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ +#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ +#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ +#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ +#define MAC_CFG1_LB BIT(8) /* Loopback mode */ +#define MAC_CFG1_SR BIT(31) /* Soft Reset */ + +#define MAC_CFG2_FDX BIT(0) +#define MAC_CFG2_CRC_EN BIT(1) +#define MAC_CFG2_PAD_CRC_EN BIT(2) +#define MAC_CFG2_LEN_CHECK BIT(4) +#define MAC_CFG2_HUGE_FRAME_EN BIT(5) +#define MAC_CFG2_IF_1000 BIT(9) +#define MAC_CFG2_IF_10_100 BIT(8) + +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ + | FIFO_CFG0_TXS | FIFO_CFG0_TXF) + +#define FIFO_CFG0_ENABLE_SHIFT 8 + +#define FIFO_CFG4_DE BIT(0) /* Drop Event */ +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG4_FC BIT(2) /* False Carrier */ +#define FIFO_CFG4_CE BIT(3) /* Code Error */ +#define FIFO_CFG4_CR BIT(4) /* CRC error */ +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ +#define FIFO_CFG4_LO BIT(6) /* Length out of range */ +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ +#define FIFO_CFG4_DR BIT(10) /* Dribble */ +#define FIFO_CFG4_LE BIT(11) /* Long Event */ +#define FIFO_CFG4_CF BIT(12) /* Control Frame */ +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ + +#define FIFO_CFG5_DE BIT(0) /* Drop Event */ +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG5_FC BIT(2) /* False Carrier */ +#define FIFO_CFG5_CE BIT(3) /* Code Error */ +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ +#define FIFO_CFG5_DR BIT(9) /* Dribble */ +#define FIFO_CFG5_CF BIT(10) /* Control Frame */ +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ +#define FIFO_CFG5_LE BIT(14) /* Long Event */ +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ +#define FIFO_CFG5_16 BIT(16) /* unknown */ +#define FIFO_CFG5_17 BIT(17) /* unknown */ +#define FIFO_CFG5_SF BIT(18) /* Short Frame */ +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ + +#define AG71XX_INT_TX_PS BIT(0) +#define AG71XX_INT_TX_UR BIT(1) +#define AG71XX_INT_TX_BE BIT(3) +#define AG71XX_INT_RX_PR BIT(4) +#define AG71XX_INT_RX_OF BIT(6) +#define AG71XX_INT_RX_BE BIT(7) + +#define MAC_IFCTL_SPEED BIT(16) + +#define MII_CFG_CLK_DIV_4 0 +#define MII_CFG_CLK_DIV_6 2 +#define MII_CFG_CLK_DIV_8 3 +#define MII_CFG_CLK_DIV_10 4 +#define MII_CFG_CLK_DIV_14 5 +#define MII_CFG_CLK_DIV_20 6 +#define MII_CFG_CLK_DIV_28 7 +#define MII_CFG_CLK_DIV_34 8 +#define MII_CFG_CLK_DIV_42 9 +#define MII_CFG_CLK_DIV_50 10 +#define MII_CFG_CLK_DIV_58 11 +#define MII_CFG_CLK_DIV_66 12 +#define MII_CFG_CLK_DIV_74 13 +#define MII_CFG_CLK_DIV_82 14 +#define MII_CFG_CLK_DIV_98 15 +#define MII_CFG_RESET BIT(31) + +#define MII_CMD_WRITE 0x0 +#define MII_CMD_READ 0x1 +#define MII_ADDR_SHIFT 8 +#define MII_IND_BUSY BIT(0) +#define MII_IND_INVALID BIT(2) + +#define TX_CTRL_TXE BIT(0) /* Tx Enable */ + +#define TX_STATUS_PS BIT(0) /* Packet Sent */ +#define TX_STATUS_UR BIT(1) /* Tx Underrun */ +#define TX_STATUS_BE BIT(3) /* Bus Error */ + +#define RX_CTRL_RXE BIT(0) /* Rx Enable */ + +#define RX_STATUS_PR BIT(0) /* Packet Received */ +#define RX_STATUS_OF BIT(2) /* Rx Overflow */ +#define RX_STATUS_BE BIT(3) /* Bus Error */ + +static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) +{ + switch (reg) { + case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: + case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM: + case AG71XX_REG_MII_CFG: + break; + + default: + BUG(); + } +} + +static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) +{ + ag71xx_check_reg_offset(ag, reg); + + __raw_writel(value, ag->mac_base + reg); + /* flush write */ + (void) __raw_readl(ag->mac_base + reg); +} + +static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) +{ + ag71xx_check_reg_offset(ag, reg); + + return __raw_readl(ag->mac_base + reg); +} + +static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) +{ + void __iomem *r; + + ag71xx_check_reg_offset(ag, reg); + + r = ag->mac_base + reg; + __raw_writel(__raw_readl(r) | mask, r); + /* flush write */ + (void)__raw_readl(r); +} + +static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) +{ + void __iomem *r; + + ag71xx_check_reg_offset(ag, reg); + + r = ag->mac_base + reg; + __raw_writel(__raw_readl(r) & ~mask, r); + /* flush write */ + (void) __raw_readl(r); +} + +static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) +{ + ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); +} + +static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) +{ + ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); +} + +#ifdef CONFIG_AG71XX_AR8216_SUPPORT +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, + int pktlen); +static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ + return ag71xx_get_pdata(ag)->has_ar8216; +} +#else +static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, + struct sk_buff *skb) +{ +} + +static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, + struct sk_buff *skb, + int pktlen) +{ + return 0; +} +static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ + return 0; +} +#endif + +#ifdef CONFIG_AG71XX_DEBUG_FS +int ag71xx_debugfs_root_init(void); +void ag71xx_debugfs_root_exit(void); +int ag71xx_debugfs_init(struct ag71xx *ag); +void ag71xx_debugfs_exit(struct ag71xx *ag); +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); +#else +static inline int ag71xx_debugfs_root_init(void) { return 0; } +static inline void ag71xx_debugfs_root_exit(void) {} +static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } +static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} +static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, + u32 status) {} +static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, + int rx, int tx) {} +#endif /* CONFIG_AG71XX_DEBUG_FS */ + +void ag71xx_ar7240_start(struct ag71xx *ag); +void ag71xx_ar7240_stop(struct ag71xx *ag); +int ag71xx_ar7240_init(struct ag71xx *ag); +void ag71xx_ar7240_cleanup(struct ag71xx *ag); + +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg); +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val); + +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr); +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr, u16 reg_val); + +#endif /* _AG71XX_H */ diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c new file mode 100644 index 000000000..49f077520 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c @@ -0,0 +1,1193 @@ +/* + * Driver for the built-in ethernet switch of the Atheros AR7240 SoC + * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include <linux/etherdevice.h> +#include <linux/list.h> +#include <linux/netdevice.h> +#include <linux/phy.h> +#include <linux/mii.h> +#include <linux/bitops.h> +#include <linux/switch.h> +#include "ag71xx.h" + +#define BITM(_count) (BIT(_count) - 1) +#define BITS(_shift, _count) (BITM(_count) << _shift) + +#define AR7240_REG_MASK_CTRL 0x00 +#define AR7240_MASK_CTRL_REVISION_M BITM(8) +#define AR7240_MASK_CTRL_VERSION_M BITM(8) +#define AR7240_MASK_CTRL_VERSION_S 8 +#define AR7240_MASK_CTRL_VERSION_AR7240 0x01 +#define AR7240_MASK_CTRL_VERSION_AR934X 0x02 +#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) + +#define AR7240_REG_MAC_ADDR0 0x20 +#define AR7240_REG_MAC_ADDR1 0x24 + +#define AR7240_REG_FLOOD_MASK 0x2c +#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) + +#define AR7240_REG_GLOBAL_CTRL 0x30 +#define AR7240_GLOBAL_CTRL_MTU_M BITM(12) + +#define AR7240_REG_VTU 0x0040 +#define AR7240_VTU_OP BITM(3) +#define AR7240_VTU_OP_NOOP 0x0 +#define AR7240_VTU_OP_FLUSH 0x1 +#define AR7240_VTU_OP_LOAD 0x2 +#define AR7240_VTU_OP_PURGE 0x3 +#define AR7240_VTU_OP_REMOVE_PORT 0x4 +#define AR7240_VTU_ACTIVE BIT(3) +#define AR7240_VTU_FULL BIT(4) +#define AR7240_VTU_PORT BITS(8, 4) +#define AR7240_VTU_PORT_S 8 +#define AR7240_VTU_VID BITS(16, 12) +#define AR7240_VTU_VID_S 16 +#define AR7240_VTU_PRIO BITS(28, 3) +#define AR7240_VTU_PRIO_S 28 +#define AR7240_VTU_PRIO_EN BIT(31) + +#define AR7240_REG_VTU_DATA 0x0044 +#define AR7240_VTUDATA_MEMBER BITS(0, 10) +#define AR7240_VTUDATA_VALID BIT(11) + +#define AR7240_REG_ATU 0x50 +#define AR7240_ATU_FLUSH_ALL 0x1 + +#define AR7240_REG_AT_CTRL 0x5c +#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR7240_AT_CTRL_AGE_EN BIT(17) +#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18) +#define AR7240_AT_CTRL_RESERVED BIT(19) +#define AR7240_AT_CTRL_ARP_EN BIT(20) + +#define AR7240_REG_TAG_PRIORITY 0x70 + +#define AR7240_REG_SERVICE_TAG 0x74 +#define AR7240_SERVICE_TAG_M BITM(16) + +#define AR7240_REG_CPU_PORT 0x78 +#define AR7240_MIRROR_PORT_S 4 +#define AR7240_CPU_PORT_EN BIT(8) + +#define AR7240_REG_MIB_FUNCTION0 0x80 +#define AR7240_MIB_TIMER_M BITM(16) +#define AR7240_MIB_AT_HALF_EN BIT(16) +#define AR7240_MIB_BUSY BIT(17) +#define AR7240_MIB_FUNC_S 24 +#define AR7240_MIB_FUNC_M BITM(3) +#define AR7240_MIB_FUNC_NO_OP 0x0 +#define AR7240_MIB_FUNC_FLUSH 0x1 +#define AR7240_MIB_FUNC_CAPTURE 0x3 + +#define AR7240_REG_MDIO_CTRL 0x98 +#define AR7240_MDIO_CTRL_DATA_M BITM(16) +#define AR7240_MDIO_CTRL_REG_ADDR_S 16 +#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 +#define AR7240_MDIO_CTRL_CMD_WRITE 0 +#define AR7240_MDIO_CTRL_CMD_READ BIT(27) +#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) +#define AR7240_MDIO_CTRL_BUSY BIT(31) + +#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) +#define AR7240_PORT_STATUS_SPEED_S 0 +#define AR7240_PORT_STATUS_SPEED_M BITM(2) +#define AR7240_PORT_STATUS_SPEED_10 0 +#define AR7240_PORT_STATUS_SPEED_100 1 +#define AR7240_PORT_STATUS_SPEED_1000 2 +#define AR7240_PORT_STATUS_TXMAC BIT(2) +#define AR7240_PORT_STATUS_RXMAC BIT(3) +#define AR7240_PORT_STATUS_TXFLOW BIT(4) +#define AR7240_PORT_STATUS_RXFLOW BIT(5) +#define AR7240_PORT_STATUS_DUPLEX BIT(6) +#define AR7240_PORT_STATUS_LINK_UP BIT(8) +#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) +#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) + +#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) +#define AR7240_PORT_CTRL_STATE_M BITM(3) +#define AR7240_PORT_CTRL_STATE_DISABLED 0 +#define AR7240_PORT_CTRL_STATE_BLOCK 1 +#define AR7240_PORT_CTRL_STATE_LISTEN 2 +#define AR7240_PORT_CTRL_STATE_LEARN 3 +#define AR7240_PORT_CTRL_STATE_FORWARD 4 +#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) +#define AR7240_PORT_CTRL_VLAN_MODE_S 8 +#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 +#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 +#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 +#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 +#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) +#define AR7240_PORT_CTRL_HEADER BIT(11) +#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) +#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) +#define AR7240_PORT_CTRL_LEARN BIT(14) +#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) +#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) +#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) + +#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) + +#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 +#define AR7240_PORT_VLAN_DEST_PORTS_S 16 +#define AR7240_PORT_VLAN_MODE_S 30 +#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0 +#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1 +#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2 +#define AR7240_PORT_VLAN_MODE_SECURE 3 + + +#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) + +#define AR7240_STATS_RXBROAD 0x00 +#define AR7240_STATS_RXPAUSE 0x04 +#define AR7240_STATS_RXMULTI 0x08 +#define AR7240_STATS_RXFCSERR 0x0c +#define AR7240_STATS_RXALIGNERR 0x10 +#define AR7240_STATS_RXRUNT 0x14 +#define AR7240_STATS_RXFRAGMENT 0x18 +#define AR7240_STATS_RX64BYTE 0x1c +#define AR7240_STATS_RX128BYTE 0x20 +#define AR7240_STATS_RX256BYTE 0x24 +#define AR7240_STATS_RX512BYTE 0x28 +#define AR7240_STATS_RX1024BYTE 0x2c +#define AR7240_STATS_RX1518BYTE 0x30 +#define AR7240_STATS_RXMAXBYTE 0x34 +#define AR7240_STATS_RXTOOLONG 0x38 +#define AR7240_STATS_RXGOODBYTE 0x3c +#define AR7240_STATS_RXBADBYTE 0x44 +#define AR7240_STATS_RXOVERFLOW 0x4c +#define AR7240_STATS_FILTERED 0x50 +#define AR7240_STATS_TXBROAD 0x54 +#define AR7240_STATS_TXPAUSE 0x58 +#define AR7240_STATS_TXMULTI 0x5c +#define AR7240_STATS_TXUNDERRUN 0x60 +#define AR7240_STATS_TX64BYTE 0x64 +#define AR7240_STATS_TX128BYTE 0x68 +#define AR7240_STATS_TX256BYTE 0x6c +#define AR7240_STATS_TX512BYTE 0x70 +#define AR7240_STATS_TX1024BYTE 0x74 +#define AR7240_STATS_TX1518BYTE 0x78 +#define AR7240_STATS_TXMAXBYTE 0x7c +#define AR7240_STATS_TXOVERSIZE 0x80 +#define AR7240_STATS_TXBYTE 0x84 +#define AR7240_STATS_TXCOLLISION 0x8c +#define AR7240_STATS_TXABORTCOL 0x90 +#define AR7240_STATS_TXMULTICOL 0x94 +#define AR7240_STATS_TXSINGLECOL 0x98 +#define AR7240_STATS_TXEXCDEFER 0x9c +#define AR7240_STATS_TXDEFER 0xa0 +#define AR7240_STATS_TXLATECOL 0xa4 + +#define AR7240_PORT_CPU 0 +#define AR7240_NUM_PORTS 6 +#define AR7240_NUM_PHYS 5 + +#define AR7240_PHY_ID1 0x004d +#define AR7240_PHY_ID2 0xd041 + +#define AR934X_PHY_ID1 0x004d +#define AR934X_PHY_ID2 0xd042 + +#define AR7240_MAX_VLANS 16 + +#define AR934X_REG_OPER_MODE0 0x04 +#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6) +#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10) + +#define AR934X_REG_OPER_MODE1 0x08 +#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28) + +#define AR934X_REG_FLOOD_MASK 0x2c +#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p)) + +#define AR934X_REG_QM_CTRL 0x3c +#define AR934X_QM_CTRL_ARP_EN BIT(15) + +#define AR934X_REG_AT_CTRL 0x5c +#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR934X_AT_CTRL_AGE_EN BIT(17) +#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18) + +#define AR934X_MIB_ENABLE BIT(30) + +#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) +#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 +#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12) +#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13) +#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14) +#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15) +#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 +#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28) +#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 + +#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) +#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 +#define AR934X_PORT_VLAN2_8021Q_MODE_S 30 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 +#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 +#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 + +#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev) + +struct ar7240sw_port_stat { + unsigned long rx_broadcast; + unsigned long rx_pause; + unsigned long rx_multicast; + unsigned long rx_fcs_error; + unsigned long rx_align_error; + unsigned long rx_runt; + unsigned long rx_fragments; + unsigned long rx_64byte; + unsigned long rx_128byte; + unsigned long rx_256byte; + unsigned long rx_512byte; + unsigned long rx_1024byte; + unsigned long rx_1518byte; + unsigned long rx_maxbyte; + unsigned long rx_toolong; + unsigned long rx_good_byte; + unsigned long rx_bad_byte; + unsigned long rx_overflow; + unsigned long filtered; + + unsigned long tx_broadcast; + unsigned long tx_pause; + unsigned long tx_multicast; + unsigned long tx_underrun; + unsigned long tx_64byte; + unsigned long tx_128byte; + unsigned long tx_256byte; + unsigned long tx_512byte; + unsigned long tx_1024byte; + unsigned long tx_1518byte; + unsigned long tx_maxbyte; + unsigned long tx_oversize; + unsigned long tx_byte; + unsigned long tx_collision; + unsigned long tx_abortcol; + unsigned long tx_multicol; + unsigned long tx_singlecol; + unsigned long tx_excdefer; + unsigned long tx_defer; + unsigned long tx_xlatecol; +}; + +struct ar7240sw { + struct mii_bus *mii_bus; + struct ag71xx_switch_platform_data *swdata; + struct switch_dev swdev; + int num_ports; + u8 ver; + bool vlan; + u16 vlan_id[AR7240_MAX_VLANS]; + u8 vlan_table[AR7240_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[AR7240_NUM_PORTS]; + char buf[80]; + + rwlock_t stats_lock; + struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS]; +}; + +struct ar7240sw_hw_stat { + char string[ETH_GSTRING_LEN]; + int sizeof_stat; + int reg; +}; + +static DEFINE_MUTEX(reg_mutex); + +static inline int sw_is_ar7240(struct ar7240sw *as) +{ + return as->ver == AR7240_MASK_CTRL_VERSION_AR7240; +} + +static inline int sw_is_ar934x(struct ar7240sw *as) +{ + return as->ver == AR7240_MASK_CTRL_VERSION_AR934X; +} + +static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port) +{ + return BIT(port); +} + +static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as) +{ + return BIT(as->swdev.ports) - 1; +} + +static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port) +{ + return ar7240sw_port_mask_all(as) & ~BIT(port); +} + +static inline u16 mk_phy_addr(u32 reg) +{ + return 0x17 & ((reg >> 4) | 0x10); +} + +static inline u16 mk_phy_reg(u32 reg) +{ + return (reg << 1) & 0x1e; +} + +static inline u16 mk_high_addr(u32 reg) +{ + return (reg >> 7) & 0x1ff; +} + +static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg) +{ + unsigned long flags; + u16 phy_addr; + u16 phy_reg; + u32 hi, lo; + + reg = (reg & 0xfffffffc) >> 2; + phy_addr = mk_phy_addr(reg); + phy_reg = mk_phy_reg(reg); + + local_irq_save(flags); + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); + lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg); + hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1); + local_irq_restore(flags); + + return (hi << 16) | lo; +} + +static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val) +{ + unsigned long flags; + u16 phy_addr; + u16 phy_reg; + + reg = (reg & 0xfffffffc) >> 2; + phy_addr = mk_phy_addr(reg); + phy_reg = mk_phy_reg(reg); + + local_irq_save(flags); + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16)); + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff)); + local_irq_restore(flags); +} + +static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr) +{ + u32 ret; + + mutex_lock(®_mutex); + ret = __ar7240sw_reg_read(mii, reg_addr); + mutex_unlock(®_mutex); + + return ret; +} + +static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val) +{ + mutex_lock(®_mutex); + __ar7240sw_reg_write(mii, reg_addr, reg_val); + mutex_unlock(®_mutex); +} + +static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val) +{ + u32 t; + + mutex_lock(®_mutex); + t = __ar7240sw_reg_read(mii, reg); + t &= ~mask; + t |= val; + __ar7240sw_reg_write(mii, reg, t); + mutex_unlock(®_mutex); + + return t; +} + +static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val) +{ + u32 t; + + mutex_lock(®_mutex); + t = __ar7240sw_reg_read(mii, reg); + t |= val; + __ar7240sw_reg_write(mii, reg, t); + mutex_unlock(®_mutex); +} + +static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int i; + + for (i = 0; i < timeout; i++) { + u32 t; + + t = __ar7240sw_reg_read(mii, reg); + if ((t & mask) == val) + return 0; + + msleep(1); + } + + return -ETIMEDOUT; +} + +static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int ret; + + mutex_lock(®_mutex); + ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout); + mutex_unlock(®_mutex); + return ret; +} + +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr) +{ + u32 t, val = 0xffff; + int err; + + if (phy_addr >= AR7240_NUM_PHYS) + return 0xffff; + + mutex_lock(®_mutex); + t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | + (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | + AR7240_MDIO_CTRL_MASTER_EN | + AR7240_MDIO_CTRL_BUSY | + AR7240_MDIO_CTRL_CMD_READ; + + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); + err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, + AR7240_MDIO_CTRL_BUSY, 0, 5); + if (!err) + val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL); + mutex_unlock(®_mutex); + + return val & AR7240_MDIO_CTRL_DATA_M; +} + +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr, u16 reg_val) +{ + u32 t; + int ret; + + if (phy_addr >= AR7240_NUM_PHYS) + return -EINVAL; + + mutex_lock(®_mutex); + t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | + (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | + AR7240_MDIO_CTRL_MASTER_EN | + AR7240_MDIO_CTRL_BUSY | + AR7240_MDIO_CTRL_CMD_WRITE | + reg_val; + + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); + ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, + AR7240_MDIO_CTRL_BUSY, 0, 5); + mutex_unlock(®_mutex); + + return ret; +} + +static int ar7240sw_capture_stats(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + int port; + int ret; + + write_lock(&as->stats_lock); + + /* Capture the hardware statistics for all ports */ + ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0, + (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S), + (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); + + /* Wait for the capturing to complete. */ + ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0, + AR7240_MIB_BUSY, 0, 10); + + if (ret) + goto unlock; + + for (port = 0; port < AR7240_NUM_PORTS; port++) { + unsigned int base; + struct ar7240sw_port_stat *stats; + + base = AR7240_REG_STATS_BASE(port); + stats = &as->port_stats[port]; + +#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r) + + stats->rx_good_byte += READ_STAT(RXGOODBYTE); + stats->tx_byte += READ_STAT(TXBYTE); + +#undef READ_STAT + } + + ret = 0; + +unlock: + write_unlock(&as->stats_lock); + return ret; +} + +static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) +{ + ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port), + AR7240_PORT_CTRL_STATE_DISABLED); +} + +static void ar7240sw_setup(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + + /* Enable CPU port, and disable mirror port */ + ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT, + AR7240_CPU_PORT_EN | + (15 << AR7240_MIRROR_PORT_S)); + + /* Setup TAG priority mapping */ + ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); + + if (sw_is_ar934x(as)) { + /* Enable aging, MAC replacing */ + ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL, + 0x2b /* 5 min age time */ | + AR934X_AT_CTRL_AGE_EN | + AR934X_AT_CTRL_LEARN_CHANGE); + /* Enable ARP frame acknowledge */ + ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL, + AR934X_QM_CTRL_ARP_EN); + /* Enable Broadcast frames transmitted to the CPU */ + ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK, + AR934X_FLOOD_MASK_BC_DP(0)); + + /* Enable MIB counters */ + ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0, + AR934X_MIB_ENABLE); + + } else { + /* Enable ARP frame acknowledge, aging, MAC replacing */ + ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, + AR7240_AT_CTRL_RESERVED | + 0x2b /* 5 min age time */ | + AR7240_AT_CTRL_AGE_EN | + AR7240_AT_CTRL_ARP_EN | + AR7240_AT_CTRL_LEARN_CHANGE); + /* Enable Broadcast frames transmitted to the CPU */ + ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, + AR7240_FLOOD_MASK_BROAD_TO_CPU); + } + + /* setup MTU */ + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M, + 1536); + + /* setup Service TAG */ + ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0); +} + +static int ar7240sw_reset(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + int ret; + int i; + + /* Set all ports to disabled state. */ + for (i = 0; i < AR7240_NUM_PORTS; i++) + ar7240sw_disable_port(as, i); + + /* Wait for transmit queues to drain. */ + msleep(2); + + /* Reset the switch. */ + ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, + AR7240_MASK_CTRL_SOFT_RESET); + + ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, + AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); + + /* setup PHYs */ + for (i = 0; i < AR7240_NUM_PHYS; i++) { + ar7240sw_phy_write(mii, i, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + ar7240sw_phy_write(mii, i, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); + } + msleep(1000); + + ar7240sw_setup(as); + return ret; +} + +static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask) +{ + struct mii_bus *mii = as->mii_bus; + u32 ctrl; + u32 vid, mode; + + ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN | + AR7240_PORT_CTRL_SINGLE_VLAN; + + if (port == AR7240_PORT_CPU) { + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), + AR7240_PORT_STATUS_SPEED_1000 | + AR7240_PORT_STATUS_TXFLOW | + AR7240_PORT_STATUS_RXFLOW | + AR7240_PORT_STATUS_TXMAC | + AR7240_PORT_STATUS_RXMAC | + AR7240_PORT_STATUS_DUPLEX); + } else { + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), + AR7240_PORT_STATUS_LINK_AUTO); + } + + /* Set the default VID for this port */ + if (as->vlan) { + vid = as->vlan_id[as->pvid[port]]; + mode = AR7240_PORT_VLAN_MODE_SECURE; + } else { + vid = port; + mode = AR7240_PORT_VLAN_MODE_PORT_ONLY; + } + + if (as->vlan) { + if (as->vlan_tagged & BIT(port)) + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD << + AR7240_PORT_CTRL_VLAN_MODE_S; + else + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP << + AR7240_PORT_CTRL_VLAN_MODE_S; + } else { + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP << + AR7240_PORT_CTRL_VLAN_MODE_S; + } + + if (!portmask) { + if (port == AR7240_PORT_CPU) + portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU); + else + portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU); + } + + /* allow the port to talk to all other ports, but exclude its + * own ID to prevent frames from being reflected back to the + * port that they came from */ + portmask &= ar7240sw_port_mask_but(as, port); + + ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl); + if (sw_is_ar934x(as)) { + u32 vlan1, vlan2; + + vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S); + vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) | + (mode << AR934X_PORT_VLAN2_8021Q_MODE_S); + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1); + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2); + } else { + u32 vlan; + + vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) | + (portmask << AR7240_PORT_VLAN_DEST_PORTS_S); + + ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan); + } +} + +static int ar7240_set_addr(struct ar7240sw *as, u8 *addr) +{ + struct mii_bus *mii = as->mii_bus; + u32 t; + + t = (addr[4] << 8) | addr[5]; + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t); + + t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t); + + return 0; +} + +static int +ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + as->vlan_id[val->port_vlan] = val->value.i; + return 0; +} + +static int +ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + val->value.i = as->vlan_id[val->port_vlan]; + return 0; +} + +static int +ar7240_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + + /* make sure no invalid PVIDs get set */ + + if (vlan >= dev->vlans) + return -EINVAL; + + as->pvid[port] = vlan; + return 0; +} + +static int +ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + *vlan = as->pvid[port]; + return 0; +} + +static int +ar7240_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 ports = as->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < as->swdev.ports; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (as->vlan_tagged & (1 << i)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int +ar7240_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 *vt = &as->vlan_table[val->port_vlan]; + int i, j; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) + as->vlan_tagged |= (1 << p->id); + else { + as->vlan_tagged &= ~(1 << p->id); + as->pvid[p->id] = val->port_vlan; + + /* make sure that an untagged port does not + * appear in other vlans */ + for (j = 0; j < AR7240_MAX_VLANS; j++) { + if (j == val->port_vlan) + continue; + as->vlan_table[j] &= ~(1 << p->id); + } + } + + *vt |= 1 << p->id; + } + return 0; +} + +static int +ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + as->vlan = !!val->value.i; + return 0; +} + +static int +ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + val->value.i = as->vlan; + return 0; +} + +static void +ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val) +{ + struct mii_bus *mii = as->mii_bus; + + if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5)) + return; + + if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) { + val &= AR7240_VTUDATA_MEMBER; + val |= AR7240_VTUDATA_VALID; + ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val); + } + op |= AR7240_VTU_ACTIVE; + ar7240sw_reg_write(mii, AR7240_REG_VTU, op); +} + +static int +ar7240_hw_apply(struct switch_dev *dev) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 portmask[AR7240_NUM_PORTS]; + int i, j; + + /* flush all vlan translation unit entries */ + ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0); + + memset(portmask, 0, sizeof(portmask)); + if (as->vlan) { + /* calculate the port destination masks and load vlans + * into the vlan translation unit */ + for (j = 0; j < AR7240_MAX_VLANS; j++) { + u8 vp = as->vlan_table[j]; + + if (!vp) + continue; + + for (i = 0; i < as->swdev.ports; i++) { + u8 mask = (1 << i); + if (vp & mask) + portmask[i] |= vp & ~mask; + } + + ar7240_vtu_op(as, + AR7240_VTU_OP_LOAD | + (as->vlan_id[j] << AR7240_VTU_VID_S), + as->vlan_table[j]); + } + } else { + /* vlan disabled: + * isolate all ports, but connect them to the cpu port */ + for (i = 0; i < as->swdev.ports; i++) { + if (i == AR7240_PORT_CPU) + continue; + + portmask[i] = 1 << AR7240_PORT_CPU; + portmask[AR7240_PORT_CPU] |= (1 << i); + } + } + + /* update the port destination mask registers and tag settings */ + for (i = 0; i < as->swdev.ports; i++) + ar7240sw_setup_port(as, i, portmask[i]); + + return 0; +} + +static int +ar7240_reset_switch(struct switch_dev *dev) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + ar7240sw_reset(as); + return 0; +} + +static int +ar7240_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + struct mii_bus *mii = as->mii_bus; + u32 status; + + if (port > AR7240_NUM_PORTS) + return -EINVAL; + + status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port)); + link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO); + if (link->aneg) { + link->link = !!(status & AR7240_PORT_STATUS_LINK_UP); + if (!link->link) + return 0; + } else { + link->link = true; + } + + link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX); + link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW); + link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW); + switch (status & AR7240_PORT_STATUS_SPEED_M) { + case AR7240_PORT_STATUS_SPEED_10: + link->speed = SWITCH_PORT_SPEED_10; + break; + case AR7240_PORT_STATUS_SPEED_100: + link->speed = SWITCH_PORT_SPEED_100; + break; + case AR7240_PORT_STATUS_SPEED_1000: + link->speed = SWITCH_PORT_SPEED_1000; + break; + } + + return 0; +} + +static int +ar7240_get_port_stats(struct switch_dev *dev, int port, + struct switch_port_stats *stats) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + + if (port > AR7240_NUM_PORTS) + return -EINVAL; + + ar7240sw_capture_stats(as); + + read_lock(&as->stats_lock); + stats->rx_bytes = as->port_stats[port].rx_good_byte; + stats->tx_bytes = as->port_stats[port].tx_byte; + read_unlock(&as->stats_lock); + + return 0; +} + +static struct switch_attr ar7240_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = ar7240_set_vlan, + .get = ar7240_get_vlan, + .max = 1 + }, +}; + +static struct switch_attr ar7240_port[] = { +}; + +static struct switch_attr ar7240_vlan[] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID", + .set = ar7240_set_vid, + .get = ar7240_get_vid, + .max = 4094, + }, +}; + +static const struct switch_dev_ops ar7240_ops = { + .attr_global = { + .attr = ar7240_globals, + .n_attr = ARRAY_SIZE(ar7240_globals), + }, + .attr_port = { + .attr = ar7240_port, + .n_attr = ARRAY_SIZE(ar7240_port), + }, + .attr_vlan = { + .attr = ar7240_vlan, + .n_attr = ARRAY_SIZE(ar7240_vlan), + }, + .get_port_pvid = ar7240_get_pvid, + .set_port_pvid = ar7240_set_pvid, + .get_vlan_ports = ar7240_get_ports, + .set_vlan_ports = ar7240_set_ports, + .apply_config = ar7240_hw_apply, + .reset_switch = ar7240_reset_switch, + .get_port_link = ar7240_get_port_link, + .get_port_stats = ar7240_get_port_stats, +}; + +static struct ar7240sw *ar7240_probe(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct mii_bus *mii = ag->mii_bus; + struct ar7240sw *as; + struct switch_dev *swdev; + u32 ctrl; + u16 phy_id1; + u16 phy_id2; + int i; + + phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1); + phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2); + if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) && + (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) { + pr_err("%s: unknown phy id '%04x:%04x'\n", + ag->dev->name, phy_id1, phy_id2); + return NULL; + } + + as = kzalloc(sizeof(*as), GFP_KERNEL); + if (!as) + return NULL; + + as->mii_bus = mii; + as->swdata = pdata->switch_data; + + swdev = &as->swdev; + + ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL); + as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & + AR7240_MASK_CTRL_VERSION_M; + + if (sw_is_ar7240(as)) { + swdev->name = "AR7240/AR9330 built-in switch"; + swdev->ports = AR7240_NUM_PORTS - 1; + } else if (sw_is_ar934x(as)) { + swdev->name = "AR934X built-in switch"; + + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, + AR934X_OPER_MODE0_MAC_GMII_EN); + } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, + AR934X_OPER_MODE0_PHY_MII_EN); + } else { + pr_err("%s: invalid PHY interface mode\n", + ag->dev->name); + goto err_free; + } + + if (as->swdata->phy4_mii_en) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1, + AR934X_REG_OPER_MODE1_PHY4_MII_EN); + swdev->ports = AR7240_NUM_PORTS - 1; + } else { + swdev->ports = AR7240_NUM_PORTS; + } + } else { + pr_err("%s: unsupported chip, ctrl=%08x\n", + ag->dev->name, ctrl); + goto err_free; + } + + swdev->cpu_port = AR7240_PORT_CPU; + swdev->vlans = AR7240_MAX_VLANS; + swdev->ops = &ar7240_ops; + + if (register_switch(&as->swdev, ag->dev) < 0) + goto err_free; + + pr_info("%s: Found an %s\n", ag->dev->name, swdev->name); + + /* initialize defaults */ + for (i = 0; i < AR7240_MAX_VLANS; i++) + as->vlan_id[i] = i; + + as->vlan_table[0] = ar7240sw_port_mask_all(as); + + return as; + +err_free: + kfree(as); + return NULL; +} + +static void link_function(struct work_struct *work) { + struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work); + struct ar7240sw *as = ag->phy_priv; + unsigned long flags; + u8 mask; + int i; + int status = 0; + + mask = ~as->swdata->phy_poll_mask; + for (i = 0; i < AR7240_NUM_PHYS; i++) { + int link; + + if (!(mask & BIT(i))) + continue; + + link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR); + if (link & BMSR_LSTATUS) { + status = 1; + break; + } + } + + spin_lock_irqsave(&ag->lock, flags); + if (status != ag->link) { + ag->link = status; + ag71xx_link_adjust(ag); + } + spin_unlock_irqrestore(&ag->lock, flags); + + schedule_delayed_work(&ag->link_work, HZ / 2); +} + +void ag71xx_ar7240_start(struct ag71xx *ag) +{ + struct ar7240sw *as = ag->phy_priv; + + ar7240sw_reset(as); + + ag->speed = SPEED_1000; + ag->duplex = 1; + + ar7240_set_addr(as, ag->dev->dev_addr); + ar7240_hw_apply(&as->swdev); + + schedule_delayed_work(&ag->link_work, HZ / 10); +} + +void ag71xx_ar7240_stop(struct ag71xx *ag) +{ + cancel_delayed_work_sync(&ag->link_work); +} + +int __devinit ag71xx_ar7240_init(struct ag71xx *ag) +{ + struct ar7240sw *as; + + as = ar7240_probe(ag); + if (!as) + return -ENODEV; + + ag->phy_priv = as; + ar7240sw_reset(as); + + rwlock_init(&as->stats_lock); + INIT_DELAYED_WORK(&ag->link_work, link_function); + + return 0; +} + +void ag71xx_ar7240_cleanup(struct ag71xx *ag) +{ + struct ar7240sw *as = ag->phy_priv; + + if (!as) + return; + + unregister_switch(&as->swdev); + kfree(as); + ag->phy_priv = NULL; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c new file mode 100644 index 000000000..7ec43b722 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c @@ -0,0 +1,44 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * Special support for the Atheros ar8216 switch chip + * + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AR8216_PACKET_TYPE_MASK 0xf +#define AR8216_PACKET_TYPE_NORMAL 0 + +#define AR8216_HEADER_LEN 2 + +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) +{ + skb_push(skb, AR8216_HEADER_LEN); + skb->data[0] = 0x10; + skb->data[1] = 0x80; +} + +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, + int pktlen) +{ + u8 type; + + type = skb->data[1] & AR8216_PACKET_TYPE_MASK; + switch (type) { + case AR8216_PACKET_TYPE_NORMAL: + break; + + default: + return -EINVAL; + } + + skb_pull(skb, AR8216_HEADER_LEN); + return 0; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c new file mode 100644 index 000000000..65f2be198 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c @@ -0,0 +1,280 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/debugfs.h> + +#include "ag71xx.h" + +static struct dentry *ag71xx_debugfs_root; + +static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) +{ + if (status) + ag->debug.int_stats.total++; + if (status & AG71XX_INT_TX_PS) + ag->debug.int_stats.tx_ps++; + if (status & AG71XX_INT_TX_UR) + ag->debug.int_stats.tx_ur++; + if (status & AG71XX_INT_TX_BE) + ag->debug.int_stats.tx_be++; + if (status & AG71XX_INT_RX_PR) + ag->debug.int_stats.rx_pr++; + if (status & AG71XX_INT_RX_OF) + ag->debug.int_stats.rx_of++; + if (status & AG71XX_INT_RX_BE) + ag->debug.int_stats.rx_be++; +} + +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ +#define PR_INT_STAT(_label, _field) \ + len += snprintf(buf + len, sizeof(buf) - len, \ + "%20s: %10lu\n", _label, ag->debug.int_stats._field); + + struct ag71xx *ag = file->private_data; + char buf[256]; + unsigned int len = 0; + + PR_INT_STAT("TX Packet Sent", tx_ps); + PR_INT_STAT("TX Underrun", tx_ur); + PR_INT_STAT("TX Bus Error", tx_be); + PR_INT_STAT("RX Packet Received", rx_pr); + PR_INT_STAT("RX Overflow", rx_of); + PR_INT_STAT("RX Bus Error", rx_be); + len += snprintf(buf + len, sizeof(buf) - len, "\n"); + PR_INT_STAT("Total", total); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +#undef PR_INT_STAT +} + +static const struct file_operations ag71xx_fops_int_stats = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_int_stats, + .owner = THIS_MODULE +}; + +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) +{ + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + + if (rx) { + stats->rx_count++; + stats->rx_packets += rx; + if (rx <= AG71XX_NAPI_WEIGHT) + stats->rx[rx]++; + if (rx > stats->rx_packets_max) + stats->rx_packets_max = rx; + } + + if (tx) { + stats->tx_count++; + stats->tx_packets += tx; + if (tx <= AG71XX_NAPI_WEIGHT) + stats->tx[tx]++; + if (tx > stats->tx_packets_max) + stats->tx_packets_max = tx; + } +} + +static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + char *buf; + unsigned int buflen; + unsigned int len = 0; + unsigned long rx_avg = 0; + unsigned long tx_avg = 0; + int ret; + int i; + + buflen = 2048; + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + if (stats->rx_count) + rx_avg = stats->rx_packets / stats->rx_count; + + if (stats->tx_count) + tx_avg = stats->tx_packets / stats->tx_count; + + len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n", + "len", "rx", "tx"); + + for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) + len += snprintf(buf + len, buflen - len, + "%3d: %10lu %10lu\n", + i, stats->rx[i], stats->tx[i]); + + len += snprintf(buf + len, buflen - len, "\n"); + + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "sum", stats->rx_count, stats->tx_count); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "avg", rx_avg, tx_avg); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "max", stats->rx_packets_max, stats->tx_packets_max); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "pkt", stats->rx_packets, stats->tx_packets); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return ret; +} + +static const struct file_operations ag71xx_fops_napi_stats = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_napi_stats, + .owner = THIS_MODULE +}; + +#define DESC_PRINT_LEN 64 + +static ssize_t read_file_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos, + struct ag71xx *ag, + struct ag71xx_ring *ring, + unsigned desc_reg) +{ + char *buf; + unsigned int buflen; + unsigned int len = 0; + unsigned long flags; + ssize_t ret; + int curr; + int dirty; + u32 desc_hw; + int i; + + buflen = (ring->size * DESC_PRINT_LEN); + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len += snprintf(buf + len, buflen - len, + "Idx ... %-8s %-8s %-8s %-8s . %-10s\n", + "desc", "next", "data", "ctrl", "timestamp"); + + spin_lock_irqsave(&ag->lock, flags); + + curr = (ring->curr % ring->size); + dirty = (ring->dirty % ring->size); + desc_hw = ag71xx_rr(ag, desc_reg); + for (i = 0; i < ring->size; i++) { + struct ag71xx_buf *ab = &ring->buf[i]; + u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size; + + len += snprintf(buf + len, buflen - len, + "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n", + i, + (i == curr) ? 'C' : ' ', + (i == dirty) ? 'D' : ' ', + (desc_hw == desc_dma) ? 'H' : ' ', + desc_dma, + ab->desc->next, + ab->desc->data, + ab->desc->ctrl, + (ab->desc->ctrl & DESC_EMPTY) ? 'E' : '*', + ab->timestamp); + } + + spin_unlock_irqrestore(&ag->lock, flags); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return ret; +} + +static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + + return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring, + AG71XX_REG_TX_DESC); +} + +static const struct file_operations ag71xx_fops_tx_ring = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_tx_ring, + .owner = THIS_MODULE +}; + +static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + + return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring, + AG71XX_REG_RX_DESC); +} + +static const struct file_operations ag71xx_fops_rx_ring = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_rx_ring, + .owner = THIS_MODULE +}; + +void ag71xx_debugfs_exit(struct ag71xx *ag) +{ + debugfs_remove_recursive(ag->debug.debugfs_dir); +} + +int ag71xx_debugfs_init(struct ag71xx *ag) +{ + ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, + ag71xx_debugfs_root); + if (!ag->debug.debugfs_dir) + return -ENOMEM; + + debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_int_stats); + debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_napi_stats); + debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_tx_ring); + debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_rx_ring); + + return 0; +} + +int ag71xx_debugfs_root_init(void) +{ + if (ag71xx_debugfs_root) + return -EBUSY; + + ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); + if (!ag71xx_debugfs_root) + return -ENOENT; + + return 0; +} + +void ag71xx_debugfs_root_exit(void) +{ + debugfs_remove(ag71xx_debugfs_root); + ag71xx_debugfs_root = NULL; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c new file mode 100644 index 000000000..498fbed1f --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c @@ -0,0 +1,124 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +static int ag71xx_ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_gset(phydev, cmd); +} + +static int ag71xx_ethtool_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_sset(phydev, cmd); +} + +static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct ag71xx *ag = netdev_priv(dev); + + strcpy(info->driver, ag->pdev->dev.driver->name); + strcpy(info->version, AG71XX_DRV_VERSION); + strcpy(info->bus_info, dev_name(&ag->pdev->dev)); +} + +static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + + return ag->msg_enable; +} + +static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) +{ + struct ag71xx *ag = netdev_priv(dev); + + ag->msg_enable = msg_level; +} + +static void ag71xx_ethtool_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *er) +{ + struct ag71xx *ag = netdev_priv(dev); + + er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX; + er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX; + er->rx_mini_max_pending = 0; + er->rx_jumbo_max_pending = 0; + + er->tx_pending = ag->tx_ring.size; + er->rx_pending = ag->rx_ring.size; + er->rx_mini_pending = 0; + er->rx_jumbo_pending = 0; +} + +static int ag71xx_ethtool_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *er) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned tx_size; + unsigned rx_size; + int err; + + if (er->rx_mini_pending != 0|| + er->rx_jumbo_pending != 0 || + er->rx_pending == 0 || + er->tx_pending == 0) + return -EINVAL; + + tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ? + er->tx_pending : AG71XX_TX_RING_SIZE_MAX; + + rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ? + er->rx_pending : AG71XX_RX_RING_SIZE_MAX; + + if (netif_running(dev)) { + err = dev->netdev_ops->ndo_stop(dev); + if (err) + return err; + } + + ag->tx_ring.size = tx_size; + ag->rx_ring.size = rx_size; + + if (netif_running(dev)) + err = dev->netdev_ops->ndo_open(dev); + + return err; +} + +struct ethtool_ops ag71xx_ethtool_ops = { + .set_settings = ag71xx_ethtool_set_settings, + .get_settings = ag71xx_ethtool_get_settings, + .get_drvinfo = ag71xx_ethtool_get_drvinfo, + .get_msglevel = ag71xx_ethtool_get_msglevel, + .set_msglevel = ag71xx_ethtool_set_msglevel, + .get_ringparam = ag71xx_ethtool_get_ringparam, + .set_ringparam = ag71xx_ethtool_set_ringparam, + .get_link = ethtool_op_get_link, +}; diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c new file mode 100644 index 000000000..fb99d2728 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -0,0 +1,1258 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AG71XX_DEFAULT_MSG_ENABLE \ + (NETIF_MSG_DRV \ + | NETIF_MSG_PROBE \ + | NETIF_MSG_LINK \ + | NETIF_MSG_TIMER \ + | NETIF_MSG_IFDOWN \ + | NETIF_MSG_IFUP \ + | NETIF_MSG_RX_ERR \ + | NETIF_MSG_TX_ERR) + +static int ag71xx_msg_level = -1; + +module_param_named(msg_level, ag71xx_msg_level, int, 0); +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); + +static void ag71xx_dump_dma_regs(struct ag71xx *ag) +{ + DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_TX_CTRL), + ag71xx_rr(ag, AG71XX_REG_TX_DESC), + ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); + + DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_RX_CTRL), + ag71xx_rr(ag, AG71XX_REG_RX_DESC), + ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); +} + +static void ag71xx_dump_regs(struct ag71xx *ag) +{ + DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), + ag71xx_rr(ag, AG71XX_REG_MAC_IPG), + ag71xx_rr(ag, AG71XX_REG_MAC_HDX), + ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); + DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); + DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); +} + +static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) +{ + DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", + ag->dev->name, label, intr, + (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", + (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", + (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", + (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", + (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", + (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); +} + +static void ag71xx_ring_free(struct ag71xx_ring *ring) +{ + kfree(ring->buf); + + if (ring->descs_cpu) + dma_free_coherent(NULL, ring->size * ring->desc_size, + ring->descs_cpu, ring->descs_dma); +} + +static int ag71xx_ring_alloc(struct ag71xx_ring *ring) +{ + int err; + int i; + + ring->desc_size = sizeof(struct ag71xx_desc); + if (ring->desc_size % cache_line_size()) { + DBG("ag71xx: ring %p, desc size %u rounded to %u\n", + ring, ring->desc_size, + roundup(ring->desc_size, cache_line_size())); + ring->desc_size = roundup(ring->desc_size, cache_line_size()); + } + + ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size, + &ring->descs_dma, GFP_ATOMIC); + if (!ring->descs_cpu) { + err = -ENOMEM; + goto err; + } + + + ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL); + if (!ring->buf) { + err = -ENOMEM; + goto err; + } + + for (i = 0; i < ring->size; i++) { + int idx = i * ring->desc_size; + ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx]; + DBG("ag71xx: ring %p, desc %d at %p\n", + ring, i, ring->buf[i].desc); + } + + return 0; + +err: + return err; +} + +static void ag71xx_ring_tx_clean(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + struct net_device *dev = ag->dev; + u32 bytes_compl = 0, pkts_compl = 0; + + while (ring->curr != ring->dirty) { + u32 i = ring->dirty % ring->size; + + if (!ag71xx_desc_empty(ring->buf[i].desc)) { + ring->buf[i].desc->ctrl = 0; + dev->stats.tx_errors++; + } + + if (ring->buf[i].skb) { + bytes_compl += ring->buf[i].skb->len; + pkts_compl++; + dev_kfree_skb_any(ring->buf[i].skb); + } + ring->buf[i].skb = NULL; + ring->dirty++; + } + + /* flush descriptors */ + wmb(); + + netdev_completed_queue(dev, pkts_compl, bytes_compl); +} + +static void ag71xx_ring_tx_init(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + int i; + + for (i = 0; i < ring->size; i++) { + ring->buf[i].desc->next = (u32) (ring->descs_dma + + ring->desc_size * ((i + 1) % ring->size)); + + ring->buf[i].desc->ctrl = DESC_EMPTY; + ring->buf[i].skb = NULL; + } + + /* flush descriptors */ + wmb(); + + ring->curr = 0; + ring->dirty = 0; + netdev_reset_queue(ag->dev); +} + +static void ag71xx_ring_rx_clean(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + int i; + + if (!ring->buf) + return; + + for (i = 0; i < ring->size; i++) + if (ring->buf[i].rx_buf) { + dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, + AG71XX_RX_BUF_SIZE, DMA_FROM_DEVICE); + kfree(ring->buf[i].rx_buf); + } +} + +static int ag71xx_buffer_offset(struct ag71xx *ag) +{ + int offset = NET_SKB_PAD; + + /* + * On AR71xx/AR91xx packets must be 4-byte aligned. + * + * When using builtin AR8216 support, hardware adds a 2-byte header, + * so we don't need any extra alignment in that case. + */ + if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag)) + return offset; + + return offset + NET_IP_ALIGN; +} + +static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, + int offset) +{ + void *data; + + data = kmalloc(AG71XX_RX_BUF_SIZE + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), + GFP_ATOMIC); + if (!data) + return false; + + buf->rx_buf = data; + buf->dma_addr = dma_map_single(&ag->dev->dev, data, + AG71XX_RX_BUF_SIZE, DMA_FROM_DEVICE); + buf->desc->data = (u32) buf->dma_addr + offset; + return true; +} + +static int ag71xx_ring_rx_init(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + unsigned int i; + int ret; + int offset = ag71xx_buffer_offset(ag); + + ret = 0; + for (i = 0; i < ring->size; i++) { + ring->buf[i].desc->next = (u32) (ring->descs_dma + + ring->desc_size * ((i + 1) % ring->size)); + + DBG("ag71xx: RX desc at %p, next is %08x\n", + ring->buf[i].desc, + ring->buf[i].desc->next); + } + + for (i = 0; i < ring->size; i++) { + if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) { + ret = -ENOMEM; + break; + } + + ring->buf[i].desc->ctrl = DESC_EMPTY; + } + + /* flush descriptors */ + wmb(); + + ring->curr = 0; + ring->dirty = 0; + + return ret; +} + +static int ag71xx_ring_rx_refill(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + unsigned int count; + int offset = ag71xx_buffer_offset(ag); + + count = 0; + for (; ring->curr - ring->dirty > 0; ring->dirty++) { + unsigned int i; + + i = ring->dirty % ring->size; + + if (!ring->buf[i].rx_buf && + !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) + break; + + ring->buf[i].desc->ctrl = DESC_EMPTY; + count++; + } + + /* flush descriptors */ + wmb(); + + DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); + + return count; +} + +static int ag71xx_rings_init(struct ag71xx *ag) +{ + int ret; + + ret = ag71xx_ring_alloc(&ag->tx_ring); + if (ret) + return ret; + + ag71xx_ring_tx_init(ag); + + ret = ag71xx_ring_alloc(&ag->rx_ring); + if (ret) + return ret; + + ret = ag71xx_ring_rx_init(ag); + return ret; +} + +static void ag71xx_rings_cleanup(struct ag71xx *ag) +{ + ag71xx_ring_rx_clean(ag); + ag71xx_ring_free(&ag->rx_ring); + + ag71xx_ring_tx_clean(ag); + netdev_reset_queue(ag->dev); + ag71xx_ring_free(&ag->tx_ring); +} + +static unsigned char *ag71xx_speed_str(struct ag71xx *ag) +{ + switch (ag->speed) { + case SPEED_1000: + return "1000"; + case SPEED_100: + return "100"; + case SPEED_10: + return "10"; + } + + return "?"; +} + +static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) +{ + u32 t; + + t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) + | (((u32) mac[3]) << 8) | ((u32) mac[2]); + + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); + + t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); +} + +static void ag71xx_dma_reset(struct ag71xx *ag) +{ + u32 val; + int i; + + ag71xx_dump_dma_regs(ag); + + /* stop RX and TX */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); + + /* + * give the hardware some time to really stop all rx/tx activity + * clearing the descriptors too early causes random memory corruption + */ + mdelay(1); + + /* clear descriptor addresses */ + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); + + /* clear pending RX/TX interrupts */ + for (i = 0; i < 256; i++) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + } + + /* clear pending errors */ + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); + + val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); + if (val) + pr_alert("%s: unable to clear DMA Rx status: %08x\n", + ag->dev->name, val); + + val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + + /* mask out reserved bits */ + val &= ~0xff000000; + + if (val) + pr_alert("%s: unable to clear DMA Tx status: %08x\n", + ag->dev->name, val); + + ag71xx_dump_dma_regs(ag); +} + +#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ + MAC_CFG1_SRX | MAC_CFG1_STX) + +#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) + +#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ + FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ + FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ + FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ + FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ + FIFO_CFG4_VT) + +#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ + FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ + FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ + FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ + FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ + FIFO_CFG5_17 | FIFO_CFG5_SF) + +static void ag71xx_hw_stop(struct ag71xx *ag) +{ + /* disable all interrupts and stop the rx/tx engine */ + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); +} + +static void ag71xx_hw_setup(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + /* setup MAC configuration registers */ + ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); + + ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, + MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); + + /* setup max frame length */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); + + /* setup FIFO configuration registers */ + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); + if (pdata->is_ar724x) { + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); + } else { + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); + } + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); +} + +static void ag71xx_hw_init(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 reset_mask = pdata->reset_bit; + + ag71xx_hw_stop(ag); + + if (pdata->is_ar724x) { + u32 reset_phy = reset_mask; + + reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY; + reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY); + + ath79_device_reset_set(reset_phy); + mdelay(50); + ath79_device_reset_clear(reset_phy); + mdelay(200); + } + + ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); + udelay(20); + + ath79_device_reset_set(reset_mask); + mdelay(100); + ath79_device_reset_clear(reset_mask); + mdelay(200); + + ag71xx_hw_setup(ag); + + ag71xx_dma_reset(ag); +} + +static void ag71xx_fast_reset(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct net_device *dev = ag->dev; + u32 reset_mask = pdata->reset_bit; + u32 rx_ds, tx_ds; + u32 mii_reg; + + reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC; + + mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); + rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); + tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC); + + ath79_device_reset_set(reset_mask); + udelay(10); + ath79_device_reset_clear(reset_mask); + udelay(10); + + ag71xx_dma_reset(ag); + ag71xx_hw_setup(ag); + + ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); + ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds); + ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); + + ag71xx_hw_set_macaddr(ag, dev->dev_addr); +} + +static void ag71xx_hw_start(struct ag71xx *ag) +{ + /* start RX engine */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + + /* enable interrupts */ + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); +} + +void ag71xx_link_adjust(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 cfg2; + u32 ifctl; + u32 fifo5; + + if (!ag->link) { + ag71xx_hw_stop(ag); + netif_carrier_off(ag->dev); + if (netif_msg_link(ag)) + pr_info("%s: link down\n", ag->dev->name); + return; + } + + if (pdata->is_ar724x) + ag71xx_fast_reset(ag); + + cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); + cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); + cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; + + ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); + ifctl &= ~(MAC_IFCTL_SPEED); + + fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); + fifo5 &= ~FIFO_CFG5_BM; + + switch (ag->speed) { + case SPEED_1000: + cfg2 |= MAC_CFG2_IF_1000; + fifo5 |= FIFO_CFG5_BM; + break; + case SPEED_100: + cfg2 |= MAC_CFG2_IF_10_100; + ifctl |= MAC_IFCTL_SPEED; + break; + case SPEED_10: + cfg2 |= MAC_CFG2_IF_10_100; + break; + default: + BUG(); + return; + } + + if (pdata->is_ar91xx) + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); + else if (pdata->is_ar724x) + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); + else + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); + + if (pdata->set_speed) + pdata->set_speed(ag->speed); + + ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); + ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); + ag71xx_hw_start(ag); + + netif_carrier_on(ag->dev); + if (netif_msg_link(ag)) + pr_info("%s: link up (%sMbps/%s duplex)\n", + ag->dev->name, + ag71xx_speed_str(ag), + (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); + + DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + + DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); + + DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL)); +} + +static int ag71xx_open(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + int ret; + + ret = ag71xx_rings_init(ag); + if (ret) + goto err; + + napi_enable(&ag->napi); + + netif_carrier_off(dev); + ag71xx_phy_start(ag); + + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); + + ag71xx_hw_set_macaddr(ag, dev->dev_addr); + + netif_start_queue(dev); + + return 0; + +err: + ag71xx_rings_cleanup(ag); + return ret; +} + +static int ag71xx_stop(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned long flags; + + netif_carrier_off(dev); + ag71xx_phy_stop(ag); + + spin_lock_irqsave(&ag->lock, flags); + + netif_stop_queue(dev); + + ag71xx_hw_stop(ag); + ag71xx_dma_reset(ag); + + napi_disable(&ag->napi); + del_timer_sync(&ag->oom_timer); + + spin_unlock_irqrestore(&ag->lock, flags); + + ag71xx_rings_cleanup(ag); + + return 0; +} + +static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + struct ag71xx_ring *ring = &ag->tx_ring; + struct ag71xx_desc *desc; + dma_addr_t dma_addr; + int i; + + i = ring->curr % ring->size; + desc = ring->buf[i].desc; + + if (!ag71xx_desc_empty(desc)) + goto err_drop; + + if (ag71xx_has_ar8216(ag)) + ag71xx_add_ar8216_header(ag, skb); + + if (skb->len <= 0) { + DBG("%s: packet len is too small\n", ag->dev->name); + goto err_drop; + } + + dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + netdev_sent_queue(dev, skb->len); + ring->buf[i].skb = skb; + ring->buf[i].timestamp = jiffies; + + /* setup descriptor fields */ + desc->data = (u32) dma_addr; + desc->ctrl = (skb->len & DESC_PKTLEN_M); + + /* flush descriptor */ + wmb(); + + ring->curr++; + if (ring->curr == (ring->dirty + ring->size)) { + DBG("%s: tx queue full\n", ag->dev->name); + netif_stop_queue(dev); + } + + DBG("%s: packet injected into TX queue\n", ag->dev->name); + + /* enable TX engine */ + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); + + return NETDEV_TX_OK; + +err_drop: + dev->stats.tx_dropped++; + + dev_kfree_skb(skb); + return NETDEV_TX_OK; +} + +static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + int ret; + + switch (cmd) { + case SIOCETHTOOL: + if (ag->phy_dev == NULL) + break; + + spin_lock_irq(&ag->lock); + ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); + spin_unlock_irq(&ag->lock); + return ret; + + case SIOCSIFHWADDR: + if (copy_from_user + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGIFHWADDR: + if (copy_to_user + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGMIIPHY: + case SIOCGMIIREG: + case SIOCSMIIREG: + if (ag->phy_dev == NULL) + break; + + return phy_mii_ioctl(ag->phy_dev, ifr, cmd); + + default: + break; + } + + return -EOPNOTSUPP; +} + +static void ag71xx_oom_timer_handler(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct ag71xx *ag = netdev_priv(dev); + + napi_schedule(&ag->napi); +} + +static void ag71xx_tx_timeout(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + + if (netif_msg_tx_err(ag)) + pr_info("%s: tx timeout\n", ag->dev->name); + + schedule_work(&ag->restart_work); +} + +static void ag71xx_restart_work_func(struct work_struct *work) +{ + struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); + + if (ag71xx_get_pdata(ag)->is_ar724x) { + ag->link = 0; + ag71xx_link_adjust(ag); + return; + } + + ag71xx_stop(ag->dev); + ag71xx_open(ag->dev); +} + +static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp) +{ + u32 rx_sm, tx_sm, rx_fd; + + if (likely(time_before(jiffies, timestamp + HZ/10))) + return false; + + if (!netif_carrier_ok(ag->dev)) + return false; + + rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); + if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) + return true; + + tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); + rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); + if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && + ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) + return true; + + return false; +} + +static int ag71xx_tx_packets(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + int sent = 0; + int bytes_compl = 0; + + DBG("%s: processing TX ring\n", ag->dev->name); + + while (ring->dirty != ring->curr) { + unsigned int i = ring->dirty % ring->size; + struct ag71xx_desc *desc = ring->buf[i].desc; + struct sk_buff *skb = ring->buf[i].skb; + + if (!ag71xx_desc_empty(desc)) { + if (pdata->is_ar7240 && + ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) + schedule_work(&ag->restart_work); + break; + } + + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + + bytes_compl += skb->len; + ag->dev->stats.tx_bytes += skb->len; + ag->dev->stats.tx_packets++; + + dev_kfree_skb_any(skb); + ring->buf[i].skb = NULL; + + ring->dirty++; + sent++; + } + + DBG("%s: %d packets sent out\n", ag->dev->name, sent); + + netdev_completed_queue(ag->dev, sent, bytes_compl); + if ((ring->curr - ring->dirty) < (ring->size * 3) / 4) + netif_wake_queue(ag->dev); + + return sent; +} + +static int ag71xx_rx_packets(struct ag71xx *ag, int limit) +{ + struct net_device *dev = ag->dev; + struct ag71xx_ring *ring = &ag->rx_ring; + int offset = ag71xx_buffer_offset(ag); + int done = 0; + + DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", + dev->name, limit, ring->curr, ring->dirty); + + while (done < limit) { + unsigned int i = ring->curr % ring->size; + struct ag71xx_desc *desc = ring->buf[i].desc; + struct sk_buff *skb; + int pktlen; + int err = 0; + + if (ag71xx_desc_empty(desc)) + break; + + if ((ring->dirty + ring->size) == ring->curr) { + ag71xx_assert(0); + break; + } + + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + + pktlen = ag71xx_desc_pktlen(desc); + pktlen -= ETH_FCS_LEN; + + dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, + AG71XX_RX_BUF_SIZE, DMA_FROM_DEVICE); + + dev->last_rx = jiffies; + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + + skb = build_skb(ring->buf[i].rx_buf); + if (!skb) { + kfree(ring->buf[i].rx_buf); + goto next; + } + + skb_reserve(skb, offset); + skb_put(skb, pktlen); + + if (ag71xx_has_ar8216(ag)) + err = ag71xx_remove_ar8216_header(ag, skb, pktlen); + + if (err) { + dev->stats.rx_dropped++; + kfree_skb(skb); + } else { + skb->dev = dev; + skb->ip_summed = CHECKSUM_NONE; + skb->protocol = eth_type_trans(skb, dev); + netif_receive_skb(skb); + } + +next: + ring->buf[i].rx_buf = NULL; + done++; + + ring->curr++; + } + + ag71xx_ring_rx_refill(ag); + + DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", + dev->name, ring->curr, ring->dirty, done); + + return done; +} + +static int ag71xx_poll(struct napi_struct *napi, int limit) +{ + struct ag71xx *ag = container_of(napi, struct ag71xx, napi); + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct net_device *dev = ag->dev; + struct ag71xx_ring *rx_ring; + unsigned long flags; + u32 status; + int tx_done; + int rx_done; + + pdata->ddr_flush(); + tx_done = ag71xx_tx_packets(ag); + + DBG("%s: processing RX ring\n", dev->name); + rx_done = ag71xx_rx_packets(ag, limit); + + ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); + + rx_ring = &ag->rx_ring; + if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL) + goto oom; + + status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); + if (unlikely(status & RX_STATUS_OF)) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); + dev->stats.rx_fifo_errors++; + + /* restart RX */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + } + + if (rx_done < limit) { + if (status & RX_STATUS_PR) + goto more; + + status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + if (status & TX_STATUS_PS) + goto more; + + DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", + dev->name, rx_done, tx_done, limit); + + napi_complete(napi); + + /* enable interrupts */ + spin_lock_irqsave(&ag->lock, flags); + ag71xx_int_enable(ag, AG71XX_INT_POLL); + spin_unlock_irqrestore(&ag->lock, flags); + return rx_done; + } + +more: + DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", + dev->name, rx_done, tx_done, limit); + return rx_done; + +oom: + if (netif_msg_rx_err(ag)) + pr_info("%s: out of memory\n", dev->name); + + mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); + napi_complete(napi); + return 0; +} + +static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct ag71xx *ag = netdev_priv(dev); + u32 status; + + status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); + ag71xx_dump_intr(ag, "raw", status); + + if (unlikely(!status)) + return IRQ_NONE; + + if (unlikely(status & AG71XX_INT_ERR)) { + if (status & AG71XX_INT_TX_BE) { + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); + dev_err(&dev->dev, "TX BUS error\n"); + } + if (status & AG71XX_INT_RX_BE) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); + dev_err(&dev->dev, "RX BUS error\n"); + } + } + + if (likely(status & AG71XX_INT_POLL)) { + ag71xx_int_disable(ag, AG71XX_INT_POLL); + DBG("%s: enable polling mode\n", dev->name); + napi_schedule(&ag->napi); + } + + ag71xx_debugfs_update_int_stats(ag, status); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +/* + * Polling 'interrupt' - used by things like netconsole to send skbs + * without having to re-enable interrupts. It's not called while + * the interrupt routine is executing. + */ +static void ag71xx_netpoll(struct net_device *dev) +{ + disable_irq(dev->irq); + ag71xx_interrupt(dev->irq, dev); + enable_irq(dev->irq); +} +#endif + +static const struct net_device_ops ag71xx_netdev_ops = { + .ndo_open = ag71xx_open, + .ndo_stop = ag71xx_stop, + .ndo_start_xmit = ag71xx_hard_start_xmit, + .ndo_do_ioctl = ag71xx_do_ioctl, + .ndo_tx_timeout = ag71xx_tx_timeout, + .ndo_change_mtu = eth_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = ag71xx_netpoll, +#endif +}; + +static int __devinit ag71xx_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct resource *res; + struct ag71xx *ag; + struct ag71xx_platform_data *pdata; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data specified\n"); + err = -ENXIO; + goto err_out; + } + + if (pdata->mii_bus_dev == NULL) { + dev_err(&pdev->dev, "no MII bus device specified\n"); + err = -EINVAL; + goto err_out; + } + + dev = alloc_etherdev(sizeof(*ag)); + if (!dev) { + dev_err(&pdev->dev, "alloc_etherdev failed\n"); + err = -ENOMEM; + goto err_out; + } + + SET_NETDEV_DEV(dev, &pdev->dev); + + ag = netdev_priv(dev); + ag->pdev = pdev; + ag->dev = dev; + ag->msg_enable = netif_msg_init(ag71xx_msg_level, + AG71XX_DEFAULT_MSG_ENABLE); + spin_lock_init(&ag->lock); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); + if (!res) { + dev_err(&pdev->dev, "no mac_base resource found\n"); + err = -ENXIO; + goto err_out; + } + + ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!ag->mac_base) { + dev_err(&pdev->dev, "unable to ioremap mac_base\n"); + err = -ENOMEM; + goto err_free_dev; + } + + dev->irq = platform_get_irq(pdev, 0); + err = request_irq(dev->irq, ag71xx_interrupt, + IRQF_DISABLED, + dev->name, dev); + if (err) { + dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); + goto err_unmap_base; + } + + dev->base_addr = (unsigned long)ag->mac_base; + dev->netdev_ops = &ag71xx_netdev_ops; + dev->ethtool_ops = &ag71xx_ethtool_ops; + + INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); + + init_timer(&ag->oom_timer); + ag->oom_timer.data = (unsigned long) dev; + ag->oom_timer.function = ag71xx_oom_timer_handler; + + ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT; + ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT; + + ag->stop_desc = dma_alloc_coherent(NULL, + sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL); + + if (!ag->stop_desc) + goto err_free_irq; + + ag->stop_desc->data = 0; + ag->stop_desc->ctrl = 0; + ag->stop_desc->next = (u32) ag->stop_desc_dma; + + memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); + + netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); + + err = register_netdev(dev); + if (err) { + dev_err(&pdev->dev, "unable to register net device\n"); + goto err_free_desc; + } + + pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n", + dev->name, dev->base_addr, dev->irq); + + ag71xx_dump_regs(ag); + + ag71xx_hw_init(ag); + + ag71xx_dump_regs(ag); + + err = ag71xx_phy_connect(ag); + if (err) + goto err_unregister_netdev; + + err = ag71xx_debugfs_init(ag); + if (err) + goto err_phy_disconnect; + + platform_set_drvdata(pdev, dev); + + return 0; + +err_phy_disconnect: + ag71xx_phy_disconnect(ag); +err_unregister_netdev: + unregister_netdev(dev); +err_free_desc: + dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc, + ag->stop_desc_dma); +err_free_irq: + free_irq(dev->irq, dev); +err_unmap_base: + iounmap(ag->mac_base); +err_free_dev: + kfree(dev); +err_out: + platform_set_drvdata(pdev, NULL); + return err; +} + +static int __devexit ag71xx_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + struct ag71xx *ag = netdev_priv(dev); + + ag71xx_debugfs_exit(ag); + ag71xx_phy_disconnect(ag); + unregister_netdev(dev); + free_irq(dev->irq, dev); + iounmap(ag->mac_base); + kfree(dev); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver ag71xx_driver = { + .probe = ag71xx_probe, + .remove = __exit_p(ag71xx_remove), + .driver = { + .name = AG71XX_DRV_NAME, + } +}; + +static int __init ag71xx_module_init(void) +{ + int ret; + + ret = ag71xx_debugfs_root_init(); + if (ret) + goto err_out; + + ret = ag71xx_mdio_driver_init(); + if (ret) + goto err_debugfs_exit; + + ret = platform_driver_register(&ag71xx_driver); + if (ret) + goto err_mdio_exit; + + return 0; + +err_mdio_exit: + ag71xx_mdio_driver_exit(); +err_debugfs_exit: + ag71xx_debugfs_root_exit(); +err_out: + return ret; +} + +static void __exit ag71xx_module_exit(void) +{ + platform_driver_unregister(&ag71xx_driver); + ag71xx_mdio_driver_exit(); + ag71xx_debugfs_root_exit(); +} + +module_init(ag71xx_module_init); +module_exit(ag71xx_module_exit); + +MODULE_VERSION(AG71XX_DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" AG71XX_DRV_NAME); diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c new file mode 100644 index 000000000..e123505c7 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c @@ -0,0 +1,315 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AG71XX_MDIO_RETRY 1000 +#define AG71XX_MDIO_DELAY 5 + +static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, + u32 value) +{ + void __iomem *r; + + r = am->mdio_base + reg; + __raw_writel(value, r); + + /* flush write */ + (void) __raw_readl(r); +} + +static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) +{ + return __raw_readl(am->mdio_base + reg); +} + +static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) +{ + DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", + am->mii_bus->name, + ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), + ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), + ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); + DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", + am->mii_bus->name, + ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), + ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), + ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); +} + +static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am) +{ + int i; + + for (i = 0; i < AG71XX_MDIO_RETRY; i++) { + u32 busy; + + udelay(AG71XX_MDIO_DELAY); + + busy = ag71xx_mdio_rr(am, AG71XX_REG_MII_IND); + if (!busy) + return 0; + + udelay(AG71XX_MDIO_DELAY); + } + + pr_err("%s: MDIO operation timed out\n", am->mii_bus->name); + + return -ETIMEDOUT; +} + +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) +{ + int err; + int ret; + + err = ag71xx_mdio_wait_busy(am); + if (err) + return 0xffff; + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); + + err = ag71xx_mdio_wait_busy(am); + if (err) + return 0xffff; + + ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + + DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); + + return ret; +} + +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val) +{ + DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); + + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); + ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); + + ag71xx_mdio_wait_busy(am); +} + +static const u32 ar71xx_mdio_div_table[] = { + 4, 4, 6, 8, 10, 14, 20, 28, +}; + +static const u32 ar7240_mdio_div_table[] = { + 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, +}; + +static const u32 ar933x_mdio_div_table[] = { + 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, +}; + +static int ag71xx_mdio_get_divider(struct ag71xx_mdio *am, u32 *div) +{ + unsigned long ref_clock, mdio_clock; + const u32 *table; + int ndivs; + int i; + + ref_clock = am->pdata->ref_clock; + mdio_clock = am->pdata->mdio_clock; + + if (!ref_clock || !mdio_clock) + return -EINVAL; + + if (am->pdata->is_ar9330 || am->pdata->is_ar934x) { + table = ar933x_mdio_div_table; + ndivs = ARRAY_SIZE(ar933x_mdio_div_table); + } else if (am->pdata->is_ar7240) { + table = ar7240_mdio_div_table; + ndivs = ARRAY_SIZE(ar7240_mdio_div_table); + } else { + table = ar71xx_mdio_div_table; + ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); + } + + for (i = 0; i < ndivs; i++) { + unsigned long t; + + t = ref_clock / table[i]; + if (t <= mdio_clock) { + *div = i; + return 0; + } + } + + dev_err(&am->mii_bus->dev, "no divider found for %lu/%lu\n", + ref_clock, mdio_clock); + return -ENOENT; +} + +static int ag71xx_mdio_reset(struct mii_bus *bus) +{ + struct ag71xx_mdio *am = bus->priv; + u32 t; + int err; + + err = ag71xx_mdio_get_divider(am, &t); + if (err) { + /* fallback */ + if (am->pdata->is_ar7240) + t = MII_CFG_CLK_DIV_6; + else if (am->pdata->builtin_switch && !am->pdata->is_ar934x) + t = MII_CFG_CLK_DIV_10; + else if (!am->pdata->builtin_switch && am->pdata->is_ar934x) + t = MII_CFG_CLK_DIV_58; + else + t = MII_CFG_CLK_DIV_28; + } + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); + udelay(100); + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); + udelay(100); + + return 0; +} + +static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) +{ + struct ag71xx_mdio *am = bus->priv; + + if (am->pdata->builtin_switch) + return ar7240sw_phy_read(bus, addr, reg); + else + return ag71xx_mdio_mii_read(am, addr, reg); +} + +static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct ag71xx_mdio *am = bus->priv; + + if (am->pdata->builtin_switch) + ar7240sw_phy_write(bus, addr, reg, val); + else + ag71xx_mdio_mii_write(am, addr, reg, val); + return 0; +} + +static int __devinit ag71xx_mdio_probe(struct platform_device *pdev) +{ + struct ag71xx_mdio_platform_data *pdata; + struct ag71xx_mdio *am; + struct resource *res; + int i; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + am = kzalloc(sizeof(*am), GFP_KERNEL); + if (!am) { + err = -ENOMEM; + goto err_out; + } + + am->pdata = pdata; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no iomem resource found\n"); + err = -ENXIO; + goto err_out; + } + + am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!am->mdio_base) { + dev_err(&pdev->dev, "unable to ioremap registers\n"); + err = -ENOMEM; + goto err_free_mdio; + } + + am->mii_bus = mdiobus_alloc(); + if (am->mii_bus == NULL) { + err = -ENOMEM; + goto err_iounmap; + } + + am->mii_bus->name = "ag71xx_mdio"; + am->mii_bus->read = ag71xx_mdio_read; + am->mii_bus->write = ag71xx_mdio_write; + am->mii_bus->reset = ag71xx_mdio_reset; + am->mii_bus->irq = am->mii_irq; + am->mii_bus->priv = am; + am->mii_bus->parent = &pdev->dev; + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); + am->mii_bus->phy_mask = pdata->phy_mask; + + for (i = 0; i < PHY_MAX_ADDR; i++) + am->mii_irq[i] = PHY_POLL; + + ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); + + err = mdiobus_register(am->mii_bus); + if (err) + goto err_free_bus; + + ag71xx_mdio_dump_regs(am); + + platform_set_drvdata(pdev, am); + return 0; + +err_free_bus: + mdiobus_free(am->mii_bus); +err_iounmap: + iounmap(am->mdio_base); +err_free_mdio: + kfree(am); +err_out: + return err; +} + +static int __devexit ag71xx_mdio_remove(struct platform_device *pdev) +{ + struct ag71xx_mdio *am = platform_get_drvdata(pdev); + + if (am) { + mdiobus_unregister(am->mii_bus); + mdiobus_free(am->mii_bus); + iounmap(am->mdio_base); + kfree(am); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver ag71xx_mdio_driver = { + .probe = ag71xx_mdio_probe, + .remove = __exit_p(ag71xx_mdio_remove), + .driver = { + .name = "ag71xx-mdio", + } +}; + +int __init ag71xx_mdio_driver_init(void) +{ + return platform_driver_register(&ag71xx_mdio_driver); +} + +void ag71xx_mdio_driver_exit(void) +{ + platform_driver_unregister(&ag71xx_mdio_driver); +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c new file mode 100644 index 000000000..ebdbc5b9a --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c @@ -0,0 +1,235 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +static void ag71xx_phy_link_adjust(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&ag->lock, flags); + + if (phydev->link) { + if (ag->duplex != phydev->duplex + || ag->speed != phydev->speed) { + status_change = 1; + } + } + + if (phydev->link != ag->link) + status_change = 1; + + ag->link = phydev->link; + ag->duplex = phydev->duplex; + ag->speed = phydev->speed; + + if (status_change) + ag71xx_link_adjust(ag); + + spin_unlock_irqrestore(&ag->lock, flags); +} + +void ag71xx_phy_start(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (ag->phy_dev) { + phy_start(ag->phy_dev); + } else if (pdata->switch_data) { + ag71xx_ar7240_start(ag); + } else { + ag->link = 1; + ag71xx_link_adjust(ag); + } +} + +void ag71xx_phy_stop(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + unsigned long flags; + + if (ag->phy_dev) + phy_stop(ag->phy_dev); + else if (pdata->switch_data) + ag71xx_ar7240_stop(ag); + + spin_lock_irqsave(&ag->lock, flags); + if (ag->link) { + ag->link = 0; + ag71xx_link_adjust(ag); + } + spin_unlock_irqrestore(&ag->lock, flags); +} + +static int ag71xx_phy_connect_fixed(struct ag71xx *ag) +{ + struct net_device *dev = ag->dev; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + int ret = 0; + + /* use fixed settings */ + switch (pdata->speed) { + case SPEED_10: + case SPEED_100: + case SPEED_1000: + break; + default: + netdev_err(dev, "invalid speed specified\n"); + ret = -EINVAL; + break; + } + + netdev_dbg(dev, "using fixed link parameters\n"); + + ag->duplex = pdata->duplex; + ag->speed = pdata->speed; + + return ret; +} + +static int ag71xx_phy_connect_multi(struct ag71xx *ag) +{ + struct net_device *dev = ag->dev; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct phy_device *phydev = NULL; + int phy_addr; + int ret = 0; + + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (!(pdata->phy_mask & (1 << phy_addr))) + continue; + + if (ag->mii_bus->phy_map[phy_addr] == NULL) + continue; + + DBG("%s: PHY found at %s, uid=%08x\n", + dev->name, + dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), + ag->mii_bus->phy_map[phy_addr]->phy_id); + + if (phydev == NULL) + phydev = ag->mii_bus->phy_map[phy_addr]; + } + + if (!phydev) { + netdev_err(dev, "no PHY found with phy_mask=%08x\n", + pdata->phy_mask); + return -ENODEV; + } + + ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), + &ag71xx_phy_link_adjust, 0, + pdata->phy_if_mode); + + if (IS_ERR(ag->phy_dev)) { + netdev_err(dev, "could not connect to PHY at %s\n", + dev_name(&phydev->dev)); + return PTR_ERR(ag->phy_dev); + } + + /* mask with MAC supported features */ + if (pdata->has_gbit) + phydev->supported &= PHY_GBIT_FEATURES; + else + phydev->supported &= PHY_BASIC_FEATURES; + + phydev->advertising = phydev->supported; + + netdev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n", + dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name); + + ag->link = 0; + ag->speed = 0; + ag->duplex = -1; + + return ret; +} + +static int dev_is_class(struct device *dev, void *class) +{ + if (dev->class != NULL && !strcmp(dev->class->name, class)) + return 1; + + return 0; +} + +static struct device *dev_find_class(struct device *parent, char *class) +{ + if (dev_is_class(parent, class)) { + get_device(parent); + return parent; + } + + return device_find_child(parent, class, dev_is_class); +} + +static struct mii_bus *dev_to_mii_bus(struct device *dev) +{ + struct device *d; + + d = dev_find_class(dev, "mdio_bus"); + if (d != NULL) { + struct mii_bus *bus; + + bus = to_mii_bus(d); + put_device(d); + + return bus; + } + + return NULL; +} + +int __devinit ag71xx_phy_connect(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (pdata->mii_bus_dev == NULL || + pdata->mii_bus_dev->bus == NULL ) + return ag71xx_phy_connect_fixed(ag); + + ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); + if (ag->mii_bus == NULL) { + netdev_err(ag->dev, "unable to find MII bus on device '%s'\n", + dev_name(pdata->mii_bus_dev)); + return -ENODEV; + } + + /* Reset the mdio bus explicitly */ + if (ag->mii_bus->reset) { + mutex_lock(&ag->mii_bus->mdio_lock); + ag->mii_bus->reset(ag->mii_bus); + mutex_unlock(&ag->mii_bus->mdio_lock); + } + + if (pdata->switch_data) + return ag71xx_ar7240_init(ag); + + if (pdata->phy_mask) + return ag71xx_phy_connect_multi(ag); + + return ag71xx_phy_connect_fixed(ag); +} + +void ag71xx_phy_disconnect(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (pdata->switch_data) + ag71xx_ar7240_cleanup(ag); + else if (ag->phy_dev) + phy_disconnect(ag->phy_dev); +} diff --git a/target/linux/ar71xx/files/drivers/spi/spi-ap83.c b/target/linux/ar71xx/files/drivers/spi/spi-ap83.c new file mode 100644 index 000000000..33843a6da --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-ap83.c @@ -0,0 +1,283 @@ +/* + * Atheros AP83 board specific SPI Controller driver + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/workqueue.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_bitbang.h> +#include <linux/bitops.h> +#include <linux/gpio.h> + +#include <asm/mach-ath79/ath79.h> + +#define DRV_DESC "Atheros AP83 board SPI Controller driver" +#define DRV_VERSION "0.1.0" +#define DRV_NAME "ap83-spi" + +#define AP83_SPI_CLK_HIGH (1 << 23) +#define AP83_SPI_CLK_LOW 0 +#define AP83_SPI_MOSI_HIGH (1 << 22) +#define AP83_SPI_MOSI_LOW 0 + +#define AP83_SPI_GPIO_CS 1 +#define AP83_SPI_GPIO_MISO 3 + +struct ap83_spi { + struct spi_bitbang bitbang; + void __iomem *base; + u32 addr; + + struct platform_device *pdev; +}; + +static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) +{ + return __raw_readl(sp->base + reg); +} + +static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static inline void setsck(struct spi_device *spi, int val) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + if (val) + sp->addr |= AP83_SPI_CLK_HIGH; + else + sp->addr &= ~AP83_SPI_CLK_HIGH; + + dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", + sp->addr, (val) ? "HIGH" : "LOW"); + + ap83_spi_rr(sp, sp->addr); +} + +static inline void setmosi(struct spi_device *spi, int val) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + if (val) + sp->addr |= AP83_SPI_MOSI_HIGH; + else + sp->addr &= ~AP83_SPI_MOSI_HIGH; + + dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", + sp->addr, (val) ? "HIGH" : "LOW"); + + ap83_spi_rr(sp, sp->addr); +} + +static inline u32 getmiso(struct spi_device *spi) +{ + u32 ret; + + ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; + dev_dbg(&spi->dev, "get MISO: %d\n", ret); + + return ret; +} + +static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) +{ + ndelay(nsecs); +} + +static void ap83_spi_chipselect(struct spi_device *spi, int on) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); + + if (on) { + ath79_flash_acquire(); + + sp->addr = 0; + ap83_spi_rr(sp, sp->addr); + + gpio_set_value(AP83_SPI_GPIO_CS, 0); + } else { + gpio_set_value(AP83_SPI_GPIO_CS, 1); + ath79_flash_release(); + } +} + +#define spidelay(nsecs) \ + do { \ + /* Steal the spi_device pointer from our caller. \ + * The bitbang-API should probably get fixed here... */ \ + do_spidelay(spi, nsecs); \ + } while (0) + +#define EXPAND_BITBANG_TXRX +#include <linux/spi/spi_bitbang.h> +#include "spi-bitbang-txrx.h" + +static u32 ap83_spi_txrx_mode0(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode1(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode2(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode3(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); +} + +static int ap83_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct ap83_spi *sp; + struct ap83_spi_platform_data *pdata; + struct resource *r; + int ret; + + ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); + if (ret) { + dev_err(&pdev->dev, "gpio request failed for MISO\n"); + return ret; + } + + ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); + if (ret) { + dev_err(&pdev->dev, "gpio request failed for CS\n"); + goto err_free_miso; + } + + ret = gpio_direction_input(AP83_SPI_GPIO_MISO); + if (ret) { + dev_err(&pdev->dev, "unable to set direction of MISO\n"); + goto err_free_cs; + } + + ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set direction of CS\n"); + goto err_free_cs; + } + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); + return -ENOMEM; + } + + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + + pdata = pdev->dev.platform_data; + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ap83_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; + sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; + sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; + sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; + + sp->bitbang.master->bus_num = pdev->id; + sp->bitbang.master->num_chipselect = 1; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + ret = -ENOENT; + goto err_spi_put; + } + + sp->base = ioremap_nocache(r->start, r->end - r->start + 1); + if (!sp->base) { + ret = -ENXIO; + goto err_spi_put; + } + + ret = spi_bitbang_start(&sp->bitbang); + if (!ret) + goto err_unmap; + + dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); + + return 0; + +err_unmap: + iounmap(sp->base); +err_spi_put: + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + +err_free_cs: + gpio_free(AP83_SPI_GPIO_CS); +err_free_miso: + gpio_free(AP83_SPI_GPIO_MISO); + return ret; +} + +static int ap83_spi_remove(struct platform_device *pdev) +{ + struct ap83_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return 0; +} + +static struct platform_driver ap83_spi_drv = { + .probe = ap83_spi_probe, + .remove = ap83_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ap83_spi_init(void) +{ + return platform_driver_register(&ap83_spi_drv); +} +module_init(ap83_spi_init); + +static void __exit ap83_spi_exit(void) +{ + platform_driver_unregister(&ap83_spi_drv); +} +module_exit(ap83_spi_exit); + +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c new file mode 100644 index 000000000..4e8ce3105 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c @@ -0,0 +1,441 @@ +/* + * SPI driver for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/bitops.h> +#include <linux/spi/spi.h> +#include <linux/gpio.h> +#include <linux/slab.h> + +#include <asm/mach-ath79/rb4xx_cpld.h> + +#define DRV_NAME "spi-rb4xx-cpld" +#define DRV_DESC "RB4xx CPLD driver" +#define DRV_VERSION "0.1.0" + +#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send indle */ +#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ +#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */ +#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ +#define CPLD_CMD_LED5_ON 0x0c /* send cmd */ +#define CPLD_CMD_LED5_OFF 0x0d /* send cmd */ + +struct rb4xx_cpld { + struct spi_device *spi; + struct mutex lock; + struct gpio_chip chip; + unsigned int config; +}; + +static struct rb4xx_cpld *rb4xx_cpld; + +static inline struct rb4xx_cpld *gpio_to_cpld(struct gpio_chip *chip) +{ + return container_of(chip, struct rb4xx_cpld, chip); +} + +static int rb4xx_cpld_write_cmd(struct rb4xx_cpld *cpld, unsigned char cmd) +{ + struct spi_transfer t[1]; + struct spi_message m; + unsigned char tx_buf[1]; + int err; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = tx_buf; + t[0].len = sizeof(tx_buf); + spi_message_add_tail(&t[0], &m); + + tx_buf[0] = cmd; + + err = spi_sync(cpld->spi, &m); + return err; +} + +static int rb4xx_cpld_write_cfg(struct rb4xx_cpld *cpld, unsigned char config) +{ + struct spi_transfer t[1]; + struct spi_message m; + unsigned char cmd[2]; + int err; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_WRITE_CFG; + cmd[1] = config; + + err = spi_sync(cpld->spi, &m); + return err; +} + +static int __rb4xx_cpld_change_cfg(struct rb4xx_cpld *cpld, unsigned mask, + unsigned value) +{ + unsigned int config; + int err; + + config = cpld->config & ~mask; + config |= value; + + if ((cpld->config ^ config) & 0xff) { + err = rb4xx_cpld_write_cfg(cpld, config); + if (err) + return err; + } + + if ((cpld->config ^ config) & CPLD_CFG_nLED5) { + err = rb4xx_cpld_write_cmd(cpld, (value) ? CPLD_CMD_LED5_ON : + CPLD_CMD_LED5_OFF); + if (err) + return err; + } + + cpld->config = config; + return 0; +} + +int rb4xx_cpld_change_cfg(unsigned mask, unsigned value) +{ + int ret; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + mutex_lock(&rb4xx_cpld->lock); + ret = __rb4xx_cpld_change_cfg(rb4xx_cpld, mask, value); + mutex_unlock(&rb4xx_cpld->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_change_cfg); + +int rb4xx_cpld_read_from(unsigned addr, unsigned char *rx_buf, + const unsigned char *verify_buf, unsigned count) +{ + const unsigned char cmd[5] = { + CPLD_CMD_READ_FAST, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + addr & 0xff, + 0 + }; + struct spi_transfer t[2] = { + { + .tx_buf = &cmd, + .len = 5, + }, + { + .tx_buf = verify_buf, + .rx_buf = rx_buf, + .len = count, + .verify = (verify_buf != NULL), + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + m.fast_read = 1; + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + return spi_sync(rb4xx_cpld->spi, &m); +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_read_from); + +#if 0 +int rb4xx_cpld_read(unsigned char *buf, unsigned char *verify_buf, + unsigned count) +{ + struct spi_transfer t[2]; + struct spi_message m; + unsigned char cmd[2]; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + /* send command */ + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_READ_NAND; + cmd[1] = 0; + + /* read data */ + t[1].rx_buf = buf; + t[1].len = count; + spi_message_add_tail(&t[1], &m); + + return spi_sync(rb4xx_cpld->spi, &m); +} +#else +int rb4xx_cpld_read(unsigned char *rx_buf, const unsigned char *verify_buf, + unsigned count) +{ + static const unsigned char cmd[2] = { CPLD_CMD_READ_NAND, 0 }; + struct spi_transfer t[2] = { + { + .tx_buf = &cmd, + .len = 2, + }, { + .tx_buf = verify_buf, + .rx_buf = rx_buf, + .len = count, + .verify = (verify_buf != NULL), + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + return spi_sync(rb4xx_cpld->spi, &m); +} +#endif +EXPORT_SYMBOL_GPL(rb4xx_cpld_read); + +int rb4xx_cpld_write(const unsigned char *buf, unsigned count) +{ +#if 0 + struct spi_transfer t[3]; + struct spi_message m; + unsigned char cmd[1]; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + memset(&t, 0, sizeof(t)); + spi_message_init(&m); + + /* send command */ + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_WRITE_NAND; + + /* write data */ + t[1].tx_buf = buf; + t[1].len = count; + spi_message_add_tail(&t[1], &m); + + /* send idle */ + t[2].len = 1; + spi_message_add_tail(&t[2], &m); + + return spi_sync(rb4xx_cpld->spi, &m); +#else + static const unsigned char cmd = CPLD_CMD_WRITE_NAND; + struct spi_transfer t[3] = { + { + .tx_buf = &cmd, + .len = 1, + }, { + .tx_buf = buf, + .len = count, + .fast_write = 1, + }, { + .len = 1, + .fast_write = 1, + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + return spi_sync(rb4xx_cpld->spi, &m); +#endif +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_write); + +static int rb4xx_cpld_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + int ret; + + mutex_lock(&cpld->lock); + ret = (cpld->config >> offset) & 1; + mutex_unlock(&cpld->lock); + + return ret; +} + +static void rb4xx_cpld_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + + mutex_lock(&cpld->lock); + __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); + mutex_unlock(&cpld->lock); +} + +static int rb4xx_cpld_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + return -EOPNOTSUPP; +} + +static int rb4xx_cpld_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + int ret; + + mutex_lock(&cpld->lock); + ret = __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); + mutex_unlock(&cpld->lock); + + return ret; +} + +static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base) +{ + int err; + + /* init config */ + cpld->config = CPLD_CFG_nLED1 | CPLD_CFG_nLED2 | CPLD_CFG_nLED3 | + CPLD_CFG_nLED4 | CPLD_CFG_nCE; + rb4xx_cpld_write_cfg(cpld, cpld->config); + + /* setup GPIO chip */ + cpld->chip.label = DRV_NAME; + + cpld->chip.get = rb4xx_cpld_gpio_get; + cpld->chip.set = rb4xx_cpld_gpio_set; + cpld->chip.direction_input = rb4xx_cpld_gpio_direction_input; + cpld->chip.direction_output = rb4xx_cpld_gpio_direction_output; + + cpld->chip.base = base; + cpld->chip.ngpio = CPLD_NUM_GPIOS; + cpld->chip.can_sleep = 1; + cpld->chip.dev = &cpld->spi->dev; + cpld->chip.owner = THIS_MODULE; + + err = gpiochip_add(&cpld->chip); + if (err) + dev_err(&cpld->spi->dev, "adding GPIO chip failed, err=%d\n", + err); + + return err; +} + +static int __devinit rb4xx_cpld_probe(struct spi_device *spi) +{ + struct rb4xx_cpld *cpld; + struct rb4xx_cpld_platform_data *pdata; + int err; + + pdata = spi->dev.platform_data; + if (!pdata) { + dev_dbg(&spi->dev, "no platform data\n"); + return -EINVAL; + } + + cpld = kzalloc(sizeof(*cpld), GFP_KERNEL); + if (!cpld) { + dev_err(&spi->dev, "no memory for private data\n"); + return -ENOMEM; + } + + mutex_init(&cpld->lock); + cpld->spi = spi_dev_get(spi); + dev_set_drvdata(&spi->dev, cpld); + + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + err = spi_setup(spi); + if (err) { + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); + goto err_drvdata; + } + + err = rb4xx_cpld_gpio_init(cpld, pdata->gpio_base); + if (err) + goto err_drvdata; + + rb4xx_cpld = cpld; + + return 0; + +err_drvdata: + dev_set_drvdata(&spi->dev, NULL); + kfree(cpld); + + return err; +} + +static int __devexit rb4xx_cpld_remove(struct spi_device *spi) +{ + struct rb4xx_cpld *cpld; + + rb4xx_cpld = NULL; + cpld = dev_get_drvdata(&spi->dev); + dev_set_drvdata(&spi->dev, NULL); + kfree(cpld); + + return 0; +} + +static struct spi_driver rb4xx_cpld_driver = { + .driver = { + .name = DRV_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = rb4xx_cpld_probe, + .remove = __devexit_p(rb4xx_cpld_remove), +}; + +static int __init rb4xx_cpld_init(void) +{ + return spi_register_driver(&rb4xx_cpld_driver); +} +module_init(rb4xx_cpld_init); + +static void __exit rb4xx_cpld_exit(void) +{ + spi_unregister_driver(&rb4xx_cpld_driver); +} +module_exit(rb4xx_cpld_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c new file mode 100644 index 000000000..56260ffc9 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c @@ -0,0 +1,507 @@ +/* + * SPI controller driver for the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/workqueue.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#define DRV_NAME "rb4xx-spi" +#define DRV_DESC "Mikrotik RB4xx SPI controller driver" +#define DRV_VERSION "0.1.0" + +#define SPI_CTRL_FASTEST 0x40 +#define SPI_FLASH_HZ 33333334 +#define SPI_CPLD_HZ 33333334 + +#define CPLD_CMD_READ_FAST 0x0b + +#undef RB4XX_SPI_DEBUG + +struct rb4xx_spi { + void __iomem *base; + struct spi_master *master; + + unsigned spi_ctrl_flash; + unsigned spi_ctrl_fread; + + struct clk *ahb_clk; + unsigned long ahb_freq; + + spinlock_t lock; + struct list_head queue; + int busy:1; + int cs_wait; +}; + +static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1; + +#ifdef RB4XX_SPI_DEBUG +static inline void do_spi_delay(void) +{ + ndelay(20000); +} +#else +static inline void do_spi_delay(void) { } +#endif + +static inline void do_spi_init(struct spi_device *spi) +{ + unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1; + + if (!(spi->mode & SPI_CS_HIGH)) + cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 : + AR71XX_SPI_IOC_CS0; + + spi_clk_low = cs; +} + +static inline void do_spi_finish(void __iomem *base) +{ + do_spi_delay(); + __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1, + base + AR71XX_SPI_REG_IOC); +} + +static inline void do_spi_clk(void __iomem *base, int bit) +{ + unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0); + + do_spi_delay(); + __raw_writel(bval, base + AR71XX_SPI_REG_IOC); + do_spi_delay(); + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); +} + +static void do_spi_byte(void __iomem *base, unsigned char byte) +{ + do_spi_clk(base, byte >> 7); + do_spi_clk(base, byte >> 6); + do_spi_clk(base, byte >> 5); + do_spi_clk(base, byte >> 4); + do_spi_clk(base, byte >> 3); + do_spi_clk(base, byte >> 2); + do_spi_clk(base, byte >> 1); + do_spi_clk(base, byte); + + pr_debug("spi_byte sent 0x%02x got 0x%02x\n", + (unsigned)byte, + (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS)); +} + +static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, + unsigned bit2) +{ + unsigned bval = (spi_clk_low | + ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) | + ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0)); + do_spi_delay(); + __raw_writel(bval, base + AR71XX_SPI_REG_IOC); + do_spi_delay(); + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); +} + +static void do_spi_byte_fast(void __iomem *base, unsigned char byte) +{ + do_spi_clk_fast(base, byte >> 7, byte >> 6); + do_spi_clk_fast(base, byte >> 5, byte >> 4); + do_spi_clk_fast(base, byte >> 3, byte >> 2); + do_spi_clk_fast(base, byte >> 1, byte >> 0); + + pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n", + (unsigned)byte, + (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS)); +} + +static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t) +{ + const unsigned char *rxv_ptr = NULL; + const unsigned char *tx_ptr = t->tx_buf; + unsigned char *rx_ptr = t->rx_buf; + unsigned i; + + pr_debug("spi_txrx len %u tx %u rx %u\n", + t->len, + (t->tx_buf ? 1 : 0), + (t->rx_buf ? 1 : 0)); + + if (t->verify) { + rxv_ptr = tx_ptr; + tx_ptr = NULL; + } + + for (i = 0; i < t->len; ++i) { + unsigned char sdata = tx_ptr ? tx_ptr[i] : 0; + + if (t->fast_write) + do_spi_byte_fast(base, sdata); + else + do_spi_byte(base, sdata); + + if (rx_ptr) { + rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff; + } else if (rxv_ptr) { + unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS); + if (rxv_ptr[i] != c) + return i; + } + } + + return i; +} + +static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi, + struct spi_message *m) +{ + struct spi_transfer *t; + const unsigned char *tx_ptr; + unsigned addr; + void __iomem *base = rbspi->base; + + /* check for exactly two transfers */ + if (list_empty(&m->transfers) || + list_is_last(m->transfers.next, &m->transfers) || + !list_is_last(m->transfers.next->next, &m->transfers)) { + return -1; + } + + /* first transfer contains command and address */ + t = list_entry(m->transfers.next, + struct spi_transfer, transfer_list); + + if (t->len != 5 || t->tx_buf == NULL) + return -1; + + tx_ptr = t->tx_buf; + if (tx_ptr[0] != CPLD_CMD_READ_FAST) + return -1; + + addr = tx_ptr[1]; + addr = tx_ptr[2] | (addr << 8); + addr = tx_ptr[3] | (addr << 8); + addr += (unsigned) base; + + m->actual_length += t->len; + + /* second transfer contains data itself */ + t = list_entry(m->transfers.next->next, + struct spi_transfer, transfer_list); + + if (t->tx_buf && !t->verify) + return -1; + + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + + if (t->rx_buf) { + memcpy(t->rx_buf, (const void *)addr, t->len); + } else if (t->tx_buf) { + unsigned char buf[t->len]; + memcpy(buf, (const void *)addr, t->len); + if (memcmp(t->tx_buf, buf, t->len) != 0) + m->status = -EMSGSIZE; + } + m->actual_length += t->len; + + if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) { + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + } + + return 0; +} + +static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m) +{ + struct spi_transfer *t = NULL; + void __iomem *base = rbspi->base; + + m->status = 0; + if (list_empty(&m->transfers)) + return -1; + + if (m->fast_read) + if (rb4xx_spi_read_fast(rbspi, m) == 0) + return -1; + + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL); + do_spi_init(m->spi); + + list_for_each_entry(t, &m->transfers, transfer_list) { + int len; + + len = rb4xx_spi_txrx(base, t); + if (len != t->len) { + m->status = -EMSGSIZE; + break; + } + m->actual_length += len; + + if (t->cs_change) { + if (list_is_last(&t->transfer_list, &m->transfers)) { + /* wait for continuation */ + return m->spi->chip_select; + } + do_spi_finish(base); + ndelay(100); + } + } + + do_spi_finish(base); + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + return -1; +} + +static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi, + unsigned long *flags) +{ + int cs = rbspi->cs_wait; + + rbspi->busy = 1; + while (!list_empty(&rbspi->queue)) { + struct spi_message *m; + + list_for_each_entry(m, &rbspi->queue, queue) + if (cs < 0 || cs == m->spi->chip_select) + break; + + if (&m->queue == &rbspi->queue) + break; + + list_del_init(&m->queue); + spin_unlock_irqrestore(&rbspi->lock, *flags); + + cs = rb4xx_spi_msg(rbspi, m); + m->complete(m->context); + + spin_lock_irqsave(&rbspi->lock, *flags); + } + + rbspi->cs_wait = cs; + rbspi->busy = 0; + + if (cs >= 0) { + /* TODO: add timer to unlock cs after 1s inactivity */ + } +} + +static int rb4xx_spi_transfer(struct spi_device *spi, + struct spi_message *m) +{ + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); + unsigned long flags; + + m->actual_length = 0; + m->status = -EINPROGRESS; + + spin_lock_irqsave(&rbspi->lock, flags); + list_add_tail(&m->queue, &rbspi->queue); + if (rbspi->busy || + (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) { + /* job will be done later */ + spin_unlock_irqrestore(&rbspi->lock, flags); + return 0; + } + + /* process job in current context */ + rb4xx_spi_process_queue_locked(rbspi, &flags); + spin_unlock_irqrestore(&rbspi->lock, flags); + + return 0; +} + +static int rb4xx_spi_setup(struct spi_device *spi) +{ + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); + unsigned long flags; + + if (spi->mode & ~(SPI_CS_HIGH)) { + dev_err(&spi->dev, "mode %x not supported\n", + (unsigned) spi->mode); + return -EINVAL; + } + + if (spi->bits_per_word != 8 && spi->bits_per_word != 0) { + dev_err(&spi->dev, "bits_per_word %u not supported\n", + (unsigned) spi->bits_per_word); + return -EINVAL; + } + + spin_lock_irqsave(&rbspi->lock, flags); + if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) { + rbspi->cs_wait = -1; + rb4xx_spi_process_queue_locked(rbspi, &flags); + } + spin_unlock_irqrestore(&rbspi->lock, flags); + + return 0; +} + +static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max, + const char *name) +{ + unsigned div; + + div = (rbspi->ahb_freq - 1) / (2 * hz_max); + + /* + * CPU has a bug at (div == 0) - first bit read is random + */ + if (div == 0) + ++div; + + if (name) { + unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000; + unsigned div_real = 2 * (div + 1); + pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n", + name, + ahb_khz / div_real, + ahb_khz, div_real); + } + + return SPI_CTRL_FASTEST + div; +} + +static int rb4xx_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct rb4xx_spi *rbspi; + struct resource *r; + int err = 0; + + master = spi_alloc_master(&pdev->dev, sizeof(*rbspi)); + if (master == NULL) { + dev_err(&pdev->dev, "no memory for spi_master\n"); + err = -ENOMEM; + goto err_out; + } + + master->bus_num = 0; + master->num_chipselect = 3; + master->setup = rb4xx_spi_setup; + master->transfer = rb4xx_spi_transfer; + + rbspi = spi_master_get_devdata(master); + + rbspi->ahb_clk = clk_get(&pdev->dev, "ahb"); + if (IS_ERR(rbspi->ahb_clk)) { + err = PTR_ERR(rbspi->ahb_clk); + goto err_put_master; + } + + err = clk_enable(rbspi->ahb_clk); + if (err) + goto err_clk_put; + + rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk); + if (!rbspi->ahb_freq) { + err = -EINVAL; + goto err_clk_disable; + } + + platform_set_drvdata(pdev, rbspi); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + err = -ENOENT; + goto err_clk_disable; + } + + rbspi->base = ioremap(r->start, r->end - r->start + 1); + if (!rbspi->base) { + err = -ENXIO; + goto err_clk_disable; + } + + rbspi->master = master; + rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH"); + rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD"); + rbspi->cs_wait = -1; + + spin_lock_init(&rbspi->lock); + INIT_LIST_HEAD(&rbspi->queue); + + err = spi_register_master(master); + if (err) { + dev_err(&pdev->dev, "failed to register SPI master\n"); + goto err_iounmap; + } + + return 0; + +err_iounmap: + iounmap(rbspi->base); +err_clk_disable: + clk_disable(rbspi->ahb_clk); +err_clk_put: + clk_put(rbspi->ahb_clk); +err_put_master: + platform_set_drvdata(pdev, NULL); + spi_master_put(master); +err_out: + return err; +} + +static int rb4xx_spi_remove(struct platform_device *pdev) +{ + struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); + + iounmap(rbspi->base); + clk_disable(rbspi->ahb_clk); + clk_put(rbspi->ahb_clk); + platform_set_drvdata(pdev, NULL); + spi_master_put(rbspi->master); + + return 0; +} + +static struct platform_driver rb4xx_spi_drv = { + .probe = rb4xx_spi_probe, + .remove = rb4xx_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb4xx_spi_init(void) +{ + return platform_driver_register(&rb4xx_spi_drv); +} +subsys_initcall(rb4xx_spi_init); + +static void __exit rb4xx_spi_exit(void) +{ + platform_driver_unregister(&rb4xx_spi_drv); +} + +module_exit(rb4xx_spi_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c b/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c new file mode 100644 index 000000000..9340df268 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c @@ -0,0 +1,621 @@ +/* + * SPI driver for the Vitesse VSC7385 ethernet switch + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/bitops.h> +#include <linux/firmware.h> +#include <linux/spi/spi.h> +#include <linux/spi/vsc7385.h> + +#define DRV_NAME "spi-vsc7385" +#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" +#define DRV_VERSION "0.1.0" + +#define VSC73XX_BLOCK_MAC 0x1 +#define VSC73XX_BLOCK_2 0x2 +#define VSC73XX_BLOCK_MII 0x3 +#define VSC73XX_BLOCK_4 0x4 +#define VSC73XX_BLOCK_5 0x5 +#define VSC73XX_BLOCK_SYSTEM 0x7 + +#define VSC73XX_SUBBLOCK_PORT_0 0 +#define VSC73XX_SUBBLOCK_PORT_1 1 +#define VSC73XX_SUBBLOCK_PORT_2 2 +#define VSC73XX_SUBBLOCK_PORT_3 3 +#define VSC73XX_SUBBLOCK_PORT_4 4 +#define VSC73XX_SUBBLOCK_PORT_MAC 6 + +/* MAC Block registers */ +#define VSC73XX_MAC_CFG 0x0 +#define VSC73XX_ADVPORTM 0x19 +#define VSC73XX_RXOCT 0x50 +#define VSC73XX_TXOCT 0x51 +#define VSC73XX_C_RX0 0x52 +#define VSC73XX_C_RX1 0x53 +#define VSC73XX_C_RX2 0x54 +#define VSC73XX_C_TX0 0x55 +#define VSC73XX_C_TX1 0x56 +#define VSC73XX_C_TX2 0x57 +#define VSC73XX_C_CFG 0x58 + +/* MAC_CFG register bits */ +#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) +#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) +#define VSC73XX_MAC_CFG_TX_EN (1 << 28) +#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) +#define VSC73XX_MAC_CFG_FDX (1 << 18) +#define VSC73XX_MAC_CFG_GIGE (1 << 17) +#define VSC73XX_MAC_CFG_RX_EN (1 << 16) +#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) +#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) +#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) +#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) +#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) +#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) +#define VSC73XX_MAC_CFG_BIT2 (1 << 2) +#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) + +/* ADVPORTM register bits */ +#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) +#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) +#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) +#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) +#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) +#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) +#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) +#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) + +/* MII Block registers */ +#define VSC73XX_MII_STAT 0x0 +#define VSC73XX_MII_CMD 0x1 +#define VSC73XX_MII_DATA 0x2 + +/* System Block registers */ +#define VSC73XX_ICPU_SIPAD 0x01 +#define VSC73XX_ICPU_CLOCK_DELAY 0x05 +#define VSC73XX_ICPU_CTRL 0x10 +#define VSC73XX_ICPU_ADDR 0x11 +#define VSC73XX_ICPU_SRAM 0x12 +#define VSC73XX_ICPU_MBOX_VAL 0x15 +#define VSC73XX_ICPU_MBOX_SET 0x16 +#define VSC73XX_ICPU_MBOX_CLR 0x17 +#define VSC73XX_ICPU_CHIPID 0x18 +#define VSC73XX_ICPU_GPIO 0x34 + +#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) +#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) +#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) +#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) +#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) +#define VSC73XX_ICPU_CTRL_SRST (1 << 0) + +#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 +#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff +#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 +#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf +#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 +#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 + +#define VSC73XX_CMD_MODE_READ 0 +#define VSC73XX_CMD_MODE_WRITE 1 +#define VSC73XX_CMD_MODE_SHIFT 4 +#define VSC73XX_CMD_BLOCK_SHIFT 5 +#define VSC73XX_CMD_BLOCK_MASK 0x7 +#define VSC73XX_CMD_SUBBLOCK_MASK 0xf + +#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) +#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) + +#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ + VSC73XX_ICPU_CTRL_BOOT_EN | \ + VSC73XX_ICPU_CTRL_EXT_ACC_EN) + +#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ + VSC73XX_ICPU_CTRL_BOOT_EN | \ + VSC73XX_ICPU_CTRL_CLK_EN | \ + VSC73XX_ICPU_CTRL_SRST) + +#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ + VSC73XX_ADVPORTM_EXC_COL_CONT | \ + VSC73XX_ADVPORTM_EXT_PORT | \ + VSC73XX_ADVPORTM_INV_GTX | \ + VSC73XX_ADVPORTM_ENA_GTX | \ + VSC73XX_ADVPORTM_DDR_MODE | \ + VSC73XX_ADVPORTM_IO_LOOPBACK | \ + VSC73XX_ADVPORTM_HOST_LOOPBACK) + +#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ + VSC73XX_ADVPORTM_ENA_GTX | \ + VSC73XX_ADVPORTM_DDR_MODE) + +#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ + VSC73XX_MAC_CFG_MAC_RX_RST | \ + VSC73XX_MAC_CFG_MAC_TX_RST) + +#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ + VSC73XX_MAC_CFG_FDX | \ + VSC73XX_MAC_CFG_GIGE | \ + VSC73XX_MAC_CFG_RX_EN) + +#define VSC73XX_RESET_DELAY 100 + +struct vsc7385 { + struct spi_device *spi; + struct mutex lock; + struct vsc7385_platform_data *pdata; +}; + +static int vsc7385_is_addr_valid(u8 block, u8 subblock) +{ + switch (block) { + case VSC73XX_BLOCK_MAC: + switch (subblock) { + case 0 ... 4: + case 6: + return 1; + } + break; + + case VSC73XX_BLOCK_2: + case VSC73XX_BLOCK_SYSTEM: + switch (subblock) { + case 0: + return 1; + } + break; + + case VSC73XX_BLOCK_MII: + case VSC73XX_BLOCK_4: + case VSC73XX_BLOCK_5: + switch (subblock) { + case 0 ... 1: + return 1; + } + break; + } + + return 0; +} + +static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) +{ + u8 ret; + + ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; + ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; + ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; + + return ret; +} + +static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, + u32 *value) +{ + u8 cmd[4]; + u8 buf[4]; + struct spi_transfer t[2]; + struct spi_message m; + int err; + + if (!vsc7385_is_addr_valid(block, subblock)) + return -EINVAL; + + spi_message_init(&m); + + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + t[1].rx_buf = buf; + t[1].len = sizeof(buf); + spi_message_add_tail(&t[1], &m); + + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); + cmd[1] = reg; + cmd[2] = 0; + cmd[3] = 0; + + mutex_lock(&vsc->lock); + err = spi_sync(vsc->spi, &m); + mutex_unlock(&vsc->lock); + + if (err) + return err; + + *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | + (((u32) buf[2]) << 8) | ((u32) buf[3]); + + return 0; +} + + +static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, + u32 value) +{ + u8 cmd[2]; + u8 buf[4]; + struct spi_transfer t[2]; + struct spi_message m; + int err; + + if (!vsc7385_is_addr_valid(block, subblock)) + return -EINVAL; + + spi_message_init(&m); + + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + t[1].tx_buf = buf; + t[1].len = sizeof(buf); + spi_message_add_tail(&t[1], &m); + + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); + cmd[1] = reg; + + buf[0] = (value >> 24) & 0xff; + buf[1] = (value >> 16) & 0xff; + buf[2] = (value >> 8) & 0xff; + buf[3] = value & 0xff; + + mutex_lock(&vsc->lock); + err = spi_sync(vsc->spi, &m); + mutex_unlock(&vsc->lock); + + return err; +} + +static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, + u8 subblock, u8 reg, u32 value, + u32 read_mask, u32 read_val) +{ + struct spi_device *spi = vsc->spi; + u32 t; + int err; + + err = vsc7385_write(vsc, block, subblock, reg, value); + if (err) + return err; + + err = vsc7385_read(vsc, block, subblock, reg, &t); + if (err) + return err; + + if ((t & read_mask) != read_val) { + dev_err(&spi->dev, "register write error\n"); + return -EIO; + } + + return 0; +} + +static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, val); +} + +static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) +{ + return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, val); +} + +static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, + VSC73XX_ICPU_CTRL_STOP); +} + +static inline int vsc7385_icpu_start(struct vsc7385 *vsc) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, + VSC73XX_ICPU_CTRL_START); +} + +static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) +{ + int rc; + + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, + 0x0000); + if (rc) + dev_err(&vsc->spi->dev, + "could not reset microcode, err=%d\n", rc); + + return rc; +} + +static int vsc7385_upload_ucode(struct vsc7385 *vsc) +{ + struct spi_device *spi = vsc->spi; + const struct firmware *firmware; + char *ucode_name; + unsigned char *dp; + unsigned int curVal; + int i; + int diffs; + int rc; + + ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name + : "vsc7385_ucode.bin"; + rc = request_firmware(&firmware, ucode_name, &spi->dev); + if (rc) { + dev_err(&spi->dev, "request_firmware failed, err=%d\n", + rc); + return rc; + } + + rc = vsc7385_icpu_stop(vsc); + if (rc) + goto out; + + rc = vsc7385_icpu_reset(vsc); + if (rc) + goto out; + + dev_info(&spi->dev, "uploading microcode...\n"); + + dp = (unsigned char *) firmware->data; + for (i = 0; i < firmware->size; i++) { + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_SRAM, *dp++); + if (rc) { + dev_err(&spi->dev, "could not load microcode, err=%d\n", + rc); + goto out; + } + } + + rc = vsc7385_icpu_reset(vsc); + if (rc) + goto out; + + dev_info(&spi->dev, "verifying microcode...\n"); + + dp = (unsigned char *) firmware->data; + diffs = 0; + for (i = 0; i < firmware->size; i++) { + rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_SRAM, &curVal); + if (rc) { + dev_err(&spi->dev, "could not read microcode %d\n", + rc); + goto out; + } + + if (curVal > 0xff) { + dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", + i, *dp, curVal); + rc = -EIO; + goto out; + } + + if ((curVal & 0xff) != *dp) { + diffs++; + dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", + i, *dp, curVal); + + if (diffs > 4) + break; + } + dp++; + } + + if (diffs) { + dev_err(&spi->dev, "microcode verification failed\n"); + rc = -EIO; + goto out; + } + + dev_info(&spi->dev, "microcode uploaded\n"); + + rc = vsc7385_icpu_start(vsc); + +out: + release_firmware(firmware); + return rc; +} + +static int vsc7385_setup(struct vsc7385 *vsc) +{ + struct vsc7385_platform_data *pdata = vsc->pdata; + u32 t; + int err; + + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, + VSC7385_CLOCK_DELAY, + VSC7385_CLOCK_DELAY_MASK, + VSC7385_CLOCK_DELAY); + if (err) + goto err; + + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, + VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, + VSC7385_ADVPORTM_INIT, + VSC7385_ADVPORTM_MASK, + VSC7385_ADVPORTM_INIT); + if (err) + goto err; + + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, + VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); + if (err) + goto err; + + t = VSC73XX_MAC_CFG_INIT; + t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); + t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); + if (pdata->mac_cfg.bit2) + t |= VSC73XX_MAC_CFG_BIT2; + + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, + VSC73XX_MAC_CFG, t); + if (err) + goto err; + + return 0; + +err: + return err; +} + +static int vsc7385_detect(struct vsc7385 *vsc) +{ + struct spi_device *spi = vsc->spi; + u32 t; + u32 id; + u32 rev; + int err; + + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_MBOX_VAL, &t); + if (err) { + dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); + return err; + } + + if (t == 0xffffffff) { + dev_dbg(&spi->dev, "assert chip reset\n"); + if (vsc->pdata->reset) + vsc->pdata->reset(); + + } + + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CHIPID, &t); + if (err) { + dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); + return err; + } + + id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; + switch (id) { + case VSC73XX_ICPU_CHIPID_ID_7385: + case VSC73XX_ICPU_CHIPID_ID_7395: + break; + default: + dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); + return -ENODEV; + } + + rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & + VSC73XX_ICPU_CHIPID_REV_MASK; + dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev); + + return 0; +} + +static int __devinit vsc7385_probe(struct spi_device *spi) +{ + struct vsc7385 *vsc; + struct vsc7385_platform_data *pdata; + int err; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); + + pdata = spi->dev.platform_data; + if (!pdata) { + dev_err(&spi->dev, "no platform data specified\n"); + return -ENODEV; + } + + vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); + if (!vsc) { + dev_err(&spi->dev, "no memory for private data\n"); + return -ENOMEM; + } + + mutex_init(&vsc->lock); + vsc->pdata = pdata; + vsc->spi = spi_dev_get(spi); + dev_set_drvdata(&spi->dev, vsc); + + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + err = spi_setup(spi); + if (err) { + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); + goto err_drvdata; + } + + err = vsc7385_detect(vsc); + if (err) { + dev_err(&spi->dev, "no chip found, err=%d\n", err); + goto err_drvdata; + } + + err = vsc7385_upload_ucode(vsc); + if (err) + goto err_drvdata; + + err = vsc7385_setup(vsc); + if (err) + goto err_drvdata; + + return 0; + +err_drvdata: + dev_set_drvdata(&spi->dev, NULL); + kfree(vsc); + return err; +} + +static int __devexit vsc7385_remove(struct spi_device *spi) +{ + struct vsc7385_data *vsc; + + vsc = dev_get_drvdata(&spi->dev); + dev_set_drvdata(&spi->dev, NULL); + kfree(vsc); + + return 0; +} + +static struct spi_driver vsc7385_driver = { + .driver = { + .name = DRV_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = vsc7385_probe, + .remove = __devexit_p(vsc7385_remove), +}; + +static int __init vsc7385_init(void) +{ + return spi_register_driver(&vsc7385_driver); +} +module_init(vsc7385_init); + +static void __exit vsc7385_exit(void) +{ + spi_unregister_driver(&vsc7385_driver); +} +module_exit(vsc7385_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL v2"); + diff --git a/target/linux/ar71xx/files/include/linux/nxp_74hc153.h b/target/linux/ar71xx/files/include/linux/nxp_74hc153.h new file mode 100644 index 000000000..20b8845e5 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/nxp_74hc153.h @@ -0,0 +1,24 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer defines + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _NXP_74HC153_H +#define _NXP_74HC153_H + +#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" + +struct nxp_74hc153_platform_data { + unsigned gpio_base; + unsigned gpio_pin_s0; + unsigned gpio_pin_s1; + unsigned gpio_pin_1y; + unsigned gpio_pin_2y; +}; + +#endif /* _NXP_74HC153_H */ diff --git a/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h b/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h new file mode 100644 index 000000000..3e4c6d988 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h @@ -0,0 +1,30 @@ +/* + * Platform data definition for the built-in NAND controller of the + * Atheros AR934x SoCs + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _AR934X_NFC_PLATFORM_H +#define _AR934X_NFC_PLATFORM_H + +#define AR934X_NFC_DRIVER_NAME "ar934x-nfc" + +struct mtd_info; +struct mtd_partition; + +struct ar934x_nfc_platform_data { + const char *name; + struct mtd_partition *parts; + int nr_parts; + + void (*hw_reset)(bool active); + void (*select_chip)(int chip_no); + int (*scan_fixup)(struct mtd_info *mtd); +}; + +#endif /* _AR934X_NFC_PLATFORM_H */ diff --git a/target/linux/ar71xx/files/include/linux/spi/vsc7385.h b/target/linux/ar71xx/files/include/linux/spi/vsc7385.h new file mode 100644 index 000000000..1072ad794 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/spi/vsc7385.h @@ -0,0 +1,19 @@ +/* + * Platform data definition for the Vitesse VSC7385 ethernet switch driver + * + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +struct vsc7385_platform_data { + void (*reset)(void); + char *ucode_name; + struct { + u32 tx_ipg:5; + u32 bit2:1; + u32 clk_sel:3; + } mac_cfg; +}; diff --git a/target/linux/ar71xx/files/net/dsa/mv88e6063.c b/target/linux/ar71xx/files/net/dsa/mv88e6063.c new file mode 100644 index 000000000..5638a9fe9 --- /dev/null +++ b/target/linux/ar71xx/files/net/dsa/mv88e6063.c @@ -0,0 +1,294 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips + * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org> + * + * This driver was base on: net/dsa/mv88e6060.c + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips + * Copyright (c) 2008-2009 Marvell Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/list.h> +#include <linux/netdevice.h> +#include <linux/phy.h> +#include "dsa_priv.h" + +#define REG_BASE 0x10 +#define REG_PHY(p) (REG_BASE + (p)) +#define REG_PORT(p) (REG_BASE + 8 + (p)) +#define REG_GLOBAL (REG_BASE + 0x0f) +#define NUM_PORTS 7 + +static int reg_read(struct dsa_switch *ds, int addr, int reg) +{ + return mdiobus_read(ds->master_mii_bus, addr, reg); +} + +#define REG_READ(addr, reg) \ + ({ \ + int __ret; \ + \ + __ret = reg_read(ds, addr, reg); \ + if (__ret < 0) \ + return __ret; \ + __ret; \ + }) + + +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) +{ + return mdiobus_write(ds->master_mii_bus, addr, reg, val); +} + +#define REG_WRITE(addr, reg, val) \ + ({ \ + int __ret; \ + \ + __ret = reg_write(ds, addr, reg, val); \ + if (__ret < 0) \ + return __ret; \ + }) + +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) +{ + int ret; + + ret = mdiobus_read(bus, REG_PORT(0), 0x03); + if (ret >= 0) { + ret &= 0xfff0; + if (ret == 0x1530) + return "Marvell 88E6063"; + } + + return NULL; +} + +static int mv88e6063_switch_reset(struct dsa_switch *ds) +{ + int i; + int ret; + + /* + * Set all ports to the disabled state. + */ + for (i = 0; i < NUM_PORTS; i++) { + ret = REG_READ(REG_PORT(i), 0x04); + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); + } + + /* + * Wait for transmit queues to drain. + */ + msleep(2); + + /* + * Reset the switch. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); + + /* + * Wait up to one second for reset to complete. + */ + for (i = 0; i < 1000; i++) { + ret = REG_READ(REG_GLOBAL, 0x00); + if ((ret & 0x8000) == 0x0000) + break; + + msleep(1); + } + if (i == 1000) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6063_setup_global(struct dsa_switch *ds) +{ + /* + * Disable discarding of frames with excessive collisions, + * set the maximum frame size to 1536 bytes, and mask all + * interrupt sources. + */ + REG_WRITE(REG_GLOBAL, 0x04, 0x0800); + + /* + * Enable automatic address learning, set the address + * database size to 1024 entries, and set the default aging + * time to 5 minutes. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); + + return 0; +} + +static int mv88e6063_setup_port(struct dsa_switch *ds, int p) +{ + int addr = REG_PORT(p); + + /* + * Do not force flow control, disable Ingress and Egress + * Header tagging, disable VLAN tunneling, and set the port + * state to Forwarding. Additionally, if this is the CPU + * port, enable Ingress and Egress Trailer tagging mode. + */ + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); + + /* + * Port based VLAN map: give each port its own address + * database, allow the CPU port to talk to each of the 'real' + * ports, and allow each of the 'real' ports to only talk to + * the CPU port. + */ + REG_WRITE(addr, 0x06, + ((p & 0xf) << 12) | + (dsa_is_cpu_port(ds, p) ? + ds->phys_port_mask : + (1 << ds->dst->cpu_port))); + + /* + * Port Association Vector: when learning source addresses + * of packets, add the address to the address database using + * a port bitmap that has only the bit for this port set and + * the other bits clear. + */ + REG_WRITE(addr, 0x0b, 1 << p); + + return 0; +} + +static int mv88e6063_setup(struct dsa_switch *ds) +{ + int i; + int ret; + + ret = mv88e6063_switch_reset(ds); + if (ret < 0) + return ret; + + /* @@@ initialise atu */ + + ret = mv88e6063_setup_global(ds); + if (ret < 0) + return ret; + + for (i = 0; i < NUM_PORTS; i++) { + ret = mv88e6063_setup_port(ds, i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) +{ + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); + + return 0; +} + +static int mv88e6063_port_to_phy_addr(int port) +{ + if (port >= 0 && port <= NUM_PORTS) + return REG_PHY(port); + return -1; +} + +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_read(ds, addr, regnum); +} + +static int +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_write(ds, addr, regnum, val); +} + +static void mv88e6063_poll_link(struct dsa_switch *ds) +{ + int i; + + for (i = 0; i < DSA_MAX_PORTS; i++) { + struct net_device *dev; + int uninitialized_var(port_status); + int link; + int speed; + int duplex; + int fc; + + dev = ds->ports[i]; + if (dev == NULL) + continue; + + link = 0; + if (dev->flags & IFF_UP) { + port_status = reg_read(ds, REG_PORT(i), 0x00); + if (port_status < 0) + continue; + + link = !!(port_status & 0x1000); + } + + if (!link) { + if (netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + continue; + } + + speed = (port_status & 0x0100) ? 100 : 10; + duplex = (port_status & 0x0200) ? 1 : 0; + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; + + if (!netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " + "flow control %sabled\n", dev->name, + speed, duplex ? "full" : "half", + fc ? "en" : "dis"); + netif_carrier_on(dev); + } + } +} + +static struct dsa_switch_driver mv88e6063_switch_driver = { + .tag_protocol = htons(ETH_P_TRAILER), + .probe = mv88e6063_probe, + .setup = mv88e6063_setup, + .set_addr = mv88e6063_set_addr, + .phy_read = mv88e6063_phy_read, + .phy_write = mv88e6063_phy_write, + .poll_link = mv88e6063_poll_link, +}; + +static int __init mv88e6063_init(void) +{ + register_switch_driver(&mv88e6063_switch_driver); + return 0; +} +module_init(mv88e6063_init); + +static void __exit mv88e6063_cleanup(void) +{ + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); diff --git a/target/linux/ar71xx/generic/config-default b/target/linux/ar71xx/generic/config-default new file mode 100644 index 000000000..45169689e --- /dev/null +++ b/target/linux/ar71xx/generic/config-default @@ -0,0 +1 @@ +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd" diff --git a/target/linux/ar71xx/generic/profiles/00-default.mk b/target/linux/ar71xx/generic/profiles/00-default.mk new file mode 100644 index 000000000..36c4aa61b --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/00-default.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:= \ + kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/ar71xx/generic/profiles/01-minimal.mk b/target/linux/ar71xx/generic/profiles/01-minimal.mk new file mode 100644 index 000000000..dfaa3b0b3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Minimal + NAME:=Minimal Profile (no drivers) + PACKAGES:=-kmod-ath9k -wpad-mini +endef + +define Profile/Minimal/Description + Minimal package set compatible with most boards. +endef +$(eval $(call Profile,Minimal)) diff --git a/target/linux/ar71xx/generic/profiles/02-ath5k.mk b/target/linux/ar71xx/generic/profiles/02-ath5k.mk new file mode 100644 index 000000000..78203497f --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/02-ath5k.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ath5k + NAME:=Atheros 802.11abg WiFi (ath5k) + PACKAGES:=kmod-ath5k -kmod-ath9k +endef + +define Profile/ath5k/Description + Package set compatible with hardware using Atheros 802.11abg cards. +endef +$(eval $(call Profile,ath5k)) diff --git a/target/linux/ar71xx/generic/profiles/alfa.mk b/target/linux/ar71xx/generic/profiles/alfa.mk new file mode 100644 index 000000000..06baf240c --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/alfa.mk @@ -0,0 +1,42 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ALFAAP96 + NAME:=ALFA Network AP96 board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-rtc-pcf2123 +endef + +define Profile/ALFAAP96/Description + Package set optimized for the ALFA Network AP96 board. +endef + +$(eval $(call Profile,ALFAAP96)) + + +define Profile/HORNETUB + NAME:=ALFA Network Hornet-UB board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/HORNETUB/Description + Package set optimized for the ALFA Network Hornet-UB board. +endef + +$(eval $(call Profile,HORNETUB)) + + +define Profile/ALFANX + NAME:=ALFA Network N2/N5 board + PACKAGES:= +endef + +define Profile/ALFANX/Description + Package set optimized for the ALFA Network N2/N5 boards. +endef + +$(eval $(call Profile,ALFANX)) + diff --git a/target/linux/ar71xx/generic/profiles/allnet.mk b/target/linux/ar71xx/generic/profiles/allnet.mk new file mode 100644 index 000000000..07ca96444 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/allnet.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 20012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ALL0305 + NAME:=Allnet ALL0305 + PACKAGES:=fconfig kmod-ath5k -kmod-ath9k +endef + +define Profile/ALL0305/Description + Package set optimized for the Allnet ALL0305. +endef + +$(eval $(call Profile,ALL0305)) + +define Profile/ALL0258N + NAME:=Allnet ALL0258N + PACKAGES:=uboot-envtools rssileds +endef + +define Profile/ALL0258N/Description + Package set optimized for the Allnet ALL0258N. +endef + +$(eval $(call Profile,ALL0258N)) + +define Profile/ALL0315N + NAME:=Allnet ALL0315N + PACKAGES:=uboot-envtools rssileds +endef + +define Profile/ALL0315N/Description + Package set optimized for the Allnet ALL0315N. +endef + +$(eval $(call Profile,ALL0315N)) diff --git a/target/linux/ar71xx/generic/profiles/atheros.mk b/target/linux/ar71xx/generic/profiles/atheros.mk new file mode 100644 index 000000000..8e79f4cd5 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/atheros.mk @@ -0,0 +1,129 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AP113 + NAME:=Atheros AP113 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP113/description + Package set optimized for the Atheros AP113 reference board. +endef + +$(eval $(call Profile,AP113)) + +define Profile/AP121 + NAME:=Atheros AP121 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP121/Description + Package set optimized for the Atheros AP121 reference board. +endef + +$(eval $(call Profile,AP121)) + +define Profile/AP121MINI + NAME:=Atheros AP121-MINI reference board + PACKAGES:= +endef + +define Profile/AP121MINI/Description + Package set optimized for the Atheros AP121-MINI reference board. +endef + +$(eval $(call Profile,AP121MINI)) + +define Profile/AP136 + NAME:=Atheros AP136 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP136/Description + Package set optimized for the Atheros AP136 reference board. +endef + +$(eval $(call Profile,AP136)) + +define Profile/AP81 + NAME:=Atheros AP81 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP81/Description + Package set optimized for the Atheros AP81 reference board. +endef + +$(eval $(call Profile,AP81)) + +define Profile/AP83 + NAME:=Atheros AP83 reference board + PACKAGES:=kmod-usb-core kmod-usb2 \ + vsc7385-ucode-ap83 vsc7395-ucode-ap83 +endef + +define Profile/AP83/Description + Package set optimized for the Atheros AP83 reference board. +endef + +$(eval $(call Profile,AP83)) + +define Profile/AP96 + NAME:=Atheros AP96 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP96/Description + Package set optimized for the Atheros AP96 reference board. +endef + +$(eval $(call Profile,AP96)) + +define Profile/DB120 + NAME:=Atheros DB120 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/DB120/Description + Package set optimized for the Atheros DB120 reference board. +endef + +$(eval $(call Profile,DB120)) + +define Profile/PB42 + NAME:=Atheros PB42 reference board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/PB42/Description + Package set optimized for the Atheros PB42 reference board. +endef + +$(eval $(call Profile,PB42)) + +define Profile/PB44 + NAME:=Atheros PB44 reference board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 \ + vsc7385-ucode-pb44 vsc7395-ucode-pb44 +endef + +define Profile/PB44/Description + Package set optimized for the Atheros PB44 reference board. +endef + +$(eval $(call Profile,PB44)) + +define Profile/PB92 + NAME:=Atheros PB92 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/PB92/Description + Package set optimized for the Atheros PB92 reference board. +endef + +$(eval $(call Profile,PB92)) diff --git a/target/linux/ar71xx/generic/profiles/atlantis.mk b/target/linux/ar71xx/generic/profiles/atlantis.mk new file mode 100644 index 000000000..073d8d1f8 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/atlantis.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/A02RBW300N + NAME:=Atlantis-Land A02-RB-W300N + PACKAGES:= +endef + +define Profile/A02RBW300N/Description + Package set optimized for the Atlantis-Land A02-RB-W300N. +endef + +$(eval $(call Profile,A02RBW300N)) diff --git a/target/linux/ar71xx/generic/profiles/buffalo.mk b/target/linux/ar71xx/generic/profiles/buffalo.mk new file mode 100644 index 000000000..887be2657 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/buffalo.mk @@ -0,0 +1,96 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WZRHPG300NH + NAME:=Buffalo WZR-HP-G300NH + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG300NH/Description + Package set optimized for the Buffalo WZR-HP-G300NH and WZR-HP-G301NH +endef + +$(eval $(call Profile,WZRHPG300NH)) + +define Profile/WZRHPG300NH2 + NAME:=Buffalo WZR-HP-G300NH2 + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG300NH/Description + Package set optimized for the Buffalo WZR-HP-G300NH2 +endef + +$(eval $(call Profile,WZRHPG300NH2)) + +define Profile/WZRHPAG300H + NAME:=Buffalo WZR-HP-AG300H + PACKAGES:=kmod-usb-ohci kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPAG300H/Description + Package set optimized for the Buffalo WZR-HP-AG300H +endef + +$(eval $(call Profile,WZRHPAG300H)) + +define Profile/WZRHPG450H + NAME:=Buffalo WZR-HP-G450H + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG450H/Description + Package set optimized for the Buffalo WZR-HP-G450H +endef + +$(eval $(call Profile,WZRHPG450H)) + +define Profile/WHRG301N + NAME:=Buffalo WHR-G301N + PACKAGES:= +endef + +define Profile/WHRG301N/Description + Package set optimized for the Buffalo WHR-G301N. +endef + +$(eval $(call Profile,WHRG301N)) + + +define Profile/WHRHPG300N + NAME:=Buffalo WHR-HP-G300N + PACKAGES:= +endef + +define Profile/WHRHPG300N/Description + Package set optimized for the Buffalo WHR-HP-G300N +endef + +$(eval $(call Profile,WHRHPG300N)) + + +define Profile/WHRHPGN + NAME:=Buffalo WHR-HP-GN + PACKAGES:= +endef + +define Profile/WHRHPGN/Description + Package set optimized for the Buffalo WHR-HP-GN. +endef + +$(eval $(call Profile,WHRHPGN)) + +define Profile/WLAEAG300N + NAME:=Buffalo WLAE-AG300N + PACKAGES:=kmod-ledtrig-netdev +endef + +define Profile/WLAEAG300N/Description + Package set optimized for the Buffalo WLAE-AG300N +endef + +$(eval $(call Profile,WLAEAG300N)) diff --git a/target/linux/ar71xx/generic/profiles/compex.mk b/target/linux/ar71xx/generic/profiles/compex.mk new file mode 100644 index 000000000..349147381 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/compex.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WP543 + NAME:=Compex WP543/WPJ543 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/WP543/Description + Package set optimized for the Compex WP543/WPJ543 boards. +endef + +$(eval $(call Profile,WP543)) + +define Profile/WPE72 + NAME:=Compex WPE72/WPE72NX + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/WPE72/Description + Package set optimized for the Compex WPE72 boards including Compex WPE72NX Indoor Access Point. +endef + +$(eval $(call Profile,WPE72)) diff --git a/target/linux/ar71xx/generic/profiles/d-link.mk b/target/linux/ar71xx/generic/profiles/d-link.mk new file mode 100644 index 000000000..98fe00fc2 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/d-link.mk @@ -0,0 +1,63 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DIR600A1 + NAME:=D-Link DIR-600 rev. A1 + PACKAGES:= +endef + +define Profile/DIR600A1/Description + Package set optimized for the D-Link DIR-600 rev. A1. +endef + +$(eval $(call Profile,DIR600A1)) + +define Profile/DIR601A1 + NAME:=D-Link DIR-601 rev. A1 + PACKAGES:= +endef + +define Profile/DIR601A1/Description + Package set optimized for the D-Link DIR-601 rev. A1. +endef + +$(eval $(call Profile,DIR601A1)) + +define Profile/DIR615C1 + NAME:=D-Link DIR-615 rev. C1 + PACKAGES:= +endef + +define Profile/DIR615C1/Description + Package set optimized for the D-Link DIR-615 rev. C1. +endef + +$(eval $(call Profile,DIR615C1)) + + +define Profile/DIR615E4 + NAME:=D-Link DIR-615 rev. E4 + PACKAGES:= +endef + +define Profile/DIR615E4/Description + Package set optimized for the D-Link DIR-615 rev. E4. +endef + +$(eval $(call Profile,DIR615E4)) + + +define Profile/DIR825B1 + NAME:=D-Link DIR-825 rev. B1 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR825B1/Description + Package set optimized for the D-Link DIR-825 rev. B1. +endef + +$(eval $(call Profile,DIR825B1)) diff --git a/target/linux/ar71xx/generic/profiles/ew.mk b/target/linux/ar71xx/generic/profiles/ew.mk new file mode 100644 index 000000000..b4e15e322 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/ew.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EWDORIN + NAME:=Embedded Wireless Dorin Platform + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev kmod-usb-storage \ + kmod-fs-vfat kmod-fs-msdos kmod-fs-ntfs kmod-fs-ext4 \ + kmod-nls-cp437 kmod-nls-cp850 kmod-nls-cp852 kmod-nls-iso8859-1 kmod-nls-utf8 +endef + +define Profile/EWDORIN/Description + Package set optimized for the Dorin Platform. +endef + +$(eval $(call Profile,EWDORIN)) + diff --git a/target/linux/ar71xx/generic/profiles/jjplus.mk b/target/linux/ar71xx/generic/profiles/jjplus.mk new file mode 100644 index 000000000..3f97dbf02 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/jjplus.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/JA76PF + NAME:=jjPlus JA76PF + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-hwmon-core kmod-i2c-core kmod-hwmon-lm75 +endef + +define Profile/JA76PF/Description + Package set optimized for the jjPlus JA76PF board. +endef + +$(eval $(call Profile,JA76PF)) + +define Profile/JA76PF2 + NAME:=jjPlus JA76PF2 + PACKAGES:= +endef + +define Profile/JA76PF2/Description + Package set optimized for the jjPlus JA76PF2 board. +endef + +$(eval $(call Profile,JA76PF2)) + +define Profile/JWAP003 + NAME:=jjPlus JWAP0003 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/JWAP003/Description + Package set optimized for the jjPlus JWAP003 board. +endef + +$(eval $(call Profile,JWAP003)) diff --git a/target/linux/ar71xx/generic/profiles/linksys.mk b/target/linux/ar71xx/generic/profiles/linksys.mk new file mode 100644 index 000000000..bedf3a3d4 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/linksys.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRT160NL + NAME:=Linksys WRT160NL + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/WRT160NL/Description + Package set optimized for the Linksys WRT160NL. +endef + +define Profile/WRT400N + NAME:=Linksys WRT400N + PACKAGES:= +endef + +define Profile/WRT400N/Description + Package set optimized for the Linksys WRT400N. +endef + +$(eval $(call Profile,WRT160NL)) +$(eval $(call Profile,WRT400N)) diff --git a/target/linux/ar71xx/generic/profiles/netgear.mk b/target/linux/ar71xx/generic/profiles/netgear.mk new file mode 100644 index 000000000..fe136234f --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/netgear.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WNDR3700 + NAME:=NETGEAR WNDR3700/WNDR3800/WNDRMAC + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev kmod-leds-wndr3700-usb +endef + +define Profile/WNDR3700/Description + Package set optimized for the NETGEAR WNDR3700/WNDR3800/WNDRMAC +endef + +$(eval $(call Profile,WNDR3700)) diff --git a/target/linux/ar71xx/generic/profiles/openmesh.mk b/target/linux/ar71xx/generic/profiles/openmesh.mk new file mode 100644 index 000000000..88e37ee56 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/openmesh.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OM2P + NAME:=OpenMesh OM2P/OM2P-LC + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/OM2P/Description + Package set optimized for the OpenMesh OM2P/OM2P-LC. +endef + +$(eval $(call Profile,OM2P)) + diff --git a/target/linux/ar71xx/generic/profiles/planex.mk b/target/linux/ar71xx/generic/profiles/planex.mk new file mode 100644 index 000000000..3d192ba74 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/planex.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MZKW04NU + NAME:=Planex MZK-W04NU + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/MZKW04NU/Description + Package set optimized for the Planex MZK-W04NU. +endef + +$(eval $(call Profile,MZKW04NU)) + +define Profile/MZKW300NH + NAME:=Planex MZK-W300NH + PACKAGES:= +endef + +define Profile/MZKW300NH/Description + Package set optimized for the Planex MZK-W300NH. +endef + +$(eval $(call Profile,MZKW300NH)) diff --git a/target/linux/ar71xx/generic/profiles/redwave.mk b/target/linux/ar71xx/generic/profiles/redwave.mk new file mode 100644 index 000000000..069dd8f7b --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/redwave.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RW2458N + NAME:=Redwave RW2458N + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-ath9k wpad-mini +endef + +define Profile/RW2458N/Description + Package set optimized for the Redwave RW2458N board. +endef + +$(eval $(call Profile,RW2458N)) diff --git a/target/linux/ar71xx/generic/profiles/tp-link.mk b/target/linux/ar71xx/generic/profiles/tp-link.mk new file mode 100644 index 000000000..056a91703 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/tp-link.mk @@ -0,0 +1,204 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/TLMR11U + NAME:=TP-LINK TL-MR11U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR11U/Description + Package set optimized for the TP-LINK TL-MR11U. +endef +$(eval $(call Profile,TLMR11U)) + + +define Profile/TLMR3020 + NAME:=TP-LINK TL-MR3020 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3020/Description + Package set optimized for the TP-LINK TL-MR3020. +endef +$(eval $(call Profile,TLMR3020)) + + +define Profile/TLMR3040 + NAME:=TP-LINK TL-MR3040 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3040/Description + Package set optimized for the TP-LINK TL-MR3040. +endef +$(eval $(call Profile,TLMR3040)) + + +define Profile/TLMR3220 + NAME:=TP-LINK TL-MR3220 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3220/Description + Package set optimized for the TP-LINK TL-MR3220. +endef +$(eval $(call Profile,TLMR3220)) + + +define Profile/TLMR3420 + NAME:=TP-LINK TL-MR3420 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3420/Description + Package set optimized for the TP-LINK TL-MR3420. +endef +$(eval $(call Profile,TLMR3420)) + + +define Profile/TLWR703 + NAME:=TP-LINK TL-WR703N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR703/Description + Package set optimized for the TP-LINK TL-WR703N. +endef +$(eval $(call Profile,TLWR703)) + + +define Profile/TLWA701 + NAME:=TP-LINK TL-WA701N/ND + PACKAGES:= +endef + +define Profile/TLWA701/Description + Package set optimized for the TP-LINK TL-WA701N/ND. +endef +$(eval $(call Profile,TLWA701)) + + +define Profile/TLWA901 + NAME:=TP-LINK TL-WA901N/ND + PACKAGES:= +endef + +define Profile/TLWA901/Description + Package set optimized for the TP-LINK TL-WA901N/ND. +endef +$(eval $(call Profile,TLWA901)) + + +define Profile/TLWDR4300 + NAME:=TP-LINK TL-WDR3600/4300/4310 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR4300/Description + Package set optimized for the TP-LINK TL-WDR3600/4300/4310. +endef +$(eval $(call Profile,TLWDR4300)) + + +define Profile/TLWR740 + NAME:=TP-LINK TL-WR740N/ND + PACKAGES:= +endef + +define Profile/TLWR740/Description + Package set optimized for the TP-LINK TL-WR740N/ND. +endef +$(eval $(call Profile,TLWR740)) + + +define Profile/TLWR741 + NAME:=TP-LINK TL-WR741N/ND + PACKAGES:= +endef + +define Profile/TLWR741/Description + Package set optimized for the TP-LINK TL-WR741N/ND. +endef +$(eval $(call Profile,TLWR741)) + + +define Profile/TLWR743 + NAME:=TP-LINK TL-WR743N/ND + PACKAGES:= +endef + +define Profile/TLWR743/Description + Package set optimized for the TP-LINK TL-WR743N/ND. +endef +$(eval $(call Profile,TLWR743)) + + +define Profile/TLWR841 + NAME:=TP-LINK TL-WR841N/ND + PACKAGES:= +endef + +define Profile/TLWR841/Description + Package set optimized for the TP-LINK TL-WR841N/ND. +endef +$(eval $(call Profile,TLWR841)) + + +define Profile/TLWR842 + NAME:=TP-LINK TL-WR842N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR842/Description + Package set optimized for the TP-LINK TL-WR842N/ND. +endef +$(eval $(call Profile,TLWR842)) + + +define Profile/TLWR941 + NAME:=TP-LINK TL-WR941N/ND + PACKAGES:= +endef + +define Profile/TLWR941/Description + Package set optimized for the TP-LINK TL-WR941N/ND. +endef +$(eval $(call Profile,TLWR941)) + + +define Profile/TLWR1041 + NAME:=TP-LINK TL-WR1041N + PACKAGES:= +endef + +define Profile/TLWR1041/Description + Package set optimized for the TP-LINK TL-WR1041N/ND. +endef +$(eval $(call Profile,TLWR1041)) + + +define Profile/TLWR1043 + NAME:=TP-LINK TL-WR1043N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR1043/Description + Package set optimized for the TP-LINK TL-WR1043N/ND. +endef +$(eval $(call Profile,TLWR1043)) + + +define Profile/TLWR2543 + NAME:=TP-LINK TL-WR2543N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR2543/Description + Package set optimized for the TP-LINK TL-WR2543N/ND. +endef +$(eval $(call Profile,TLWR2543)) diff --git a/target/linux/ar71xx/generic/profiles/trendnet.mk b/target/linux/ar71xx/generic/profiles/trendnet.mk new file mode 100644 index 000000000..c6fe9cf79 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/trendnet.mk @@ -0,0 +1,51 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/TEW632BRP + NAME:=TRENDNet TEW-632BRP + PACKAGES:= +endef + +define Profile/TEW632BRP/Description + Package set optimized for the TRENDNet TEW-632BRP. +endef + +$(eval $(call Profile,TEW632BRP)) + +define Profile/TEW652BRP + NAME:=TRENDNet TEW-652BRP + PACKAGES:= +endef + +define Profile/TEW652BRP/Description + Package set optimized for the TRENDNet TEW-652BRP. +endef + +$(eval $(call Profile,TEW652BRP)) + +define Profile/TEW673GRU + NAME:=TRENDNet TEW-673GRU + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/TEW673GRU/Description + Package set optimized for the TRENDNet TEW-673GRU. +endef + +$(eval $(call Profile,TEW673GRU)) + +define Profile/TEW712BR + NAME:=TRENDNet TEW-712BR + PACKAGES:= +endef + +define Profile/TEW712BR/Description + Package set optimized for the TRENDNet TEW-712BR. +endef + +$(eval $(call Profile,TEW712BR)) + diff --git a/target/linux/ar71xx/generic/profiles/ubnt.mk b/target/linux/ar71xx/generic/profiles/ubnt.mk new file mode 100644 index 000000000..668171b8e --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/ubnt.mk @@ -0,0 +1,50 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/UBNTRS + NAME:=Ubiquiti RouterStation + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNTRS/Description + Package set optimized for the Ubiquiti RouterStation. +endef + +$(eval $(call Profile,UBNTRS)) + +define Profile/UBNTRSPRO + NAME:=Ubiquiti RouterStation Pro + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNTRSPRO/Description + Package set optimized for the Ubiquiti RouterStation Pro. +endef + +$(eval $(call Profile,UBNTRSPRO)) + +define Profile/UBNTUNIFI + NAME:=Ubiquiti UniFi AP + PACKAGES:= +endef + +define Profile/UBNTUNIFI/Description + Package set optimized for the Ubiquiti UniFi AP. +endef + +$(eval $(call Profile,UBNTUNIFI)) + +define Profile/UBNT + NAME:=Ubiquiti Products + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNT/Description + Build images for all Ubiquiti products (including LS-SR71, RouterStation and RouterStation Pro) +endef + +$(eval $(call Profile,UBNT)) diff --git a/target/linux/ar71xx/generic/profiles/zcomax.mk b/target/linux/ar71xx/generic/profiles/zcomax.mk new file mode 100644 index 000000000..b9ab77e80 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/zcomax.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ZCN1523H28 + NAME:=Zcomax ZCN-1523H-2-8 + PACKAGES:= +endef + +define Profile/ZCN1523H28/Description + Package set optimized for the Zcomax ZCN-1523H-2-8 board. +endef + +$(eval $(call Profile,ZCN1523H28)) + +define Profile/ZCN1523H516 + NAME:=Zcomax ZCN-1523H-5-16 + PACKAGES:= +endef + +define Profile/ZCN1523H516/Description + Package set optimized for the Zcomax ZCN-1523H-5-16 board. +endef + +$(eval $(call Profile,ZCN1523H516)) diff --git a/target/linux/ar71xx/generic/profiles/zyxel.mk b/target/linux/ar71xx/generic/profiles/zyxel.mk new file mode 100644 index 000000000..66258bdb8 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/zyxel.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NBG_460N_550N_550NH + NAME:=Zyxel NBG 460N/550N/550NH + PACKAGES:=kmod-rtc-pcf8563 +endef + +define Profile/NBG_460N_550N_550NH/Description + Package set optimized for the Zyxel NBG 460N/550N/550NH Routers. +endef + +$(eval $(call Profile,NBG_460N_550N_550NH)) diff --git a/target/linux/ar71xx/generic/target.mk b/target/linux/ar71xx/generic/target.mk new file mode 100644 index 000000000..c08f92962 --- /dev/null +++ b/target/linux/ar71xx/generic/target.mk @@ -0,0 +1,7 @@ +BOARDNAME:=Generic + +define Target/Description + Build firmware images for generic Atheros AR71xx/AR913x/AR934x based boards. +endef + + diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile new file mode 100644 index 000000000..569bdc9ef --- /dev/null +++ b/target/linux/ar71xx/image/Makefile @@ -0,0 +1,901 @@ +# +# Copyright (C) 2008-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +JFFS2_BLOCKSIZE = 64k 128k 256k + +define imgname +$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(patsubst jffs2-%,jffs2,$(patsubst squashfs-%,squashfs,$(1))) +endef + +define rootfs_align +$(patsubst %-256k,0x40000,$(patsubst %-128k,0x20000,$(patsubst %-64k,0x10000,$(patsubst squashfs-%,0x4,$(1))))) +endef + +define sysupname +$(call imgname,$(1),$(2))-sysupgrade.bin +endef + +define factoryname +$(call imgname,$(1),$(2))-factory.bin +endef + +COMMA:=, + +define mkcmdline +$(if $(1),board=$(1) )$(if $(2),console=$(2)$(COMMA)$(3)) +endef + +SINGLE_PROFILES:= + +define SingleProfile + define Image/Build/Profile/$(3) + $$(call Image/Build/Template/$(2)/$$(1),$(1),$(4),$$(call mkcmdline,$(5),$(6),$(7)),$(8),$(9),$(10),$(11),$(12)) + endef + SINGLE_PROFILES += $(3) +endef + +define MultiProfile + define Image/Build/Profile/$(1) + $(foreach p,$(2), + $$(call Image/Build/Profile/$p,$$(1)) + ) + endef +endef + +LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR) + +KDIR_TMP:=$(KDIR)/tmp +VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux +UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage +fs_squash:=squashfs-only +fs_64k:=64k +fs_64kraw:=64kraw +fs_128k:=128k +fs_256k:=256k +ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y) + fs_squash:=initramfs + fs_64k:=initramfs + fs_64kraw:=initramfs + fs_128k:=initramfs + fs_256k:=initramfs + VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs + UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs +endif + +define CompressLzma + $(STAGING_DIR_HOST)/bin/lzma e $(1) -lc1 -lp2 -pb2 $(2) +endef + +define PatchKernelLzma + cp $(KDIR)/vmlinux $(KDIR_TMP)/vmlinux-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux-$(1) "$(strip $(2))" + $(call CompressLzma,$(KDIR_TMP)/vmlinux-$(1),$(KDIR_TMP)/vmlinux-$(1).bin.lzma) +endef + +define PatchKernelGzip + cp $(KDIR)/vmlinux $(KDIR_TMP)/vmlinux-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux-$(1) "$(strip $(2))" + gzip -9 -c $(KDIR_TMP)/vmlinux-$(1) > $(KDIR_TMP)/vmlinux-$(1).bin.gz +endef + +define MkuImage + mkimage -A mips -O linux -T kernel -a 0x80060000 -C $(1) $(2) \ + -e 0x80060000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(3) $(4) +endef + +define MkuImageLzma + $(call PatchKernelLzma,$(1),$(2)) + $(call MkuImage,lzma,,$(KDIR_TMP)/vmlinux-$(1).bin.lzma,$(KDIR_TMP)/vmlinux-$(1).uImage) +endef + +define MkuImageLzma/initramfs + $(call PatchKernelLzma,$(1),$(2)) + $(call MkuImage,lzma,,$(KDIR_TMP)/vmlinux-$(1).bin.lzma,$(call imgname,initramfs,$(1))-uImage.bin) +endef + +define MkuImageGzip + $(call PatchKernelGzip,$(1),$(2)) + $(call MkuImage,gzip,,$(KDIR_TMP)/vmlinux-$(1).bin.gz,$(KDIR_TMP)/vmlinux-$(1).uImage) +endef + +define MkuImageGzip/initramfs + $(call PatchKernelGzip,$(1),$(2)) + $(call MkuImage,gzip,,$(KDIR_TMP)/vmlinux-$(1).bin.gz,$(call imgname,initramfs,$(1))-uImage.bin) +endef + +define MkuImageOKLI + $(call MkuImage,lzma,-M 0x4f4b4c49,$(KDIR)/vmlinux.bin.lzma,$(KDIR_TMP)/vmlinux-$(1).okli) +endef + +define CatFiles + if [ `stat -c%s "$(1)"` -gt $(2) ]; then \ + echo "Warning: $(1) is too big"; \ + else if [ `stat -c%s $(3)` -gt $(4) ]; then \ + echo "Warning: $(3) is too big"; \ + else \ + ( dd if=$(1) bs=$(2) conv=sync; dd if=$(3) ) > $(5); \ + fi; fi +endef + +define Sysupgrade/KR + $(call CatFiles,$(2),$(3),$(KDIR)/root.$(1),$(4),$(call sysupname,$(1),$(5))) +endef + +define Sysupgrade/KRuImage + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage,$(3),$(KDIR)/root.$(1),$(4),$(call sysupname,$(1),$(2))) +endef + +define Sysupgrade/RKuImage + $(call CatFiles,$(KDIR)/root.$(1),$(4),$(KDIR_TMP)/vmlinux-$(2).uImage,$(3),$(call sysupname,$(1),$(2))) +endef + +define Image/BuildLoader + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) KERNEL_CMDLINE="$(3)"\ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + LOADER_DATA="$(KDIR)/vmlinux.bin.lzma" BOARD="$(1)" \ + compile loader.$(2) +endef + +define Image/BuildLoaderAlone + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) KERNEL_CMDLINE="$(3)" \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + BOARD="$(1)" FLASH_OFFS=$(4) FLASH_MAX=$(5) \ + compile loader.$(2) +endef + +define Build/Clean + $(LOADER_MAKE) clean +endef + + +alfa_ap96_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13312k(rootfs),2048k(kernel),512k(caldata)ro,15360k@0x80000(firmware) +alfa_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1600k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +all0258n_mtdlayout=mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),1024k(kernel),5248k(rootfs),1536k(failsafe),64k(art),6272k@0x50000(firmware) +all0315n_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env),1024k(kernel),12544k(rootfs),2048k(failsafe),256k(art)ro,13568k@0x80000(firmware) +ap96_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1728k(kernel),64k(art)ro,7872k@0x40000(firmware) +ap113_mtd_layout=mtdparts=spi0.0:64k(u-boot),3008k(rootfs),896k(uImage),64k(NVRAM),64k(ART),3904k@0x10000(firmware) +ap121_mtdlayout_2M=mtdparts=spi0.0:64k(u-boot)ro,1216k(rootfs),704k(kernel),64k(art)ro,1920k@0x10000(firmware) +ap121_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2752k(rootfs),896k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware) +ap136_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(mib0),64k(art)ro,7744k@0x50000(firmware) +cameo7240_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,960k(kernel),2752k(rootfs),64k(mac)ro,64k(art)ro,3712k@0x40000(firmware) +cameo913x_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(config)ro,960k(kernel),2880k(rootfs),64k(art)ro,3840k@0x30000(firmware) +cameo933x_mtdlayout=mtdparts=spi0.0:64k(u-boot)ro,64k(art)ro,64k(mac)ro,64k(nvram)ro,192k(language)ro,896k(kernel),2752k(rootfs),3648k@0x70000(firmware) +db120_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +dir825b1_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,1024k(kernel),5184k(rootfs),64k(caldata)ro,1600k(unknown)ro,6208k@0x50000(firmware),64k@0x7f0000(caldata_copy) +dir825b1_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,1024k(kernel),6784k(rootfs),64k(caldata)ro,7808k@0x50000(firmware),64k@0x660000(caldata_orig),6208k@0x50000(firmware_orig) +ew-dorin_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),1024k(kernel),2688k(rootfs),64k(art),3712k@0x50000(firmware) +pb92_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2752k(rootfs),896k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware) +planex_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,960k(kernel),6784k(rootfs),128k(art)ro,7744k@0x50000(firmware) +ubntxm_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1024k(kernel),6528k(rootfs),256k(cfg)ro,64k(EEPROM)ro,7552k@0x50000(firmware) +whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,960k(kernel),2816k(rootfs),64k(art)ro,3712k@0x40000(firmware) +wndr3700_mtdlayout=mtdparts=spi0.0:320k(u-boot)ro,128k(u-boot-env)ro,1024k(kernel),6656k(rootfs),64k(art)ro,7680k@0x70000(firmware) +wndr3700v2_mtdlayout=mtdparts=spi0.0:320k(u-boot)ro,128k(u-boot-env)ro,1024k(kernel),14848k(rootfs),64k(art)ro,15872k@0x70000(firmware) +zcn1523h_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6208k(rootfs),1472k(kernel),64k(configure)ro,64k(mfg)ro,64k(art)ro,7680k@0x50000(firmware) + +define Image/BuildKernel + cp $(KDIR)/vmlinux.elf $(VMLINUX).elf + cp $(KDIR)/vmlinux $(VMLINUX).bin + dd if=$(KDIR)/vmlinux.bin.lzma of=$(VMLINUX).lzma bs=65536 conv=sync + dd if=$(KDIR)/vmlinux.bin.gz of=$(VMLINUX).gz bs=65536 conv=sync + $(call MkuImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(UIMAGE)-gzip.bin) + $(call MkuImage,lzma,,$(KDIR)/vmlinux.bin.lzma,$(UIMAGE)-lzma.bin) + -mkdir -p $(KDIR_TMP) + $(call Image/Build/Initramfs) +endef + +define Image/Build/WRT400N + $(call MkuImageLzma,$(2),$(3)) + $(call Sysupgrade/KRuImage,$(1),$(2),1310720,6488064) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + wrt400n $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR)/root.$(1) $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/DIR825B1 + $(call MkuImageLzma,$(2),$(3) $(dir825b1_mtdlayout)) + $(call Sysupgrade/KRuImage,$(1),$(2),1048576,5308416) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + dd if=$(call sysupname,$(1),$(2)); \ + echo -n "$(4)"; \ + ) > $(call imgname,$(1),$(2))-backup-loader.bin; \ + if [ `stat -c%s $(call sysupname,$(1),$(2))` -gt 4194304 ]; then \ + echo "Warning: $(call sysupname,$(1),$(2)) is too big"; \ + else \ + ( \ + dd if=$(call sysupname,$(1),$(2)) bs=4096k conv=sync; \ + echo -n "$(5)"; \ + ) > $(call factoryname,$(1),$(2)); \ + fi; \ + fi + $(call MkuImageLzma,$(2)-fat,$(3) $(dir825b1_mtdlayout_fat)) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2)-fat.uImage,1048576,$(KDIR)/root.$(1),6946816,$(KDIR_TMP)/$(2)-fat.bin) + if [ -e "$(KDIR_TMP)/$(2)-fat.bin" ]; then \ + echo -n "" > $(KDIR_TMP)/$(2)-fat.dummy; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + "$(KDIR_TMP)/$(2)-fat.bin" \ + "$(KDIR_TMP)/$(2)-fat.dummy" \ + $(call sysupname,$(1),$(2)-fat); \ + fi +endef + +define Image/Build/WZRHPG30XNH + $(call MkuImageLzma,$(2),$(3)) + $(call Sysupgrade/KRuImage,$(1),$(2),1048576,31850496) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + echo -n -e "# Airstation Public Fmt1\x00\x00\x00\x00\x00\x00\x00\x00"; \ + dd if=$(call sysupname,$(1),$(2)); \ + ) > $(call imgname,$(1),$(2))-tftp.bin; \ + buffalo-enc -p $(4) -v 1.99 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(KDIR_TMP)/$(2).enc; \ + buffalo-tag -b $(4) -p $(4) -a ath -v 1.99 -m 1.01 -l mlang8 \ + -w 3 -c 0x80041000 -d 0x801e8000 -f 1 -r M_ \ + -i $(KDIR_TMP)/$(2).enc \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/WHRHPG300N + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call Sysupgrade/KRuImage,$(1),$(2),983040,2883584) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + echo -n -e "# Airstation Public Fmt1\x00\x00\x00\x00\x00\x00\x00\x00"; \ + dd if=$(call sysupname,$(1),$(2)); \ + ) > $(call imgname,$(1),$(2))-tftp.bin; \ + buffalo-enc -p $(5) -v 1.99 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(KDIR_TMP)/$(2).enc; \ + buffalo-tag -b $(5) -p $(5) -a ath -v 1.99 -m 1.01 -l mlang8 \ + -w 3 -c 0x80041000 -d 0x801e8000 -f 1 -r M_ \ + -i $(KDIR_TMP)/$(2).enc \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/WHRHPG300N/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +endef + +define Image/Build/Cameo + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call Sysupgrade/KRuImage,$(1),$(2),$(5),$(6)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage bs=$(5) conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=$(6) conv=sync; \ + echo -n $(7); \ + ) > $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/CameoHornet + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call Sysupgrade/KRuImage,$(1),$(2),$(5),$(6)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + mkcameofw -M HORNET -R "DEF" -S $(7) -V "1.99" \ + -K $(5) -I $$$$(($(5)+$(6))) \ + -k $(KDIR_TMP)/vmlinux-$(2).uImage \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/Cameo913x + $(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo913x_mtdlayout),983040,2949120,$(4)) +endef + +define Image/Build/Cameo913x/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3) $(cameo913x_mtdlayout)) +endef + +define Image/Build/Cameo7240 + $(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo7240_mtdlayout),983040,2818048,$(4)) +endef + +define Image/Build/Cameo7240/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3) $(cameo7240_mtdlayout)) +endef + +define Image/Build/Cameo933x + $(call Image/Build/CameoHornet,$(1),$(2),$(3),$(cameo933x_mtdlayout),917504,2818048,$(4)) +endef + +define Image/Build/Cameo933x/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3) $(cameo933x_mtdlayout)) +endef + +define Image/Build/Ath + $(call Sysupgrade/$(7),$(1),$(2),$(5),$(6)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + fi +endef + +define Image/Build/AthGzip + $(call MkuImageGzip,$(2),$(3) $(4)) + $(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +endef + +define Image/Build/AthGzip/initramfs + $(call MkuImageGzip/initramfs,$(2),$(3) $(4)) +endef + +define Image/Build/AthLzma + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +endef + +define Image/Build/AthLzma/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +endef + +define Image/Build/PB4X + $(call PatchKernelLzma,$(2),$(3)) + dd if=$(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync + -sh $(TOPDIR)/scripts/combined-image.sh \ + "$(call imgname,kernel,$(2)).bin" \ + "$(call imgname,$(1),$(2)-rootfs).bin" \ + $(call sysupname,$(1),$(2)) +endef + + +define Image/Build/MyLoader + $(call PatchKernelLzma,$(2),$(3)) + -$(STAGING_DIR_HOST)/bin/mkmylofw -B $(2) -s $(4) \ + -p0x030000:0xe0000:al:0x80060000:kernel:$(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + -p0x110000:0:::rootfs:$(KDIR)/root.$(1) \ + $(call imgname,$(1),$(2))-$(5)-factory.img +endef + +define Image/Build/UBNTXM + $(call MkuImageLzma,$(2),$(3) $(ubntxm_mtdlayout)) + $(call Sysupgrade/KRuImage,$(1),$(2),1048576,6684672) + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage of=$(KDIR_TMP)/vmlinux-$(2).uImage.bin bs=1024k conv=sync + -$(STAGING_DIR_HOST)/bin/mkfwimage \ + -B $(4) -v $(5).$(6).v6.0.0-OpenWrt-$(REVISION) \ + -k $(KDIR_TMP)/vmlinux-$(2).uImage.bin \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(call factoryname,$(1),$(2)) +endef + +define Image/Build/UBNT + $(call PatchKernelLzma,$(2),$(3)) + dd if=$(KDIR_TMP)/vmlinux-$(2).bin.lzma of=$(KDIR_TMP)/vmlinux-$(2).lzma bs=64k conv=sync + -$(STAGING_DIR_HOST)/bin/mkfwimage \ + -B $(4) -v $(5).$(6).OpenWrt.$(REVISION) \ + -k $(KDIR_TMP)/vmlinux-$(2).lzma \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(call factoryname,$(1),$(2)) + -sh $(TOPDIR)/scripts/combined-image.sh \ + "$(KDIR_TMP)/vmlinux-$(2).lzma" \ + "$(BIN_DIR)/$(IMG_PREFIX)-root.$(1)" \ + $(call sysupname,$(1),$(2)) +endef + +define Image/Build/Planex/loader + $(call Image/BuildLoaderAlone,$(1),gz,$(2) $(planex_mtdlayout),0x52000,0) +endef + +define Image/Build/Planex + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImage,gzip,,$(KDIR)/loader-$(2).gz,$(KDIR_TMP)/vmlinux-$(2).uImage) + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage bs=8k count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + $(call Sysupgrade/KR,$(1),$(KDIR_TMP)/kernel-$(2).bin,983040,6815744,$(2)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + $(STAGING_DIR_HOST)/bin/mkplanexfw \ + -B $(2) \ + -v 2.00.00 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/ALFA + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call Sysupgrade/RKuImage,$(1),$(2),$(5),$(6)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + rm -rf $(KDIR)/$(1); \ + mkdir -p $(KDIR)/$(1); \ + cd $(KDIR)/$(1); \ + cp $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR)/$(1)/$(7); \ + cp $(KDIR)/root.$(1) $(KDIR)/$(1)/$(8); \ + $(TAR) zcf $(call factoryname,$(1),$(2)) -C $(KDIR)/$(1) $(7) $(8); \ + ( \ + echo WRM7222C | dd bs=32 count=1 conv=sync; \ + echo -ne '\xfe'; \ + ) >> $(call factoryname,$(1),$(2)); \ + fi +endef + +define Image/Build/ALFA/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +endef + +define Image/Build/TPLINKOLD/loader + $(call Image/BuildLoaderAlone,$(1),gz,$(2),0x22000,0) +endef + +define Image/Build/TPLINKOLD + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR)/loader-$(2).gz bs=7680 count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli conv=sync; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION)\ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINKOLD/initramfs + $(call Image/BuildLoader,$(2),gz,$(3),0x80060000) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -k $(KDIR)/loader-$(2).gz \ + -o $(call imgname,$(1),$(2))-uImage.bin +endef + +define Image/Build/TPLINK/loader + $(call Image/BuildLoaderAlone,$(1),gz,$(2),0x22000,0) +endef + +define Image/Build/TPLINK + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR)/loader-$(2).gz bs=7680 count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli conv=sync; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION)\ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINK/initramfs + $(call Image/BuildLoader,$(2),gz,$(3),0x80060000) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -k $(KDIR)/loader-$(2).gz \ + -o $(call imgname,$(1),$(2))-uImage.bin +endef + +define Image/Build/TPLINK-LZMA + $(call PatchKernelLzma,$(2),$(3)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) -s \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINK-LZMA/initramfs + $(call PatchKernelLzma,$(2),$(3)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) -s \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + -o $(call imgname,$(1),$(2))-uImage.bin +endef + +define Image/Build/CyberTAN + $(call MkuImageGzip,$(2),$(3)) + $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/image.tmp -f $(KDIR_TMP)/vmlinux-$(2).uImage \ + -x 32 -a 0x10000 -x -32 -f $(KDIR)/root.$(1) + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(4) \ + -i $(KDIR)/image.tmp \ + -o $(call sysupname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(4) -g \ + -i $(KDIR)/image.tmp \ + -o $(call factoryname,$(1),$(2)) + rm $(KDIR)/image.tmp +endef + +define Image/Build/Netgear/Build_uImage + $(call MkuImageLzma,$(1),$(2) $(3)) + -rm -rf $(KDIR)/$(1) + mkdir -p $(KDIR)/$(1)/image + $(STAGING_DIR_HOST)/bin/wndr3700 \ + $(KDIR_TMP)/vmlinux-$(1).uImage \ + $(KDIR)/$(1)/image/uImage \ + $(4) + $(STAGING_DIR_HOST)/bin/mksquashfs-lzma \ + $(KDIR)/$(1) $(KDIR_TMP)/vmlinux-$(1).uImage.squashfs.tmp \ + -nopad -noappend -root-owned -be + -rm -rf $(KDIR)/$(1) + mkimage -A mips -O linux -T filesystem -C none \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR_TMP)/vmlinux-$(1).uImage.squashfs.tmp \ + $(KDIR_TMP)/vmlinux-$(1).uImage.squashfs.tmp2 + $(STAGING_DIR_HOST)/bin/wndr3700 \ + $(KDIR_TMP)/vmlinux-$(1).uImage.squashfs.tmp2 \ + $(KDIR_TMP)/vmlinux-$(1).uImage.squashfs \ + $(4) + -rm -f $(KDIR_TMP)/vmlinux-$(1).uImage.squashfs.tmp* +endef + +define Image/Build/Netgear/Estimate_uImage + $(call Image/Build/Netgear/Build_uImage,$(1)_est,$(2),$(3),$(4)) + ( \ + set -e; \ + kk=`echo '$(3)' | sed -e 's/.*[:,]\([0-9]*\)k(kernel).*/\1/'`; \ + rk=`echo '$(3)' | sed -e 's/.*[:,]\([0-9]*\)k(rootfs).*/\1/'`; \ + let 'tk = kk + rk'; \ + s=`stat -c'%s' '$(KDIR_TMP)/vmlinux-$(1)_est.uImage.squashfs'`; \ + c=`echo '$(3)' | wc -c`; \ + let 'kk = (((s + c) / (64 * 1024) + 1) * 64)'; \ + let 'rk = tk - kk'; \ + echo '$(3)' | sed -e "s/[0-9]*k(kernel)/$$$${kk}k(kernel)/" \ + -e "s/[0-9]*k(rootfs)/$$$${rk}k(rootfs)/" > \ + '$(KDIR_TMP)/$(1)_mtdparts'; \ + let 'k = kk * 1024'; \ + echo "$$$${k}" > '$(KDIR_TMP)/$(1)_kernel_maxsize'; \ + let 'r = rk * 1024'; \ + echo "$$$${r}" > '$(KDIR_TMP)/$(1)_rootfs_maxsize'; \ + ) + -rm -f $(KDIR_TMP)/vmlinux-$(1)_est \ + $(KDIR_TMP)/vmlinux-$(1)_est.bin.lzma \ + $(KDIR_TMP)/vmlinux-$(1)_est.uImage \ + $(KDIR_TMP)/vmlinux-$(1)_est.uImage.squashfs +endef + +define Image/Build/Netgear + $(call Image/Build/Netgear/Estimate_uImage,$(2),$(3),$(4),$(5)) + $(call Image/Build/Netgear/Build_uImage,$(2),$(3),`cat $(KDIR_TMP)/$(2)_mtdparts`,$(5)) + if [ `stat -c%s '$(KDIR_TMP)/vmlinux-$(2).uImage.squashfs'` -gt \ + `cat '$(KDIR_TMP)/$(2)_kernel_maxsize'` ]; then \ + echo "$(KDIR_TMP)/vmlinux-$(2).uImage.squashfs is too big" >& 2; \ + else if [ `stat -c%s '$(KDIR)/root.$(1)'` -gt \ + `cat '$(KDIR_TMP)/$(2)_rootfs_maxsize'` ]; then \ + echo "$(KDIR)/root.$(1) is too big" >& 2; \ + else \ + ( \ + set -e; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage.squashfs \ + bs=`cat '$(KDIR_TMP)/$(2)_kernel_maxsize'` conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=64k; \ + ) > $(call sysupname,$(1),$(2)); \ + for r in $(7) ; do \ + [ -n "$$$$r" ] && dashr="-$$$$r" || dashr= ; \ + $(STAGING_DIR_HOST)/bin/mkdniimg \ + -B $(6) -v OpenWrt.$(REVISION) -r "$$$$r" $(8) \ + -i $(call sysupname,$(1),$(2)) \ + -o $(call imgname,$(1),$(2))-factory$$$$dashr.img; \ + done; \ + fi; fi +endef + +define Image/Build/Netgear/initramfs + $(call MkuImageLzma,$(2),$(3) $(4)) + $(STAGING_DIR_HOST)/bin/wndr3700 \ + $(KDIR_TMP)/vmlinux-$(2).uImage \ + $(call imgname,$(1),$(2))-uImage.bin \ + $(5) +endef + +ifdef CONFIG_PACKAGE_uboot-ar71xx-nbg460n_550n_550nh + define Image/Build/ZyXEL + $(call MkuImageLzma,$(2),$(3)) + $(call Sysupgrade/KRuImage,$(1),$(2),917504,2752512) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + if [ ! -f $(BIN_DIR)/$(IMG_PREFIX)-$(2)-u-boot.bin ]; then \ + echo "Warning: $(IMG_PREFIX)-$(2)-u-boot.bin not found"; \ + else \ + $(STAGING_DIR_HOST)/bin/mkzynfw \ + -B $(4) \ + -b $(BIN_DIR)/$(IMG_PREFIX)-$(2)-u-boot.bin \ + -r $(call sysupname,$(1),$(2)):0x10000 \ + -o $(call factoryname,$(1),$(2)); \ + fi; fi + endef +endif + +define Image/Build/OpenMesh + $(call MkuImageLzma,$(2)) + -sh $(TOPDIR)/scripts/om2p-fwupgradecfg-gen.sh \ + "$(BUILD_DIR)/om2p-fwupgrade.cfg" \ + "$(KDIR_TMP)/vmlinux-$(2).uImage" \ + "$(KDIR)/root.$(1)" + -sh $(TOPDIR)/scripts/combined-ext-image.sh \ + "$(3)" "$(call factoryname,$(1),$(2))" \ + "$(BUILD_DIR)/om2p-fwupgrade.cfg" "fwupgrade.cfg" \ + "$(KDIR_TMP)/vmlinux-$(2).uImage" "kernel" \ + "$(KDIR)/root.$(1)" "rootfs" +endef + +define Image/Build/Zcomax + $(call MkuImageLzma,$(2),$(3)) + $(call Sysupgrade/RKuImage,$(1),$(2),1507328,6356992) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + $(STAGING_DIR_HOST)/bin/mkzcfw \ + -B $(2) \ + -k $(KDIR_TMP)/vmlinux-$(2).uImage \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(call imgname,$(1),$(2))-factory.img; \ + fi +endef + +define Image/Build/Zcomax/initramfs + $(call MkuImageLzma/initramfs,$(2),$(3)) +endef + +define Image/Build/Template/initramfs/initramfs + $(call Image/Build/$(1)/initramfs,initramfs,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/all/squashfs + $(call Image/Build/$(1),squashfs,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/all/jffs2-64k + $(call Image/Build/$(1),jffs2-64k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/all/jffs2-128k + $(call Image/Build/$(1),jffs2-128k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/all/jffs2-256k + $(call Image/Build/$(1),jffs2-256k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/squashfs-only/loader + $(call Image/Build/$(1)/loader,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/squashfs-only/squashfs + $(call Image/Build/$(1),squashfs,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/64k/loader + $(call Image/Build/$(1)/loader,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/64k/squashfs + $(call Image/Build/$(1),squashfs-64k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/64k/jffs2-64k + $(call Image/Build/$(1),jffs2-64k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/64kraw/loader + $(call Image/Build/$(1)/loader,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/64kraw/squashfs + $(call Image/Build/$(1),squashfs-raw,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/64kraw/jffs2-64k + $(call Image/Build/$(1),jffs2-64k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/128k/squashfs + $(call Image/Build/$(1),squashfs,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/128k/jffs2-128k + $(call Image/Build/$(1),jffs2-128k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/256k/squashfs + $(call Image/Build/$(1),squashfs,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +define Image/Build/Template/256k/jffs2-256k + $(call Image/Build/$(1),jffs2-256k,$(2),$(3),$(4),$(5),$(6),$(7),$(8)) +endef + +$(eval $(call SingleProfile,ALFA,$(fs_64k),ALFANX,alfa-nx,ALFA-NX,ttyS0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,vmlinux.gz.uImage,pb9x-2.6.31-jffs2)) +$(eval $(call SingleProfile,ALFA,$(fs_64k),HORNETUB,hornet-ub,HORNET-UB,ttyATH0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,kernel_image,rootfs_image)) + +$(eval $(call SingleProfile,AthGzip,$(fs_64k),AP81,ap81,AP81,ttyS0,115200,,1310720,6619136,KRuImage)) +$(eval $(call SingleProfile,AthGzip,$(fs_64k),AP83,ap83,AP83,ttyS0,115200,,1310720,6619136,KRuImage)) +$(eval $(call SingleProfile,AthGzip,$(fs_64k),AP96,ap96,AP96,ttyS0,115200,$$(ap96_mtdlayout),1769472,6291456,RKuImage)) + +$(eval $(call SingleProfile,AthLzma,$(fs_64k),ALFAAP96,alfa-ap96,ALFA-AP96,ttyS0,115200,$$(alfa_ap96_mtdlayout),2097152,13631488,RKuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),ALL0258N,all0258n,ALL0258N,ttyS0,115200,$$(all0258n_mtdlayout),1048576,5373952,KRuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_256k),ALL0315N,all0315n,ALL0315N,ttyS0,115200,$$(all0315n_mtdlayout),1048576,12845056,KRuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),AP113,ap113,AP113,ttyS0,115200,$$(ap113_mtd_layout),917504,3080192,RK)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),AP121_2M,ap121-2M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_2M),720896,1245184,RKuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),AP121_4M,ap121-4M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_4M),917504,2818048,RKuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),AP121MINI,ap121-mini,AP121-MINI,ttyATH0,115200,$$(ap121_mtdlayout_4M),917504,2818048,RKuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),AP136,ap136,AP136,ttyS0,115200,$$(ap136_mtdlayout),1441792,6488064,RKuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),DB120,db120,DB120,ttyS0,115200,$$(db120_mtdlayout),1441792,6488064,RKuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),EWDORINAP,ew-dorin,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),1048576,2752512,KRuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),EWDORINRT,ew-dorin-router,EW-DORIN-ROUTER,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),1048576,2752512,KRuImage)) +$(eval $(call SingleProfile,AthLzma,$(fs_64k),PB92,pb92,PB92,ttyS0,115200,$$(pb92_mtdlayout),917504,2818048,KRuImage)) + +$(eval $(call SingleProfile,Cameo7240,$(fs_64k),DIR600A1,dir-600-a1,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-00")) +$(eval $(call SingleProfile,Cameo7240,$(fs_64k),DIR601A1,dir-601-a1,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-02")) +$(eval $(call SingleProfile,Cameo7240,$(fs_64k),DIR615E4,dir-615-e4,DIR-615-E4,ttyS0,115200,"AP99-AR7240-RT-091105-05")) +$(eval $(call SingleProfile,Cameo7240,$(fs_64k),FR54RTR,fr-54rtr,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-01")) + +$(eval $(call SingleProfile,Cameo913x,$(fs_squash),A02RBW300N,a02-rb-w300n,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-03")) +$(eval $(call SingleProfile,Cameo913x,$(fs_squash),DIR615C1,dir-615-c1,DIR-615-C1,ttyS0,115200,"AP81-AR9130-RT-070614-02")) +$(eval $(call SingleProfile,Cameo913x,$(fs_squash),TEW632BRP,tew-632brp,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-00")) +$(eval $(call SingleProfile,Cameo913x,$(fs_squash),TEW652BRP_FW,tew-652brp,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-080609-05")) +$(eval $(call SingleProfile,Cameo913x,$(fs_squash),TEW652BRP_RECOVERY,tew-652brp-recovery,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-02")) + +$(eval $(call SingleProfile,Cameo933x,$(fs_squash),TEW712BR,tew-712br,TEW-712BR,ttyATH0,115200,"HORNET-RT-TEW712BR-3")) + +$(eval $(call SingleProfile,CyberTAN,$(fs_64k),WRT160NL,wrt160nl,WRT160NL,ttyS0,115200,1.00.01)) + +$(eval $(call SingleProfile,DIR825B1,$(fs_64k),DIR825B1,dir-825-b1,DIR-825-B1,ttyS0,115200,01AP94-AR7161-RT-080619-00,00AP94-AR7161-RT-080619-00)) +$(eval $(call SingleProfile,DIR825B1,$(fs_64k),TEW673GRU,tew-673gru,TEW-673GRU,ttyS0,115200,01AP94-AR7161-RT-080619-01,00AP94-AR7161-RT-080619-01)) + +$(eval $(call SingleProfile,MyLoader,$(fs_64k),WP543_2M,wp543,,ttyS0,115200,0x200000,2M)) +$(eval $(call SingleProfile,MyLoader,$(fs_64k),WP543_4M,wp543,,ttyS0,115200,0x400000,4M)) +$(eval $(call SingleProfile,MyLoader,$(fs_64k),WP543_8M,wp543,,ttyS0,115200,0x800000,8M)) +$(eval $(call SingleProfile,MyLoader,$(fs_64k),WP543_16M,wp543,,ttyS0,115200,0x1000000,16M)) +$(eval $(call SingleProfile,MyLoader,$(fs_64k),WPE72,wpe72,,ttyS0,115200,0x800000,8M)) + +$(eval $(call SingleProfile,Netgear,$(fs_64k),WNDR3700V1,wndr3700,WNDR3700,ttyS0,115200,$$(wndr3700_mtdlayout),3700,WNDR3700,"" NA,)) +$(eval $(call SingleProfile,Netgear,$(fs_64k),WNDR3700V2,wndr3700v2,WNDR3700,ttyS0,115200,$$(wndr3700v2_mtdlayout),3701,WNDR3700v2,"",-H 29763654+16+64)) +$(eval $(call SingleProfile,Netgear,$(fs_64k),WNDR3800,wndr3800,WNDR3700,ttyS0,115200,$$(wndr3700v2_mtdlayout),3701,WNDR3800,"",-H 29763654+16+128)) +$(eval $(call SingleProfile,Netgear,$(fs_64k),WNDRMAC,wndrmac,WNDR3700,ttyS0,115200,$$(wndr3700v2_mtdlayout),3701,WNDRMAC,"",-H 29763654+16+64)) +$(eval $(call SingleProfile,Netgear,$(fs_64k),WNDRMACV2,wndrmacv2,WNDR3700,ttyS0,115200,$$(wndr3700v2_mtdlayout),3701,WNDRMACv2,"",-H 29763654+16+128)) + +$(eval $(call SingleProfile,OpenMesh,$(fs_squash),OM2P,om2p,OM2P)) + +$(eval $(call SingleProfile,PB4X,$(fs_128k),ALL0305,all0305,ALL0305,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,$(fs_128k),EAP7660D,eap7660d,EAP7660D,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,$(fs_64k),JA76PF,ja76pf,JA76PF,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,$(fs_64k),JA76PF2,ja76pf2,JA76PF2,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,$(fs_64k),JWAP003,jwap003,JWAP003,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,$(fs_64k),PB42,pb42,PB42,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,$(fs_64k),PB44,pb44,PB44,ttyS0,115200)) + +$(eval $(call SingleProfile,Planex,$(fs_64k),MZKW04NU,mzk-w04nu,MZK-W04NU,ttyS0,115200)) +$(eval $(call SingleProfile,Planex,$(fs_64k),MZKW300NH,mzk-w300nh,MZK-W300NH,ttyS0,115200)) + +$(eval $(call SingleProfile,TPLINKOLD,$(fs_squash),TLWR841NV15,tl-wr841nd-v1.5,TL-WR841N-v1.5,ttyS0,115200,0x08410002,2,4M)) + +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLMR3220,tl-mr3220-v1,TL-MR3220,ttyS0,115200,0x32200001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLMR3420,tl-mr3420-v1,TL-MR3420,ttyS0,115200,0x34200001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWA701,tl-wa701n-v1,TL-WA901ND,ttyS0,115200,0x07010001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWA901NV1,tl-wa901nd-v1,TL-WA901ND,ttyS0,115200,0x09010001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWA901NV2,tl-wa901nd-v2,TL-WA901ND-v2,ttyS0,115200,0x09010002,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR740NV1,tl-wr740n-v1,TL-WR741ND,ttyS0,115200,0x07400001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR740NV3,tl-wr740n-v3,TL-WR741ND,ttyS0,115200,0x07400003,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR741NV1,tl-wr741nd-v1,TL-WR741ND,ttyS0,115200,0x07410001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR741NV2,tl-wr741nd-v2,TL-WR741ND,ttyS0,115200,0x07410001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR743,tl-wr743nd-v1,TL-WR741ND,ttyS0,115200,0x07430001,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR841NV3,tl-wr841nd-v3,TL-WR941ND,ttyS0,115200,0x08410003,3,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR841NV5,tl-wr841nd-v5,TL-WR741ND,ttyS0,115200,0x08410005,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR841NV7,tl-wr841nd-v7,TL-WR841N-v7,ttyS0,115200,0x08410007,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR842,tl-wr842n-v1,TL-MR3420,ttyS0,115200,0x08420001,1,8M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR941NV2,tl-wr941nd-v2,TL-WR941ND,ttyS0,115200,0x09410002,2,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR941NV3,tl-wr941nd-v3,TL-WR941ND,ttyS0,115200,0x09410002,2,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR941NV4,tl-wr941nd-v4,TL-WR741ND,ttyS0,115200,0x09410004,1,4M)) +$(eval $(call SingleProfile,TPLINK,$(fs_64kraw),TLWR1043,tl-wr1043nd-v1,TL-WR1043ND,ttyS0,115200,0x10430001,1,8M)) + +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLMR11U,tl-mr11u-v1,TL-MR11U,ttyATH0,115200,0x00110101,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLMR3020,tl-mr3020-v1,TL-MR3020,ttyATH0,115200,0x30200001,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLMR3040,tl-mr3040-v1,TL-MR3040,ttyATH0,115200,0x30400001,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR703,tl-wr703n-v1,TL-WR703N,ttyATH0,115200,0x07030101,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR740NV4,tl-wr740n-v4,TL-WR741ND-v4,ttyATH0,115200,0x07400004,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR741NV4,tl-wr741nd-v4,TL-WR741ND-v4,ttyATH0,115200,0x07410004,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR841NV8,tl-wr841n-v8,TL-WR841N-v8,ttyS0,115200,0x08410008,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR1041,tl-wr1041n-v2,TL-WR1041N-v2,ttyS0,115200,0x10410002,1,4Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWR2543,tl-wr2543-v1,TL-WR2543N,ttyS0,115200,0x25430001,1,8Mlzma,-v 3.13.99)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWDR3600V1,tl-wdr3600-v1,TL-WDR4300,ttyS0,115200,0x36000001,1,8Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWDR4300V1,tl-wdr4300-v1,TL-WDR4300,ttyS0,115200,0x43000001,1,8Mlzma)) +$(eval $(call SingleProfile,TPLINK-LZMA,$(fs_64kraw),TLWDR4310V1,tl-wdr4310-v1,TL-WDR4300,ttyS0,115200,0x43100001,1,8Mlzma)) + +$(eval $(call SingleProfile,UBNT,$(fs_64k),UBNTRS,ubnt-rs,UBNT-RS,ttyS0,115200,RS,RSx,ar7100)) +$(eval $(call SingleProfile,UBNT,$(fs_64k),UBNTRSPRO,ubnt-rspro,UBNT-RSPRO,ttyS0,115200,RSPRO,RSPRO,ar7100pro)) +$(eval $(call SingleProfile,UBNT,$(fs_64k),UBNTLSSR71,ubnt-ls-sr71,UBNT-LS-SR71,ttyS0,115200,LS-SR71,LS-SR71,ar7100)) + +$(eval $(call SingleProfile,UBNTXM,$(fs_64k),RW2458N,rw2458n,RW2458N,ttyS0,115200,XM,XM,ar7240)) +$(eval $(call SingleProfile,UBNTXM,$(fs_64k),UBNTAIRROUTER,ubnt-airrouter,UBNT-AR,ttyS0,115200,XM,XM,ar7240)) +$(eval $(call SingleProfile,UBNTXM,$(fs_64k),UBNTBULLETM,ubnt-bullet-m,UBNT-BM,ttyS0,115200,XM,XM,ar7240)) +$(eval $(call SingleProfile,UBNTXM,$(fs_64k),UBNTROCKETM,ubnt-rocket-m,UBNT-RM,ttyS0,115200,XM,XM,ar7240)) +$(eval $(call SingleProfile,UBNTXM,$(fs_64k),UBNTNANOM,ubnt-nano-m,UBNT-NM,ttyS0,115200,XM,XM,ar7240)) +$(eval $(call SingleProfile,UBNTXM,$(fs_64k),UBNTUNIFI,ubnt-unifi,UBNT-UF,ttyS0,115200,XM,XM,ar7240)) + +$(eval $(call SingleProfile,WHRHPG300N,$(fs_64k),WHRG301N,whr-g301n,WHR-G301N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-G301N)) +$(eval $(call SingleProfile,WHRHPG300N,$(fs_64k),WHRHPG300N,whr-hp-g300n,WHR-HP-G300N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-HP-G300N)) +$(eval $(call SingleProfile,WHRHPG300N,$(fs_64k),WHRHPGN,whr-hp-gn,WHR-HP-GN,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-HP-GN)) +$(eval $(call SingleProfile,WHRHPG300N,$(fs_64k),WLAEAG300N,wlae-ag300n,WLAE-AG300N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WLAE-AG300N)) + +$(eval $(call SingleProfile,WRT400N,$(fs_64k),WRT400N,wrt400n,WRT400N,ttyS0,115200)) + +$(eval $(call SingleProfile,WZRHPG30XNH,$(fs_128k),WZRHPG300NH,wzr-hp-g300nh,WZR-HP-G300NH,ttyS0,115200,WZR-HP-G300NH)) +$(eval $(call SingleProfile,WZRHPG30XNH,$(fs_64k),WZRHPG300NH2,wzr-hp-g300nh2,WZR-HP-G300NH2,ttyS0,115200,WZR-HP-G300NH2)) +$(eval $(call SingleProfile,WZRHPG30XNH,$(fs_64k),WZRHPAG300H,wzr-hp-ag300h,WZR-HP-AG300H,ttyS0,115200,WZR-HP-AG300H)) +$(eval $(call SingleProfile,WZRHPG30XNH,$(fs_64k),WZRHPG450H,wzr-hp-g450h,WZR-HP-G450H,ttyS0,115200,WZR-HP-AG450H)) + +$(eval $(call SingleProfile,Zcomax,$(fs_64k),ZCN1523H28,zcn-1523h-2-8,ZCN-1523H-2,ttyS0,115200,$$(zcn1523h_mtdlayout))) +$(eval $(call SingleProfile,Zcomax,$(fs_64k),ZCN1523H516,zcn-1523h-5-16,ZCN-1523H-5,ttyS0,115200,$$(zcn1523h_mtdlayout))) + +$(eval $(call SingleProfile,ZyXEL,$(fs_64k),NBG_460N_550N_550NH,nbg460n_550n_550nh,NBG460N,ttyS0,115200,NBG-460N)) + + +$(eval $(call MultiProfile,AP121,AP121_2M AP121_4M)) +$(eval $(call MultiProfile,EWDORIN, EWDORINAP EWDORINRT)) +$(eval $(call MultiProfile,TEW652BRP,TEW652BRP_FW TEW652BRP_RECOVERY)) +$(eval $(call MultiProfile,TLWA901,TLWA901NV1 TLWA901NV2)) +$(eval $(call MultiProfile,TLWR740,TLWR740NV1 TLWR740NV3 TLWR740NV4)) +$(eval $(call MultiProfile,TLWR741,TLWR741NV1 TLWR741NV2 TLWR741NV4)) +$(eval $(call MultiProfile,TLWR841,TLWR841NV15 TLWR841NV3 TLWR841NV5 TLWR841NV7 TLWR841NV8)) +$(eval $(call MultiProfile,TLWR941,TLWR941NV2 TLWR941NV3 TLWR941NV4)) +$(eval $(call MultiProfile,TLWDR4300,TLWDR3600V1 TLWDR4300V1 TLWDR4310V1)) +$(eval $(call MultiProfile,UBNT,UBNTAIRROUTER UBNTRS UBNTRSPRO UBNTLSSR71 UBNTBULLETM UBNTROCKETM UBNTNANOM UBNTUNIFI)) +$(eval $(call MultiProfile,WNDR3700,WNDR3700V1 WNDR3700V2 WNDR3800 WNDRMAC WNDRMACV2)) +$(eval $(call MultiProfile,WP543,WP543_2M WP543_4M WP543_8M WP543_16M)) + +$(eval $(call MultiProfile,Default,$(SINGLE_PROFILES))) +$(eval $(call MultiProfile,Minimal,$(SINGLE_PROFILES))) +$(eval $(call MultiProfile,Madwifi,EAP7660D UBNTRS UBNTRSPRO UBNTLSSR71 WP543)) + +define Image/Build/squashfs + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-raw + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-64k + $(STAGING_DIR_HOST)/bin/padjffs2 $(KDIR)/root.squashfs-64k 64 + cp $(KDIR)/root.squashfs-64k $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs-64k + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build/Initramfs + $(call Image/Build/Profile/$(PROFILE),initramfs) +endef + +define Image/Prepare + gzip -9 -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz + $(call CompressLzma,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.lzma) + $(call Image/Build/Profile/$(if $(CONFIG_IB),Default,$(PROFILE)),loader) +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync + $(call Image/Build/Profile/$(PROFILE),$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ar71xx/image/lzma-loader/Makefile b/target/linux/ar71xx/image/lzma-loader/Makefile new file mode 100644 index 000000000..2e0b9111f --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/Makefile @@ -0,0 +1,64 @@ +# +# Copyright (C) 2011 OpenWrt.org +# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +LZMA_TEXT_START := 0x80a00000 +LOADER := loader.bin +LOADER_NAME := $(basename $(notdir $(LOADER))) +LOADER_DATA := +TARGET_DIR := +FLASH_OFFS := +FLASH_MAX := +BOARD := + +ifeq ($(TARGET_DIR),) +TARGET_DIR := $(KDIR) +endif + +LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin +LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz +LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME) + +.PHONY : loader-compile loader.bin loader.elf loader.gz + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +loader-compile: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + LOADER_DATA=$(LOADER_DATA) \ + FLASH_OFFS=$(FLASH_OFFS) \ + FLASH_MAX=$(FLASH_MAX) \ + BOARD="$(BOARD)" \ + clean all + +loader.gz: $(PKG_BUILD_DIR)/loader.bin + gzip -nc9 $< > $(LOADER_GZ) + +loader.elf: $(PKG_BUILD_DIR)/loader.elf + $(CP) $< $(LOADER_ELF) + +loader.bin: $(PKG_BUILD_DIR)/loader.bin + $(CP) $< $(LOADER_BIN) + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: loader-compile + +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 000000000..cb8345377 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,584 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 000000000..2870eeb9c --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h b/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h new file mode 100644 index 000000000..9c2729075 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_NO_SYSTEM_SIZE_T */ +/* You can use it, if you don't want <stddef.h> */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +#include <stddef.h> +typedef size_t SizeT; +#endif +#endif + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/Makefile b/target/linux/ar71xx/image/lzma-loader/src/Makefile new file mode 100644 index 000000000..3e6839c7c --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/Makefile @@ -0,0 +1,99 @@ +# +# Makefile for the LZMA compressed kernel loader for +# Atheros AR7XXX/AR9XXX based boards +# +# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> +# +# Some parts of this file was based on the OpenWrt specific lzma-loader +# for the BCM47xx and ADM5120 based boards: +# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) +# Copyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com> +# Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su> +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. +# + +LOADADDR := +LZMA_TEXT_START := 0x80a00000 +LOADER_DATA := +BOARD := +FLASH_OFFS := +FLASH_MAX := + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \ + -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \ + -fno-common -ffreestanding -fhonour-copts \ + -mabi=32 -march=mips32r2 \ + -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap +CFLAGS += -D_LZMA_PROB32 + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o loader.o cache.o board.o printf.o LzmaDecode.o + +ifneq ($(strip $(LOADER_DATA)),) +OBJECTS += data.o +CFLAGS += -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR) +endif + +ifneq ($(strip $(KERNEL_CMDLINE)),) +CFLAGS += -DCONFIG_KERNEL_CMDLINE='"$(KERNEL_CMDLINE)"' +endif + +ifneq ($(strip $(FLASH_OFFS)),) +CFLAGS += -DCONFIG_FLASH_OFFS=$(FLASH_OFFS) +endif + +ifneq ($(strip $(FLASH_MAX)),) +CFLAGS += -DCONFIG_FLASH_MAX=$(FLASH_MAX) +endif + +BOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _) +ifneq ($(BOARD_DEF),) +CFLAGS += -DCONFIG_BOARD_$(BOARD_DEF) +endif + +all: loader.bin + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +data.o: $(LOADER_DATA) + $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $< + +loader.bin: loader.elf + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +loader.elf: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +mrproper: clean + +clean: + rm -f *.elf *.bin *.o + + + diff --git a/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h b/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h new file mode 100644 index 000000000..19a4785bb --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h @@ -0,0 +1,725 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#define BIT(_x) (1UL << (_x)) + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9558 0x1130 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define AR944X_REV_ID_REVISION_MASK 0xf + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) + +#define AR934X_GPIO_OUT_GPIO 0x00 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/board.c b/target/linux/ar71xx/image/lzma-loader/src/board.c new file mode 100644 index 000000000..2f4dd6b1f --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/board.c @@ -0,0 +1,56 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <stddef.h> +#include "config.h" +#include "ar71xx_regs.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) + +#define UART_BASE 0xb8020000 + +#define UART_TX 0 +#define UART_LSR 5 + +#define UART_LSR_THRE 0x20 + +#define UART_READ(r) READREG(UART_BASE + 4 * (r)) +#define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) + +void board_putc(int ch) +{ + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_TX, ch); + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + +#ifdef CONFIG_BOARD_TL_WR1043ND_V1 +static void tlwr1043nd_init(void) +{ + unsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE); + unsigned int t; + + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); + t |= AR71XX_RESET_GE0_PHY; + WRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t); + /* flush write */ + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); +} +#else +static inline void tlwr1043nd_init(void) {} +#endif + +void board_init(void) +{ + tlwr1043nd_init(); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/cache.c b/target/linux/ar71xx/image/lzma-loader/src/cache.c new file mode 100644 index 000000000..28cc84833 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cache.c @@ -0,0 +1,43 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/cache.h b/target/linux/ar71xx/image/lzma-loader/src/cache.h new file mode 100644 index 000000000..506a23588 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cache.h @@ -0,0 +1,17 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __CACHE_H +#define __CACHE_H + +void flush_cache(unsigned long start_addr, unsigned long size); + +#endif /* __CACHE_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/cacheops.h b/target/linux/ar71xx/image/lzma-loader/src/cacheops.h new file mode 100644 index 000000000..70bcad769 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cacheops.h @@ -0,0 +1,85 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/config.h b/target/linux/ar71xx/image/lzma-loader/src/config.h new file mode 100644 index 000000000..287392b34 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/config.h @@ -0,0 +1,31 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define CONFIG_ICACHE_SIZE (32 * 1024) +#define CONFIG_DCACHE_SIZE (64 * 1024) +#define CONFIG_CACHELINE_SIZE 32 + +#ifndef CONFIG_FLASH_OFFS +#define CONFIG_FLASH_OFFS 0 +#endif + +#ifndef CONFIG_FLASH_MAX +#define CONFIG_FLASH_MAX 0 +#endif + +#ifndef CONFIG_FLASH_STEP +#define CONFIG_FLASH_STEP 0x1000 +#endif + +#endif /* _CONFIG_H_ */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h b/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h new file mode 100644 index 000000000..c1188ad8c --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * + * Copyright (C) 2001, Monta Vista Software + * Author: jsun@mvista.com or jsun@junsun.net + */ +#ifndef _cp0regdef_h_ +#define _cp0regdef_h_ + +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/head.S b/target/linux/ar71xx/image/lzma-loader/src/head.S new file mode 100644 index 000000000..543996a0d --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/head.S @@ -0,0 +1,118 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <asm/asm.h> +#include <asm/regdef.h> +#include "cp0regdef.h" +#include "cacheops.h" +#include "config.h" + +#define KSEG0 0x80000000 + + .macro ehb + sll zero, 3 + .endm + + .text + +LEAF(startup) + .set noreorder + .set mips32 + + mtc0 zero, CP0_WATCHLO # clear watch registers + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_CAUSE # clear before writing status register + + mfc0 t0, CP0_STATUS + li t1, 0x1000001f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS + ehb + + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + ehb + + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + + beqz t0, __reloc_done # if delta is 0 we are in the right place + nop + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + addu t0, t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + + /* flush cache */ + la t0, _code_start + la t1, _code_end + + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __flush_check + nop + +__flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__flush_check: + bne t0, t1, __flush_line + nop + + sync + +__reloc_done: + + /* clear bss */ + la t0, _bss_start + la t1, _bss_end + b __bss_check + nop + +__bss_fill: + sw zero, 0(t0) + addi t0, 4 + +__bss_check: + bne t0, t1, __bss_fill + nop + + /* Setup new "C" stack */ + la sp, _stack + + /* jump to the decompressor routine */ + la t0, loader_main + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader.c b/target/linux/ar71xx/image/lzma-loader/src/loader.c new file mode 100644 index 000000000..5c674ae5f --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader.c @@ -0,0 +1,263 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com> + * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su> + * + * The image_header structure has been taken from the U-Boot project. + * (C) Copyright 2008 Semihalf + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <stddef.h> +#include <stdint.h> + +#include "config.h" +#include "cache.h" +#include "printf.h" +#include "LzmaDecode.h" + +#define AR71XX_FLASH_START 0x1f000000 +#define AR71XX_FLASH_END 0x1fe00000 + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#undef LZMA_DEBUG + +#ifdef LZMA_DEBUG +# define DBG(f, a...) printf(f, ## a) +#else +# define DBG(f, a...) do {} while (0) +#endif + +#define IH_MAGIC_OKLI 0x4f4b4c49 /* 'OKLI' */ + +#define IH_NMLEN 32 /* Image Name Length */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +/* beyond the image end, size not known in advance */ +extern unsigned char workspace[]; +extern void board_init(void); + +static CLzmaDecoderState lzma_state; +static unsigned char *lzma_data; +static unsigned long lzma_datasize; +static unsigned long lzma_outsize; +static unsigned long kernel_la; + +#ifdef CONFIG_KERNEL_CMDLINE +#define kernel_argc 1 +static const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE; +static const char *kernel_argv[] = { + kernel_cmdline, + NULL, +}; +#endif /* CONFIG_KERNEL_CMDLINE */ + +static void halt(void) +{ + printf("\nSystem halted!\n"); + for(;;); +} + +static __inline__ unsigned long get_be32(void *buf) +{ + unsigned char *p = buf; + + return (((unsigned long) p[0] << 24) + + ((unsigned long) p[1] << 16) + + ((unsigned long) p[2] << 8) + + (unsigned long) p[3]); +} + +static __inline__ unsigned char lzma_get_byte(void) +{ + unsigned char c; + + lzma_datasize--; + c = *lzma_data++; + + return c; +} + +static int lzma_init_props(void) +{ + unsigned char props[LZMA_PROPERTIES_SIZE]; + int res; + int i; + + /* read lzma properties */ + for (i = 0; i < LZMA_PROPERTIES_SIZE; i++) + props[i] = lzma_get_byte(); + + /* read the lower half of uncompressed size in the header */ + lzma_outsize = ((SizeT) lzma_get_byte()) + + ((SizeT) lzma_get_byte() << 8) + + ((SizeT) lzma_get_byte() << 16) + + ((SizeT) lzma_get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + lzma_get_byte(); + + res = LzmaDecodeProperties(&lzma_state.Properties, props, + LZMA_PROPERTIES_SIZE); + return res; +} + +static int lzma_decompress(unsigned char *outStream) +{ + SizeT ip, op; + int ret; + + lzma_state.Probs = (CProb *) workspace; + + ret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream, + lzma_outsize, &op); + + if (ret != LZMA_RESULT_OK) { + int i; + + DBG("LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\n", + ret, lzma_data + ip, lzma_outsize, ip, op); + + for (i = 0; i < 16; i++) + DBG("%02x ", lzma_data[ip + i]); + + DBG("\n"); + } + + return ret; +} + +#if (LZMA_WRAPPER) +static void lzma_init_data(void) +{ + extern unsigned char _lzma_data_start[]; + extern unsigned char _lzma_data_end[]; + + kernel_la = LOADADDR; + lzma_data = _lzma_data_start; + lzma_datasize = _lzma_data_end - _lzma_data_start; +} +#else +static void lzma_init_data(void) +{ + struct image_header *hdr = NULL; + unsigned char *flash_base; + unsigned long flash_ofs; + unsigned long kernel_ofs; + unsigned long kernel_size; + + flash_base = (unsigned char *) KSEG1ADDR(AR71XX_FLASH_START); + + printf("Looking for OpenWrt image... "); + + for (flash_ofs = CONFIG_FLASH_OFFS; + flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX); + flash_ofs += CONFIG_FLASH_STEP) { + unsigned long magic; + unsigned char *p; + + p = flash_base + flash_ofs; + magic = get_be32(p); + if (magic == IH_MAGIC_OKLI) { + hdr = (struct image_header *) p; + break; + } + } + + if (hdr == NULL) { + printf("not found!\n"); + halt(); + } + + printf("found at 0x%08x\n", flash_base + flash_ofs); + + kernel_ofs = sizeof(struct image_header); + kernel_size = get_be32(&hdr->ih_size); + kernel_la = get_be32(&hdr->ih_load); + + lzma_data = flash_base + flash_ofs + kernel_ofs; + lzma_datasize = kernel_size; +} +#endif /* (LZMA_WRAPPER) */ + +void loader_main(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3) +{ + void (*kernel_entry) (unsigned long, unsigned long, unsigned long, + unsigned long); + int res; + + board_init(); + + printf("\n\nOpenWrt kernel loader for AR7XXX/AR9XXX\n"); + printf("Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n"); + + lzma_init_data(); + + res = lzma_init_props(); + if (res != LZMA_RESULT_OK) { + printf("Incorrect LZMA stream properties!\n"); + halt(); + } + + printf("Decompressing kernel... "); + + res = lzma_decompress((unsigned char *) kernel_la); + if (res != LZMA_RESULT_OK) { + printf("failed, "); + switch (res) { + case LZMA_RESULT_DATA_ERROR: + printf("data error!\n"); + break; + default: + printf("unknown error %d!\n", res); + } + halt(); + } else { + printf("done!\n"); + } + + flush_cache(kernel_la, lzma_outsize); + + printf("Starting kernel at %08x...\n\n", kernel_la); + +#ifdef CONFIG_KERNEL_CMDLINE + reg_a0 = kernel_argc; + reg_a1 = (unsigned long) kernel_argv; + reg_a2 = 0; + reg_a3 = 0; +#endif + + kernel_entry = (void *) kernel_la; + kernel_entry(reg_a0, reg_a1, reg_a2, reg_a3); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader.lds b/target/linux/ar71xx/image/lzma-loader/src/loader.lds new file mode 100644 index 000000000..80cc7ca3e --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader.lds @@ -0,0 +1,35 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.data.lzma) + } + + . = ALIGN(32); + .data : { + *(.data) + *(.data.*) + . = . + 524288; /* workaround for buggy bootloaders */ + } + + . = ALIGN(32); + _code_end = .; + + _bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + } + + . = ALIGN(32); + _bss_end = .; + + . = . + 8192; + _stack = .; + + workspace = .; +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds b/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds new file mode 100644 index 000000000..abf756ba1 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds @@ -0,0 +1,8 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .data.lzma : { + _lzma_data_start = .; + *(.data) + _lzma_data_end = .; + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/printf.c b/target/linux/ar71xx/image/lzma-loader/src/printf.c new file mode 100644 index 000000000..7bb5a86e1 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/printf.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" + +extern void board_putc(int ch); + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 256 + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +static int PrintChar(char *, char, int, int); +static int PrintString(char *, char *, int, int); +static int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +static void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +static int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +static int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +static int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} + +static void printf_output(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + board_putc(s[i]); + if (s[i] == '\n') board_putc('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(printf_output, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/printf.h b/target/linux/ar71xx/image/lzma-loader/src/printf.h new file mode 100644 index 000000000..9b1c1df23 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include <stdarg.h> +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/ar71xx/modules.mk b/target/linux/ar71xx/modules.mk new file mode 100644 index 000000000..5607d188c --- /dev/null +++ b/target/linux/ar71xx/modules.mk @@ -0,0 +1,86 @@ +# +# Copyright (C) 2006-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/leds-rb750 + SUBMENU:=$(LEDS_MENU) + TITLE:=RouterBOARD 750 LED support + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_LEDS_RB750 + FILES:=$(LINUX_DIR)/drivers/leds/leds-rb750.ko + AUTOLOAD:=$(call AutoLoad,60,leds-rb750) +endef + +define KernelPackage/leds-rb750/description + Kernel module for the LEDs on the MikroTik RouterBOARD 750. +endef + +$(eval $(call KernelPackage,leds-rb750)) + + +define KernelPackage/leds-wndr3700-usb + SUBMENU:=$(LEDS_MENU) + TITLE:=WNDR3700 USB LED support + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_LEDS_WNDR3700_USB + FILES:=$(LINUX_DIR)/drivers/leds/leds-wndr3700-usb.ko + AUTOLOAD:=$(call AutoLoad,60,leds-wndr3700-usb) +endef + +define KernelPackage/leds-wndr3700-usb/description + Kernel module for the USB LED on the NETGEAR WNDR3700 board. +endef + +$(eval $(call KernelPackage,leds-wndr3700-usb)) + + +define KernelPackage/nand-ar934x + SUBMENU:=$(OTHER_MENU) + TITLE:=Atheros AR934x NAND flash controller driver + KCONFIG:=CONFIG_MTD_NAND_AR934X + DEPENDS:=@TARGET_ar71xx +kmod-nand + FILES:=$(LINUX_DIR)/drivers/mtd/nand/ar934x_nfc.ko + AUTOLOAD:=$(call AutoLoad,30,ar934x_nfc) +endef + +define KernelPackage/nand-ar934x/description + Atheros AR934x NAND flash controller driver. +endef + +$(eval $(call KernelPackage,nand-ar934x)) + + +define KernelPackage/spi-vsc7385 + SUBMENU:=$(SPI_MENU) + TITLE:=Vitesse VSC7385 ethernet switch driver + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_SPI_VSC7385 + FILES:=$(LINUX_DIR)/drivers/spi/spi-vsc7385.ko + AUTOLOAD:=$(call AutoLoad,93,spi-vsc7385) +endef + +define KernelPackage/spi-vsc7385/description + This package contains the SPI driver for the Vitesse VSC7385 ethernet switch. +endef + +$(eval $(call KernelPackage,spi-vsc7385)) + + +define KernelPackage/wdt-ath79 + SUBMENU:=$(OTHER_MENU) + TITLE:=Atheros AR7XXX/AR9XXX watchdog timer + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_ATH79_WDT + FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/ath79_wdt.ko + AUTOLOAD:=$(call AutoLoad,50,ath79_wdt) +endef + +define KernelPackage/wdt-ath79/description + Kernel module for AR7XXX/AR9XXX watchdog timer. +endef + +$(eval $(call KernelPackage,wdt-ath79)) + diff --git a/target/linux/ar71xx/nand/config-default b/target/linux/ar71xx/nand/config-default new file mode 100644 index 000000000..1015cf1fb --- /dev/null +++ b/target/linux/ar71xx/nand/config-default @@ -0,0 +1,29 @@ +CONFIG_ATH79_DEV_NFC=y +CONFIG_CMDLINE="rootfstype=yaffs noinitrd" +# CONFIG_JFFS2_CMODE_PRIORITY is not set +# CONFIG_JFFS2_FS is not set +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AR934X=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_RB4XX=y +CONFIG_MTD_NAND_RB750=y +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_OVERLAYFS_FS is not set +CONFIG_SPI_RB4XX=y +CONFIG_SPI_RB4XX_CPLD=y +# CONFIG_SQUASHFS is not set +CONFIG_YAFFS_9BYTE_TAGS=y +CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_BACKGROUND is not set +# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +CONFIG_YAFFS_XATTR=y +CONFIG_YAFFS_YAFFS1=y +CONFIG_YAFFS_YAFFS2=y diff --git a/target/linux/ar71xx/nand/profiles/01-minimal.mk b/target/linux/ar71xx/nand/profiles/01-minimal.mk new file mode 100644 index 000000000..3651c88ab --- /dev/null +++ b/target/linux/ar71xx/nand/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DefaultNoWifi + NAME:=Default Profile (no WiFi) + PACKAGES:= +endef + +define Profile/DefaultNoWifi/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,DefaultNoWifi)) diff --git a/target/linux/ar71xx/nand/profiles/02-ath5k.mk b/target/linux/ar71xx/nand/profiles/02-ath5k.mk new file mode 100644 index 000000000..a291ff68a --- /dev/null +++ b/target/linux/ar71xx/nand/profiles/02-ath5k.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Ath5k + NAME:=Atheros WiFi (ath5k) + PACKAGES:=kmod-ath5k -kmod-ath9k +endef + +define Profile/Ath5k/Description + Package set compatible with hardware using Atheros WiFi cards. +endef +$(eval $(call Profile,Ath5k)) diff --git a/target/linux/ar71xx/nand/target.mk b/target/linux/ar71xx/nand/target.mk new file mode 100644 index 000000000..c571c5006 --- /dev/null +++ b/target/linux/ar71xx/nand/target.mk @@ -0,0 +1,8 @@ +BOARDNAME:=Devices with NAND flash (mostly Mikrotik) + +define Target/Description + Build firmware images for Atheros AR71xx/AR913x based boards with + NAND flash, e.g. MikroTik RB-4xx or RB-750 +endef + + diff --git a/target/linux/ar71xx/patches-3.3/000-USB-OHCI-Add-a-generic-platform-device-driver.patch b/target/linux/ar71xx/patches-3.3/000-USB-OHCI-Add-a-generic-platform-device-driver.patch new file mode 100644 index 000000000..240cca03b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/000-USB-OHCI-Add-a-generic-platform-device-driver.patch @@ -0,0 +1,293 @@ +From be77ba57151bd35ce63ccf52d74b6c626fa73817 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Tue, 13 Mar 2012 01:04:47 +0100 +Subject: [PATCH 01/47] USB: OHCI: Add a generic platform device driver + +This adds a generic driver for platform devices. It works like the PCI +driver and is based on it. This is for devices which do not have an own +bus but their OHCI controller works like a PCI controller. It will be +used for the Broadcom bcma and ssb USB OHCI controller. + +Acked-by: Alan Stern <stern@rowland.harvard.edu> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +--- + drivers/usb/host/Kconfig | 10 ++ + drivers/usb/host/ohci-hcd.c | 5 + + drivers/usb/host/ohci-platform.c | 194 ++++++++++++++++++++++++++++++++++++++ + include/linux/usb/ohci_pdriver.h | 38 ++++++++ + 4 files changed, 247 insertions(+), 0 deletions(-) + create mode 100644 drivers/usb/host/ohci-platform.c + create mode 100644 include/linux/usb/ohci_pdriver.h + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -393,6 +393,16 @@ config USB_CNS3XXX_OHCI + Enable support for the CNS3XXX SOC's on-chip OHCI controller. + It is needed for low-speed USB 1.0 device support. + ++config USB_OHCI_HCD_PLATFORM ++ bool "Generic OHCI driver for a platform device" ++ depends on USB_OHCI_HCD && EXPERIMENTAL ++ default n ++ ---help--- ++ Adds an OHCI host driver for a generic platform device, which ++ provieds a memory space and an irq. ++ ++ If unsure, say N. ++ + config USB_OHCI_BIG_ENDIAN_DESC + bool + depends on USB_OHCI_HCD +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1121,6 +1121,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ohci_xls_driver + #endif + ++#ifdef CONFIG_USB_OHCI_HCD_PLATFORM ++#include "ohci-platform.c" ++#define PLATFORM_DRIVER ohci_platform_driver ++#endif ++ + #if !defined(PCI_DRIVER) && \ + !defined(PLATFORM_DRIVER) && \ + !defined(OMAP1_PLATFORM_DRIVER) && \ +--- /dev/null ++++ b/drivers/usb/host/ohci-platform.c +@@ -0,0 +1,194 @@ ++/* ++ * Generic platform ohci driver ++ * ++ * Copyright 2007 Michael Buesch <m@bues.ch> ++ * Copyright 2011-2012 Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Derived from the OCHI-SSB driver ++ * Derived from the OHCI-PCI driver ++ * Copyright 1999 Roman Weissgaerber ++ * Copyright 2000-2002 David Brownell ++ * Copyright 1999 Linus Torvalds ++ * Copyright 1999 Gregory P. Smith ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++#include <linux/platform_device.h> ++#include <linux/usb/ohci_pdriver.h> ++ ++static int ohci_platform_reset(struct usb_hcd *hcd) ++{ ++ struct platform_device *pdev = to_platform_device(hcd->self.controller); ++ struct usb_ohci_pdata *pdata = pdev->dev.platform_data; ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int err; ++ ++ if (pdata->big_endian_desc) ++ ohci->flags |= OHCI_QUIRK_BE_DESC; ++ if (pdata->big_endian_mmio) ++ ohci->flags |= OHCI_QUIRK_BE_MMIO; ++ if (pdata->no_big_frame_no) ++ ohci->flags |= OHCI_QUIRK_FRAME_NO; ++ ++ ohci_hcd_init(ohci); ++ err = ohci_init(ohci); ++ ++ return err; ++} ++ ++static int ohci_platform_start(struct usb_hcd *hcd) ++{ ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int err; ++ ++ err = ohci_run(ohci); ++ if (err < 0) { ++ ohci_err(ohci, "can't start\n"); ++ ohci_stop(hcd); ++ } ++ ++ return err; ++} ++ ++static const struct hc_driver ohci_platform_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Generic Platform OHCI Controller", ++ .hcd_priv_size = sizeof(struct ohci_hcd), ++ ++ .irq = ohci_irq, ++ .flags = HCD_MEMORY | HCD_USB11, ++ ++ .reset = ohci_platform_reset, ++ .start = ohci_platform_start, ++ .stop = ohci_stop, ++ .shutdown = ohci_shutdown, ++ ++ .urb_enqueue = ohci_urb_enqueue, ++ .urb_dequeue = ohci_urb_dequeue, ++ .endpoint_disable = ohci_endpoint_disable, ++ ++ .get_frame_number = ohci_get_frame, ++ ++ .hub_status_data = ohci_hub_status_data, ++ .hub_control = ohci_hub_control, ++#ifdef CONFIG_PM ++ .bus_suspend = ohci_bus_suspend, ++ .bus_resume = ohci_bus_resume, ++#endif ++ ++ .start_port_reset = ohci_start_port_reset, ++}; ++ ++static int __devinit ohci_platform_probe(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd; ++ struct resource *res_mem; ++ int irq; ++ int err = -ENOMEM; ++ ++ BUG_ON(!dev->dev.platform_data); ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ irq = platform_get_irq(dev, 0); ++ if (irq < 0) { ++ pr_err("no irq provieded"); ++ return irq; ++ } ++ ++ res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!res_mem) { ++ pr_err("no memory recourse provieded"); ++ return -ENXIO; ++ } ++ ++ hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev, ++ dev_name(&dev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ hcd->rsrc_start = res_mem->start; ++ hcd->rsrc_len = resource_size(res_mem); ++ ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ pr_err("controller already in use"); ++ err = -EBUSY; ++ goto err_put_hcd; ++ } ++ ++ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) ++ goto err_release_region; ++ err = usb_add_hcd(hcd, irq, IRQF_SHARED); ++ if (err) ++ goto err_iounmap; ++ ++ platform_set_drvdata(dev, hcd); ++ ++ return err; ++ ++err_iounmap: ++ iounmap(hcd->regs); ++err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err_put_hcd: ++ usb_put_hcd(hcd); ++ return err; ++} ++ ++static int __devexit ohci_platform_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); ++ platform_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++ ++static int ohci_platform_suspend(struct device *dev) ++{ ++ return 0; ++} ++ ++static int ohci_platform_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ ++ ohci_finish_controller_resume(hcd); ++ return 0; ++} ++ ++#else /* !CONFIG_PM */ ++#define ohci_platform_suspend NULL ++#define ohci_platform_resume NULL ++#endif /* CONFIG_PM */ ++ ++static const struct platform_device_id ohci_platform_table[] = { ++ { "ohci-platform", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(platform, ohci_platform_table); ++ ++static const struct dev_pm_ops ohci_platform_pm_ops = { ++ .suspend = ohci_platform_suspend, ++ .resume = ohci_platform_resume, ++}; ++ ++static struct platform_driver ohci_platform_driver = { ++ .id_table = ohci_platform_table, ++ .probe = ohci_platform_probe, ++ .remove = __devexit_p(ohci_platform_remove), ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "ohci-platform", ++ .pm = &ohci_platform_pm_ops, ++ } ++}; +--- /dev/null ++++ b/include/linux/usb/ohci_pdriver.h +@@ -0,0 +1,38 @@ ++/* ++ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __USB_CORE_OHCI_PDRIVER_H ++#define __USB_CORE_OHCI_PDRIVER_H ++ ++/** ++ * struct usb_ohci_pdata - platform_data for generic ohci driver ++ * ++ * @big_endian_desc: BE descriptors ++ * @big_endian_mmio: BE registers ++ * @no_big_frame_no: no big endian frame_no shift ++ * ++ * These are general configuration options for the OHCI controller. All of ++ * these options are activating more or less workarounds for some hardware. ++ */ ++struct usb_ohci_pdata { ++ unsigned big_endian_desc:1; ++ unsigned big_endian_mmio:1; ++ unsigned no_big_frame_no:1; ++}; ++ ++#endif /* __USB_CORE_OHCI_PDRIVER_H */ diff --git a/target/linux/ar71xx/patches-3.3/001-USB-EHCI-Add-a-generic-platform-device-driver.patch b/target/linux/ar71xx/patches-3.3/001-USB-EHCI-Add-a-generic-platform-device-driver.patch new file mode 100644 index 000000000..f94f39c2e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/001-USB-EHCI-Add-a-generic-platform-device-driver.patch @@ -0,0 +1,305 @@ +From 4fa3face95f1ca2e396dd59324a6c6ef01df24cc Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Tue, 13 Mar 2012 01:04:48 +0100 +Subject: [PATCH 02/47] USB: EHCI: Add a generic platform device driver + +This adds a generic driver for platform devices. It works like the PCI +driver and is based on it. This is for devices which do not have an own +bus but their EHCI controller works like a PCI controller. It will be +used for the Broadcom bcma and ssb USB EHCI controller. + +Acked-by: Alan Stern <stern@rowland.harvard.edu> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +--- + drivers/usb/host/Kconfig | 10 ++ + drivers/usb/host/ehci-hcd.c | 5 + + drivers/usb/host/ehci-platform.c | 198 ++++++++++++++++++++++++++++++++++++++ + include/linux/usb/ehci_pdriver.h | 46 +++++++++ + 4 files changed, 259 insertions(+), 0 deletions(-) + create mode 100644 drivers/usb/host/ehci-platform.c + create mode 100644 include/linux/usb/ehci_pdriver.h + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -403,6 +403,16 @@ config USB_OHCI_HCD_PLATFORM + + If unsure, say N. + ++config USB_EHCI_HCD_PLATFORM ++ bool "Generic EHCI driver for a platform device" ++ depends on USB_EHCI_HCD && EXPERIMENTAL ++ default n ++ ---help--- ++ Adds an EHCI host driver for a generic platform device, which ++ provieds a memory space and an irq. ++ ++ If unsure, say N. ++ + config USB_OHCI_BIG_ENDIAN_DESC + bool + depends on USB_OHCI_HCD +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1381,6 +1381,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ehci_mv_driver + #endif + ++#ifdef CONFIG_USB_EHCI_HCD_PLATFORM ++#include "ehci-platform.c" ++#define PLATFORM_DRIVER ehci_platform_driver ++#endif ++ + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ + !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ + !defined(XILINX_OF_PLATFORM_DRIVER) +--- /dev/null ++++ b/drivers/usb/host/ehci-platform.c +@@ -0,0 +1,198 @@ ++/* ++ * Generic platform ehci driver ++ * ++ * Copyright 2007 Steven Brown <sbrown@cortland.com> ++ * Copyright 2010-2012 Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Derived from the ohci-ssb driver ++ * Copyright 2007 Michael Buesch <m@bues.ch> ++ * ++ * Derived from the EHCI-PCI driver ++ * Copyright (c) 2000-2004 by David Brownell ++ * ++ * Derived from the ohci-pci driver ++ * Copyright 1999 Roman Weissgaerber ++ * Copyright 2000-2002 David Brownell ++ * Copyright 1999 Linus Torvalds ++ * Copyright 1999 Gregory P. Smith ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++#include <linux/platform_device.h> ++#include <linux/usb/ehci_pdriver.h> ++ ++static int ehci_platform_reset(struct usb_hcd *hcd) ++{ ++ struct platform_device *pdev = to_platform_device(hcd->self.controller); ++ struct usb_ehci_pdata *pdata = pdev->dev.platform_data; ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int retval; ++ ++ hcd->has_tt = pdata->has_tt; ++ ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug; ++ ehci->big_endian_desc = pdata->big_endian_desc; ++ ehci->big_endian_mmio = pdata->big_endian_mmio; ++ ++ ehci->caps = hcd->regs + pdata->caps_offset; ++ retval = ehci_setup(hcd); ++ if (retval) ++ return retval; ++ ++ if (pdata->port_power_on) ++ ehci_port_power(ehci, 1); ++ if (pdata->port_power_off) ++ ehci_port_power(ehci, 0); ++ ++ return 0; ++} ++ ++static const struct hc_driver ehci_platform_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Generic Platform EHCI Controller", ++ .hcd_priv_size = sizeof(struct ehci_hcd), ++ ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ .reset = ehci_platform_reset, ++ .start = ehci_run, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, ++ ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ .endpoint_reset = ehci_endpoint_reset, ++ ++ .get_frame_number = ehci_get_frame, ++ ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#if defined(CONFIG_PM) ++ .bus_suspend = ehci_bus_suspend, ++ .bus_resume = ehci_bus_resume, ++#endif ++ .relinquish_port = ehci_relinquish_port, ++ .port_handed_over = ehci_port_handed_over, ++ ++ .update_device = ehci_update_device, ++ ++ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++}; ++ ++static int __devinit ehci_platform_probe(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd; ++ struct resource *res_mem; ++ int irq; ++ int err = -ENOMEM; ++ ++ BUG_ON(!dev->dev.platform_data); ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ irq = platform_get_irq(dev, 0); ++ if (irq < 0) { ++ pr_err("no irq provieded"); ++ return irq; ++ } ++ res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!res_mem) { ++ pr_err("no memory recourse provieded"); ++ return -ENXIO; ++ } ++ ++ hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev, ++ dev_name(&dev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ hcd->rsrc_start = res_mem->start; ++ hcd->rsrc_len = resource_size(res_mem); ++ ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ pr_err("controller already in use"); ++ err = -EBUSY; ++ goto err_put_hcd; ++ } ++ ++ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) ++ goto err_release_region; ++ err = usb_add_hcd(hcd, irq, IRQF_SHARED); ++ if (err) ++ goto err_iounmap; ++ ++ platform_set_drvdata(dev, hcd); ++ ++ return err; ++ ++err_iounmap: ++ iounmap(hcd->regs); ++err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err_put_hcd: ++ usb_put_hcd(hcd); ++ return err; ++} ++ ++static int __devexit ehci_platform_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); ++ platform_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++ ++static int ehci_platform_suspend(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ bool wakeup = device_may_wakeup(dev); ++ ++ ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), wakeup); ++ return 0; ++} ++ ++static int ehci_platform_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ ++ ehci_prepare_ports_for_controller_resume(hcd_to_ehci(hcd)); ++ return 0; ++} ++ ++#else /* !CONFIG_PM */ ++#define ehci_platform_suspend NULL ++#define ehci_platform_resume NULL ++#endif /* CONFIG_PM */ ++ ++static const struct platform_device_id ehci_platform_table[] = { ++ { "ehci-platform", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(platform, ehci_platform_table); ++ ++static const struct dev_pm_ops ehci_platform_pm_ops = { ++ .suspend = ehci_platform_suspend, ++ .resume = ehci_platform_resume, ++}; ++ ++static struct platform_driver ehci_platform_driver = { ++ .id_table = ehci_platform_table, ++ .probe = ehci_platform_probe, ++ .remove = __devexit_p(ehci_platform_remove), ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "ehci-platform", ++ .pm = &ehci_platform_pm_ops, ++ } ++}; +--- /dev/null ++++ b/include/linux/usb/ehci_pdriver.h +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __USB_CORE_EHCI_PDRIVER_H ++#define __USB_CORE_EHCI_PDRIVER_H ++ ++/** ++ * struct usb_ehci_pdata - platform_data for generic ehci driver ++ * ++ * @caps_offset: offset of the EHCI Capability Registers to the start of ++ * the io memory region provided to the driver. ++ * @has_tt: set to 1 if TT is integrated in root hub. ++ * @port_power_on: set to 1 if the controller needs a power up after ++ * initialization. ++ * @port_power_off: set to 1 if the controller needs to be powered down ++ * after initialization. ++ * ++ * These are general configuration options for the EHCI controller. All of ++ * these options are activating more or less workarounds for some hardware. ++ */ ++struct usb_ehci_pdata { ++ int caps_offset; ++ unsigned has_tt:1; ++ unsigned has_synopsys_hc_bug:1; ++ unsigned big_endian_desc:1; ++ unsigned big_endian_mmio:1; ++ unsigned port_power_on:1; ++ unsigned port_power_off:1; ++}; ++ ++#endif /* __USB_CORE_EHCI_PDRIVER_H */ diff --git a/target/linux/ar71xx/patches-3.3/002-USB-use-generic-platform-driver-on-ath79.patch b/target/linux/ar71xx/patches-3.3/002-USB-use-generic-platform-driver-on-ath79.patch new file mode 100644 index 000000000..d3a3b7106 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/002-USB-use-generic-platform-driver-on-ath79.patch @@ -0,0 +1,544 @@ +From dbcbcdd001c5943adbb18db3b8f0dafc405559eb Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Tue, 13 Mar 2012 01:04:53 +0100 +Subject: [PATCH 03/47] USB: use generic platform driver on ath79 + +The ath79 usb driver doesn't do anything special and is now converted +to the generic ehci and ohci driver. +This was tested on a TP-Link TL-WR1043ND (AR9132) + +Acked-by: Gabor Juhos <juhosg@openwrt.org> +CC: Imre Kaloz <kaloz@openwrt.org> +CC: linux-mips@linux-mips.org +CC: Ralf Baechle <ralf@linux-mips.org> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +--- + arch/mips/ath79/dev-usb.c | 31 +++++- + drivers/usb/host/Kconfig | 12 ++- + drivers/usb/host/ehci-ath79.c | 208 ----------------------------------------- + drivers/usb/host/ehci-hcd.c | 5 - + drivers/usb/host/ohci-ath79.c | 151 ----------------------------- + drivers/usb/host/ohci-hcd.c | 5 - + 6 files changed, 35 insertions(+), 377 deletions(-) + delete mode 100644 drivers/usb/host/ehci-ath79.c + delete mode 100644 drivers/usb/host/ohci-ath79.c + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -17,6 +17,8 @@ + #include <linux/irq.h> + #include <linux/dma-mapping.h> + #include <linux/platform_device.h> ++#include <linux/usb/ehci_pdriver.h> ++#include <linux/usb/ohci_pdriver.h> + + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/ar71xx_regs.h> +@@ -36,14 +38,19 @@ static struct resource ath79_ohci_resour + }; + + static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); ++ ++static struct usb_ohci_pdata ath79_ohci_pdata = { ++}; ++ + static struct platform_device ath79_ohci_device = { +- .name = "ath79-ohci", ++ .name = "ohci-platform", + .id = -1, + .resource = ath79_ohci_resources, + .num_resources = ARRAY_SIZE(ath79_ohci_resources), + .dev = { + .dma_mask = &ath79_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &ath79_ohci_pdata, + }, + }; + +@@ -60,8 +67,20 @@ static struct resource ath79_ehci_resour + }; + + static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); ++ ++static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { ++ .has_synopsys_hc_bug = 1, ++ .port_power_off = 1, ++}; ++ ++static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { ++ .caps_offset = 0x100, ++ .has_tt = 1, ++ .port_power_off = 1, ++}; ++ + static struct platform_device ath79_ehci_device = { +- .name = "ath79-ehci", ++ .name = "ehci-platform", + .id = -1, + .resource = ath79_ehci_resources, + .num_resources = ARRAY_SIZE(ath79_ehci_resources), +@@ -101,7 +120,7 @@ static void __init ath79_usb_setup(void) + + ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; + ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar71xx-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; + platform_device_register(&ath79_ehci_device); + } + +@@ -142,7 +161,7 @@ static void __init ar724x_usb_setup(void + + ath79_ehci_resources[0].start = AR724X_EHCI_BASE; + ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar724x-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } + +@@ -159,7 +178,7 @@ static void __init ar913x_usb_setup(void + + ath79_ehci_resources[0].start = AR913X_EHCI_BASE; + ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar913x-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } + +@@ -176,7 +195,7 @@ static void __init ar933x_usb_setup(void + + ath79_ehci_resources[0].start = AR933X_EHCI_BASE; + ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar933x-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -218,11 +218,15 @@ config USB_CNS3XXX_EHCI + support. + + config USB_EHCI_ATH79 +- bool "EHCI support for AR7XXX/AR9XXX SoCs" ++ bool "EHCI support for AR7XXX/AR9XXX SoCs (DEPRECATED)" + depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) + select USB_EHCI_ROOT_HUB_TT ++ select USB_EHCI_HCD_PLATFORM + default y + ---help--- ++ This option is deprecated now and the driver was removed, use ++ USB_EHCI_HCD_PLATFORM instead. ++ + Enables support for the built-in EHCI controller present + on the Atheros AR7XXX/AR9XXX SoCs. + +@@ -312,10 +316,14 @@ config USB_OHCI_HCD_OMAP3 + OMAP3 and later chips. + + config USB_OHCI_ATH79 +- bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" ++ bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs (DEPRECATED)" + depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) ++ select USB_OHCI_HCD_PLATFORM + default y + help ++ This option is deprecated now and the driver was removed, use ++ USB_OHCI_HCD_PLATFORM instead. ++ + Enables support for the built-in OHCI controller present on the + Atheros AR71XX/AR7240 SoCs. + +--- a/drivers/usb/host/ehci-ath79.c ++++ /dev/null +@@ -1,208 +0,0 @@ +-/* +- * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. +- * +- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> +- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> +- * +- * Parts of this file are based on Atheros' 2.6.15 BSP +- * Copyright (C) 2007 Atheros Communications, Inc. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include <linux/platform_device.h> +- +-enum { +- EHCI_ATH79_IP_V1 = 0, +- EHCI_ATH79_IP_V2, +-}; +- +-static const struct platform_device_id ehci_ath79_id_table[] = { +- { +- .name = "ar71xx-ehci", +- .driver_data = EHCI_ATH79_IP_V1, +- }, +- { +- .name = "ar724x-ehci", +- .driver_data = EHCI_ATH79_IP_V2, +- }, +- { +- .name = "ar913x-ehci", +- .driver_data = EHCI_ATH79_IP_V2, +- }, +- { +- .name = "ar933x-ehci", +- .driver_data = EHCI_ATH79_IP_V2, +- }, +- { +- /* terminating entry */ +- }, +-}; +- +-MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); +- +-static int ehci_ath79_init(struct usb_hcd *hcd) +-{ +- struct ehci_hcd *ehci = hcd_to_ehci(hcd); +- struct platform_device *pdev = to_platform_device(hcd->self.controller); +- const struct platform_device_id *id; +- int ret; +- +- id = platform_get_device_id(pdev); +- if (!id) { +- dev_err(hcd->self.controller, "missing device id\n"); +- return -EINVAL; +- } +- +- switch (id->driver_data) { +- case EHCI_ATH79_IP_V1: +- ehci->has_synopsys_hc_bug = 1; +- +- ehci->caps = hcd->regs; +- ehci->regs = hcd->regs + +- HC_LENGTH(ehci, +- ehci_readl(ehci, &ehci->caps->hc_capbase)); +- break; +- +- case EHCI_ATH79_IP_V2: +- hcd->has_tt = 1; +- +- ehci->caps = hcd->regs + 0x100; +- ehci->regs = hcd->regs + 0x100 + +- HC_LENGTH(ehci, +- ehci_readl(ehci, &ehci->caps->hc_capbase)); +- break; +- +- default: +- BUG(); +- } +- +- dbg_hcs_params(ehci, "reset"); +- dbg_hcc_params(ehci, "reset"); +- ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); +- ehci->sbrn = 0x20; +- +- ehci_reset(ehci); +- +- ret = ehci_init(hcd); +- if (ret) +- return ret; +- +- ehci_port_power(ehci, 0); +- +- return 0; +-} +- +-static const struct hc_driver ehci_ath79_hc_driver = { +- .description = hcd_name, +- .product_desc = "Atheros built-in EHCI controller", +- .hcd_priv_size = sizeof(struct ehci_hcd), +- .irq = ehci_irq, +- .flags = HCD_MEMORY | HCD_USB2, +- +- .reset = ehci_ath79_init, +- .start = ehci_run, +- .stop = ehci_stop, +- .shutdown = ehci_shutdown, +- +- .urb_enqueue = ehci_urb_enqueue, +- .urb_dequeue = ehci_urb_dequeue, +- .endpoint_disable = ehci_endpoint_disable, +- .endpoint_reset = ehci_endpoint_reset, +- +- .get_frame_number = ehci_get_frame, +- +- .hub_status_data = ehci_hub_status_data, +- .hub_control = ehci_hub_control, +- +- .relinquish_port = ehci_relinquish_port, +- .port_handed_over = ehci_port_handed_over, +- +- .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +-}; +- +-static int ehci_ath79_probe(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd; +- struct resource *res; +- int irq; +- int ret; +- +- if (usb_disabled()) +- return -ENODEV; +- +- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no IRQ specified\n"); +- return -ENODEV; +- } +- irq = res->start; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no base address specified\n"); +- return -ENODEV; +- } +- +- hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, +- dev_name(&pdev->dev)); +- if (!hcd) +- return -ENOMEM; +- +- hcd->rsrc_start = res->start; +- hcd->rsrc_len = resource_size(res); +- +- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { +- dev_dbg(&pdev->dev, "controller already in use\n"); +- ret = -EBUSY; +- goto err_put_hcd; +- } +- +- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); +- if (!hcd->regs) { +- dev_dbg(&pdev->dev, "error mapping memory\n"); +- ret = -EFAULT; +- goto err_release_region; +- } +- +- ret = usb_add_hcd(hcd, irq, IRQF_SHARED); +- if (ret) +- goto err_iounmap; +- +- return 0; +- +-err_iounmap: +- iounmap(hcd->regs); +- +-err_release_region: +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +-err_put_hcd: +- usb_put_hcd(hcd); +- return ret; +-} +- +-static int ehci_ath79_remove(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd = platform_get_drvdata(pdev); +- +- usb_remove_hcd(hcd); +- iounmap(hcd->regs); +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +- usb_put_hcd(hcd); +- +- return 0; +-} +- +-static struct platform_driver ehci_ath79_driver = { +- .probe = ehci_ath79_probe, +- .remove = ehci_ath79_remove, +- .id_table = ehci_ath79_id_table, +- .driver = { +- .owner = THIS_MODULE, +- .name = "ath79-ehci", +- } +-}; +- +-MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1356,11 +1356,6 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER s5p_ehci_driver + #endif + +-#ifdef CONFIG_USB_EHCI_ATH79 +-#include "ehci-ath79.c" +-#define PLATFORM_DRIVER ehci_ath79_driver +-#endif +- + #ifdef CONFIG_SPARC_LEON + #include "ehci-grlib.c" + #define PLATFORM_DRIVER ehci_grlib_driver +--- a/drivers/usb/host/ohci-ath79.c ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * OHCI HCD (Host Controller Driver) for USB. +- * +- * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. +- * +- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> +- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> +- * +- * Parts of this file are based on Atheros' 2.6.15 BSP +- * Copyright (C) 2007 Atheros Communications, Inc. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include <linux/platform_device.h> +- +-static int __devinit ohci_ath79_start(struct usb_hcd *hcd) +-{ +- struct ohci_hcd *ohci = hcd_to_ohci(hcd); +- int ret; +- +- ret = ohci_init(ohci); +- if (ret < 0) +- return ret; +- +- ret = ohci_run(ohci); +- if (ret < 0) +- goto err; +- +- return 0; +- +-err: +- ohci_stop(hcd); +- return ret; +-} +- +-static const struct hc_driver ohci_ath79_hc_driver = { +- .description = hcd_name, +- .product_desc = "Atheros built-in OHCI controller", +- .hcd_priv_size = sizeof(struct ohci_hcd), +- +- .irq = ohci_irq, +- .flags = HCD_USB11 | HCD_MEMORY, +- +- .start = ohci_ath79_start, +- .stop = ohci_stop, +- .shutdown = ohci_shutdown, +- +- .urb_enqueue = ohci_urb_enqueue, +- .urb_dequeue = ohci_urb_dequeue, +- .endpoint_disable = ohci_endpoint_disable, +- +- /* +- * scheduling support +- */ +- .get_frame_number = ohci_get_frame, +- +- /* +- * root hub support +- */ +- .hub_status_data = ohci_hub_status_data, +- .hub_control = ohci_hub_control, +- .start_port_reset = ohci_start_port_reset, +-}; +- +-static int ohci_ath79_probe(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd; +- struct resource *res; +- int irq; +- int ret; +- +- if (usb_disabled()) +- return -ENODEV; +- +- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no IRQ specified\n"); +- return -ENODEV; +- } +- irq = res->start; +- +- hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, +- dev_name(&pdev->dev)); +- if (!hcd) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no base address specified\n"); +- ret = -ENODEV; +- goto err_put_hcd; +- } +- hcd->rsrc_start = res->start; +- hcd->rsrc_len = resource_size(res); +- +- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { +- dev_dbg(&pdev->dev, "controller already in use\n"); +- ret = -EBUSY; +- goto err_put_hcd; +- } +- +- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); +- if (!hcd->regs) { +- dev_dbg(&pdev->dev, "error mapping memory\n"); +- ret = -EFAULT; +- goto err_release_region; +- } +- +- ohci_hcd_init(hcd_to_ohci(hcd)); +- +- ret = usb_add_hcd(hcd, irq, 0); +- if (ret) +- goto err_stop_hcd; +- +- return 0; +- +-err_stop_hcd: +- iounmap(hcd->regs); +-err_release_region: +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +-err_put_hcd: +- usb_put_hcd(hcd); +- return ret; +-} +- +-static int ohci_ath79_remove(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd = platform_get_drvdata(pdev); +- +- usb_remove_hcd(hcd); +- iounmap(hcd->regs); +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +- usb_put_hcd(hcd); +- +- return 0; +-} +- +-static struct platform_driver ohci_hcd_ath79_driver = { +- .probe = ohci_ath79_probe, +- .remove = ohci_ath79_remove, +- .shutdown = usb_hcd_platform_shutdown, +- .driver = { +- .name = "ath79-ohci", +- .owner = THIS_MODULE, +- }, +-}; +- +-MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1111,11 +1111,6 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver + #endif + +-#ifdef CONFIG_USB_OHCI_ATH79 +-#include "ohci-ath79.c" +-#define PLATFORM_DRIVER ohci_hcd_ath79_driver +-#endif +- + #ifdef CONFIG_CPU_XLR + #include "ohci-xls.c" + #define PLATFORM_DRIVER ohci_xls_driver diff --git a/target/linux/ar71xx/patches-3.3/100-MIPS-ath79-separate-common-PCI-code.patch b/target/linux/ar71xx/patches-3.3/100-MIPS-ath79-separate-common-PCI-code.patch new file mode 100644 index 000000000..6062c894f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/100-MIPS-ath79-separate-common-PCI-code.patch @@ -0,0 +1,150 @@ +From 9d9c0d49315520754660c8df3f42d93ecf7dba7a Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:21 +0100 +Subject: [PATCH 05/47] MIPS: ath79: separate common PCI code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The 'pcibios_map_irq' and 'pcibios_plat_dev_init' +are common functions and only instance one of them +can be present in a single kernel. + +Currently these functions can be built only if the +CONFIG_SOC_AR724X option is selected. However the +ath79 platform contain support for the AR71XX SoCs,. +The AR71XX SoCs have a differnet PCI controller, +and those will require a different code. + +Move the common PCI code into a separeate file in +order to be able to use that with other SoCs as +well. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: René Bolldorf <xsecute@googlemail.com> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3485/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Makefile | 1 + + arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++ + arch/mips/pci/pci-ath724x.c | 34 ------------------------------- + 3 files changed, 47 insertions(+), 34 deletions(-) + create mode 100644 arch/mips/ath79/pci.c + +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -11,6 +11,7 @@ + obj-y := prom.o setup.o irq.o common.o clock.o gpio.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++obj-$(CONFIG_PCI) += pci.o + + # + # Devices +--- /dev/null ++++ b/arch/mips/ath79/pci.c +@@ -0,0 +1,46 @@ ++/* ++ * Atheros AR71XX/AR724X specific PCI setup code ++ * ++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include <linux/pci.h> ++#include <asm/mach-ath79/pci-ath724x.h> ++ ++static struct ath724x_pci_data *pci_data; ++static int pci_data_size; ++ ++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) ++{ ++ pci_data = data; ++ pci_data_size = size; ++} ++ ++int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) ++{ ++ unsigned int devfn = dev->devfn; ++ int irq = -1; ++ ++ if (devfn > pci_data_size - 1) ++ return irq; ++ ++ irq = pci_data[devfn].irq; ++ ++ return irq; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ unsigned int devfn = dev->devfn; ++ ++ if (devfn > pci_data_size - 1) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ dev->dev.platform_data = pci_data[devfn].pdata; ++ ++ return PCIBIOS_SUCCESSFUL; ++} +--- a/arch/mips/pci/pci-ath724x.c ++++ b/arch/mips/pci/pci-ath724x.c +@@ -9,7 +9,6 @@ + */ + + #include <linux/pci.h> +-#include <asm/mach-ath79/pci-ath724x.h> + + #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) + #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +@@ -19,8 +18,6 @@ + #define ATH724X_PCI_MEM_SIZE 0x08000000 + + static DEFINE_SPINLOCK(ath724x_pci_lock); +-static struct ath724x_pci_data *pci_data; +-static int pci_data_size; + + static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) +@@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci + .mem_resource = &ath724x_mem_resource, + }; + +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) +-{ +- pci_data = data; +- pci_data_size = size; +-} +- +-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) +-{ +- unsigned int devfn = dev->devfn; +- int irq = -1; +- +- if (devfn > pci_data_size - 1) +- return irq; +- +- irq = pci_data[devfn].irq; +- +- return irq; +-} +- +-int pcibios_plat_dev_init(struct pci_dev *dev) +-{ +- unsigned int devfn = dev->devfn; +- +- if (devfn > pci_data_size - 1) +- return PCIBIOS_DEVICE_NOT_FOUND; +- +- dev->dev.platform_data = pci_data[devfn].pdata; +- +- return PCIBIOS_SUCCESSFUL; +-} +- + static int __init ath724x_pcibios_init(void) + { + register_pci_controller(&ath724x_pci_controller); diff --git a/target/linux/ar71xx/patches-3.3/101-MIPS-ath79-rename-pci-ath724x.h.patch b/target/linux/ar71xx/patches-3.3/101-MIPS-ath79-rename-pci-ath724x.h.patch new file mode 100644 index 000000000..f28f20cb2 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/101-MIPS-ath79-rename-pci-ath724x.h.patch @@ -0,0 +1,102 @@ +From 293dcf4142717d8059540bd69d1517c442617569 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:22 +0100 +Subject: [PATCH 06/47] MIPS: ath79: rename pci-ath724x.h +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The declared function in this header file is used by the +ath79 platform code only. Move the header to the platform +directory. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: René Bolldorf <xsecute@googlemail.com> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3486/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 2 +- + arch/mips/ath79/pci.c | 2 +- + arch/mips/ath79/pci.h | 21 +++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 --------------------- + 4 files changed, 23 insertions(+), 23 deletions(-) + create mode 100644 arch/mips/ath79/pci.h + delete mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -15,13 +15,13 @@ + + #ifdef CONFIG_PCI + #include <linux/ath9k_platform.h> +-#include <asm/mach-ath79/pci-ath724x.h> + #endif /* CONFIG_PCI */ + + #include "machtypes.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" ++#include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 + #define UBNT_XM_GPIO_LED_L2 1 +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -9,7 +9,7 @@ + */ + + #include <linux/pci.h> +-#include <asm/mach-ath79/pci-ath724x.h> ++#include "pci.h" + + static struct ath724x_pci_data *pci_data; + static int pci_data_size; +--- /dev/null ++++ b/arch/mips/ath79/pci.h +@@ -0,0 +1,21 @@ ++/* ++ * Atheros 724x PCI support ++ * ++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H ++#define __ASM_MACH_ATH79_PCI_ATH724X_H ++ ++struct ath724x_pci_data { ++ int irq; ++ void *pdata; ++}; ++ ++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); ++ ++#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ +--- a/arch/mips/include/asm/mach-ath79/pci-ath724x.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* +- * Atheros 724x PCI support +- * +- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H +-#define __ASM_MACH_ATH79_PCI_ATH724X_H +- +-struct ath724x_pci_data { +- int irq; +- void *pdata; +-}; +- +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); +- +-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ diff --git a/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch b/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch new file mode 100644 index 000000000..9696a7522 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch @@ -0,0 +1,61 @@ +From a9e38566ebe755219db10fa155fa8f0f4efc20d9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:23 +0100 +Subject: [PATCH 07/47] MIPS: ath79: make ath724x_pcibios_init visible for external code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: René Bolldorf <xsecute@googlemail.com> +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3487/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++ + arch/mips/pci/pci-ath724x.c | 3 ++- + 2 files changed, 22 insertions(+), 1 deletions(-) + create mode 100644 arch/mips/include/asm/mach-ath79/pci.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -0,0 +1,20 @@ ++/* ++ * Atheros 724x PCI support ++ * ++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_PCI_H ++#define __ASM_MACH_ATH79_PCI_H ++ ++#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) ++int ath724x_pcibios_init(void); ++#else ++static inline int ath724x_pcibios_init(void) { return 0; } ++#endif ++ ++#endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ath724x.c ++++ b/arch/mips/pci/pci-ath724x.c +@@ -9,6 +9,7 @@ + */ + + #include <linux/pci.h> ++#include <asm/mach-ath79/pci.h> + + #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) + #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +@@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci + .mem_resource = &ath724x_mem_resource, + }; + +-static int __init ath724x_pcibios_init(void) ++int __init ath724x_pcibios_init(void) + { + register_pci_controller(&ath724x_pci_controller); + diff --git a/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-add-a-common-PCI-registration-function.patch b/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-add-a-common-PCI-registration-function.patch new file mode 100644 index 000000000..34587b63a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-add-a-common-PCI-registration-function.patch @@ -0,0 +1,78 @@ +From e3edaac2e967f07ae3b726e64e1c290233361bc7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:24 +0100 +Subject: [PATCH 08/47] MIPS: ath79: add a common PCI registration function + +The current code unconditionally registers the AR724X +specific PCI controller, even if the kernel is running +on a different SoC. + +Add a common function for PCI controller registration, +and only register the AR724X PCI controller if the kernel +is running on an AR724X SoC. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3488/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 1 + + arch/mips/ath79/pci.c | 10 ++++++++++ + arch/mips/ath79/pci.h | 6 ++++++ + arch/mips/pci/pci-ath724x.c | 2 -- + 4 files changed, 17 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void) + ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + #endif /* CONFIG_PCI */ + ++ ath79_register_pci(); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -9,6 +9,8 @@ + */ + + #include <linux/pci.h> ++#include <asm/mach-ath79/ath79.h> ++#include <asm/mach-ath79/pci.h> + #include "pci.h" + + static struct ath724x_pci_data *pci_data; +@@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev + + return PCIBIOS_SUCCESSFUL; + } ++ ++int __init ath79_register_pci(void) ++{ ++ if (soc_is_ar724x()) ++ return ath724x_pcibios_init(); ++ ++ return -ENODEV; ++} +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -18,4 +18,10 @@ struct ath724x_pci_data { + + void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); + ++#ifdef CONFIG_PCI ++int ath79_register_pci(void); ++#else ++static inline int ath79_register_pci(void) { return 0; } ++#endif ++ + #endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ +--- a/arch/mips/pci/pci-ath724x.c ++++ b/arch/mips/pci/pci-ath724x.c +@@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void) + + return PCIBIOS_SUCCESSFUL; + } +- +-arch_initcall(ath724x_pcibios_init); diff --git a/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch b/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch new file mode 100644 index 000000000..e7189289c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch @@ -0,0 +1,316 @@ +From 36dfdaa097ee1b12139187dc89cfa23fbb92b53b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:25 +0100 +Subject: [PATCH 09/47] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: René Bolldorf <xsecute@googlemail.com> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3489/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/pci/Makefile | 2 +- + arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++ + arch/mips/pci/pci-ath724x.c | 139 ------------------------------------------- + 3 files changed, 140 insertions(+), 140 deletions(-) + create mode 100644 arch/mips/pci/pci-ar724x.c + delete mode 100644 arch/mips/pci/pci-ath724x.c + +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o +-obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o ++obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o + + # + # These are still pretty much in the old state, watch, go blind. +--- /dev/null ++++ b/arch/mips/pci/pci-ar724x.c +@@ -0,0 +1,139 @@ ++/* ++ * Atheros 724x PCI support ++ * ++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include <linux/pci.h> ++#include <asm/mach-ath79/pci.h> ++ ++#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) ++#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) ++ ++#define ATH724X_PCI_DEV_BASE 0x14000000 ++#define ATH724X_PCI_MEM_BASE 0x10000000 ++#define ATH724X_PCI_MEM_SIZE 0x08000000 ++ ++static DEFINE_SPINLOCK(ath724x_pci_lock); ++ ++static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, uint32_t *value) ++{ ++ unsigned long flags, addr, tval, mask; ++ ++ if (devfn) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ if (where & (size - 1)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ spin_lock_irqsave(&ath724x_pci_lock, flags); ++ ++ switch (size) { ++ case 1: ++ addr = where & ~3; ++ mask = 0xff000000 >> ((where % 4) * 8); ++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = tval & ~mask; ++ *value = (tval >> ((4 - (where % 4))*8)); ++ break; ++ case 2: ++ addr = where & ~3; ++ mask = 0xffff0000 >> ((where % 4)*8); ++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = tval & ~mask; ++ *value = (tval >> ((4 - (where % 4))*8)); ++ break; ++ case 4: ++ *value = reg_read(ATH724X_PCI_DEV_BASE + where); ++ break; ++ default: ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, uint32_t value) ++{ ++ unsigned long flags, tval, addr, mask; ++ ++ if (devfn) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ if (where & (size - 1)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ spin_lock_irqsave(&ath724x_pci_lock, flags); ++ ++ switch (size) { ++ case 1: ++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ mask = 0xff000000 >> ((where % 4)*8); ++ tval = reg_read(addr); ++ tval = tval & ~mask; ++ tval |= (value << ((4 - (where % 4))*8)) & mask; ++ reg_write(addr, tval); ++ break; ++ case 2: ++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ mask = 0xffff0000 >> ((where % 4)*8); ++ tval = reg_read(addr); ++ tval = tval & ~mask; ++ tval |= (value << ((4 - (where % 4))*8)) & mask; ++ reg_write(addr, tval); ++ break; ++ case 4: ++ reg_write((ATH724X_PCI_DEV_BASE + where), value); ++ break; ++ default: ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static struct pci_ops ath724x_pci_ops = { ++ .read = ath724x_pci_read, ++ .write = ath724x_pci_write, ++}; ++ ++static struct resource ath724x_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ath724x_mem_resource = { ++ .name = "PCI memory space", ++ .start = ATH724X_PCI_MEM_BASE, ++ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_controller ath724x_pci_controller = { ++ .pci_ops = &ath724x_pci_ops, ++ .io_resource = &ath724x_io_resource, ++ .mem_resource = &ath724x_mem_resource, ++}; ++ ++int __init ath724x_pcibios_init(void) ++{ ++ register_pci_controller(&ath724x_pci_controller); ++ ++ return PCIBIOS_SUCCESSFUL; ++} +--- a/arch/mips/pci/pci-ath724x.c ++++ /dev/null +@@ -1,139 +0,0 @@ +-/* +- * Atheros 724x PCI support +- * +- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include <linux/pci.h> +-#include <asm/mach-ath79/pci.h> +- +-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) +-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +- +-#define ATH724X_PCI_DEV_BASE 0x14000000 +-#define ATH724X_PCI_MEM_BASE 0x10000000 +-#define ATH724X_PCI_MEM_SIZE 0x08000000 +- +-static DEFINE_SPINLOCK(ath724x_pci_lock); +- +-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, +- int size, uint32_t *value) +-{ +- unsigned long flags, addr, tval, mask; +- +- if (devfn) +- return PCIBIOS_DEVICE_NOT_FOUND; +- +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- +- spin_lock_irqsave(&ath724x_pci_lock, flags); +- +- switch (size) { +- case 1: +- addr = where & ~3; +- mask = 0xff000000 >> ((where % 4) * 8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); +- break; +- case 2: +- addr = where & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); +- break; +- case 4: +- *value = reg_read(ATH724X_PCI_DEV_BASE + where); +- break; +- default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_BAD_REGISTER_NUMBER; +- } +- +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_SUCCESSFUL; +-} +- +-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, +- int size, uint32_t value) +-{ +- unsigned long flags, tval, addr, mask; +- +- if (devfn) +- return PCIBIOS_DEVICE_NOT_FOUND; +- +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- +- spin_lock_irqsave(&ath724x_pci_lock, flags); +- +- switch (size) { +- case 1: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; +- mask = 0xff000000 >> ((where % 4)*8); +- tval = reg_read(addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); +- break; +- case 2: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); +- break; +- case 4: +- reg_write((ATH724X_PCI_DEV_BASE + where), value); +- break; +- default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_BAD_REGISTER_NUMBER; +- } +- +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_SUCCESSFUL; +-} +- +-static struct pci_ops ath724x_pci_ops = { +- .read = ath724x_pci_read, +- .write = ath724x_pci_write, +-}; +- +-static struct resource ath724x_io_resource = { +- .name = "PCI IO space", +- .start = 0, +- .end = 0, +- .flags = IORESOURCE_IO, +-}; +- +-static struct resource ath724x_mem_resource = { +- .name = "PCI memory space", +- .start = ATH724X_PCI_MEM_BASE, +- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-static struct pci_controller ath724x_pci_controller = { +- .pci_ops = &ath724x_pci_ops, +- .io_resource = &ath724x_io_resource, +- .mem_resource = &ath724x_mem_resource, +-}; +- +-int __init ath724x_pcibios_init(void) +-{ +- register_pci_controller(&ath724x_pci_controller); +- +- return PCIBIOS_SUCCESSFUL; +-} diff --git a/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-replace-ath724x-to-ar724x.patch b/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-replace-ath724x-to-ar724x.patch new file mode 100644 index 000000000..0a224ed54 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-replace-ath724x-to-ar724x.patch @@ -0,0 +1,264 @@ +From 9f0c37b1d071355d4c027958f370823c8f891480 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:26 +0100 +Subject: [PATCH 10/47] MIPS: ath79: replace ath724x to ar724x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace the 'ath724x' to 'ar724x' in function, variable and +structure names to reflect the name of the real SoC. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: René Bolldorf <xsecute@googlemail.com> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3490/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 4 +- + arch/mips/ath79/pci.c | 6 ++-- + arch/mips/ath79/pci.h | 10 +++--- + arch/mips/include/asm/mach-ath79/pci.h | 4 +- + arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++---------------- + 5 files changed, 43 insertions(+), 43 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub + #ifdef CONFIG_PCI + static struct ath9k_platform_data ubnt_xm_eeprom_data; + +-static struct ath724x_pci_data ubnt_xm_pci_data[] = { ++static struct ar724x_pci_data ubnt_xm_pci_data[] = { + { + .irq = UBNT_XM_PCI_IRQ, + .pdata = &ubnt_xm_eeprom_data, +@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void) + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + +- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ++ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + #endif /* CONFIG_PCI */ + + ath79_register_pci(); +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -13,10 +13,10 @@ + #include <asm/mach-ath79/pci.h> + #include "pci.h" + +-static struct ath724x_pci_data *pci_data; ++static struct ar724x_pci_data *pci_data; + static int pci_data_size; + +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) ++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) + { + pci_data = data; + pci_data_size = size; +@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev + int __init ath79_register_pci(void) + { + if (soc_is_ar724x()) +- return ath724x_pcibios_init(); ++ return ar724x_pcibios_init(); + + return -ENODEV; + } +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -8,15 +8,15 @@ + * by the Free Software Foundation. + */ + +-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H +-#define __ASM_MACH_ATH79_PCI_ATH724X_H ++#ifndef _ATH79_PCI_H ++#define _ATH79_PCI_H + +-struct ath724x_pci_data { ++struct ar724x_pci_data { + int irq; + void *pdata; + }; + +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); ++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); + + #ifdef CONFIG_PCI + int ath79_register_pci(void); +@@ -24,4 +24,4 @@ int ath79_register_pci(void); + static inline int ath79_register_pci(void) { return 0; } + #endif + +-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ ++#endif /* _ATH79_PCI_H */ +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -12,9 +12,9 @@ + #define __ASM_MACH_ATH79_PCI_H + + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) +-int ath724x_pcibios_init(void); ++int ar724x_pcibios_init(void); + #else +-static inline int ath724x_pcibios_init(void) { return 0; } ++static inline int ar724x_pcibios_init(void) { return 0; } + #endif + + #endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -14,13 +14,13 @@ + #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) + #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) + +-#define ATH724X_PCI_DEV_BASE 0x14000000 +-#define ATH724X_PCI_MEM_BASE 0x10000000 +-#define ATH724X_PCI_MEM_SIZE 0x08000000 ++#define AR724X_PCI_DEV_BASE 0x14000000 ++#define AR724X_PCI_MEM_BASE 0x10000000 ++#define AR724X_PCI_MEM_SIZE 0x08000000 + +-static DEFINE_SPINLOCK(ath724x_pci_lock); ++static DEFINE_SPINLOCK(ar724x_pci_lock); + +-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, ++static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { + unsigned long flags, addr, tval, mask; +@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + +- spin_lock_irqsave(&ath724x_pci_lock, flags); ++ spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: + addr = where & ~3; + mask = 0xff000000 >> ((where % 4) * 8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = reg_read(AR724X_PCI_DEV_BASE + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 2: + addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = reg_read(AR724X_PCI_DEV_BASE + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 4: +- *value = reg_read(ATH724X_PCI_DEV_BASE + where); ++ *value = reg_read(AR724X_PCI_DEV_BASE + where); + break; + default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; + } + +-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, ++static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t value) + { + unsigned long flags, tval, addr, mask; +@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_ + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + +- spin_lock_irqsave(&ath724x_pci_lock, flags); ++ spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ addr = (AR724X_PCI_DEV_BASE + where) & ~3; + mask = 0xff000000 >> ((where % 4)*8); + tval = reg_read(addr); + tval = tval & ~mask; +@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_ + reg_write(addr, tval); + break; + case 2: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ addr = (AR724X_PCI_DEV_BASE + where) & ~3; + mask = 0xffff0000 >> ((where % 4)*8); + tval = reg_read(addr); + tval = tval & ~mask; +@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_ + reg_write(addr, tval); + break; + case 4: +- reg_write((ATH724X_PCI_DEV_BASE + where), value); ++ reg_write((AR724X_PCI_DEV_BASE + where), value); + break; + default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; + } + +-static struct pci_ops ath724x_pci_ops = { +- .read = ath724x_pci_read, +- .write = ath724x_pci_write, ++static struct pci_ops ar724x_pci_ops = { ++ .read = ar724x_pci_read, ++ .write = ar724x_pci_write, + }; + +-static struct resource ath724x_io_resource = { ++static struct resource ar724x_io_resource = { + .name = "PCI IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO, + }; + +-static struct resource ath724x_mem_resource = { ++static struct resource ar724x_mem_resource = { + .name = "PCI memory space", +- .start = ATH724X_PCI_MEM_BASE, +- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, ++ .start = AR724X_PCI_MEM_BASE, ++ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }; + +-static struct pci_controller ath724x_pci_controller = { +- .pci_ops = &ath724x_pci_ops, +- .io_resource = &ath724x_io_resource, +- .mem_resource = &ath724x_mem_resource, ++static struct pci_controller ar724x_pci_controller = { ++ .pci_ops = &ar724x_pci_ops, ++ .io_resource = &ar724x_io_resource, ++ .mem_resource = &ar724x_mem_resource, + }; + +-int __init ath724x_pcibios_init(void) ++int __init ar724x_pcibios_init(void) + { +- register_pci_controller(&ath724x_pci_controller); ++ register_pci_controller(&ar724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; + } diff --git a/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch b/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch new file mode 100644 index 000000000..108ac10e4 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch @@ -0,0 +1,131 @@ +From 0f5728e7e6fa7f0969ec79bd623261d3d830e5e7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:29:27 +0100 +Subject: [PATCH 11/47] MIPS: ath79: use io-accessor macros in pci-ar724x.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: René Bolldorf <xsecute@googlemail.com> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3491/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++-------------- + 1 files changed, 24 insertions(+), 14 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -11,19 +11,19 @@ + #include <linux/pci.h> + #include <asm/mach-ath79/pci.h> + +-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) +-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +- +-#define AR724X_PCI_DEV_BASE 0x14000000 ++#define AR724X_PCI_CFG_BASE 0x14000000 ++#define AR724X_PCI_CFG_SIZE 0x1000 + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + + static DEFINE_SPINLOCK(ar724x_pci_lock); ++static void __iomem *ar724x_pci_devcfg_base; + + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { + unsigned long flags, addr, tval, mask; ++ void __iomem *base; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + ++ base = ar724x_pci_devcfg_base; ++ + spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: + addr = where & ~3; + mask = 0xff000000 >> ((where % 4) * 8); +- tval = reg_read(AR724X_PCI_DEV_BASE + addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 2: + addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(AR724X_PCI_DEV_BASE + addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 4: +- *value = reg_read(AR724X_PCI_DEV_BASE + where); ++ *value = __raw_readl(base + where); + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b + int size, uint32_t value) + { + unsigned long flags, tval, addr, mask; ++ void __iomem *base; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + ++ base = ar724x_pci_devcfg_base; ++ + spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: +- addr = (AR724X_PCI_DEV_BASE + where) & ~3; ++ addr = where & ~3; + mask = 0xff000000 >> ((where % 4)*8); +- tval = reg_read(addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); ++ __raw_writel(tval, base + addr); + break; + case 2: +- addr = (AR724X_PCI_DEV_BASE + where) & ~3; ++ addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); ++ __raw_writel(tval, base + addr); + break; + case 4: +- reg_write((AR724X_PCI_DEV_BASE + where), value); ++ __raw_writel(value, (base + where)); + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_ + + int __init ar724x_pcibios_init(void) + { ++ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, ++ AR724X_PCI_CFG_SIZE); ++ if (ar724x_pci_devcfg_base == NULL) ++ return -ENOMEM; ++ + register_pci_controller(&ar724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; diff --git a/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch b/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch new file mode 100644 index 000000000..9ce1c396e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch @@ -0,0 +1,38 @@ +From e9889bee75d03338daf7ed422661ae28f3aa7063 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:03 +0100 +Subject: [PATCH 12/47] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c + +The alignment of the 'where' parameters are checked +in the core PCI code already. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3492/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/pci/pci-ar724x.c | 6 ------ + 1 files changed, 0 insertions(+), 6 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bu + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); +@@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_b + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); diff --git a/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch b/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch new file mode 100644 index 000000000..97db6de9a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch @@ -0,0 +1,134 @@ +From 39f3275077a5b143616fcb3e7a6457a5c42739ee Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:04 +0100 +Subject: [PATCH 13/47] MIPS: ath79: fix broken ar724x_pci_{read,write} functions + +The current ar724x_pci_{read,write} functions are +broken. Due to that, pci_read_config_byte returns +with bogus values, and pci_write_config_{byte,word} +unconditionally clears the accessed PCI configuration +registers instead of changing the value of them. + +The patch fixes the broken functions, thus the PCI +configuration space can be accessed correctly. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3493/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++---------------------- + 1 files changed, 26 insertions(+), 26 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { +- unsigned long flags, addr, tval, mask; ++ unsigned long flags; + void __iomem *base; ++ u32 data; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); + + switch (size) { + case 1: +- addr = where & ~3; +- mask = 0xff000000 >> ((where % 4) * 8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); ++ if (where & 1) ++ data >>= 8; ++ if (where & 2) ++ data >>= 16; ++ data &= 0xff; + break; + case 2: +- addr = where & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); ++ if (where & 2) ++ data >>= 16; ++ data &= 0xffff; + break; + case 4: +- *value = __raw_readl(base + where); + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu + } + + spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++ *value = data; + + return PCIBIOS_SUCCESSFUL; + } +@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu + static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t value) + { +- unsigned long flags, tval, addr, mask; ++ unsigned long flags; + void __iomem *base; ++ u32 data; ++ int s; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); + + switch (size) { + case 1: +- addr = where & ~3; +- mask = 0xff000000 >> ((where % 4)*8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- __raw_writel(tval, base + addr); ++ s = ((where & 3) * 8); ++ data &= ~(0xff << s); ++ data |= ((value & 0xff) << s); + break; + case 2: +- addr = where & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- __raw_writel(tval, base + addr); ++ s = ((where & 2) * 8); ++ data &= ~(0xffff << s); ++ data |= ((value & 0xffff) << s); + break; + case 4: +- __raw_writel(value, (base + where)); ++ data = value; + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b + return PCIBIOS_BAD_REGISTER_NUMBER; + } + ++ __raw_writel(data, base + (where & ~3)); ++ /* flush write */ ++ __raw_readl(base + (where & ~3)); + spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; diff --git a/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch b/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch new file mode 100644 index 000000000..8ed823b59 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch @@ -0,0 +1,134 @@ +From 14eaf9b1cda516b4182e56f61c21fa2eaa9ade6b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:05 +0100 +Subject: [PATCH 14/47] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs + +The PCI controller of the AR724X SoCs has a hardware +bag. If the BAR0 register of the PCI device is set to +the proper base address, the memory address space of +the device is not accessible. + +When the device driver tries to access the memory +address space of the PCI device, it leads to data +bus error, similiar to this: + +Data bus error, epc == 801f69a0, ra == 801f698c +Oops[#1]: +Cpu 0 +$ 0 : 00000000 00000061 deadbeef 000000ff +$ 4 : 00000000 000000ff 00000014 00000000 +$ 8 : ff000000 fffffffc 00000000 00000000 +$12 : 000001f5 00000006 00000000 6e637920 +$16 : 81ca4000 81ca0260 81ca4000 804d70f0 +$20 : fffffff4 0000002b 803ad4c4 00000000 +$24 : 00000003 00000000 +$28 : 81c20000 81c21c60 00000000 801f698c +Hi : 00000000 +Lo : 00000000 +epc : 801f69a0 ath9k_hw_init+0xd0/0xa70 + Not tainted +ra : 801f698c ath9k_hw_init+0xbc/0xa70 +Status: 1000c103 KERNEL EXL IE +Cause : 1080001c +PrId : 00019374 (MIPS 24Kc) +Modules linked in: +Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) +Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0 + 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b + 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c + 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000 + 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320 + ... +Call Trace: +[<801f69a0>] ath9k_hw_init+0xd0/0xa70 +[<801e3ae8>] ath9k_init_device+0x174/0x680 +[<801f08a4>] ath_pci_probe+0x27c/0x380 +[<8019e490>] pci_device_probe+0x74/0x9c +[<801bfadc>] driver_probe_device+0x9c/0x1b4 +[<801bfcb0>] __driver_attach+0xbc/0xc4 +[<801bea0c>] bus_for_each_dev+0x5c/0x98 +[<801bf394>] bus_add_driver+0x1d0/0x2a4 +[<801c0364>] driver_register+0x8c/0x16c +[<8019e72c>] __pci_register_driver+0x4c/0xe4 +[<803d3d40>] ath9k_init+0x3c/0x88 +[<80060930>] do_one_initcall+0x3c/0x1cc +[<803c297c>] kernel_init+0xa4/0x138 +[<80063c04>] kernel_thread_helper+0x10/0x18 + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3494/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++- + 1 files changed, 35 insertions(+), 1 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -9,6 +9,7 @@ + */ + + #include <linux/pci.h> ++#include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/pci.h> + + #define AR724X_PCI_CFG_BASE 0x14000000 +@@ -16,9 +17,14 @@ + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + ++#define AR7240_BAR0_WAR_VALUE 0xffff ++ + static DEFINE_SPINLOCK(ar724x_pci_lock); + static void __iomem *ar724x_pci_devcfg_base; + ++static u32 ar724x_pci_bar0_value; ++static bool ar724x_pci_bar0_is_cached; ++ + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { +@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu + } + + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +- *value = data; ++ ++ if (where == PCI_BASE_ADDRESS_0 && size == 4 && ++ ar724x_pci_bar0_is_cached) { ++ /* use the cached value */ ++ *value = ar724x_pci_bar0_value; ++ } else { ++ *value = data; ++ } + + return PCIBIOS_SUCCESSFUL; + } +@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + ++ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) { ++ if (value != 0xffffffff) { ++ /* ++ * WAR for a hw issue. If the BAR0 register of the ++ * device is set to the proper base address, the ++ * memory space of the device is not accessible. ++ * ++ * Cache the intended value so it can be read back, ++ * and write a SoC specific constant value to the ++ * BAR0 register in order to make the device memory ++ * accessible. ++ */ ++ ar724x_pci_bar0_is_cached = true; ++ ar724x_pci_bar0_value = value; ++ ++ value = AR7240_BAR0_WAR_VALUE; ++ } else { ++ ar724x_pci_bar0_is_cached = false; ++ } ++ } ++ + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); diff --git a/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch b/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch new file mode 100644 index 000000000..8702e65fc --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch @@ -0,0 +1,73 @@ +From d710990df726cceffb62488e597ecfc4a9e13aa5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:06 +0100 +Subject: [PATCH 15/47] MIPS: ath79: fix a wrong IRQ number + +The Ubiquiti XM board setup code uses an invalid +IRQ number, because it if above of NR_IRQS. This +leads to failed 'request_irq' calls: + + ath9k 0000:00:00.0: request_irq failed + ath9k: probe of 0000:00:00.0 failed with error -22 + +Preserve some IRQ numbers for the built-in IRQ +controller of PCI host controllers in the +AR71XX/AR724X SoCs, and use the correct IRQ +number in the board setup code. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3495/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 5 +++-- + arch/mips/include/asm/mach-ath79/irq.h | 6 +++++- + 2 files changed, 8 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -17,6 +17,8 @@ + #include <linux/ath9k_platform.h> + #endif /* CONFIG_PCI */ + ++#include <asm/mach-ath79/irq.h> ++ + #include "machtypes.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +@@ -33,7 +35,6 @@ + #define UBNT_XM_KEYS_POLL_INTERVAL 20 + #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +-#define UBNT_XM_PCI_IRQ 48 + #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { +@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x + + static struct ar724x_pci_data ubnt_xm_pci_data[] = { + { +- .irq = UBNT_XM_PCI_IRQ, ++ .irq = ATH79_PCI_IRQ(0), + .pdata = &ubnt_xm_eeprom_data, + }, + }; +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,11 +10,15 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 40 ++#define NR_IRQS 46 + + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 + ++#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) ++#define ATH79_PCI_IRQ_COUNT 6 ++#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) ++ + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) + #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) + #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) diff --git a/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch b/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch new file mode 100644 index 000000000..0c15a5496 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch @@ -0,0 +1,213 @@ +From 1fd24b552708544ca6233ff7ba60342e9f7e5582 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:07 +0100 +Subject: [PATCH 16/47] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs + +The PCI Host Controller of the AR724x SoC has a +built-in IRQ controller. The current code does +not supports that, so the IRQ lines wired to this +controller are not usable. This leads to failed +'request_irq' calls: + + ath9k 0000:00:00.0: request_irq failed + ath9k: probe of 0000:00:00.0 failed with error -89 + +This patch adds support for the IRQ controller +in order to make PCI IRQs work. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3496/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/pci.c | 3 +- + arch/mips/include/asm/mach-ath79/pci.h | 4 +- + arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++- + 3 files changed, 120 insertions(+), 5 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -10,6 +10,7 @@ + + #include <linux/pci.h> + #include <asm/mach-ath79/ath79.h> ++#include <asm/mach-ath79/irq.h> + #include <asm/mach-ath79/pci.h> + #include "pci.h" + +@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev + int __init ath79_register_pci(void) + { + if (soc_is_ar724x()) +- return ar724x_pcibios_init(); ++ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + + return -ENODEV; + } +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -12,9 +12,9 @@ + #define __ASM_MACH_ATH79_PCI_H + + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) +-int ar724x_pcibios_init(void); ++int ar724x_pcibios_init(int irq); + #else +-static inline int ar724x_pcibios_init(void) { return 0; } ++static inline int ar724x_pcibios_init(int irq) { return 0; } + #endif + + #endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -8,19 +8,32 @@ + * by the Free Software Foundation. + */ + ++#include <linux/irq.h> + #include <linux/pci.h> + #include <asm/mach-ath79/ath79.h> ++#include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/pci.h> + + #define AR724X_PCI_CFG_BASE 0x14000000 + #define AR724X_PCI_CFG_SIZE 0x1000 ++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) ++#define AR724X_PCI_CTRL_SIZE 0x100 ++ + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + ++#define AR724X_PCI_REG_INT_STATUS 0x4c ++#define AR724X_PCI_REG_INT_MASK 0x50 ++ ++#define AR724X_PCI_INT_DEV0 BIT(14) ++ ++#define AR724X_PCI_IRQ_COUNT 1 ++ + #define AR7240_BAR0_WAR_VALUE 0xffff + + static DEFINE_SPINLOCK(ar724x_pci_lock); + static void __iomem *ar724x_pci_devcfg_base; ++static void __iomem *ar724x_pci_ctrl_base; + + static u32 ar724x_pci_bar0_value; + static bool ar724x_pci_bar0_is_cached; +@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_ + .mem_resource = &ar724x_mem_resource, + }; + +-int __init ar724x_pcibios_init(void) ++static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base; ++ u32 pending; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ ++ if (pending & AR724X_PCI_INT_DEV0) ++ generic_handle_irq(ATH79_PCI_IRQ(0)); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar724x_pci_irq_unmask(struct irq_data *d) ++{ ++ void __iomem *base; ++ u32 t; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ switch (d->irq) { ++ case ATH79_PCI_IRQ(0): ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ /* flush write */ ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ } ++} ++ ++static void ar724x_pci_irq_mask(struct irq_data *d) ++{ ++ void __iomem *base; ++ u32 t; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ switch (d->irq) { ++ case ATH79_PCI_IRQ(0): ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t & ~AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ ++ /* flush write */ ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ ++ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_STATUS); ++ ++ /* flush write */ ++ __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ } ++} ++ ++static struct irq_chip ar724x_pci_irq_chip = { ++ .name = "AR724X PCI ", ++ .irq_mask = ar724x_pci_irq_mask, ++ .irq_unmask = ar724x_pci_irq_unmask, ++ .irq_mask_ack = ar724x_pci_irq_mask, ++}; ++ ++static void __init ar724x_pci_irq_init(int irq) ++{ ++ void __iomem *base; ++ int i; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); ++ ++ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); ++ ++ for (i = ATH79_PCI_IRQ_BASE; ++ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(irq, ar724x_pci_irq_handler); ++} ++ ++int __init ar724x_pcibios_init(int irq) + { ++ int ret; ++ ++ ret = -ENOMEM; ++ + ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, + AR724X_PCI_CFG_SIZE); + if (ar724x_pci_devcfg_base == NULL) +- return -ENOMEM; ++ goto err; + ++ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_CTRL_SIZE); ++ if (ar724x_pci_ctrl_base == NULL) ++ goto err_unmap_devcfg; ++ ++ ar724x_pci_irq_init(irq); + register_pci_controller(&ar724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; ++ ++err_unmap_devcfg: ++ iounmap(ar724x_pci_devcfg_base); ++err: ++ return ret; + } diff --git a/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch b/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch new file mode 100644 index 000000000..4ef080541 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch @@ -0,0 +1,64 @@ +From b2ab491ed634a4c0b7af5f11940e0ca42b1a87c8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:08 +0100 +Subject: [PATCH 17/47] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c + +Remove a superfluous ifdef around an include. Also +reorganize the board setup code a bit, so another +ifdef can be removed. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3497/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++----------- + 1 files changed, 12 insertions(+), 11 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -12,10 +12,7 @@ + + #include <linux/init.h> + #include <linux/pci.h> +- +-#ifdef CONFIG_PCI + #include <linux/ath9k_platform.h> +-#endif /* CONFIG_PCI */ + + #include <asm/mach-ath79/irq.h> + +@@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pc + .pdata = &ubnt_xm_eeprom_data, + }, + }; ++ ++static void __init ubnt_xm_pci_init(void) ++{ ++ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, ++ sizeof(ubnt_xm_eeprom_data.eeprom_data)); ++ ++ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ++ ath79_register_pci(); ++} ++#else ++static inline void ubnt_xm_pci_init(void) {} + #endif /* CONFIG_PCI */ + + static void __init ubnt_xm_init(void) +@@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void) + ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, + ARRAY_SIZE(ubnt_xm_spi_info)); + +-#ifdef CONFIG_PCI +- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, +- sizeof(ubnt_xm_eeprom_data.eeprom_data)); +- +- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); +-#endif /* CONFIG_PCI */ +- +- ath79_register_pci(); ++ ubnt_xm_pci_init(); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch b/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch new file mode 100644 index 000000000..38765b0a9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch @@ -0,0 +1,141 @@ +From 2b62c9d685d9bb048a006b695683b2a812c0a847 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:09 +0100 +Subject: [PATCH 18/47] MIPS: ath79: allow to use board specific pci_plat_dev_init functions + +Th current implementation causes NULL pointer dereference +if 'pci_data' is not set: + +pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit] +pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI +address [0x10000000-0x1000ffff]) +CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4 +Oops[#1]: +Cpu 0 +$ 0 : 00000000 80420000 00000000 00000000 +$ 4 : 00000000 00000000 00000001 00000001 +$ 8 : 00000001 0000032c 81c54700 00000001 +$12 : 0000032d 0000000f 00000000 ffffffff +$16 : 81c14c00 00000001 802dac74 80195f98 +$20 : 802ea050 00000000 00000000 00000000 +$24 : 00000003 800617f0 +$28 : 81c20000 81c21e70 00000000 802e78a4 +Hi : 00000000 +Lo : 4190ab00 +epc : 802daca0 0x802daca0 + Not tainted +ra : 802e78a4 0x802e78a4 +Status: 1000c003 KERNEL EXL IE +Cause : 00800008 +BadVA : 00000000 +PrId : 00019374 (MIPS 24Kc) +Modules linked in: +Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) +Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000 + 802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290 + 80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000 + 00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000 + 00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000 + +This can be avoided by calling the 'ar724x_pci_add_data' +function from the board specific setup code. However it +makes no sense to use that function for every board, +especially when the board does not needs to set the +platform_data field of any PCI device. + +The patch allows the board setup code to specify a board +specific function if that is required. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3499/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++- + arch/mips/ath79/pci.c | 14 ++++++++------ + arch/mips/ath79/pci.h | 4 +++- + 3 files changed, 23 insertions(+), 8 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_x + static struct ar724x_pci_data ubnt_xm_pci_data[] = { + { + .irq = ATH79_PCI_IRQ(0), +- .pdata = &ubnt_xm_eeprom_data, + }, + }; + ++static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &ubnt_xm_eeprom_data; ++ break; ++ } ++ ++ return 0; ++} ++ + static void __init ubnt_xm_pci_init(void) + { + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + + ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ++ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); + ath79_register_pci(); + } + #else +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -14,6 +14,7 @@ + #include <asm/mach-ath79/pci.h> + #include "pci.h" + ++static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); + static struct ar724x_pci_data *pci_data; + static int pci_data_size; + +@@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct + + int pcibios_plat_dev_init(struct pci_dev *dev) + { +- unsigned int devfn = dev->devfn; +- +- if (devfn > pci_data_size - 1) +- return PCIBIOS_DEVICE_NOT_FOUND; ++ if (ath79_pci_plat_dev_init) ++ return ath79_pci_plat_dev_init(dev); + +- dev->dev.platform_data = pci_data[devfn].pdata; ++ return 0; ++} + +- return PCIBIOS_SUCCESSFUL; ++void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) ++{ ++ ath79_pci_plat_dev_init = func; + } + + int __init ath79_register_pci(void) +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -13,14 +13,16 @@ + + struct ar724x_pci_data { + int irq; +- void *pdata; + }; + + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); + + #ifdef CONFIG_PCI ++void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); + int ath79_register_pci(void); + #else ++static inline void ++ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} + static inline int ath79_register_pci(void) { return 0; } + #endif + diff --git a/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch b/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch new file mode 100644 index 000000000..4021af2ca --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch @@ -0,0 +1,436 @@ +From 4201b6aeb059b481571c241a2fc96fd3f41032e9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:10 +0100 +Subject: [PATCH 19/47] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs + +The Atheros AR71XX SoCs have a built-in PCI Host Controller. +This patch adds a driver for that, and modifies the relevant +files in order to allow to register the PCI controller from +board specific setup. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Signed-off-by: Imre Kaloz <kaloz@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3498/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Kconfig | 1 + + arch/mips/include/asm/mach-ath79/pci.h | 6 + + arch/mips/pci/Makefile | 1 + + arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++ + 4 files changed, 383 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/pci/pci-ar71xx.c + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -52,6 +52,7 @@ endmenu + config SOC_AR71XX + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI ++ select HW_HAS_PCI + def_bool n + + config SOC_AR724X +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -11,6 +11,12 @@ + #ifndef __ASM_MACH_ATH79_PCI_H + #define __ASM_MACH_ATH79_PCI_H + ++#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) ++int ar71xx_pcibios_init(void); ++#else ++static inline int ar71xx_pcibios_init(void) { return 0; } ++#endif ++ + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) + int ar724x_pcibios_init(int irq); + #else +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o ++obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o + obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o + + # +--- /dev/null ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -0,0 +1,375 @@ ++/* ++ * Atheros AR71xx PCI host controller driver ++ * ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include <linux/resource.h> ++#include <linux/types.h> ++#include <linux/delay.h> ++#include <linux/bitops.h> ++#include <linux/pci.h> ++#include <linux/pci_regs.h> ++#include <linux/interrupt.h> ++ ++#include <asm/mach-ath79/ar71xx_regs.h> ++#include <asm/mach-ath79/ath79.h> ++#include <asm/mach-ath79/pci.h> ++ ++#define AR71XX_PCI_MEM_BASE 0x10000000 ++#define AR71XX_PCI_MEM_SIZE 0x08000000 ++ ++#define AR71XX_PCI_WIN0_OFFS 0x10000000 ++#define AR71XX_PCI_WIN1_OFFS 0x11000000 ++#define AR71XX_PCI_WIN2_OFFS 0x12000000 ++#define AR71XX_PCI_WIN3_OFFS 0x13000000 ++#define AR71XX_PCI_WIN4_OFFS 0x14000000 ++#define AR71XX_PCI_WIN5_OFFS 0x15000000 ++#define AR71XX_PCI_WIN6_OFFS 0x16000000 ++#define AR71XX_PCI_WIN7_OFFS 0x07000000 ++ ++#define AR71XX_PCI_CFG_BASE \ ++ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) ++#define AR71XX_PCI_CFG_SIZE 0x100 ++ ++#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 ++#define AR71XX_PCI_REG_CRP_WRDATA 0x04 ++#define AR71XX_PCI_REG_CRP_RDDATA 0x08 ++#define AR71XX_PCI_REG_CFG_AD 0x0c ++#define AR71XX_PCI_REG_CFG_CBE 0x10 ++#define AR71XX_PCI_REG_CFG_WRDATA 0x14 ++#define AR71XX_PCI_REG_CFG_RDDATA 0x18 ++#define AR71XX_PCI_REG_PCI_ERR 0x1c ++#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20 ++#define AR71XX_PCI_REG_AHB_ERR 0x24 ++#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28 ++ ++#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000 ++#define AR71XX_PCI_CRP_CMD_READ 0x00000000 ++#define AR71XX_PCI_CFG_CMD_READ 0x0000000a ++#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b ++ ++#define AR71XX_PCI_INT_CORE BIT(4) ++#define AR71XX_PCI_INT_DEV2 BIT(2) ++#define AR71XX_PCI_INT_DEV1 BIT(1) ++#define AR71XX_PCI_INT_DEV0 BIT(0) ++ ++#define AR71XX_PCI_IRQ_COUNT 5 ++ ++static DEFINE_SPINLOCK(ar71xx_pci_lock); ++static void __iomem *ar71xx_pcicfg_base; ++ ++/* Byte lane enable bits */ ++static const u8 ar71xx_pci_ble_table[4][4] = { ++ {0x0, 0xf, 0xf, 0xf}, ++ {0xe, 0xd, 0xb, 0x7}, ++ {0xc, 0xf, 0x3, 0xf}, ++ {0xf, 0xf, 0xf, 0xf}, ++}; ++ ++static const u32 ar71xx_pci_read_mask[8] = { ++ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 ++}; ++ ++static inline u32 ar71xx_pci_get_ble(int where, int size, int local) ++{ ++ u32 t; ++ ++ t = ar71xx_pci_ble_table[size & 3][where & 3]; ++ BUG_ON(t == 0xf); ++ t <<= (local) ? 20 : 4; ++ ++ return t; ++} ++ ++static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ u32 ret; ++ ++ if (!bus->number) { ++ /* type 0 */ ++ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | ++ (where & ~3); ++ } else { ++ /* type 1 */ ++ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) | ++ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; ++ } ++ ++ return ret; ++} ++ ++static int ar71xx_pci_check_error(int quiet) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 pci_err; ++ u32 ahb_err; ++ ++ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; ++ if (pci_err) { ++ if (!quiet) { ++ u32 addr; ++ ++ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); ++ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", ++ "PCI", pci_err, addr); ++ } ++ ++ /* clear PCI error status */ ++ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); ++ } ++ ++ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; ++ if (ahb_err) { ++ if (!quiet) { ++ u32 addr; ++ ++ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); ++ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", ++ "AHB", ahb_err, addr); ++ } ++ ++ /* clear AHB error status */ ++ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); ++ } ++ ++ return !!(ahb_err | pci_err); ++} ++ ++static inline void ar71xx_pci_local_write(int where, int size, u32 value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 ad_cbe; ++ ++ value = value << (8 * (where & 3)); ++ ++ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3); ++ ad_cbe |= ar71xx_pci_get_ble(where, size, 1); ++ ++ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); ++ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); ++} ++ ++static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, ++ unsigned int devfn, ++ int where, int size, u32 cmd) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 addr; ++ ++ addr = ar71xx_pci_bus_addr(bus, devfn, where); ++ ++ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); ++ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), ++ base + AR71XX_PCI_REG_CFG_CBE); ++ ++ return ar71xx_pci_check_error(1); ++} ++ ++static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ unsigned long flags; ++ u32 data; ++ int err; ++ int ret; ++ ++ ret = PCIBIOS_SUCCESSFUL; ++ data = ~0; ++ ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ AR71XX_PCI_CFG_CMD_READ); ++ if (err) ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ else ++ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); ++ ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ++ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; ++ ++ return ret; ++} ++ ++static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ unsigned long flags; ++ int err; ++ int ret; ++ ++ value = value << (8 * (where & 3)); ++ ret = PCIBIOS_SUCCESSFUL; ++ ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ AR71XX_PCI_CFG_CMD_WRITE); ++ if (err) ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ else ++ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); ++ ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ++ return ret; ++} ++ ++static struct pci_ops ar71xx_pci_ops = { ++ .read = ar71xx_pci_read_config, ++ .write = ar71xx_pci_write_config, ++}; ++ ++static struct resource ar71xx_pci_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ar71xx_pci_mem_resource = { ++ .name = "PCI memory space", ++ .start = AR71XX_PCI_MEM_BASE, ++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct pci_controller ar71xx_pci_controller = { ++ .pci_ops = &ar71xx_pci_ops, ++ .mem_resource = &ar71xx_pci_mem_resource, ++ .io_resource = &ar71xx_pci_io_resource, ++}; ++ ++static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base = ath79_reset_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ if (pending & AR71XX_PCI_INT_DEV0) ++ generic_handle_irq(ATH79_PCI_IRQ(0)); ++ ++ else if (pending & AR71XX_PCI_INT_DEV1) ++ generic_handle_irq(ATH79_PCI_IRQ(1)); ++ ++ else if (pending & AR71XX_PCI_INT_DEV2) ++ generic_handle_irq(ATH79_PCI_IRQ(2)); ++ ++ else if (pending & AR71XX_PCI_INT_CORE) ++ generic_handle_irq(ATH79_PCI_IRQ(4)); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar71xx_pci_irq_unmask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; ++ void __iomem *base = ath79_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ /* flush write */ ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} ++ ++static void ar71xx_pci_irq_mask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; ++ void __iomem *base = ath79_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ /* flush write */ ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} ++ ++static struct irq_chip ar71xx_pci_irq_chip = { ++ .name = "AR71XX PCI", ++ .irq_mask = ar71xx_pci_irq_mask, ++ .irq_unmask = ar71xx_pci_irq_unmask, ++ .irq_mask_ack = ar71xx_pci_irq_mask, ++}; ++ ++static __init void ar71xx_pci_irq_init(void) ++{ ++ void __iomem *base = ath79_reset_base; ++ int i; ++ ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); ++ ++ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); ++ ++ for (i = ATH79_PCI_IRQ_BASE; ++ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); ++} ++ ++static __init void ar71xx_pci_reset(void) ++{ ++ void __iomem *ddr_base = ath79_ddr_base; ++ ++ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); ++ mdelay(100); ++ ++ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); ++ mdelay(100); ++ ++ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); ++ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); ++ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); ++ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); ++ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); ++ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); ++ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); ++ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); ++ ++ mdelay(100); ++} ++ ++__init int ar71xx_pcibios_init(void) ++{ ++ u32 t; ++ ++ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); ++ if (ar71xx_pcicfg_base == NULL) ++ return -ENOMEM; ++ ++ ar71xx_pci_reset(); ++ ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE ++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ++ ar71xx_pci_local_write(PCI_COMMAND, 4, t); ++ ++ /* clear bus errors */ ++ ar71xx_pci_check_error(1); ++ ++ ar71xx_pci_irq_init(); ++ ++ register_pci_controller(&ar71xx_pci_controller); ++ ++ return 0; ++} diff --git a/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch b/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch new file mode 100644 index 000000000..7daaf1923 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch @@ -0,0 +1,165 @@ +From fd1dd2f2c317bc0fc2c30fba440d911654bf592e Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:11 +0100 +Subject: [PATCH 20/47] MIPS: ath79: allow to use SoC specific PCI IRQ maps + +The PCI controllers in the AR71XX and in the +AR724X SoCs are different, and both of them +uses different IRQ wiring. + +The patch modifies the 'pcibios_map_irq' function +in order to allow to use different IRQ maps for +the different SoCs. The patch also adds a function, +which lets the board setup code to override the +default IRQ map. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3500/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++--- + arch/mips/ath79/pci.h | 9 ++++++ + 2 files changed, 77 insertions(+), 4 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -8,6 +8,7 @@ + * by the Free Software Foundation. + */ + ++#include <linux/init.h> + #include <linux/pci.h> + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/irq.h> +@@ -15,9 +16,35 @@ + #include "pci.h" + + static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); ++static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; ++static unsigned ath79_pci_nr_irqs __initdata; + static struct ar724x_pci_data *pci_data; + static int pci_data_size; + ++static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { ++ { ++ .slot = 17, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, { ++ .slot = 18, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(1), ++ }, { ++ .slot = 19, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(2), ++ } ++}; ++ ++static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ } ++}; ++ + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) + { + pci_data = data; +@@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p + + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { +- unsigned int devfn = dev->devfn; + int irq = -1; ++ int i; + +- if (devfn > pci_data_size - 1) +- return irq; +- +- irq = pci_data[devfn].irq; ++ if (ath79_pci_nr_irqs == 0 || ++ ath79_pci_irq_map == NULL) { ++ if (soc_is_ar71xx()) { ++ ath79_pci_irq_map = ar71xx_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); ++ } else if (soc_is_ar724x()) { ++ ath79_pci_irq_map = ar724x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); ++ } else { ++ pr_crit("pci %s: invalid irq map\n", ++ pci_name((struct pci_dev *) dev)); ++ return irq; ++ } ++ } ++ ++ for (i = 0; i < ath79_pci_nr_irqs; i++) { ++ const struct ath79_pci_irq *entry; ++ ++ entry = &ath79_pci_irq_map[i]; ++ if (entry->slot == slot && entry->pin == pin) { ++ irq = entry->irq; ++ break; ++ } ++ } ++ ++ if (irq < 0) ++ pr_crit("pci %s: no irq found for pin %u\n", ++ pci_name((struct pci_dev *) dev), pin); ++ else ++ pr_info("pci %s: using irq %d for pin %u\n", ++ pci_name((struct pci_dev *) dev), irq, pin); + + return irq; + } +@@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev + return 0; + } + ++void __init ath79_pci_set_irq_map(unsigned nr_irqs, ++ const struct ath79_pci_irq *map) ++{ ++ ath79_pci_nr_irqs = nr_irqs; ++ ath79_pci_irq_map = map; ++} ++ + void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) + { + ath79_pci_plat_dev_init = func; +@@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init( + + int __init ath79_register_pci(void) + { ++ if (soc_is_ar71xx()) ++ return ar71xx_pcibios_init(); ++ + if (soc_is_ar724x()) + return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -15,13 +15,22 @@ struct ar724x_pci_data { + int irq; + }; + ++struct ath79_pci_irq { ++ u8 slot; ++ u8 pin; ++ int irq; ++}; ++ + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); + + #ifdef CONFIG_PCI ++void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); + void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); + int ath79_register_pci(void); + #else + static inline void ++ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} ++static inline void + ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} + static inline int ath79_register_pci(void) { return 0; } + #endif diff --git a/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-remove-ar724x_pci_add_data-function.patch b/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-remove-ar724x_pci_add_data-function.patch new file mode 100644 index 000000000..70013c8d9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-remove-ar724x_pci_add_data-function.patch @@ -0,0 +1,86 @@ +From 29398cf1212afc9a6474127259cbb3a48d0751e5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:12 +0100 +Subject: [PATCH 21/47] MIPS: ath79: remove ar724x_pci_add_data function + +The variables set by this function are not used anymore. +Remove the function and the relevant variables as well. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3501/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-ubnt-xm.c | 7 ------- + arch/mips/ath79/pci.c | 8 -------- + arch/mips/ath79/pci.h | 6 ------ + 3 files changed, 0 insertions(+), 21 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ub + #ifdef CONFIG_PCI + static struct ath9k_platform_data ubnt_xm_eeprom_data; + +-static struct ar724x_pci_data ubnt_xm_pci_data[] = { +- { +- .irq = ATH79_PCI_IRQ(0), +- }, +-}; +- + static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) + { + switch (PCI_SLOT(dev->devfn)) { +@@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + +- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); + ath79_register_pci(); + } +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -18,8 +18,6 @@ + static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); + static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; + static unsigned ath79_pci_nr_irqs __initdata; +-static struct ar724x_pci_data *pci_data; +-static int pci_data_size; + + static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { + { +@@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x + } + }; + +-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) +-{ +- pci_data = data; +- pci_data_size = size; +-} +- + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { + int irq = -1; +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -11,18 +11,12 @@ + #ifndef _ATH79_PCI_H + #define _ATH79_PCI_H + +-struct ar724x_pci_data { +- int irq; +-}; +- + struct ath79_pci_irq { + u8 slot; + u8 pin; + int irq; + }; + +-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); +- + #ifdef CONFIG_PCI + void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); + void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); diff --git a/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch b/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch new file mode 100644 index 000000000..969b79d8b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch @@ -0,0 +1,34 @@ +From 12db6a98b438a50799873bfd2b736a3b02a4bd57 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:13 +0100 +Subject: [PATCH 22/47] MIPS: ath79: register PCI controller on the PB44 board + +The PB44 reference board has two miniPCI slots. Register +the PCI controller to make those usable. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3502/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/mach-pb44.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -19,6 +19,7 @@ + #include "dev-leds-gpio.h" + #include "dev-spi.h" + #include "dev-usb.h" ++#include "pci.h" + + #define PB44_GPIO_I2C_SCL 0 + #define PB44_GPIO_I2C_SDA 1 +@@ -114,6 +115,7 @@ static void __init pb44_init(void) + ath79_register_spi(&pb44_spi_data, pb44_spi_info, + ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); ++ ath79_register_pci(); + } + + MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch b/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch new file mode 100644 index 000000000..da173a5f1 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch @@ -0,0 +1,71 @@ +From d3b5329b89d1bc733c56e4d609a89b429bf6cd4e Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:36:14 +0100 +Subject: [PATCH 23/47] MIPS: ath79: update copyright headers of PCI related files + +Add copyright records according to the recent changes in +the PCI code. Also fix up the descriptions. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Signed-off-by: Imre Kaloz <kaloz@openwrt.org> +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3503/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/pci.c | 4 ++++ + arch/mips/ath79/pci.h | 4 +++- + arch/mips/include/asm/mach-ath79/pci.h | 4 +++- + arch/mips/pci/pci-ar724x.c | 3 ++- + 4 files changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -2,6 +2,10 @@ + * Atheros AR71XX/AR724X specific PCI setup code + * + * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -1,7 +1,9 @@ + /* +- * Atheros 724x PCI support ++ * Atheros AR71XX/AR724X PCI support + * + * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -1,7 +1,9 @@ + /* +- * Atheros 724x PCI support ++ * Atheros AR71XX/AR724X PCI support + * + * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -1,7 +1,8 @@ + /* +- * Atheros 724x PCI support ++ * Atheros AR724X PCI host controller driver + * + * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> ++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published diff --git a/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-add-early_printk-support-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-add-early_printk-support-for-AR934X.patch new file mode 100644 index 000000000..512f2da10 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-add-early_printk-support-for-AR934X.patch @@ -0,0 +1,56 @@ +From 5c1f1041309ede56d48eb3c665025e87c9824a64 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:19 +0100 +Subject: [PATCH 24/47] MIPS: ath79: add early_printk support for AR934X + +The patch allows to see kernel messages on AR934X SoCs in +early boot stage. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3504/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/early_printk.c | 3 +++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++- + 2 files changed, 8 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -71,6 +71,9 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR7241: + case REV_ID_MAJOR_AR7242: + case REV_ID_MAJOR_AR913X: ++ case REV_ID_MAJOR_AR9341: ++ case REV_ID_MAJOR_AR9342: ++ case REV_ID_MAJOR_AR9344: + _prom_putchar = prom_putchar_ar71xx; + break; + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1,10 +1,11 @@ + /* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * +- * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +@@ -249,6 +250,9 @@ + #define REV_ID_MAJOR_AR7242 0x1100 + #define REV_ID_MAJOR_AR9330 0x0110 + #define REV_ID_MAJOR_AR9331 0x1110 ++#define REV_ID_MAJOR_AR9341 0x0120 ++#define REV_ID_MAJOR_AR9342 0x1120 ++#define REV_ID_MAJOR_AR9344 0x2120 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 + #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch b/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch new file mode 100644 index 000000000..afbb04e4f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch @@ -0,0 +1,58 @@ +From ccb089bbbe49949063cc348743605b3d813ca1c0 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:20 +0100 +Subject: [PATCH 25/47] MIPS: ath79: sort case statements in ath79_detect_sys_type + +Sort the case statements alphabetically in order to improve +readability. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3505/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/setup.c | 24 ++++++++++++------------ + 1 files changed, 12 insertions(+), 12 deletions(-) + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + +- case REV_ID_MAJOR_AR9330: +- ath79_soc = ATH79_SOC_AR9330; +- chip = "9330"; +- rev = id & AR933X_REV_ID_REVISION_MASK; +- break; +- +- case REV_ID_MAJOR_AR9331: +- ath79_soc = ATH79_SOC_AR9331; +- chip = "9331"; +- rev = id & AR933X_REV_ID_REVISION_MASK; +- break; +- + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; +@@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type + } + break; + ++ case REV_ID_MAJOR_AR9330: ++ ath79_soc = ATH79_SOC_AR9330; ++ chip = "9330"; ++ rev = id & AR933X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9331: ++ ath79_soc = ATH79_SOC_AR9331; ++ chip = "9331"; ++ rev = id & AR933X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } diff --git a/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch new file mode 100644 index 000000000..59bb3d8c5 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch @@ -0,0 +1,124 @@ +From bf5cb424312f28e51803286a53cb8613bedc5bc8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:21 +0100 +Subject: [PATCH 26/47] MIPS: ath79: add SoC detection code for AR934X + +Also add 'soc_is_ar934[124x]' helper functions and a Kconfig +symbol for the AR934X SoCs. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3506/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/ath79/setup.c | 21 ++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++ + 4 files changed, 49 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -69,6 +69,10 @@ config SOC_AR933X + select USB_ARCH_HAS_EHCI + def_bool n + ++config SOC_AR934X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config ATH79_DEV_GPIO_BUTTONS + def_bool n + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -1,10 +1,11 @@ + /* + * Atheros AR71XX/AR724X/AR913X specific setup + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * +- * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_AR9341: ++ ath79_soc = ATH79_SOC_AR9341; ++ chip = "9341"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9342: ++ ath79_soc = ATH79_SOC_AR9342; ++ chip = "9342"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9344: ++ ath79_soc = ATH79_SOC_AR9344; ++ chip = "9344"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -271,6 +271,8 @@ + + #define AR724X_REV_ID_REVISION_MASK 0x3 + ++#define AR934X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -29,6 +29,9 @@ enum ath79_soc_type { + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, ++ ATH79_SOC_AR9341, ++ ATH79_SOC_AR9342, ++ ATH79_SOC_AR9344, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void) + ath79_soc == ATH79_SOC_AR9331); + } + ++static inline int soc_is_ar9341(void) ++{ ++ return (ath79_soc == ATH79_SOC_AR9341); ++} ++ ++static inline int soc_is_ar9342(void) ++{ ++ return (ath79_soc == ATH79_SOC_AR9342); ++} ++ ++static inline int soc_is_ar9344(void) ++{ ++ return (ath79_soc == ATH79_SOC_AR9344); ++} ++ ++static inline int soc_is_ar934x(void) ++{ ++ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; diff --git a/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch new file mode 100644 index 000000000..39e161cc2 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch @@ -0,0 +1,198 @@ +From e9706fc0a97feb7992a98806b69a1fc1fcb910c7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:22 +0100 +Subject: [PATCH 27/47] MIPS: ath79: add clock initialization code for AR934X + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3507/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++ + 2 files changed, 134 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -1,8 +1,11 @@ + /* + * Atheros AR71XX/AR724X/AR913X common routines + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo + ath79_uart_clk.rate = ath79_ref_clk.rate; + } + ++static void __init ar934x_clocks_init(void) ++{ ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) ++ ath79_ref_clk.rate = 40 * 1000 * 1000; ++ else ++ ath79_ref_clk.rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ath79_ref_clk.rate / ref_div; ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ath79_ref_clk.rate / ref_div; ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) ++ ath79_cpu_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); ++ else ++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) ++ ath79_ddr_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) ++ ath79_ahb_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); ++ ++ ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_uart_clk.rate = ath79_ref_clk.rate; ++} ++ + void __init ath79_clocks_init(void) + { + if (soc_is_ar71xx()) +@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void) + ar913x_clocks_init(); + else if (soc_is_ar933x()) + ar933x_clocks_init(); ++ else if (soc_is_ar934x()) ++ ar934x_clocks_init(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -151,6 +151,41 @@ + #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 + #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + ++#define AR934X_PLL_CPU_CONFIG_REG 0x00 ++#define AR934X_PLL_DDR_CONFIG_REG 0x04 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 ++ ++#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 ++ ++#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + /* + * USB_CONFIG block + */ +@@ -186,6 +221,8 @@ + #define AR933X_RESET_REG_RESET_MODULE 0x1c + #define AR933X_RESET_REG_BOOTSTRAP 0xac + ++#define AR934X_RESET_REG_BOOTSTRAP 0xb0 ++ + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) + #define MISC_INT_TIMER3 BIT(9) +@@ -242,6 +279,22 @@ + + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + ++#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) ++#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) ++#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) ++#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) ++#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) ++#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) ++#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) ++#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) ++#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) ++#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) ++#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) ++#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) ++#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) ++#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) ++#define AR934X_BOOTSTRAP_DDR1 BIT(0) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch new file mode 100644 index 000000000..77c8d5a57 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch @@ -0,0 +1,102 @@ +From 77bb01d1919bcb6787d5cde9056936420288ab34 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:23 +0100 +Subject: [PATCH 28/47] MIPS: ath79: add GPIO support code for AR934X + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3508/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 47 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -1,9 +1,12 @@ + /* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * +- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s + return 0; + } + ++static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ ++static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ++ int value) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ if (value) ++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); ++ else ++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ + static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, +@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR913X_GPIO_COUNT; + else if (soc_is_ar933x()) + ath79_gpio_count = AR933X_GPIO_COUNT; ++ else if (soc_is_ar934x()) ++ ath79_gpio_count = AR934X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; ++ if (soc_is_ar934x()) { ++ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; ++ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; ++ } + + err = gpiochip_add(&ath79_gpio_chip); + if (err) +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -367,5 +367,6 @@ + #define AR724X_GPIO_COUNT 18 + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 ++#define AR934X_GPIO_COUNT 23 + + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch b/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch new file mode 100644 index 000000000..0f30d3836 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch @@ -0,0 +1,158 @@ +From f44c70eb5368c0742a8f401ccf39f2ba7252f5a7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:24 +0100 +Subject: [PATCH 29/47] MIPS: ath79: rework IP2/IP3 interrupt handling + +The current implementation assumes that flushing the +DDR writeback buffer is required for IP2/IP3 interrupts, +however this is not true for all SoCs. + +Use SoC specific IP2/IP3 handlers instead of flushing +the buffers in the dispatcher code. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3509/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++----------- + 1 files changed, 72 insertions(+), 20 deletions(-) + +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -1,7 +1,7 @@ + /* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * +- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Atheros' 2.6.15 BSP +@@ -23,8 +23,8 @@ + #include <asm/mach-ath79/ar71xx_regs.h> + #include "common.h" + +-static unsigned int ath79_ip2_flush_reg; +-static unsigned int ath79_ip3_flush_reg; ++static void (*ath79_ip2_handler)(void); ++static void (*ath79_ip3_handler)(void); + + static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) + { +@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void) + if (pending & STATUSF_IP7) + do_IRQ(ATH79_CPU_IRQ_TIMER); + +- else if (pending & STATUSF_IP2) { +- ath79_ddr_wb_flush(ath79_ip2_flush_reg); +- do_IRQ(ATH79_CPU_IRQ_IP2); +- } ++ else if (pending & STATUSF_IP2) ++ ath79_ip2_handler(); + + else if (pending & STATUSF_IP4) + do_IRQ(ATH79_CPU_IRQ_GE0); +@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void) + else if (pending & STATUSF_IP5) + do_IRQ(ATH79_CPU_IRQ_GE1); + +- else if (pending & STATUSF_IP3) { +- ath79_ddr_wb_flush(ath79_ip3_flush_reg); +- do_IRQ(ATH79_CPU_IRQ_USB); +- } ++ else if (pending & STATUSF_IP3) ++ ath79_ip3_handler(); + + else if (pending & STATUSF_IP6) + do_IRQ(ATH79_CPU_IRQ_MISC); +@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void) + spurious_interrupt(); + } + ++/* ++ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for ++ * these devices typically allocate coherent DMA memory, however the ++ * DMA controller may still have some unsynchronized data in the FIFO. ++ * Issue a flush in the handlers to ensure that the driver sees ++ * the update. ++ */ ++static void ar71xx_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar724x_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar913x_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar933x_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar71xx_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ ++static void ar724x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ ++static void ar913x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ ++static void ar933x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ + void __init arch_init_irq(void) + { + if (soc_is_ar71xx()) { +- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; +- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; ++ ath79_ip2_handler = ar71xx_ip2_handler; ++ ath79_ip3_handler = ar71xx_ip3_handler; + } else if (soc_is_ar724x()) { +- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; +- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; ++ ath79_ip2_handler = ar724x_ip2_handler; ++ ath79_ip3_handler = ar724x_ip3_handler; + } else if (soc_is_ar913x()) { +- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; +- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; ++ ath79_ip2_handler = ar913x_ip2_handler; ++ ath79_ip3_handler = ar913x_ip3_handler; + } else if (soc_is_ar933x()) { +- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; +- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; +- } else ++ ath79_ip2_handler = ar933x_ip2_handler; ++ ath79_ip3_handler = ar933x_ip3_handler; ++ } else { + BUG(); ++ } + + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); diff --git a/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch new file mode 100644 index 000000000..126807725 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch @@ -0,0 +1,194 @@ +From b16fdecf14d24fe213c81409c0c2dca66d5b7bc9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:25 +0100 +Subject: [PATCH 30/47] MIPS: ath79: add IRQ handling code for AR934X + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3510/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++ + arch/mips/include/asm/mach-ath79/irq.h | 6 ++- + 3 files changed, 83 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -1,10 +1,11 @@ + /* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * +- * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; +- else if (soc_is_ar724x() || soc_is_ar933x()) ++ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else + BUG(); +@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v + irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); + } + ++static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); ++ ++ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { ++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE); ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { ++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC); ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } else { ++ spurious_interrupt(); ++ } ++ ++ enable_irq(irq); ++} ++ ++static void ar934x_ip2_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); ++} ++ + asmlinkage void plat_irq_dispatch(void) + { + unsigned long pending; +@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void) + do_IRQ(ATH79_CPU_IRQ_IP2); + } + ++static void ar934x_ip2_handler(void) ++{ ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ + static void ar71xx_ip3_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); +@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void) + do_IRQ(ATH79_CPU_IRQ_USB); + } + ++static void ar934x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ + void __init arch_init_irq(void) + { + if (soc_is_ar71xx()) { +@@ -240,6 +285,9 @@ void __init arch_init_irq(void) + } else if (soc_is_ar933x()) { + ath79_ip2_handler = ar933x_ip2_handler; + ath79_ip3_handler = ar933x_ip3_handler; ++ } else if (soc_is_ar934x()) { ++ ath79_ip2_handler = ar934x_ip2_handler; ++ ath79_ip3_handler = ar934x_ip3_handler; + } else { + BUG(); + } +@@ -247,4 +295,7 @@ void __init arch_init_irq(void) + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); + ath79_misc_irq_init(); ++ ++ if (soc_is_ar934x()) ++ ar934x_ip2_irq_init(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -92,6 +92,12 @@ + #define AR933X_DDR_REG_FLUSH_USB 0x84 + #define AR933X_DDR_REG_FLUSH_WMAC 0x88 + ++#define AR934X_DDR_REG_FLUSH_GE0 0x9c ++#define AR934X_DDR_REG_FLUSH_GE1 0xa0 ++#define AR934X_DDR_REG_FLUSH_USB 0xa4 ++#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 ++#define AR934X_DDR_REG_FLUSH_WMAC 0xac ++ + /* + * PLL block + */ +@@ -222,6 +228,7 @@ + #define AR933X_RESET_REG_BOOTSTRAP 0xac + + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 ++#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) +@@ -295,6 +302,24 @@ + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) ++#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) ++#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) ++#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) ++#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ ++ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ ++ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) ++ ++#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ ++ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ ++ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ ++ AR934X_PCIE_WMAC_INT_PCIE_RC3) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,7 +10,7 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 46 ++#define NR_IRQS 48 + + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 +@@ -19,6 +19,10 @@ + #define ATH79_PCI_IRQ_COUNT 6 + #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) + ++#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT) ++#define ATH79_IP2_IRQ_COUNT 2 ++#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) ++ + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) + #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) + #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) diff --git a/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch b/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch new file mode 100644 index 000000000..14d4a27d1 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch @@ -0,0 +1,60 @@ +From 98bfbb0b3f126d93076377fcd9553a493e45e304 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:26 +0100 +Subject: [PATCH 31/47] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set} + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3511/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/common.c | 9 ++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 9 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -1,9 +1,12 @@ + /* + * Atheros AR71XX/AR724X/AR913X common routines + * +- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> ++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; + else + BUG(); + +@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -227,6 +227,7 @@ + #define AR933X_RESET_REG_RESET_MODULE 0x1c + #define AR933X_RESET_REG_BOOTSTRAP 0xac + ++#define AR934X_RESET_REG_RESET_MODULE 0x1c + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + diff --git a/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch b/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch new file mode 100644 index 000000000..2c7eecabf --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch @@ -0,0 +1,27 @@ +From 2d4ed1c7405d05da812b67830eaac15f43b862b7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:27 +0100 +Subject: [PATCH 32/47] MIPS: ath79: register UART device for AR934X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3512/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/dev-common.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -89,7 +89,8 @@ void __init ath79_register_uart(void) + + if (soc_is_ar71xx() || + soc_is_ar724x() || +- soc_is_ar913x()) { ++ soc_is_ar913x() || ++ soc_is_ar934x()) { + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { diff --git a/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch new file mode 100644 index 000000000..adbe3e4bb --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch @@ -0,0 +1,116 @@ +From d677877e2688813e5e0c12d0228a631021ed70c4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:28 +0100 +Subject: [PATCH 33/47] MIPS: ath79: add WMAC registration code for AR934X + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3513/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Kconfig | 2 +- + arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++ + 3 files changed, 32 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -86,7 +86,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) + def_bool n + + endif +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -1,9 +1,12 @@ + /* + * Atheros AR913X/AR933X SoC built-in WMAC device support + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * ++ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resour + /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_MEM, + }, { +- .start = ATH79_CPU_IRQ_IP2, +- .end = ATH79_CPU_IRQ_IP2, ++ /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_IRQ, + }, + }; +@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(voi + + ath79_wmac_resources[0].start = AR913X_WMAC_BASE; + ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; + } + + +@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(voi + + ath79_wmac_resources[0].start = AR933X_WMAC_BASE; + ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (t & AR933X_BOOTSTRAP_REF_CLK_40) +@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(voi + ath79_wmac_data.external_reset = ar933x_wmac_reset; + } + ++static void ar934x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "ar934x_wmac"; ++ ++ ath79_wmac_resources[0].start = AR934X_WMAC_BASE; ++ ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (t & AR934X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data) + { + if (soc_is_ar913x()) + ar913x_wmac_setup(); + else if (soc_is_ar933x()) + ar933x_wmac_setup(); ++ else if (soc_is_ar934x()) ++ ar934x_wmac_setup(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -61,6 +61,9 @@ + #define AR933X_EHCI_BASE 0x1b000000 + #define AR933X_EHCI_SIZE 0x1000 + ++#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define AR934X_WMAC_SIZE 0x20000 ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch b/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch new file mode 100644 index 000000000..27a46e638 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch @@ -0,0 +1,66 @@ +From 27a5b2948831f4fd8e66e2e1a98b4c23902728cc Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:29 +0100 +Subject: [PATCH 34/47] MIPS: ath79: add PCI_AR724X Kconfig symbol + +The AR724X specific PCI code can be used for the +AR934X SoCs, however it can be selected only if +SOC_AR724X is set. + +Introduce a new Kconfig symbol in order to be able +to use the code for AR934X as well. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3514/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/include/asm/mach-ath79/pci.h | 2 +- + arch/mips/pci/Makefile | 2 +- + 3 files changed, 6 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -59,6 +59,7 @@ config SOC_AR724X + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + select HW_HAS_PCI ++ select PCI_AR724X if PCI + def_bool n + + config SOC_AR913X +@@ -73,6 +74,9 @@ config SOC_AR934X + select USB_ARCH_HAS_EHCI + def_bool n + ++config PCI_AR724X ++ def_bool n ++ + config ATH79_DEV_GPIO_BUTTONS + def_bool n + +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void); + static inline int ar71xx_pcibios_init(void) { return 0; } + #endif + +-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) ++#if defined(CONFIG_PCI_AR724X) + int ar724x_pcibios_init(int irq); + #else + static inline int ar724x_pcibios_init(int irq) { return 0; } +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o + obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o +-obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o ++obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o + + # + # These are still pretty much in the old state, watch, go blind. diff --git a/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch new file mode 100644 index 000000000..bd9386d8c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch @@ -0,0 +1,62 @@ +From 902b348cdddd4c858993e02aced615aa6caf04d0 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 10:45:30 +0100 +Subject: [PATCH 35/47] MIPS: ath79: add PCI registration code for AR934X + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3516/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Kconfig | 2 ++ + arch/mips/ath79/pci.c | 13 ++++++++++++- + 2 files changed, 14 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -72,6 +72,8 @@ config SOC_AR933X + + config SOC_AR934X + select USB_ARCH_HAS_EHCI ++ select HW_HAS_PCI ++ select PCI_AR724X if PCI + def_bool n + + config PCI_AR724X +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -14,6 +14,7 @@ + + #include <linux/init.h> + #include <linux/pci.h> ++#include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/irq.h> + #include <asm/mach-ath79/pci.h> +@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct + if (soc_is_ar71xx()) { + ath79_pci_irq_map = ar71xx_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); +- } else if (soc_is_ar724x()) { ++ } else if (soc_is_ar724x() || ++ soc_is_ar9342() || ++ soc_is_ar9344()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); + } else { +@@ -115,5 +118,13 @@ int __init ath79_register_pci(void) + if (soc_is_ar724x()) + return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + ++ if (soc_is_ar9342() || soc_is_ar9344()) { ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) ++ return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); ++ } ++ + return -ENODEV; + } diff --git a/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch b/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch new file mode 100644 index 000000000..30c2c1b18 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch @@ -0,0 +1,196 @@ +From 4921cb7d9f6997b6f7aefd37c7cfd50324e8fd75 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Mar 2012 20:39:35 +0100 +Subject: [PATCH 36/47] MIPS: ath79: add initial support for the Atheros DB120 board + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3517/ +Signed-off-by: Ralf Baechle <ralf@linux-mips.org> +--- + arch/mips/ath79/Kconfig | 12 ++++ + arch/mips/ath79/Makefile | 1 + + arch/mips/ath79/mach-db120.c | 134 ++++++++++++++++++++++++++++++++++++++++++ + arch/mips/ath79/machtypes.h | 1 + + 4 files changed, 148 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/ath79/mach-db120.c + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -26,6 +26,18 @@ config ATH79_MACH_AP81 + Say 'Y' here if you want your kernel to support the + Atheros AP81 reference board. + ++config ATH79_MACH_DB120 ++ bool "Atheros DB120 reference board" ++ select SOC_AR934X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros DB120 reference board. ++ + config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o + obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o +--- /dev/null ++++ b/arch/mips/ath79/mach-db120.c +@@ -0,0 +1,134 @@ ++/* ++ * Atheros DB120 reference board support ++ * ++ * Copyright (c) 2011 Qualcomm Atheros ++ * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ * ++ */ ++ ++#include <linux/pci.h> ++#include <linux/ath9k_platform.h> ++ ++#include "machtypes.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-spi.h" ++#include "dev-wmac.h" ++#include "pci.h" ++ ++#define DB120_GPIO_LED_WLAN_5G 12 ++#define DB120_GPIO_LED_WLAN_2G 13 ++#define DB120_GPIO_LED_STATUS 14 ++#define DB120_GPIO_LED_WPS 15 ++ ++#define DB120_GPIO_BTN_WPS 16 ++ ++#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) ++ ++#define DB120_WMAC_CALDATA_OFFSET 0x1000 ++#define DB120_PCIE_CALDATA_OFFSET 0x5000 ++ ++static struct gpio_led db120_leds_gpio[] __initdata = { ++ { ++ .name = "db120:green:status", ++ .gpio = DB120_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, ++ { ++ .name = "db120:green:wps", ++ .gpio = DB120_GPIO_LED_WPS, ++ .active_low = 1, ++ }, ++ { ++ .name = "db120:green:wlan-5g", ++ .gpio = DB120_GPIO_LED_WLAN_5G, ++ .active_low = 1, ++ }, ++ { ++ .name = "db120:green:wlan-2g", ++ .gpio = DB120_GPIO_LED_WLAN_2G, ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_keys_button db120_gpio_keys[] __initdata = { ++ { ++ .desc = "WPS button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DB120_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, ++}; ++ ++static struct spi_board_info db120_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "s25sl064a", ++ } ++}; ++ ++static struct ath79_spi_platform_data db120_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 1, ++}; ++ ++#ifdef CONFIG_PCI ++static struct ath9k_platform_data db120_ath9k_data; ++ ++static int db120_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &db120_ath9k_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++static void __init db120_pci_init(u8 *eeprom) ++{ ++ memcpy(db120_ath9k_data.eeprom_data, eeprom, ++ sizeof(db120_ath9k_data.eeprom_data)); ++ ++ ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); ++ ath79_register_pci(); ++} ++#else ++static inline void db120_pci_init(void) {} ++#endif /* CONFIG_PCI */ ++ ++static void __init db120_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), ++ db120_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(db120_gpio_keys), ++ db120_gpio_keys); ++ ath79_register_spi(&db120_spi_data, db120_spi_info, ++ ARRAY_SIZE(db120_spi_info)); ++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); ++ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); ++} ++ ++MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", ++ db120_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -18,6 +18,7 @@ enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ++ ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ + }; diff --git a/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-use-correct-IRQ-number-for-the-OHCI-contr.patch b/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-use-correct-IRQ-number-for-the-OHCI-contr.patch new file mode 100644 index 000000000..07ddb512d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-use-correct-IRQ-number-for-the-OHCI-contr.patch @@ -0,0 +1,37 @@ +From fe0cc1327ddfb69b171102019a8148a9c8b352b8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 28 Mar 2012 11:00:19 +0200 +Subject: [PATCH 37/47] MIPS: ath79: use correct IRQ number for the OHCI controller on AR7240 + +The currently assigned IRQ number to the OHCI +controller is incorrect for the AR7240 SoC, and +that leads to the following error message from +the OHCI driver: + +ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +ath79-ohci ath79-ohci: Atheros built-in OHCI controller +ath79-ohci ath79-ohci: new USB bus registered, assigned bus number 1 +ath79-ohci ath79-ohci: irq 14, io mem 0x1b000000 +hub 1-0:1.0: USB hub found +hub 1-0:1.0: 1 port detected +usb 1-1: new full-speed USB device number 2 using ath79-ohci +ath79-ohci ath79-ohci: Unlink after no-IRQ? Controller is probably using the wrong IRQ. + +Fix this by using the correct IRQ number. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/dev-usb.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -145,6 +145,8 @@ static void __init ar7240_usb_setup(void + + ath79_ohci_resources[0].start = AR7240_OHCI_BASE; + ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; ++ ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; ++ ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; + platform_device_register(&ath79_ohci_device); + } + diff --git a/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-use-a-helper-function-for-USB-resource-in.patch b/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-use-a-helper-function-for-USB-resource-in.patch new file mode 100644 index 000000000..0def09f13 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-use-a-helper-function-for-USB-resource-in.patch @@ -0,0 +1,140 @@ +From 30b15d9a4b05e38ae19e340b63e1a2bca917d557 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 28 Mar 2012 14:15:23 +0200 +Subject: [PATCH 38/47] MIPS: ath79: use a helper function for USB resource initialization + +This improves code readability, and ensures that +all resource fields will be initialized correctly. +Additionally, it helps to reduce the size of the +kernel image by using uninitialized resource +variables. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/dev-usb.c | 64 +++++++++++++++++++------------------------- + 1 files changed, 28 insertions(+), 36 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -25,17 +25,7 @@ + #include "common.h" + #include "dev-usb.h" + +-static struct resource ath79_ohci_resources[] = { +- [0] = { +- /* .start and .end fields are filled dynamically */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = ATH79_MISC_IRQ_OHCI, +- .end = ATH79_MISC_IRQ_OHCI, +- .flags = IORESOURCE_IRQ, +- }, +-}; ++static struct resource ath79_ohci_resources[2]; + + static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); + +@@ -54,17 +44,7 @@ static struct platform_device ath79_ohci + }, + }; + +-static struct resource ath79_ehci_resources[] = { +- [0] = { +- /* .start and .end fields are filled dynamically */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = ATH79_CPU_IRQ_USB, +- .end = ATH79_CPU_IRQ_USB, +- .flags = IORESOURCE_IRQ, +- }, +-}; ++static struct resource ath79_ehci_resources[2]; + + static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); + +@@ -90,6 +70,20 @@ static struct platform_device ath79_ehci + }, + }; + ++static void __init ath79_usb_init_resource(struct resource res[2], ++ unsigned long base, ++ unsigned long size, ++ int irq) ++{ ++ res[0].flags = IORESOURCE_MEM; ++ res[0].start = base; ++ res[0].end = base + size - 1; ++ ++ res[1].flags = IORESOURCE_IRQ; ++ res[1].start = irq; ++ res[1].end = irq; ++} ++ + #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ + AR71XX_RESET_USB_PHY | \ + AR71XX_RESET_USB_OHCI_DLL) +@@ -114,12 +108,12 @@ static void __init ath79_usb_setup(void) + + mdelay(900); + +- ath79_ohci_resources[0].start = AR71XX_OHCI_BASE; +- ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, ++ AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); + platform_device_register(&ath79_ohci_device); + +- ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; +- ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, ++ AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; + platform_device_register(&ath79_ehci_device); + } +@@ -143,10 +137,8 @@ static void __init ar7240_usb_setup(void + + iounmap(usb_ctrl_base); + +- ath79_ohci_resources[0].start = AR7240_OHCI_BASE; +- ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; +- ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; +- ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; ++ ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, ++ AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); + platform_device_register(&ath79_ohci_device); + } + +@@ -161,8 +153,8 @@ static void __init ar724x_usb_setup(void + ath79_device_reset_clear(AR724X_RESET_USB_PHY); + mdelay(10); + +- ath79_ehci_resources[0].start = AR724X_EHCI_BASE; +- ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, ++ AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -178,8 +170,8 @@ static void __init ar913x_usb_setup(void + ath79_device_reset_clear(AR913X_RESET_USB_PHY); + mdelay(10); + +- ath79_ehci_resources[0].start = AR913X_EHCI_BASE; +- ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, ++ AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -195,8 +187,8 @@ static void __init ar933x_usb_setup(void + ath79_device_reset_clear(AR933X_RESET_USB_PHY); + mdelay(10); + +- ath79_ehci_resources[0].start = AR933X_EHCI_BASE; +- ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, ++ AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } diff --git a/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch new file mode 100644 index 000000000..c77de2803 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch @@ -0,0 +1,78 @@ +From 635d5a2ac8aa483c3a0635c60bff8ea8978ff6a7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 11 Dec 2011 18:34:13 +0100 +Subject: [PATCH 39/47] MIPS: ath79: add USB platform setup code for AR934X + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/dev-usb.c | 28 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 ++++++ + 2 files changed, 35 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -193,6 +193,32 @@ static void __init ar933x_usb_setup(void + platform_device_register(&ath79_ehci_device); + } + ++static void __init ar934x_usb_setup(void) ++{ ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) ++ return; ++ ++ ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); ++ udelay(1000); ++ ++ ath79_device_reset_clear(AR934X_RESET_USB_PHY); ++ udelay(1000); ++ ++ ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); ++ udelay(1000); ++ ++ ath79_device_reset_clear(AR934X_RESET_USB_HOST); ++ udelay(1000); ++ ++ ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, ++ AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; ++ platform_device_register(&ath79_ehci_device); ++} ++ + void __init ath79_register_usb(void) + { + if (soc_is_ar71xx()) +@@ -205,6 +231,8 @@ void __init ath79_register_usb(void) + ar913x_usb_setup(); + else if (soc_is_ar933x()) + ar933x_usb_setup(); ++ else if (soc_is_ar934x()) ++ ar934x_usb_setup(); + else + BUG(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -63,6 +63,8 @@ + + #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR934X_WMAC_SIZE 0x20000 ++#define AR934X_EHCI_BASE 0x1b000000 ++#define AR934X_EHCI_SIZE 0x200 + + /* + * DDR_CTRL block +@@ -288,6 +290,11 @@ + #define AR933X_RESET_USB_PHY BIT(4) + #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + ++#define AR934X_RESET_USB_PHY_ANALOG BIT(11) ++#define AR934X_RESET_USB_HOST BIT(5) ++#define AR934X_RESET_USB_PHY BIT(4) ++#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) ++ + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + + #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) diff --git a/target/linux/ar71xx/patches-3.3/135-MIPS-ath79-register-USB-host-controller-on-the-DB120.patch b/target/linux/ar71xx/patches-3.3/135-MIPS-ath79-register-USB-host-controller-on-the-DB120.patch new file mode 100644 index 000000000..e82da3daa --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/135-MIPS-ath79-register-USB-host-controller-on-the-DB120.patch @@ -0,0 +1,28 @@ +From 932c1688e960bff170f1fc8072b3d3e958407a60 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Tue, 13 Mar 2012 13:51:09 +0100 +Subject: [PATCH 40/47] MIPS: ath79: register USB host controller on the DB120 board + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/mach-db120.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -25,6 +25,7 @@ + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" ++#include "dev-usb.h" + #include "dev-wmac.h" + #include "pci.h" + +@@ -126,6 +127,7 @@ static void __init db120_setup(void) + db120_gpio_keys); + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); ++ ath79_register_usb(); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); + } diff --git a/target/linux/ar71xx/patches-3.3/136-MIPS-ath79-use-correct-fractional-dividers-for-CPU-D.patch b/target/linux/ar71xx/patches-3.3/136-MIPS-ath79-use-correct-fractional-dividers-for-CPU-D.patch new file mode 100644 index 000000000..cb6aa3221 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/136-MIPS-ath79-use-correct-fractional-dividers-for-CPU-D.patch @@ -0,0 +1,49 @@ +From 7328ff547389ee0b455cbf98bdfc819731d9f7b9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Fri, 31 Aug 2012 14:22:35 +0200 +Subject: [PATCH] MIPS: ath79: use correct fractional dividers for + {CPU,DDR}_PLL on AR934x + +The current dividers in the code are wrong and this +leads to broken CPU frequency calculation on boards +where the fractional part is used. + +For example, if the SoC is running from a 40MHz +reference clock, refdiv=1, nint=14, outdiv=0 and +nfrac=31 the real frequency is 579.375MHz but the +current code calculates 569.687MHz instead. + +Because the system time is indirectly related to +the CPU frequency the broken computation causes +drift in the system time. + +The correct divider is 2^6 for the CPU PLL and 2^10 +for the DDR PLL. Use the correct values to fix the +issue. + +Cc: <stable@vger.kernel.org> [3.5+] +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/clock.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(vo + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ath79_ref_clk.rate / ref_div; +- cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); + cpu_pll /= (1 << out_div); + + pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); +@@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(vo + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ath79_ref_clk.rate / ref_div; +- ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); + ddr_pll /= (1 << out_div); + + clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); diff --git a/target/linux/ar71xx/patches-3.3/137-MIPS-ath79-fix-CPU-DDR-frequency-calculation-for-SRI.patch b/target/linux/ar71xx/patches-3.3/137-MIPS-ath79-fix-CPU-DDR-frequency-calculation-for-SRI.patch new file mode 100644 index 000000000..a2fa4db56 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/137-MIPS-ath79-fix-CPU-DDR-frequency-calculation-for-SRI.patch @@ -0,0 +1,205 @@ +From 3f735e202d5099a5b7c621443bea365b87b0e3bb Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sat, 8 Sep 2012 12:12:50 +0200 +Subject: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs + +Besides the CPU and DDR PLLs, the CPU and DDR frequencies +can be derived from other PLLs in the SRIF block on the +AR934x SoCs. The current code does not checks if the SRIF +PLLs are used and this can lead to incorrectly calculated +CPU/DDR frequencies. + +Fix it by calculating the frequencies from SRIF PLLs if +those are used on a given board. + +Cc: <stable@vger.kernel.org> +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- +This depends on the following patch: +'MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x' +https://patchwork.linux-mips.org/patch/4305/ + + arch/mips/ath79/clock.c | 109 ++++++++++++++++++------ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 23 +++++ + 2 files changed, 104 insertions(+), 28 deletions(-) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -17,6 +17,8 @@ + #include <linux/err.h> + #include <linux/clk.h> + ++#include <asm/div64.h> ++ + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/ar71xx_regs.h> + #include "common.h" +@@ -166,11 +168,34 @@ static void __init ar933x_clocks_init(vo + ath79_uart_clk.rate = ath79_ref_clk.rate; + } + ++static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, ++ u32 frac, u32 out_div) ++{ ++ u64 t; ++ u32 ret; ++ ++ t = ath79_ref_clk.rate; ++ t *= nint; ++ do_div(t, ref_div); ++ ret = t; ++ ++ t = ath79_ref_clk.rate; ++ t *= nfrac; ++ do_div(t, ref_div * frac); ++ ret += t; ++ ++ ret /= (1 << out_div); ++ return ret; ++} ++ + static void __init ar934x_clocks_init(void) + { +- u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; + u32 cpu_pll, ddr_pll; + u32 bootstrap; ++ void __iomem *dpll_base; ++ ++ dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) +@@ -178,33 +203,59 @@ static void __init ar934x_clocks_init(vo + else + ath79_ref_clk.rate = 25 * 1000 * 1000; + +- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); +- out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & +- AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; +- ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & +- AR934X_PLL_CPU_CONFIG_REFDIV_MASK; +- nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & +- AR934X_PLL_CPU_CONFIG_NINT_MASK; +- frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & +- AR934X_PLL_CPU_CONFIG_NFRAC_MASK; +- +- cpu_pll = nint * ath79_ref_clk.rate / ref_div; +- cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); +- cpu_pll /= (1 << out_div); +- +- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); +- out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & +- AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; +- ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & +- AR934X_PLL_DDR_CONFIG_REFDIV_MASK; +- nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & +- AR934X_PLL_DDR_CONFIG_NINT_MASK; +- frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & +- AR934X_PLL_DDR_CONFIG_NFRAC_MASK; +- +- ddr_pll = nint * ath79_ref_clk.rate / ref_div; +- ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); +- ddr_pll /= (1 << out_div); ++ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); ++ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { ++ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & ++ AR934X_SRIF_DPLL2_OUTDIV_MASK; ++ pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); ++ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & ++ AR934X_SRIF_DPLL1_NINT_MASK; ++ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; ++ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & ++ AR934X_SRIF_DPLL1_REFDIV_MASK; ++ frac = 1 << 18; ++ } else { ++ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NINT_MASK; ++ nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NFRAC_MASK; ++ frac = 1 << 6; ++ } ++ ++ cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, ++ nfrac, frac, out_div); ++ ++ pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); ++ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { ++ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & ++ AR934X_SRIF_DPLL2_OUTDIV_MASK; ++ pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); ++ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & ++ AR934X_SRIF_DPLL1_NINT_MASK; ++ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; ++ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & ++ AR934X_SRIF_DPLL1_REFDIV_MASK; ++ frac = 1 << 18; ++ } else { ++ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NINT_MASK; ++ nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ++ frac = 1 << 10; ++ } ++ ++ ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, ++ nfrac, frac, out_div); + + clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + +@@ -240,6 +291,8 @@ static void __init ar934x_clocks_init(vo + + ath79_wdt_clk.rate = ath79_ref_clk.rate; + ath79_uart_clk.rate = ath79_ref_clk.rate; ++ ++ iounmap(dpll_base); + } + + void __init ath79_clocks_init(void) +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -65,6 +65,8 @@ + #define AR934X_WMAC_SIZE 0x20000 + #define AR934X_EHCI_BASE 0x1b000000 + #define AR934X_EHCI_SIZE 0x200 ++#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) ++#define AR934X_SRIF_SIZE 0x1000 + + /* + * DDR_CTRL block +@@ -405,4 +407,25 @@ + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 + ++/* ++ * SRIF block ++ */ ++#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 ++#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 ++#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 ++ ++#define AR934X_SRIF_DDR_DPLL1_REG 0x240 ++#define AR934X_SRIF_DDR_DPLL2_REG 0x244 ++#define AR934X_SRIF_DDR_DPLL3_REG 0x248 ++ ++#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 ++#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f ++#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 ++#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff ++#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff ++ ++#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) ++#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 ++#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 ++ + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-3.3/140-MIPS-pci-ar724x-avoid-data-bus-error-due-to-a-missin.patch b/target/linux/ar71xx/patches-3.3/140-MIPS-pci-ar724x-avoid-data-bus-error-due-to-a-missin.patch new file mode 100644 index 000000000..a05b1e7a9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/140-MIPS-pci-ar724x-avoid-data-bus-error-due-to-a-missin.patch @@ -0,0 +1,78 @@ +From 9cfa64ddaba49975b420ce5e5020efc3301061ac Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Tue, 26 Jun 2012 10:19:46 +0200 +Subject: [PATCH 01/34] MIPS: pci-ar724x: avoid data bus error due to a missing PCIe module + +If the controller has no PCIe module attached, +accessing of the device configuration space +causes a data bus error. Avoid this by checking +the status of the PCIe link in advance, and +indicate an error if the link is down. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar724x.c | 22 ++++++++++++++++++++++ + 1 files changed, 22 insertions(+), 0 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -23,9 +23,12 @@ + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + ++#define AR724X_PCI_REG_RESET 0x18 + #define AR724X_PCI_REG_INT_STATUS 0x4c + #define AR724X_PCI_REG_INT_MASK 0x50 + ++#define AR724X_PCI_RESET_LINK_UP BIT(0) ++ + #define AR724X_PCI_INT_DEV0 BIT(14) + + #define AR724X_PCI_IRQ_COUNT 1 +@@ -38,6 +41,15 @@ static void __iomem *ar724x_pci_ctrl_bas + + static u32 ar724x_pci_bar0_value; + static bool ar724x_pci_bar0_is_cached; ++static bool ar724x_pci_link_up; ++ ++static inline bool ar724x_pci_check_link(void) ++{ ++ u32 reset; ++ ++ reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); ++ return reset & AR724X_PCI_RESET_LINK_UP; ++} + + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) +@@ -46,6 +58,9 @@ static int ar724x_pci_read(struct pci_bu + void __iomem *base; + u32 data; + ++ if (!ar724x_pci_link_up) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +@@ -96,6 +111,9 @@ static int ar724x_pci_write(struct pci_b + u32 data; + int s; + ++ if (!ar724x_pci_link_up) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +@@ -280,6 +298,10 @@ int __init ar724x_pcibios_init(int irq) + if (ar724x_pci_ctrl_base == NULL) + goto err_unmap_devcfg; + ++ ar724x_pci_link_up = ar724x_pci_check_link(); ++ if (!ar724x_pci_link_up) ++ pr_warn("ar724x: PCIe link is down\n"); ++ + ar724x_pci_irq_init(irq); + register_pci_controller(&ar724x_pci_controller); + diff --git a/target/linux/ar71xx/patches-3.3/141-MIPS-pci-ar724x-use-correct-value-for-AR724X_PCI_MEM.patch b/target/linux/ar71xx/patches-3.3/141-MIPS-pci-ar724x-use-correct-value-for-AR724X_PCI_MEM.patch new file mode 100644 index 000000000..d409a7a6a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/141-MIPS-pci-ar724x-use-correct-value-for-AR724X_PCI_MEM.patch @@ -0,0 +1,24 @@ +From 4b0f8aaea1f9e2f931c4de785d9ce46ff7164627 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 17 Jun 2012 12:55:24 +0200 +Subject: [PATCH 02/34] MIPS: pci-ar724x: use correct value for AR724X_PCI_MEM_SIZE + +The current definiton is wrong, it is conflicting +with AR724X_PCI_CFG_BASE. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar724x.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -21,7 +21,7 @@ + #define AR724X_PCI_CTRL_SIZE 0x100 + + #define AR724X_PCI_MEM_BASE 0x10000000 +-#define AR724X_PCI_MEM_SIZE 0x08000000 ++#define AR724X_PCI_MEM_SIZE 0x04000000 + + #define AR724X_PCI_REG_RESET 0x18 + #define AR724X_PCI_REG_INT_STATUS 0x4c diff --git a/target/linux/ar71xx/patches-3.3/142-MIPS-pci-ar71xx-fix-AR71XX_PCI_MEM_SIZE.patch b/target/linux/ar71xx/patches-3.3/142-MIPS-pci-ar71xx-fix-AR71XX_PCI_MEM_SIZE.patch new file mode 100644 index 000000000..7fb56f831 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/142-MIPS-pci-ar71xx-fix-AR71XX_PCI_MEM_SIZE.patch @@ -0,0 +1,21 @@ +From 01dbfe17b8ff628b6e2b3c75e1fc8c11d4cca644 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Thu, 28 Jun 2012 19:19:58 +0200 +Subject: [PATCH 03/34] MIPS: pci-ar71xx: fix AR71XX_PCI_MEM_SIZE + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar71xx.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -24,7 +24,7 @@ + #include <asm/mach-ath79/pci.h> + + #define AR71XX_PCI_MEM_BASE 0x10000000 +-#define AR71XX_PCI_MEM_SIZE 0x08000000 ++#define AR71XX_PCI_MEM_SIZE 0x07000000 + + #define AR71XX_PCI_WIN0_OFFS 0x10000000 + #define AR71XX_PCI_WIN1_OFFS 0x11000000 diff --git a/target/linux/ar71xx/patches-3.3/143-MIPS-pci-ar724x-convert-to-a-platform-driver.patch b/target/linux/ar71xx/patches-3.3/143-MIPS-pci-ar724x-convert-to-a-platform-driver.patch new file mode 100644 index 000000000..fd9868963 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/143-MIPS-pci-ar724x-convert-to-a-platform-driver.patch @@ -0,0 +1,94 @@ +From f2d2d928c3900b67a5f95e53b86de5b61a3ab12c Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 11 Jun 2012 13:19:44 +0200 +Subject: [PATCH 04/34] MIPS: pci-ar724x: convert to a platform driver + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar724x.c | 57 ++++++++++++++++++++++++++++++++++++++++++- + 1 files changed, 55 insertions(+), 2 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -11,6 +11,8 @@ + + #include <linux/irq.h> + #include <linux/pci.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/pci.h> +@@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_ch + .irq_mask_ack = ar724x_pci_irq_mask, + }; + +-static void __init ar724x_pci_irq_init(int irq) ++static void __devinit ar724x_pci_irq_init(int irq) + { + void __iomem *base; + int i; +@@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(i + irq_set_chained_handler(irq, ar724x_pci_irq_handler); + } + +-int __init ar724x_pcibios_init(int irq) ++int __devinit ar724x_pcibios_init(int irq) + { + int ret; + +@@ -312,3 +314,54 @@ err_unmap_devcfg: + err: + return ret; + } ++ ++static int __devinit ar724x_pci_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ int irq; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); ++ if (!res) ++ return -EINVAL; ++ ++ ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (ar724x_pci_ctrl_base == NULL) ++ return -EBUSY; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); ++ if (!res) ++ return -EINVAL; ++ ++ ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (!ar724x_pci_devcfg_base) ++ return -EBUSY; ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return -EINVAL; ++ ++ ar724x_pci_link_up = ar724x_pci_check_link(); ++ if (!ar724x_pci_link_up) ++ dev_warn(&pdev->dev, "PCIe link is down\n"); ++ ++ ar724x_pci_irq_init(irq); ++ ++ register_pci_controller(&ar724x_pci_controller); ++ ++ return 0; ++} ++ ++static struct platform_driver ar724x_pci_driver = { ++ .probe = ar724x_pci_probe, ++ .driver = { ++ .name = "ar724x-pci", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar724x_pci_init(void) ++{ ++ return platform_driver_register(&ar724x_pci_driver); ++} ++ ++postcore_initcall(ar724x_pci_init); diff --git a/target/linux/ar71xx/patches-3.3/144-MIPS-pci-ar71xx-convert-to-a-platform-driver.patch b/target/linux/ar71xx/patches-3.3/144-MIPS-pci-ar71xx-convert-to-a-platform-driver.patch new file mode 100644 index 000000000..a78469b71 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/144-MIPS-pci-ar71xx-convert-to-a-platform-driver.patch @@ -0,0 +1,104 @@ +From d1a22e73f991145a4abd7d0c37bcf318703c89ed Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 11 Jun 2012 13:24:55 +0200 +Subject: [PATCH 05/34] MIPS: pci-ar71xx: convert to a platform driver + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar71xx.c | 60 +++++++++++++++++++++++++++++++++++++++++--- + 1 files changed, 56 insertions(+), 4 deletions(-) + +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -18,6 +18,8 @@ + #include <linux/pci.h> + #include <linux/pci_regs.h> + #include <linux/interrupt.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> + + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79.h> +@@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_ch + .irq_mask_ack = ar71xx_pci_irq_mask, + }; + +-static __init void ar71xx_pci_irq_init(void) ++static __devinit void ar71xx_pci_irq_init(int irq) + { + void __iomem *base = ath79_reset_base; + int i; +@@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(v + irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, + handle_level_irq); + +- irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); ++ irq_set_chained_handler(irq, ar71xx_pci_irq_handler); + } + +-static __init void ar71xx_pci_reset(void) ++static __devinit void ar71xx_pci_reset(void) + { + void __iomem *ddr_base = ath79_ddr_base; + +@@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void) + /* clear bus errors */ + ar71xx_pci_check_error(1); + +- ar71xx_pci_irq_init(); ++ ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2); + + register_pci_controller(&ar71xx_pci_controller); + + return 0; + } ++ ++static int __devinit ar71xx_pci_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ int irq; ++ u32 t; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); ++ if (!res) ++ return -EINVAL; ++ ++ ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (!ar71xx_pcicfg_base) ++ return -ENOMEM; ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return -EINVAL; ++ ++ ar71xx_pci_reset(); ++ ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE ++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ++ ar71xx_pci_local_write(PCI_COMMAND, 4, t); ++ ++ /* clear bus errors */ ++ ar71xx_pci_check_error(1); ++ ++ ar71xx_pci_irq_init(irq); ++ ++ register_pci_controller(&ar71xx_pci_controller); ++ ++ return 0; ++} ++ ++static struct platform_driver ar71xx_pci_driver = { ++ .probe = ar71xx_pci_probe, ++ .driver = { ++ .name = "ar71xx-pci", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar71xx_pci_init(void) ++{ ++ return platform_driver_register(&ar71xx_pci_driver); ++} ++ ++postcore_initcall(ar71xx_pci_init); diff --git a/target/linux/ar71xx/patches-3.3/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch b/target/linux/ar71xx/patches-3.3/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch new file mode 100644 index 000000000..4861db00f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch @@ -0,0 +1,94 @@ +From c3a8b5fa196cedc4b940c1e5ec482dd875aa3180 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 11 Jun 2012 13:38:06 +0200 +Subject: [PATCH 06/34] MIPS: ath79: move global PCI defines into a common header + +The constants will be used by a subsequent patch. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 24 ++++++++++++++++++++++++ + arch/mips/pci/pci-ar71xx.c | 16 ---------------- + arch/mips/pci/pci-ar724x.c | 8 -------- + 3 files changed, 24 insertions(+), 24 deletions(-) + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -41,11 +41,35 @@ + #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) + #define AR71XX_RESET_SIZE 0x100 + ++#define AR71XX_PCI_MEM_BASE 0x10000000 ++#define AR71XX_PCI_MEM_SIZE 0x07000000 ++ ++#define AR71XX_PCI_WIN0_OFFS 0x10000000 ++#define AR71XX_PCI_WIN1_OFFS 0x11000000 ++#define AR71XX_PCI_WIN2_OFFS 0x12000000 ++#define AR71XX_PCI_WIN3_OFFS 0x13000000 ++#define AR71XX_PCI_WIN4_OFFS 0x14000000 ++#define AR71XX_PCI_WIN5_OFFS 0x15000000 ++#define AR71XX_PCI_WIN6_OFFS 0x16000000 ++#define AR71XX_PCI_WIN7_OFFS 0x07000000 ++ ++#define AR71XX_PCI_CFG_BASE \ ++ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) ++#define AR71XX_PCI_CFG_SIZE 0x100 ++ + #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) + #define AR7240_USB_CTRL_SIZE 0x100 + #define AR7240_OHCI_BASE 0x1b000000 + #define AR7240_OHCI_SIZE 0x1000 + ++#define AR724X_PCI_MEM_BASE 0x10000000 ++#define AR724X_PCI_MEM_SIZE 0x04000000 ++ ++#define AR724X_PCI_CFG_BASE 0x14000000 ++#define AR724X_PCI_CFG_SIZE 0x1000 ++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) ++#define AR724X_PCI_CTRL_SIZE 0x100 ++ + #define AR724X_EHCI_BASE 0x1b000000 + #define AR724X_EHCI_SIZE 0x1000 + +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -25,22 +25,6 @@ + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/pci.h> + +-#define AR71XX_PCI_MEM_BASE 0x10000000 +-#define AR71XX_PCI_MEM_SIZE 0x07000000 +- +-#define AR71XX_PCI_WIN0_OFFS 0x10000000 +-#define AR71XX_PCI_WIN1_OFFS 0x11000000 +-#define AR71XX_PCI_WIN2_OFFS 0x12000000 +-#define AR71XX_PCI_WIN3_OFFS 0x13000000 +-#define AR71XX_PCI_WIN4_OFFS 0x14000000 +-#define AR71XX_PCI_WIN5_OFFS 0x15000000 +-#define AR71XX_PCI_WIN6_OFFS 0x16000000 +-#define AR71XX_PCI_WIN7_OFFS 0x07000000 +- +-#define AR71XX_PCI_CFG_BASE \ +- (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +-#define AR71XX_PCI_CFG_SIZE 0x100 +- + #define AR71XX_PCI_REG_CRP_AD_CBE 0x00 + #define AR71XX_PCI_REG_CRP_WRDATA 0x04 + #define AR71XX_PCI_REG_CRP_RDDATA 0x08 +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -17,14 +17,6 @@ + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/pci.h> + +-#define AR724X_PCI_CFG_BASE 0x14000000 +-#define AR724X_PCI_CFG_SIZE 0x1000 +-#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +-#define AR724X_PCI_CTRL_SIZE 0x100 +- +-#define AR724X_PCI_MEM_BASE 0x10000000 +-#define AR724X_PCI_MEM_SIZE 0x04000000 +- + #define AR724X_PCI_REG_RESET 0x18 + #define AR724X_PCI_REG_INT_STATUS 0x4c + #define AR724X_PCI_REG_INT_MASK 0x50 diff --git a/target/linux/ar71xx/patches-3.3/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch b/target/linux/ar71xx/patches-3.3/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch new file mode 100644 index 000000000..cc2572f88 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch @@ -0,0 +1,119 @@ +From 2fdf8dcff3ffaa806e9f9d7f1c1bd876222cff4d Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 11 Jun 2012 13:39:32 +0200 +Subject: [PATCH 07/34] MIPS: ath79: register platform devices for the PCI controllers + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/pci.c | 87 +++++++++++++++++++++++++++++++++++++++++++----- + 1 files changed, 78 insertions(+), 9 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -14,6 +14,8 @@ + + #include <linux/init.h> + #include <linux/pci.h> ++#include <linux/resource.h> ++#include <linux/platform_device.h> + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/irq.h> +@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init( + ath79_pci_plat_dev_init = func; + } + +-int __init ath79_register_pci(void) ++static struct platform_device * ++ath79_register_pci_ar71xx(void) + { +- if (soc_is_ar71xx()) +- return ar71xx_pcibios_init(); ++ struct platform_device *pdev; ++ struct resource res[2]; ++ ++ memset(res, 0, sizeof(res)); + +- if (soc_is_ar724x()) +- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); ++ res[0].name = "cfg_base"; ++ res[0].flags = IORESOURCE_MEM; ++ res[0].start = AR71XX_PCI_CFG_BASE; ++ res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; ++ ++ res[1].flags = IORESOURCE_IRQ; ++ res[1].start = ATH79_CPU_IRQ_IP2; ++ res[1].end = ATH79_CPU_IRQ_IP2; ++ ++ pdev = platform_device_register_simple("ar71xx-pci", -1, ++ res, ARRAY_SIZE(res)); ++ return pdev; ++} + +- if (soc_is_ar9342() || soc_is_ar9344()) { ++static struct platform_device * ++ath79_register_pci_ar724x(int id, ++ unsigned long cfg_base, ++ unsigned long ctrl_base, ++ int irq) ++{ ++ struct platform_device *pdev; ++ struct resource res[3]; ++ ++ memset(res, 0, sizeof(res)); ++ ++ res[0].name = "cfg_base"; ++ res[0].flags = IORESOURCE_MEM; ++ res[0].start = cfg_base; ++ res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; ++ ++ res[1].name = "ctrl_base"; ++ res[1].flags = IORESOURCE_MEM; ++ res[1].start = ctrl_base; ++ res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; ++ ++ res[2].flags = IORESOURCE_IRQ; ++ res[2].start = irq; ++ res[2].end = irq; ++ ++ pdev = platform_device_register_simple("ar724x-pci", id, ++ res, ARRAY_SIZE(res)); ++ return pdev; ++} ++ ++int __init ath79_register_pci(void) ++{ ++ struct platform_device *pdev = NULL; ++ ++ if (soc_is_ar71xx()) { ++ pdev = ath79_register_pci_ar71xx(); ++ } else if (soc_is_ar724x()) { ++ pdev = ath79_register_pci_ar724x(-1, ++ AR724X_PCI_CFG_BASE, ++ AR724X_PCI_CTRL_BASE, ++ ATH79_CPU_IRQ_IP2); ++ } else if (soc_is_ar9342() || ++ soc_is_ar9344()) { + u32 bootstrap; + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); +- if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) +- return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); ++ if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) ++ return -ENODEV; ++ ++ pdev = ath79_register_pci_ar724x(-1, ++ AR724X_PCI_CFG_BASE, ++ AR724X_PCI_CTRL_BASE, ++ ATH79_IP2_IRQ(0)); ++ } else { ++ /* No PCI support */ ++ return -ENODEV; + } + +- return -ENODEV; ++ if (!pdev) ++ pr_err("unable to register PCI controller device\n"); ++ ++ return pdev ? 0 : -ENODEV; + } diff --git a/target/linux/ar71xx/patches-3.3/147-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch b/target/linux/ar71xx/patches-3.3/147-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch new file mode 100644 index 000000000..0157e347c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/147-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch @@ -0,0 +1,147 @@ +From 07224e2fa5f889162ee0560c6ab1eb8cd16a8dd2 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 11 Jun 2012 14:59:39 +0200 +Subject: [PATCH 08/34] MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init functions + +The functions are unused now, so remove them. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/pci.c | 1 - + arch/mips/include/asm/mach-ath79/pci.h | 28 ---------------------------- + arch/mips/pci/pci-ar71xx.c | 26 -------------------------- + arch/mips/pci/pci-ar724x.c | 32 -------------------------------- + 4 files changed, 0 insertions(+), 87 deletions(-) + delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -19,7 +19,6 @@ + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/irq.h> +-#include <asm/mach-ath79/pci.h> + #include "pci.h" + + static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * Atheros AR71XX/AR724X PCI support +- * +- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> +- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> +- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#ifndef __ASM_MACH_ATH79_PCI_H +-#define __ASM_MACH_ATH79_PCI_H +- +-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) +-int ar71xx_pcibios_init(void); +-#else +-static inline int ar71xx_pcibios_init(void) { return 0; } +-#endif +- +-#if defined(CONFIG_PCI_AR724X) +-int ar724x_pcibios_init(int irq); +-#else +-static inline int ar724x_pcibios_init(int irq) { return 0; } +-#endif +- +-#endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -23,7 +23,6 @@ + + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79.h> +-#include <asm/mach-ath79/pci.h> + + #define AR71XX_PCI_REG_CRP_AD_CBE 0x00 + #define AR71XX_PCI_REG_CRP_WRDATA 0x04 +@@ -335,31 +334,6 @@ static __devinit void ar71xx_pci_reset(v + mdelay(100); + } + +-__init int ar71xx_pcibios_init(void) +-{ +- u32 t; +- +- ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); +- if (ar71xx_pcicfg_base == NULL) +- return -ENOMEM; +- +- ar71xx_pci_reset(); +- +- /* setup COMMAND register */ +- t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE +- | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; +- ar71xx_pci_local_write(PCI_COMMAND, 4, t); +- +- /* clear bus errors */ +- ar71xx_pci_check_error(1); +- +- ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2); +- +- register_pci_controller(&ar71xx_pci_controller); +- +- return 0; +-} +- + static int __devinit ar71xx_pci_probe(struct platform_device *pdev) + { + struct resource *res; +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -15,7 +15,6 @@ + #include <linux/platform_device.h> + #include <asm/mach-ath79/ath79.h> + #include <asm/mach-ath79/ar71xx_regs.h> +-#include <asm/mach-ath79/pci.h> + + #define AR724X_PCI_REG_RESET 0x18 + #define AR724X_PCI_REG_INT_STATUS 0x4c +@@ -276,37 +275,6 @@ static void __devinit ar724x_pci_irq_ini + irq_set_chained_handler(irq, ar724x_pci_irq_handler); + } + +-int __devinit ar724x_pcibios_init(int irq) +-{ +- int ret; +- +- ret = -ENOMEM; +- +- ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, +- AR724X_PCI_CFG_SIZE); +- if (ar724x_pci_devcfg_base == NULL) +- goto err; +- +- ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, +- AR724X_PCI_CTRL_SIZE); +- if (ar724x_pci_ctrl_base == NULL) +- goto err_unmap_devcfg; +- +- ar724x_pci_link_up = ar724x_pci_check_link(); +- if (!ar724x_pci_link_up) +- pr_warn("ar724x: PCIe link is down\n"); +- +- ar724x_pci_irq_init(irq); +- register_pci_controller(&ar724x_pci_controller); +- +- return PCIBIOS_SUCCESSFUL; +- +-err_unmap_devcfg: +- iounmap(ar724x_pci_devcfg_base); +-err: +- return ret; +-} +- + static int __devinit ar724x_pci_probe(struct platform_device *pdev) + { + struct resource *res; diff --git a/target/linux/ar71xx/patches-3.3/148-MIPS-avoid-possible-resource-conflict-in-register_pc.patch b/target/linux/ar71xx/patches-3.3/148-MIPS-avoid-possible-resource-conflict-in-register_pc.patch new file mode 100644 index 000000000..fc1385fc7 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/148-MIPS-avoid-possible-resource-conflict-in-register_pc.patch @@ -0,0 +1,35 @@ +From a018b28d3953a32008de839d997a992a724ae314 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 17:40:45 +0200 +Subject: [PATCH 09/34] MIPS: avoid possible resource conflict in register_pci_controller + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci.c | 15 +++++++++++++-- + 1 files changed, 13 insertions(+), 2 deletions(-) + +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -127,9 +127,20 @@ static DEFINE_MUTEX(pci_scan_mutex); + + void __devinit register_pci_controller(struct pci_controller *hose) + { +- if (request_resource(&iomem_resource, hose->mem_resource) < 0) ++ struct resource *parent; ++ ++ parent = hose->mem_resource->parent; ++ if (!parent) ++ parent = &iomem_resource; ++ ++ if (request_resource(parent, hose->mem_resource) < 0) + goto out; +- if (request_resource(&ioport_resource, hose->io_resource) < 0) { ++ ++ parent = hose->io_resource->parent; ++ if (!parent) ++ parent = &ioport_resource; ++ ++ if (request_resource(parent, hose->io_resource) < 0) { + release_resource(hose->mem_resource); + goto out; + } diff --git a/target/linux/ar71xx/patches-3.3/149-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch b/target/linux/ar71xx/patches-3.3/149-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch new file mode 100644 index 000000000..3a67cae2d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/149-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch @@ -0,0 +1,307 @@ +From 242aedf3246dc5085271aca56134ac455bfb64b5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 11:51:34 +0200 +Subject: [PATCH 10/34] MIPS: pci-ar724x: use dynamically allocated PCI controller structure + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar724x.c | 129 ++++++++++++++++++++++++++++---------------- + 1 files changed, 82 insertions(+), 47 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -9,6 +9,7 @@ + * by the Free Software Foundation. + */ + ++#include <linux/spinlock.h> + #include <linux/irq.h> + #include <linux/pci.h> + #include <linux/module.h> +@@ -28,38 +29,56 @@ + + #define AR7240_BAR0_WAR_VALUE 0xffff + +-static DEFINE_SPINLOCK(ar724x_pci_lock); +-static void __iomem *ar724x_pci_devcfg_base; +-static void __iomem *ar724x_pci_ctrl_base; +- +-static u32 ar724x_pci_bar0_value; +-static bool ar724x_pci_bar0_is_cached; +-static bool ar724x_pci_link_up; ++struct ar724x_pci_controller { ++ void __iomem *devcfg_base; ++ void __iomem *ctrl_base; + +-static inline bool ar724x_pci_check_link(void) ++ int irq; ++ ++ bool link_up; ++ bool bar0_is_cached; ++ u32 bar0_value; ++ ++ spinlock_t lock; ++ ++ struct pci_controller pci_controller; ++}; ++ ++static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) + { + u32 reset; + +- reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); ++ reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); + return reset & AR724X_PCI_RESET_LINK_UP; + } + ++static inline struct ar724x_pci_controller * ++pci_bus_to_ar724x_controller(struct pci_bus *bus) ++{ ++ struct pci_controller *hose; ++ ++ hose = (struct pci_controller *) bus->sysdata; ++ return container_of(hose, struct ar724x_pci_controller, pci_controller); ++} ++ + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { ++ struct ar724x_pci_controller *apc; + unsigned long flags; + void __iomem *base; + u32 data; + +- if (!ar724x_pci_link_up) ++ apc = pci_bus_to_ar724x_controller(bus); ++ if (!apc->link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +- base = ar724x_pci_devcfg_base; ++ base = apc->devcfg_base; + +- spin_lock_irqsave(&ar724x_pci_lock, flags); ++ spin_lock_irqsave(&apc->lock, flags); + data = __raw_readl(base + (where & ~3)); + + switch (size) { +@@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bu + case 4: + break; + default: +- spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++ spin_unlock_irqrestore(&apc->lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + +- spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++ spin_unlock_irqrestore(&apc->lock, flags); + + if (where == PCI_BASE_ADDRESS_0 && size == 4 && +- ar724x_pci_bar0_is_cached) { ++ apc->bar0_is_cached) { + /* use the cached value */ +- *value = ar724x_pci_bar0_value; ++ *value = apc->bar0_value; + } else { + *value = data; + } +@@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bu + static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t value) + { ++ struct ar724x_pci_controller *apc; + unsigned long flags; + void __iomem *base; + u32 data; + int s; + +- if (!ar724x_pci_link_up) ++ apc = pci_bus_to_ar724x_controller(bus); ++ if (!apc->link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (devfn) +@@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_b + * BAR0 register in order to make the device memory + * accessible. + */ +- ar724x_pci_bar0_is_cached = true; +- ar724x_pci_bar0_value = value; ++ apc->bar0_is_cached = true; ++ apc->bar0_value = value; + + value = AR7240_BAR0_WAR_VALUE; + } else { +- ar724x_pci_bar0_is_cached = false; ++ apc->bar0_is_cached = false; + } + } + +- base = ar724x_pci_devcfg_base; ++ base = apc->devcfg_base; + +- spin_lock_irqsave(&ar724x_pci_lock, flags); ++ spin_lock_irqsave(&apc->lock, flags); + data = __raw_readl(base + (where & ~3)); + + switch (size) { +@@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_b + data = value; + break; + default: +- spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++ spin_unlock_irqrestore(&apc->lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } +@@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_b + __raw_writel(data, base + (where & ~3)); + /* flush write */ + __raw_readl(base + (where & ~3)); +- spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++ spin_unlock_irqrestore(&apc->lock, flags); + + return PCIBIOS_SUCCESSFUL; + } +@@ -183,18 +204,14 @@ static struct resource ar724x_mem_resour + .flags = IORESOURCE_MEM, + }; + +-static struct pci_controller ar724x_pci_controller = { +- .pci_ops = &ar724x_pci_ops, +- .io_resource = &ar724x_io_resource, +- .mem_resource = &ar724x_mem_resource, +-}; +- + static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) + { ++ struct ar724x_pci_controller *apc; + void __iomem *base; + u32 pending; + +- base = ar724x_pci_ctrl_base; ++ apc = irq_get_handler_data(irq); ++ base = apc->ctrl_base; + + pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & + __raw_readl(base + AR724X_PCI_REG_INT_MASK); +@@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsig + + static void ar724x_pci_irq_unmask(struct irq_data *d) + { ++ struct ar724x_pci_controller *apc; + void __iomem *base; + u32 t; + +- base = ar724x_pci_ctrl_base; ++ apc = irq_data_get_irq_chip_data(d); ++ base = apc->ctrl_base; + + switch (d->irq) { + case ATH79_PCI_IRQ(0): +@@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct + + static void ar724x_pci_irq_mask(struct irq_data *d) + { ++ struct ar724x_pci_controller *apc; + void __iomem *base; + u32 t; + +- base = ar724x_pci_ctrl_base; ++ apc = irq_data_get_irq_chip_data(d); ++ base = apc->ctrl_base; + + switch (d->irq) { + case ATH79_PCI_IRQ(0): +@@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_ch + .irq_mask_ack = ar724x_pci_irq_mask, + }; + +-static void __devinit ar724x_pci_irq_init(int irq) ++static void __devinit ar724x_pci_irq_init(struct ar724x_pci_controller *apc) + { + void __iomem *base; + int i; + +- base = ar724x_pci_ctrl_base; ++ base = apc->ctrl_base; + + __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); + __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); +@@ -268,45 +289,59 @@ static void __devinit ar724x_pci_irq_ini + BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); + + for (i = ATH79_PCI_IRQ_BASE; +- i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) ++ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) { + irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, + handle_level_irq); ++ irq_set_chip_data(i, apc); ++ } + +- irq_set_chained_handler(irq, ar724x_pci_irq_handler); ++ irq_set_handler_data(apc->irq, apc); ++ irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler); + } + + static int __devinit ar724x_pci_probe(struct platform_device *pdev) + { ++ struct ar724x_pci_controller *apc; + struct resource *res; +- int irq; ++ ++ apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), ++ GFP_KERNEL); ++ if (!apc) ++ return -ENOMEM; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base"); + if (!res) + return -EINVAL; + +- ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res); +- if (ar724x_pci_ctrl_base == NULL) ++ apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (apc->ctrl_base == NULL) + return -EBUSY; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); + if (!res) + return -EINVAL; + +- ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res); +- if (!ar724x_pci_devcfg_base) ++ apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (!apc->devcfg_base) + return -EBUSY; + +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) ++ apc->irq = platform_get_irq(pdev, 0); ++ if (apc->irq < 0) + return -EINVAL; + +- ar724x_pci_link_up = ar724x_pci_check_link(); +- if (!ar724x_pci_link_up) ++ spin_lock_init(&apc->lock); ++ ++ apc->pci_controller.pci_ops = &ar724x_pci_ops; ++ apc->pci_controller.io_resource = &ar724x_io_resource; ++ apc->pci_controller.mem_resource = &ar724x_mem_resource; ++ ++ apc->link_up = ar724x_pci_check_link(apc); ++ if (!apc->link_up) + dev_warn(&pdev->dev, "PCIe link is down\n"); + +- ar724x_pci_irq_init(irq); ++ ar724x_pci_irq_init(apc); + +- register_pci_controller(&ar724x_pci_controller); ++ register_pci_controller(&apc->pci_controller); + + return 0; + } diff --git a/target/linux/ar71xx/patches-3.3/150-MIPS-pci-ar724x-remove-static-PCI-resources.patch b/target/linux/ar71xx/patches-3.3/150-MIPS-pci-ar724x-remove-static-PCI-resources.patch new file mode 100644 index 000000000..698b2ae0a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/150-MIPS-pci-ar724x-remove-static-PCI-resources.patch @@ -0,0 +1,131 @@ +From f1c3a7dadf7b77809cda7f77df4b1ba3b24fbfa3 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 27 Jun 2012 10:12:50 +0200 +Subject: [PATCH 11/34] MIPS: pci-ar724x: remove static PCI resources + +Get those from the platform device instead. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/pci.c | 21 ++++++++++++++++++++- + arch/mips/pci/pci-ar724x.c | 40 ++++++++++++++++++++++++---------------- + 2 files changed, 44 insertions(+), 17 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -137,10 +137,13 @@ static struct platform_device * + ath79_register_pci_ar724x(int id, + unsigned long cfg_base, + unsigned long ctrl_base, ++ unsigned long mem_base, ++ unsigned long mem_size, ++ unsigned long io_base, + int irq) + { + struct platform_device *pdev; +- struct resource res[3]; ++ struct resource res[5]; + + memset(res, 0, sizeof(res)); + +@@ -158,6 +161,16 @@ ath79_register_pci_ar724x(int id, + res[2].start = irq; + res[2].end = irq; + ++ res[3].name = "mem_base"; ++ res[3].flags = IORESOURCE_MEM; ++ res[3].start = mem_base; ++ res[3].end = mem_base + mem_size - 1; ++ ++ res[4].name = "io_base"; ++ res[4].flags = IORESOURCE_IO; ++ res[4].start = io_base; ++ res[4].end = io_base; ++ + pdev = platform_device_register_simple("ar724x-pci", id, + res, ARRAY_SIZE(res)); + return pdev; +@@ -173,6 +186,9 @@ int __init ath79_register_pci(void) + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, + AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_MEM_BASE, ++ AR724X_PCI_MEM_SIZE, ++ 0, + ATH79_CPU_IRQ_IP2); + } else if (soc_is_ar9342() || + soc_is_ar9344()) { +@@ -185,6 +201,9 @@ int __init ath79_register_pci(void) + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, + AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_MEM_BASE, ++ AR724X_PCI_MEM_SIZE, ++ 0, + ATH79_IP2_IRQ(0)); + } else { + /* No PCI support */ +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -42,6 +42,8 @@ struct ar724x_pci_controller { + spinlock_t lock; + + struct pci_controller pci_controller; ++ struct resource io_res; ++ struct resource mem_res; + }; + + static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) +@@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = { + .write = ar724x_pci_write, + }; + +-static struct resource ar724x_io_resource = { +- .name = "PCI IO space", +- .start = 0, +- .end = 0, +- .flags = IORESOURCE_IO, +-}; +- +-static struct resource ar724x_mem_resource = { +- .name = "PCI memory space", +- .start = AR724X_PCI_MEM_BASE, +- .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- + static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) + { + struct ar724x_pci_controller *apc; +@@ -331,9 +319,29 @@ static int __devinit ar724x_pci_probe(st + + spin_lock_init(&apc->lock); + ++ res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); ++ if (!res) ++ return -EINVAL; ++ ++ apc->io_res.parent = res; ++ apc->io_res.name = "PCI IO space"; ++ apc->io_res.start = res->start; ++ apc->io_res.end = res->end; ++ apc->io_res.flags = IORESOURCE_IO; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); ++ if (!res) ++ return -EINVAL; ++ ++ apc->mem_res.parent = res; ++ apc->mem_res.name = "PCI memory space"; ++ apc->mem_res.start = res->start; ++ apc->mem_res.end = res->end; ++ apc->mem_res.flags = IORESOURCE_MEM; ++ + apc->pci_controller.pci_ops = &ar724x_pci_ops; +- apc->pci_controller.io_resource = &ar724x_io_resource; +- apc->pci_controller.mem_resource = &ar724x_mem_resource; ++ apc->pci_controller.io_resource = &apc->io_res; ++ apc->pci_controller.mem_resource = &apc->mem_res; + + apc->link_up = ar724x_pci_check_link(apc); + if (!apc->link_up) diff --git a/target/linux/ar71xx/patches-3.3/151-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch b/target/linux/ar71xx/patches-3.3/151-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch new file mode 100644 index 000000000..5b690ab3e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/151-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch @@ -0,0 +1,110 @@ +From d258929cd4c8c495f619f0e66d9d1c23f3f9246f Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Tue, 26 Jun 2012 11:59:45 +0200 +Subject: [PATCH 12/34] MIPS: pci-ar724x: use per-controller IRQ base + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar724x.c | 31 +++++++++++++++++++++---------- + 1 files changed, 21 insertions(+), 10 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -34,6 +34,7 @@ struct ar724x_pci_controller { + void __iomem *ctrl_base; + + int irq; ++ int irq_base; + + bool link_up; + bool bar0_is_cached; +@@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig + __raw_readl(base + AR724X_PCI_REG_INT_MASK); + + if (pending & AR724X_PCI_INT_DEV0) +- generic_handle_irq(ATH79_PCI_IRQ(0)); ++ generic_handle_irq(apc->irq_base + 0); + + else + spurious_interrupt(); +@@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct + { + struct ar724x_pci_controller *apc; + void __iomem *base; ++ int offset; + u32 t; + + apc = irq_data_get_irq_chip_data(d); + base = apc->ctrl_base; ++ offset = apc->irq_base - d->irq; + +- switch (d->irq) { +- case ATH79_PCI_IRQ(0): ++ switch (offset) { ++ case 0: + t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); + __raw_writel(t | AR724X_PCI_INT_DEV0, + base + AR724X_PCI_REG_INT_MASK); +@@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i + { + struct ar724x_pci_controller *apc; + void __iomem *base; ++ int offset; + u32 t; + + apc = irq_data_get_irq_chip_data(d); + base = apc->ctrl_base; ++ offset = apc->irq_base - d->irq; + +- switch (d->irq) { +- case ATH79_PCI_IRQ(0): ++ switch (offset) { ++ case 0: + t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); + __raw_writel(t & ~AR724X_PCI_INT_DEV0, + base + AR724X_PCI_REG_INT_MASK); +@@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch + .irq_mask_ack = ar724x_pci_irq_mask, + }; + +-static void __devinit ar724x_pci_irq_init(struct ar724x_pci_controller *apc) ++static void __devinit ar724x_pci_irq_init(struct ar724x_pci_controller *apc, ++ int id) + { + void __iomem *base; + int i; +@@ -274,10 +280,10 @@ static void __devinit ar724x_pci_irq_ini + __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); + __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); + +- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); ++ apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); + +- for (i = ATH79_PCI_IRQ_BASE; +- i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) { ++ for (i = apc->irq_base; ++ i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { + irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, + handle_level_irq); + irq_set_chip_data(i, apc); +@@ -291,6 +297,11 @@ static int __devinit ar724x_pci_probe(st + { + struct ar724x_pci_controller *apc; + struct resource *res; ++ int id; ++ ++ id = pdev->id; ++ if (id == -1) ++ id = 0; + + apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller), + GFP_KERNEL); +@@ -347,7 +358,7 @@ static int __devinit ar724x_pci_probe(st + if (!apc->link_up) + dev_warn(&pdev->dev, "PCIe link is down\n"); + +- ar724x_pci_irq_init(apc); ++ ar724x_pci_irq_init(apc, id); + + register_pci_controller(&apc->pci_controller); + diff --git a/target/linux/ar71xx/patches-3.3/152-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch b/target/linux/ar71xx/patches-3.3/152-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch new file mode 100644 index 000000000..38c43bccd --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/152-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch @@ -0,0 +1,165 @@ +From 93824983ceb36d4ce1f4a644031ec6fb5f332f1d Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Tue, 26 Jun 2012 15:14:47 +0200 +Subject: [PATCH 13/34] MIPS: pci-ar724x: setup command register of the PCI controller + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/pci.c | 10 +++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 + + arch/mips/pci/pci-ar724x.c | 63 ++++++++++++++++++++++++ + 3 files changed, 74 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -137,13 +137,14 @@ static struct platform_device * + ath79_register_pci_ar724x(int id, + unsigned long cfg_base, + unsigned long ctrl_base, ++ unsigned long crp_base, + unsigned long mem_base, + unsigned long mem_size, + unsigned long io_base, + int irq) + { + struct platform_device *pdev; +- struct resource res[5]; ++ struct resource res[6]; + + memset(res, 0, sizeof(res)); + +@@ -171,6 +172,11 @@ ath79_register_pci_ar724x(int id, + res[4].start = io_base; + res[4].end = io_base; + ++ res[5].name = "crp_base"; ++ res[5].flags = IORESOURCE_MEM; ++ res[5].start = crp_base; ++ res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1; ++ + pdev = platform_device_register_simple("ar724x-pci", id, + res, ARRAY_SIZE(res)); + return pdev; +@@ -186,6 +192,7 @@ int __init ath79_register_pci(void) + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, + AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_CRP_BASE, + AR724X_PCI_MEM_BASE, + AR724X_PCI_MEM_SIZE, + 0, +@@ -201,6 +208,7 @@ int __init ath79_register_pci(void) + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, + AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_CRP_BASE, + AR724X_PCI_MEM_BASE, + AR724X_PCI_MEM_SIZE, + 0, +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -67,6 +67,8 @@ + + #define AR724X_PCI_CFG_BASE 0x14000000 + #define AR724X_PCI_CFG_SIZE 0x1000 ++#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) ++#define AR724X_PCI_CRP_SIZE 0x1000 + #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) + #define AR724X_PCI_CTRL_SIZE 0x100 + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -29,9 +29,17 @@ + + #define AR7240_BAR0_WAR_VALUE 0xffff + ++#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \ ++ PCI_COMMAND_MASTER | \ ++ PCI_COMMAND_INVALIDATE | \ ++ PCI_COMMAND_PARITY | \ ++ PCI_COMMAND_SERR | \ ++ PCI_COMMAND_FAST_BACK) ++ + struct ar724x_pci_controller { + void __iomem *devcfg_base; + void __iomem *ctrl_base; ++ void __iomem *crp_base; + + int irq; + int irq_base; +@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_ + return container_of(hose, struct ar724x_pci_controller, pci_controller); + } + ++static int ar724x_pci_local_write(struct ar724x_pci_controller *apc, ++ int where, int size, u32 value) ++{ ++ unsigned long flags; ++ void __iomem *base; ++ u32 data; ++ int s; ++ ++ WARN_ON(where & (size - 1)); ++ ++ if (!apc->link_up) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ base = apc->crp_base; ++ ++ spin_lock_irqsave(&apc->lock, flags); ++ data = __raw_readl(base + (where & ~3)); ++ ++ switch (size) { ++ case 1: ++ s = ((where & 3) * 8); ++ data &= ~(0xff << s); ++ data |= ((value & 0xff) << s); ++ break; ++ case 2: ++ s = ((where & 2) * 8); ++ data &= ~(0xffff << s); ++ data |= ((value & 0xffff) << s); ++ break; ++ case 4: ++ data = value; ++ break; ++ default: ++ spin_unlock_irqrestore(&apc->lock, flags); ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ __raw_writel(data, base + (where & ~3)); ++ /* flush write */ ++ __raw_readl(base + (where & ~3)); ++ spin_unlock_irqrestore(&apc->lock, flags); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { +@@ -324,6 +377,14 @@ static int __devinit ar724x_pci_probe(st + if (!apc->devcfg_base) + return -EBUSY; + ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base"); ++ if (!res) ++ return -EINVAL; ++ ++ apc->crp_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (apc->crp_base == NULL) ++ return -EBUSY; ++ + apc->irq = platform_get_irq(pdev, 0); + if (apc->irq < 0) + return -EINVAL; +@@ -360,6 +421,8 @@ static int __devinit ar724x_pci_probe(st + + ar724x_pci_irq_init(apc, id); + ++ ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT); ++ + register_pci_controller(&apc->pci_controller); + + return 0; diff --git a/target/linux/ar71xx/patches-3.3/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch b/target/linux/ar71xx/patches-3.3/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch new file mode 100644 index 000000000..4db1fd92b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch @@ -0,0 +1,228 @@ +From 6c3ef689e4364dca74eaaecd72384be09e5a6bc8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 25 Jun 2012 09:19:08 +0200 +Subject: [PATCH 14/34] MIPS: pci-ar71xx: use dynamically allocated PCI controller structure + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar71xx.c | 84 +++++++++++++++++++++++++++---------------- + 1 files changed, 53 insertions(+), 31 deletions(-) + +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -20,6 +20,7 @@ + #include <linux/interrupt.h> + #include <linux/module.h> + #include <linux/platform_device.h> ++#include <linux/slab.h> + + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79.h> +@@ -48,8 +49,12 @@ + + #define AR71XX_PCI_IRQ_COUNT 5 + +-static DEFINE_SPINLOCK(ar71xx_pci_lock); +-static void __iomem *ar71xx_pcicfg_base; ++struct ar71xx_pci_controller { ++ void __iomem *cfg_base; ++ spinlock_t lock; ++ int irq; ++ struct pci_controller pci_ctrl; ++}; + + /* Byte lane enable bits */ + static const u8 ar71xx_pci_ble_table[4][4] = { +@@ -92,9 +97,18 @@ static inline u32 ar71xx_pci_bus_addr(st + return ret; + } + +-static int ar71xx_pci_check_error(int quiet) ++static inline struct ar71xx_pci_controller * ++pci_bus_to_ar71xx_controller(struct pci_bus *bus) + { +- void __iomem *base = ar71xx_pcicfg_base; ++ struct pci_controller *hose; ++ ++ hose = (struct pci_controller *) bus->sysdata; ++ return container_of(hose, struct ar71xx_pci_controller, pci_ctrl); ++} ++ ++static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet) ++{ ++ void __iomem *base = apc->cfg_base; + u32 pci_err; + u32 ahb_err; + +@@ -129,9 +143,10 @@ static int ar71xx_pci_check_error(int qu + return !!(ahb_err | pci_err); + } + +-static inline void ar71xx_pci_local_write(int where, int size, u32 value) ++static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc, ++ int where, int size, u32 value) + { +- void __iomem *base = ar71xx_pcicfg_base; ++ void __iomem *base = apc->cfg_base; + u32 ad_cbe; + + value = value << (8 * (where & 3)); +@@ -147,7 +162,8 @@ static inline int ar71xx_pci_set_cfgaddr + unsigned int devfn, + int where, int size, u32 cmd) + { +- void __iomem *base = ar71xx_pcicfg_base; ++ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); ++ void __iomem *base = apc->cfg_base; + u32 addr; + + addr = ar71xx_pci_bus_addr(bus, devfn, where); +@@ -156,13 +172,14 @@ static inline int ar71xx_pci_set_cfgaddr + __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), + base + AR71XX_PCI_REG_CFG_CBE); + +- return ar71xx_pci_check_error(1); ++ return ar71xx_pci_check_error(apc, 1); + } + + static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) + { +- void __iomem *base = ar71xx_pcicfg_base; ++ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); ++ void __iomem *base = apc->cfg_base; + unsigned long flags; + u32 data; + int err; +@@ -171,7 +188,7 @@ static int ar71xx_pci_read_config(struct + ret = PCIBIOS_SUCCESSFUL; + data = ~0; + +- spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ spin_lock_irqsave(&apc->lock, flags); + + err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, + AR71XX_PCI_CFG_CMD_READ); +@@ -180,7 +197,7 @@ static int ar71xx_pci_read_config(struct + else + data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); + +- spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ spin_unlock_irqrestore(&apc->lock, flags); + + *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; + +@@ -190,7 +207,8 @@ static int ar71xx_pci_read_config(struct + static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) + { +- void __iomem *base = ar71xx_pcicfg_base; ++ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); ++ void __iomem *base = apc->cfg_base; + unsigned long flags; + int err; + int ret; +@@ -198,7 +216,7 @@ static int ar71xx_pci_write_config(struc + value = value << (8 * (where & 3)); + ret = PCIBIOS_SUCCESSFUL; + +- spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ spin_lock_irqsave(&apc->lock, flags); + + err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, + AR71XX_PCI_CFG_CMD_WRITE); +@@ -207,7 +225,7 @@ static int ar71xx_pci_write_config(struc + else + __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); + +- spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ spin_unlock_irqrestore(&apc->lock, flags); + + return ret; + } +@@ -231,12 +249,6 @@ static struct resource ar71xx_pci_mem_re + .flags = IORESOURCE_MEM + }; + +-static struct pci_controller ar71xx_pci_controller = { +- .pci_ops = &ar71xx_pci_ops, +- .mem_resource = &ar71xx_pci_mem_resource, +- .io_resource = &ar71xx_pci_io_resource, +-}; +- + static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) + { + void __iomem *base = ath79_reset_base; +@@ -294,7 +306,7 @@ static struct irq_chip ar71xx_pci_irq_ch + .irq_mask_ack = ar71xx_pci_irq_mask, + }; + +-static __devinit void ar71xx_pci_irq_init(int irq) ++static __devinit void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) + { + void __iomem *base = ath79_reset_base; + int i; +@@ -309,7 +321,7 @@ static __devinit void ar71xx_pci_irq_ini + irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, + handle_level_irq); + +- irq_set_chained_handler(irq, ar71xx_pci_irq_handler); ++ irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler); + } + + static __devinit void ar71xx_pci_reset(void) +@@ -336,20 +348,26 @@ static __devinit void ar71xx_pci_reset(v + + static int __devinit ar71xx_pci_probe(struct platform_device *pdev) + { ++ struct ar71xx_pci_controller *apc; + struct resource *res; +- int irq; + u32 t; + ++ apc = kzalloc(sizeof(struct ar71xx_pci_controller), GFP_KERNEL); ++ if (!apc) ++ return -ENOMEM; ++ ++ spin_lock_init(&apc->lock); ++ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); + if (!res) + return -EINVAL; + +- ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res); +- if (!ar71xx_pcicfg_base) ++ apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (!apc->cfg_base) + return -ENOMEM; + +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) ++ apc->irq = platform_get_irq(pdev, 0); ++ if (apc->irq < 0) + return -EINVAL; + + ar71xx_pci_reset(); +@@ -357,14 +375,18 @@ static int __devinit ar71xx_pci_probe(st + /* setup COMMAND register */ + t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE + | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; +- ar71xx_pci_local_write(PCI_COMMAND, 4, t); ++ ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t); + + /* clear bus errors */ +- ar71xx_pci_check_error(1); ++ ar71xx_pci_check_error(apc, 1); ++ ++ ar71xx_pci_irq_init(apc); + +- ar71xx_pci_irq_init(irq); ++ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; ++ apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource; ++ apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource; + +- register_pci_controller(&ar71xx_pci_controller); ++ register_pci_controller(&apc->pci_ctrl); + + return 0; + } diff --git a/target/linux/ar71xx/patches-3.3/154-MIPS-pci-ar71xx-remove-static-PCI-controller-resourc.patch b/target/linux/ar71xx/patches-3.3/154-MIPS-pci-ar71xx-remove-static-PCI-controller-resourc.patch new file mode 100644 index 000000000..d31ba264b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/154-MIPS-pci-ar71xx-remove-static-PCI-controller-resourc.patch @@ -0,0 +1,70 @@ +From 7dc3ccb5dc972b06c41b309653d132beaaedeb37 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 25 Jun 2012 09:52:23 +0200 +Subject: [PATCH 15/34] MIPS: pci-ar71xx: remove static PCI controller resources + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/pci/pci-ar71xx.c | 30 ++++++++++++++---------------- + 1 files changed, 14 insertions(+), 16 deletions(-) + +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -54,6 +54,8 @@ struct ar71xx_pci_controller { + spinlock_t lock; + int irq; + struct pci_controller pci_ctrl; ++ struct resource io_res; ++ struct resource mem_res; + }; + + /* Byte lane enable bits */ +@@ -235,20 +237,6 @@ static struct pci_ops ar71xx_pci_ops = { + .write = ar71xx_pci_write_config, + }; + +-static struct resource ar71xx_pci_io_resource = { +- .name = "PCI IO space", +- .start = 0, +- .end = 0, +- .flags = IORESOURCE_IO, +-}; +- +-static struct resource ar71xx_pci_mem_resource = { +- .name = "PCI memory space", +- .start = AR71XX_PCI_MEM_BASE, +- .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, +- .flags = IORESOURCE_MEM +-}; +- + static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) + { + void __iomem *base = ath79_reset_base; +@@ -370,6 +358,16 @@ static int __devinit ar71xx_pci_probe(st + if (apc->irq < 0) + return -EINVAL; + ++ apc->io_res.name = "PCI IO space"; ++ apc->io_res.start = 0; ++ apc->io_res.end = 0; ++ apc->io_res.flags = IORESOURCE_IO; ++ ++ apc->mem_res.name = "PCI memory space"; ++ apc->mem_res.start = AR71XX_PCI_MEM_BASE; ++ apc->mem_res.end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1; ++ apc->mem_res.flags = IORESOURCE_MEM; ++ + ar71xx_pci_reset(); + + /* setup COMMAND register */ +@@ -383,8 +381,8 @@ static int __devinit ar71xx_pci_probe(st + ar71xx_pci_irq_init(apc); + + apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; +- apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource; +- apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource; ++ apc->pci_ctrl.mem_resource = &apc->mem_res; ++ apc->pci_ctrl.io_resource = &apc->io_res; + + register_pci_controller(&apc->pci_ctrl); + diff --git a/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch new file mode 100644 index 000000000..7f1f2302f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch @@ -0,0 +1,31 @@ +From 114df1e368b8503de1fe63e97d6eea521eecfbe4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:40:38 +0200 +Subject: [PATCH 16/34] MIPS: ath79: add early printk support for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/early_printk.c | 1 + + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -74,6 +74,7 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: ++ case REV_ID_MAJOR_QCA9558: + _prom_putchar = prom_putchar_ar71xx; + break; + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -370,6 +370,7 @@ + #define REV_ID_MAJOR_AR9341 0x0120 + #define REV_ID_MAJOR_AR9342 0x1120 + #define REV_ID_MAJOR_AR9344 0x2120 ++#define REV_ID_MAJOR_QCA9558 0x1130 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 + #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch b/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch new file mode 100644 index 000000000..1d9dd4beb --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch @@ -0,0 +1,91 @@ +From 3c3c0eccf63b12fea98fd0eb65d0ccf69a7c5a57 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:42:16 +0200 +Subject: [PATCH 17/34] MIPS: ath79: add SoC detection code for the QCA9558 SoC + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/ath79/setup.c | 12 +++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + arch/mips/include/asm/mach-ath79/ath79.h | 11 +++++++++++ + 4 files changed, 28 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -88,6 +88,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA955X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config PCI_AR724X + def_bool n + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -164,13 +164,23 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9558: ++ ath79_soc = ATH79_SOC_QCA9558; ++ chip = "9558"; ++ rev = id & AR944X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } + + ath79_soc_rev = rev; + +- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); ++ if (soc_is_qca955x()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", ++ chip, rev); ++ else ++ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); + } + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -391,6 +391,8 @@ + + #define AR934X_REV_ID_REVISION_MASK 0xf + ++#define AR944X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,7 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9558, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -98,6 +99,16 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9558(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9558; ++} ++ ++static inline int soc_is_qca955x(void) ++{ ++ return soc_is_qca9558(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; diff --git a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch new file mode 100644 index 000000000..bb0924c43 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch @@ -0,0 +1,167 @@ +From f465a16766a015a31d4e83af1ad62cc718d64f5a Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:43:08 +0200 +Subject: [PATCH 18/34] MIPS: ath79: add clock setup for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 39 ++++++++++++ + 2 files changed, 117 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo + iounmap(dpll_base); + } + ++static void __init qca955x_clocks_init(void) ++{ ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) ++ ath79_ref_clk.rate = 40 * 1000 * 1000; ++ else ++ ath79_ref_clk.rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ath79_ref_clk.rate / ref_div; ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ath79_ref_clk.rate / ref_div; ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ ath79_cpu_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ath79_ddr_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); ++ else ++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ath79_ahb_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); ++ ++ ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_uart_clk.rate = ath79_ref_clk.rate; ++} ++ + void __init ath79_clocks_init(void) + { + if (soc_is_ar71xx()) +@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void) + ar933x_clocks_init(); + else if (soc_is_ar934x()) + ar934x_clocks_init(); ++ else if (soc_is_qca955x()) ++ qca955x_clocks_init(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -225,6 +225,41 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA955X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA955X_PLL_DDR_CONFIG_REG 0x04 ++#define QCA955X_PLL_CLK_CTRL_REG 0x08 ++ ++#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 ++ ++#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + /* + * USB_CONFIG block + */ +@@ -264,6 +299,8 @@ + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + ++#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 ++ + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) + #define MISC_INT_TIMER3 BIT(9) +@@ -341,6 +378,8 @@ + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) ++ + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) + #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) + #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) diff --git a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch new file mode 100644 index 000000000..8d24c742d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch @@ -0,0 +1,239 @@ +From 5d0de52f8e36916485a61b820916b71b5d918e6f Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:44:23 +0200 +Subject: [PATCH 19/34] MIPS: ath79: add IRQ handling code for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++-- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++ + arch/mips/include/asm/mach-ath79/irq.h | 9 ++- + 3 files changed, 142 insertions(+), 9 deletions(-) + +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -130,7 +130,10 @@ static void __init ath79_misc_irq_init(v + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; +- else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) ++ else if (soc_is_ar724x() || ++ soc_is_ar933x() || ++ soc_is_ar934x() || ++ soc_is_qca955x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else + BUG(); +@@ -177,6 +180,88 @@ static void ar934x_ip2_irq_init(void) + irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); + } + ++static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } ++ ++ if (status & QCA955X_EXT_INT_WMAC_ALL) { ++ /* TODO: flsuh DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA955X_EXT_INT_PCIE_RC2_ALL | ++ QCA955X_EXT_INT_USB1 | ++ QCA955X_EXT_INT_USB2; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA955X_EXT_INT_USB1) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(0)); ++ } ++ ++ if (status & QCA955X_EXT_INT_USB2) { ++ /* TODO: flsuh DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(1)); ++ } ++ ++ if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(2)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca955x_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca955x_ip2_irq_dispatch); ++ ++ for (i = ATH79_IP3_IRQ_BASE; ++ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca955x_ip3_irq_dispatch); ++} ++ + asmlinkage void plat_irq_dispatch(void) + { + unsigned long pending; +@@ -212,6 +297,17 @@ asmlinkage void plat_irq_dispatch(void) + * Issue a flush in the handlers to ensure that the driver sees + * the update. + */ ++ ++static void ath79_default_ip2_handler(void) ++{ ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ath79_default_ip3_handler(void) ++{ ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ + static void ar71xx_ip2_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); +@@ -236,11 +332,6 @@ static void ar933x_ip2_handler(void) + do_IRQ(ATH79_CPU_IRQ_IP2); + } + +-static void ar934x_ip2_handler(void) +-{ +- do_IRQ(ATH79_CPU_IRQ_IP2); +-} +- + static void ar71xx_ip3_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); +@@ -286,8 +377,11 @@ void __init arch_init_irq(void) + ath79_ip2_handler = ar933x_ip2_handler; + ath79_ip3_handler = ar933x_ip3_handler; + } else if (soc_is_ar934x()) { +- ath79_ip2_handler = ar934x_ip2_handler; ++ ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ar934x_ip3_handler; ++ } else if (soc_is_qca955x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = ath79_default_ip3_handler; + } else { + BUG(); + } +@@ -298,4 +392,6 @@ void __init arch_init_irq(void) + + if (soc_is_ar934x()) + ar934x_ip2_irq_init(); ++ else if (soc_is_qca955x()) ++ qca955x_irq_init(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -300,6 +300,7 @@ + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) +@@ -398,6 +399,37 @@ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + ++#define QCA955X_EXT_INT_WMAC_MISC BIT(0) ++#define QCA955X_EXT_INT_WMAC_TX BIT(1) ++#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) ++#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) ++#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) ++#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) ++#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) ++#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) ++#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) ++#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) ++#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) ++#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) ++#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) ++#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) ++#define QCA955X_EXT_INT_USB1 BIT(24) ++#define QCA955X_EXT_INT_USB2 BIT(28) ++ ++#define QCA955X_EXT_INT_WMAC_ALL \ ++ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ ++ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) ++ ++#define QCA955X_EXT_INT_PCIE_RC1_ALL \ ++ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ ++ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ ++ QCA955X_EXT_INT_PCIE_RC1_INT3) ++ ++#define QCA955X_EXT_INT_PCIE_RC2_ALL \ ++ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ ++ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ ++ QCA955X_EXT_INT_PCIE_RC2_INT3) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,7 +10,7 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 48 ++#define NR_IRQS 51 + + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 +@@ -23,8 +23,13 @@ + #define ATH79_IP2_IRQ_COUNT 2 + #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) + ++#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT) ++#define ATH79_IP3_IRQ_COUNT 3 ++#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) ++ + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) +-#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) ++#define ATH79_CPU_IRQ_IP3 (MIPS_CPU_IRQ_BASE + 3) ++#define ATH79_CPU_IRQ_USB ATH79_CPU_IRQ_IP3 + #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) + #define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) + #define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) diff --git a/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch new file mode 100644 index 000000000..dc4251be9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch @@ -0,0 +1,39 @@ +From c9a552f3007f0621b2440ae17bad816578299e52 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:45:27 +0200 +Subject: [PATCH 20/34] MIPS: ath79: add GPIO setup code for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/gpio.c | 4 +++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 4 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -196,12 +196,14 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; ++ else if (soc_is_qca955x()) ++ ath79_gpio_count = QCA955X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x()) { ++ if (soc_is_ar934x() || soc_is_qca955x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -506,6 +506,7 @@ + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 ++#define QCA955X_GPIO_COUNT 24 + + /* + * SRIF block diff --git a/target/linux/ar71xx/patches-3.3/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch b/target/linux/ar71xx/patches-3.3/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch new file mode 100644 index 000000000..f3e3b6eec --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch @@ -0,0 +1,31 @@ +From 68368e80b4db83afe39664a7d43c8b5c7b8ac3b4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:49:33 +0200 +Subject: [PATCH 21/34] MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set,clear} + +--- + arch/mips/ath79/common.c | 6 ++++-- + 1 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -70,7 +70,8 @@ void ath79_device_reset_set(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; +- else if (soc_is_ar934x()) ++ else if (soc_is_ar934x() || ++ soc_is_qca955x()) + reg = AR934X_RESET_REG_RESET_MODULE; + else + BUG(); +@@ -96,7 +97,8 @@ void ath79_device_reset_clear(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; +- else if (soc_is_ar934x()) ++ else if (soc_is_ar934x() || ++ soc_is_qca955x()) + reg = AR934X_RESET_REG_RESET_MODULE; + else + BUG(); diff --git a/target/linux/ar71xx/patches-3.3/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch new file mode 100644 index 000000000..aacb8bbeb --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch @@ -0,0 +1,22 @@ +From f7d7b362b51c51c1ae80bb7ade2039d6f74d4070 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:46:26 +0200 +Subject: [PATCH 22/34] MIPS: ath79: register UART for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/dev-common.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -90,7 +90,8 @@ void __init ath79_register_uart(void) + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || +- soc_is_ar934x()) { ++ soc_is_ar934x() || ++ soc_is_qca955x()) { + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { diff --git a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch new file mode 100644 index 000000000..5a27a9b71 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch @@ -0,0 +1,93 @@ +From e4ba5e2bffd1f373f57dd692233aa6b7b46ae76c Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:47:35 +0200 +Subject: [PATCH 23/34] MIPS: ath79: add USB controller registration code for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/dev-usb.c | 46 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++ + 2 files changed, 50 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -75,6 +75,8 @@ static void __init ath79_usb_init_resour + unsigned long size, + int irq) + { ++ memset(res, 0, sizeof(res)); ++ + res[0].flags = IORESOURCE_MEM; + res[0].start = base; + res[0].end = base + size - 1; +@@ -219,6 +221,48 @@ static void __init ar934x_usb_setup(void + platform_device_register(&ath79_ehci_device); + } + ++static void __init qca955x_usb_setup(void) ++{ ++ struct platform_device *pdev; ++ ++ ath79_usb_init_resource(ath79_ehci_resources, ++ QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, ++ ATH79_IP3_IRQ(0)); ++ ++ pdev = platform_device_register_resndata(NULL, "ehci-platform", 0, ++ ath79_ehci_resources, ++ ARRAY_SIZE(ath79_ehci_resources), ++ &ath79_ehci_pdata_v2, ++ sizeof(ath79_ehci_pdata_v2)); ++ if (IS_ERR(pdev)) { ++ pr_err("Unable to register USB %d device, err=%d\n", 0, ++ (int) PTR_ERR(pdev)); ++ return; ++ } ++ ++ pdev->dev.dma_mask = &ath79_ehci_dmamask; ++ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); ++ ++ ath79_usb_init_resource(ath79_ehci_resources, ++ QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, ++ ATH79_IP3_IRQ(1)); ++ ++ pdev = platform_device_register_resndata(NULL, "ehci-platform", 1, ++ ath79_ehci_resources, ++ ARRAY_SIZE(ath79_ehci_resources), ++ &ath79_ehci_pdata_v2, ++ sizeof(ath79_ehci_pdata_v2)); ++ ++ if (IS_ERR(pdev)) { ++ pr_err("Unable to register USB %d device, err=%d\n", 1, ++ (int) PTR_ERR(pdev)); ++ return; ++ } ++ ++ pdev->dev.dma_mask = &ath79_ehci_dmamask; ++ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); ++} ++ + void __init ath79_register_usb(void) + { + if (soc_is_ar71xx()) +@@ -233,6 +277,8 @@ void __init ath79_register_usb(void) + ar933x_usb_setup(); + else if (soc_is_ar934x()) + ar934x_usb_setup(); ++ else if (soc_is_qca955x()) ++ qca955x_usb_setup(); + else + BUG(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -94,6 +94,10 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA955X_EHCI0_BASE 0x1b000000 ++#define QCA955X_EHCI1_BASE 0x1b400000 ++#define QCA955X_EHCI_SIZE 0x200 ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch new file mode 100644 index 000000000..efc354e9d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch @@ -0,0 +1,70 @@ +From 0568e7f92ecf2bfd2af0a5c59b1249fef002c89f Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Tue, 3 Jul 2012 10:24:43 +0200 +Subject: [PATCH 24/34] MIPS: ath79: add WMAC registration code for the QCA955X SoCs + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/Kconfig | 2 +- + arch/mips/ath79/dev-wmac.c | 20 ++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + 3 files changed, 23 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -108,7 +108,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) + def_bool n + + endif +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static void qca955x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca955x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); ++ if (t & QCA955X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data) + { + if (soc_is_ar913x()) +@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_ + ar933x_wmac_setup(); + else if (soc_is_ar934x()) + ar934x_wmac_setup(); ++ else if (soc_is_qca955x()) ++ qca955x_wmac_setup(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -94,6 +94,8 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x200 diff --git a/target/linux/ar71xx/patches-3.3/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch b/target/linux/ar71xx/patches-3.3/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch new file mode 100644 index 000000000..bd95d718b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch @@ -0,0 +1,34 @@ +From 12c68e4fccadc22a0470177141a57892a76e4a2b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 15:33:16 +0200 +Subject: [PATCH 25/34] MIPS: ath79: allow to specify bus number in PCI IRQ maps + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/pci.c | 4 +++- + arch/mips/ath79/pci.h | 1 + + 2 files changed, 4 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct + const struct ath79_pci_irq *entry; + + entry = &ath79_pci_irq_map[i]; +- if (entry->slot == slot && entry->pin == pin) { ++ if (entry->bus == dev->bus->number && ++ entry->slot == slot && ++ entry->pin == pin) { + irq = entry->irq; + break; + } +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -14,6 +14,7 @@ + #define _ATH79_PCI_H + + struct ath79_pci_irq { ++ int bus; + u8 slot; + u8 pin; + int irq; diff --git a/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch new file mode 100644 index 000000000..0c3889fdb --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch @@ -0,0 +1,103 @@ +From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 23:05:20 +0200 +Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC + +--- + arch/mips/ath79/Kconfig | 2 + + arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 ++++++++ + 3 files changed, 51 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -90,6 +90,8 @@ config SOC_AR934X + + config SOC_QCA955X + select USB_ARCH_HAS_EHCI ++ select HW_HAS_PCI ++ select PCI_AR724X if PCI + def_bool n + + config PCI_AR724X +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x + } + }; + ++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { ++ { ++ .bus = 0, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, ++ { ++ .bus = 1, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(1), ++ }, ++}; ++ + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { + int irq = -1; +@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct + soc_is_ar9344()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); ++ } else if (soc_is_qca955x()) { ++ ath79_pci_irq_map = qca955x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); + } else { + pr_crit("pci %s: invalid irq map\n", + pci_name((struct pci_dev *) dev)); +@@ -215,6 +233,24 @@ int __init ath79_register_pci(void) + AR724X_PCI_MEM_SIZE, + 0, + ATH79_IP2_IRQ(0)); ++ } else if (soc_is_qca9558()) { ++ pdev = ath79_register_pci_ar724x(0, ++ QCA955X_PCI_CFG_BASE0, ++ QCA955X_PCI_CTRL_BASE0, ++ QCA955X_PCI_CRP_BASE0, ++ QCA955X_PCI_MEM_BASE0, ++ QCA955X_PCI_MEM_SIZE, ++ 0, ++ ATH79_IP2_IRQ(0)); ++ ++ pdev = ath79_register_pci_ar724x(1, ++ QCA955X_PCI_CFG_BASE1, ++ QCA955X_PCI_CTRL_BASE1, ++ QCA955X_PCI_CRP_BASE1, ++ QCA955X_PCI_MEM_BASE1, ++ QCA955X_PCI_MEM_SIZE, ++ 1, ++ ATH79_IP3_IRQ(2)); + } else { + /* No PCI support */ + return -ENODEV; +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -94,6 +94,19 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA955X_PCI_MEM_BASE0 0x10000000 ++#define QCA955X_PCI_MEM_BASE1 0x12000000 ++#define QCA955X_PCI_MEM_SIZE 0x02000000 ++#define QCA955X_PCI_CFG_BASE0 0x14000000 ++#define QCA955X_PCI_CFG_BASE1 0x16000000 ++#define QCA955X_PCI_CFG_SIZE 0x1000 ++#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) ++#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) ++#define QCA955X_PCI_CRP_SIZE 0x1000 ++#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) ++#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) ++#define QCA955X_PCI_CTRL_SIZE 0x100 ++ + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 diff --git a/target/linux/ar71xx/patches-3.3/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch b/target/linux/ar71xx/patches-3.3/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch new file mode 100644 index 000000000..dc26f9c7b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch @@ -0,0 +1,213 @@ +From a034da3e4d4960266a94d15c811d5f4529fdff44 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Sun, 24 Jun 2012 13:52:23 +0200 +Subject: [PATCH 27/34] MIPS: ath79: add support for the Qualcomm Atheros AP136 board + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/Kconfig | 12 +++ + arch/mips/ath79/Makefile | 1 + + arch/mips/ath79/mach-ap136.c | 155 ++++++++++++++++++++++++++++++++++++++++++ + arch/mips/ath79/machtypes.h | 1 + + 4 files changed, 169 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/ath79/mach-ap136.c + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -14,6 +14,18 @@ config ATH79_MACH_AP121 + Say 'Y' here if you want your kernel to support the + Atheros AP121 reference board. + ++config ATH79_MACH_AP136 ++ bool "Atheros AP136 reference board" ++ select SOC_QCA955X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP136 reference board. ++ + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma + # Machines + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o ++obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o + obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o +--- /dev/null ++++ b/arch/mips/ath79/mach-ap136.c +@@ -0,0 +1,155 @@ ++/* ++ * Qualcomm Atheros AP136 reference board support ++ * ++ * Copyright (c) 2012 Qualcomm Atheros ++ * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ * ++ */ ++ ++#include <linux/pci.h> ++#include <linux/ath9k_platform.h> ++ ++#include "machtypes.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-spi.h" ++#include "dev-usb.h" ++#include "dev-wmac.h" ++#include "pci.h" ++ ++#define AP136_GPIO_LED_STATUS_RED 14 ++#define AP136_GPIO_LED_STATUS_GREEN 19 ++#define AP136_GPIO_LED_USB 4 ++#define AP136_GPIO_LED_WLAN_2G 13 ++#define AP136_GPIO_LED_WLAN_5G 12 ++#define AP136_GPIO_LED_WPS_RED 15 ++#define AP136_GPIO_LED_WPS_GREEN 20 ++ ++#define AP136_GPIO_BTN_WPS 16 ++#define AP136_GPIO_BTN_RFKILL 21 ++ ++#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) ++ ++#define AP136_WMAC_CALDATA_OFFSET 0x1000 ++#define AP136_PCIE_CALDATA_OFFSET 0x5000 ++ ++static struct gpio_led ap136_leds_gpio[] __initdata = { ++ { ++ .name = "ap136:green:status", ++ .gpio = AP136_GPIO_LED_STATUS_GREEN, ++ .active_low = 1, ++ }, ++ { ++ .name = "ap136:red:status", ++ .gpio = AP136_GPIO_LED_STATUS_RED, ++ .active_low = 1, ++ }, ++ { ++ .name = "ap136:green:wps", ++ .gpio = AP136_GPIO_LED_WPS_GREEN, ++ .active_low = 1, ++ }, ++ { ++ .name = "ap136:red:wps", ++ .gpio = AP136_GPIO_LED_WPS_RED, ++ .active_low = 1, ++ }, ++ { ++ .name = "ap136:red:wlan-2g", ++ .gpio = AP136_GPIO_LED_WLAN_2G, ++ .active_low = 1, ++ }, ++ { ++ .name = "ap136:red:usb", ++ .gpio = AP136_GPIO_LED_USB, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button ap136_gpio_keys[] __initdata = { ++ { ++ .desc = "WPS button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP136_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, ++ { ++ .desc = "RFKILL button", ++ .type = EV_KEY, ++ .code = KEY_RFKILL, ++ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP136_GPIO_BTN_RFKILL, ++ .active_low = 1, ++ }, ++}; ++ ++static struct spi_board_info ap136_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "mx25l6405d", ++ } ++}; ++ ++static struct ath79_spi_platform_data ap136_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 1, ++}; ++ ++#ifdef CONFIG_PCI ++static struct ath9k_platform_data ap136_ath9k_data; ++ ++static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) ++ dev->dev.platform_data = &ap136_ath9k_data; ++ ++ return 0; ++} ++ ++static void __init ap136_pci_init(u8 *eeprom) ++{ ++ memcpy(ap136_ath9k_data.eeprom_data, eeprom, ++ sizeof(ap136_ath9k_data.eeprom_data)); ++ ++ ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); ++ ath79_register_pci(); ++} ++#else ++static inline void ap136_pci_init(void) {} ++#endif /* CONFIG_PCI */ ++ ++static void __init ap136_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), ++ ap136_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap136_gpio_keys), ++ ap136_gpio_keys); ++ ath79_register_spi(&ap136_spi_data, ap136_spi_info, ++ ARRAY_SIZE(ap136_spi_info)); ++ ath79_register_usb(); ++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); ++ ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", ++ ap136_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -17,6 +17,7 @@ + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ ++ ATH79_MACH_AP136, /* Atheros AP136 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ diff --git a/target/linux/ar71xx/patches-3.3/200-spi-ath79-add-delay-between-SCK-changes.patch b/target/linux/ar71xx/patches-3.3/200-spi-ath79-add-delay-between-SCK-changes.patch new file mode 100644 index 000000000..28cc1fbe9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/200-spi-ath79-add-delay-between-SCK-changes.patch @@ -0,0 +1,122 @@ +From cbb3ade4765bc715b5c2eae4a7b6eaf3ff7ad958 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 11 Jan 2012 20:06:35 +0100 +Subject: [PATCH 28/34] spi/ath79: add delay between SCK changes + +The driver uses the "as fast as it can" approach +to drive the SCK signal. However this does not +work with certain low speed SPI chips (e.g. the +PCF2123 RTC chip). Add per-bit slowdowns in order +to be able to use the driver with such chips as +well. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + drivers/spi/spi-ath79.c | 44 +++++++++++++++++++++++++++++++++++++++++++- + 1 files changed, 43 insertions(+), 1 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -24,17 +24,24 @@ + #include <linux/spi/spi_bitbang.h> + #include <linux/bitops.h> + #include <linux/gpio.h> ++#include <linux/clk.h> ++#include <linux/err.h> + + #include <asm/mach-ath79/ar71xx_regs.h> + #include <asm/mach-ath79/ath79_spi_platform.h> + + #define DRV_NAME "ath79-spi" + ++#define ATH79_SPI_RRW_DELAY_FACTOR 12000 ++#define MHZ (1000 * 1000) ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; + u32 reg_ctrl; + void __iomem *base; ++ struct clk *clk; ++ unsigned rrw_delay; + }; + + static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp + return spi_master_get_devdata(spi->master); + } + ++static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) ++{ ++ if (nsecs > sp->rrw_delay) ++ ndelay(nsecs - sp->rrw_delay); ++} ++ + static void ath79_spi_chipselect(struct spi_device *spi, int is_active) + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); +@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s + + /* setup MSB (to slave) on trailing edge */ + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); ++ ath79_spi_delay(sp, nsecs); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); ++ ath79_spi_delay(sp, nsecs); + + word <<= 1; + } +@@ -198,6 +213,7 @@ static __devinit int ath79_spi_probe(str + struct ath79_spi *sp; + struct ath79_spi_platform_data *pdata; + struct resource *r; ++ unsigned long rate; + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); +@@ -239,12 +255,36 @@ static __devinit int ath79_spi_probe(str + goto err_put_master; + } + ++ sp->clk = clk_get(&pdev->dev, "ahb"); ++ if (IS_ERR(sp->clk)) { ++ ret = PTR_ERR(sp->clk); ++ goto err_unmap; ++ } ++ ++ ret = clk_enable(sp->clk); ++ if (ret) ++ goto err_clk_put; ++ ++ rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); ++ if (!rate) { ++ ret = -EINVAL; ++ goto err_clk_disable; ++ } ++ ++ sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; ++ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", ++ sp->rrw_delay); ++ + ret = spi_bitbang_start(&sp->bitbang); + if (ret) +- goto err_unmap; ++ goto err_clk_disable; + + return 0; + ++err_clk_disable: ++ clk_disable(sp->clk); ++err_clk_put: ++ clk_put(sp->clk); + err_unmap: + iounmap(sp->base); + err_put_master: +@@ -259,6 +299,8 @@ static __devexit int ath79_spi_remove(st + struct ath79_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); ++ clk_disable(sp->clk); ++ clk_put(sp->clk); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); diff --git a/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch b/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch new file mode 100644 index 000000000..fd3d9689a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch @@ -0,0 +1,21 @@ +From bcb0fdebc08f828b54d0a2eb74a9d1378701a8e0 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 11 Jan 2012 20:33:41 +0100 +Subject: [PATCH 29/34] spi/ath79: add missing HIGH->LOW SCK transition + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + drivers/spi/spi-ath79.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s + ath79_spi_delay(sp, nsecs); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); + ath79_spi_delay(sp, nsecs); ++ if (bits == 1) ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); + + word <<= 1; + } diff --git a/target/linux/ar71xx/patches-3.3/202-spi-ath79-remove-superfluous-chip-select-code.patch b/target/linux/ar71xx/patches-3.3/202-spi-ath79-remove-superfluous-chip-select-code.patch new file mode 100644 index 000000000..eec3293d9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/202-spi-ath79-remove-superfluous-chip-select-code.patch @@ -0,0 +1,30 @@ +From 06752f9b169493cd1323f8337c147ad2dd31025c Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 9 Jan 2012 15:03:28 +0100 +Subject: [PATCH 30/34] spi/ath79: remove superfluous chip select code + +The spi_bitbang driver calls the chipselect function +of the driver from spi_bitbang_setup in order to +deselect the given SPI chip, so we don't have to +initialize the CS line here. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + drivers/spi/spi-ath79.c | 6 ------ + 1 files changed, 0 insertions(+), 6 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi + gpio_free(cdata->gpio); + return status; + } +- } else { +- if (spi->mode & SPI_CS_HIGH) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; +- else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; +- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + + return 0; diff --git a/target/linux/ar71xx/patches-3.3/203-spi-ath79-use-gpio_request_one.patch b/target/linux/ar71xx/patches-3.3/203-spi-ath79-use-gpio_request_one.patch new file mode 100644 index 000000000..12559bcae --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/203-spi-ath79-use-gpio_request_one.patch @@ -0,0 +1,56 @@ +From 6bd876a46b977643f27d2cc63f49e1bc84b78134 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 9 Jan 2012 15:04:21 +0100 +Subject: [PATCH 31/34] spi/ath79: use gpio_request_one + +Use gpio_request_one() instead of multiple gpiolib calls. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + drivers/spi/spi-ath79.c | 26 +++++++++++++------------- + 1 files changed, 13 insertions(+), 13 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + struct ath79_spi_controller_data *cdata; ++ int status; + + cdata = spi->controller_data; + if (spi->chip_select && !cdata) +@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi + /* TODO: setup speed? */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + ++ status = 0; + if (spi->chip_select) { +- int status = 0; ++ unsigned long flags; + +- status = gpio_request(cdata->gpio, dev_name(&spi->dev)); +- if (status) +- return status; +- +- status = gpio_direction_output(cdata->gpio, +- spi->mode & SPI_CS_HIGH); +- if (status) { +- gpio_free(cdata->gpio); +- return status; +- } ++ flags = GPIOF_DIR_OUT; ++ if (spi->mode & SPI_CS_HIGH) ++ flags |= GPIOF_INIT_HIGH; ++ else ++ flags |= GPIOF_INIT_LOW; ++ ++ status = gpio_request_one(cdata->gpio, flags, ++ dev_name(&spi->dev)); + } + +- return 0; ++ return status; + } + + static void ath79_spi_cleanup_cs(struct spi_device *spi) diff --git a/target/linux/ar71xx/patches-3.3/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.3/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch new file mode 100644 index 000000000..084bd98bb --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch @@ -0,0 +1,108 @@ +From e63ceaa0c4f7be0498cd452981073d3ce8e7d1f5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 9 Jan 2012 15:00:46 +0100 +Subject: [PATCH 32/34] spi/ath79: avoid multiple initialization of the SPI controller + +Currently we are initializing the SPI controller in +the chip select line function, and that function is +called once for each SPI device on the bus. If a +board has multiple SPI devices, the controller will +be initialized multiple times. + +Introduce ath79_spi_{en,dis}able helper functions, +and call those from probe/response in order to avoid +the mutliple initialization of the controller. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + drivers/spi/spi-ath79.c | 41 ++++++++++++++++++++++++----------------- + 1 files changed, 24 insertions(+), 17 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct + + } + +-static int ath79_spi_setup_cs(struct spi_device *spi) ++static void ath79_spi_enable(struct ath79_spi *sp) + { +- struct ath79_spi *sp = ath79_spidev_to_sp(spi); +- struct ath79_spi_controller_data *cdata; +- int status; +- +- cdata = spi->controller_data; +- if (spi->chip_select && !cdata) +- return -EINVAL; +- + /* enable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + +@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi + + /* TODO: setup speed? */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); ++} ++ ++static void ath79_spi_disable(struct ath79_spi *sp) ++{ ++ /* restore CTRL register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++} ++ ++static int ath79_spi_setup_cs(struct spi_device *spi) ++{ ++ struct ath79_spi_controller_data *cdata; ++ int status; ++ ++ cdata = spi->controller_data; ++ if (spi->chip_select && !cdata) ++ return -EINVAL; + + status = 0; + if (spi->chip_select) { +@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- struct ath79_spi *sp = ath79_spidev_to_sp(spi); +- + if (spi->chip_select) { + struct ath79_spi_controller_data *cdata = spi->controller_data; + gpio_free(cdata->gpio); + } +- +- /* restore CTRL register */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); +- /* disable GPIO mode */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); + } + + static int ath79_spi_setup(struct spi_device *spi) +@@ -271,12 +274,15 @@ static __devinit int ath79_spi_probe(str + dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", + sp->rrw_delay); + ++ ath79_spi_enable(sp); + ret = spi_bitbang_start(&sp->bitbang); + if (ret) +- goto err_clk_disable; ++ goto err_disable; + + return 0; + ++err_disable: ++ ath79_spi_disable(sp); + err_clk_disable: + clk_disable(sp->clk); + err_clk_put: +@@ -295,6 +301,7 @@ static __devexit int ath79_spi_remove(st + struct ath79_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); ++ ath79_spi_disable(sp); + clk_disable(sp->clk); + clk_put(sp->clk); + iounmap(sp->base); diff --git a/target/linux/ar71xx/patches-3.3/205-spi-ath79-add-shutdown-handler.patch b/target/linux/ar71xx/patches-3.3/205-spi-ath79-add-shutdown-handler.patch new file mode 100644 index 000000000..a1461ceae --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/205-spi-ath79-add-shutdown-handler.patch @@ -0,0 +1,45 @@ +From dab305def68a9ea28c1c0ca2fc20bba645944914 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 11 Jan 2012 22:19:32 +0100 +Subject: [PATCH 33/34] spi/ath79: add shutdown handler + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + drivers/spi/spi-ath79.c | 12 +++++++++++- + 1 files changed, 11 insertions(+), 1 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -296,7 +296,7 @@ err_put_master: + return ret; + } + +-static __devexit int ath79_spi_remove(struct platform_device *pdev) ++static void __ath79_spi_remove(struct platform_device *pdev) + { + struct ath79_spi *sp = platform_get_drvdata(pdev); + +@@ -307,13 +307,23 @@ static __devexit int ath79_spi_remove(st + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); ++} + ++static __devexit int ath79_spi_remove(struct platform_device *pdev) ++{ ++ __ath79_spi_remove(pdev); + return 0; + } + ++static void ath79_spi_shutdown(struct platform_device *pdev) ++{ ++ __ath79_spi_remove(pdev); ++} ++ + static struct platform_driver ath79_spi_driver = { + .probe = ath79_spi_probe, + .remove = __devexit_p(ath79_spi_remove), ++ .shutdown = ath79_spi_shutdown, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, diff --git a/target/linux/ar71xx/patches-3.3/206-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-3.3/206-spi-ath79-make-chipselect-logic-more-flexible.patch new file mode 100644 index 000000000..5a4c0df5d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/206-spi-ath79-make-chipselect-logic-more-flexible.patch @@ -0,0 +1,313 @@ +From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 11 Jan 2012 22:25:11 +0100 +Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/mach-ap121.c | 6 ++ + arch/mips/ath79/mach-ap136.c | 6 ++ + arch/mips/ath79/mach-ap81.c | 6 ++ + arch/mips/ath79/mach-db120.c | 6 ++ + arch/mips/ath79/mach-pb44.c | 6 ++ + arch/mips/ath79/mach-ubnt-xm.c | 6 ++ + .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++- + drivers/spi/spi-ath79.c | 67 +++++++++++++------- + 8 files changed, 88 insertions(+), 23 deletions(-) + +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi + } + }; + ++static struct ath79_spi_controller_data ap121_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ap121_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l1606e", ++ .controller_data = &ap121_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-ap136.c ++++ b/arch/mips/ath79/mach-ap136.c +@@ -98,12 +98,18 @@ static struct gpio_keys_button ap136_gpi + }, + }; + ++static struct ath79_spi_controller_data ap136_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ap136_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l6405d", ++ .controller_data = &ap136_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio + } + }; + ++static struct ath79_spi_controller_data ap81_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ap81_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .controller_data = &ap81_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -76,12 +76,18 @@ static struct gpio_keys_button db120_gpi + }, + }; + ++static struct ath79_spi_controller_data db120_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info db120_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "s25sl064a", ++ .controller_data = &db120_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio + } + }; + ++static struct ath79_spi_controller_data pb44_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .controller_data = &pb44_spi0_data, + }, + }; + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + ++static struct ath79_spi_controller_data ubnt_xm_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ubnt_xm_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l6405d", ++ .controller_data = &ubnt_xm_spi0_data, + } + }; + +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -16,8 +16,14 @@ struct ath79_spi_platform_data { + unsigned num_chipselect; + }; + ++enum ath79_spi_cs_type { ++ ATH79_SPI_CS_TYPE_INTERNAL, ++ ATH79_SPI_CS_TYPE_GPIO, ++}; ++ + struct ath79_spi_controller_data { +- unsigned gpio; ++ enum ath79_spi_cs_type cs_type; ++ unsigned cs_line; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -35,6 +35,8 @@ + #define ATH79_SPI_RRW_DELAY_FACTOR 12000 + #define MHZ (1000 * 1000) + ++#define ATH79_SPI_CS_LINE_MAX 2 ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; ++ struct ath79_spi_controller_data *cdata = spi->controller_data; + + if (is_active) { + /* set initial clock polarity */ +@@ -80,20 +83,24 @@ static void ath79_spi_chipselect(struct + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- +- /* SPI is normally active-low */ +- gpio_set_value(cdata->gpio, cs_high); +- } else { ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: + if (cs_high) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; ++ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line); + else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ++ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line); + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); +- } ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: ++ /* SPI is normally active-low */ ++ if (gpio_cansleep(cdata->cs_line)) ++ gpio_set_value_cansleep(cdata->cs_line, cs_high); ++ else ++ gpio_set_value(cdata->cs_line, cs_high); ++ break; ++ } + } + + static void ath79_spi_enable(struct ath79_spi *sp) +@@ -120,24 +127,30 @@ static void ath79_spi_disable(struct ath + static int ath79_spi_setup_cs(struct spi_device *spi) + { + struct ath79_spi_controller_data *cdata; ++ unsigned long flags; + int status; + + cdata = spi->controller_data; +- if (spi->chip_select && !cdata) ++ if (!cdata) + return -EINVAL; + + status = 0; +- if (spi->chip_select) { +- unsigned long flags; ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX) ++ status = -EINVAL; ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: + flags = GPIOF_DIR_OUT; + if (spi->mode & SPI_CS_HIGH) + flags |= GPIOF_INIT_HIGH; + else + flags |= GPIOF_INIT_LOW; + +- status = gpio_request_one(cdata->gpio, flags, ++ status = gpio_request_one(cdata->cs_line, flags, + dev_name(&spi->dev)); ++ break; + } + + return status; +@@ -145,9 +158,19 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- gpio_free(cdata->gpio); ++ struct ath79_spi_controller_data *cdata; ++ ++ cdata = spi->controller_data; ++ if (!cdata) ++ return; ++ ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ /* nothing to do */ ++ break; ++ case ATH79_SPI_CS_TYPE_GPIO: ++ gpio_free(cdata->cs_line); ++ break; + } + } + +@@ -155,6 +178,9 @@ static int ath79_spi_setup(struct spi_de + { + int status = 0; + ++ if (spi->controller_data == NULL) ++ return -EINVAL; ++ + if (spi->bits_per_word > 32) + return -EINVAL; + +@@ -215,6 +241,10 @@ static __devinit int ath79_spi_probe(str + unsigned long rate; + int ret; + ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; ++ + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); +@@ -224,17 +254,10 @@ static __devinit int ath79_spi_probe(str + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + +- pdata = pdev->dev.platform_data; +- + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; +- if (pdata) { +- master->bus_num = pdata->bus_num; +- master->num_chipselect = pdata->num_chipselect; +- } else { +- master->bus_num = -1; +- master->num_chipselect = 1; +- } ++ master->bus_num = pdata->bus_num; ++ master->num_chipselect = pdata->num_chipselect; + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ar71xx/patches-3.3/210-MIPS-ath79-simplify-misc-irq-handling.patch b/target/linux/ar71xx/patches-3.3/210-MIPS-ath79-simplify-misc-irq-handling.patch new file mode 100644 index 000000000..84a8ca36f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/210-MIPS-ath79-simplify-misc-irq-handling.patch @@ -0,0 +1,66 @@ +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsig + pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & + __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + +- if (pending & MISC_INT_UART) +- generic_handle_irq(ATH79_MISC_IRQ_UART); +- +- else if (pending & MISC_INT_DMA) +- generic_handle_irq(ATH79_MISC_IRQ_DMA); +- +- else if (pending & MISC_INT_PERFC) +- generic_handle_irq(ATH79_MISC_IRQ_PERFC); +- +- else if (pending & MISC_INT_TIMER) +- generic_handle_irq(ATH79_MISC_IRQ_TIMER); +- +- else if (pending & MISC_INT_TIMER2) +- generic_handle_irq(ATH79_MISC_IRQ_TIMER2); +- +- else if (pending & MISC_INT_TIMER3) +- generic_handle_irq(ATH79_MISC_IRQ_TIMER3); +- +- else if (pending & MISC_INT_TIMER4) +- generic_handle_irq(ATH79_MISC_IRQ_TIMER4); +- +- else if (pending & MISC_INT_OHCI) +- generic_handle_irq(ATH79_MISC_IRQ_OHCI); +- +- else if (pending & MISC_INT_ERROR) +- generic_handle_irq(ATH79_MISC_IRQ_ERROR); +- +- else if (pending & MISC_INT_GPIO) +- generic_handle_irq(ATH79_MISC_IRQ_GPIO); +- +- else if (pending & MISC_INT_WDOG) +- generic_handle_irq(ATH79_MISC_IRQ_WDOG); ++ if (!pending) { ++ spurious_interrupt(); ++ return; ++ } + +- else if (pending & MISC_INT_ETHSW) +- generic_handle_irq(ATH79_MISC_IRQ_ETHSW); ++ while (pending) { ++ int bit = __ffs(pending); + +- else +- spurious_interrupt(); ++ generic_handle_irq(ATH79_MISC_IRQ(bit)); ++ pending &= ~BIT(bit); ++ } + } + + static void ar71xx_misc_irq_unmask(struct irq_data *d) +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -14,6 +14,7 @@ + + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 ++#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x)) + + #define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) + #define ATH79_PCI_IRQ_COUNT 6 diff --git a/target/linux/ar71xx/patches-3.3/211-ar933x_uart-improve-serial-clock-calculation.patch b/target/linux/ar71xx/patches-3.3/211-ar933x_uart-improve-serial-clock-calculation.patch new file mode 100644 index 000000000..510b75ed0 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/211-ar933x_uart-improve-serial-clock-calculation.patch @@ -0,0 +1,181 @@ +--- a/drivers/tty/serial/ar933x_uart.c ++++ b/drivers/tty/serial/ar933x_uart.c +@@ -25,11 +25,19 @@ + #include <linux/io.h> + #include <linux/irq.h> + ++#include <asm/div64.h> ++ + #include <asm/mach-ath79/ar933x_uart.h> + #include <asm/mach-ath79/ar933x_uart_platform.h> + + #define DRIVER_NAME "ar933x-uart" + ++#define AR933X_UART_MAX_SCALE 0xff ++#define AR933X_UART_MAX_STEP 0xffff ++ ++#define AR933X_UART_MIN_BAUD 300 ++#define AR933X_UART_MAX_BAUD 3000000 ++ + #define AR933X_DUMMY_STATUS_RD 0x01 + + static struct uart_driver ar933x_uart_driver; +@@ -37,6 +45,8 @@ static struct uart_driver ar933x_uart_dr + struct ar933x_uart_port { + struct uart_port port; + unsigned int ier; /* shadow Interrupt Enable Register */ ++ unsigned int min_baud; ++ unsigned int max_baud; + }; + + static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up, +@@ -162,6 +172,57 @@ static void ar933x_uart_enable_ms(struct + { + } + ++/* ++ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17)) ++ */ ++static unsigned long ar933x_uart_get_baud(unsigned int clk, ++ unsigned int scale, ++ unsigned int step) ++{ ++ u64 t; ++ u32 div; ++ ++ div = (2 << 16) * (scale + 1); ++ t = clk; ++ t *= step; ++ t += (div / 2); ++ do_div(t, div); ++ ++ return t; ++} ++ ++static void ar933x_uart_get_scale_step(unsigned int clk, ++ unsigned int baud, ++ unsigned int *scale, ++ unsigned int *step) ++{ ++ unsigned int tscale; ++ long min_diff; ++ ++ *scale = 0; ++ *step = 0; ++ ++ min_diff = baud; ++ for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) { ++ u64 tstep; ++ int diff; ++ ++ tstep = baud * (tscale + 1); ++ tstep *= (2 << 16); ++ do_div(tstep, clk); ++ ++ if (tstep > AR933X_UART_MAX_STEP) ++ break; ++ ++ diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud); ++ if (diff < min_diff) { ++ min_diff = diff; ++ *scale = tscale; ++ *step = tstep; ++ } ++ } ++} ++ + static void ar933x_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +@@ -169,7 +230,7 @@ static void ar933x_uart_set_termios(stru + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned int cs; + unsigned long flags; +- unsigned int baud, scale; ++ unsigned int baud, scale, step; + + /* Only CS8 is supported */ + new->c_cflag &= ~CSIZE; +@@ -191,8 +252,8 @@ static void ar933x_uart_set_termios(stru + /* Mark/space parity is not supported */ + new->c_cflag &= ~CMSPAR; + +- baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); +- scale = (port->uartclk / (16 * baud)) - 1; ++ baud = uart_get_baud_rate(port, new, old, up->min_baud, up->max_baud); ++ ar933x_uart_get_scale_step(port->uartclk, baud, &scale, &step); + + /* + * Ok, we're now changing the port state. Do it with +@@ -200,6 +261,10 @@ static void ar933x_uart_set_termios(stru + */ + spin_lock_irqsave(&up->port.lock, flags); + ++ /* disable the UART */ ++ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S); ++ + /* Update the per-port timeout. */ + uart_update_timeout(port, new->c_cflag, baud); + +@@ -210,7 +275,7 @@ static void ar933x_uart_set_termios(stru + up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD; + + ar933x_uart_write(up, AR933X_UART_CLOCK_REG, +- scale << AR933X_UART_CLOCK_SCALE_S | 8192); ++ scale << AR933X_UART_CLOCK_SCALE_S | step); + + /* setup configuration register */ + ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs); +@@ -219,6 +284,11 @@ static void ar933x_uart_set_termios(stru + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_HOST_INT_EN); + ++ /* reenable the UART */ ++ ar933x_uart_rmw(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S, ++ AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S); ++ + spin_unlock_irqrestore(&up->port.lock, flags); + + if (tty_termios_baud_rate(new)) +@@ -401,6 +471,8 @@ static void ar933x_uart_config_port(stru + static int ar933x_uart_verify_port(struct uart_port *port, + struct serial_struct *ser) + { ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ + if (ser->type != PORT_UNKNOWN && + ser->type != PORT_AR933X) + return -EINVAL; +@@ -408,7 +480,8 @@ static int ar933x_uart_verify_port(struc + if (ser->irq < 0 || ser->irq >= NR_IRQS) + return -EINVAL; + +- if (ser->baud_base < 28800) ++ if (ser->baud_base < up->min_baud || ++ ser->baud_base > up->max_baud) + return -EINVAL; + + return 0; +@@ -561,6 +634,7 @@ static int __devinit ar933x_uart_probe(s + struct uart_port *port; + struct resource *mem_res; + struct resource *irq_res; ++ unsigned int baud; + int id; + int ret; + +@@ -611,6 +685,12 @@ static int __devinit ar933x_uart_probe(s + port->fifosize = AR933X_UART_FIFO_SIZE; + port->ops = &ar933x_uart_ops; + ++ baud = ar933x_uart_get_baud(port->uartclk, AR933X_UART_MAX_SCALE, 1); ++ up->min_baud = max_t(unsigned int, baud, AR933X_UART_MIN_BAUD); ++ ++ baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP); ++ up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD); ++ + ar933x_uart_add_console_port(up); + + ret = uart_add_one_port(&ar933x_uart_driver, &up->port); diff --git a/target/linux/ar71xx/patches-3.3/300-ehcpi-platform-remove-ehci_update_device.patch b/target/linux/ar71xx/patches-3.3/300-ehcpi-platform-remove-ehci_update_device.patch new file mode 100644 index 000000000..e9a5b7005 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/300-ehcpi-platform-remove-ehci_update_device.patch @@ -0,0 +1,11 @@ +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -75,8 +75,6 @@ static const struct hc_driver ehci_platf + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + +- .update_device = ehci_update_device, +- + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, + }; + diff --git a/target/linux/ar71xx/patches-3.3/310-lib-add-rle-decompression.patch b/target/linux/ar71xx/patches-3.3/310-lib-add-rle-decompression.patch new file mode 100644 index 000000000..0cb946229 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/310-lib-add-rle-decompression.patch @@ -0,0 +1,114 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -124,6 +124,9 @@ config LZMA_COMPRESS + config LZMA_DECOMPRESS + tristate + ++config RLE_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -85,6 +85,7 @@ obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ + obj-$(CONFIG_LZMA_COMPRESS) += lzma/ + obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ ++obj-$(CONFIG_RLE_DECOMPRESS) += rle.o + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/include/linux/rle.h +@@ -0,0 +1,8 @@ ++#ifndef _RLE_H_ ++#define _RLE_H_ ++ ++int rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done); ++ ++#endif /* _RLE_H_ */ +--- /dev/null ++++ b/lib/rle.c +@@ -0,0 +1,78 @@ ++/* ++ * RLE decoding routine ++ * ++ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/rle.h> ++ ++int rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done) ++{ ++ size_t srcpos, dstpos; ++ int ret; ++ ++ srcpos = 0; ++ dstpos = 0; ++ ret = -EINVAL; ++ ++ /* sanity checks */ ++ if (!src || !srclen || !dst || !dstlen) ++ goto out; ++ ++ while (1) { ++ char count; ++ ++ if (srcpos >= srclen) ++ break; ++ ++ count = (char) src[srcpos++]; ++ if (count == 0) { ++ ret = 0; ++ break; ++ } ++ ++ if (count > 0) { ++ unsigned char c; ++ ++ if (srcpos >= srclen) ++ break; ++ ++ c = src[srcpos++]; ++ ++ while (count--) { ++ if (dstpos >= dstlen) ++ break; ++ ++ dst[dstpos++] = c; ++ } ++ } else { ++ count *= -1; ++ ++ while (count--) { ++ if (srcpos >= srclen) ++ break; ++ if (dstpos >= dstlen) ++ break; ++ dst[dstpos++] = src[srcpos++]; ++ } ++ } ++ } ++ ++out: ++ if (src_done) ++ *src_done = srcpos; ++ if (dst_done) ++ *dst_done = dstpos; ++ ++ return ret; ++} ++ ++EXPORT_SYMBOL_GPL(rle_decode); diff --git a/target/linux/ar71xx/patches-3.3/401-mtd-physmap-add-lock-unlock.patch b/target/linux/ar71xx/patches-3.3/401-mtd-physmap-add-lock-unlock.patch new file mode 100644 index 000000000..36e30c246 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/401-mtd-physmap-add-lock-unlock.patch @@ -0,0 +1,94 @@ +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -29,6 +29,66 @@ struct physmap_flash_info { + struct map_info map[MAX_RESOURCES]; + }; + ++static struct platform_device *physmap_map2pdev(struct map_info *map) ++{ ++ return (struct platform_device *) map->map_priv_1; ++} ++ ++static void physmap_lock(struct map_info *map) ++{ ++ struct platform_device *pdev; ++ struct physmap_flash_data *physmap_data; ++ ++ pdev = physmap_map2pdev(map); ++ physmap_data = pdev->dev.platform_data; ++ physmap_data->lock(pdev); ++} ++ ++static void physmap_unlock(struct map_info *map) ++{ ++ struct platform_device *pdev; ++ struct physmap_flash_data *physmap_data; ++ ++ pdev = physmap_map2pdev(map); ++ physmap_data = pdev->dev.platform_data; ++ physmap_data->unlock(pdev); ++} ++ ++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs) ++{ ++ map_word ret; ++ ++ physmap_lock(map); ++ ret = inline_map_read(map, ofs); ++ physmap_unlock(map); ++ ++ return ret; ++} ++ ++static void physmap_flash_write_lock(struct map_info *map, map_word d, ++ unsigned long ofs) ++{ ++ physmap_lock(map); ++ inline_map_write(map, d, ofs); ++ physmap_unlock(map); ++} ++ ++static void physmap_flash_copy_from_lock(struct map_info *map, void *to, ++ unsigned long from, ssize_t len) ++{ ++ physmap_lock(map); ++ inline_map_copy_from(map, to, from, len); ++ physmap_unlock(map); ++} ++ ++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to, ++ const void *from, ssize_t len) ++{ ++ physmap_lock(map); ++ inline_map_copy_to(map, to, from, len); ++ physmap_unlock(map); ++} ++ + static int physmap_flash_remove(struct platform_device *dev) + { + struct physmap_flash_info *info; +@@ -141,6 +201,13 @@ static int physmap_flash_probe(struct pl + + simple_map_init(&info->map[i]); + ++ if (physmap_data->lock && physmap_data->unlock) { ++ info->map[i].read = physmap_flash_read_lock; ++ info->map[i].write = physmap_flash_write_lock; ++ info->map[i].copy_from = physmap_flash_copy_from_lock; ++ info->map[i].copy_to = physmap_flash_copy_to_lock; ++ } ++ + probe_type = rom_probe_types; + if (physmap_data->probe_type == NULL) { + for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++) +--- a/include/linux/mtd/physmap.h ++++ b/include/linux/mtd/physmap.h +@@ -26,6 +26,8 @@ struct physmap_flash_data { + unsigned int width; + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); ++ void (*lock)(struct platform_device *); ++ void (*unlock)(struct platform_device *); + void (*set_vpp)(struct platform_device *, int); + unsigned int nr_parts; + unsigned int pfow_base; diff --git a/target/linux/ar71xx/patches-3.3/402-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-3.3/402-mtd-SST39VF6401B-support.patch new file mode 100644 index 000000000..246abd5dc --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/402-mtd-SST39VF6401B-support.patch @@ -0,0 +1,29 @@ +--- a/drivers/mtd/chips/jedec_probe.c ++++ b/drivers/mtd/chips/jedec_probe.c +@@ -148,6 +148,7 @@ + #define SST39LF160 0x2782 + #define SST39VF1601 0x234b + #define SST39VF3201 0x235b ++#define SST39VF6401B 0x236d + #define SST39WF1601 0x274b + #define SST39WF1602 0x274a + #define SST39LF512 0x00D4 +@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec + ERASEINFO(0x10000,64), + } + }, { ++ .mfr_id = CFI_MFR_SST, ++ .dev_id = SST39VF6401B, ++ .name = "SST 39VF6401B", ++ .devtypes = CFI_DEVICETYPE_X16, ++ .uaddr = MTD_UADDR_0xAAAA_0x5555, ++ .dev_size = SIZE_8MiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x10000,128) ++ } ++ }, { + .mfr_id = CFI_MFR_ST, + .dev_id = M29F800AB, + .name = "ST M29F800AB", diff --git a/target/linux/ar71xx/patches-3.3/403-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-3.3/403-mtd_fix_cfi_cmdset_0002_status_check.patch new file mode 100644 index 000000000..9ed059822 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/403-mtd_fix_cfi_cmdset_0002_status_check.patch @@ -0,0 +1,69 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1214,8 +1214,8 @@ static int __xipram do_write_oneword(str + break; + } + +- if (chip_ready(map, adr)) +- break; ++ if (chip_good(map, adr, datum)) ++ goto enable_xip; + + /* Latency issues. Drop the lock, wait a while and retry */ + UDELAY(map, chip, adr, 1); +@@ -1231,6 +1231,8 @@ static int __xipram do_write_oneword(str + + ret = -EIO; + } ++ ++ enable_xip: + xip_enable(map, chip, adr); + op_done: + chip->state = FL_READY; +@@ -1563,7 +1565,6 @@ static int cfi_amdstd_write_buffers(stru + return 0; + } + +- + /* + * Handle devices with one erase region, that only implement + * the chip erase command. +@@ -1627,8 +1628,8 @@ static int __xipram do_erase_chip(struct + chip->erase_suspended = 0; + } + +- if (chip_ready(map, adr)) +- break; ++ if (chip_good(map, adr, map_word_ff(map))) ++ goto op_done; + + if (time_after(jiffies, timeo)) { + printk(KERN_WARNING "MTD %s(): software timeout\n", +@@ -1648,6 +1649,7 @@ static int __xipram do_erase_chip(struct + ret = -EIO; + } + ++ op_done: + chip->state = FL_READY; + xip_enable(map, chip, adr); + put_chip(map, chip, adr); +@@ -1715,9 +1717,9 @@ static int __xipram do_erase_oneblock(st + chip->erase_suspended = 0; + } + +- if (chip_ready(map, adr)) { ++ if (chip_good(map, adr, map_word_ff(map))) { + xip_enable(map, chip, adr); +- break; ++ goto op_done; + } + + if (time_after(jiffies, timeo)) { +@@ -1739,6 +1741,7 @@ static int __xipram do_erase_oneblock(st + ret = -EIO; + } + ++ op_done: + chip->state = FL_READY; + put_chip(map, chip, adr); + mutex_unlock(&chip->mutex); diff --git a/target/linux/ar71xx/patches-3.3/404-mtd-wrt160nl-trx-parser.patch b/target/linux/ar71xx/patches-3.3/404-mtd-wrt160nl-trx-parser.patch new file mode 100644 index 000000000..75bfbc315 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/404-mtd-wrt160nl-trx-parser.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -156,6 +156,12 @@ config MTD_BCM63XX_PARTS + This provides partions parsing for BCM63xx devices with CFE + bootloaders. + ++config MTD_WRT160NL_PARTS ++ tristate "Linksys WRT160NL partitioning support" ++ depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL ++ ---help--- ++ Linksys WRT160NL partitioning support ++ + config MTD_MYLOADER_PARTS + tristate "MyLoader partition parsing" + depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79 +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_CHAR) += mtdchar.o diff --git a/target/linux/ar71xx/patches-3.3/405-mtd-tp-link-partition-parser.patch b/target/linux/ar71xx/patches-3.3/405-mtd-tp-link-partition-parser.patch new file mode 100644 index 000000000..021491591 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/405-mtd-tp-link-partition-parser.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -158,7 +158,7 @@ config MTD_BCM63XX_PARTS + + config MTD_WRT160NL_PARTS + tristate "Linksys WRT160NL partitioning support" +- depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL ++ depends on ATH79_MACH_WRT160NL + ---help--- + Linksys WRT160NL partitioning support + +@@ -178,6 +178,12 @@ config MTD_MYLOADER_PARTS + You will still need the parsing functions to be called by the driver + for your particular device. It won't happen automatically. + ++config MTD_TPLINK_PARTS ++ tristate "TP-Link AR7XXX/AR9XXX partitioning support" ++ depends on ATH79 ++ ---help--- ++ TBD. ++ + comment "User Modules And Translation Layers" + + config MTD_CHAR +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o + obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o + + # 'Users' - code which presents functionality to userspace. diff --git a/target/linux/ar71xx/patches-3.3/406-mtd-m25p80-allow-to-specify-max-read-size.patch b/target/linux/ar71xx/patches-3.3/406-mtd-m25p80-allow-to-specify-max-read-size.patch new file mode 100644 index 000000000..8861c615f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/406-mtd-m25p80-allow-to-specify-max-read-size.patch @@ -0,0 +1,112 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -100,6 +100,7 @@ struct m25p { + u16 addr_width; + u8 erase_opcode; + u8 *command; ++ size_t max_read_len; + }; + + static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) +@@ -352,6 +353,7 @@ static int m25p80_read(struct mtd_info * + struct m25p *flash = mtd_to_m25p(mtd); + struct spi_transfer t[2]; + struct spi_message m; ++ loff_t ofs; + + pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev), + __func__, (u32)from, len); +@@ -374,8 +376,6 @@ static int m25p80_read(struct mtd_info * + t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE; + spi_message_add_tail(&t[0], &m); + +- t[1].rx_buf = buf; +- t[1].len = len; + spi_message_add_tail(&t[1], &m); + + /* Byte count starts at zero. */ +@@ -383,13 +383,6 @@ static int m25p80_read(struct mtd_info * + + mutex_lock(&flash->lock); + +- /* Wait till previous write/erase is done. */ +- if (wait_till_ready(flash)) { +- /* REVISIT status return?? */ +- mutex_unlock(&flash->lock); +- return 1; +- } +- + /* FIXME switch to OPCODE_FAST_READ. It's required for higher + * clocks; and at this writing, every chip this driver handles + * supports that opcode. +@@ -397,11 +390,44 @@ static int m25p80_read(struct mtd_info * + + /* Set up the write data buffer. */ + flash->command[0] = OPCODE_READ; +- m25p_addr2cmd(flash, from, flash->command); + +- spi_sync(flash->spi, &m); ++ ofs = 0; ++ while (len) { ++ size_t readlen; ++ size_t done; ++ int ret; ++ ++ ret = wait_till_ready(flash); ++ if (ret) { ++ mutex_unlock(&flash->lock); ++ return 1; ++ } ++ ++ if (flash->max_read_len > 0 && ++ flash->max_read_len < len) ++ readlen = flash->max_read_len; ++ else ++ readlen = len; ++ ++ t[1].rx_buf = buf + ofs; ++ t[1].len = readlen; ++ ++ m25p_addr2cmd(flash, from + ofs, flash->command); ++ ++ spi_sync(flash->spi, &m); + +- *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE; ++ done = m.actual_length - m25p_cmdsz(flash) - ++ FAST_READ_DUMMY_BYTE; ++ if (done != readlen) { ++ mutex_unlock(&flash->lock); ++ return 1; ++ } ++ ++ ofs += done; ++ len -= done; ++ } ++ ++ *retlen = ofs; + + mutex_unlock(&flash->lock); + +@@ -925,6 +951,12 @@ static int __devinit m25p_probe(struct s + flash->mtd.erase = m25p80_erase; + flash->mtd.read = m25p80_read; + ++ if (data && data->max_read_len) { ++ flash->max_read_len = data->max_read_len; ++ dev_warn(&spi->dev, "max_read_len set to %d bytes\n", ++ flash->max_read_len); ++ } ++ + /* sst flash chips use AAI word program */ + if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) + flash->mtd.write = sst_write; +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -25,6 +25,7 @@ struct flash_platform_data { + + char *type; + ++ size_t max_read_len; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/ar71xx/patches-3.3/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-3.3/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch new file mode 100644 index 000000000..14f2de536 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -1018,7 +1018,9 @@ static int __devinit m25p_probe(struct s + /* partitions should match sector boundaries; and it may be good to + * use readonly partitions for writeprotected sectors (BP2..BP0). + */ +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ return mtd_device_parse_register(&flash->mtd, ++ data ? data->part_probes : NULL, ++ &ppdata, + data ? data->parts : NULL, + data ? data->nr_parts : 0); + } +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -24,6 +24,7 @@ struct flash_platform_data { + unsigned int nr_parts; + + char *type; ++ const char **part_probes; + + size_t max_read_len; + /* we'll likely add more ... use JEDEC IDs, etc */ diff --git a/target/linux/ar71xx/patches-3.3/408-mtd-redboot_partition_scan.patch b/target/linux/ar71xx/patches-3.3/408-mtd-redboot_partition_scan.patch new file mode 100644 index 000000000..9d7a696f1 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/408-mtd-redboot_partition_scan.patch @@ -0,0 +1,45 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -79,6 +79,11 @@ static int parse_redboot_partitions(stru + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; + while (mtd_can_have_bb(master) && +@@ -86,6 +91,7 @@ static int parse_redboot_partitions(stru + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; +@@ -99,10 +105,6 @@ static int parse_redboot_partitions(stru + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; + + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); +@@ -175,6 +177,11 @@ static int parse_redboot_partitions(stru + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; diff --git a/target/linux/ar71xx/patches-3.3/409-mtd-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-3.3/409-mtd-rb4xx_nand_driver.patch new file mode 100644 index 000000000..e1a339890 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/409-mtd-rb4xx_nand_driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -536,4 +536,8 @@ config MTD_NAND_FSMC + Enables support for NAND Flash chips on the ST Microelectronics + Flexible Static Memory Controller (FSMC) + ++config MTD_NAND_RB4XX ++ tristate "NAND flash driver for RouterBoard 4xx series" ++ depends on MTD_NAND && ATH79_MACH_RB4XX ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27 + obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-3.3/410-mtd-rb750-nand-driver.patch b/target/linux/ar71xx/patches-3.3/410-mtd-rb750-nand-driver.patch new file mode 100644 index 000000000..d67f720d6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/410-mtd-rb750-nand-driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -540,4 +540,8 @@ config MTD_NAND_RB4XX + tristate "NAND flash driver for RouterBoard 4xx series" + depends on MTD_NAND && ATH79_MACH_RB4XX + ++config MTD_NAND_RB750 ++ tristate "NAND flash driver for the RouterBoard 750" ++ depends on MTD_NAND && ATH79_MACH_RB750 ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o + obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o ++obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/target/linux/ar71xx/patches-3.3/411-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-3.3/411-mtd-cfi_cmdset_0002-force-word-write.patch new file mode 100644 index 000000000..e4e879b5b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/411-mtd-cfi_cmdset_0002-force-word-write.patch @@ -0,0 +1,61 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -39,7 +39,7 @@ + #include <linux/mtd/xip.h> + + #define AMD_BOOTLOC_BUG +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + #define MAX_WORD_RETRIES 3 + +@@ -50,7 +50,9 @@ + + static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); + static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#if !FORCE_WORD_WRITE + static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#endif + static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); + static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); + static void cfi_amdstd_sync (struct mtd_info *); +@@ -183,6 +185,7 @@ static void fixup_amd_bootblock(struct m + } + #endif + ++#if !FORCE_WORD_WRITE + static void fixup_use_write_buffers(struct mtd_info *mtd) + { + struct map_info *map = mtd->priv; +@@ -192,6 +195,7 @@ static void fixup_use_write_buffers(stru + mtd->write = cfi_amdstd_write_buffers; + } + } ++#endif /* !FORCE_WORD_WRITE */ + + /* Atmel chips don't use the same PRI format as AMD chips */ + static void fixup_convert_atmel_pri(struct mtd_info *mtd) +@@ -1374,6 +1378,7 @@ static int cfi_amdstd_write_words(struct + /* + * FIXME: interleaved mode not tested, and probably not supported! + */ ++#if !FORCE_WORD_WRITE + static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, + unsigned long adr, const u_char *buf, + int len) +@@ -1485,7 +1490,6 @@ static int __xipram do_write_buffer(stru + return ret; + } + +- + static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) + { +@@ -1564,6 +1568,7 @@ static int cfi_amdstd_write_buffers(stru + + return 0; + } ++#endif /* !FORCE_WORD_WRITE */ + + /* + * Handle devices with one erase region, that only implement diff --git a/target/linux/ar71xx/patches-3.3/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-3.3/412-mtd-m25p80-zero-partition-parser-data.patch new file mode 100644 index 000000000..a667139d0 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/412-mtd-m25p80-zero-partition-parser-data.patch @@ -0,0 +1,10 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -978,6 +978,7 @@ static int __devinit m25p_probe(struct s + if (info->flags & M25P_NO_ERASE) + flash->mtd.flags |= MTD_NO_ERASE; + ++ memset(&ppdata, '\0', sizeof(ppdata)); + ppdata.of_node = spi->dev.of_node; + flash->mtd.dev.parent = &spi->dev; + flash->page_size = info->page_size; diff --git a/target/linux/ar71xx/patches-3.3/413-mtd-ar934x-nand-driver.patch b/target/linux/ar71xx/patches-3.3/413-mtd-ar934x-nand-driver.patch new file mode 100644 index 000000000..289458fbd --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/413-mtd-ar934x-nand-driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -544,4 +544,8 @@ config MTD_NAND_RB750 + tristate "NAND flash driver for the RouterBoard 750" + depends on MTD_NAND && ATH79_MACH_RB750 + ++config MTD_NAND_AR934X ++ tristate "NAND flash driver for the Atheros AR934x SoCs" ++ depends on SOC_AR934X ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_MTD_SM_COMMON) += sm_comm + obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o + obj-$(CONFIG_MTD_NAND_SPIA) += spia.o + obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o ++obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nfc.o + obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o + obj-$(CONFIG_MTD_NAND_DENALI) += denali.o + obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o diff --git a/target/linux/ar71xx/patches-3.3/420-net-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-3.3/420-net-ar71xx_mac_driver.patch new file mode 100644 index 000000000..f11713316 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/420-net-ar71xx_mac_driver.patch @@ -0,0 +1,28 @@ +--- a/drivers/net/ethernet/atheros/Kconfig ++++ b/drivers/net/ethernet/atheros/Kconfig +@@ -5,7 +5,7 @@ + config NET_VENDOR_ATHEROS + bool "Atheros devices" + default y +- depends on PCI ++ depends on (PCI || ATH79) + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from +@@ -67,4 +67,6 @@ config ATL1C + To compile this driver as a module, choose M here. The module + will be called atl1c. + ++source drivers/net/ethernet/atheros/ag71xx/Kconfig ++ + endif # NET_VENDOR_ATHEROS +--- a/drivers/net/ethernet/atheros/Makefile ++++ b/drivers/net/ethernet/atheros/Makefile +@@ -2,6 +2,7 @@ + # Makefile for the Atheros network device drivers. + # + ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_ATL1) += atlx/ + obj-$(CONFIG_ATL2) += atlx/ + obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ar71xx/patches-3.3/422-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-3.3/422-dsa-trailer-tag-validation-fix.patch new file mode 100644 index 000000000..3e3902bac --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/422-dsa-trailer-tag-validation-fix.patch @@ -0,0 +1,11 @@ +--- a/net/dsa/tag_trailer.c ++++ b/net/dsa/tag_trailer.c +@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s + + trailer = skb_tail_pointer(skb) - 4; + if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || +- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00) ++ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00) + goto out_drop; + + source_port = trailer[1] & 7; diff --git a/target/linux/ar71xx/patches-3.3/423-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-3.3/423-dsa-add-88e6063-driver.patch new file mode 100644 index 000000000..bfb0b8e75 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/423-dsa-add-88e6063-driver.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -12,6 +12,13 @@ config NET_DSA_MV88E6060 + This enables support for the Marvell 88E6060 ethernet switch + chip. + ++config NET_DSA_MV88E6063 ++ bool "Marvell 88E6063 ethernet switch chip support" ++ select NET_DSA_TAG_TRAILER ++ ---help--- ++ This enables support for the Marvell 88E6063 ethernet switch ++ chip ++ + config NET_DSA_MV88E6XXX_NEED_PPU + bool + default n +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -1,4 +1,5 @@ + obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o ++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o + obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o + mv88e6xxx_drv-y += mv88e6xxx.o + ifdef CONFIG_NET_DSA_MV88E6123_61_65 diff --git a/target/linux/ar71xx/patches-3.3/430-drivers-link-spi-before-mtd.patch b/target/linux/ar71xx/patches-3.3/430-drivers-link-spi-before-mtd.patch new file mode 100644 index 000000000..f54861be6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/430-drivers-link-spi-before-mtd.patch @@ -0,0 +1,12 @@ +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -52,8 +52,8 @@ obj-$(CONFIG_IDE) += ide/ + obj-$(CONFIG_SCSI) += scsi/ + obj-$(CONFIG_ATA) += ata/ + obj-$(CONFIG_TARGET_CORE) += target/ +-obj-$(CONFIG_MTD) += mtd/ + obj-$(CONFIG_SPI) += spi/ ++obj-$(CONFIG_MTD) += mtd/ + obj-y += net/ + obj-$(CONFIG_ATM) += atm/ + obj-$(CONFIG_FUSION) += message/ diff --git a/target/linux/ar71xx/patches-3.3/431-spi-add-various-flags.patch b/target/linux/ar71xx/patches-3.3/431-spi-add-various-flags.patch new file mode 100644 index 000000000..67ba43f0c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/431-spi-add-various-flags.patch @@ -0,0 +1,19 @@ +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -503,6 +503,8 @@ struct spi_transfer { + dma_addr_t rx_dma; + + unsigned cs_change:1; ++ unsigned verify:1; ++ unsigned fast_write:1; + u8 bits_per_word; + u16 delay_usecs; + u32 speed_hz; +@@ -544,6 +546,7 @@ struct spi_message { + struct spi_device *spi; + + unsigned is_dma_mapped:1; ++ unsigned fast_read:1; + + /* REVISIT: we might want a flag affecting the behavior of the + * last transfer ... allowing things like "read 16 bit length L" diff --git a/target/linux/ar71xx/patches-3.3/432-spi-rb4xx-spi-driver.patch b/target/linux/ar71xx/patches-3.3/432-spi-rb4xx-spi-driver.patch new file mode 100644 index 000000000..6cfe2e832 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/432-spi-rb4xx-spi-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -288,6 +288,12 @@ config SPI_PXA2XX + config SPI_PXA2XX_PCI + def_bool SPI_PXA2XX && X86_32 && PCI + ++config SPI_RB4XX ++ tristate "Mikrotik RB4XX SPI master" ++ depends on SPI_MASTER && ATH79_MACH_RB4XX ++ help ++ SPI controller driver for the Mikrotik RB4xx series boards. ++ + config SPI_S3C24XX + tristate "Samsung S3C24XX series SPI" + depends on ARCH_S3C2410 && EXPERIMENTAL +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_PL022) += spi-pl022.o + obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o + obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o + obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o ++obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o + obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o + spi-s3c24xx-hw-y := spi-s3c24xx.o + spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o diff --git a/target/linux/ar71xx/patches-3.3/433-spi-rb4xx-cpld-driver.patch b/target/linux/ar71xx/patches-3.3/433-spi-rb4xx-cpld-driver.patch new file mode 100644 index 000000000..579315b3a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/433-spi-rb4xx-cpld-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -439,6 +439,13 @@ config SPI_TLE62X0 + sysfs interface, with each line presented as a kind of GPIO + exposing both switch control and diagnostic feedback. + ++config SPI_RB4XX_CPLD ++ tristate "MikroTik RB4XX CPLD driver" ++ depends on ATH79_MACH_RB4XX ++ help ++ SPI driver for the Xilinx CPLD chip present on the ++ MikroTik RB4xx boards. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx. + obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o + obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o ++obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o + obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o + spi-s3c24xx-hw-y := spi-s3c24xx.o + spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o diff --git a/target/linux/ar71xx/patches-3.3/434-spi-ap83_spi_controller.patch b/target/linux/ar71xx/patches-3.3/434-spi-ap83_spi_controller.patch new file mode 100644 index 000000000..b4dbcd470 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/434-spi-ap83_spi_controller.patch @@ -0,0 +1,27 @@ +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o + # SPI master controller drivers (bus) + obj-$(CONFIG_SPI_ALTERA) += spi-altera.o + obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o ++obj-$(CONFIG_SPI_AP83) += spi-ap83.o + obj-$(CONFIG_SPI_ATH79) += spi-ath79.o + obj-$(CONFIG_SPI_AU1550) += spi-au1550.o + obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -59,6 +59,14 @@ config SPI_ALTERA + help + This is the driver for the Altera SPI Controller. + ++config SPI_AP83 ++ tristate "Atheros AP83 specific SPI Controller" ++ depends on SPI_MASTER && ATH79_MACH_AP83 ++ select SPI_BITBANG ++ help ++ This is a specific SPI controller driver for the Atheros AP83 ++ reference board. ++ + config SPI_ATH79 + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" + depends on ATH79 && GENERIC_GPIO diff --git a/target/linux/ar71xx/patches-3.3/435-spi-vsc7385_driver.patch b/target/linux/ar71xx/patches-3.3/435-spi-vsc7385_driver.patch new file mode 100644 index 000000000..14626879b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/435-spi-vsc7385_driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -454,6 +454,11 @@ config SPI_RB4XX_CPLD + SPI driver for the Xilinx CPLD chip present on the + MikroTik RB4xx boards. + ++config SPI_VSC7385 ++ tristate "Vitesse VSC7385 ethernet switch driver" ++ help ++ SPI driver for the Vitesse VSC7385 ethernet switch. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -61,5 +61,5 @@ obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp. + obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o + obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o + obj-$(CONFIG_SPI_TXX9) += spi-txx9.o ++obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o +- diff --git a/target/linux/ar71xx/patches-3.3/440-leds-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-3.3/440-leds-wndr3700-usb-led-driver.patch new file mode 100644 index 000000000..88d09089d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/440-leds-wndr3700-usb-led-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -418,6 +418,13 @@ config LEDS_TRIGGERS + These triggers allow kernel events to drive the LEDs and can + be configured via sysfs. If unsure, say Y. + ++config LEDS_WNDR3700_USB ++ tristate "NETGEAR WNDR3700 USB LED driver" ++ depends on LEDS_CLASS && ATH79_MACH_WNDR3700 ++ help ++ This option enables support for the USB LED found on the ++ NETGEAR WNDR3700 board. ++ + comment "LED Triggers" + + config LEDS_TRIGGER_TIMER +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903 + obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o + obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o + obj-$(CONFIG_LEDS_PWM) += leds-pwm.o ++obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o + obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o + obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o + obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o diff --git a/target/linux/ar71xx/patches-3.3/441-leds-rb750-led-driver.patch b/target/linux/ar71xx/patches-3.3/441-leds-rb750-led-driver.patch new file mode 100644 index 000000000..e8073a2e8 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/441-leds-rb750-led-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -425,6 +425,10 @@ config LEDS_WNDR3700_USB + This option enables support for the USB LED found on the + NETGEAR WNDR3700 board. + ++config LEDS_RB750 ++ tristate "LED driver for the Mikrotik RouterBOARD 750" ++ depends on LEDS_CLASS && ATH79_MACH_RB750 ++ + comment "LED Triggers" + + config LEDS_TRIGGER_TIMER +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359 + obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o + obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o + obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o ++obj-$(CONFIG_LEDS_RB750) += leds-rb750.o + obj-$(CONFIG_LEDS_NS2) += leds-ns2.o + obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o + obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o diff --git a/target/linux/ar71xx/patches-3.3/450-gpio-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-3.3/450-gpio-nxp-74hc153-gpio-chip-driver.patch new file mode 100644 index 000000000..1e67abfdd --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/450-gpio-nxp-74hc153-gpio-chip-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -489,4 +489,13 @@ config GPIO_TPS65910 + help + Select this option to enable GPIO driver for the TPS65910 + chip family. ++ ++comment "Other GPIO expanders" ++ ++config GPIO_NXP_74HC153 ++ tristate "NXP 74HC153 Dual 4-input multiplexer" ++ help ++ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This ++ provides a GPIO interface supporting input mode only. ++ + endif +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2 + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o + obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o ++obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o + obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o + obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o + obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o diff --git a/target/linux/ar71xx/patches-3.3/460-spi-bitbang-export-spi_bitbang_bufs.patch b/target/linux/ar71xx/patches-3.3/460-spi-bitbang-export-spi_bitbang_bufs.patch new file mode 100644 index 000000000..919b85cb7 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/460-spi-bitbang-export-spi_bitbang_bufs.patch @@ -0,0 +1,28 @@ +--- a/drivers/spi/spi-bitbang.c ++++ b/drivers/spi/spi-bitbang.c +@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi + } + EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); + +-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) ++int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) + { + struct spi_bitbang_cs *cs = spi->controller_state; + unsigned nsecs = cs->nsecs; + + return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); + } ++EXPORT_SYMBOL_GPL(spi_bitbang_bufs); + + /*----------------------------------------------------------------------*/ + +--- a/include/linux/spi/spi_bitbang.h ++++ b/include/linux/spi/spi_bitbang.h +@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s + extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m); + extern int spi_bitbang_setup_transfer(struct spi_device *spi, + struct spi_transfer *t); ++extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t); + + /* start or stop queue processing */ + extern int spi_bitbang_start(struct spi_bitbang *spi); diff --git a/target/linux/ar71xx/patches-3.3/461-spi-add-type-field-to-spi_transfer.patch b/target/linux/ar71xx/patches-3.3/461-spi-add-type-field-to-spi_transfer.patch new file mode 100644 index 000000000..850f24a07 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/461-spi-add-type-field-to-spi_transfer.patch @@ -0,0 +1,23 @@ +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -406,6 +406,12 @@ extern struct spi_master *spi_busnum_to_ + + /*---------------------------------------------------------------------------*/ + ++enum spi_transfer_type { ++ SPI_TRANSFER_GENERIC = 0, ++ SPI_TRANSFER_FLASH_READ_CMD, ++ SPI_TRANSFER_FLASH_READ_DATA, ++}; ++ + /* + * I/O INTERFACE between SPI controller and protocol drivers + * +@@ -508,6 +514,7 @@ struct spi_transfer { + u8 bits_per_word; + u16 delay_usecs; + u32 speed_hz; ++ enum spi_transfer_type type; + + struct list_head transfer_list; + }; diff --git a/target/linux/ar71xx/patches-3.3/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-3.3/462-mtd-m25p80-set-spi-transfer-type.patch new file mode 100644 index 000000000..48e69c0d6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/462-mtd-m25p80-set-spi-transfer-type.patch @@ -0,0 +1,15 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -372,10 +372,12 @@ static int m25p80_read(struct mtd_info * + * OPCODE_FAST_READ (if available) is faster. + * Should add 1 byte DUMMY_BYTE. + */ ++ t[0].type = SPI_TRANSFER_FLASH_READ_CMD; + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE; + spi_message_add_tail(&t[0], &m); + ++ t[1].type = SPI_TRANSFER_FLASH_READ_DATA; + spi_message_add_tail(&t[1], &m); + + /* Byte count starts at zero. */ diff --git a/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch new file mode 100644 index 000000000..9ccc4a45e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch @@ -0,0 +1,185 @@ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -37,6 +37,11 @@ + + #define ATH79_SPI_CS_LINE_MAX 2 + ++enum ath79_spi_state { ++ ATH79_SPI_STATE_WAIT_CMD = 0, ++ ATH79_SPI_STATE_WAIT_READ, ++}; ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -44,6 +49,11 @@ struct ath79_spi { + void __iomem *base; + struct clk *clk; + unsigned rrw_delay; ++ ++ enum ath79_spi_state state; ++ u32 clk_div; ++ unsigned long read_addr; ++ unsigned long ahb_rate; + }; + + static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +@@ -111,9 +121,6 @@ static void ath79_spi_enable(struct ath7 + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); +- +- /* TODO: setup speed? */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + } + + static void ath79_spi_disable(struct ath79_spi *sp) +@@ -232,6 +239,110 @@ static u32 ath79_spi_txrx_mode0(struct s + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); + } + ++static int ath79_spi_do_read_flash_data(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++ ++ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len); ++ ++ /* enable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); ++ ++ /* restore IOC register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); ++ ++ return t->len; ++} ++ ++static int ath79_spi_do_read_flash_cmd(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ int len; ++ const u8 *p; ++ ++ sp->read_addr = 0; ++ ++ len = t->len - 1; ++ p = t->tx_buf; ++ ++ while (len--) { ++ p++; ++ sp->read_addr <<= 8; ++ sp->read_addr |= *p; ++ } ++ ++ return t->len; ++} ++ ++static bool ath79_spi_is_read_cmd(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ return t->type == SPI_TRANSFER_FLASH_READ_CMD; ++} ++ ++static bool ath79_spi_is_data_read(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ return t->type == SPI_TRANSFER_FLASH_READ_DATA; ++} ++ ++static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ int ret; ++ ++ switch (sp->state) { ++ case ATH79_SPI_STATE_WAIT_CMD: ++ if (ath79_spi_is_read_cmd(spi, t)) { ++ ret = ath79_spi_do_read_flash_cmd(spi, t); ++ sp->state = ATH79_SPI_STATE_WAIT_READ; ++ } else { ++ ret = spi_bitbang_bufs(spi, t); ++ } ++ break; ++ ++ case ATH79_SPI_STATE_WAIT_READ: ++ if (ath79_spi_is_data_read(spi, t)) { ++ ret = ath79_spi_do_read_flash_data(spi, t); ++ } else { ++ dev_warn(&spi->dev, "flash data read expected\n"); ++ ret = -EIO; ++ } ++ sp->state = ATH79_SPI_STATE_WAIT_CMD; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ return ret; ++} ++ ++static int ath79_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ struct ath79_spi_controller_data *cdata; ++ int ret; ++ ++ ret = spi_bitbang_setup_transfer(spi, t); ++ if (ret) ++ return ret; ++ ++ cdata = spi->controller_data; ++ if (cdata->is_flash) ++ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs; ++ else ++ sp->bitbang.txrx_bufs = spi_bitbang_bufs; ++ ++ return ret; ++} ++ + static __devinit int ath79_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -254,6 +365,8 @@ static __devinit int ath79_spi_probe(str + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + ++ sp->state = ATH79_SPI_STATE_WAIT_CMD; ++ + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; + master->bus_num = pdata->bus_num; +@@ -262,7 +375,7 @@ static __devinit int ath79_spi_probe(str + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ath79_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; +- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ sp->bitbang.setup_transfer = ath79_spi_setup_transfer; + sp->bitbang.flags = SPI_CS_HIGH; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -287,7 +400,8 @@ static __devinit int ath79_spi_probe(str + if (ret) + goto err_clk_put; + +- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); ++ sp->ahb_rate = clk_get_rate(sp->clk); ++ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ); + if (!rate) { + ret = -EINVAL; + goto err_clk_disable; +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -24,6 +24,7 @@ enum ath79_spi_cs_type { + struct ath79_spi_controller_data { + enum ath79_spi_cs_type cs_type; + unsigned cs_line; ++ bool is_flash; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ diff --git a/target/linux/ar71xx/patches-3.3/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ar71xx/patches-3.3/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch new file mode 100644 index 000000000..7912384d3 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch @@ -0,0 +1,111 @@ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H ++#define __ASM_MACH_ATH79_MANGLE_PORT_H ++ ++#ifdef CONFIG_PCI ++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); ++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); ++#else ++#define ath79_pci_swizzle_b(port) (port) ++#define ath79_pci_swizzle_w(port) (port) ++#endif ++ ++#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) ++#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) ++#define __swizzle_addr_l(port) (port) ++#define __swizzle_addr_q(port) (port) ++ ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) (x) ++# define __mem_ioswabw(a, x) cpu_to_le16(x) ++# define ioswabl(a, x) (x) ++# define __mem_ioswabl(a, x) cpu_to_le32(x) ++# define ioswabq(a, x) (x) ++# define __mem_ioswabq(a, x) cpu_to_le64(x) ++ ++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -13,6 +13,7 @@ + */ + + #include <linux/init.h> ++#include <linux/export.h> + #include <linux/pci.h> + #include <linux/resource.h> + #include <linux/platform_device.h> +@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st + static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; + static unsigned ath79_pci_nr_irqs __initdata; + ++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); ++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); ++ + static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { + { + .slot = 17, +@@ -202,12 +206,50 @@ ath79_register_pci_ar724x(int id, + return pdev; + } + ++static inline bool ar71xx_is_pci_addr(unsigned long port) ++{ ++ unsigned long phys = CPHYSADDR(port); ++ ++ return (phys >= AR71XX_PCI_MEM_BASE && ++ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); ++} ++ ++static unsigned long ar71xx_pci_swizzle_b(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; ++} ++ ++static unsigned long ar71xx_pci_swizzle_w(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; ++} ++ ++unsigned long ath79_pci_swizzle_b(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_b) ++ return __ath79_pci_swizzle_b(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_b); ++ ++unsigned long ath79_pci_swizzle_w(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_w) ++ return __ath79_pci_swizzle_w(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_w); ++ + int __init ath79_register_pci(void) + { + struct platform_device *pdev = NULL; + + if (soc_is_ar71xx()) { + pdev = ath79_register_pci_ar71xx(); ++ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; ++ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; + } else if (soc_is_ar724x()) { + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, diff --git a/target/linux/ar71xx/patches-3.3/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-3.3/500-MIPS-fw-myloader.patch new file mode 100644 index 000000000..f269763ed --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/500-MIPS-fw-myloader.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -175,6 +175,7 @@ endif + # + libs-$(CONFIG_ARC) += arch/mips/fw/arc/ + libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ ++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ + libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ + libs-y += arch/mips/fw/lib/ + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -981,6 +981,9 @@ config MIPS_NILE4 + config MIPS_DISABLE_OBSOLETE_IDE + bool + ++config MYLOADER ++ bool ++ + config SYNC_R4K + bool + diff --git a/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch new file mode 100644 index 000000000..bab4f701d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch @@ -0,0 +1,81 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -15,6 +15,7 @@ + #include <linux/init.h> + #include <linux/delay.h> + #include <linux/irq.h> ++#include <linux/etherdevice.h> + #include <linux/platform_device.h> + #include <linux/ath9k_platform.h> + +@@ -22,6 +23,7 @@ + #include <asm/mach-ath79/ar71xx_regs.h> + #include "dev-wmac.h" + ++static u8 ath79_wmac_mac[ETH_ALEN]; + static struct ath9k_platform_data ath79_wmac_data; + + static struct resource ath79_wmac_resources[] = { +@@ -134,7 +136,7 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + +-void __init ath79_register_wmac(u8 *cal_data) ++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) + ar913x_wmac_setup(); +@@ -151,5 +153,10 @@ void __init ath79_register_wmac(u8 *cal_ + memcpy(ath79_wmac_data.eeprom_data, cal_data, + sizeof(ath79_wmac_data.eeprom_data)); + ++ if (mac_addr) { ++ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac)); ++ ath79_wmac_data.macaddr = ath79_wmac_mac; ++ } ++ + platform_device_register(&ath79_wmac_device); + } +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -12,6 +12,6 @@ + #ifndef _ATH79_DEV_WMAC_H + #define _ATH79_DEV_WMAC_H + +-void ath79_register_wmac(u8 *cal_data); ++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + + #endif /* _ATH79_DEV_WMAC_H */ +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -98,7 +98,7 @@ static void __init ap81_setup(void) + ap81_gpio_keys); + ath79_register_spi(&ap81_spi_data, ap81_spi_info, + ARRAY_SIZE(ap81_spi_info)); +- ath79_register_wmac(cal_data); ++ ath79_register_wmac(cal_data, NULL); + ath79_register_usb(); + } + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -134,7 +134,7 @@ static void __init db120_setup(void) + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); ++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); + } + +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -91,7 +91,7 @@ static void __init ap121_setup(void) + ath79_register_spi(&ap121_spi_data, ap121_spi_info, + ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(cal_data); ++ ath79_register_wmac(cal_data, NULL); + } + + MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", diff --git a/target/linux/ar71xx/patches-3.3/502-MIPS-ath79-export-ath79_gpio_base.patch b/target/linux/ar71xx/patches-3.3/502-MIPS-ath79-export-ath79_gpio_base.patch new file mode 100644 index 000000000..0a218a684 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/502-MIPS-ath79-export-ath79_gpio_base.patch @@ -0,0 +1,23 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -25,7 +25,9 @@ + #include <asm/mach-ath79/ath79.h> + #include "common.h" + +-static void __iomem *ath79_gpio_base; ++void __iomem *ath79_gpio_base; ++EXPORT_SYMBOL_GPL(ath79_gpio_base); ++ + static unsigned long ath79_gpio_count; + static DEFINE_SPINLOCK(ath79_gpio_lock); + +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -110,6 +110,7 @@ static inline int soc_is_qca955x(void) + } + + extern void __iomem *ath79_ddr_base; ++extern void __iomem *ath79_gpio_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; + diff --git a/target/linux/ar71xx/patches-3.3/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-3.3/503-MIPS-ath79-add-flash-acquire-release.patch new file mode 100644 index 000000000..81350ca3b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/503-MIPS-ath79-add-flash-acquire-release.patch @@ -0,0 +1,37 @@ +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -22,6 +22,7 @@ + #include "common.h" + + static DEFINE_SPINLOCK(ath79_device_reset_lock); ++static DEFINE_MUTEX(ath79_flash_mutex); + + u32 ath79_cpu_freq; + EXPORT_SYMBOL_GPL(ath79_cpu_freq); +@@ -109,3 +110,16 @@ void ath79_device_reset_clear(u32 mask) + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); + } + EXPORT_SYMBOL_GPL(ath79_device_reset_clear); ++ ++void ath79_flash_acquire(void) ++{ ++ mutex_lock(&ath79_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ath79_flash_acquire); ++ ++void ath79_flash_release(void) ++{ ++ mutex_unlock(&ath79_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ath79_flash_release); ++ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -137,4 +137,7 @@ static inline u32 ath79_reset_rr(unsigne + void ath79_device_reset_set(u32 mask); + void ath79_device_reset_clear(u32 mask); + ++void ath79_flash_acquire(void); ++void ath79_flash_release(void); ++ + #endif /* __ASM_MACH_ATH79_H */ diff --git a/target/linux/ar71xx/patches-3.3/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-3.3/504-MIPS-ath79-add-ath79_device_reset_get.patch new file mode 100644 index 000000000..55780996f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/504-MIPS-ath79-add-ath79_device_reset_get.patch @@ -0,0 +1,45 @@ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -136,6 +136,7 @@ static inline u32 ath79_reset_rr(unsigne + + void ath79_device_reset_set(u32 mask); + void ath79_device_reset_clear(u32 mask); ++u32 ath79_device_reset_get(u32 mask); + + void ath79_flash_acquire(void); + void ath79_flash_release(void); +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -111,6 +111,32 @@ void ath79_device_reset_clear(u32 mask) + } + EXPORT_SYMBOL_GPL(ath79_device_reset_clear); + ++u32 ath79_device_reset_get(u32 mask) ++{ ++ unsigned long flags; ++ u32 reg; ++ u32 ret; ++ ++ if (soc_is_ar71xx()) ++ reg = AR71XX_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar724x()) ++ reg = AR724X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar913x()) ++ reg = AR913X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar933x()) ++ reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; ++ else ++ BUG(); ++ ++ spin_lock_irqsave(&ath79_device_reset_lock, flags); ++ ret = ath79_reset_rr(reg); ++ spin_unlock_irqrestore(&ath79_device_reset_lock, flags); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ath79_device_reset_get); ++ + void ath79_flash_acquire(void) + { + mutex_lock(&ath79_flash_mutex); diff --git a/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch new file mode 100644 index 000000000..6b09fc0a9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg + void ath79_gpio_function_enable(u32 mask); + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); ++void ath79_gpio_output_select(unsigned gpio, u8 val); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set, + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + ++void __init ath79_gpio_output_select(unsigned gpio, u8 val) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ unsigned int reg; ++ u32 t, s; ++ ++ BUG_ON(!soc_is_ar934x()); ++ ++ if (gpio >= AR934X_GPIO_COUNT) ++ return; ++ ++ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); ++ s = 8 * (gpio % 4); ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ t = __raw_readl(base + reg); ++ t &= ~(0xff << s); ++ t |= val << s; ++ __raw_writel(t, base + reg); ++ ++ /* flush write */ ++ (void) __raw_readl(base + reg); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++} ++ + void __init ath79_gpio_init(void) + { + int err; diff --git a/target/linux/ar71xx/patches-3.3/506-MIPS-ath79-prom-parse-redboot-args.patch b/target/linux/ar71xx/patches-3.3/506-MIPS-ath79-prom-parse-redboot-args.patch new file mode 100644 index 000000000..aab959b90 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/506-MIPS-ath79-prom-parse-redboot-args.patch @@ -0,0 +1,86 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -19,6 +19,8 @@ + + #include "common.h" + ++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata; ++ + static inline int is_valid_ram_addr(void *addr) + { + if (((u32) addr > KSEG0) && +@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void + return 0; + } + ++static void __init ath79_prom_append_cmdline(const char *name, ++ const char *value) ++{ ++ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf), ++ " %s=%s", name, value); ++ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); ++} ++ ++static const char * __init ath79_prom_find_env(char **envp, const char *name) ++{ ++ const char *ret = NULL; ++ int len; ++ char **p; ++ ++ if (!is_valid_ram_addr(envp)) ++ return NULL; ++ ++ len = strlen(name); ++ for (p = envp; is_valid_ram_addr(*p); p++) { ++ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { ++ ret = *p + len + 1; ++ break; ++ } ++ ++ /* RedBoot env comes in pointer pairs - key, value */ ++ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) ++ if (is_valid_ram_addr(*(++p))) { ++ ret = *p; ++ break; ++ } ++ } ++ ++ return ret; ++} ++ + static __init void ath79_prom_init_cmdline(int argc, char **argv) + { + int i; +@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli + + void __init prom_init(void) + { ++ const char *env; ++ char **envp; ++ + ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); ++ ++ envp = (char **)fw_arg2; ++ if (!strstr(arcs_cmdline, "ethaddr=")) { ++ env = ath79_prom_find_env(envp, "ethaddr"); ++ if (env) ++ ath79_prom_append_cmdline("ethaddr", env); ++ } ++ ++ if (!strstr(arcs_cmdline, "board=")) { ++ env = ath79_prom_find_env(envp, "board"); ++ if (env) { ++ /* Workaround for buggy bootloaders */ ++ if (strcmp(env, "RouterStation") == 0 || ++ strcmp(env, "Ubiquiti AR71xx-based board") == 0) ++ env = "UBNT-RS"; ++ ++ if (strcmp(env, "RouterStation PRO") == 0) ++ env = "UBNT-RSPRO"; ++ ++ ath79_prom_append_cmdline("board", env); ++ } ++ } + } + + void __init prom_free_prom_memory(void) diff --git a/target/linux/ar71xx/patches-3.3/507-MIPS-ath79-prom-add-myloader-support.patch b/target/linux/ar71xx/patches-3.3/507-MIPS-ath79-prom-add-myloader-support.patch new file mode 100644 index 000000000..67c1faf9b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/507-MIPS-ath79-prom-add-myloader-support.patch @@ -0,0 +1,58 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -16,6 +16,7 @@ + + #include <asm/bootinfo.h> + #include <asm/addrspace.h> ++#include <asm/fw/myloader/myloader.h> + + #include "common.h" + +@@ -69,6 +70,37 @@ static const char * __init ath79_prom_fi + return ret; + } + ++static int __init ath79_prom_init_myloader(void) ++{ ++ struct myloader_info *mylo; ++ char mac_buf[32]; ++ unsigned char *mac; ++ ++ mylo = myloader_get_info(); ++ if (!mylo) ++ return 0; ++ ++ switch (mylo->did) { ++ case DEVID_COMPEX_WP543: ++ ath79_prom_append_cmdline("board", "WP543"); ++ break; ++ case DEVID_COMPEX_WPE72: ++ ath79_prom_append_cmdline("board", "WPE72"); ++ break; ++ default: ++ pr_warn("prom: unknown device id: %x\n", mylo->did); ++ return 0; ++ } ++ ++ mac = mylo->macs[0]; ++ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++ ++ ath79_prom_append_cmdline("ethaddr", mac_buf); ++ ++ return 1; ++} ++ + static __init void ath79_prom_init_cmdline(int argc, char **argv) + { + int i; +@@ -88,6 +120,9 @@ void __init prom_init(void) + const char *env; + char **envp; + ++ if (ath79_prom_init_myloader()) ++ return; ++ + ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); + + envp = (char **)fw_arg2; diff --git a/target/linux/ar71xx/patches-3.3/508-MIPS-ath79-prom-image-command-line-hack.patch b/target/linux/ar71xx/patches-3.3/508-MIPS-ath79-prom-image-command-line-hack.patch new file mode 100644 index 000000000..72a3b5664 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/508-MIPS-ath79-prom-image-command-line-hack.patch @@ -0,0 +1,57 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi + return ret; + } + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static int __init ath79_use_image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return 0; ++ ++ if (replace) { ++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++ ++ return 1; ++} ++#else ++static inline int ath79_use_image_cmdline(void) { return 0; } ++#endif ++ + static int __init ath79_prom_init_myloader(void) + { + struct myloader_info *mylo; +@@ -98,6 +127,8 @@ static int __init ath79_prom_init_myload + + ath79_prom_append_cmdline("ethaddr", mac_buf); + ++ ath79_use_image_cmdline(); ++ + return 1; + } + +@@ -105,6 +136,9 @@ static __init void ath79_prom_init_cmdli + { + int i; + ++ if (ath79_use_image_cmdline()) ++ return; ++ + if (!is_valid_ram_addr(argv)) + return; + diff --git a/target/linux/ar71xx/patches-3.3/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-3.3/509-MIPS-ath79-process-board-kernel-option.patch new file mode 100644 index 000000000..9236c6686 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/509-MIPS-ath79-process-board-kernel-option.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -225,6 +225,8 @@ void __init plat_time_init(void) + mips_hpt_frequency = clk_get_rate(clk) / 2; + } + ++__setup("board=", mips_machtype_setup); ++ + static int __init ath79_setup(void) + { + ath79_gpio_init(); diff --git a/target/linux/ar71xx/patches-3.3/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch b/target/linux/ar71xx/patches-3.3/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch new file mode 100644 index 000000000..2d2235e29 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -24,7 +24,10 @@ + #include "dev-wmac.h" + + static u8 ath79_wmac_mac[ETH_ALEN]; +-static struct ath9k_platform_data ath79_wmac_data; ++ ++static struct ath9k_platform_data ath79_wmac_data = { ++ .led_pin = -1, ++}; + + static struct resource ath79_wmac_resources[] = { + { diff --git a/target/linux/ar71xx/patches-3.3/511-MIPS-ath79-add-ath79_set_usb_power_gpio.patch b/target/linux/ar71xx/patches-3.3/511-MIPS-ath79-add-ath79_set_usb_power_gpio.patch new file mode 100644 index 000000000..91a793d5e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/511-MIPS-ath79-add-ath79_set_usb_power_gpio.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -15,6 +15,7 @@ + #include <linux/init.h> + #include <linux/delay.h> + #include <linux/irq.h> ++#include <linux/gpio.h> + #include <linux/dma-mapping.h> + #include <linux/platform_device.h> + #include <linux/usb/ehci_pdriver.h> +@@ -282,3 +283,26 @@ void __init ath79_register_usb(void) + else + BUG(); + } ++ ++void __init ath79_set_usb_power_gpio(unsigned int gpio, unsigned long flags, ++ const char *label) ++{ ++ int err; ++ ++ err = gpio_request_one(gpio, flags, label); ++ if (err) { ++ pr_err("ath79: can't setup GPIO%u (%s), err=%d\n", ++ gpio, label, err); ++ return; ++ } ++ ++ err = gpio_export(gpio, false); ++ if (err) { ++ pr_err("ath79: can't export GPIO%u (%s), err=%d\n", ++ gpio, label, err); ++ } ++ ++ return; ++} ++ ++ +--- a/arch/mips/ath79/dev-usb.h ++++ b/arch/mips/ath79/dev-usb.h +@@ -13,5 +13,7 @@ + #define _ATH79_DEV_USB_H + + void ath79_register_usb(void); ++void ath79_set_usb_power_gpio(unsigned int gpio, unsigned long flags, ++ const char *label); + + #endif /* _ATH79_DEV_USB_H */ diff --git a/target/linux/ar71xx/patches-3.3/520-MIPS-ath79-enable-UART-function.patch b/target/linux/ar71xx/patches-3.3/520-MIPS-ath79-enable-UART-function.patch new file mode 100644 index 000000000..1cb407f83 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/520-MIPS-ath79-enable-UART-function.patch @@ -0,0 +1,18 @@ +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -87,6 +87,15 @@ void __init ath79_register_uart(void) + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + ++ if (soc_is_ar71xx()) ++ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar724x()) ++ ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar913x()) ++ ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar933x()) ++ ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); ++ + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || diff --git a/target/linux/ar71xx/patches-3.3/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-3.3/521-MIPS-ath79-enable-UART-for-early_serial.patch new file mode 100644 index 000000000..489bc9673 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/521-MIPS-ath79-enable-UART-for-early_serial.patch @@ -0,0 +1,61 @@ +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned + /* nothing to do */ + } + ++static void prom_enable_uart(u32 id) ++{ ++ void __iomem *gpio_base; ++ u32 uart_en; ++ u32 t; ++ ++ switch (id) { ++ case REV_ID_MAJOR_AR71XX: ++ uart_en = AR71XX_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR7240: ++ case REV_ID_MAJOR_AR7241: ++ case REV_ID_MAJOR_AR7242: ++ uart_en = AR724X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR913X: ++ uart_en = AR913X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR9330: ++ case REV_ID_MAJOR_AR9331: ++ uart_en = AR933X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR9341: ++ case REV_ID_MAJOR_AR9342: ++ case REV_ID_MAJOR_AR9344: ++ /* TODO */ ++ default: ++ return; ++ } ++ ++ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE)); ++ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); ++ t |= uart_en; ++ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); ++} ++ + static void prom_putchar_init(void) + { + void __iomem *base; +@@ -85,8 +125,10 @@ static void prom_putchar_init(void) + + default: + _prom_putchar = prom_putchar_dummy; +- break; ++ return; + } ++ ++ prom_enable_uart(id); + } + + void prom_putchar(unsigned char ch) diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch new file mode 100644 index 000000000..8a11a70d1 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch @@ -0,0 +1,304 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -21,6 +21,10 @@ + #include <linux/bitops.h> + + #define AR71XX_APB_BASE 0x18000000 ++#define AR71XX_GE0_BASE 0x19000000 ++#define AR71XX_GE0_SIZE 0x10000 ++#define AR71XX_GE1_BASE 0x1a000000 ++#define AR71XX_GE1_SIZE 0x10000 + #define AR71XX_EHCI_BASE 0x1b000000 + #define AR71XX_EHCI_SIZE 0x1000 + #define AR71XX_OHCI_BASE 0x1c000000 +@@ -40,6 +44,8 @@ + #define AR71XX_PLL_SIZE 0x100 + #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) + #define AR71XX_RESET_SIZE 0x100 ++#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR71XX_MII_SIZE 0x100 + + #define AR71XX_PCI_MEM_BASE 0x10000000 + #define AR71XX_PCI_MEM_SIZE 0x07000000 +@@ -82,17 +88,23 @@ + + #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) + #define AR933X_UART_SIZE 0x14 ++#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR933X_GMAC_SIZE 0x04 + #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR933X_WMAC_SIZE 0x20000 + #define AR933X_EHCI_BASE 0x1b000000 + #define AR933X_EHCI_SIZE 0x1000 + ++#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR934X_GMAC_SIZE 0x14 + #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR934X_WMAC_SIZE 0x20000 + #define AR934X_EHCI_BASE 0x1b000000 + #define AR934X_EHCI_SIZE 0x200 + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 ++#define AR934X_NFC_BASE 0x1b000200 ++#define AR934X_NFC_SIZE 0xb8 + + #define QCA955X_PCI_MEM_BASE0 0x10000000 + #define QCA955X_PCI_MEM_BASE1 0x12000000 +@@ -112,6 +124,10 @@ + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x200 ++#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA955X_GMAC_SIZE 0x40 ++#define QCA955X_NFC_BASE 0x1b000200 ++#define QCA955X_NFC_SIZE 0xb8 + + /* + * DDR_CTRL block +@@ -167,6 +183,9 @@ + #define AR71XX_AHB_DIV_SHIFT 20 + #define AR71XX_AHB_DIV_MASK 0x7 + ++#define AR71XX_ETH0_PLL_SHIFT 17 ++#define AR71XX_ETH1_PLL_SHIFT 19 ++ + #define AR724X_PLL_REG_CPU_CONFIG 0x00 + #define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +@@ -179,6 +198,8 @@ + #define AR724X_DDR_DIV_SHIFT 22 + #define AR724X_DDR_DIV_MASK 0x3 + ++#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c ++ + #define AR913X_PLL_REG_CPU_CONFIG 0x00 + #define AR913X_PLL_REG_ETH_CONFIG 0x04 + #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +@@ -191,6 +212,9 @@ + #define AR913X_AHB_DIV_SHIFT 19 + #define AR913X_AHB_DIV_MASK 0x1 + ++#define AR913X_ETH0_PLL_SHIFT 20 ++#define AR913X_ETH1_PLL_SHIFT 22 ++ + #define AR933X_PLL_CPU_CONFIG_REG 0x00 + #define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +@@ -212,6 +236,8 @@ + #define AR934X_PLL_CPU_CONFIG_REG 0x00 + #define AR934X_PLL_DDR_CONFIG_REG 0x04 + #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 ++#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + + #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -244,6 +270,8 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 +@@ -370,16 +398,50 @@ + #define AR913X_RESET_USB_HOST BIT(5) + #define AR913X_RESET_USB_PHY BIT(4) + ++#define AR933X_RESET_GE1_MDIO BIT(23) ++#define AR933X_RESET_GE0_MDIO BIT(22) ++#define AR933X_RESET_GE1_MAC BIT(13) + #define AR933X_RESET_WMAC BIT(11) ++#define AR933X_RESET_GE0_MAC BIT(9) + #define AR933X_RESET_USB_HOST BIT(5) + #define AR933X_RESET_USB_PHY BIT(4) + #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + ++#define AR934X_RESET_HOST BIT(31) ++#define AR934X_RESET_SLIC BIT(30) ++#define AR934X_RESET_HDMA BIT(29) ++#define AR934X_RESET_EXTERNAL BIT(28) ++#define AR934X_RESET_RTC BIT(27) ++#define AR934X_RESET_PCIE_EP_INT BIT(26) ++#define AR934X_RESET_CHKSUM_ACC BIT(25) ++#define AR934X_RESET_FULL_CHIP BIT(24) ++#define AR934X_RESET_GE1_MDIO BIT(23) ++#define AR934X_RESET_GE0_MDIO BIT(22) ++#define AR934X_RESET_CPU_NMI BIT(21) ++#define AR934X_RESET_CPU_COLD BIT(20) ++#define AR934X_RESET_HOST_RESET_INT BIT(19) ++#define AR934X_RESET_PCIE_EP BIT(18) ++#define AR934X_RESET_UART1 BIT(17) ++#define AR934X_RESET_DDR BIT(16) ++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define AR934X_RESET_NANDF BIT(14) ++#define AR934X_RESET_GE1_MAC BIT(13) ++#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) + #define AR934X_RESET_USB_PHY_ANALOG BIT(11) ++#define AR934X_RESET_HOST_DMA_INT BIT(10) ++#define AR934X_RESET_GE0_MAC BIT(9) ++#define AR934X_RESET_ETH_SWITCH BIT(8) ++#define AR934X_RESET_PCIE_PHY BIT(7) ++#define AR934X_RESET_PCIE BIT(6) + #define AR934X_RESET_USB_HOST BIT(5) + #define AR934X_RESET_USB_PHY BIT(4) + #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) ++#define AR934X_RESET_LUT BIT(2) ++#define AR934X_RESET_MBOX BIT(1) ++#define AR934X_RESET_I2S BIT(0) + ++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) ++#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + + #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +@@ -520,6 +582,14 @@ + #define AR71XX_GPIO_REG_INT_ENABLE 0x24 + #define AR71XX_GPIO_REG_FUNC 0x28 + ++#define AR934X_GPIO_REG_OUT_FUNC0 0x2c ++#define AR934X_GPIO_REG_OUT_FUNC1 0x30 ++#define AR934X_GPIO_REG_OUT_FUNC2 0x34 ++#define AR934X_GPIO_REG_OUT_FUNC3 0x38 ++#define AR934X_GPIO_REG_OUT_FUNC4 0x3c ++#define AR934X_GPIO_REG_OUT_FUNC5 0x40 ++#define AR934X_GPIO_REG_FUNC 0x6c ++ + #define AR71XX_GPIO_COUNT 16 + #define AR724X_GPIO_COUNT 18 + #define AR913X_GPIO_COUNT 22 +@@ -548,4 +618,133 @@ + #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + ++#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) ++#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) ++#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) ++#define AR71XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) ++#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) ++ ++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) ++#define AR724X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) ++#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) ++#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) ++#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) ++#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR724X_GPIO_FUNC_UART_EN BIT(1) ++#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) ++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) ++#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) ++#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) ++#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) ++#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) ++#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) ++#define AR913X_GPIO_FUNC_UART_EN BIT(8) ++#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) ++ ++#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) ++#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) ++#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) ++#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) ++#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) ++#define AR933X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR933X_GPIO_FUNC_UART_EN BIT(1) ++#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) ++#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) ++#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) ++ ++#define AR934X_GPIO_OUT_GPIO 0x00 ++ ++/* ++ * MII_CTRL block ++ */ ++#define AR71XX_MII_REG_MII0_CTRL 0x00 ++#define AR71XX_MII_REG_MII1_CTRL 0x04 ++ ++#define AR71XX_MII_CTRL_IF_MASK 3 ++#define AR71XX_MII_CTRL_SPEED_SHIFT 4 ++#define AR71XX_MII_CTRL_SPEED_MASK 3 ++#define AR71XX_MII_CTRL_SPEED_10 0 ++#define AR71XX_MII_CTRL_SPEED_100 1 ++#define AR71XX_MII_CTRL_SPEED_1000 2 ++ ++#define AR71XX_MII0_CTRL_IF_GMII 0 ++#define AR71XX_MII0_CTRL_IF_MII 1 ++#define AR71XX_MII0_CTRL_IF_RGMII 2 ++#define AR71XX_MII0_CTRL_IF_RMII 3 ++ ++#define AR71XX_MII1_CTRL_IF_RGMII 0 ++#define AR71XX_MII1_CTRL_IF_RMII 1 ++ ++/* ++ * AR933X GMAC interface ++ */ ++#define AR933X_GMAC_REG_ETH_CFG 0x00 ++ ++#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) ++#define AR933X_ETH_CFG_MII_GE0 BIT(1) ++#define AR933X_ETH_CFG_GMII_GE0 BIT(2) ++#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) ++#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) ++#define AR933X_ETH_CFG_RMII_GE0 BIT(9) ++#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 ++#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) ++ ++/* ++ * AR934X GMAC Interface ++ */ ++#define AR934X_GMAC_REG_ETH_CFG 0x00 ++ ++#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) ++#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) ++#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) ++#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) ++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) ++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) ++#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) ++#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) ++#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) ++#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) ++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++ ++/* ++ * QCA955X GMAC Interface ++ */ ++ ++#define QCA955X_GMAC_REG_ETH_CFG 0x00 ++ ++#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) ++#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) ++ + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-3.3/602-MIPS-ath79-add-openwrt-stuff.patch b/target/linux/ar71xx/patches-3.3/602-MIPS-ath79-add-openwrt-stuff.patch new file mode 100644 index 000000000..e61496fcd --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/602-MIPS-ath79-add-openwrt-stuff.patch @@ -0,0 +1,76 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -106,6 +106,20 @@ config SOC_QCA955X + select PCI_AR724X if PCI + def_bool n + ++config ATH79_DEV_M25P80 ++ select ATH79_DEV_SPI ++ def_bool n ++ ++config ATH79_DEV_AP9X_PCI ++ select ATH79_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config ATH79_DEV_DSA ++ def_bool n ++ ++config ATH79_DEV_ETH ++ def_bool n ++ + config PCI_AR724X + def_bool n + +@@ -115,6 +129,10 @@ config ATH79_DEV_GPIO_BUTTONS + config ATH79_DEV_LEDS_GPIO + def_bool n + ++config ATH79_DEV_NFC ++ depends on (SOC_AR934X) ++ def_bool n ++ + config ATH79_DEV_SPI + def_bool n + +@@ -125,4 +143,13 @@ config ATH79_DEV_WMAC + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) + def_bool n + ++config ATH79_NVRAM ++ def_bool n ++ ++config ATH79_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config ATH79_ROUTERBOOT ++ def_bool n ++ + endif +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -17,13 +17,25 @@ obj-$(CONFIG_PCI) += pci.o + # Devices + # + obj-y += dev-common.o ++obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o ++obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o ++obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o + obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o + obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o ++obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o ++obj-$(CONFIG_ATH79_DEV_NFC) += dev-nfc.o + obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o + obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o + obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o + + # ++# Miscellaneous objects ++# ++obj-$(CONFIG_ATH79_NVRAM) += nvram.o ++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o ++obj-$(CONFIG_ATH79_ROUTERBOOT) += routerboot.o ++ ++# + # Machines + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o diff --git a/target/linux/ar71xx/patches-3.3/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-3.3/603-MIPS-ath79-ap121-fixes.patch new file mode 100644 index 000000000..1cacde604 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/603-MIPS-ath79-ap121-fixes.patch @@ -0,0 +1,163 @@ +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -1,19 +1,21 @@ + /* + * Atheros AP121 board support + * +- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +-#include "machtypes.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" ++#include "dev-m25p80.h" + #include "dev-spi.h" + #include "dev-usb.h" + #include "dev-wmac.h" ++#include "machtypes.h" + + #define AP121_GPIO_LED_WLAN 0 + #define AP121_GPIO_LED_USB 1 +@@ -24,7 +26,14 @@ + #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) + +-#define AP121_CAL_DATA_ADDR 0x1fff1000 ++#define AP121_MAC0_OFFSET 0x0000 ++#define AP121_MAC1_OFFSET 0x0006 ++#define AP121_CALDATA_OFFSET 0x1000 ++#define AP121_WMAC_MAC_OFFSET 0x1002 ++ ++#define AP121_MINI_GPIO_LED_WLAN 0 ++#define AP121_MINI_GPIO_BTN_JUMPSTART 12 ++#define AP121_MINI_GPIO_BTN_RESET 11 + + static struct gpio_led ap121_leds_gpio[] __initdata = { + { +@@ -58,41 +67,78 @@ static struct gpio_keys_button ap121_gpi + } + }; + +-static struct ath79_spi_controller_data ap121_spi0_data = { +- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, +- .cs_line = 0, ++static struct gpio_led ap121_mini_leds_gpio[] __initdata = { ++ { ++ .name = "ap121:green:wlan", ++ .gpio = AP121_MINI_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, + }; + +-static struct spi_board_info ap121_spi_info[] = { ++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = { + { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l1606e", +- .controller_data = &ap121_spi0_data, ++ .desc = "jumpstart button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ }, ++ { ++ .desc = "reset button", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_RESET, ++ .active_low = 1, + } + }; + +-static struct ath79_spi_platform_data ap121_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; ++static void __init ap121_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_wmac(art + AP121_CALDATA_OFFSET, ++ art + AP121_WMAC_MAC_OFFSET); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ /* LAN ports */ ++ ath79_register_eth(1); ++ ++ /* WAN port */ ++ ath79_register_eth(0); ++} + + static void __init ap121_setup(void) + { +- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); ++ ap121_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), + ap121_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap121_gpio_keys), + ap121_gpio_keys); +- +- ath79_register_spi(&ap121_spi_data, ap121_spi_info, +- ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(cal_data, NULL); + } + + MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", + ap121_setup); ++ ++static void __init ap121_mini_setup(void) ++{ ++ ap121_common_setup(); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio), ++ ap121_mini_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap121_mini_gpio_keys), ++ ap121_mini_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI", ++ ap121_mini_setup); +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi + config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -17,6 +17,7 @@ + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ ++ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ + ATH79_MACH_AP136, /* Atheros AP136 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ diff --git a/target/linux/ar71xx/patches-3.3/604-MIPS-ath79-ap81-fixes.patch b/target/linux/ar71xx/patches-3.3/604-MIPS-ath79-ap81-fixes.patch new file mode 100644 index 000000000..3cc012d1a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/604-MIPS-ath79-ap81-fixes.patch @@ -0,0 +1,128 @@ +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -9,12 +9,16 @@ + * by the Free Software Foundation. + */ + +-#include "machtypes.h" +-#include "dev-wmac.h" ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/partitions.h> ++ ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" + #include "dev-usb.h" ++#include "dev-wmac.h" ++#include "machtypes.h" + + #define AP81_GPIO_LED_STATUS 1 + #define AP81_GPIO_LED_AOSS 3 +@@ -29,6 +33,37 @@ + + #define AP81_CAL_DATA_ADDR 0x1fff1000 + ++static struct mtd_partition ap81_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x500000, ++ }, { ++ .name = "uImage", ++ .offset = 0x550000, ++ .size = 0x100000, ++ }, { ++ .name = "ART", ++ .offset = 0x650000, ++ .size = 0x1b0000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++ ++static struct flash_platform_data ap81_flash_data = { ++ .parts = ap81_partitions, ++ .nr_parts = ARRAY_SIZE(ap81_partitions), ++}; ++ + static struct gpio_led ap81_leds_gpio[] __initdata = { + { + .name = "ap81:green:status", +@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio + } + }; + +-static struct ath79_spi_controller_data ap81_spi0_data = { +- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, +- .cs_line = 0, +-}; +- +-static struct spi_board_info ap81_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "m25p64", +- .controller_data = &ap81_spi0_data, +- } +-}; +- +-static struct ath79_spi_platform_data ap81_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; +- + static void __init ap81_setup(void) + { + u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); +@@ -96,10 +111,24 @@ static void __init ap81_setup(void) + ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap81_gpio_keys), + ap81_gpio_keys); +- ath79_register_spi(&ap81_spi_data, ap81_spi_info, +- ARRAY_SIZE(ap81_spi_info)); ++ ath79_register_m25p80(&ap81_flash_data); + ath79_register_wmac(cal_data, NULL); + ath79_register_usb(); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0); ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ath79_eth0_data.speed = SPEED_100; ++ ath79_eth0_data.duplex = DUPLEX_FULL; ++ ath79_eth0_data.has_ar8216 = 1; ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ath79_eth1_data.phy_mask = 0x10; ++ ++ ath79_register_eth(0); ++ ath79_register_eth(1); + } + + MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -30,9 +30,10 @@ config ATH79_MACH_AP136 + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help diff --git a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch new file mode 100644 index 000000000..34e39e375 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch @@ -0,0 +1,219 @@ +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -2,7 +2,7 @@ + * Atheros DB120 reference board support + * + * Copyright (c) 2011 Qualcomm Atheros +- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org> ++ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -19,16 +19,26 @@ + */ + + #include <linux/pci.h> ++#include <linux/phy.h> ++#include <linux/platform_device.h> + #include <linux/ath9k_platform.h> ++#include <linux/ar8216_platform.h> + +-#include "machtypes.h" ++#include <asm/mach-ath79/ar71xx_regs.h> ++ ++#include "common.h" ++#include "dev-ap9x-pci.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-nfc.h" + #include "dev-spi.h" + #include "dev-usb.h" + #include "dev-wmac.h" +-#include "pci.h" ++#include "machtypes.h" + ++#define DB120_GPIO_LED_USB 11 + #define DB120_GPIO_LED_WLAN_5G 12 + #define DB120_GPIO_LED_WLAN_2G 13 + #define DB120_GPIO_LED_STATUS 14 +@@ -39,8 +49,10 @@ + #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ + #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) + +-#define DB120_WMAC_CALDATA_OFFSET 0x1000 +-#define DB120_PCIE_CALDATA_OFFSET 0x5000 ++#define DB120_MAC0_OFFSET 0 ++#define DB120_MAC1_OFFSET 6 ++#define DB120_WMAC_CALDATA_OFFSET 0x1000 ++#define DB120_PCIE_CALDATA_OFFSET 0x5000 + + static struct gpio_led db120_leds_gpio[] __initdata = { + { +@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[] + .gpio = DB120_GPIO_LED_WLAN_2G, + .active_low = 1, + }, ++ { ++ .name = "db120:green:usb", ++ .gpio = DB120_GPIO_LED_USB, ++ .active_low = 1, ++ } + }; + + static struct gpio_keys_button db120_gpio_keys[] __initdata = { +@@ -76,66 +93,101 @@ static struct gpio_keys_button db120_gpi + }, + }; + +-static struct ath79_spi_controller_data db120_spi0_data = { +- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, +- .cs_line = 0, ++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + }; + +-static struct spi_board_info db120_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "s25sl064a", +- .controller_data = &db120_spi0_data, +- } ++static struct ar8327_led_cfg db120_ar8327_led_cfg = { ++ .led_ctrl0 = 0x00000000, ++ .led_ctrl1 = 0xc737c737, ++ .led_ctrl2 = 0x00000000, ++ .led_ctrl3 = 0x00c30c00, ++ .open_drain = true, + }; + +-static struct ath79_spi_platform_data db120_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct ar8327_platform_data db120_ar8327_data = { ++ .pad0_cfg = &db120_ar8327_pad0_cfg, ++ .cpuport_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .led_cfg = &db120_ar8327_led_cfg, + }; + +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data db120_ath9k_data; ++static struct mdio_board_info db120_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &db120_ar8327_data, ++ }, ++}; + +-static int db120_pci_plat_dev_init(struct pci_dev *dev) ++static void __init db120_gmac_setup(void) + { +- switch (PCI_SLOT(dev->devfn)) { +- case 0: +- dev->dev.platform_data = &db120_ath9k_data; +- break; +- } ++ void __iomem *base; ++ u32 t; + +- return 0; +-} ++ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + +-static void __init db120_pci_init(u8 *eeprom) +-{ +- memcpy(db120_ath9k_data.eeprom_data, eeprom, +- sizeof(db120_ath9k_data.eeprom_data)); ++ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); ++ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | ++ AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); ++ t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE; ++ ++ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + +- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); +- ath79_register_pci(); ++ iounmap(base); + } +-#else +-static inline void db120_pci_init(void) {} +-#endif /* CONFIG_PCI */ + + static void __init db120_setup(void) + { + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + ++ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); ++ ath79_register_m25p80(NULL); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), + db120_leds_gpio); + ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, + ARRAY_SIZE(db120_gpio_keys), + db120_gpio_keys); +- ath79_register_spi(&db120_spi_data, db120_spi_info, +- ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); +- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); ++ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); ++ ++ db120_gmac_setup(); ++ ++ ath79_register_mdio(1, 0x0); ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); ++ ++ mdiobus_register_board_info(db120_mdio0_info, ++ ARRAY_SIZE(db120_mdio0_info)); ++ ++ /* GMAC0 is connected to an AR8327 switch */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++ ++ /* GMAC1 is connected to the internal switch */ ++ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ++ ath79_register_eth(1); ++ ++ ath79_register_nfc(); + } + + MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -43,9 +43,12 @@ config ATH79_MACH_AP81 + config ATH79_MACH_DB120 + bool "Atheros DB120 reference board" + select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help diff --git a/target/linux/ar71xx/patches-3.3/606-MIPS-ath79-pb44-fixes.patch b/target/linux/ar71xx/patches-3.3/606-MIPS-ath79-pb44-fixes.patch new file mode 100644 index 000000000..f9ec7753f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/606-MIPS-ath79-pb44-fixes.patch @@ -0,0 +1,153 @@ +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -8,23 +8,48 @@ + * by the Free Software Foundation. + */ + ++#include <linux/delay.h> + #include <linux/init.h> + #include <linux/platform_device.h> + #include <linux/i2c.h> + #include <linux/i2c-gpio.h> + #include <linux/i2c/pcf857x.h> ++#include <linux/i2c/pcf857x.h> ++#include <linux/spi/flash.h> ++#include <linux/spi/vsc7385.h> + +-#include "machtypes.h" ++#include <asm/mach-ath79/ar71xx_regs.h> ++#include <asm/mach-ath79/ath79.h> ++ ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" + #include "dev-usb.h" ++#include "machtypes.h" + #include "pci.h" + + #define PB44_GPIO_I2C_SCL 0 + #define PB44_GPIO_I2C_SDA 1 + ++#define PB44_PCF8757_VSC7395_CS 0 ++#define PB44_PCF8757_STEREO_CS 1 ++#define PB44_PCF8757_SLIC_CS0 2 ++#define PB44_PCF8757_SLIC_TEST 3 ++#define PB44_PCF8757_SLIC_INT0 4 ++#define PB44_PCF8757_SLIC_INT1 5 ++#define PB44_PCF8757_SW_RESET 6 ++#define PB44_PCF8757_SW_JUMP 8 ++#define PB44_PCF8757_LED_JUMP1 9 ++#define PB44_PCF8757_LED_JUMP2 10 ++#define PB44_PCF8757_TP24 11 ++#define PB44_PCF8757_TP25 12 ++#define PB44_PCF8757_TP26 13 ++#define PB44_PCF8757_TP27 14 ++#define PB44_PCF8757_TP28 15 ++ + #define PB44_GPIO_EXP_BASE 16 ++#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) + #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) + #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) + #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data + .cs_line = 0, + }; + ++static struct ath79_spi_controller_data pb44_spi1_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_GPIO, ++ .cs_line = PB44_GPIO_VSC7395_CS, ++}; ++ ++static void pb44_vsc7395_reset(void) ++{ ++ ath79_device_reset_set(AR71XX_RESET_GE1_PHY); ++ udelay(10); ++ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); ++ mdelay(50); ++} ++ ++static struct vsc7385_platform_data pb44_vsc7395_data = { ++ .reset = pb44_vsc7395_reset, ++ .ucode_name = "vsc7395_ucode_pb44.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 1, ++ .clk_sel = 0, ++ }, ++}; ++ ++static const char *pb44_part_probes[] = { ++ "RedBoot", ++ NULL, ++}; ++ ++static struct flash_platform_data pb44_flash_data = { ++ .part_probes = pb44_part_probes, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .platform_data = &pb44_flash_data, + .controller_data = &pb44_spi0_data, + }, ++ { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &pb44_vsc7395_data, ++ .controller_data = &pb44_spi1_data, ++ } + }; + + static struct ath79_spi_platform_data pb44_spi_data = { + .bus_num = 0, +- .num_chipselect = 1, ++ .num_chipselect = 2, + }; + ++#define PB44_WAN_PHYMASK BIT(0) ++#define PB44_LAN_PHYMASK 0 ++#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) ++ + static void __init pb44_init(void) + { + i2c_register_board_info(0, pb44_i2c_board_info, +@@ -122,6 +192,22 @@ static void __init pb44_init(void) + ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); + ath79_register_pci(); ++ ++ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK; ++ ++ ath79_register_eth(0); ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ath79_eth1_pll_data.pll_1000 = 0x110000; ++ ++ ath79_register_eth(1); + } + + MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -58,6 +58,7 @@ config ATH79_MACH_DB120 + config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI diff --git a/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch new file mode 100644 index 000000000..cbbe20b49 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch @@ -0,0 +1,109 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -70,9 +70,10 @@ config ATH79_MACH_PB44 + config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM (rev 1.0) board" + select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -16,10 +16,11 @@ + + #include <asm/mach-ath79/irq.h> + +-#include "machtypes.h" ++#include "dev-ap9x-pci.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" ++#include "machtypes.h" + #include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 +@@ -32,7 +33,7 @@ + #define UBNT_XM_KEYS_POLL_INTERVAL 20 + #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +-#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) ++#define UBNT_XM_EEPROM_ADDR 0x1fff1000 + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { +@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + +-static struct ath79_spi_controller_data ubnt_xm_spi0_data = { +- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, +- .cs_line = 0, +-}; +- +-static struct spi_board_info ubnt_xm_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l6405d", +- .controller_data = &ubnt_xm_spi0_data, +- } +-}; +- +-static struct ath79_spi_platform_data ubnt_xm_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; +- +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data ubnt_xm_eeprom_data; +- +-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) +-{ +- switch (PCI_SLOT(dev->devfn)) { +- case 0: +- dev->dev.platform_data = &ubnt_xm_eeprom_data; +- break; +- } +- +- return 0; +-} +- +-static void __init ubnt_xm_pci_init(void) +-{ +- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, +- sizeof(ubnt_xm_eeprom_data.eeprom_data)); +- +- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); +- ath79_register_pci(); +-} +-#else +-static inline void ubnt_xm_pci_init(void) {} +-#endif /* CONFIG_PCI */ +- + static void __init ubnt_xm_init(void) + { ++ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); + +@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void) + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + +- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, +- ARRAY_SIZE(ubnt_xm_spi_info)); +- +- ubnt_xm_pci_init(); ++ ath79_register_m25p80(NULL); ++ ap91_pci_init(eeprom, NULL); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/target/linux/ar71xx/patches-3.3/608-MIPS-ath79-ubnt-xm-add-more-boards.patch b/target/linux/ar71xx/patches-3.3/608-MIPS-ath79-ubnt-xm-add-more-boards.patch new file mode 100644 index 000000000..bee07b35c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/608-MIPS-ath79-ubnt-xm-add-more-boards.patch @@ -0,0 +1,200 @@ +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -13,15 +13,17 @@ + #include <linux/init.h> + #include <linux/pci.h> + #include <linux/ath9k_platform.h> ++#include <linux/etherdevice.h> + + #include <asm/mach-ath79/irq.h> + + #include "dev-ap9x-pci.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-m25p80.h" ++#include "dev-usb.h" + #include "machtypes.h" +-#include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 + #define UBNT_XM_GPIO_LED_L2 1 +@@ -37,19 +39,19 @@ + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { +- .name = "ubnt-xm:red:link1", ++ .name = "ubnt:red:link1", + .gpio = UBNT_XM_GPIO_LED_L1, + .active_low = 0, + }, { +- .name = "ubnt-xm:orange:link2", ++ .name = "ubnt:orange:link2", + .gpio = UBNT_XM_GPIO_LED_L2, + .active_low = 0, + }, { +- .name = "ubnt-xm:green:link3", ++ .name = "ubnt:green:link3", + .gpio = UBNT_XM_GPIO_LED_L3, + .active_low = 0, + }, { +- .name = "ubnt-xm:green:link4", ++ .name = "ubnt:green:link4", + .gpio = UBNT_XM_GPIO_LED_L4, + .active_low = 0, + }, +@@ -66,9 +68,13 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + ++#define UBNT_M_WAN_PHYMASK BIT(4) ++ + static void __init ubnt_xm_init(void) + { + u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); +@@ -79,9 +85,112 @@ static void __init ubnt_xm_init(void) + + ath79_register_m25p80(NULL); + ap91_pci_init(eeprom, NULL); ++ ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, + "UBNT-XM", + "Ubiquiti Networks XM (rev 1.0) board", + ubnt_xm_init); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", ++ ubnt_xm_init); ++ ++static void __init ubnt_rocket_m_setup(void) ++{ ++ ubnt_xm_init(); ++ ath79_register_usb(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", ++ ubnt_rocket_m_setup); ++ ++static void __init ubnt_nano_m_setup(void) ++{ ++ ubnt_xm_init(); ++ ath79_register_eth(1); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", ++ ubnt_nano_m_setup); ++ ++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:globe", ++ .gpio = 0, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:power", ++ .gpio = 11, ++ .active_low = 1, ++ .default_state = LEDS_GPIO_DEFSTATE_ON, ++ } ++}; ++ ++static void __init ubnt_airrouter_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1); ++ ++ ath79_register_eth(1); ++ ath79_register_eth(0); ++ ath79_register_usb(); ++ ++ ap91_pci_init(ee, NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio), ++ ubnt_airrouter_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter", ++ ubnt_airrouter_setup); ++ ++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:orange:dome", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:dome", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++static void __init ubnt_unifi_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ++ ath79_register_eth(0); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio), ++ ubnt_unifi_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi", ++ ubnt_unifi_setup); +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -71,9 +71,11 @@ config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM (rev 1.0) board" + select SOC_AR724X + select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -22,6 +22,11 @@ enum ath79_mach_type { + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ ++ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ ++ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ ++ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ + }; + diff --git a/target/linux/ar71xx/patches-3.3/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.3/609-MIPS-ath79-ap136-fixes.patch new file mode 100644 index 000000000..bd07c7bc8 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/609-MIPS-ath79-ap136-fixes.patch @@ -0,0 +1,175 @@ +--- a/arch/mips/ath79/mach-ap136.c ++++ b/arch/mips/ath79/mach-ap136.c +@@ -1,5 +1,5 @@ + /* +- * Qualcomm Atheros AP136 reference board support ++ * Atheros AP136 reference board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org> +@@ -18,23 +18,27 @@ + * + */ + +-#include <linux/pci.h> +-#include <linux/ath9k_platform.h> ++#include <linux/platform_device.h> ++#include <linux/ar8216_platform.h> + +-#include "machtypes.h" ++#include <asm/mach-ath79/ar71xx_regs.h> ++ ++#include "common.h" ++#include "dev-ap9x-pci.h" + #include "dev-gpio-buttons.h" ++#include "dev-eth.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" + #include "dev-usb.h" + #include "dev-wmac.h" +-#include "pci.h" ++#include "machtypes.h" + +-#define AP136_GPIO_LED_STATUS_RED 14 +-#define AP136_GPIO_LED_STATUS_GREEN 19 + #define AP136_GPIO_LED_USB 4 +-#define AP136_GPIO_LED_WLAN_2G 13 + #define AP136_GPIO_LED_WLAN_5G 12 ++#define AP136_GPIO_LED_WLAN_2G 13 ++#define AP136_GPIO_LED_STATUS_RED 14 + #define AP136_GPIO_LED_WPS_RED 15 ++#define AP136_GPIO_LED_STATUS_GREEN 19 + #define AP136_GPIO_LED_WPS_GREEN 20 + + #define AP136_GPIO_BTN_WPS 16 +@@ -43,8 +47,10 @@ + #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) + +-#define AP136_WMAC_CALDATA_OFFSET 0x1000 +-#define AP136_PCIE_CALDATA_OFFSET 0x5000 ++#define AP136_MAC0_OFFSET 0 ++#define AP136_MAC1_OFFSET 6 ++#define AP136_WMAC_CALDATA_OFFSET 0x1000 ++#define AP136_PCIE_CALDATA_OFFSET 0x5000 + + static struct gpio_led ap136_leds_gpio[] __initdata = { + { +@@ -98,63 +104,82 @@ static struct gpio_keys_button ap136_gpi + }, + }; + +-static struct ath79_spi_controller_data ap136_spi0_data = { +- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, +- .cs_line = 0, ++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + }; + +-static struct spi_board_info ap136_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l6405d", +- .controller_data = &ap136_spi0_data, ++static struct ar8327_platform_data ap136_ar8327_data = { ++ .pad0_cfg = &ap136_ar8327_pad0_cfg, ++ .cpuport_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, + } + }; + +-static struct ath79_spi_platform_data ap136_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct mdio_board_info ap136_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &ap136_ar8327_data, ++ }, + }; + +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data ap136_ath9k_data; +- +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++static void __init ap136_gmac_setup(void) + { +- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) +- dev->dev.platform_data = &ap136_ath9k_data; ++ void __iomem *base; ++ u32 t; + +- return 0; +-} ++ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + +-static void __init ap136_pci_init(u8 *eeprom) +-{ +- memcpy(ap136_ath9k_data.eeprom_data, eeprom, +- sizeof(ap136_ath9k_data.eeprom_data)); ++ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); ++ ++ t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0); ++ t |= QCA955X_ETH_CFG_RGMII_GMAC0; + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); ++ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); ++ ++ iounmap(base); + } +-#else +-static inline void ap136_pci_init(void) {} +-#endif /* CONFIG_PCI */ + + static void __init ap136_setup(void) + { + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + ++ ath79_register_m25p80(NULL); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), + ap136_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap136_gpio_keys), + ap136_gpio_keys); +- ath79_register_spi(&ap136_spi_data, ap136_spi_info, +- ARRAY_SIZE(ap136_spi_info)); ++ + ath79_register_usb(); +- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); +- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); ++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); ++ ++ ap136_gmac_setup(); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); ++ ++ mdiobus_register_board_info(ap136_mdio0_info, ++ ARRAY_SIZE(ap136_mdio0_info)); ++ ++ /* GMAC0 is connected to an AR8327 switch */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ++ ath79_register_eth(0); + } + + MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", diff --git a/target/linux/ar71xx/patches-3.3/610-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-3.3/610-MIPS-ath79-openwrt-machines.patch new file mode 100644 index 000000000..6f6da2d30 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/610-MIPS-ath79-openwrt-machines.patch @@ -0,0 +1,793 @@ +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -16,18 +16,98 @@ + + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, ++ ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */ ++ ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */ ++ ATH79_MACH_ALL0258N, /* Allnet ALL0258N */ ++ ATH79_MACH_ALL0305, /* Allnet ALL0305 */ ++ ATH79_MACH_ALL0315N, /* Allnet ALL0315N */ ++ ATH79_MACH_AP113, /* Atheros AP113 reference board */ + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ + ATH79_MACH_AP136, /* Atheros AP136 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ++ ATH79_MACH_AP83, /* Atheros AP83 */ ++ ATH79_MACH_AP96, /* Atheros AP96 */ ++ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ ++ ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ ++ ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ ++ ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */ ++ ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ ++ ATH79_MACH_EW_DORIN, /* embedded wireless Dorin Platform */ ++ ATH79_MACH_EW_DORIN_ROUTER, /* embedded wireless Dorin Router Platform */ ++ ATH79_MACH_EAP7660D, /* Senao EAP7660D */ ++ ATH79_MACH_JA76PF, /* jjPlus JA76PF */ ++ ATH79_MACH_JA76PF2, /* jjPlus JA76PF2 */ ++ ATH79_MACH_JWAP003, /* jjPlus JWAP003 */ ++ ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */ ++ ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */ ++ ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */ ++ ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ ++ ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */ ++ ATH79_MACH_OM2P, /* OpenMesh OM2P */ ++ ATH79_MACH_PB42, /* Atheros PB42 */ ++ ATH79_MACH_PB92, /* Atheros PB92 */ ++ ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ ++ ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ ++ ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ ++ ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ ++ ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ ++ ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */ ++ ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ ++ ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */ ++ ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */ ++ ATH79_MACH_RB_750G_R3, /* MikroTik RouterBOARD 750GL */ ++ ATH79_MACH_RB_751, /* MikroTik RouterBOARD 751 */ ++ ATH79_MACH_RB_751G, /* Mikrotik RouterBOARD 751G */ ++ ATH79_MACH_RB_2011G, /* Mikrotik RouterBOARD 2011UAS-2HnD */ ++ ATH79_MACH_RB_2011L, /* Mikrotik RouterBOARD 2011L */ ++ ATH79_MACH_RW2458N, /* Redwave RW2458N */ ++ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ ++ ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */ ++ ATH79_MACH_TEW_712BR, /* TRENDnet TEW-712BR */ ++ ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */ ++ ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */ ++ ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */ ++ ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */ ++ ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ ++ ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ ++ ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ ++ ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */ ++ ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */ ++ ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */ ++ ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */ ++ ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ ++ ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/ ++ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ ++ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */ ++ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ + ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ + ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ ++ ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */ + ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ + ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ ++ ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ ++ ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */ + ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ ++ ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */ ++ ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */ ++ ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */ ++ ATH79_MACH_WLAE_AG300N, /* Buffalo WLAE-AG300N */ ++ ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */ ++ ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */ ++ ATH79_MACH_WP543, /* Compex WP543 */ ++ ATH79_MACH_WPE72, /* Compex WPE72 */ ++ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */ ++ ATH79_MACH_WRT400N, /* Linksys WRT400N */ ++ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */ ++ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ ++ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */ ++ ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */ ++ ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */ + }; + + #endif /* _ATH79_MACHTYPE_H */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -2,6 +2,61 @@ if ATH79 + + menu "Atheros AR71XX/AR724X/AR913X machine selection" + ++config ATH79_MACH_ALFA_AP96 ++ bool "ALFA Network AP96 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_HORNET_UB ++ bool "ALFA Network Hornet-UB board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ALFA_NX ++ bool "ALFA Network N2/N5 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ALL0258N ++ bool "Allnet ALL0258N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ALL0315N ++ bool "Allnet ALL0315N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_AP113 ++ bool "Atheros AP113 board support" ++ select SOC_AR724X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_PB9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_ETH ++ + config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X +@@ -40,6 +95,24 @@ config ATH79_MACH_AP81 + Say 'Y' here if you want your kernel to support the + Atheros AP81 reference board. + ++config ATH79_MACH_AP83 ++ bool "Atheros AP83 board support" ++ select SOC_AR913X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_AP96 ++ bool "Atheros AP96 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ + config ATH79_MACH_DB120 + bool "Atheros DB120 reference board" + select SOC_AR934X +@@ -55,6 +128,13 @@ config ATH79_MACH_DB120 + Say 'Y' here if you want your kernel to support the + Atheros DB120 reference board. + ++config ATH79_MACH_PB42 ++ bool "Atheros PB42 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ + config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX +@@ -67,6 +147,447 @@ config ATH79_MACH_PB44 + Say 'Y' here if you want your kernel to support the + Atheros PB44 reference board. + ++config ATH79_MACH_PB92 ++ bool "Atheros PB92 board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_PB9X_PCI if PCI ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_AW_NR580 ++ bool "AzureWave AW-NR580 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WHR_HP_G300N ++ bool "Buffalo WHR-HP-G300N board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WLAE_AG300N ++ bool "Buffalo WLAE-AG300N board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WZR_HP_AG300H ++ bool "Buffalo WZR-HP-AG300H board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_HP_G300NH ++ bool "Buffalo WZR-HP-G300NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select RTL8366_SMI ++ ++config ATH79_MACH_WZR_HP_G300NH2 ++ bool "Buffalo WZR-HP-G300NH2 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_HP_G450H ++ bool "Buffalo WZR-HP-G450H board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WP543 ++ bool "Compex WP543/WPJ543 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select MYLOADER ++ ++config ATH79_MACH_WPE72 ++ bool "Compex WPE72/WPE72NX board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select MYLOADER ++ ++config ATH79_MACH_DIR_600_A1 ++ bool "D-Link DIR-600 A1/DIR-615 E4 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_615_C1 ++ bool "D-Link DIR-615 rev. C1 support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_825_B1 ++ bool "D-Link DIR-825 rev. B1 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_EW_DORIN ++ bool "embedded wireless Dorin Platform support" ++ select SOC_AR933X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ help ++ Say 'Y' here if you want your kernel to support the ++ Dorin Platform from www.80211.de . ++ ++config ATH79_MACH_JA76PF ++ bool "jjPlus JA76PF board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_JWAP003 ++ bool "jjPlus JWAP003 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WRT160NL ++ bool "Linksys WRT160NL board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_WRT400N ++ bool "Linksys WRT400N board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_RB4XX ++ bool "MikroTik RouterBOARD 4xx series support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_RB750 ++ bool "MikroTik RouterBOARD 750 support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ select RLE_DECOMPRESS ++ ++config ATH79_MACH_RB2011 ++ bool "MikroTik RouterBOARD 2011 support" ++ select SOC_AR934x ++ select ATH79_DEV_ETH ++ select ATH79_DEV_NFC ++ select ATH79_DEV_WMAC ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_WNDR3700 ++ bool "NETGEAR WNDR3700 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WNR2000 ++ bool "NETGEAR WNR2000 board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_OM2P ++ bool "OpenMesh OM2P board support" ++ select SOC_AR724X ++ select SOC_AR933X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MZK_W04NU ++ bool "Planex MZK-W04NU board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MZK_W300NH ++ bool "Planex MZK-W300NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_RW2458N ++ bool "Redwave RW2458N board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_EAP7660D ++ bool "Senao EAP7660D support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_MR11U ++ bool "TP-LINK TL-MR11U support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR3020 ++ bool "TP-LINK TL-MR3020 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR3X20 ++ bool "TP-LINK TL-MR3220/3420 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_TL_WA901ND ++ bool "TP-LINK TL-WA901ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WA901ND_V2 ++ bool "TP-LINK TL-WA901ND v2 support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WDR4300 ++ bool "TP-LINK TL-WDR3600/4300/4310 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR703N ++ bool "TP-LINK TL-WR703N support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR741ND ++ bool "TP-LINK TL-WR741ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WR741ND_V4 ++ bool "TP-LINK TL-WR741ND v4 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR841N_V1 ++ bool "TP-LINK TL-WR841N v1 support" ++ select SOC_AR71XX ++ select ATH79_DEV_DSA ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WR941ND ++ bool "TP-LINK TL-WR941ND support" ++ select SOC_AR913X ++ select ATH79_DEV_DSA ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1041N_V2 ++ bool "TP-LINK TL-WR1041N v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1043ND ++ bool "TP-LINK TL-WR1043ND support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR2543N ++ bool "TP-LINK TL-WR2543N/ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_TEW_632BRP ++ bool "TRENDnet TEW-632BRP support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_673GRU ++ bool "TRENDnet TEW-673GRU support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_712BR ++ bool "TRENDnet TEW-712BR support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_UBNT ++ bool "Ubiquiti AR71xx based boards support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ + config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM (rev 1.0) board" + select SOC_AR724X +@@ -80,6 +601,24 @@ config ATH79_MACH_UBNT_XM + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. + ++config ATH79_MACH_ZCN_1523H ++ bool "Zcomax ZCN-1523H support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_NBG460N ++ bool "Zyxel NBG460N/550N/550NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ + endmenu + + config SOC_AR71XX +@@ -115,10 +654,6 @@ config SOC_QCA955X + select PCI_AR724X if PCI + def_bool n + +-config ATH79_DEV_M25P80 +- select ATH79_DEV_SPI +- def_bool n +- + config ATH79_DEV_AP9X_PCI + select ATH79_PCI_ATH9K_FIXUP + def_bool n +@@ -129,7 +664,14 @@ config ATH79_DEV_DSA + config ATH79_DEV_ETH + def_bool n + +-config PCI_AR724X ++config ATH79_DEV_M25P80 ++ select ATH79_DEV_SPI ++ def_bool n ++ ++config ATH79_DEV_DSA ++ def_bool n ++ ++config ATH79_DEV_ETH + def_bool n + + config ATH79_DEV_GPIO_BUTTONS +@@ -161,4 +703,7 @@ config ATH79_PCI_ATH9K_FIXUP + config ATH79_ROUTERBOOT + def_bool n + ++config PCI_AR724X ++ def_bool n ++ + endif +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -38,9 +38,65 @@ obj-$(CONFIG_ATH79_ROUTERBOOT) += route + # + # Machines + # ++obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o ++obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o ++obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o ++obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o ++obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o ++obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o ++obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o + obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o ++obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o ++obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o ++obj-$(CONFIG_ATH79_MACH_EW_DORIN) += mach-ew-dorin.o ++obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o ++obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o ++obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o ++obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o ++obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o ++obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o ++obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o ++obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o ++obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o ++obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o ++obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o ++obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o ++obj-$(CONFIG_ATH79_MACH_RB2011) += mach-rb2011.o ++obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o ++obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o ++obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o ++obj-$(CONFIG_ATH79_MACH_TEW_712BR) += mach-tew-712br.o ++obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o ++obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o ++obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o ++obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o ++obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o ++obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o + obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o ++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o ++obj-$(CONFIG_ATH79_MACH_WLAE_AG300N) += mach-wlae-ag300n.o ++obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o ++obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o ++obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o ++obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o ++obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o ++obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -180,6 +180,10 @@ void __init prom_init(void) + ath79_prom_append_cmdline("board", env); + } + } ++ ++ if (strstr(arcs_cmdline, "board=750Gr3") || ++ strstr(arcs_cmdline, "board=2011L")) ++ ath79_prom_append_cmdline("console", "ttyS0,115200"); + } + + void __init prom_free_prom_memory(void) diff --git a/target/linux/ar71xx/patches-3.3/611-MIPS-ath79-TL-MR3040-support.patch b/target/linux/ar71xx/patches-3.3/611-MIPS-ath79-TL-MR3040-support.patch new file mode 100644 index 000000000..4e6d491d9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/611-MIPS-ath79-TL-MR3040-support.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -412,7 +412,7 @@ config ATH79_MACH_EAP7660D + select ATH79_DEV_M25P80 + + config ATH79_MACH_TL_MR11U +- bool "TP-LINK TL-MR11U support" ++ bool "TP-LINK TL-MR11U/TL-MR3040 support" + select SOC_AR933X + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -69,6 +69,7 @@ enum ath79_mach_type { + ATH79_MACH_TEW_712BR, /* TRENDnet TEW-712BR */ + ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */ + ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */ ++ ATH79_MACH_TL_MR3040, /* TP-LINK TL-MR3040 */ + ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */ + ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */ + ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ diff --git a/target/linux/ar71xx/patches-3.3/612-MIPS-ath79-TL-WR841N-v8-support.patch b/target/linux/ar71xx/patches-3.3/612-MIPS-ath79-TL-WR841N-v8-support.patch new file mode 100644 index 000000000..da1714d1a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/612-MIPS-ath79-TL-WR841N-v8-support.patch @@ -0,0 +1,38 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -507,6 +507,15 @@ config ATH79_MACH_TL_WR841N_V1 + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 + ++config ATH79_MACH_TL_WR841N_V8 ++ bool "TP-LINK TL-WR841N/ND v8 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_TL_WR941ND + bool "TP-LINK TL-WR941ND support" + select SOC_AR913X +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -83,6 +83,7 @@ enum ath79_mach_type { + ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/ + ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ + ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */ ++ ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */ + ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ + ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ + ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WDR4300) + obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o + obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o + obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o + obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o + obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o diff --git a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch new file mode 100644 index 000000000..087dbc082 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch @@ -0,0 +1,166 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -139,6 +139,137 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static bool __init ++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) ++{ ++ int timeout = 1000; ++ u32 val; ++ ++ __raw_readl(base + AR9300_OTP_BASE + (4 * addr)); ++ while (timeout--) { ++ val = __raw_readl(base + AR9300_OTP_STATUS); ++ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID) ++ break; ++ ++ udelay(10); ++ } ++ ++ if (!timeout) ++ return false; ++ ++ *data = __raw_readl(base + AR9300_OTP_READ_DATA); ++ return true; ++} ++ ++static bool __init ++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len) ++{ ++ u32 data; ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ int offset = 8 * ((addr - i) % 4); ++ ++ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data)) ++ return false; ++ ++ dest[i] = (data >> offset) & 0xff; ++ } ++ ++ return true; ++} ++ ++static bool __init ++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest, ++ int dest_start, int dest_len) ++{ ++ int dest_bytes = 0; ++ int offset = 0; ++ int end = addr - len; ++ u8 hdr[2]; ++ ++ while (addr > end) { ++ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2)) ++ return false; ++ ++ addr -= 2; ++ offset += hdr[0]; ++ ++ if (offset <= dest_start + dest_len && ++ offset + len >= dest_start) { ++ int data_offset = 0; ++ int dest_offset = 0; ++ int copy_len; ++ ++ if (offset < dest_start) ++ data_offset = dest_start - offset; ++ else ++ dest_offset = offset - dest_start; ++ ++ copy_len = len - data_offset; ++ if (copy_len > dest_len - dest_offset) ++ copy_len = dest_len - dest_offset; ++ ++ ar93xx_wmac_otp_read(base, addr - data_offset, ++ dest + dest_offset, ++ copy_len); ++ ++ dest_bytes += copy_len; ++ } ++ addr -= hdr[1]; ++ } ++ return !!dest_bytes; ++} ++ ++bool __init ar93xx_wmac_read_mac_address(u8 *dest) ++{ ++ void __iomem *base; ++ bool ret = false; ++ int addr = 0x1ff; ++ unsigned int len; ++ u32 hdr_u32; ++ u8 *hdr = (u8 *) &hdr_u32; ++ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 }; ++ int mac_start = 2, mac_end = 8; ++ ++ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x()); ++ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE); ++ while (addr > sizeof(hdr)) { ++ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr))) ++ break; ++ ++ if (hdr_u32 == 0 || hdr_u32 == ~0) ++ break; ++ ++ len = (hdr[1] << 4) | (hdr[2] >> 4); ++ addr -= 4; ++ ++ switch (hdr[0] >> 5) { ++ case 0: ++ if (len < mac_end) ++ break; ++ ++ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6); ++ ret = true; ++ break; ++ case 3: ++ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac, ++ mac_start, 6); ++ break; ++ default: ++ break; ++ } ++ ++ addr -= len + 2; ++ } ++ ++ iounmap(base); ++ if (ret) ++ memcpy(dest, mac, 6); ++ ++ return ret; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -13,5 +13,6 @@ + #define _ATH79_DEV_WMAC_H + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); ++bool ar93xx_wmac_read_mac_address(u8 *dest); + + #endif /* _ATH79_DEV_WMAC_H */ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -129,6 +129,14 @@ + #define QCA955X_NFC_BASE 0x1b000200 + #define QCA955X_NFC_SIZE 0xb8 + ++#define AR9300_OTP_BASE 0x14000 ++#define AR9300_OTP_STATUS 0x15f18 ++#define AR9300_OTP_STATUS_TYPE 0x7 ++#define AR9300_OTP_STATUS_VALID 0x4 ++#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 ++#define AR9300_OTP_STATUS_SM_BUSY 0x1 ++#define AR9300_OTP_READ_DATA 0x15f1c ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-3.3/630-MIPS-ath79-enable-dsp.patch b/target/linux/ar71xx/patches-3.3/630-MIPS-ath79-enable-dsp.patch new file mode 100644 index 000000000..3071ab88f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/630-MIPS-ath79-enable-dsp.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h ++++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +@@ -42,7 +42,6 @@ + #define cpu_has_mips64r1 0 + #define cpu_has_mips64r2 0 + +-#define cpu_has_dsp 0 + #define cpu_has_mipsmt 0 + + #define cpu_has_64bits 0 diff --git a/target/linux/ar71xx/patches-3.3/650-MIPS-ath79-fix-ar933x-reset.patch b/target/linux/ar71xx/patches-3.3/650-MIPS-ath79-fix-ar933x-reset.patch new file mode 100644 index 000000000..a81d6ea6e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/650-MIPS-ath79-fix-ar933x-reset.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -67,10 +67,27 @@ static void __init ar913x_wmac_setup(voi + + static int ar933x_wmac_reset(void) + { ++ int retries = 20; ++ + ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); + +- return 0; ++ while (1) { ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) ++ return 0; ++ ++ if (retries-- == 0) ++ break; ++ ++ udelay(10000); ++ retries++; ++ } ++ ++ pr_err("ar933x: WMAC reset timed out"); ++ return -ETIMEDOUT; + } + + static int ar933x_r1_get_wmac_revision(void) diff --git a/target/linux/ar71xx/patches-3.3/901-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-3.3/901-mdio_bitbang_ignore_ta_value.patch new file mode 100644 index 000000000..39584aabf --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/901-mdio_bitbang_ignore_ta_value.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/phy/mdio-bitbang.c ++++ b/drivers/net/phy/mdio-bitbang.c +@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b + + ctrl->ops->set_mdio_dir(ctrl, 0); + +- /* check the turnaround bit: the PHY should be driving it to zero */ +- if (mdiobb_get_bit(ctrl) != 0) { +- /* PHY didn't drive TA low -- flush any bits it +- * may be trying to send. +- */ +- for (i = 0; i < 32; i++) +- mdiobb_get_bit(ctrl); +- +- return 0xffff; +- } ++ mdiobb_get_bit(ctrl); + + ret = mdiobb_get_num(ctrl, 16); + mdiobb_get_bit(ctrl); diff --git a/target/linux/ar71xx/patches-3.3/902-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-3.3/902-unaligned_access_hacks.patch new file mode 100644 index 000000000..921cf194d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/902-unaligned_access_hacks.patch @@ -0,0 +1,117 @@ +--- a/arch/mips/include/asm/checksum.h ++++ b/arch/mips/include/asm/checksum.h +@@ -12,6 +12,7 @@ + #define _ASM_CHECKSUM_H + + #include <linux/in6.h> ++#include <linux/unaligned/packed_struct.h> + + #include <asm/uaccess.h> + +@@ -104,26 +105,30 @@ static inline __sum16 ip_fast_csum(const + const unsigned int *stop = word + ihl; + unsigned int csum; + int carry; ++ unsigned int w; + +- csum = word[0]; +- csum += word[1]; +- carry = (csum < word[1]); ++ csum = __get_unaligned_cpu32(word++); ++ ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[2]; +- carry = (csum < word[2]); ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[3]; +- carry = (csum < word[3]); ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- word += 4; + do { +- csum += *word; +- carry = (csum < *word); ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; +- word++; + } while (word != stop); + + return csum_fold(csum); +--- a/include/linux/ip.h ++++ b/include/linux/ip.h +@@ -102,7 +102,7 @@ struct iphdr { + __be32 saddr; + __be32 daddr; + /*The options start here. */ +-}; ++} __packed; + + #ifdef __KERNEL__ + #include <linux/skbuff.h> +--- a/include/linux/ipv6.h ++++ b/include/linux/ipv6.h +@@ -126,7 +126,7 @@ struct ipv6hdr { + + struct in6_addr saddr; + struct in6_addr daddr; +-}; ++} __packed; + + #ifdef __KERNEL__ + /* +--- a/include/linux/tcp.h ++++ b/include/linux/tcp.h +@@ -54,7 +54,7 @@ struct tcphdr { + __be16 window; + __sum16 check; + __be16 urg_ptr; +-}; ++} __packed; + + /* + * The union cast uses a gcc extension to avoid aliasing problems +--- a/include/linux/udp.h ++++ b/include/linux/udp.h +@@ -24,7 +24,7 @@ struct udphdr { + __be16 dest; + __be16 len; + __sum16 check; +-}; ++} __packed; + + /* UDP socket options */ + #define UDP_CORK 1 /* Never send partially complete segments */ +--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c ++++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c +@@ -14,6 +14,7 @@ + #include <linux/skbuff.h> + #include <linux/icmp.h> + #include <linux/sysctl.h> ++#include <linux/unaligned/packed_struct.h> + #include <net/route.h> + #include <net/ip.h> + +@@ -44,8 +45,8 @@ static bool ipv4_pkt_to_tuple(const stru + if (ap == NULL) + return false; + +- tuple->src.u3.ip = ap[0]; +- tuple->dst.u3.ip = ap[1]; ++ tuple->src.u3.ip = __get_unaligned_cpu32(ap++); ++ tuple->dst.u3.ip = __get_unaligned_cpu32(ap); + + return true; + } |