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| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-10-05 10:12:53 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-10-05 10:12:53 +0000 |
| commit | 5c105d9f3fd086aff195d3849dcf847d6b0bd927 (patch) | |
| tree | 1229a11f725bfa58aa7c57a76898553bb5f6654a /target/linux/lantiq/files/arch/mips/include | |
| download | openwrt-5c105d9f3fd086aff195d3849dcf847d6b0bd927.tar.gz openwrt-5c105d9f3fd086aff195d3849dcf847d6b0bd927.zip | |
branch Attitude Adjustment
git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@33625 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/files/arch/mips/include')
25 files changed, 9943 insertions, 0 deletions
diff --git a/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h b/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h new file mode 100644 index 000000000..262475414 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h @@ -0,0 +1,25 @@ +/* + * based on arch/arm/include/asm/clkdev.h + * + * Copyright (C) 2008 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Helper for the clk API to assist looking up a struct clk. + */ +#ifndef __ASM_CLKDEV_H +#define __ASM_CLKDEV_H + +#include <linux/slab.h> + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) +{ + return kzalloc(size, GFP_KERNEL); +} + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h new file mode 100644 index 000000000..adb531c39 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h @@ -0,0 +1,26 @@ +/* + * Lantiq GPIO button support + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _LANTIQ_DEV_GPIO_BUTTONS_H +#define _LANTIQ_DEV_GPIO_BUTTONS_H + +#include <linux/input.h> +#include <linux/gpio_keys.h> + +#define LTQ_KEYS_POLL_INTERVAL 20 /* msecs */ +#define LTQ_KEYS_DEBOUNCE_INTERVAL (3 * LTQ_KEYS_POLL_INTERVAL) + +void ltq_register_gpio_keys_polled(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons); + +#endif /* _LANTIQ_DEV_GPIO_BUTTONS_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h new file mode 100644 index 000000000..d51e496d1 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h @@ -0,0 +1,21 @@ +/* + * Lantiq GPIO LED device support + * + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _LANTIQ_DEV_LEDS_GPIO_H +#define _LANTIQ_DEV_LEDS_GPIO_H + +#include <linux/leds.h> + +void ltq_add_device_gpio_leds(int id, + unsigned num_leds, + struct gpio_led *leds) __init; + +#endif /* _LANTIQ_DEV_LEDS_GPIO_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h new file mode 100644 index 000000000..4dc6466e8 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -0,0 +1,268 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> + */ + +#ifndef _FALCON_IRQ__ +#define _FALCON_IRQ__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define MIPS_CPU_TIMER_IRQ 7 + +/* HOST IF Event Interrupt */ +#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) +/* HOST IF Mailbox0 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) +/* HOST IF Mailbox0 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) +/* HOST IF Mailbox1 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) +/* HOST IF Mailbox1 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) +/* I2C Last Single Data Transfer Request */ +#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) +/* I2C Single Data Transfer Request */ +#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) +/* I2C Last Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) +/* I2C Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) +/* I2C Error Interrupt */ +#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) +/* I2C Protocol Interrupt */ +#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) +/* SSC Transmit Interrupt */ +#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) +/* SSC Receive Interrupt */ +#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) +/* SSC Error Interrupt */ +#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) +/* SSC Frame Interrupt */ +#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) +/* Advanced Encryption Standard Interrupt */ +#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) +/* Secure Hash Algorithm Interrupt */ +#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) +/* PCM Receive Interrupt */ +#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) +/* PCM Transmit Interrupt */ +#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) +/* PCM Transmit Crash Interrupt */ +#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) + +/* EBU Serial Flash Command Error */ +#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) +/* EBU Serial Flash Command Overwrite Error */ +#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) +/* EBU Serial Flash Busy */ +#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) +/* External Interrupt from GPIO P0 */ +#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) +/* External Interrupt from GPIO P1 */ +#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) +/* External Interrupt from GPIO P2 */ +#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) +/* External Interrupt from GPIO P3 */ +#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) +/* External Interrupt from GPIO P4 */ +#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) +/* 8kHz backup interrupt derived from core-PLL */ +#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) +/* FSC Timer Interrupt 0 */ +#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) +/* FSC Timer Interrupt 1 */ +#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) +/* 8kHz root interrupt derived from GPON interface */ +#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) +/* Time of Day */ +#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) +/* PMA Interrupt from IntNode of the 200MHz Domain */ +#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) +/* PMA Interrupt from IntNode of the TX Clk Domain */ +#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) +/* PMA Interrupt from IntNode of the RX Clk Domain */ +#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) +/* SYS1 Interrupt */ +#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) +/* SYS GPE Interrupt */ +#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) +/* Watchdog Access Error Interrupt */ +#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) +/* Watchdog Prewarning Interrupt */ +#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) +/* SBIU interrupt */ +#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) +/* FPI Bus Control Unit Interrupt */ +#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) +/* DDR Controller Interrupt */ +#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) +/* Crossbar Error Interrupt */ +#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) + +/* ICTRLL 0 Interrupt */ +#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) +/* ICTRLL 1 Interrupt */ +#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) +/* ICTRLL 2 Interrupt */ +#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) +/* ICTRLL 3 Interrupt */ +#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) +/* OCTRLL 0 Interrupt */ +#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) +/* OCTRLL 1 Interrupt */ +#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) +/* OCTRLL 2 Interrupt */ +#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) +/* OCTRLL 3 Interrupt */ +#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) +/* OCTRLG Interrupt */ +#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) +/* IQM Interrupt */ +#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) +/* FSQM Interrupt */ +#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) +/* TMU Interrupt */ +#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) +/* LINK1 Interrupt */ +#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) +/* ICTRLC 0 Interrupt */ +#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) +/* ICTRLC 1 Interrupt */ +#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) +/* OCTRLC Interrupt */ +#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) +/* CONFIG Break Interrupt */ +#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) +/* CONFIG Interrupt */ +#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) +/* Dispatcher Interrupt */ +#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) +/* TBM Interrupt */ +#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) +/* GTC Downstream Interrupt */ +#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) +/* GTC Upstream Interrupt */ +#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) +/* EIM Interrupt */ +#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) + +/* ASC0 Transmit Interrupt */ +#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) +/* ASC0 Receive Interrupt */ +#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) +/* ASC0 Error Interrupt */ +#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) +/* ASC0 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) +/* ASC0 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) +/* ASC0 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) +/* ASC0 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) +/* ASC1 Transmit Interrupt */ +#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) +/* ASC1 Receive Interrupt */ +#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) +/* ASC1 Error Interrupt */ +#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) +/* ASC1 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) +/* ASC1 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) +/* ASC1 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) +/* ASC1 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) +/* GPTC Timer/Counter 1A Interrupt */ +#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) +/* GPTC Timer/Counter 1B Interrupt */ +#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) +/* GPTC Timer/Counter 2A Interrupt */ +#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) +/* GPTC Timer/Counter 2B Interrupt */ +#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) +/* GPTC Timer/Counter 3A Interrupt */ +#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) +/* GPTC Timer/Counter 3B Interrupt */ +#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) +/* DFEV0, Channel 1 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) +/* DFEV0, Channel 1 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) +/* DFEV0, Channel 1 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) +/* DFEV0, Channel 0 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) +/* DFEV0, Channel 0 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) +/* DFEV0, Channel 0 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) + +/* ICTRLL 0 Error */ +#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) +/* ICTRLL 1 Error */ +#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) +/* ICTRLL 2 Error */ +#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) +/* ICTRLL 3 Error */ +#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) +/* OCTRLL 0 Error */ +#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) +/* OCTRLL 1 Error */ +#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) +/* OCTRLL 2 Error */ +#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) +/* OCTRLL 3 Error */ +#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) +/* ICTRLG Error */ +#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) +/* OCTRLG Error */ +#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) +/* IQM Error */ +#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) +/* FSQM Error */ +#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) +/* TMU Error */ +#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) +/* MPS Status Interrupt #0 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) +/* MPS Status Interrupt #1 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) +/* MPS Status Interrupt #2 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) +/* MPS Status Interrupt #3 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) +/* MPS Status Interrupt #4 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) +/* MPS Status Interrupt #5 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) +/* MPS Status Interrupt #6 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) +/* MPS Status Interrupt #7 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) +/* MPS Status Interrupt #8 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) +/* VPE0 Exception Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) +/* VPE0 Error Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) +/* VPE0 Performance Monitoring Counter Interrupt */ +#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) + +#endif /* _FALCON_IRQ__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h new file mode 100644 index 000000000..2caccd9f9 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> + */ + +#ifndef __FALCON_IRQ_H +#define __FALCON_IRQ_H + +#include <falcon_irq.h> + +#define NR_IRQS 328 + +#include_next <irq.h> + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h new file mode 100644 index 000000000..fff5ecdbe --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -0,0 +1,152 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#ifndef _LTQ_FALCON_H__ +#define _LTQ_FALCON_H__ + +#ifdef CONFIG_SOC_FALCON + +#include <lantiq.h> + +/* Chip IDs */ +#define SOC_ID_FALCON 0x01B8 + +/* SoC Types */ +#define SOC_TYPE_FALCON 0x01 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x1E100C00 +#define LTQ_ASC1_BASE_ADDR 0x1E100B00 +#define LTQ_ASC_SIZE 0x100 + +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) + +/* + * during early_printk no ioremap possible at this early stage + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_ICU_SIZE 0x100 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 +#define LTQ_WDT_SIZE 0x10 + +#define LTQ_RST_CAUSE_WDTRST 0x0002 + +/* EBU - external bus unit */ +#define LTQ_EBU_BASE_ADDR 0x18000000 +#define LTQ_EBU_SIZE 0x0100 + +#define LTQ_EBU_MODCON 0x000C + +/* GPIO */ +#define LTQ_GPIO0_BASE_ADDR 0x1D810000 +#define LTQ_GPIO0_SIZE 0x0080 +#define LTQ_GPIO1_BASE_ADDR 0x1E800100 +#define LTQ_GPIO1_SIZE 0x0080 +#define LTQ_GPIO2_BASE_ADDR 0x1D810100 +#define LTQ_GPIO2_SIZE 0x0080 +#define LTQ_GPIO3_BASE_ADDR 0x1E800200 +#define LTQ_GPIO3_SIZE 0x0080 +#define LTQ_GPIO4_BASE_ADDR 0x1E800300 +#define LTQ_GPIO4_SIZE 0x0080 +#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 +#define LTQ_PADCTRL0_SIZE 0x0100 +#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 +#define LTQ_PADCTRL1_SIZE 0x0100 +#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 +#define LTQ_PADCTRL2_SIZE 0x0100 +#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 +#define LTQ_PADCTRL3_SIZE 0x0100 +#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 +#define LTQ_PADCTRL4_SIZE 0x0100 + +/* I2C */ +#define GPON_I2C_BASE 0x1E200000 +#define GPON_I2C_SIZE 0x00010000 + +/* CHIP ID */ +#define LTQ_STATUS_BASE_ADDR 0x1E802000 + +#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) +#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) +#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) + +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ +#define LTQ_SYS1_BASE_ADDR 0x1EF00000 +#define LTQ_SYS1_SIZE 0x0100 +#define LTQ_STATUS_BASE_ADDR 0x1E802000 +#define LTQ_STATUS_SIZE 0x0080 +#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 +#define LTQ_SYS_ETH_SIZE 0x0100 +#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 +#define LTQ_SYS_GPE_SIZE 0x0100 + +#define SYSCTL_SYS1 0 +#define SYSCTL_SYSETH 1 +#define SYSCTL_SYSGPE 2 + +/* Activation Status Register */ +#define ACTS_ASC1_ACT 0x00000800 +#define ACTS_I2C_ACT 0x00004000 +#define ACTS_P0 0x00010000 +#define ACTS_P1 0x00010000 +#define ACTS_P2 0x00020000 +#define ACTS_P3 0x00020000 +#define ACTS_P4 0x00040000 +#define ACTS_PADCTRL0 0x00100000 +#define ACTS_PADCTRL1 0x00100000 +#define ACTS_PADCTRL2 0x00200000 +#define ACTS_PADCTRL3 0x00200000 +#define ACTS_PADCTRL4 0x00400000 +#define ACTS_I2C_ACT 0x00004000 + +/* global register ranges */ +extern __iomem void *ltq_ebu_membase; +extern __iomem void *ltq_sys1_membase; +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) +#define ltq_ebu_w32_mask(clear, set, reg) \ + ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) + +#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) +#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) +#define ltq_sys1_w32_mask(clear, set, reg) \ + ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) + +/* gpio wrapper to help configure the pin muxing */ +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); + +/* to keep the irq code generic we need to define these to 0 as falcon + has no EIU/EBU */ +#define LTQ_EIU_BASE_ADDR 0 +#define LTQ_EBU_PCC_ISTAT 0 + +static inline int ltq_is_ar9(void) +{ + return 0; +} + +static inline int ltq_is_vr9(void) +{ + return 0; +} + +static inline int ltq_is_falcon(void) +{ + return 1; +} + +#endif /* CONFIG_SOC_FALCON */ +#endif /* _LTQ_XWAY_H__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h new file mode 100644 index 000000000..ef564abc3 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h @@ -0,0 +1,155 @@ +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ + + +/****************************************************************************** + Copyright (c) 2002, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. +******************************************************************************/ + + +/* + * #################################### + * Definition + * #################################### + */ + +/* + * Available Timer/Counter Index + */ +#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) +#define TIMER_ANY 0x00 +#define TIMER1A TIMER(1, 0) +#define TIMER1B TIMER(1, 1) +#define TIMER2A TIMER(2, 0) +#define TIMER2B TIMER(2, 1) +#define TIMER3A TIMER(3, 0) +#define TIMER3B TIMER(3, 1) + +/* + * Flag of Timer/Counter + * These flags specify the way in which timer is configured. + */ +/* Bit size of timer/counter. */ +#define TIMER_FLAG_16BIT 0x0000 +#define TIMER_FLAG_32BIT 0x0001 +/* Switch between timer and counter. */ +#define TIMER_FLAG_TIMER 0x0000 +#define TIMER_FLAG_COUNTER 0x0002 +/* Stop or continue when overflowing/underflowing. */ +#define TIMER_FLAG_ONCE 0x0000 +#define TIMER_FLAG_CYCLIC 0x0004 +/* Count up or counter down. */ +#define TIMER_FLAG_UP 0x0000 +#define TIMER_FLAG_DOWN 0x0008 +/* Count on specific level or edge. */ +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 +#define TIMER_FLAG_RISE_EDGE 0x0010 +#define TIMER_FLAG_FALL_EDGE 0x0020 +#define TIMER_FLAG_ANY_EDGE 0x0030 +/* Signal is syncronous to module clock or not. */ +#define TIMER_FLAG_UNSYNC 0x0000 +#define TIMER_FLAG_SYNC 0x0080 +/* Different interrupt handle type. */ +#define TIMER_FLAG_NO_HANDLE 0x0000 +#if defined(__KERNEL__) + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 +#endif // defined(__KERNEL__) +#define TIMER_FLAG_SIGNAL 0x0300 +/* Internal clock source or external clock source */ +#define TIMER_FLAG_INT_SRC 0x0000 +#define TIMER_FLAG_EXT_SRC 0x1000 + + +/* + * ioctl Command + */ +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ + +/* + * Data Type Used to Call ioctl + */ +struct gptu_ioctl_param { + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * + * GPTU_SET_COUNTER, this field is ID of expected * + * timer/counter. If it's zero, a timer/counter would * + * be dynamically allocated and ID would be stored in * + * this field. * + * In command GPTU_GET_COUNT_VALUE, this field is * + * ignored. * + * In other command, this field is ID of timer/counter * + * allocated. */ + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * + * GPTU_SET_COUNTER, this field contains flags to * + * specify how to configure timer/counter. * + * In command GPTU_START_TIMER, zero indicate start * + * and non-zero indicate resume timer/counter. * + * In other command, this field is ignored. */ + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * + * init/reload value. * + * In command GPTU_SET_TIMER, this field contains * + * frequency (0.001Hz) of timer. * + * In command GPTU_GET_COUNT_VALUE, current count * + * value would be stored in this field. * + * In command GPTU_CALCULATE_DIVIDER, this field * + * contains frequency wanted, and after calculation, * + * divider would be stored in this field to overwrite * + * the frequency. * + * In other command, this field is ignored. */ + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * + * if signal is required, this field contains process * + * ID to which signal would be sent. * + * In other command, this field is ignored. */ + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * + * if signal is required, this field contains signal * + * number which would be sent. * + * In other command, this field is ignored. */ +}; + +/* + * #################################### + * Data Type + * #################################### + */ +typedef void (*timer_callback)(unsigned long arg); + +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); +extern int lq_free_timer(unsigned int); +extern int lq_start_timer(unsigned int, int); +extern int lq_stop_timer(unsigned int); +extern int lq_reset_counter_flags(u32 timer, u32 flags); +extern int lq_get_count_value(unsigned int, unsigned long *); +extern u32 lq_cal_divider(unsigned long); +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); +extern int lq_set_counter(unsigned int timer, unsigned int flag, + u32 reload, unsigned long arg1, unsigned long arg2); + +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h new file mode 100644 index 000000000..8149f1204 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h @@ -0,0 +1,56 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __BASE_REG_H +#define __BASE_REG_H + +#ifndef KSEG1 +#define KSEG1 0xA0000000 +#endif + +#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000) +#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000) +#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000) +#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000) + +#define LTQ_ASC0_BASE (KSEG1 + 0x14100100) +#define LTQ_ASC1_BASE (KSEG1 + 0x14100200) + +#define LTQ_SSC0_BASE (0x14100300) +#define LTQ_SSC1_BASE (0x14100400) + +#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600) +#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100) +#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800) +#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900) +#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400) + +#define LTQ_EBU_BASE (KSEG1 + 0x14102000) +#define LTQ_DMA_BASE (KSEG1 + 0x14104000) + +#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000) +#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000) + +#define LTQ_ES_BASE (KSEG1 + 0x18000000) + +#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000) +#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800) +#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000) + +#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000) + +#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100) +#define LTQ_MBS_BASE (KSEG1 + 0x1E000200) + +#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h new file mode 100644 index 000000000..9c33516e8 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h @@ -0,0 +1,37 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + +******************************************************************************/ + +#ifndef __BOOT_REG_H +#define __BOOT_REG_H + +#define LTQ_BOOT_CPU_OFFSET 0x20 + +#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00) +#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04) +#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08) +#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C) +#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10) +#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14) +#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */ +#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */ +#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h new file mode 100644 index 000000000..9fde2f6dd --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h @@ -0,0 +1,308 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __DMA_REG_H +#define __DMA_REG_H + +#define dma_r32(reg) ltq_r32(&dma->reg) +#define dma_w32(val, reg) ltq_w32(val, &dma->reg) +#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg) + +/** DMA register structure */ +struct svip_reg_dma { + volatile unsigned long clc; /* 0x00 */ + volatile unsigned long reserved0; /* 0x04 */ + volatile unsigned long id; /* 0x08 */ + volatile unsigned long reserved1; /* 0x0c */ + volatile unsigned long ctrl; /* 0x10 */ + volatile unsigned long cpoll; /* 0x14 */ + volatile unsigned long cs; /* 0x18 */ + volatile unsigned long cctrl; /* 0x1C */ + volatile unsigned long cdba; /* 0x20 */ + volatile unsigned long cdlen; /* 0x24 */ + volatile unsigned long cis; /* 0x28 */ + volatile unsigned long cie; /* 0x2C */ + volatile unsigned long cgbl; /* 0x30 */ + volatile unsigned long reserved2[3]; /* 0x34 */ + volatile unsigned long ps; /* 0x40 */ + volatile unsigned long pctrl; /* 0x44 */ + volatile unsigned long reserved3[43]; /* 0x48 */ + volatile unsigned long irnen; /* 0xF4 */ + volatile unsigned long irncr; /* 0xF8 */ + volatile unsigned long irnicr; /* 0xFC */ +}; + +/******************************************************************************* + * CLC Register + ******************************************************************************/ + +/* Fast Shut-Off Enable Bit (5) */ +#define DMA_CLC_FSOE (0x1 << 5) +#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) +#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1) +#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5)) +/* Suspend Bit Write Enable for OCDS (4) */ +#define DMA_CLC_SBWE (0x1 << 4) +#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) +#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4) +/* External Request Disable (3) */ +#define DMA_CLC_EDIS (0x1 << 3) +#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) +#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1) +#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3)) +/* Suspend Enable Bit for OCDS (2) */ +#define DMA_CLC_SPEN (0x1 << 2) +#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) +#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1) +#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2)) +/* Disable Status Bit (1) */ +#define DMA_CLC_DISS (0x1 << 1) +#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1) +/* Disable Request Bit (0) */ +#define DMA_CLC_DISR (0x1) +#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0) +#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1) +#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * ID Register + ******************************************************************************/ + +/* Number of Channels (25:20) */ +#define DMA_ID_CHNR (0x3f << 20) +#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f) +/* Number of Ports (19:16) */ +#define DMA_ID_PRTNR (0xf << 16) +#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf) +/* Module ID (15:8) */ +#define DMA_ID_ID (0xff << 8) +#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff) +/* Revision (4:0) */ +#define DMA_ID_REV (0x1f) +#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f) + +/******************************************************************************* + * Control Register + ******************************************************************************/ + +/* Global Software Reset (0) */ +#define DMA_CTRL_RST (0x1) +#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1) + +/******************************************************************************* + * Channel Polling Register + ******************************************************************************/ + +/* Enable (31) */ +#define DMA_CPOLL_EN (0x1 << 31) +#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) +#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1) +#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31)) +/* Counter (15:4) */ +#define DMA_CPOLL_CNT (0xfff << 4) +#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) +#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff) +#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4)) + +/******************************************************************************* + * Global Buffer Length Register + ******************************************************************************/ + +/* Global Buffer Length (15:0) */ +#define DMA_CGBL_GBL (0xffff) +#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0) +#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff) +#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * Channel Select Register + ******************************************************************************/ + +/* Channel Selection (4:0) */ +#define DMA_CS_CS (0x1f) +#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0) +#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f) +#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0)) + +/******************************************************************************* + * Channel Control Register + ******************************************************************************/ + +/* Peripheral to Peripheral Copy (24) */ +#define DMA_CCTRL_P2PCPY (0x1 << 24) +#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) +#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1) +#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24)) +/* Channel Weight for Transmit Direction (17:16) */ +#define DMA_CCTRL_TXWGT (0x3 << 16) +#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) +#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3) +#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16)) +/* Port Assignment (13:11) */ +#define DMA_CCTRL_PRTNR (0x7 << 11) +#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7) +/* Class (10:9) */ +#define DMA_CCTRL_CLASS (0x3 << 9) +#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) +#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3) +#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9)) +/* Direction (8) */ +#define DMA_CCTRL_DIR (0x1 << 8) +#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1) +/* Reset (1) */ +#define DMA_CCTRL_RST (0x1 << 1) +#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1) +#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1) +#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1)) +/* Channel On or Off (0) */ +#define DMA_CCTRL_ON_OFF (0x1) +#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0) +#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1) +#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Channel Descriptor Base Address Register + ******************************************************************************/ + +/* Channel Descriptor Base Address (29:3) */ +#define DMA_CDBA_CDBA (0x7ffffff << 3) +#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3) +#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff) +#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3)) + +/******************************************************************************* + * Channel Descriptor Length Register + ******************************************************************************/ + +/* Channel Descriptor Length (7:0) */ +#define DMA_CDLEN_CDLEN (0xff) +#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0) +#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff) +#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * Channel Interrupt Status Register + ******************************************************************************/ + +/* SAI Read Error Interrupt (5) */ +#define DMA_CIS_RDERR (0x1 << 5) +#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1) +/* Channel Off Interrupt (4) */ +#define DMA_CIS_CHOFF (0x1 << 4) +#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1) +/* Descriptor Complete Interrupt (3) */ +#define DMA_CIS_DESCPT (0x1 << 3) +#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1) +/* Descriptor Under-Run Interrupt (2) */ +#define DMA_CIS_DUR (0x1 << 2) +#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1) +/* End of Packet Interrupt (1) */ +#define DMA_CIS_EOP (0x1 << 1) +#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1) + +/******************************************************************************* + * Channel Interrupt Enable Register + ******************************************************************************/ + +/* SAI Read Error Interrupt (5) */ +#define DMA_CIE_RDERR (0x1 << 5) +#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1) +/* Channel Off Interrupt (4) */ +#define DMA_CIE_CHOFF (0x1 << 4) +#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1) +/* Descriptor Complete Interrupt Enable (3) */ +#define DMA_CIE_DESCPT (0x1 << 3) +#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1) +/* Descriptor Under Run Interrupt Enable (2) */ +#define DMA_CIE_DUR (0x1 << 2) +#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1) +/* End of Packet Interrupt Enable (1) */ +#define DMA_CIE_EOP (0x1 << 1) +#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1) + +/******************************************************************************* + * Port Select Register + ******************************************************************************/ + +/* Port Selection (2:0) */ +#define DMA_PS_PS (0x7) +#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) +#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7) +#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0)) + +/******************************************************************************* + * Port Control Register + ******************************************************************************/ + +/* General Purpose Control (16) */ +#define DMA_PCTRL_GPC (0x1 << 16) +#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) +#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1) +#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16)) +/* Port Weight for Transmit Direction (14:12) */ +#define DMA_PCTRL_TXWGT (0x7 << 12) +#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) +#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7) +#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12)) +/* Endianness for Transmit Direction (11:10) */ +#define DMA_PCTRL_TXENDI (0x3 << 10) +#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) +#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3) +#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10)) +/* Endianness for Receive Direction (9:8) */ +#define DMA_PCTRL_RXENDI (0x3 << 8) +#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) +#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3) +#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8)) +/* Packet Drop Enable (6) */ +#define DMA_PCTRL_PDEN (0x1 << 6) +#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) +#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1) +#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6)) +/* Burst Length for Transmit Direction (5:4) */ +#define DMA_PCTRL_TXBL (0x3 << 4) +#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) +#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3) +#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4)) +/* Burst Length for Receive Direction (3:2) */ +#define DMA_PCTRL_RXBL (0x3 << 2) +#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) +#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3) +#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2)) + +/******************************************************************************* + * DMA_IRNEN Register + ******************************************************************************/ + +/* Channel x Interrupt Request Enable (23) */ +#define DMA_IRNEN_CH23 (0x1 << 23) +#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23) +#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1) +#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23)) + +/******************************************************************************* + * DMA_IRNCR Register + ******************************************************************************/ + +/* Channel x Interrupt (23) */ +#define DMA_IRNCR_CH23 (0x1 << 23) +#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1) + +/******************************************************************************* + * DMA_IRNICR Register + ******************************************************************************/ + +/* Channel x Interrupt Request (23) */ +#define DMA_IRNICR_CH23 (0x1 << 23) +#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h new file mode 100644 index 000000000..4e00d01ba --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h @@ -0,0 +1,615 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __EBU_REG_H +#define __EBU_REG_H + +#define ebu_r32(reg) ltq_r32(&ebu->reg) +#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg) +#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg) + +/** EBU register structure */ +struct svip_reg_ebu { + volatile unsigned long clc; /* 0x0000 */ + volatile unsigned long reserved0; /* 0x04 */ + volatile unsigned long id; /* 0x0008 */ + volatile unsigned long reserved1; /* 0x0c */ + volatile unsigned long con; /* 0x0010 */ + volatile unsigned long reserved2[3]; /* 0x14 */ + volatile unsigned long addr_sel_0; /* 0x0020 */ + volatile unsigned long addr_sel_1; /* 0x0024 */ + volatile unsigned long addr_sel_2; /* 0x0028 */ + volatile unsigned long addr_sel_3; /* 0x002c */ + volatile unsigned long reserved3[12]; /* 0x30 */ + volatile unsigned long con_0; /* 0x0060 */ + volatile unsigned long con_1; /* 0x0064 */ + volatile unsigned long con_2; /* 0x0068 */ + volatile unsigned long con_3; /* 0x006c */ + volatile unsigned long reserved4[4]; /* 0x70 */ + volatile unsigned long emu_addr; /* 0x0080 */ + volatile unsigned long emu_bc; /* 0x0084 */ + volatile unsigned long emu_con; /* 0x0088 */ + volatile unsigned long reserved5; /* 0x8c */ + volatile unsigned long pcc_con; /* 0x0090 */ + volatile unsigned long pcc_stat; /* 0x0094 */ + volatile unsigned long reserved6[2]; /* 0x98 */ + volatile unsigned long pcc_istat; /* 0x00A0 */ + volatile unsigned long pcc_ien; /* 0x00A4 */ + volatile unsigned long pcc_int_out; /* 0x00A8 */ + volatile unsigned long pcc_irs; /* 0x00AC */ + volatile unsigned long nand_con; /* 0x00B0 */ + volatile unsigned long nand_wait; /* 0x00B4 */ + volatile unsigned long nand_ecc0; /* 0x00B8 */ + volatile unsigned long nand_ecc_ac; /* 0x00BC */ +}; + +/******************************************************************************* + * EBU + ******************************************************************************/ +#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000)) +#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008)) +#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010)) +#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020)) +#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024)) +#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028)) +#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c)) +#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060)) +#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064)) +#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068)) +#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c)) +#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084)) +#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090)) +#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094)) +#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0)) +#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4)) +#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8)) +#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC)) +#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0)) +#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4)) +#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8)) +#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC)) +#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080)) +#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088)) + +/******************************************************************************* + * EBU Clock Control Register + ******************************************************************************/ + +/* EBU Disable Status Bit (1) */ +#define LTQ_EBU_CLC_DISS (0x1 << 1) +#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1) +/* Used for Enable/disable Control of the EBU (0) */ +#define LTQ_EBU_CLC_DISR (0x1) +#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1) +#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * EBU Identification Register (Internal) + ******************************************************************************/ + +/* Module Number (31:8) */ +#define LTQ_EBU_ID_MODNUM (0xffffff << 8) +#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff) +/* Revision Number (7:0) */ +#define LTQ_EBU_ID_REVNUM (0xff) +#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff) + +/******************************************************************************* + * External Bus Unit Control Register + ******************************************************************************/ + +/* Driver Turn-Around Control, Chip Select Triggered (22:20) */ +#define LTQ_EBU_CON_DTACS (0x7 << 20) +#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20) +#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7) +#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20)) +/* Driver Turn-Around Control, Read-write Triggered (18:16) */ +#define LTQ_EBU_CON_DTARW (0x7 << 16) +#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16) +#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7) +#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16)) +/* Time-Out Control (15:8) */ +#define LTQ_EBU_CON_TOUTC (0xff << 8) +#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8) +#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff) +#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8)) +/* Arbitration Mode (7:6) */ +#define LTQ_EBU_CON_ARBMODE (0x3 << 6) +#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6) +#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3) +#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6)) +/* Arbitration Synchronization (5) */ +#define LTQ_EBU_CON_ARBSYNC (0x1 << 5) +#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5) +#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1) +#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5)) + +/******************************************************************************* + * Address Select Registers + ******************************************************************************/ + +/* Memory Region Base Address (31:12) */ +#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12) +#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12) +#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff) +#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12)) +/* Memory Region Address Mask (7:4) */ +#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4) +#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4) +#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf) +#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4)) +/* Memory Region Mirror Enable Control (1) */ +#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1) +#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1) +#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1)) +/* Memory Region Enable Control (0) */ +#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1) +#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1) +#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Bus Configuration Registers + ******************************************************************************/ + +/* Memory Region Write Protection (31) */ +#define LTQ_EBU_CON_0_WRDIS (0x1 << 31) +#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31) +#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1) +#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31)) +/* Address Swapping (30) */ +#define LTQ_EBU_CON_0_ADSWP (0x1 << 30) +#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30) +#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1) +#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30)) +/* Address Generation Control (26:24) */ +#define LTQ_EBU_CON_0_AGEN (0x7 << 24) +#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24) +#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7) +#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24)) +/* Extended Address Setup Control (22) */ +#define LTQ_EBU_CON_0_SETUP (0x1 << 22) +#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22) +#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1) +#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22)) +/* Variable Wait-State Insertion Control (21:20) */ +#define LTQ_EBU_CON_0_WAIT (0x3 << 20) +#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20) +#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3) +#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20)) +/* Active WAIT Level Control (19) */ +#define LTQ_EBU_CON_0_WINV (0x1 << 19) +#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19) +#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1) +#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19)) +/* External Device Data Width Control (17:16) */ +#define LTQ_EBU_CON_0_PW (0x3 << 16) +#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16) +#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3) +#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16)) +/* Address Latch Enable ALE Duration Control (15:14) */ +#define LTQ_EBU_CON_0_ALEC (0x3 << 14) +#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14) +#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3) +#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14)) +/* Byte Control Signal Timing Mode Control (13:12) */ +#define LTQ_EBU_CON_0_BCGEN (0x3 << 12) +#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12) +#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3) +#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12)) +/* Write Access Wait-State Control (10:8) */ +#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8) +#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8) +#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7) +#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8)) +/* Read Access Wait-State Control (7:6) */ +#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6) +#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6) +#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3) +#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6)) +/* Hold/Pause Cycle Control (5:4) */ +#define LTQ_EBU_CON_0_HOLDC (0x3 << 4) +#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4) +#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3) +#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4)) +/* Recovery Cycle Control (3:2) */ +#define LTQ_EBU_CON_0_RECOVC (0x3 << 2) +#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2) +#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3) +#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2)) +/* Wait Cycle Multiplier Control (1:0) */ +#define LTQ_EBU_CON_0_CMULT (0x3) +#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0) +#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3) +#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * External Bus Unit Emulator Bus Configuration Register + ******************************************************************************/ + +/* Write Protection (31) */ +#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31) +#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31) +#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1) +#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31)) +/* Address Generation Control (26:24) */ +#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24) +#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24) +#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7) +#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24)) +/* Extended Address Setup Control (22) */ +#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22) +#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22) +#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1) +#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22)) +/* Variable Waitstate Insertion Control (21:20) */ +#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20) +#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20) +#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3) +#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20)) +/* Active WAIT Level Control (19) */ +#define LTQ_EBU_EMU_BC_WINV (0x1 << 19) +#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19) +#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1) +#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19)) +/* External Device Data Width Control (17:16) */ +#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16) +#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16) +#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3) +#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16)) +/* Address Latch Enable Function (15:14) */ +#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14) +#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14) +#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3) +#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14)) +/* Byte Control Signal Timing Mode (13:12) */ +#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12) +#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12) +#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3) +#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12)) +/* Write Access Waitstate Control (10:8) */ +#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8) +#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8) +#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7) +#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8)) +/* Read Access Waitstate Control (7:6) */ +#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6) +#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6) +#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3) +#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6)) +/* Hold/Pause Cycle Control (5:4) */ +#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4) +#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4) +#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3) +#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4)) +/* Recovery Cycles Control (3:2) */ +#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2) +#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2) +#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3) +#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2)) +/* Cycle Multiplier Control (1:0) */ +#define LTQ_EBU_EMU_BC_CMULT (0x3) +#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0) +#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3) +#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * PC-Card Control Register + ******************************************************************************/ + +/* External Interrupt Input IREQ (3:1) */ +#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1) +#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1) +#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7) +#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1)) +/* PC Card ON (0) */ +#define LTQ_EBU_PCC_CON_ON (0x1) +#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1) +#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PCC Status Register + ******************************************************************************/ + +/* Interrupt Request (6) */ +#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6) +#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1) +/* PC-Card Overcurrent (5) */ +#define LTQ_EBU_PCC_STAT_OC (0x1 << 5) +#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1) +/* PC-Card Socket Power On (4) */ +#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4) +#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1) +/* Card Detect Status (1:0) */ +#define LTQ_EBU_PCC_STAT_CD (0x3) +#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3) + +/******************************************************************************* + * PCC Interrupt Status Register + ******************************************************************************/ + +/* Interrupt Request Active Interrupt (4) */ +#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4) +#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1) +#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4)) +/* Over Current Status Change Interrupt (3) */ +#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3) +#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1) +#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3)) +/* Socket Power on Status Change Interrupt (2) */ +#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2) +#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1) +#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2)) +/* Voltage Sense Status Change Interrupt (1) */ +#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1) +#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1) +#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1)) +/* Card Detect Status Change Interrupt (0) */ +#define LTQ_EBU_PCC_ISTAT_CD (0x1) +#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1) +#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PCC Interrupt Enable Register + ******************************************************************************/ + +/* Enable of Interrupt Request IR (4) */ +#define LTQ_EBU_PCC_IEN_IR (0x1 << 4) +#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1) +#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4)) +/* Enable of Interrupt Request OC event (3) */ +#define LTQ_EBU_PCC_IEN_OC (0x1 << 3) +#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1) +#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3)) +/* Enable of Interrupt Request Socket Power On (2) */ +#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2) +#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1) +#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2)) +/* Enable of Interrupt Request Voltage Sense (1) */ +#define LTQ_EBU_PCC_IEN_VS (0x1 << 1) +#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1) +#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1)) +/* Enable of Interrupt Request Card Detect (0) */ +#define LTQ_EBU_PCC_IEN_CD (0x1) +#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1) +#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PCC Interrupt Output Status Register + ******************************************************************************/ + +/* Status of Interrupt Request IR (4) */ +#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4) +#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1) +/* Status of Interrupt Request OC (3) */ +#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3) +#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1) +/* Status of Interrupt Request Socket Power On (2) */ +#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2) +#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1) +/* Status of Interrupt Request Voltage Sense (1) */ +#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1) +#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1) +/* Status of Interrupt Request Card Detect (0) */ +#define LTQ_EBU_PCC_INT_OUT_CD (0x1) +#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1) + +/******************************************************************************* + * PCC Interrupt Request Set Register + ******************************************************************************/ + +/* Set Interrupt Request IR (4) */ +#define LTQ_EBU_PCC_IRS_IR (0x1 << 4) +#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4) +/* Set Interrupt Request OC (3) */ +#define LTQ_EBU_PCC_IRS_OC (0x1 << 3) +#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3) +/* Set Interrupt Request Socket Power On (2) */ +#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2) +#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2) +/* Set Interrupt Request Voltage Sense (1) */ +#define LTQ_EBU_PCC_IRS_VS (0x1 << 1) +#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1) +/* Set Interrupt Request Card Detect (0) */ +#define LTQ_EBU_PCC_IRS_CD (0x1) +#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0) + +/******************************************************************************* + * NAND Flash Control Register + ******************************************************************************/ + +/* ECC Enabling (31) */ +#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31) +#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31) +#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1) +#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31)) +/* Latch enable (23:18) */ +#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18) +#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18) +#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f) +#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18)) +/* Output ChipSelect# Selection (11:10) */ +#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10) +#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10) +#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3) +#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10)) +/* Input ChipSelect# Selection (9:8) */ +#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8) +#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8) +#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3) +#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8)) +/* Set PRE (7) */ +#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7) +#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7) +#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1) +#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7)) +/* Set WP Active Polarity (6) */ +#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6) +#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6) +#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1) +#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6)) +/* Set SE Active Polarity (5) */ +#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5) +#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5) +#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1) +#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5)) +/* Set CS Active Polarity (4) */ +#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4) +#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1) +#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4)) +/* Set CLE Active Polarity (3) */ +#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3) +#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1) +#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3)) +/* Set ALE Active Polarity (2) */ +#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2) +#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1) +#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2)) +/* NAND CS Mux with EBU CS Enable (1) */ +#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1) +#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1) +#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1)) +/* NAND FLASH Mode Support (0) */ +#define LTQ_EBU_NAND_CON_NANDMODE (0x1) +#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1) +#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * NAND Flash State Register + ******************************************************************************/ + +/* Reserved (31:3) */ +#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3) +#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff) +/* NAND Write Complete (3) */ +#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3) +#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1) +/* Record the RD Edge (rising ) (2) */ +#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2) +#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1) +/* Record the BY# Edge (falling) (1) */ +#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1) +#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1) +/* Rd/BY# value (0) */ +#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1) +#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1) + +/******************************************************************************* + * NAND ECC Result Register 0 + ******************************************************************************/ + +/* Reserved (31:24) */ +#define LTQ_EBU_NAND_ECC0_RES (0xff << 24) +#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff) +/* ECC value (23:16) */ +#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16) +#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16) +#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16)) +/* ECC value (15:8) */ +#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8) +#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8) +#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8)) +/* ECC value (7:0) */ +#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0) +#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * NAND ECC Address Counter Register + ******************************************************************************/ + +/* Reserved (31:9) */ +#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9) +#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff) +/* ECC address counter (8:0) */ +#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff) +#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0) +#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff) +#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0)) + +/******************************************************************************* + * Internal Address Emulation Register + ******************************************************************************/ + +/* Memory Region Base Address (31:12) */ +#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12) +#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12) +#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff) +#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12)) +/* Memory Region Address Mask (7:4) */ +#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4) +#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4) +#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf) +#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4)) +/* Memory Region Mirror Segment B Control (1) */ +#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1) +#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1) +#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1)) +/* Memory Region Enable Control (0) */ +#define LTQ_EBU_EMU_ADDR_MREC (0x1) +#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1) +#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * nternal Emulator Configuration Register + ******************************************************************************/ + +/* Overlay Memory Control Region 3 (3) */ +#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3) +#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1) +#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3)) +/* Overlay Memory Control Region 2 (2) */ +#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2) +#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1) +#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2)) +/* Overlay Memory Control Region 1 (1) */ +#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1) +#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1) +#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1)) +/* Overlay Memory Control Region 0 (0) */ +#define LTQ_EBU_EMU_CON_OVL0 (0x1) +#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1) +#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0)) + +#endif /* __LTQ_EBU_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h new file mode 100644 index 000000000..da84900f5 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h @@ -0,0 +1,2098 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __ES_REG_H +#define __ES_REG_H + +#define es_r32(reg) ltq_r32(&es->reg) +#define es_w32(val, reg) ltq_w32(val, &es->reg) +#define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg) + +/** ES register structure */ +struct svip_reg_es { + volatile unsigned long ps; /* 0x0000 */ + volatile unsigned long p0_ctl; /* 0x0004 */ + volatile unsigned long p1_ctl; /* 0x0008 */ + volatile unsigned long p2_ctl; /* 0x000C */ + volatile unsigned long p0_vlan; /* 0x0010 */ + volatile unsigned long p1_vlan; /* 0x0014 */ + volatile unsigned long p2_vlan; /* 0x0018 */ + volatile unsigned long reserved1[1]; /* 0x001C */ + volatile unsigned long p0_inctl; /* 0x0020 */ + volatile unsigned long p1_inctl; /* 0x0024 */ + volatile unsigned long p2_inctl; /* 0x0028 */ + volatile unsigned long reserved2[1]; /* 0x002C */ + volatile unsigned long p0_ecs_q32; /* 0x0030 */ + volatile unsigned long p0_ecs_q10; /* 0x0034 */ + volatile unsigned long p0_ecw_q32; /* 0x0038 */ + volatile unsigned long p0_ecw_q10; /* 0x003C */ + volatile unsigned long p1_ecs_q32; /* 0x0040 */ + volatile unsigned long p1_ecs_q10; /* 0x0044 */ + volatile unsigned long p1_ecw_q32; /* 0x0048 */ + volatile unsigned long p1_ecw_q10; /* 0x004C */ + volatile unsigned long p2_ecs_q32; /* 0x0050 */ + volatile unsigned long p2_ecs_q10; /* 0x0054 */ + volatile unsigned long p2_ecw_q32; /* 0x0058 */ + volatile unsigned long p2_ecw_q10; /* 0x005C */ + volatile unsigned long int_ena; /* 0x0060 */ + volatile unsigned long int_st; /* 0x0064 */ + volatile unsigned long sw_gctl0; /* 0x0068 */ + volatile unsigned long sw_gctl1; /* 0x006C */ + volatile unsigned long arp; /* 0x0070 */ + volatile unsigned long strm_ctl; /* 0x0074 */ + volatile unsigned long rgmii_ctl; /* 0x0078 */ + volatile unsigned long prt_1p; /* 0x007C */ + volatile unsigned long gbkt_szbs; /* 0x0080 */ + volatile unsigned long gbkt_szebs; /* 0x0084 */ + volatile unsigned long bf_th; /* 0x0088 */ + volatile unsigned long pmac_hd_ctl; /* 0x008C */ + volatile unsigned long pmac_sa1; /* 0x0090 */ + volatile unsigned long pmac_sa2; /* 0x0094 */ + volatile unsigned long pmac_da1; /* 0x0098 */ + volatile unsigned long pmac_da2; /* 0x009C */ + volatile unsigned long pmac_vlan; /* 0x00A0 */ + volatile unsigned long pmac_tx_ipg; /* 0x00A4 */ + volatile unsigned long pmac_rx_ipg; /* 0x00A8 */ + volatile unsigned long adr_tb_ctl0; /* 0x00AC */ + volatile unsigned long adr_tb_ctl1; /* 0x00B0 */ + volatile unsigned long adr_tb_ctl2; /* 0x00B4 */ + volatile unsigned long adr_tb_st0; /* 0x00B8 */ + volatile unsigned long adr_tb_st1; /* 0x00BC */ + volatile unsigned long adr_tb_st2; /* 0x00C0 */ + volatile unsigned long rmon_ctl; /* 0x00C4 */ + volatile unsigned long rmon_st; /* 0x00C8 */ + volatile unsigned long mdio_ctl; /* 0x00CC */ + volatile unsigned long mdio_data; /* 0x00D0 */ + volatile unsigned long tp_flt_act; /* 0x00D4 */ + volatile unsigned long prtcl_flt_act; /* 0x00D8 */ + volatile unsigned long reserved4[9]; /* 0xdc */ + volatile unsigned long vlan_flt0; /* 0x0100 */ + volatile unsigned long vlan_flt1; /* 0x0104 */ + volatile unsigned long vlan_flt2; /* 0x0108 */ + volatile unsigned long vlan_flt3; /* 0x010C */ + volatile unsigned long vlan_flt4; /* 0x0110 */ + volatile unsigned long vlan_flt5; /* 0x0114 */ + volatile unsigned long vlan_flt6; /* 0x0118 */ + volatile unsigned long vlan_flt7; /* 0x011C */ + volatile unsigned long vlan_flt8; /* 0x0120 */ + volatile unsigned long vlan_flt9; /* 0x0124 */ + volatile unsigned long vlan_flt10; /* 0x0128 */ + volatile unsigned long vlan_flt11; /* 0x012C */ + volatile unsigned long vlan_flt12; /* 0x0130 */ + volatile unsigned long vlan_flt13; /* 0x0134 */ + volatile unsigned long vlan_flt14; /* 0x0138 */ + volatile unsigned long vlan_flt15; /* 0x013C */ + volatile unsigned long tp_flt10; /* 0x0140 */ + volatile unsigned long tp_flt32; /* 0x0144 */ + volatile unsigned long tp_flt54; /* 0x0148 */ + volatile unsigned long tp_flt76; /* 0x014C */ + volatile unsigned long dfsrv_map0; /* 0x0150 */ + volatile unsigned long dfsrv_map1; /* 0x0154 */ + volatile unsigned long dfsrv_map2; /* 0x0158 */ + volatile unsigned long dfsrv_map3; /* 0x015C */ + volatile unsigned long tcp_pf0; /* 0x0160 */ + volatile unsigned long tcp_pf1; /* 0x0164 */ + volatile unsigned long tcp_pf2; /* 0x0168 */ + volatile unsigned long tcp_pf3; /* 0x016C */ + volatile unsigned long tcp_pf4; /* 0x0170 */ + volatile unsigned long tcp_pf5; /* 0x0174 */ + volatile unsigned long tcp_pf6; /* 0x0178 */ + volatile unsigned long tcp_pf7; /* 0x017C */ + volatile unsigned long ra_03_00; /* 0x0180 */ + volatile unsigned long ra_07_04; /* 0x0184 */ + volatile unsigned long ra_0b_08; /* 0x0188 */ + volatile unsigned long ra_0f_0c; /* 0x018C */ + volatile unsigned long ra_13_10; /* 0x0190 */ + volatile unsigned long ra_17_14; /* 0x0194 */ + volatile unsigned long ra_1b_18; /* 0x0198 */ + volatile unsigned long ra_1f_1c; /* 0x019C */ + volatile unsigned long ra_23_20; /* 0x01A0 */ + volatile unsigned long ra_27_24; /* 0x01A4 */ + volatile unsigned long ra_2b_28; /* 0x01A8 */ + volatile unsigned long ra_2f_2c; /* 0x01AC */ + volatile unsigned long prtcl_f0; /* 0x01B0 */ + volatile unsigned long prtcl_f1; /* 0x01B4 */ +}; + +/******************************************************************************* + * ES + ******************************************************************************/ +#define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000)) +#define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004)) +#define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008)) +#define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C)) +#define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) +#define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014)) +#define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) +#define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020)) +#define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024)) +#define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028)) +#define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) +#define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) +#define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) +#define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) +#define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) +#define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) +#define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) +#define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) +#define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) +#define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) +#define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) +#define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) +#define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060)) +#define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064)) +#define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068)) +#define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C)) +#define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070)) +#define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074)) +#define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078)) +#define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C)) +#define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080)) +#define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084)) +#define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088)) +#define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C)) +#define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090)) +#define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094)) +#define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098)) +#define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C)) +#define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0)) +#define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4)) +#define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8)) +#define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC)) +#define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0)) +#define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4)) +#define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8)) +#define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC)) +#define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0)) +#define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4)) +#define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8)) +#define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC)) +#define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0)) +#define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4)) +#define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8)) +#define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100)) +#define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104)) +#define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108)) +#define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C)) +#define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110)) +#define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114)) +#define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118)) +#define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C)) +#define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120)) +#define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124)) +#define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128)) +#define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C)) +#define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130)) +#define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134)) +#define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138)) +#define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C)) +#define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140)) +#define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144)) +#define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148)) +#define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C)) +#define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150)) +#define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154)) +#define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158)) +#define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C)) +#define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160)) +#define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164)) +#define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168)) +#define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C)) +#define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170)) +#define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174)) +#define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178)) +#define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C)) +#define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180)) +#define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184)) +#define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188)) +#define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C)) +#define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190)) +#define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194)) +#define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198)) +#define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C)) +#define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0)) +#define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4)) +#define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8)) +#define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC)) +#define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0)) +#define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4)) + +/******************************************************************************* + * Port Status Register + ******************************************************************************/ + +/* Port 1 Flow Control Status (12) */ +#define LTQ_ES_PS_REG_P1FCS (0x1 << 12) +#define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1) +/* Port 1 Duplex Status (11) */ +#define LTQ_ES_PS_REG_P1DS (0x1 << 11) +#define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1) +/* Port 1 Speed High Status (10) */ +#define LTQ_ES_PS_REG_P1SHS (0x1 << 10) +#define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1) +/* Port 1 Speed Status (9) */ +#define LTQ_ES_PS_REG_P1SS (0x1 << 9) +#define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1) +/* Port 1 Link Status (8) */ +#define LTQ_ES_PS_REG_P1LS (0x1 << 8) +#define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1) +/* Port 0 Flow Control Status (4) */ +#define LTQ_ES_PS_REG_P0FCS (0x1 << 4) +#define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1) +/* Port 0 Duplex Status (3) */ +#define LTQ_ES_PS_REG_P0DS (0x1 << 3) +#define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1) +/* Port 0 Speed High Status (2) */ +#define LTQ_ES_PS_REG_P0SHS (0x1 << 2) +#define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1) +/* Port 0 Speed Status (1) */ +#define LTQ_ES_PS_REG_P0SS (0x1 << 1) +#define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1) +/* Port 0 Link Status (0) */ +#define LTQ_ES_PS_REG_P0LS (0x1) +#define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1) + +/******************************************************************************* + * P0 Control Register + ******************************************************************************/ + +/* STP/RSTP port state (31:30) */ +#define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30) +#define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3) +#define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30)) +/* TCP/UDP PRIEN (29) */ +#define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29) +#define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29) +#define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1) +#define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29)) +/* IP over TCP/UDP (28) */ +#define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28) +#define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1) +#define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28)) +/* VLAN Priority Enable (27) */ +#define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27) +#define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27) +#define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1) +#define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27)) +/* Service Priority Enable (26) */ +#define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26) +#define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1) +#define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26)) +/* IP over VLAN PRI (25) */ +#define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25) +#define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25) +#define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1) +#define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25)) +/* Ether Type Priority Enable (24) */ +#define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24) +#define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24) +#define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1) +#define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24)) +/* Force Link Up (18) */ +#define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18) +#define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18) +#define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1) +#define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18)) +/* Force Link Down (17) */ +#define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17) +#define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17) +#define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1) +#define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17)) +/* Ratio Mode for WFQ (16) */ +#define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16) +#define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16) +#define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1) +#define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16)) +/* Aging Disable (15) */ +#define LTQ_ES_P0_CTL_REG_AD (0x1 << 15) +#define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1) +#define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15)) +/* Learning Disable (14) */ +#define LTQ_ES_P0_CTL_REG_LD (0x1 << 14) +#define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1) +#define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14)) +/* Maximum Number of Addresses (12:8) */ +#define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8) +#define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8) +#define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f) +#define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8)) +/* PPPOE Port Only (7) */ +#define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7) +#define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7) +#define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1) +#define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7)) +/* PPPOE Manage (6) */ +#define LTQ_ES_P0_CTL_REG_PM (0x1 << 6) +#define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6) +#define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1) +#define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6)) +/* Port Mirror Option (5:4) */ +#define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4) +#define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3) +#define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4)) +/* 802.1x Port Authorized state (3:2) */ +#define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2) +#define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3) +#define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2)) +/* Drop Scheme for voilation 802.1x (1) */ +#define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1) +#define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1) +#define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1)) +/* ByPass Mode for Output (0) */ +#define LTQ_ES_P0_CTL_REG_BYPASS (0x1) +#define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1) +#define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 VLAN Control Register + ******************************************************************************/ + +/* Default FID (31:30) */ +#define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30) +#define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3) +#define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30)) +/* Tagged Base VLAN Enable (29) */ +#define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29) +#define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29) +#define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1) +#define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29)) +/* Input Force No TAG Enable (28) */ +#define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28) +#define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1) +#define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28)) +/* VID Check with the VID table (27) */ +#define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27) +#define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27) +#define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1) +#define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27)) +/* VLAN Security Disable (26) */ +#define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26) +#define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1) +#define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26)) +/* Admit Only VLAN_Tagged Packet (25) */ +#define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25) +#define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25) +#define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1) +#define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25)) +/* VLAN Member Check Enable (24) */ +#define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24) +#define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24) +#define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1) +#define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24)) +/* Reserved (23:19) */ +#define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19) +#define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f) +/* Default VLAN Port Map (18:16) */ +#define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16) +#define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16) +#define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7) +#define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16)) +/* Port Priority (15:14) */ +#define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14) +#define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3) +#define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14)) +/* Port Priority Enable (13) */ +#define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13) +#define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1) +#define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13)) +/* Portbase VLAN tag member for Port 0 (12) */ +#define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12) +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1) +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12)) +/* PVID (11:0) */ +#define LTQ_ES_P0_VLAN_REG_PVID (0xfff) +#define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0) +#define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff) +#define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0)) + +/******************************************************************************* + * Port 0 Ingress Control Register + ******************************************************************************/ + +/* Reserved (31:13) */ +#define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13) +#define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff) +/* Port 0 Ingress/Egress Timer Tick T selection (12:11) */ +#define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11) +#define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11) +#define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3) +#define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11)) +/* Port 0 Igress Token R (10:0) */ +#define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff) +#define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff) +#define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for Strict Q32 Register + ******************************************************************************/ + +/* Port 0 Egress Token R for Strict Priority Q3 (26:16) */ +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for Strict Priority Q2 (10:0) */ +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for Strict Q10 Register + ******************************************************************************/ + +/* Reserved (31:27) */ +#define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27) +#define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f) +/* Port 0 Egress Token R for Strict Priority Q1 (26:16) */ +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for Strict Priority Q0 (10:0) */ +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for WFQ Q32 Register + ******************************************************************************/ + +/* Reserved (31:27) */ +#define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27) +#define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f) +/* Port 0 Egress Token R for WFQ Q3 (26:16) */ +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for WFQ Q2 (10:0) */ +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for WFQ Q10 Register + ******************************************************************************/ + +/* Reserved (31:27) */ +#define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27) +#define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f) +/* Port 0 Egress Token R for WFQ Q1 (26:16) */ +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for WFQ Q0 (10:0) */ +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Interrupt Enable Register + ******************************************************************************/ + +/* Reserved (31:8) */ +#define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8) +#define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff) +/* Data Buffer is Full Interrupt Enable (7) */ +#define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7) +#define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7) +#define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1) +#define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7)) +/* Data Buffer is nearly Full Interrupt Enable (6) */ +#define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6) +#define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6) +#define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1) +#define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6)) +/* Learning Table Full Interrupt Enable (5) */ +#define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5) +#define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5) +#define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1) +#define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5)) +/* Leaning Table Access Done Interrupt Enable (4) */ +#define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4) +#define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4) +#define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1) +#define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4)) +/* Port Security Violation Interrupt Enable (3:1) */ +#define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1) +#define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1) +#define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7) +#define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1)) +/* Port Status Change Interrupt Enable (0) */ +#define LTQ_ES_INT_ENA_REG_PSCIE (0x1) +#define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1) +#define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Interrupt Status Register + ******************************************************************************/ + +/* Reserved (31:8) */ +#define LTQ_ES_INT_ST_REG_RES (0xffffff << 8) +#define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff) +/* Data Buffer is Full (7) */ +#define LTQ_ES_INT_ST_REG_DBF (0x1 << 7) +#define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1) +/* Data Buffer is nearly Full (6) */ +#define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6) +#define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1) +/* Learning Table Full (5) */ +#define LTQ_ES_INT_ST_REG_LTF (0x1 << 5) +#define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1) +/* Leaning Table Access Done (4) */ +#define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4) +#define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1) +/* Port Security Violation (3:1) */ +#define LTQ_ES_INT_ST_REG_PSV (0x7 << 1) +#define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7) +/* Port Status Change (0) */ +#define LTQ_ES_INT_ST_REG_PSC (0x1) +#define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1) + +/******************************************************************************* + * Switch Global Control Register 0 + ******************************************************************************/ + +/* Switch Enable (31) */ +#define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31) +#define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31) +#define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31)) +/* CRC Check Disable (30) */ +#define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30) +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30) +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30)) +/* Replace VID0 (28) */ +#define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28) +#define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28)) +/* Replace VID1 (27) */ +#define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27) +#define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27) +#define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27)) +/* Replace VIDFFF (26) */ +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26) +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26)) +/* Priority Change Rule (25) */ +#define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25) +#define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25) +#define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25)) +/* Priority Change Enable (24) */ +#define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24) +#define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24) +#define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24)) +/* Transmit Short IPG Enable (23) */ +#define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23) +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23) +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23)) +/* PHY Base Address (22) */ +#define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22) +#define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22) +#define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22)) +/* Drop Packet When Excessive Collision Happen (21) */ +#define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21) +#define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21) +#define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21)) +/* Aging Timer Select (20:18) */ +#define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18) +#define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18) +#define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7) +#define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18)) +/* Mirror CRC Also (17) */ +#define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17) +#define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17) +#define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17)) +/* Mirror RXER Also (16) */ +#define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16) +#define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16) +#define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16)) +/* Mirror PAUSE Also (15) */ +#define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15) +#define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15)) +/* Mirror Long Also (14) */ +#define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14) +#define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14)) +/* Mirror Short Also (13) */ +#define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13) +#define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13)) +/* Sniffer port number (12:11) */ +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11) +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11) +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11)) +/* Max Packet Length (MAXPKTLEN) (9:8) */ +#define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8) +#define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8)) +/* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6) +#define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6)) +/* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4) +#define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4)) +/* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2) +#define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2)) +/* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Switch Global Control Register 1 + ******************************************************************************/ + +/* BIST Done (27) */ +#define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27) +#define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1) +/* Enable drop scheme of TX and RX (26) */ +#define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26) +#define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26)) +/* Congestion threshold for TX queue (25:24) */ +#define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24) +#define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3) +#define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24)) +/* Input Jam Threshold (23:21) */ +#define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21) +#define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21) +#define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21)) +/* Do not Identify VLAN after SNAP (20) */ +#define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20) +#define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20) +#define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20)) +/* Do not Identify IPV6 in PPPOE (19) */ +#define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19) +#define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19) +#define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19)) +/* Do not Identify IP in PPPOE after SNAP (18) */ +#define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18) +#define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18) +#define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18)) +/* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */ +#define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17) +#define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17) +#define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17)) +/* Do not Identify IP in PPPOE (16) */ +#define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16) +#define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16) +#define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16)) +/* Do not Identify SNAP (15) */ +#define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15) +#define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15)) +/* Unicast Portmap (14:12) */ +#define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12) +#define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12) +#define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12)) +/* Broadcast Portmap (10:8) */ +#define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8) +#define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8) +#define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8)) +/* Multicast Portmap (6:4) */ +#define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4) +#define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4) +#define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4)) +/* Reserve Portmap (2:0) */ +#define LTQ_ES_SW_GCTL1_REG_RP (0x7) +#define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0) +#define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0)) + +/******************************************************************************* + * ARP/RARP Register + ******************************************************************************/ + +/* MAC Control Action (15:14) */ +#define LTQ_ES_ARP_REG_MACA (0x3 << 14) +#define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3) +#define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14)) +/* Unicast packet Treated as Cross_VLAN packet (13) */ +#define LTQ_ES_ARP_REG_UPT (0x1 << 13) +#define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1) +#define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13)) +/* RARP Packet Treated as Cross_VLAN Packet (12) */ +#define LTQ_ES_ARP_REG_RPT (0x1 << 12) +#define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1) +#define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12)) +/* RARP/ARP Packet Action (11:10) */ +#define LTQ_ES_ARP_REG_RAPA (0x3 << 10) +#define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3) +#define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10)) +/* RARP/ARP Packet Priority Enable (9) */ +#define LTQ_ES_ARP_REG_RAPPE (0x1 << 9) +#define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9) +#define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1) +#define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9)) +/* RARP/ARP Packet Priority (8:7) */ +#define LTQ_ES_ARP_REG_RAPP (0x3 << 7) +#define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7) +#define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3) +#define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7)) +/* RARP/ARP Packet Output Tag Handle (6:5) */ +#define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5) +#define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5) +#define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3) +#define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5)) +/* ARP Packet Treated as Cross _ VLAN Packet (4) */ +#define LTQ_ES_ARP_REG_APT (0x1 << 4) +#define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4) +#define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1) +#define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4)) +/* RARP/ARP Packet Treated as Management Packet (3) */ +#define LTQ_ES_ARP_REG_RAPTM (0x1 << 3) +#define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3) +#define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1) +#define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3)) +/* RARP/ARP Packet Treated as Span Packet (2) */ +#define LTQ_ES_ARP_REG_TAPTS (0x1 << 2) +#define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2) +#define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1) +#define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2)) +/* Trap ARP Packet (1) */ +#define LTQ_ES_ARP_REG_TAP (0x1 << 1) +#define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1) +#define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1)) +/* Trap RARP Packet (0) */ +#define LTQ_ES_ARP_REG_TRP (0x1) +#define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1) +#define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Storm control Register + ******************************************************************************/ + +/* Reserved (31:29) */ +#define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29) +#define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7) +/* 10M Threshold (28:16) */ +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16) +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16) +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff) +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16)) +/* Storm Enable for Broadcast Packets (15) */ +#define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15) +#define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1) +#define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15)) +/* Storm Enable for Multicast Packets (14) */ +#define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14) +#define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1) +#define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14)) +/* Storm Enable for Un-learned Unicast Packets (13) */ +#define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13) +#define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1) +#define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13)) +/* 100M Threshold (12:0) */ +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff) +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0) +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff) +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0)) + +/******************************************************************************* + * RGMII/GMII Port Control Register + ******************************************************************************/ + +/* Management Clock Select (31:24) */ +#define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24) +#define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24) +#define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff) +#define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24)) +/* Interface Selection (19:18) */ +#define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18) +#define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3) +/* Port 1 RGMII Rx Clock Delay (17:16) */ +#define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16) +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16)) +/* Port 1 RGMII Tx Clock Delay (15:14) */ +#define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14) +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14)) +/* Port 1 Speed (13:12) */ +#define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12) +#define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12)) +/* Port 1 Duplex mode (11) */ +#define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11) +#define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11) +#define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11)) +/* Port 1 Flow Control Enable (10) */ +#define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10) +#define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10) +#define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10)) +/* Port 0 RGMII Rx Clock Delay (7:6) */ +#define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6) +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6)) +/* Port 0 RGMII Tx Clock Delay (5:4) */ +#define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4) +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4)) +/* Port 0 Speed (3:2) */ +#define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2) +#define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2)) +/* Port 0 Duplex mode (1) */ +#define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1) +#define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1)) +/* Port 0 Flow Control Enable (0) */ +#define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1) +#define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * 802.1p Priority Map Register + ******************************************************************************/ + +/* Priority Queue 7 (15:14) */ +#define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14) +#define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14)) +/* Priority Queue 6 (13:12) */ +#define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12) +#define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12)) +/* Priority Queue 5 (11:10) */ +#define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10) +#define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10)) +/* Priority Queue 4 (9:8) */ +#define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8) +#define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8)) +/* Priority Queue 3 (7:6) */ +#define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6) +#define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6)) +/* Priority Queue 2 (5:4) */ +#define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4) +#define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4)) +/* Priority Queue 1 (3:2) */ +#define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2) +#define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2)) +/* Priority Queue 0 (1:0) */ +#define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Global Bucket Size Base counter + ******************************************************************************/ + +/* Reserved (31:18) */ +#define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18) +#define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff) +/* Base[17:0] (17:0) */ +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff) +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0) +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff) +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0)) + +/******************************************************************************* + * Global Bucket Size Extend Base Counter + ******************************************************************************/ + +/* Reserved (31:18) */ +#define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18) +#define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff) +/* Extend Base[17:0] (17:0) */ +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff) +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0) +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff) +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0)) + +/******************************************************************************* + * Buffer Threshold Register + ******************************************************************************/ + +/* Port Unfull Offset 3 (31:30) */ +#define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30) +#define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30)) +/* Port Unfull Offset 2 (29:28) */ +#define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28) +#define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28)) +/* Port Unfull Offset 1 (27:26) */ +#define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26) +#define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26)) +/* Port Unfull Offset 0 (25:24) */ +#define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24) +#define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24)) +/* Port Full Offset 3 (23:22) */ +#define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22) +#define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22)) +/* Port Full Offset 2 (21:20) */ +#define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20) +#define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20)) +/* Port Full Offset 1 (19:18) */ +#define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18) +#define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18)) +/* Port Full Offset 0 (17:16) */ +#define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16) +#define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16)) +/* Reserved (15:14) */ +#define LTQ_ES_BF_TH_REG_RES (0x3 << 14) +#define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3) +/* Total Low Add (13) */ +#define LTQ_ES_BF_TH_REG_TLA (0x1 << 13) +#define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1) +#define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13)) +/* Total High Add (12) */ +#define LTQ_ES_BF_TH_REG_THA (0x1 << 12) +#define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1) +#define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12)) +/* Total Low Offset (11:10) */ +#define LTQ_ES_BF_TH_REG_TLO (0x3 << 10) +#define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3) +#define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10)) +/* Total High Offset (9:8) */ +#define LTQ_ES_BF_TH_REG_THO (0x3 << 8) +#define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3) +#define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8)) +/* Port Unfull Add (7:4) */ +#define LTQ_ES_BF_TH_REG_PUA (0xf << 4) +#define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4) +#define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf) +#define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4)) +/* Port Full Add (3:0) */ +#define LTQ_ES_BF_TH_REG_PFA (0xf) +#define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0) +#define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf) +#define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0)) + +/******************************************************************************* + * PMAC Header Control Register + ******************************************************************************/ + +/* Reserved (31:22) */ +#define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22) +#define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff) +/* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */ +#define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21) +#define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21) +#define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21)) +/* Remove CRC from Packets Going from PMAC to DMA (20) */ +#define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20) +#define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20) +#define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20)) +/* Status Header for Packets from PMAC to DMA (19) */ +#define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19) +#define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19) +#define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19)) +/* Add CRC for packets from DMA to PMAC (18) */ +#define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18) +#define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18) +#define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18)) +/* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */ +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2) +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2) +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff) +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2)) +/* Add TAG to Packets from DMA to PMAC (1) */ +#define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1) +#define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1)) +/* ADD Header to Packets from DMA to PMAC (0) */ +#define LTQ_ES_PMAC_HD_CTL_ADD (0x1) +#define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PMAC Source Address Register 1 + ******************************************************************************/ + +/* Source Address to be inserted as a part of the Ethernet header. (15:0) */ +#define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff) +#define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff) +#define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * PMAC Source Address Register 2 + ******************************************************************************/ + +/* Source Address (31:0) */ +#define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL) +#define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL) +#define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * PMAC Destination Address Register 1 + ******************************************************************************/ + +/* Destination Address (15:0) */ +#define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff) +#define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff) +#define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * PMAC Destination Address Register 2 + ******************************************************************************/ + +/* Destination Address to be inserted as a part of the Ethernet header. (31:0) */ +#define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL) +#define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL) +#define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * PMAC VLAN Register + ******************************************************************************/ + +/* Priority to be inserted as a part of VLAN tag (15:13) */ +#define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13) +#define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13) +#define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7) +#define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13)) +/* CFI bit to be inserted as a part of VLAN tag (12) */ +#define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12) +#define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1) +#define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12)) +/* VLAN ID to be inserted as a part of VLAN tag (11:0) */ +#define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff) +#define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0) +#define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff) +#define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0)) + +/******************************************************************************* + * PMAC TX IPG Counter Register + ******************************************************************************/ + +/* IPG Counter (7:0) */ +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff) +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff) +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * PMAC RX IPG Counter Register + ******************************************************************************/ + +/* IPG Counter (7:0) */ +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff) +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff) +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * Address Table Control 0 Register + ******************************************************************************/ + +/* Address [31:0] (31:0) */ +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL) +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL) +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * Address Table Control 1 Register + ******************************************************************************/ + +/* Port Map (22:20) */ +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20) +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20) +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7) +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20)) +/* FID group (17:16) */ +#define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16) +#define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3) +#define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16)) +/* Address [47:32] (15:0) */ +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff) +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff) +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * Address Table Control 2 Register + ******************************************************************************/ + +/* Command (22:20) */ +#define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20) +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20) +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7) +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20)) +/* Access Control (19:16) */ +#define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16) +#define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16) +#define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf) +#define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16)) +/* Info Type: Static address (12) */ +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12) +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1) +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12)) +/* Info_Ctrl/Age Timer (10:0) */ +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff) +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff) +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Address Table Status 0 Register + ******************************************************************************/ + +/* Address [31:0] (31:0) */ +#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL) +#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL) + +/******************************************************************************* + * Address Table Status 1 Register + ******************************************************************************/ + +/* Port Map (22:20) */ +#define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20) +#define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7) +/* FID group (17:16) */ +#define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16) +#define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3) +/* Address [47:32] (15:0) */ +#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff) +#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff) + +/******************************************************************************* + * Address Table Status 2 Register + ******************************************************************************/ + +/* Busy (31) */ +#define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31) +#define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1) +/* Result (30:28) */ +#define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28) +#define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7) +/* Command (22:20) */ +#define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20) +#define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7) +/* Access Control (19:16) */ +#define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16) +#define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf) +/* Bad Status (14) */ +#define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14) +#define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1) +/* Occupy (13) */ +#define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13) +#define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1) +/* Info Type: Static address (12) */ +#define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12) +#define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1) +/* Info_Ctrl/Age Timer Status (10:0) */ +#define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff) +#define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff) + +/******************************************************************************* + * RMON Counter Control Register + ******************************************************************************/ + +/* Reserved (31:12) */ +#define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12) +#define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff) +/* Busy/Access Start (11) */ +#define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11) +#define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11) +#define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1) +#define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11)) +/* Command for access counter (10:9) */ +#define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9) +#define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9) +#define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3) +#define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9)) +/* Port (8:6) */ +#define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6) +#define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6) +#define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7) +#define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6)) +/* Counter Offset (5:0) */ +#define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f) +#define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0) +#define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f) +#define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0)) + +/******************************************************************************* + * RMON Counter Status Register + ******************************************************************************/ + +/* Counter [31:0] or Counter[63:32] for byte count (31:0) */ +#define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL) +#define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL) + +/******************************************************************************* + * MDIO Indirect Access Control + ******************************************************************************/ + +/* The Write Data to the MDIO register (31:16) */ +#define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16) +#define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16) +#define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff) +#define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16)) +/* Busy state (15) */ +#define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15) +#define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1) +#define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15)) +/* Reserved (14:12) */ +#define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12) +#define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7) +/* Operation Code (11:10) */ +#define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10) +#define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3) +#define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10)) +/* PHY Address (9:5) */ +#define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5) +#define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5) +#define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f) +#define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5)) +/* Register Address (4:0) */ +#define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f) +#define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0) +#define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f) +#define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0)) + +/******************************************************************************* + * MDIO Indirect Read Data + ******************************************************************************/ + +/* Reserved (31:16) */ +#define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16) +#define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff) +/* The Read Data (15:0) */ +#define LTQ_ES_MDIO_DATA_REG_RD (0xffff) +#define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff) + +/******************************************************************************* + * Type Filter Action + ******************************************************************************/ + +/* Destination Queue for Type Filter 7 (31:30) */ +#define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30) +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30)) +/* Destination Queue for Type Filter 6 (29:28) */ +#define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28) +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28)) +/* Destination Queue for Type Filter 5 (27:26) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26) +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26)) +/* Destination Queue for Type Filter 4 (25:24) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24) +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24)) +/* Destination Queue for Type Filter 3 (23:22) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22) +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22)) +/* Destination Queue for Type Filter 2 (21:20) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20) +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20)) +/* Destination Queue for Type Filter 1 (19:18) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18) +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18)) +/* Destination Queue for Type Filter 0 (17:16) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16) +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16)) +/* Action for Type Filter 7 (15:14) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14) +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14)) +/* Action for Type Filter 6 (13:12) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12) +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12)) +/* Action for Type Filter 5 (11:10) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10) +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10)) +/* Action for Type Filter 4 (9:8) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8) +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8)) +/* Action for Type Filter 3 (7:6) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6) +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6)) +/* Action for Type Filter 2 (5:4) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4) +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4)) +/* Action for Type Filter 1 (3:2) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2) +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2)) +/* Action for Type Filter 0 (1:0) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Protocol Filter Action + ******************************************************************************/ + +/* Action for Protocol Filter 7 (15:14) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14)) +/* Action for Protocol Filter 6 (13:12) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12)) +/* Action for Protocol Filter 5 (11:10) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10)) +/* Action for Protocol Filter 4 (9:8) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8)) +/* Action for Protocol Filter 3 (7:6) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6)) +/* Action for Protocol Filter 2 (5:4) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4)) +/* Action for Protocol Filter 1 (3:2) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2)) +/* Action for Protocol Filter 0 (1:0) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * VLAN Filter 0 + ******************************************************************************/ + +/* Res (31:24) */ +#define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24) +#define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24) +#define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff) +#define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24)) +/* FID (23:22) */ +#define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22) +#define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3) +#define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22)) +/* Tagged Member (21:19) */ +#define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19) +#define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19) +#define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7) +#define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19)) +/* Member (18:16) */ +#define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16) +#define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16) +#define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7) +#define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16)) +/* VLAN_Valid (15) */ +#define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15) +#define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1) +#define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15)) +/* VLAN PRI (14:12) */ +#define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12) +#define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12) +#define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7) +#define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12)) +/* VID (11:0) */ +#define LTQ_ES_VLAN_FLT0_REG_VID (0xfff) +#define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0) +#define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff) +#define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0)) + +/******************************************************************************* + * Type Filter 10 + ******************************************************************************/ + +/* Value 1 Compared with Ether-Type (31:16) */ +#define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16) +#define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16) +#define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff) +#define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16)) +/* Value 0 Compared with Ether-Type (15:0) */ +#define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff) +#define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff) +#define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * DiffServMapping 0 + ******************************************************************************/ + +/* Priority Queue F (31:30) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30) +#define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30)) +/* Priority Queue E (29:28) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28) +#define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28)) +/* Priority Queue D (27:26) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26) +#define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26)) +/* Priority Queue C (25:24) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24) +#define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24)) +/* Priority Queue B (23:22) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22) +#define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22)) +/* Priority Queue A (21:20) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20) +#define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20)) +/* Priority Queue 9 (19:18) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18)) +/* Priority Queue 8 (17:16) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16)) +/* Priority Queue 7 (15:14) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14)) +/* Priority Queue 6 (13:12) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12)) +/* Priority Queue 5 (11:10) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10)) +/* Priority Queue 4 (9:8) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8)) +/* Priority Queue 3 (7:6) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6)) +/* Priority Queue 2 (5:4) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4)) +/* Priority Queue 1 (3:2) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2)) +/* Priority Queue 0 (1:0) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * DiffServMapping 1 + ******************************************************************************/ + +/* Priority Queue 1F (31:30) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30)) +/* Priority Queue 1E (29:28) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28)) +/* Priority Queue 1D (27:26) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26)) +/* Priority Queue 1C (25:24) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24)) +/* Priority Queue 1B (23:22) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22)) +/* Priority Queue 1A (21:20) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20)) +/* Priority Queue 19 (19:18) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18)) +/* Priority Queue 18 (17:16) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16)) +/* Priority Queue 17 (15:14) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14)) +/* Priority Queue 16 (13:12) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12)) +/* Priority Queue 15 (11:10) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10)) +/* Priority Queue 14 (9:8) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8)) +/* Priority Queue 13 (7:6) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6)) +/* Priority Queue 12 (5:4) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4)) +/* Priority Queue 11 (3:2) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2)) +/* Priority Queue 10 (1:0) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * DiffServMapping 2 + ******************************************************************************/ + +/* Priority Queue 2F (31:30) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30)) +/* Priority Queue 2E (29:28) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28)) +/* Priority Queue 2D (27:26) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26)) +/* Priority Queue 2C (25:24) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24)) +/* Priority Queue 2B (23:22) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22)) +/* Priority Queue 2A (21:20) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20)) +/* Priority Queue 29 (19:18) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18)) +/* Priority Queue 28 (17:16) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16)) +/* Priority Queue 27 (15:14) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14)) +/* Priority Queue 26 (13:12) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12)) +/* Priority Queue 25 (11:10) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10)) +/* Priority Queue 24 (9:8) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8)) +/* Priority Queue 23 (7:6) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6)) +/* Priority Queue 22 (5:4) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4)) +/* Priority Queue 21 (3:2) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2)) +/* Priority Queue 20 (1:0) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * DiffServMapping 3 + ******************************************************************************/ + +/* Priority Queue 3F (31:30) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30)) +/* Priority Queue 3E (29:28) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28)) +/* Priority Queue 3D (27:26) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26)) +/* Priority Queue 3C (25:24) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24)) +/* Priority Queue 3B (23:22) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22)) +/* Priority Queue 3A (21:20) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20)) +/* Priority Queue 39 (19:18) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18)) +/* Priority Queue 38 (17:16) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16)) +/* Priority Queue 37 (15:14) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14)) +/* Priority Queue 36 (13:12) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12)) +/* Priority Queue 35 (11:10) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10)) +/* Priority Queue 34 (9:8) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8)) +/* Priority Queue 33 (7:6) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6)) +/* Priority Queue 32 (5:4) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4)) +/* Priority Queue 31 (3:2) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2)) +/* Priority Queue 30 (1:0) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * TCP/UDP Port Filter 0 + ******************************************************************************/ + +/* Reserved (31:30) */ +#define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30) +#define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3) +/* Action for TCP/UDP Port Filter 0 (29:28) */ +#define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28) +#define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3) +#define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28)) +/* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */ +#define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26) +#define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3) +#define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26)) +/* Compare TCP/UDP Source Port or Destination Port (25:24) */ +#define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24) +#define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3) +#define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24)) +/* Port Range in TCP/UDP (23:16) */ +#define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16) +#define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16) +#define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff) +#define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16)) +/* Base Port number 0 (15:0) */ +#define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff) +#define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff) +#define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * Reserved DA(0180C2000003~0180C2000000) control register + ******************************************************************************/ + +/* Valid bit for 0180C2000003 (31) */ +#define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31) +#define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31) +#define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31)) +/* Span bit for 0180C2000003 (30) */ +#define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30) +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30) +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30)) +/* Management bit for 0180C2000003 (29) */ +#define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29) +#define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29) +#define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29)) +/* Cross_VLAN bit for 0180C2000003 (28) */ +#define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28) +#define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28)) +/* TXTAG bit for 0180C2000003 (27:26) */ +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26) +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26)) +/* Action bit for 0180C2000003 (25:24) */ +#define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24) +#define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24)) +/* Valid bit for 0180C2000002 (23) */ +#define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23) +#define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23) +#define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23)) +/* Span bit for 0180C2000002 (22) */ +#define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22) +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22) +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22)) +/* Management bit for 0180C2000002 (21) */ +#define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21) +#define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21) +#define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21)) +/* Cross_VLAN bit for 0180C2000002 (20) */ +#define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20) +#define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20) +#define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20)) +/* TXTAG bit for 0180C2000002 (19:18) */ +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18) +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18)) +/* Action bit for 0180C2000002 (17:16) */ +#define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16) +#define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16)) +/* Valid bit for 0180C2000001 (15) */ +#define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15) +#define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15)) +/* Span bit for 0180C2000001 (14) */ +#define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14) +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14)) +/* Management bit for 0180C2000001 (13) */ +#define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13) +#define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13)) +/* Cross_VLAN bit for 0180C2000001 (12) */ +#define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12) +#define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12)) +/* TXTAG bit for 0180C2000001 (11:10) */ +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10) +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10)) +/* Action bit for 0180C2000001 (9:8) */ +#define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8) +#define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8)) +/* Valid bit for 0180C2000000 (7) */ +#define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7) +#define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7) +#define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7)) +/* Span bit for 0180C2000000 (6) */ +#define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6) +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6) +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6)) +/* Management bit for 0180C2000000 (5) */ +#define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5) +#define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5) +#define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5)) +/* Cross_VLAN bit for 0180C2000000 (4) */ +#define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4) +#define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4) +#define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4)) +/* TXTAG bit for 0180C2000000 (3:2) */ +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2) +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2)) +/* Action bit for 0180C2000000 (1:0) */ +#define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3) +#define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Protocol Filter 0 + ******************************************************************************/ + +/* Value Compared with Protocol in IP Header (31:24) */ +#define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24) +#define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24) +#define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24)) +/* Value Compared with Protocol in IP Header (23:16) */ +#define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16) +#define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16) +#define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16)) +/* Value Compared with Protocol in IP Header (15:8) */ +#define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8) +#define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8) +#define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8)) +/* Value Compared with Protocol in IP Header (7:0) */ +#define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0) +#define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0)) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h new file mode 100644 index 000000000..06dc17354 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h @@ -0,0 +1,36 @@ +/* + * arch/mips/include/asm/mach-lantiq/svip/irq.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2010 Lantiq + * + */ + +#ifndef __IRQ_H +#define __IRQ_H + +#include <svip_irq.h> + +#define NR_IRQS 264 + +#include_next <irq.h> + +/* Functions for EXINT handling */ +extern int ifx_enable_external_int(u32 exint, u32 mode); +extern int ifx_disable_external_int(u32 exint); +extern int ifx_external_int_level(u32 exint); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h new file mode 100644 index 000000000..697d672f3 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h @@ -0,0 +1,71 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + */ + +#ifndef _LTQ_SVIP_H__ +#define _LTQ_SVIP_H__ + +#ifdef CONFIG_SOC_SVIP + +#include <lantiq.h> + +/* Chip IDs */ +#define SOC_ID_SVIP 0x169 + +/* SoC Types */ +#define SOC_TYPE_SVIP 0x01 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x14100100 +#define LTQ_ASC1_BASE_ADDR 0x14100200 +#define LTQ_ASC_SIZE 0x100 +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) + +#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2) +#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3) + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x14106000 +#define LTQ_ICU_BASE_ADDR1 0x14106028 +#define LTQ_ICU_BASE_ADDR2 0x1E016000 +#define LTQ_ICU_BASE_ADDR3 0x1E016028 +#define LTQ_ICU_BASE_ADDR4 0x14106050 +#define LTQ_ICU_BASE_ADDR5 0x14106078 +#define LTQ_ICU_SIZE 0x100 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 +#define LTQ_WDT_SIZE 0x10 + +/* Status */ +#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500) +#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C)) + +#define LTQ_EIU_BASE_ADDR 0 + +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) + +extern __iomem void *ltq_ebu_membase; + +extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, + bool altsel0, bool altsel1); +extern int ltq_port_get_dir(unsigned int port, unsigned int pin); +extern int ltq_port_get_puden(unsigned int port, unsigned int pin); +extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin); +extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin); + +#define ltq_is_ar9() 0 +#define ltq_is_vr9() 0 +#define ltq_is_falcon() 0 + +#define BS_FLASH 0 +#define LTQ_RST_CAUSE_WDTRST 0x2 + +#endif /* CONFIG_SOC_SVIP */ +#endif /* _LTQ_SVIP_H__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h new file mode 100644 index 000000000..79966b7be --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h @@ -0,0 +1,242 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __MPS_REG_H +#define __MPS_REG_H + +#define mbs_r32(reg) ltq_r32(&mbs->reg) +#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg) +#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg) + +/** MBS register structure */ +struct svip_reg_mbs { + unsigned long reserved0[4]; + unsigned long mbsr0; /* 0x0010 */ + unsigned long mbsr1; /* 0x0014 */ + unsigned long mbsr2; /* 0x0018 */ + unsigned long mbsr3; /* 0x001c */ + unsigned long mbsr4; /* 0x0020 */ + unsigned long mbsr5; /* 0x0024 */ + unsigned long mbsr6; /* 0x0028 */ + unsigned long mbsr7; /* 0x002c */ + unsigned long mbsr8; /* 0x0030 */ + unsigned long mbsr9; /* 0x0034 */ + unsigned long mbsr10; /* 0x0038 */ + unsigned long mbsr11; /* 0x003c */ + unsigned long mbsr12; /* 0x0040 */ + unsigned long mbsr13; /* 0x0044 */ + unsigned long mbsr14; /* 0x0048 */ + unsigned long mbsr15; /* 0x004c */ + unsigned long mbsr16; /* 0x0050 */ + unsigned long mbsr17; /* 0x0054 */ + unsigned long mbsr18; /* 0x0058 */ + unsigned long mbsr19; /* 0x005c */ + unsigned long mbsr20; /* 0x0060 */ + unsigned long mbsr21; /* 0x0064 */ + unsigned long mbsr22; /* 0x0068 */ + unsigned long mbsr23; /* 0x006c */ + unsigned long mbsr24; /* 0x0070 */ + unsigned long mbsr25; /* 0x0074 */ + unsigned long mbsr26; /* 0x0078 */ + unsigned long mbsr27; /* 0x007c */ + unsigned long mbsr28; /* 0x0080 */ +}; + +/** MPS register structure */ +struct svip_reg_mps { + volatile unsigned long mps_swirn0set; /* 0x0000 */ + volatile unsigned long mps_swirn0en; /* 0x0004 */ + volatile unsigned long mps_swirn0cr; /* 0x0008 */ + volatile unsigned long mps_swirn0icr; /* 0x000C */ + volatile unsigned long mps_swirn1set; /* 0x0010 */ + volatile unsigned long mps_swirn1en; /* 0x0014 */ + volatile unsigned long mps_swirn1cr; /* 0x0018 */ + volatile unsigned long mps_swirn1icr; /* 0x001C */ + volatile unsigned long mps_swirn2set; /* 0x0020 */ + volatile unsigned long mps_swirn2en; /* 0x0024 */ + volatile unsigned long mps_swirn2cr; /* 0x0028 */ + volatile unsigned long mps_swirn2icr; /* 0x002C */ + volatile unsigned long mps_swirn3set; /* 0x0030 */ + volatile unsigned long mps_swirn3en; /* 0x0034 */ + volatile unsigned long mps_swirn3cr; /* 0x0038 */ + volatile unsigned long mps_swirn3icr; /* 0x003C */ + volatile unsigned long mps_swirn4set; /* 0x0040 */ + volatile unsigned long mps_swirn4en; /* 0x0044 */ + volatile unsigned long mps_swirn4cr; /* 0x0048 */ + volatile unsigned long mps_swirn4icr; /* 0x004C */ + volatile unsigned long mps_swirn5set; /* 0x0050 */ + volatile unsigned long mps_swirn5en; /* 0x0054 */ + volatile unsigned long mps_swirn5cr; /* 0x0058 */ + volatile unsigned long mps_swirn5icr; /* 0x005C */ + volatile unsigned long mps_swirn6set; /* 0x0060 */ + volatile unsigned long mps_swirn6en; /* 0x0064 */ + volatile unsigned long mps_swirn6cr; /* 0x0068 */ + volatile unsigned long mps_swirn6icr; /* 0x006C */ + volatile unsigned long mps_swirn7set; /* 0x0070 */ + volatile unsigned long mps_swirn7en; /* 0x0074 */ + volatile unsigned long mps_swirn7cr; /* 0x0078 */ + volatile unsigned long mps_swirn7icr; /* 0x007C */ + volatile unsigned long mps_swirn8set; /* 0x0080 */ + volatile unsigned long mps_swirn8en; /* 0x0084 */ + volatile unsigned long mps_swirn8cr; /* 0x0088 */ + volatile unsigned long mps_swirn8icr; /* 0x008C */ +}; + +/* Software Interrupt */ +#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000)) +#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004)) +#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008)) +#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C)) +#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010)) +#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014)) +#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018)) +#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C)) +#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020)) +#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024)) +#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028)) +#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C)) +#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030)) +#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034)) +#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038)) +#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C)) +#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040)) +#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044)) +#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048)) +#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C)) +#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050)) +#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054)) +#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058)) +#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C)) +#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060)) +#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064)) +#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068)) +#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C)) +#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070)) +#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074)) +#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078)) +#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C)) +#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080)) +#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084)) +#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C)) +#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088)) + +/******************************************************************************* + * MPS_SWIRNSET Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5) +#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4) +#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3) +#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2) +#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1) +#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNSET_IR0 (0x1) +#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0) +#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0) + +/******************************************************************************* + * MPS_SWIRNEN Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5) +#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1) +#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5)) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4) +#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1) +#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4)) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3) +#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1) +#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3)) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2) +#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1) +#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2)) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1) +#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1) +#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1)) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNEN_IR0 (0x1) +#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0) +#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1) +#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * MPS_SWIRNICR Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNICR_IR0 (0x1) +#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1) + +/******************************************************************************* + * MPS_SWIRNCR Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNCR_IR0 (0x1) +#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h new file mode 100644 index 000000000..57d04917f --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h @@ -0,0 +1,3262 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __PORT_REG_H +#define __PORT_REG_H + +#define port_r32(reg) __raw_readl(®) +#define port_w32(val, reg) __raw_writel(val, ®) + +/** PORT register structure */ +struct svip_reg_port { + volatile u32 out; /* 0x0000 */ + volatile u32 in; /* 0x0004 */ + volatile u32 dir; /* 0x0008 */ + volatile u32 altsel0; /* 0x000C */ + volatile u32 altsel1; /* 0x0010 */ + volatile u32 puen; /* 0x0014 */ + volatile u32 exintcr0; /* 0x0018 */ + volatile u32 exintcr1; /* 0x001C */ + volatile u32 irncr; /* 0x0020 */ + volatile u32 irnicr; /* 0x0024 */ + volatile u32 irnen; /* 0x0028 */ + volatile u32 irncfg; /* 0x002C */ + volatile u32 irnenset; /* 0x0030 */ + volatile u32 irnenclr; /* 0x0034 */ +}; + +/******************************************************************************* + * Port 0 Data Output Register + ******************************************************************************/ + +/* Port 0 Pin # Output Value (19) */ +#define PORT_P0_OUT_P19 (0x1 << 19) +#define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1) +#define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 0 Pin # Output Value (18) */ +#define PORT_P0_OUT_P18 (0x1 << 18) +#define PORT_P0_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_OUT_P18_GET(val) ((((val) & PORT_P0_OUT_P18) >> 18) & 0x1) +#define PORT_P0_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 0 Pin # Output Value (17) */ +#define PORT_P0_OUT_P17 (0x1 << 17) +#define PORT_P0_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_OUT_P17_GET(val) ((((val) & PORT_P0_OUT_P17) >> 17) & 0x1) +#define PORT_P0_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 0 Pin # Output Value (16) */ +#define PORT_P0_OUT_P16 (0x1 << 16) +#define PORT_P0_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_OUT_P16_GET(val) ((((val) & PORT_P0_OUT_P16) >> 16) & 0x1) +#define PORT_P0_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 0 Pin # Output Value (15) */ +#define PORT_P0_OUT_P15 (0x1 << 15) +#define PORT_P0_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_OUT_P15_GET(val) ((((val) & PORT_P0_OUT_P15) >> 15) & 0x1) +#define PORT_P0_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 0 Pin # Output Value (14) */ +#define PORT_P0_OUT_P14 (0x1 << 14) +#define PORT_P0_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_OUT_P14_GET(val) ((((val) & PORT_P0_OUT_P14) >> 14) & 0x1) +#define PORT_P0_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 0 Pin # Output Value (13) */ +#define PORT_P0_OUT_P13 (0x1 << 13) +#define PORT_P0_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_OUT_P13_GET(val) ((((val) & PORT_P0_OUT_P13) >> 13) & 0x1) +#define PORT_P0_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 0 Pin # Output Value (12) */ +#define PORT_P0_OUT_P12 (0x1 << 12) +#define PORT_P0_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_OUT_P12_GET(val) ((((val) & PORT_P0_OUT_P12) >> 12) & 0x1) +#define PORT_P0_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 0 Pin # Output Value (11) */ +#define PORT_P0_OUT_P11 (0x1 << 11) +#define PORT_P0_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_OUT_P11_GET(val) ((((val) & PORT_P0_OUT_P11) >> 11) & 0x1) +#define PORT_P0_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 0 Pin # Output Value (10) */ +#define PORT_P0_OUT_P10 (0x1 << 10) +#define PORT_P0_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_OUT_P10_GET(val) ((((val) & PORT_P0_OUT_P10) >> 10) & 0x1) +#define PORT_P0_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 0 Pin # Output Value (9) */ +#define PORT_P0_OUT_P9 (0x1 << 9) +#define PORT_P0_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_OUT_P9_GET(val) ((((val) & PORT_P0_OUT_P9) >> 9) & 0x1) +#define PORT_P0_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 0 Pin # Output Value (8) */ +#define PORT_P0_OUT_P8 (0x1 << 8) +#define PORT_P0_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_OUT_P8_GET(val) ((((val) & PORT_P0_OUT_P8) >> 8) & 0x1) +#define PORT_P0_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 0 Pin # Output Value (7) */ +#define PORT_P0_OUT_P7 (0x1 << 7) +#define PORT_P0_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_OUT_P7_GET(val) ((((val) & PORT_P0_OUT_P7) >> 7) & 0x1) +#define PORT_P0_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 0 Pin # Output Value (6) */ +#define PORT_P0_OUT_P6 (0x1 << 6) +#define PORT_P0_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_OUT_P6_GET(val) ((((val) & PORT_P0_OUT_P6) >> 6) & 0x1) +#define PORT_P0_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 0 Pin # Output Value (5) */ +#define PORT_P0_OUT_P5 (0x1 << 5) +#define PORT_P0_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_OUT_P5_GET(val) ((((val) & PORT_P0_OUT_P5) >> 5) & 0x1) +#define PORT_P0_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 0 Pin # Output Value (4) */ +#define PORT_P0_OUT_P4 (0x1 << 4) +#define PORT_P0_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_OUT_P4_GET(val) ((((val) & PORT_P0_OUT_P4) >> 4) & 0x1) +#define PORT_P0_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 0 Pin # Output Value (3) */ +#define PORT_P0_OUT_P3 (0x1 << 3) +#define PORT_P0_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_OUT_P3_GET(val) ((((val) & PORT_P0_OUT_P3) >> 3) & 0x1) +#define PORT_P0_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 0 Pin # Output Value (2) */ +#define PORT_P0_OUT_P2 (0x1 << 2) +#define PORT_P0_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_OUT_P2_GET(val) ((((val) & PORT_P0_OUT_P2) >> 2) & 0x1) +#define PORT_P0_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 0 Pin # Output Value (1) */ +#define PORT_P0_OUT_P1 (0x1 << 1) +#define PORT_P0_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_OUT_P1_GET(val) ((((val) & PORT_P0_OUT_P1) >> 1) & 0x1) +#define PORT_P0_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 0 Pin # Output Value (0) */ +#define PORT_P0_OUT_P0 (0x1) +#define PORT_P0_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_OUT_P0_GET(val) ((((val) & PORT_P0_OUT_P0) >> 0) & 0x1) +#define PORT_P0_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 Data Input Register + ******************************************************************************/ + +/* Port 0 Pin # Latched Input Value (19) */ +#define PORT_P0_IN_P19 (0x1 << 19) +#define PORT_P0_IN_P19_GET(val) ((((val) & PORT_P0_IN_P19) >> 19) & 0x1) +/* Port 0 Pin # Latched Input Value (18) */ +#define PORT_P0_IN_P18 (0x1 << 18) +#define PORT_P0_IN_P18_GET(val) ((((val) & PORT_P0_IN_P18) >> 18) & 0x1) +/* Port 0 Pin # Latched Input Value (17) */ +#define PORT_P0_IN_P17 (0x1 << 17) +#define PORT_P0_IN_P17_GET(val) ((((val) & PORT_P0_IN_P17) >> 17) & 0x1) +/* Port 0 Pin # Latched Input Value (16) */ +#define PORT_P0_IN_P16 (0x1 << 16) +#define PORT_P0_IN_P16_GET(val) ((((val) & PORT_P0_IN_P16) >> 16) & 0x1) +/* Port 0 Pin # Latched Input Value (15) */ +#define PORT_P0_IN_P15 (0x1 << 15) +#define PORT_P0_IN_P15_GET(val) ((((val) & PORT_P0_IN_P15) >> 15) & 0x1) +/* Port 0 Pin # Latched Input Value (14) */ +#define PORT_P0_IN_P14 (0x1 << 14) +#define PORT_P0_IN_P14_GET(val) ((((val) & PORT_P0_IN_P14) >> 14) & 0x1) +/* Port 0 Pin # Latched Input Value (13) */ +#define PORT_P0_IN_P13 (0x1 << 13) +#define PORT_P0_IN_P13_GET(val) ((((val) & PORT_P0_IN_P13) >> 13) & 0x1) +/* Port 0 Pin # Latched Input Value (12) */ +#define PORT_P0_IN_P12 (0x1 << 12) +#define PORT_P0_IN_P12_GET(val) ((((val) & PORT_P0_IN_P12) >> 12) & 0x1) +/* Port 0 Pin # Latched Input Value (11) */ +#define PORT_P0_IN_P11 (0x1 << 11) +#define PORT_P0_IN_P11_GET(val) ((((val) & PORT_P0_IN_P11) >> 11) & 0x1) +/* Port 0 Pin # Latched Input Value (10) */ +#define PORT_P0_IN_P10 (0x1 << 10) +#define PORT_P0_IN_P10_GET(val) ((((val) & PORT_P0_IN_P10) >> 10) & 0x1) +/* Port 0 Pin # Latched Input Value (9) */ +#define PORT_P0_IN_P9 (0x1 << 9) +#define PORT_P0_IN_P9_GET(val) ((((val) & PORT_P0_IN_P9) >> 9) & 0x1) +/* Port 0 Pin # Latched Input Value (8) */ +#define PORT_P0_IN_P8 (0x1 << 8) +#define PORT_P0_IN_P8_GET(val) ((((val) & PORT_P0_IN_P8) >> 8) & 0x1) +/* Port 0 Pin # Latched Input Value (7) */ +#define PORT_P0_IN_P7 (0x1 << 7) +#define PORT_P0_IN_P7_GET(val) ((((val) & PORT_P0_IN_P7) >> 7) & 0x1) +/* Port 0 Pin # Latched Input Value (6) */ +#define PORT_P0_IN_P6 (0x1 << 6) +#define PORT_P0_IN_P6_GET(val) ((((val) & PORT_P0_IN_P6) >> 6) & 0x1) +/* Port 0 Pin # Latched Input Value (5) */ +#define PORT_P0_IN_P5 (0x1 << 5) +#define PORT_P0_IN_P5_GET(val) ((((val) & PORT_P0_IN_P5) >> 5) & 0x1) +/* Port 0 Pin # Latched Input Value (4) */ +#define PORT_P0_IN_P4 (0x1 << 4) +#define PORT_P0_IN_P4_GET(val) ((((val) & PORT_P0_IN_P4) >> 4) & 0x1) +/* Port 0 Pin # Latched Input Value (3) */ +#define PORT_P0_IN_P3 (0x1 << 3) +#define PORT_P0_IN_P3_GET(val) ((((val) & PORT_P0_IN_P3) >> 3) & 0x1) +/* Port 0 Pin # Latched Input Value (2) */ +#define PORT_P0_IN_P2 (0x1 << 2) +#define PORT_P0_IN_P2_GET(val) ((((val) & PORT_P0_IN_P2) >> 2) & 0x1) +/* Port 0 Pin # Latched Input Value (1) */ +#define PORT_P0_IN_P1 (0x1 << 1) +#define PORT_P0_IN_P1_GET(val) ((((val) & PORT_P0_IN_P1) >> 1) & 0x1) +/* Port 0 Pin # Latched Input Value (0) */ +#define PORT_P0_IN_P0 (0x1) +#define PORT_P0_IN_P0_GET(val) ((((val) & PORT_P0_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 0 Direction Register + ******************************************************************************/ + +/* Port 0 Pin #Direction Control (19) */ +#define PORT_P0_DIR_P19 (0x1 << 19) +#define PORT_P0_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_DIR_P19_GET(val) ((((val) & PORT_P0_DIR_P19) >> 19) & 0x1) +#define PORT_P0_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 0 Pin #Direction Control (18) */ +#define PORT_P0_DIR_P18 (0x1 << 18) +#define PORT_P0_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_DIR_P18_GET(val) ((((val) & PORT_P0_DIR_P18) >> 18) & 0x1) +#define PORT_P0_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 0 Pin #Direction Control (17) */ +#define PORT_P0_DIR_P17 (0x1 << 17) +#define PORT_P0_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_DIR_P17_GET(val) ((((val) & PORT_P0_DIR_P17) >> 17) & 0x1) +#define PORT_P0_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 0 Pin #Direction Control (16) */ +#define PORT_P0_DIR_P16 (0x1 << 16) +#define PORT_P0_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_DIR_P16_GET(val) ((((val) & PORT_P0_DIR_P16) >> 16) & 0x1) +#define PORT_P0_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 0 Pin #Direction Control (15) */ +#define PORT_P0_DIR_P15 (0x1 << 15) +#define PORT_P0_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_DIR_P15_GET(val) ((((val) & PORT_P0_DIR_P15) >> 15) & 0x1) +#define PORT_P0_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 0 Pin #Direction Control (14) */ +#define PORT_P0_DIR_P14 (0x1 << 14) +#define PORT_P0_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_DIR_P14_GET(val) ((((val) & PORT_P0_DIR_P14) >> 14) & 0x1) +#define PORT_P0_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 0 Pin #Direction Control (13) */ +#define PORT_P0_DIR_P13 (0x1 << 13) +#define PORT_P0_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_DIR_P13_GET(val) ((((val) & PORT_P0_DIR_P13) >> 13) & 0x1) +#define PORT_P0_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 0 Pin #Direction Control (12) */ +#define PORT_P0_DIR_P12 (0x1 << 12) +#define PORT_P0_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_DIR_P12_GET(val) ((((val) & PORT_P0_DIR_P12) >> 12) & 0x1) +#define PORT_P0_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 0 Pin #Direction Control (11) */ +#define PORT_P0_DIR_P11 (0x1 << 11) +#define PORT_P0_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_DIR_P11_GET(val) ((((val) & PORT_P0_DIR_P11) >> 11) & 0x1) +#define PORT_P0_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 0 Pin #Direction Control (10) */ +#define PORT_P0_DIR_P10 (0x1 << 10) +#define PORT_P0_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_DIR_P10_GET(val) ((((val) & PORT_P0_DIR_P10) >> 10) & 0x1) +#define PORT_P0_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 0 Pin #Direction Control (9) */ +#define PORT_P0_DIR_P9 (0x1 << 9) +#define PORT_P0_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_DIR_P9_GET(val) ((((val) & PORT_P0_DIR_P9) >> 9) & 0x1) +#define PORT_P0_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 0 Pin #Direction Control (8) */ +#define PORT_P0_DIR_P8 (0x1 << 8) +#define PORT_P0_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_DIR_P8_GET(val) ((((val) & PORT_P0_DIR_P8) >> 8) & 0x1) +#define PORT_P0_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 0 Pin #Direction Control (7) */ +#define PORT_P0_DIR_P7 (0x1 << 7) +#define PORT_P0_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_DIR_P7_GET(val) ((((val) & PORT_P0_DIR_P7) >> 7) & 0x1) +#define PORT_P0_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 0 Pin #Direction Control (6) */ +#define PORT_P0_DIR_P6 (0x1 << 6) +#define PORT_P0_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_DIR_P6_GET(val) ((((val) & PORT_P0_DIR_P6) >> 6) & 0x1) +#define PORT_P0_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 0 Pin #Direction Control (5) */ +#define PORT_P0_DIR_P5 (0x1 << 5) +#define PORT_P0_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_DIR_P5_GET(val) ((((val) & PORT_P0_DIR_P5) >> 5) & 0x1) +#define PORT_P0_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 0 Pin #Direction Control (4) */ +#define PORT_P0_DIR_P4 (0x1 << 4) +#define PORT_P0_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_DIR_P4_GET(val) ((((val) & PORT_P0_DIR_P4) >> 4) & 0x1) +#define PORT_P0_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 0 Pin #Direction Control (3) */ +#define PORT_P0_DIR_P3 (0x1 << 3) +#define PORT_P0_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_DIR_P3_GET(val) ((((val) & PORT_P0_DIR_P3) >> 3) & 0x1) +#define PORT_P0_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 0 Pin #Direction Control (2) */ +#define PORT_P0_DIR_P2 (0x1 << 2) +#define PORT_P0_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_DIR_P2_GET(val) ((((val) & PORT_P0_DIR_P2) >> 2) & 0x1) +#define PORT_P0_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 0 Pin #Direction Control (1) */ +#define PORT_P0_DIR_P1 (0x1 << 1) +#define PORT_P0_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_DIR_P1_GET(val) ((((val) & PORT_P0_DIR_P1) >> 1) & 0x1) +#define PORT_P0_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 0 Pin #Direction Control (0) */ +#define PORT_P0_DIR_P0 (0x1) +#define PORT_P0_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_DIR_P0_GET(val) ((((val) & PORT_P0_DIR_P0) >> 0) & 0x1) +#define PORT_P0_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 0 Bit # (19) */ +#define PORT_P0_ALTSEL0_P19 (0x1 << 19) +#define PORT_P0_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_ALTSEL0_P19_GET(val) ((((val) & PORT_P0_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P0_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 0 Bit # (18) */ +#define PORT_P0_ALTSEL0_P18 (0x1 << 18) +#define PORT_P0_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_ALTSEL0_P18_GET(val) ((((val) & PORT_P0_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P0_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 0 Bit # (17) */ +#define PORT_P0_ALTSEL0_P17 (0x1 << 17) +#define PORT_P0_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_ALTSEL0_P17_GET(val) ((((val) & PORT_P0_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P0_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 0 Bit # (16) */ +#define PORT_P0_ALTSEL0_P16 (0x1 << 16) +#define PORT_P0_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_ALTSEL0_P16_GET(val) ((((val) & PORT_P0_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P0_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 0 Bit # (15) */ +#define PORT_P0_ALTSEL0_P15 (0x1 << 15) +#define PORT_P0_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_ALTSEL0_P15_GET(val) ((((val) & PORT_P0_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P0_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 0 Bit # (14) */ +#define PORT_P0_ALTSEL0_P14 (0x1 << 14) +#define PORT_P0_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_ALTSEL0_P14_GET(val) ((((val) & PORT_P0_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P0_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 0 Bit # (13) */ +#define PORT_P0_ALTSEL0_P13 (0x1 << 13) +#define PORT_P0_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_ALTSEL0_P13_GET(val) ((((val) & PORT_P0_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P0_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 0 Bit # (12) */ +#define PORT_P0_ALTSEL0_P12 (0x1 << 12) +#define PORT_P0_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_ALTSEL0_P12_GET(val) ((((val) & PORT_P0_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P0_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 0 Bit # (11) */ +#define PORT_P0_ALTSEL0_P11 (0x1 << 11) +#define PORT_P0_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_ALTSEL0_P11_GET(val) ((((val) & PORT_P0_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P0_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 0 Bit # (10) */ +#define PORT_P0_ALTSEL0_P10 (0x1 << 10) +#define PORT_P0_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_ALTSEL0_P10_GET(val) ((((val) & PORT_P0_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P0_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 0 Bit # (9) */ +#define PORT_P0_ALTSEL0_P9 (0x1 << 9) +#define PORT_P0_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_ALTSEL0_P9_GET(val) ((((val) & PORT_P0_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P0_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 0 Bit # (8) */ +#define PORT_P0_ALTSEL0_P8 (0x1 << 8) +#define PORT_P0_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_ALTSEL0_P8_GET(val) ((((val) & PORT_P0_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P0_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 0 Bit # (7) */ +#define PORT_P0_ALTSEL0_P7 (0x1 << 7) +#define PORT_P0_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_ALTSEL0_P7_GET(val) ((((val) & PORT_P0_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P0_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 0 Bit # (6) */ +#define PORT_P0_ALTSEL0_P6 (0x1 << 6) +#define PORT_P0_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_ALTSEL0_P6_GET(val) ((((val) & PORT_P0_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P0_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 0 Bit # (5) */ +#define PORT_P0_ALTSEL0_P5 (0x1 << 5) +#define PORT_P0_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_ALTSEL0_P5_GET(val) ((((val) & PORT_P0_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P0_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 0 Bit # (4) */ +#define PORT_P0_ALTSEL0_P4 (0x1 << 4) +#define PORT_P0_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_ALTSEL0_P4_GET(val) ((((val) & PORT_P0_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P0_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 0 Bit # (3) */ +#define PORT_P0_ALTSEL0_P3 (0x1 << 3) +#define PORT_P0_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_ALTSEL0_P3_GET(val) ((((val) & PORT_P0_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P0_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 0 Bit # (2) */ +#define PORT_P0_ALTSEL0_P2 (0x1 << 2) +#define PORT_P0_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_ALTSEL0_P2_GET(val) ((((val) & PORT_P0_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P0_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 0 Bit # (1) */ +#define PORT_P0_ALTSEL0_P1 (0x1 << 1) +#define PORT_P0_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_ALTSEL0_P1_GET(val) ((((val) & PORT_P0_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P0_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 0 Bit # (0) */ +#define PORT_P0_ALTSEL0_P0 (0x1) +#define PORT_P0_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_ALTSEL0_P0_GET(val) ((((val) & PORT_P0_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P0_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 Alternate Function Select Register 1 + ******************************************************************************/ + +/* Alternate Function at Port 0 Bit # (13) */ +#define PORT_P0_ALTSEL1_P13 (0x1 << 13) +#define PORT_P0_ALTSEL1_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_ALTSEL1_P13_GET(val) ((((val) & PORT_P0_ALTSEL1_P13) >> 13) & 0x1) +#define PORT_P0_ALTSEL1_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 0 Bit # (12) */ +#define PORT_P0_ALTSEL1_P12 (0x1 << 12) +#define PORT_P0_ALTSEL1_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_ALTSEL1_P12_GET(val) ((((val) & PORT_P0_ALTSEL1_P12) >> 12) & 0x1) +#define PORT_P0_ALTSEL1_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 0 Bit # (11) */ +#define PORT_P0_ALTSEL1_P11 (0x1 << 11) +#define PORT_P0_ALTSEL1_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_ALTSEL1_P11_GET(val) ((((val) & PORT_P0_ALTSEL1_P11) >> 11) & 0x1) +#define PORT_P0_ALTSEL1_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 0 Bit # (10) */ +#define PORT_P0_ALTSEL1_P10 (0x1 << 10) +#define PORT_P0_ALTSEL1_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_ALTSEL1_P10_GET(val) ((((val) & PORT_P0_ALTSEL1_P10) >> 10) & 0x1) +#define PORT_P0_ALTSEL1_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 0 Bit # (9) */ +#define PORT_P0_ALTSEL1_P9 (0x1 << 9) +#define PORT_P0_ALTSEL1_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_ALTSEL1_P9_GET(val) ((((val) & PORT_P0_ALTSEL1_P9) >> 9) & 0x1) +#define PORT_P0_ALTSEL1_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 0 Bit # (8) */ +#define PORT_P0_ALTSEL1_P8 (0x1 << 8) +#define PORT_P0_ALTSEL1_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_ALTSEL1_P8_GET(val) ((((val) & PORT_P0_ALTSEL1_P8) >> 8) & 0x1) +#define PORT_P0_ALTSEL1_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 0 Bit # (7) */ +#define PORT_P0_ALTSEL1_P7 (0x1 << 7) +#define PORT_P0_ALTSEL1_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_ALTSEL1_P7_GET(val) ((((val) & PORT_P0_ALTSEL1_P7) >> 7) & 0x1) +#define PORT_P0_ALTSEL1_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 0 Bit # (6) */ +#define PORT_P0_ALTSEL1_P6 (0x1 << 6) +#define PORT_P0_ALTSEL1_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_ALTSEL1_P6_GET(val) ((((val) & PORT_P0_ALTSEL1_P6) >> 6) & 0x1) +#define PORT_P0_ALTSEL1_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 0 Bit # (3) */ +#define PORT_P0_ALTSEL1_P3 (0x1 << 3) +#define PORT_P0_ALTSEL1_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_ALTSEL1_P3_GET(val) ((((val) & PORT_P0_ALTSEL1_P3) >> 3) & 0x1) +#define PORT_P0_ALTSEL1_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P3) | (((val) & 0x1) << 3)) + +/******************************************************************************* + * Port 0 Pull Up Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 0 Bit # (19) */ +#define PORT_P0_PUEN_P19 (0x1 << 19) +#define PORT_P0_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_PUEN_P19_GET(val) ((((val) & PORT_P0_PUEN_P19) >> 19) & 0x1) +#define PORT_P0_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 0 Bit # (18) */ +#define PORT_P0_PUEN_P18 (0x1 << 18) +#define PORT_P0_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_PUEN_P18_GET(val) ((((val) & PORT_P0_PUEN_P18) >> 18) & 0x1) +#define PORT_P0_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 0 Bit # (17) */ +#define PORT_P0_PUEN_P17 (0x1 << 17) +#define PORT_P0_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_PUEN_P17_GET(val) ((((val) & PORT_P0_PUEN_P17) >> 17) & 0x1) +#define PORT_P0_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 0 Bit # (16) */ +#define PORT_P0_PUEN_P16 (0x1 << 16) +#define PORT_P0_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_PUEN_P16_GET(val) ((((val) & PORT_P0_PUEN_P16) >> 16) & 0x1) +#define PORT_P0_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 0 Bit # (15) */ +#define PORT_P0_PUEN_P15 (0x1 << 15) +#define PORT_P0_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_PUEN_P15_GET(val) ((((val) & PORT_P0_PUEN_P15) >> 15) & 0x1) +#define PORT_P0_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 0 Bit # (14) */ +#define PORT_P0_PUEN_P14 (0x1 << 14) +#define PORT_P0_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_PUEN_P14_GET(val) ((((val) & PORT_P0_PUEN_P14) >> 14) & 0x1) +#define PORT_P0_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 0 Bit # (13) */ +#define PORT_P0_PUEN_P13 (0x1 << 13) +#define PORT_P0_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_PUEN_P13_GET(val) ((((val) & PORT_P0_PUEN_P13) >> 13) & 0x1) +#define PORT_P0_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 0 Bit # (12) */ +#define PORT_P0_PUEN_P12 (0x1 << 12) +#define PORT_P0_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_PUEN_P12_GET(val) ((((val) & PORT_P0_PUEN_P12) >> 12) & 0x1) +#define PORT_P0_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 0 Bit # (11) */ +#define PORT_P0_PUEN_P11 (0x1 << 11) +#define PORT_P0_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_PUEN_P11_GET(val) ((((val) & PORT_P0_PUEN_P11) >> 11) & 0x1) +#define PORT_P0_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 0 Bit # (10) */ +#define PORT_P0_PUEN_P10 (0x1 << 10) +#define PORT_P0_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_PUEN_P10_GET(val) ((((val) & PORT_P0_PUEN_P10) >> 10) & 0x1) +#define PORT_P0_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 0 Bit # (9) */ +#define PORT_P0_PUEN_P9 (0x1 << 9) +#define PORT_P0_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_PUEN_P9_GET(val) ((((val) & PORT_P0_PUEN_P9) >> 9) & 0x1) +#define PORT_P0_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 0 Bit # (8) */ +#define PORT_P0_PUEN_P8 (0x1 << 8) +#define PORT_P0_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_PUEN_P8_GET(val) ((((val) & PORT_P0_PUEN_P8) >> 8) & 0x1) +#define PORT_P0_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 0 Bit # (7) */ +#define PORT_P0_PUEN_P7 (0x1 << 7) +#define PORT_P0_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_PUEN_P7_GET(val) ((((val) & PORT_P0_PUEN_P7) >> 7) & 0x1) +#define PORT_P0_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 0 Bit # (6) */ +#define PORT_P0_PUEN_P6 (0x1 << 6) +#define PORT_P0_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_PUEN_P6_GET(val) ((((val) & PORT_P0_PUEN_P6) >> 6) & 0x1) +#define PORT_P0_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 0 Bit # (5) */ +#define PORT_P0_PUEN_P5 (0x1 << 5) +#define PORT_P0_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_PUEN_P5_GET(val) ((((val) & PORT_P0_PUEN_P5) >> 5) & 0x1) +#define PORT_P0_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 0 Bit # (4) */ +#define PORT_P0_PUEN_P4 (0x1 << 4) +#define PORT_P0_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_PUEN_P4_GET(val) ((((val) & PORT_P0_PUEN_P4) >> 4) & 0x1) +#define PORT_P0_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 0 Bit # (3) */ +#define PORT_P0_PUEN_P3 (0x1 << 3) +#define PORT_P0_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_PUEN_P3_GET(val) ((((val) & PORT_P0_PUEN_P3) >> 3) & 0x1) +#define PORT_P0_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 0 Bit # (2) */ +#define PORT_P0_PUEN_P2 (0x1 << 2) +#define PORT_P0_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_PUEN_P2_GET(val) ((((val) & PORT_P0_PUEN_P2) >> 2) & 0x1) +#define PORT_P0_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 0 Bit # (1) */ +#define PORT_P0_PUEN_P1 (0x1 << 1) +#define PORT_P0_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_PUEN_P1_GET(val) ((((val) & PORT_P0_PUEN_P1) >> 1) & 0x1) +#define PORT_P0_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 0 Bit # (0) */ +#define PORT_P0_PUEN_P0 (0x1) +#define PORT_P0_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_PUEN_P0_GET(val) ((((val) & PORT_P0_PUEN_P0) >> 0) & 0x1) +#define PORT_P0_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * External Interrupt Control Register 0 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT16 (19) */ +#define PORT_P0_EXINTCR0_EXINT16 (0x1 << 19) +#define PORT_P0_EXINTCR0_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_EXINTCR0_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT16) >> 19) & 0x1) +#define PORT_P0_EXINTCR0_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT16) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT10 (17) */ +#define PORT_P0_EXINTCR0_EXINT10 (0x1 << 17) +#define PORT_P0_EXINTCR0_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_EXINTCR0_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT10) >> 17) & 0x1) +#define PORT_P0_EXINTCR0_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT10) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT9 (16) */ +#define PORT_P0_EXINTCR0_EXINT9 (0x1 << 16) +#define PORT_P0_EXINTCR0_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_EXINTCR0_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT9) >> 16) & 0x1) +#define PORT_P0_EXINTCR0_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT9) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT8 (15) */ +#define PORT_P0_EXINTCR0_EXINT8 (0x1 << 15) +#define PORT_P0_EXINTCR0_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_EXINTCR0_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT8) >> 15) & 0x1) +#define PORT_P0_EXINTCR0_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT8) | (((val) & 0x1) << 15)) +/* Type of Level or Edge Detection of EXINT7 (14) */ +#define PORT_P0_EXINTCR0_EXINT7 (0x1 << 14) +#define PORT_P0_EXINTCR0_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_EXINTCR0_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT7) >> 14) & 0x1) +#define PORT_P0_EXINTCR0_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT7) | (((val) & 0x1) << 14)) +/* Type of Level or Edge Detection of EXINT6 (13) */ +#define PORT_P0_EXINTCR0_EXINT6 (0x1 << 13) +#define PORT_P0_EXINTCR0_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_EXINTCR0_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT6) >> 13) & 0x1) +#define PORT_P0_EXINTCR0_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT6) | (((val) & 0x1) << 13)) +/* Type of Level or Edge Detection of EXINT5 (12) */ +#define PORT_P0_EXINTCR0_EXINT5 (0x1 << 12) +#define PORT_P0_EXINTCR0_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_EXINTCR0_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT5) >> 12) & 0x1) +#define PORT_P0_EXINTCR0_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT5) | (((val) & 0x1) << 12)) +/* Type of Level or Edge Detection of EXINT4 (11) */ +#define PORT_P0_EXINTCR0_EXINT4 (0x1 << 11) +#define PORT_P0_EXINTCR0_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_EXINTCR0_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT4) >> 11) & 0x1) +#define PORT_P0_EXINTCR0_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT4) | (((val) & 0x1) << 11)) +/* Type of Level or Edge Detection of EXINT3 (10) */ +#define PORT_P0_EXINTCR0_EXINT3 (0x1 << 10) +#define PORT_P0_EXINTCR0_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_EXINTCR0_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT3) >> 10) & 0x1) +#define PORT_P0_EXINTCR0_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT3) | (((val) & 0x1) << 10)) +/* Type of Level or Edge Detection of EXINT2 (9) */ +#define PORT_P0_EXINTCR0_EXINT2 (0x1 << 9) +#define PORT_P0_EXINTCR0_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_EXINTCR0_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT2) >> 9) & 0x1) +#define PORT_P0_EXINTCR0_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT2) | (((val) & 0x1) << 9)) +/* Type of Level or Edge Detection of EXINT1 (8) */ +#define PORT_P0_EXINTCR0_EXINT1 (0x1 << 8) +#define PORT_P0_EXINTCR0_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_EXINTCR0_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT1) >> 8) & 0x1) +#define PORT_P0_EXINTCR0_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT1) | (((val) & 0x1) << 8)) +/* Type of Level or Edge Detection of EXINT0 (7) */ +#define PORT_P0_EXINTCR0_EXINT0 (0x1 << 7) +#define PORT_P0_EXINTCR0_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_EXINTCR0_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT0) >> 7) & 0x1) +#define PORT_P0_EXINTCR0_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * External Interrupt Control Register 1 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT16 (19) */ +#define PORT_P0_EXINTCR1_EXINT16 (0x1 << 19) +#define PORT_P0_EXINTCR1_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_EXINTCR1_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT16) >> 19) & 0x1) +#define PORT_P0_EXINTCR1_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT16) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT10 (17) */ +#define PORT_P0_EXINTCR1_EXINT10 (0x1 << 17) +#define PORT_P0_EXINTCR1_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_EXINTCR1_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT10) >> 17) & 0x1) +#define PORT_P0_EXINTCR1_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT10) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT9 (16) */ +#define PORT_P0_EXINTCR1_EXINT9 (0x1 << 16) +#define PORT_P0_EXINTCR1_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_EXINTCR1_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT9) >> 16) & 0x1) +#define PORT_P0_EXINTCR1_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT9) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT8 (15) */ +#define PORT_P0_EXINTCR1_EXINT8 (0x1 << 15) +#define PORT_P0_EXINTCR1_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_EXINTCR1_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT8) >> 15) & 0x1) +#define PORT_P0_EXINTCR1_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT8) | (((val) & 0x1) << 15)) +/* Type of Level or Edge Detection of EXINT7 (14) */ +#define PORT_P0_EXINTCR1_EXINT7 (0x1 << 14) +#define PORT_P0_EXINTCR1_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_EXINTCR1_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT7) >> 14) & 0x1) +#define PORT_P0_EXINTCR1_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT7) | (((val) & 0x1) << 14)) +/* Type of Level or Edge Detection of EXINT6 (13) */ +#define PORT_P0_EXINTCR1_EXINT6 (0x1 << 13) +#define PORT_P0_EXINTCR1_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_EXINTCR1_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT6) >> 13) & 0x1) +#define PORT_P0_EXINTCR1_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT6) | (((val) & 0x1) << 13)) +/* Type of Level or Edge Detection of EXINT5 (12) */ +#define PORT_P0_EXINTCR1_EXINT5 (0x1 << 12) +#define PORT_P0_EXINTCR1_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_EXINTCR1_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT5) >> 12) & 0x1) +#define PORT_P0_EXINTCR1_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT5) | (((val) & 0x1) << 12)) +/* Type of Level or Edge Detection of EXINT4 (11) */ +#define PORT_P0_EXINTCR1_EXINT4 (0x1 << 11) +#define PORT_P0_EXINTCR1_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_EXINTCR1_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT4) >> 11) & 0x1) +#define PORT_P0_EXINTCR1_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT4) | (((val) & 0x1) << 11)) +/* Type of Level or Edge Detection of EXINT3 (10) */ +#define PORT_P0_EXINTCR1_EXINT3 (0x1 << 10) +#define PORT_P0_EXINTCR1_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_EXINTCR1_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT3) >> 10) & 0x1) +#define PORT_P0_EXINTCR1_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT3) | (((val) & 0x1) << 10)) +/* Type of Level or Edge Detection of EXINT2 (9) */ +#define PORT_P0_EXINTCR1_EXINT2 (0x1 << 9) +#define PORT_P0_EXINTCR1_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_EXINTCR1_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT2) >> 9) & 0x1) +#define PORT_P0_EXINTCR1_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT2) | (((val) & 0x1) << 9)) +/* Type of Level or Edge Detection of EXINT1 (8) */ +#define PORT_P0_EXINTCR1_EXINT1 (0x1 << 8) +#define PORT_P0_EXINTCR1_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_EXINTCR1_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT1) >> 8) & 0x1) +#define PORT_P0_EXINTCR1_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT1) | (((val) & 0x1) << 8)) +/* Type of Level or Edge Detection of EXINT0 (7) */ +#define PORT_P0_EXINTCR1_EXINT0 (0x1 << 7) +#define PORT_P0_EXINTCR1_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_EXINTCR1_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT0) >> 7) & 0x1) +#define PORT_P0_EXINTCR1_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * P0_IRNEN Register + ******************************************************************************/ + +/* EXINT16 Interrupt Request Enable (19) */ +#define PORT_P0_IRNEN_EXINT16 (0x1 << 19) +#define PORT_P0_IRNEN_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNEN_EXINT16_GET(val) ((((val) & PORT_P0_IRNEN_EXINT16) >> 19) & 0x1) +#define PORT_P0_IRNEN_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT16) | (((val) & 0x1) << 19)) +/* EXINT10 Interrupt Request Enable (17) */ +#define PORT_P0_IRNEN_EXINT10 (0x1 << 17) +#define PORT_P0_IRNEN_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNEN_EXINT10_GET(val) ((((val) & PORT_P0_IRNEN_EXINT10) >> 17) & 0x1) +#define PORT_P0_IRNEN_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT10) | (((val) & 0x1) << 17)) +/* EXINT9 Interrupt Request Enable (16) */ +#define PORT_P0_IRNEN_EXINT9 (0x1 << 16) +#define PORT_P0_IRNEN_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNEN_EXINT9_GET(val) ((((val) & PORT_P0_IRNEN_EXINT9) >> 16) & 0x1) +#define PORT_P0_IRNEN_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT9) | (((val) & 0x1) << 16)) +/* EXINT8 Interrupt Request Enable (15) */ +#define PORT_P0_IRNEN_EXINT8 (0x1 << 15) +#define PORT_P0_IRNEN_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNEN_EXINT8_GET(val) ((((val) & PORT_P0_IRNEN_EXINT8) >> 15) & 0x1) +#define PORT_P0_IRNEN_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT8) | (((val) & 0x1) << 15)) +/* EXINT7 Interrupt Request Enable (14) */ +#define PORT_P0_IRNEN_EXINT7 (0x1 << 14) +#define PORT_P0_IRNEN_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNEN_EXINT7_GET(val) ((((val) & PORT_P0_IRNEN_EXINT7) >> 14) & 0x1) +#define PORT_P0_IRNEN_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT7) | (((val) & 0x1) << 14)) +/* EXINT6 Interrupt Request Enable (13) */ +#define PORT_P0_IRNEN_EXINT6 (0x1 << 13) +#define PORT_P0_IRNEN_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNEN_EXINT6_GET(val) ((((val) & PORT_P0_IRNEN_EXINT6) >> 13) & 0x1) +#define PORT_P0_IRNEN_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT6) | (((val) & 0x1) << 13)) +/* EXINT5 Interrupt Request Enable (12) */ +#define PORT_P0_IRNEN_EXINT5 (0x1 << 12) +#define PORT_P0_IRNEN_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNEN_EXINT5_GET(val) ((((val) & PORT_P0_IRNEN_EXINT5) >> 12) & 0x1) +#define PORT_P0_IRNEN_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT5) | (((val) & 0x1) << 12)) +/* EXINT4 Interrupt Request Enable (11) */ +#define PORT_P0_IRNEN_EXINT4 (0x1 << 11) +#define PORT_P0_IRNEN_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNEN_EXINT4_GET(val) ((((val) & PORT_P0_IRNEN_EXINT4) >> 11) & 0x1) +#define PORT_P0_IRNEN_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT4) | (((val) & 0x1) << 11)) +/* EXINT3 Interrupt Request Enable (10) */ +#define PORT_P0_IRNEN_EXINT3 (0x1 << 10) +#define PORT_P0_IRNEN_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNEN_EXINT3_GET(val) ((((val) & PORT_P0_IRNEN_EXINT3) >> 10) & 0x1) +#define PORT_P0_IRNEN_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT3) | (((val) & 0x1) << 10)) +/* EXINT2 Interrupt Request Enable (9) */ +#define PORT_P0_IRNEN_EXINT2 (0x1 << 9) +#define PORT_P0_IRNEN_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNEN_EXINT2_GET(val) ((((val) & PORT_P0_IRNEN_EXINT2) >> 9) & 0x1) +#define PORT_P0_IRNEN_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT2) | (((val) & 0x1) << 9)) +/* EXINT1 Interrupt Request Enable (8) */ +#define PORT_P0_IRNEN_EXINT1 (0x1 << 8) +#define PORT_P0_IRNEN_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNEN_EXINT1_GET(val) ((((val) & PORT_P0_IRNEN_EXINT1) >> 8) & 0x1) +#define PORT_P0_IRNEN_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT1) | (((val) & 0x1) << 8)) +/* EXINT0 Interrupt Request Enable (7) */ +#define PORT_P0_IRNEN_EXINT0 (0x1 << 7) +#define PORT_P0_IRNEN_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNEN_EXINT0_GET(val) ((((val) & PORT_P0_IRNEN_EXINT0) >> 7) & 0x1) +#define PORT_P0_IRNEN_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * P0_IRNICR Register + ******************************************************************************/ + +/* EXINT16 Interrupt Request (19) */ +#define PORT_P0_IRNICR_EXINT16 (0x1 << 19) +#define PORT_P0_IRNICR_EXINT16_GET(val) ((((val) & PORT_P0_IRNICR_EXINT16) >> 19) & 0x1) +/* EXINT10 Interrupt Request (17) */ +#define PORT_P0_IRNICR_EXINT10 (0x1 << 17) +#define PORT_P0_IRNICR_EXINT10_GET(val) ((((val) & PORT_P0_IRNICR_EXINT10) >> 17) & 0x1) +/* EXINT9 Interrupt Request (16) */ +#define PORT_P0_IRNICR_EXINT9 (0x1 << 16) +#define PORT_P0_IRNICR_EXINT9_GET(val) ((((val) & PORT_P0_IRNICR_EXINT9) >> 16) & 0x1) +/* EXINT8 Interrupt Request (15) */ +#define PORT_P0_IRNICR_EXINT8 (0x1 << 15) +#define PORT_P0_IRNICR_EXINT8_GET(val) ((((val) & PORT_P0_IRNICR_EXINT8) >> 15) & 0x1) +/* EXINT7 Interrupt Request (14) */ +#define PORT_P0_IRNICR_EXINT7 (0x1 << 14) +#define PORT_P0_IRNICR_EXINT7_GET(val) ((((val) & PORT_P0_IRNICR_EXINT7) >> 14) & 0x1) +/* EXINT6 Interrupt Request (13) */ +#define PORT_P0_IRNICR_EXINT6 (0x1 << 13) +#define PORT_P0_IRNICR_EXINT6_GET(val) ((((val) & PORT_P0_IRNICR_EXINT6) >> 13) & 0x1) +/* EXINT5 Interrupt Request (12) */ +#define PORT_P0_IRNICR_EXINT5 (0x1 << 12) +#define PORT_P0_IRNICR_EXINT5_GET(val) ((((val) & PORT_P0_IRNICR_EXINT5) >> 12) & 0x1) +/* EXINT4 Interrupt Request (11) */ +#define PORT_P0_IRNICR_EXINT4 (0x1 << 11) +#define PORT_P0_IRNICR_EXINT4_GET(val) ((((val) & PORT_P0_IRNICR_EXINT4) >> 11) & 0x1) +/* EXINT3 Interrupt Request (10) */ +#define PORT_P0_IRNICR_EXINT3 (0x1 << 10) +#define PORT_P0_IRNICR_EXINT3_GET(val) ((((val) & PORT_P0_IRNICR_EXINT3) >> 10) & 0x1) +/* EXINT2 Interrupt Request (9) */ +#define PORT_P0_IRNICR_EXINT2 (0x1 << 9) +#define PORT_P0_IRNICR_EXINT2_GET(val) ((((val) & PORT_P0_IRNICR_EXINT2) >> 9) & 0x1) +/* EXINT1 Interrupt Request (8) */ +#define PORT_P0_IRNICR_EXINT1 (0x1 << 8) +#define PORT_P0_IRNICR_EXINT1_GET(val) ((((val) & PORT_P0_IRNICR_EXINT1) >> 8) & 0x1) +/* EXINT0 Interrupt Request (7) */ +#define PORT_P0_IRNICR_EXINT0 (0x1 << 7) +#define PORT_P0_IRNICR_EXINT0_GET(val) ((((val) & PORT_P0_IRNICR_EXINT0) >> 7) & 0x1) + +/******************************************************************************* + * P0_IRNCR Register + ******************************************************************************/ + +/* EXINT16 Interrupt Request (19) */ +#define PORT_P0_IRNCR_EXINT16 (0x1 << 19) +#define PORT_P0_IRNCR_EXINT16_GET(val) ((((val) & PORT_P0_IRNCR_EXINT16) >> 19) & 0x1) +/* EXINT10 Interrupt Request (17) */ +#define PORT_P0_IRNCR_EXINT10 (0x1 << 17) +#define PORT_P0_IRNCR_EXINT10_GET(val) ((((val) & PORT_P0_IRNCR_EXINT10) >> 17) & 0x1) +/* EXINT9 Interrupt Request (16) */ +#define PORT_P0_IRNCR_EXINT9 (0x1 << 16) +#define PORT_P0_IRNCR_EXINT9_GET(val) ((((val) & PORT_P0_IRNCR_EXINT9) >> 16) & 0x1) +/* EXINT8 Interrupt Request (15) */ +#define PORT_P0_IRNCR_EXINT8 (0x1 << 15) +#define PORT_P0_IRNCR_EXINT8_GET(val) ((((val) & PORT_P0_IRNCR_EXINT8) >> 15) & 0x1) +/* EXINT7 Interrupt Request (14) */ +#define PORT_P0_IRNCR_EXINT7 (0x1 << 14) +#define PORT_P0_IRNCR_EXINT7_GET(val) ((((val) & PORT_P0_IRNCR_EXINT7) >> 14) & 0x1) +/* EXINT6 Interrupt Request (13) */ +#define PORT_P0_IRNCR_EXINT6 (0x1 << 13) +#define PORT_P0_IRNCR_EXINT6_GET(val) ((((val) & PORT_P0_IRNCR_EXINT6) >> 13) & 0x1) +/* EXINT5 Interrupt Request (12) */ +#define PORT_P0_IRNCR_EXINT5 (0x1 << 12) +#define PORT_P0_IRNCR_EXINT5_GET(val) ((((val) & PORT_P0_IRNCR_EXINT5) >> 12) & 0x1) +/* EXINT4 Interrupt Request (11) */ +#define PORT_P0_IRNCR_EXINT4 (0x1 << 11) +#define PORT_P0_IRNCR_EXINT4_GET(val) ((((val) & PORT_P0_IRNCR_EXINT4) >> 11) & 0x1) +/* EXINT3 Interrupt Request (10) */ +#define PORT_P0_IRNCR_EXINT3 (0x1 << 10) +#define PORT_P0_IRNCR_EXINT3_GET(val) ((((val) & PORT_P0_IRNCR_EXINT3) >> 10) & 0x1) +/* EXINT2 Interrupt Request (9) */ +#define PORT_P0_IRNCR_EXINT2 (0x1 << 9) +#define PORT_P0_IRNCR_EXINT2_GET(val) ((((val) & PORT_P0_IRNCR_EXINT2) >> 9) & 0x1) +/* EXINT1 Interrupt Request (8) */ +#define PORT_P0_IRNCR_EXINT1 (0x1 << 8) +#define PORT_P0_IRNCR_EXINT1_GET(val) ((((val) & PORT_P0_IRNCR_EXINT1) >> 8) & 0x1) +/* EXINT0 Interrupt Request (7) */ +#define PORT_P0_IRNCR_EXINT0 (0x1 << 7) +#define PORT_P0_IRNCR_EXINT0_GET(val) ((((val) & PORT_P0_IRNCR_EXINT0) >> 7) & 0x1) + +/******************************************************************************* + * P0 External Event Detection Configuration Register + ******************************************************************************/ + +/* EXINT16 configured for Edge or Level Detection (19) */ +#define PORT_P0_IRNCFG_EXINT16 (0x1 << 19) +#define PORT_P0_IRNCFG_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNCFG_EXINT16_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT16) >> 19) & 0x1) +#define PORT_P0_IRNCFG_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT16) | (((val) & 0x1) << 19)) +/* EXINT10 configured for Edge or Level Detection (17) */ +#define PORT_P0_IRNCFG_EXINT10 (0x1 << 17) +#define PORT_P0_IRNCFG_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNCFG_EXINT10_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT10) >> 17) & 0x1) +#define PORT_P0_IRNCFG_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT10) | (((val) & 0x1) << 17)) +/* EXINT9 configured for Edge or Level Detection (16) */ +#define PORT_P0_IRNCFG_EXINT9 (0x1 << 16) +#define PORT_P0_IRNCFG_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNCFG_EXINT9_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT9) >> 16) & 0x1) +#define PORT_P0_IRNCFG_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT9) | (((val) & 0x1) << 16)) +/* EXINT8 configured for Edge or Level Detection (15) */ +#define PORT_P0_IRNCFG_EXINT8 (0x1 << 15) +#define PORT_P0_IRNCFG_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNCFG_EXINT8_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT8) >> 15) & 0x1) +#define PORT_P0_IRNCFG_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT8) | (((val) & 0x1) << 15)) +/* EXINT7 configured for Edge or Level Detection (14) */ +#define PORT_P0_IRNCFG_EXINT7 (0x1 << 14) +#define PORT_P0_IRNCFG_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNCFG_EXINT7_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT7) >> 14) & 0x1) +#define PORT_P0_IRNCFG_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT7) | (((val) & 0x1) << 14)) +/* EXINT6 configured for Edge or Level Detection (13) */ +#define PORT_P0_IRNCFG_EXINT6 (0x1 << 13) +#define PORT_P0_IRNCFG_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNCFG_EXINT6_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT6) >> 13) & 0x1) +#define PORT_P0_IRNCFG_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT6) | (((val) & 0x1) << 13)) +/* EXINT5 configured for Edge or Level Detection (12) */ +#define PORT_P0_IRNCFG_EXINT5 (0x1 << 12) +#define PORT_P0_IRNCFG_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNCFG_EXINT5_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT5) >> 12) & 0x1) +#define PORT_P0_IRNCFG_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT5) | (((val) & 0x1) << 12)) +/* EXINT4 configured for Edge or Level Detection (11) */ +#define PORT_P0_IRNCFG_EXINT4 (0x1 << 11) +#define PORT_P0_IRNCFG_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNCFG_EXINT4_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT4) >> 11) & 0x1) +#define PORT_P0_IRNCFG_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT4) | (((val) & 0x1) << 11)) +/* EXINT3 configured for Edge or Level Detection (10) */ +#define PORT_P0_IRNCFG_EXINT3 (0x1 << 10) +#define PORT_P0_IRNCFG_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNCFG_EXINT3_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT3) >> 10) & 0x1) +#define PORT_P0_IRNCFG_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT3) | (((val) & 0x1) << 10)) +/* EXINT2 configured for Edge or Level Detection (9) */ +#define PORT_P0_IRNCFG_EXINT2 (0x1 << 9) +#define PORT_P0_IRNCFG_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNCFG_EXINT2_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT2) >> 9) & 0x1) +#define PORT_P0_IRNCFG_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT2) | (((val) & 0x1) << 9)) +/* EXINT1 configured for Edge or Level Detection (8) */ +#define PORT_P0_IRNCFG_EXINT1 (0x1 << 8) +#define PORT_P0_IRNCFG_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNCFG_EXINT1_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT1) >> 8) & 0x1) +#define PORT_P0_IRNCFG_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT1) | (((val) & 0x1) << 8)) +/* EXINT0 configured for Edge or Level Detection (7) */ +#define PORT_P0_IRNCFG_EXINT0 (0x1 << 7) +#define PORT_P0_IRNCFG_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNCFG_EXINT0_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT0) >> 7) & 0x1) +#define PORT_P0_IRNCFG_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * P0_IRNENSET Register + ******************************************************************************/ + +/* Set Interrupt Node Enable Flag EXINT16 (19) */ +#define PORT_P0_IRNENSET_EXINT16 (0x1 << 19) +#define PORT_P0_IRNENSET_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNENSET_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT16) | (val) & 1) << 19) +/* Set Interrupt Node Enable Flag EXINT10 (17) */ +#define PORT_P0_IRNENSET_EXINT10 (0x1 << 17) +#define PORT_P0_IRNENSET_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNENSET_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT10) | (val) & 1) << 17) +/* Set Interrupt Node Enable Flag EXINT9 (16) */ +#define PORT_P0_IRNENSET_EXINT9 (0x1 << 16) +#define PORT_P0_IRNENSET_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNENSET_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT9) | (val) & 1) << 16) +/* Set Interrupt Node Enable Flag EXINT8 (15) */ +#define PORT_P0_IRNENSET_EXINT8 (0x1 << 15) +#define PORT_P0_IRNENSET_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNENSET_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT8) | (val) & 1) << 15) +/* Set Interrupt Node Enable Flag EXINT7 (14) */ +#define PORT_P0_IRNENSET_EXINT7 (0x1 << 14) +#define PORT_P0_IRNENSET_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNENSET_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT7) | (val) & 1) << 14) +/* Set Interrupt Node Enable Flag EXINT6 (13) */ +#define PORT_P0_IRNENSET_EXINT6 (0x1 << 13) +#define PORT_P0_IRNENSET_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNENSET_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT6) | (val) & 1) << 13) +/* Set Interrupt Node Enable Flag EXINT5 (12) */ +#define PORT_P0_IRNENSET_EXINT5 (0x1 << 12) +#define PORT_P0_IRNENSET_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNENSET_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT5) | (val) & 1) << 12) +/* Set Interrupt Node Enable Flag EXINT4 (11) */ +#define PORT_P0_IRNENSET_EXINT4 (0x1 << 11) +#define PORT_P0_IRNENSET_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNENSET_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT4) | (val) & 1) << 11) +/* Set Interrupt Node Enable Flag EXINT3 (10) */ +#define PORT_P0_IRNENSET_EXINT3 (0x1 << 10) +#define PORT_P0_IRNENSET_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNENSET_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT3) | (val) & 1) << 10) +/* Set Interrupt Node Enable Flag EXINT2 (9) */ +#define PORT_P0_IRNENSET_EXINT2 (0x1 << 9) +#define PORT_P0_IRNENSET_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNENSET_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT2) | (val) & 1) << 9) +/* Set Interrupt Node Enable Flag EXINT1 (8) */ +#define PORT_P0_IRNENSET_EXINT1 (0x1 << 8) +#define PORT_P0_IRNENSET_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNENSET_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT1) | (val) & 1) << 8) +/* Set Interrupt Node Enable Flag EXINT0 (7) */ +#define PORT_P0_IRNENSET_EXINT0 (0x1 << 7) +#define PORT_P0_IRNENSET_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNENSET_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT0) | (val) & 1) << 7) + +/******************************************************************************* + * P0_IRNENCLR Register + ******************************************************************************/ + +/* Clear Interrupt Node Enable Flag EXINT16 (19) */ +#define PORT_P0_IRNENCLR_EXINT16 (0x1 << 19) +#define PORT_P0_IRNENCLR_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNENCLR_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT16) | (val) & 1) << 19) +/* Clear Interrupt Node Enable Flag EXINT10 (17) */ +#define PORT_P0_IRNENCLR_EXINT10 (0x1 << 17) +#define PORT_P0_IRNENCLR_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNENCLR_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT10) | (val) & 1) << 17) +/* Clear Interrupt Node Enable Flag EXINT9 (16) */ +#define PORT_P0_IRNENCLR_EXINT9 (0x1 << 16) +#define PORT_P0_IRNENCLR_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNENCLR_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT9) | (val) & 1) << 16) +/* Clear Interrupt Node Enable Flag EXINT8 (15) */ +#define PORT_P0_IRNENCLR_EXINT8 (0x1 << 15) +#define PORT_P0_IRNENCLR_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNENCLR_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT8) | (val) & 1) << 15) +/* Clear Interrupt Node Enable Flag EXINT7 (14) */ +#define PORT_P0_IRNENCLR_EXINT7 (0x1 << 14) +#define PORT_P0_IRNENCLR_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNENCLR_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT7) | (val) & 1) << 14) +/* Clear Interrupt Node Enable Flag EXINT6 (13) */ +#define PORT_P0_IRNENCLR_EXINT6 (0x1 << 13) +#define PORT_P0_IRNENCLR_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNENCLR_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT6) | (val) & 1) << 13) +/* Clear Interrupt Node Enable Flag EXINT5 (12) */ +#define PORT_P0_IRNENCLR_EXINT5 (0x1 << 12) +#define PORT_P0_IRNENCLR_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNENCLR_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT5) | (val) & 1) << 12) +/* Clear Interrupt Node Enable Flag EXINT4 (11) */ +#define PORT_P0_IRNENCLR_EXINT4 (0x1 << 11) +#define PORT_P0_IRNENCLR_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNENCLR_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT4) | (val) & 1) << 11) +/* Clear Interrupt Node Enable Flag EXINT3 (10) */ +#define PORT_P0_IRNENCLR_EXINT3 (0x1 << 10) +#define PORT_P0_IRNENCLR_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNENCLR_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT3) | (val) & 1) << 10) +/* Clear Interrupt Node Enable Flag EXINT2 (9) */ +#define PORT_P0_IRNENCLR_EXINT2 (0x1 << 9) +#define PORT_P0_IRNENCLR_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNENCLR_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT2) | (val) & 1) << 9) +/* Clear Interrupt Node Enable Flag EXINT1 (8) */ +#define PORT_P0_IRNENCLR_EXINT1 (0x1 << 8) +#define PORT_P0_IRNENCLR_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNENCLR_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT1) | (val) & 1) << 8) +/* Clear Interrupt Node Enable Flag EXINT0 (7) */ +#define PORT_P0_IRNENCLR_EXINT0 (0x1 << 7) +#define PORT_P0_IRNENCLR_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNENCLR_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT0) | (val) & 1) << 7) + +/******************************************************************************* + * Port 1 Data Output Register + ******************************************************************************/ + +/* Port 1 Pin # Output Value (19) */ +#define PORT_P1_OUT_P19 (0x1 << 19) +#define PORT_P1_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_OUT_P19_GET(val) ((((val) & PORT_P1_OUT_P19) >> 19) & 0x1) +#define PORT_P1_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 1 Pin # Output Value (18) */ +#define PORT_P1_OUT_P18 (0x1 << 18) +#define PORT_P1_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_OUT_P18_GET(val) ((((val) & PORT_P1_OUT_P18) >> 18) & 0x1) +#define PORT_P1_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 1 Pin # Output Value (17) */ +#define PORT_P1_OUT_P17 (0x1 << 17) +#define PORT_P1_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_OUT_P17_GET(val) ((((val) & PORT_P1_OUT_P17) >> 17) & 0x1) +#define PORT_P1_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 1 Pin # Output Value (16) */ +#define PORT_P1_OUT_P16 (0x1 << 16) +#define PORT_P1_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_OUT_P16_GET(val) ((((val) & PORT_P1_OUT_P16) >> 16) & 0x1) +#define PORT_P1_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 1 Pin # Output Value (15) */ +#define PORT_P1_OUT_P15 (0x1 << 15) +#define PORT_P1_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_OUT_P15_GET(val) ((((val) & PORT_P1_OUT_P15) >> 15) & 0x1) +#define PORT_P1_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 1 Pin # Output Value (14) */ +#define PORT_P1_OUT_P14 (0x1 << 14) +#define PORT_P1_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_OUT_P14_GET(val) ((((val) & PORT_P1_OUT_P14) >> 14) & 0x1) +#define PORT_P1_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 1 Pin # Output Value (13) */ +#define PORT_P1_OUT_P13 (0x1 << 13) +#define PORT_P1_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_OUT_P13_GET(val) ((((val) & PORT_P1_OUT_P13) >> 13) & 0x1) +#define PORT_P1_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 1 Pin # Output Value (12) */ +#define PORT_P1_OUT_P12 (0x1 << 12) +#define PORT_P1_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_OUT_P12_GET(val) ((((val) & PORT_P1_OUT_P12) >> 12) & 0x1) +#define PORT_P1_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 1 Pin # Output Value (11) */ +#define PORT_P1_OUT_P11 (0x1 << 11) +#define PORT_P1_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_OUT_P11_GET(val) ((((val) & PORT_P1_OUT_P11) >> 11) & 0x1) +#define PORT_P1_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 1 Pin # Output Value (10) */ +#define PORT_P1_OUT_P10 (0x1 << 10) +#define PORT_P1_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_OUT_P10_GET(val) ((((val) & PORT_P1_OUT_P10) >> 10) & 0x1) +#define PORT_P1_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 1 Pin # Output Value (9) */ +#define PORT_P1_OUT_P9 (0x1 << 9) +#define PORT_P1_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_OUT_P9_GET(val) ((((val) & PORT_P1_OUT_P9) >> 9) & 0x1) +#define PORT_P1_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 1 Pin # Output Value (8) */ +#define PORT_P1_OUT_P8 (0x1 << 8) +#define PORT_P1_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_OUT_P8_GET(val) ((((val) & PORT_P1_OUT_P8) >> 8) & 0x1) +#define PORT_P1_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 1 Pin # Output Value (7) */ +#define PORT_P1_OUT_P7 (0x1 << 7) +#define PORT_P1_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_OUT_P7_GET(val) ((((val) & PORT_P1_OUT_P7) >> 7) & 0x1) +#define PORT_P1_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 1 Pin # Output Value (6) */ +#define PORT_P1_OUT_P6 (0x1 << 6) +#define PORT_P1_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_OUT_P6_GET(val) ((((val) & PORT_P1_OUT_P6) >> 6) & 0x1) +#define PORT_P1_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 1 Pin # Output Value (5) */ +#define PORT_P1_OUT_P5 (0x1 << 5) +#define PORT_P1_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_OUT_P5_GET(val) ((((val) & PORT_P1_OUT_P5) >> 5) & 0x1) +#define PORT_P1_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 1 Pin # Output Value (4) */ +#define PORT_P1_OUT_P4 (0x1 << 4) +#define PORT_P1_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_OUT_P4_GET(val) ((((val) & PORT_P1_OUT_P4) >> 4) & 0x1) +#define PORT_P1_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 1 Pin # Output Value (3) */ +#define PORT_P1_OUT_P3 (0x1 << 3) +#define PORT_P1_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_OUT_P3_GET(val) ((((val) & PORT_P1_OUT_P3) >> 3) & 0x1) +#define PORT_P1_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 1 Pin # Output Value (2) */ +#define PORT_P1_OUT_P2 (0x1 << 2) +#define PORT_P1_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_OUT_P2_GET(val) ((((val) & PORT_P1_OUT_P2) >> 2) & 0x1) +#define PORT_P1_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 1 Pin # Output Value (1) */ +#define PORT_P1_OUT_P1 (0x1 << 1) +#define PORT_P1_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_OUT_P1_GET(val) ((((val) & PORT_P1_OUT_P1) >> 1) & 0x1) +#define PORT_P1_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 1 Pin # Output Value (0) */ +#define PORT_P1_OUT_P0 (0x1) +#define PORT_P1_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_OUT_P0_GET(val) ((((val) & PORT_P1_OUT_P0) >> 0) & 0x1) +#define PORT_P1_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 1 Data Input Register + ******************************************************************************/ + +/* Port 1 Pin # Latched Input Value (19) */ +#define PORT_P1_IN_P19 (0x1 << 19) +#define PORT_P1_IN_P19_GET(val) ((((val) & PORT_P1_IN_P19) >> 19) & 0x1) +/* Port 1 Pin # Latched Input Value (18) */ +#define PORT_P1_IN_P18 (0x1 << 18) +#define PORT_P1_IN_P18_GET(val) ((((val) & PORT_P1_IN_P18) >> 18) & 0x1) +/* Port 1 Pin # Latched Input Value (17) */ +#define PORT_P1_IN_P17 (0x1 << 17) +#define PORT_P1_IN_P17_GET(val) ((((val) & PORT_P1_IN_P17) >> 17) & 0x1) +/* Port 1 Pin # Latched Input Value (16) */ +#define PORT_P1_IN_P16 (0x1 << 16) +#define PORT_P1_IN_P16_GET(val) ((((val) & PORT_P1_IN_P16) >> 16) & 0x1) +/* Port 1 Pin # Latched Input Value (15) */ +#define PORT_P1_IN_P15 (0x1 << 15) +#define PORT_P1_IN_P15_GET(val) ((((val) & PORT_P1_IN_P15) >> 15) & 0x1) +/* Port 1 Pin # Latched Input Value (14) */ +#define PORT_P1_IN_P14 (0x1 << 14) +#define PORT_P1_IN_P14_GET(val) ((((val) & PORT_P1_IN_P14) >> 14) & 0x1) +/* Port 1 Pin # Latched Input Value (13) */ +#define PORT_P1_IN_P13 (0x1 << 13) +#define PORT_P1_IN_P13_GET(val) ((((val) & PORT_P1_IN_P13) >> 13) & 0x1) +/* Port 1 Pin # Latched Input Value (12) */ +#define PORT_P1_IN_P12 (0x1 << 12) +#define PORT_P1_IN_P12_GET(val) ((((val) & PORT_P1_IN_P12) >> 12) & 0x1) +/* Port 1 Pin # Latched Input Value (11) */ +#define PORT_P1_IN_P11 (0x1 << 11) +#define PORT_P1_IN_P11_GET(val) ((((val) & PORT_P1_IN_P11) >> 11) & 0x1) +/* Port 1 Pin # Latched Input Value (10) */ +#define PORT_P1_IN_P10 (0x1 << 10) +#define PORT_P1_IN_P10_GET(val) ((((val) & PORT_P1_IN_P10) >> 10) & 0x1) +/* Port 1 Pin # Latched Input Value (9) */ +#define PORT_P1_IN_P9 (0x1 << 9) +#define PORT_P1_IN_P9_GET(val) ((((val) & PORT_P1_IN_P9) >> 9) & 0x1) +/* Port 1 Pin # Latched Input Value (8) */ +#define PORT_P1_IN_P8 (0x1 << 8) +#define PORT_P1_IN_P8_GET(val) ((((val) & PORT_P1_IN_P8) >> 8) & 0x1) +/* Port 1 Pin # Latched Input Value (7) */ +#define PORT_P1_IN_P7 (0x1 << 7) +#define PORT_P1_IN_P7_GET(val) ((((val) & PORT_P1_IN_P7) >> 7) & 0x1) +/* Port 1 Pin # Latched Input Value (6) */ +#define PORT_P1_IN_P6 (0x1 << 6) +#define PORT_P1_IN_P6_GET(val) ((((val) & PORT_P1_IN_P6) >> 6) & 0x1) +/* Port 1 Pin # Latched Input Value (5) */ +#define PORT_P1_IN_P5 (0x1 << 5) +#define PORT_P1_IN_P5_GET(val) ((((val) & PORT_P1_IN_P5) >> 5) & 0x1) +/* Port 1 Pin # Latched Input Value (4) */ +#define PORT_P1_IN_P4 (0x1 << 4) +#define PORT_P1_IN_P4_GET(val) ((((val) & PORT_P1_IN_P4) >> 4) & 0x1) +/* Port 1 Pin # Latched Input Value (3) */ +#define PORT_P1_IN_P3 (0x1 << 3) +#define PORT_P1_IN_P3_GET(val) ((((val) & PORT_P1_IN_P3) >> 3) & 0x1) +/* Port 1 Pin # Latched Input Value (2) */ +#define PORT_P1_IN_P2 (0x1 << 2) +#define PORT_P1_IN_P2_GET(val) ((((val) & PORT_P1_IN_P2) >> 2) & 0x1) +/* Port 1 Pin # Latched Input Value (1) */ +#define PORT_P1_IN_P1 (0x1 << 1) +#define PORT_P1_IN_P1_GET(val) ((((val) & PORT_P1_IN_P1) >> 1) & 0x1) +/* Port 1 Pin # Latched Input Value (0) */ +#define PORT_P1_IN_P0 (0x1) +#define PORT_P1_IN_P0_GET(val) ((((val) & PORT_P1_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 1 Direction Register + ******************************************************************************/ + +/* Port 1 Pin #Direction Control (19) */ +#define PORT_P1_DIR_P19 (0x1 << 19) +#define PORT_P1_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_DIR_P19_GET(val) ((((val) & PORT_P1_DIR_P19) >> 19) & 0x1) +#define PORT_P1_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 1 Pin #Direction Control (18) */ +#define PORT_P1_DIR_P18 (0x1 << 18) +#define PORT_P1_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_DIR_P18_GET(val) ((((val) & PORT_P1_DIR_P18) >> 18) & 0x1) +#define PORT_P1_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 1 Pin #Direction Control (17) */ +#define PORT_P1_DIR_P17 (0x1 << 17) +#define PORT_P1_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_DIR_P17_GET(val) ((((val) & PORT_P1_DIR_P17) >> 17) & 0x1) +#define PORT_P1_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 1 Pin #Direction Control (16) */ +#define PORT_P1_DIR_P16 (0x1 << 16) +#define PORT_P1_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_DIR_P16_GET(val) ((((val) & PORT_P1_DIR_P16) >> 16) & 0x1) +#define PORT_P1_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 1 Pin #Direction Control (15) */ +#define PORT_P1_DIR_P15 (0x1 << 15) +#define PORT_P1_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_DIR_P15_GET(val) ((((val) & PORT_P1_DIR_P15) >> 15) & 0x1) +#define PORT_P1_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 1 Pin #Direction Control (14) */ +#define PORT_P1_DIR_P14 (0x1 << 14) +#define PORT_P1_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_DIR_P14_GET(val) ((((val) & PORT_P1_DIR_P14) >> 14) & 0x1) +#define PORT_P1_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 1 Pin #Direction Control (13) */ +#define PORT_P1_DIR_P13 (0x1 << 13) +#define PORT_P1_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_DIR_P13_GET(val) ((((val) & PORT_P1_DIR_P13) >> 13) & 0x1) +#define PORT_P1_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 1 Pin #Direction Control (12) */ +#define PORT_P1_DIR_P12 (0x1 << 12) +#define PORT_P1_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_DIR_P12_GET(val) ((((val) & PORT_P1_DIR_P12) >> 12) & 0x1) +#define PORT_P1_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 1 Pin #Direction Control (11) */ +#define PORT_P1_DIR_P11 (0x1 << 11) +#define PORT_P1_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_DIR_P11_GET(val) ((((val) & PORT_P1_DIR_P11) >> 11) & 0x1) +#define PORT_P1_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 1 Pin #Direction Control (10) */ +#define PORT_P1_DIR_P10 (0x1 << 10) +#define PORT_P1_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_DIR_P10_GET(val) ((((val) & PORT_P1_DIR_P10) >> 10) & 0x1) +#define PORT_P1_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 1 Pin #Direction Control (9) */ +#define PORT_P1_DIR_P9 (0x1 << 9) +#define PORT_P1_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_DIR_P9_GET(val) ((((val) & PORT_P1_DIR_P9) >> 9) & 0x1) +#define PORT_P1_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 1 Pin #Direction Control (8) */ +#define PORT_P1_DIR_P8 (0x1 << 8) +#define PORT_P1_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_DIR_P8_GET(val) ((((val) & PORT_P1_DIR_P8) >> 8) & 0x1) +#define PORT_P1_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 1 Pin #Direction Control (7) */ +#define PORT_P1_DIR_P7 (0x1 << 7) +#define PORT_P1_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_DIR_P7_GET(val) ((((val) & PORT_P1_DIR_P7) >> 7) & 0x1) +#define PORT_P1_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 1 Pin #Direction Control (6) */ +#define PORT_P1_DIR_P6 (0x1 << 6) +#define PORT_P1_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_DIR_P6_GET(val) ((((val) & PORT_P1_DIR_P6) >> 6) & 0x1) +#define PORT_P1_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 1 Pin #Direction Control (5) */ +#define PORT_P1_DIR_P5 (0x1 << 5) +#define PORT_P1_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_DIR_P5_GET(val) ((((val) & PORT_P1_DIR_P5) >> 5) & 0x1) +#define PORT_P1_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 1 Pin #Direction Control (4) */ +#define PORT_P1_DIR_P4 (0x1 << 4) +#define PORT_P1_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_DIR_P4_GET(val) ((((val) & PORT_P1_DIR_P4) >> 4) & 0x1) +#define PORT_P1_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 1 Pin #Direction Control (3) */ +#define PORT_P1_DIR_P3 (0x1 << 3) +#define PORT_P1_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_DIR_P3_GET(val) ((((val) & PORT_P1_DIR_P3) >> 3) & 0x1) +#define PORT_P1_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 1 Pin #Direction Control (2) */ +#define PORT_P1_DIR_P2 (0x1 << 2) +#define PORT_P1_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_DIR_P2_GET(val) ((((val) & PORT_P1_DIR_P2) >> 2) & 0x1) +#define PORT_P1_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 1 Pin #Direction Control (1) */ +#define PORT_P1_DIR_P1 (0x1 << 1) +#define PORT_P1_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_DIR_P1_GET(val) ((((val) & PORT_P1_DIR_P1) >> 1) & 0x1) +#define PORT_P1_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 1 Pin #Direction Control (0) */ +#define PORT_P1_DIR_P0 (0x1) +#define PORT_P1_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_DIR_P0_GET(val) ((((val) & PORT_P1_DIR_P0) >> 0) & 0x1) +#define PORT_P1_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 1 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 1 Bit # (19) */ +#define PORT_P1_ALTSEL0_P19 (0x1 << 19) +#define PORT_P1_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_ALTSEL0_P19_GET(val) ((((val) & PORT_P1_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P1_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 1 Bit # (18) */ +#define PORT_P1_ALTSEL0_P18 (0x1 << 18) +#define PORT_P1_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_ALTSEL0_P18_GET(val) ((((val) & PORT_P1_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P1_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 1 Bit # (17) */ +#define PORT_P1_ALTSEL0_P17 (0x1 << 17) +#define PORT_P1_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_ALTSEL0_P17_GET(val) ((((val) & PORT_P1_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P1_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 1 Bit # (16) */ +#define PORT_P1_ALTSEL0_P16 (0x1 << 16) +#define PORT_P1_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_ALTSEL0_P16_GET(val) ((((val) & PORT_P1_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P1_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 1 Bit # (15) */ +#define PORT_P1_ALTSEL0_P15 (0x1 << 15) +#define PORT_P1_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_ALTSEL0_P15_GET(val) ((((val) & PORT_P1_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P1_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 1 Bit # (14) */ +#define PORT_P1_ALTSEL0_P14 (0x1 << 14) +#define PORT_P1_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_ALTSEL0_P14_GET(val) ((((val) & PORT_P1_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P1_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 1 Bit # (13) */ +#define PORT_P1_ALTSEL0_P13 (0x1 << 13) +#define PORT_P1_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_ALTSEL0_P13_GET(val) ((((val) & PORT_P1_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P1_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 1 Bit # (12) */ +#define PORT_P1_ALTSEL0_P12 (0x1 << 12) +#define PORT_P1_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_ALTSEL0_P12_GET(val) ((((val) & PORT_P1_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P1_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 1 Bit # (11) */ +#define PORT_P1_ALTSEL0_P11 (0x1 << 11) +#define PORT_P1_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_ALTSEL0_P11_GET(val) ((((val) & PORT_P1_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P1_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 1 Bit # (10) */ +#define PORT_P1_ALTSEL0_P10 (0x1 << 10) +#define PORT_P1_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_ALTSEL0_P10_GET(val) ((((val) & PORT_P1_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P1_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 1 Bit # (9) */ +#define PORT_P1_ALTSEL0_P9 (0x1 << 9) +#define PORT_P1_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_ALTSEL0_P9_GET(val) ((((val) & PORT_P1_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P1_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 1 Bit # (8) */ +#define PORT_P1_ALTSEL0_P8 (0x1 << 8) +#define PORT_P1_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_ALTSEL0_P8_GET(val) ((((val) & PORT_P1_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P1_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 1 Bit # (7) */ +#define PORT_P1_ALTSEL0_P7 (0x1 << 7) +#define PORT_P1_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_ALTSEL0_P7_GET(val) ((((val) & PORT_P1_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P1_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 1 Bit # (6) */ +#define PORT_P1_ALTSEL0_P6 (0x1 << 6) +#define PORT_P1_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_ALTSEL0_P6_GET(val) ((((val) & PORT_P1_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P1_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 1 Bit # (5) */ +#define PORT_P1_ALTSEL0_P5 (0x1 << 5) +#define PORT_P1_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_ALTSEL0_P5_GET(val) ((((val) & PORT_P1_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P1_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 1 Bit # (4) */ +#define PORT_P1_ALTSEL0_P4 (0x1 << 4) +#define PORT_P1_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_ALTSEL0_P4_GET(val) ((((val) & PORT_P1_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P1_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 1 Bit # (3) */ +#define PORT_P1_ALTSEL0_P3 (0x1 << 3) +#define PORT_P1_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_ALTSEL0_P3_GET(val) ((((val) & PORT_P1_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P1_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 1 Bit # (2) */ +#define PORT_P1_ALTSEL0_P2 (0x1 << 2) +#define PORT_P1_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_ALTSEL0_P2_GET(val) ((((val) & PORT_P1_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P1_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 1 Bit # (1) */ +#define PORT_P1_ALTSEL0_P1 (0x1 << 1) +#define PORT_P1_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_ALTSEL0_P1_GET(val) ((((val) & PORT_P1_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P1_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 1 Bit # (0) */ +#define PORT_P1_ALTSEL0_P0 (0x1) +#define PORT_P1_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_ALTSEL0_P0_GET(val) ((((val) & PORT_P1_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P1_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 1 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 1 Bit # (19) */ +#define PORT_P1_PUEN_P19 (0x1 << 19) +#define PORT_P1_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_PUEN_P19_GET(val) ((((val) & PORT_P1_PUEN_P19) >> 19) & 0x1) +#define PORT_P1_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 1 Bit # (18) */ +#define PORT_P1_PUEN_P18 (0x1 << 18) +#define PORT_P1_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_PUEN_P18_GET(val) ((((val) & PORT_P1_PUEN_P18) >> 18) & 0x1) +#define PORT_P1_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 1 Bit # (17) */ +#define PORT_P1_PUEN_P17 (0x1 << 17) +#define PORT_P1_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_PUEN_P17_GET(val) ((((val) & PORT_P1_PUEN_P17) >> 17) & 0x1) +#define PORT_P1_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 1 Bit # (16) */ +#define PORT_P1_PUEN_P16 (0x1 << 16) +#define PORT_P1_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_PUEN_P16_GET(val) ((((val) & PORT_P1_PUEN_P16) >> 16) & 0x1) +#define PORT_P1_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 1 Bit # (15) */ +#define PORT_P1_PUEN_P15 (0x1 << 15) +#define PORT_P1_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_PUEN_P15_GET(val) ((((val) & PORT_P1_PUEN_P15) >> 15) & 0x1) +#define PORT_P1_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 1 Bit # (14) */ +#define PORT_P1_PUEN_P14 (0x1 << 14) +#define PORT_P1_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_PUEN_P14_GET(val) ((((val) & PORT_P1_PUEN_P14) >> 14) & 0x1) +#define PORT_P1_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 1 Bit # (13) */ +#define PORT_P1_PUEN_P13 (0x1 << 13) +#define PORT_P1_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_PUEN_P13_GET(val) ((((val) & PORT_P1_PUEN_P13) >> 13) & 0x1) +#define PORT_P1_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 1 Bit # (12) */ +#define PORT_P1_PUEN_P12 (0x1 << 12) +#define PORT_P1_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_PUEN_P12_GET(val) ((((val) & PORT_P1_PUEN_P12) >> 12) & 0x1) +#define PORT_P1_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 1 Bit # (11) */ +#define PORT_P1_PUEN_P11 (0x1 << 11) +#define PORT_P1_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_PUEN_P11_GET(val) ((((val) & PORT_P1_PUEN_P11) >> 11) & 0x1) +#define PORT_P1_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 1 Bit # (10) */ +#define PORT_P1_PUEN_P10 (0x1 << 10) +#define PORT_P1_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_PUEN_P10_GET(val) ((((val) & PORT_P1_PUEN_P10) >> 10) & 0x1) +#define PORT_P1_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 1 Bit # (9) */ +#define PORT_P1_PUEN_P9 (0x1 << 9) +#define PORT_P1_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_PUEN_P9_GET(val) ((((val) & PORT_P1_PUEN_P9) >> 9) & 0x1) +#define PORT_P1_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 1 Bit # (8) */ +#define PORT_P1_PUEN_P8 (0x1 << 8) +#define PORT_P1_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_PUEN_P8_GET(val) ((((val) & PORT_P1_PUEN_P8) >> 8) & 0x1) +#define PORT_P1_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 1 Bit # (7) */ +#define PORT_P1_PUEN_P7 (0x1 << 7) +#define PORT_P1_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_PUEN_P7_GET(val) ((((val) & PORT_P1_PUEN_P7) >> 7) & 0x1) +#define PORT_P1_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 1 Bit # (6) */ +#define PORT_P1_PUEN_P6 (0x1 << 6) +#define PORT_P1_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_PUEN_P6_GET(val) ((((val) & PORT_P1_PUEN_P6) >> 6) & 0x1) +#define PORT_P1_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 1 Bit # (5) */ +#define PORT_P1_PUEN_P5 (0x1 << 5) +#define PORT_P1_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_PUEN_P5_GET(val) ((((val) & PORT_P1_PUEN_P5) >> 5) & 0x1) +#define PORT_P1_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 1 Bit # (4) */ +#define PORT_P1_PUEN_P4 (0x1 << 4) +#define PORT_P1_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_PUEN_P4_GET(val) ((((val) & PORT_P1_PUEN_P4) >> 4) & 0x1) +#define PORT_P1_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 1 Bit # (3) */ +#define PORT_P1_PUEN_P3 (0x1 << 3) +#define PORT_P1_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_PUEN_P3_GET(val) ((((val) & PORT_P1_PUEN_P3) >> 3) & 0x1) +#define PORT_P1_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 1 Bit # (2) */ +#define PORT_P1_PUEN_P2 (0x1 << 2) +#define PORT_P1_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_PUEN_P2_GET(val) ((((val) & PORT_P1_PUEN_P2) >> 2) & 0x1) +#define PORT_P1_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 1 Bit # (1) */ +#define PORT_P1_PUEN_P1 (0x1 << 1) +#define PORT_P1_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_PUEN_P1_GET(val) ((((val) & PORT_P1_PUEN_P1) >> 1) & 0x1) +#define PORT_P1_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 1 Bit # (0) */ +#define PORT_P1_PUEN_P0 (0x1) +#define PORT_P1_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_PUEN_P0_GET(val) ((((val) & PORT_P1_PUEN_P0) >> 0) & 0x1) +#define PORT_P1_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * External Interrupt Control Register 0 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT15 (19) */ +#define PORT_P1_EXINTCR0_EXINT15 (0x1 << 19) +#define PORT_P1_EXINTCR0_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_EXINTCR0_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT15) >> 19) & 0x1) +#define PORT_P1_EXINTCR0_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT15) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT11 (18) */ +#define PORT_P1_EXINTCR0_EXINT11 (0x1 << 18) +#define PORT_P1_EXINTCR0_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_EXINTCR0_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT11) >> 18) & 0x1) +#define PORT_P1_EXINTCR0_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT11) | (((val) & 0x1) << 18)) +/* Type of Level or Edge Detection of EXINT12 (17) */ +#define PORT_P1_EXINTCR0_EXINT12 (0x1 << 17) +#define PORT_P1_EXINTCR0_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_EXINTCR0_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT12) >> 17) & 0x1) +#define PORT_P1_EXINTCR0_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT12) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT13 (16) */ +#define PORT_P1_EXINTCR0_EXINT13 (0x1 << 16) +#define PORT_P1_EXINTCR0_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_EXINTCR0_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT13) >> 16) & 0x1) +#define PORT_P1_EXINTCR0_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT13) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT14 (15) */ +#define PORT_P1_EXINTCR0_EXINT14 (0x1 << 15) +#define PORT_P1_EXINTCR0_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_EXINTCR0_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT14) >> 15) & 0x1) +#define PORT_P1_EXINTCR0_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * External Interrupt Control Register 1 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT15 (19) */ +#define PORT_P1_EXINTCR1_EXINT15 (0x1 << 19) +#define PORT_P1_EXINTCR1_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_EXINTCR1_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT15) >> 19) & 0x1) +#define PORT_P1_EXINTCR1_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT15) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT11 (18) */ +#define PORT_P1_EXINTCR1_EXINT11 (0x1 << 18) +#define PORT_P1_EXINTCR1_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_EXINTCR1_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT11) >> 18) & 0x1) +#define PORT_P1_EXINTCR1_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT11) | (((val) & 0x1) << 18)) +/* Type of Level or Edge Detection of EXINT12 (17) */ +#define PORT_P1_EXINTCR1_EXINT12 (0x1 << 17) +#define PORT_P1_EXINTCR1_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_EXINTCR1_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT12) >> 17) & 0x1) +#define PORT_P1_EXINTCR1_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT12) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT13 (16) */ +#define PORT_P1_EXINTCR1_EXINT13 (0x1 << 16) +#define PORT_P1_EXINTCR1_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_EXINTCR1_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT13) >> 16) & 0x1) +#define PORT_P1_EXINTCR1_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT13) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT14 (15) */ +#define PORT_P1_EXINTCR1_EXINT14 (0x1 << 15) +#define PORT_P1_EXINTCR1_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_EXINTCR1_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT14) >> 15) & 0x1) +#define PORT_P1_EXINTCR1_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * P1_IRNEN Register + ******************************************************************************/ + +/* EXINT15 Interrupt Request Enable (19) */ +#define PORT_P1_IRNEN_EXINT15 (0x1 << 19) +#define PORT_P1_IRNEN_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNEN_EXINT15_GET(val) ((((val) & PORT_P1_IRNEN_EXINT15) >> 19) & 0x1) +#define PORT_P1_IRNEN_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT15) | (((val) & 0x1) << 19)) +/* EXINT11 Interrupt Request Enable (18) */ +#define PORT_P1_IRNEN_EXINT11 (0x1 << 18) +#define PORT_P1_IRNEN_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNEN_EXINT11_GET(val) ((((val) & PORT_P1_IRNEN_EXINT11) >> 18) & 0x1) +#define PORT_P1_IRNEN_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT11) | (((val) & 0x1) << 18)) +/* EXINT12 Interrupt Request Enable (17) */ +#define PORT_P1_IRNEN_EXINT12 (0x1 << 17) +#define PORT_P1_IRNEN_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNEN_EXINT12_GET(val) ((((val) & PORT_P1_IRNEN_EXINT12) >> 17) & 0x1) +#define PORT_P1_IRNEN_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT12) | (((val) & 0x1) << 17)) +/* EXINT13 Interrupt Request Enable (16) */ +#define PORT_P1_IRNEN_EXINT13 (0x1 << 16) +#define PORT_P1_IRNEN_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNEN_EXINT13_GET(val) ((((val) & PORT_P1_IRNEN_EXINT13) >> 16) & 0x1) +#define PORT_P1_IRNEN_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT13) | (((val) & 0x1) << 16)) +/* EXINT14 Interrupt Request Enable (15) */ +#define PORT_P1_IRNEN_EXINT14 (0x1 << 15) +#define PORT_P1_IRNEN_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNEN_EXINT14_GET(val) ((((val) & PORT_P1_IRNEN_EXINT14) >> 15) & 0x1) +#define PORT_P1_IRNEN_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * P1_IRNICR Register + ******************************************************************************/ + +/* EXINT15 Interrupt Request (19) */ +#define PORT_P1_IRNICR_EXINT15 (0x1 << 19) +#define PORT_P1_IRNICR_EXINT15_GET(val) ((((val) & PORT_P1_IRNICR_EXINT15) >> 19) & 0x1) +/* EXINT11 Interrupt Request (18) */ +#define PORT_P1_IRNICR_EXINT11 (0x1 << 18) +#define PORT_P1_IRNICR_EXINT11_GET(val) ((((val) & PORT_P1_IRNICR_EXINT11) >> 18) & 0x1) +/* EXINT12 Interrupt Request (17) */ +#define PORT_P1_IRNICR_EXINT12 (0x1 << 17) +#define PORT_P1_IRNICR_EXINT12_GET(val) ((((val) & PORT_P1_IRNICR_EXINT12) >> 17) & 0x1) +/* EXINT13 Interrupt Request (16) */ +#define PORT_P1_IRNICR_EXINT13 (0x1 << 16) +#define PORT_P1_IRNICR_EXINT13_GET(val) ((((val) & PORT_P1_IRNICR_EXINT13) >> 16) & 0x1) +/* EXINT14 Interrupt Request (15) */ +#define PORT_P1_IRNICR_EXINT14 (0x1 << 15) +#define PORT_P1_IRNICR_EXINT14_GET(val) ((((val) & PORT_P1_IRNICR_EXINT14) >> 15) & 0x1) + +/******************************************************************************* + * P1_IRNCR Register + ******************************************************************************/ + +/* EXINT15 Interrupt Request (19) */ +#define PORT_P1_IRNCR_EXINT15 (0x1 << 19) +#define PORT_P1_IRNCR_EXINT15_GET(val) ((((val) & PORT_P1_IRNCR_EXINT15) >> 19) & 0x1) +/* EXINT11 Interrupt Request (18) */ +#define PORT_P1_IRNCR_EXINT11 (0x1 << 18) +#define PORT_P1_IRNCR_EXINT11_GET(val) ((((val) & PORT_P1_IRNCR_EXINT11) >> 18) & 0x1) +/* EXINT12 Interrupt Request (17) */ +#define PORT_P1_IRNCR_EXINT12 (0x1 << 17) +#define PORT_P1_IRNCR_EXINT12_GET(val) ((((val) & PORT_P1_IRNCR_EXINT12) >> 17) & 0x1) +/* EXINT13 Interrupt Request (16) */ +#define PORT_P1_IRNCR_EXINT13 (0x1 << 16) +#define PORT_P1_IRNCR_EXINT13_GET(val) ((((val) & PORT_P1_IRNCR_EXINT13) >> 16) & 0x1) +/* EXINT14 Interrupt Request (15) */ +#define PORT_P1_IRNCR_EXINT14 (0x1 << 15) +#define PORT_P1_IRNCR_EXINT14_GET(val) ((((val) & PORT_P1_IRNCR_EXINT14) >> 15) & 0x1) + +/******************************************************************************* + * P1 External Event Detection Configuration Register + ******************************************************************************/ + +/* EXINT15 configured for Edge or Level Detection (19) */ +#define PORT_P1_IRNCFG_EXINT15 (0x1 << 19) +#define PORT_P1_IRNCFG_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNCFG_EXINT15_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT15) >> 19) & 0x1) +#define PORT_P1_IRNCFG_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT15) | (((val) & 0x1) << 19)) +/* EXINT11 configured for Edge or Level Detection (18) */ +#define PORT_P1_IRNCFG_EXINT11 (0x1 << 18) +#define PORT_P1_IRNCFG_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNCFG_EXINT11_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT11) >> 18) & 0x1) +#define PORT_P1_IRNCFG_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT11) | (((val) & 0x1) << 18)) +/* EXINT12 configured for Edge or Level Detection (17) */ +#define PORT_P1_IRNCFG_EXINT12 (0x1 << 17) +#define PORT_P1_IRNCFG_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNCFG_EXINT12_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT12) >> 17) & 0x1) +#define PORT_P1_IRNCFG_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT12) | (((val) & 0x1) << 17)) +/* EXINT13 configured for Edge or Level Detection (16) */ +#define PORT_P1_IRNCFG_EXINT13 (0x1 << 16) +#define PORT_P1_IRNCFG_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNCFG_EXINT13_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT13) >> 16) & 0x1) +#define PORT_P1_IRNCFG_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT13) | (((val) & 0x1) << 16)) +/* EXINT14 configured for Edge or Level Detection (15) */ +#define PORT_P1_IRNCFG_EXINT14 (0x1 << 15) +#define PORT_P1_IRNCFG_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNCFG_EXINT14_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT14) >> 15) & 0x1) +#define PORT_P1_IRNCFG_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * P1_IRNENSET Register + ******************************************************************************/ + +/* Set Interrupt Node Enable Flag EXINT15 (19) */ +#define PORT_P1_IRNENSET_EXINT15 (0x1 << 19) +#define PORT_P1_IRNENSET_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNENSET_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT15) | (val) & 1) << 19) +/* Set Interrupt Node Enable Flag EXINT11 (18) */ +#define PORT_P1_IRNENSET_EXINT11 (0x1 << 18) +#define PORT_P1_IRNENSET_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNENSET_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT11) | (val) & 1) << 18) +/* Set Interrupt Node Enable Flag EXINT12 (17) */ +#define PORT_P1_IRNENSET_EXINT12 (0x1 << 17) +#define PORT_P1_IRNENSET_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNENSET_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT12) | (val) & 1) << 17) +/* Set Interrupt Node Enable Flag EXINT13 (16) */ +#define PORT_P1_IRNENSET_EXINT13 (0x1 << 16) +#define PORT_P1_IRNENSET_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNENSET_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT13) | (val) & 1) << 16) +/* Set Interrupt Node Enable Flag EXINT14 (15) */ +#define PORT_P1_IRNENSET_EXINT14 (0x1 << 15) +#define PORT_P1_IRNENSET_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNENSET_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT14) | (val) & 1) << 15) + +/******************************************************************************* + * P1_IRNENCLR Register + ******************************************************************************/ + +/* Clear Interrupt Node Enable Flag EXINT15 (19) */ +#define PORT_P1_IRNENCLR_EXINT15 (0x1 << 19) +#define PORT_P1_IRNENCLR_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNENCLR_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT15) | (val) & 1) << 19) +/* Clear Interrupt Node Enable Flag EXINT11 (18) */ +#define PORT_P1_IRNENCLR_EXINT11 (0x1 << 18) +#define PORT_P1_IRNENCLR_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNENCLR_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT11) | (val) & 1) << 18) +/* Clear Interrupt Node Enable Flag EXINT12 (17) */ +#define PORT_P1_IRNENCLR_EXINT12 (0x1 << 17) +#define PORT_P1_IRNENCLR_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNENCLR_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT12) | (val) & 1) << 17) +/* Clear Interrupt Node Enable Flag EXINT13 (16) */ +#define PORT_P1_IRNENCLR_EXINT13 (0x1 << 16) +#define PORT_P1_IRNENCLR_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNENCLR_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT13) | (val) & 1) << 16) +/* Clear Interrupt Node Enable Flag EXINT14 (15) */ +#define PORT_P1_IRNENCLR_EXINT14 (0x1 << 15) +#define PORT_P1_IRNENCLR_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNENCLR_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT14) | (val) & 1) << 15) + +/******************************************************************************* + * Port 2 Data Output Register + ******************************************************************************/ + +/* Port 2 Pin # Output Value (19) */ +#define PORT_P2_OUT_P19 (0x1 << 19) +#define PORT_P2_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_OUT_P19_GET(val) ((((val) & PORT_P2_OUT_P19) >> 19) & 0x1) +#define PORT_P2_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 2 Pin # Output Value (18) */ +#define PORT_P2_OUT_P18 (0x1 << 18) +#define PORT_P2_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_OUT_P18_GET(val) ((((val) & PORT_P2_OUT_P18) >> 18) & 0x1) +#define PORT_P2_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 2 Pin # Output Value (17) */ +#define PORT_P2_OUT_P17 (0x1 << 17) +#define PORT_P2_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_OUT_P17_GET(val) ((((val) & PORT_P2_OUT_P17) >> 17) & 0x1) +#define PORT_P2_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 2 Pin # Output Value (16) */ +#define PORT_P2_OUT_P16 (0x1 << 16) +#define PORT_P2_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_OUT_P16_GET(val) ((((val) & PORT_P2_OUT_P16) >> 16) & 0x1) +#define PORT_P2_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 2 Pin # Output Value (15) */ +#define PORT_P2_OUT_P15 (0x1 << 15) +#define PORT_P2_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_OUT_P15_GET(val) ((((val) & PORT_P2_OUT_P15) >> 15) & 0x1) +#define PORT_P2_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 2 Pin # Output Value (14) */ +#define PORT_P2_OUT_P14 (0x1 << 14) +#define PORT_P2_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_OUT_P14_GET(val) ((((val) & PORT_P2_OUT_P14) >> 14) & 0x1) +#define PORT_P2_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 2 Pin # Output Value (13) */ +#define PORT_P2_OUT_P13 (0x1 << 13) +#define PORT_P2_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_OUT_P13_GET(val) ((((val) & PORT_P2_OUT_P13) >> 13) & 0x1) +#define PORT_P2_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 2 Pin # Output Value (12) */ +#define PORT_P2_OUT_P12 (0x1 << 12) +#define PORT_P2_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_OUT_P12_GET(val) ((((val) & PORT_P2_OUT_P12) >> 12) & 0x1) +#define PORT_P2_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 2 Pin # Output Value (11) */ +#define PORT_P2_OUT_P11 (0x1 << 11) +#define PORT_P2_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_OUT_P11_GET(val) ((((val) & PORT_P2_OUT_P11) >> 11) & 0x1) +#define PORT_P2_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 2 Pin # Output Value (10) */ +#define PORT_P2_OUT_P10 (0x1 << 10) +#define PORT_P2_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_OUT_P10_GET(val) ((((val) & PORT_P2_OUT_P10) >> 10) & 0x1) +#define PORT_P2_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 2 Pin # Output Value (9) */ +#define PORT_P2_OUT_P9 (0x1 << 9) +#define PORT_P2_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_OUT_P9_GET(val) ((((val) & PORT_P2_OUT_P9) >> 9) & 0x1) +#define PORT_P2_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 2 Pin # Output Value (8) */ +#define PORT_P2_OUT_P8 (0x1 << 8) +#define PORT_P2_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_OUT_P8_GET(val) ((((val) & PORT_P2_OUT_P8) >> 8) & 0x1) +#define PORT_P2_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 2 Pin # Output Value (7) */ +#define PORT_P2_OUT_P7 (0x1 << 7) +#define PORT_P2_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_OUT_P7_GET(val) ((((val) & PORT_P2_OUT_P7) >> 7) & 0x1) +#define PORT_P2_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 2 Pin # Output Value (6) */ +#define PORT_P2_OUT_P6 (0x1 << 6) +#define PORT_P2_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_OUT_P6_GET(val) ((((val) & PORT_P2_OUT_P6) >> 6) & 0x1) +#define PORT_P2_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 2 Pin # Output Value (5) */ +#define PORT_P2_OUT_P5 (0x1 << 5) +#define PORT_P2_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_OUT_P5_GET(val) ((((val) & PORT_P2_OUT_P5) >> 5) & 0x1) +#define PORT_P2_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 2 Pin # Output Value (4) */ +#define PORT_P2_OUT_P4 (0x1 << 4) +#define PORT_P2_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_OUT_P4_GET(val) ((((val) & PORT_P2_OUT_P4) >> 4) & 0x1) +#define PORT_P2_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 2 Pin # Output Value (3) */ +#define PORT_P2_OUT_P3 (0x1 << 3) +#define PORT_P2_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_OUT_P3_GET(val) ((((val) & PORT_P2_OUT_P3) >> 3) & 0x1) +#define PORT_P2_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 2 Pin # Output Value (2) */ +#define PORT_P2_OUT_P2 (0x1 << 2) +#define PORT_P2_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_OUT_P2_GET(val) ((((val) & PORT_P2_OUT_P2) >> 2) & 0x1) +#define PORT_P2_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 2 Pin # Output Value (1) */ +#define PORT_P2_OUT_P1 (0x1 << 1) +#define PORT_P2_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_OUT_P1_GET(val) ((((val) & PORT_P2_OUT_P1) >> 1) & 0x1) +#define PORT_P2_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 2 Pin # Output Value (0) */ +#define PORT_P2_OUT_P0 (0x1) +#define PORT_P2_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_OUT_P0_GET(val) ((((val) & PORT_P2_OUT_P0) >> 0) & 0x1) +#define PORT_P2_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 2 Data Input Register + ******************************************************************************/ + +/* Port 2 Pin # Latched Input Value (19) */ +#define PORT_P2_IN_P19 (0x1 << 19) +#define PORT_P2_IN_P19_GET(val) ((((val) & PORT_P2_IN_P19) >> 19) & 0x1) +/* Port 2 Pin # Latched Input Value (18) */ +#define PORT_P2_IN_P18 (0x1 << 18) +#define PORT_P2_IN_P18_GET(val) ((((val) & PORT_P2_IN_P18) >> 18) & 0x1) +/* Port 2 Pin # Latched Input Value (17) */ +#define PORT_P2_IN_P17 (0x1 << 17) +#define PORT_P2_IN_P17_GET(val) ((((val) & PORT_P2_IN_P17) >> 17) & 0x1) +/* Port 2 Pin # Latched Input Value (16) */ +#define PORT_P2_IN_P16 (0x1 << 16) +#define PORT_P2_IN_P16_GET(val) ((((val) & PORT_P2_IN_P16) >> 16) & 0x1) +/* Port 2 Pin # Latched Input Value (15) */ +#define PORT_P2_IN_P15 (0x1 << 15) +#define PORT_P2_IN_P15_GET(val) ((((val) & PORT_P2_IN_P15) >> 15) & 0x1) +/* Port 2 Pin # Latched Input Value (14) */ +#define PORT_P2_IN_P14 (0x1 << 14) +#define PORT_P2_IN_P14_GET(val) ((((val) & PORT_P2_IN_P14) >> 14) & 0x1) +/* Port 2 Pin # Latched Input Value (13) */ +#define PORT_P2_IN_P13 (0x1 << 13) +#define PORT_P2_IN_P13_GET(val) ((((val) & PORT_P2_IN_P13) >> 13) & 0x1) +/* Port 2 Pin # Latched Input Value (12) */ +#define PORT_P2_IN_P12 (0x1 << 12) +#define PORT_P2_IN_P12_GET(val) ((((val) & PORT_P2_IN_P12) >> 12) & 0x1) +/* Port 2 Pin # Latched Input Value (11) */ +#define PORT_P2_IN_P11 (0x1 << 11) +#define PORT_P2_IN_P11_GET(val) ((((val) & PORT_P2_IN_P11) >> 11) & 0x1) +/* Port 2 Pin # Latched Input Value (10) */ +#define PORT_P2_IN_P10 (0x1 << 10) +#define PORT_P2_IN_P10_GET(val) ((((val) & PORT_P2_IN_P10) >> 10) & 0x1) +/* Port 2 Pin # Latched Input Value (9) */ +#define PORT_P2_IN_P9 (0x1 << 9) +#define PORT_P2_IN_P9_GET(val) ((((val) & PORT_P2_IN_P9) >> 9) & 0x1) +/* Port 2 Pin # Latched Input Value (8) */ +#define PORT_P2_IN_P8 (0x1 << 8) +#define PORT_P2_IN_P8_GET(val) ((((val) & PORT_P2_IN_P8) >> 8) & 0x1) +/* Port 2 Pin # Latched Input Value (7) */ +#define PORT_P2_IN_P7 (0x1 << 7) +#define PORT_P2_IN_P7_GET(val) ((((val) & PORT_P2_IN_P7) >> 7) & 0x1) +/* Port 2 Pin # Latched Input Value (6) */ +#define PORT_P2_IN_P6 (0x1 << 6) +#define PORT_P2_IN_P6_GET(val) ((((val) & PORT_P2_IN_P6) >> 6) & 0x1) +/* Port 2 Pin # Latched Input Value (5) */ +#define PORT_P2_IN_P5 (0x1 << 5) +#define PORT_P2_IN_P5_GET(val) ((((val) & PORT_P2_IN_P5) >> 5) & 0x1) +/* Port 2 Pin # Latched Input Value (4) */ +#define PORT_P2_IN_P4 (0x1 << 4) +#define PORT_P2_IN_P4_GET(val) ((((val) & PORT_P2_IN_P4) >> 4) & 0x1) +/* Port 2 Pin # Latched Input Value (3) */ +#define PORT_P2_IN_P3 (0x1 << 3) +#define PORT_P2_IN_P3_GET(val) ((((val) & PORT_P2_IN_P3) >> 3) & 0x1) +/* Port 2 Pin # Latched Input Value (2) */ +#define PORT_P2_IN_P2 (0x1 << 2) +#define PORT_P2_IN_P2_GET(val) ((((val) & PORT_P2_IN_P2) >> 2) & 0x1) +/* Port 2 Pin # Latched Input Value (1) */ +#define PORT_P2_IN_P1 (0x1 << 1) +#define PORT_P2_IN_P1_GET(val) ((((val) & PORT_P2_IN_P1) >> 1) & 0x1) +/* Port 2 Pin # Latched Input Value (0) */ +#define PORT_P2_IN_P0 (0x1) +#define PORT_P2_IN_P0_GET(val) ((((val) & PORT_P2_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 2 Direction Register + ******************************************************************************/ + +/* Port 2 Pin #Direction Control (19) */ +#define PORT_P2_DIR_P19 (0x1 << 19) +#define PORT_P2_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_DIR_P19_GET(val) ((((val) & PORT_P2_DIR_P19) >> 19) & 0x1) +#define PORT_P2_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 2 Pin #Direction Control (18) */ +#define PORT_P2_DIR_P18 (0x1 << 18) +#define PORT_P2_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_DIR_P18_GET(val) ((((val) & PORT_P2_DIR_P18) >> 18) & 0x1) +#define PORT_P2_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 2 Pin #Direction Control (17) */ +#define PORT_P2_DIR_P17 (0x1 << 17) +#define PORT_P2_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_DIR_P17_GET(val) ((((val) & PORT_P2_DIR_P17) >> 17) & 0x1) +#define PORT_P2_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 2 Pin #Direction Control (16) */ +#define PORT_P2_DIR_P16 (0x1 << 16) +#define PORT_P2_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_DIR_P16_GET(val) ((((val) & PORT_P2_DIR_P16) >> 16) & 0x1) +#define PORT_P2_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 2 Pin #Direction Control (15) */ +#define PORT_P2_DIR_P15 (0x1 << 15) +#define PORT_P2_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_DIR_P15_GET(val) ((((val) & PORT_P2_DIR_P15) >> 15) & 0x1) +#define PORT_P2_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 2 Pin #Direction Control (14) */ +#define PORT_P2_DIR_P14 (0x1 << 14) +#define PORT_P2_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_DIR_P14_GET(val) ((((val) & PORT_P2_DIR_P14) >> 14) & 0x1) +#define PORT_P2_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 2 Pin #Direction Control (13) */ +#define PORT_P2_DIR_P13 (0x1 << 13) +#define PORT_P2_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_DIR_P13_GET(val) ((((val) & PORT_P2_DIR_P13) >> 13) & 0x1) +#define PORT_P2_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 2 Pin #Direction Control (12) */ +#define PORT_P2_DIR_P12 (0x1 << 12) +#define PORT_P2_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_DIR_P12_GET(val) ((((val) & PORT_P2_DIR_P12) >> 12) & 0x1) +#define PORT_P2_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 2 Pin #Direction Control (11) */ +#define PORT_P2_DIR_P11 (0x1 << 11) +#define PORT_P2_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_DIR_P11_GET(val) ((((val) & PORT_P2_DIR_P11) >> 11) & 0x1) +#define PORT_P2_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 2 Pin #Direction Control (10) */ +#define PORT_P2_DIR_P10 (0x1 << 10) +#define PORT_P2_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_DIR_P10_GET(val) ((((val) & PORT_P2_DIR_P10) >> 10) & 0x1) +#define PORT_P2_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 2 Pin #Direction Control (9) */ +#define PORT_P2_DIR_P9 (0x1 << 9) +#define PORT_P2_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_DIR_P9_GET(val) ((((val) & PORT_P2_DIR_P9) >> 9) & 0x1) +#define PORT_P2_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 2 Pin #Direction Control (8) */ +#define PORT_P2_DIR_P8 (0x1 << 8) +#define PORT_P2_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_DIR_P8_GET(val) ((((val) & PORT_P2_DIR_P8) >> 8) & 0x1) +#define PORT_P2_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 2 Pin #Direction Control (7) */ +#define PORT_P2_DIR_P7 (0x1 << 7) +#define PORT_P2_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_DIR_P7_GET(val) ((((val) & PORT_P2_DIR_P7) >> 7) & 0x1) +#define PORT_P2_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 2 Pin #Direction Control (6) */ +#define PORT_P2_DIR_P6 (0x1 << 6) +#define PORT_P2_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_DIR_P6_GET(val) ((((val) & PORT_P2_DIR_P6) >> 6) & 0x1) +#define PORT_P2_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 2 Pin #Direction Control (5) */ +#define PORT_P2_DIR_P5 (0x1 << 5) +#define PORT_P2_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_DIR_P5_GET(val) ((((val) & PORT_P2_DIR_P5) >> 5) & 0x1) +#define PORT_P2_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 2 Pin #Direction Control (4) */ +#define PORT_P2_DIR_P4 (0x1 << 4) +#define PORT_P2_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_DIR_P4_GET(val) ((((val) & PORT_P2_DIR_P4) >> 4) & 0x1) +#define PORT_P2_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 2 Pin #Direction Control (3) */ +#define PORT_P2_DIR_P3 (0x1 << 3) +#define PORT_P2_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_DIR_P3_GET(val) ((((val) & PORT_P2_DIR_P3) >> 3) & 0x1) +#define PORT_P2_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 2 Pin #Direction Control (2) */ +#define PORT_P2_DIR_P2 (0x1 << 2) +#define PORT_P2_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_DIR_P2_GET(val) ((((val) & PORT_P2_DIR_P2) >> 2) & 0x1) +#define PORT_P2_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 2 Pin #Direction Control (1) */ +#define PORT_P2_DIR_P1 (0x1 << 1) +#define PORT_P2_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_DIR_P1_GET(val) ((((val) & PORT_P2_DIR_P1) >> 1) & 0x1) +#define PORT_P2_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 2 Pin #Direction Control (0) */ +#define PORT_P2_DIR_P0 (0x1) +#define PORT_P2_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_DIR_P0_GET(val) ((((val) & PORT_P2_DIR_P0) >> 0) & 0x1) +#define PORT_P2_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 2 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 2 Bit # (19) */ +#define PORT_P2_ALTSEL0_P19 (0x1 << 19) +#define PORT_P2_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_ALTSEL0_P19_GET(val) ((((val) & PORT_P2_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P2_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 2 Bit # (18) */ +#define PORT_P2_ALTSEL0_P18 (0x1 << 18) +#define PORT_P2_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_ALTSEL0_P18_GET(val) ((((val) & PORT_P2_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P2_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 2 Bit # (17) */ +#define PORT_P2_ALTSEL0_P17 (0x1 << 17) +#define PORT_P2_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_ALTSEL0_P17_GET(val) ((((val) & PORT_P2_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P2_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 2 Bit # (16) */ +#define PORT_P2_ALTSEL0_P16 (0x1 << 16) +#define PORT_P2_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_ALTSEL0_P16_GET(val) ((((val) & PORT_P2_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P2_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 2 Bit # (15) */ +#define PORT_P2_ALTSEL0_P15 (0x1 << 15) +#define PORT_P2_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_ALTSEL0_P15_GET(val) ((((val) & PORT_P2_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P2_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 2 Bit # (14) */ +#define PORT_P2_ALTSEL0_P14 (0x1 << 14) +#define PORT_P2_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_ALTSEL0_P14_GET(val) ((((val) & PORT_P2_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P2_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 2 Bit # (13) */ +#define PORT_P2_ALTSEL0_P13 (0x1 << 13) +#define PORT_P2_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_ALTSEL0_P13_GET(val) ((((val) & PORT_P2_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P2_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 2 Bit # (12) */ +#define PORT_P2_ALTSEL0_P12 (0x1 << 12) +#define PORT_P2_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_ALTSEL0_P12_GET(val) ((((val) & PORT_P2_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P2_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 2 Bit # (11) */ +#define PORT_P2_ALTSEL0_P11 (0x1 << 11) +#define PORT_P2_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_ALTSEL0_P11_GET(val) ((((val) & PORT_P2_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P2_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 2 Bit # (10) */ +#define PORT_P2_ALTSEL0_P10 (0x1 << 10) +#define PORT_P2_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_ALTSEL0_P10_GET(val) ((((val) & PORT_P2_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P2_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 2 Bit # (9) */ +#define PORT_P2_ALTSEL0_P9 (0x1 << 9) +#define PORT_P2_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_ALTSEL0_P9_GET(val) ((((val) & PORT_P2_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P2_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 2 Bit # (8) */ +#define PORT_P2_ALTSEL0_P8 (0x1 << 8) +#define PORT_P2_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_ALTSEL0_P8_GET(val) ((((val) & PORT_P2_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P2_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 2 Bit # (7) */ +#define PORT_P2_ALTSEL0_P7 (0x1 << 7) +#define PORT_P2_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_ALTSEL0_P7_GET(val) ((((val) & PORT_P2_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P2_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 2 Bit # (6) */ +#define PORT_P2_ALTSEL0_P6 (0x1 << 6) +#define PORT_P2_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_ALTSEL0_P6_GET(val) ((((val) & PORT_P2_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P2_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 2 Bit # (5) */ +#define PORT_P2_ALTSEL0_P5 (0x1 << 5) +#define PORT_P2_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_ALTSEL0_P5_GET(val) ((((val) & PORT_P2_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P2_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 2 Bit # (4) */ +#define PORT_P2_ALTSEL0_P4 (0x1 << 4) +#define PORT_P2_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_ALTSEL0_P4_GET(val) ((((val) & PORT_P2_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P2_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 2 Bit # (3) */ +#define PORT_P2_ALTSEL0_P3 (0x1 << 3) +#define PORT_P2_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_ALTSEL0_P3_GET(val) ((((val) & PORT_P2_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P2_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 2 Bit # (2) */ +#define PORT_P2_ALTSEL0_P2 (0x1 << 2) +#define PORT_P2_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_ALTSEL0_P2_GET(val) ((((val) & PORT_P2_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P2_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 2 Bit # (1) */ +#define PORT_P2_ALTSEL0_P1 (0x1 << 1) +#define PORT_P2_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_ALTSEL0_P1_GET(val) ((((val) & PORT_P2_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P2_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 2 Bit # (0) */ +#define PORT_P2_ALTSEL0_P0 (0x1) +#define PORT_P2_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_ALTSEL0_P0_GET(val) ((((val) & PORT_P2_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P2_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 2 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 2 Bit # (19) */ +#define PORT_P2_PUEN_P19 (0x1 << 19) +#define PORT_P2_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_PUEN_P19_GET(val) ((((val) & PORT_P2_PUEN_P19) >> 19) & 0x1) +#define PORT_P2_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 2 Bit # (18) */ +#define PORT_P2_PUEN_P18 (0x1 << 18) +#define PORT_P2_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_PUEN_P18_GET(val) ((((val) & PORT_P2_PUEN_P18) >> 18) & 0x1) +#define PORT_P2_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 2 Bit # (17) */ +#define PORT_P2_PUEN_P17 (0x1 << 17) +#define PORT_P2_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_PUEN_P17_GET(val) ((((val) & PORT_P2_PUEN_P17) >> 17) & 0x1) +#define PORT_P2_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 2 Bit # (16) */ +#define PORT_P2_PUEN_P16 (0x1 << 16) +#define PORT_P2_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_PUEN_P16_GET(val) ((((val) & PORT_P2_PUEN_P16) >> 16) & 0x1) +#define PORT_P2_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 2 Bit # (15) */ +#define PORT_P2_PUEN_P15 (0x1 << 15) +#define PORT_P2_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_PUEN_P15_GET(val) ((((val) & PORT_P2_PUEN_P15) >> 15) & 0x1) +#define PORT_P2_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 2 Bit # (14) */ +#define PORT_P2_PUEN_P14 (0x1 << 14) +#define PORT_P2_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_PUEN_P14_GET(val) ((((val) & PORT_P2_PUEN_P14) >> 14) & 0x1) +#define PORT_P2_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 2 Bit # (13) */ +#define PORT_P2_PUEN_P13 (0x1 << 13) +#define PORT_P2_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_PUEN_P13_GET(val) ((((val) & PORT_P2_PUEN_P13) >> 13) & 0x1) +#define PORT_P2_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 2 Bit # (12) */ +#define PORT_P2_PUEN_P12 (0x1 << 12) +#define PORT_P2_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_PUEN_P12_GET(val) ((((val) & PORT_P2_PUEN_P12) >> 12) & 0x1) +#define PORT_P2_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 2 Bit # (11) */ +#define PORT_P2_PUEN_P11 (0x1 << 11) +#define PORT_P2_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_PUEN_P11_GET(val) ((((val) & PORT_P2_PUEN_P11) >> 11) & 0x1) +#define PORT_P2_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 2 Bit # (10) */ +#define PORT_P2_PUEN_P10 (0x1 << 10) +#define PORT_P2_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_PUEN_P10_GET(val) ((((val) & PORT_P2_PUEN_P10) >> 10) & 0x1) +#define PORT_P2_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 2 Bit # (9) */ +#define PORT_P2_PUEN_P9 (0x1 << 9) +#define PORT_P2_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_PUEN_P9_GET(val) ((((val) & PORT_P2_PUEN_P9) >> 9) & 0x1) +#define PORT_P2_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 2 Bit # (8) */ +#define PORT_P2_PUEN_P8 (0x1 << 8) +#define PORT_P2_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_PUEN_P8_GET(val) ((((val) & PORT_P2_PUEN_P8) >> 8) & 0x1) +#define PORT_P2_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 2 Bit # (7) */ +#define PORT_P2_PUEN_P7 (0x1 << 7) +#define PORT_P2_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_PUEN_P7_GET(val) ((((val) & PORT_P2_PUEN_P7) >> 7) & 0x1) +#define PORT_P2_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 2 Bit # (6) */ +#define PORT_P2_PUEN_P6 (0x1 << 6) +#define PORT_P2_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_PUEN_P6_GET(val) ((((val) & PORT_P2_PUEN_P6) >> 6) & 0x1) +#define PORT_P2_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 2 Bit # (5) */ +#define PORT_P2_PUEN_P5 (0x1 << 5) +#define PORT_P2_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_PUEN_P5_GET(val) ((((val) & PORT_P2_PUEN_P5) >> 5) & 0x1) +#define PORT_P2_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 2 Bit # (4) */ +#define PORT_P2_PUEN_P4 (0x1 << 4) +#define PORT_P2_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_PUEN_P4_GET(val) ((((val) & PORT_P2_PUEN_P4) >> 4) & 0x1) +#define PORT_P2_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 2 Bit # (3) */ +#define PORT_P2_PUEN_P3 (0x1 << 3) +#define PORT_P2_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_PUEN_P3_GET(val) ((((val) & PORT_P2_PUEN_P3) >> 3) & 0x1) +#define PORT_P2_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 2 Bit # (2) */ +#define PORT_P2_PUEN_P2 (0x1 << 2) +#define PORT_P2_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_PUEN_P2_GET(val) ((((val) & PORT_P2_PUEN_P2) >> 2) & 0x1) +#define PORT_P2_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 2 Bit # (1) */ +#define PORT_P2_PUEN_P1 (0x1 << 1) +#define PORT_P2_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_PUEN_P1_GET(val) ((((val) & PORT_P2_PUEN_P1) >> 1) & 0x1) +#define PORT_P2_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 2 Bit # (0) */ +#define PORT_P2_PUEN_P0 (0x1) +#define PORT_P2_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_PUEN_P0_GET(val) ((((val) & PORT_P2_PUEN_P0) >> 0) & 0x1) +#define PORT_P2_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Data Output Register + ******************************************************************************/ + +/* Port 3 Pin # Output Value (19) */ +#define PORT_P3_OUT_P19 (0x1 << 19) +#define PORT_P3_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_OUT_P19_GET(val) ((((val) & PORT_P3_OUT_P19) >> 19) & 0x1) +#define PORT_P3_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 3 Pin # Output Value (18) */ +#define PORT_P3_OUT_P18 (0x1 << 18) +#define PORT_P3_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_OUT_P18_GET(val) ((((val) & PORT_P3_OUT_P18) >> 18) & 0x1) +#define PORT_P3_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 3 Pin # Output Value (17) */ +#define PORT_P3_OUT_P17 (0x1 << 17) +#define PORT_P3_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_OUT_P17_GET(val) ((((val) & PORT_P3_OUT_P17) >> 17) & 0x1) +#define PORT_P3_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 3 Pin # Output Value (16) */ +#define PORT_P3_OUT_P16 (0x1 << 16) +#define PORT_P3_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_OUT_P16_GET(val) ((((val) & PORT_P3_OUT_P16) >> 16) & 0x1) +#define PORT_P3_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 3 Pin # Output Value (15) */ +#define PORT_P3_OUT_P15 (0x1 << 15) +#define PORT_P3_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_OUT_P15_GET(val) ((((val) & PORT_P3_OUT_P15) >> 15) & 0x1) +#define PORT_P3_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 3 Pin # Output Value (14) */ +#define PORT_P3_OUT_P14 (0x1 << 14) +#define PORT_P3_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_OUT_P14_GET(val) ((((val) & PORT_P3_OUT_P14) >> 14) & 0x1) +#define PORT_P3_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 3 Pin # Output Value (13) */ +#define PORT_P3_OUT_P13 (0x1 << 13) +#define PORT_P3_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_OUT_P13_GET(val) ((((val) & PORT_P3_OUT_P13) >> 13) & 0x1) +#define PORT_P3_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 3 Pin # Output Value (12) */ +#define PORT_P3_OUT_P12 (0x1 << 12) +#define PORT_P3_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_OUT_P12_GET(val) ((((val) & PORT_P3_OUT_P12) >> 12) & 0x1) +#define PORT_P3_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 3 Pin # Output Value (11) */ +#define PORT_P3_OUT_P11 (0x1 << 11) +#define PORT_P3_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_OUT_P11_GET(val) ((((val) & PORT_P3_OUT_P11) >> 11) & 0x1) +#define PORT_P3_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 3 Pin # Output Value (10) */ +#define PORT_P3_OUT_P10 (0x1 << 10) +#define PORT_P3_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_OUT_P10_GET(val) ((((val) & PORT_P3_OUT_P10) >> 10) & 0x1) +#define PORT_P3_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 3 Pin # Output Value (9) */ +#define PORT_P3_OUT_P9 (0x1 << 9) +#define PORT_P3_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_OUT_P9_GET(val) ((((val) & PORT_P3_OUT_P9) >> 9) & 0x1) +#define PORT_P3_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 3 Pin # Output Value (8) */ +#define PORT_P3_OUT_P8 (0x1 << 8) +#define PORT_P3_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_OUT_P8_GET(val) ((((val) & PORT_P3_OUT_P8) >> 8) & 0x1) +#define PORT_P3_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 3 Pin # Output Value (7) */ +#define PORT_P3_OUT_P7 (0x1 << 7) +#define PORT_P3_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_OUT_P7_GET(val) ((((val) & PORT_P3_OUT_P7) >> 7) & 0x1) +#define PORT_P3_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 3 Pin # Output Value (6) */ +#define PORT_P3_OUT_P6 (0x1 << 6) +#define PORT_P3_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_OUT_P6_GET(val) ((((val) & PORT_P3_OUT_P6) >> 6) & 0x1) +#define PORT_P3_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 3 Pin # Output Value (5) */ +#define PORT_P3_OUT_P5 (0x1 << 5) +#define PORT_P3_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_OUT_P5_GET(val) ((((val) & PORT_P3_OUT_P5) >> 5) & 0x1) +#define PORT_P3_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 3 Pin # Output Value (4) */ +#define PORT_P3_OUT_P4 (0x1 << 4) +#define PORT_P3_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_OUT_P4_GET(val) ((((val) & PORT_P3_OUT_P4) >> 4) & 0x1) +#define PORT_P3_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 3 Pin # Output Value (3) */ +#define PORT_P3_OUT_P3 (0x1 << 3) +#define PORT_P3_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_OUT_P3_GET(val) ((((val) & PORT_P3_OUT_P3) >> 3) & 0x1) +#define PORT_P3_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 3 Pin # Output Value (2) */ +#define PORT_P3_OUT_P2 (0x1 << 2) +#define PORT_P3_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_OUT_P2_GET(val) ((((val) & PORT_P3_OUT_P2) >> 2) & 0x1) +#define PORT_P3_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 3 Pin # Output Value (1) */ +#define PORT_P3_OUT_P1 (0x1 << 1) +#define PORT_P3_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_OUT_P1_GET(val) ((((val) & PORT_P3_OUT_P1) >> 1) & 0x1) +#define PORT_P3_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 3 Pin # Output Value (0) */ +#define PORT_P3_OUT_P0 (0x1) +#define PORT_P3_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_OUT_P0_GET(val) ((((val) & PORT_P3_OUT_P0) >> 0) & 0x1) +#define PORT_P3_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Data Input Register + ******************************************************************************/ + +/* Port 3 Pin # Latched Input Value (19) */ +#define PORT_P3_IN_P19 (0x1 << 19) +#define PORT_P3_IN_P19_GET(val) ((((val) & PORT_P3_IN_P19) >> 19) & 0x1) +/* Port 3 Pin # Latched Input Value (18) */ +#define PORT_P3_IN_P18 (0x1 << 18) +#define PORT_P3_IN_P18_GET(val) ((((val) & PORT_P3_IN_P18) >> 18) & 0x1) +/* Port 3 Pin # Latched Input Value (17) */ +#define PORT_P3_IN_P17 (0x1 << 17) +#define PORT_P3_IN_P17_GET(val) ((((val) & PORT_P3_IN_P17) >> 17) & 0x1) +/* Port 3 Pin # Latched Input Value (16) */ +#define PORT_P3_IN_P16 (0x1 << 16) +#define PORT_P3_IN_P16_GET(val) ((((val) & PORT_P3_IN_P16) >> 16) & 0x1) +/* Port 3 Pin # Latched Input Value (15) */ +#define PORT_P3_IN_P15 (0x1 << 15) +#define PORT_P3_IN_P15_GET(val) ((((val) & PORT_P3_IN_P15) >> 15) & 0x1) +/* Port 3 Pin # Latched Input Value (14) */ +#define PORT_P3_IN_P14 (0x1 << 14) +#define PORT_P3_IN_P14_GET(val) ((((val) & PORT_P3_IN_P14) >> 14) & 0x1) +/* Port 3 Pin # Latched Input Value (13) */ +#define PORT_P3_IN_P13 (0x1 << 13) +#define PORT_P3_IN_P13_GET(val) ((((val) & PORT_P3_IN_P13) >> 13) & 0x1) +/* Port 3 Pin # Latched Input Value (12) */ +#define PORT_P3_IN_P12 (0x1 << 12) +#define PORT_P3_IN_P12_GET(val) ((((val) & PORT_P3_IN_P12) >> 12) & 0x1) +/* Port 3 Pin # Latched Input Value (11) */ +#define PORT_P3_IN_P11 (0x1 << 11) +#define PORT_P3_IN_P11_GET(val) ((((val) & PORT_P3_IN_P11) >> 11) & 0x1) +/* Port 3 Pin # Latched Input Value (10) */ +#define PORT_P3_IN_P10 (0x1 << 10) +#define PORT_P3_IN_P10_GET(val) ((((val) & PORT_P3_IN_P10) >> 10) & 0x1) +/* Port 3 Pin # Latched Input Value (9) */ +#define PORT_P3_IN_P9 (0x1 << 9) +#define PORT_P3_IN_P9_GET(val) ((((val) & PORT_P3_IN_P9) >> 9) & 0x1) +/* Port 3 Pin # Latched Input Value (8) */ +#define PORT_P3_IN_P8 (0x1 << 8) +#define PORT_P3_IN_P8_GET(val) ((((val) & PORT_P3_IN_P8) >> 8) & 0x1) +/* Port 3 Pin # Latched Input Value (7) */ +#define PORT_P3_IN_P7 (0x1 << 7) +#define PORT_P3_IN_P7_GET(val) ((((val) & PORT_P3_IN_P7) >> 7) & 0x1) +/* Port 3 Pin # Latched Input Value (6) */ +#define PORT_P3_IN_P6 (0x1 << 6) +#define PORT_P3_IN_P6_GET(val) ((((val) & PORT_P3_IN_P6) >> 6) & 0x1) +/* Port 3 Pin # Latched Input Value (5) */ +#define PORT_P3_IN_P5 (0x1 << 5) +#define PORT_P3_IN_P5_GET(val) ((((val) & PORT_P3_IN_P5) >> 5) & 0x1) +/* Port 3 Pin # Latched Input Value (4) */ +#define PORT_P3_IN_P4 (0x1 << 4) +#define PORT_P3_IN_P4_GET(val) ((((val) & PORT_P3_IN_P4) >> 4) & 0x1) +/* Port 3 Pin # Latched Input Value (3) */ +#define PORT_P3_IN_P3 (0x1 << 3) +#define PORT_P3_IN_P3_GET(val) ((((val) & PORT_P3_IN_P3) >> 3) & 0x1) +/* Port 3 Pin # Latched Input Value (2) */ +#define PORT_P3_IN_P2 (0x1 << 2) +#define PORT_P3_IN_P2_GET(val) ((((val) & PORT_P3_IN_P2) >> 2) & 0x1) +/* Port 3 Pin # Latched Input Value (1) */ +#define PORT_P3_IN_P1 (0x1 << 1) +#define PORT_P3_IN_P1_GET(val) ((((val) & PORT_P3_IN_P1) >> 1) & 0x1) +/* Port 3 Pin # Latched Input Value (0) */ +#define PORT_P3_IN_P0 (0x1) +#define PORT_P3_IN_P0_GET(val) ((((val) & PORT_P3_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 3 Direction Register + ******************************************************************************/ + +/* Port 3 Pin #Direction Control (19) */ +#define PORT_P3_DIR_P19 (0x1 << 19) +#define PORT_P3_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_DIR_P19_GET(val) ((((val) & PORT_P3_DIR_P19) >> 19) & 0x1) +#define PORT_P3_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 3 Pin #Direction Control (18) */ +#define PORT_P3_DIR_P18 (0x1 << 18) +#define PORT_P3_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_DIR_P18_GET(val) ((((val) & PORT_P3_DIR_P18) >> 18) & 0x1) +#define PORT_P3_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 3 Pin #Direction Control (17) */ +#define PORT_P3_DIR_P17 (0x1 << 17) +#define PORT_P3_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_DIR_P17_GET(val) ((((val) & PORT_P3_DIR_P17) >> 17) & 0x1) +#define PORT_P3_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 3 Pin #Direction Control (16) */ +#define PORT_P3_DIR_P16 (0x1 << 16) +#define PORT_P3_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_DIR_P16_GET(val) ((((val) & PORT_P3_DIR_P16) >> 16) & 0x1) +#define PORT_P3_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 3 Pin #Direction Control (15) */ +#define PORT_P3_DIR_P15 (0x1 << 15) +#define PORT_P3_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_DIR_P15_GET(val) ((((val) & PORT_P3_DIR_P15) >> 15) & 0x1) +#define PORT_P3_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 3 Pin #Direction Control (14) */ +#define PORT_P3_DIR_P14 (0x1 << 14) +#define PORT_P3_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_DIR_P14_GET(val) ((((val) & PORT_P3_DIR_P14) >> 14) & 0x1) +#define PORT_P3_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 3 Pin #Direction Control (13) */ +#define PORT_P3_DIR_P13 (0x1 << 13) +#define PORT_P3_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_DIR_P13_GET(val) ((((val) & PORT_P3_DIR_P13) >> 13) & 0x1) +#define PORT_P3_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 3 Pin #Direction Control (12) */ +#define PORT_P3_DIR_P12 (0x1 << 12) +#define PORT_P3_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_DIR_P12_GET(val) ((((val) & PORT_P3_DIR_P12) >> 12) & 0x1) +#define PORT_P3_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 3 Pin #Direction Control (11) */ +#define PORT_P3_DIR_P11 (0x1 << 11) +#define PORT_P3_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_DIR_P11_GET(val) ((((val) & PORT_P3_DIR_P11) >> 11) & 0x1) +#define PORT_P3_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 3 Pin #Direction Control (10) */ +#define PORT_P3_DIR_P10 (0x1 << 10) +#define PORT_P3_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_DIR_P10_GET(val) ((((val) & PORT_P3_DIR_P10) >> 10) & 0x1) +#define PORT_P3_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 3 Pin #Direction Control (9) */ +#define PORT_P3_DIR_P9 (0x1 << 9) +#define PORT_P3_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_DIR_P9_GET(val) ((((val) & PORT_P3_DIR_P9) >> 9) & 0x1) +#define PORT_P3_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 3 Pin #Direction Control (8) */ +#define PORT_P3_DIR_P8 (0x1 << 8) +#define PORT_P3_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_DIR_P8_GET(val) ((((val) & PORT_P3_DIR_P8) >> 8) & 0x1) +#define PORT_P3_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 3 Pin #Direction Control (7) */ +#define PORT_P3_DIR_P7 (0x1 << 7) +#define PORT_P3_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_DIR_P7_GET(val) ((((val) & PORT_P3_DIR_P7) >> 7) & 0x1) +#define PORT_P3_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 3 Pin #Direction Control (6) */ +#define PORT_P3_DIR_P6 (0x1 << 6) +#define PORT_P3_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_DIR_P6_GET(val) ((((val) & PORT_P3_DIR_P6) >> 6) & 0x1) +#define PORT_P3_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 3 Pin #Direction Control (5) */ +#define PORT_P3_DIR_P5 (0x1 << 5) +#define PORT_P3_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_DIR_P5_GET(val) ((((val) & PORT_P3_DIR_P5) >> 5) & 0x1) +#define PORT_P3_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 3 Pin #Direction Control (4) */ +#define PORT_P3_DIR_P4 (0x1 << 4) +#define PORT_P3_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_DIR_P4_GET(val) ((((val) & PORT_P3_DIR_P4) >> 4) & 0x1) +#define PORT_P3_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 3 Pin #Direction Control (3) */ +#define PORT_P3_DIR_P3 (0x1 << 3) +#define PORT_P3_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_DIR_P3_GET(val) ((((val) & PORT_P3_DIR_P3) >> 3) & 0x1) +#define PORT_P3_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 3 Pin #Direction Control (2) */ +#define PORT_P3_DIR_P2 (0x1 << 2) +#define PORT_P3_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_DIR_P2_GET(val) ((((val) & PORT_P3_DIR_P2) >> 2) & 0x1) +#define PORT_P3_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 3 Pin #Direction Control (1) */ +#define PORT_P3_DIR_P1 (0x1 << 1) +#define PORT_P3_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_DIR_P1_GET(val) ((((val) & PORT_P3_DIR_P1) >> 1) & 0x1) +#define PORT_P3_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 3 Pin #Direction Control (0) */ +#define PORT_P3_DIR_P0 (0x1) +#define PORT_P3_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_DIR_P0_GET(val) ((((val) & PORT_P3_DIR_P0) >> 0) & 0x1) +#define PORT_P3_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 3 Bit # (19) */ +#define PORT_P3_ALTSEL0_P19 (0x1 << 19) +#define PORT_P3_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_ALTSEL0_P19_GET(val) ((((val) & PORT_P3_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P3_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 3 Bit # (18) */ +#define PORT_P3_ALTSEL0_P18 (0x1 << 18) +#define PORT_P3_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_ALTSEL0_P18_GET(val) ((((val) & PORT_P3_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P3_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 3 Bit # (17) */ +#define PORT_P3_ALTSEL0_P17 (0x1 << 17) +#define PORT_P3_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_ALTSEL0_P17_GET(val) ((((val) & PORT_P3_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P3_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 3 Bit # (16) */ +#define PORT_P3_ALTSEL0_P16 (0x1 << 16) +#define PORT_P3_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_ALTSEL0_P16_GET(val) ((((val) & PORT_P3_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P3_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 3 Bit # (15) */ +#define PORT_P3_ALTSEL0_P15 (0x1 << 15) +#define PORT_P3_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_ALTSEL0_P15_GET(val) ((((val) & PORT_P3_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P3_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 3 Bit # (14) */ +#define PORT_P3_ALTSEL0_P14 (0x1 << 14) +#define PORT_P3_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_ALTSEL0_P14_GET(val) ((((val) & PORT_P3_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P3_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 3 Bit # (13) */ +#define PORT_P3_ALTSEL0_P13 (0x1 << 13) +#define PORT_P3_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_ALTSEL0_P13_GET(val) ((((val) & PORT_P3_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P3_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 3 Bit # (12) */ +#define PORT_P3_ALTSEL0_P12 (0x1 << 12) +#define PORT_P3_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_ALTSEL0_P12_GET(val) ((((val) & PORT_P3_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P3_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 3 Bit # (11) */ +#define PORT_P3_ALTSEL0_P11 (0x1 << 11) +#define PORT_P3_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_ALTSEL0_P11_GET(val) ((((val) & PORT_P3_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P3_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 3 Bit # (10) */ +#define PORT_P3_ALTSEL0_P10 (0x1 << 10) +#define PORT_P3_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_ALTSEL0_P10_GET(val) ((((val) & PORT_P3_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P3_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 3 Bit # (9) */ +#define PORT_P3_ALTSEL0_P9 (0x1 << 9) +#define PORT_P3_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_ALTSEL0_P9_GET(val) ((((val) & PORT_P3_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P3_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 3 Bit # (8) */ +#define PORT_P3_ALTSEL0_P8 (0x1 << 8) +#define PORT_P3_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_ALTSEL0_P8_GET(val) ((((val) & PORT_P3_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P3_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 3 Bit # (7) */ +#define PORT_P3_ALTSEL0_P7 (0x1 << 7) +#define PORT_P3_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_ALTSEL0_P7_GET(val) ((((val) & PORT_P3_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P3_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 3 Bit # (6) */ +#define PORT_P3_ALTSEL0_P6 (0x1 << 6) +#define PORT_P3_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_ALTSEL0_P6_GET(val) ((((val) & PORT_P3_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P3_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 3 Bit # (5) */ +#define PORT_P3_ALTSEL0_P5 (0x1 << 5) +#define PORT_P3_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_ALTSEL0_P5_GET(val) ((((val) & PORT_P3_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P3_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 3 Bit # (4) */ +#define PORT_P3_ALTSEL0_P4 (0x1 << 4) +#define PORT_P3_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_ALTSEL0_P4_GET(val) ((((val) & PORT_P3_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P3_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 3 Bit # (3) */ +#define PORT_P3_ALTSEL0_P3 (0x1 << 3) +#define PORT_P3_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_ALTSEL0_P3_GET(val) ((((val) & PORT_P3_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P3_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 3 Bit # (2) */ +#define PORT_P3_ALTSEL0_P2 (0x1 << 2) +#define PORT_P3_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_ALTSEL0_P2_GET(val) ((((val) & PORT_P3_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P3_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 3 Bit # (1) */ +#define PORT_P3_ALTSEL0_P1 (0x1 << 1) +#define PORT_P3_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_ALTSEL0_P1_GET(val) ((((val) & PORT_P3_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P3_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 3 Bit # (0) */ +#define PORT_P3_ALTSEL0_P0 (0x1) +#define PORT_P3_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_ALTSEL0_P0_GET(val) ((((val) & PORT_P3_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P3_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 3 Bit # (19) */ +#define PORT_P3_PUEN_P19 (0x1 << 19) +#define PORT_P3_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_PUEN_P19_GET(val) ((((val) & PORT_P3_PUEN_P19) >> 19) & 0x1) +#define PORT_P3_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 3 Bit # (18) */ +#define PORT_P3_PUEN_P18 (0x1 << 18) +#define PORT_P3_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_PUEN_P18_GET(val) ((((val) & PORT_P3_PUEN_P18) >> 18) & 0x1) +#define PORT_P3_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 3 Bit # (17) */ +#define PORT_P3_PUEN_P17 (0x1 << 17) +#define PORT_P3_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_PUEN_P17_GET(val) ((((val) & PORT_P3_PUEN_P17) >> 17) & 0x1) +#define PORT_P3_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 3 Bit # (16) */ +#define PORT_P3_PUEN_P16 (0x1 << 16) +#define PORT_P3_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_PUEN_P16_GET(val) ((((val) & PORT_P3_PUEN_P16) >> 16) & 0x1) +#define PORT_P3_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 3 Bit # (15) */ +#define PORT_P3_PUEN_P15 (0x1 << 15) +#define PORT_P3_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_PUEN_P15_GET(val) ((((val) & PORT_P3_PUEN_P15) >> 15) & 0x1) +#define PORT_P3_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 3 Bit # (14) */ +#define PORT_P3_PUEN_P14 (0x1 << 14) +#define PORT_P3_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_PUEN_P14_GET(val) ((((val) & PORT_P3_PUEN_P14) >> 14) & 0x1) +#define PORT_P3_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 3 Bit # (13) */ +#define PORT_P3_PUEN_P13 (0x1 << 13) +#define PORT_P3_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_PUEN_P13_GET(val) ((((val) & PORT_P3_PUEN_P13) >> 13) & 0x1) +#define PORT_P3_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 3 Bit # (12) */ +#define PORT_P3_PUEN_P12 (0x1 << 12) +#define PORT_P3_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_PUEN_P12_GET(val) ((((val) & PORT_P3_PUEN_P12) >> 12) & 0x1) +#define PORT_P3_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 3 Bit # (11) */ +#define PORT_P3_PUEN_P11 (0x1 << 11) +#define PORT_P3_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_PUEN_P11_GET(val) ((((val) & PORT_P3_PUEN_P11) >> 11) & 0x1) +#define PORT_P3_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 3 Bit # (10) */ +#define PORT_P3_PUEN_P10 (0x1 << 10) +#define PORT_P3_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_PUEN_P10_GET(val) ((((val) & PORT_P3_PUEN_P10) >> 10) & 0x1) +#define PORT_P3_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 3 Bit # (9) */ +#define PORT_P3_PUEN_P9 (0x1 << 9) +#define PORT_P3_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_PUEN_P9_GET(val) ((((val) & PORT_P3_PUEN_P9) >> 9) & 0x1) +#define PORT_P3_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 3 Bit # (8) */ +#define PORT_P3_PUEN_P8 (0x1 << 8) +#define PORT_P3_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_PUEN_P8_GET(val) ((((val) & PORT_P3_PUEN_P8) >> 8) & 0x1) +#define PORT_P3_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 3 Bit # (7) */ +#define PORT_P3_PUEN_P7 (0x1 << 7) +#define PORT_P3_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_PUEN_P7_GET(val) ((((val) & PORT_P3_PUEN_P7) >> 7) & 0x1) +#define PORT_P3_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 3 Bit # (6) */ +#define PORT_P3_PUEN_P6 (0x1 << 6) +#define PORT_P3_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_PUEN_P6_GET(val) ((((val) & PORT_P3_PUEN_P6) >> 6) & 0x1) +#define PORT_P3_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 3 Bit # (5) */ +#define PORT_P3_PUEN_P5 (0x1 << 5) +#define PORT_P3_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_PUEN_P5_GET(val) ((((val) & PORT_P3_PUEN_P5) >> 5) & 0x1) +#define PORT_P3_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 3 Bit # (4) */ +#define PORT_P3_PUEN_P4 (0x1 << 4) +#define PORT_P3_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_PUEN_P4_GET(val) ((((val) & PORT_P3_PUEN_P4) >> 4) & 0x1) +#define PORT_P3_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 3 Bit # (3) */ +#define PORT_P3_PUEN_P3 (0x1 << 3) +#define PORT_P3_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_PUEN_P3_GET(val) ((((val) & PORT_P3_PUEN_P3) >> 3) & 0x1) +#define PORT_P3_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 3 Bit # (2) */ +#define PORT_P3_PUEN_P2 (0x1 << 2) +#define PORT_P3_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_PUEN_P2_GET(val) ((((val) & PORT_P3_PUEN_P2) >> 2) & 0x1) +#define PORT_P3_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 3 Bit # (1) */ +#define PORT_P3_PUEN_P1 (0x1 << 1) +#define PORT_P3_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_PUEN_P1_GET(val) ((((val) & PORT_P3_PUEN_P1) >> 1) & 0x1) +#define PORT_P3_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 3 Bit # (0) */ +#define PORT_P3_PUEN_P0 (0x1) +#define PORT_P3_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_PUEN_P0_GET(val) ((((val) & PORT_P3_PUEN_P0) >> 0) & 0x1) +#define PORT_P3_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Data Output Register + ******************************************************************************/ + +/* Port 4 Pin # Output Value (23) */ +#define PORT_P4_OUT_P23 (0x1 << 23) +#define PORT_P4_OUT_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_OUT_P23_GET(val) ((((val) & PORT_P4_OUT_P23) >> 23) & 0x1) +#define PORT_P4_OUT_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P23) | (((val) & 0x1) << 23)) +/* Port 4 Pin # Output Value (22) */ +#define PORT_P4_OUT_P22 (0x1 << 22) +#define PORT_P4_OUT_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_OUT_P22_GET(val) ((((val) & PORT_P4_OUT_P22) >> 22) & 0x1) +#define PORT_P4_OUT_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P22) | (((val) & 0x1) << 22)) +/* Port 4 Pin # Output Value (21) */ +#define PORT_P4_OUT_P21 (0x1 << 21) +#define PORT_P4_OUT_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_OUT_P21_GET(val) ((((val) & PORT_P4_OUT_P21) >> 21) & 0x1) +#define PORT_P4_OUT_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P21) | (((val) & 0x1) << 21)) +/* Port 4 Pin # Output Value (20) */ +#define PORT_P4_OUT_P20 (0x1 << 20) +#define PORT_P4_OUT_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_OUT_P20_GET(val) ((((val) & PORT_P4_OUT_P20) >> 20) & 0x1) +#define PORT_P4_OUT_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P20) | (((val) & 0x1) << 20)) +/* Port 4 Pin # Output Value (19) */ +#define PORT_P4_OUT_P19 (0x1 << 19) +#define PORT_P4_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_OUT_P19_GET(val) ((((val) & PORT_P4_OUT_P19) >> 19) & 0x1) +#define PORT_P4_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 4 Pin # Output Value (18) */ +#define PORT_P4_OUT_P18 (0x1 << 18) +#define PORT_P4_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_OUT_P18_GET(val) ((((val) & PORT_P4_OUT_P18) >> 18) & 0x1) +#define PORT_P4_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 4 Pin # Output Value (17) */ +#define PORT_P4_OUT_P17 (0x1 << 17) +#define PORT_P4_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_OUT_P17_GET(val) ((((val) & PORT_P4_OUT_P17) >> 17) & 0x1) +#define PORT_P4_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 4 Pin # Output Value (16) */ +#define PORT_P4_OUT_P16 (0x1 << 16) +#define PORT_P4_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_OUT_P16_GET(val) ((((val) & PORT_P4_OUT_P16) >> 16) & 0x1) +#define PORT_P4_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 4 Pin # Output Value (15) */ +#define PORT_P4_OUT_P15 (0x1 << 15) +#define PORT_P4_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_OUT_P15_GET(val) ((((val) & PORT_P4_OUT_P15) >> 15) & 0x1) +#define PORT_P4_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 4 Pin # Output Value (14) */ +#define PORT_P4_OUT_P14 (0x1 << 14) +#define PORT_P4_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_OUT_P14_GET(val) ((((val) & PORT_P4_OUT_P14) >> 14) & 0x1) +#define PORT_P4_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 4 Pin # Output Value (13) */ +#define PORT_P4_OUT_P13 (0x1 << 13) +#define PORT_P4_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_OUT_P13_GET(val) ((((val) & PORT_P4_OUT_P13) >> 13) & 0x1) +#define PORT_P4_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 4 Pin # Output Value (12) */ +#define PORT_P4_OUT_P12 (0x1 << 12) +#define PORT_P4_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_OUT_P12_GET(val) ((((val) & PORT_P4_OUT_P12) >> 12) & 0x1) +#define PORT_P4_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 4 Pin # Output Value (11) */ +#define PORT_P4_OUT_P11 (0x1 << 11) +#define PORT_P4_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_OUT_P11_GET(val) ((((val) & PORT_P4_OUT_P11) >> 11) & 0x1) +#define PORT_P4_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 4 Pin # Output Value (10) */ +#define PORT_P4_OUT_P10 (0x1 << 10) +#define PORT_P4_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_OUT_P10_GET(val) ((((val) & PORT_P4_OUT_P10) >> 10) & 0x1) +#define PORT_P4_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 4 Pin # Output Value (9) */ +#define PORT_P4_OUT_P9 (0x1 << 9) +#define PORT_P4_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_OUT_P9_GET(val) ((((val) & PORT_P4_OUT_P9) >> 9) & 0x1) +#define PORT_P4_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 4 Pin # Output Value (8) */ +#define PORT_P4_OUT_P8 (0x1 << 8) +#define PORT_P4_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_OUT_P8_GET(val) ((((val) & PORT_P4_OUT_P8) >> 8) & 0x1) +#define PORT_P4_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 4 Pin # Output Value (7) */ +#define PORT_P4_OUT_P7 (0x1 << 7) +#define PORT_P4_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_OUT_P7_GET(val) ((((val) & PORT_P4_OUT_P7) >> 7) & 0x1) +#define PORT_P4_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 4 Pin # Output Value (6) */ +#define PORT_P4_OUT_P6 (0x1 << 6) +#define PORT_P4_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_OUT_P6_GET(val) ((((val) & PORT_P4_OUT_P6) >> 6) & 0x1) +#define PORT_P4_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 4 Pin # Output Value (5) */ +#define PORT_P4_OUT_P5 (0x1 << 5) +#define PORT_P4_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_OUT_P5_GET(val) ((((val) & PORT_P4_OUT_P5) >> 5) & 0x1) +#define PORT_P4_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 4 Pin # Output Value (4) */ +#define PORT_P4_OUT_P4 (0x1 << 4) +#define PORT_P4_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_OUT_P4_GET(val) ((((val) & PORT_P4_OUT_P4) >> 4) & 0x1) +#define PORT_P4_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 4 Pin # Output Value (3) */ +#define PORT_P4_OUT_P3 (0x1 << 3) +#define PORT_P4_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_OUT_P3_GET(val) ((((val) & PORT_P4_OUT_P3) >> 3) & 0x1) +#define PORT_P4_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 4 Pin # Output Value (2) */ +#define PORT_P4_OUT_P2 (0x1 << 2) +#define PORT_P4_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_OUT_P2_GET(val) ((((val) & PORT_P4_OUT_P2) >> 2) & 0x1) +#define PORT_P4_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 4 Pin # Output Value (1) */ +#define PORT_P4_OUT_P1 (0x1 << 1) +#define PORT_P4_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_OUT_P1_GET(val) ((((val) & PORT_P4_OUT_P1) >> 1) & 0x1) +#define PORT_P4_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 4 Pin # Output Value (0) */ +#define PORT_P4_OUT_P0 (0x1) +#define PORT_P4_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_OUT_P0_GET(val) ((((val) & PORT_P4_OUT_P0) >> 0) & 0x1) +#define PORT_P4_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Data Input Register + ******************************************************************************/ + +/* Port 4 Pin # Latched Input Value (23) */ +#define PORT_P4_IN_P23 (0x1 << 23) +#define PORT_P4_IN_P23_GET(val) ((((val) & PORT_P4_IN_P23) >> 23) & 0x1) +/* Port 4 Pin # Latched Input Value (22) */ +#define PORT_P4_IN_P22 (0x1 << 22) +#define PORT_P4_IN_P22_GET(val) ((((val) & PORT_P4_IN_P22) >> 22) & 0x1) +/* Port 4 Pin # Latched Input Value (21) */ +#define PORT_P4_IN_P21 (0x1 << 21) +#define PORT_P4_IN_P21_GET(val) ((((val) & PORT_P4_IN_P21) >> 21) & 0x1) +/* Port 4 Pin # Latched Input Value (20) */ +#define PORT_P4_IN_P20 (0x1 << 20) +#define PORT_P4_IN_P20_GET(val) ((((val) & PORT_P4_IN_P20) >> 20) & 0x1) +/* Port 4 Pin # Latched Input Value (19) */ +#define PORT_P4_IN_P19 (0x1 << 19) +#define PORT_P4_IN_P19_GET(val) ((((val) & PORT_P4_IN_P19) >> 19) & 0x1) +/* Port 4 Pin # Latched Input Value (18) */ +#define PORT_P4_IN_P18 (0x1 << 18) +#define PORT_P4_IN_P18_GET(val) ((((val) & PORT_P4_IN_P18) >> 18) & 0x1) +/* Port 4 Pin # Latched Input Value (17) */ +#define PORT_P4_IN_P17 (0x1 << 17) +#define PORT_P4_IN_P17_GET(val) ((((val) & PORT_P4_IN_P17) >> 17) & 0x1) +/* Port 4 Pin # Latched Input Value (16) */ +#define PORT_P4_IN_P16 (0x1 << 16) +#define PORT_P4_IN_P16_GET(val) ((((val) & PORT_P4_IN_P16) >> 16) & 0x1) +/* Port 4 Pin # Latched Input Value (15) */ +#define PORT_P4_IN_P15 (0x1 << 15) +#define PORT_P4_IN_P15_GET(val) ((((val) & PORT_P4_IN_P15) >> 15) & 0x1) +/* Port 4 Pin # Latched Input Value (14) */ +#define PORT_P4_IN_P14 (0x1 << 14) +#define PORT_P4_IN_P14_GET(val) ((((val) & PORT_P4_IN_P14) >> 14) & 0x1) +/* Port 4 Pin # Latched Input Value (13) */ +#define PORT_P4_IN_P13 (0x1 << 13) +#define PORT_P4_IN_P13_GET(val) ((((val) & PORT_P4_IN_P13) >> 13) & 0x1) +/* Port 4 Pin # Latched Input Value (12) */ +#define PORT_P4_IN_P12 (0x1 << 12) +#define PORT_P4_IN_P12_GET(val) ((((val) & PORT_P4_IN_P12) >> 12) & 0x1) +/* Port 4 Pin # Latched Input Value (11) */ +#define PORT_P4_IN_P11 (0x1 << 11) +#define PORT_P4_IN_P11_GET(val) ((((val) & PORT_P4_IN_P11) >> 11) & 0x1) +/* Port 4 Pin # Latched Input Value (10) */ +#define PORT_P4_IN_P10 (0x1 << 10) +#define PORT_P4_IN_P10_GET(val) ((((val) & PORT_P4_IN_P10) >> 10) & 0x1) +/* Port 4 Pin # Latched Input Value (9) */ +#define PORT_P4_IN_P9 (0x1 << 9) +#define PORT_P4_IN_P9_GET(val) ((((val) & PORT_P4_IN_P9) >> 9) & 0x1) +/* Port 4 Pin # Latched Input Value (8) */ +#define PORT_P4_IN_P8 (0x1 << 8) +#define PORT_P4_IN_P8_GET(val) ((((val) & PORT_P4_IN_P8) >> 8) & 0x1) +/* Port 4 Pin # Latched Input Value (7) */ +#define PORT_P4_IN_P7 (0x1 << 7) +#define PORT_P4_IN_P7_GET(val) ((((val) & PORT_P4_IN_P7) >> 7) & 0x1) +/* Port 4 Pin # Latched Input Value (6) */ +#define PORT_P4_IN_P6 (0x1 << 6) +#define PORT_P4_IN_P6_GET(val) ((((val) & PORT_P4_IN_P6) >> 6) & 0x1) +/* Port 4 Pin # Latched Input Value (5) */ +#define PORT_P4_IN_P5 (0x1 << 5) +#define PORT_P4_IN_P5_GET(val) ((((val) & PORT_P4_IN_P5) >> 5) & 0x1) +/* Port 4 Pin # Latched Input Value (4) */ +#define PORT_P4_IN_P4 (0x1 << 4) +#define PORT_P4_IN_P4_GET(val) ((((val) & PORT_P4_IN_P4) >> 4) & 0x1) +/* Port 4 Pin # Latched Input Value (3) */ +#define PORT_P4_IN_P3 (0x1 << 3) +#define PORT_P4_IN_P3_GET(val) ((((val) & PORT_P4_IN_P3) >> 3) & 0x1) +/* Port 4 Pin # Latched Input Value (2) */ +#define PORT_P4_IN_P2 (0x1 << 2) +#define PORT_P4_IN_P2_GET(val) ((((val) & PORT_P4_IN_P2) >> 2) & 0x1) +/* Port 4 Pin # Latched Input Value (1) */ +#define PORT_P4_IN_P1 (0x1 << 1) +#define PORT_P4_IN_P1_GET(val) ((((val) & PORT_P4_IN_P1) >> 1) & 0x1) +/* Port 4 Pin # Latched Input Value (0) */ +#define PORT_P4_IN_P0 (0x1) +#define PORT_P4_IN_P0_GET(val) ((((val) & PORT_P4_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 4 Direction Register + ******************************************************************************/ + +/* Port 4 Pin #Direction Control (23) */ +#define PORT_P4_DIR_P23 (0x1 << 23) +#define PORT_P4_DIR_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_DIR_P23_GET(val) ((((val) & PORT_P4_DIR_P23) >> 23) & 0x1) +#define PORT_P4_DIR_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P23) | (((val) & 0x1) << 23)) +/* Port 4 Pin #Direction Control (22) */ +#define PORT_P4_DIR_P22 (0x1 << 22) +#define PORT_P4_DIR_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_DIR_P22_GET(val) ((((val) & PORT_P4_DIR_P22) >> 22) & 0x1) +#define PORT_P4_DIR_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P22) | (((val) & 0x1) << 22)) +/* Port 4 Pin #Direction Control (21) */ +#define PORT_P4_DIR_P21 (0x1 << 21) +#define PORT_P4_DIR_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_DIR_P21_GET(val) ((((val) & PORT_P4_DIR_P21) >> 21) & 0x1) +#define PORT_P4_DIR_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P21) | (((val) & 0x1) << 21)) +/* Port 4 Pin #Direction Control (20) */ +#define PORT_P4_DIR_P20 (0x1 << 20) +#define PORT_P4_DIR_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_DIR_P20_GET(val) ((((val) & PORT_P4_DIR_P20) >> 20) & 0x1) +#define PORT_P4_DIR_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P20) | (((val) & 0x1) << 20)) +/* Port 4 Pin #Direction Control (19) */ +#define PORT_P4_DIR_P19 (0x1 << 19) +#define PORT_P4_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_DIR_P19_GET(val) ((((val) & PORT_P4_DIR_P19) >> 19) & 0x1) +#define PORT_P4_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 4 Pin #Direction Control (18) */ +#define PORT_P4_DIR_P18 (0x1 << 18) +#define PORT_P4_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_DIR_P18_GET(val) ((((val) & PORT_P4_DIR_P18) >> 18) & 0x1) +#define PORT_P4_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 4 Pin #Direction Control (17) */ +#define PORT_P4_DIR_P17 (0x1 << 17) +#define PORT_P4_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_DIR_P17_GET(val) ((((val) & PORT_P4_DIR_P17) >> 17) & 0x1) +#define PORT_P4_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 4 Pin #Direction Control (16) */ +#define PORT_P4_DIR_P16 (0x1 << 16) +#define PORT_P4_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_DIR_P16_GET(val) ((((val) & PORT_P4_DIR_P16) >> 16) & 0x1) +#define PORT_P4_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 4 Pin #Direction Control (15) */ +#define PORT_P4_DIR_P15 (0x1 << 15) +#define PORT_P4_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_DIR_P15_GET(val) ((((val) & PORT_P4_DIR_P15) >> 15) & 0x1) +#define PORT_P4_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 4 Pin #Direction Control (14) */ +#define PORT_P4_DIR_P14 (0x1 << 14) +#define PORT_P4_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_DIR_P14_GET(val) ((((val) & PORT_P4_DIR_P14) >> 14) & 0x1) +#define PORT_P4_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 4 Pin #Direction Control (13) */ +#define PORT_P4_DIR_P13 (0x1 << 13) +#define PORT_P4_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_DIR_P13_GET(val) ((((val) & PORT_P4_DIR_P13) >> 13) & 0x1) +#define PORT_P4_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 4 Pin #Direction Control (12) */ +#define PORT_P4_DIR_P12 (0x1 << 12) +#define PORT_P4_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_DIR_P12_GET(val) ((((val) & PORT_P4_DIR_P12) >> 12) & 0x1) +#define PORT_P4_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 4 Pin #Direction Control (11) */ +#define PORT_P4_DIR_P11 (0x1 << 11) +#define PORT_P4_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_DIR_P11_GET(val) ((((val) & PORT_P4_DIR_P11) >> 11) & 0x1) +#define PORT_P4_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 4 Pin #Direction Control (10) */ +#define PORT_P4_DIR_P10 (0x1 << 10) +#define PORT_P4_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_DIR_P10_GET(val) ((((val) & PORT_P4_DIR_P10) >> 10) & 0x1) +#define PORT_P4_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 4 Pin #Direction Control (9) */ +#define PORT_P4_DIR_P9 (0x1 << 9) +#define PORT_P4_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_DIR_P9_GET(val) ((((val) & PORT_P4_DIR_P9) >> 9) & 0x1) +#define PORT_P4_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 4 Pin #Direction Control (8) */ +#define PORT_P4_DIR_P8 (0x1 << 8) +#define PORT_P4_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_DIR_P8_GET(val) ((((val) & PORT_P4_DIR_P8) >> 8) & 0x1) +#define PORT_P4_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 4 Pin #Direction Control (7) */ +#define PORT_P4_DIR_P7 (0x1 << 7) +#define PORT_P4_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_DIR_P7_GET(val) ((((val) & PORT_P4_DIR_P7) >> 7) & 0x1) +#define PORT_P4_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 4 Pin #Direction Control (6) */ +#define PORT_P4_DIR_P6 (0x1 << 6) +#define PORT_P4_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_DIR_P6_GET(val) ((((val) & PORT_P4_DIR_P6) >> 6) & 0x1) +#define PORT_P4_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 4 Pin #Direction Control (5) */ +#define PORT_P4_DIR_P5 (0x1 << 5) +#define PORT_P4_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_DIR_P5_GET(val) ((((val) & PORT_P4_DIR_P5) >> 5) & 0x1) +#define PORT_P4_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 4 Pin #Direction Control (4) */ +#define PORT_P4_DIR_P4 (0x1 << 4) +#define PORT_P4_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_DIR_P4_GET(val) ((((val) & PORT_P4_DIR_P4) >> 4) & 0x1) +#define PORT_P4_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 4 Pin #Direction Control (3) */ +#define PORT_P4_DIR_P3 (0x1 << 3) +#define PORT_P4_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_DIR_P3_GET(val) ((((val) & PORT_P4_DIR_P3) >> 3) & 0x1) +#define PORT_P4_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 4 Pin #Direction Control (2) */ +#define PORT_P4_DIR_P2 (0x1 << 2) +#define PORT_P4_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_DIR_P2_GET(val) ((((val) & PORT_P4_DIR_P2) >> 2) & 0x1) +#define PORT_P4_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 4 Pin #Direction Control (1) */ +#define PORT_P4_DIR_P1 (0x1 << 1) +#define PORT_P4_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_DIR_P1_GET(val) ((((val) & PORT_P4_DIR_P1) >> 1) & 0x1) +#define PORT_P4_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 4 Pin #Direction Control (0) */ +#define PORT_P4_DIR_P0 (0x1) +#define PORT_P4_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_DIR_P0_GET(val) ((((val) & PORT_P4_DIR_P0) >> 0) & 0x1) +#define PORT_P4_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 4 Bit # (23) */ +#define PORT_P4_ALTSEL0_P23 (0x1 << 23) +#define PORT_P4_ALTSEL0_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_ALTSEL0_P23_GET(val) ((((val) & PORT_P4_ALTSEL0_P23) >> 23) & 0x1) +#define PORT_P4_ALTSEL0_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P23) | (((val) & 0x1) << 23)) +/* Alternate Function at Port 4 Bit # (22) */ +#define PORT_P4_ALTSEL0_P22 (0x1 << 22) +#define PORT_P4_ALTSEL0_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_ALTSEL0_P22_GET(val) ((((val) & PORT_P4_ALTSEL0_P22) >> 22) & 0x1) +#define PORT_P4_ALTSEL0_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P22) | (((val) & 0x1) << 22)) +/* Alternate Function at Port 4 Bit # (21) */ +#define PORT_P4_ALTSEL0_P21 (0x1 << 21) +#define PORT_P4_ALTSEL0_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_ALTSEL0_P21_GET(val) ((((val) & PORT_P4_ALTSEL0_P21) >> 21) & 0x1) +#define PORT_P4_ALTSEL0_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P21) | (((val) & 0x1) << 21)) +/* Alternate Function at Port 4 Bit # (20) */ +#define PORT_P4_ALTSEL0_P20 (0x1 << 20) +#define PORT_P4_ALTSEL0_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_ALTSEL0_P20_GET(val) ((((val) & PORT_P4_ALTSEL0_P20) >> 20) & 0x1) +#define PORT_P4_ALTSEL0_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P20) | (((val) & 0x1) << 20)) +/* Alternate Function at Port 4 Bit # (19) */ +#define PORT_P4_ALTSEL0_P19 (0x1 << 19) +#define PORT_P4_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_ALTSEL0_P19_GET(val) ((((val) & PORT_P4_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P4_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 4 Bit # (18) */ +#define PORT_P4_ALTSEL0_P18 (0x1 << 18) +#define PORT_P4_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_ALTSEL0_P18_GET(val) ((((val) & PORT_P4_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P4_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 4 Bit # (17) */ +#define PORT_P4_ALTSEL0_P17 (0x1 << 17) +#define PORT_P4_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_ALTSEL0_P17_GET(val) ((((val) & PORT_P4_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P4_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 4 Bit # (16) */ +#define PORT_P4_ALTSEL0_P16 (0x1 << 16) +#define PORT_P4_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_ALTSEL0_P16_GET(val) ((((val) & PORT_P4_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P4_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 4 Bit # (15) */ +#define PORT_P4_ALTSEL0_P15 (0x1 << 15) +#define PORT_P4_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_ALTSEL0_P15_GET(val) ((((val) & PORT_P4_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P4_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 4 Bit # (14) */ +#define PORT_P4_ALTSEL0_P14 (0x1 << 14) +#define PORT_P4_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_ALTSEL0_P14_GET(val) ((((val) & PORT_P4_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P4_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 4 Bit # (13) */ +#define PORT_P4_ALTSEL0_P13 (0x1 << 13) +#define PORT_P4_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_ALTSEL0_P13_GET(val) ((((val) & PORT_P4_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P4_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 4 Bit # (12) */ +#define PORT_P4_ALTSEL0_P12 (0x1 << 12) +#define PORT_P4_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_ALTSEL0_P12_GET(val) ((((val) & PORT_P4_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P4_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 4 Bit # (11) */ +#define PORT_P4_ALTSEL0_P11 (0x1 << 11) +#define PORT_P4_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_ALTSEL0_P11_GET(val) ((((val) & PORT_P4_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P4_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 4 Bit # (10) */ +#define PORT_P4_ALTSEL0_P10 (0x1 << 10) +#define PORT_P4_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_ALTSEL0_P10_GET(val) ((((val) & PORT_P4_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P4_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 4 Bit # (9) */ +#define PORT_P4_ALTSEL0_P9 (0x1 << 9) +#define PORT_P4_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_ALTSEL0_P9_GET(val) ((((val) & PORT_P4_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P4_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 4 Bit # (8) */ +#define PORT_P4_ALTSEL0_P8 (0x1 << 8) +#define PORT_P4_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_ALTSEL0_P8_GET(val) ((((val) & PORT_P4_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P4_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 4 Bit # (7) */ +#define PORT_P4_ALTSEL0_P7 (0x1 << 7) +#define PORT_P4_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_ALTSEL0_P7_GET(val) ((((val) & PORT_P4_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P4_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 4 Bit # (6) */ +#define PORT_P4_ALTSEL0_P6 (0x1 << 6) +#define PORT_P4_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_ALTSEL0_P6_GET(val) ((((val) & PORT_P4_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P4_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 4 Bit # (5) */ +#define PORT_P4_ALTSEL0_P5 (0x1 << 5) +#define PORT_P4_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_ALTSEL0_P5_GET(val) ((((val) & PORT_P4_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P4_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 4 Bit # (4) */ +#define PORT_P4_ALTSEL0_P4 (0x1 << 4) +#define PORT_P4_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_ALTSEL0_P4_GET(val) ((((val) & PORT_P4_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P4_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 4 Bit # (3) */ +#define PORT_P4_ALTSEL0_P3 (0x1 << 3) +#define PORT_P4_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_ALTSEL0_P3_GET(val) ((((val) & PORT_P4_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P4_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 4 Bit # (2) */ +#define PORT_P4_ALTSEL0_P2 (0x1 << 2) +#define PORT_P4_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_ALTSEL0_P2_GET(val) ((((val) & PORT_P4_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P4_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 4 Bit # (1) */ +#define PORT_P4_ALTSEL0_P1 (0x1 << 1) +#define PORT_P4_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_ALTSEL0_P1_GET(val) ((((val) & PORT_P4_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P4_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 4 Bit # (0) */ +#define PORT_P4_ALTSEL0_P0 (0x1) +#define PORT_P4_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_ALTSEL0_P0_GET(val) ((((val) & PORT_P4_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P4_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 4 Bit # (23) */ +#define PORT_P4_PUEN_P23 (0x1 << 23) +#define PORT_P4_PUEN_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_PUEN_P23_GET(val) ((((val) & PORT_P4_PUEN_P23) >> 23) & 0x1) +#define PORT_P4_PUEN_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P23) | (((val) & 0x1) << 23)) +/* Pull Up Device Enable at Port 4 Bit # (22) */ +#define PORT_P4_PUEN_P22 (0x1 << 22) +#define PORT_P4_PUEN_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_PUEN_P22_GET(val) ((((val) & PORT_P4_PUEN_P22) >> 22) & 0x1) +#define PORT_P4_PUEN_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P22) | (((val) & 0x1) << 22)) +/* Pull Up Device Enable at Port 4 Bit # (21) */ +#define PORT_P4_PUEN_P21 (0x1 << 21) +#define PORT_P4_PUEN_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_PUEN_P21_GET(val) ((((val) & PORT_P4_PUEN_P21) >> 21) & 0x1) +#define PORT_P4_PUEN_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P21) | (((val) & 0x1) << 21)) +/* Pull Up Device Enable at Port 4 Bit # (20) */ +#define PORT_P4_PUEN_P20 (0x1 << 20) +#define PORT_P4_PUEN_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_PUEN_P20_GET(val) ((((val) & PORT_P4_PUEN_P20) >> 20) & 0x1) +#define PORT_P4_PUEN_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P20) | (((val) & 0x1) << 20)) +/* Pull Up Device Enable at Port 4 Bit # (19) */ +#define PORT_P4_PUEN_P19 (0x1 << 19) +#define PORT_P4_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_PUEN_P19_GET(val) ((((val) & PORT_P4_PUEN_P19) >> 19) & 0x1) +#define PORT_P4_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 4 Bit # (18) */ +#define PORT_P4_PUEN_P18 (0x1 << 18) +#define PORT_P4_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_PUEN_P18_GET(val) ((((val) & PORT_P4_PUEN_P18) >> 18) & 0x1) +#define PORT_P4_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 4 Bit # (17) */ +#define PORT_P4_PUEN_P17 (0x1 << 17) +#define PORT_P4_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_PUEN_P17_GET(val) ((((val) & PORT_P4_PUEN_P17) >> 17) & 0x1) +#define PORT_P4_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 4 Bit # (16) */ +#define PORT_P4_PUEN_P16 (0x1 << 16) +#define PORT_P4_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_PUEN_P16_GET(val) ((((val) & PORT_P4_PUEN_P16) >> 16) & 0x1) +#define PORT_P4_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 4 Bit # (15) */ +#define PORT_P4_PUEN_P15 (0x1 << 15) +#define PORT_P4_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_PUEN_P15_GET(val) ((((val) & PORT_P4_PUEN_P15) >> 15) & 0x1) +#define PORT_P4_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 4 Bit # (14) */ +#define PORT_P4_PUEN_P14 (0x1 << 14) +#define PORT_P4_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_PUEN_P14_GET(val) ((((val) & PORT_P4_PUEN_P14) >> 14) & 0x1) +#define PORT_P4_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 4 Bit # (13) */ +#define PORT_P4_PUEN_P13 (0x1 << 13) +#define PORT_P4_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_PUEN_P13_GET(val) ((((val) & PORT_P4_PUEN_P13) >> 13) & 0x1) +#define PORT_P4_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 4 Bit # (12) */ +#define PORT_P4_PUEN_P12 (0x1 << 12) +#define PORT_P4_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_PUEN_P12_GET(val) ((((val) & PORT_P4_PUEN_P12) >> 12) & 0x1) +#define PORT_P4_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 4 Bit # (11) */ +#define PORT_P4_PUEN_P11 (0x1 << 11) +#define PORT_P4_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_PUEN_P11_GET(val) ((((val) & PORT_P4_PUEN_P11) >> 11) & 0x1) +#define PORT_P4_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 4 Bit # (10) */ +#define PORT_P4_PUEN_P10 (0x1 << 10) +#define PORT_P4_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_PUEN_P10_GET(val) ((((val) & PORT_P4_PUEN_P10) >> 10) & 0x1) +#define PORT_P4_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 4 Bit # (9) */ +#define PORT_P4_PUEN_P9 (0x1 << 9) +#define PORT_P4_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_PUEN_P9_GET(val) ((((val) & PORT_P4_PUEN_P9) >> 9) & 0x1) +#define PORT_P4_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 4 Bit # (8) */ +#define PORT_P4_PUEN_P8 (0x1 << 8) +#define PORT_P4_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_PUEN_P8_GET(val) ((((val) & PORT_P4_PUEN_P8) >> 8) & 0x1) +#define PORT_P4_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 4 Bit # (7) */ +#define PORT_P4_PUEN_P7 (0x1 << 7) +#define PORT_P4_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_PUEN_P7_GET(val) ((((val) & PORT_P4_PUEN_P7) >> 7) & 0x1) +#define PORT_P4_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 4 Bit # (6) */ +#define PORT_P4_PUEN_P6 (0x1 << 6) +#define PORT_P4_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_PUEN_P6_GET(val) ((((val) & PORT_P4_PUEN_P6) >> 6) & 0x1) +#define PORT_P4_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 4 Bit # (5) */ +#define PORT_P4_PUEN_P5 (0x1 << 5) +#define PORT_P4_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_PUEN_P5_GET(val) ((((val) & PORT_P4_PUEN_P5) >> 5) & 0x1) +#define PORT_P4_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 4 Bit # (4) */ +#define PORT_P4_PUEN_P4 (0x1 << 4) +#define PORT_P4_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_PUEN_P4_GET(val) ((((val) & PORT_P4_PUEN_P4) >> 4) & 0x1) +#define PORT_P4_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 4 Bit # (3) */ +#define PORT_P4_PUEN_P3 (0x1 << 3) +#define PORT_P4_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_PUEN_P3_GET(val) ((((val) & PORT_P4_PUEN_P3) >> 3) & 0x1) +#define PORT_P4_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 4 Bit # (2) */ +#define PORT_P4_PUEN_P2 (0x1 << 2) +#define PORT_P4_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_PUEN_P2_GET(val) ((((val) & PORT_P4_PUEN_P2) >> 2) & 0x1) +#define PORT_P4_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 4 Bit # (1) */ +#define PORT_P4_PUEN_P1 (0x1 << 1) +#define PORT_P4_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_PUEN_P1_GET(val) ((((val) & PORT_P4_PUEN_P1) >> 1) & 0x1) +#define PORT_P4_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 4 Bit # (0) */ +#define PORT_P4_PUEN_P0 (0x1) +#define PORT_P4_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_PUEN_P0_GET(val) ((((val) & PORT_P4_PUEN_P0) >> 0) & 0x1) +#define PORT_P4_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P0) | (((val) & 0x1) << 0)) + +#endif /* __PORT_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h new file mode 100644 index 000000000..4ea2f5a68 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h @@ -0,0 +1,624 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SSC_REG_H +#define __SSC_REG_H + +/** SSC register structure */ +struct svip_reg_ssc { + volatile unsigned long clc; /* 0x00 */ + volatile unsigned long pisel; /* 0x04 */ + volatile unsigned long id; /* 0x08 */ + volatile unsigned long reserved0; /* 0x0c */ + volatile unsigned long mcon; /* 0x10 */ + volatile unsigned long state; /* 0x14 */ + volatile unsigned long whbstate; /* 0x18 */ + volatile unsigned long reserved1; /* 0x1c */ + volatile unsigned long tb; /* 0x20 */ + volatile unsigned long rb; /* 0x24 */ + volatile unsigned long reserved2[2]; /* 0x28 */ + volatile unsigned long rxfcon; /* 0x30 */ + volatile unsigned long txfcon; /* 0x34 */ + volatile unsigned long fstat; /* 0x38 */ + volatile unsigned long reserved3; /* 0x3c */ + volatile unsigned long br; /* 0x40 */ + volatile unsigned long brstat; /* 0x44 */ + volatile unsigned long reserved4[6]; /* 0x48 */ + volatile unsigned long sfcon; /* 0x60 */ + volatile unsigned long sfstat; /* 0x64 */ + volatile unsigned long reserved5[2]; /* 0x68 */ + volatile unsigned long gpocon; /* 0x70 */ + volatile unsigned long gpostat; /* 0x74 */ + volatile unsigned long whbgpostat; /* 0x78 */ + volatile unsigned long reserved6; /* 0x7c */ + volatile unsigned long rxreq; /* 0x80 */ + volatile unsigned long rxcnt; /* 0x84 */ + volatile unsigned long reserved7[25]; /* 0x88 */ + volatile unsigned long dma_con; /* 0xEC */ + volatile unsigned long reserved8; /* 0xf0 */ + volatile unsigned long irnen; /* 0xF4 */ + volatile unsigned long irncr; /* 0xF8 */ + volatile unsigned long irnicr; /* 0xFC */ +}; + +/******************************************************************************* + * CLC Register + ******************************************************************************/ + +/* Clock Divider for Sleep Mode (23:16) */ +#define SSC_CLC_SMC (0xff << 16) +#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16) +#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff) +#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16)) +/* Clock Divider for Normal Run Mode (15:8) */ +#define SSC_CLC_RMC (0xff << 8) +#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8) +#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff) +#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8)) +/* Fast Shut-Off Enable Bit (5) */ +#define SSC_CLC_FSOE (0x1 << 5) +#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) +#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1) +#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5)) +/* Suspend Bit Write Enable for OCDS (4) */ +#define SSC_CLC_SBWE (0x1 << 4) +#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) +#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4) +/* External Request Disable (3) */ +#define SSC_CLC_EDIS (0x1 << 3) +#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) +#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1) +#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3)) +/* Suspend Enable Bit for OCDS (2) */ +#define SSC_CLC_SPEN (0x1 << 2) +#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) +#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1) +#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2)) +/* Disable Status Bit (1) */ +#define SSC_CLC_DISS (0x1 << 1) +#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1) +/* Disable Request Bit (0) */ +#define SSC_CLC_DISR (0x1) +#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0) +#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1) +#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * ID Register + ******************************************************************************/ + +/* Transmit FIFO Size (29:24) */ +#define SSC_ID_TXFS (0x3f << 24) +#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f) +/* Receive FIFO Size (21:16) */ +#define SSC_ID_RXFS (0x3f << 16) +#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f) +/* Module ID (15:8) */ +#define SSC_ID_ID (0xff << 8) +#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff) +/* Configuration (5) */ +#define SSC_ID_CFG (0x1 << 5) +#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1) +/* Revision (4:0) */ +#define SSC_ID_REV (0x1f) +#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f) + +/******************************************************************************* + * MCON Register + ******************************************************************************/ + +/* Echo Mode (24) */ +#define SSC_MCON_EM (0x1 << 24) +#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24) +#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1) +#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24)) +/* Idle Bit Value (23) */ +#define SSC_MCON_IDLE (0x1 << 23) +#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23) +#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1) +#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23)) +/* Enable Byte Valid Control (22) */ +#define SSC_MCON_ENBV (0x1 << 22) +#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22) +#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1) +#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22)) +/* Data Width Selection (20:16) */ +#define SSC_MCON_BM (0x1f << 16) +#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16) +#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f) +#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16)) +/* Receive Underflow Error Enable (12) */ +#define SSC_MCON_RUEN (0x1 << 12) +#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12) +#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1) +#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12)) +/* Transmit Underflow Error Enable (11) */ +#define SSC_MCON_TUEN (0x1 << 11) +#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11) +#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1) +#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11)) +/* Abort Error Enable (10) */ +#define SSC_MCON_AEN (0x1 << 10) +#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10) +#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1) +#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10)) +/* Receive Overflow Error Enable (9) */ +#define SSC_MCON_REN (0x1 << 9) +#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9) +#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1) +#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9)) +/* Transmit Overflow Error Enable (8) */ +#define SSC_MCON_TEN (0x1 << 8) +#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8) +#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1) +#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8)) +/* Loop Back Control (7) */ +#define SSC_MCON_LB (0x1 << 7) +#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7) +#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1) +#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7)) +/* Clock Polarity Control (6) */ +#define SSC_MCON_PO (0x1 << 6) +#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6) +#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1) +#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6)) +/* Clock Phase Control (5) */ +#define SSC_MCON_PH (0x1 << 5) +#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5) +#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1) +#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5)) +/* Heading Control (4) */ +#define SSC_MCON_HB (0x1 << 4) +#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4) +#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1) +#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4)) +/* Chip Select Enable (3) */ +#define SSC_MCON_CSBEN (0x1 << 3) +#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3) +#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1) +#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3)) +/* Chip Select Invert (2) */ +#define SSC_MCON_CSBINV (0x1 << 2) +#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2) +#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1) +#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2)) +/* Receive Off (1) */ +#define SSC_MCON_RXOFF (0x1 << 1) +#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1) +#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1) +#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1)) +/* Transmit Off (0) */ +#define SSC_MCON_TXOFF (0x1) +#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0) +#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1) +#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * STATE Register + ******************************************************************************/ + +/* Receive End-of-Message (31) */ +#define SSC_STATE_RXEOM (0x1 << 31) +#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1) +/* Receive Byte Valid (30:28) */ +#define SSC_STATE_RXBV (0x7 << 28) +#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7) +/* Transmit End-of-Message (27) */ +#define SSC_STATE_TXEOM (0x1 << 27) +#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1) +/* Transmit Byte Valid (26:24) */ +#define SSC_STATE_TXBV (0x7 << 24) +#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7) +/* Bit Count Field (20:16) */ +#define SSC_STATE_BC (0x1f << 16) +#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f) +/* Busy Flag (13) */ +#define SSC_STATE_BSY (0x1 << 13) +#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1) +/* Receive Underflow Error Flag (12) */ +#define SSC_STATE_RUE (0x1 << 12) +#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1) +/* Transmit Underflow Error Flag (11) */ +#define SSC_STATE_TUE (0x1 << 11) +#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1) +/* Abort Error Flag (10) */ +#define SSC_STATE_AE (0x1 << 10) +#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1) +/* Receive Error Flag (9) */ +#define SSC_STATE_RE (0x1 << 9) +#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1) +/* Transmit Error Flag (8) */ +#define SSC_STATE_TE (0x1 << 8) +#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1) +/* Mode Error Flag (7) */ +#define SSC_STATE_ME (0x1 << 7) +#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1) +/* Slave Selected (2) */ +#define SSC_STATE_SSEL (0x1 << 2) +#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1) +/* Master Select Bit (1) */ +#define SSC_STATE_MS (0x1 << 1) +#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1) +/* Enable Bit (0) */ +#define SSC_STATE_EN (0x1) +#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1) + +/******************************************************************************* + * WHBSTATE Register + ******************************************************************************/ + +/* Set Transmit Underflow Error Flag Bit (15) */ +#define SSC_WHBSTATE_SETTUE (0x1 << 15) +#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15) +#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15) +/* Set Abort Error Flag Bit (14) */ +#define SSC_WHBSTATE_SETAE (0x1 << 14) +#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14) +#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14) +/* Set Receive Error Flag Bit (13) */ +#define SSC_WHBSTATE_SETRE (0x1 << 13) +#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13) +#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13) +/* Set Transmit Error Flag Bit (12) */ +#define SSC_WHBSTATE_SETTE (0x1 << 12) +#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12) +#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12) +/* Clear Transmit Underflow Error Flag Bit (11) */ +#define SSC_WHBSTATE_CLRTUE (0x1 << 11) +#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11) +#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11) +/* Clear Abort Error Flag Bit (10) */ +#define SSC_WHBSTATE_CLRAE (0x1 << 10) +#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10) +#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10) +/* Clear Receive Error Flag Bit (9) */ +#define SSC_WHBSTATE_CLRRE (0x1 << 9) +#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9) +#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9) +/* Clear Transmit Error Flag Bit (8) */ +#define SSC_WHBSTATE_CLRTE (0x1 << 8) +#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8) +#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8) +/* Set Mode Error Flag Bit (7) */ +#define SSC_WHBSTATE_SETME (0x1 << 7) +#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7) +#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7) +/* Clear Mode Error Flag Bit (6) */ +#define SSC_WHBSTATE_CLRME (0x1 << 6) +#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6) +#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6) +/* Set Receive Underflow Error Bit (5) */ +#define SSC_WHBSTATE_SETRUE (0x1 << 5) +#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5) +#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5) +/* Clear Receive Underflow Error Bit (4) */ +#define SSC_WHBSTATE_CLRRUE (0x1 << 4) +#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4) +#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4) +/* Set Master Select Bit (3) */ +#define SSC_WHBSTATE_SETMS (0x1 << 3) +#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3) +#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3) +/* Clear Master Select Bit (2) */ +#define SSC_WHBSTATE_CLRMS (0x1 << 2) +#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2) +#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2) +/* Set Enable Bit (1) */ +#define SSC_WHBSTATE_SETEN (0x1 << 1) +#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1) +#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1) +/* Clear Enable Bit (0) */ +#define SSC_WHBSTATE_CLREN (0x1) +#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0) +#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0) + +/******************************************************************************* + * TB Register + ******************************************************************************/ + +/* Transmit Data Register Value (31:0) */ +#define SSC_TB_TB_VAL (0xFFFFFFFFL) +#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL) +#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * RB Register + ******************************************************************************/ + +/* Receive Data Register Value (31:0) */ +#define SSC_RB_RB_VAL (0xFFFFFFFFL) +#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL) + +/******************************************************************************* + * FSTAT Register + ******************************************************************************/ + +/* Transmit FIFO Filling Level (13:8) */ +#define SSC_FSTAT_TXFFL (0x3f << 8) +#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f) +/* Receive FIFO Filling Level (5:0) */ +#define SSC_FSTAT_RXFFL (0x3f) +#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f) + +/******************************************************************************* + * PISEL Register + ******************************************************************************/ + +/* Slave Mode Clock Input Select (2) */ +#define SSC_PISEL_CIS (0x1 << 2) +#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2) +#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1) +#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2)) +/* Slave Mode Receiver Input Select (1) */ +#define SSC_PISEL_SIS (0x1 << 1) +#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1) +#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1) +#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1)) +/* Master Mode Receiver Input Select (0) */ +#define SSC_PISEL_MIS (0x1) +#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0) +#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1) +#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * RXFCON Register + ******************************************************************************/ + +/* Receive FIFO Interrupt Trigger Level (13:8) */ +#define SSC_RXFCON_RXFITL (0x3f << 8) +#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8) +#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f) +#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8)) +/* Receive FIFO Flush (1) */ +#define SSC_RXFCON_RXFLU (0x1 << 1) +#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1) +#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1) +/* Receive FIFO Enable (0) */ +#define SSC_RXFCON_RXFEN (0x1) +#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0) +#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1) +#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * TXFCON Register + ******************************************************************************/ + +/* Transmit FIFO Interrupt Trigger Level (13:8) */ +#define SSC_TXFCON_TXFITL (0x3f << 8) +#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8) +#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f) +#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8)) +/* Transmit FIFO Flush (1) */ +#define SSC_TXFCON_TXFLU (0x1 << 1) +#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1) +#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1) +/* Transmit FIFO Enable (0) */ +#define SSC_TXFCON_TXFEN (0x1) +#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0) +#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1) +#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * BR Register + ******************************************************************************/ + +/* Baudrate Timer Reload Register Value (15:0) */ +#define SSC_BR_BR_VAL (0xffff) +#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0) +#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff) +#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * BRSTAT Register + ******************************************************************************/ + +/* Baudrate Timer Register Value (15:0) */ +#define SSC_BRSTAT_BT_VAL (0xffff) +#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff) + +/******************************************************************************* + * SFCON Register + ******************************************************************************/ + +/* Pause Length (31:22) */ +#define SSC_SFCON_PLEN (0x3ff << 22) +#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22) +#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff) +#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22)) +/* Stop After Pause (20) */ +#define SSC_SFCON_STOP (0x1 << 20) +#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20) +#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1) +#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20)) +/* Idle Clock Configuration (19:18) */ +#define SSC_SFCON_ICLK (0x3 << 18) +#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18) +#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3) +#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18)) +/* Idle Data Configuration (17:16) */ +#define SSC_SFCON_IDAT (0x3 << 16) +#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16) +#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3) +#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16)) +/* Data Length (15:4) */ +#define SSC_SFCON_DLEN (0xfff << 4) +#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4) +#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff) +#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4)) +/* Enable Interrupt After Pause (3) */ +#define SSC_SFCON_IAEN (0x1 << 3) +#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3) +#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1) +#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3)) +/* Enable Interrupt Before Pause (2) */ +#define SSC_SFCON_IBEN (0x1 << 2) +#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2) +#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1) +#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2)) +/* Serial Frame Enable (0) */ +#define SSC_SFCON_SFEN (0x1) +#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0) +#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1) +#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SFSTAT Register + ******************************************************************************/ + +/* Pause Count (31:22) */ +#define SSC_SFSTAT_PCNT (0x3ff << 22) +#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff) +/* Data Bit Count (15:4) */ +#define SSC_SFSTAT_DCNT (0xfff << 4) +#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff) +/* Pause Busy (1) */ +#define SSC_SFSTAT_PBSY (0x1 << 1) +#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1) +/* Data Busy (0) */ +#define SSC_SFSTAT_DBSY (0x1) +#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1) + +/******************************************************************************* + * GPOCON Register + ******************************************************************************/ + +/* Output OUTn Is Chip Select (15:8) */ +#define SSC_GPOCON_ISCSBN (0xff << 8) +#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8) +#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff) +#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8)) +/* Invert Output OUTn (7:0) */ +#define SSC_GPOCON_INVOUTN (0xff) +#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0) +#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff) +#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * GPOSTAT Register + ******************************************************************************/ + +/* Output Register Bit n (7:0) */ +#define SSC_GPOSTAT_OUTN (0xff) +#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff) + +/******************************************************************************* + * WHBGPOSTAT + ******************************************************************************/ + +/* Set Output Register Bit n (15:8) */ +#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8) +#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8) +#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8) +/* Clear Output Register Bit n (7:0) */ +#define SSC_WHBGPOSTAT_CLROUTN (0xff) +#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0) +#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0) + +/******************************************************************************* + * RXREQ Register + ******************************************************************************/ + +/* Receive Count Value (15:0) */ +#define SSC_RXREQ_RXCNT (0xffff) +#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0) +#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff) +#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * RXCNT Register + ******************************************************************************/ + +/* Receive To Do Value (15:0) */ +#define SSC_RXCNT_TODO (0xffff) +#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff) + +/******************************************************************************* + * DMA_CON Register + ******************************************************************************/ + +/* Receive Class (3:2) */ +#define SSC_DMA_CON_RXCLS (0x3 << 2) +#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2) +#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3) +#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2)) +/* Transmit Path On (1) */ +#define SSC_DMA_CON_TXON (0x1 << 1) +#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1) +#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1) +#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1)) +/* Receive Path On (0) */ +#define SSC_DMA_CON_RXON (0x1) +#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0) +#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1) +#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * IRNEN Register + ******************************************************************************/ + +/* Frame End Interrupt Request Enable (3) */ +#define SSC_IRNEN_F (0x1 << 3) +#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3) +#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1) +#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3)) +/* Error Interrupt Request Enable (2) */ +#define SSC_IRNEN_E (0x1 << 2) +#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2) +#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1) +#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2)) +/* Receive Interrupt Request Enable (1) */ +#define SSC_IRNEN_R (0x1 << 1) +#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1) +#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1) +#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1)) +/* Transmit Interrupt Request Enable (0) */ +#define SSC_IRNEN_T (0x1) +#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0) +#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1) +#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * IRNICR Register + ******************************************************************************/ + +/* Frame End Interrupt Request (3) */ +#define SSC_IRNICR_F (0x1 << 3) +#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1) +/* Error Interrupt Request (2) */ +#define SSC_IRNICR_E (0x1 << 2) +#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1) +/* Receive Interrupt Request (1) */ +#define SSC_IRNICR_R (0x1 << 1) +#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1) +/* Transmit Interrupt Request (0) */ +#define SSC_IRNICR_T (0x1) +#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1) + +/******************************************************************************* + * IRNCR Register + ******************************************************************************/ + +/* Frame End Interrupt Request (3) */ +#define SSC_IRNCR_F (0x1 << 3) +#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1) +/* Error Interrupt Request (2) */ +#define SSC_IRNCR_E (0x1 << 2) +#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1) +/* Receive Interrupt Request (1) */ +#define SSC_IRNCR_R (0x1 << 1) +#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1) +/* Transmit Interrupt Request (0) */ +#define SSC_IRNCR_T (0x1) +#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1) + +#endif /* __SSC_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h new file mode 100644 index 000000000..100230fa7 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h @@ -0,0 +1,130 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __STATUS_REG_H +#define __STATUS_REG_H + +#define status_r32(reg) ltq_r32(&status->reg) +#define status_w32(val, reg) ltq_w32(val, &status->reg) +#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg) + +/** STATUS register structure */ +struct svip_reg_status { + unsigned long fuse_deu; /* 0x0000 */ + unsigned long fuse_cpu; /* 0x0004 */ + unsigned long fuse_pll; /* 0x0008 */ + unsigned long chipid; /* 0x000C */ + unsigned long config; /* 0x0010 */ + unsigned long chip_loc; /* 0x0014 */ + unsigned long fuse_spare; /* 0x0018 */ +}; + +/******************************************************************************* + * Fuse for DEU Settings + ******************************************************************************/ + +/* Fuse for Enabling the TRNG (6) */ +#define STATUS_FUSE_DEU_TRNG (0x1 << 6) +#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1) +/* Fuse for Enabling the DES Submodule (5) */ +#define STATUS_FUSE_DEU_DES (0x1 << 5) +#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1) +/* Fuse for Enabling the 3DES Submodule (4) */ +#define STATUS_FUSE_DEU_3DES (0x1 << 4) +#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1) +/* Fuse for Enabling the AES Submodule (3) */ +#define STATUS_FUSE_DEU_AES (0x1 << 3) +#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1) +/* Fuse for Enabling the HASH Submodule (2) */ +#define STATUS_FUSE_DEU_HASH (0x1 << 2) +#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1) +/* Fuse for Enabling the ARC4 Submodule (1) */ +#define STATUS_FUSE_DEU_ARC4 (0x1 << 1) +#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1) +/* Fuse for Enabling the DEU Module (0) */ +#define STATUS_FUSE_DEU_DEU (0x1) +#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1) + +/******************************************************************************* + * Fuse for CPU Settings + ******************************************************************************/ + +/* Fuse for Enabling CPU5 (5) */ +#define STATUS_FUSE_CPU_CPU5 (0x1 << 5) +#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1) +/* Fuse for Enabling the CPU4 (4) */ +#define STATUS_FUSE_CPU_CPU4 (0x1 << 4) +#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1) +/* Fuse for Enabling the CPU3 (3) */ +#define STATUS_FUSE_CPU_CPU3 (0x1 << 3) +#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1) +/* Fuse for Enabling the CPU2 (2) */ +#define STATUS_FUSE_CPU_CPU2 (0x1 << 2) +#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1) +/* Fuse for Enabling the CPU1 (1) */ +#define STATUS_FUSE_CPU_CPU1 (0x1 << 1) +#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1) +/* Fuse for Enabling the CPU0 (0) */ +#define STATUS_FUSE_CPU_CPU0 (0x1) +#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1) + +/******************************************************************************* + * Fuse for PLL Settings + ******************************************************************************/ + +/* Fuse for Enabling PLL (7:0) */ +#define STATUS_FUSE_PLL_PLL (0xff) +#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff) + +/******************************************************************************* + * Chip Identification Register + ******************************************************************************/ + +/* Chip Version Number (31:28) */ +#define STATUS_CHIPID_VERSION (0xf << 28) +#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf) +/* Part Number (27:12) */ +#define STATUS_CHIPID_PART_NUMBER (0xffff << 12) +#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff) +/* Manufacturer ID (11:1) */ +#define STATUS_CHIPID_MANID (0x7ff << 1) +#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff) + +/******************************************************************************* + * Chip Configuration Register + ******************************************************************************/ + +/* Number of Analog Channels (8:5) */ +#define STATUS_CONFIG_ANA_CHAN (0xf << 5) +#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf) +/* Clock Mode (4) */ +#define STATUS_CONFIG_CLK_MODE (0x1 << 1) +#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1) +/* Subversion Number (3:0) */ +#define STATUS_CONFIG_SUB_VERS (0xF) +#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF) + +/******************************************************************************* + * Chip Location Register + ******************************************************************************/ + +/* Chip Lot ID (31:16) */ +#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16) +#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff) +/* Chip X Coordinate (15:8) */ +#define STATUS_CHIP_LOC_CHIP_X (0xff << 8) +#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff) +/* Chip Y Coordinate (7:0) */ +#define STATUS_CHIP_LOC_CHIP_Y (0xff) +#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h new file mode 100644 index 000000000..5c34bb690 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h @@ -0,0 +1,245 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#ifndef __SVIP_DMA_H +#define __SVIP_DMA_H + +#define LTQ_DMA_CH_ON 1 +#define LTQ_DMA_CH_OFF 0 +#define LTQ_DMA_CH_DEFAULT_WEIGHT 100; + +#define DMA_OWN 1 +#define CPU_OWN 0 +#define DMA_MAJOR 250 + +/* Descriptors */ +#define DMA_DESC_OWN_CPU 0x0 +#define DMA_DESC_OWN_DMA 0x80000000 +#define DMA_DESC_CPT_SET 0x40000000 +#define DMA_DESC_SOP_SET 0x20000000 +#define DMA_DESC_EOP_SET 0x10000000 + +struct rx_desc { + union { + struct { +#ifdef CONFIG_CPU_LITTLE_ENDIAN + volatile u32 data_length:16; + volatile u32 reserve2:7; + volatile u32 byte_offset:2; + volatile u32 reserve1:3; + volatile u32 eop:1; + volatile u32 sop:1; + volatile u32 c:1; + volatile u32 own:1; +#else + volatile u32 own:1; + volatile u32 c:1; + volatile u32 sop:1; + volatile u32 eop:1; + volatile u32 reserve1:3; + volatile u32 byte_offset:2; + volatile u32 reserve2:7; + volatile u32 data_length:16; +#endif + } field; + + volatile u32 word; + } status; + + volatile u32 data_pointer; +}; + +struct tx_desc { + union { + struct { +#ifdef CONFIG_CPU_LITTLE_ENDIAN + volatile u32 data_length:16; + volatile u32 reserved:7; + volatile u32 byte_offset:5; + volatile u32 eop:1; + volatile u32 sop:1; + volatile u32 c:1; + volatile u32 own:1; +#else + volatile u32 own:1; + volatile u32 c:1; + volatile u32 sop:1; + volatile u32 eop:1; + volatile u32 byte_offset:5; + volatile u32 reserved:7; + volatile u32 data_length:16; +#endif + } field; + + volatile u32 word; + } status; + + volatile u32 data_pointer; +}; + +/* DMA pseudo interrupts notified to switch driver */ +#define RCV_INT 0x01 +#define TX_BUF_FULL_INT 0x02 +#define TRANSMIT_CPT_INT 0x04 +#define CHANNEL_CLOSED 0x10 + +/* Parameters for switch DMA device */ +#define DEFAULT_SW_CHANNEL_WEIGHT 3 +#define DEFAULT_SW_PORT_WEIGHT 7 + +#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ +#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_SW_TX_CHANNEL_NUM 4 +#define DEFAULT_SW_RX_CHANNEL_NUM 4 + +#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20 +#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20 + +/* Parameters for SSC DMA device */ +#define DEFAULT_SSC_CHANNEL_WEIGHT 3 +#define DEFAULT_SSC_PORT_WEIGHT 7 + +#define DEFAULT_SSC_TX_CHANNEL_CLASS 3 +#define DEFAULT_SSC_RX_CHANNEL_CLASS 0 + +#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ +#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_SSC0_TX_CHANNEL_NUM 1 +#define DEFAULT_SSC0_RX_CHANNEL_NUM 1 +#define DEFAULT_SSC1_TX_CHANNEL_NUM 1 +#define DEFAULT_SSC1_RX_CHANNEL_NUM 1 + +#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10 +#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10 + +/* Parameters for memory DMA device */ +#define DEFAULT_MEM_CHANNEL_WEIGHT 3 +#define DEFAULT_MEM_PORT_WEIGHT 7 + +#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ +#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_MEM_TX_CHANNEL_NUM 1 +#define DEFAULT_MEM_RX_CHANNEL_NUM 1 + +#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2 +#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2 + +/* Parameters for DEU DMA device */ +#define DEFAULT_DEU_CHANNEL_WEIGHT 1 +#define DEFAULT_DEU_PORT_WEIGHT 1 + +#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ +#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20 +#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20 + +#define DMA_DESCR_NUM 30 /* number of descriptors per channel */ + +enum dma_dir_t { + DIR_RX = 0, + DIR_TX = 1, +}; + +struct dma_device_info; + +struct dma_channel_info { + /*Pointer to the peripheral device who is using this channel*/ + /*const*/ struct dma_device_info *dma_dev; + /*direction*/ + const enum dma_dir_t dir; /*RX or TX*/ + /*class for this channel for QoS*/ + int pri; + /*irq number*/ + const int irq; + /*relative channel number*/ + const int rel_chan_no; + /*absolute channel number*/ + int abs_chan_no; + + /*specify byte_offset*/ + int byte_offset; + int tx_weight; + + /*descriptor parameter*/ + int desc_base; + int desc_len; + int curr_desc; + int prev_desc;/*only used if it is a tx channel*/ + + /*weight setting for WFQ algorithm*/ + int weight; + int default_weight; + + int packet_size; + + /*status of this channel*/ + int control; /*on or off*/ + int xfer_cnt; + int dur; /*descriptor underrun*/ + + /**optional information for the upper layer devices*/ + void *opt[DMA_DESCR_NUM]; + + /*channel operations*/ + int (*open)(struct dma_channel_info *ch); + int (*close)(struct dma_channel_info *ch); + int (*reset)(struct dma_channel_info *ch); + void (*enable_irq)(struct dma_channel_info *ch); + void (*disable_irq)(struct dma_channel_info *ch); +}; + + +struct dma_device_info { + /*device name of this peripheral*/ + const char device_name[16]; + const int max_rx_chan_num; + const int max_tx_chan_num; + int drop_enable; + + int reserved; + + int tx_burst_len; + int rx_burst_len; + int tx_weight; + + int current_tx_chan; + int current_rx_chan; + int num_tx_chan; + int num_rx_chan; + int tx_endianness_mode; + int rx_endianness_mode; + struct dma_channel_info *tx_chan[4]; + struct dma_channel_info *rx_chan[4]; + + /*functions, optional*/ + u8 *(*buffer_alloc)(int len,int *offset, void **opt); + void (*buffer_free)(u8 *dataptr, void *opt); + int (*intr_handler)(struct dma_device_info *dma_dev, int status); + + /* used by peripheral driver only */ + void *priv; +}; + +struct dma_device_info *dma_device_reserve(char *dev_name); +int dma_device_release(struct dma_device_info *dma_dev); +int dma_device_register(struct dma_device_info *dma_dev); +int dma_device_unregister(struct dma_device_info *dma_dev); +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt); +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, + int len, void *opt); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h new file mode 100644 index 000000000..bca8df9fd --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h @@ -0,0 +1,35 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2010 Lantiq + */ +#ifndef __SVIP_IRQ_H +#define __SVIP_IRQ_H + +#define IM_NUM 6 + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160) +#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h new file mode 100644 index 000000000..8ca3285f2 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h @@ -0,0 +1,467 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#ifndef __SVIP_MUX_H +#define __SVIP_MUX_H + +#define LTQ_MUX_P0_PINS 20 +#define LTQ_MUX_P1_PINS 20 +#define LTQ_MUX_P2_PINS 19 +#define LTQ_MUX_P3_PINS 20 +#define LTQ_MUX_P4_PINS 24 + +struct ltq_mux_pin { + int dirin; + int puen; + int altsel0; + int altsel1; +}; + +struct ltq_mux_settings { + const struct ltq_mux_pin *mux_p0; + const struct ltq_mux_pin *mux_p1; + const struct ltq_mux_pin *mux_p2; + const struct ltq_mux_pin *mux_p3; + const struct ltq_mux_pin *mux_p4; +}; + +#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_19 { 0, 0, 1, 0 } + +#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 } +#define LTQ_MUX_P0_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_17 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_16 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 } + +#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_15 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_14 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_13 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 } +#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 } + +#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_12 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_11 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 } +#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 } +#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 } + +#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 } +#define LTQ_MUX_P0_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 } + +#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 } +#define LTQ_MUX_P0_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 } +#define LTQ_MUX_P0_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 } +#define LTQ_MUX_P0_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 } +#define LTQ_MUX_P0_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 } +#define LTQ_MUX_P0_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_19 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_18 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_17 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_16 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_15 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_17 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 } +#define LTQ_MUX_P2_16 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 } +#define LTQ_MUX_P2_15 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 } +#define LTQ_MUX_P2_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 } +#define LTQ_MUX_P2_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 } +#define LTQ_MUX_P2_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_19 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_17 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_16 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_15 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_23 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_22 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_21 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_20 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_19 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_17 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_16 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_15 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 } + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h new file mode 100644 index 000000000..732971185 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h @@ -0,0 +1,23 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#ifndef __SVIP_PMS_H +#define __SVIP_PMS_H + +void svip_sys1_clk_enable(u32 mask); +int svip_sys1_clk_is_enabled(u32 mask); + +void svip_sys2_clk_enable(u32 mask); +int svip_sys2_clk_is_enabled(u32 mask); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h new file mode 100644 index 000000000..7428cccc8 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h @@ -0,0 +1,165 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SYS0_REG_H +#define __SYS0_REG_H + +#define sys0_r32(reg) ltq_r32(&sys0->reg) +#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg) +#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg) + +/** SYS0 register structure */ +struct svip_reg_sys0 { + unsigned long sr; /* 0x0000 */ + unsigned long bcr; /* 0x0004 */ + unsigned long pll1cr; /* 0x0008 */ + unsigned long pll2cr; /* 0x000c */ + unsigned long tscr; /* 0x0010 */ + unsigned long phyclkr; /* 0x0014 */ +}; + +/******************************************************************************* + * SYS0 Status Register + ******************************************************************************/ + +/* Endian select pin (31) */ +#define SYS0_SR_ESEL (0x1 << 31) +#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1) +/* Boot mode pins (27:24) */ +#define SYS0_SR_BMODE (0xf << 24) +#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf) +/* PLL2 Lock (18) */ +#define SYS0_SR_PLL2LOCK (0x1 << 18) +#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1) +/* PLL1 Lock (17) */ +#define SYS0_SR_PLL1LOCK (0x1 << 17) +#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1) +/* Discrete Timing Oscillator Lock (16) */ +#define SYS0_SR_DTOLOCK (0x1 << 16) +#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1) +/* Hardware Reset Indication (1) */ +#define SYS0_SR_HRSTIN (0x1 << 1) +#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1) +#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1) +#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1)) +/* Power-on Reset Indication (0) */ +#define SYS0_SR_POR (0x1 << 0) +#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0) +#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1) +#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SYS0 Boot Control Register + ******************************************************************************/ + +/* Configuration of Boot Source for CPU5 (25) */ +#define SYS0_BCR_BMODECPU5 (0x1 << 25) +#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25) +#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1) +#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25)) +/* Configuration of Boot Source for CPU4 (24) */ +#define SYS0_BCR_BMODECPU4 (0x1 << 24) +#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24) +#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1) +#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24)) +/* Configuration of Boot Source for CPU3 (23) */ +#define SYS0_BCR_BMODECPU3 (0x1 << 23) +#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23) +#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1) +#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23)) +/* Configuration of Boot Source for CPU2 (22) */ +#define SYS0_BCR_BMODECPU2 (0x1 << 22) +#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22) +#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1) +#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22)) +/* Configuration of Boot Source for CPU1 (21) */ +#define SYS0_BCR_BMODECPU1 (0x1 << 21) +#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21) +#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1) +#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21)) +/* Configuration of Boot Source for CPU0 (20:16) */ +#define SYS0_BCR_BMODECPU0 (0x1f << 16) +#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16) +#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f) +#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16)) +/* Configuration of Endianess for CPU5 (5) */ +#define SYS0_BCR_ESELCPU5 (0x1 << 5) +#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5) +#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1) +#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5)) +/* Configuration of Endianess for CPU4 (4) */ +#define SYS0_BCR_ESELCPU4 (0x1 << 4) +#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4) +#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1) +#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4)) +/* Configuration of Endianess for CPU3 (3) */ +#define SYS0_BCR_ESELCPU3 (0x1 << 3) +#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3) +#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1) +#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3)) +/* Configuration of Endianess for CPU2 (2) */ +#define SYS0_BCR_ESELCPU2 (0x1 << 2) +#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2) +#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1) +#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2)) +/* Configuration of Endianess for CPU1 (1) */ +#define SYS0_BCR_ESELCPU1 (0x1 << 1) +#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1) +#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1) +#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1)) +/* Configuration of Endianess for CPU0 (0) */ +#define SYS0_BCR_ESELCPU0 (0x1) +#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0) +#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1) +#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PLL1 Control Register + ******************************************************************************/ + +/* PLL1 Bypass Enable (31) */ +#define SYS0_PLL1CR_OSCBYP (0x1 << 31) +#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31) +#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1) +#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31)) +/* PLL1 Divider Value (1:0) */ +#define SYS0_PLL1CR_PLLDIV (0x3) +#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0) +#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3) +#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * PLL2 Control Register + ******************************************************************************/ + +/* PLL2 clear deepsleep (31) */ +#define SYS0_PLL2CR_CLRDS (0x1 << 31) +#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31) +#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1) +#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31)) +/* PLL2 set deepsleep (30) */ +#define SYS0_PLL2CR_SETDS (0x1 << 30) +#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30) +#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1) +#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30)) +/* PLL2 Fractional division enable (16) */ +#define SYS0_PLL2CR_FRACTEN (0x1 << 16) +#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16) +#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1) +#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16)) +/* PLL2 Fractional division value (9:0) */ +#define SYS0_FRACTVAL (0x3f) +#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0) +#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f) +#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0)) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h new file mode 100644 index 000000000..e0c2e84b1 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h @@ -0,0 +1,370 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SYS1_REG_H +#define __SYS1_REG_H + +#define sys1_r32(reg) ltq_r32(&sys1->reg) +#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg) +#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg) + +/** SYS1 register structure */ +struct svip_reg_sys1 { + unsigned long clksr; /* 0x0000 */ + unsigned long clkenr; /* 0x0004 */ + unsigned long clkclr; /* 0x0008 */ + unsigned long reserved0[1]; + unsigned long l2ccr; /* 0x0010 */ + unsigned long fpicr; /* 0x0014 */ + unsigned long wdtcr; /* 0x0018 */ + unsigned long reserved1[1]; + unsigned long cpucr[6]; /* 0x0020 */ + unsigned long reserved2[2]; + unsigned long rsr; /* 0x0040 */ + unsigned long rreqr; /* 0x0044 */ + unsigned long rrlsr; /* 0x0048 */ + unsigned long rbtr; /* 0x004c */ + unsigned long irncr; /* 0x0050 */ + unsigned long irnicr; /* 0x0054 */ + unsigned long irnen; /* 0x0058 */ + unsigned long reserved3[1]; + unsigned long cpursr[6]; /* 0x0060 */ + unsigned long reserved4[2]; + unsigned long cpusrssr[6]; /* 0x0080 */ + unsigned long reserved5[2]; + unsigned long cpuwrssr[6]; /* 0x00a0 */ +}; + +/******************************************************************************* + * SYS1 Clock Status Register + ******************************************************************************/ +/* (r) Clock Enable for L2C */ +#define SYS1_CLKSR_L2C (0x1 << 31) +/* (r) Clock Enable for DDR2 */ +#define SYS1_CLKSR_DDR2 (0x1 << 30) +/* (r) Clock Enable for SMI2 */ +#define SYS1_CLKSR_SMI2 (0x1 << 29) +/* (r) Clock Enable for SMI1 */ +#define SYS1_CLKSR_SMI1 (0x1 << 28) +/* (r) Clock Enable for SMI0 */ +#define SYS1_CLKSR_SMI0 (0x1 << 27) +/* (r) Clock Enable for FMI0 */ +#define SYS1_CLKSR_FMI0 (0x1 << 26) +/* (r) Clock Enable for PORT0 */ +#define SYS1_CLKSR_PORT0 (0x1 << 0) +/* (r) Clock Enable for PCM3 */ +#define SYS1_CLKSR_PCM3 (0x1 << 19) +/* (r) Clock Enable for PCM2 */ +#define SYS1_CLKSR_PCM2 (0x1 << 18) +/* (r) Clock Enable for PCM1 */ +#define SYS1_CLKSR_PCM1 (0x1 << 17) +/* (r) Clock Enable for PCM0 */ +#define SYS1_CLKSR_PCM0 (0x1 << 16) +/* (r) Clock Enable for ASC1 */ +#define SYS1_CLKSR_ASC1 (0x1 << 15) +/* (r) Clock Enable for ASC0 */ +#define SYS1_CLKSR_ASC0 (0x1 << 14) +/* (r) Clock Enable for SSC2 */ +#define SYS1_CLKSR_SSC2 (0x1 << 13) +/* (r) Clock Enable for SSC1 */ +#define SYS1_CLKSR_SSC1 (0x1 << 12) +/* (r) Clock Enable for SSC0 */ +#define SYS1_CLKSR_SSC0 (0x1 << 11) +/* (r) Clock Enable for GPTC */ +#define SYS1_CLKSR_GPTC (0x1 << 10) +/* (r) Clock Enable for DMA */ +#define SYS1_CLKSR_DMA (0x1 << 9) +/* (r) Clock Enable for FSCT */ +#define SYS1_CLKSR_FSCT (0x1 << 8) +/* (r) Clock Enable for ETHSW */ +#define SYS1_CLKSR_ETHSW (0x1 << 7) +/* (r) Clock Enable for EBU */ +#define SYS1_CLKSR_EBU (0x1 << 6) +/* (r) Clock Enable for TRNG */ +#define SYS1_CLKSR_TRNG (0x1 << 5) +/* (r) Clock Enable for DEU */ +#define SYS1_CLKSR_DEU (0x1 << 4) +/* (r) Clock Enable for PORT3 */ +#define SYS1_CLKSR_PORT3 (0x1 << 3) +/* (r) Clock Enable for PORT2 */ +#define SYS1_CLKSR_PORT2 (0x1 << 2) +/* (r) Clock Enable for PORT1 */ +#define SYS1_CLKSR_PORT1 (0x1 << 1) + +/******************************************************************************* + * SYS1 Clock Enable Register + ******************************************************************************/ +/* (w) Clock Enable Request for L2C */ +#define SYS1_CLKENR_L2C (0x1 << 31) +/* (w) Clock Enable Request for DDR2 */ +#define SYS1_CLKENR_DDR2 (0x1 << 30) +/* (w) Clock Enable Request for SMI2 */ +#define SYS1_CLKENR_SMI2 (0x1 << 29) +/* (w) Clock Enable Request for SMI1 */ +#define SYS1_CLKENR_SMI1 (0x1 << 28) +/* (w) Clock Enable Request for SMI0 */ +#define SYS1_CLKENR_SMI0 (0x1 << 27) +/* (w) Clock Enable Request for FMI0 */ +#define SYS1_CLKENR_FMI0 (0x1 << 26) +/* (w) Clock Enable Request for PORT0 */ +#define SYS1_CLKENR_PORT0 (0x1 << 0) +/* (w) Clock Enable Request for PCM3 */ +#define SYS1_CLKENR_PCM3 (0x1 << 19) +/* (w) Clock Enable Request for PCM2 */ +#define SYS1_CLKENR_PCM2 (0x1 << 18) +/* (w) Clock Enable Request for PCM1 */ +#define SYS1_CLKENR_PCM1 (0x1 << 17) +/* (w) Clock Enable Request for PCM0 */ +#define SYS1_CLKENR_PCM0 (0x1 << 16) +/* (w) Clock Enable Request for ASC1 */ +#define SYS1_CLKENR_ASC1 (0x1 << 15) +/* (w) Clock Enable Request for ASC0 */ +#define SYS1_CLKENR_ASC0 (0x1 << 14) +/* (w) Clock Enable Request for SSC2 */ +#define SYS1_CLKENR_SSC2 (0x1 << 13) +/* (w) Clock Enable Request for SSC1 */ +#define SYS1_CLKENR_SSC1 (0x1 << 12) +/* (w) Clock Enable Request for SSC0 */ +#define SYS1_CLKENR_SSC0 (0x1 << 11) +/* (w) Clock Enable Request for GPTC */ +#define SYS1_CLKENR_GPTC (0x1 << 10) +/* (w) Clock Enable Request for DMA */ +#define SYS1_CLKENR_DMA (0x1 << 9) +/* (w) Clock Enable Request for FSCT */ +#define SYS1_CLKENR_FSCT (0x1 << 8) +/* (w) Clock Enable Request for ETHSW */ +#define SYS1_CLKENR_ETHSW (0x1 << 7) +/* (w) Clock Enable Request for EBU */ +#define SYS1_CLKENR_EBU (0x1 << 6) +/* (w) Clock Enable Request for TRNG */ +#define SYS1_CLKENR_TRNG (0x1 << 5) +/* (w) Clock Enable Request for DEU */ +#define SYS1_CLKENR_DEU (0x1 << 4) +/* (w) Clock Enable Request for PORT3 */ +#define SYS1_CLKENR_PORT3 (0x1 << 3) +/* (w) Clock Enable Request for PORT2 */ +#define SYS1_CLKENR_PORT2 (0x1 << 2) +/* (w) Clock Enable Request for PORT1 */ +#define SYS1_CLKENR_PORT1 (0x1 << 1) + +/******************************************************************************* + * SYS1 Clock Clear Register + ******************************************************************************/ +/* (w) Clock Disable Request for L2C */ +#define SYS1_CLKCLR_L2C (0x1 << 31) +/* (w) Clock Disable Request for DDR2 */ +#define SYS1_CLKCLR_DDR2 (0x1 << 30) +/* (w) Clock Disable Request for SMI2 */ +#define SYS1_CLKCLR_SMI2 (0x1 << 29) +/* (w) Clock Disable Request for SMI1 */ +#define SYS1_CLKCLR_SMI1 (0x1 << 28) +/* (w) Clock Disable Request for SMI0 */ +#define SYS1_CLKCLR_SMI0 (0x1 << 27) +/* (w) Clock Disable Request for FMI0 */ +#define SYS1_CLKCLR_FMI0 (0x1 << 26) +/* (w) Clock Disable Request for PORT0 */ +#define SYS1_CLKCLR_PORT0 (0x1 << 0) +/* (w) Clock Disable Request for PCM3 */ +#define SYS1_CLKCLR_PCM3 (0x1 << 19) +/* (w) Clock Disable Request for PCM2 */ +#define SYS1_CLKCLR_PCM2 (0x1 << 18) +/* (w) Clock Disable Request for PCM1 */ +#define SYS1_CLKCLR_PCM1 (0x1 << 17) +/* (w) Clock Disable Request for PCM0 */ +#define SYS1_CLKCLR_PCM0 (0x1 << 16) +/* (w) Clock Disable Request for ASC1 */ +#define SYS1_CLKCLR_ASC1 (0x1 << 15) +/* (w) Clock Disable Request for ASC0 */ +#define SYS1_CLKCLR_ASC0 (0x1 << 14) +/* (w) Clock Disable Request for SSC2 */ +#define SYS1_CLKCLR_SSC2 (0x1 << 13) +/* (w) Clock Disable Request for SSC1 */ +#define SYS1_CLKCLR_SSC1 (0x1 << 12) +/* (w) Clock Disable Request for SSC0 */ +#define SYS1_CLKCLR_SSC0 (0x1 << 11) +/* (w) Clock Disable Request for GPTC */ +#define SYS1_CLKCLR_GPTC (0x1 << 10) +/* (w) Clock Disable Request for DMA */ +#define SYS1_CLKCLR_DMA (0x1 << 9) +/* (w) Clock Disable Request for FSCT */ +#define SYS1_CLKCLR_FSCT (0x1 << 8) +/* (w) Clock Disable Request for ETHSW */ +#define SYS1_CLKCLR_ETHSW (0x1 << 7) +/* (w) Clock Disable Request for EBU */ +#define SYS1_CLKCLR_EBU (0x1 << 6) +/* (w) Clock Disable Request for TRNG */ +#define SYS1_CLKCLR_TRNG (0x1 << 5) +/* (w) Clock Disable Request for DEU */ +#define SYS1_CLKCLR_DEU (0x1 << 4) +/* (w) Clock Disable Request for PORT3 */ +#define SYS1_CLKCLR_PORT3 (0x1 << 3) +/* (w) Clock Disable Request for PORT2 */ +#define SYS1_CLKCLR_PORT2 (0x1 << 2) +/* (w) Clock Disable Request for PORT1 */ +#define SYS1_CLKCLR_PORT1 (0x1 << 1) + +/******************************************************************************* + * SYS1 FPI Control Register + ******************************************************************************/ + +/* FPI Bus Clock divider (0) */ +#define SYS1_FPICR_FPIDIV (0x1) +#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0) +#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1) +#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SYS1 Clock Control Register for CPUn + ******************************************************************************/ + +/* Enable bit for clock of CPUn (1) */ +#define SYS1_CPUCR_CPUCLKEN (0x1 << 1) +#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1) +#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1) +#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1)) +/* Divider factor for clock of CPUn (0) */ +#define SYS1_CPUCR_CPUDIV (0x1) +#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0) +#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1) +#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SYS1 Reset Request Register + ******************************************************************************/ + +/* HRSTOUT Reset Request (18) */ +#define SYS1_RREQ_HRSTOUT (0x1 << 18) +#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18) +#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18)) + /* FBS0 Reset Request (17) */ +#define SYS1_RREQ_FBS0 (0x1 << 17) +#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17) +#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17)) + /* SUBSYS Reset Request (16) */ +#define SYS1_RREQ_SUBSYS (0x1 << 16) +#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16) +#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16)) + /* Watchdog5 Reset Request (13) */ +#define SYS1_RREQ_WDT5 (0x1 << 13) +#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13) +#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13)) + /* Watchdog4 Reset Request (12) */ +#define SYS1_RREQ_WDT4 (0x1 << 12) +#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12) +#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12)) + /* Watchdog3 Reset Request (11) */ +#define SYS1_RREQ_WDT3 (0x1 << 11) +#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11) +#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11)) + /* Watchdog2 Reset Request (10) */ +#define SYS1_RREQ_WDT2 (0x1 << 10) +#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10) +#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10)) + /* Watchdog1 Reset Request (9) */ +#define SYS1_RREQ_WDT1 (0x1 << 9) +#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9) +#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9)) + /* Watchdog0 Reset Request (8) */ +#define SYS1_RREQ_WDT0 (0x1 << 8) +#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8) +#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8)) + /* CPU5 Reset Request (5) */ +#define SYS1_RREQ_CPU5 (0x1 << 5) +#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5) +#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5)) + /* CPU4 Reset Request (4) */ +#define SYS1_RREQ_CPU4 (0x1 << 4) +#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4) +#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4)) + /* CPU3 Reset Request (3) */ +#define SYS1_RREQ_CPU3 (0x1 << 3) +#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3) +#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3)) + /* CPU2 Reset Request (2) */ +#define SYS1_RREQ_CPU2 (0x1 << 2) +#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2) +#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2)) + /* CPU1 Reset Request (1) */ +#define SYS1_RREQ_CPU1 (0x1 << 1) +#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1) +#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1)) +/* CPU0 Reset Request (0) */ +#define SYS1_RREQ_CPU0 (0x1) +#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0) +#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0)) + +/******************************************************************************* + * SYS1 Reset Release Register + ******************************************************************************/ + +/* HRSTOUT Reset Release (18) */ +#define SYS1_RRLSR_HRSTOUT (0x1 << 18) +#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18) +#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18)) +/* FBS0 Reset Release (17) */ +#define SYS1_RRLSR_FBS0 (0x1 << 17) +#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17) +#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17)) +/* SUBSYS Reset Release (16) */ +#define SYS1_RRLSR_SUBSYS (0x1 << 16) +#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16) +#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16)) +/* Watchdog5 Reset Release (13) */ +#define SYS1_RRLSR_WDT5 (0x1 << 13) +#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13) +#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13)) +/* Watchdog4 Reset Release (12) */ +#define SYS1_RRLSR_WDT4 (0x1 << 12) +#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12) +#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12)) +/* Watchdog3 Reset Release (11) */ +#define SYS1_RRLSR_WDT3 (0x1 << 11) +#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11) +#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11)) +/* Watchdog2 Reset Release (10) */ +#define SYS1_RRLSR_WDT2 (0x1 << 10) +#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10) +#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10)) +/* Watchdog1 Reset Release (9) */ +#define SYS1_RRLSR_WDT1 (0x1 << 9) +#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9) +#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9)) +/* Watchdog0 Reset Release (8) */ +#define SYS1_RRLSR_WDT0 (0x1 << 8) +#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8) +#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8)) +/* CPU5 Reset Release (5) */ +#define SYS1_RRLSR_CPU5 (0x1 << 5) +#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5) +#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5)) +/* CPU4 Reset Release (4) */ +#define SYS1_RRLSR_CPU4 (0x1 << 4) +#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4) +#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4)) +/* CPU3 Reset Release (3) */ +#define SYS1_RRLSR_CPU3 (0x1 << 3) +#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3) +#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3)) +/* CPU2 Reset Release (2) */ +#define SYS1_RRLSR_CPU2 (0x1 << 2) +#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2) +#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2)) +/* CPU1 Reset Release (1) */ +#define SYS1_RRLSR_CPU1 (0x1 << 1) +#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1) +#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1)) +/* CPU0 Reset Release (0) */ +#define SYS1_RRLSR_CPU0 (0x1) +#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0) +#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0)) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h new file mode 100644 index 000000000..ff9f04b4d --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h @@ -0,0 +1,494 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SYS2_REG_H +#define __SYS2_REG_H + +#define sys2_r32(reg) ltq_r32(&sys2->reg) +#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg) +#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg) + +/** SYS2 register structure */ +struct svip_reg_sys2 { + volatile unsigned long clksr; /* 0x0000 */ + volatile unsigned long clkenr; /* 0x0004 */ + volatile unsigned long clkclr; /* 0x0008 */ + volatile unsigned long reserved0[1]; + volatile unsigned long rsr; /* 0x0010 */ + volatile unsigned long rreqr; /* 0x0014 */ + volatile unsigned long rrlsr; /* 0x0018 */ +}; + +/******************************************************************************* + * SYS2 Clock Status Register + ******************************************************************************/ + +/* Clock Enable for PORT4 */ +#define SYS2_CLKSR_PORT4 (0x1 << 27) +#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27) +#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27) +/* Clock Enable for HWSYNC */ +#define SYS2_CLKSR_HWSYNC (0x1 << 26) +#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) & +#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26) + /* Clock Enable for MBS */ +#define SYS2_CLKSR_MBS (0x1 << 25) +#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25) +#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25) + /* Clock Enable for SWINT */ +#define SYS2_CLKSR_SWINT (0x1 << 24) +#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24) +#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24) + /* Clock Enable for HWACC3 */ +#define SYS2_CLKSR_HWACC3 (0x1 << 19) +#define SYS2_CLKSR_HWACC3_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19) + /* Clock Enable for HWACC2 */ +#define SYS2_CLKSR_HWACC2 (0x1 << 18) +#define SYS2_CLKSR_HWACC2_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18) + /* Clock Enable for HWACC1 */ +#define SYS2_CLKSR_HWACC1 (0x1 << 17) +#define SYS2_CLKSR_HWACC1_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17) + /* Clock Enable for HWACC0 */ +#define SYS2_CLKSR_HWACC0 (0x1 << 16) +#define SYS2_CLKSR_HWACC0_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16) + /* Clock Enable for SIF7 */ +#define SYS2_CLKSR_SIF7 (0x1 << 15) +#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15) +#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15) + /* Clock Enable for SIF6 */ +#define SYS2_CLKSR_SIF6 (0x1 << 14) +#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14) +#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14) + /* Clock Enable for SIF5 */ +#define SYS2_CLKSR_SIF5 (0x1 << 13) +#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13) +#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13) + /* Clock Enable for SIF4 */ +#define SYS2_CLKSR_SIF4 (0x1 << 12) +#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12) +#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12) + /* Clock Enable for SIF3 */ +#define SYS2_CLKSR_SIF3 (0x1 << 11) +#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11) +/* Clock Enable for SIF2 */ +#define SYS2_CLKSR_SIF2 (0x1 << 10) +#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10) +/* Clock Enable for SIF1 */ +#define SYS2_CLKSR_SIF1 (0x1 << 9) +#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9) +/* Clock Enable for SIF0 */ +#define SYS2_CLKSR_SIF0 (0x1 << 8) +#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8) +/* Clock Enable for DFEV7 */ +#define SYS2_CLKSR_DFEV7 (0x1 << 7) +#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7) +/* Clock Enable for DFEV6 */ +#define SYS2_CLKSR_DFEV6 (0x1 << 6) +#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6) +/* Clock Enable for DFEV5 */ +#define SYS2_CLKSR_DFEV5 (0x1 << 5) +#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5) +/* Clock Enable for DFEV4 */ +#define SYS2_CLKSR_DFEV4 (0x1 << 4) +#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4) +/* Clock Enable for DFEV3 */ +#define SYS2_CLKSR_DFEV3 (0x1 << 3) +#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3) +/* Clock Enable for DFEV2 */ +#define SYS2_CLKSR_DFEV2 (0x1 << 2) +#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2) +/* Clock Enable for DFEV1 */ +#define SYS2_CLKSR_DFEV1 (0x1 << 1) +#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1) +/* Clock Enable for DFEV0 */ +#define SYS2_CLKSR_DFEV0 (0x1) +#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0) + +/******************************************************************************* + * SYS2 Clock Enable Register + ******************************************************************************/ + +/* Clock Enable Request for PORT4 */ +#define SYS2_CLKENR_PORT4 (0x1 << 27) +#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27) +#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27)) +/* Clock Enable Request for HWSYNC */ +#define SYS2_CLKENR_HWSYNC (0x1 << 26) +#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26) +#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26)) +/* Clock Enable Request for MBS */ +#define SYS2_CLKENR_MBS (0x1 << 25) +#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25) +#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25)) +/* Clock Enable Request for SWINT */ +#define SYS2_CLKENR_SWINT (0x1 << 24) +#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24) +#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24)) +/* Clock Enable Request for HWACC3 */ +#define SYS2_CLKENR_HWACC3 (0x1 << 19) +#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19) +#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19)) +/* Clock Enable Request for HWACC2 */ +#define SYS2_CLKENR_HWACC2 (0x1 << 18) +#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18) +#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18)) +/* Clock Enable Request for HWACC1 */ +#define SYS2_CLKENR_HWACC1 (0x1 << 17) +#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17) +#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17)) +/* Clock Enable Request for HWACC0 */ +#define SYS2_CLKENR_HWACC0 (0x1 << 16) +#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16) +#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16)) +/* Clock Enable Request for SIF7 */ +#define SYS2_CLKENR_SIF7 (0x1 << 15) +#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15) +#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15)) +/* Clock Enable Request for SIF6 */ +#define SYS2_CLKENR_SIF6 (0x1 << 14) +#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14) +#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14)) +/* Clock Enable Request for SIF5 */ +#define SYS2_CLKENR_SIF5 (0x1 << 13) +#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13) +#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13)) +/* Clock Enable Request for SIF4 */ +#define SYS2_CLKENR_SIF4 (0x1 << 12) +#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12) +#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12)) +/* Clock Enable Request for SIF3 */ +#define SYS2_CLKENR_SIF3 (0x1 << 11) +#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11)) +/* Clock Enable Request for SIF2 */ +#define SYS2_CLKENR_SIF2 (0x1 << 10) +#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10)) +/* Clock Enable Request for SIF1 */ +#define SYS2_CLKENR_SIF1 (0x1 << 9) +#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9)) +/* Clock Enable Request for SIF0 */ +#define SYS2_CLKENR_SIF0 (0x1 << 8) +#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8)) +/* Clock Enable Request for DFEV7 */ +#define SYS2_CLKENR_DFEV7 (0x1 << 7) +#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7)) +/* Clock Enable Request for DFEV6 */ +#define SYS2_CLKENR_DFEV6 (0x1 << 6) +#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6)) +/* Clock Enable Request for DFEV5 */ +#define SYS2_CLKENR_DFEV5 (0x1 << 5) +#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5)) +/* Clock Enable Request for DFEV4 */ +#define SYS2_CLKENR_DFEV4 (0x1 << 4) +#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4)) +/* Clock Enable Request for DFEV3 */ +#define SYS2_CLKENR_DFEV3 (0x1 << 3) +#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3)) +/* Clock Enable Request for DFEV2 */ +#define SYS2_CLKENR_DFEV2 (0x1 << 2) +#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2)) +/* Clock Enable Request for DFEV1 */ +#define SYS2_CLKENR_DFEV1 (0x1 << 1) +#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1)) +/* Clock Enable Request for DFEV0 */ +#define SYS2_CLKENR_DFEV0 (0x1) +#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1))) + +/******************************************************************************* + * SYS2 Clock Clear Register + ******************************************************************************/ + +/* Clock Disable Request for PORT4 */ +#define SYS2_CLKCLR_PORT4 (0x1 << 27) +#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27) +#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27)) +/* Clock Disable Request for HWSYNC */ +#define SYS2_CLKCLR_HWSYNC (0x1 << 26) +#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26) +#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26)) +/* Clock Disable Request for MBS */ +#define SYS2_CLKCLR_MBS (0x1 << 25) +#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25) +#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25)) +/* Clock Disable Request for SWINT */ +#define SYS2_CLKCLR_SWINT (0x1 << 24) +#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24) +#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24)) +/* Clock Disable Request for HWACC3 */ +#define SYS2_CLKCLR_HWACC3 (0x1 << 19) +#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19) +#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19)) +/* Clock Disable Request for HWACC2 */ +#define SYS2_CLKCLR_HWACC2 (0x1 << 18) +#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18) +#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18)) +/* Clock Disable Request for HWACC1 */ +#define SYS2_CLKCLR_HWACC1 (0x1 << 17) +#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17) +#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17)) +/* Clock Disable Request for HWACC0 */ +#define SYS2_CLKCLR_HWACC0 (0x1 << 16) +#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16) +#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16)) +/* Clock Disable Request for SIF7 */ +#define SYS2_CLKCLR_SIF7 (0x1 << 15) +#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15) +#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15)) +/* Clock Disable Request for SIF6 */ +#define SYS2_CLKCLR_SIF6 (0x1 << 14) +#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14) +#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14)) +/* Clock Disable Request for SIF5 */ +#define SYS2_CLKCLR_SIF5 (0x1 << 13) +#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13) +#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13)) +/* Clock Disable Request for SIF4 */ +#define SYS2_CLKCLR_SIF4 (0x1 << 12) +#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12) +#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12)) +/* Clock Disable Request for SIF3 */ +#define SYS2_CLKCLR_SIF3 (0x1 << 11) +#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11)) +/* Clock Disable Request for SIF2 */ +#define SYS2_CLKCLR_SIF2 (0x1 << 10) +#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10)) +/* Clock Disable Request for SIF1 */ +#define SYS2_CLKCLR_SIF1 (0x1 << 9) +#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9)) +/* Clock Disable Request for SIF0 */ +#define SYS2_CLKCLR_SIF0 (0x1 << 8) +#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8)) +/* Clock Disable Request for DFEV7 */ +#define SYS2_CLKCLR_DFEV7 (0x1 << 7) +#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7)) +/* Clock Disable Request for DFEV6 */ +#define SYS2_CLKCLR_DFEV6 (0x1 << 6) +#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6)) +/* Clock Disable Request for DFEV5 */ +#define SYS2_CLKCLR_DFEV5 (0x1 << 5) +#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5)) +/* Clock Disable Request for DFEV4 */ +#define SYS2_CLKCLR_DFEV4 (0x1 << 4) +#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4)) +/* Clock Disable Request for DFEV3 */ +#define SYS2_CLKCLR_DFEV3 (0x1 << 3) +#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3)) +/* Clock Disable Request for DFEV2 */ +#define SYS2_CLKCLR_DFEV2 (0x1 << 2) +#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2)) +/* Clock Disable Request for DFEV1 */ +#define SYS2_CLKCLR_DFEV1 (0x1 << 1) +#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1)) +/* Clock Disable Request for DFEV0 */ +#define SYS2_CLKCLR_DFEV0 (0x1) +#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1))) + +/******************************************************************************* + * SYS2 Reset Status Register + ******************************************************************************/ + +/* HWACC3 Reset */ +#define SYS2_RSR_HWACC3 (0x1 << 11) +#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11) +/* HWACC2 Reset */ +#define SYS2_RSR_HWACC2 (0x1 << 10) +#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10) +/* HWACC1 Reset */ +#define SYS2_RSR_HWACC1 (0x1 << 9) +#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9) +/* HWACC0 Reset */ +#define SYS2_RSR_HWACC0 (0x1 << 8) +#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8) +/* DFEV7 Reset */ +#define SYS2_RSR_DFEV7 (0x1 << 7) +#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7) +/* DFEV6 Reset */ +#define SYS2_RSR_DFEV6 (0x1 << 6) +#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6) +/* DFEV5 Reset */ +#define SYS2_RSR_DFEV5 (0x1 << 5) +#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5) +/* DFEV4 Reset */ +#define SYS2_RSR_DFEV4 (0x1 << 4) +#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4) +/* DFEV3 Reset */ +#define SYS2_RSR_DFEV3 (0x1 << 3) +#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3) +/* DFEV2 Reset */ +#define SYS2_RSR_DFEV2 (0x1 << 2) +#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2) +/* DFEV1 Reset */ +#define SYS2_RSR_DFEV1 (0x1 << 1) +#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1) +/* DFEV0 Reset */ +#define SYS2_RSR_DFEV0 (0x1) +#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0) + +/****************************************************************************** + * SYS2 Reset Request Register + ******************************************************************************/ + +/* HWACC3 Reset Request */ +#define SYS2_RREQR_HWACC3 (0x1 << 11) +#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11)) +/* HWACC2 Reset Request */ +#define SYS2_RREQR_HWACC2 (0x1 << 10) +#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10)) +/* HWACC1 Reset Request */ +#define SYS2_RREQR_HWACC1 (0x1 << 9) +#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9)) +/* HWACC0 Reset Request */ +#define SYS2_RREQR_HWACC0 (0x1 << 8) +#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8)) +/* DFEV7 Reset Request */ +#define SYS2_RREQR_DFEV7 (0x1 << 7) +#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7)) +/* DFEV6 Reset Request */ +#define SYS2_RREQR_DFEV6 (0x1 << 6) +#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6)) +/* DFEV5 Reset Request */ +#define SYS2_RREQR_DFEV5 (0x1 << 5) +#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5)) +/* DFEV4 Reset Request */ +#define SYS2_RREQR_DFEV4 (0x1 << 4) +#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4)) +/* DFEV3 Reset Request */ +#define SYS2_RREQR_DFEV3 (0x1 << 3) +#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3)) +/* DFEV2 Reset Request */ +#define SYS2_RREQR_DFEV2 (0x1 << 2) +#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2)) +/* DFEV1 Reset Request */ +#define SYS2_RREQR_DFEV1 (0x1 << 1) +#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1)) +/* DFEV0 Reset Request */ +#define SYS2_RREQR_DFEV0 (0x1) +#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1))) + +/******************************************************************************* + * SYS2 Reset Release Register + ******************************************************************************/ + +/* HWACC3 Reset Release */ +#define SYS2_RRLSR_HWACC3 (0x1 << 11) +#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11)) +/* HWACC2 Reset Release */ +#define SYS2_RRLSR_HWACC2 (0x1 << 10) +#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10)) +/* HWACC1 Reset Release */ +#define SYS2_RRLSR_HWACC1 (0x1 << 9) +#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9)) +/* HWACC0 Reset Release */ +#define SYS2_RRLSR_HWACC0 (0x1 << 8) +#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8)) +/* DFEV7 Reset Release */ +#define SYS2_RRLSR_DFEV7 (0x1 << 7) +#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7)) +/* DFEV6 Reset Release */ +#define SYS2_RRLSR_DFEV6 (0x1 << 6) +#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6)) +/* DFEV5 Reset Release */ +#define SYS2_RRLSR_DFEV5 (0x1 << 5) +#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5)) +/* DFEV4 Reset Release */ +#define SYS2_RRLSR_DFEV4 (0x1 << 4) +#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4)) +/* DFEV3 Reset Release */ +#define SYS2_RRLSR_DFEV3 (0x1 << 3) +#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3)) +/* DFEV2 Reset Release */ +#define SYS2_RRLSR_DFEV2 (0x1 << 2) +#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2)) +/* DFEV1 Reset Release */ +#define SYS2_RRLSR_DFEV1 (0x1 << 1) +#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1)) +/* DFEV0 Reset Release */ +#define SYS2_RRLSR_DFEV0 (0x1) +#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1))) + +#endif /* __SYS2_H */ + |