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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-10-05 10:12:53 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-10-05 10:12:53 +0000
commit5c105d9f3fd086aff195d3849dcf847d6b0bd927 (patch)
tree1229a11f725bfa58aa7c57a76898553bb5f6654a /target/linux/generic/files/crypto/ocf/kirkwood/mvHal
downloadopenwrt-5c105d9f3fd086aff195d3849dcf847d6b0bd927.tar.gz
openwrt-5c105d9f3fd086aff195d3849dcf847d6b0bd927.zip
branch Attitude Adjustment
git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@33625 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/files/crypto/ocf/kirkwood/mvHal')
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mv802_3.h213
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.c277
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h308
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c326
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h178
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h225
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h73
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c100
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h140
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h245
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c110
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h24
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c2513
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h376
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c848
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h262
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c320
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h99
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c296
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h203
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h98
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c1825
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h185
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h419
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h257
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c1048
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h130
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h143
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c1036
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h120
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S163
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h304
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c324
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h123
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c382
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h100
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c348
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h80
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c658
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h113
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.c1697
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h348
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c430
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h128
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c427
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h125
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c462
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h106
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.c591
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h110
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c497
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.h125
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.c662
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h140
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c75
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h74
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h101
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c211
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h423
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h158
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h375
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c376
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h121
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h121
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c207
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h213
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c143
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h151
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c1479
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h191
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c1599
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h179
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S988
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S668
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h192
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h306
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c1855
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h172
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S986
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S528
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h157
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h423
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h179
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c1474
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h192
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c2952
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c748
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h146
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h751
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h700
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h356
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c362
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h118
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h116
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c669
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h134
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h245
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c1006
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h323
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c1047
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h185
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h411
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c1143
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h168
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h751
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c313
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h82
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c1522
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h166
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h233
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c576
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h94
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c249
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h82
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h98
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt4
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c1023
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h121
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S457
-rw-r--r--target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h160
132 files changed, 52716 insertions, 0 deletions
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mv802_3.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mv802_3.h
new file mode 100644
index 000000000..3769dde2f
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mv802_3.h
@@ -0,0 +1,213 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmv802_3h
+#define __INCmv802_3h
+
+
+/* includes */
+#include "mvTypes.h"
+
+/* Defines */
+#define MV_MAX_ETH_DATA 1500
+
+/* 802.3 types */
+#define MV_IP_TYPE 0x0800
+#define MV_IP_ARP_TYPE 0x0806
+#define MV_APPLE_TALK_ARP_TYPE 0x80F3
+#define MV_NOVELL_IPX_TYPE 0x8137
+#define MV_EAPOL_TYPE 0x888e
+
+
+
+/* Encapsulation header for RFC1042 and Ethernet_tunnel */
+
+#define MV_RFC1042_SNAP_HEADER {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00}
+
+#define MV_ETH_SNAP_LSB 0xF8
+
+
+#define MV_MAC_ADDR_SIZE (6)
+#define MV_MAC_STR_SIZE (20)
+#define MV_VLAN_HLEN (4)
+
+/* This macro checks for a multicast mac address */
+#define MV_IS_MULTICAST_MAC(mac) (((mac)[0] & 0x1) == 1)
+
+
+/* This macro checks for an broadcast mac address */
+#define MV_IS_BROADCAST_MAC(mac) \
+ (((mac)[0] == 0xFF) && \
+ ((mac)[1] == 0xFF) && \
+ ((mac)[2] == 0xFF) && \
+ ((mac)[3] == 0xFF) && \
+ ((mac)[4] == 0xFF) && \
+ ((mac)[5] == 0xFF))
+
+
+/* Typedefs */
+typedef struct
+{
+ MV_U8 pDA[MV_MAC_ADDR_SIZE];
+ MV_U8 pSA[MV_MAC_ADDR_SIZE];
+ MV_U16 typeOrLen;
+
+} MV_802_3_HEADER;
+
+enum {
+ MV_IP_PROTO_NULL = 0, /* Dummy protocol for TCP */
+ MV_IP_PROTO_ICMP = 1, /* Internet Control Message Protocol */
+ MV_IP_PROTO_IGMP = 2, /* Internet Group Management Protocol */
+ MV_IP_PROTO_IPIP = 4, /* IPIP tunnels (older KA9Q tunnels use 94) */
+ MV_IP_PROTO_TCP = 6, /* Transmission Control Protocol */
+ MV_IP_PROTO_EGP = 8, /* Exterior Gateway Protocol */
+ MV_IP_PROTO_PUP = 12, /* PUP protocol */
+ MV_IP_PROTO_UDP = 17, /* User Datagram Protocol */
+ MV_IP_PROTO_IDP = 22, /* XNS IDP protocol */
+ MV_IP_PROTO_DCCP = 33, /* Datagram Congestion Control Protocol */
+ MV_IP_PROTO_IPV6 = 41, /* IPv6-in-IPv4 tunnelling */
+ MV_IP_PROTO_RSVP = 46, /* RSVP protocol */
+ MV_IP_PROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */
+ MV_IP_PROTO_ESP = 50, /* Encapsulation Security Payload protocol */
+ MV_IP_PROTO_AH = 51, /* Authentication Header protocol */
+ MV_IP_PROTO_BEETPH = 94, /* IP option pseudo header for BEET */
+ MV_IP_PROTO_PIM = 103,
+ MV_IP_PROTO_COMP = 108, /* Compression Header protocol */
+ MV_IP_PROTO_ZERO_HOP = 114, /* Any 0 hop protocol (IANA) */
+ MV_IP_PROTO_SCTP = 132, /* Stream Control Transport Protocol */
+ MV_IP_PROTO_UDPLITE = 136, /* UDP-Lite (RFC 3828) */
+
+ MV_IP_PROTO_RAW = 255, /* Raw IP packets */
+ MV_IP_PROTO_MAX
+};
+
+typedef struct
+{
+ MV_U8 version;
+ MV_U8 tos;
+ MV_U16 totalLength;
+ MV_U16 identifier;
+ MV_U16 fragmentCtrl;
+ MV_U8 ttl;
+ MV_U8 protocol;
+ MV_U16 checksum;
+ MV_U32 srcIP;
+ MV_U32 dstIP;
+
+} MV_IP_HEADER;
+
+typedef struct
+{
+ MV_U32 spi;
+ MV_U32 seqNum;
+} MV_ESP_HEADER;
+
+#define MV_ICMP_ECHOREPLY 0 /* Echo Reply */
+#define MV_ICMP_DEST_UNREACH 3 /* Destination Unreachable */
+#define MV_ICMP_SOURCE_QUENCH 4 /* Source Quench */
+#define MV_ICMP_REDIRECT 5 /* Redirect (change route) */
+#define MV_ICMP_ECHO 8 /* Echo Request */
+#define MV_ICMP_TIME_EXCEEDED 11 /* Time Exceeded */
+#define MV_ICMP_PARAMETERPROB 12 /* Parameter Problem */
+#define MV_ICMP_TIMESTAMP 13 /* Timestamp Request */
+#define MV_ICMP_TIMESTAMPREPLY 14 /* Timestamp Reply */
+#define MV_ICMP_INFO_REQUEST 15 /* Information Request */
+#define MV_ICMP_INFO_REPLY 16 /* Information Reply */
+#define MV_ICMP_ADDRESS 17 /* Address Mask Request */
+#define MV_ICMP_ADDRESSREPLY 18 /* Address Mask Reply */
+
+typedef struct
+{
+ MV_U8 type;
+ MV_U8 code;
+ MV_U16 checksum;
+ MV_U16 id;
+ MV_U16 sequence;
+
+} MV_ICMP_ECHO_HEADER;
+
+typedef struct
+{
+ MV_U16 source;
+ MV_U16 dest;
+ MV_U32 seq;
+ MV_U32 ack_seq;
+ MV_U16 flags;
+ MV_U16 window;
+ MV_U16 chksum;
+ MV_U16 urg_offset;
+
+} MV_TCP_HEADER;
+
+typedef struct
+{
+ MV_U16 source;
+ MV_U16 dest;
+ MV_U16 len;
+ MV_U16 check;
+
+} MV_UDP_HEADER;
+
+#endif /* __INCmv802_3h */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.c
new file mode 100644
index 000000000..dc0e0cfc4
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.c
@@ -0,0 +1,277 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "mvOs.h"
+#include "mv802_3.h"
+#include "mvCommon.h"
+
+
+/*******************************************************************************
+* mvMacStrToHex - Convert MAC format string to hex.
+*
+* DESCRIPTION:
+* This function convert MAC format string to hex.
+*
+* INPUT:
+* macStr - MAC address string. Fornat of address string is
+* uu:vv:ww:xx:yy:zz, where ":" can be any delimiter.
+*
+* OUTPUT:
+* macHex - MAC in hex format.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex)
+{
+ int i;
+ char tmp[3];
+
+ for(i = 0; i < MV_MAC_ADDR_SIZE; i++)
+ {
+ tmp[0] = macStr[(i * 3) + 0];
+ tmp[1] = macStr[(i * 3) + 1];
+ tmp[2] = '\0';
+ macHex[i] = (MV_U8) (strtol(tmp, NULL, 16));
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvMacHexToStr - Convert MAC in hex format to string format.
+*
+* DESCRIPTION:
+* This function convert MAC in hex format to string format.
+*
+* INPUT:
+* macHex - MAC in hex format.
+*
+* OUTPUT:
+* macStr - MAC address string. String format is uu:vv:ww:xx:yy:zz.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr)
+{
+ int i;
+
+ for(i = 0; i < MV_MAC_ADDR_SIZE; i++)
+ {
+ mvOsSPrintf(&macStr[i * 3], "%02x:", macHex[i]);
+ }
+ macStr[(i * 3) - 1] = '\0';
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSizePrint - Print the given size with size unit description.
+*
+* DESCRIPTION:
+* This function print the given size with size unit description.
+* FOr example when size paramter is 0x180000, the function prints:
+* "size 1MB+500KB"
+*
+* INPUT:
+* size - Size in bytes.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvSizePrint(MV_U32 size)
+{
+ mvOsOutput("size ");
+
+ if(size >= _1G)
+ {
+ mvOsOutput("%3dGB ", size / _1G);
+ size %= _1G;
+ if(size)
+ mvOsOutput("+");
+ }
+ if(size >= _1M )
+ {
+ mvOsOutput("%3dMB ", size / _1M);
+ size %= _1M;
+ if(size)
+ mvOsOutput("+");
+ }
+ if(size >= _1K)
+ {
+ mvOsOutput("%3dKB ", size / _1K);
+ size %= _1K;
+ if(size)
+ mvOsOutput("+");
+ }
+ if(size > 0)
+ {
+ mvOsOutput("%3dB ", size);
+ }
+}
+
+/*******************************************************************************
+* mvHexToBin - Convert hex to binary
+*
+* DESCRIPTION:
+* This function Convert hex to binary.
+*
+* INPUT:
+* pHexStr - hex buffer pointer.
+* size - Size to convert.
+*
+* OUTPUT:
+* pBin - Binary buffer pointer.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size)
+{
+ int j, i;
+ char tmp[3];
+ MV_U8 byte;
+
+ for(j=0, i=0; j<size; j++, i+=2)
+ {
+ tmp[0] = pHexStr[i];
+ tmp[1] = pHexStr[i+1];
+ tmp[2] = '\0';
+ byte = (MV_U8) (strtol(tmp, NULL, 16) & 0xFF);
+ pBin[j] = byte;
+ }
+}
+
+void mvAsciiToHex(const char* asciiStr, char* hexStr)
+{
+ int i=0;
+
+ while(asciiStr[i] != 0)
+ {
+ mvOsSPrintf(&hexStr[i*2], "%02x", asciiStr[i]);
+ i++;
+ }
+ hexStr[i*2] = 0;
+}
+
+
+void mvBinToHex(const MV_U8* bin, char* hexStr, int size)
+{
+ int i;
+
+ for(i=0; i<size; i++)
+ {
+ mvOsSPrintf(&hexStr[i*2], "%02x", bin[i]);
+ }
+ hexStr[i*2] = '\0';
+}
+
+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size)
+{
+ int i;
+
+ for(i=0; i<size; i++)
+ {
+ mvOsSPrintf(&asciiStr[i*2], "%c", bin[i]);
+ }
+ asciiStr[i*2] = '\0';
+}
+
+/*******************************************************************************
+* mvLog2 -
+*
+* DESCRIPTION:
+* Calculate the Log2 of a given number.
+*
+* INPUT:
+* num - A number to calculate the Log2 for.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Log 2 of the input number, or 0xFFFFFFFF if input is 0.
+*
+*******************************************************************************/
+MV_U32 mvLog2(MV_U32 num)
+{
+ MV_U32 result = 0;
+ if(num == 0)
+ return 0xFFFFFFFF;
+ while(num != 1)
+ {
+ num = num >> 1;
+ result++;
+ }
+ return result;
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h
new file mode 100644
index 000000000..c8e9ce100
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h
@@ -0,0 +1,308 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+
+#ifndef __INCmvCommonh
+#define __INCmvCommonh
+
+#include "mvTypes.h"
+
+/* Swap tool */
+
+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */
+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \
+ ((X&0xf0) >> 4) | \
+ ((X&0xf00) << 4) | \
+ ((X&0xf000) >> 4))
+
+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */
+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \
+ ((X&0xf0) >> 4) | \
+ ((X&0xf00) << 4) | \
+ ((X&0xf000) >> 4) | \
+ ((X&0xf0000) << 4) | \
+ ((X&0xf00000) >> 4) | \
+ ((X&0xf000000) << 4) | \
+ ((X&0xf0000000) >> 4))
+
+/* 16bit byte swap. For example 0x1122 -> 0x2211 */
+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8))
+
+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */
+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
+ (((X)&0xff00)<<8) | \
+ (((X)&0xff0000)>>8) | \
+ (((X)&0xff000000)>>24))
+
+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */
+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \
+ (((X)&0xff00ULL)<<40) | \
+ (((X)&0xff0000ULL)<<24) | \
+ (((X)&0xff000000ULL)<<8) | \
+ (((X)&0xff00000000ULL)>>8) | \
+ (((X)&0xff0000000000ULL)>>24) | \
+ (((X)&0xff000000000000ULL)>>40) | \
+ (((X)&0xff00000000000000ULL)>>56)))
+
+/* Endianess macros. */
+#if defined(MV_CPU_LE)
+ #define MV_16BIT_LE(X) (X)
+ #define MV_32BIT_LE(X) (X)
+ #define MV_64BIT_LE(X) (X)
+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X)
+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X)
+#elif defined(MV_CPU_BE)
+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X)
+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X)
+ #define MV_16BIT_BE(X) (X)
+ #define MV_32BIT_BE(X) (X)
+ #define MV_64BIT_BE(X) (X)
+#else
+ #error "CPU endianess isn't defined!\n"
+#endif
+
+
+/* Bit field definitions */
+#define NO_BIT 0x00000000
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+/* Handy sizes */
+#define _1K 0x00000400
+#define _2K 0x00000800
+#define _4K 0x00001000
+#define _8K 0x00002000
+#define _16K 0x00004000
+#define _32K 0x00008000
+#define _64K 0x00010000
+#define _128K 0x00020000
+#define _256K 0x00040000
+#define _512K 0x00080000
+
+#define _1M 0x00100000
+#define _2M 0x00200000
+#define _4M 0x00400000
+#define _8M 0x00800000
+#define _16M 0x01000000
+#define _32M 0x02000000
+#define _64M 0x04000000
+#define _128M 0x08000000
+#define _256M 0x10000000
+#define _512M 0x20000000
+
+#define _1G 0x40000000
+#define _2G 0x80000000
+
+/* Tclock and Sys clock define */
+#define _100MHz 100000000
+#define _125MHz 125000000
+#define _133MHz 133333334
+#define _150MHz 150000000
+#define _160MHz 160000000
+#define _166MHz 166666667
+#define _175MHz 175000000
+#define _178MHz 178000000
+#define _183MHz 183333334
+#define _187MHz 187000000
+#define _192MHz 192000000
+#define _194MHz 194000000
+#define _200MHz 200000000
+#define _233MHz 233333334
+#define _250MHz 250000000
+#define _266MHz 266666667
+#define _300MHz 300000000
+
+/* For better address window table readability */
+#define EN MV_TRUE
+#define DIS MV_FALSE
+#define N_A -1 /* Not applicable */
+
+/* Cache configuration options for memory (DRAM, SRAM, ... ) */
+
+/* Memory uncached, HW or SW cache coherency is not needed */
+#define MV_UNCACHED 0
+/* Memory cached, HW cache coherency supported in WriteThrough mode */
+#define MV_CACHE_COHER_HW_WT 1
+/* Memory cached, HW cache coherency supported in WriteBack mode */
+#define MV_CACHE_COHER_HW_WB 2
+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
+#define MV_CACHE_COHER_SW 3
+
+
+/* Macro for testing aligment. Positive if number is NOT aligned */
+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1))
+
+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */
+#define MV_ALIGN_UP(number, align) \
+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number))
+
+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */
+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1))
+
+/* This macro returns absolute value */
+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number))
+
+
+/* Bit fields manipulation macros */
+
+/* An integer word which its 'x' bit is set */
+#define MV_BIT_MASK(bitNum) (1 << (bitNum) )
+
+/* Checks wheter bit 'x' in integer word is set */
+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) )
+
+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */
+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) )
+
+/* Set bit 'x' in integer word (RMW) */
+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) )
+
+/* Invert bit 'x' in integer word (RMW) */
+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) )
+
+/* Get the min between 'a' or 'b' */
+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b))
+
+/* Get the max between 'a' or 'b' */
+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a))
+
+/* Temporary */
+#define mvOsDivide(num, div) \
+({ \
+ int i=0, rem=(num); \
+ \
+ while(rem >= (div)) \
+ { \
+ rem -= (div); \
+ i++; \
+ } \
+ (i); \
+})
+
+/* Temporary */
+#define mvOsReminder(num, div) \
+({ \
+ int rem = (num); \
+ \
+ while(rem >= (div)) \
+ rem -= (div); \
+ (rem); \
+})
+
+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \
+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)
+
+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0))
+
+#ifndef MV_ASMLANGUAGE
+/* mvCommon API list */
+
+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size);
+void mvAsciiToHex(const char* asciiStr, char* hexStr);
+void mvBinToHex(const MV_U8* bin, char* hexStr, int size);
+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size);
+
+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex);
+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr);
+void mvSizePrint(MV_U32);
+
+MV_U32 mvLog2(MV_U32 num);
+
+#endif /* MV_ASMLANGUAGE */
+
+
+#endif /* __INCmvCommonh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt
new file mode 100644
index 000000000..38a926440
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.4
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c
new file mode 100644
index 000000000..087f36d32
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c
@@ -0,0 +1,326 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+
+/* includes */
+#include "mvOs.h"
+#include "mv802_3.h"
+#include "mvCommon.h"
+#include "mvDebug.h"
+
+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros
+ * mvDebug - map of bits (one for each module) bit=1 means enable
+ * debug code and messages for this module
+ * mvModuleDebug - array of 32 bits varables one for each module
+ */
+MV_U32 mvDebug = 0;
+MV_U32 mvDebugModules[MV_MODULE_MAX];
+
+/* Init mvModuleDebug array to default values */
+void mvDebugInit(void)
+{
+ int bit;
+
+ mvDebug = 0;
+ for(bit=0; bit<MV_MODULE_MAX; bit++)
+ {
+ mvDebugModules[bit] = MV_DEBUG_FLAG_ERR | MV_DEBUG_FLAG_STATS;
+ mvDebug |= MV_BIT_MASK(bit);
+ }
+}
+
+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable)
+{
+ if (isEnable)
+ {
+ MV_BIT_SET(mvDebug, module);
+ }
+ else
+ MV_BIT_CLEAR(mvDebug, module);
+}
+
+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags)
+{
+ mvDebugModules[module] |= flags;
+}
+
+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags)
+{
+ mvDebugModules[module] &= ~flags;
+}
+
+/* Dump memory in specific format:
+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8
+ */
+void mvDebugMemDump(void* addr, int size, int access)
+{
+ int i, j;
+ MV_U32 memAddr = (MV_U32)addr;
+
+ if(access == 0)
+ access = 1;
+
+ if( (access != 4) && (access != 2) && (access != 1) )
+ {
+ mvOsPrintf("%d wrong access size. Access must be 1 or 2 or 4\n",
+ access);
+ return;
+ }
+ memAddr = MV_ALIGN_DOWN( (unsigned int)addr, 4);
+ size = MV_ALIGN_UP(size, 4);
+ addr = (void*)MV_ALIGN_DOWN( (unsigned int)addr, access);
+ while(size > 0)
+ {
+ mvOsPrintf("%08x: ", memAddr);
+ i = 0;
+ /* 32 bytes in the line */
+ while(i < 32)
+ {
+ if(memAddr >= (MV_U32)addr)
+ {
+ switch(access)
+ {
+ case 1:
+ if( memAddr == CPU_PHY_MEM(memAddr) )
+ {
+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr));
+ }
+ else
+ {
+ mvOsPrintf("%02x ", *((MV_U8*)memAddr));
+ }
+ break;
+
+ case 2:
+ if( memAddr == CPU_PHY_MEM(memAddr) )
+ {
+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr));
+ }
+ else
+ {
+ mvOsPrintf("%04x ", *((MV_U16*)memAddr));
+ }
+ break;
+
+ case 4:
+ if( memAddr == CPU_PHY_MEM(memAddr) )
+ {
+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr));
+ }
+ else
+ {
+ mvOsPrintf("%08x ", *((MV_U32*)memAddr));
+ }
+ break;
+ }
+ }
+ else
+ {
+ for(j=0; j<(access*2+1); j++)
+ mvOsPrintf(" ");
+ }
+ i += access;
+ memAddr += access;
+ size -= access;
+ if(size <= 0)
+ break;
+ }
+ mvOsPrintf("\n");
+ }
+}
+
+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access)
+{
+ if(pBufInfo == NULL)
+ {
+ mvOsPrintf("\n!!! pBufInfo = NULL\n");
+ return;
+ }
+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n",
+ (unsigned int)pBufInfo,
+ (unsigned int)pBufInfo->cmdSts,
+ (unsigned int)pBufInfo->pBuff,
+ (unsigned int)pBufInfo->bufSize);
+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n",
+ (unsigned int)pBufInfo->pData,
+ (unsigned int)pBufInfo->byteCnt,
+ (unsigned int)pBufInfo->pNextBufInfo,
+ (unsigned int)pBufInfo->userInfo1,
+ (unsigned int)pBufInfo->userInfo2);
+ if(pBufInfo->pData != NULL)
+ {
+ if(size > pBufInfo->byteCnt)
+ size = pBufInfo->byteCnt;
+ mvDebugMemDump(pBufInfo->pData, size, access);
+ }
+}
+
+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access)
+{
+ int frag, len;
+
+ if(pPktInfo == NULL)
+ {
+ mvOsPrintf("\n!!! pPktInfo = NULL\n");
+ return;
+ }
+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n",
+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize,
+ pPktInfo->pFrags, pPktInfo->osInfo);
+
+ for(frag=0; frag<pPktInfo->numFrags; frag++)
+ {
+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n",
+ frag, pPktInfo->pFrags[frag].bufVirtPtr,
+ pPktInfo->pFrags[frag].bufSize);
+ if(size > 0)
+ {
+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size);
+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access);
+ size -= len;
+ }
+ }
+
+}
+
+void mvDebugPrintIpAddr(MV_U32 ipAddr)
+{
+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF),
+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF));
+}
+
+void mvDebugPrintMacAddr(const MV_U8* pMacAddr)
+{
+ int i;
+
+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]);
+ for(i=1; i<MV_MAC_ADDR_SIZE; i++)
+ {
+ mvOsPrintf(":%02x", pMacAddr[i]);
+ }
+ /* mvOsPrintf("\n");*/
+}
+
+
+/******* There are three functions deals with MV_DEBUG_TIMES structure ********/
+
+/* Reset MV_DEBUG_TIMES entry */
+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* pName)
+{
+ pTimeEntry->begin = 0;
+ pTimeEntry->count = count;
+ pTimeEntry->end = 0;
+ pTimeEntry->left = pTimeEntry->count;
+ pTimeEntry->total = 0;
+ pTimeEntry->min = 0xFFFFFFFF;
+ pTimeEntry->max = 0x0;
+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1);
+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0';
+}
+
+/* Print out MV_DEBUG_TIMES entry */
+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle)
+{
+ int num;
+
+ if(isTitle == MV_TRUE)
+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n");
+
+ num = pTimeEntry->count-pTimeEntry->left;
+ if(num > 0)
+ {
+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n",
+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num,
+ pTimeEntry->min, pTimeEntry->max);
+ }
+}
+
+/* Update MV_DEBUG_TIMES entry */
+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry)
+{
+ MV_U32 delta;
+
+ if(pTimeEntry->left > 0)
+ {
+ if(pTimeEntry->end <= pTimeEntry->begin)
+ {
+ delta = pTimeEntry->begin - pTimeEntry->end;
+ }
+ else
+ {
+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin;
+ }
+ pTimeEntry->total += delta;
+
+ if(delta < pTimeEntry->min)
+ pTimeEntry->min = delta;
+
+ if(delta > pTimeEntry->max)
+ pTimeEntry->max = delta;
+
+ pTimeEntry->left--;
+ }
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h
new file mode 100644
index 000000000..e4975bed5
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h
@@ -0,0 +1,178 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+
+#ifndef __INCmvDebugh
+#define __INCmvDebugh
+
+/* includes */
+#include "mvTypes.h"
+
+typedef enum
+{
+ MV_MODULE_INVALID = -1,
+ MV_MODULE_ETH = 0,
+ MV_MODULE_IDMA,
+ MV_MODULE_XOR,
+ MV_MODULE_TWASI,
+ MV_MODULE_MGI,
+ MV_MODULE_USB,
+ MV_MODULE_CESA,
+
+ MV_MODULE_MAX
+}MV_MODULE_ID;
+
+/* Define generic flags useful for most of modules */
+#define MV_DEBUG_FLAG_ALL (0)
+#define MV_DEBUG_FLAG_INIT (1 << 0)
+#define MV_DEBUG_FLAG_RX (1 << 1)
+#define MV_DEBUG_FLAG_TX (1 << 2)
+#define MV_DEBUG_FLAG_ERR (1 << 3)
+#define MV_DEBUG_FLAG_TRACE (1 << 4)
+#define MV_DEBUG_FLAG_DUMP (1 << 5)
+#define MV_DEBUG_FLAG_CACHE (1 << 6)
+#define MV_DEBUG_FLAG_IOCTL (1 << 7)
+#define MV_DEBUG_FLAG_STATS (1 << 8)
+
+extern MV_U32 mvDebug;
+extern MV_U32 mvDebugModules[MV_MODULE_MAX];
+
+#ifdef MV_DEBUG
+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg
+# define MV_DEBUG_CODE(module, flags, code) code
+#elif defined(MV_RT_DEBUG)
+# define MV_DEBUG_PRINT(module, flags, msg) \
+ if( (mvDebug & (1<<(module))) && \
+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \
+ mvOsPrintf msg
+# define MV_DEBUG_CODE(module, flags, code) \
+ if( (mvDebug & (1<<(module))) && \
+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \
+ code
+#else
+# define MV_DEBUG_PRINT(module, flags, msg)
+# define MV_DEBUG_CODE(module, flags, code)
+#endif
+
+
+
+/* typedefs */
+
+/* time measurement structure used to check how much time pass between
+ * two points
+ */
+typedef struct {
+ char name[20]; /* name of the entry */
+ unsigned long begin; /* time measured on begin point */
+ unsigned long end; /* time measured on end point */
+ unsigned long total; /* Accumulated time */
+ unsigned long left; /* The rest measurement actions */
+ unsigned long count; /* Maximum measurement actions */
+ unsigned long min; /* Minimum time from begin to end */
+ unsigned long max; /* Maximum time from begin to end */
+} MV_DEBUG_TIMES;
+
+
+/* mvDebug.h API list */
+
+/****** Error Recording ******/
+
+/* Dump memory in specific format:
+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8
+ */
+void mvDebugMemDump(void* addr, int size, int access);
+
+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access);
+
+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access);
+
+void mvDebugPrintIpAddr(MV_U32 ipAddr);
+
+void mvDebugPrintMacAddr(const MV_U8* pMacAddr);
+
+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/
+
+/* Reset MV_DEBUG_TIMES entry */
+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name);
+
+/* Update MV_DEBUG_TIMES entry */
+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry);
+
+/* Print out MV_DEBUG_TIMES entry */
+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle);
+
+
+/******** General ***********/
+
+/* Change value of mvDebugPrint global variable */
+
+void mvDebugInit(void);
+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable);
+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags);
+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags);
+
+
+#endif /* __INCmvDebug.h */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h
new file mode 100644
index 000000000..478209407
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h
@@ -0,0 +1,225 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDeviceIdh
+#define __INCmvDeviceIdh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines */
+#define MARVELL_VEN_ID 0x11ab
+
+/* Disco-3 */
+#define MV64460_DEV_ID 0x6480
+#define MV64460B_DEV_ID 0x6485
+#define MV64430_DEV_ID 0x6420
+
+/* Disco-5 */
+#define MV64560_DEV_ID 0x6450
+
+/* Disco-6 */
+#define MV64660_DEV_ID 0x6460
+
+/* Orion */
+#define MV_1181_DEV_ID 0x1181
+#define MV_5181_DEV_ID 0x5181
+#define MV_5281_DEV_ID 0x5281
+#define MV_5182_DEV_ID 0x5182
+#define MV_8660_DEV_ID 0x8660
+#define MV_5180_DEV_ID 0x5180
+#define MV_5082_DEV_ID 0x5082
+#define MV_1281_DEV_ID 0x1281
+#define MV_6082_DEV_ID 0x6082
+#define MV_6183_DEV_ID 0x6183
+#define MV_6183L_DEV_ID 0x6083
+
+#define MV_5281_D0_REV 0x4
+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV)
+#define MV_5281_D0_NAME "88F5281 D0"
+
+#define MV_5281_D1_REV 0x5
+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV)
+#define MV_5281_D1_NAME "88F5281 D1"
+
+#define MV_5281_D2_REV 0x6
+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV)
+#define MV_5281_D2_NAME "88F5281 D2"
+
+
+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */
+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/
+#define MV_5181_B0_REV 0x2
+#define MV_5181_B1_REV 0x3
+#define MV_5182_A1_REV 0x1
+#define MV_5180N_B1_REV 0x3
+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV)
+
+
+
+/* kw */
+#define MV_6281_DEV_ID 0x6281
+#define MV_6192_DEV_ID 0x6192
+#define MV_6190_DEV_ID 0x6190
+#define MV_6180_DEV_ID 0x6180
+
+#define MV_6281_A0_REV 0x2
+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV)
+#define MV_6281_A0_NAME "88F6281 A0"
+
+#define MV_6192_A0_REV 0x2
+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV)
+#define MV_6192_A0_NAME "88F6192 A0"
+
+#define MV_6190_A0_REV 0x2
+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV)
+#define MV_6190_A0_NAME "88F6190 A0"
+
+#define MV_6180_A0_REV 0x2
+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV)
+#define MV_6180_A0_NAME "88F6180 A0"
+
+#define MV_6281_A1_REV 0x3
+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV)
+#define MV_6281_A1_NAME "88F6281 A1"
+
+#define MV_6192_A1_REV 0x3
+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV)
+#define MV_6192_A1_NAME "88F6192 A1"
+
+#define MV_6190_A1_REV 0x3
+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV)
+#define MV_6190_A1_NAME "88F6190 A1"
+
+#define MV_6180_A1_REV 0x3
+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV)
+#define MV_6180_A1_NAME "88F6180 A1"
+
+#define MV_88F6XXX_A0_REV 0x2
+#define MV_88F6XXX_A1_REV 0x3
+/* Disco-Duo */
+#define MV_78XX0_ZY_DEV_ID 0x6381
+#define MV_78XX0_ZY_NAME "MV78X00"
+
+#define MV_78XX0_Z0_REV 0x1
+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV)
+#define MV_78XX0_Z0_NAME "78X00 Z0"
+
+#define MV_78XX0_Y0_REV 0x2
+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV)
+#define MV_78XX0_Y0_NAME "78X00 Y0"
+
+#define MV_78XX0_DEV_ID 0x7800
+#define MV_78XX0_NAME "MV78X00"
+
+#define MV_76100_DEV_ID 0x7610
+#define MV_78200_DEV_ID 0x7820
+#define MV_78100_DEV_ID 0x7810
+#define MV_78XX0_A0_REV 0x1
+#define MV_78XX0_A1_REV 0x2
+
+#define MV_76100_NAME "MV76100"
+#define MV_78100_NAME "MV78100"
+#define MV_78200_NAME "MV78200"
+
+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV)
+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV)
+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV)
+
+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV)
+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV)
+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV)
+
+#define MV_76100_A0_NAME "MV76100 A0"
+#define MV_78100_A0_NAME "MV78100 A0"
+#define MV_78200_A0_NAME "MV78200 A0"
+#define MV_78XX0_A0_NAME "MV78XX0 A0"
+
+#define MV_76100_A1_NAME "MV76100 A1"
+#define MV_78100_A1_NAME "MV78100 A1"
+#define MV_78200_A1_NAME "MV78200 A1"
+#define MV_78XX0_A1_NAME "MV78XX0 A1"
+
+/*MV88F632X family*/
+#define MV_6321_DEV_ID 0x6321
+#define MV_6322_DEV_ID 0x6322
+#define MV_6323_DEV_ID 0x6323
+
+#define MV_6321_NAME "88F6321"
+#define MV_6322_NAME "88F6322"
+#define MV_6323_NAME "88F6323"
+
+#define MV_632X_A1_REV 0x2
+
+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV)
+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV)
+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV)
+
+#define MV_6321_A1_NAME "88F6321 A1"
+#define MV_6322_A1_NAME "88F6322 A1"
+#define MV_6323_A1_NAME "88F6323 A1"
+
+
+#endif /* __INCmvDeviceIdh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h
new file mode 100644
index 000000000..3bfcfe19e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h
@@ -0,0 +1,73 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvHalVerh
+#define __INCmvHalVerh
+
+/* Defines */
+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7"
+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4"
+
+#endif /* __INCmvHalVerh */ \ No newline at end of file
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c
new file mode 100644
index 000000000..41ca7ceba
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* Copyright 2003, Marvell Semiconductor Israel LTD. *
+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
+* *
+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). *
+********************************************************************************
+* mvQueue.c
+*
+* FILENAME: $Workfile: mvStack.c $
+* REVISION: $Revision: 1.1 $
+* LAST UPDATE: $Modtime: $
+*
+* DESCRIPTION:
+* This file implements simple Stack LIFO functionality.
+*******************************************************************************/
+
+/* includes */
+#include "mvOs.h"
+#include "mvTypes.h"
+#include "mvDebug.h"
+#include "mvStack.h"
+
+/* defines */
+
+
+/* Public functions */
+
+
+/* Purpose: Create new stack
+ * Inputs:
+ * - MV_U32 noOfElements - maximum number of elements in the stack.
+ * Each element 4 bytes size
+ * Return: void* - pointer to created stack.
+ */
+void* mvStackCreate(int numOfElements)
+{
+ MV_STACK* pStack;
+ MV_U32* pStackElements;
+
+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK));
+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32));
+ if( (pStack == NULL) || (pStackElements == NULL) )
+ {
+ mvOsPrintf("mvStack: Can't create new stack\n");
+ return NULL;
+ }
+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32));
+ pStack->numOfElements = numOfElements;
+ pStack->stackIdx = 0;
+ pStack->stackElements = pStackElements;
+
+ return pStack;
+}
+
+/* Purpose: Delete existing stack
+ * Inputs:
+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function
+ *
+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid.
+ * MV_OK - Success.
+ */
+MV_STATUS mvStackDelete(void* stackHndl)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+ if( (pStack == NULL) || (pStack->stackElements == NULL) )
+ return MV_NOT_FOUND;
+
+ mvOsFree(pStack->stackElements);
+ mvOsFree(pStack);
+
+ return MV_OK;
+}
+
+
+/* PrintOut status of the stack */
+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements)
+{
+ int i;
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n",
+ stackHndl, pStack->stackElements, pStack->numOfElements,
+ pStack->stackIdx);
+ if(isPrintElements == MV_TRUE)
+ {
+ for(i=0; i<pStack->stackIdx; i++)
+ {
+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]);
+ }
+ }
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h
new file mode 100644
index 000000000..e247e61c2
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h
@@ -0,0 +1,140 @@
+/*******************************************************************************
+* Copyright 2003, Marvell Semiconductor Israel LTD. *
+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. *
+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, *
+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
+* *
+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL *
+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. *
+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). *
+********************************************************************************
+* mvStack.h - Header File for :
+*
+* FILENAME: $Workfile: mvStack.h $
+* REVISION: $Revision: 1.1 $
+* LAST UPDATE: $Modtime: $
+*
+* DESCRIPTION:
+* This file defines simple Stack (LIFO) functionality.
+*
+*******************************************************************************/
+
+#ifndef __mvStack_h__
+#define __mvStack_h__
+
+
+/* includes */
+#include "mvTypes.h"
+
+
+/* defines */
+
+
+/* typedefs */
+/* Data structure describes general purpose Stack */
+typedef struct
+{
+ int stackIdx;
+ int numOfElements;
+ MV_U32* stackElements;
+} MV_STACK;
+
+static INLINE MV_BOOL mvStackIsFull(void* stackHndl)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+ if(pStack->stackIdx == pStack->numOfElements)
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+
+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+ if(pStack->stackIdx == 0)
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+/* Purpose: Push new element to stack
+ * Inputs:
+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function.
+ * - MV_U32 value - New element.
+ *
+ * Return: MV_STATUS MV_FULL - Failure. Stack is full.
+ * MV_OK - Success. Element is put to stack.
+ */
+static INLINE void mvStackPush(void* stackHndl, MV_U32 value)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+#ifdef MV_RT_DEBUG
+ if(pStack->stackIdx == pStack->numOfElements)
+ {
+ mvOsPrintf("mvStackPush: Stack is FULL\n");
+ return;
+ }
+#endif /* MV_RT_DEBUG */
+
+ pStack->stackElements[pStack->stackIdx] = value;
+ pStack->stackIdx++;
+}
+
+/* Purpose: Pop element from the top of stack and copy it to "pValue"
+ * Inputs:
+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function.
+ * - MV_U32 value - Element in the top of stack.
+ *
+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty.
+ * MV_OK - Success. Element is removed from the stack and
+ * copied to pValue argument
+ */
+static INLINE MV_U32 mvStackPop(void* stackHndl)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+#ifdef MV_RT_DEBUG
+ if(pStack->stackIdx == 0)
+ {
+ mvOsPrintf("mvStackPop: Stack is EMPTY\n");
+ return 0;
+ }
+#endif /* MV_RT_DEBUG */
+
+ pStack->stackIdx--;
+ return pStack->stackElements[pStack->stackIdx];
+}
+
+static INLINE int mvStackIndex(void* stackHndl)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+ return pStack->stackIdx;
+}
+
+static INLINE int mvStackFreeElements(void* stackHndl)
+{
+ MV_STACK* pStack = (MV_STACK*)stackHndl;
+
+ return (pStack->numOfElements - pStack->stackIdx);
+}
+
+/* mvStack.h API list */
+
+/* Create new Stack */
+void* mvStackCreate(int numOfElements);
+
+/* Delete existing stack */
+MV_STATUS mvStackDelete(void* stackHndl);
+
+/* Print status of the stack */
+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements);
+
+#endif /* __mvStack_h__ */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h
new file mode 100644
index 000000000..de212a141
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h
@@ -0,0 +1,245 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvTypesh
+#define __INCmvTypesh
+
+/* Defines */
+
+/* The following is a list of Marvell status */
+#define MV_ERROR (-1)
+#define MV_OK (0x00) /* Operation succeeded */
+#define MV_FAIL (0x01) /* Operation failed */
+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
+#define MV_BAD_PTR (0x05) /* Illegal pointer value */
+#define MV_BAD_SIZE (0x06) /* Illegal size */
+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
+#define MV_SET_ERROR (0x08) /* Set operation failed */
+#define MV_GET_ERROR (0x09) /* Get operation failed */
+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
+#define MV_NOT_FOUND (0x0B) /* Item not found */
+#define MV_NO_MORE (0x0C) /* No more items found */
+#define MV_NO_SUCH (0x0D) /* No such item */
+#define MV_TIMEOUT (0x0E) /* Time Out */
+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */
+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
+#define MV_HW_ERROR (0x17) /* Hardware error */
+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
+#define MV_NOT_STARTED (0x1D) /* Not started yet */
+#define MV_BUSY (0x1E) /* Item is busy. */
+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
+#define MV_WRITE_PROTECT (0x22) /* Write protected */
+
+
+#define MV_INVALID (int)(-1)
+
+#define MV_FALSE 0
+#define MV_TRUE (!(MV_FALSE))
+
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+
+#ifndef MV_ASMLANGUAGE
+/* typedefs */
+
+typedef char MV_8;
+typedef unsigned char MV_U8;
+
+typedef int MV_32;
+typedef unsigned int MV_U32;
+
+typedef short MV_16;
+typedef unsigned short MV_U16;
+
+#ifdef MV_PPC64
+typedef long MV_64;
+typedef unsigned long MV_U64;
+#else
+typedef long long MV_64;
+typedef unsigned long long MV_U64;
+#endif
+
+typedef long MV_LONG; /* 32/64 */
+typedef unsigned long MV_ULONG; /* 32/64 */
+
+typedef int MV_STATUS;
+typedef int MV_BOOL;
+typedef void MV_VOID;
+typedef float MV_FLOAT;
+
+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */
+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */
+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/
+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */
+
+typedef MV_U32 MV_KHZ;
+typedef MV_U32 MV_MHZ;
+typedef MV_U32 MV_HZ;
+
+
+/* This enumerator describes the set of commands that can be applied on */
+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */
+/* status (see MV_STATE enumerator) */
+/* Start can be applied only when status is IDLE */
+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */
+/* Pause can be applied only when status is ACTIVE */
+/* Restart can be applied only when status is PAUSED */
+typedef enum _mvCommand
+{
+ MV_START, /* Start */
+ MV_STOP, /* Stop */
+ MV_PAUSE, /* Pause */
+ MV_RESTART /* Restart */
+} MV_COMMAND;
+
+/* This enumerator describes the set of state conditions. */
+/* Moving from one state to other is stricted. */
+typedef enum _mvState
+{
+ MV_IDLE,
+ MV_ACTIVE,
+ MV_PAUSED,
+ MV_UNDEFINED_STATE
+} MV_STATE;
+
+
+/* This structure describes address space window. Window base can be */
+/* 64 bit, window size up to 4GB */
+typedef struct _mvAddrWin
+{
+ MV_U32 baseLow; /* 32bit base low */
+ MV_U32 baseHigh; /* 32bit base high */
+ MV_U32 size; /* 32bit size */
+}MV_ADDR_WIN;
+
+/* This binary enumerator describes protection attribute status */
+typedef enum _mvProtRight
+{
+ ALLOWED, /* Protection attribute allowed */
+ FORBIDDEN /* Protection attribute forbidden */
+}MV_PROT_RIGHT;
+
+/* Unified struct for Rx and Tx packet operations. The user is required to */
+/* be familier only with Tx/Rx descriptor command status. */
+typedef struct _bufInfo
+{
+ MV_U32 cmdSts; /* Tx/Rx command status */
+ MV_U16 byteCnt; /* Size of valid data in the buffer */
+ MV_U16 bufSize; /* Total size of the buffer */
+ MV_U8 *pBuff; /* Pointer to Buffer */
+ MV_U8 *pData; /* Pointer to data in the Buffer */
+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */
+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */
+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */
+} BUF_INFO;
+
+/* This structure contains information describing one of buffers
+ * (fragments) they are built Ethernet packet.
+ */
+typedef struct
+{
+ MV_U8* bufVirtPtr;
+ MV_ULONG bufPhysAddr;
+ MV_U32 bufSize;
+ MV_U32 dataSize;
+ MV_U32 memHandle;
+ MV_32 bufAddrShift;
+} MV_BUF_INFO;
+
+/* This structure contains information describing Ethernet packet.
+ * The packet can be divided for few buffers (fragments)
+ */
+typedef struct
+{
+ MV_ULONG osInfo;
+ MV_BUF_INFO *pFrags;
+ MV_U32 status;
+ MV_U16 pktSize;
+ MV_U16 numFrags;
+ MV_U32 ownerId;
+ MV_U32 fragIP;
+} MV_PKT_INFO;
+
+#endif /* MV_ASMLANGUAGE */
+
+#endif /* __INCmvTypesh */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c
new file mode 100644
index 000000000..644fd02da
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c
@@ -0,0 +1,110 @@
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/time.h>
+#include "dbg-trace.h"
+
+#define TRACE_ARR_LEN 800
+#define STR_LEN 128
+struct trace {
+ struct timeval tv;
+ char str[STR_LEN];
+ unsigned int callback_val1;
+ unsigned int callback_val2;
+ char valid;
+};
+static unsigned int (*trc_callback1) (unsigned char) = NULL;
+static unsigned int (*trc_callback2) (unsigned char) = NULL;
+static unsigned char trc_param1 = 0;
+static unsigned char trc_param2 = 0;
+struct trace *trc_arr;
+static int trc_index;
+static int trc_active = 0;
+
+void TRC_START()
+{
+ trc_active = 1;
+}
+
+void TRC_STOP()
+{
+ trc_active = 0;
+}
+
+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param)
+{
+ printk("Marvell debug tracing is on\n");
+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL);
+ if(trc_arr == NULL)
+ {
+ printk("Can't allocate Debug Trace buffer\n");
+ return;
+ }
+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace));
+ trc_index = 0;
+ trc_callback1 = callback1;
+ trc_callback2 = callback2;
+ trc_param1 = callback1_param;
+ trc_param2 = callback2_param;
+}
+void TRC_REC(char *fmt,...)
+{
+ va_list args;
+ struct trace *trc = &trc_arr[trc_index];
+
+ if(trc_active == 0)
+ return;
+
+ do_gettimeofday(&trc->tv);
+ if(trc_callback1)
+ trc->callback_val1 = trc_callback1(trc_param1);
+ if(trc_callback2)
+ trc->callback_val2 = trc_callback2(trc_param2);
+ va_start(args, fmt);
+ vsprintf(trc->str,fmt,args);
+ va_end(args);
+ trc->valid = 1;
+ if((++trc_index) == TRACE_ARR_LEN) {
+ trc_index = 0;
+ }
+}
+void TRC_OUTPUT(void)
+{
+ int i,j;
+ struct trace *p;
+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN);
+ for(i=0,j=trc_index; i<TRACE_ARR_LEN; i++,j++) {
+ if(j == TRACE_ARR_LEN)
+ j = 0;
+ p = &trc_arr[j];
+ if(p->valid) {
+ unsigned long uoffs;
+ struct trace *plast;
+ if(p == &trc_arr[0])
+ plast = &trc_arr[TRACE_ARR_LEN-1];
+ else
+ plast = p-1;
+ if(p->tv.tv_sec == ((plast)->tv.tv_sec))
+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec));
+ else
+ uoffs = (1000000 - ((plast)->tv.tv_usec)) +
+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) +
+ p->tv.tv_usec;
+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs);
+ if(trc_callback1)
+ printk("[%u]",p->callback_val1);
+ if(trc_callback2)
+ printk("[%u]",p->callback_val2);
+ printk(": %s",p->str);
+ }
+ p->valid = 0;
+ }
+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace));
+ trc_index = 0;
+}
+void TRC_RELEASE(void)
+{
+ kfree(trc_arr);
+ trc_index = 0;
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h
new file mode 100644
index 000000000..a5aac2673
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h
@@ -0,0 +1,24 @@
+
+#ifndef _MV_DBG_TRCE_H_
+#define _MV_DBG_TRCE_H_
+
+#ifdef CONFIG_MV_DBG_TRACE
+void TRC_INIT(void *callback1, void *callback2,
+ unsigned char callback1_param, unsigned char callback2_param);
+void TRC_REC(char *fmt,...);
+void TRC_OUTPUT(void);
+void TRC_RELEASE(void);
+void TRC_START(void);
+void TRC_STOP(void);
+
+#else
+#define TRC_INIT(x1,x2,x3,x4)
+#define TRC_REC(X...)
+#define TRC_OUTPUT()
+#define TRC_RELEASE()
+#define TRC_START()
+#define TRC_STOP()
+#endif
+
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c
new file mode 100644
index 000000000..5f6278447
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c
@@ -0,0 +1,2513 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "boardEnv/mvBoardEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "cpu/mvCpu.h"
+#include "cntmr/mvCntmr.h"
+#include "gpp/mvGpp.h"
+#include "twsi/mvTwsi.h"
+#include "pex/mvPex.h"
+#include "device/mvDevice.h"
+#include "eth/gbe/mvEthRegs.h"
+
+/* defines */
+/* #define MV_DEBUG */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[];
+
+#define CODE_IN_ROM MV_FALSE
+#define CODE_IN_RAM MV_TRUE
+
+extern MV_BOARD_INFO* boardInfoTbl[];
+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE]
+
+/* Locals */
+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+
+MV_U32 tClkRate = -1;
+
+
+/*******************************************************************************
+* mvBoardEnvInit - Init board
+*
+* DESCRIPTION:
+* In this function the board environment take care of device bank
+* initialization.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvBoardEnvInit(MV_VOID)
+{
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n");
+ return;
+
+ }
+
+ /* Set GPP Out value */
+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow);
+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh);
+
+ /* set GPP polarity */
+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow);
+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh);
+
+ /* Workaround for Erratum FE-MISC-70*/
+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV)
+ {
+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd;
+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002;
+ } /*End of WA*/
+
+ /* Set GPP Out Enable*/
+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow);
+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh);
+
+ /* Nand CE */
+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT);
+}
+
+/*******************************************************************************
+* mvBoardModelGet - Get Board model
+*
+* DESCRIPTION:
+* This function returns 16bit describing board model.
+* Board model is constructed of one byte major and minor numbers in the
+* following manner:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* String describing board model.
+*
+*******************************************************************************/
+MV_U16 mvBoardModelGet(MV_VOID)
+{
+ return (mvBoardIdGet() >> 16);
+}
+
+/*******************************************************************************
+* mbBoardRevlGet - Get Board revision
+*
+* DESCRIPTION:
+* This function returns a 32bit describing the board revision.
+* Board revision is constructed of 4bytes. 2bytes describes major number
+* and the other 2bytes describes minor munber.
+* For example for board revision 3.4 the function will return
+* 0x00030004.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* String describing board model.
+*
+*******************************************************************************/
+MV_U16 mvBoardRevGet(MV_VOID)
+{
+ return (mvBoardIdGet() & 0xFFFF);
+}
+
+/*******************************************************************************
+* mvBoardNameGet - Get Board name
+*
+* DESCRIPTION:
+* This function returns a string describing the board model and revision.
+* String is extracted from board I2C EEPROM.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
+*
+* RETURN:
+*
+* MV_ERROR if informantion can not be read.
+*******************************************************************************/
+MV_STATUS mvBoardNameGet(char *pNameBuff)
+{
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsSPrintf (pNameBuff, "Board unknown.\n");
+ return MV_ERROR;
+
+ }
+
+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvBoardIsPortInSgmii -
+*
+* DESCRIPTION:
+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE
+* For all other options.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE - port in SGMII.
+* MV_FALSE - other.
+*
+*******************************************************************************/
+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum)
+{
+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII;
+
+ if(ethPortNum >= BOARD_ETH_PORT_NUM)
+ {
+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum);
+ return MV_FALSE;
+ }
+ return ethPortSgmiiSupport[ethPortNum];
+}
+
+/*******************************************************************************
+* mvBoardIsPortInGmii -
+*
+* DESCRIPTION:
+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE
+* For all other options.
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE - port in GMII.
+* MV_FALSE - other.
+*
+*******************************************************************************/
+MV_BOOL mvBoardIsPortInGmii(MV_VOID)
+{
+ MV_U32 devClassId, devClass = 0;
+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO)
+ {
+ /* Get MPP module ID */
+ devClassId = mvBoarModuleTypeGet(devClass);
+ if (MV_BOARD_MODULE_GMII_ID == devClassId)
+ return MV_TRUE;
+ }
+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+/*******************************************************************************
+* mvBoardPhyAddrGet - Get the phy address
+*
+* DESCRIPTION:
+* This routine returns the Phy address of a given ethernet port.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit describing Phy address, -1 if the port number is wrong.
+*
+*******************************************************************************/
+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum)
+{
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n");
+ return MV_ERROR;
+ }
+
+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr;
+}
+
+/*******************************************************************************
+* mvBoardMacSpeedGet - Get the Mac speed
+*
+* DESCRIPTION:
+* This routine returns the Mac speed if pre define of a given ethernet port.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong.
+*
+*******************************************************************************/
+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum)
+{
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n");
+ return MV_ERROR;
+ }
+
+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed;
+}
+
+/*******************************************************************************
+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication
+*
+* DESCRIPTION:
+* This routine returns the IRQ number for the link status indication.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* the number of the IRQ for the link status indication, -1 if the port
+* number is wrong or if not relevant.
+*
+*******************************************************************************/
+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum)
+{
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n");
+ return MV_ERROR;
+ }
+
+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq;
+}
+
+/*******************************************************************************
+* mvBoardSwitchPortGet - Get the mapping between the board connector and the
+* Ethernet Switch port
+*
+* DESCRIPTION:
+* This routine returns the matching Switch port.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+* boardPortNum - logical number of the connector on the board
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* the matching Switch port, -1 if the port number is wrong or if not relevant.
+*
+*******************************************************************************/
+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum)
+{
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n");
+ return MV_ERROR;
+ }
+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM)
+ {
+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n");
+ return MV_ERROR;
+ }
+
+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum];
+}
+
+/*******************************************************************************
+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port
+*
+* DESCRIPTION:
+* This routine returns the Switch CPU port.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* the Switch CPU port, -1 if the port number is wrong or if not relevant.
+*
+*******************************************************************************/
+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum)
+{
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n");
+ return MV_ERROR;
+ }
+
+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort;
+}
+
+/*******************************************************************************
+* mvBoardIsSwitchConnected - Get switch connection status
+* DESCRIPTION:
+* This routine returns port's connection status
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 1 - if ethPortNum is connected to switch, 0 otherwise
+*
+*******************************************************************************/
+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum)
+{
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n");
+ return MV_ERROR;
+ }
+
+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo)
+ {
+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum);
+ return MV_ERROR;
+ }
+
+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo))
+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum);
+ else
+ return 0;
+}
+/*******************************************************************************
+* mvBoardSmiScanModeGet - Get Switch SMI scan mode
+*
+* DESCRIPTION:
+* This routine returns Switch SMI scan mode.
+*
+* INPUT:
+* ethPortNum - Ethernet port number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant.
+*
+*******************************************************************************/
+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum)
+{
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n");
+ return MV_ERROR;
+ }
+
+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode;
+}
+/*******************************************************************************
+* mvBoardSpecInitGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init,
+* otherwise return MV_FALSE.
+*
+*
+*******************************************************************************/
+
+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data)
+{
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvBoardTclkGet - Get the board Tclk (Controller clock)
+*
+* DESCRIPTION:
+* This routine extract the controller core clock.
+* This function uses the controller counters to make identification.
+* Note: In order to avoid interference, make sure task context switch
+* and interrupts will not occure during this function operation
+*
+* INPUT:
+* countNum - Counter number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit clock cycles in Hertz.
+*
+*******************************************************************************/
+MV_U32 mvBoardTclkGet(MV_VOID)
+{
+ if(mvCtrlModelGet()==MV_6281_DEV_ID)
+ {
+#if defined(TCLK_AUTO_DETECT)
+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ;
+
+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ tmpTClkRate &= MSAR_TCLCK_MASK;
+
+ switch (tmpTClkRate)
+ {
+ case MSAR_TCLCK_166:
+ return MV_BOARD_TCLK_166MHZ;
+ break;
+ case MSAR_TCLCK_200:
+ return MV_BOARD_TCLK_200MHZ;
+ break;
+ }
+#else
+ return MV_BOARD_TCLK_200MHZ;
+#endif
+ }
+
+ return MV_BOARD_TCLK_166MHZ;
+
+}
+/*******************************************************************************
+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock)
+*
+* DESCRIPTION:
+* This routine extract the CPU bus clock.
+*
+* INPUT:
+* countNum - Counter number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit clock cycles in Hertz.
+*
+*******************************************************************************/
+static MV_U32 mvBoard6180SysClkGet(MV_VOID)
+{
+ MV_U32 sysClkRate=0;
+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
+
+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180;
+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180;
+
+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk;
+
+ return sysClkRate;
+
+}
+
+MV_U32 mvBoardSysClkGet(MV_VOID)
+{
+#ifdef SYSCLK_AUTO_DETECT
+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio;
+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL;
+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL;
+
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ return mvBoard6180SysClkGet();
+
+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp);
+ pClkRate = cpuCLK[pClkRate];
+
+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK;
+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS;
+ if(ddrRtio[indexDdrRtio][0] != 0)
+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]);
+ else
+ sysClkRate = 0;
+ return sysClkRate;
+#else
+ return MV_BOARD_DEFAULT_SYSCLK;
+#endif
+}
+
+
+/*******************************************************************************
+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number
+*
+* DESCRIPTION:
+* Multi-ported PCI Express bridges that is implemented on the board
+* collapse interrupts across multiple conventional PCI/PCI-X buses.
+* A dual-headed PCI Express bridge would map (or "swizzle") the
+* interrupts per the following table (in accordance with the respective
+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD#
+* signals from its two logical PCI/PCI-X bridges, collapse the
+* INTA#-INTD# signals from any internal sources, and convert the
+* signals to in-band PCI Express messages. 10
+* This function returns the upstream interrupt as it was converted by
+* the bridge, according to board configuration and the following table:
+* PCI dev num
+* Interrupt pin 7, 8, 9
+* A -> A D C
+* B -> B A D
+* C -> C B A
+* D -> D C B
+*
+*
+* INPUT:
+* devNum - PCI/PCIX device number.
+* intPin - PCI Int pin
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Int pin connected to the Interrupt controller
+*
+*******************************************************************************/
+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin)
+{
+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 );
+
+ if (realIntPin == 0) return 4;
+ else return realIntPin;
+
+}
+
+/*******************************************************************************
+* mvBoardDebugLedNumGet - Get number of debug Leds
+*
+* DESCRIPTION:
+* INPUT:
+* boardId
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId)
+{
+ return BOARD_INFO(boardId)->activeLedsNumber;
+}
+
+/*******************************************************************************
+* mvBoardDebugLeg - Set the board debug Leds
+*
+* DESCRIPTION: turn on/off status leds.
+* Note: assume MPP leds are part of group 0 only.
+*
+* INPUT:
+* hexNum - Number to be displied in hex by Leds.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvBoardDebugLed(MV_U32 hexNum)
+{
+ MV_U32 val = 0,totalMask, currentBitMask = 1,i;
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (BOARD_INFO(boardId)->pLedGppPin == NULL)
+ return;
+
+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1;
+ hexNum &= totalMask;
+ totalMask = 0;
+
+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++)
+ {
+ if (hexNum & currentBitMask)
+ {
+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]);
+ }
+
+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]);
+
+ currentBitMask = (currentBitMask << 1);
+ }
+
+ if (BOARD_INFO(boardId)->ledsPolarity)
+ {
+ mvGppValueSet(0, totalMask, val);
+ }
+ else
+ {
+ mvGppValueSet(0, totalMask, ~val);
+ }
+}
+
+
+/*******************************************************************************
+* mvBoarGpioPinGet - mvBoarGpioPinGet
+*
+* DESCRIPTION:
+*
+* INPUT:
+* class - MV_BOARD_GPP_CLASS enum.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* GPIO pin number. The function return -1 for bad parameters.
+*
+*******************************************************************************/
+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index)
+{
+ MV_U32 boardId, i;
+ MV_U32 indexFound = 0;
+
+ boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n");
+ return MV_ERROR;
+
+ }
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++)
+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) {
+ if (indexFound == index)
+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum;
+ else
+ indexFound++;
+
+ }
+
+ return MV_ERROR;
+}
+
+
+/*******************************************************************************
+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* GPIO pin number. The function return -1 for bad parameters.
+*
+*******************************************************************************/
+MV_32 mvBoardRTCGpioPinGet(MV_VOID)
+{
+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0);
+}
+
+
+/*******************************************************************************
+* mvBoardReset - mvBoardReset
+*
+* DESCRIPTION:
+* Reset the board
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None
+*
+*******************************************************************************/
+MV_VOID mvBoardReset(MV_VOID)
+{
+ MV_32 resetPin;
+
+ /* Get gpp reset pin if define */
+ resetPin = mvBoardResetGpioPinGet();
+ if (resetPin != MV_ERROR)
+ {
+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin));
+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin));
+
+ }
+ else
+ {
+ /* No gpp reset pin was found, try to reset ussing
+ system reset out */
+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2);
+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0);
+ }
+}
+
+/*******************************************************************************
+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* GPIO pin number. The function return -1 for bad parameters.
+*
+*******************************************************************************/
+MV_32 mvBoardResetGpioPinGet(MV_VOID)
+{
+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0);
+}
+/*******************************************************************************
+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet
+*
+* DESCRIPTION:
+* used for hotswap detection
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* GPIO pin number. The function return -1 for bad parameters.
+*
+*******************************************************************************/
+MV_32 mvBoardSDIOGpioPinGet(MV_VOID)
+{
+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0);
+}
+
+/*******************************************************************************
+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP
+*
+* DESCRIPTION:
+*
+* INPUT:
+* int devNo.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* GPIO pin number. The function return -1 for bad parameters.
+*
+*******************************************************************************/
+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId)
+{
+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId);
+}
+
+/*******************************************************************************
+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP
+*
+* DESCRIPTION:
+*
+* INPUT:
+* int devNo.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* GPIO pin number. The function return -1 for bad parameters.
+*
+*******************************************************************************/
+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId)
+{
+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId);
+}
+
+
+/*******************************************************************************
+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins
+*
+* DESCRIPTION:
+* This function returns a 32-bit mask of GPP pins that connected to
+* interrupt generating sources on board.
+* For example if UART channel A is hardwired to GPP pin 8 and
+* UART channel B is hardwired to GPP pin 4 the fuinction will return
+* the value 0x000000110
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* See description. The function return -1 if board is not identified.
+*
+*******************************************************************************/
+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID)
+{
+ MV_U32 boardId;
+
+ boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n");
+ return MV_ERROR;
+
+ }
+
+ return BOARD_INFO(boardId)->intsGppMaskLow;
+}
+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID)
+{
+ MV_U32 boardId;
+
+ boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n");
+ return MV_ERROR;
+
+ }
+
+ return BOARD_INFO(boardId)->intsGppMaskHigh;
+}
+
+
+/*******************************************************************************
+* mvBoardMppGet - Get board dependent MPP register value
+*
+* DESCRIPTION:
+* MPP settings are derived from board design.
+* MPP group consist of 8 MPPs. An MPP group represent MPP
+* control register.
+* This function retrieves board dependend MPP register value.
+*
+* INPUT:
+* mppGroupNum - MPP group number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit value describing MPP control register value.
+*
+*******************************************************************************/
+MV_32 mvBoardMppGet(MV_U32 mppGroupNum)
+{
+ MV_U32 boardId;
+
+ boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardMppGet:Board unknown.\n");
+ return MV_ERROR;
+
+ }
+
+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum];
+}
+
+
+/*******************************************************************************
+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID)
+{
+
+ MV_BOARD_MPP_GROUP_CLASS devClass;
+ MV_BOARD_MODULE_ID_CLASS devClassId;
+ MV_BOARD_MPP_TYPE_CLASS mppGroupType;
+ MV_U32 devId;
+ MV_U32 maxMppGrp = 1;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ maxMppGrp = MV_6281_MPP_MAX_MODULE;
+ break;
+ case MV_6192_DEV_ID:
+ maxMppGrp = MV_6192_MPP_MAX_MODULE;
+ break;
+ case MV_6190_DEV_ID:
+ maxMppGrp = MV_6190_MPP_MAX_MODULE;
+ break;
+ case MV_6180_DEV_ID:
+ maxMppGrp = MV_6180_MPP_MAX_MODULE;
+ break;
+ }
+
+ for (devClass = 0; devClass < maxMppGrp; devClass++)
+ {
+ /* If MPP group can be defined by the module connected to it */
+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO)
+ {
+ /* Get MPP module ID */
+ devClassId = mvBoarModuleTypeGet(devClass);
+ if (MV_ERROR != devClassId)
+ {
+ switch(devClassId)
+ {
+ case MV_BOARD_MODULE_TDM_ID:
+ case MV_BOARD_MODULE_TDM_5CHAN_ID:
+ mppGroupType = MV_BOARD_TDM;
+ break;
+ case MV_BOARD_MODULE_AUDIO_ID:
+ mppGroupType = MV_BOARD_AUDIO;
+ break;
+ case MV_BOARD_MODULE_RGMII_ID:
+ mppGroupType = MV_BOARD_RGMII;
+ break;
+ case MV_BOARD_MODULE_GMII_ID:
+ mppGroupType = MV_BOARD_GMII;
+ break;
+ case MV_BOARD_MODULE_TS_ID:
+ mppGroupType = MV_BOARD_TS;
+ break;
+ case MV_BOARD_MODULE_MII_ID:
+ mppGroupType = MV_BOARD_MII;
+ break;
+ default:
+ mppGroupType = MV_BOARD_OTHER;
+ break;
+ }
+ }
+ else
+ /* The module bay is empty */
+ mppGroupType = MV_BOARD_OTHER;
+
+ /* Update MPP group type */
+ mvBoardMppGroupTypeSet(devClass, mppGroupType);
+ }
+
+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */
+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII))
+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE);
+ else
+ {
+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII))
+ {
+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15);
+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3);
+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3);
+ }
+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII))
+ {
+ /* Assumption that the MDC & MDIO should be 3.3V */
+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15);
+ /* Assumption that only ETH1 can be MII when using modules on DB */
+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3);
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* mvBoardMppGroupTypeGet
+*
+* DESCRIPTION:
+*
+* INPUT:
+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36].
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass)
+{
+ MV_U32 boardId;
+
+ boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardMppGet:Board unknown.\n");
+ return MV_ERROR;
+
+ }
+
+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1)
+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1;
+ else
+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2;
+}
+
+/*******************************************************************************
+* mvBoardMppGroupTypeSet
+*
+* DESCRIPTION:
+*
+* INPUT:
+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36].
+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36].
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass,
+ MV_BOARD_MPP_TYPE_CLASS mppGroupType)
+{
+ MV_U32 boardId;
+
+ boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardMppGet:Board unknown.\n");
+ }
+
+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1)
+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType;
+ else
+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType;
+
+}
+
+/*******************************************************************************
+* mvBoardMppMuxSet - Update MPP mux
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvBoardMppMuxSet(MV_VOID)
+{
+
+ MV_BOARD_MPP_GROUP_CLASS devClass;
+ MV_BOARD_MPP_TYPE_CLASS mppGroupType;
+ MV_U32 devId;
+ MV_U8 muxVal = 0xf;
+ MV_U32 maxMppGrp = 1;
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ maxMppGrp = MV_6281_MPP_MAX_MODULE;
+ break;
+ case MV_6192_DEV_ID:
+ maxMppGrp = MV_6192_MPP_MAX_MODULE;
+ break;
+ case MV_6190_DEV_ID:
+ maxMppGrp = MV_6190_MPP_MAX_MODULE;
+ break;
+ case MV_6180_DEV_ID:
+ maxMppGrp = MV_6180_MPP_MAX_MODULE;
+ break;
+ }
+
+ for (devClass = 0; devClass < maxMppGrp; devClass++)
+ {
+ mppGroupType = mvBoardMppGroupTypeGet(devClass);
+
+ switch(mppGroupType)
+ {
+ case MV_BOARD_TDM:
+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0);
+ break;
+ case MV_BOARD_AUDIO:
+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/
+ break;
+ case MV_BOARD_TS:
+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0);
+ break;
+ default:
+ muxVal |= (devClass ? 0xf : 0);
+ break;
+ }
+ }
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: twsi exp set\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY);
+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY);
+ twsiSlave.validOffset = MV_TRUE;
+ /* Offset is the first command after the address which indicate the register number to be read
+ in next operation */
+ twsiSlave.offset = 2;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp out val fail\n"));
+ return;
+ }
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+ /* Change twsi exp to output */
+ twsiSlave.offset = 6;
+ muxVal = 0;
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp change to out fail\n"));
+ return;
+ }
+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n"));
+
+}
+
+/*******************************************************************************
+* mvBoardTdmMppSet - set MPPs in TDM module
+*
+* DESCRIPTION:
+*
+* INPUT: type of second telephony device
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvBoardTdmMppSet(MV_32 chType)
+{
+
+ MV_BOARD_MPP_GROUP_CLASS devClass;
+ MV_BOARD_MPP_TYPE_CLASS mppGroupType;
+ MV_U32 devId;
+ MV_U8 muxVal = 1;
+ MV_U8 muxValMask = 1;
+ MV_U8 twsiVal;
+ MV_U32 maxMppGrp = 1;
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ maxMppGrp = MV_6281_MPP_MAX_MODULE;
+ break;
+ case MV_6192_DEV_ID:
+ maxMppGrp = MV_6192_MPP_MAX_MODULE;
+ break;
+ case MV_6190_DEV_ID:
+ maxMppGrp = MV_6190_MPP_MAX_MODULE;
+ break;
+ case MV_6180_DEV_ID:
+ maxMppGrp = MV_6180_MPP_MAX_MODULE;
+ break;
+ }
+
+ for (devClass = 0; devClass < maxMppGrp; devClass++)
+ {
+ mppGroupType = mvBoardMppGroupTypeGet(devClass);
+ if(mppGroupType == MV_BOARD_TDM)
+ break;
+ }
+
+ if(devClass == maxMppGrp)
+ return; /* TDM module not found */
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: twsi exp set\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass);
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ /* Offset is the first command after the address which indicate the register number to be read
+ in next operation */
+ twsiSlave.offset = 3;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if(mvBoardIdGet() == RD_88F6281A_ID)
+ {
+ muxVal = 0xc;
+ muxValMask = 0xf3;
+ }
+
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ muxVal = (twsiVal & muxValMask) | muxVal;
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ mvOsPrintf("Board: twsi exp out val fail\n");
+ return;
+ }
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+ /* Change twsi exp to output */
+ twsiSlave.offset = 7;
+ muxVal = 0xfe;
+ if(mvBoardIdGet() == RD_88F6281A_ID)
+ muxVal = 0xf3;
+
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ muxVal = (twsiVal & muxVal);
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ mvOsPrintf("Board: twsi exp change to out fail\n");
+ return;
+ }
+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n"));
+ /* reset the line to 0 */
+ twsiSlave.offset = 3;
+ muxVal = 0;
+ muxValMask = 1;
+
+ if(mvBoardIdGet() == RD_88F6281A_ID) {
+ muxVal = 0x0;
+ muxValMask = 0xf3;
+ }
+
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ muxVal = (twsiVal & muxValMask) | muxVal;
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ mvOsPrintf("Board: twsi exp out val fail\n");
+ return;
+ }
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+ mvOsDelay(20);
+
+ /* set the line to 1 */
+ twsiSlave.offset = 3;
+ muxVal = 1;
+ muxValMask = 1;
+
+ if(mvBoardIdGet() == RD_88F6281A_ID)
+ {
+ muxVal = 0xc;
+ muxValMask = 0xf3;
+ if(chType) /* FXS - issue reset properly */
+ {
+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12);
+ mvOsDelay(50);
+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12);
+ }
+ else /* FXO - issue reset via TDM_CODEC_RST*/
+ {
+ /* change MPP44 type to TDM_CODEC_RST(0x2) */
+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17));
+ }
+ }
+
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ muxVal = (twsiVal & muxValMask) | muxVal;
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ mvOsPrintf("Board: twsi exp out val fail\n");
+ return;
+ }
+
+ /* TBD - 5 channels */
+#if defined(MV_TDM_5CHANNELS)
+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */
+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF));
+ mvGppPolaritySet(1, MV_GPP6, 0);
+
+ twsiSlave.offset = 6;
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2);
+
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ muxVal = (twsiVal & ~BIT2);
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ mvOsPrintf("Board: twsi exp change to out fail\n");
+ return;
+ }
+
+
+ twsiSlave.offset = 2;
+
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ muxVal = (twsiVal & ~BIT2);
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) )
+ {
+ mvOsPrintf("Board: twsi exp change to out fail\n");
+ return;
+ }
+#endif
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+
+}
+/*******************************************************************************
+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+
+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode)
+{
+ switch(mvBoardIdGet())
+ {
+ case RD_88F6281A_ID:
+ *connMode = DAISY_CHAIN_MODE;
+ *irqMode = INTERRUPT_TO_TDM;
+ break;
+ case DB_88F6281A_BP_ID:
+ *connMode = DUAL_CHIP_SELECT_MODE;
+ *irqMode = INTERRUPT_TO_TDM;
+ break;
+ case RD_88F6192A_ID:
+ *connMode = DUAL_CHIP_SELECT_MODE;
+ *irqMode = INTERRUPT_TO_TDM;
+ break;
+ case DB_88F6192A_BP_ID:
+ *connMode = DUAL_CHIP_SELECT_MODE;
+ *irqMode = INTERRUPT_TO_TDM;
+ break;
+ default:
+ *connMode = *irqMode = -1;
+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet());
+ }
+ return;
+
+}
+
+/*******************************************************************************
+* mvBoardMppModuleTypePrint - print module detect
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvBoardMppModuleTypePrint(MV_VOID)
+{
+
+ MV_BOARD_MPP_GROUP_CLASS devClass;
+ MV_BOARD_MPP_TYPE_CLASS mppGroupType;
+ MV_U32 devId;
+ MV_U32 maxMppGrp = 1;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ maxMppGrp = MV_6281_MPP_MAX_MODULE;
+ break;
+ case MV_6192_DEV_ID:
+ maxMppGrp = MV_6192_MPP_MAX_MODULE;
+ break;
+ case MV_6190_DEV_ID:
+ maxMppGrp = MV_6190_MPP_MAX_MODULE;
+ break;
+ case MV_6180_DEV_ID:
+ maxMppGrp = MV_6180_MPP_MAX_MODULE;
+ break;
+ }
+
+ for (devClass = 0; devClass < maxMppGrp; devClass++)
+ {
+ mppGroupType = mvBoardMppGroupTypeGet(devClass);
+
+ switch(mppGroupType)
+ {
+ case MV_BOARD_TDM:
+ if(devId != MV_6190_DEV_ID)
+ mvOsPrintf("Module %d is TDM\n", devClass);
+ break;
+ case MV_BOARD_AUDIO:
+ if(devId != MV_6190_DEV_ID)
+ mvOsPrintf("Module %d is AUDIO\n", devClass);
+ break;
+ case MV_BOARD_RGMII:
+ if(devId != MV_6190_DEV_ID)
+ mvOsPrintf("Module %d is RGMII\n", devClass);
+ break;
+ case MV_BOARD_GMII:
+ if(devId != MV_6190_DEV_ID)
+ mvOsPrintf("Module %d is GMII\n", devClass);
+ break;
+ case MV_BOARD_TS:
+ if(devId != MV_6190_DEV_ID)
+ mvOsPrintf("Module %d is TS\n", devClass);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/* Board devices API managments */
+
+/*******************************************************************************
+* mvBoardGetDeviceNumber - Get number of device of some type on the board
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* number of those devices else the function returns 0
+*
+*
+*******************************************************************************/
+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass)
+{
+ MV_U32 foundIndex=0,devNum;
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n");
+ return 0xFFFFFFFF;
+
+ }
+
+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++)
+ {
+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass)
+ {
+ foundIndex++;
+ }
+ }
+
+ return foundIndex;
+
+}
+
+/*******************************************************************************
+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* Base address else the function returns 0xffffffff
+*
+*
+*******************************************************************************/
+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO* devEntry;
+ devEntry = boardGetDevEntry(devNum,devClass);
+ if (devEntry != NULL)
+ {
+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS));
+
+ }
+
+ return 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* Bus width else the function returns 0xffffffff
+*
+*
+*******************************************************************************/
+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO* devEntry;
+
+ devEntry = boardGetDevEntry(devNum,devClass);
+ if (devEntry != NULL)
+ {
+ return 8;
+ }
+
+ return 0xFFFFFFFF;
+
+}
+
+/*******************************************************************************
+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* dev width else the function returns 0xffffffff
+*
+*
+*******************************************************************************/
+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO* devEntry;
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("Board unknown.\n");
+ return 0xFFFFFFFF;
+ }
+
+ devEntry = boardGetDevEntry(devNum,devClass);
+ if (devEntry != NULL)
+ return devEntry->devWidth;
+
+ return MV_ERROR;
+
+}
+
+/*******************************************************************************
+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* window size else the function returns 0xffffffff
+*
+*
+*******************************************************************************/
+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO* devEntry;
+ MV_U32 boardId = mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("Board unknown.\n");
+ return 0xFFFFFFFF;
+ }
+
+ devEntry = boardGetDevEntry(devNum,devClass);
+ if (devEntry != NULL)
+ {
+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS));
+ }
+
+ return 0xFFFFFFFF;
+}
+
+
+/*******************************************************************************
+* boardGetDevEntry - returns the entry pointer of a device on the board
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devIndex - The device sequential number on the board
+* devType - The device type ( Flash,RTC , etc .. )
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* If the device is found on the board the then the functions returns the
+* dev number else the function returns 0x0
+*
+*
+*******************************************************************************/
+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_U32 foundIndex=0,devIndex;
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("boardGetDevEntry: Board unknown.\n");
+ return NULL;
+
+ }
+
+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++)
+ {
+ /* TBR */
+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX)
+ continue;*/
+
+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass)
+ {
+ if (foundIndex == devNum)
+ {
+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]);
+ }
+ foundIndex++;
+ }
+ }
+
+ /* device not found */
+ return NULL;
+}
+
+/* Get device CS number */
+
+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass)
+{
+ MV_DEV_CS_INFO* devEntry;
+ MV_U32 boardId= mvBoardIdGet();
+
+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
+ {
+ mvOsPrintf("Board unknown.\n");
+ return 0xFFFFFFFF;
+
+ }
+
+
+ devEntry = boardGetDevEntry(devNum,devClass);
+ if (devEntry != NULL)
+ return devEntry->deviceCS;
+
+ return 0xFFFFFFFF;
+
+}
+
+/*******************************************************************************
+* mvBoardRtcTwsiAddrTypeGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardRtcTwsiAddrTypeGet()
+{
+ int i;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType;
+ return (MV_ERROR);
+}
+
+/*******************************************************************************
+* mvBoardRtcTwsiAddrGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardRtcTwsiAddrGet()
+{
+ int i;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr;
+ return (0xFF);
+}
+
+/*******************************************************************************
+* mvBoardA2DTwsiAddrTypeGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardA2DTwsiAddrTypeGet()
+{
+ int i;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType;
+ return (MV_ERROR);
+}
+
+/*******************************************************************************
+* mvBoardA2DTwsiAddrGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardA2DTwsiAddrGet()
+{
+ int i;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr;
+ return (0xFF);
+}
+
+/*******************************************************************************
+* mvBoardTwsiExpAddrTypeGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index)
+{
+ int i;
+ MV_U32 indexFound = 0;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP)
+ {
+ if (indexFound == index)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType;
+ else
+ indexFound++;
+ }
+
+ return (MV_ERROR);
+}
+
+/*******************************************************************************
+* mvBoardTwsiExpAddrGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index)
+{
+ int i;
+ MV_U32 indexFound = 0;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP)
+ {
+ if (indexFound == index)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr;
+ else
+ indexFound++;
+ }
+
+ return (0xFF);
+}
+
+
+/*******************************************************************************
+* mvBoardTwsiSatRAddrTypeGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index)
+{
+ int i;
+ MV_U32 indexFound = 0;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR)
+ {
+ if (indexFound == index)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType;
+ else
+ indexFound++;
+ }
+
+ return (MV_ERROR);
+}
+
+/*******************************************************************************
+* mvBoardTwsiSatRAddrGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index)
+{
+ int i;
+ MV_U32 indexFound = 0;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++)
+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR)
+ {
+ if (indexFound == index)
+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr;
+ else
+ indexFound++;
+ }
+
+ return (0xFF);
+}
+
+/*******************************************************************************
+* mvBoardNandWidthGet -
+*
+* DESCRIPTION: Get the width of the first NAND device in byte.
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN: 1, 2, 4 or MV_ERROR
+*
+*
+*******************************************************************************/
+/* */
+MV_32 mvBoardNandWidthGet(void)
+{
+ MV_U32 devNum;
+ MV_U32 devWidth;
+ MV_U32 boardId= mvBoardIdGet();
+
+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++)
+ {
+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH);
+ if (devWidth != MV_ERROR)
+ return (devWidth / 8);
+ }
+
+ /* NAND wasn't found */
+ return MV_ERROR;
+}
+
+MV_U32 gBoardId = -1;
+
+/*******************************************************************************
+* mvBoardIdGet - Get Board model
+*
+* DESCRIPTION:
+* This function returns board ID.
+* Board ID is 32bit word constructed of board model (16bit) and
+* board revision (16bit) in the following way: 0xMMMMRRRR.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit board ID number, '-1' if board is undefined.
+*
+*******************************************************************************/
+MV_U32 mvBoardIdGet(MV_VOID)
+{
+ MV_U32 tmpBoardId = -1;
+
+ if(gBoardId == -1)
+ {
+ #if defined(DB_88F6281A)
+ tmpBoardId = DB_88F6281A_BP_ID;
+ #elif defined(RD_88F6281A)
+ tmpBoardId = RD_88F6281A_ID;
+ #elif defined(DB_88F6192A)
+ tmpBoardId = DB_88F6192A_BP_ID;
+ #elif defined(DB_88F6190A)
+ tmpBoardId = DB_88F6190A_BP_ID;
+ #elif defined(RD_88F6192A)
+ tmpBoardId = RD_88F6192A_ID;
+ #elif defined(RD_88F6190A)
+ tmpBoardId = RD_88F6190A_ID;
+ #elif defined(DB_88F6180A)
+ tmpBoardId = DB_88F6180A_BP_ID;
+ #elif defined(RD_88F6281A_PCAC)
+ tmpBoardId = RD_88F6281A_PCAC_ID;
+ #elif defined(RD_88F6281A_SHEEVA_PLUG)
+ tmpBoardId = SHEEVA_PLUG_ID;
+ #elif defined(DB_CUSTOMER)
+ tmpBoardId = DB_CUSTOMER_ID;
+ #endif
+ gBoardId = tmpBoardId;
+ }
+
+ return gBoardId;
+}
+
+
+/*******************************************************************************
+* mvBoarModuleTypeGet - mvBoarModuleTypeGet
+*
+* DESCRIPTION:
+*
+* INPUT:
+* group num - MV_BOARD_MPP_GROUP_CLASS enum
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* module num - MV_BOARD_MODULE_CLASS enum
+*
+*******************************************************************************/
+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass)
+{
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+ MV_U8 data;
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: Read MPP module ID\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass);
+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass);
+ twsiSlave.validOffset = MV_TRUE;
+ /* Offset is the first command after the address which indicate the register number to be read
+ in next operation */
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+
+
+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) )
+ {
+ DB(mvOsPrintf("Board: Read MPP module ID fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n"));
+
+ return data;
+}
+
+/*******************************************************************************
+* mvBoarTwsiSatRGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* device num - one of three devices
+* reg num - 0 or 1
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* reg value
+*
+*******************************************************************************/
+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum)
+{
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+ MV_U8 data;
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: Read S@R device read\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum);
+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum);
+ twsiSlave.validOffset = MV_TRUE;
+ /* Use offset as command */
+ twsiSlave.offset = regNum;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) )
+ {
+ DB(mvOsPrintf("Board: Read S@R fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: Read S@R succeded\n"));
+
+ return data;
+}
+
+/*******************************************************************************
+* mvBoarTwsiSatRSet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* devNum - one of three devices
+* regNum - 0 or 1
+* regVal - value
+*
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* reg value
+*
+*******************************************************************************/
+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal)
+{
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum);
+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum);
+ twsiSlave.validOffset = MV_TRUE;
+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\
+ twsiSlave.slaveAddr.type, regVal));
+ /* Use offset as command */
+ twsiSlave.offset = regNum;
+ twsiSlave.moreThen256 = MV_FALSE;
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &regVal, 1) )
+ {
+ DB(mvOsPrintf("Board: Write S@R fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: Write S@R succeded\n"));
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvBoardSlicGpioPinGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*
+*******************************************************************************/
+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum)
+{
+ MV_U32 boardId;
+ boardId = mvBoardIdGet();
+
+ switch (boardId)
+ {
+ case DB_88F6281A_BP_ID:
+ case RD_88F6281A_ID:
+ default:
+ return MV_ERROR;
+ break;
+
+ }
+}
+
+/*******************************************************************************
+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A
+*
+* DESCRIPTION:
+*
+* INPUT:
+* mode - MV_TRUE = on ; MV_FALSE = off
+*
+* OUTPUT:
+* MV_STATUS - MV_OK , MV_ERROR.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode)
+{
+
+ MV_U8 val = 1, twsiVal;
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+
+ if(mvBoardIdGet() != RD_88F6281A_ID)
+ return MV_ERROR;
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: twsi exp set\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1);
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ /* Offset is the first command after the address which indicate the register number to be read
+ in next operation */
+ twsiSlave.offset = 3;
+ twsiSlave.moreThen256 = MV_FALSE;
+ if(mode == MV_TRUE)
+ val = 0x1;
+ else
+ val = 0;
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ val = (twsiVal & 0xfe) | val;
+
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp out val fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+ /* Change twsi exp to output */
+ twsiSlave.offset = 7;
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ val = (twsiVal & 0xfe);
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp change to out fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n"));
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A
+*
+* DESCRIPTION:
+*
+* INPUT:
+* mode - MV_TRUE = on ; MV_FALSE = off
+*
+* OUTPUT:
+* MV_STATUS - MV_OK , MV_ERROR.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode)
+{
+
+ MV_U8 val = 1, twsiVal;
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+
+ if(mvBoardIdGet() != RD_88F6281A_ID)
+ return MV_ERROR;
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: twsi exp set\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1);
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ /* Offset is the first command after the address which indicate the register number to be read
+ in next operation */
+ twsiSlave.offset = 3;
+ twsiSlave.moreThen256 = MV_FALSE;
+ if(mode == MV_TRUE)
+ val = 0x2;
+ else
+ val = 0;
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ val = (twsiVal & 0xfd) | val;
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp out val fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+ /* Change twsi exp to output */
+ twsiSlave.offset = 7;
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ val = (twsiVal & 0xfd);
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp change to out fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n"));
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A
+*
+* DESCRIPTION:
+*
+* INPUT:
+* mode - MV_TRUE = on ; MV_FALSE = off
+*
+* OUTPUT:
+* MV_STATUS - MV_OK , MV_ERROR.
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode)
+{
+
+ MV_U8 val = 1, twsiVal;
+ MV_TWSI_SLAVE twsiSlave;
+ MV_TWSI_ADDR slave;
+
+ if(mvBoardIdGet() != RD_88F6281A_ID)
+ return MV_ERROR;
+
+ /* TWSI init */
+ slave.type = ADDR7_BIT;
+ slave.address = 0;
+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
+
+ /* Read MPP module ID */
+ DB(mvOsPrintf("Board: twsi exp set\n"));
+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0);
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ /* Offset is the first command after the address which indicate the register number to be read
+ in next operation */
+ twsiSlave.offset = 3;
+ twsiSlave.moreThen256 = MV_FALSE;
+ if(mode == MV_TRUE)
+ val = 0x10;
+ else
+ val = 0;
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ val = (twsiVal & 0xef) | val;
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp out val fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: twsi exp out val succeded\n"));
+
+ /* Change twsi exp to output */
+ twsiSlave.offset = 7;
+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1);
+ val = (twsiVal & 0xef);
+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) )
+ {
+ DB(mvOsPrintf("Board: twsi exp change to out fail\n"));
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n"));
+ return MV_OK;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h
new file mode 100644
index 000000000..dead63369
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h
@@ -0,0 +1,376 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __INCmvBoardEnvLibh
+#define __INCmvBoardEnvLibh
+
+/* defines */
+/* The below constant macros defines the board I2C EEPROM data offsets */
+
+
+
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "mvSysHwConfig.h"
+#include "boardEnv/mvBoardEnvSpec.h"
+
+
+/* DUART stuff for Tclk detection only */
+#define DUART_BAUD_RATE 115200
+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */
+
+/* Voice devices assembly modes */
+#define DAISY_CHAIN_MODE 1
+#define DUAL_CHIP_SELECT_MODE 0
+#define INTERRUPT_TO_MPP 1
+#define INTERRUPT_TO_TDM 0
+
+
+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS
+#define BOARD_ETH_SWITCH_PORT_NUM 5
+
+#define MV_BOARD_MAX_USB_IF 1
+#define MV_BOARD_MAX_MPP 7
+#define MV_BOARD_NAME_LEN 0x20
+
+typedef struct _boardData
+{
+ MV_U32 magic;
+ MV_U16 boardId;
+ MV_U8 boardVer;
+ MV_U8 boardRev;
+ MV_U32 reserved1;
+ MV_U32 reserved2;
+
+}BOARD_DATA;
+
+typedef enum _devBoardMppGroupClass
+{
+ MV_BOARD_MPP_GROUP_1,
+ MV_BOARD_MPP_GROUP_2,
+ MV_BOARD_MAX_MPP_GROUP
+}MV_BOARD_MPP_GROUP_CLASS;
+
+typedef enum _devBoardMppTypeClass
+{
+ MV_BOARD_AUTO,
+ MV_BOARD_TDM,
+ MV_BOARD_AUDIO,
+ MV_BOARD_RGMII,
+ MV_BOARD_GMII,
+ MV_BOARD_TS,
+ MV_BOARD_MII,
+ MV_BOARD_OTHER
+}MV_BOARD_MPP_TYPE_CLASS;
+
+typedef enum _devBoardModuleIdClass
+{
+ MV_BOARD_MODULE_TDM_ID = 1,
+ MV_BOARD_MODULE_AUDIO_ID,
+ MV_BOARD_MODULE_RGMII_ID,
+ MV_BOARD_MODULE_GMII_ID,
+ MV_BOARD_MODULE_TS_ID,
+ MV_BOARD_MODULE_MII_ID,
+ MV_BOARD_MODULE_TDM_5CHAN_ID,
+ MV_BOARD_MODULE_OTHER_ID
+}MV_BOARD_MODULE_ID_CLASS;
+
+typedef struct _boardMppTypeInfo
+{
+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1;
+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2;
+
+}MV_BOARD_MPP_TYPE_INFO;
+
+
+typedef enum _devBoardClass
+{
+ BOARD_DEV_NOR_FLASH,
+ BOARD_DEV_NAND_FLASH,
+ BOARD_DEV_SEVEN_SEG,
+ BOARD_DEV_FPGA,
+ BOARD_DEV_SRAM,
+ BOARD_DEV_SPI_FLASH,
+ BOARD_DEV_OTHER,
+}MV_BOARD_DEV_CLASS;
+
+typedef enum _devTwsiBoardClass
+{
+ BOARD_TWSI_RTC,
+ BOARD_DEV_TWSI_EXP,
+ BOARD_DEV_TWSI_SATR,
+ BOARD_TWSI_AUDIO_DEC,
+ BOARD_TWSI_OTHER
+}MV_BOARD_TWSI_CLASS;
+
+typedef enum _devGppBoardClass
+{
+ BOARD_GPP_RTC,
+ BOARD_GPP_MV_SWITCH,
+ BOARD_GPP_USB_VBUS,
+ BOARD_GPP_USB_VBUS_EN,
+ BOARD_GPP_USB_OC,
+ BOARD_GPP_USB_HOST_DEVICE,
+ BOARD_GPP_REF_CLCK,
+ BOARD_GPP_VOIP_SLIC,
+ BOARD_GPP_LIFELINE,
+ BOARD_GPP_BUTTON,
+ BOARD_GPP_TS_BUTTON_C,
+ BOARD_GPP_TS_BUTTON_U,
+ BOARD_GPP_TS_BUTTON_D,
+ BOARD_GPP_TS_BUTTON_L,
+ BOARD_GPP_TS_BUTTON_R,
+ BOARD_GPP_POWER_BUTTON,
+ BOARD_GPP_RESTOR_BUTTON,
+ BOARD_GPP_WPS_BUTTON,
+ BOARD_GPP_HDD0_POWER,
+ BOARD_GPP_HDD1_POWER,
+ BOARD_GPP_FAN_POWER,
+ BOARD_GPP_RESET,
+ BOARD_GPP_POWER_ON_LED,
+ BOARD_GPP_HDD_POWER,
+ BOARD_GPP_SDIO_POWER,
+ BOARD_GPP_SDIO_DETECT,
+ BOARD_GPP_SDIO_WP,
+ BOARD_GPP_SWITCH_PHY_INT,
+ BOARD_GPP_TSU_DIRCTION,
+ BOARD_GPP_OTHER
+}MV_BOARD_GPP_CLASS;
+
+
+typedef struct _devCsInfo
+{
+ MV_U8 deviceCS;
+ MV_U32 params;
+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */
+ MV_U8 devWidth;
+
+}MV_DEV_CS_INFO;
+
+
+#define MV_BOARD_PHY_FORCE_10MB 0x0
+#define MV_BOARD_PHY_FORCE_100MB 0x1
+#define MV_BOARD_PHY_FORCE_1000MB 0x2
+#define MV_BOARD_PHY_SPEED_AUTO 0x3
+
+typedef struct _boardSwitchInfo
+{
+ MV_32 linkStatusIrq;
+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM];
+ MV_32 qdCpuPort;
+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */
+ MV_32 switchOnPort;
+
+}MV_BOARD_SWITCH_INFO;
+
+typedef struct _boardLedInfo
+{
+ MV_U8 activeLedsNumber;
+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
+ MV_U8* gppPinNum; /* Pointer to GPP values */
+
+}MV_BOARD_LED_INFO;
+
+typedef struct _boardGppInfo
+{
+ MV_BOARD_GPP_CLASS devClass;
+ MV_U8 gppPinNum;
+
+}MV_BOARD_GPP_INFO;
+
+
+typedef struct _boardTwsiInfo
+{
+ MV_BOARD_TWSI_CLASS devClass;
+ MV_U8 twsiDevAddr;
+ MV_U8 twsiDevAddrType;
+
+}MV_BOARD_TWSI_INFO;
+
+
+typedef enum _boardMacSpeed
+{
+ BOARD_MAC_SPEED_10M,
+ BOARD_MAC_SPEED_100M,
+ BOARD_MAC_SPEED_1000M,
+ BOARD_MAC_SPEED_AUTO,
+
+}MV_BOARD_MAC_SPEED;
+
+typedef struct _boardMacInfo
+{
+ MV_BOARD_MAC_SPEED boardMacSpeed;
+ MV_U8 boardEthSmiAddr;
+
+}MV_BOARD_MAC_INFO;
+
+typedef struct _boardMppInfo
+{
+ MV_U32 mppGroup[MV_BOARD_MAX_MPP];
+
+}MV_BOARD_MPP_INFO;
+
+typedef struct _boardInfo
+{
+ char boardName[MV_BOARD_NAME_LEN];
+ MV_U8 numBoardMppTypeValue;
+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue;
+ MV_U8 numBoardMppConfigValue;
+ MV_BOARD_MPP_INFO* pBoardMppConfigValue;
+ MV_U32 intsGppMaskLow;
+ MV_U32 intsGppMaskHigh;
+ MV_U8 numBoardDeviceIf;
+ MV_DEV_CS_INFO* pDevCsInfo;
+ MV_U8 numBoardTwsiDev;
+ MV_BOARD_TWSI_INFO* pBoardTwsiDev;
+ MV_U8 numBoardMacInfo;
+ MV_BOARD_MAC_INFO* pBoardMacInfo;
+ MV_U8 numBoardGppInfo;
+ MV_BOARD_GPP_INFO* pBoardGppInfo;
+ MV_U8 activeLedsNumber;
+ MV_U8* pLedGppPin;
+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */
+ /* GPP values */
+ MV_U32 gppOutEnValLow;
+ MV_U32 gppOutEnValHigh;
+ MV_U32 gppOutValLow;
+ MV_U32 gppOutValHigh;
+ MV_U32 gppPolarityValLow;
+ MV_U32 gppPolarityValHigh;
+
+ /* Switch Configuration */
+ MV_BOARD_SWITCH_INFO* pSwitchInfo;
+}MV_BOARD_INFO;
+
+
+
+MV_VOID mvBoardEnvInit(MV_VOID);
+MV_U32 mvBoardIdGet(MV_VOID);
+MV_U16 mvBoardModelGet(MV_VOID);
+MV_U16 mvBoardRevGet(MV_VOID);
+MV_STATUS mvBoardNameGet(char *pNameBuff);
+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum);
+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum);
+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum);
+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum);
+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum);
+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum);
+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum);
+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum);
+MV_BOOL mvBoardIsPortInGmii(MV_VOID);
+MV_U32 mvBoardTclkGet(MV_VOID);
+MV_U32 mvBoardSysClkGet(MV_VOID);
+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId);
+MV_VOID mvBoardDebugLed(MV_U32 hexNum);
+MV_32 mvBoardMppGet(MV_U32 mppGroupNum);
+
+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID);
+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID);
+
+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID);
+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID);
+
+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index);
+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index);
+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index);
+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index);
+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass);
+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass);
+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass,
+ MV_BOARD_MPP_TYPE_CLASS mppGroupType);
+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID);
+MV_VOID mvBoardMppMuxSet(MV_VOID);
+MV_VOID mvBoardTdmMppSet(MV_32 chType);
+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode);
+
+MV_VOID mvBoardMppModuleTypePrint(MV_VOID);
+MV_VOID mvBoardReset(MV_VOID);
+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum);
+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal);
+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data);
+/* Board devices API managments */
+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass);
+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass);
+
+/* Gpio Pin Connections API */
+MV_32 mvBoardUSBVbusGpioPinGet(int devId);
+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId);
+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin);
+
+MV_32 mvBoardResetGpioPinGet(MV_VOID);
+MV_32 mvBoardRTCGpioPinGet(MV_VOID);
+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID);
+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID);
+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum);
+
+MV_32 mvBoardSDIOGpioPinGet(MV_VOID);
+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode);
+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index);
+
+MV_32 mvBoardNandWidthGet(void);
+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode);
+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode);
+#endif /* __INCmvBoardEnvLibh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c
new file mode 100644
index 000000000..e256c4f70
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c
@@ -0,0 +1,848 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "mvCommon.h"
+#include "mvBoardEnvLib.h"
+#include "mvBoardEnvSpec.h"
+#include "twsi/mvTwsi.h"
+
+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0
+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7
+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2
+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3
+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1
+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2
+#else
+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
+#endif
+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0
+
+
+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {
+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT},
+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
+ };
+
+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {
+ {BOARD_MAC_SPEED_AUTO, 0x8},
+ {BOARD_MAC_SPEED_AUTO, 0x9}
+ };
+
+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] =
+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
+ {{MV_BOARD_AUTO, MV_BOARD_AUTO}
+ };
+
+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] =
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+ {
+ {BOARD_GPP_TSU_DIRCTION, 33}
+ /*muxed with TDM/Audio module via IOexpender
+ {BOARD_GPP_SDIO_DETECT, 38},
+ {BOARD_GPP_USB_VBUS, 49}*/
+ };
+
+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ {
+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
+ };
+#else
+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+#endif
+
+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] =
+ {{{
+ DB_88F6281A_MPP0_7,
+ DB_88F6281A_MPP8_15,
+ DB_88F6281A_MPP16_23,
+ DB_88F6281A_MPP24_31,
+ DB_88F6281A_MPP32_39,
+ DB_88F6281A_MPP40_47,
+ DB_88F6281A_MPP48_55
+ }}};
+
+
+MV_BOARD_INFO db88f6281AInfo = {
+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ db88f6281AInfoBoardMppTypeInfo,
+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ db88f6281AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ 0, /* intsGppMaskHigh */
+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ db88f6281AInfoBoardDeCsInfo,
+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ db88f6281AInfoBoardTwsiDev,
+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ db88f6281AInfoBoardMacInfo,
+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ db88f6281AInfoBoardGppInfo,
+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ DB_88F6281A_OE_LOW, /* gppOutEnLow */
+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */
+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */
+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ BIT6, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+
+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0
+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2
+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2
+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5
+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1
+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2
+#else
+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1
+#endif
+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0
+
+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {{BOARD_MAC_SPEED_1000M, 0xa},
+ {BOARD_MAC_SPEED_AUTO, 0xb}
+ };
+
+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] =
+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4},
+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */
+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0},
+ {-1, {-1}, -1, -1, -1}};
+
+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {
+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */
+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}
+ };
+
+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] =
+ {{MV_BOARD_RGMII, MV_BOARD_TDM}
+ };
+
+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ {
+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
+ };
+#else
+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+#endif
+
+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] =
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+ {{BOARD_GPP_SDIO_DETECT, 28},
+ {BOARD_GPP_USB_OC, 29},
+ {BOARD_GPP_WPS_BUTTON, 35},
+ {BOARD_GPP_MV_SWITCH, 38},
+ {BOARD_GPP_USB_VBUS, 49}
+ };
+
+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] =
+ {{{
+ RD_88F6281A_MPP0_7,
+ RD_88F6281A_MPP8_15,
+ RD_88F6281A_MPP16_23,
+ RD_88F6281A_MPP24_31,
+ RD_88F6281A_MPP32_39,
+ RD_88F6281A_MPP40_47,
+ RD_88F6281A_MPP48_55
+ }}};
+
+MV_BOARD_INFO rd88f6281AInfo = {
+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */
+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ rd88f6281AInfoBoardMppTypeInfo,
+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ rd88f6281AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ (1 << 3), /* intsGppMaskHigh */
+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ rd88f6281AInfoBoardDeCsInfo,
+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ rd88f6281AInfoBoardTwsiDev,
+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ rd88f6281AInfoBoardMacInfo,
+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ rd88f6281AInfoBoardGppInfo,
+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ RD_88F6281A_OE_LOW, /* gppOutEnLow */
+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */
+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */
+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ BIT6, /* gppPolarityValHigh */
+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */
+};
+
+
+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0
+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7
+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2
+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3
+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1
+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2
+#else
+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
+#endif
+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0
+
+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {
+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT},
+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
+ };
+
+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {
+ {BOARD_MAC_SPEED_AUTO, 0x8},
+ {BOARD_MAC_SPEED_AUTO, 0x9}
+ };
+
+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] =
+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
+ {{MV_BOARD_AUTO, MV_BOARD_OTHER}
+ };
+
+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ {
+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
+ };
+#else
+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+#endif
+
+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] =
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+ {
+ {BOARD_GPP_SDIO_WP, 20},
+ {BOARD_GPP_USB_VBUS, 22},
+ {BOARD_GPP_SDIO_DETECT, 23},
+ };
+
+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] =
+ {{{
+ DB_88F6192A_MPP0_7,
+ DB_88F6192A_MPP8_15,
+ DB_88F6192A_MPP16_23,
+ DB_88F6192A_MPP24_31,
+ DB_88F6192A_MPP32_35
+ }}};
+
+MV_BOARD_INFO db88f6192AInfo = {
+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ db88f6192AInfoBoardMppTypeInfo,
+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ db88f6192AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ (1 << 3), /* intsGppMaskHigh */
+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ db88f6192AInfoBoardDeCsInfo,
+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ db88f6192AInfoBoardTwsiDev,
+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ db88f6192AInfoBoardMacInfo,
+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ db88f6192AInfoBoardGppInfo,
+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ DB_88F6192A_OE_LOW, /* gppOutEnLow */
+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */
+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */
+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1
+
+MV_BOARD_INFO db88f6190AInfo = {
+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ db88f6192AInfoBoardMppTypeInfo,
+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ db88f6192AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ (1 << 3), /* intsGppMaskHigh */
+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ db88f6192AInfoBoardDeCsInfo,
+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ db88f6192AInfoBoardTwsiDev,
+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ db88f6192AInfoBoardMacInfo,
+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ db88f6192AInfoBoardGppInfo,
+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ DB_88F6192A_OE_LOW, /* gppOutEnLow */
+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */
+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */
+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0
+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0
+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1
+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE
+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1
+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1
+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1
+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3
+
+MV_U8 rd88f6192AInfoBoardDebugLedIf[] =
+ {17, 28, 29};
+
+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {{BOARD_MAC_SPEED_AUTO, 0x8}
+ };
+
+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] =
+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
+ {{MV_BOARD_OTHER, MV_BOARD_OTHER}
+ };
+
+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+
+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] =
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+ {
+ {BOARD_GPP_USB_VBUS_EN, 10},
+ {BOARD_GPP_USB_HOST_DEVICE, 11},
+ {BOARD_GPP_RESET, 14},
+ {BOARD_GPP_POWER_ON_LED, 15},
+ {BOARD_GPP_HDD_POWER, 16},
+ {BOARD_GPP_WPS_BUTTON, 24},
+ {BOARD_GPP_TS_BUTTON_C, 25},
+ {BOARD_GPP_USB_VBUS, 26},
+ {BOARD_GPP_USB_OC, 27},
+ {BOARD_GPP_TS_BUTTON_U, 30},
+ {BOARD_GPP_TS_BUTTON_R, 31},
+ {BOARD_GPP_TS_BUTTON_L, 32},
+ {BOARD_GPP_TS_BUTTON_D, 34},
+ {BOARD_GPP_FAN_POWER, 35}
+ };
+
+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] =
+ {{{
+ RD_88F6192A_MPP0_7,
+ RD_88F6192A_MPP8_15,
+ RD_88F6192A_MPP16_23,
+ RD_88F6192A_MPP24_31,
+ RD_88F6192A_MPP32_35
+ }}};
+
+MV_BOARD_INFO rd88f6192AInfo = {
+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */
+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ rd88f6192AInfoBoardMppTypeInfo,
+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ rd88f6192AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ (1 << 3), /* intsGppMaskHigh */
+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ rd88f6192AInfoBoardDeCsInfo,
+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ NULL,
+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ rd88f6192AInfoBoardMacInfo,
+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ rd88f6192AInfoBoardGppInfo,
+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ rd88f6192AInfoBoardDebugLedIf,
+ 0, /* ledsPolarity */
+ RD_88F6192A_OE_LOW, /* gppOutEnLow */
+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */
+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */
+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+MV_BOARD_INFO rd88f6190AInfo = {
+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */
+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ rd88f6192AInfoBoardMppTypeInfo,
+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ rd88f6192AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ (1 << 3), /* intsGppMaskHigh */
+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ rd88f6192AInfoBoardDeCsInfo,
+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ NULL,
+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ rd88f6192AInfoBoardMacInfo,
+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ rd88f6192AInfoBoardGppInfo,
+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ rd88f6192AInfoBoardDebugLedIf,
+ 0, /* ledsPolarity */
+ RD_88F6192A_OE_LOW, /* gppOutEnLow */
+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */
+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */
+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0
+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5
+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1
+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0
+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2
+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1
+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1
+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0
+
+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {
+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT},
+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT},
+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT},
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT},
+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT}
+ };
+
+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {{BOARD_MAC_SPEED_AUTO, 0x8}
+ };
+
+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] =
+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+ {
+ /* Muxed with TDM/Audio module via IOexpender
+ {BOARD_GPP_USB_VBUS, 6} */
+ };
+
+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] =
+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1,
+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */
+ {{MV_BOARD_OTHER, MV_BOARD_AUTO}
+ };
+
+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_NAND_BOOT)
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+#else
+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+#endif
+
+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] =
+ {{{
+ DB_88F6180A_MPP0_7,
+ DB_88F6180A_MPP8_15,
+ DB_88F6180A_MPP16_23,
+ DB_88F6180A_MPP24_31,
+ DB_88F6180A_MPP32_39,
+ DB_88F6180A_MPP40_44
+ }}};
+
+MV_BOARD_INFO db88f6180AInfo = {
+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */
+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ db88f6180AInfoBoardMppTypeInfo,
+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ db88f6180AInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ 0, /* intsGppMaskHigh */
+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ db88f6180AInfoBoardDeCsInfo,
+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ db88f6180AInfoBoardTwsiDev,
+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ db88f6180AInfoBoardMacInfo,
+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ NULL,
+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ DB_88F6180A_OE_LOW, /* gppOutEnLow */
+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */
+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */
+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+
+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0
+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1
+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1
+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0
+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1
+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2
+#else
+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1
+#endif
+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4
+
+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] =
+ {38, 39, 40, 41};
+
+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {{BOARD_MAC_SPEED_AUTO, 0x8}
+ };
+
+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {
+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT}
+ };
+
+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] =
+ {{MV_BOARD_OTHER, MV_BOARD_OTHER}
+ };
+
+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ {
+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
+ };
+#else
+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+#endif
+
+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] =
+ {{{
+ RD_88F6281A_PCAC_MPP0_7,
+ RD_88F6281A_PCAC_MPP8_15,
+ RD_88F6281A_PCAC_MPP16_23,
+ RD_88F6281A_PCAC_MPP24_31,
+ RD_88F6281A_PCAC_MPP32_39,
+ RD_88F6281A_PCAC_MPP40_47,
+ RD_88F6281A_PCAC_MPP48_55
+ }}};
+
+MV_BOARD_INFO rd88f6281APcacInfo = {
+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */
+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */
+ rd88f6281APcacInfoBoardMppTypeInfo,
+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ rd88f6281APcacInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ (1 << 3), /* intsGppMaskHigh */
+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ rd88f6281APcacInfoBoardDeCsInfo,
+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ rd88f6281APcacInfoBoardTwsiDev,
+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ rd88f6281APcacInfoBoardMacInfo,
+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ 0,
+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */
+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */
+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */
+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+
+/* 6281 Sheeva Plug*/
+
+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0
+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0
+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1
+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0
+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1
+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1
+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1
+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1
+
+MV_U8 sheevaPlugInfoBoardDebugLedIf[] =
+ {49};
+
+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {{BOARD_MAC_SPEED_AUTO, 0x0}};
+
+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}};
+
+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] =
+ {{MV_BOARD_OTHER, MV_BOARD_OTHER}
+ };
+
+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+
+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] =
+ {{{
+ RD_SHEEVA_PLUG_MPP0_7,
+ RD_SHEEVA_PLUG_MPP8_15,
+ RD_SHEEVA_PLUG_MPP16_23,
+ RD_SHEEVA_PLUG_MPP24_31,
+ RD_SHEEVA_PLUG_MPP32_39,
+ RD_SHEEVA_PLUG_MPP40_47,
+ RD_SHEEVA_PLUG_MPP48_55
+ }}};
+
+MV_BOARD_INFO sheevaPlugInfo = {
+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */
+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */
+ sheevaPlugInfoBoardMppTypeInfo,
+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ sheevaPlugInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ 0, /* intsGppMaskHigh */
+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ sheevaPlugInfoBoardDeCsInfo,
+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ sheevaPlugInfoBoardTwsiDev,
+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ sheevaPlugInfoBoardMacInfo,
+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ 0,
+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ sheevaPlugInfoBoardDebugLedIf,
+ 0, /* ledsPolarity */
+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */
+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */
+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */
+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+/* Customer specific board place holder*/
+
+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0
+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0
+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0
+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0
+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0
+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
+#else
+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0
+#endif
+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0
+
+MV_U8 dbCustomerInfoBoardDebugLedIf[] =
+ {0};
+
+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] =
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+ {{BOARD_MAC_SPEED_AUTO, 0x0}};
+
+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] =
+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}};
+
+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] =
+ {{MV_BOARD_OTHER, MV_BOARD_OTHER}
+ };
+
+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] =
+ /*{deviceCS, params, devType, devWidth}*/
+#if defined(MV_NAND) && defined(MV_NAND_BOOT)
+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */
+#elif defined(MV_NAND) && defined(MV_SPI_BOOT)
+ {
+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */
+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */
+ };
+#else
+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */
+#endif
+
+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] =
+ {{{
+ DB_CUSTOMER_MPP0_7,
+ DB_CUSTOMER_MPP8_15,
+ DB_CUSTOMER_MPP16_23,
+ DB_CUSTOMER_MPP24_31,
+ DB_CUSTOMER_MPP32_39,
+ DB_CUSTOMER_MPP40_47,
+ DB_CUSTOMER_MPP48_55
+ }}};
+
+MV_BOARD_INFO dbCustomerInfo = {
+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */
+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */
+ dbCustomerInfoBoardMppTypeInfo,
+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */
+ dbCustomerInfoBoardMppConfigValue,
+ 0, /* intsGppMaskLow */
+ 0, /* intsGppMaskHigh */
+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */
+ dbCustomerInfoBoardDeCsInfo,
+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */
+ dbCustomerInfoBoardTwsiDev,
+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */
+ dbCustomerInfoBoardMacInfo,
+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */
+ 0,
+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */
+ NULL,
+ 0, /* ledsPolarity */
+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */
+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */
+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */
+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */
+ 0, /* gppPolarityValLow */
+ 0, /* gppPolarityValHigh */
+ NULL /* pSwitchInfo */
+};
+
+MV_BOARD_INFO* boardInfoTbl[] = {
+ &db88f6281AInfo,
+ &rd88f6281AInfo,
+ &db88f6192AInfo,
+ &rd88f6192AInfo,
+ &db88f6180AInfo,
+ &db88f6190AInfo,
+ &rd88f6190AInfo,
+ &rd88f6281APcacInfo,
+ &dbCustomerInfo,
+ &sheevaPlugInfo
+ };
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h
new file mode 100644
index 000000000..0372eee5d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h
@@ -0,0 +1,262 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvBoardEnvSpech
+#define __INCmvBoardEnvSpech
+
+#include "mvSysHwConfig.h"
+
+
+/* For future use */
+#define BD_ID_DATA_START_OFFS 0x0
+#define BD_DETECT_SEQ_OFFS 0x0
+#define BD_SYS_NUM_OFFS 0x4
+#define BD_NAME_OFFS 0x8
+
+/* I2C bus addresses */
+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */
+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT
+#define MV_BOARD_DIMM0_I2C_ADDR 0x56
+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT
+#define MV_BOARD_DIMM1_I2C_ADDR 0x54
+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT
+#define MV_BOARD_EEPROM_I2C_ADDR 0x51
+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50
+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2
+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0
+
+#define BOOT_FLASH_INDEX 0
+#define MAIN_FLASH_INDEX 1
+
+#define BOARD_ETH_START_PORT_NUM 0
+
+/* Supported clocks */
+#define MV_BOARD_TCLK_100MHZ 100000000
+#define MV_BOARD_TCLK_125MHZ 125000000
+#define MV_BOARD_TCLK_133MHZ 133333333
+#define MV_BOARD_TCLK_150MHZ 150000000
+#define MV_BOARD_TCLK_166MHZ 166666667
+#define MV_BOARD_TCLK_200MHZ 200000000
+
+#define MV_BOARD_SYSCLK_100MHZ 100000000
+#define MV_BOARD_SYSCLK_125MHZ 125000000
+#define MV_BOARD_SYSCLK_133MHZ 133333333
+#define MV_BOARD_SYSCLK_150MHZ 150000000
+#define MV_BOARD_SYSCLK_166MHZ 166666667
+#define MV_BOARD_SYSCLK_200MHZ 200000000
+#define MV_BOARD_SYSCLK_233MHZ 233333333
+#define MV_BOARD_SYSCLK_250MHZ 250000000
+#define MV_BOARD_SYSCLK_267MHZ 266666667
+#define MV_BOARD_SYSCLK_300MHZ 300000000
+#define MV_BOARD_SYSCLK_333MHZ 333333334
+#define MV_BOARD_SYSCLK_400MHZ 400000000
+
+#define MV_BOARD_REFCLK_25MHZ 25000000
+
+/* Board specific */
+/* =============================== */
+
+/* boards ID numbers */
+
+#define BOARD_ID_BASE 0x0
+
+/* New board ID numbers */
+#define DB_88F6281A_BP_ID (BOARD_ID_BASE)
+#define DB_88F6281_BP_MLL_ID 1680
+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1)
+#define RD_88F6281_MLL_ID 1682
+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2)
+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3)
+#define RD_88F6192_MLL_ID 1681
+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4)
+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5)
+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6)
+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7)
+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8)
+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9)
+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1)
+
+/* DB-88F6281A-BP */
+#if defined(MV_NAND)
+ #define DB_88F6281A_MPP0_7 0x21111111
+#else
+ #define DB_88F6281A_MPP0_7 0x21112220
+#endif
+#define DB_88F6281A_MPP8_15 0x11113311
+#define DB_88F6281A_MPP16_23 0x00551111
+#define DB_88F6281A_MPP24_31 0x00000000
+#define DB_88F6281A_MPP32_39 0x00000000
+#define DB_88F6281A_MPP40_47 0x00000000
+#define DB_88F6281A_MPP48_55 0x00000000
+#define DB_88F6281A_OE_LOW 0x0
+#if defined(MV_TDM_5CHANNELS)
+ #define DB_88F6281A_OE_HIGH (BIT6)
+#else
+#define DB_88F6281A_OE_HIGH 0x0
+#endif
+#define DB_88F6281A_OE_VAL_LOW 0x0
+#define DB_88F6281A_OE_VAL_HIGH 0x0
+
+/* RD-88F6281A */
+#if defined(MV_NAND)
+ #define RD_88F6281A_MPP0_7 0x21111111
+#else
+ #define RD_88F6281A_MPP0_7 0x21112220
+#endif
+#define RD_88F6281A_MPP8_15 0x11113311
+#define RD_88F6281A_MPP16_23 0x33331111
+#define RD_88F6281A_MPP24_31 0x33003333
+#define RD_88F6281A_MPP32_39 0x20440533
+#define RD_88F6281A_MPP40_47 0x22202222
+#define RD_88F6281A_MPP48_55 0x00000002
+#define RD_88F6281A_OE_LOW (BIT28 | BIT29)
+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17)
+#define RD_88F6281A_OE_VAL_LOW 0x0
+#define RD_88F6281A_OE_VAL_HIGH 0x0
+
+/* DB-88F6192A-BP */
+#if defined(MV_NAND)
+ #define DB_88F6192A_MPP0_7 0x21111111
+#else
+ #define DB_88F6192A_MPP0_7 0x21112220
+#endif
+#define DB_88F6192A_MPP8_15 0x11113311
+#define DB_88F6192A_MPP16_23 0x00501111
+#define DB_88F6192A_MPP24_31 0x00000000
+#define DB_88F6192A_MPP32_35 0x00000000
+#define DB_88F6192A_OE_LOW (BIT22 | BIT23)
+#define DB_88F6192A_OE_HIGH 0x0
+#define DB_88F6192A_OE_VAL_LOW 0x0
+#define DB_88F6192A_OE_VAL_HIGH 0x0
+
+/* RD-88F6192A */
+#define RD_88F6192A_MPP0_7 0x01222222
+#define RD_88F6192A_MPP8_15 0x00000011
+#define RD_88F6192A_MPP16_23 0x05550000
+#define RD_88F6192A_MPP24_31 0x0
+#define RD_88F6192A_MPP32_35 0x0
+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31)
+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2)
+#define RD_88F6192A_OE_VAL_LOW 0x18400
+#define RD_88F6192A_OE_VAL_HIGH 0x8
+
+/* DB-88F6180A-BP */
+#if defined(MV_NAND)
+ #define DB_88F6180A_MPP0_7 0x21111111
+#else
+ #define DB_88F6180A_MPP0_7 0x01112222
+#endif
+#define DB_88F6180A_MPP8_15 0x11113311
+#define DB_88F6180A_MPP16_23 0x00001111
+#define DB_88F6180A_MPP24_31 0x0
+#define DB_88F6180A_MPP32_39 0x4444c000
+#define DB_88F6180A_MPP40_44 0x00044444
+#define DB_88F6180A_OE_LOW 0x0
+#define DB_88F6180A_OE_HIGH 0x0
+#define DB_88F6180A_OE_VAL_LOW 0x0
+#define DB_88F6180A_OE_VAL_HIGH 0x0
+
+/* RD-88F6281A_PCAC */
+#define RD_88F6281A_PCAC_MPP0_7 0x21111111
+#define RD_88F6281A_PCAC_MPP8_15 0x00003311
+#define RD_88F6281A_PCAC_MPP16_23 0x00001100
+#define RD_88F6281A_PCAC_MPP24_31 0x00000000
+#define RD_88F6281A_PCAC_MPP32_39 0x00000000
+#define RD_88F6281A_PCAC_MPP40_47 0x00000000
+#define RD_88F6281A_PCAC_MPP48_55 0x00000000
+#define RD_88F6281A_PCAC_OE_LOW 0x0
+#define RD_88F6281A_PCAC_OE_HIGH 0x0
+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0
+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0
+
+/* SHEEVA PLUG */
+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111
+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322
+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111
+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000
+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000
+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000
+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000
+#define RD_SHEEVA_PLUG_OE_LOW 0x0
+#define RD_SHEEVA_PLUG_OE_HIGH 0x0
+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29)
+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14)
+
+/* DB-CUSTOMER */
+#define DB_CUSTOMER_MPP0_7 0x21111111
+#define DB_CUSTOMER_MPP8_15 0x00003311
+#define DB_CUSTOMER_MPP16_23 0x00001100
+#define DB_CUSTOMER_MPP24_31 0x00000000
+#define DB_CUSTOMER_MPP32_39 0x00000000
+#define DB_CUSTOMER_MPP40_47 0x00000000
+#define DB_CUSTOMER_MPP48_55 0x00000000
+#define DB_CUSTOMER_OE_LOW 0x0
+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9)))
+#define DB_CUSTOMER_OE_VAL_LOW 0x0
+#define DB_CUSTOMER_OE_VAL_HIGH 0x0
+
+#endif /* __INCmvBoardEnvSpech */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c
new file mode 100644
index 000000000..fed0fa114
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c
@@ -0,0 +1,320 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include "cpu/mvCpu.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvRegs.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+/* locals */
+
+/*******************************************************************************
+* mvCpuPclkGet - Get the CPU pClk (pipe clock)
+*
+* DESCRIPTION:
+* This routine extract the CPU core clock.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit clock cycles in MHertz.
+*
+*******************************************************************************/
+/* 6180 have different clk reset sampling */
+
+static MV_U32 mvCpu6180PclkGet(MV_VOID)
+{
+ MV_U32 tmpPClkRate=0;
+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
+
+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180;
+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180;
+
+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk;
+
+ return tmpPClkRate;
+}
+
+
+MV_U32 mvCpuPclkGet(MV_VOID)
+{
+#if defined(PCLCK_AUTO_DETECT)
+ MV_U32 tmpPClkRate=0;
+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL;
+
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ return mvCpu6180PclkGet();
+
+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate);
+ tmpPClkRate = cpuCLK[tmpPClkRate];
+
+ return tmpPClkRate;
+#else
+ return MV_DEFAULT_PCLK
+#endif
+}
+
+/*******************************************************************************
+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock)
+*
+* DESCRIPTION:
+* This routine extract the CPU L2 clock.
+*
+* RETURN:
+* 32bit clock cycles in Hertz.
+*
+*******************************************************************************/
+static MV_U32 mvCpu6180L2ClkGet(MV_VOID)
+{
+ MV_U32 L2ClkRate=0;
+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
+
+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180;
+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180;
+
+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk;
+
+ return L2ClkRate;
+
+}
+
+MV_U32 mvCpuL2ClkGet(MV_VOID)
+{
+#ifdef L2CLK_AUTO_DETECT
+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio;
+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL;
+
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ return mvCpu6180L2ClkGet();
+
+ pClkRate = mvCpuPclkGet();
+
+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp);
+
+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]);
+
+ return L2ClkRate;
+#else
+ return MV_BOARD_DEFAULT_L2CLK;
+#endif
+}
+
+
+/*******************************************************************************
+* mvCpuNameGet - Get CPU name
+*
+* DESCRIPTION:
+* This function returns a string describing the CPU model and revision.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
+*
+* RETURN:
+* None.
+*******************************************************************************/
+MV_VOID mvCpuNameGet(char *pNameBuff)
+{
+ MV_U32 cpuModel;
+
+ cpuModel = mvOsCpuPartGet();
+
+ /* The CPU module is indicated in the Processor Version Register (PVR) */
+ switch(cpuModel)
+ {
+ case CPU_PART_MRVL131:
+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet());
+ break;
+ case CPU_PART_ARM926:
+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet());
+ break;
+ case CPU_PART_ARM946:
+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet());
+ break;
+ default:
+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet());
+ break;
+ } /* switch */
+
+ return;
+}
+
+
+#define MV_PROC_STR_SIZE 50
+
+static void mvCpuIfGetL2EccMode(MV_8 *buf)
+{
+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG);
+ if (regVal & BIT2)
+ mvOsSPrintf(buf, "L2 ECC Enabled");
+ else
+ mvOsSPrintf(buf, "L2 ECC Disabled");
+}
+
+static void mvCpuIfGetL2Mode(MV_8 *buf)
+{
+ MV_U32 regVal = 0;
+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
+ if (regVal & BIT22)
+ mvOsSPrintf(buf, "L2 Enabled");
+ else
+ mvOsSPrintf(buf, "L2 Disabled");
+}
+
+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf)
+{
+ MV_U32 regVal = 0;
+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
+ if (regVal & BIT24)
+ mvOsSPrintf(buf, "L2 Prefetch Disabled");
+ else
+ mvOsSPrintf(buf, "L2 Prefetch Enabled");
+}
+
+static void mvCpuIfGetWriteAllocMode(MV_8 *buf)
+{
+ MV_U32 regVal = 0;
+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
+ if (regVal & BIT28)
+ mvOsSPrintf(buf, "Write Allocate Enabled");
+ else
+ mvOsSPrintf(buf, "Write Allocate Disabled");
+}
+
+static void mvCpuIfGetCpuStreamMode(MV_8 *buf)
+{
+ MV_U32 regVal = 0;
+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
+ if (regVal & BIT29)
+ mvOsSPrintf(buf, "CPU Streaming Enabled");
+ else
+ mvOsSPrintf(buf, "CPU Streaming Disabled");
+}
+
+static void mvCpuIfPrintCpuRegs(void)
+{
+ MV_U32 regVal = 0;
+
+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal);
+
+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */
+ mvOsPrintf("Control Reg = 0x%x\n",regVal);
+
+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */
+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal);
+
+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */
+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal);
+
+}
+
+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index)
+{
+ MV_U32 count = 0;
+
+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE];
+ MV_8 L2_En_str[MV_PROC_STR_SIZE];
+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE];
+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE];
+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE];
+
+ mvCpuIfGetL2Mode(L2_En_str);
+ mvCpuIfGetL2EccMode(L2_ECC_str);
+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str);
+ mvCpuIfGetWriteAllocMode(Write_Alloc_str);
+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str);
+ mvCpuIfPrintCpuRegs();
+
+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str);
+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str);
+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str);
+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str);
+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str);
+ return count;
+}
+
+MV_U32 whoAmI(MV_VOID)
+{
+ return 0;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h
new file mode 100644
index 000000000..7f58b03f1
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h
@@ -0,0 +1,99 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvCpuh
+#define __INCmvCpuh
+
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+
+/* defines */
+#define CPU_PART_MRVL131 0x131
+#define CPU_PART_ARM926 0x926
+#define CPU_PART_ARM946 0x946
+#define MV_CPU_ARM_CLK_ELM_SIZE 12
+#define MV_CPU_ARM_CLK_RATIO_OFF 8
+#define MV_CPU_ARM_CLK_DDR_OFF 4
+
+#ifndef MV_ASMLANGUAGE
+typedef struct _mvCpuArmClk
+{
+ MV_U32 cpuClk; /* CPU clock in MHz */
+ MV_U32 ddrClk; /* DDR clock in MHz */
+ MV_U32 l2Clk; /* CPU DDR clock ratio */
+
+}MV_CPU_ARM_CLK;
+
+MV_U32 mvCpuPclkGet(MV_VOID);
+MV_VOID mvCpuNameGet(char *pNameBuff);
+MV_U32 mvCpuL2ClkGet(MV_VOID);
+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index);
+MV_U32 whoAmI(MV_VOID);
+
+#endif /* MV_ASMLANGUAGE */
+
+
+#endif /* __INCmvCpuh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c
new file mode 100644
index 000000000..fbe7c566d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c
@@ -0,0 +1,296 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvCtrlEnvAddrDec.h - Marvell controller address decode library
+*
+* DESCRIPTION:
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+/* includes */
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
+#include "ddr2/mvDramIfRegs.h"
+#include "pex/mvPexRegs.h"
+
+#define MV_DEBUG
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+/* Default Attributes array */
+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY;
+extern MV_TARGET *sampleAtResetTargetArray;
+/* Dram\AHBToMbus\PEX share regsiter */
+
+#define CTRL_DEC_BASE_OFFS 16
+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS)
+#define CTRL_DEC_BASE_ALIGNMENT 0x10000
+
+#define CTRL_DEC_SIZE_OFFS 16
+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS)
+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000
+
+#define CTRL_DEC_WIN_EN BIT0
+
+
+
+/*******************************************************************************
+* mvCtrlAddrDecToReg - Get address decode register format values
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs)
+{
+
+ MV_U32 baseToReg=0 , sizeToReg=0;
+
+ /* BaseLow[31:16] => base register [31:16] */
+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK;
+
+ /* Write to address decode Base Address Register */
+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK;
+ pAddrDecRegs->baseReg |= baseToReg;
+
+ /* Get size register value according to window size */
+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT);
+
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ return MV_BAD_PARAM;
+ }
+
+ /* set size */
+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK;
+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS);
+
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvCtrlRegToAddrDec - Extract address decode struct from registers.
+*
+* DESCRIPTION:
+* This function extract address decode struct from address decode
+* registers given as parameters.
+*
+* INPUT:
+* pAddrDecRegs - Address decode register struct.
+*
+* OUTPUT:
+* pAddrDecWin - Target window data structure.
+*
+* RETURN:
+* MV_BAD_PARAM if address decode registers data is invalid.
+*
+*******************************************************************************/
+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin)
+{
+ MV_U32 sizeRegVal;
+
+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >>
+ CTRL_DEC_SIZE_OFFS;
+
+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT);
+
+
+ /* Extract base address */
+ /* Base register [31:16] ==> baseLow[31:16] */
+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK;
+
+ pAddrDecWin->baseHigh = 0;
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvCtrlAttribGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+
+MV_STATUS mvCtrlAttribGet(MV_TARGET target,
+ MV_TARGET_ATTRIB *targetAttrib)
+{
+
+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib;
+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId;
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvCtrlGetAttrib -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib)
+{
+ MV_TARGET target;
+ MV_TARGET x;
+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++)
+ {
+ x = MV_CHANGE_BOOT_CS(target);
+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) &&
+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId))
+ {
+ /* found it */
+ break;
+ }
+ }
+
+ return target;
+}
+
+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
+ MV_DEC_WIN_PARAMS *pWinParam)
+{
+ MV_U32 baseToReg=0, sizeToReg=0;
+
+ /* BaseLow[31:16] => base register [31:16] */
+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK;
+
+ /* Write to address decode Base Address Register */
+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK;
+ pWinParam->baseAddr |= baseToReg;
+
+ /* Get size register value according to window size */
+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT);
+
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n");
+ return MV_BAD_PARAM;
+ }
+ pWinParam->size = sizeToReg;
+
+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib;
+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId;
+
+ return MV_OK;
+}
+
+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
+ MV_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttrib;
+
+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr;
+
+ /* Upper 32bit address base is supported under PCI High Address remap */
+ pAddrDecWin->addrWin.baseHigh = 0;
+
+ /* Prepare sizeReg to ctrlRegToSize function */
+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT);
+
+ if (-1 == pAddrDecWin->addrWin.size)
+ {
+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n"));
+ return MV_BAD_PARAM;
+ }
+ targetAttrib.targetId = pWinParam->targetId;
+ targetAttrib.attrib = pWinParam->attrib;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ return MV_OK;
+}
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h
new file mode 100644
index 000000000..946737f58
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h
@@ -0,0 +1,203 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvCtrlEnvAddrDech
+#define __INCmvCtrlEnvAddrDech
+
+/* includes */
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvRegs.h"
+
+
+/* defines */
+/* DUnit attributes */
+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0
+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0
+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS)
+
+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1
+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1
+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS)
+
+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2
+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2
+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS)
+
+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3
+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3
+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS)
+
+/* RUnit (Device) attributes */
+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0
+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0
+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS)
+
+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1
+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1
+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS)
+
+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2
+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2
+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS)
+
+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4
+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4
+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS)
+
+/* LMaster (PCI) attributes */
+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0
+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0
+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS)
+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS)
+
+
+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1
+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1
+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS)
+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS)
+
+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2
+
+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3
+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3
+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS)
+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS)
+
+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4
+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4
+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS)
+
+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6
+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6
+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS)
+
+/* PEX Attributes */
+#define ATMWCR_WIN_PEX_TYPE_OFFS 3
+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3
+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS)
+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS)
+
+/* typedefs */
+
+/* Unsupported attributes for address decode: */
+/* 2) PCI0/1_REQ64n control */
+
+typedef struct _mvDecRegs
+{
+ MV_U32 baseReg;
+ MV_U32 baseRegHigh;
+ MV_U32 sizeReg;
+
+}MV_DEC_REGS;
+
+typedef struct _mvTargetAttrib
+{
+ MV_U8 attrib; /* chip select attributes */
+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */
+
+}MV_TARGET_ATTRIB;
+
+
+/* This structure describes address decode window */
+typedef struct _mvDecWin
+{
+ MV_TARGET target; /* Target for addr decode window */
+ MV_ADDR_WIN addrWin; /* Address window of target */
+ MV_BOOL enable; /* Window enable/disable */
+}MV_DEC_WIN;
+
+typedef struct _mvDecWinParams
+{
+ MV_TARGET_ID targetId; /* Target ID field */
+ MV_U8 attrib; /* Attribute field */
+ MV_U32 baseAddr; /* Base address in register format */
+ MV_U32 size; /* Size in register format */
+}MV_DEC_WIN_PARAMS;
+
+
+/* mvCtrlEnvAddrDec API list */
+
+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin,
+ MV_DEC_REGS *pAddrDecRegs);
+
+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs,
+ MV_ADDR_WIN *pAddrDecWin);
+
+MV_STATUS mvCtrlAttribGet(MV_TARGET target,
+ MV_TARGET_ATTRIB *targetAttrib);
+
+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib);
+
+
+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
+ MV_DEC_WIN_PARAMS *pWinParam);
+
+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
+ MV_DEC_WIN *pAddrDecWin);
+
+
+
+
+#endif /* __INCmvCtrlEnvAddrDech */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h
new file mode 100644
index 000000000..6f6367a2f
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h
@@ -0,0 +1,98 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvCtrlEnvAsmh
+#define __INCmvCtrlEnvAsmh
+#include "pex/mvPexRegs.h"
+
+#define CHIP_BOND_REG 0x10034
+#define PCKG_OPT_MASK_AS #3
+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK
+
+/* Read device ID into toReg bits 15:0 from 0xd0000000 */
+/* defines */
+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \
+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\
+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */
+
+/* Read device ID into toReg bits 15:0 from 0xf1000000*/
+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \
+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\
+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */
+
+/* Read Revision into toReg bits 7:0 0xd0000000*/
+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \
+ /* Read device revision */ \
+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\
+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */
+
+/* Read Revision into toReg bits 7:0 0xf1000000*/
+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \
+ /* Read device revision */ \
+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\
+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */
+
+
+#endif /* __INCmvCtrlEnvAsmh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c
new file mode 100644
index 000000000..adf451d3e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c
@@ -0,0 +1,1825 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#include "mvCommon.h"
+#include "mvCtrlEnvLib.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+#if defined(MV_INCLUDE_PEX)
+#include "pex/mvPex.h"
+#include "ctrlEnv/sys/mvSysPex.h"
+#endif
+
+#if defined(MV_INCLUDE_GIG_ETH)
+#include "ctrlEnv/sys/mvSysGbe.h"
+#endif
+
+#if defined(MV_INCLUDE_XOR)
+#include "ctrlEnv/sys/mvSysXor.h"
+#endif
+
+#if defined(MV_INCLUDE_SATA)
+#include "ctrlEnv/sys/mvSysSata.h"
+#endif
+
+#if defined(MV_INCLUDE_USB)
+#include "ctrlEnv/sys/mvSysUsb.h"
+#endif
+
+#if defined(MV_INCLUDE_AUDIO)
+#include "ctrlEnv/sys/mvSysAudio.h"
+#endif
+
+#if defined(MV_INCLUDE_CESA)
+#include "ctrlEnv/sys/mvSysCesa.h"
+#endif
+
+#if defined(MV_INCLUDE_TS)
+#include "ctrlEnv/sys/mvSysTs.h"
+#endif
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+/*******************************************************************************
+* mvCtrlEnvInit - Initialize Marvell controller environment.
+*
+* DESCRIPTION:
+* This function get environment information and initialize controller
+* internal/external environment. For example
+* 1) MPP settings according to board MPP macros.
+* NOTE: It is the user responsibility to shut down all DMA channels
+* in device and disable controller sub units interrupts during
+* boot process.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvCtrlEnvInit(MV_VOID)
+{
+ MV_U32 mppGroup;
+ MV_U32 devId;
+ MV_U32 boardId;
+ MV_U32 i;
+ MV_U32 maxMppGrp = 1;
+ MV_U32 mppVal = 0;
+ MV_U32 bootVal = 0;
+ MV_U32 mppGroupType = 0;
+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE;
+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE;
+
+ devId = mvCtrlModelGet();
+ boardId= mvBoardIdGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ maxMppGrp = MV_6281_MPP_MAX_GROUP;
+ break;
+ case MV_6192_DEV_ID:
+ maxMppGrp = MV_6192_MPP_MAX_GROUP;
+ break;
+ case MV_6190_DEV_ID:
+ maxMppGrp = MV_6190_MPP_MAX_GROUP;
+ break;
+ case MV_6180_DEV_ID:
+ maxMppGrp = MV_6180_MPP_MAX_GROUP;
+ break;
+ }
+
+ /* MPP Init */
+ /* We split mpp init to 3 phases:
+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write
+ * in phase 2.
+ * 2. We detect the mpp group type and according the mpp values [35:20].
+ * 3. We detect the mpp group type and according the mpp values [49:36].
+ */
+ /* Mpp phase 1 mpp[19:0] */
+ /* Read MPP group from board level and assign to MPP register */
+ for (mppGroup = 0; mppGroup < 3; mppGroup++)
+ {
+ mppVal = mvBoardMppGet(mppGroup);
+ if (mppGroup == 0)
+ {
+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
+ if (mvCtrlIsBootFromSPI())
+ {
+ mppVal &= ~0xffff;
+ bootVal &= 0xffff;
+ mppVal |= bootVal;
+ }
+ else if (mvCtrlIsBootFromSPIUseNAND())
+ {
+ mppVal &= ~0xf0000000;
+ bootVal &= 0xf0000000;
+ mppVal |= bootVal;
+ }
+ else if (mvCtrlIsBootFromNAND())
+ {
+ mppVal &= ~0xffffff;
+ bootVal &= 0xffffff;
+ mppVal |= bootVal;
+ }
+ }
+
+ if (mppGroup == 2)
+ {
+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
+ if (mvCtrlIsBootFromNAND())
+ {
+ mppVal &= ~0xff00;
+ bootVal &= 0xff00;
+ mppVal |= bootVal;
+ }
+ }
+
+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
+ }
+
+ /* Identify MPPs group */
+ mvBoardMppGroupIdUpdate();
+
+ /* Update MPPs mux relevent only on Marvell DB */
+ if ((boardId == DB_88F6281A_BP_ID) ||
+ (boardId == DB_88F6180A_BP_ID))
+ mvBoardMppMuxSet();
+
+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1);
+
+ /* Mpp phase 2 */
+ /* Read MPP group from board level and assign to MPP register */
+ if (devId != MV_6180_DEV_ID)
+ {
+ i = 0;
+ for (mppGroup = 2; mppGroup < 5; mppGroup++)
+ {
+ if ((mppGroupType == MV_BOARD_OTHER) ||
+ (boardId == RD_88F6281A_ID) ||
+ (boardId == RD_88F6192A_ID) ||
+ (boardId == RD_88F6190A_ID) ||
+ (boardId == RD_88F6281A_PCAC_ID) ||
+ (boardId == SHEEVA_PLUG_ID))
+ mppVal = mvBoardMppGet(mppGroup);
+ else
+ {
+ mppVal = mppGroup1[mppGroupType][i];
+ i++;
+ }
+
+ /* Group 2 is shared mpp[23:16] */
+ if (mppGroup == 2)
+ {
+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
+ mppVal &= ~0xffff;
+ bootVal &= 0xffff;
+ mppVal |= bootVal;
+ }
+
+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
+ }
+ }
+
+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID))
+ return MV_OK;
+
+ /* Mpp phase 3 */
+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2);
+ /* Read MPP group from board level and assign to MPP register */
+ i = 0;
+ for (mppGroup = 4; mppGroup < 7; mppGroup++)
+ {
+ if ((mppGroupType == MV_BOARD_OTHER) ||
+ (boardId == RD_88F6281A_ID) ||
+ (boardId == RD_88F6281A_PCAC_ID) ||
+ (boardId == SHEEVA_PLUG_ID))
+ mppVal = mvBoardMppGet(mppGroup);
+ else
+ {
+ mppVal = mppGroup2[mppGroupType][i];
+ i++;
+ }
+
+ /* Group 4 is shared mpp[35:32] */
+ if (mppGroup == 4)
+ {
+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup));
+ mppVal &= ~0xffff;
+ bootVal &= 0xffff;
+ mppVal |= bootVal;
+ }
+
+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
+ }
+ /* Update SSCG configuration register*/
+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID ||
+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID)
+ MV_REG_WRITE(0x100d8, 0x53);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCtrlMppRegGet - return reg address of mpp group
+*
+* DESCRIPTION:
+*
+* INPUT:
+* mppGroup - MPP group.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_U32 - Register address.
+*
+*******************************************************************************/
+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup)
+{
+ MV_U32 ret;
+
+ switch(mppGroup){
+ case (0): ret = MPP_CONTROL_REG0;
+ break;
+ case (1): ret = MPP_CONTROL_REG1;
+ break;
+ case (2): ret = MPP_CONTROL_REG2;
+ break;
+ case (3): ret = MPP_CONTROL_REG3;
+ break;
+ case (4): ret = MPP_CONTROL_REG4;
+ break;
+ case (5): ret = MPP_CONTROL_REG5;
+ break;
+ case (6): ret = MPP_CONTROL_REG6;
+ break;
+ default: ret = MPP_CONTROL_REG0;
+ break;
+ }
+ return ret;
+}
+#if defined(MV_INCLUDE_PEX)
+/*******************************************************************************
+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces.
+*
+* DESCRIPTION:
+* This function returns Marvell controller number of PEX interfaces.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Marvell controller number of PEX interfaces. If controller
+* ID is undefined the function returns '0'.
+*
+*******************************************************************************/
+MV_U32 mvCtrlPexMaxIfGet(MV_VOID)
+{
+
+ return MV_PEX_MAX_IF;
+}
+#endif
+
+#if defined(MV_INCLUDE_GIG_ETH)
+/*******************************************************************************
+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports.
+*
+* DESCRIPTION:
+* This function returns Marvell controller number of etherent port.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Marvell controller number of etherent port.
+*
+*******************************************************************************/
+MV_U32 mvCtrlEthMaxPortGet(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ return MV_6281_ETH_MAX_PORTS;
+ break;
+ case MV_6192_DEV_ID:
+ return MV_6192_ETH_MAX_PORTS;
+ break;
+ case MV_6190_DEV_ID:
+ return MV_6190_ETH_MAX_PORTS;
+ break;
+ case MV_6180_DEV_ID:
+ return MV_6180_ETH_MAX_PORTS;
+ break;
+ }
+ return 0;
+
+}
+#endif
+
+#if defined(MV_INCLUDE_XOR)
+/*******************************************************************************
+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels.
+*
+* DESCRIPTION:
+* This function returns Marvell controller number of XOR channels.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Marvell controller number of XOR channels.
+*
+*******************************************************************************/
+MV_U32 mvCtrlXorMaxChanGet(MV_VOID)
+{
+ return MV_XOR_MAX_CHAN;
+}
+#endif
+
+#if defined(MV_INCLUDE_USB)
+/*******************************************************************************
+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* returns number of Marvell USB controllers.
+*
+*******************************************************************************/
+MV_U32 mvCtrlUsbMaxGet(void)
+{
+ return MV_USB_MAX_PORTS;
+}
+#endif
+
+
+#if defined(MV_INCLUDE_NAND)
+/*******************************************************************************
+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if NAND is supported and MV_FALSE otherwise
+*
+*******************************************************************************/
+MV_U32 mvCtrlNandSupport(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ return MV_6281_NAND;
+ break;
+ case MV_6192_DEV_ID:
+ return MV_6192_NAND;
+ break;
+ case MV_6190_DEV_ID:
+ return MV_6190_NAND;
+ break;
+ case MV_6180_DEV_ID:
+ return MV_6180_NAND;
+ break;
+ }
+ return 0;
+
+}
+#endif
+
+#if defined(MV_INCLUDE_SDIO)
+/*******************************************************************************
+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if SDIO is supported and MV_FALSE otherwise
+*
+*******************************************************************************/
+MV_U32 mvCtrlSdioSupport(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ return MV_6281_SDIO;
+ break;
+ case MV_6192_DEV_ID:
+ return MV_6192_SDIO;
+ break;
+ case MV_6190_DEV_ID:
+ return MV_6190_SDIO;
+ break;
+ case MV_6180_DEV_ID:
+ return MV_6180_SDIO;
+ break;
+ }
+ return 0;
+
+}
+#endif
+
+#if defined(MV_INCLUDE_TS)
+/*******************************************************************************
+* mvCtrlTsSupport - Return if this controller has integrated TS flash support
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if TS is supported and MV_FALSE otherwise
+*
+*******************************************************************************/
+MV_U32 mvCtrlTsSupport(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ return MV_6281_TS;
+ break;
+ case MV_6192_DEV_ID:
+ return MV_6192_TS;
+ break;
+ case MV_6190_DEV_ID:
+ return MV_6190_TS;
+ break;
+ case MV_6180_DEV_ID:
+ return MV_6180_TS;
+ break;
+ }
+ return 0;
+}
+#endif
+
+#if defined(MV_INCLUDE_AUDIO)
+/*******************************************************************************
+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise
+*
+*******************************************************************************/
+MV_U32 mvCtrlAudioSupport(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ return MV_6281_AUDIO;
+ break;
+ case MV_6192_DEV_ID:
+ return MV_6192_AUDIO;
+ break;
+ case MV_6190_DEV_ID:
+ return MV_6190_AUDIO;
+ break;
+ case MV_6180_DEV_ID:
+ return MV_6180_AUDIO;
+ break;
+ }
+ return 0;
+
+}
+#endif
+
+#if defined(MV_INCLUDE_TDM)
+/*******************************************************************************
+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if TDM is supported and MV_FALSE otherwise
+*
+*******************************************************************************/
+MV_U32 mvCtrlTdmSupport(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = mvCtrlModelGet();
+
+ switch(devId){
+ case MV_6281_DEV_ID:
+ return MV_6281_TDM;
+ break;
+ case MV_6192_DEV_ID:
+ return MV_6192_TDM;
+ break;
+ case MV_6190_DEV_ID:
+ return MV_6190_TDM;
+ break;
+ case MV_6180_DEV_ID:
+ return MV_6180_TDM;
+ break;
+ }
+ return 0;
+
+}
+#endif
+
+/*******************************************************************************
+* mvCtrlModelGet - Get Marvell controller device model (Id)
+*
+* DESCRIPTION:
+* This function returns 16bit describing the device model (ID) as defined
+* in PCI Device and Vendor ID configuration register offset 0x0.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 16bit desscribing Marvell controller ID
+*
+*******************************************************************************/
+MV_U16 mvCtrlModelGet(MV_VOID)
+{
+ MV_U32 devId;
+
+ devId = MV_REG_READ(CHIP_BOND_REG);
+ devId &= PCKG_OPT_MASK;
+
+ switch(devId){
+ case 2:
+ return MV_6281_DEV_ID;
+ break;
+ case 1:
+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16)
+ == MV_6190_DEV_ID)
+ return MV_6190_DEV_ID;
+ else
+ return MV_6192_DEV_ID;
+ break;
+ case 0:
+ return MV_6180_DEV_ID;
+ break;
+ }
+
+ return 0;
+}
+/*******************************************************************************
+* mvCtrlRevGet - Get Marvell controller device revision number
+*
+* DESCRIPTION:
+* This function returns 8bit describing the device revision as defined
+* in PCI Express Class Code and Revision ID Register.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 8bit desscribing Marvell controller revision number
+*
+*******************************************************************************/
+MV_U8 mvCtrlRevGet(MV_VOID)
+{
+ MV_U8 revNum;
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Check pex power state */
+ MV_U32 pexPower;
+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0);
+ if (pexPower == MV_FALSE)
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE);
+#endif
+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID));
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+ /* Return to power off state */
+ if (pexPower == MV_FALSE)
+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE);
+#endif
+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS);
+}
+
+/*******************************************************************************
+* mvCtrlNameGet - Get Marvell controller name
+*
+* DESCRIPTION:
+* This function returns a string describing the device model and revision.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars.
+*
+* RETURN:
+*
+* MV_ERROR if informantion can not be read.
+*******************************************************************************/
+MV_STATUS mvCtrlNameGet(char *pNameBuff)
+{
+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX,
+ mvCtrlModelGet(), mvCtrlRevGet());
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision
+*
+* DESCRIPTION:
+* This function returns 32bit value describing both Device ID and Revision
+* as defined in PCI Express Device and Vendor ID Register and device revision
+* as defined in PCI Express Class Code and Revision ID Register.
+
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit describing both controller device ID and revision number
+*
+*******************************************************************************/
+MV_U32 mvCtrlModelRevGet(MV_VOID)
+{
+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet());
+}
+
+/*******************************************************************************
+* mvCtrlModelRevNameGet - Get Marvell controller name
+*
+* DESCRIPTION:
+* This function returns a string describing the device model and revision.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars.
+*
+* RETURN:
+*
+* MV_ERROR if informantion can not be read.
+*******************************************************************************/
+
+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff)
+{
+
+ switch (mvCtrlModelRevGet())
+ {
+ case MV_6281_A0_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME);
+ break;
+ case MV_6192_A0_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME);
+ break;
+ case MV_6180_A0_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME);
+ break;
+ case MV_6190_A0_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME);
+ break;
+ case MV_6281_A1_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME);
+ break;
+ case MV_6192_A1_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME);
+ break;
+ case MV_6180_A1_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME);
+ break;
+ case MV_6190_A1_ID:
+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME);
+ break;
+ default:
+ mvCtrlNameGet(pNameBuff);
+ break;
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* ctrlWinOverlapTest - Test address windows for overlaping.
+*
+* DESCRIPTION:
+* This function checks the given two address windows for overlaping.
+*
+* INPUT:
+* pAddrWin1 - Address window 1.
+* pAddrWin2 - Address window 2.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+* MV_TRUE if address window overlaps, MV_FALSE otherwise.
+*******************************************************************************/
+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2)
+{
+ MV_U32 winBase1, winBase2;
+ MV_U32 winTop1, winTop2;
+
+ /* check if we have overflow than 4G*/
+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)||
+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1))
+ {
+ return MV_TRUE;
+ }
+
+ winBase1 = pAddrWin1->baseLow;
+ winBase2 = pAddrWin2->baseLow;
+ winTop1 = winBase1 + pAddrWin1->size-1;
+ winTop2 = winBase2 + pAddrWin2->size-1;
+
+
+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) ||
+ ((winBase1 <= winBase2) && (winBase2 <= winTop1)))
+ {
+ return MV_TRUE;
+ }
+ else
+ {
+ return MV_FALSE;
+ }
+}
+
+/*******************************************************************************
+* ctrlWinWithinWinTest - Test address windows for overlaping.
+*
+* DESCRIPTION:
+* This function checks the given win1 boundries is within
+* win2 boundries.
+*
+* INPUT:
+* pAddrWin1 - Address window 1.
+* pAddrWin2 - Address window 2.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise.
+*******************************************************************************/
+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2)
+{
+ MV_U32 winBase1, winBase2;
+ MV_U32 winTop1, winTop2;
+
+ winBase1 = pAddrWin1->baseLow;
+ winBase2 = pAddrWin2->baseLow;
+ winTop1 = winBase1 + pAddrWin1->size -1;
+ winTop2 = winBase2 + pAddrWin2->size -1;
+
+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) ||
+ ((winTop1 >= winBase2) && (winTop1 <= winTop2)))
+ {
+ return MV_TRUE;
+ }
+ else
+ {
+ return MV_FALSE;
+ }
+}
+
+static const char* cntrlName[] = TARGETS_NAME_ARRAY;
+
+/*******************************************************************************
+* mvCtrlTargetNameGet - Get Marvell controller target name
+*
+* DESCRIPTION:
+* This function convert the trget enumeration to string.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Target name (const MV_8 *)
+*******************************************************************************/
+const MV_8* mvCtrlTargetNameGet( MV_TARGET target )
+{
+
+ if (target >= MAX_TARGETS)
+ {
+ return "target unknown";
+ }
+
+ return cntrlName[target];
+}
+
+/*******************************************************************************
+* mvCtrlAddrDecShow - Print the Controller units address decode map.
+*
+* DESCRIPTION:
+* This function the Controller units address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvCtrlAddrDecShow(MV_VOID)
+{
+ mvCpuIfAddDecShow();
+ mvAhbToMbusAddDecShow();
+#if defined(MV_INCLUDE_PEX)
+ mvPexAddrDecShow();
+#endif
+#if defined(MV_INCLUDE_USB)
+ mvUsbAddrDecShow();
+#endif
+#if defined(MV_INCLUDE_GIG_ETH)
+ mvEthAddrDecShow();
+#endif
+#if defined(MV_INCLUDE_XOR)
+ mvXorAddrDecShow();
+#endif
+#if defined(MV_INCLUDE_SATA)
+ mvSataAddrDecShow();
+#endif
+#if defined(MV_INCLUDE_AUDIO)
+ mvAudioAddrDecShow();
+#endif
+#if defined(MV_INCLUDE_TS)
+ mvTsuAddrDecShow();
+#endif
+}
+
+/*******************************************************************************
+* ctrlSizeToReg - Extract size value for register assignment.
+*
+* DESCRIPTION:
+* Address decode size parameter must be programed from LSB to MSB as
+* sequence of 1's followed by sequence of 0's. The number of 1's
+* specifies the size of the window in 64 KB granularity (e.g. a
+* value of 0x00ff specifies 256x64k = 16 MB).
+* This function extract the size value from the size parameter according
+* to given aligment paramter. For example for size 0x1000000 (16MB) and
+* aligment 0x10000 (64KB) the function will return 0x00FF.
+*
+* INPUT:
+* size - Size.
+* alignment - Size alignment. Note that alignment must be power of 2!
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit describing size register value correspond to size parameter.
+* If value is '-1' size parameter or aligment are invalid.
+*******************************************************************************/
+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment)
+{
+ MV_U32 retVal;
+
+ /* Check size parameter alignment */
+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment)))
+ {
+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n"));
+ return -1;
+ }
+
+ /* Take out the "alignment" portion out of the size parameter */
+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */
+ /* and size is 0x1000000 (16MB) for example */
+ while(alignment & 1) /* Check that alignmet LSB is set */
+ {
+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */
+ alignment = (alignment >> 1);
+ }
+
+ /* If after the alignment first '0' was met we still have '1' in */
+ /* it then aligment is invalid (not power of 2) */
+ if (alignment)
+ {
+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n",
+ (MV_U32)alignment));
+ return -1;
+ }
+
+ /* Now the size is shifted right according to aligment: 0x0100 */
+ size--; /* Now the size is a sequance of '1': 0x00ff */
+
+ retVal = size ;
+
+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */
+ while(size & 1) /* Check that LSB is set */
+ {
+ size = (size >> 1); /* If LSB is set, move one bit to the right */
+ }
+
+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */
+ {
+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n",
+ size));
+ return -1;
+ }
+
+ return retVal;
+
+}
+
+/*******************************************************************************
+* ctrlRegToSize - Extract size value from register value.
+*
+* DESCRIPTION:
+* This function extract a size value from the register size parameter
+* according to given aligment paramter. For example for register size
+* value 0xff and aligment 0x10000 the function will return 0x01000000.
+*
+* INPUT:
+* regSize - Size as in register format. See ctrlSizeToReg.
+* alignment - Size alignment. Note that alignment must be power of 2!
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit describing size.
+* If value is '-1' size parameter or aligment are invalid.
+*******************************************************************************/
+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment)
+{
+ MV_U32 temp;
+
+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */
+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */
+
+ while(temp & 1) /* Check that LSB is set */
+ {
+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */
+ }
+
+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */
+ {
+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n",
+ regSize));
+ return -1;
+ }
+
+
+ /* Check that aligment is a power of two */
+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */
+
+ while(temp & 1) /* Check that alignmet LSB is set */
+ {
+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */
+ }
+
+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */
+ /* then 'temp' is invalid (not power of 2) */
+ if (temp)
+ {
+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n",
+ alignment));
+ return -1;
+ }
+
+ regSize++; /* Now the size is 0x0100 */
+
+ /* Add in the "alignment" portion to the register size parameter */
+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */
+
+ while(alignment & 1) /* Check that alignmet LSB is set */
+ {
+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */
+ alignment = (alignment >> 1);
+ }
+
+ return regSize;
+}
+
+
+/*******************************************************************************
+* ctrlSizeRegRoundUp - Round up given size
+*
+* DESCRIPTION:
+* This function round up a given size to a size that fits the
+* restrictions of size format given an aligment parameter.
+* to given aligment paramter. For example for size parameter 0xa1000 and
+* aligment 0x1000 the function will return 0xFF000.
+*
+* INPUT:
+* size - Size.
+* alignment - Size alignment. Note that alignment must be power of 2!
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit describing size value correspond to size in register.
+*******************************************************************************/
+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment)
+{
+ MV_U32 msbBit = 0;
+ MV_U32 retSize;
+
+ /* Check if size parameter is already comply with restriction */
+ if (!(-1 == ctrlSizeToReg(size, alignment)))
+ {
+ return size;
+ }
+
+ while(size)
+ {
+ size = (size >> 1);
+ msbBit++;
+ }
+
+ retSize = (1 << msbBit);
+
+ if (retSize < alignment)
+ {
+ return alignment;
+ }
+ else
+ {
+ return retSize;
+ }
+}
+/*******************************************************************************
+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button
+* was pressed and clear counter
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN: number of milliseconds the reset button was pressed
+*******************************************************************************/
+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID)
+{
+ static volatile MV_U32 Count = 0;
+
+ if(!Count) {
+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK);
+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000));
+ /* clear counter for next boot */
+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK);
+ }
+
+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count));
+
+ return Count;
+}
+
+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID)
+{
+ MV_U32 satr = 0;
+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ {
+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180)
+ return MV_TRUE;
+ else
+ return MV_FALSE;
+ }
+ satr = satr & MSAR_BOOT_MODE_MASK;
+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM)
+ return MV_TRUE;
+ else
+ return MV_FALSE;
+}
+
+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID)
+{
+ MV_U32 satr = 0;
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ return MV_FALSE;
+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ satr = satr & MSAR_BOOT_MODE_MASK;
+
+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM)
+ return MV_TRUE;
+ else
+ return MV_FALSE;
+}
+
+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID)
+{
+ MV_U32 satr = 0;
+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET);
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ {
+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180)
+ return MV_TRUE;
+ else
+ return MV_FALSE;
+ }
+ satr = satr & MSAR_BOOT_MODE_MASK;
+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM))
+ return MV_TRUE;
+ else
+ return MV_FALSE;
+}
+
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+/*******************************************************************************
+* mvCtrlPwrSaveOn - Set Power save mode
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*******************************************************************************/
+MV_VOID mvCtrlPwrSaveOn(MV_VOID)
+{
+ unsigned long old,temp;
+ /* Disable int */
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+
+ /* Set SoC in power save */
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11);
+ /* Wait for int */
+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4");
+
+ /* Enabled int */
+ __asm__ __volatile__("msr cpsr_c, %0"
+ :
+ : "r" (old)
+ : "memory");
+}
+
+
+
+/*******************************************************************************
+* mvCtrlPwrSaveOff - Go out of power save mode
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*******************************************************************************/
+MV_VOID mvCtrlPwrSaveOff(MV_VOID)
+{
+ unsigned long old,temp;
+ /* Disable int */
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+
+ /* Set SoC in power save */
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11);
+ /* Wait for int */
+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4");
+
+ /* Enabled int */
+ __asm__ __volatile__("msr cpsr_c, %0"
+ :
+ : "r" (old)
+ : "memory");
+}
+
+/*******************************************************************************
+* mvCtrlPwrClckSet - Set Power State for specific Unit
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*******************************************************************************/
+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable)
+{
+ switch (unitId)
+ {
+#if defined(MV_INCLUDE_PEX)
+ case PEX_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_GIG_ETH)
+ case ETH_GIG_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index));
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_INTEG_SATA)
+ case SATA_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index));
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index));
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+ case CESA_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_USB)
+ case USB_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_AUDIO)
+ case AUDIO_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_TS)
+ case TS_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_SDIO)
+ case SDIO_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_TDM)
+ case TDM_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK);
+ }
+ break;
+#endif
+
+ default:
+
+ break;
+
+ }
+}
+
+/*******************************************************************************
+* mvCtrlPwrClckGet - Get Power State of specific Unit
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+******************************************************************************/
+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index)
+{
+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG);
+ MV_BOOL state = MV_TRUE;
+
+ switch (unitId)
+ {
+#if defined(MV_INCLUDE_PEX)
+ case PEX_UNIT_ID:
+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+
+ break;
+#endif
+#if defined(MV_INCLUDE_GIG_ETH)
+ case ETH_GIG_UNIT_ID:
+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index))
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_SATA)
+ case SATA_UNIT_ID:
+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index))
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+ case CESA_UNIT_ID:
+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_USB)
+ case USB_UNIT_ID:
+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_AUDIO)
+ case AUDIO_UNIT_ID:
+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_TS)
+ case TS_UNIT_ID:
+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_SDIO)
+ case SDIO_UNIT_ID:
+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_TDM)
+ case TDM_UNIT_ID:
+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+
+ default:
+ state = MV_TRUE;
+ break;
+ }
+
+
+ return state;
+}
+/*******************************************************************************
+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*******************************************************************************/
+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable)
+{
+ switch (unitId)
+ {
+#if defined(MV_INCLUDE_PEX)
+ case PEX_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_GIG_ETH)
+ case ETH_GIG_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index));
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index));
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_INTEG_SATA)
+ case SATA_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index));
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index));
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+ case CESA_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_USB)
+ case USB_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_AUDIO)
+ case AUDIO_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK);
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK);
+ }
+ break;
+#endif
+#if defined(MV_INCLUDE_XOR)
+ case XOR_UNIT_ID:
+ if (enable == MV_FALSE)
+ {
+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index));
+ }
+ else
+ {
+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index));
+ }
+ break;
+#endif
+ default:
+
+ break;
+
+ }
+}
+
+/*******************************************************************************
+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+******************************************************************************/
+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index)
+{
+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG);
+ MV_BOOL state = MV_TRUE;
+
+ switch (unitId)
+ {
+#if defined(MV_INCLUDE_PEX)
+ case PEX_UNIT_ID:
+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+
+ break;
+#endif
+#if defined(MV_INCLUDE_GIG_ETH)
+ case ETH_GIG_UNIT_ID:
+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index))
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_SATA)
+ case SATA_UNIT_ID:
+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index))
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_CESA)
+ case CESA_UNIT_ID:
+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_USB)
+ case USB_UNIT_ID:
+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_AUDIO)
+ case AUDIO_UNIT_ID:
+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP)
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+#if defined(MV_INCLUDE_XOR)
+ case XOR_UNIT_ID:
+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index))
+ {
+ state = MV_FALSE;
+ }
+ else state = MV_TRUE;
+ break;
+#endif
+
+ default:
+ state = MV_TRUE;
+ break;
+ }
+
+
+ return state;
+}
+#else
+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;}
+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;}
+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */
+
+
+/*******************************************************************************
+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+******************************************************************************/
+MV_VOID mvMPPConfigToSPI(MV_VOID)
+{
+ MV_U32 mppVal = 0;
+ MV_U32 bootVal = 0;
+
+ if(!mvCtrlIsBootFromSPIUseNAND())
+ return;
+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */
+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0));
+ bootVal &= 0xffff000f;
+ mppVal |= bootVal;
+
+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal);
+}
+
+
+/*******************************************************************************
+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+******************************************************************************/
+MV_VOID mvMPPConfigToDefault(MV_VOID)
+{
+ MV_U32 mppVal = 0;
+ MV_U32 bootVal = 0;
+
+ if(!mvCtrlIsBootFromSPIUseNAND())
+ return;
+ mppVal = mvBoardMppGet(0);
+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0));
+ mppVal &= ~0xffff000f;
+ bootVal &= 0xffff000f;
+ mppVal |= bootVal;
+
+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal);
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h
new file mode 100644
index 000000000..6e2e8137a
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h
@@ -0,0 +1,185 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvCtrlEnvLibh
+#define __INCmvCtrlEnvLibh
+
+/* includes */
+#include "mvSysHwConfig.h"
+#include "mvCommon.h"
+#include "mvTypes.h"
+#include "mvOs.h"
+#include "boardEnv/mvBoardEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "ctrlEnv/mvCtrlEnvRegs.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+
+/* typedefs */
+
+/* This enumerator describes the possible HW cache coherency policies the */
+/* controllers supports. */
+typedef enum _mvCachePolicy
+{
+ NO_COHERENCY, /* No HW cache coherency support */
+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */
+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */
+}MV_CACHE_POLICY;
+
+
+/* The swapping is referred to a 64-bit words (as this is the controller */
+/* internal data path width). This enumerator describes the possible */
+/* data swap types. Below is an example of the data 0x0011223344556677 */
+typedef enum _mvSwapType
+{
+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */
+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */
+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */
+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */
+ SWAP_TYPE_MAX /* Delimiter for this enumerator */
+}MV_SWAP_TYPE;
+
+/* This structure describes access rights for Access protection windows */
+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */
+/* Note that the permission enumerator coresponds to its register format. */
+/* For example, Read only premission is presented as "1" in register field. */
+typedef enum _mvAccessRights
+{
+ NO_ACCESS_ALLOWED = 0, /* No access allowed */
+ READ_ONLY = 1, /* Read only permission */
+ ACC_RESERVED = 2, /* Reserved access right */
+ FULL_ACCESS = 3, /* Read and Write permission */
+ MAX_ACC_RIGHTS
+}MV_ACCESS_RIGHTS;
+
+
+/* mcspLib.h API list */
+
+MV_STATUS mvCtrlEnvInit(MV_VOID);
+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup);
+
+#if defined(MV_INCLUDE_PEX)
+MV_U32 mvCtrlPexMaxIfGet(MV_VOID);
+#else
+#define mvCtrlPexMaxIfGet() (0)
+#endif
+
+#define mvCtrlPciIfMaxIfGet() (0)
+
+#if defined(MV_INCLUDE_GIG_ETH)
+MV_U32 mvCtrlEthMaxPortGet(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_XOR)
+MV_U32 mvCtrlXorMaxChanGet(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_USB)
+MV_U32 mvCtrlUsbMaxGet(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_NAND)
+MV_U32 mvCtrlNandSupport(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_SDIO)
+MV_U32 mvCtrlSdioSupport(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_TS)
+MV_U32 mvCtrlTsSupport(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_AUDIO)
+MV_U32 mvCtrlAudioSupport(MV_VOID);
+#endif
+#if defined(MV_INCLUDE_TDM)
+MV_U32 mvCtrlTdmSupport(MV_VOID);
+#endif
+
+MV_U16 mvCtrlModelGet(MV_VOID);
+MV_U8 mvCtrlRevGet(MV_VOID);
+MV_STATUS mvCtrlNameGet(char *pNameBuff);
+MV_U32 mvCtrlModelRevGet(MV_VOID);
+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff);
+MV_VOID mvCtrlAddrDecShow(MV_VOID);
+const MV_8* mvCtrlTargetNameGet(MV_TARGET target);
+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment);
+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment);
+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment);
+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID);
+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
+
+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index);
+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID);
+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID);
+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID);
+#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
+MV_VOID mvCtrlPwrSaveOn(MV_VOID);
+MV_VOID mvCtrlPwrSaveOff(MV_VOID);
+#endif
+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index);
+MV_VOID mvMPPConfigToSPI(MV_VOID);
+MV_VOID mvMPPConfigToDefault(MV_VOID);
+
+
+#endif /* __INCmvCtrlEnvLibh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h
new file mode 100644
index 000000000..ae3f141a0
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -0,0 +1,419 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvCtrlEnvRegsh
+#define __INCmvCtrlEnvRegsh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* CV Support */
+#define PEX0_MEM0 PEX0_MEM
+#define PCI0_MEM0 PEX0_MEM
+
+/* Controller revision info */
+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define PCCRIR_REVID_OFFS 0 /* Revision ID */
+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
+
+/* Controler environment registers offsets */
+
+/* Power Managment Control */
+#define POWER_MNG_MEM_CTRL_REG 0x20118
+
+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0)
+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port))
+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port))
+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port))
+
+#define PMC_PEXSTOPMEM_OFFS 1
+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS)
+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS)
+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS)
+
+#define PMC_USBSTOPMEM_OFFS 2
+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS)
+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS)
+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS)
+
+#define PMC_DUNITSTOPMEM_OFFS 3
+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS)
+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS)
+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS)
+
+#define PMC_RUNITSTOPMEM_OFFS 4
+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS)
+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS)
+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS)
+
+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2))
+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port))
+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port))
+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port))
+
+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5))
+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port))
+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port))
+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port))
+
+#define PMC_SESTOPMEM_OFFS 8
+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS)
+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS)
+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS)
+
+#define PMC_AUDIOSTOPMEM_OFFS 9
+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS)
+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS)
+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS)
+
+#define POWER_MNG_CTRL_REG 0x2011C
+
+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0)
+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port))
+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port))
+
+#define PMC_PEXPHYSTOPCLOCK_OFFS 1
+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS)
+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS)
+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS)
+
+#define PMC_PEXSTOPCLOCK_OFFS 2
+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS)
+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS)
+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS)
+
+#define PMC_USBSTOPCLOCK_OFFS 3
+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS)
+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS)
+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS)
+
+#define PMC_SDIOSTOPCLOCK_OFFS 4
+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS)
+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS)
+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS)
+
+#define PMC_TSSTOPCLOCK_OFFS 5
+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS)
+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS)
+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS)
+
+#define PMC_AUDIOSTOPCLOCK_OFFS 9
+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS)
+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS)
+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS)
+
+#define PMC_POWERSAVE_OFFS 11
+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS)
+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS)
+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS)
+
+
+
+
+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port))
+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port))
+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port))
+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port))
+
+#define PMC_SESTOPCLOCK_OFFS 17
+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS)
+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS)
+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS)
+
+#define PMC_TDMSTOPCLOCK_OFFS 20
+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS)
+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS)
+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS)
+
+
+/* Controler environment registers offsets */
+#define MPP_CONTROL_REG0 0x10000
+#define MPP_CONTROL_REG1 0x10004
+#define MPP_CONTROL_REG2 0x10008
+#define MPP_CONTROL_REG3 0x1000C
+#define MPP_CONTROL_REG4 0x10010
+#define MPP_CONTROL_REG5 0x10014
+#define MPP_CONTROL_REG6 0x10018
+#define MPP_SAMPLE_AT_RESET 0x10030
+#define CHIP_BOND_REG 0x10034
+#define SYSRST_LENGTH_COUNTER_REG 0x10050
+#define SLCR_COUNT_OFFS 0
+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS)
+#define SLCR_CLR_OFFS 31
+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS)
+#define PCKG_OPT_MASK 0x3
+#define MPP_OUTPUT_DRIVE_REG 0x100E0
+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7
+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS)
+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS)
+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15
+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS)
+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS)
+
+#define MSAR_BOOT_MODE_OFFS 12
+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS)
+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS)
+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS)
+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS)
+
+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \
+ ((X & 0x2) << 1))
+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1
+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5
+
+#define MSAR_TCLCK_OFFS 21
+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS)
+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS)
+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS)
+
+
+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \
+ ((X & 0x18) >> 1))
+
+#define MSAR_CPUCLCK_OFFS_6180 2
+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180)
+
+#define MSAR_DDRCLCK_RTIO_OFFS 5
+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS)
+
+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17))
+
+#ifndef MV_ASMLANGUAGE
+/* CPU clock for 6281,6192 0->Resereved */
+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \
+ 600000000, 0, 800000000, 1000000000, \
+ 0, 1200000000, 0, 0, \
+ 1500000000, 0, 0, 0}
+
+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */
+#define MV_DDR_CLCK_RTIO_TBL {\
+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \
+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \
+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \
+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \
+}
+
+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */
+#define MV_L2_CLCK_RTIO_TBL {\
+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \
+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \
+}
+
+/* 6180 have different clk reset sampling */
+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */
+#define MV_CPU6180_DDR_L2_CLCK_TBL { \
+ {0, 0, 0 },\
+ {0, 0, 0 },\
+ {0, 0, 0 },\
+ {0, 0, 0 },\
+ {0, 0, 0 },\
+ {600000000, 200000000, 300000000 },\
+ {800000000, 200000000, 400000000 },\
+ {0, 0, 0 }\
+}
+
+
+
+/* These macros help units to identify a target Mbus Arbiter group */
+#define MV_TARGET_IS_DRAM(target) \
+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3))
+
+#define MV_TARGET_IS_PEX0(target) \
+ ((target >= PEX0_MEM) && (target <= PEX0_IO))
+
+#define MV_TARGET_IS_PEX1(target) 0
+
+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target))
+
+#define MV_TARGET_IS_DEVICE(target) \
+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3))
+
+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0
+
+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \
+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \
+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\
+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)]))
+
+
+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\
+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \
+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \
+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\
+ >> MSAR_BOOT_MODE_OFFS)]:(target))
+
+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */
+
+#define BOOT_TARGETS_NAME_ARRAY { \
+ TBL_TERM, \
+ TBL_TERM, \
+ BOOT_ROM_CS, \
+ TBL_TERM, \
+ BOOT_ROM_CS, \
+ BOOT_ROM_CS, \
+ TBL_TERM, \
+ TBL_TERM \
+}
+
+#define BOOT_TARGETS_NAME_ARRAY_6180 { \
+ TBL_TERM, \
+ BOOT_ROM_CS, \
+ TBL_TERM, \
+ TBL_TERM, \
+ TBL_TERM, \
+ BOOT_ROM_CS, \
+ TBL_TERM, \
+ TBL_TERM \
+}
+
+
+/* For old competability */
+#define DEVICE_CS0 NFLASH_CS
+#define DEVICE_CS1 SPI_CS
+#define DEVICE_CS2 BOOT_ROM_CS
+#define DEVICE_CS3 DEV_BOOCS
+#define MV_BOOTDEVICE_INDEX 0
+
+#define START_DEV_CS DEV_CS0
+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0)
+
+#define PCI_IF0_MEM0 PEX0_MEM
+#define PCI_IF0_IO PEX0_IO
+
+
+/* This enumerator defines the Marvell controller target ID */
+typedef enum _mvTargetId
+{
+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */
+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */
+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */
+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */
+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */
+ MAX_TARGETS_ID
+}MV_TARGET_ID;
+
+
+/* This enumerator described the possible Controller paripheral targets. */
+/* Controller peripherals are designated memory/IO address spaces that the */
+/* controller can access. They are also refered as "targets" */
+typedef enum _mvTarget
+{
+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/
+ SDRAM_CS0, /* SDRAM chip select 0 */
+ SDRAM_CS1, /* SDRAM chip select 1 */
+ SDRAM_CS2, /* SDRAM chip select 2 */
+ SDRAM_CS3, /* SDRAM chip select 3 */
+ PEX0_MEM, /* PCI Express 0 Memory */
+ PEX0_IO, /* PCI Express 0 IO */
+ INTER_REGS, /* Internal registers */
+ NFLASH_CS, /* NFLASH_CS */
+ SPI_CS, /* SPI_CS */
+ BOOT_ROM_CS, /* BOOT_ROM_CS */
+ DEV_BOOCS, /* DEV_BOOCS */
+ CRYPT_ENG, /* Crypto Engine */
+#ifdef MV_INCLUDE_SAGE
+ SAGE_UNIT, /* SAGE Unit */
+#endif
+ MAX_TARGETS
+
+}MV_TARGET;
+
+#define TARGETS_DEF_ARRAY { \
+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \
+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \
+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \
+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \
+ {0xFF, 0xFF }, /* INTER_REGS */ \
+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \
+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \
+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \
+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \
+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \
+ {0x00, SAGE_TARGET_ID } \
+}
+
+
+#define TARGETS_NAME_ARRAY { \
+ "SDRAM_CS0", /* SDRAM_CS0 */ \
+ "SDRAM_CS1", /* SDRAM_CS1 */ \
+ "SDRAM_CS2", /* SDRAM_CS2 */ \
+ "SDRAM_CS3", /* SDRAM_CS3 */ \
+ "PEX0_MEM", /* PEX0_MEM */ \
+ "PEX0_IO", /* PEX0_IO */ \
+ "INTER_REGS", /* INTER_REGS */ \
+ "NFLASH_CS", /* NFLASH_CS */ \
+ "SPI_CS", /* SPI_CS */ \
+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \
+ "DEV_BOOTCS", /* DEV_BOOCS */ \
+ "CRYPT_ENG", /* CRYPT_ENG */ \
+ "SAGE_UNIT" /* SAGE_UNIT */ \
+}
+#endif /* MV_ASMLANGUAGE */
+
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h
new file mode 100644
index 000000000..e41d80a42
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -0,0 +1,257 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvCtrlEnvSpech
+#define __INCmvCtrlEnvSpech
+
+#include "mvDeviceId.h"
+#include "mvSysHwConfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define MV_ARM_SOC
+#define SOC_NAME_PREFIX "MV88F"
+
+
+/* units base and port numbers */
+#ifdef MV_ASMLANGUAGE
+#define XOR_UNIT_BASE(unit) 0x60800
+#else
+#define MV_XOR_REG_BASE 0x60000
+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800)
+#endif
+
+#define TDM_REG_BASE 0xD0000
+#define USB_REG_BASE(dev) 0x50000
+#define AUDIO_REG_BASE 0xA0000
+#define SATA_REG_BASE 0x80000
+#define MV_CESA_REG_BASE 0x3D000
+#define MV_CESA_TDMA_REG_BASE 0x30000
+#define MV_SDIO_REG_BASE 0x90000
+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000)
+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100))
+#define DRAM_BASE 0x0
+#define CNTMR_BASE 0x20300
+#define TWSI_SLAVE_BASE(chanNum) 0x11000
+#define PEX_IF_BASE(pexIf) 0x40000
+#define MPP_REG_BASE 0x10000
+#define TSU_GLOBAL_REG_BASE 0xB4000
+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000
+
+#define INTER_REGS_SIZE _1M
+/* This define describes the TWSI interrupt bit and location */
+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200
+#define TWSI0_CPU_MAIN_INT_BIT (1<<29)
+#define TWSI_SPEED 100000
+
+#define MV_GPP_MAX_GROUP 2
+#define MV_CNTMR_MAX_COUNTER 2
+#define MV_UART_MAX_CHAN 2
+#define MV_XOR_MAX_UNIT 2
+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/
+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
+#define MV_SATA_MAX_CHAN 2
+
+#define MV_6281_MPP_MAX_MODULE 2
+#define MV_6192_MPP_MAX_MODULE 1
+#define MV_6190_MPP_MAX_MODULE 1
+#define MV_6180_MPP_MAX_MODULE 2
+#define MV_6281_MPP_MAX_GROUP 7
+#define MV_6192_MPP_MAX_GROUP 4
+#define MV_6190_MPP_MAX_GROUP 4
+#define MV_6180_MPP_MAX_GROUP 3
+
+#define MV_DRAM_MAX_CS 4
+
+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/
+#define MV_PCI_MAX_IF 0
+#define MV_PCI_START_IF 0
+
+/* This define describes the maximum number of supported PEX Interfaces */
+#define MV_INCLUDE_PEX0
+#define MV_DISABLE_PEX_DEVICE_BAR
+#define MV_PEX_MAX_IF 1
+#define MV_PEX_START_IF MV_PCI_MAX_IF
+
+/* This define describes the maximum number of supported PCI Interfaces */
+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF)
+
+#define MV_ETH_MAX_PORTS 2
+#define MV_6281_ETH_MAX_PORTS 2
+#define MV_6192_ETH_MAX_PORTS 2
+#define MV_6190_ETH_MAX_PORTS 1
+#define MV_6180_ETH_MAX_PORTS 1
+
+#define MV_IDMA_MAX_CHAN 0
+
+#define MV_USB_MAX_PORTS 1
+
+#define MV_USB_VERSION 1
+
+
+#define MV_6281_NAND 1
+#define MV_6192_NAND 1
+#define MV_6190_NAND 1
+#define MV_6180_NAND 0
+
+#define MV_6281_SDIO 1
+#define MV_6192_SDIO 1
+#define MV_6190_SDIO 1
+#define MV_6180_SDIO 1
+
+#define MV_6281_TS 1
+#define MV_6192_TS 1
+#define MV_6190_TS 0
+#define MV_6180_TS 0
+
+#define MV_6281_AUDIO 1
+#define MV_6192_AUDIO 1
+#define MV_6190_AUDIO 0
+#define MV_6180_AUDIO 1
+
+#define MV_6281_TDM 1
+#define MV_6192_TDM 1
+#define MV_6190_TDM 0
+#define MV_6180_TDM 0
+
+#define MV_DEVICE_MAX_CS 4
+
+/* Others */
+#define PEX_HOST_BUS_NUM(pciIf) (pciIf)
+#define PEX_HOST_DEV_NUM(pciIf) 0
+
+#define PCI_IO(pciIf) (PEX0_IO)
+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0)
+/* CESA version #2: One channel, 2KB SRAM, TDMA */
+#if defined(MV_CESA_CHAIN_MODE_SUPPORT)
+ #define MV_CESA_VERSION 3
+#else
+#define MV_CESA_VERSION 2
+#endif
+#define MV_CESA_SRAM_SIZE 2*1024
+/* This define describes the maximum number of supported Ethernet ports */
+#define MV_ETH_VERSION 4
+#define MV_ETH_MAX_RXQ 8
+#define MV_ETH_MAX_TXQ 8
+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE }
+/* This define describes the the support of USB */
+#define MV_USB_VERSION 1
+
+#define MV_INCLUDE_SDRAM_CS0
+#define MV_INCLUDE_SDRAM_CS1
+#define MV_INCLUDE_SDRAM_CS2
+#define MV_INCLUDE_SDRAM_CS3
+
+#define MV_INCLUDE_DEVICE_CS0
+#define MV_INCLUDE_DEVICE_CS1
+#define MV_INCLUDE_DEVICE_CS2
+#define MV_INCLUDE_DEVICE_CS3
+
+#define MPP_GROUP_1_TYPE {\
+ {0, 0, 0}, /* Reserved for AUTO */ \
+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \
+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \
+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \
+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \
+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \
+ {0x33330000, 0x33333333, 0x3333} /* MII */ \
+}
+
+#define MPP_GROUP_2_TYPE {\
+ {0, 0, 0}, /* Reserved for AUTO */ \
+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \
+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \
+ {0, 0, 0}, /* N_A */ \
+ {0, 0, 0}, /* N_A */ \
+ {0x11110000, 0x11111111, 0x01} /* TS */ \
+}
+
+#ifndef MV_ASMLANGUAGE
+
+/* This enumerator defines the Marvell Units ID */
+typedef enum _mvUnitId
+{
+ DRAM_UNIT_ID,
+ PEX_UNIT_ID,
+ ETH_GIG_UNIT_ID,
+ USB_UNIT_ID,
+ IDMA_UNIT_ID,
+ XOR_UNIT_ID,
+ SATA_UNIT_ID,
+ TDM_UNIT_ID,
+ UART_UNIT_ID,
+ CESA_UNIT_ID,
+ SPI_UNIT_ID,
+ AUDIO_UNIT_ID,
+ SDIO_UNIT_ID,
+ TS_UNIT_ID,
+ MAX_UNITS_ID
+
+}MV_UNIT_ID;
+
+#endif
+
+#endif /* __INCmvCtrlEnvSpech */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c
new file mode 100644
index 000000000..d21bb074d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c
@@ -0,0 +1,1048 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#include "ctrlEnv/sys/mvAhbToMbus.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+#undef MV_DEBUG
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+/* typedefs */
+
+
+/* CPU address remap registers offsets are inconsecutive. This struct */
+/* describes address remap register offsets */
+typedef struct _ahbToMbusRemapRegOffs
+{
+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */
+ MV_U32 highRegOffs; /* High 32 bit remap register offset */
+}AHB_TO_MBUS_REMAP_REG_OFFS;
+
+/* locals */
+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum,
+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs);
+
+/*******************************************************************************
+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map !
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK laways.
+*
+*******************************************************************************/
+MV_STATUS mvAhbToMbusInit(void)
+{
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window
+*
+* DESCRIPTION:
+* This function sets
+* address window, also known as address decode window.
+* A new address decode window is set for specified winNum address window.
+* If address decode window parameter structure enables the window,
+* the routine will also enable the winNum window, allowing CPU to access
+* the winNum window.
+*
+* INPUT:
+* winNum - Windows number.
+* pAddrDecWin - CPU winNum window data structure.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of
+* address window overlapps with other active CPU winNum window or
+* trying to assign 36bit base address while CPU does not support that.
+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported.
+*
+*******************************************************************************/
+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+
+ /* Parameter checking */
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+
+ /* read base register*/
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum));
+ }
+ else
+ {
+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG);
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ /* read control register*/
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum));
+ }
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n");
+ return MV_ERROR;
+ }
+
+ /* enable\Disable */
+ if (MV_TRUE == pAddrDecWin->enable)
+ {
+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE;
+ }
+ else
+ {
+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
+
+ /* set attributes */
+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK;
+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS;
+ /* set target ID */
+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK;
+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS;
+
+#if !defined(MV_RUN_FROM_FLASH)
+ /* To be on the safe side we disable the window before writing the */
+ /* new values. */
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ mvAhbToMbusWinEnable(winNum,MV_FALSE);
+ }
+#endif
+
+ /* 3) Write to address decode Base Address Register */
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg);
+ }
+ else
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg);
+ }
+
+
+ /* Internal register space have no size */
+ /* register. Do not perform size register assigment for those targets */
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ /* Write to address decode Size Register */
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window
+*
+* DESCRIPTION:
+* Get the CPU peripheral winNum address window.
+*
+* INPUT:
+* winNum - Peripheral winNum enumerator
+*
+* OUTPUT:
+* pAddrDecWin - CPU winNum window information data structure.
+*
+* RETURN:
+* MV_OK if winNum exist, MV_ERROR otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+
+ /* Parameter checking */
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+
+ /* Internal register space size have no size register*/
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum));
+ }
+ else
+ {
+ decRegs.sizeReg = 0;
+ }
+
+
+ /* Read base and size */
+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum));
+ }
+ else
+ {
+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG);
+ }
+
+
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
+ {
+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n");
+ return MV_ERROR;
+ }
+
+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE;
+ pAddrDecWin->target = INTER_REGS;
+ pAddrDecWin->enable = MV_TRUE;
+
+ return MV_OK;
+ }
+
+
+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+
+ }
+
+
+
+ if (-1 == pAddrDecWin->addrWin.size)
+ {
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >>
+ ATMWCR_WIN_ATTR_OFFS;
+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >>
+ ATMWCR_WIN_TARGET_OFFS;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvAhbToMbusWinTargetGet - Get Window number associated with target
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target)
+{
+ MV_AHB_TO_MBUS_DEC_WIN decWin;
+ MV_U32 winNum;
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target);
+ return 0xffffffff;
+ }
+
+ if (INTER_REGS == target)
+ {
+ return MV_AHB_TO_MBUS_INTREG_WIN;
+ }
+
+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++)
+ {
+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN)
+ continue;
+
+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n");
+ return 0xffffffff;
+
+ }
+
+ if (decWin.enable == MV_TRUE)
+ {
+ if (decWin.target == target)
+ {
+ return winNum;
+ }
+
+ }
+
+ }
+
+ return 0xFFFFFFFF;
+
+
+}
+
+/*******************************************************************************
+* mvAhbToMbusWinAvailGet - Get First Available window number.
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID)
+{
+ MV_AHB_TO_MBUS_DEC_WIN decWin;
+ MV_U32 winNum;
+
+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++)
+ {
+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN)
+ continue;
+
+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n");
+ return 0xffffffff;
+
+ }
+
+ if (decWin.enable == MV_FALSE)
+ {
+ return winNum;
+ }
+
+ }
+
+ return 0xFFFFFFFF;
+}
+
+
+/*******************************************************************************
+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window
+*
+* DESCRIPTION:
+* This function enable/disable a CPU address decode window.
+* if parameter 'enable' == MV_TRUE the routine will enable the
+* window, thus enabling CPU accesses (before enabling the window it is
+* tested for overlapping). Otherwise, the window will be disabled.
+*
+* INPUT:
+* winNum - Peripheral winNum enumerator.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if protection window number was wrong, or the window
+* overlapps other winNum window.
+*
+*******************************************************************************/
+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable)
+{
+
+ /* Parameter checking */
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ /* Internal registers bar can't be disable or enabled */
+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN)
+ {
+ return (enable ? MV_OK : MV_ERROR);
+ }
+
+ if (enable == MV_TRUE)
+ {
+ /* enable the window */
+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE);
+ }
+ else
+ { /* Disable address decode winNum window */
+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE);
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvAhbToMbusWinRemap - Set CPU remap register for address windows.
+*
+* DESCRIPTION:
+* After a CPU address hits one of PCI address decode windows there is an
+* option to remap the address to a different one. For example, CPU
+* executes a read from PCI winNum window address 0x1200.0000. This
+* can be modified so the address on the PCI bus would be 0x1400.0000
+* Using the PCI address remap mechanism.
+*
+* INPUT:
+* winNum - Peripheral winNum enumerator. Must be a PCI winNum.
+* pAddrDecWin - CPU winNum window information data structure.
+* Note that caller has to fill in the base field only. The
+* size field is ignored.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 baseAddr;
+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs;
+
+ MV_U32 effectiveBaseAddress=0,
+ baseAddrValue=0,windowSizeValue=0;
+
+
+ /* Get registers offsets of given winNum */
+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs))
+ {
+ return 0xffffffff;
+ }
+
+ /* 1) Set address remap low */
+ baseAddr = pAddrWin->baseLow;
+
+ /* Check base address aligment */
+ /*
+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT))
+ {
+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n",
+ baseAddr);
+ return MV_ERROR;
+ }
+ */
+
+ /* BaseLow[31:16] => base register [31:16] */
+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK;
+
+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr);
+
+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh);
+
+
+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum));
+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum));
+
+ baseAddrValue &= ATMWBR_BASE_MASK;
+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK;
+
+ /* Start calculating the effective Base Address */
+ effectiveBaseAddress = baseAddrValue ;
+
+ /* The effective base address will be combined from the chopped (if any)
+ remap value (according to the size value and remap mechanism) and the
+ window's base address */
+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow);
+ /* If the effectiveBaseAddress exceed the window boundaries return an
+ invalid value. */
+
+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff)))
+ {
+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n");
+ return 0xffffffff;
+ }
+
+ return effectiveBaseAddress;
+
+
+}
+/*******************************************************************************
+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets
+*
+* DESCRIPTION:
+*
+* INPUT:
+* target1 - CPU Interface target 1
+* target2 - CPU Interface target 2
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if targets are illigal, or if one of the targets is not
+* associated to a valid window .
+* MV_OK otherwise.
+*
+*******************************************************************************/
+
+
+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2)
+{
+ MV_U32 winNum1,winNum2;
+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp;
+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2;
+ MV_U32 remapBaseLow1=0,remapBaseLow2=0;
+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0;
+
+
+ /* Check parameters */
+ if (target1 >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1);
+ return MV_ERROR;
+ }
+
+ if (target2 >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1);
+ return MV_ERROR;
+ }
+
+
+ /* get window associated with this target */
+ winNum1 = mvAhbToMbusWinTargetGet(target1);
+
+ if (winNum1 == 0xffffffff)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n",
+ target1,winNum1);
+ return MV_ERROR;
+
+ }
+
+ /* get window associated with this target */
+ winNum2 = mvAhbToMbusWinTargetGet(target2);
+
+ if (winNum2 == 0xffffffff)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n",
+ target2,winNum2);
+ return MV_ERROR;
+
+ }
+
+ /* now Get original values of both Windows */
+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1))
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n",
+ winNum1);
+ return MV_ERROR;
+
+ }
+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2))
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n",
+ winNum2);
+ return MV_ERROR;
+
+ }
+
+
+ /* disable both windows */
+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE))
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n",
+ winNum1);
+ return MV_ERROR;
+
+ }
+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE))
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n",
+ winNum2);
+ return MV_ERROR;
+
+ }
+
+
+ /* now swap targets */
+
+ /* first save winDec2 values */
+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh;
+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow;
+ winDecTemp.addrWin.size = winDec2.addrWin.size;
+ winDecTemp.enable = winDec2.enable;
+ winDecTemp.target = winDec2.target;
+
+ /* winDec2 = winDec1 */
+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh;
+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow;
+ winDec2.addrWin.size = winDec1.addrWin.size;
+ winDec2.enable = winDec1.enable;
+ winDec2.target = winDec1.target;
+
+
+ /* winDec1 = winDecTemp */
+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh;
+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow;
+ winDec1.addrWin.size = winDecTemp.addrWin.size;
+ winDec1.enable = winDecTemp.enable;
+ winDec1.target = winDecTemp.target;
+
+
+ /* now set the new values */
+
+
+ mvAhbToMbusWinSet(winNum1,&winDec1);
+ mvAhbToMbusWinSet(winNum2,&winDec2);
+
+
+
+
+
+ /* now we will treat the remap windows if exist */
+
+
+ /* now check if one or both windows has a remap window
+ as well after the swap ! */
+
+ /* if a window had a remap value differnt than the base value
+ before the swap , then after the swap the remap value will be
+ equal to the base value unless both windows has a remap windows*/
+
+ /* first get old values */
+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1))
+ {
+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs);
+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs);
+
+ }
+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2))
+ {
+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs);
+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs);
+
+
+ }
+
+ /* now do the swap */
+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1))
+ {
+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2))
+ {
+ /* Two windows has a remap !!! so swap */
+
+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1);
+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1);
+
+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2);
+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2);
+
+
+
+ }
+ else
+ {
+ /* remap == base */
+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh);
+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow);
+
+ }
+
+ }
+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2))
+ {
+ /* remap == base */
+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh);
+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow);
+
+ }
+
+
+
+ return MV_OK;
+
+
+}
+
+
+
+#if defined(MV_88F1181)
+
+/*******************************************************************************
+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration.
+*
+* DESCRIPTION:
+* This function sets CPU Mbus Arbiter
+*
+* INPUT:
+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At
+* each clock cycle, the crossbar arbiter samples all
+* requests and gives the bus to the next agent according
+* to the "pizza".
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if paramers to function invalid.
+*
+*******************************************************************************/
+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray)
+{
+ MV_U32 sliceNum;
+ MV_U32 xbarCtrl = 0;
+ MV_MBUS_ARB_TARGET xbarTarget;
+
+ /* 1) Set crossbar control low register */
+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++)
+ {
+ xbarTarget = pPizzaArbArray[sliceNum];
+
+ /* sliceNum parameter check */
+ if (xbarTarget > MAX_MBUS_ARB_TARGETS)
+ {
+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n",
+ xbarTarget);
+ return MV_ERROR;
+ }
+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum));
+ }
+ /* Write to crossbar control low register */
+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl);
+
+ xbarCtrl = 0;
+
+ /* 2) Set crossbar control high register */
+ for (sliceNum = MRLR_SLICE_NUM;
+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM;
+ sliceNum++)
+ {
+
+ xbarTarget = pPizzaArbArray[sliceNum];
+
+ /* sliceNum parameter check */
+ if (xbarTarget > MAX_MBUS_ARB_TARGETS)
+ {
+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n",
+ xbarTarget);
+ return MV_ERROR;
+ }
+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum));
+ }
+ /* Write to crossbar control high register */
+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvMbusArbCtrlSet - Set MBus Arbiter control register
+*
+* DESCRIPTION:
+*
+* INPUT:
+* ctrl - pointer to MV_MBUS_ARB_CTRL register
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if paramers to function invalid.
+*
+*******************************************************************************/
+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl)
+{
+
+ if (ctrl->highPrio == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP);
+ }
+ else
+ {
+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP);
+ }
+
+ if (ctrl->fixedRoundRobin == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED);
+ }
+ else
+ {
+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED);
+ }
+
+ if (ctrl->starvEn == MV_FALSE)
+ {
+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN);
+ }
+ else
+ {
+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvMbusArbCtrlGet - Get MBus Arbiter control register
+*
+* DESCRIPTION:
+*
+* INPUT:
+* ctrl - pointer to MV_MBUS_ARB_CTRL register
+*
+* OUTPUT:
+* ctrl - pointer to MV_MBUS_ARB_CTRL register
+*
+* RETURN:
+* MV_ERROR if paramers to function invalid.
+*
+*******************************************************************************/
+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl)
+{
+
+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG);
+
+ if (ctrlReg & MACR_ARB_ARM_TOP)
+ {
+ ctrl->highPrio = MV_TRUE;
+ }
+ else
+ {
+ ctrl->highPrio = MV_FALSE;
+ }
+
+ if (ctrlReg & MACR_ARB_TARGET_FIXED)
+ {
+ ctrl->fixedRoundRobin = MV_TRUE;
+ }
+ else
+ {
+ ctrl->fixedRoundRobin = MV_FALSE;
+ }
+
+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN)
+ {
+ ctrl->starvEn = MV_TRUE;
+ }
+ else
+ {
+ ctrl->starvEn = MV_FALSE;
+ }
+
+
+ return MV_OK;
+}
+
+#endif /* #if defined(MV_88F1181) */
+
+
+
+/*******************************************************************************
+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets
+*
+* DESCRIPTION:
+* CPU to PCI address remap registers offsets are inconsecutive.
+* This function returns PCI address remap registers offsets.
+*
+* INPUT:
+* winNum - Address decode window number. See MV_U32 enumerator.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if winNum is not a PCI one.
+*
+*******************************************************************************/
+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum,
+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs)
+{
+ switch (winNum)
+ {
+ case 0:
+ case 1:
+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum);
+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum);
+ break;
+ case 2:
+ case 3:
+ if((mvCtrlModelGet() == MV_5281_DEV_ID) ||
+ (mvCtrlModelGet() == MV_1281_DEV_ID) ||
+ (mvCtrlModelGet() == MV_6183_DEV_ID) ||
+ (mvCtrlModelGet() == MV_6183L_DEV_ID))
+ {
+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum);
+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum);
+ break;
+ }
+ else
+ {
+ pRemapRegs->lowRegOffs = 0;
+ pRemapRegs->highRegOffs = 0;
+
+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n",
+ winNum));
+ return MV_NO_SUCH;
+ }
+ default:
+ {
+ pRemapRegs->lowRegOffs = 0;
+ pRemapRegs->highRegOffs = 0;
+
+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n",
+ winNum));
+ return MV_NO_SUCH;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map.
+*
+* DESCRIPTION:
+* This function print the CPU address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvAhbToMbusAddDecShow(MV_VOID)
+{
+ MV_AHB_TO_MBUS_DEC_WIN win;
+ MV_U32 winNum;
+ mvOsOutput( "\n" );
+ mvOsOutput( "AHB To MBUS Bridge:\n" );
+ mvOsOutput( "-------------------\n" );
+
+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ )
+ {
+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", winNum );
+
+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+ mvOsOutput( "...." );
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h
new file mode 100644
index 000000000..1b352a1f6
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h
@@ -0,0 +1,130 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvAhbToMbush
+#define __INCmvAhbToMbush
+
+/* includes */
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+/* defines */
+
+#if defined(MV_88F1181)
+/* This enumerator defines the Marvell controller possible MBUS arbiter */
+/* target ports. It is used to define crossbar priority scheame (pizza) */
+typedef enum _mvMBusArbTargetId
+{
+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */
+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */
+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */
+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */
+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */
+ MAX_MBUS_ARB_TARGETS
+}MV_MBUS_ARB_TARGET;
+
+typedef struct _mvMBusArbCtrl
+{
+ MV_BOOL starvEn;
+ MV_BOOL highPrio;
+ MV_BOOL fixedRoundRobin;
+
+}MV_MBUS_ARB_CTRL;
+
+#endif /* #if defined(MV_88F1181) */
+
+typedef struct _mvAhbtoMbusDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_AHB_TO_MBUS_DEC_WIN;
+
+/* mvAhbToMbus.h API list */
+
+MV_STATUS mvAhbToMbusInit(MV_VOID);
+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin);
+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin);
+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable);
+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin);
+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target);
+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID);
+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2);
+
+#if defined(MV_88F1181)
+
+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray);
+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl);
+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl);
+
+#endif /* #if defined(MV_88F1181) */
+
+
+MV_VOID mvAhbToMbusAddDecShow(MV_VOID);
+
+
+#endif /* __INCmvAhbToMbush */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h
new file mode 100644
index 000000000..97dc63189
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h
@@ -0,0 +1,143 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvAhbToMbusRegsh
+#define __INCmvAhbToMbusRegsh
+
+/******************************/
+/* ARM Address Map Registers */
+/******************************/
+
+#define MAX_AHB_TO_MBUS_WINS 9
+#define MV_AHB_TO_MBUS_INTREG_WIN 8
+
+
+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10)
+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10)
+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10)
+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10)
+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080
+
+/* Window Control Register */
+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/
+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */
+
+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated
+ with this window*/
+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS)
+
+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes
+ Associated with this window */
+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS)
+
+
+/*
+Used with the Base register to set the address window size and location
+Must be programed from LSB to MSB as sequence of 1’s followed
+by sequence of 0’s. The number of 1’s specifies the size of the window
+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB).
+
+NOTE: A value of 0x0 specifies 64KB size.
+*/
+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */
+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS)
+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000
+
+/* Window Base Register */
+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */
+
+/*
+Used with the size field to set the address window size and location.
+Corresponds to transaction address[31:16]
+*/
+#define ATMWBR_BASE_OFFS 16 /* Base Address */
+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS)
+#define ATMWBR_BASE_ALIGNMENT 0x10000
+
+/* Window Remap Low Register */
+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */
+
+/*
+Used with the size field to specifies address bits[31:0] to be driven to
+the target interface.:
+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0])
+*/
+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */
+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS)
+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000
+
+/* Window Remap High Register */
+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */
+
+/*
+Specifies address bits[63:32] to be driven to the target interface.
+target_addr[63:32] = (RemapHigh[31:0]
+*/
+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */
+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS)
+
+
+#endif /* __INCmvAhbToMbusRegsh */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c
new file mode 100644
index 000000000..872dc6e9d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c
@@ -0,0 +1,1036 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "ctrlEnv/sys/mvAhbToMbusRegs.h"
+#include "cpu/mvCpu.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "mvSysHwConfig.h"
+#include "mvSysDram.h"
+
+/*#define MV_DEBUG*/
+/* defines */
+
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+/* locals */
+/* static functions */
+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin);
+
+MV_TARGET * sampleAtResetTargetArray;
+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY;
+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180;
+/*******************************************************************************
+* mvCpuIfInit - Initialize Controller CPU interface
+*
+* DESCRIPTION:
+* This function initialize Controller CPU interface:
+* 1. Set CPU interface configuration registers.
+* 2. Set CPU master Pizza arbiter control according to static
+* configuration described in configuration file.
+* 3. Opens CPU address decode windows. DRAM windows are assumed to be
+* already set (auto detection).
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap)
+{
+ MV_U32 regVal;
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin;
+
+ if (cpuAddrWinMap == NULL)
+ {
+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n"));
+ return MV_ERROR;
+ }
+
+ /*Initialize the boot target array according to device type*/
+ if(mvCtrlModelGet() == MV_6180_DEV_ID)
+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P;
+ else
+ sampleAtResetTargetArray = sampleAtResetTargetArrayP;
+
+ /* Set ARM Configuration register */
+ regVal = MV_REG_READ(CPU_CONFIG_REG);
+ regVal &= ~CPU_CONFIG_DEFAULT_MASK;
+ regVal |= CPU_CONFIG_DEFAULT;
+ MV_REG_WRITE(CPU_CONFIG_REG,regVal);
+
+ /* First disable all CPU target windows */
+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++)
+ {
+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS))
+ {
+ continue;
+ }
+
+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA)
+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */
+ if (MV_TARGET_IS_PCI(target))
+ {
+ continue;
+ }
+#endif
+
+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA)
+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */
+ if (MV_TARGET_IS_PEX(target))
+ {
+ continue;
+ }
+#endif
+#if defined(MV_RUN_FROM_FLASH)
+ /* Don't disable the boot device. */
+ if (target == DEV_BOOCS)
+ {
+ continue;
+ }
+#endif /* MV_RUN_FROM_FLASH */
+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE);
+ }
+
+#if defined(MV_RUN_FROM_FLASH)
+ /* Resize the bootcs windows before other windows, because this */
+ /* window is enabled and will cause an overlap if not resized. */
+ target = DEV_BOOCS;
+
+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target]))
+ {
+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n"));
+ return MV_ERROR;
+ }
+
+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow;
+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh;
+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin))
+ {
+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n",
+ cpuAddrWinMap[target].winNum));
+ }
+
+#endif /* MV_RUN_FROM_FLASH */
+
+ /* Go through all targets in user table until table terminator */
+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++)
+ {
+
+#if defined(MV_RUN_FROM_FLASH)
+ if (target == DEV_BOOCS)
+ {
+ continue;
+ }
+#endif /* MV_RUN_FROM_FLASH */
+
+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */
+ /* assuming this already has been done earlier. */
+#ifdef MV_DRAM_AUTO_SIZE
+ if (MV_TARGET_IS_DRAM(target))
+ {
+ continue;
+ }
+#endif
+
+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA)
+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */
+ if (MV_TARGET_IS_PCI(target))
+ {
+ continue;
+ }
+#endif
+
+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA)
+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */
+ if (MV_TARGET_IS_PEX(target))
+ {
+ continue;
+ }
+#endif
+ /* If the target attribute is the same as the boot device attribute */
+ /* then it's stays disable */
+ if (MV_TARGET_IS_AS_BOOT(target))
+ {
+ continue;
+ }
+
+ if((0 == cpuAddrWinMap[target].addrWin.size) ||
+ (DIS == cpuAddrWinMap[target].enable))
+
+ {
+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE))
+ {
+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n"));
+ return MV_ERROR;
+ }
+
+ }
+ else
+ {
+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target]))
+ {
+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n"));
+ return MV_ERROR;
+ }
+
+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow;
+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh;
+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin))
+ {
+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n",
+ cpuAddrWinMap[target].winNum));
+ }
+
+
+ }
+ }
+
+ return MV_OK;
+
+
+}
+
+
+/*******************************************************************************
+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0)
+* address window, also known as address decode window.
+* A new address decode window is set for specified target address window.
+* If address decode window parameter structure enables the window,
+* the routine will also enable the target window, allowing CPU to access
+* the target window.
+*
+* INPUT:
+* target - Peripheral target enumerator.
+* pAddrDecWin - CPU target window data structure.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_OK if CPU target window was set correctly, MV_ERROR in case of
+* address window overlapps with other active CPU target window or
+* trying to assign 36bit base address while CPU does not support that.
+* The function returns MV_NOT_SUPPORTED, if the target is unsupported.
+*
+*******************************************************************************/
+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin)
+{
+ MV_AHB_TO_MBUS_DEC_WIN decWin;
+ MV_U32 existingWinNum;
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ target = MV_CHANGE_BOOT_CS(target);
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ /* 2) Check if the requested window overlaps with current windows */
+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target);
+ return MV_BAD_PARAM;
+ }
+
+ if (MV_TARGET_IS_DRAM(target))
+ {
+ /* copy relevant data to MV_DRAM_DEC_WIN structure */
+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh;
+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow;
+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size;
+ addrDecWin.enable = pAddrDecWin->enable;
+
+
+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK);
+ {
+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n");
+ return MV_ERROR;
+ }
+
+ }
+ else
+ {
+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */
+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow;
+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh;
+ decWin.addrWin.size = pAddrDecWin->addrWin.size;
+ decWin.enable = pAddrDecWin->enable;
+ decWin.target = target;
+
+ existingWinNum = mvAhbToMbusWinTargetGet(target);
+
+ /* check if there is already another Window configured
+ for this target */
+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&&
+ (existingWinNum != pAddrDecWin->winNum))
+ {
+ /* if we want to enable the new winow number
+ passed by the user , then the old one should
+ be disabled */
+ if (MV_TRUE == pAddrDecWin->enable)
+ {
+ /* be sure it is disabled */
+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE);
+ }
+ }
+
+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK)
+ {
+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n");
+ return MV_ERROR;
+ }
+
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window
+*
+* DESCRIPTION:
+* Get the CPU peripheral target address window.
+*
+* INPUT:
+* target - Peripheral target enumerator
+*
+* OUTPUT:
+* pAddrDecWin - CPU target window information data structure.
+*
+* RETURN:
+* MV_OK if target exist, MV_ERROR otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin)
+{
+
+ MV_U32 winNum=0xffffffff;
+ MV_AHB_TO_MBUS_DEC_WIN decWin;
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ target = MV_CHANGE_BOOT_CS(target);
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ if (MV_TARGET_IS_DRAM(target))
+ {
+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK)
+ {
+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n",
+ target);
+ return MV_ERROR;
+ }
+
+ /* copy relevant data to MV_CPU_DEC_WIN structure */
+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow;
+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size;
+ pAddrDecWin->enable = addrDecWin.enable;
+ pAddrDecWin->winNum = 0xffffffff;
+
+ }
+ else
+ {
+ /* get the Window number associated with this target */
+
+ winNum = mvAhbToMbusWinTargetGet(target);
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ return MV_NO_SUCH;
+
+ }
+
+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK)
+ {
+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n",
+ __FUNCTION__, winNum);
+ return MV_ERROR;
+
+ }
+
+ /* copy relevant data to MV_CPU_DEC_WIN structure */
+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow;
+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh;
+ pAddrDecWin->addrWin.size = decWin.addrWin.size;
+ pAddrDecWin->enable = decWin.enable;
+ pAddrDecWin->winNum = winNum;
+
+ }
+
+
+
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window
+*
+* DESCRIPTION:
+* This function enable/disable a CPU address decode window.
+* if parameter 'enable' == MV_TRUE the routine will enable the
+* window, thus enabling CPU accesses (before enabling the window it is
+* tested for overlapping). Otherwise, the window will be disabled.
+*
+* INPUT:
+* target - Peripheral target enumerator.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if protection window number was wrong, or the window
+* overlapps other target window.
+*
+*******************************************************************************/
+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable)
+{
+ MV_U32 winNum, temp;
+ MV_CPU_DEC_WIN addrDecWin;
+
+ target = MV_CHANGE_BOOT_CS(target);
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ /* get the window and check if it exist */
+ temp = mvCpuIfTargetWinGet(target, &addrDecWin);
+ if (MV_NO_SUCH == temp)
+ {
+ return (enable? MV_ERROR: MV_OK);
+ }
+ else if( MV_OK != temp)
+ {
+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target);
+ return MV_ERROR;
+ }
+
+
+ /* check overlap */
+
+ if (MV_TRUE == enable)
+ {
+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin))
+ {
+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target));
+ return MV_ERROR;
+ }
+
+ }
+
+
+ if (MV_TARGET_IS_DRAM(target))
+ {
+ if (mvDramIfWinEnable(target , enable) != MV_OK)
+ {
+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n");
+ return MV_ERROR;
+
+ }
+
+ }
+ else
+ {
+ /* get the Window number associated with this target */
+
+ winNum = mvAhbToMbusWinTargetGet(target);
+
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ return (enable? MV_ERROR: MV_OK);
+ }
+
+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK)
+ {
+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n",
+ winNum);
+ return MV_ERROR;
+
+ }
+
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvCpuIfTargetWinSizeGet - Get CPU target address window size
+*
+* DESCRIPTION:
+* Get the size of CPU-to-peripheral target window.
+*
+* INPUT:
+* target - Peripheral target enumerator
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit size. Function also returns '0' if window is closed.
+* Function returns 0xFFFFFFFF in case of an error.
+*
+*******************************************************************************/
+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target)
+{
+ MV_CPU_DEC_WIN addrDecWin;
+
+ target = MV_CHANGE_BOOT_CS(target);
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target);
+ return 0;
+ }
+
+ /* Get the winNum window */
+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin))
+ {
+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n",
+ target);
+ return 0;
+ }
+
+ /* Check if window is enabled */
+ if (addrDecWin.enable == MV_TRUE)
+ {
+ return (addrDecWin.addrWin.size);
+ }
+ else
+ {
+ return 0; /* Window disabled. return 0 */
+ }
+}
+
+/*******************************************************************************
+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low
+*
+* DESCRIPTION:
+* CPU-to-peripheral target address window base is constructed of
+* two parts: Low and high.
+* This function gets the CPU peripheral target low base address.
+*
+* INPUT:
+* target - Peripheral target enumerator
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit low base address.
+*
+*******************************************************************************/
+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target)
+{
+ MV_CPU_DEC_WIN addrDecWin;
+
+ target = MV_CHANGE_BOOT_CS(target);
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target);
+ return 0xffffffff;
+ }
+
+ /* Get the target window */
+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin))
+ {
+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n",
+ target);
+ return 0xffffffff;
+ }
+
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ return 0xffffffff;
+ }
+ return (addrDecWin.addrWin.baseLow);
+}
+
+/*******************************************************************************
+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high
+*
+* DESCRIPTION:
+* CPU-to-peripheral target address window base is constructed of
+* two parts: Low and high.
+* This function gets the CPU peripheral target high base address.
+*
+* INPUT:
+* target - Peripheral target enumerator
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit high base address.
+*
+*******************************************************************************/
+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target)
+{
+ MV_CPU_DEC_WIN addrDecWin;
+
+ target = MV_CHANGE_BOOT_CS(target);
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target);
+ return 0xffffffff;
+ }
+
+ /* Get the target window */
+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin))
+ {
+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n",
+ target);
+ return 0xffffffff;
+ }
+
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ return 0;
+ }
+
+ return (addrDecWin.addrWin.baseHigh);
+}
+
+#if defined(MV_INCLUDE_PEX)
+/*******************************************************************************
+* mvCpuIfPexRemap - Set CPU remap register for address windows.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* pexTarget - Peripheral target enumerator. Must be a PEX target.
+* pAddrDecWin - CPU target window information data structure.
+* Note that caller has to fill in the base field only. The
+* size field is ignored.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if target is not a PEX one, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin)
+{
+ MV_U32 winNum;
+
+ /* Check parameters */
+
+ if (mvCtrlPexMaxIfGet() > 1)
+ {
+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget)))
+ {
+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget);
+ return 0xffffffff;
+ }
+
+ }
+ else
+ {
+ if (!MV_TARGET_IS_PEX0(pexTarget))
+ {
+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget);
+ return 0xffffffff;
+ }
+
+ }
+
+ /* get the Window number associated with this target */
+ winNum = mvAhbToMbusWinTargetGet(pexTarget);
+
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n");
+ return 0xffffffff;
+
+ }
+
+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin);
+}
+
+#endif
+
+#if defined(MV_INCLUDE_PCI)
+/*******************************************************************************
+* mvCpuIfPciRemap - Set CPU remap register for address windows.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* pciTarget - Peripheral target enumerator. Must be a PCI target.
+* pAddrDecWin - CPU target window information data structure.
+* Note that caller has to fill in the base field only. The
+* size field is ignored.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if target is not a PCI one, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin)
+{
+ MV_U32 winNum;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_PCI(pciTarget))
+ {
+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget);
+ return 0xffffffff;
+ }
+
+ /* get the Window number associated with this target */
+ winNum = mvAhbToMbusWinTargetGet(pciTarget);
+
+ if (winNum >= MAX_AHB_TO_MBUS_WINS)
+ {
+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n");
+ return 0xffffffff;
+
+ }
+
+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin);
+}
+#endif /* MV_INCLUDE_PCI */
+
+
+/*******************************************************************************
+* mvCpuIfPciIfRemap - Set CPU remap register for address windows.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* pciTarget - Peripheral target enumerator. Must be a PCI target.
+* pAddrDecWin - CPU target window information data structure.
+* Note that caller has to fill in the base field only. The
+* size field is ignored.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if target is not a PCI one, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin)
+{
+#if defined(MV_INCLUDE_PEX)
+ if (MV_TARGET_IS_PEX(pciIfTarget))
+ {
+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin);
+ }
+#endif
+#if defined(MV_INCLUDE_PCI)
+
+ if (MV_TARGET_IS_PCI(pciIfTarget))
+ {
+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin);
+ }
+#endif
+ return 0;
+}
+
+
+
+/*******************************************************************************
+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address
+*
+* DESCRIPTION:
+*
+* INPUT:
+* baseAddress - base address to be checked
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* the target number that baseAddress belongs to or MAX_TARGETS is not
+* found
+*
+*******************************************************************************/
+
+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress)
+{
+ MV_CPU_DEC_WIN win;
+ MV_U32 target;
+
+ for( target = 0; target < MAX_TARGETS; target++ )
+ {
+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ if ((baseAddress >= win.addrWin.baseLow) &&
+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break;
+ }
+ }
+ else return MAX_TARGETS;
+
+ }
+
+ return target;
+}
+/*******************************************************************************
+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviur is expected in case CPU address decode
+* windows overlapps.
+* This function detects CPU address decode windows overlapping of a
+* specified target. The function does not check the target itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* target - Peripheral target enumerator.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlaps current address
+* decode map, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 targetNum;
+ MV_CPU_DEC_WIN addrDecWin;
+ MV_STATUS status;
+
+
+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++)
+ {
+#if defined(MV_RUN_FROM_FLASH)
+ if(MV_TARGET_IS_AS_BOOT(target))
+ {
+ if (MV_CHANGE_BOOT_CS(targetNum) == target)
+ continue;
+ }
+#endif /* MV_RUN_FROM_FLASH */
+
+ /* don't check our target or illegal targets */
+ if (targetNum == target)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin);
+ if(MV_NO_SUCH == status)
+ {
+ continue;
+ }
+ if(MV_OK != status)
+ {
+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n"));
+ return MV_TRUE;
+ }
+
+ /* Do not check disabled windows */
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ continue;
+ }
+
+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin))
+ {
+ DB(mvOsPrintf(
+ "cpuTargetWinOverlap: Required target %d overlap current %d\n",
+ target, targetNum));
+ return MV_TRUE;
+ }
+ }
+
+ return MV_FALSE;
+
+}
+
+/*******************************************************************************
+* mvCpuIfAddDecShow - Print the CPU address decode map.
+*
+* DESCRIPTION:
+* This function print the CPU address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvCpuIfAddDecShow(MV_VOID)
+{
+ MV_CPU_DEC_WIN win;
+ MV_U32 target;
+ mvOsOutput( "\n" );
+ mvOsOutput( "CPU Interface\n" );
+ mvOsOutput( "-------------\n" );
+
+ for( target = 0; target < MAX_TARGETS; target++ )
+ {
+
+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) );
+
+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target));
+ mvOsOutput( "...." );
+
+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "base %08x, ", win.addrWin.baseLow );
+ mvSizePrint( win.addrWin.size );
+ mvOsOutput( "\n" );
+
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH )
+ {
+ mvOsOutput( "no such\n" );
+ }
+ }
+}
+
+/*******************************************************************************
+* mvCpuIfEnablePex - Enable PCI Express.
+*
+* DESCRIPTION:
+* This function Enable PCI Express.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* pexType - MV_PEX_ROOT_COMPLEX - root complex device
+* MV_PEX_END_POINT - end point device
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+#if defined(MV_INCLUDE_PEX)
+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType)
+{
+ /* Set pex mode incase S@R not exist */
+ if( pexType == MV_PEX_END_POINT)
+ {
+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK);
+ /* Change pex mode in capability reg */
+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22);
+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20);
+
+ }
+ else
+ {
+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK);
+ }
+
+ /* CPU config register Pex enable */
+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK);
+}
+#endif
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h
new file mode 100644
index 000000000..224ed07f5
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h
@@ -0,0 +1,120 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvCpuIfh
+#define __INCmvCpuIfh
+
+/* includes */
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "ctrlEnv/sys/mvAhbToMbus.h"
+#include "ddr2/mvDramIf.h"
+#include "ctrlEnv/sys/mvSysDram.h"
+#if defined(MV_INCLUDE_PEX)
+#include "pex/mvPex.h"
+#endif
+
+/* defines */
+
+/* typedefs */
+/* This structure describes CPU interface address decode window */
+typedef struct _mvCpuIfDecWin
+{
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_CPU_DEC_WIN;
+
+
+
+/* mvCpuIfLib.h API list */
+
+/* mvCpuIfLib.h API list */
+
+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap);
+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin);
+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin);
+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable);
+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target);
+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target);
+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target);
+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress);
+#if defined(MV_INCLUDE_PEX)
+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin);
+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType);
+#endif
+#if defined(MV_INCLUDE_PCI)
+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin);
+#endif
+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin);
+
+MV_VOID mvCpuIfAddDecShow(MV_VOID);
+
+#if defined(MV88F6281)
+MV_STATUS mvCpuIfBridgeReorderWAInit(void);
+#endif
+
+#endif /* __INCmvCpuIfh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S
new file mode 100644
index 000000000..b7efda02c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S
@@ -0,0 +1,163 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define MV_ASMLANGUAGE
+#include "mvOsAsm.h"
+#include "mvDeviceId.h"
+#include "mvCtrlEnvRegs.h"
+#include "mvCpuIfRegs.h"
+#include "mvCtrlEnvAsm.h"
+
+
+/*******************************************************************************
+* mvCpuIfPreInit - Make early initialization of CPU interface.
+*
+* DESCRIPTION:
+* The function will initialize the CPU interface parameters that must
+* be initialize before any BUS activity towards the DDR interface,
+* which means it must be executed from ROM. Because of that, the function
+* is implemented in assembly code.
+* The function configure the following CPU config register parameters:
+* 1) CPU2MbusLTickDrv
+* 2) CPU2MbusLTickSample.
+* NOTE: This function must be called AFTER the internal register
+* base is modified to INTER_REGS_BASE.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+* r11 holds return function address.
+*******************************************************************************/
+#define MV88F6281_PCKG_OPT 2
+#define MV88F6192_PCKG_OPT 1
+#define MV88F6180_PCKG_OPT 0
+
+ .globl _mvCpuIfPreInit
+_mvCpuIfPreInit:
+
+ mov r11, LR /* Save link register */
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r4, r5);
+
+ /* goto calcConfigReg if device is 6281 */
+ ldr r5, =MV88F6281_PCKG_OPT
+ cmp r4, r5
+ beq calcConfigReg
+
+ /* goto calcConfigReg if device is 6192/6190 */
+ ldr r5, =MV88F6192_PCKG_OPT
+ cmp r4, r5
+ beq calcConfigReg
+
+ /* Else 6180 */
+ /* Get the "sample on reset" register */
+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
+ ldr r5, =MSAR_CPUCLCK_MASK_6180
+ and r5, r4, r5
+ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
+ cmp r5, #CPU_2_DDR_CLK_1x3_1
+ beq setConfigReg
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
+ cmp r5, #CPU_2_DDR_CLK_1x4_1
+ beq setConfigReg
+ b setConfigReg
+
+calcConfigReg:
+ /* Get the "sample on reset" register */
+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
+ ldr r5, =MSAR_DDRCLCK_RTIO_MASK
+ and r5, r4, r5
+ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
+ cmp r5, #CPU_2_DDR_CLK_1x3
+ beq setConfigReg
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
+ cmp r5, #CPU_2_DDR_CLK_1x4
+ beq setConfigReg
+
+ /* Else */
+ ldr r4, =0
+
+setConfigReg:
+ /* Read CPU Config register */
+ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG)
+ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK)
+ and r7, r7, r5 /* Clear register fields */
+ orr r7, r7, r4 /* Set the values according to the findings */
+ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG)
+
+done:
+ mov PC, r11 /* r11 is saved link register */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h
new file mode 100644
index 000000000..8cfeee2db
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h
@@ -0,0 +1,304 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvCpuIfRegsh
+#define __INCmvCpuIfRegsh
+
+/****************************************/
+/* ARM Control and Status Registers Map */
+/****************************************/
+
+#define CPU_CONFIG_REG 0x20100
+#define CPU_CTRL_STAT_REG 0x20104
+#define CPU_RSTOUTN_MASK_REG 0x20108
+#define CPU_SYS_SOFT_RST_REG 0x2010C
+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110
+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114
+#define CPU_FTDLL_CONFIG_REG 0x20120
+#define CPU_L2_CONFIG_REG 0x20128
+
+
+
+/* ARM Configuration register */
+/* CPU_CONFIG_REG (CCR) */
+
+
+/* Reset vector location */
+#define CCR_VEC_INIT_LOC_OFFS 1
+#define CCR_VEC_INIT_LOC_MASK BIT1
+/* reset at 0x00000000 */
+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS)
+/* reset at 0xFFFF0000 */
+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS)
+
+
+#define CCR_AHB_ERROR_PROP_OFFS 2
+#define CCR_AHB_ERROR_PROP_MASK BIT2
+/* Erros are not propogated to AHB */
+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS)
+/* Erros are propogated to AHB */
+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS)
+
+
+#define CCR_ENDIAN_INIT_OFFS 3
+#define CCR_ENDIAN_INIT_MASK BIT3
+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS)
+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS)
+
+
+#define CCR_INCR_EN_OFFS 4
+#define CCR_INCR_EN_MASK BIT4
+#define CCR_INCR_EN BIT4
+
+
+#define CCR_NCB_BLOCKING_OFFS 5
+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS)
+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS)
+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS)
+
+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8
+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS)
+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12
+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)
+#define CCR_ICACH_PREF_BUF_ENABLE BIT16
+#define CCR_DCACH_PREF_BUF_ENABLE BIT17
+
+/* Ratio options for CPU to DDR for 6281/6192/6190 */
+#define CPU_2_DDR_CLK_1x3 4
+#define CPU_2_DDR_CLK_1x4 6
+
+/* Ratio options for CPU to DDR for 6281 only */
+#define CPU_2_DDR_CLK_2x9 7
+#define CPU_2_DDR_CLK_1x5 8
+#define CPU_2_DDR_CLK_1x6 9
+
+/* Ratio options for CPU to DDR for 6180 only */
+#define CPU_2_DDR_CLK_1x3_1 0x5
+#define CPU_2_DDR_CLK_1x4_1 0x6
+
+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */
+/* CPU to Mbus-L Tick Sample fields in CPU config register */
+
+#define TICK_DRV_1x1 0
+#define TICK_DRV_1x2 0
+#define TICK_DRV_1x3 1
+#define TICK_DRV_1x4 2
+#define TICK_SMPL_1x1 0
+#define TICK_SMPL_1x2 1
+#define TICK_SMPL_1x3 0
+#define TICK_SMPL_1x4 0
+
+#define CPU_2_MBUSL_DDR_CLK_1x2 \
+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
+#define CPU_2_MBUSL_DDR_CLK_1x3 \
+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
+#define CPU_2_MBUSL_DDR_CLK_1x4 \
+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
+
+/* ARM Control and Status register */
+/* CPU_CTRL_STAT_REG (CCSR) */
+
+
+/*
+This is used to block PCI express\PCI from access Socrates/Feroceon GP
+while ARM boot is still in progress
+*/
+
+#define CCSR_PCI_ACCESS_OFFS 0
+#define CCSR_PCI_ACCESS_MASK BIT0
+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS)
+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS)
+
+#define CCSR_ARM_RESET BIT1
+#define CCSR_SELF_INT BIT2
+#define CCSR_BIG_ENDIAN BIT15
+
+
+/* RSTOUTn Mask Register */
+/* CPU_RSTOUTN_MASK_REG (CRMR) */
+
+#define CRMR_PEX_RST_OUT_OFFS 0
+#define CRMR_PEX_RST_OUT_MASK BIT0
+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS)
+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS)
+
+#define CRMR_WD_RST_OUT_OFFS 1
+#define CRMR_WD_RST_OUT_MASK BIT1
+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS)
+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS)
+
+#define CRMR_SOFT_RST_OUT_OFFS 2
+#define CRMR_SOFT_RST_OUT_MASK BIT2
+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS)
+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS)
+
+/* System Software Reset Register */
+/* CPU_SYS_SOFT_RST_REG (CSSRR) */
+
+#define CSSRR_SYSTEM_SOFT_RST BIT0
+
+/* AHB to Mbus Bridge Interrupt Cause Register*/
+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */
+
+#define CAMCIR_ARM_SELF_INT BIT0
+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1
+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2
+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3
+
+
+/* AHB to Mbus Bridge Interrupt Mask Register*/
+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */
+
+#define CAMCIR_ARM_SELF_INT_OFFS 0
+#define CAMCIR_ARM_SELF_INT_MASK BIT0
+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS)
+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS)
+
+
+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1
+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1
+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
+
+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2
+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2
+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
+
+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3
+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3
+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
+
+/* CPU FTDLL Config register (CFCR) fields */
+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0
+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS)
+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8
+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS)
+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15)
+/* For Orion 2 D2 only */
+#define CFCR_MRVL_CPU_ID_OFFS 16
+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS)
+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS)
+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS)
+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7
+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS)
+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
+
+/* CPU_L2_CONFIG_REG fields */
+#ifdef MV_CPU_LE
+#define CL2CR_L2_ECC_EN_OFFS 2
+#define CL2CR_L2_WT_MODE_OFFS 4
+#else
+#define CL2CR_L2_ECC_EN_OFFS 26
+#define CL2CR_L2_WT_MODE_OFFS 28
+#endif
+
+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS)
+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS)
+
+/*******************************************/
+/* Main Interrupt Controller Registers Map */
+/*******************************************/
+
+#define CPU_MAIN_INT_CAUSE_REG 0x20200
+#define CPU_MAIN_IRQ_MASK_REG 0x20204
+#define CPU_MAIN_FIQ_MASK_REG 0x20208
+#define CPU_ENPOINT_MASK_REG 0x2020C
+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210
+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214
+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218
+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C
+
+
+/*******************************************/
+/* ARM Doorbell Registers Map */
+/*******************************************/
+
+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400
+#define CPU_HOST_TO_ARM_MASK_REG 0x20404
+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408
+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C
+
+
+
+/* CPU control register map */
+/* Set bits means value is about to change according to new value */
+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK)
+
+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00)
+
+/* CPU Control and status defaults */
+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK)
+
+
+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE)
+
+#endif /* __INCmvCpuIfRegsh */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c
new file mode 100644
index 000000000..769475f8f
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c
@@ -0,0 +1,324 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "mvSysAudio.h"
+
+/*******************************************************************************
+* mvAudioWinSet - Set AUDIO target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the AUDIO will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - AUDIO target address decode window number.
+* pAddrDecWin - AUDIO target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if address window overlapps with other address decode windows.
+* MV_BAD_PARAM if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+
+ /* Parameter checking */
+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ decRegs.baseReg = 0;
+ decRegs.sizeReg = 0;
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
+
+ /* set attributes */
+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK;
+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET);
+
+ /* set target ID */
+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK;
+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET);
+
+ if (pAddrDecWin->enable == MV_TRUE)
+ {
+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK;
+ }
+ else
+ {
+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK;
+ }
+
+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg);
+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvAudioWinGet - Get AUDIO peripheral target address window.
+*
+* DESCRIPTION:
+* Get AUDIO peripheral target address window.
+*
+* INPUT:
+* winNum - AUDIO target address decode window number.
+*
+* OUTPUT:
+* pAddrDecWin - AUDIO target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+ /* Parameter checking */
+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s : ERR. Invalid winNum %d\n",
+ __FUNCTION__, winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) );
+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) );
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
+ {
+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >>
+ MV_AUDIO_WIN_ATTR_OFFSET;
+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >>
+ MV_AUDIO_WIN_TARGET_OFFSET;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ /* Check if window is enabled */
+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+ return MV_OK;
+}
+/*******************************************************************************
+* mvAudioAddrDecShow - Print the AUDIO address decode map.
+*
+* DESCRIPTION:
+* This function print the AUDIO address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvAudioAddrDecShow(MV_VOID)
+{
+
+ MV_AUDIO_DEC_WIN win;
+ int i;
+
+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0))
+ return;
+
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "AUDIO:\n" );
+ mvOsOutput( "----\n" );
+
+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ )
+ {
+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", i );
+
+ if( mvAudioWinGet( i, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+ mvOsOutput( "...." );
+
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+}
+
+
+/*******************************************************************************
+* mvAudioWinInit - Initialize the integrated AUDIO target address window.
+*
+* DESCRIPTION:
+* Initialize the AUDIO peripheral target address window.
+*
+* INPUT:
+*
+*
+* OUTPUT:
+*
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvAudioInit(MV_VOID)
+{
+ int winNum;
+ MV_AUDIO_DEC_WIN audioWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ MV_U32 status;
+
+ mvAudioHalInit();
+
+ /* Initiate Audio address decode */
+
+ /* First disable all address decode windows */
+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++)
+ {
+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum));
+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK;
+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal);
+ }
+
+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++)
+ {
+
+ /* We will set the Window to DRAM_CS0 in default */
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(SDRAM_CS0,
+ &cpuAddrDecWin);
+
+ if (MV_OK != status)
+ {
+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ audioWin.enable = MV_TRUE;
+ audioWin.target = SDRAM_CS0;
+
+ if(MV_OK != mvAudioWinSet(winNum, &audioWin))
+ {
+ return MV_ERROR;
+ }
+ }
+ }
+
+ return MV_OK;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h
new file mode 100644
index 000000000..f59eb9a90
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h
@@ -0,0 +1,123 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __INCMVSysAudioH
+#define __INCMVSysAudioH
+
+#include "mvCommon.h"
+#include "audio/mvAudio.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+/***********************************/
+/* Audio Address Decoding registers*/
+/***********************************/
+
+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2
+#define MV_AUDIO_RECORD_WIN_NUM 0
+#define MV_AUDIO_PLAYBACK_WIN_NUM 1
+
+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3))
+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3))
+
+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM)
+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM)
+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM)
+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM)
+
+
+/* BITs in Windows 0-3 Control and Base Registers */
+#define MV_AUDIO_WIN_ENABLE_BIT 0
+#define MV_AUDIO_WIN_ENABLE_MASK (1<<MV_AUDIO_WIN_ENABLE_BIT)
+
+#define MV_AUDIO_WIN_TARGET_OFFSET 4
+#define MV_AUDIO_WIN_TARGET_MASK (0xF<<MV_AUDIO_WIN_TARGET_OFFSET)
+
+#define MV_AUDIO_WIN_ATTR_OFFSET 8
+#define MV_AUDIO_WIN_ATTR_MASK (0xFF<<MV_AUDIO_WIN_ATTR_OFFSET)
+
+#define MV_AUDIO_WIN_SIZE_OFFSET 16
+#define MV_AUDIO_WIN_SIZE_MASK (0xFFFF<<MV_AUDIO_WIN_SIZE_OFFSET)
+
+#define MV_AUDIO_WIN_BASE_OFFSET 16
+#define MV_AUDIO_WIN_BASE_MASK (0xFFFF<<MV_AUDIO_WIN_BASE_OFFSET)
+
+
+typedef struct _mvAudioDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+} MV_AUDIO_DEC_WIN;
+
+
+MV_STATUS mvAudioInit(MV_VOID);
+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin);
+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin);
+MV_STATUS mvAudioWinInit(MV_VOID);
+MV_VOID mvAudioAddrDecShow(MV_VOID);
+
+
+#endif
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c
new file mode 100644
index 000000000..84d0cd0bd
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c
@@ -0,0 +1,382 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "mvSysCesa.h"
+
+#if (MV_CESA_VERSION >= 2)
+MV_TARGET tdmaAddrDecPrioTable[] =
+{
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_MEM,
+#endif
+
+ TBL_TERM
+};
+
+/*******************************************************************************
+* mvCesaWinGet - Get TDMA target address window.
+*
+* DESCRIPTION:
+* Get TDMA target address window.
+*
+* INPUT:
+* winNum - TDMA target address decode window number.
+*
+* OUTPUT:
+* pDecWin - TDMA target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin)
+{
+ MV_DEC_WIN_PARAMS winParam;
+ MV_U32 sizeReg, baseReg;
+
+ /* Parameter checking */
+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN)
+ {
+ mvOsPrintf("%s : ERR. Invalid winNum %d\n",
+ __FUNCTION__, winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) );
+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) );
+
+ /* Check if window is enabled */
+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK)
+ {
+ pDecWin->enable = MV_TRUE;
+
+ /* Extract window parameters from registers */
+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET;
+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET;
+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET;
+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK);
+
+ /* Translate the decode window parameters to address decode struct */
+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin))
+ {
+ mvOsPrintf("Failed to translate register parameters to CESA address" \
+ " decode window structure\n");
+ return MV_ERROR;
+ }
+ }
+ else
+ {
+ pDecWin->enable = MV_FALSE;
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviur is expected in case TDMA address decode
+* windows overlapps.
+* This function detects TDMA address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE - if the given address window overlap current address
+* decode map,
+* MV_FALSE - otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 winNumIndex;
+ MV_DEC_WIN addrDecWin;
+
+ for(winNumIndex=0; winNumIndex<MV_CESA_TDMA_ADDR_DEC_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvCesaWinGet(winNumIndex, &addrDecWin))
+ {
+ mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if(addrDecWin.enable == MV_FALSE)
+ {
+ continue;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvCesaTdmaWinSet - Set CESA TDMA target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the CESA TDMA will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - CESA TDMA target address decode window number.
+* pAddrDecWin - CESA TDMA target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR - if address window overlapps with other address decode windows.
+* MV_BAD_PARAM - if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+static MV_STATUS mvCesaTdmaWinSet(MV_U32 winNum, MV_DEC_WIN *pDecWin)
+{
+ MV_DEC_WIN_PARAMS winParams;
+ MV_U32 sizeReg, baseReg;
+
+ /* Parameter checking */
+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN)
+ {
+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin))
+ {
+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pDecWin->target),
+ pDecWin->addrWin.baseLow,
+ pDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams))
+ {
+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* set Size, Attributes and TargetID */
+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) |
+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) |
+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK));
+
+ if (pDecWin->enable == MV_TRUE)
+ {
+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK;
+ }
+ else
+ {
+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK;
+ }
+
+ /* Update Base value */
+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK);
+
+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg);
+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg);
+
+ return MV_OK;
+}
+
+
+static MV_STATUS mvCesaTdmaAddrDecInit (void)
+{
+ MV_U32 winNum;
+ MV_STATUS status;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ MV_DEC_WIN cesaWin;
+ MV_U32 winPrioIndex = 0;
+
+ /* First disable all address decode windows */
+ for(winNum=0; winNum<MV_CESA_TDMA_ADDR_DEC_WIN; winNum++)
+ {
+ MV_REG_BIT_RESET(MV_CESA_TDMA_WIN_CTRL_REG(winNum), MV_CESA_TDMA_WIN_ENABLE_MASK);
+ }
+
+ /* Go through all windows in user table until table terminator */
+ winNum = 0;
+ while( (tdmaAddrDecPrioTable[winPrioIndex] != TBL_TERM) &&
+ (winNum < MV_CESA_TDMA_ADDR_DEC_WIN) ) {
+
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(tdmaAddrDecPrioTable[winPrioIndex],
+ &cpuAddrDecWin);
+ if(MV_NO_SUCH == status){
+ winPrioIndex++;
+ continue;
+ }
+
+ if (MV_OK != status)
+ {
+ mvOsPrintf("cesaInit: TargetWinGet failed. winNum=%d, winIdx=%d, target=%d, status=0x%x\n",
+ winNum, winPrioIndex, tdmaAddrDecPrioTable[winPrioIndex], status);
+ return MV_ERROR;
+ }
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ cesaWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ cesaWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ cesaWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ cesaWin.enable = MV_TRUE;
+ cesaWin.target = tdmaAddrDecPrioTable[winPrioIndex];
+
+#if defined(MV646xx)
+ /* Get the default attributes for that target window */
+ mvCtrlDefAttribGet(cesaWin.target, &cesaWin.addrWinAttr);
+#endif /* MV646xx */
+
+ if(MV_OK != mvCesaTdmaWinSet(winNum, &cesaWin))
+ {
+ mvOsPrintf("mvCesaTdmaWinSet FAILED: winNum=%d\n",
+ winNum);
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex++;
+ }
+ return MV_OK;
+}
+#endif /* MV_CESA_VERSION >= 2 */
+
+
+
+
+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle)
+{
+ MV_U32 cesaCryptEngBase;
+ MV_CPU_DEC_WIN addrDecWin;
+
+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE)
+ {
+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n",
+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE);
+ return MV_FAIL;
+ }
+#if 0
+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK)
+ cesaCryptEngBase = addrDecWin.addrWin.baseLow;
+ else
+ {
+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n");
+ return MV_ERROR;
+ }
+#else
+ cesaCryptEngBase = (MV_U32)pSramBase;
+#endif
+
+#if 0 /* Already done in the platform init */
+#if (MV_CESA_VERSION >= 2)
+ mvCesaTdmaAddrDecInit();
+#endif /* MV_CESA_VERSION >= 2 */
+#endif
+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase,
+ osHandle);
+
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h
new file mode 100644
index 000000000..73bcdc583
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h
@@ -0,0 +1,100 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __mvSysCesa_h__
+#define __mvSysCesa_h__
+
+
+#include "mvCommon.h"
+#include "cesa/mvCesa.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+/***************************** TDMA Registers *************************************/
+
+#define MV_CESA_TDMA_ADDR_DEC_WIN 4
+
+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3))
+
+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3))
+
+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0
+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT)
+
+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4
+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET)
+
+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8
+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET)
+
+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16
+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET)
+
+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16
+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET)
+
+
+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle);
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c
new file mode 100644
index 000000000..6f76c2caa
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c
@@ -0,0 +1,348 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+
+#include "ddr2/mvDramIf.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "ctrlEnv/sys/mvSysDram.h"
+
+/* #define MV_DEBUG */
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin);
+
+/*******************************************************************************
+* mvDramIfWinSet - Set DRAM interface address decode window
+*
+* DESCRIPTION:
+* This function sets DRAM interface address decode window.
+*
+* INPUT:
+* target - System target. Use only SDRAM targets.
+* pAddrDecWin - SDRAM address window structure.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
+* otherwise.
+*******************************************************************************/
+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
+{
+ MV_U32 baseReg=0,sizeReg=0;
+ MV_U32 baseToReg=0 , sizeToReg=0;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(target))
+ {
+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlaps with current enabled windows */
+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target);
+ return MV_BAD_PARAM;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\
+ "\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ target,
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ /* read base register*/
+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target));
+
+ /* read size register */
+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target));
+
+ /* BaseLow[31:16] => base register [31:16] */
+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK;
+
+ /* Write to address decode Base Address Register */
+ baseReg &= ~SCBAR_BASE_MASK;
+ baseReg |= baseToReg;
+
+ /* Translate the given window size to register format */
+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT);
+
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target);
+ return MV_BAD_PARAM;
+ }
+
+ /* set size */
+ sizeReg &= ~SCSR_SIZE_MASK;
+ /* Size is located at upper 16 bits */
+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS);
+
+ /* enable/Disable */
+ if (MV_TRUE == pAddrDecWin->enable)
+ {
+ sizeReg |= SCSR_WIN_EN;
+ }
+ else
+ {
+ sizeReg &= ~SCSR_WIN_EN;
+ }
+
+ /* 3) Write to address decode Base Address Register */
+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg);
+
+ /* Write to address decode Size Register */
+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg);
+
+ return MV_OK;
+}
+/*******************************************************************************
+* mvDramIfWinGet - Get DRAM interface address decode window
+*
+* DESCRIPTION:
+* This function gets DRAM interface address decode window.
+*
+* INPUT:
+* target - System target. Use only SDRAM targets.
+*
+* OUTPUT:
+* pAddrDecWin - SDRAM address window structure.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
+* otherwise.
+*******************************************************************************/
+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
+{
+ MV_U32 baseReg,sizeReg;
+ MV_U32 sizeRegVal;
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(target))
+ {
+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ /* Read base and size registers */
+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target));
+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target));
+
+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS;
+
+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal,
+ SCSR_SIZE_ALIGNMENT);
+
+ /* Check if ctrlRegToSize returned OK */
+ if (-1 == pAddrDecWin->addrWin.size)
+ {
+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ /* Extract base address */
+ /* Base register [31:16] ==> baseLow[31:16] */
+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK;
+
+ pAddrDecWin->addrWin.baseHigh = 0;
+
+
+ if (sizeReg & SCSR_WIN_EN)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+
+ return MV_OK;
+}
+/*******************************************************************************
+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window
+*
+* DESCRIPTION:
+* This function enable/Disable SDRAM address decode window.
+*
+* INPUT:
+* target - System target. Use only SDRAM targets.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR in case function parameter are invalid, MV_OK otherewise.
+*
+*******************************************************************************/
+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable)
+{
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(target))
+ {
+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ if (enable == MV_TRUE)
+ { /* First check for overlap with other enabled windows */
+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin))
+ {
+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n",
+ target);
+ return MV_ERROR;
+ }
+ /* Check for overlapping */
+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin)))
+ {
+ /* No Overlap. Enable address decode winNum window */
+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN);
+ }
+ else
+ { /* Overlap detected */
+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n",
+ target);
+ return MV_ERROR;
+ }
+ }
+ else
+ { /* Disable address decode winNum window */
+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window
+*
+* DESCRIPTION:
+* This function scan each SDRAM address decode window to test if it
+* overlapps the given address windoow
+*
+* INPUT:
+* target - SDRAM target where the function skips checking.
+* pAddrDecWin - The tested address window for overlapping with
+* SDRAM windows.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlaps any enabled address
+* decode map, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin)
+{
+ MV_TARGET targetNum;
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++)
+ {
+ /* don't check our winNum or illegal targets */
+ if (targetNum == target)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin))
+ {
+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ continue;
+ }
+
+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin))
+ {
+ mvOsPrintf(
+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n",
+ target, targetNum);
+ return MV_TRUE;
+ }
+ }
+
+ return MV_FALSE;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h
new file mode 100644
index 000000000..7bd9c9de2
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h
@@ -0,0 +1,80 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __sysDram
+#define __sysDram
+
+/* This structure describes CPU interface address decode window */
+typedef struct _mvDramIfDecWin
+{
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+}MV_DRAM_DEC_WIN;
+
+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable);
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c
new file mode 100644
index 000000000..7f6e4a59d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c
@@ -0,0 +1,658 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include "ctrlEnv/sys/mvSysGbe.h"
+
+
+
+typedef struct _mvEthDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_ETH_DEC_WIN;
+
+MV_TARGET ethAddrDecPrioTap[] =
+{
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS0)
+ DEVICE_CS0,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS1)
+ DEVICE_CS1,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS2)
+ DEVICE_CS2,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS3)
+ DEVICE_CS3,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_IO,
+#endif
+ TBL_TERM
+};
+
+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin);
+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin);
+
+
+/*******************************************************************************
+* mvEthWinInit - Initialize ETH address decode windows
+*
+* DESCRIPTION:
+* This function initialize ETH window decode unit. It set the
+* default address decode windows of the unit.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if setting fail.
+*******************************************************************************/
+/* Configure EthDrv memory map registes. */
+MV_STATUS mvEthWinInit (int port)
+{
+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0;
+ MV_ETH_DEC_WIN ethWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ static MV_U32 accessProtReg = 0;
+
+#if (MV_ETH_VERSION <= 1)
+ static MV_BOOL isFirst = MV_TRUE;
+
+ if(isFirst == MV_FALSE)
+ {
+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg);
+ return MV_OK;
+ }
+ isFirst = MV_FALSE;
+#endif /* MV_GIGA_ETH_VERSION */
+
+ /* Initiate Ethernet address decode */
+
+ /* First disable all address decode windows */
+ for(winNum=0; winNum<ETH_MAX_DECODE_WIN; winNum++)
+ {
+ regVal |= MV_BIT_MASK(winNum);
+ }
+ MV_REG_WRITE(ETH_BASE_ADDR_ENABLE_REG(port), regVal);
+
+ /* Go through all windows in user table until table terminator */
+ for (winNum=0; ((ethAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
+ (winNum < ETH_MAX_DECODE_WIN)); )
+ {
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(ethAddrDecPrioTap[winPrioIndex],
+ &cpuAddrDecWin);
+
+ if(MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if (MV_OK != status)
+ {
+ mvOsPrintf("mvEthWinInit: ERR. mvCpuIfTargetWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ ethWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ ethWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ ethWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ ethWin.enable = MV_TRUE;
+ ethWin.target = ethAddrDecPrioTap[winPrioIndex];
+
+ if(MV_OK != mvEthWinSet(port, winNum, &ethWin))
+ {
+ mvOsPrintf("mvEthWinInit: ERR. mvEthWinSet failed winNum=%d\n",
+ winNum);
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex ++;
+ }
+
+ /* set full access to all windows. */
+ for(i=0; i<winNum; i++)
+ {
+ accessProtReg |= (FULL_ACCESS << (i*2));
+ }
+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthWinSet - Set ETH target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the ETH will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - ETH to target address decode window number.
+* pAddrDecWin - ETH target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if address window overlapps with other address decode windows.
+* MV_BAD_PARAM if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+
+ /* Parameter checking */
+ if (winNum >= ETH_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+
+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum));
+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum));
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n");
+ return MV_ERROR;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
+
+ /* set attributes */
+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK;
+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS;
+ /* set target ID */
+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK;
+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS;
+
+ /* for the safe side we disable the window before writing the new
+ values */
+ mvEthWinEnable(port, winNum, MV_FALSE);
+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg);
+
+ /* Write to address decode Size Register */
+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg);
+
+ /* Enable address decode target window */
+ if (pAddrDecWin->enable == MV_TRUE)
+ {
+ mvEthWinEnable(port, winNum, MV_TRUE);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvETHWinGet - Get dma peripheral target address window.
+*
+* DESCRIPTION:
+* Get ETH peripheral target address window.
+*
+* INPUT:
+* winNum - ETH to target address decode window number.
+*
+* OUTPUT:
+* pAddrDecWin - ETH target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+ /* Parameter checking */
+ if (winNum >= ETH_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum));
+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum));
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
+ {
+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n");
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib =
+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS;
+ targetAttrib.targetId =
+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ /* Check if window is enabled */
+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) )
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthWinEnable - Enable/disable a ETH to target address window
+*
+* DESCRIPTION:
+* This function enable/disable a ETH to target address window.
+* According to parameter 'enable' the routine will enable the
+* window, thus enabling ETH accesses (before enabling the window it is
+* tested for overlapping). Otherwise, the window will be disabled.
+*
+* INPUT:
+* winNum - ETH to target address decode window number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if decode window number was wrong or enabled window overlapps.
+*
+*******************************************************************************/
+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable)
+{
+ MV_ETH_DEC_WIN addrDecWin;
+
+ /* Parameter checking */
+ if (winNum >= ETH_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum);
+ return MV_ERROR;
+ }
+
+ if (enable == MV_TRUE)
+ { /* First check for overlap with other enabled windows */
+ /* Get current window */
+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin))
+ {
+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n");
+ return MV_ERROR;
+ }
+ /* Check for overlapping */
+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin)))
+ {
+ /* No Overlap. Enable address decode target window */
+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum));
+ }
+ else
+ { /* Overlap detected */
+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n");
+ return MV_ERROR;
+ }
+ }
+ else
+ { /* Disable address decode target window */
+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum));
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthWinTargetGet - Get Window number associated with target
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+* window number
+*
+*******************************************************************************/
+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target)
+{
+ MV_ETH_DEC_WIN decWin;
+ MV_U32 winNum;
+
+ /* Check parameters */
+ if (target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target);
+ return 0xffffffff;
+ }
+
+ for (winNum=0; winNum<ETH_MAX_DECODE_WIN; winNum++)
+ {
+ if (mvEthWinGet(port, winNum,&decWin) != MV_OK)
+ {
+ mvOsPrintf("mvAhbToMbusWinTargetGet: window returned error\n");
+ return 0xffffffff;
+ }
+
+ if (decWin.enable == MV_TRUE)
+ {
+ if (decWin.target == target)
+ {
+ return winNum;
+ }
+ }
+ }
+ return 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* mvEthProtWinSet - Set access protection of Ethernet to target window.
+*
+* DESCRIPTION:
+* Each Ethernet port can be configured with access attributes for each
+* of the Ethenret to target windows (address decode windows). This
+* function sets access attributes to a given window for the given channel.
+*
+* INPUTS:
+* ethPort - ETH channel number. See MV_ETH_CHANNEL enumerator.
+* winNum - IETH to target address decode window number.
+* access - IETH access rights. See MV_ACCESS_RIGHTS enumerator.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR in case window number is invalid or access right reserved.
+*
+*******************************************************************************/
+MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS access)
+{
+ MV_U32 protReg;
+
+ /* Parameter checking */
+ if(portNo >= mvCtrlEthMaxPortGet())
+ {
+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo);
+ return MV_ERROR;
+ }
+
+ if (winNum >= ETH_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum);
+ return MV_ERROR;
+ }
+
+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS))
+ {
+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access);
+ return MV_ERROR;
+ }
+ /* Read current protection register */
+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo));
+
+ /* Clear protection window field */
+ protReg &= ~(ETH_PROT_WIN_MASK(winNum));
+
+ /* Set new protection field value */
+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum)));
+
+ /* Write protection register back */
+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* ethWinOverlapDetect - Detect ETH address windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviur is expected in case ETH address decode
+* windows overlapps.
+* This function detects ETH address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 baseAddrEnableReg;
+ MV_U32 winNumIndex;
+ MV_ETH_DEC_WIN addrDecWin;
+
+ /* Read base address enable register. Do not check disabled windows */
+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port));
+
+ for (winNumIndex=0; winNumIndex<ETH_MAX_DECODE_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Do not check disabled windows */
+ if (baseAddrEnableReg & (1 << winNumIndex))
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvEthWinGet(port, winNumIndex, &addrDecWin))
+ {
+ mvOsPrintf("ethWinOverlapDetect: ERR. TargetWinGet failed\n");
+ return MV_ERROR;
+ }
+/*
+ mvOsPrintf("ethWinOverlapDetect:\n
+ winNumIndex =%d baseHigh =0x%x baseLow=0x%x size=0x%x enable=0x%x\n",
+ winNumIndex,
+ addrDecWin.addrWin.baseHigh,
+ addrDecWin.addrWin.baseLow,
+ addrDecWin.addrWin.size,
+ addrDecWin.enable);
+*/
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvEthAddrDecShow - Print the Etherent address decode map.
+*
+* DESCRIPTION:
+* This function print the Etherent address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void mvEthPortAddrDecShow(int port)
+{
+ MV_ETH_DEC_WIN win;
+ int i;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "ETH %d:\n", port );
+ mvOsOutput( "----\n" );
+
+ for( i = 0; i < ETH_MAX_DECODE_WIN; i++ )
+ {
+ memset( &win, 0, sizeof(ETH_MAX_DECODE_WIN) );
+
+ mvOsOutput( "win%d - ", i );
+
+ if( mvEthWinGet(port, i, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+ mvOsOutput( "...." );
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+ return;
+}
+
+void mvEthAddrDecShow(void)
+{
+ int port;
+
+ for(port=0; port<mvCtrlEthMaxPortGet(); port++)
+ {
+ if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port)) continue;
+
+ mvEthPortAddrDecShow(port);
+ }
+}
+
+
+void mvEthInit(void)
+{
+ MV_U32 port;
+
+ /* Power down all existing ports */
+ for(port=0; port<mvCtrlEthMaxPortGet(); port++)
+ {
+ if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port))
+ continue;
+
+ mvEthPortPowerUp(port);
+ mvEthWinInit(port);
+ }
+ mvEthHalInit();
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h
new file mode 100644
index 000000000..615af512d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h
@@ -0,0 +1,113 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSysGbeh
+#define __INCmvSysGbeh
+
+#include "mvCommon.h"
+#include "eth/mvEth.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+#define ETH_WIN_BASE_REG(port, win) (MV_ETH_REG_BASE(port) + 0x200 + ((win)<<3))
+#define ETH_WIN_SIZE_REG(port, win) (MV_ETH_REG_BASE(port) + 0x204 + ((win)<<3))
+#define ETH_WIN_REMAP_REG(port, win) (MV_ETH_REG_BASE(port) + 0x280 + ((win)<<2))
+#define ETH_BASE_ADDR_ENABLE_REG(port) (MV_ETH_REG_BASE(port) + 0x290)
+#define ETH_ACCESS_PROTECT_REG(port) (MV_ETH_REG_BASE(port) + 0x294)
+
+/**** Address decode parameters ****/
+
+/* Ethernet Base Address Register bits */
+#define ETH_MAX_DECODE_WIN 6
+#define ETH_MAX_HIGH_ADDR_REMAP_WIN 4
+
+/* Ethernet Port Access Protect (EPAP) register */
+
+/* The target associated with this window*/
+#define ETH_WIN_TARGET_OFFS 0
+#define ETH_WIN_TARGET_MASK (0xf << ETH_WIN_TARGET_OFFS)
+/* The target attributes Associated with window */
+#define ETH_WIN_ATTR_OFFS 8
+#define ETH_WIN_ATTR_MASK (0xff << ETH_WIN_ATTR_OFFS)
+
+/* Ethernet Port Access Protect Register (EPAPR) */
+#define ETH_PROT_NO_ACCESS NO_ACCESS_ALLOWED
+#define ETH_PROT_READ_ONLY READ_ONLY
+#define ETH_PROT_FULL_ACCESS FULL_ACCESS
+#define ETH_PROT_WIN_OFFS(winNum) (2 * (winNum))
+#define ETH_PROT_WIN_MASK(winNum) (0x3 << ETH_PROT_WIN_OFFS(winNum))
+
+MV_STATUS mvEthWinInit (int port);
+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum, MV_BOOL enable);
+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target);
+MV_STATUS mvEthProtWinSet(MV_U32 portNo, MV_U32 winNum, MV_ACCESS_RIGHTS
+ access);
+
+void mvEthPortAddrDecShow(int port);
+
+MV_VOID mvEthAddrDecShow(MV_VOID);
+
+void mvEthInit(void);
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.c
new file mode 100644
index 000000000..b0cb466ab
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.c
@@ -0,0 +1,1697 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ctrlEnv/sys/mvSysPex.h"
+
+/* this structure describes the mapping between a Pex Window and a CPU target*/
+typedef struct _pexWinToTarget
+{
+ MV_TARGET target;
+ MV_BOOL enable;
+
+}PEX_WIN_TO_TARGET;
+
+/* this array is a priority array that define How Pex windows should be
+configured , We have only 6 Pex Windows that can be configured , but we
+have maximum of 9 CPU target windows ! the following array is a priority
+array where the lowest index has the highest priotiy and the highest
+index has the lowest priority of being cnfigured */
+
+MV_U32 pexDevBarPrioTable[] =
+{
+#if defined(MV_INCLUDE_DEVICE_CS0)
+ DEVICE_CS0,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS1)
+ DEVICE_CS1,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS2)
+ DEVICE_CS2,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS3)
+ DEVICE_CS3,
+#endif
+/*
+#if defined(MV_INCLUDE_DEVICE_CS4)
+ DEVICE_CS4,
+#endif
+*/
+ TBL_TERM
+};
+
+
+/* PEX Wins registers offsets are inconsecutive. This struct describes WIN */
+/* register offsets and its function where its is located. */
+/* Also, PEX address remap registers offsets are inconsecutive. This struct */
+/* describes address remap register offsets */
+typedef struct _pexWinRegInfo
+{
+ MV_U32 baseLowRegOffs;
+ MV_U32 baseHighRegOffs;
+ MV_U32 sizeRegOffs;
+ MV_U32 remapLowRegOffs;
+ MV_U32 remapHighRegOffs;
+
+}PEX_WIN_REG_INFO;
+
+static MV_STATUS pexWinOverlapDetect(MV_U32 pexIf, MV_U32 winNum,
+ MV_ADDR_WIN *pAddrWin);
+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, MV_U32 winNum,
+ PEX_WIN_REG_INFO *pWinRegInfo);
+
+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size);
+
+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf,MV_ADDR_WIN *pAddrWin);
+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf,MV_U32 barNum,
+ MV_ADDR_WIN *pAddrWin);
+const MV_8* pexBarNameGet( MV_U32 bar );
+
+
+/*******************************************************************************
+* mvPexInit - Initialize PEX interfaces
+*
+* DESCRIPTION:
+*
+* This function is responsible of intialization of the Pex Interface , It
+* configure the Pex Bars and Windows in the following manner:
+*
+* Assumptions :
+* Bar0 is always internal registers bar
+* Bar1 is always the DRAM bar
+* Bar2 is always the Device bar
+*
+* 1) Sets the Internal registers bar base by obtaining the base from
+* the CPU Interface
+* 2) Sets the DRAM bar base and size by getting the base and size from
+* the CPU Interface when the size is the sum of all enabled DRAM
+* chip selects and the base is the base of CS0 .
+* 3) Sets the Device bar base and size by getting these values from the
+* CPU Interface when the base is the base of the lowest base of the
+* Device chip selects, and the
+*
+*
+* INPUT:
+*
+* pexIf - PEX interface number.
+*
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
+*
+*******************************************************************************/
+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType)
+{
+ MV_U32 bar;
+ MV_U32 winNum;
+ MV_PEX_BAR pexBar;
+ MV_PEX_DEC_WIN pexWin;
+ MV_CPU_DEC_WIN addrDecWin;
+ MV_TARGET target;
+ MV_U32 pexCurrWin=0;
+ MV_U32 status;
+ /* default and exapntion rom
+ are always configured */
+
+#ifndef MV_DISABLE_PEX_DEVICE_BAR
+ MV_U32 winIndex;
+ MV_U32 maxBase=0, sizeOfMaxBase=0;
+ MV_U32 pexStartWindow;
+#endif
+
+ /* Parameter checking */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ /* Enabled CPU access to PCI-Express */
+ mvCpuIfEnablePex(pexIf, pexType);
+
+ /* Start with bars */
+ /* First disable all PEX bars*/
+ for (bar = 0; bar < PEX_MAX_BARS; bar++)
+ {
+ if (PEX_INTER_REGS_BAR != bar)
+ {
+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE))
+ {
+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar);
+ return MV_ERROR;
+ }
+
+ }
+
+ }
+
+ /* and disable all PEX target windows */
+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++)
+ {
+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE))
+ {
+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n",
+ winNum);
+ return MV_ERROR;
+
+ }
+ }
+
+ /* Now, go through all bars*/
+
+
+
+/******************************************************************************/
+/* Internal registers bar */
+/******************************************************************************/
+ bar = PEX_INTER_REGS_BAR;
+
+ /* we only open the bar , no need to open windows for this bar */
+
+ /* first get the CS attribute from the CPU Interface */
+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin))
+ {
+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS);
+ return MV_ERROR;
+ }
+
+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow;
+ pexBar.addrWin.size = addrDecWin.addrWin.size;
+ pexBar.enable = MV_TRUE;
+
+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar))
+ {
+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar);
+ return MV_ERROR;
+ }
+
+/******************************************************************************/
+/* DRAM bar */
+/******************************************************************************/
+
+ bar = PEX_DRAM_BAR;
+
+ pexBar.addrWin.size = 0;
+
+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ )
+ {
+
+ status = mvCpuIfTargetWinGet(target,&addrDecWin);
+
+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0))
+ {
+ continue;
+ }
+
+ /* first get attributes from CPU If */
+ if (MV_OK != status)
+ {
+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target);
+ return MV_ERROR;
+ }
+ if (addrDecWin.enable == MV_TRUE)
+ {
+ /* the base is the base of DRAM CS0 always */
+ if (SDRAM_CS0 == target )
+ {
+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow;
+
+ }
+
+ /* increment the bar size to be the sum of the size of all
+ DRAM chips selecs */
+ pexBar.addrWin.size += addrDecWin.addrWin.size;
+
+ /* set a Pex window for this target !
+ DRAM CS always will have a Pex Window , and is not a
+ part of the priority table */
+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow;
+ pexWin.addrWin.size = addrDecWin.addrWin.size;
+
+ /* we disable the windows at first because we are not
+ sure that it is witihin bar boundries */
+ pexWin.enable =MV_FALSE;
+ pexWin.target = target;
+ pexWin.targetBar = bar;
+
+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin))
+ {
+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n");
+ return MV_ERROR;
+ }
+ }
+ }
+
+ /* check if the size of the bar is illeggal */
+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT))
+ {
+ /* try to get a good size */
+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size,
+ PXBCR_BAR_SIZE_ALIGNMENT);
+ }
+
+ /* check if the size and base are valid */
+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin))
+ {
+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar);
+ mvOsPrintf("it will be disabled\n");
+ mvOsPrintf("please check Pex and CPU windows configuration\n");
+ }
+ else
+ {
+ pexBar.enable = MV_TRUE;
+
+ /* configure the bar */
+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar))
+ {
+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar);
+ return MV_ERROR;
+ }
+
+ /* after the bar was configured then we enable the Pex windows*/
+ for (winNum = 0;winNum < pexCurrWin ;winNum++)
+ {
+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE))
+ {
+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum);
+ return MV_ERROR;
+ }
+
+ }
+ }
+
+/******************************************************************************/
+/* DEVICE bar */
+/******************************************************************************/
+
+/* Open the Device BAR for non linux only */
+#ifndef MV_DISABLE_PEX_DEVICE_BAR
+
+ /* then device bar*/
+ bar = PEX_DEVICE_BAR;
+
+ /* save the starting window */
+ pexStartWindow = pexCurrWin;
+ pexBar.addrWin.size = 0;
+ pexBar.addrWin.baseLow = 0xffffffff;
+ pexBar.addrWin.baseHigh = 0;
+ maxBase = 0;
+
+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ )
+ {
+ status = mvCpuIfTargetWinGet(target,&addrDecWin);
+
+ if (MV_NO_SUCH == status)
+ {
+ continue;
+ }
+
+ if (MV_OK != status)
+ {
+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target);
+ return MV_ERROR;
+ }
+
+ if (addrDecWin.enable == MV_TRUE)
+ {
+ /* get the minimum base */
+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow)
+ {
+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow;
+ }
+
+ /* get the maximum base */
+ if (addrDecWin.addrWin.baseLow > maxBase)
+ {
+ maxBase = addrDecWin.addrWin.baseLow;
+ sizeOfMaxBase = addrDecWin.addrWin.size;
+ }
+
+ /* search in the priority table for this target */
+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM;
+ winIndex++)
+ {
+ if (pexDevBarPrioTable[winIndex] != target)
+ {
+ continue;
+ }
+ else if (pexDevBarPrioTable[winIndex] == target)
+ {
+ /*found it */
+
+ /* if the index of this target in the prio table is valid
+ then we set the Pex window for this target, a valid index is
+ an index that is lower than the number of the windows that
+ was not configured yet */
+
+ /* we subtract 2 always because the default and expantion
+ rom windows are always configured */
+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2)
+ {
+ /* set a Pex window for this target ! */
+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh;
+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow;
+ pexWin.addrWin.size = addrDecWin.addrWin.size;
+
+ /* we disable the windows at first because we are not
+ sure that it is witihin bar boundries */
+ pexWin.enable = MV_FALSE;
+ pexWin.target = target;
+ pexWin.targetBar = bar;
+
+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,
+ &pexWin))
+ {
+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n");
+ return MV_ERROR;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase;
+ pexBar.enable = MV_TRUE;
+
+ /* check if the size of the bar is illegal */
+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT))
+ {
+ /* try to get a good size */
+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size,
+ PXBCR_BAR_SIZE_ALIGNMENT);
+ }
+
+ /* check if the size and base are valid */
+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin))
+ {
+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar);
+ mvOsPrintf("it will be disabled\n");
+ mvOsPrintf("please check Pex and CPU windows configuration\n");
+ }
+ else
+ {
+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar))
+ {
+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar);
+ return MV_ERROR;
+ }
+
+ /* now enable the windows */
+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++)
+ {
+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE))
+ {
+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n",
+ winNum);
+ return MV_ERROR;
+ }
+ }
+ }
+
+#endif
+
+ return mvPexHalInit(pexIf, pexType);
+
+}
+
+/*******************************************************************************
+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_OK if PEX BAR target window was set correctly,
+* MV_BAD_PARAM on bad params
+* MV_ERROR otherwise
+* (e.g. address window overlapps with other active PEX target window).
+*
+*******************************************************************************/
+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum,
+ MV_PEX_DEC_WIN *pAddrDecWin)
+{
+
+ MV_DEC_REGS decRegs;
+ PEX_WIN_REG_INFO winRegInfo;
+ MV_TARGET_ATTRIB targetAttribs;
+
+ /* Parameter checking */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ if (winNum >= PEX_MAX_TARGET_WIN)
+ {
+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum);
+ return MV_BAD_PARAM;
+
+ }
+
+ /* get the pex Window registers offsets */
+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo);
+
+
+ if (MV_TRUE == pAddrDecWin->enable)
+ {
+
+ /* 2) Check if the requested window overlaps with current windows */
+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* 2) Check if the requested window overlaps with current windows */
+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n",
+ winNum);
+ return MV_BAD_PARAM;
+ }
+
+ }
+
+
+
+ /* read base register*/
+
+ if (winRegInfo.baseLowRegOffs)
+ {
+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs);
+ }
+ else
+ {
+ decRegs.baseReg = 0;
+ }
+
+ if (winRegInfo.sizeRegOffs)
+ {
+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs);
+ }
+ else
+ {
+ decRegs.sizeReg =0;
+ }
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n");
+ return MV_ERROR;
+ }
+
+ /* enable\Disable */
+ if (MV_TRUE == pAddrDecWin->enable)
+ {
+ decRegs.sizeReg |= PXWCR_WIN_EN;
+ }
+ else
+ {
+ decRegs.sizeReg &= ~PXWCR_WIN_EN;
+ }
+
+
+ /* clear bit location */
+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK;
+
+ /* set bar Mapping */
+ if (pAddrDecWin->targetBar == 1)
+ {
+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1;
+ }
+ else if (pAddrDecWin->targetBar == 2)
+ {
+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
+
+ /* set attributes */
+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK;
+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS;
+ /* set target ID */
+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK;
+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS;
+
+
+ /* 3) Write to address decode Base Address Register */
+
+ if (winRegInfo.baseLowRegOffs)
+ {
+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg);
+ }
+
+ /* write size reg */
+ if (winRegInfo.sizeRegOffs)
+ {
+ if ((MV_PEX_WIN_DEFAULT == winNum)||
+ (MV_PEX_WIN_EXP_ROM == winNum))
+ {
+ /* clear size because there is no size field*/
+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK;
+
+ /* clear enable because there is no enable field*/
+ decRegs.sizeReg &= ~PXWCR_WIN_EN;
+
+ }
+
+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg);
+ }
+
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvPexTargetWinGet - Get PEX to peripheral target address window
+*
+* DESCRIPTION:
+* Get the PEX to peripheral target address window BAR.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* bar - BAR to be accessed by slave.
+*
+* OUTPUT:
+* pAddrBarWin - PEX target window information data structure.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum,
+ MV_PEX_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttrib;
+ MV_DEC_REGS decRegs;
+
+ PEX_WIN_REG_INFO winRegInfo;
+
+ /* Parameter checking */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ if (winNum >= PEX_MAX_TARGET_WIN)
+ {
+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum);
+ return MV_BAD_PARAM;
+
+ }
+
+ /* get the pex Window registers offsets */
+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo);
+
+ /* read base register*/
+ if (winRegInfo.baseLowRegOffs)
+ {
+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs);
+ }
+ else
+ {
+ decRegs.baseReg = 0;
+ }
+
+ /* read size reg */
+ if (winRegInfo.sizeRegOffs)
+ {
+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs);
+ }
+ else
+ {
+ decRegs.sizeReg =0;
+ }
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
+ {
+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n");
+ return MV_ERROR;
+
+ }
+
+ if (decRegs.sizeReg & PXWCR_WIN_EN)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+
+ }
+
+
+ #if 0
+ if (-1 == pAddrDecWin->addrWin.size)
+ {
+ return MV_ERROR;
+ }
+ #endif
+
+
+ /* get target bar */
+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 )
+ {
+ pAddrDecWin->targetBar = 1;
+ }
+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) ==
+ PXWCR_WIN_BAR_MAP_BAR2 )
+ {
+ pAddrDecWin->targetBar = 2;
+ }
+
+ /* attrib and targetId */
+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >>
+ PXWCR_ATTRIB_OFFS;
+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >>
+ PXWCR_TARGET_OFFS;
+
+ targetAttrib.attrib = pAddrDecWin->attrib;
+ targetAttrib.targetId = pAddrDecWin->targetId;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ return MV_OK;
+
+}
+
+
+/*******************************************************************************
+* mvPexTargetWinEnable - Enable/disable a PEX BAR window
+*
+* DESCRIPTION:
+* This function enable/disable a PEX BAR window.
+* if parameter 'enable' == MV_TRUE the routine will enable the
+* window, thus enabling PEX accesses for that BAR (before enabling the
+* window it is tested for overlapping). Otherwise, the window will
+* be disabled.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* bar - BAR to be accessed by slave.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable)
+{
+ PEX_WIN_REG_INFO winRegInfo;
+ MV_PEX_DEC_WIN addrDecWin;
+
+ /* Parameter checking */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ if (winNum >= PEX_MAX_TARGET_WIN)
+ {
+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum);
+ return MV_BAD_PARAM;
+
+ }
+
+
+ /* get the pex Window registers offsets */
+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo);
+
+
+ /* if the address windows is disabled , we only disable the appropriare
+ pex window and ignore other settings */
+
+ if (MV_FALSE == enable)
+ {
+
+ /* this is not relevant to default and expantion rom
+ windows */
+ if (winRegInfo.sizeRegOffs)
+ {
+ if ((MV_PEX_WIN_DEFAULT != winNum)&&
+ (MV_PEX_WIN_EXP_ROM != winNum))
+ {
+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN);
+ }
+ }
+
+ }
+ else
+ {
+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin))
+ {
+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n");
+ return MV_ERROR;
+ }
+
+ /* Check if the requested window overlaps with current windows */
+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin))
+ {
+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum);
+ return MV_BAD_PARAM;
+ }
+
+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin))
+ {
+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n",
+ winNum);
+ return MV_BAD_PARAM;
+ }
+
+
+ /* this is not relevant to default and expantion rom
+ windows */
+ if (winRegInfo.sizeRegOffs)
+ {
+ if ((MV_PEX_WIN_DEFAULT != winNum)&&
+ (MV_PEX_WIN_EXP_ROM != winNum))
+ {
+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN);
+ }
+ }
+
+
+ }
+
+ return MV_OK;
+
+}
+
+
+
+/*******************************************************************************
+* mvPexTargetWinRemap - Set PEX to target address window remap.
+*
+* DESCRIPTION:
+* The PEX interface supports remap of the BAR original address window.
+* For each BAR it is possible to define a remap address. For example
+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified
+* according to remap register but will also be targeted to the
+* SDRAM CS[0].
+*
+* INPUT:
+* pexIf - PEX interface number.
+* bar - Peripheral target enumerator accessed by slave.
+* pAddrWin - Address window to be checked.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum,
+ MV_PEX_REMAP_WIN *pAddrWin)
+{
+
+ PEX_WIN_REG_INFO winRegInfo;
+
+ /* Parameter checking */
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n",
+ pexIf);
+ return MV_BAD_PARAM;
+ }
+ if (MV_PEX_WIN_DEFAULT == winNum)
+ {
+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n",
+ winNum);
+ return MV_BAD_PARAM;
+
+ }
+
+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT))
+ {
+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\
+ "\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ pexIf,
+ winNum,
+ pAddrWin->addrWin.baseLow,
+ pAddrWin->addrWin.size);
+
+ return MV_ERROR;
+ }
+
+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo);
+
+ /* Set remap low register value */
+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow);
+
+ /* Skip base high settings if the BAR has only base low (32-bit) */
+ if (0 != winRegInfo.remapHighRegOffs)
+ {
+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh);
+ }
+
+
+ if (pAddrWin->enable == MV_TRUE)
+ {
+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
+ }
+ else
+ {
+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPexTargetWinRemapEnable -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+
+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum,
+ MV_BOOL enable)
+{
+ PEX_WIN_REG_INFO winRegInfo;
+
+ /* Parameter checking */
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n",
+ pexIf);
+ return MV_BAD_PARAM;
+ }
+ if (MV_PEX_WIN_DEFAULT == winNum)
+ {
+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n",
+ winNum);
+ return MV_BAD_PARAM;
+
+ }
+
+
+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo);
+
+ if (enable == MV_TRUE)
+ {
+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
+ }
+ else
+ {
+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN);
+ }
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvPexBarSet - Set PEX bar address and size
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexBarSet(MV_U32 pexIf,
+ MV_U32 barNum,
+ MV_PEX_BAR *pAddrWin)
+{
+ MV_U32 regBaseLow;
+ MV_U32 regSize,sizeToReg;
+
+
+ /* check parameters */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ if(barNum >= PEX_MAX_BARS)
+ {
+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum);
+ return MV_BAD_PARAM;
+ }
+
+
+ if (pAddrWin->addrWin.size == 0)
+ {
+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" );
+ return MV_BAD_PARAM;
+ }
+
+
+ /* Check if the window complies with PEX spec */
+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow,
+ pAddrWin->addrWin.size))
+ {
+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* 2) Check if the requested bar overlaps with current bars */
+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin))
+ {
+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Get size register value according to window size */
+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT);
+
+ /* Read bar size */
+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */
+ {
+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum));
+
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum);
+ return MV_BAD_PARAM;
+ }
+
+ regSize &= ~PXBCR_BAR_SIZE_MASK;
+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ;
+
+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize);
+
+ }
+
+ /* set size */
+
+
+
+ /* Read base address low */
+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,
+ PEX_MV_BAR_BASE(barNum)));
+
+ /* clear current base */
+ if (PEX_INTER_REGS_BAR == barNum)
+ {
+ regBaseLow &= ~PXBIR_BASE_MASK;
+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK);
+ }
+ else
+ {
+ regBaseLow &= ~PXBR_BASE_MASK;
+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK);
+ }
+
+ /* if we had a previous value that contain the bar type (MeM\IO), we want to
+ restore it */
+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB;
+
+
+
+ /* write base low */
+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)),
+ regBaseLow);
+
+ if (pAddrWin->addrWin.baseHigh != 0)
+ {
+ /* Read base address high */
+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)),
+ pAddrWin->addrWin.baseHigh);
+
+ }
+
+ /* lastly enable the Bar */
+ if (pAddrWin->enable == MV_TRUE)
+ {
+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers
+ are enabled always */
+ {
+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN);
+ }
+ }
+ else if (MV_FALSE == pAddrWin->enable)
+ {
+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers
+ are enabled always */
+ {
+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN);
+ }
+
+ }
+
+
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPexBarGet - Get PEX bar address and size
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+
+MV_STATUS mvPexBarGet(MV_U32 pexIf,
+ MV_U32 barNum,
+ MV_PEX_BAR *pAddrWin)
+{
+ /* check parameters */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ if(barNum >= PEX_MAX_BARS)
+ {
+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* read base low */
+ pAddrWin->addrWin.baseLow =
+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)));
+
+
+ if (PEX_INTER_REGS_BAR == barNum)
+ {
+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK;
+ }
+ else
+ {
+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK;
+ }
+
+
+ /* read base high */
+ pAddrWin->addrWin.baseHigh =
+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)));
+
+
+ /* Read bar size */
+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */
+ {
+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum));
+
+ /* check if enable or not */
+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN)
+ {
+ pAddrWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrWin->enable = MV_FALSE;
+ }
+
+ /* now get the size */
+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK;
+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS;
+
+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size,
+ PXBCR_BAR_SIZE_ALIGNMENT);
+
+ }
+ else /* PEX_INTER_REGS_BAR */
+ {
+ pAddrWin->addrWin.size = INTER_REGS_SIZE;
+ pAddrWin->enable = MV_TRUE;
+ }
+
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPexBarEnable -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+
+
+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable)
+{
+
+ MV_PEX_BAR pexBar;
+
+ /* check parameters */
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+
+ if(barNum >= PEX_MAX_BARS)
+ {
+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum);
+ return MV_BAD_PARAM;
+ }
+
+ if (PEX_INTER_REGS_BAR == barNum)
+ {
+ if (MV_TRUE == enable)
+ {
+ return MV_OK;
+ }
+ else
+ {
+ return MV_ERROR;
+ }
+ }
+
+
+ if (MV_FALSE == enable)
+ {
+ /* disable bar and quit */
+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN);
+ return MV_OK;
+ }
+
+ /* else */
+
+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK)
+ {
+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n");
+ return MV_ERROR;
+
+ }
+
+ if (MV_TRUE == pexBar.enable)
+ {
+ /* it is already enabled !!! */
+ return MV_OK;
+ }
+
+ /* else enable the bar*/
+
+ pexBar.enable = MV_TRUE;
+
+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK)
+ {
+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n");
+ return MV_ERROR;
+
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* pexWinOverlapDetect - Detect address windows overlapping
+*
+* DESCRIPTION:
+* This function detects address window overlapping of a given address
+* window in PEX BARs.
+*
+* INPUT:
+* pAddrWin - Address window to be checked.
+* bar - BAR to be accessed by slave.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf,
+ MV_U32 winNum,
+ MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 win;
+ MV_PEX_DEC_WIN addrDecWin;
+
+
+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++)
+ {
+ /* don't check our target or illegal targets */
+ if (winNum == win)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin))
+ {
+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n",
+ win);
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ continue;
+ }
+
+
+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin))
+ {
+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n",
+ winNum, win);
+ return MV_TRUE;
+ }
+ }
+
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* pexIsWinWithinBar - Detect if address is within PEX bar boundries
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf,
+ MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 bar;
+ MV_PEX_BAR addrDecWin;
+
+ for(bar = 0; bar < PEX_MAX_BARS; bar++)
+ {
+
+ /* Get window parameters */
+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin))
+ {
+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n");
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled bars */
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ continue;
+ }
+
+
+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin))
+ {
+ return MV_TRUE;
+ }
+ }
+
+ return MV_FALSE;
+
+}
+
+/*******************************************************************************
+* pexBarOverlapDetect - Detect address windows overlapping
+*
+* DESCRIPTION:
+* This function detects address window overlapping of a given address
+* window in PEX BARs.
+*
+* INPUT:
+* pAddrWin - Address window to be checked.
+* bar - BAR to be accessed by slave.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf,
+ MV_U32 barNum,
+ MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 bar;
+ MV_PEX_BAR barDecWin;
+
+
+ for(bar = 0; bar < PEX_MAX_BARS; bar++)
+ {
+ /* don't check our target or illegal targets */
+ if (barNum == bar)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin))
+ {
+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ /* don'nt check disabled bars */
+ if (barDecWin.enable == MV_FALSE)
+ {
+ continue;
+ }
+
+
+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin))
+ {
+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n",
+ barNum, bar);
+ return MV_TRUE;
+ }
+ }
+
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* pexBarIsValid - Check if the given address window is valid
+*
+* DESCRIPTION:
+* PEX spec restrict BAR base to be aligned to BAR size.
+* This function checks if the given address window is valid.
+*
+* INPUT:
+* baseLow - 32bit low base address.
+* size - Window size.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the address window is valid, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size)
+{
+
+ /* PCI spec restrict BAR base to be aligned to BAR size */
+ if(MV_IS_NOT_ALIGN(baseLow, size))
+ {
+ return MV_ERROR;
+ }
+ else
+ {
+ return MV_TRUE;
+ }
+
+ return MV_TRUE;
+}
+
+/*******************************************************************************
+* pexBarRegInfoGet - Get BAR register information
+*
+* DESCRIPTION:
+* PEX BARs registers offsets are inconsecutive.
+* This function gets a PEX BAR register information like register offsets
+* and function location of the BAR.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* bar - The PEX BAR in question.
+*
+* OUTPUT:
+* pBarRegInfo - BAR register info struct.
+*
+* RETURN:
+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK
+*
+*******************************************************************************/
+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf,
+ MV_U32 winNum,
+ PEX_WIN_REG_INFO *pWinRegInfo)
+{
+
+ if ((winNum >= 0)&&(winNum <=3))
+ {
+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum);
+ pWinRegInfo->baseHighRegOffs = 0;
+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum);
+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum);
+ pWinRegInfo->remapHighRegOffs = 0;
+ }
+ else if ((winNum >= 4)&&(winNum <=5))
+ {
+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum);
+ pWinRegInfo->baseHighRegOffs = 0;
+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum);
+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum);
+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum);
+
+ }
+ else if (MV_PEX_WIN_DEFAULT == winNum)
+ {
+ pWinRegInfo->baseLowRegOffs = 0;
+ pWinRegInfo->baseHighRegOffs = 0;
+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf);
+ pWinRegInfo->remapLowRegOffs = 0;
+ pWinRegInfo->remapHighRegOffs = 0;
+ }
+ else if (MV_PEX_WIN_EXP_ROM == winNum)
+ {
+ pWinRegInfo->baseLowRegOffs = 0;
+ pWinRegInfo->baseHighRegOffs = 0;
+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf);
+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf);
+ pWinRegInfo->remapHighRegOffs = 0;
+
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* pexBarNameGet - Get the string name of PEX BAR.
+*
+* DESCRIPTION:
+* This function get the string name of PEX BAR.
+*
+* INPUT:
+* bar - PEX bar number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* pointer to the string name of PEX BAR.
+*
+*******************************************************************************/
+const MV_8* pexBarNameGet( MV_U32 bar )
+{
+ switch( bar )
+ {
+ case PEX_INTER_REGS_BAR:
+ return "Internal Regs Bar0....";
+ case PEX_DRAM_BAR:
+ return "DRAM Bar1.............";
+ case PEX_DEVICE_BAR:
+ return "Devices Bar2..........";
+ default:
+ return "Bar unknown";
+ }
+}
+/*******************************************************************************
+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows).
+*
+* DESCRIPTION:
+* This function print the PEX address decode map (BARs and windows).
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvPexAddrDecShow(MV_VOID)
+{
+ MV_PEX_BAR pexBar;
+ MV_PEX_DEC_WIN win;
+ MV_U32 pexIf;
+ MV_U32 bar,winNum;
+
+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ )
+ {
+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue;
+ mvOsOutput( "\n" );
+ mvOsOutput( "PEX%d:\n", pexIf );
+ mvOsOutput( "-----\n" );
+
+ mvOsOutput( "\nPex Bars \n\n");
+
+ for( bar = 0; bar < PEX_MAX_BARS; bar++ )
+ {
+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) );
+
+ mvOsOutput( "%s ", pexBarNameGet(bar) );
+
+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK )
+ {
+ if( pexBar.enable )
+ {
+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow );
+ mvSizePrint( pexBar.addrWin.size );
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+ mvOsOutput( "\nPex Decode Windows\n\n");
+
+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++)
+ {
+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", winNum );
+
+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK)
+ {
+ if (win.enable)
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+ mvOsOutput( "...." );
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+
+
+ }
+ }
+
+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) );
+
+ mvOsOutput( "default win - " );
+
+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK)
+ {
+ mvOsOutput( "%s ",
+ mvCtrlTargetNameGet(win.target) );
+ mvOsOutput( "\n" );
+ }
+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) );
+
+ mvOsOutput( "Expansion ROM - " );
+
+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK)
+ {
+ mvOsOutput( "%s ",
+ mvCtrlTargetNameGet(win.target) );
+ mvOsOutput( "\n" );
+ }
+
+ }
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h
new file mode 100644
index 000000000..3505613b7
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h
@@ -0,0 +1,348 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCSysPEXH
+#define __INCSysPEXH
+
+#include "mvCommon.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+/* 4KB granularity */
+#define MINIMUM_WINDOW_SIZE 0x1000
+#define MINIMUM_BAR_SIZE 0x1000
+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000
+#define BAR_SIZE_OFFS 12
+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS)
+
+
+
+#define MV_PEX_WIN_DEFAULT 6
+#define MV_PEX_WIN_EXP_ROM 7
+#define PEX_MAX_TARGET_WIN 8
+
+
+#define PEX_MAX_BARS 3
+#define PEX_INTER_REGS_BAR 0
+#define PEX_DRAM_BAR 1
+#define PEX_DEVICE_BAR 2
+
+/*************************************/
+/* PCI Express BAR Control Registers */
+/*************************************/
+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000)
+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000)
+
+
+/* PCI Express BAR Control Register */
+/* PEX_BAR_CTRL_REG (PXBCR) */
+
+#define PXBCR_BAR_EN BIT0
+#define PXBCR_BAR_SIZE_OFFS 16
+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS)
+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000
+
+
+
+/* PCI Express Expansion ROM BAR Control Register */
+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */
+
+#define PXERBCR_EXPROM_EN BIT0
+#define PXERBCR_EXPROMSZ_OFFS 19
+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS)
+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS)
+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS)
+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS)
+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS)
+
+/************************************************/
+/* PCI Express Address Window Control Registers */
+/************************************************/
+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \
+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000)
+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \
+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000)
+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \
+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000)
+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \
+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \
+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \
+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \
+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000)
+
+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000)
+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000)
+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000)
+
+/* PCI Express Window Control Register */
+/* PEX_WIN_CTRL_REG (PXWCR) */
+
+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/
+
+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/
+#define PXWCR_WIN_BAR_MAP_MASK BIT1
+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS)
+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS)
+
+#define PXWCR_TARGET_OFFS 4 /*Unit ID */
+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS)
+
+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */
+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS)
+
+#define PXWCR_SIZE_OFFS 16 /* size */
+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS)
+#define PXWCR_SIZE_ALIGNMENT 0x10000
+
+/* PCI Express Window Base Register */
+/* PEX_WIN_BASE_REG (PXWBR)*/
+
+#define PXWBR_BASE_OFFS 16 /* address[31:16] */
+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS)
+#define PXWBR_BASE_ALIGNMENT 0x10000
+
+/* PCI Express Window Remap Register */
+/* PEX_WIN_REMAP_REG (PXWRR)*/
+
+#define PXWRR_REMAP_EN BIT0
+#define PXWRR_REMAP_OFFS 16
+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS)
+#define PXWRR_REMAP_ALIGNMENT 0x10000
+
+/* PCI Express Window Remap (High) Register */
+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/
+
+#define PXWRHR_REMAP_HIGH_OFFS 0
+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS)
+
+/* PCI Express Default Window Control Register */
+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */
+
+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */
+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS)
+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */
+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS)
+
+/* PCI Express Expansion ROM Window Control Register */
+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/
+
+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */
+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS)
+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */
+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS)
+
+/* PCI Express Expansion ROM Window Remap Register */
+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/
+
+#define PXWERRR_REMAP_EN BIT0
+#define PXWERRR_REMAP_OFFS 16
+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS)
+#define PXWERRR_REMAP_ALIGNMENT 0x10000
+
+
+
+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/
+/* PCI Express BAR0 Internal Register*/
+/*PEX BAR0_INTER_REG (PXBIR)*/
+
+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */
+
+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */
+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS)
+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS)
+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS)
+
+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */
+
+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */
+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS)
+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS)
+
+
+/* PCI Express BAR0 Internal (High) Register*/
+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/
+
+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */
+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS)
+
+
+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */
+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB
+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB
+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB
+
+
+/* PCI Express BAR1 Register */
+/* PCI Express BAR2 Register*/
+/*PEX BAR1_REG (PXBR)*/
+/*PEX BAR2_REG (PXBR)*/
+
+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */
+
+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */
+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS)
+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS)
+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS)
+
+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */
+
+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */
+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS)
+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS)
+
+
+/* PCI Express BAR1 (High) Register*/
+/* PCI Express BAR2 (High) Register*/
+/*PEX BAR1_REG_HIGH (PXBRH)*/
+/*PEX BAR2_REG_HIGH (PXBRH)*/
+
+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */
+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS)
+
+/* PCI Express Expansion ROM BAR Register*/
+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/
+
+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */
+
+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */
+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS)
+
+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */
+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS)
+
+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */
+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS)
+
+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */
+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS)
+
+/* PEX Bar attributes */
+typedef struct _mvPexBar
+{
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_PEX_BAR;
+
+/* PEX Remap Window attributes */
+typedef struct _mvPexRemapWin
+{
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_PEX_REMAP_WIN;
+
+/* PEX Remap Window attributes */
+typedef struct _mvPexDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_U32 targetBar;
+ MV_U8 attrib; /* chip select attributes */
+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_PEX_DEC_WIN;
+
+/* Global Functions prototypes */
+/* mvPexHalInit - Initialize PEX interfaces*/
+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType);
+
+
+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/
+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum,
+ MV_PEX_DEC_WIN *pAddrDecWin);
+
+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/
+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum,
+ MV_PEX_DEC_WIN *pAddrDecWin);
+
+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/
+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable);
+
+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/
+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum,
+ MV_PEX_REMAP_WIN *pAddrWin);
+
+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/
+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum,
+ MV_BOOL enable);
+
+/* mvPexBarSet - Set PEX bar address and size */
+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin);
+
+/* mvPexBarGet - Get PEX bar address and size */
+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin);
+
+/* mvPexBarEnable - enable\disable a PEX bar*/
+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable);
+
+/* mvPexAddrDecShow - Display address decode windows attributes */
+MV_VOID mvPexAddrDecShow(MV_VOID);
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c
new file mode 100644
index 000000000..f100a12d1
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c
@@ -0,0 +1,430 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include "mvTypes.h"
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "cpu/mvCpu.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "sata/CoreDriver/mvRegs.h"
+#include "ctrlEnv/sys/mvSysSata.h"
+
+MV_TARGET sataAddrDecPrioTab[] =
+{
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_MEM,
+#endif
+ TBL_TERM
+};
+
+
+/*******************************************************************************
+* sataWinOverlapDetect - Detect SATA address windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviur is expected in case SATA address decode
+* windows overlapps.
+* This function detects SATA address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum,
+ MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 winNumIndex;
+ MV_SATA_DEC_WIN addrDecWin;
+
+ for(winNumIndex=0; winNumIndex<MV_SATA_MAX_ADDR_DECODE_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvSataWinGet(dev, winNumIndex, &addrDecWin))
+ {
+ mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if(addrDecWin.enable == MV_FALSE)
+ {
+ continue;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ return MV_FALSE;
+}
+
+
+/*******************************************************************************
+* mvSataWinSet - Set SATA target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the SATA will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - SATA target address decode window number.
+* pAddrDecWin - SATA target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if address window overlapps with other address decode windows.
+* MV_BAD_PARAM if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+MV_STATUS mvSataWinSet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+
+ /* Parameter checking */
+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ decRegs.baseReg = 0;
+ decRegs.sizeReg = 0;
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
+
+ /* set attributes */
+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK;
+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET);
+
+ /* set target ID */
+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK;
+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET);
+
+ if (pAddrDecWin->enable == MV_TRUE)
+ {
+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK;
+ }
+ else
+ {
+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK;
+ }
+
+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg);
+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSataWinGet - Get SATA peripheral target address window.
+*
+* DESCRIPTION:
+* Get SATA peripheral target address window.
+*
+* INPUT:
+* winNum - SATA target address decode window number.
+*
+* OUTPUT:
+* pAddrDecWin - SATA target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+ /* Parameter checking */
+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
+ __FUNCTION__, dev, winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) );
+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) );
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
+ {
+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >>
+ MV_SATA_WIN_ATTR_OFFSET;
+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >>
+ MV_SATA_WIN_TARGET_OFFSET;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ /* Check if window is enabled */
+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+ return MV_OK;
+}
+/*******************************************************************************
+* mvSataAddrDecShow - Print the SATA address decode map.
+*
+* DESCRIPTION:
+* This function print the SATA address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvSataAddrDecShow(MV_VOID)
+{
+
+ MV_SATA_DEC_WIN win;
+ int i,j;
+
+
+
+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ )
+ {
+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j))
+ return;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "SATA %d:\n", j );
+ mvOsOutput( "----\n" );
+
+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ )
+ {
+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", i );
+
+ if( mvSataWinGet(j, i, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+ mvOsOutput( "...." );
+
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+ }
+}
+
+
+/*******************************************************************************
+* mvSataWinInit - Initialize the integrated SATA target address window.
+*
+* DESCRIPTION:
+* Initialize the SATA peripheral target address window.
+*
+* INPUT:
+*
+*
+* OUTPUT:
+*
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvSataWinInit(MV_VOID)
+{
+ int winNum;
+ MV_SATA_DEC_WIN sataWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ MV_U32 status, winPrioIndex = 0;
+
+ /* Initiate Sata address decode */
+
+ /* First disable all address decode windows */
+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++)
+ {
+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum));
+ regVal &= ~MV_SATA_WIN_ENABLE_MASK;
+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal);
+ }
+
+ winNum = 0;
+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) )
+ {
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex],
+ &cpuAddrDecWin);
+
+ if(MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if (MV_OK != status)
+ {
+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ sataWin.enable = MV_TRUE;
+ sataWin.target = sataAddrDecPrioTab[winPrioIndex];
+
+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin))
+ {
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex++;
+ }
+ return MV_OK;
+}
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h
new file mode 100644
index 000000000..325fb8d06
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h
@@ -0,0 +1,128 @@
+
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __INCMVSysSataAddrDech
+#define __INCMVSysSataAddrDech
+
+#include "mvCommon.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct _mvSataDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+} MV_SATA_DEC_WIN;
+
+
+#define MV_SATA_MAX_ADDR_DECODE_WIN 4
+
+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4))
+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4))
+
+/* BITs in Bridge Interrupt Cause and Mask registers */
+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0
+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<<MV_SATA_ADDR_DECODE_ERROR_BIT)
+
+/* BITs in Windows 0-3 Control and Base Registers */
+#define MV_SATA_WIN_ENABLE_BIT 0
+#define MV_SATA_WIN_ENABLE_MASK (1<<MV_SATA_WIN_ENABLE_BIT)
+
+#define MV_SATA_WIN_TARGET_OFFSET 4
+#define MV_SATA_WIN_TARGET_MASK (0xF<<MV_SATA_WIN_TARGET_OFFSET)
+
+#define MV_SATA_WIN_ATTR_OFFSET 8
+#define MV_SATA_WIN_ATTR_MASK (0xFF<<MV_SATA_WIN_ATTR_OFFSET)
+
+#define MV_SATA_WIN_SIZE_OFFSET 16
+#define MV_SATA_WIN_SIZE_MASK (0xFFFF<<MV_SATA_WIN_SIZE_OFFSET)
+
+#define MV_SATA_WIN_BASE_OFFSET 16
+#define MV_SATA_WIN_BASE_MASK (0xFFFF<<MV_SATA_WIN_BASE_OFFSET)
+
+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);
+MV_STATUS mvSataWinSet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);
+MV_STATUS mvSataWinByTargetGet(MV_TARGET target, MV_SATA_DEC_WIN *pAddrDecWin);
+MV_STATUS mvSataWinInit(MV_VOID);
+MV_VOID mvSataAddrDecShow(MV_VOID);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
+
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c
new file mode 100644
index 000000000..6d2a91924
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c
@@ -0,0 +1,427 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include "mvTypes.h"
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "cpu/mvCpu.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "mvRegs.h"
+#include "ctrlEnv/sys/mvSysSdmmc.h"
+
+MV_TARGET sdmmcAddrDecPrioTab[] =
+{
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_MEM,
+#endif
+ TBL_TERM
+};
+
+
+/*******************************************************************************
+* sdmmcWinOverlapDetect - Detect SDMMC address windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviur is expected in case SDMMC address decode
+* windows overlapps.
+* This function detects SDMMC address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS sdmmcWinOverlapDetect(int dev, MV_U32 winNum,
+ MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 winNumIndex;
+ MV_SDMMC_DEC_WIN addrDecWin;
+
+ for(winNumIndex=0; winNumIndex<MV_SDMMC_MAX_ADDR_DECODE_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvSdmmcWinGet(dev, winNumIndex, &addrDecWin))
+ {
+ mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if(addrDecWin.enable == MV_FALSE)
+ {
+ continue;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ return MV_FALSE;
+}
+
+
+/*******************************************************************************
+* mvSdmmcWinSet - Set SDMMC target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the SDMMC will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - SDMMC target address decode window number.
+* pAddrDecWin - SDMMC target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if address window overlapps with other address decode windows.
+* MV_BAD_PARAM if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+MV_STATUS mvSdmmcWinSet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+
+ /* Parameter checking */
+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ decRegs.baseReg = 0;
+ decRegs.sizeReg = 0;
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
+
+ /* set attributes */
+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK;
+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET);
+
+ /* set target ID */
+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK;
+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET);
+
+ if (pAddrDecWin->enable == MV_TRUE)
+ {
+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK;
+ }
+ else
+ {
+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK;
+ }
+
+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg);
+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSdmmcWinGet - Get SDMMC peripheral target address window.
+*
+* DESCRIPTION:
+* Get SDMMC peripheral target address window.
+*
+* INPUT:
+* winNum - SDMMC target address decode window number.
+*d
+* OUTPUT:
+* pAddrDecWin - SDMMC target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+ /* Parameter checking */
+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
+ __FUNCTION__, dev, winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) );
+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) );
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) )
+ {
+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >>
+ MV_SDMMC_WIN_ATTR_OFFSET;
+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >>
+ MV_SDMMC_WIN_TARGET_OFFSET;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ /* Check if window is enabled */
+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+ return MV_OK;
+}
+/*******************************************************************************
+* mvSdmmcAddrDecShow - Print the SDMMC address decode map.
+*
+* DESCRIPTION:
+* This function print the SDMMC address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvSdmmcAddrDecShow(MV_VOID)
+{
+
+ MV_SDMMC_DEC_WIN win;
+ int i,j=0;
+
+
+
+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0))
+ return;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "SDMMC %d:\n", j );
+ mvOsOutput( "----\n" );
+
+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ )
+ {
+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", i );
+
+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+ mvOsOutput( "...." );
+
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+}
+
+
+/*******************************************************************************
+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window.
+*
+* DESCRIPTION:
+* Initialize the SDMMC peripheral target address window.
+*
+* INPUT:
+*
+*
+* OUTPUT:
+*
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvSdmmcWinInit(MV_VOID)
+{
+ int winNum;
+ MV_SDMMC_DEC_WIN sdmmcWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ MV_U32 status, winPrioIndex = 0;
+
+ /* Initiate Sdmmc address decode */
+
+ /* First disable all address decode windows */
+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++)
+ {
+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum));
+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK;
+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal);
+ }
+
+ winNum = 0;
+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) )
+ {
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex],
+ &cpuAddrDecWin);
+
+ if(MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if (MV_OK != status)
+ {
+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ sdmmcWin.enable = MV_TRUE;
+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex];
+
+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin))
+ {
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex++;
+ }
+ return MV_OK;
+}
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h
new file mode 100644
index 000000000..4c50a2b69
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h
@@ -0,0 +1,125 @@
+
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __INCMVSysSdmmcAddrDech
+#define __INCMVSysSdmmcAddrDech
+
+#include "mvCommon.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct _mvSdmmcDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+} MV_SDMMC_DEC_WIN;
+
+
+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4
+
+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3))
+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3))
+
+
+/* BITs in Windows 0-3 Control and Base Registers */
+#define MV_SDMMC_WIN_ENABLE_BIT 0
+#define MV_SDMMC_WIN_ENABLE_MASK (1<<MV_SDMMC_WIN_ENABLE_BIT)
+
+#define MV_SDMMC_WIN_TARGET_OFFSET 4
+#define MV_SDMMC_WIN_TARGET_MASK (0xF<<MV_SDMMC_WIN_TARGET_OFFSET)
+
+#define MV_SDMMC_WIN_ATTR_OFFSET 8
+#define MV_SDMMC_WIN_ATTR_MASK (0xFF<<MV_SDMMC_WIN_ATTR_OFFSET)
+
+#define MV_SDMMC_WIN_SIZE_OFFSET 16
+#define MV_SDMMC_WIN_SIZE_MASK (0xFFFF<<MV_SDMMC_WIN_SIZE_OFFSET)
+
+#define MV_SDMMC_WIN_BASE_OFFSET 16
+#define MV_SDMMC_WIN_BASE_MASK (0xFFFF<<MV_SDMMC_WIN_BASE_OFFSET)
+
+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);
+MV_STATUS mvSdmmcWinSet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);
+MV_STATUS mvSdmmcWinByTargetGet(MV_TARGET target, MV_SDMMC_DEC_WIN *pAddrDecWin);
+MV_STATUS mvSdmmcWinInit(MV_VOID);
+MV_VOID mvSdmmcAddrDecShow(MV_VOID);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
+
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c
new file mode 100644
index 000000000..ecf6944b8
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c
@@ -0,0 +1,462 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "mvSysTdm.h"
+
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+static MV_TARGET tdmAddrDecPrioTap[] =
+{
+ PEX0_MEM,
+ SDRAM_CS0,
+ SDRAM_CS1,
+ SDRAM_CS2,
+ SDRAM_CS3,
+ DEVICE_CS0,
+ DEVICE_CS1,
+ DEVICE_CS2,
+ DEV_BOOCS,
+ PEX0_IO,
+ TBL_TERM
+};
+
+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
+
+/*******************************************************************************
+* mvTdmWinInit - Initialize TDM address decode windows
+*
+* DESCRIPTION:
+* This function initialize TDM window decode unit. It set the
+* default address decode
+* windows of the unit.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if setting fail.
+*******************************************************************************/
+
+MV_STATUS mvTdmWinInit(void)
+{
+ MV_U32 winNum;
+ MV_U32 winPrioIndex = 0;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ MV_TDM_DEC_WIN tdmWin;
+ MV_STATUS status;
+
+ /*Disable all windows*/
+ for (winNum = 0; winNum < TDM_MBUS_MAX_WIN; winNum++)
+ {
+ mvTdmWinEnable(winNum, MV_FALSE);
+ }
+
+ for (winNum = 0; ((tdmAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
+ (winNum < TDM_MBUS_MAX_WIN)); )
+ {
+ status = mvCpuIfTargetWinGet(tdmAddrDecPrioTap[winPrioIndex],
+ &cpuAddrDecWin);
+ if (MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if (MV_OK != status)
+ {
+ mvOsPrintf("mvTdmInit: ERR. mvCpuIfTargetWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ tdmWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ tdmWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ tdmWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ tdmWin.enable = MV_TRUE;
+ tdmWin.target = tdmAddrDecPrioTap[winPrioIndex];
+ if (MV_OK != mvTdmWinSet(winNum, &tdmWin))
+ {
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex++;
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvTdmWinSet - Set TDM target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the TDM will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - TDM to target address decode window number.
+* pAddrDecWin - TDM target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if address window overlapps with other address decode windows.
+* MV_BAD_PARAM if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+
+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+ MV_U32 ctrlReg = 0;
+
+ /* Parameter checking */
+ if (winNum >= TDM_MBUS_MAX_WIN)
+ {
+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));
+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;
+
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n");
+ return MV_ERROR;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
+
+ /* for the safe side we disable the window before writing the new
+ values */
+ mvTdmWinEnable(winNum, MV_FALSE);
+
+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS);
+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS);
+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK);
+
+ /* Write to address base and control registers */
+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg);
+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg);
+ /* Enable address decode target window */
+ if (pAddrDecWin->enable == MV_TRUE)
+ {
+ mvTdmWinEnable(winNum, MV_TRUE);
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvTdmWinGet - Get peripheral target address window.
+*
+* DESCRIPTION:
+* Get TDM peripheral target address window.
+*
+* INPUT:
+* winNum - TDM to target address decode window number.
+*
+* OUTPUT:
+* pAddrDecWin - TDM target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+
+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)
+{
+
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+ /* Parameter checking */
+ if (winNum >= TDM_MBUS_MAX_WIN)
+ {
+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));
+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;
+
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
+ {
+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n");
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib =
+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS;
+ targetAttrib.targetId =
+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ /* Check if window is enabled */
+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvTdmWinEnable - Enable/disable a TDM to target address window
+*
+* DESCRIPTION:
+* This function enable/disable a TDM to target address window.
+* According to parameter 'enable' the routine will enable the
+* window, thus enabling TDM accesses (before enabling the window it is
+* tested for overlapping). Otherwise, the window will be disabled.
+*
+* INPUT:
+* winNum - TDM to target address decode window number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if decode window number was wrong or enabled window overlapps.
+*
+*******************************************************************************/
+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable)
+{
+ MV_TDM_DEC_WIN addrDecWin;
+
+ if (MV_TRUE == enable)
+ {
+ if (winNum >= TDM_MBUS_MAX_WIN)
+ {
+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum);
+ return MV_ERROR;
+ }
+
+ /* First check for overlap with other enabled windows */
+ /* Get current window */
+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin))
+ {
+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n");
+ return MV_ERROR;
+ }
+ /* Check for overlapping */
+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin)))
+ {
+ /* No Overlap. Enable address decode target window */
+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);
+ }
+ else
+ { /* Overlap detected */
+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n");
+ return MV_ERROR;
+ }
+ }
+ else
+ {
+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);
+ }
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* tdmWinOverlapDetect - Detect TDM address windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviour is expected in case TDM address decode
+* windows overlapps.
+* This function detects TDM address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 winNumIndex;
+ MV_TDM_DEC_WIN addrDecWin;
+
+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+ /* Do not check disabled windows */
+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)
+ {
+ /* Get window parameters */
+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin))
+ {
+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n"));
+ return MV_ERROR;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ }
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvTdmAddrDecShow - Print the TDM address decode map.
+*
+* DESCRIPTION:
+* This function print the TDM address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvTdmAddrDecShow(MV_VOID)
+{
+ MV_TDM_DEC_WIN win;
+ int i;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "TDM:\n" );
+ mvOsOutput( "----\n" );
+
+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ )
+ {
+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", i );
+
+ if (mvTdmWinGet(i, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow);
+ mvOsOutput( "...." );
+ mvSizePrint( win.addrWin.size );
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h
new file mode 100644
index 000000000..0d3140f5e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h
@@ -0,0 +1,106 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSysTdmh
+#define __INCmvSysTdmh
+
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+typedef struct _mvTdmDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+} MV_TDM_DEC_WIN;
+
+MV_STATUS mvTdmWinInit(MV_VOID);
+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin);
+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin);
+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable);
+MV_VOID mvTdmAddrDecShow(MV_VOID);
+
+
+#define TDM_MBUS_MAX_WIN 4
+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4))
+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4))
+
+/* TDM_WIN_CTRL_REG bits */
+#define TDM_WIN_ENABLE_OFFS 0
+#define TDM_WIN_ENABLE_MASK (1<<TDM_WIN_ENABLE_OFFS)
+#define TDM_WIN_ENABLE 1
+#define TDM_WIN_TARGET_OFFS 4
+#define TDM_WIN_TARGET_MASK (0xf<<TDM_WIN_TARGET_OFFS)
+#define TDM_WIN_ATTRIB_OFFS 8
+#define TDM_WIN_ATTRIB_MASK (0xff<<TDM_WIN_ATTRIB_OFFS)
+#define TDM_WIN_SIZE_OFFS 16
+#define TDM_WIN_SIZE_MASK (0xffff<<TDM_WIN_SIZE_OFFS)
+
+/* TDM_WIN_BASE_REG bits */
+#define TDM_BASE_OFFS 16
+#define TDM_BASE_MASK (0xffff<<TDM_BASE_OFFS)
+
+#endif /*__INCmvSysTdmh*/
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.c
new file mode 100644
index 000000000..4415c7c26
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.c
@@ -0,0 +1,591 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include "ctrlEnv/sys/mvSysTs.h"
+
+
+typedef struct _mvTsuDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_TSU_DEC_WIN;
+
+
+MV_TARGET tsuAddrDecPrioTap[] =
+{
+#if defined(MV_INCLUDE_PEX)
+ PEX0_MEM,
+#endif
+#if defined(MV_INCLUDE_PCI)
+ PCI0_MEM,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS0)
+ DEVICE_CS0,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS1)
+ DEVICE_CS1,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS2)
+ DEVICE_CS2,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS3)
+ DEVICE_CS3,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_IO,
+#endif
+#if defined(MV_INCLUDE_PCI)
+ PCI0_IO,
+#endif
+ TBL_TERM
+};
+
+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
+static MV_STATUS mvTsuWinSet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin);
+static MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin);
+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable);
+
+/*******************************************************************************
+* mvTsuWinInit
+*
+* DESCRIPTION:
+* Initialize the TSU unit address decode windows.
+*
+* INPUT:
+* None.
+* OUTPUT:
+* None.
+* RETURN:
+* MV_OK - on success,
+*
+*******************************************************************************/
+MV_STATUS mvTsuWinInit(void)
+{
+ MV_U32 winNum, status, winPrioIndex=0;
+ MV_TSU_DEC_WIN tsuWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+
+ /* First disable all address decode windows */
+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++)
+ {
+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum),
+ TSU_WIN_CTRL_EN_MASK);
+ }
+
+ /* Go through all windows in user table until table terminator */
+ for(winNum = 0; ((tsuAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
+ (winNum < TSU_MAX_DECODE_WIN));)
+ {
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(tsuAddrDecPrioTap[winPrioIndex],
+ &cpuAddrDecWin);
+
+ if(MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if(MV_OK != status)
+ {
+ mvOsPrintf("mvTsuWinInit: ERR. mvCpuIfTargetWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ tsuWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ tsuWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ tsuWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ tsuWin.enable = MV_TRUE;
+ tsuWin.target = tsuAddrDecPrioTap[winPrioIndex];
+
+ if(MV_OK != mvTsuWinSet(winNum, &tsuWin))
+ {
+ mvOsPrintf("mvTsuWinInit: ERR. mvTsuWinSet failed winNum=%d\n",
+ winNum);
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex ++;
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvTsuWinSet
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the TSU will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - TSU to target address decode window number.
+* pAddrDecWin - TSU target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR - if address window overlapps with other address decode
+* windows.
+* MV_BAD_PARAM - if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+MV_STATUS mvTsuWinSet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin)
+{
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_DEC_REGS decRegs;
+
+ /* Parameter checking */
+ if(winNum >= TSU_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target "
+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target),
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum));
+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum));
+
+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
+ {
+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n");
+ return MV_ERROR;
+ }
+
+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
+
+ /* set attributes */
+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK;
+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS;
+ /* set target ID */
+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK;
+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS;
+
+ /* for the safe side we disable the window before writing the new */
+ /* values */
+ mvTsuWinEnable(winNum, MV_FALSE);
+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg);
+
+ /* Write to address decode Size Register */
+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg);
+
+ /* Enable address decode target window */
+ if(pAddrDecWin->enable == MV_TRUE)
+ {
+ mvTsuWinEnable(winNum,MV_TRUE);
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvTsuWinGet
+*
+* DESCRIPTION:
+* Get TSU peripheral target address window.
+*
+* INPUT:
+* winNum - TSU to target address decode window number.
+*
+* OUTPUT:
+* pAddrDecWin - TSU target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS decRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+
+ /* Parameter checking */
+ if(winNum >= TSU_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum));
+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum));
+
+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
+ {
+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n");
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib =
+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS;
+ targetAttrib.targetId =
+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS;
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ /* Check if window is enabled */
+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK))
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvTsuWinEnable
+*
+* DESCRIPTION:
+* This function enable/disable a TSU to target address window.
+* According to parameter 'enable' the routine will enable the
+* window, thus enabling TSU accesses (before enabling the window it is
+* tested for overlapping). Otherwise, the window will be disabled.
+*
+* INPUT:
+* winNum - TSU to target address decode window number.
+* enable - Enable / disable parameter.
+*
+* OUTPUT:
+* N/A
+*
+* RETURN:
+* MV_ERROR if decode window number was wrong or enabled window overlapps.
+*
+*******************************************************************************/
+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable)
+{
+ MV_TSU_DEC_WIN addrDecWin;
+
+ /* Parameter checking */
+ if(winNum >= TSU_MAX_DECODE_WIN)
+ {
+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum);
+ return MV_ERROR;
+ }
+
+ if(enable == MV_TRUE)
+ {
+ /* First check for overlap with other enabled windows */
+ /* Get current window. */
+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin))
+ {
+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n");
+ return MV_ERROR;
+ }
+ /* Check for overlapping. */
+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin)))
+ {
+ /* No Overlap. Enable address decode target window */
+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum),
+ TSU_WIN_CTRL_EN_MASK);
+ }
+ else
+ {
+ /* Overlap detected */
+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n");
+ return MV_ERROR;
+ }
+ }
+ else
+ {
+ /* Disable address decode target window */
+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum),
+ TSU_WIN_CTRL_EN_MASK);
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvTsuWinTargetGet
+*
+* DESCRIPTION:
+* Get Window number associated with target
+*
+* INPUT:
+* target - Target ID to get the window number for.
+* OUTPUT:
+*
+* RETURN:
+* window number or 0xFFFFFFFF on error.
+*
+*******************************************************************************/
+MV_U32 mvTsuWinTargetGet(MV_TARGET target)
+{
+ MV_TSU_DEC_WIN decWin;
+ MV_U32 winNum;
+
+ /* Check parameters */
+ if(target >= MAX_TARGETS)
+ {
+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target);
+ return 0xffffffff;
+ }
+
+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++)
+ {
+ if(mvTsuWinGet(winNum,&decWin) != MV_OK)
+ {
+ mvOsPrintf("mvTsuWinGet: window returned error\n");
+ return 0xffffffff;
+ }
+
+ if (decWin.enable == MV_TRUE)
+ {
+ if(decWin.target == target)
+ {
+ return winNum;
+ }
+ }
+ }
+ return 0xFFFFFFFF;
+}
+
+
+/*******************************************************************************
+* tsuWinOverlapDetect
+*
+* DESCRIPTION:
+* Detect TSU address windows overlapping
+* An unpredicted behaviur is expected in case TSU address decode
+* windows overlapps.
+* This function detects TSU address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 ctrlReg;
+ MV_U32 winNumIndex;
+ MV_TSU_DEC_WIN addrDecWin;
+
+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if(winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Do not check disabled windows */
+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex));
+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin))
+ {
+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ return MV_FALSE;
+}
+
+
+/*******************************************************************************
+* mvTsuAddrDecShow
+*
+* DESCRIPTION:
+* Print the TSU address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void mvTsuAddrDecShow(void)
+{
+ MV_TSU_DEC_WIN win;
+ int i;
+
+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0))
+ return;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "TSU:\n");
+ mvOsOutput( "----\n" );
+
+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++)
+ {
+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN));
+ mvOsOutput( "win%d - ", i );
+
+ if(mvTsuWinGet(i, &win ) == MV_OK )
+ {
+ if(win.enable == MV_TRUE)
+ {
+ mvOsOutput("%s base %08x, ",
+ mvCtrlTargetNameGet(win.target),
+ win.addrWin.baseLow);
+ mvOsOutput( "...." );
+ mvSizePrint(win.addrWin.size );
+ mvOsOutput( "\n" );
+ }
+ else
+ {
+ mvOsOutput( "disable\n" );
+ }
+ }
+ }
+ return;
+}
+
+
+/*******************************************************************************
+* mvTsuInit
+*
+* DESCRIPTION:
+* Initialize the TSU unit, and get unit out of reset.
+*
+* INPUT:
+* coreClock - The core clock at which the TSU should operate.
+* mode - The mode on configure the unit into (serial/parallel).
+* memHandle - Memory handle used for memory allocations.
+* OUTPUT:
+* None.
+* RETURN:
+* MV_OK - on success,
+*
+*******************************************************************************/
+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode,
+ void *osHandle)
+{
+ MV_STATUS status;
+
+ status = mvTsuWinInit();
+ if(status == MV_OK)
+ status = mvTsuHalInit(coreClock,mode,osHandle);
+
+ return status;
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h
new file mode 100644
index 000000000..42825893c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h
@@ -0,0 +1,110 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSysTsh
+#define __INCmvSysTsh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* includes */
+#include "ts/mvTsu.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+#define TSU_MAX_DECODE_WIN 4
+
+
+/*******************************************/
+/* TSU Windows Registers */
+/*******************************************/
+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win)
+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win)
+
+/* TSU windows control register. */
+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0)
+#define TSU_WIN_CTRL_TARGET_OFFS 4
+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS)
+#define TSU_WIN_CTRL_ATTR_OFFS 8
+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS)
+#define TSU_WIN_CTRL_SIZE_OFFS 16
+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS)
+
+/* TSU windows base register. */
+#define TSU_WIN_BASE_OFFS 16
+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS)
+
+MV_STATUS mvTsuWinInit(void);
+
+void mvTsuAddrDecShow(void);
+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode,
+ void *osHandle);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvTsh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c
new file mode 100644
index 000000000..195b5e13e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c
@@ -0,0 +1,497 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ctrlEnv/sys/mvSysUsb.h"
+
+MV_TARGET usbAddrDecPrioTab[] =
+{
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA)
+ CRYPT_ENG,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_MEM,
+#endif
+ TBL_TERM
+};
+
+
+
+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost)
+{
+ MV_STATUS status;
+
+ status = mvUsbWinInit(dev);
+ if(status != MV_OK)
+ return status;
+
+ return mvUsbHalInit(dev, isHost);
+}
+
+
+/*******************************************************************************
+* usbWinOverlapDetect - Detect USB address windows overlapping
+*
+* DESCRIPTION:
+* An unpredicted behaviur is expected in case USB address decode
+* windows overlapps.
+* This function detects USB address decode windows overlapping of a
+* specified window. The function does not check the window itself for
+* overlapping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum,
+ MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 winNumIndex;
+ MV_DEC_WIN addrDecWin;
+
+ for(winNumIndex=0; winNumIndex<MV_USB_MAX_ADDR_DECODE_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvUsbWinGet(dev, winNumIndex, &addrDecWin))
+ {
+ mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if(addrDecWin.enable == MV_FALSE)
+ {
+ continue;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvUsbWinSet - Set USB target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window, also known as address decode window.
+* After setting this target window, the USB will be able to access the
+* target within the address window.
+*
+* INPUT:
+* winNum - USB target address decode window number.
+* pAddrDecWin - USB target window data structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR if address window overlapps with other address decode windows.
+* MV_BAD_PARAM if base address is invalid parameter or target is
+* unknown.
+*
+*******************************************************************************/
+MV_STATUS mvUsbWinSet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin)
+{
+ MV_DEC_WIN_PARAMS winParams;
+ MV_U32 sizeReg, baseReg;
+
+ /* Parameter checking */
+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlapps with current windows */
+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin))
+ {
+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum);
+ return MV_ERROR;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ winNum,
+ mvCtrlTargetNameGet(pDecWin->target),
+ pDecWin->addrWin.baseLow,
+ pDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams))
+ {
+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* set Size, Attributes and TargetID */
+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) |
+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) |
+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK));
+
+#if defined(MV645xx) || defined(MV646xx)
+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */
+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK;
+
+ if((MV_TARGET_IS_DRAM(pDecWin->target)) &&
+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY))
+ {
+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT;
+ }
+ else
+ {
+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT;
+ }
+#endif /* MV645xx || MV646xx */
+
+ if (pDecWin->enable == MV_TRUE)
+ {
+ sizeReg |= MV_USB_WIN_ENABLE_MASK;
+ }
+ else
+ {
+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK;
+ }
+
+ /* Update Base value */
+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK);
+
+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg);
+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvUsbWinGet - Get USB peripheral target address window.
+*
+* DESCRIPTION:
+* Get USB peripheral target address window.
+*
+* INPUT:
+* winNum - USB target address decode window number.
+*
+* OUTPUT:
+* pDecWin - USB target window data structure.
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin)
+{
+ MV_DEC_WIN_PARAMS winParam;
+ MV_U32 sizeReg, baseReg;
+
+ /* Parameter checking */
+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN)
+ {
+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n",
+ __FUNCTION__, dev, winNum);
+ return MV_NOT_SUPPORTED;
+ }
+
+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) );
+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) );
+
+ /* Check if window is enabled */
+ if(sizeReg & MV_USB_WIN_ENABLE_MASK)
+ {
+ pDecWin->enable = MV_TRUE;
+
+ /* Extract window parameters from registers */
+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET;
+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET;
+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET;
+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK);
+
+ /* Translate the decode window parameters to address decode struct */
+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin))
+ {
+ mvOsPrintf("Failed to translate register parameters to USB address" \
+ " decode window structure\n");
+ return MV_ERROR;
+ }
+ }
+ else
+ {
+ pDecWin->enable = MV_FALSE;
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvUsbWinInit -
+*
+* INPUT:
+*
+* OUTPUT:
+*
+* RETURN:
+* MV_ERROR if register parameters are invalid.
+*
+*******************************************************************************/
+MV_STATUS mvUsbWinInit(int dev)
+{
+ MV_STATUS status;
+ MV_DEC_WIN usbWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ int winNum;
+ MV_U32 winPrioIndex = 0;
+
+ /* First disable all address decode windows */
+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++)
+ {
+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK);
+ }
+
+ /* Go through all windows in user table until table terminator */
+ winNum = 0;
+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) &&
+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) )
+ {
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex],
+ &cpuAddrDecWin);
+
+ if(MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if (MV_OK != status)
+ {
+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ usbWin.enable = MV_TRUE;
+ usbWin.target = usbAddrDecPrioTab[winPrioIndex];
+
+#if defined(MV645xx) || defined(MV646xx)
+ /* Get the default attributes for that target window */
+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr);
+#endif /* MV645xx || MV646xx */
+
+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin))
+ {
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex++;
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvUsbAddrDecShow - Print the USB address decode map.
+*
+* DESCRIPTION:
+* This function print the USB address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvUsbAddrDecShow(MV_VOID)
+{
+ MV_DEC_WIN addrDecWin;
+ int i, winNum;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "USB:\n" );
+ mvOsOutput( "----\n" );
+
+ for(i=0; i<mvCtrlUsbMaxGet(); i++)
+ {
+ mvOsOutput( "Device %d:\n", i);
+
+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++)
+ {
+ memset(&addrDecWin, 0, sizeof(MV_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", winNum );
+
+ if( mvUsbWinGet(i, winNum, &addrDecWin ) == MV_OK )
+ {
+ if( addrDecWin.enable )
+ {
+ mvOsOutput( "%s base %08x, ",
+ mvCtrlTargetNameGet(addrDecWin.target), addrDecWin.addrWin.baseLow );
+
+ mvSizePrint( addrDecWin.addrWin.size );
+
+#if defined(MV645xx) || defined(MV646xx)
+ switch( addrDecWin.addrWinAttr.swapType)
+ {
+ case MV_BYTE_SWAP:
+ mvOsOutput( "BYTE_SWAP, " );
+ break;
+ case MV_NO_SWAP:
+ mvOsOutput( "NO_SWAP , " );
+ break;
+ case MV_BYTE_WORD_SWAP:
+ mvOsOutput( "BYTE_WORD_SWAP, " );
+ break;
+ case MV_WORD_SWAP:
+ mvOsOutput( "WORD_SWAP, " );
+ break;
+ default:
+ mvOsOutput( "SWAP N/A , " );
+ }
+
+ switch( addrDecWin.addrWinAttr.cachePolicy )
+ {
+ case NO_COHERENCY:
+ mvOsOutput( "NO_COHERENCY , " );
+ break;
+ case WT_COHERENCY:
+ mvOsOutput( "WT_COHERENCY , " );
+ break;
+ case WB_COHERENCY:
+ mvOsOutput( "WB_COHERENCY , " );
+ break;
+ default:
+ mvOsOutput( "COHERENCY N/A, " );
+ }
+
+ switch( addrDecWin.addrWinAttr.pcixNoSnoop )
+ {
+ case 0:
+ mvOsOutput( "PCI-X NS inactive, " );
+ break;
+ case 1:
+ mvOsOutput( "PCI-X NS active , " );
+ break;
+ default:
+ mvOsOutput( "PCI-X NS N/A , " );
+ }
+
+ switch( addrDecWin.addrWinAttr.p2pReq64 )
+ {
+ case 0:
+ mvOsOutput( "REQ64 force" );
+ break;
+ case 1:
+ mvOsOutput( "REQ64 detect" );
+ break;
+ default:
+ mvOsOutput( "REQ64 N/A" );
+ }
+#endif /* MV645xx || MV646xx */
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+ }
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.h
new file mode 100644
index 000000000..07f98de9c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.h
@@ -0,0 +1,125 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSysUsbh
+#define __INCmvSysUsbh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* includes */
+#include "usb/mvUsb.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+#define MV_USB_MAX_ADDR_DECODE_WIN 4
+
+/*******************************************/
+/* USB Bridge Registers */
+/*******************************************/
+#define MV_USB_BRIDGE_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x300)
+
+#define MV_USB_WIN_CTRL_REG(dev, win) (USB_REG_BASE(dev) + 0x320 + ((win)<<4))
+#define MV_USB_WIN_BASE_REG(dev, win) (USB_REG_BASE(dev) + 0x324 + ((win)<<4))
+
+/* BITs in Windows 0-3 Control and Base Registers */
+#define MV_USB_WIN_ENABLE_BIT 0
+#define MV_USB_WIN_ENABLE_MASK (1 << MV_USB_WIN_ENABLE_BIT)
+
+#define MV_USB_WIN_BURST_WR_LIMIT_BIT 1
+#define MV_USB_WIN_BURST_WR_LIMIT_MASK (1 << MV_USB_WIN_BURST_WR_LIMIT_BIT)
+#define MV_USB_WIN_BURST_WR_NO_LIMIT (0 << MV_USB_WIN_BURST_WR_LIMIT_BIT)
+#define MV_USB_WIN_BURST_WR_32BIT_LIMIT (1 << MV_USB_WIN_BURST_WR_LIMIT_BIT)
+
+#define MV_USB_WIN_TARGET_OFFSET 4
+#define MV_USB_WIN_TARGET_MASK (0xF << MV_USB_WIN_TARGET_OFFSET)
+
+#define MV_USB_WIN_ATTR_OFFSET 8
+#define MV_USB_WIN_ATTR_MASK (0xFF << MV_USB_WIN_ATTR_OFFSET)
+
+#define MV_USB_WIN_SIZE_OFFSET 16
+#define MV_USB_WIN_SIZE_MASK (0xFFFF << MV_USB_WIN_SIZE_OFFSET)
+
+#define MV_USB_WIN_BASE_OFFSET 16
+#define MV_USB_WIN_BASE_MASK (0xFFFF << MV_USB_WIN_BASE_OFFSET)
+
+
+#define MV_USB_BRIDGE_IPG_REG(dev) (USB_REG_BASE(dev) + 0x360)
+
+
+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost);
+
+MV_STATUS mvUsbWinInit(int dev);
+MV_STATUS mvUsbWinSet(int dev, MV_U32 winNum, MV_DEC_WIN *pAddrWin);
+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pAddrWin);
+
+void mvUsbAddrDecShow(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvUsbh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.c
new file mode 100644
index 000000000..f9d0ab37d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.c
@@ -0,0 +1,662 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "xor/mvXor.h"
+#include "mvSysXor.h"
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+
+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
+
+MV_TARGET xorAddrDecPrioTap[] =
+{
+#if defined(MV_INCLUDE_DEVICE_CS0)
+ DEVICE_CS0,
+#endif
+#if defined(MV_INCLUDE_PEX)
+ PEX0_MEM,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS0)
+ SDRAM_CS0,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ SDRAM_CS1,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS2)
+ SDRAM_CS2,
+#endif
+#if defined(MV_INCLUDE_SDRAM_CS3)
+ SDRAM_CS3,
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS1)
+ DEVICE_CS1,
+#endif
+#if defined(MV_INCLUDE_CESA)
+ CRYPT_ENG,
+#endif
+ TBL_TERM
+};
+static MV_STATUS mvXorInitWinsUnit (MV_U32 unit)
+{
+ MV_U32 winNum;
+ MV_XOR_DEC_WIN addrDecWin;
+ MV_CPU_DEC_WIN cpuAddrDecWin;
+ MV_U32 status;
+ MV_U32 winPrioIndex=0;
+
+ /* Initiate XOR address decode */
+
+ /* First disable all address decode windows */
+ for(winNum = 0; winNum < XOR_MAX_ADDR_DEC_WIN; winNum++)
+ {
+ mvXorTargetWinEnable(unit,winNum, MV_FALSE);
+ }
+
+ /* Go through all windows in user table until table terminator */
+ for (winNum = 0; ((xorAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
+ (winNum < XOR_MAX_ADDR_DEC_WIN));)
+ {
+ /* first get attributes from CPU If */
+ status = mvCpuIfTargetWinGet(xorAddrDecPrioTap[winPrioIndex],
+ &cpuAddrDecWin);
+
+ if(MV_NO_SUCH == status)
+ {
+ winPrioIndex++;
+ continue;
+ }
+ if (MV_OK != status)
+ {
+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+
+ if (cpuAddrDecWin.enable == MV_TRUE)
+ {
+
+ addrDecWin.target = xorAddrDecPrioTap[winPrioIndex];
+ addrDecWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
+ addrDecWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
+ addrDecWin.addrWin.size = cpuAddrDecWin.addrWin.size;
+ addrDecWin.enable = MV_TRUE;
+
+ if (MV_OK != mvXorTargetWinSet(unit,winNum, &addrDecWin))
+ {
+ DB(mvOsPrintf("mvXorInit: ERR. mvDmaTargetWinSet failed\n"));
+ return MV_ERROR;
+ }
+ winNum++;
+ }
+ winPrioIndex++;
+
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvXorInit - Initialize XOR engine
+*
+* DESCRIPTION:
+* This function initialize XOR unit. It set the default address decode
+* windows of the unit.
+* Note that if the address window is disabled in xorAddrDecMap, the
+* window parameters will be set but the window will remain disabled.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
+*******************************************************************************/
+MV_STATUS mvXorInit (MV_VOID)
+{
+ MV_U32 i;
+
+ /* Initiate XOR address decode */
+ for(i = 0; i < MV_XOR_MAX_UNIT; i++)
+ mvXorInitWinsUnit(i);
+
+ mvXorHalInit(MV_XOR_MAX_CHAN);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvXorTargetWinSet - Set XOR target address window
+*
+* DESCRIPTION:
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
+* address window. After setting this target window, the XOR will be
+* able to access the target within the address window.
+*
+* INPUT:
+* winNum - One of the possible XOR memory decode windows.
+* target - Peripheral target enumerator.
+* base - Window base address.
+* size - Window size.
+* enable - Window enable/disable.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS xorDecRegs;
+ MV_TARGET_ATTRIB targetAttribs;
+ MV_U32 chan;
+
+ /* Parameter checking */
+ if (winNum >= XOR_MAX_ADDR_DEC_WIN)
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum));
+ return MV_BAD_PARAM;
+ }
+ if (pAddrDecWin == NULL)
+ {
+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ ));
+ return MV_BAD_PTR;
+ }
+ /* Check if the requested window overlaps with current windows */
+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin))
+ {
+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum));
+ return MV_ERROR;
+ }
+
+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum));
+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum));
+
+ /* Get Base Address and size registers values */
+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs))
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__));
+ return MV_BAD_PARAM;
+ }
+
+
+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs);
+
+ /* set attributes */
+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK;
+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS;
+ /* set target ID */
+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK;
+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS;
+
+
+ /* Write to address decode Base Address Register */
+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg);
+
+ /* Write to Size Register */
+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg);
+
+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
+ {
+ if (pAddrDecWin->enable)
+ {
+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan),
+ XEXWCR_WIN_EN_MASK(winNum));
+ }
+ else
+ {
+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan),
+ XEXWCR_WIN_EN_MASK(winNum));
+ }
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvXorTargetWinGet - Get xor peripheral target address window.
+*
+* DESCRIPTION:
+* Get xor peripheral target address window.
+*
+* INPUT:
+* winNum - One of the possible XOR memory decode windows.
+*
+* OUTPUT:
+* base - Window base address.
+* size - Window size.
+* enable - window enable/disable.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin)
+{
+ MV_DEC_REGS xorDecRegs;
+ MV_TARGET_ATTRIB targetAttrib;
+ MV_U32 chan=0,chanWinEn;
+
+ /* Parameter checking */
+ if (winNum >= XOR_MAX_ADDR_DEC_WIN)
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum));
+ return MV_ERROR;
+ }
+
+ if (NULL == pAddrDecWin)
+ {
+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ ));
+ return MV_BAD_PTR;
+ }
+
+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum);
+
+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */
+ {
+ /* Check if enable bit is equal for all channels */
+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) &
+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn)
+ {
+ mvOsPrintf("%s: ERR. Window enable field must be equal in "
+ "all channels(chan=%d)\n",__FUNCTION__, chan);
+ return MV_ERROR;
+ }
+ }
+
+
+
+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum));
+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum));
+
+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__);
+ return MV_ERROR;
+ }
+
+ /* attrib and targetId */
+ targetAttrib.attrib =
+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS;
+ targetAttrib.targetId =
+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS;
+
+
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
+
+ if(chanWinEn)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else pAddrDecWin->enable = MV_FALSE;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvXorTargetWinEnable - Enable/disable a Xor address decode window
+*
+* DESCRIPTION:
+* This function enable/disable a XOR address decode window.
+* if parameter 'enable' == MV_TRUE the routine will enable the
+* window, thus enabling XOR accesses (before enabling the window it is
+* tested for overlapping). Otherwise, the window will be disabled.
+*
+* INPUT:
+* winNum - Decode window number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable)
+{
+ MV_XOR_DEC_WIN addrDecWin;
+ MV_U32 chan;
+
+ /* Parameter checking */
+ if (winNum >= XOR_MAX_ADDR_DEC_WIN)
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum));
+ return MV_ERROR;
+ }
+
+ if (enable == MV_TRUE)
+ {
+ /* Get current window */
+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin))
+ {
+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__));
+ return MV_ERROR;
+ }
+
+ /* Check for overlapping */
+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin)))
+ {
+ /* Overlap detected */
+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__));
+ return MV_ERROR;
+ }
+
+ /* No Overlap. Enable address decode target window */
+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
+ {
+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan),
+ XEXWCR_WIN_EN_MASK(winNum));
+ }
+
+ }
+ else
+ {
+ /* Disable address decode target window */
+
+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
+ {
+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan),
+ XEXWCR_WIN_EN_MASK(winNum));
+ }
+
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvXorSetProtWinSet - Configure access attributes of a XOR engine
+* to one of the XOR memory windows.
+*
+* DESCRIPTION:
+* Each engine can be configured with access attributes for each of the
+* memory spaces. This function sets access attributes
+* to a given window for the given engine
+*
+* INPUTS:
+* chan - One of the possible engines.
+* winNum - One of the possible XOR memory spaces.
+* access - Protection access rights.
+* write - Write rights.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access,
+ MV_BOOL write)
+{
+ MV_U32 temp;
+
+ /* Parameter checking */
+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT)
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan));
+ return MV_BAD_PARAM;
+ }
+ if (winNum >= XOR_MAX_ADDR_DEC_WIN)
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum));
+ return MV_BAD_PARAM;
+ }
+
+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) &
+ (~XEXWCR_WIN_ACC_MASK(winNum));
+
+ /* if access is disable */
+ if (!access)
+ {
+ /* disable access */
+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum);
+ }
+ /* if access is enable */
+ else
+ {
+ /* if write is enable */
+ if (write)
+ {
+ /* enable write */
+ temp |= XEXWCR_WIN_ACC_RW(winNum);
+ }
+ /* if write is disable */
+ else
+ {
+ /* disable write */
+ temp |= XEXWCR_WIN_ACC_RO(winNum);
+ }
+ }
+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp);
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvXorPciRemap - Set XOR remap register for PCI address windows.
+*
+* DESCRIPTION:
+* only Windows 0-3 can be remapped.
+*
+* INPUT:
+* winNum - window number
+* pAddrDecWin - pointer to address space window structure
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh)
+{
+ /* Parameter checking */
+ if (winNum >= XOR_MAX_REMAP_WIN)
+ {
+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum));
+ return MV_BAD_PARAM;
+ }
+
+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* xorWinOverlapDetect - Detect XOR address windows overlaping
+*
+* DESCRIPTION:
+* An unpredicted behaviour is expected in case XOR address decode
+* windows overlaps.
+* This function detects XOR address decode windows overlaping of a
+* specified window. The function does not check the window itself for
+* overlaping. The function also skipps disabled address decode windows.
+*
+* INPUT:
+* winNum - address decode window number.
+* pAddrDecWin - An address decode window struct.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlap current address
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
+* from registers.
+*
+*******************************************************************************/
+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
+{
+ MV_U32 baseAddrEnableReg;
+ MV_U32 winNumIndex,chan;
+ MV_XOR_DEC_WIN addrDecWin;
+
+ if (pAddrWin == NULL)
+ {
+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ ));
+ return MV_BAD_PTR;
+ }
+
+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++)
+ {
+ /* Read base address enable register. Do not check disabled windows */
+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan));
+
+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++)
+ {
+ /* Do not check window itself */
+ if (winNumIndex == winNum)
+ {
+ continue;
+ }
+
+ /* Do not check disabled windows */
+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin))
+ {
+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ ));
+ return MV_ERROR;
+ }
+
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
+ {
+ return MV_TRUE;
+ }
+ }
+ }
+
+ return MV_FALSE;
+}
+
+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit)
+{
+ MV_XOR_DEC_WIN win;
+ int i;
+
+ mvOsOutput( "\n" );
+ mvOsOutput( "XOR %d:\n", unit );
+ mvOsOutput( "----\n" );
+
+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ )
+ {
+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) );
+
+ mvOsOutput( "win%d - ", i );
+
+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK )
+ {
+ if( win.enable )
+ {
+ mvOsOutput( "%s base %x, ",
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
+
+ mvSizePrint( win.addrWin.size );
+
+ mvOsOutput( "\n" );
+ }
+ else
+ mvOsOutput( "disable\n" );
+ }
+ }
+}
+
+/*******************************************************************************
+* mvXorAddrDecShow - Print the XOR address decode map.
+*
+* DESCRIPTION:
+* This function print the XOR address decode map.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID mvXorAddrDecShow(MV_VOID)
+{
+ int i;
+
+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ )
+ mvXorAddrDecShowUnit(i);
+
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h
new file mode 100644
index 000000000..73b2d9e6a
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h
@@ -0,0 +1,140 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCMVSysXorh
+#define __INCMVSysXorh
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */
+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */
+
+/* XOR Engine Address Decoding Register Map */
+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4)))
+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4)))
+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4)))
+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4)))
+
+/* XOR Engine [0..1] Window Control Registers (XExWCR) */
+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum)
+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum)))
+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum)))
+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum)))
+
+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16)
+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum)))
+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum)))
+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum)))
+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum)))
+
+/* XOR Engine Base Address Registers (XEBARx) */
+#define XEBARX_TARGET_OFFS (0)
+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS)
+#define XEBARX_ATTR_OFFS (8)
+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS)
+#define XEBARX_BASE_OFFS (16)
+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS)
+
+/* XOR Engine Size Mask Registers (XESMRx) */
+#define XESMRX_SIZE_MASK_OFFS (16)
+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS)
+
+/* XOR Engine High Address Remap Register (XEHARRx1) */
+#define XEHARRX_REMAP_OFFS (0)
+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS)
+
+typedef struct _mvXorDecWin
+{
+ MV_TARGET target;
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+
+}MV_XOR_DEC_WIN;
+
+MV_STATUS mvXorInit (MV_VOID);
+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum,
+ MV_XOR_DEC_WIN *pAddrDecWin);
+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum,
+ MV_XOR_DEC_WIN *pAddrDecWin);
+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,
+ MV_U32 winNum, MV_BOOL enable);
+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access,
+ MV_BOOL write);
+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh);
+
+MV_VOID mvXorAddrDecShow(MV_VOID);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c
new file mode 100644
index 000000000..80325fc12
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c
@@ -0,0 +1,75 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "device/mvDevice.h"
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h
new file mode 100644
index 000000000..935077966
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h
@@ -0,0 +1,74 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDeviceH
+#define __INCmvDeviceH
+
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "device/mvDeviceRegs.h"
+
+
+#endif /* #ifndef __INCmvDeviceH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h
new file mode 100644
index 000000000..80778ad93
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h
@@ -0,0 +1,101 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDeviceRegsH
+#define __INCmvDeviceRegsH
+
+#ifndef MV_ASMLANGUAGE
+#include "ctrlEnv/mvCtrlEnvLib.h"
+/* This enumerator describes the Marvell controller possible devices that */
+/* can be connected to its device interface. */
+typedef enum _mvDevice
+{
+#if defined(MV_INCLUDE_DEVICE_CS0)
+ DEV_CS0 = 0, /* Device connected to dev CS[0] */
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS1)
+ DEV_CS1 = 1, /* Device connected to dev CS[1] */
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS2)
+ DEV_CS2 = 2, /* Device connected to dev CS[2] */
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS3)
+ DEV_CS3 = 3, /* Device connected to dev CS[2] */
+#endif
+#if defined(MV_INCLUDE_DEVICE_CS4)
+ DEV_CS4 = 4, /* Device connected to BOOT dev */
+#endif
+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS
+}MV_DEVICE;
+
+
+#endif /* MV_ASMLANGUAGE */
+
+
+#define NAND_CTRL_REG 0x10470
+
+#define NAND_ACTCEBOOT_BIT BIT1
+
+
+#endif /* #ifndef __INCmvDeviceRegsH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt
new file mode 100644
index 000000000..40531164c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.5
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c
new file mode 100644
index 000000000..75f7e88cf
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c
@@ -0,0 +1,211 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+*******************************************************************************/
+/*******************************************************************************
+* mvOsCpuArchLib.c - Marvell CPU architecture library
+*
+* DESCRIPTION:
+* This library introduce Marvell API for OS dependent CPU architecture
+* APIs. This library introduce single CPU architecture services APKI
+* cross OS.
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+/* includes */
+#include <asm/processor.h>
+#include "mvOs.h"
+
+static MV_U32 read_p15_c0 (void);
+
+/* defines */
+#define ARM_ID_REVISION_OFFS 0
+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS)
+
+#define ARM_ID_PART_NUM_OFFS 4
+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS)
+
+#define ARM_ID_ARCH_OFFS 16
+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS)
+
+#define ARM_ID_VAR_OFFS 20
+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS)
+
+#define ARM_ID_ASCII_OFFS 24
+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS)
+
+
+
+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr,
+ MV_U32 *memHandle)
+{
+ void *p = kmalloc( size, GFP_KERNEL );
+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL );
+ return p;
+}
+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr,
+ MV_U32 *memHandle)
+{
+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr );
+}
+
+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr,
+ MV_U32 memHandle)
+{
+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr );
+}
+
+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr,
+ MV_U32 memHandle )
+{
+ return kfree( pVirtAddr );
+}
+
+int mvOsRand(void)
+{
+ int rand;
+ get_random_bytes(&rand, sizeof(rand) );
+ return rand;
+}
+
+/*******************************************************************************
+* mvOsCpuVerGet() -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit CPU Revision
+*
+*******************************************************************************/
+MV_U32 mvOsCpuRevGet( MV_VOID )
+{
+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS);
+}
+/*******************************************************************************
+* mvOsCpuPartGet() -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit CPU Part number
+*
+*******************************************************************************/
+MV_U32 mvOsCpuPartGet( MV_VOID )
+{
+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS);
+}
+/*******************************************************************************
+* mvOsCpuArchGet() -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit CPU Architicture number
+*
+*******************************************************************************/
+MV_U32 mvOsCpuArchGet( MV_VOID )
+{
+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS);
+}
+/*******************************************************************************
+* mvOsCpuVarGet() -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit CPU Variant number
+*
+*******************************************************************************/
+MV_U32 mvOsCpuVarGet( MV_VOID )
+{
+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS);
+}
+/*******************************************************************************
+* mvOsCpuAsciiGet() -
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit CPU Variant number
+*
+*******************************************************************************/
+MV_U32 mvOsCpuAsciiGet( MV_VOID )
+{
+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS);
+}
+
+
+
+/*
+static unsigned long read_p15_c0 (void)
+*/
+/* read co-processor 15, register #0 (ID register) */
+static MV_U32 read_p15_c0 (void)
+{
+ MV_U32 value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+
+ return value;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h
new file mode 100644
index 000000000..8da562a40
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h
@@ -0,0 +1,423 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+*******************************************************************************/
+#ifndef _MV_OS_LNX_H_
+#define _MV_OS_LNX_H_
+
+
+#ifdef __KERNEL__
+/* for kernel space */
+#include <linux/autoconf.h>
+#include <linux/interrupt.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/hardirq.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+
+#include <linux/random.h>
+
+#include "dbg-trace.h"
+
+extern void mv_early_printk(char *fmt,...);
+
+#define MV_ASM __asm__ __volatile__
+#define INLINE inline
+#define MV_TRC_REC TRC_REC
+#define mvOsPrintf printk
+#define mvOsEarlyPrintf mv_early_printk
+#define mvOsOutput printk
+#define mvOsSPrintf sprintf
+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC)
+#define mvOsFree kfree
+#define mvOsMemcpy memcpy
+#define mvOsSleep(_mils_) mdelay(_mils_)
+#define mvOsTaskLock()
+#define mvOsTaskUnlock()
+#define strtol simple_strtoul
+#define mvOsDelay(x) mdelay(x)
+#define mvOsUDelay(x) udelay(x)
+#define mvCopyFromOs copy_from_user
+#define mvCopyToOs copy_to_user
+
+
+#include "mvTypes.h"
+#include "mvCommon.h"
+
+#ifdef MV_NDEBUG
+#define mvOsAssert(cond)
+#else
+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); }
+#endif /* MV_NDEBUG */
+
+#else /* __KERNEL__ */
+
+/* for user space applications */
+#include <stdlib.h>
+#include <stdio.h>
+#include <assert.h>
+#include <string.h>
+
+#define INLINE inline
+#define mvOsPrintf printf
+#define mvOsOutput printf
+#define mvOsMalloc(_size_) malloc(_size_)
+#define mvOsFree free
+#define mvOsAssert(cond) assert(cond)
+
+#endif /* __KERNEL__ */
+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \
+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL )
+
+#define mvOsCacheClear(pDev, p, size ) \
+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL)
+
+#define mvOsCacheFlush(pDev, p, size ) \
+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE)
+
+#define mvOsCacheInvalidate(pDev, p, size) \
+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE )
+
+#define mvOsCacheUnmap(pDev, phys, size) \
+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE )
+
+
+#define CPU_PHY_MEM(x) (MV_U32)x
+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x
+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x
+
+
+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */
+#define MV_MEMIO32_WRITE(addr, data) \
+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data)))
+
+#define MV_MEMIO32_READ(addr) \
+ ((*((volatile unsigned int*)(addr))))
+
+#define MV_MEMIO16_WRITE(addr, data) \
+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data)))
+
+#define MV_MEMIO16_READ(addr) \
+ ((*((volatile unsigned short*)(addr))))
+
+#define MV_MEMIO8_WRITE(addr, data) \
+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data)))
+
+#define MV_MEMIO8_READ(addr) \
+ ((*((volatile unsigned char*)(addr))))
+
+
+/* No Fast Swap implementation (in assembler) for ARM */
+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val)
+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val)
+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val)
+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val)
+
+/* 32 and 16 bit read/write in big/little endian mode */
+
+/* 16bit write in little endian mode */
+#define MV_MEMIO_LE16_WRITE(addr, data) \
+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data))
+
+/* 16bit read in little endian mode */
+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr)
+{
+ MV_U16 data;
+
+ data= (MV_U16)MV_MEMIO16_READ(addr);
+
+ return (MV_U16)MV_16BIT_LE_FAST(data);
+}
+
+/* 32bit write in little endian mode */
+#define MV_MEMIO_LE32_WRITE(addr, data) \
+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data))
+
+/* 32bit read in little endian mode */
+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr)
+{
+ MV_U32 data;
+
+ data= (MV_U32)MV_MEMIO32_READ(addr);
+
+ return (MV_U32)MV_32BIT_LE_FAST(data);
+}
+
+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount)
+{
+ while(byteCount != 0)
+ {
+ *dstAddr = *srcAddr;
+ dstAddr++;
+ srcAddr++;
+ byteCount--;
+ }
+}
+
+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu)
+{
+ MV_U64 division = 0;
+
+ if(divisor == 1)
+ return divided;
+
+ while(divided >= divisor)
+ {
+ division++;
+ divided -= divisor;
+ }
+ if (modulu != NULL)
+ *modulu = divided;
+
+ return division;
+}
+
+#if defined(MV_BRIDGE_SYNC_REORDER)
+extern MV_U32 *mvUncachedParam;
+
+static __inline void mvOsBridgeReorderWA(void)
+{
+ volatile MV_U32 val = 0;
+
+ val = mvUncachedParam[0];
+}
+#endif
+
+
+/* Flash APIs */
+#define MV_FL_8_READ MV_MEMIO8_READ
+#define MV_FL_16_READ MV_MEMIO_LE16_READ
+#define MV_FL_32_READ MV_MEMIO_LE32_READ
+#define MV_FL_8_DATA_READ MV_MEMIO8_READ
+#define MV_FL_16_DATA_READ MV_MEMIO16_READ
+#define MV_FL_32_DATA_READ MV_MEMIO32_READ
+#define MV_FL_8_WRITE MV_MEMIO8_WRITE
+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE
+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE
+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE
+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE
+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE
+
+
+/* CPU cache information */
+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */
+
+#ifdef CONFIG_L2_CACHE_ENABLE
+/* Data cache flush one line */
+#define mvOsCacheLineFlushInv(handle, addr) \
+{ \
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\
+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\
+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \
+}
+
+#else
+
+/* Data cache flush one line */
+#define mvOsCacheLineFlushInv(handle, addr) \
+{ \
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \
+}
+#endif
+
+#ifdef CONFIG_L2_CACHE_ENABLE
+#define mvOsCacheLineInv(handle,addr) \
+{ \
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \
+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \
+}
+#else
+#define mvOsCacheLineInv(handle,addr) \
+{ \
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \
+}
+#endif
+
+#ifdef CONFIG_L2_CACHE_ENABLE
+/* Data cache flush one line */
+#define mvOsCacheLineFlush(handle, addr) \
+{ \
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\
+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\
+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \
+}
+
+#else
+/* Data cache flush one line */
+#define mvOsCacheLineFlush(handle, addr) \
+{ \
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \
+}
+#endif
+
+static __inline void mvOsPrefetch(const void *ptr)
+{
+#ifdef CONFIG_USE_DSP
+ __asm__ __volatile__(
+ "pld\t%0"
+ :
+ : "o" (*(char *)ptr)
+ : "cc");
+#else
+ return;
+#endif
+}
+
+
+/* Flush CPU pipe */
+#define CPU_PIPE_FLUSH
+
+
+
+
+
+/* register manipulations */
+
+/******************************************************************************
+* This debug function enable the write of each register that u-boot access to
+* to an array in the DRAM, the function record only MV_REG_WRITE access.
+* The function could not be operate when booting from flash.
+* In order to print the array we use the printreg command.
+******************************************************************************/
+/* #define REG_DEBUG */
+#if defined(REG_DEBUG)
+extern int reg_arry[2048][2];
+extern int reg_arry_index;
+#endif
+
+/* Marvell controller register read/write macros */
+#define MV_REG_VALUE(offset) \
+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))))
+
+#define MV_REG_READ(offset) \
+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset)))
+
+#if defined(REG_DEBUG)
+#define MV_REG_WRITE(offset, val) \
+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \
+ { \
+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
+ reg_arry[reg_arry_index][1] = (val);\
+ reg_arry_index++;\
+ }
+#else
+#define MV_REG_WRITE(offset, val) \
+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val));
+#endif
+
+#define MV_REG_BYTE_READ(offset) \
+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset))))
+
+#if defined(REG_DEBUG)
+#define MV_REG_BYTE_WRITE(offset, val) \
+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \
+ { \
+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
+ reg_arry[reg_arry_index][1] = (val);\
+ reg_arry_index++;\
+ }
+#else
+#define MV_REG_BYTE_WRITE(offset, val) \
+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val))
+#endif
+
+#if defined(REG_DEBUG)
+#define MV_REG_BIT_SET(offset, bitMask) \
+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \
+ MV_32BIT_LE_FAST(bitMask)))); \
+ { \
+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\
+ reg_arry_index++;\
+ }
+#else
+#define MV_REG_BIT_SET(offset, bitMask) \
+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \
+ MV_32BIT_LE_FAST(bitMask))))
+#endif
+
+#if defined(REG_DEBUG)
+#define MV_REG_BIT_RESET(offset,bitMask) \
+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \
+ MV_32BIT_LE_FAST(~bitMask)))); \
+ { \
+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\
+ reg_arry_index++;\
+ }
+#else
+#define MV_REG_BIT_RESET(offset,bitMask) \
+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \
+ MV_32BIT_LE_FAST(~bitMask))))
+#endif
+
+
+
+/* ARM architecture APIs */
+MV_U32 mvOsCpuRevGet (MV_VOID);
+MV_U32 mvOsCpuPartGet (MV_VOID);
+MV_U32 mvOsCpuArchGet (MV_VOID);
+MV_U32 mvOsCpuVarGet (MV_VOID);
+MV_U32 mvOsCpuAsciiGet (MV_VOID);
+
+/* Other APIs */
+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle);
+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle );
+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle );
+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle );
+int mvOsRand(void);
+
+#endif /* _MV_OS_LNX_H_ */
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h
new file mode 100644
index 000000000..c925a9e9a
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h
@@ -0,0 +1,158 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+*******************************************************************************/
+/*******************************************************************************
+* mvOsLinux.h - O.S. interface header file for Linux
+*
+* DESCRIPTION:
+* This header file contains OS dependent definition under Linux
+*
+* DEPENDENCIES:
+* Linux kernel header files.
+*
+* FILE REVISION NUMBER:
+* $Revision: 1.1 $
+*******************************************************************************/
+
+#ifndef __INCmvOsLinuxh
+#define __INCmvOsLinuxh
+
+/* Includes */
+#include <linux/autoconf.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/major.h>
+#include <linux/errno.h>
+#include <linux/genhd.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/pci.h>
+
+#include <asm/byteorder.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include "mvOs.h"
+
+
+/* Definitions */
+#define MV_DEFAULT_QUEUE_DEPTH 2
+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION
+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN
+
+#ifdef CONFIG_MV88F6082
+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE
+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2
+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN
+#endif
+
+/* System dependent macro for flushing CPU write cache */
+#if defined (MV_BRIDGE_SYNC_REORDER)
+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \
+ wmb(); \
+ mvOsBridgeReorderWA(); \
+ } while (0)
+#else
+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb()
+#endif /* CONFIG_MV78XX0 */
+
+/* System dependent little endian from / to CPU conversions */
+#define MV_CPU_TO_LE16(x) cpu_to_le16(x)
+#define MV_CPU_TO_LE32(x) cpu_to_le32(x)
+
+#define MV_LE16_TO_CPU(x) le16_to_cpu(x)
+#define MV_LE32_TO_CPU(x) le32_to_cpu(x)
+
+#ifdef __BIG_ENDIAN_BITFIELD
+#define MV_BIG_ENDIAN_BITFIELD
+#endif
+
+/* System dependent register read / write in byte/word/dword variants */
+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset)
+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset)
+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset)
+#define MV_REG_READ_BYTE(base, offset) readb(base + offset)
+#define MV_REG_READ_WORD(base, offset) readw(base + offset)
+#define MV_REG_READ_DWORD(base, offset) readl(base + offset)
+
+
+/* Typedefs */
+
+/* System dependant typedefs */
+typedef void *MV_VOID_PTR;
+typedef u32 *MV_U32_PTR;
+typedef u16 *MV_U16_PTR;
+typedef u8 *MV_U8_PTR;
+typedef char *MV_CHAR_PTR;
+typedef void *MV_BUS_ADDR_T;
+typedef unsigned long MV_CPU_FLAGS;
+
+
+/* Structures */
+/* System dependent structure */
+typedef struct mvOsSemaphore
+{
+ int notUsed;
+} MV_OS_SEMAPHORE;
+
+
+/* Functions (User implemented)*/
+
+/* Semaphore init, take and release */
+#define mvOsSemInit(x) MV_TRUE
+#define mvOsSemTake(x)
+#define mvOsSemRelease(x)
+
+/* Interrupt masking and unmasking functions */
+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID);
+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS);
+
+/* Delay function in micro seconds resolution */
+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32);
+
+/* Typedefs */
+typedef enum mvBoolean
+{
+ MV_SFALSE, MV_STRUE
+} MV_BOOLEAN;
+
+/* System logging function */
+#include "mvLog.h"
+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */
+#ifdef MV_LOGGER
+#define MV_SATA_SUPPORT_READ_WRITE_LONG
+#endif
+
+#define MV_IAL_LOG_ID 3
+
+#endif /* __INCmvOsLinuxh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h
new file mode 100644
index 000000000..d761060c9
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h
@@ -0,0 +1,375 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+
+*******************************************************************************/
+/*******************************************************************************
+* mvSysHwCfg.h - Marvell system HW configuration file
+*
+* DESCRIPTION:
+* None.
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+#ifndef __INCmvSysHwConfigh
+#define __INCmvSysHwConfigh
+
+#include "../../../../include/linux/autoconf.h"
+
+#define CONFIG_MARVELL 1
+
+/* includes */
+#define _1K 0x00000400
+#define _4K 0x00001000
+#define _8K 0x00002000
+#define _16K 0x00004000
+#define _32K 0x00008000
+#define _64K 0x00010000
+#define _128K 0x00020000
+#define _256K 0x00040000
+#define _512K 0x00080000
+
+#define _1M 0x00100000
+#define _2M 0x00200000
+#define _4M 0x00400000
+#define _8M 0x00800000
+#define _16M 0x01000000
+#define _32M 0x02000000
+#define _64M 0x04000000
+#define _128M 0x08000000
+#define _256M 0x10000000
+#define _512M 0x20000000
+
+#define _1G 0x40000000
+#define _2G 0x80000000
+
+/****************************************/
+/* Soc supporeted Units definitions */
+/****************************************/
+
+#ifdef CONFIG_MV_INCLUDE_PEX
+#define MV_INCLUDE_PEX
+#endif
+#ifdef CONFIG_MV_INCLUDE_TWSI
+#define MV_INCLUDE_TWSI
+#endif
+#ifdef CONFIG_MV_INCLUDE_CESA
+#define MV_INCLUDE_CESA
+#endif
+#ifdef CONFIG_MV_INCLUDE_GIG_ETH
+#define MV_INCLUDE_GIG_ETH
+#endif
+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA
+#define MV_INCLUDE_INTEG_SATA
+#define MV_INCLUDE_SATA
+#endif
+#ifdef CONFIG_MV_INCLUDE_USB
+#define MV_INCLUDE_USB
+#define MV_USB_VOLTAGE_FIX
+#endif
+#ifdef CONFIG_MV_INCLUDE_NAND
+#define MV_INCLUDE_NAND
+#endif
+#ifdef CONFIG_MV_INCLUDE_TDM
+#define MV_INCLUDE_TDM
+#endif
+#ifdef CONFIG_MV_INCLUDE_XOR
+#define MV_INCLUDE_XOR
+#endif
+#ifdef CONFIG_MV_INCLUDE_TWSI
+#define MV_INCLUDE_TWSI
+#endif
+#ifdef CONFIG_MV_INCLUDE_UART
+#define MV_INCLUDE_UART
+#endif
+#ifdef CONFIG_MV_INCLUDE_SPI
+#define MV_INCLUDE_SPI
+#endif
+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD
+#define MV_INCLUDE_SFLASH_MTD
+#endif
+#ifdef CONFIG_MV_INCLUDE_AUDIO
+#define MV_INCLUDE_AUDIO
+#endif
+#ifdef CONFIG_MV_INCLUDE_TS
+#define MV_INCLUDE_TS
+#endif
+#ifdef CONFIG_MV_INCLUDE_SDIO
+#define MV_INCLUDE_SDIO
+#endif
+
+
+/* NAND flash stuff */
+#ifdef CONFIG_MV_NAND_BOOT
+#define MV_NAND_BOOT
+#endif
+#ifdef CONFIG_MV_NAND
+#define MV_NAND
+#endif
+
+/* SPI flash stuff */
+#ifdef CONFIG_MV_SPI_BOOT
+#define MV_SPI_BOOT
+#endif
+
+
+/****************************************************************/
+/************* General configuration ********************/
+/****************************************************************/
+
+/* Enable Clock Power Control */
+#define MV_INCLUDE_CLK_PWR_CNTRL
+
+/* Disable the DEVICE BAR in the PEX */
+#define MV_DISABLE_PEX_DEVICE_BAR
+
+/* Allow the usage of early printings during initialization */
+#define MV_INCLUDE_EARLY_PRINTK
+
+/****************************************************************/
+/************* NFP configuration ********************************/
+/****************************************************************/
+#define MV_NFP_SEC_Q_SIZE 64
+#define MV_NFP_SEC_REQ_Q_SIZE 1000
+
+
+
+/****************************************************************/
+/************* CESA configuration ********************/
+/****************************************************************/
+
+#ifdef MV_INCLUDE_CESA
+
+#define MV_CESA_MAX_CHAN 4
+
+/* Use 2K of SRAM */
+#define MV_CESA_MAX_BUF_SIZE 1600
+
+#endif /* MV_INCLUDE_CESA */
+
+#if defined(CONFIG_MV_INCLUDE_GIG_ETH)
+
+#ifdef CONFIG_MV_NFP_STATS
+#define MV_FP_STATISTICS
+#else
+#undef MV_FP_STATISTICS
+#endif
+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */
+#define MV_ETH_SKB_REUSE_DEFAULT 1
+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */
+#define MV_ETH_TX_EN_DEFAULT 0
+
+/* un-comment if you want to perform tx_done from within the poll function */
+/* #define ETH_TX_DONE_ISR */
+
+/* put descriptors in uncached memory */
+/* #define ETH_DESCR_UNCACHED */
+
+/* Descriptors location: DRAM/internal-SRAM */
+#define ETH_DESCR_IN_SDRAM
+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */
+
+#if defined(ETH_DESCR_IN_SRAM)
+#if defined(ETH_DESCR_UNCACHED)
+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM"
+#else
+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM"
+#endif
+#elif defined(ETH_DESCR_IN_SDRAM)
+#if defined(ETH_DESCR_UNCACHED)
+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM"
+#else
+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM"
+#endif
+#else
+ #error "Ethernet descriptors location undefined"
+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/
+
+/* SW Sync-Barrier: not relevant for 88fxx81*/
+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */
+/* In RX the CPU theoretically might see himself as the descriptor owner, */
+/* although the buffer hadn't been written to DRAM yet. Performance cost. */
+/* #define INCLUDE_SYNC_BARR */
+
+/* Buffers cache coherency method (buffers in DRAM) */
+#ifndef MV_CACHE_COHER_SW
+/* Taken from mvCommon.h */
+/* Memory uncached, HW or SW cache coherency is not needed */
+#define MV_UNCACHED 0
+/* Memory cached, HW cache coherency supported in WriteThrough mode */
+#define MV_CACHE_COHER_HW_WT 1
+/* Memory cached, HW cache coherency supported in WriteBack mode */
+#define MV_CACHE_COHER_HW_WB 2
+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
+#define MV_CACHE_COHER_SW 3
+
+#endif
+
+/* DRAM cache coherency configuration */
+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW
+
+
+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */
+
+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB)
+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)"
+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT)
+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)"
+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW)
+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency"
+#elif (ETHER_DRAM_COHER == MV_UNCACHED)
+# define ETH_SDRAM_CONFIG_STR "DRAM uncached"
+#else
+ #error "Ethernet-DRAM undefined"
+#endif /* ETHER_DRAM_COHER */
+
+
+/****************************************************************/
+/************* Ethernet driver configuration ********************/
+/****************************************************************/
+
+/* port's default queueus */
+#define ETH_DEF_TXQ 0
+#define ETH_DEF_RXQ 0
+
+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM
+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM
+
+/* interrupt coalescing setting */
+#define ETH_TX_COAL 200
+#define ETH_RX_COAL 200
+
+/* Checksum offloading */
+#define TX_CSUM_OFFLOAD
+#define RX_CSUM_OFFLOAD
+
+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */
+
+/****************************************************************/
+/*************** Telephony configuration ************************/
+/****************************************************************/
+#if defined(CONFIG_MV_TDM_LINEAR_MODE)
+ #define MV_TDM_LINEAR_MODE
+#elif defined(CONFIG_MV_TDM_ULAW_MODE)
+ #define MV_TDM_ULAW_MODE
+#endif
+
+#if defined(CONFIG_MV_TDM_5CHANNELS)
+ #define MV_TDM_5CHANNELS
+#endif
+
+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE)
+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE
+#endif
+
+/* We use the following registers to store DRAM interface pre configuration */
+/* auto-detection results */
+/* IMPORTANT: We are using mask register for that purpose. Before writing */
+/* to units mask register, make sure main maks register is set to disable */
+/* all interrupts. */
+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */
+#define DRAM_BUF_REG1 0x30820 /* sdram config */
+#define DRAM_BUF_REG2 0x30830 /* sdram mode */
+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */
+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */
+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */
+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */
+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */
+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */
+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */
+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */
+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */
+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */
+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */
+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */
+
+/* Following the pre-configuration registers default values restored after */
+/* auto-detection is done */
+#define DRAM_BUF_REG_DV 0
+
+/* System Mapping */
+#define SDRAM_CS0_BASE 0x00000000
+#define SDRAM_CS0_SIZE _256M
+
+#define SDRAM_CS1_BASE 0x10000000
+#define SDRAM_CS1_SIZE _256M
+
+#define SDRAM_CS2_BASE 0x20000000
+#define SDRAM_CS2_SIZE _256M
+
+#define SDRAM_CS3_BASE 0x30000000
+#define SDRAM_CS3_SIZE _256M
+
+/* PEX */
+#define PEX0_MEM_BASE 0xe8000000
+#define PEX0_MEM_SIZE _128M
+
+#define PEX0_IO_BASE 0xf2000000
+#define PEX0_IO_SIZE _1M
+
+/* Device Chip Selects */
+#define NFLASH_CS_BASE 0xfa000000
+#define NFLASH_CS_SIZE _2M
+
+#define SPI_CS_BASE 0xf4000000
+#define SPI_CS_SIZE _16M
+
+#define CRYPT_ENG_BASE 0xf0000000
+#define CRYPT_ENG_SIZE _2M
+
+#define BOOTDEV_CS_BASE 0xff800000
+#define BOOTDEV_CS_SIZE _8M
+
+/* CS2 - BOOTROM */
+#define DEVICE_CS2_BASE 0xff900000
+#define DEVICE_CS2_SIZE _1M
+
+/* PEX Work arround */
+/* the target we will use for the workarround */
+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM
+/*a flag that indicates if we are going to use the
+size and base of the target we using for the workarround
+window */
+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1
+/* if the above flag is 0 then the following values
+will be used for the workarround window base and size,
+otherwise the following defines will be ignored */
+#define PEX_CONFIG_RW_WA_BASE 0xF3000000
+#define PEX_CONFIG_RW_WA_SIZE _16M
+
+/* Internal registers: size is defined in Controllerenvironment */
+#define INTER_REGS_BASE 0xFEE00000
+
+/* DRAM detection stuff */
+#define MV_DRAM_AUTO_SIZE
+
+/* Board clock detection */
+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */
+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */
+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */
+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */
+
+/* PEX-PCI\PCI-PCI Bridge*/
+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/
+
+
+
+#endif /* __INCmvSysHwConfigh */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c
new file mode 100644
index 000000000..717c1507c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c
@@ -0,0 +1,376 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "mvCntmr.h"
+#include "cpu/mvCpu.h"
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+extern unsigned int whoAmI(void);
+
+/*******************************************************************************
+* mvCntmrLoad -
+*
+* DESCRIPTION:
+* Load an init Value to a given counter/timer
+*
+* INPUT:
+* countNum - counter number
+* value - value to be loaded
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess
+*******************************************************************************/
+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value)
+{
+ if (countNum >= MV_CNTMR_MAX_COUNTER )
+ {
+
+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n"));
+ return MV_BAD_PARAM;;
+
+ }
+
+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value);
+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCntmrRead -
+*
+* DESCRIPTION:
+* Returns the value of the given Counter/Timer
+*
+* INPUT:
+* countNum - counter number
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_U32 counter value
+*******************************************************************************/
+MV_U32 mvCntmrRead(MV_U32 countNum)
+{
+ return MV_REG_READ(CNTMR_VAL_REG(countNum));
+}
+
+/*******************************************************************************
+* mvCntmrWrite -
+*
+* DESCRIPTION:
+* Returns the value of the given Counter/Timer
+*
+* INPUT:
+* countNum - counter number
+* countVal - value to write
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None
+*******************************************************************************/
+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal)
+{
+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal);
+}
+
+/*******************************************************************************
+* mvCntmrCtrlSet -
+*
+* DESCRIPTION:
+* Set the Control to a given counter/timer
+*
+* INPUT:
+* countNum - counter number
+* pCtrl - pointer to MV_CNTMR_CTRL structure
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess
+*******************************************************************************/
+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl)
+{
+ MV_U32 cntmrCtrl;
+
+ if (countNum >= MV_CNTMR_MAX_COUNTER )
+ {
+
+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n")));
+ return MV_BAD_PARAM;;
+
+ }
+
+ /* read control register */
+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG);
+
+
+ if (pCtrl->enable) /* enable counter\timer */
+ {
+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum);
+ }
+ else /* disable counter\timer */
+ {
+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum);
+ }
+
+ if ( pCtrl->autoEnable ) /* Auto mode */
+ {
+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum);
+
+ }
+ else /* no auto mode */
+ {
+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum);
+ }
+
+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl);
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvCntmrCtrlGet -
+*
+* DESCRIPTION:
+* Get the Control value of a given counter/timer
+*
+* INPUT:
+* countNum - counter number
+* pCtrl - pointer to MV_CNTMR_CTRL structure
+*
+* OUTPUT:
+* Counter\Timer control value
+*
+* RETURN:
+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess
+*******************************************************************************/
+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl)
+{
+ MV_U32 cntmrCtrl;
+
+ if (countNum >= MV_CNTMR_MAX_COUNTER )
+ {
+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n")));
+ return MV_BAD_PARAM;;
+ }
+
+ /* read control register */
+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG);
+
+ /* enable counter\timer */
+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum))
+ {
+ pCtrl->enable = MV_TRUE;
+ }
+ else
+ {
+ pCtrl->enable = MV_FALSE;
+ }
+
+ /* counter mode */
+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum))
+ {
+ pCtrl->autoEnable = MV_TRUE;
+ }
+ else
+ {
+ pCtrl->autoEnable = MV_FALSE;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCntmrEnable -
+*
+* DESCRIPTION:
+* Set the Enable-Bit to logic '1' ==> starting the counter
+*
+* INPUT:
+* countNum - counter number
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess
+*******************************************************************************/
+MV_STATUS mvCntmrEnable(MV_U32 countNum)
+{
+ MV_U32 cntmrCtrl;
+
+ if (countNum >= MV_CNTMR_MAX_COUNTER )
+ {
+
+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n")));
+ return MV_BAD_PARAM;;
+
+ }
+
+ /* read control register */
+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG);
+
+ /* enable counter\timer */
+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum);
+
+
+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCntmrDisable -
+*
+* DESCRIPTION:
+* Stop the counter/timer running, and returns its Value
+*
+* INPUT:
+* countNum - counter number
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_U32 counter\timer value
+*******************************************************************************/
+MV_STATUS mvCntmrDisable(MV_U32 countNum)
+{
+ MV_U32 cntmrCtrl;
+
+ if (countNum >= MV_CNTMR_MAX_COUNTER )
+ {
+
+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")));
+ return MV_BAD_PARAM;;
+
+ }
+
+ /* read control register */
+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG);
+
+ /* disable counter\timer */
+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum);
+
+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvCntmrStart -
+*
+* DESCRIPTION:
+* Combined all the sub-operations above to one function: Load,setMode,Enable
+*
+* INPUT:
+* countNum - counter number
+* value - value of the counter\timer to be set
+* pCtrl - pointer to MV_CNTMR_CTRL structure
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess
+*******************************************************************************/
+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value,
+ MV_CNTMR_CTRL *pCtrl)
+{
+
+ if (countNum >= MV_CNTMR_MAX_COUNTER )
+ {
+
+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"));
+ return MV_BAD_PARAM;;
+
+ }
+
+ /* load value onto counter\timer */
+ mvCntmrLoad(countNum,value);
+
+ /* set the counter to load in the first time */
+ mvCntmrWrite(countNum,value);
+
+ /* set control for timer \ cunter and enable */
+ mvCntmrCtrlSet(countNum,pCtrl);
+
+ return MV_OK;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h
new file mode 100644
index 000000000..b911d0f04
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h
@@ -0,0 +1,121 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvTmrWtdgh
+#define __INCmvTmrWtdgh
+
+/* includes */
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "cntmr/mvCntmrRegs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+
+
+/* This enumerator describe counters\watchdog numbers */
+typedef enum _mvCntmrID
+{
+ TIMER0 = 0,
+ TIMER1,
+ WATCHDOG,
+ TIMER2,
+ TIMER3,
+}MV_CNTMR_ID;
+
+
+/* Counter / Timer control structure */
+typedef struct _mvCntmrCtrl
+{
+ MV_BOOL enable; /* enable */
+ MV_BOOL autoEnable; /* counter/Timer */
+}MV_CNTMR_CTRL;
+
+
+/* Functions */
+
+/* Load an init Value to a given counter/timer */
+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value);
+
+/* Returns the value of the given Counter/Timer */
+MV_U32 mvCntmrRead(MV_U32 countNum);
+
+/* Write a value of the given Counter/Timer */
+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal);
+
+/* Set the Control to a given counter/timer */
+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl);
+
+/* Get the value of a given counter/timer */
+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl);
+
+/* Set the Enable-Bit to logic '1' ==> starting the counter. */
+MV_STATUS mvCntmrEnable(MV_U32 countNum);
+
+/* Stop the counter/timer running, and returns its Value. */
+MV_STATUS mvCntmrDisable(MV_U32 countNum);
+
+/* Combined all the sub-operations above to one function: Load,setMode,Enable */
+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value,
+ MV_CNTMR_CTRL *pCtrl);
+
+#endif /* __INCmvTmrWtdgh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h
new file mode 100644
index 000000000..b69bc66ad
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h
@@ -0,0 +1,121 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvTmrwtdgRegsh
+#define __INCmvTmrwtdgRegsh
+
+/*******************************************/
+/* ARM Timers Registers Map */
+/*******************************************/
+
+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \
+ (((tmrNum) <= 3)?0:8))
+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \
+ (((tmrNum) <= 3)?0:8))
+#define CNTMR_CTRL_REG (CNTMR_BASE)
+
+/*For MV78XX0*/
+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI()))
+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI()))
+
+/* ARM Timers Registers Map */
+/*******************************************/
+
+
+/* ARM Timers Control Register */
+/* CPU_TIMERS_CTRL_REG (CTCR) */
+
+#define TIMER0_NUM 0
+#define TIMER1_NUM 1
+#define WATCHDOG_NUM 2
+#define TIMER2_NUM 3
+#define TIMER3_NUM 4
+
+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1
+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+
+/* ARM Timer\Watchdog Reload Register */
+/* CNTMR_RELOAD_REG (TRR) */
+
+#define TRG_ARM_TIMER_REL_OFFS 0
+#define TRG_ARM_TIMER_REL_MASK 0xffffffff
+
+/* ARM Timer\Watchdog Register */
+/* CNTMR_VAL_REG (TVRG) */
+
+#define TVR_ARM_TIMER_OFFS 0
+#define TVR_ARM_TIMER_MASK 0xffffffff
+#define TVR_ARM_TIMER_MAX 0xffffffff
+
+
+
+#endif /* __INCmvTmrwtdgRegsh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt
new file mode 100644
index 000000000..85bfa612c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.3
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c
new file mode 100644
index 000000000..609e674e3
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c
@@ -0,0 +1,207 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include "mvOs.h"
+#include "mvCpuCntrs.h"
+
+
+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] =
+{
+ /*0*/
+ {
+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS,
+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY,
+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT,
+ },
+ /*1*/
+ {
+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS,
+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_INVALID,
+ },
+ /*2*/
+ {
+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS,
+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_INVALID,
+ },
+ /*3*/
+ {
+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS,
+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS,
+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS,
+ MV_CPU_CNTRS_INVALID,
+ }
+};
+
+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM];
+
+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128];
+
+void mvCpuCntrsReset(void)
+{
+ MV_U32 reg = 0;
+
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg));
+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg));
+}
+
+void program_counter(int counter, int op)
+{
+ MV_U32 reg = (1 << op) | 0x1; /*enable*/
+
+ switch(counter)
+ {
+ case 0:
+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg));
+ return;
+
+ case 1:
+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg));
+ return;
+
+ case 2:
+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg));
+ return;
+
+ case 3:
+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg));
+ return;
+
+ default:
+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter);
+ }
+ return;
+}
+
+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent)
+{
+ int i;
+
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ {
+ pEvent->counters_sum[i] = 0;
+ }
+ pEvent->num_of_measurements = 0;
+}
+
+
+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold)
+{
+ int i;
+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT));
+
+ if(event)
+ {
+ strncpy(event->name, name, sizeof(event->name));
+ event->num_of_measurements = 0;
+ event->avg_sample_count = print_threshold;
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ {
+ event->counters_before[i] = 0;
+ event->counters_after[i] = 0;
+ event->counters_sum[i] = 0;
+ }
+ }
+ return event;
+}
+
+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event)
+{
+ if(event != NULL)
+ mvOsFree(event);
+}
+
+
+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op,
+ char* name, MV_U32 overhead)
+{
+ int i;
+
+ /* Find required operations */
+ for(i=0; i<MV_CPU_CNTRS_OPS_NUM; i++)
+ {
+ if( mvCpuCntrsOpsTbl[counter][i] == op)
+ {
+ strncpy(mvCpuCntrsTbl[counter].name, name, sizeof(mvCpuCntrsTbl[counter].name));
+ mvCpuCntrsTbl[counter].operation = op;
+ mvCpuCntrsTbl[counter].opIdx = i+1;
+ mvCpuCntrsTbl[counter].overhead = overhead;
+ program_counter(counter, mvCpuCntrsTbl[counter].opIdx);
+ mvOsPrintf("Counter=%d, opIdx=%d, overhead=%d\n",
+ counter, mvCpuCntrsTbl[counter].opIdx, mvCpuCntrsTbl[counter].overhead);
+ return MV_OK;
+ }
+ }
+ return MV_NOT_FOUND;
+}
+
+void mvCpuCntrsShow(MV_CPU_CNTRS_EVENT* pEvent)
+{
+ int i;
+ MV_U64 counters_avg;
+
+ if(pEvent->num_of_measurements < pEvent->avg_sample_count)
+ return;
+
+ mvOsPrintf("%16s: ", pEvent->name);
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ {
+ counters_avg = mvOsDivMod64(pEvent->counters_sum[i],
+ pEvent->num_of_measurements, NULL);
+ if(counters_avg >= mvCpuCntrsTbl[i].overhead)
+ counters_avg -= mvCpuCntrsTbl[i].overhead;
+ else
+ counters_avg = 0;
+
+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg);
+ }
+ mvOsPrintf("\n");
+ mvCpuCntrsEventClear(pEvent);
+ mvCpuCntrsReset();
+}
+
+void mvCpuCntrsStatus(void)
+{
+ int i;
+
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ {
+ mvOsPrintf("#%d: %s, overhead=%d\n",
+ i, mvCpuCntrsTbl[i].name, mvCpuCntrsTbl[i].overhead);
+ }
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h
new file mode 100644
index 000000000..8d49af009
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h
@@ -0,0 +1,213 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+*******************************************************************************/
+#ifndef __mvCpuCntrs_h__
+#define __mvCpuCntrs_h__
+
+#include "mvTypes.h"
+#include "mvOs.h"
+
+
+#define MV_CPU_CNTRS_NUM 4
+#define MV_CPU_CNTRS_OPS_NUM 32
+
+typedef enum
+{
+ MV_CPU_CNTRS_INVALID = 0,
+ MV_CPU_CNTRS_CYCLES,
+ MV_CPU_CNTRS_ICACHE_READ_MISS,
+ MV_CPU_CNTRS_DCACHE_ACCESS,
+ MV_CPU_CNTRS_DCACHE_READ_MISS,
+ MV_CPU_CNTRS_DCACHE_READ_HIT,
+ MV_CPU_CNTRS_DCACHE_WRITE_MISS,
+ MV_CPU_CNTRS_DCACHE_WRITE_HIT,
+ MV_CPU_CNTRS_DTLB_MISS,
+ MV_CPU_CNTRS_TLB_MISS,
+ MV_CPU_CNTRS_ITLB_MISS,
+ MV_CPU_CNTRS_INSTRUCTIONS,
+ MV_CPU_CNTRS_SINGLE_ISSUE,
+ MV_CPU_CNTRS_MMU_READ_LATENCY,
+ MV_CPU_CNTRS_MMU_READ_BEAT,
+ MV_CPU_CNTRS_BRANCH_RETIRED,
+ MV_CPU_CNTRS_BRANCH_TAKEN,
+ MV_CPU_CNTRS_BRANCH_PREDICT_MISS,
+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT,
+ MV_CPU_CNTRS_WB_FULL_CYCLES,
+ MV_CPU_CNTRS_WB_WRITE_LATENCY,
+ MV_CPU_CNTRS_WB_WRITE_BEAT,
+ MV_CPU_CNTRS_ICACHE_READ_LATENCY,
+ MV_CPU_CNTRS_ICACHE_READ_BEAT,
+ MV_CPU_CNTRS_DCACHE_READ_LATENCY,
+ MV_CPU_CNTRS_DCACHE_READ_BEAT,
+ MV_CPU_CNTRS_DCACHE_WRITE_LATENCY,
+ MV_CPU_CNTRS_DCACHE_WRITE_BEAT,
+ MV_CPU_CNTRS_LDM_STM_HOLD,
+ MV_CPU_CNTRS_IS_HOLD,
+ MV_CPU_CNTRS_DATA_WRITE_ACCESS,
+ MV_CPU_CNTRS_DATA_READ_ACCESS,
+ MV_CPU_CNTRS_BIU_SIMULT_ACCESS,
+ MV_CPU_CNTRS_BIU_ANY_ACCESS,
+
+} MV_CPU_CNTRS_OPS;
+
+typedef struct
+{
+ char name[16];
+ MV_CPU_CNTRS_OPS operation;
+ int opIdx;
+ MV_U32 overhead;
+
+} MV_CPU_CNTRS_ENTRY;
+
+
+typedef struct
+{
+ char name[16];
+ MV_U32 num_of_measurements;
+ MV_U32 avg_sample_count;
+ MV_U64 counters_before[MV_CPU_CNTRS_NUM];
+ MV_U64 counters_after[MV_CPU_CNTRS_NUM];
+ MV_U64 counters_sum[MV_CPU_CNTRS_NUM];
+
+} MV_CPU_CNTRS_EVENT;
+
+extern MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM];
+
+
+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op,
+ char* name, MV_U32 overhead);
+void mvCpuCntrsInit(void);
+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold);
+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event);
+void mvCpuCntrsReset(void);
+void mvCpuCntrsShow(MV_CPU_CNTRS_EVENT* pEvent);
+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent);
+
+/* internal */
+void program_counter(int counter, int op);
+
+static INLINE MV_U64 mvCpuCntrsRead(const int counter)
+{
+ MV_U32 low = 0, high = 0;
+ MV_U32 ll = 0;
+
+ switch(counter)
+ {
+ case 0:
+ MV_ASM ("mcr p15, 0, %0, c15, c12, 0" : : "r" (ll));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 0" : "=r" (low));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 1" : "=r" (high));
+ break;
+
+ case 1:
+ MV_ASM ("mcr p15, 0, %0, c15, c12, 1" : : "r" (ll));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 2" : "=r" (low));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 3" : "=r" (high));
+ break;
+
+ case 2:
+ MV_ASM ("mcr p15, 0, %0, c15, c12, 2" : : "r" (ll));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 4" : "=r" (low));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 5" : "=r" (high));
+ break;
+
+ case 3:
+ MV_ASM ("mcr p15, 0, %0, c15, c12, 3" : : "r" (ll));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 6" : "=r" (low));
+ MV_ASM ("mrc p15, 0, %0, c15, c13, 7" : "=r" (high));
+ break;
+
+ default:
+ mvOsPrintf("mv_cpu_cntrs_read: bad counter number (%d)\n", counter);
+ }
+ program_counter(counter, mvCpuCntrsTbl[counter].opIdx);
+ return (((MV_U64)high << 32 ) | low);
+
+}
+
+
+static INLINE void mvCpuCntrsReadBefore(MV_CPU_CNTRS_EVENT* pEvent)
+{
+#if 0
+ int i;
+
+ /* order is important - we want to measure the cycle count last here! */
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ pEvent->counters_before[i] = mvCpuCntrsRead(i);
+#else
+ pEvent->counters_before[1] = mvCpuCntrsRead(1);
+ pEvent->counters_before[3] = mvCpuCntrsRead(3);
+ pEvent->counters_before[0] = mvCpuCntrsRead(0);
+ pEvent->counters_before[2] = mvCpuCntrsRead(2);
+#endif
+}
+
+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent)
+{
+ int i;
+
+#if 0
+ /* order is important - we want to measure the cycle count first here! */
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ pEvent->counters_after[i] = mvCpuCntrsRead(i);
+#else
+ pEvent->counters_after[2] = mvCpuCntrsRead(2);
+ pEvent->counters_after[0] = mvCpuCntrsRead(0);
+ pEvent->counters_after[3] = mvCpuCntrsRead(3);
+ pEvent->counters_after[1] = mvCpuCntrsRead(1);
+#endif
+
+ for(i=0; i<MV_CPU_CNTRS_NUM; i++)
+ {
+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]);
+ }
+ pEvent->num_of_measurements++;
+}
+
+
+#ifdef CONFIG_MV_CPU_PERF_CNTRS
+
+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter)
+
+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event)
+
+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event)
+
+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event)
+
+#else
+
+#define MV_CPU_CNTRS_READ(counter)
+#define MV_CPU_CNTRS_START(event)
+#define MV_CPU_CNTRS_STOP(event)
+#define MV_CPU_CNTRS_SHOW(event)
+
+#endif /* CONFIG_MV_CPU_PERF_CNTRS */
+
+
+#endif /* __mvCpuCntrs_h__ */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c
new file mode 100644
index 000000000..033386224
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c
@@ -0,0 +1,143 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include "mvOs.h"
+#include "mvCpuL2Cntrs.h"
+
+
+
+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM];
+
+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128];
+
+void mvCpuL2CntrsReset(void)
+{
+ MV_U32 reg = 0;
+
+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg));
+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg));
+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg));
+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg));
+}
+
+static void mvCpuL2CntrConfig(int counter, int op)
+{
+ MV_U32 reg = (1 << op) | 0x1; /*enable*/
+
+ switch(counter)
+ {
+ case 0:
+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg));
+ return;
+
+ case 1:
+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg));
+ return;
+
+ default:
+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter);
+ }
+ return;
+}
+
+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent)
+{
+ int i;
+
+ for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++)
+ {
+ pEvent->counters_sum[i] = 0;
+ }
+ pEvent->num_of_measurements = 0;
+}
+
+
+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold)
+{
+ int i;
+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT));
+
+ if(event)
+ {
+ strncpy(event->name, name, sizeof(event->name));
+ event->num_of_measurements = 0;
+ event->avg_sample_count = print_threshold;
+ for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++)
+ {
+ event->counters_before[i] = 0;
+ event->counters_after[i] = 0;
+ event->counters_sum[i] = 0;
+ }
+ }
+ return event;
+}
+
+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event)
+{
+ if(event != NULL)
+ mvOsFree(event);
+}
+
+
+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op,
+ char* name, MV_U32 overhead)
+{
+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name));
+ mvCpuL2CntrsTbl[counter].operation = op;
+ mvCpuL2CntrsTbl[counter].opIdx = op;
+ mvCpuL2CntrsTbl[counter].overhead = overhead;
+ mvCpuL2CntrConfig(counter, op);
+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n",
+ counter, op, overhead);
+ return MV_OK;
+}
+
+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent)
+{
+ int i;
+ MV_U64 counters_avg;
+
+ if(pEvent->num_of_measurements < pEvent->avg_sample_count)
+ return;
+
+ mvOsPrintf("%16s: ", pEvent->name);
+ for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++)
+ {
+ counters_avg = mvOsDivMod64(pEvent->counters_sum[i],
+ pEvent->num_of_measurements, NULL);
+
+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead)
+ counters_avg -= mvCpuL2CntrsTbl[i].overhead;
+ else
+ counters_avg = 0;
+
+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg);
+ }
+ mvOsPrintf("\n");
+ mvCpuL2CntrsEventClear(pEvent);
+ mvCpuL2CntrsReset();
+}
+
+void mvCpuL2CntrsStatus(void)
+{
+ int i;
+
+ for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++)
+ {
+ mvOsPrintf("#%d: %s, overhead=%d\n",
+ i, mvCpuL2CntrsTbl[i].name, mvCpuL2CntrsTbl[i].overhead);
+ }
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h
new file mode 100644
index 000000000..570d70195
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h
@@ -0,0 +1,151 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+*******************************************************************************/
+#ifndef __mvCpuL2Cntrs_h__
+#define __mvCpuL2Cntrs_h__
+
+#include "mvTypes.h"
+#include "mvOs.h"
+
+
+#define MV_CPU_L2_CNTRS_NUM 2
+
+typedef enum
+{
+ MV_CPU_L2_CNTRS_ENABLE = 0,
+ MV_CPU_L2_CNTRS_DATA_REQ,
+ MV_CPU_L2_CNTRS_DATA_MISS_REQ,
+ MV_CPU_L2_CNTRS_INST_REQ,
+ MV_CPU_L2_CNTRS_INST_MISS_REQ,
+ MV_CPU_L2_CNTRS_DATA_READ_REQ,
+ MV_CPU_L2_CNTRS_DATA_READ_MISS_REQ,
+ MV_CPU_L2_CNTRS_DATA_WRITE_REQ,
+ MV_CPU_L2_CNTRS_DATA_WRITE_MISS_REQ,
+ MV_CPU_L2_CNTRS_RESERVED,
+ MV_CPU_L2_CNTRS_DIRTY_EVICT_REQ,
+ MV_CPU_L2_CNTRS_EVICT_BUFF_STALL,
+ MV_CPU_L2_CNTRS_ACTIVE_CYCLES,
+
+} MV_CPU_L2_CNTRS_OPS;
+
+typedef struct
+{
+ char name[16];
+ MV_CPU_L2_CNTRS_OPS operation;
+ int opIdx;
+ MV_U32 overhead;
+
+} MV_CPU_L2_CNTRS_ENTRY;
+
+
+typedef struct
+{
+ char name[16];
+ MV_U32 num_of_measurements;
+ MV_U32 avg_sample_count;
+ MV_U64 counters_before[MV_CPU_L2_CNTRS_NUM];
+ MV_U64 counters_after[MV_CPU_L2_CNTRS_NUM];
+ MV_U64 counters_sum[MV_CPU_L2_CNTRS_NUM];
+
+} MV_CPU_L2_CNTRS_EVENT;
+
+
+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op,
+ char* name, MV_U32 overhead);
+void mvCpuL2CntrsInit(void);
+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold);
+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event);
+void mvCpuL2CntrsReset(void);
+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent);
+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent);
+
+static INLINE MV_U64 mvCpuL2CntrsRead(const int counter)
+{
+ MV_U32 low = 0, high = 0;
+
+ switch(counter)
+ {
+ case 0:
+ MV_ASM ("mrc p15, 6, %0, c15, c13, 0" : "=r" (low));
+ MV_ASM ("mrc p15, 6, %0, c15, c13, 1" : "=r" (high));
+ break;
+
+ case 1:
+ MV_ASM ("mrc p15, 6, %0, c15, c13, 2" : "=r" (low));
+ MV_ASM ("mrc p15, 6, %0, c15, c13, 3" : "=r" (high));
+ break;
+
+ default:
+ mvOsPrintf("mvCpuL2CntrsRead: bad counter number (%d)\n", counter);
+ }
+ return (((MV_U64)high << 32 ) | low);
+
+}
+
+static INLINE void mvCpuL2CntrsReadBefore(MV_CPU_L2_CNTRS_EVENT* pEvent)
+{
+ int i;
+
+ for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++)
+ pEvent->counters_before[i] = mvCpuL2CntrsRead(i);
+}
+
+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent)
+{
+ int i;
+
+ for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++)
+ {
+ pEvent->counters_after[i] = mvCpuL2CntrsRead(i);
+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]);
+ }
+ pEvent->num_of_measurements++;
+}
+
+
+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS
+
+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter)
+
+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event)
+
+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event)
+
+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event)
+
+#else
+
+#define MV_CPU_L2_CNTRS_READ(counter)
+#define MV_CPU_L2_CNTRS_START(event)
+#define MV_CPU_L2_CNTRS_STOP(event)
+#define MV_CPU_L2_CNTRS_SHOW(event)
+
+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */
+
+
+#endif /* __mvCpuL2Cntrs_h__ */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt
new file mode 100644
index 000000000..85bfa612c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.3
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c
new file mode 100644
index 000000000..d1b8a3d37
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c
@@ -0,0 +1,1479 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ddr1_2/mvDram.h"
+#include "boardEnv/mvBoardEnvLib.h"
+
+#undef MV_DEBUG
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo,
+ MV_DRAM_BANK_INFO *pBankInfo);
+static MV_U32 cas2ps(MV_U8 spd_byte);
+/*******************************************************************************
+* mvDramBankGet - Get the DRAM bank paramters.
+*
+* DESCRIPTION:
+* This function retrieves DRAM bank parameters as described in
+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board
+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data
+* from it. Otherwise, if the DRAM is soldered on board, the function
+* should insert its bank information into MV_DRAM_BANK_INFO struct.
+*
+* INPUT:
+* bankNum - Board DRAM bank number.
+*
+* OUTPUT:
+* pBankInfo - DRAM bank information struct.
+*
+* RETURN:
+* MV_FAIL - Bank parameters could not be read.
+*
+*******************************************************************************/
+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo)
+{
+ MV_DIMM_INFO dimmInfo;
+
+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum));
+ /* zero pBankInfo structure */
+ memset(pBankInfo, 0, sizeof(*pBankInfo));
+
+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS ))
+ {
+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n"));
+ return MV_BAD_PARAM;
+ }
+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo))
+ {
+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n"));
+ return MV_FAIL;
+ }
+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1))
+ {
+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n"));
+ return MV_FAIL;
+ }
+
+ /* convert Dimm info to Bank info */
+ cpyDimm2BankInfo(&dimmInfo, pBankInfo);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct.
+*
+* DESCRIPTION:
+* Convert a Dimm info struct into a bank info struct.
+*
+* INPUT:
+* pDimmInfo - DIMM information structure.
+*
+* OUTPUT:
+* pBankInfo - DRAM bank information struct.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo,
+ MV_DRAM_BANK_INFO *pBankInfo)
+{
+ pBankInfo->memoryType = pDimmInfo->memoryType;
+
+ /* DIMM dimensions */
+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr;
+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr;
+ pBankInfo->dataWidth = pDimmInfo->dataWidth;
+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType;
+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth;
+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth;
+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice;
+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies;
+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval;
+
+ /* DIMM timing parameters */
+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs;
+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps =
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps;
+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps =
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps;
+
+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime;
+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive;
+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay;
+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth;
+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime;
+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay;
+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay;
+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd;
+
+ /* Parameters calculated from the extracted DIMM information */
+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks;
+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity;
+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices /
+ pDimmInfo->numOfModuleBanks;
+
+ /* DIMM attributes (MV_TRUE for yes) */
+
+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) ||
+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) )
+ {
+ if (pDimmInfo->dimmAttributes & BIT1)
+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE;
+ else
+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE;
+ }
+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */
+ {
+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4))
+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE;
+ else
+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE;
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1.
+*
+* DESCRIPTION:
+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise.
+*
+*******************************************************************************/
+MV_STATUS dimmSpdCpy(MV_VOID)
+{
+ MV_U32 i;
+ MV_U32 spdChecksum;
+
+ MV_TWSI_SLAVE twsiSlave;
+ MV_U8 data[SPD_SIZE];
+
+ /* zero dimmInfo structure */
+ memset(data, 0, SPD_SIZE);
+
+ /* read the dimm eeprom */
+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n"));
+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL,
+ &twsiSlave, data, SPD_SIZE) )
+ {
+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n"));
+ return MV_FAIL;
+ }
+ DB(puts("DRAM: Reading dimm info succeded.\n"));
+
+ /* calculate SPD checksum */
+ spdChecksum = 0;
+
+ for(i = 0 ; i <= 62 ; i++)
+ {
+ spdChecksum += data[i];
+ }
+
+ if ((spdChecksum & 0xff) != data[63])
+ {
+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n",
+ (MV_U32)(spdChecksum & 0xff), data[63]));
+ }
+ else
+ {
+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n"));
+ }
+
+ /* copy the SPD content 1:1 into the DIMM 1 SPD */
+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ for(i = 0 ; i < SPD_SIZE ; i++)
+ {
+ twsiSlave.offset = i;
+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL,
+ &twsiSlave, &data[i], 1) )
+ {
+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i);
+ return MV_FAIL;
+ }
+ mvOsDelay(5);
+ }
+
+ DB(puts("DRAM: Reading dimm info succeded.\n"));
+ return MV_OK;
+}
+
+/*******************************************************************************
+* dimmSpdGet - Get the SPD parameters.
+*
+* DESCRIPTION:
+* Read the DIMM SPD parameters into given struct parameter.
+*
+* INPUT:
+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
+*
+* OUTPUT:
+* pDimmInfo - DIMM information structure.
+*
+* RETURN:
+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise.
+*
+*******************************************************************************/
+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo)
+{
+ MV_U32 i;
+ MV_U32 density = 1;
+ MV_U32 spdChecksum;
+
+ MV_TWSI_SLAVE twsiSlave;
+ MV_U8 data[SPD_SIZE];
+
+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM))
+ {
+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n"));
+ return MV_BAD_PARAM;
+ }
+
+ /* zero dimmInfo structure */
+ memset(data, 0, SPD_SIZE);
+
+ /* read the dimm eeprom */
+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n"));
+ twsiSlave.slaveAddr.address = (dimmNum == 0) ?
+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL,
+ &twsiSlave, data, SPD_SIZE) )
+ {
+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum));
+ return MV_FAIL;
+ }
+ DB(puts("DRAM: Reading dimm info succeded.\n"));
+
+ /* calculate SPD checksum */
+ spdChecksum = 0;
+
+ for(i = 0 ; i <= 62 ; i++)
+ {
+ spdChecksum += data[i];
+ }
+
+ if ((spdChecksum & 0xff) != data[63])
+ {
+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n",
+ (MV_U32)(spdChecksum & 0xff), data[63]));
+ }
+ else
+ {
+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n"));
+ }
+
+ /* copy the SPD content 1:1 into the dimmInfo structure*/
+ for(i = 0 ; i < SPD_SIZE ; i++)
+ {
+ pDimmInfo->spdRawData[i] = data[i];
+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i]));
+ }
+
+ DB(mvOsPrintf("DRAM SPD Information:\n"));
+
+ /* Memory type (DDR / SDRAM) */
+ switch (data[DIMM_MEM_TYPE])
+ {
+ case (DIMM_MEM_TYPE_SDRAM):
+ pDimmInfo->memoryType = MEM_TYPE_SDRAM;
+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n"));
+ break;
+ case (DIMM_MEM_TYPE_DDR1):
+ pDimmInfo->memoryType = MEM_TYPE_DDR1;
+ DB(mvOsPrintf("DRAM Memeory type DDR1\n"));
+ break;
+ case (DIMM_MEM_TYPE_DDR2):
+ pDimmInfo->memoryType = MEM_TYPE_DDR2;
+ DB(mvOsPrintf("DRAM Memeory type DDR2\n"));
+ break;
+ default:
+ mvOsPrintf("ERROR: Undefined memory type!\n");
+ return MV_ERROR;
+ }
+
+
+ /* Number Of Row Addresses */
+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM];
+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr));
+
+ /* Number Of Column Addresses */
+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM];
+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr));
+
+ /* Number Of Module Banks */
+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM];
+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n",
+ pDimmInfo->numOfModuleBanks));
+
+ /* Number of module banks encoded differently for DDR2 */
+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2)
+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1;
+
+ /* Data Width */
+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH];
+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth));
+
+ /* Minimum Cycle Time At Max CasLatancy */
+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]);
+
+ /* Error Check Type */
+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE];
+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n",
+ pDimmInfo->errorCheckType));
+
+ /* Refresh Interval */
+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL];
+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n",
+ pDimmInfo->refreshInterval));
+
+ /* Sdram Width */
+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH];
+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth));
+
+ /* Error Check Data Width */
+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH];
+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n",
+ pDimmInfo->errorCheckDataWidth));
+
+ /* Burst Length Supported */
+ /* SDRAM/DDR1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 *
+ *********************************************************/
+ /* DDR2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD *
+ *********************************************************/
+
+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP];
+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n",
+ pDimmInfo->burstLengthSupported));
+
+ /* Number Of Banks On Each Device */
+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM];
+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n",
+ pDimmInfo->numOfBanksOnEachDevice));
+
+ /* Suported Cas Latencies */
+
+ /* SDRAM:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
+ ********************************************************/
+
+ /* DDR 1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
+ *********************************************************/
+
+ /* DDR 2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD *
+ *********************************************************/
+
+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL];
+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n",
+ pDimmInfo->suportedCasLatencies));
+
+ /* For DDR2 only, get the DIMM type information */
+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2)
+ {
+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION];
+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n",
+ pDimmInfo->dimmTypeInfo));
+ }
+
+ /* SDRAM Modules Attributes */
+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN];
+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n",
+ pDimmInfo->dimmAttributes));
+
+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps =
+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]);
+
+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps =
+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]);
+
+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME];
+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n",
+ pDimmInfo->minRowPrechargeTime));
+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE];
+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n",
+ pDimmInfo->minRowActiveToRowActive));
+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY];
+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n",
+ pDimmInfo->minRasToCasDelay));
+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH];
+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n",
+ pDimmInfo->minRasPulseWidth));
+
+ /* DIMM Bank Density */
+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY];
+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n",
+ pDimmInfo->dimmBankDensity));
+
+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */
+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME];
+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n",
+ pDimmInfo->minWriteRecoveryTime));
+
+ /* Only DDR2 includes Internal Write To Read Command Delay field. */
+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY];
+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n",
+ pDimmInfo->minWriteToReadCmdDelay));
+
+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */
+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY];
+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n",
+ pDimmInfo->minReadToPrechCmdDelay));
+
+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */
+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD];
+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n",
+ pDimmInfo->minRefreshToActiveCmd));
+
+ /* calculating the sdram density. Representing device density from */
+ /* bit 20 to allow representation of 4GB and above. */
+ /* For example, if density is 512Mbit 0x20000000, will be represent in */
+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */
+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */
+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20));
+ pDimmInfo->deviceDensity = density *
+ pDimmInfo->numOfBanksOnEachDevice *
+ pDimmInfo->sdramWidth;
+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity));
+
+ /* Number of devices includeing Error correction */
+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) *
+ pDimmInfo->numOfModuleBanks;
+ DB(mvOsPrintf("DRAM numberOfDevices %d\n",
+ pDimmInfo->numberOfDevices));
+
+ pDimmInfo->size = 0;
+
+ /* Note that pDimmInfo->size is in MB units */
+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM)
+ {
+ if (pDimmInfo->dimmBankDensity & BIT0)
+ pDimmInfo->size += 1024; /* Equal to 1GB */
+ else if (pDimmInfo->dimmBankDensity & BIT1)
+ pDimmInfo->size += 8; /* Equal to 8MB */
+ else if (pDimmInfo->dimmBankDensity & BIT2)
+ pDimmInfo->size += 16; /* Equal to 16MB */
+ else if (pDimmInfo->dimmBankDensity & BIT3)
+ pDimmInfo->size += 32; /* Equal to 32MB */
+ else if (pDimmInfo->dimmBankDensity & BIT4)
+ pDimmInfo->size += 64; /* Equal to 64MB */
+ else if (pDimmInfo->dimmBankDensity & BIT5)
+ pDimmInfo->size += 128; /* Equal to 128MB */
+ else if (pDimmInfo->dimmBankDensity & BIT6)
+ pDimmInfo->size += 256; /* Equal to 256MB */
+ else if (pDimmInfo->dimmBankDensity & BIT7)
+ pDimmInfo->size += 512; /* Equal to 512MB */
+ }
+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1)
+ {
+ if (pDimmInfo->dimmBankDensity & BIT0)
+ pDimmInfo->size += 1024; /* Equal to 1GB */
+ else if (pDimmInfo->dimmBankDensity & BIT1)
+ pDimmInfo->size += 2048; /* Equal to 2GB */
+ else if (pDimmInfo->dimmBankDensity & BIT2)
+ pDimmInfo->size += 16; /* Equal to 16MB */
+ else if (pDimmInfo->dimmBankDensity & BIT3)
+ pDimmInfo->size += 32; /* Equal to 32MB */
+ else if (pDimmInfo->dimmBankDensity & BIT4)
+ pDimmInfo->size += 64; /* Equal to 64MB */
+ else if (pDimmInfo->dimmBankDensity & BIT5)
+ pDimmInfo->size += 128; /* Equal to 128MB */
+ else if (pDimmInfo->dimmBankDensity & BIT6)
+ pDimmInfo->size += 256; /* Equal to 256MB */
+ else if (pDimmInfo->dimmBankDensity & BIT7)
+ pDimmInfo->size += 512; /* Equal to 512MB */
+ }
+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */
+ {
+ if (pDimmInfo->dimmBankDensity & BIT0)
+ pDimmInfo->size += 1024; /* Equal to 1GB */
+ else if (pDimmInfo->dimmBankDensity & BIT1)
+ pDimmInfo->size += 2048; /* Equal to 2GB */
+ else if (pDimmInfo->dimmBankDensity & BIT2)
+ pDimmInfo->size += 4096; /* Equal to 4GB */
+ else if (pDimmInfo->dimmBankDensity & BIT3)
+ pDimmInfo->size += 8192; /* Equal to 8GB */
+ else if (pDimmInfo->dimmBankDensity & BIT4)
+ pDimmInfo->size += 16384; /* Equal to 16GB */
+ else if (pDimmInfo->dimmBankDensity & BIT5)
+ pDimmInfo->size += 128; /* Equal to 128MB */
+ else if (pDimmInfo->dimmBankDensity & BIT6)
+ pDimmInfo->size += 256; /* Equal to 256MB */
+ else if (pDimmInfo->dimmBankDensity & BIT7)
+ pDimmInfo->size += 512; /* Equal to 512MB */
+ }
+
+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks;
+
+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size));
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* dimmSpdPrint - Print the SPD parameters.
+*
+* DESCRIPTION:
+* Print the Dimm SPD parameters.
+*
+* INPUT:
+* pDimmInfo - DIMM information structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID dimmSpdPrint(MV_U32 dimmNum)
+{
+ MV_DIMM_INFO dimmInfo;
+ MV_U32 i, temp = 0;
+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0;
+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift;
+ MV_U32 busClkPs;
+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks,
+ temp_buf[40], *spdRawData;
+
+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */
+
+ spdRawData = dimmInfo.spdRawData;
+
+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo))
+ {
+ mvOsOutput("ERROR: Could not read SPD information!\n");
+ return;
+ }
+
+ /* find Manufactura of Dimm Module */
+ mvOsOutput("\nManufacturer's JEDEC ID Code: ");
+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++)
+ {
+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]);
+ }
+ mvOsOutput("\n");
+
+ /* Manufacturer's Specific Data */
+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++)
+ {
+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i];
+ }
+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf);
+
+ /* Module Part Number */
+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++)
+ {
+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i];
+ }
+ mvOsOutput("Module Part Number: %s\n", temp_buf);
+
+ /* Module Serial Number */
+ for(i = 0; i < sizeof(MV_U32); i++)
+ {
+ temp |= spdRawData[95+i] << 8*i;
+ }
+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp,
+ (long)temp);
+
+ /* find Manufac-Data of Dimm Module */
+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n",
+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf),
+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf));
+ /* find modul_revision of Dimm Module */
+ mvOsOutput("Module Revision: %d.%d\n",
+ spdRawData[91], spdRawData[92]);
+
+ /* find manufac_place of Dimm Module */
+ mvOsOutput("manufac_place: %d\n", spdRawData[72]);
+
+ /* go over the first 35 I2C data bytes */
+ for(i = 2 ; i <= 35 ; i++)
+ switch(i)
+ {
+ case 2: /* Memory type (DDR1/2 / SDRAM) */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ mvOsOutput("Dram Type is: SDRAM\n");
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ mvOsOutput("Dram Type is: SDRAM DDR1\n");
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ mvOsOutput("Dram Type is: SDRAM DDR2\n");
+ else
+ mvOsOutput("Dram Type unknown\n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 3: /* Number Of Row Addresses */
+ mvOsOutput("Module Number of row addresses: %d\n",
+ dimmInfo.numOfRowAddr);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 4: /* Number Of Column Addresses */
+ mvOsOutput("Module Number of col addresses: %d\n",
+ dimmInfo.numOfColAddr);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 5: /* Number Of Module Banks */
+ mvOsOutput("Number of Banks on Mod.: %d\n",
+ dimmInfo.numOfModuleBanks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 6: /* Data Width */
+ mvOsOutput("Module Data Width: %d bit\n",
+ dimmInfo.dataWidth);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 8: /* Voltage Interface */
+ switch(spdRawData[i])
+ {
+ case 0x0:
+ mvOsOutput("Module is TTL_5V_TOLERANT\n");
+ break;
+ case 0x1:
+ mvOsOutput("Module is LVTTL\n");
+ break;
+ case 0x2:
+ mvOsOutput("Module is HSTL_1_5V\n");
+ break;
+ case 0x3:
+ mvOsOutput("Module is SSTL_3_3V\n");
+ break;
+ case 0x4:
+ mvOsOutput("Module is SSTL_2_5V\n");
+ break;
+ case 0x5:
+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM)
+ {
+ mvOsOutput("Module is SSTL_1_8V\n");
+ break;
+ }
+ default:
+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n");
+ break;
+ }
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 9: /* Minimum Cycle Time At Max CasLatancy */
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ rightOfPoint = (spdRawData[i] & 0x0f) * 10;
+
+ /* DDR2 addition of right of point */
+ if ((spdRawData[i] & 0x0f) == 0xA)
+ {
+ rightOfPoint = 25;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xB)
+ {
+ rightOfPoint = 33;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xC)
+ {
+ rightOfPoint = 66;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xD)
+ {
+ rightOfPoint = 75;
+ }
+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 10: /* Clock To Data Out */
+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100;
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / div;
+ rightOfPoint = time_tmp % div;
+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 11: /* Error Check Type */
+ mvOsOutput("Error Check Type (0=NONE): %d\n",
+ dimmInfo.errorCheckType);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 12: /* Refresh Interval */
+ mvOsOutput("Refresh Rate: %x\n",
+ dimmInfo.refreshInterval);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 13: /* Sdram Width */
+ mvOsOutput("Sdram Width: %d bits\n",
+ dimmInfo.sdramWidth);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 14: /* Error Check Data Width */
+ mvOsOutput("Error Check Data Width: %d bits\n",
+ dimmInfo.errorCheckDataWidth);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 15: /* Minimum Clock Delay is unsupported */
+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) ||
+ (dimmInfo.memoryType == MEM_TYPE_DDR1))
+ {
+ mvOsOutput("Minimum Clk Delay back to back: %d\n",
+ spdRawData[i]);
+ }
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 16: /* Burst Length Supported */
+ /* SDRAM/DDR1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 *
+ *********************************************************/
+ /* DDR2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD *
+ *********************************************************/
+ mvOsOutput("Burst Length Supported: ");
+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) ||
+ (dimmInfo.memoryType == MEM_TYPE_DDR1))
+ {
+ if (dimmInfo.burstLengthSupported & BIT0)
+ mvOsOutput("1, ");
+ if (dimmInfo.burstLengthSupported & BIT1)
+ mvOsOutput("2, ");
+ }
+ if (dimmInfo.burstLengthSupported & BIT2)
+ mvOsOutput("4, ");
+ if (dimmInfo.burstLengthSupported & BIT3)
+ mvOsOutput("8, ");
+
+ mvOsOutput(" Bit \n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 17: /* Number Of Banks On Each Device */
+ mvOsOutput("Number Of Banks On Each Chip: %d\n",
+ dimmInfo.numOfBanksOnEachDevice);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 18: /* Suported Cas Latencies */
+
+ /* SDRAM:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
+ ********************************************************/
+
+ /* DDR 1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
+ *********************************************************/
+
+ /* DDR 2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD *
+ *********************************************************/
+
+ mvOsOutput("Suported Cas Latencies: (CL) ");
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ for (k = 0; k <=7; k++)
+ {
+ if (dimmInfo.suportedCasLatencies & (1 << k))
+ mvOsOutput("%d, ", k+1);
+ }
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if (dimmInfo.suportedCasLatencies & BIT0)
+ mvOsOutput("1, ");
+ if (dimmInfo.suportedCasLatencies & BIT1)
+ mvOsOutput("1.5, ");
+ if (dimmInfo.suportedCasLatencies & BIT2)
+ mvOsOutput("2, ");
+ if (dimmInfo.suportedCasLatencies & BIT3)
+ mvOsOutput("2.5, ");
+ if (dimmInfo.suportedCasLatencies & BIT4)
+ mvOsOutput("3, ");
+ if (dimmInfo.suportedCasLatencies & BIT5)
+ mvOsOutput("3.5, ");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ {
+ if (dimmInfo.suportedCasLatencies & BIT2)
+ mvOsOutput("2, ");
+ if (dimmInfo.suportedCasLatencies & BIT3)
+ mvOsOutput("3, ");
+ if (dimmInfo.suportedCasLatencies & BIT4)
+ mvOsOutput("4, ");
+ if (dimmInfo.suportedCasLatencies & BIT5)
+ mvOsOutput("5, ");
+ }
+ else
+ mvOsOutput("?.?, ");
+ mvOsOutput("\n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 20: /* DDR2 DIMM type info */
+ if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ {
+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4))
+ mvOsOutput("Registered DIMM (RDIMM)\n");
+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5))
+ mvOsOutput("Unbuffered DIMM (UDIMM)\n");
+ else
+ mvOsOutput("Unknown DIMM type.\n");
+ }
+
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 21: /* SDRAM Modules Attributes */
+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n");
+
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ if (dimmInfo.dimmAttributes & BIT0)
+ mvOsOutput(" Buffered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Buffered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT1)
+ mvOsOutput(" Registered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Registered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT2)
+ mvOsOutput(" On-Card PLL (clock): Yes \n");
+ else
+ mvOsOutput(" On-Card PLL (clock): No \n");
+
+ if (dimmInfo.dimmAttributes & BIT3)
+ mvOsOutput(" Bufferd DQMB Input: Yes \n");
+ else
+ mvOsOutput(" Bufferd DQMB Inputs: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT4)
+ mvOsOutput(" Registered DQMB Inputs: Yes \n");
+ else
+ mvOsOutput(" Registered DQMB Inputs: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT5)
+ mvOsOutput(" Differential Clock Input: Yes \n");
+ else
+ mvOsOutput(" Differential Clock Input: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT6)
+ mvOsOutput(" redundant Row Addressing: Yes \n");
+ else
+ mvOsOutput(" redundant Row Addressing: No \n");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if (dimmInfo.dimmAttributes & BIT0)
+ mvOsOutput(" Buffered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Buffered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT1)
+ mvOsOutput(" Registered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Registered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT2)
+ mvOsOutput(" On-Card PLL (clock): Yes \n");
+ else
+ mvOsOutput(" On-Card PLL (clock): No \n");
+
+ if (dimmInfo.dimmAttributes & BIT3)
+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n");
+ else
+ mvOsOutput(" FET Switch On-Card Enabled: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT4)
+ mvOsOutput(" FET Switch External Enabled: Yes \n");
+ else
+ mvOsOutput(" FET Switch External Enabled: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT5)
+ mvOsOutput(" Differential Clock Input: Yes \n");
+ else
+ mvOsOutput(" Differential Clock Input: No \n");
+ }
+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */
+ {
+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n",
+ (dimmInfo.dimmAttributes & 0x3) + 1);
+
+ mvOsOutput(" Number of PLLs on the DIMM: %d\n",
+ ((dimmInfo.dimmAttributes) >> 2) & 0x3);
+
+ if (dimmInfo.dimmAttributes & BIT4)
+ mvOsOutput(" FET Switch External Enabled: Yes \n");
+ else
+ mvOsOutput(" FET Switch External Enabled: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT6)
+ mvOsOutput(" Analysis probe installed: Yes \n");
+ else
+ mvOsOutput(" Analysis probe installed: No \n");
+ }
+
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 22: /* Suported AutoPreCharge */
+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n");
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ if ( spdRawData[i] & BIT0 )
+ mvOsOutput(" Early Ras Precharge: Yes \n");
+ else
+ mvOsOutput(" Early Ras Precharge: No \n");
+
+ if ( spdRawData[i] & BIT1 )
+ mvOsOutput(" AutoPreCharge: Yes \n");
+ else
+ mvOsOutput(" AutoPreCharge: No \n");
+
+ if ( spdRawData[i] & BIT2 )
+ mvOsOutput(" Precharge All: Yes \n");
+ else
+ mvOsOutput(" Precharge All: No \n");
+
+ if ( spdRawData[i] & BIT3 )
+ mvOsOutput(" Write 1/ReadBurst: Yes \n");
+ else
+ mvOsOutput(" Write 1/ReadBurst: No \n");
+
+ if ( spdRawData[i] & BIT4 )
+ mvOsOutput(" lower VCC tolerance: 5%%\n");
+ else
+ mvOsOutput(" lower VCC tolerance: 10%%\n");
+
+ if ( spdRawData[i] & BIT5 )
+ mvOsOutput(" upper VCC tolerance: 5%%\n");
+ else
+ mvOsOutput(" upper VCC tolerance: 10%%\n");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if ( spdRawData[i] & BIT0 )
+ mvOsOutput(" Supports Weak Driver: Yes \n");
+ else
+ mvOsOutput(" Supports Weak Driver: No \n");
+
+ if ( !(spdRawData[i] & BIT4) )
+ mvOsOutput(" lower VCC tolerance: 0.2V\n");
+
+ if ( !(spdRawData[i] & BIT5) )
+ mvOsOutput(" upper VCC tolerance: 0.2V\n");
+
+ if ( spdRawData[i] & BIT6 )
+ mvOsOutput(" Concurrent Auto Preharge: Yes \n");
+ else
+ mvOsOutput(" Concurrent Auto Preharge: No \n");
+
+ if ( spdRawData[i] & BIT7 )
+ mvOsOutput(" Supports Fast AP: Yes \n");
+ else
+ mvOsOutput(" Supports Fast AP: No \n");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ {
+ if ( spdRawData[i] & BIT0 )
+ mvOsOutput(" Supports Weak Driver: Yes \n");
+ else
+ mvOsOutput(" Supports Weak Driver: No \n");
+ }
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 23:
+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ rightOfPoint = (spdRawData[i] & 0x0f) * 10;
+
+ /* DDR2 addition of right of point */
+ if ((spdRawData[i] & 0x0f) == 0xA)
+ {
+ rightOfPoint = 25;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xB)
+ {
+ rightOfPoint = 33;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xC)
+ {
+ rightOfPoint = 66;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xD)
+ {
+ rightOfPoint = 75;
+ }
+
+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy"
+ "(0 = Not supported): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint );
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/
+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100;
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / div;
+ rightOfPoint = time_tmp % div;
+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 25:
+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2;
+ rightOfPoint = (spdRawData[i] & 0x3) * 25;
+ }
+ else /* DDR1 or DDR2 */
+ {
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ rightOfPoint = (spdRawData[i] & 0x0f) * 10;
+
+ /* DDR2 addition of right of point */
+ if ((spdRawData[i] & 0x0f) == 0xA)
+ {
+ rightOfPoint = 25;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xB)
+ {
+ rightOfPoint = 33;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xC)
+ {
+ rightOfPoint = 66;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xD)
+ {
+ rightOfPoint = 75;
+ }
+ }
+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy"
+ "(0 = Not supported): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint );
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2;
+ rightOfPoint = (spdRawData[i] & 0x3) * 25;
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = 0;
+ rightOfPoint = time_tmp;
+ }
+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n",
+ leftOfPoint, rightOfPoint );
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 27: /* Minimum Row Precharge Time */
+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2;
+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0xff : 0xfc;
+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0x00 : 0x03;
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25;
+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/
+ trp_clocks = (temp + (busClkPs-1)) / busClkPs;
+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = "
+ "in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 28: /* Minimum Row Active to Row Active Time */
+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2;
+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0xff : 0xfc;
+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0x00 : 0x03;
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25;
+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/
+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs;
+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: "
+ "%d.%d = in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 29: /* Minimum Ras-To-Cas Delay */
+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2;
+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0xff : 0xfc;
+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0x00 : 0x03;
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25;
+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/
+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs;
+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = "
+ "in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 30: /* Minimum Ras Pulse Width */
+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs;
+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = "
+ "in Clk cycles %d\n", spdRawData[i], tras_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 31: /* Module Bank Density */
+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):");
+
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ if (dimmInfo.dimmBankDensity & BIT0)
+ mvOsOutput("1GB, ");
+ if (dimmInfo.dimmBankDensity & BIT1)
+ mvOsOutput("8MB, ");
+ if (dimmInfo.dimmBankDensity & BIT2)
+ mvOsOutput("16MB, ");
+ if (dimmInfo.dimmBankDensity & BIT3)
+ mvOsOutput("32MB, ");
+ if (dimmInfo.dimmBankDensity & BIT4)
+ mvOsOutput("64MB, ");
+ if (dimmInfo.dimmBankDensity & BIT5)
+ mvOsOutput("128MB, ");
+ if (dimmInfo.dimmBankDensity & BIT6)
+ mvOsOutput("256MB, ");
+ if (dimmInfo.dimmBankDensity & BIT7)
+ mvOsOutput("512MB, ");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if (dimmInfo.dimmBankDensity & BIT0)
+ mvOsOutput("1GB, ");
+ if (dimmInfo.dimmBankDensity & BIT1)
+ mvOsOutput("2GB, ");
+ if (dimmInfo.dimmBankDensity & BIT2)
+ mvOsOutput("16MB, ");
+ if (dimmInfo.dimmBankDensity & BIT3)
+ mvOsOutput("32MB, ");
+ if (dimmInfo.dimmBankDensity & BIT4)
+ mvOsOutput("64MB, ");
+ if (dimmInfo.dimmBankDensity & BIT5)
+ mvOsOutput("128MB, ");
+ if (dimmInfo.dimmBankDensity & BIT6)
+ mvOsOutput("256MB, ");
+ if (dimmInfo.dimmBankDensity & BIT7)
+ mvOsOutput("512MB, ");
+ }
+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */
+ {
+ if (dimmInfo.dimmBankDensity & BIT0)
+ mvOsOutput("1GB, ");
+ if (dimmInfo.dimmBankDensity & BIT1)
+ mvOsOutput("2GB, ");
+ if (dimmInfo.dimmBankDensity & BIT2)
+ mvOsOutput("4GB, ");
+ if (dimmInfo.dimmBankDensity & BIT3)
+ mvOsOutput("8GB, ");
+ if (dimmInfo.dimmBankDensity & BIT4)
+ mvOsOutput("16GB, ");
+ if (dimmInfo.dimmBankDensity & BIT5)
+ mvOsOutput("128MB, ");
+ if (dimmInfo.dimmBankDensity & BIT6)
+ mvOsOutput("256MB, ");
+ if (dimmInfo.dimmBankDensity & BIT7)
+ mvOsOutput("512MB, ");
+ }
+ mvOsOutput("\n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 32: /* Address And Command Setup Time (measured in ns/1000) */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 33: /* Address And Command Hold Time */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 34: /* Data Input Setup Time */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 35: /* Data Input Hold Time */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 36: /* Relevant for DDR2 only: Write Recovery Time */
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25;
+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+ }
+
+}
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into ps unit values
+ */
+/*******************************************************************************
+* cas2ps - Translate x.y ns parameter to pico-seconds values
+*
+* DESCRIPTION:
+* This function translates x.y nano seconds to its value in pico seconds.
+* For example 3.75ns will return 3750.
+*
+* INPUT:
+* spd_byte - DIMM SPD byte.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* value in pico seconds.
+*
+*******************************************************************************/
+static MV_U32 cas2ps(MV_U8 spd_byte)
+{
+ MV_U32 ns, ns10;
+
+ /* isolate upper nibble */
+ ns = (spd_byte >> 4) & 0x0F;
+ /* isolate lower nibble */
+ ns10 = (spd_byte & 0x0F);
+
+ if( ns10 < 10 ) {
+ ns10 *= 10;
+ }
+ else if( ns10 == 10 )
+ ns10 = 25;
+ else if( ns10 == 11 )
+ ns10 = 33;
+ else if( ns10 == 12 )
+ ns10 = 66;
+ else if( ns10 == 13 )
+ ns10 = 75;
+ else
+ {
+ mvOsOutput("cas2ps Err. unsupported cycle time.\n");
+ }
+
+ return (ns*1000 + ns10*10);
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h
new file mode 100644
index 000000000..678e22456
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h
@@ -0,0 +1,191 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDram
+#define __INCmvDram
+
+#include "ddr1_2/mvDramIf.h"
+#include "twsi/mvTwsi.h"
+
+#define MAX_DIMM_NUM 2
+#define SPD_SIZE 128
+
+/* Dimm spd offsets */
+#define DIMM_MEM_TYPE 2
+#define DIMM_ROW_NUM 3
+#define DIMM_COL_NUM 4
+#define DIMM_MODULE_BANK_NUM 5
+#define DIMM_DATA_WIDTH 6
+#define DIMM_VOLT_IF 8
+#define DIMM_MIN_CC_AT_MAX_CAS 9
+#define DIMM_ERR_CHECK_TYPE 11
+#define DIMM_REFRESH_INTERVAL 12
+#define DIMM_SDRAM_WIDTH 13
+#define DIMM_ERR_CHECK_DATA_WIDTH 14
+#define DIMM_MIN_CLK_DEL 15
+#define DIMM_BURST_LEN_SUP 16
+#define DIMM_DEV_BANK_NUM 17
+#define DIMM_SUP_CAL 18
+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */
+#define DIMM_BUF_ADDR_CONT_IN 21
+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23
+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25
+#define DIMM_MIN_ROW_PRECHARGE_TIME 27
+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28
+#define DIMM_MIN_RAS_TO_CAS_DELAY 29
+#define DIMM_MIN_RAS_PULSE_WIDTH 30
+#define DIMM_BANK_DENSITY 31
+#define DIMM_MIN_WRITE_RECOVERY_TIME 36
+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37
+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38
+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42
+
+/* Dimm Memory Type values */
+#define DIMM_MEM_TYPE_SDRAM 0x4
+#define DIMM_MEM_TYPE_DDR1 0x7
+#define DIMM_MEM_TYPE_DDR2 0x8
+
+#define DIMM_MODULE_MANU_OFFS 64
+#define DIMM_MODULE_MANU_SIZE 8
+#define DIMM_MODULE_VEN_OFFS 73
+#define DIMM_MODULE_VEN_SIZE 25
+#define DIMM_MODULE_ID_OFFS 99
+#define DIMM_MODULE_ID_SIZE 18
+
+/* enumeration for voltage levels. */
+typedef enum _mvDimmVoltageIf
+{
+ TTL_5V_TOLERANT,
+ LVTTL,
+ HSTL_1_5V,
+ SSTL_3_3V,
+ SSTL_2_5V,
+ VOLTAGE_UNKNOWN,
+} MV_DIMM_VOLTAGE_IF;
+
+
+/* enumaration for SDRAM CAS Latencies. */
+typedef enum _mvDimmSdramCas
+{
+ SD_CL_1 =1,
+ SD_CL_2,
+ SD_CL_3,
+ SD_CL_4,
+ SD_CL_5,
+ SD_CL_6,
+ SD_CL_7,
+ SD_FAULT
+}MV_DIMM_SDRAM_CAS;
+
+
+/* DIMM information structure */
+typedef struct _mvDimmInfo
+{
+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */
+
+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */
+
+ /* DIMM dimensions */
+ MV_U32 numOfRowAddr;
+ MV_U32 numOfColAddr;
+ MV_U32 numOfModuleBanks;
+ MV_U32 dataWidth;
+ MV_U32 errorCheckType; /* ECC , PARITY..*/
+ MV_U32 sdramWidth; /* 4,8,16 or 32 */
+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
+ MV_U32 burstLengthSupported;
+ MV_U32 numOfBanksOnEachDevice;
+ MV_U32 suportedCasLatencies;
+ MV_U32 refreshInterval;
+ MV_U32 dimmBankDensity;
+ MV_U32 dimmTypeInfo; /* DDR2 only */
+ MV_U32 dimmAttributes;
+
+ /* DIMM timing parameters */
+ MV_U32 minCycleTimeAtMaxCasLatPs;
+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
+ MV_U32 minRowPrechargeTime;
+ MV_U32 minRowActiveToRowActive;
+ MV_U32 minRasToCasDelay;
+ MV_U32 minRasPulseWidth;
+ MV_U32 minWriteRecoveryTime; /* DDR2 only */
+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */
+
+ /* Parameters calculated from the extracted DIMM information */
+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */
+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */
+ MV_U32 numberOfDevices;
+
+} MV_DIMM_INFO;
+
+
+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo);
+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo);
+MV_VOID dimmSpdPrint(MV_U32 dimmNum);
+MV_STATUS dimmSpdCpy(MV_VOID);
+
+#endif /* __INCmvDram */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c
new file mode 100644
index 000000000..12fb26ad0
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c
@@ -0,0 +1,1599 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#include "ddr1_2/mvDramIf.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+
+
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+/* DRAM bank presence encoding */
+#define BANK_PRESENT_CS0 0x1
+#define BANK_PRESENT_CS0_CS1 0x3
+#define BANK_PRESENT_CS0_CS2 0x5
+#define BANK_PRESENT_CS0_CS1_CS2 0x7
+#define BANK_PRESENT_CS0_CS2_CS3 0xd
+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf
+
+/* locals */
+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin);
+#if defined(MV_INC_BOARD_DDIM)
+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo);
+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas);
+static MV_U32 sdramModeRegCalc(MV_U32 minCas);
+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo);
+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo);
+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk);
+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk,
+ MV_U32 forcedCl);
+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo,
+ MV_U32 minCas, MV_U32 busClk);
+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo,
+ MV_U32 busClk);
+
+/*******************************************************************************
+* mvDramIfDetect - Prepare DRAM interface configuration values.
+*
+* DESCRIPTION:
+* This function implements the full DRAM detection and timing
+* configuration for best system performance.
+* Since this routine runs from a ROM device (Boot Flash), its stack
+* resides on RAM, that might be the system DRAM. Changing DRAM
+* configuration values while keeping vital data in DRAM is risky. That
+* is why the function does not preform the configuration setting but
+* prepare those in predefined 32bit registers (in this case IDMA
+* registers are used) for other routine to perform the settings.
+* The function will call for board DRAM SPD information for each DRAM
+* chip select. The function will then analyze those SPD parameters of
+* all DRAM banks in order to decide on DRAM configuration compatible
+* for all DRAM banks.
+* The function will set the CPU DRAM address decode registers.
+* Note: This routine prepares values that will overide configuration of
+* mvDramBasicAsmInit().
+*
+* INPUT:
+* forcedCl - Forced CAL Latency. If equal to zero, do not force.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvDramIfDetect(MV_U32 forcedCl)
+{
+ MV_U32 retVal = MV_OK; /* return value */
+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS];
+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW;
+ MV_U8 minCas;
+ MV_DRAM_DEC_WIN dramDecWin;
+
+ dramDecWin.addrWin.baseHigh = 0;
+
+ busClk = mvBoardSysClkGet();
+
+ if (0 == busClk)
+ {
+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n");
+ return MV_ERROR;
+ }
+
+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */
+#if defined(MV_INCLUDE_SDRAM_CS1)
+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++)
+ mvCpuIfTargetWinEnable(i, MV_FALSE);
+#endif
+
+ /* we will use bank 0 as the representative of the all the DRAM banks, */
+ /* since bank 0 must exist. */
+ for(i = 0; i < MV_DRAM_MAX_CS; i++)
+ {
+ /* if Bank exist */
+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i]))
+ {
+ /* check it isn't SDRAM */
+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM)
+ {
+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n");
+ return MV_ERROR;
+ }
+ /* All banks must support registry in order to activate it */
+ if(bankInfo[i].registeredAddrAndControlInputs !=
+ bankInfo[0].registeredAddrAndControlInputs)
+ {
+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n");
+ return MV_ERROR;
+ }
+
+ /* Init the CPU window decode */
+ /* Note that the size in Bank info is in MB units */
+ /* Note that the Dimm width might be different then the device DRAM width */
+ temp = MV_REG_READ(SDRAM_CONFIG_REG);
+
+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32;
+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16);
+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW));
+
+ /* We can not change DRAM window settings while excecuting */
+ /* code from it. That is why we skip the DRAM CS[0], saving */
+ /* it to the ROM configuration routine */
+ if(i == SDRAM_CS0)
+ {
+ MV_U32 sizeToReg;
+
+ /* Translate the given window size to register format */
+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT);
+
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n"
+ ,i);
+ return MV_BAD_PARAM;
+ }
+
+ /* Size is located at upper 16 bits */
+ sizeToReg <<= SCSR_SIZE_OFFS;
+
+ /* enable it */
+ sizeToReg |= SCSR_WIN_EN;
+
+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg);
+ }
+ else
+ {
+ dramDecWin.addrWin.baseLow = base;
+ dramDecWin.addrWin.size = size;
+ dramDecWin.enable = MV_TRUE;
+
+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin))
+ {
+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n",
+ SDRAM_CS0 + i);
+ return MV_ERROR;
+ }
+ }
+
+ base += size;
+
+ /* update the suportedCasLatencies mask */
+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies;
+
+ }
+ else
+ {
+ if( i == 0 ) /* bank 0 doesn't exist */
+ {
+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n");
+ return MV_ERROR;
+ }
+ else
+ {
+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i));
+ bankInfo[i].size = 0; /* Mark this bank as non exist */
+ }
+ }
+ }
+
+ /* calculate minimum CAS */
+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl);
+ if (0 == minCas)
+ {
+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n",
+ (busClk / 1000000));
+
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ minCas = DDR2_CL_4; /* Continue with this CAS */
+ mvOsPrintf("Set default CAS latency 4\n");
+ }
+ else
+ {
+ minCas = DDR1_CL_3; /* Continue with this CAS */
+ mvOsPrintf("Set default CAS latency 3\n");
+ }
+ }
+
+ /* calc SDRAM_CONFIG_REG and save it to temp register */
+ temp = sdramConfigRegCalc(&bankInfo[0], busClk);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG1, temp);
+
+ /* calc SDRAM_MODE_REG and save it to temp register */
+ temp = sdramModeRegCalc(minCas);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG2, temp);
+
+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */
+ temp = sdramExtModeRegCalc(&bankInfo[0]);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG10, temp);
+
+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */
+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG3, temp);
+
+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */
+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG4, temp);
+
+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */
+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG5, temp);
+
+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */
+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk);
+ if(-1 == temp)
+ {
+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG6, temp);
+
+ /* Config DDR2 On Die Termination (ODT) registers */
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ sdramDDr2OdtConfig(bankInfo);
+ }
+
+ /* Note that DDR SDRAM Address/Control and Data pad calibration */
+ /* settings is done in mvSdramIfConfig.s */
+
+ return retVal;
+}
+
+/*******************************************************************************
+* minCasCalc - Calculate the Minimum CAS latency which can be used.
+*
+* DESCRIPTION:
+* Calculate the minimum CAS latency that can be used, base on the DRAM
+* parameters and the SDRAM bus Clock freq.
+*
+* INPUT:
+* busClk - the DRAM bus Clock.
+* pBankInfo - bank info parameters.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* The minimum CAS Latency. The function returns 0 if max CAS latency
+* supported by banks is incompatible with system bus clock frequancy.
+*
+*******************************************************************************/
+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk,
+ MV_U32 forcedCl)
+{
+ MV_U32 count = 1, j;
+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */
+ MV_U32 startBit, stopBit;
+
+ /* DDR 1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
+ *********************************************************/
+
+ /* DDR 2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD *
+ *********************************************************/
+
+
+ /* If we are asked to use the forced CAL */
+ if (forcedCl)
+ {
+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10),
+ (forcedCl % 10));
+
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ if (forcedCl == 30)
+ pBankInfo->suportedCasLatencies = 0x08;
+ else if (forcedCl == 40)
+ pBankInfo->suportedCasLatencies = 0x10;
+ else
+ {
+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n",
+ (forcedCl / 10), (forcedCl % 10));
+ pBankInfo->suportedCasLatencies = 0x10;
+ }
+ }
+ else
+ {
+ if (forcedCl == 15)
+ pBankInfo->suportedCasLatencies = 0x02;
+ else if (forcedCl == 20)
+ pBankInfo->suportedCasLatencies = 0x04;
+ else if (forcedCl == 25)
+ pBankInfo->suportedCasLatencies = 0x08;
+ else if (forcedCl == 30)
+ pBankInfo->suportedCasLatencies = 0x10;
+ else if (forcedCl == 40)
+ pBankInfo->suportedCasLatencies = 0x40;
+ else
+ {
+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n",
+ (forcedCl / 10), (forcedCl % 10));
+ pBankInfo->suportedCasLatencies = 0x10;
+ }
+ }
+
+ return pBankInfo->suportedCasLatencies;
+ }
+
+ /* go over the supported cas mask from Max Cas down and check if the */
+ /* SysClk stands in its time requirments. */
+
+
+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n",
+ pBankInfo->suportedCasLatencies,busClkPs ));
+ for(j = 7; j > 0; j--)
+ {
+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
+ {
+ /* Reset the bits for CL incompatible for the sysClk */
+ switch (count)
+ {
+ case 1:
+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs)
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ case 2:
+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs)
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ case 3:
+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs)
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ default:
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ break;
+ }
+ }
+ }
+
+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n",
+ pBankInfo->suportedCasLatencies ));
+
+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */
+ /* SDRAM DDR2 controller supports CL 3 to 5 */
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */
+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */
+ }
+ else
+ {
+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */
+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */
+ }
+
+ for(j = startBit; j <= stopBit ; j++)
+ {
+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
+ {
+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j)));
+ return (BIT0 << j);
+ }
+ }
+
+ return 0;
+}
+
+/*******************************************************************************
+* sdramConfigRegCalc - Calculate sdram config register
+*
+* DESCRIPTION: Calculate sdram config register optimized value based
+* on the bank info parameters.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram config reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk)
+{
+ MV_U32 sdramConfig = 0;
+ MV_U32 refreshPeriod;
+
+ busClk /= 1000000; /* we work with busClk in MHz */
+
+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG);
+
+ /* figure out the memory refresh internal */
+ switch (pBankInfo->refreshInterval & 0xf)
+ {
+ case 0x0: /* refresh period is 15.625 usec */
+ refreshPeriod = 15625;
+ break;
+ case 0x1: /* refresh period is 3.9 usec */
+ refreshPeriod = 3900;
+ break;
+ case 0x2: /* refresh period is 7.8 usec */
+ refreshPeriod = 7800;
+ break;
+ case 0x3: /* refresh period is 31.3 usec */
+ refreshPeriod = 31300;
+ break;
+ case 0x4: /* refresh period is 62.5 usec */
+ refreshPeriod = 62500;
+ break;
+ case 0x5: /* refresh period is 125 usec */
+ refreshPeriod = 125000;
+ break;
+ default: /* refresh period undefined */
+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n");
+ return -1;
+ }
+
+ /* Now the refreshPeriod is in register format value */
+ refreshPeriod = (busClk * refreshPeriod) / 1000;
+
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n",
+ refreshPeriod));
+
+ /* make sure the refresh value is only 14 bits */
+ if(refreshPeriod > SDRAM_REFRESH_MAX)
+ {
+ refreshPeriod = SDRAM_REFRESH_MAX;
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n",
+ refreshPeriod));
+ }
+
+ /* Clear the refresh field */
+ sdramConfig &= ~SDRAM_REFRESH_MASK;
+
+ /* Set new value to refresh field */
+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK);
+
+ /* registered DRAM ? */
+ if ( pBankInfo->registeredAddrAndControlInputs )
+ {
+ /* it's registered DRAM, so set the reg. DRAM bit */
+ sdramConfig |= SDRAM_REGISTERED;
+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");
+ }
+
+ /* set DDR SDRAM devices configuration */
+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */
+
+ switch (pBankInfo->sdramWidth)
+ {
+ case 8: /* memory is x8 */
+ sdramConfig |= SDRAM_DCFG_X8_DEV;
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n"));
+ break;
+ case 16:
+ sdramConfig |= SDRAM_DCFG_X16_DEV;
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n"));
+ break;
+ default: /* memory width unsupported */
+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n");
+ return -1;
+ }
+
+ /* Set static default settings */
+ sdramConfig |= SDRAM_CONFIG_DV;
+
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n",
+ sdramConfig));
+
+ return sdramConfig;
+}
+
+/*******************************************************************************
+* sdramModeRegCalc - Calculate sdram mode register
+*
+* DESCRIPTION: Calculate sdram mode register optimized value based
+* on the bank info parameters and the minCas.
+*
+* INPUT:
+* minCas - minimum CAS supported.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram mode reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramModeRegCalc(MV_U32 minCas)
+{
+ MV_U32 sdramMode;
+
+ sdramMode = MV_REG_READ(SDRAM_MODE_REG);
+
+ /* Clear CAS Latency field */
+ sdramMode &= ~SDRAM_CL_MASK;
+
+ mvOsPrintf("DRAM CAS Latency ");
+
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ switch (minCas)
+ {
+ case DDR2_CL_3:
+ sdramMode |= SDRAM_DDR2_CL_3;
+ mvOsPrintf("3.\n");
+ break;
+ case DDR2_CL_4:
+ sdramMode |= SDRAM_DDR2_CL_4;
+ mvOsPrintf("4.\n");
+ break;
+ case DDR2_CL_5:
+ sdramMode |= SDRAM_DDR2_CL_5;
+ mvOsPrintf("5.\n");
+ break;
+ default:
+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n");
+ return -1;
+ }
+ sdramMode |= DDR2_MODE_REG_DV;
+ }
+ else /* DDR1 */
+ {
+ switch (minCas)
+ {
+ case DDR1_CL_1_5:
+ sdramMode |= SDRAM_DDR1_CL_1_5;
+ mvOsPrintf("1.5\n");
+ break;
+ case DDR1_CL_2:
+ sdramMode |= SDRAM_DDR1_CL_2;
+ mvOsPrintf("2\n");
+ break;
+ case DDR1_CL_2_5:
+ sdramMode |= SDRAM_DDR1_CL_2_5;
+ mvOsPrintf("2.5\n");
+ break;
+ case DDR1_CL_3:
+ sdramMode |= SDRAM_DDR1_CL_3;
+ mvOsPrintf("3\n");
+ break;
+ case DDR1_CL_4:
+ sdramMode |= SDRAM_DDR1_CL_4;
+ mvOsPrintf("4\n");
+ break;
+ default:
+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n");
+ return -1;
+ }
+ sdramMode |= DDR1_MODE_REG_DV;
+ }
+
+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode ));
+
+ return sdramMode;
+}
+
+/*******************************************************************************
+* sdramExtModeRegCalc - Calculate sdram Extended mode register
+*
+* DESCRIPTION:
+* Return sdram Extended mode register value based
+* on the bank info parameters and bank presence.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram Extended mode reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo)
+{
+ MV_U32 populateBanks = 0;
+ int bankNum;
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ /* Represent the populate banks in binary form */
+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ if (0 != pBankInfo[bankNum].size)
+ {
+ populateBanks |= (1 << bankNum);
+ }
+ }
+
+ switch(populateBanks)
+ {
+ case(BANK_PRESENT_CS0):
+ return DDR_SDRAM_EXT_MODE_CS0_DV;
+
+ case(BANK_PRESENT_CS0_CS1):
+ return DDR_SDRAM_EXT_MODE_CS0_DV;
+
+ case(BANK_PRESENT_CS0_CS2):
+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV;
+
+ case(BANK_PRESENT_CS0_CS1_CS2):
+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV;
+
+ case(BANK_PRESENT_CS0_CS2_CS3):
+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV;
+
+ case(BANK_PRESENT_CS0_CS2_CS3_CS4):
+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV;
+
+ default:
+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n");
+ return -1;
+ }
+ }
+ return 0;
+}
+
+/*******************************************************************************
+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register
+*
+* DESCRIPTION: Calculate sdram dunit control low register optimized value based
+* on the bank info parameters and the minCas.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* minCas - minimum CAS supported.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram dunit control low reg value.
+*
+*******************************************************************************/
+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas)
+{
+ MV_U32 dunitCtrlLow;
+
+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG);
+
+ /* Clear StBurstDel field */
+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK;
+
+#ifdef MV_88W8660
+ /* Clear address/control output timing field */
+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE;
+#endif /* MV_88W8660 */
+
+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n"));
+
+ /* For proper sample of read data set the Dunit Control register's */
+ /* stBurstDel bits [27:24] */
+ /********-********-********-********-********-*********
+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 *
+ *********-********-********-********-********-*********
+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD *
+ *********-********-********-********-********-*********
+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD *
+ *********-********-********-********-********-*********/
+
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ switch (minCas)
+ {
+ case DDR2_CL_3:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ case DDR2_CL_4:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ default:
+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n",
+ minCas);
+ return -1;
+ }
+ }
+ else /* DDR1 */
+ {
+ switch (minCas)
+ {
+ case DDR1_CL_1_5:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ case DDR1_CL_2:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ case DDR1_CL_2_5:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ case DDR1_CL_3:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ case DDR1_CL_4:
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS;
+ else
+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS;
+ break;
+ default:
+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n",
+ minCas);
+ return -1;
+ }
+
+ }
+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow ));
+
+ return dunitCtrlLow;
+}
+
+/*******************************************************************************
+* sdramAddrCtrlRegCalc - Calculate sdram address control register
+*
+* DESCRIPTION: Calculate sdram address control register optimized value based
+* on the bank info parameters and the minCas.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram address control reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo)
+{
+ MV_U32 addrCtrl = 0;
+
+ /* Set Address Control register static configuration bits */
+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG);
+
+ /* Set address control default value */
+ addrCtrl |= SDRAM_ADDR_CTRL_DV;
+
+ /* Clear DSize field */
+ addrCtrl &= ~SDRAM_DSIZE_MASK;
+
+ /* Note that density is in MB units */
+ switch (pBankInfo->deviceDensity)
+ {
+ case 128: /* 128 Mbit */
+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_128Mb;
+ break;
+ case 256: /* 256 Mbit */
+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_256Mb;
+ break;
+ case 512: /* 512 Mbit */
+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_512Mb;
+ break;
+ default:
+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n",
+ pBankInfo->deviceDensity);
+ return -1;
+ }
+
+ /* SDRAM address control */
+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl));
+
+ return addrCtrl;
+}
+
+/*******************************************************************************
+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register
+*
+* DESCRIPTION:
+* This function calculates sdram timing control low register
+* optimized value based on the bank info parameters and the minCas.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* busClk - Bus clock
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram timinf control low reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo,
+ MV_U32 minCas, MV_U32 busClk)
+{
+ MV_U32 tRp = 0;
+ MV_U32 tRrd = 0;
+ MV_U32 tRcd = 0;
+ MV_U32 tRas = 0;
+ MV_U32 tWr = 0;
+ MV_U32 tWtr = 0;
+ MV_U32 tRtp = 0;
+
+ MV_U32 bankNum;
+
+ busClk = busClk / 1000000; /* In MHz */
+
+ /* Scan all DRAM banks to find maximum timing values */
+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime);
+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive);
+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay);
+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth);
+ }
+
+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */
+ /* by shifting the data two bits right. */
+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */
+ tRrd = tRrd >> 2;
+ tRcd = tRcd >> 2;
+
+ /* Extract clock cycles from time parameter. We need to round up */
+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0);
+ /* Micron work around for 133MHz */
+ if (busClk == 133)
+ tRp += 1;
+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp));
+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0);
+ /* JEDEC min reqeirments tRrd = 2 */
+ if (tRrd < 2)
+ tRrd = 2;
+ DB(mvOsPrintf("tRrd = %d ", tRrd));
+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("tRcd = %d ", tRcd));
+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("tRas = %d ", tRas));
+
+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ /* Scan all DRAM banks to find maximum timing values */
+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime);
+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay);
+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay);
+ }
+
+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */
+ /* part by shifting the data two bits right. */
+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */
+ tWtr = tWtr >> 2;
+ tRtp = tRtp >> 2;
+
+ /* Extract clock cycles from time parameter. We need to round up */
+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("tWr = %d ", tWr));
+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0);
+ /* JEDEC min reqeirments tWtr = 2 */
+ if (tWtr < 2)
+ tWtr = 2;
+ DB(mvOsPrintf("tWtr = %d ", tWtr));
+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0);
+ /* JEDEC min reqeirments tRtp = 2 */
+ if (tRtp < 2)
+ tRtp = 2;
+ DB(mvOsPrintf("tRtp = %d ", tRtp));
+ }
+ else
+ {
+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0);
+
+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas)))
+ {
+ tWtr = 2;
+ }
+ else
+ {
+ tWtr = 1;
+ }
+
+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */
+ }
+
+ DB(mvOsPrintf("tWtr = %d\n", tWtr));
+
+ /* Note: value of 0 in register means one cycle, 1 means two and so on */
+ return (((tRp - 1) << SDRAM_TRP_OFFS) |
+ ((tRrd - 1) << SDRAM_TRRD_OFFS) |
+ ((tRcd - 1) << SDRAM_TRCD_OFFS) |
+ ((tRas - 1) << SDRAM_TRAS_OFFS) |
+ ((tWr - 1) << SDRAM_TWR_OFFS) |
+ ((tWtr - 1) << SDRAM_TWTR_OFFS) |
+ ((tRtp - 1) << SDRAM_TRTP_OFFS));
+}
+
+/*******************************************************************************
+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register
+*
+* DESCRIPTION:
+* This function calculates sdram timing control high register
+* optimized value based on the bank info parameters and the bus clock.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* busClk - Bus clock
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram timinf control high reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo,
+ MV_U32 busClk)
+{
+ MV_U32 tRfc;
+ MV_U32 timeNs = 0;
+ int bankNum;
+ MV_U32 sdramTw2wCyc = 0;
+
+ busClk = busClk / 1000000; /* In MHz */
+
+ /* tRfc is different for DDR1 and DDR2. */
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
+ {
+ MV_U32 bankNum;
+
+ /* Scan all DRAM banks to find maximum timing values */
+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd);
+ }
+ else
+ {
+ if (pBankInfo[0].deviceDensity == _1G)
+ {
+ timeNs = SDRAM_TRFC_1G;
+ }
+ else
+ {
+ if (200 == busClk)
+ {
+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ;
+ }
+ else
+ {
+ timeNs = SDRAM_TRFC_64_512M;
+ }
+ }
+ }
+
+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0);
+
+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc));
+
+
+ /* Represent the populate banks in binary form */
+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ if (0 != pBankInfo[bankNum].size)
+ sdramTw2wCyc++;
+ }
+
+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */
+ if (sdramTw2wCyc > 1)
+ sdramTw2wCyc = 1;
+ else
+ sdramTw2wCyc = 0;
+
+ /* Note: value of 0 in register means one cycle, 1 means two and so on */
+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) |
+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) |
+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) |
+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) |
+ (sdramTw2wCyc << SDRAM_TW2W_OFFS));
+
+}
+
+/*******************************************************************************
+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers.
+*
+* DESCRIPTION:
+* This function config DDR2 On Die Termination (ODT) registers.
+* ODT configuration is done according to DIMM presence:
+*
+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode
+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440
+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440
+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404
+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404
+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404
+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404
+*
+* INPUT:
+* pBankInfo - bank info parameters.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* None
+*******************************************************************************/
+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo)
+{
+ MV_U32 populateBanks = 0;
+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl;
+ int bankNum;
+
+ /* Represent the populate banks in binary form */
+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ if (0 != pBankInfo[bankNum].size)
+ {
+ populateBanks |= (1 << bankNum);
+ }
+ }
+
+ switch(populateBanks)
+ {
+ case(BANK_PRESENT_CS0):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV;
+ break;
+ case(BANK_PRESENT_CS0_CS1):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV;
+ break;
+ case(BANK_PRESENT_CS0_CS2):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV;
+ break;
+ case(BANK_PRESENT_CS0_CS1_CS2):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV;
+ break;
+ case(BANK_PRESENT_CS0_CS2_CS3):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV;
+ break;
+ case(BANK_PRESENT_CS0_CS2_CS3_CS4):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV;
+ break;
+ default:
+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n");
+ return;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow);
+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh);
+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl);
+ return;
+}
+#endif /* defined(MV_INC_BOARD_DDIM) */
+
+/*******************************************************************************
+* mvDramIfWinSet - Set DRAM interface address decode window
+*
+* DESCRIPTION:
+* This function sets DRAM interface address decode window.
+*
+* INPUT:
+* target - System target. Use only SDRAM targets.
+* pAddrDecWin - SDRAM address window structure.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
+* otherwise.
+*******************************************************************************/
+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
+{
+ MV_U32 baseReg=0,sizeReg=0;
+ MV_U32 baseToReg=0 , sizeToReg=0;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(target))
+ {
+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the requested window overlaps with current enabled windows */
+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin))
+ {
+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target);
+ return MV_BAD_PARAM;
+ }
+
+ /* check if address is aligned to the size */
+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
+ {
+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\
+ "\nAddress 0x%08x is unaligned to size 0x%x.\n",
+ target,
+ pAddrDecWin->addrWin.baseLow,
+ pAddrDecWin->addrWin.size);
+ return MV_ERROR;
+ }
+
+ /* read base register*/
+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target));
+
+ /* read size register */
+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target));
+
+ /* BaseLow[31:16] => base register [31:16] */
+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK;
+
+ /* Write to address decode Base Address Register */
+ baseReg &= ~SCBAR_BASE_MASK;
+ baseReg |= baseToReg;
+
+ /* Translate the given window size to register format */
+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT);
+
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target);
+ return MV_BAD_PARAM;
+ }
+
+ /* set size */
+ sizeReg &= ~SCSR_SIZE_MASK;
+ /* Size is located at upper 16 bits */
+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS);
+
+ /* enable/Disable */
+ if (MV_TRUE == pAddrDecWin->enable)
+ {
+ sizeReg |= SCSR_WIN_EN;
+ }
+ else
+ {
+ sizeReg &= ~SCSR_WIN_EN;
+ }
+
+ /* 3) Write to address decode Base Address Register */
+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg);
+
+ /* Write to address decode Size Register */
+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg);
+
+ return MV_OK;
+}
+/*******************************************************************************
+* mvDramIfWinGet - Get DRAM interface address decode window
+*
+* DESCRIPTION:
+* This function gets DRAM interface address decode window.
+*
+* INPUT:
+* target - System target. Use only SDRAM targets.
+*
+* OUTPUT:
+* pAddrDecWin - SDRAM address window structure.
+*
+* RETURN:
+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK
+* otherwise.
+*******************************************************************************/
+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin)
+{
+ MV_U32 baseReg,sizeReg;
+ MV_U32 sizeRegVal;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(target))
+ {
+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ /* Read base and size registers */
+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target));
+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target));
+
+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS;
+
+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal,
+ SCSR_SIZE_ALIGNMENT);
+
+ /* Check if ctrlRegToSize returned OK */
+ if (-1 == pAddrDecWin->addrWin.size)
+ {
+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ /* Extract base address */
+ /* Base register [31:16] ==> baseLow[31:16] */
+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK;
+
+ pAddrDecWin->addrWin.baseHigh = 0;
+
+
+ if (sizeReg & SCSR_WIN_EN)
+ {
+ pAddrDecWin->enable = MV_TRUE;
+ }
+ else
+ {
+ pAddrDecWin->enable = MV_FALSE;
+ }
+
+ return MV_OK;
+}
+/*******************************************************************************
+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window
+*
+* DESCRIPTION:
+* This function enable/Disable SDRAM address decode window.
+*
+* INPUT:
+* target - System target. Use only SDRAM targets.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_ERROR in case function parameter are invalid, MV_OK otherewise.
+*
+*******************************************************************************/
+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable)
+{
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(target))
+ {
+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target);
+ return MV_ERROR;
+ }
+
+ if (enable == MV_TRUE)
+ { /* First check for overlap with other enabled windows */
+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin))
+ {
+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n",
+ target);
+ return MV_ERROR;
+ }
+ /* Check for overlapping */
+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin)))
+ {
+ /* No Overlap. Enable address decode winNum window */
+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN);
+ }
+ else
+ { /* Overlap detected */
+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n",
+ target);
+ return MV_ERROR;
+ }
+ }
+ else
+ { /* Disable address decode winNum window */
+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window
+*
+* DESCRIPTION:
+* This function scan each SDRAM address decode window to test if it
+* overlapps the given address windoow
+*
+* INPUT:
+* target - SDRAM target where the function skips checking.
+* pAddrDecWin - The tested address window for overlapping with
+* SDRAM windows.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if the given address window overlaps any enabled address
+* decode map, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin)
+{
+ MV_TARGET targetNum;
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++)
+ {
+ /* don't check our winNum or illegal targets */
+ if (targetNum == target)
+ {
+ continue;
+ }
+
+ /* Get window parameters */
+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin))
+ {
+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n");
+ return MV_ERROR;
+ }
+
+ /* Do not check disabled windows */
+ if (MV_FALSE == addrDecWin.enable)
+ {
+ continue;
+ }
+
+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin))
+ {
+ mvOsPrintf(
+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n",
+ target, targetNum);
+ return MV_TRUE;
+ }
+ }
+
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvDramIfBankSizeGet - Get DRAM interface bank size.
+*
+* DESCRIPTION:
+* This function returns the size of a given DRAM bank.
+*
+* INPUT:
+* bankNum - Bank number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* DRAM bank size. If bank is disabled the function return '0'. In case
+* or paramter is invalid, the function returns -1.
+*
+*******************************************************************************/
+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum)
+{
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(bankNum))
+ {
+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum);
+ return -1;
+ }
+ /* Get window parameters */
+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin))
+ {
+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n");
+ return -1;
+ }
+
+ if (MV_TRUE == addrDecWin.enable)
+ {
+ return addrDecWin.addrWin.size;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+
+/*******************************************************************************
+* mvDramIfSizeGet - Get DRAM interface total size.
+*
+* DESCRIPTION:
+* This function get the DRAM total size.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* DRAM total size. In case or paramter is invalid, the function
+* returns -1.
+*
+*******************************************************************************/
+MV_32 mvDramIfSizeGet(MV_VOID)
+{
+ MV_U32 totalSize = 0, bankSize = 0, bankNum;
+
+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ bankSize = mvDramIfBankSizeGet(bankNum);
+
+ if (-1 == bankSize)
+ {
+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum);
+ return -1;
+ }
+ else
+ {
+ totalSize += bankSize;
+ }
+ }
+
+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize));
+
+ return totalSize;
+}
+
+/*******************************************************************************
+* mvDramIfBankBaseGet - Get DRAM interface bank base.
+*
+* DESCRIPTION:
+* This function returns the 32 bit base address of a given DRAM bank.
+*
+* INPUT:
+* bankNum - Bank number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* DRAM bank size. If bank is disabled or paramter is invalid, the
+* function returns -1.
+*
+*******************************************************************************/
+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum)
+{
+ MV_DRAM_DEC_WIN addrDecWin;
+
+ /* Check parameters */
+ if (!MV_TARGET_IS_DRAM(bankNum))
+ {
+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum);
+ return -1;
+ }
+ /* Get window parameters */
+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin))
+ {
+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n");
+ return -1;
+ }
+
+ if (MV_TRUE == addrDecWin.enable)
+ {
+ return addrDecWin.addrWin.baseLow;
+ }
+ else
+ {
+ return -1;
+ }
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h
new file mode 100644
index 000000000..8bfa3e883
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h
@@ -0,0 +1,179 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvDramIfh
+#define __INCmvDramIfh
+
+/* includes */
+#include "ddr1_2/mvDramIfRegs.h"
+#include "ddr1_2/mvDramIfConfig.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/* defines */
+/* DRAM Timing parameters */
+#define SDRAM_TWR 15 /* ns tWr */
+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */
+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */
+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */
+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */
+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */
+
+/* typedefs */
+
+/* enumeration for memory types */
+typedef enum _mvMemoryType
+{
+ MEM_TYPE_SDRAM,
+ MEM_TYPE_DDR1,
+ MEM_TYPE_DDR2
+}MV_MEMORY_TYPE;
+
+/* enumeration for DDR1 supported CAS Latencies */
+typedef enum _mvDimmDdr1Cas
+{
+ DDR1_CL_1_5 = 0x02,
+ DDR1_CL_2 = 0x04,
+ DDR1_CL_2_5 = 0x08,
+ DDR1_CL_3 = 0x10,
+ DDR1_CL_4 = 0x40,
+ DDR1_CL_FAULT
+} MV_DIMM_DDR1_CAS;
+
+/* enumeration for DDR2 supported CAS Latencies */
+typedef enum _mvDimmDdr2Cas
+{
+ DDR2_CL_3 = 0x08,
+ DDR2_CL_4 = 0x10,
+ DDR2_CL_5 = 0x20,
+ DDR2_CL_FAULT
+} MV_DIMM_DDR2_CAS;
+
+
+typedef struct _mvDramBankInfo
+{
+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */
+
+ /* DIMM dimensions */
+ MV_U32 numOfRowAddr;
+ MV_U32 numOfColAddr;
+ MV_U32 dataWidth;
+ MV_U32 errorCheckType; /* ECC , PARITY..*/
+ MV_U32 sdramWidth; /* 4,8,16 or 32 */
+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
+ MV_U32 burstLengthSupported;
+ MV_U32 numOfBanksOnEachDevice;
+ MV_U32 suportedCasLatencies;
+ MV_U32 refreshInterval;
+
+ /* DIMM timing parameters */
+ MV_U32 minCycleTimeAtMaxCasLatPs;
+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
+ MV_U32 minRowPrechargeTime;
+ MV_U32 minRowActiveToRowActive;
+ MV_U32 minRasToCasDelay;
+ MV_U32 minRasPulseWidth;
+ MV_U32 minWriteRecoveryTime; /* DDR2 only */
+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */
+
+ /* Parameters calculated from the extracted DIMM information */
+ MV_U32 size;
+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */
+ MV_U32 numberOfDevices;
+
+ /* DIMM attributes (MV_TRUE for yes) */
+ MV_BOOL registeredAddrAndControlInputs;
+
+}MV_DRAM_BANK_INFO;
+
+/* This structure describes CPU interface address decode window */
+typedef struct _mvDramIfDecWin
+{
+ MV_ADDR_WIN addrWin; /* An address window*/
+ MV_BOOL enable; /* Address decode window is enabled/disabled */
+}MV_DRAM_DEC_WIN;
+
+#include "ddr1_2/mvDram.h"
+
+/* mvDramIf.h API list */
+MV_VOID mvDramIfBasicAsmInit(MV_VOID);
+MV_STATUS mvDramIfDetect(MV_U32 forcedCl);
+MV_VOID _mvDramIfConfig(MV_VOID);
+
+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable);
+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum);
+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum);
+MV_32 mvDramIfSizeGet(MV_VOID);
+
+#if 0
+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray);
+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable);
+#endif
+
+#endif /* __INCmvDramIfh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S
new file mode 100644
index 000000000..f2a9365c0
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S
@@ -0,0 +1,988 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define MV_ASMLANGUAGE
+#include "mvSysHwConfig.h"
+#include "mvOsAsm.h"
+#include "mvBoardEnvSpec.h"
+#include "mvCpuIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "mvDramIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "pci/mvPciRegs.h"
+#include "mvCtrlEnvSpec.h"
+#include "mvCtrlEnvAsm.h"
+#include "cpu/mvCpuArm.h"
+#include "mvCommon.h"
+
+/* defines */
+
+#if !defined(MV_INC_BOARD_DDIM)
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/******************************************************************************
+*
+*
+*
+*
+*******************************************************************************/
+#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG)
+
+/* PEX_PCI and PRPMC boards 256 MB*/
+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
+#define STATIC_SDRAM_CONFIG 0x03248400
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#elif defined(DB_FPGA)
+
+/* FPGA DC boards 256 MB*/
+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
+#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */
+#define STATIC_SDRAM_MODE 0x22
+#define STATIC_DUNIT_CTRL_LOW 0x03041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x1
+
+#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER)
+
+/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */
+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
+#define STATIC_SDRAM_CONFIG 0x03158400
+#define STATIC_SDRAM_MODE 0x452
+#define STATIC_DUNIT_CTRL_LOW 0x06041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+
+
+#elif defined(RD_88F6183AP)
+
+/* DDR2 1 devices 512Mbit by 16 bit */
+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
+#define STATIC_SDRAM_CONFIG 0x1f154400
+#define STATIC_SDRAM_MODE 0x432
+#define STATIC_DUNIT_CTRL_LOW 0x04041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+
+/* 6082L MARVELL DIMM */
+#elif defined(DB_88F6082LBP)
+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
+#define STATIC_SDRAM_CONFIG 0x7f158400
+#define STATIC_SDRAM_MODE 0x432
+#define STATIC_DUNIT_CTRL_LOW 0x04041040
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+
+#elif defined(RD_88W8660_AP82S)
+
+/* Shark RD */
+
+#if defined(MV_DRAM_32M)
+#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x00000010
+#elif defined(MV_DRAM_16M)
+
+#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x00000000
+
+#else
+#error "NO DDR size selected"
+#endif
+
+#define STATIC_SDRAM_CONFIG 0x03144400
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#elif defined(RD_88W8660)
+
+/* Shark RD */
+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
+#define STATIC_SDRAM_CONFIG 0x03144400
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000010
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#else /* NAS */
+
+
+#if defined(RD_88F5182)
+
+#if defined(MV_88F5082)
+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#else
+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#endif
+
+#elif defined(RD_88F5182_3)
+
+#if defined(MV_88F5082)
+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#else
+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#endif
+
+#else
+
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x0
+
+#endif
+
+#if defined(MV_88F5082)
+#define STATIC_SDRAM_CONFIG 0x3144400
+#else
+#define STATIC_SDRAM_CONFIG 0x3148400
+#endif
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x40c
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#endif
+
+ .globl _mvDramIfStaticInit
+_mvDramIfStaticInit:
+
+ mov r11, LR /* Save link register */
+ mov r10, r2
+
+ /* If we boot from NAND jump to DRAM sddress */
+
+ mov r5, #1
+ ldr r6, =dramBoot1
+ str r5, [r6] /* We started executing from DRAM */
+
+ ldr r6, dramBoot1
+ cmp r6, #0
+ bne 1f
+
+
+ /* set all dram windows to 0 */
+ mov r6, #0
+ MV_REG_WRITE_ASM(r6, r5, 0x1504)
+ MV_REG_WRITE_ASM(r6, r5, 0x150c)
+ MV_REG_WRITE_ASM(r6, r5, 0x1514)
+ MV_REG_WRITE_ASM(r6, r5, 0x151c)
+
+ /* set all dram configuration in temp registers */
+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
+ ldr r6, = STATIC_SDRAM_CONFIG
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
+ ldr r6, = STATIC_SDRAM_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
+ ldr r6, = STATIC_DUNIT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
+ ldr r6, = STATIC_SDRAM_ADDR_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
+ ldr r6, = STATIC_SDRAM_EXT_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
+
+ mov sp, #0
+ bl _mvDramIfConfig
+1:
+ mov r2, r10
+ mov PC, r11 /* r11 is saved link register */
+
+#else /* #if !defined(MV_INC_BOARD_DDIM) */
+
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/*******************************************************************************
+* mvDramIfBasicInit - Basic initialization of DRAM interface
+*
+* DESCRIPTION:
+* The function will initialize the DRAM for basic usage. The function
+* will use the TWSI assembly API to extract DIMM parameters according
+* to which DRAM interface will be initialized.
+* The function referes to the following DRAM parameters:
+* 1) DIMM is registered or not.
+* 2) DIMM width detection.
+* 3) DIMM density.
+*
+* INPUT:
+* r3 - required size for initial DRAM.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+* Note:
+* r4 holds I2C EEPROM address
+* r5 holds SDRAM register base address
+* r7 holds returned values
+* r8 holds SDRAM various configuration registers value.
+* r11 holds return function address.
+*******************************************************************************/
+/* Setting the offsets of the I2C registers */
+#define NUM_OF_ROWS_OFFSET 3
+#define NUM_OF_COLS_OFFSET 4
+#define NUM_OF_RANKS 5
+#define SDRAM_WIDTH_OFFSET 13
+#define NUM_OF_BANKS_OFFSET 17
+#define SUPPORTED_CL_OFFSET 18
+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
+#define SDRAM_MODULES_ATTR_OFFSET 21
+
+#define DRAM_DEV_DENSITY_128M 0x080
+#define DRAM_DEV_DENSITY_256M 0x100
+#define DRAM_DEV_DENSITY_512M 0x200
+ .globl _mvDramIfBasicInit
+ .extern _i2cInit
+
+_mvDramIfBasicInit:
+
+ mov r11, LR /* Save link register */
+
+ mov r5, #1
+ ldr r8, =dramBoot1
+ str r5, [r8] /* We started executing from DRAM */
+
+ /* If we boot from NAND jump to DRAM sddress */
+ ldr r8, dramBoot1
+ cmp r8, #0
+ movne pc, r11
+
+
+
+ bl _i2cInit /* Initialize TWSI master */
+
+ /* Get default SDRAM Config values */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+ bic r8, r8, #SDRAM_DCFG_MASK
+
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r4, r5);
+
+ /* Return if OrionN */
+ ldr r5, =MV_5180_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* Return if Orion1 */
+ ldr r5, =MV_5181_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* Return if Nas */
+ ldr r5, =MV_5182_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* Return if Shark */
+ ldr r5, =MV_8660_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* goto calcConfigReg if bigger than Orion2*/
+ ldr r5, =MV_5281_DEV_ID
+ cmp r4, r5
+ bne cat_through
+
+cat_through:
+ /* set cat through - for better performance - in orion2 b0 and higher*/
+ orr r8, r8, #SDRAM_CATTHR_EN
+
+cat_through_end:
+
+
+ /* Get registered/non registered info from DIMM */
+ bl _is_Registered
+ beq nonRegistered
+
+setRegistered:
+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
+
+nonRegistered:
+ /* Get SDRAM width */
+ bl _get_width
+
+ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */
+ cmp r7, #16
+ beq setConfigReg
+
+ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */
+ cmp r7, #8
+ beq setConfigReg
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+setConfigReg:
+ mov r8, r6
+ ldr r6, =SDRAM_CONFIG_DV
+ orr r8, r8, r6 /* Add default settings */
+ mov r6, r8 /* Do not swap r8 content */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG)
+
+ /* Set maximum CL supported by DIMM */
+ bl _get_CAL
+
+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
+ clz r6, r7
+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
+
+ /* Check the DDR version */
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne casDdr2
+
+casDdr1:
+ ldr r7, =3 /* stBurstDel field value */
+ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */
+ cmp r6, #1 /* If CL = 1.5 break */
+ beq setModeReg
+
+ ldr r7, =3 /* stBurstDel field value */
+ ldr r8, =0x22 /* Assuming MAX CL = 2 */
+ cmp r6, #2 /* If CL = 2 break */
+ beq setModeReg
+
+ ldr r7, =4 /* stBurstDel field value */
+ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */
+ cmp r6, #3 /* If CL = 2.5 break */
+ beq setModeReg
+
+ ldr r7, =4 /* stBurstDel field value */
+ ldr r8, =0x32 /* Assuming MAX CL = 3 */
+ cmp r6, #4 /* If CL = 3 break */
+ beq setModeReg
+
+ ldr r7, =5 /* stBurstDel field value */
+ ldr r8, =0x42 /* Assuming MAX CL = 4 */
+ cmp r6, #6 /* If CL = 4 break */
+ b setModeReg
+
+ b exit_ddrAutoConfig /* This is an error !! */
+
+casDdr2:
+ ldr r7, =4 /* stBurstDel field value */
+ ldr r8, =0x32 /* Assuming MAX CL = 3 */
+ cmp r6, #3 /* If CL = 3 break */
+ beq casDdr2Cont
+
+ ldr r7, =5 /* stBurstDel field value */
+ ldr r8, =0x42 /* Assuming MAX CL = 4 */
+ cmp r6, #4 /* If CL = 4 break */
+ beq casDdr2Cont
+
+ /* CL 5 currently unsupported. We use CL 4 instead */
+ ldr r7, =5 /* stBurstDel field value */
+ ldr r8, =0x42 /* Assuming MAX CL = 5 */
+ cmp r6, #5 /* If CL = 5 break */
+ beq casDdr2Cont
+
+ b exit_ddrAutoConfig /* This is an error !! */
+casDdr2Cont:
+ /* Write recovery for auto-precharge relevant only in DDR2 */
+ orr r8, r8, #0x400 /* Default value */
+
+setModeReg:
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to it's new value. */
+
+ /* write 'nop' to SDRAM operation */
+ mov r6, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll1:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll1
+
+ /* Now its safe to write new value to SDRAM Mode register */
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG)
+
+ /* Make the Dunit write the DRAM its new mode */
+ mov r6, #0x3 /* Mode Register Set command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll2:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll2
+
+ /* Set Dunit control register according to max CL detected */
+ /* If we use registered DIMM, add 1 to stBurstDel */
+ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG)
+ tst r6, #SDRAM_REGISTERED
+ beq setDunitReg
+ add r7, r7, #1
+
+setDunitReg:
+ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV
+ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+
+
+ /* DIMM density configuration*/
+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
+Density:
+ bl _getDensity
+ mov r8, r7
+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */
+ /* For example 0x10000000 --> 0x1000 */
+
+ mov r6, #0x00
+ cmp r8, #DRAM_DEV_DENSITY_128M
+ beq densCont
+
+ mov r6, #0x10
+ cmp r8, #DRAM_DEV_DENSITY_256M
+ beq densCont
+
+ mov r6, #0x20
+ cmp r8, #DRAM_DEV_DENSITY_512M
+ beq densCont
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+densCont:
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG)
+
+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+ tst r8, #SDRAM_DTYPE_DDR2
+ beq _extModeODTEnd
+
+
+ /* Set DDR Extended Mode register for working with CS[0] */
+ /* write 'nop' to SDRAM operation */
+ mov r6, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll3:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll3
+
+ /* Now its safe to write new value to SDRAM Extended Mode register */
+ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG)
+
+ /* Make the Dunit write the DRAM its new extended mode */
+ mov r6, #0x4 /* Extended Mode Register Set command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll4:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll4
+
+ /* ODT configuration is done for single bank CS[0] only */
+ /* Config DDR2 On Die Termination (ODT) registers */
+ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG)
+
+ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+
+ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG)
+
+
+ /* we will check what device we are running and perform
+ Initialization according to device value */
+
+_extModeODTEnd:
+
+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
+ /* Does Not Work for Address/Control and Data Pads. */
+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r6, r5);
+ /* Read device revision */
+ MV_CTRL_REV_GET_ASM(r8, r5);
+
+ /* Continue if OrionN */
+ ldr r5, =MV_5180_DEV_ID
+ cmp r6, r5
+ bne 1f
+ b glMem2End
+1:
+
+ /* Continue if Orion1 and device revision B1 */
+ ldr r5, =MV_5181_DEV_ID
+ cmp r6, r5
+ bne 1f
+
+ cmp r8, #MV_5181_B1_REV
+ bge glMem2End
+ b glMem2Start
+1:
+
+ /* Orion NAS */
+ ldr r5, =MV_5182_DEV_ID
+ cmp r6, r5
+ beq glMem2Start
+
+ /* Orion Shark */
+ ldr r5, =MV_8660_DEV_ID
+ cmp r6, r5
+ beq glMem2Start
+
+ b glMem2End
+
+glMem2Start:
+
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r8, r6, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r5, r6
+ mov r5, r5, LSL #9
+ mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */
+ orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r5
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r8, r6, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r5, r6
+ mov r5, r5, LSL #9
+ mov r5, r5, LSR #26
+ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r5
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+glMem2End:
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r8, #SDRAM_DTYPE_DDR2
+ beq ddr1StrengthVal
+
+ddr2StrengthVal:
+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
+ b setDrvStrength
+ddr1StrengthVal:
+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
+
+setDrvStrength:
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+ HTOLL(r6,r5)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r6, r4, r6 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+ HTOLL(r6,r5)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r6, r8, r6 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+ /* Get the "sample on reset" register for the DDR frequancy */
+
+#if defined(MV_RUN_FROM_FLASH)
+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
+ ldr r7, = _cpuARMDDRCLK
+ ldr r4, =_start
+ ldr r4, [r4]
+ sub r7, r7, r4
+ ldr r4, = Lrom_start_of_data
+ ldr r4, [r4]
+ add r7, r4, r7
+#else
+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
+ ldr r7, = _cpuARMDDRCLK
+ ldr r4, =_start
+ sub r7, r7, r4
+ add r7, r7, #CFG_MONITOR_BASE
+#endif
+ /* Get the "sample on reset" register for the DDR frequancy */
+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
+ ldr r5, =MSAR_ARMDDRCLCK_MASK
+ and r5, r4, r5
+#if 0 /* YOTAM TO BE FIX */
+ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS
+#endif
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r6, r8);
+
+ /* Continue if TC90 */
+ ldr r8, =MV_1281_DEV_ID
+ cmp r6, r6
+ beq armClkMsb
+
+ /* Continue if Orion2 */
+ ldr r8, =MV_5281_DEV_ID
+ cmp r6, r8
+#if 0 /* YOTAM TO BE FIX */
+ bne 1f
+#endif
+
+armClkMsb:
+#if 0 /* YOTAM TO BE FIX */
+ tst r4, #MSAR_ARMDDRCLCK_H_MASK
+ beq 1f
+ orr r5, r5, #BIT4
+1:
+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
+ mul r5, r4, r5
+ add r7, r7, r5
+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
+ ldr r5, [r7]
+#endif
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r8, #SDRAM_DTYPE_DDR2
+ beq ddr1FtdllVal
+
+ddr2FtdllVal:
+ ldr r4, =FTDLL_DDR2_250MHZ
+ ldr r7, =_250MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ
+ ldr r7, =_200MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ
+ ldr r7, =_166MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_133MHZ
+ b setFtdllReg
+
+ddr1FtdllVal:
+ ldr r4, =FTDLL_DDR1_200MHZ
+ ldr r7, =_200MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR1_166MHZ
+ ldr r7, =_166MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR1_133MHZ
+ ldr r7, =_133MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =0
+
+setFtdllReg:
+
+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
+ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
+ orr r8, r8, r4
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
+ bic r8, r8, #1
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/
+
+
+setTimingReg:
+ /* Set default Timing parameters */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne ddr2TimeParam
+
+ddr1TimeParam:
+ ldr r6, =DDR1_TIMING_LOW_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
+ ldr r6, =DDR1_TIMING_HIGH_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
+ b timeParamDone
+
+ddr2TimeParam:
+ ldr r6, =DDR2_TIMING_LOW_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
+ ldr r6, =DDR2_TIMING_HIGH_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
+
+timeParamDone:
+ /* Open CS[0] window to requested size and enable it. Disable other */
+ /* windows */
+ ldr r6, =SCBAR_BASE_MASK
+ sub r3, r3, #1
+ and r3, r3, r6
+ orr r3, r3, #1 /* Enable bank */
+ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0))
+ ldr r6, =0
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1))
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2))
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3))
+
+exit_ddrAutoConfig:
+ mov PC, r11 /* r11 is saved link register */
+
+
+/***************************************************************************************/
+/* r4 holds I2C EEPROM address
+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
+ * r8 holds SDRAM various configuration registers value.
+ * r13 holds Link register
+ */
+/**************************/
+_getDensity:
+ mov r13, LR /* Save link register */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
+ bl _i2cRead
+ mov r8, r7 /* r8 save number of rows */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
+ bl _i2cRead
+ add r8, r8, r7 /* r8 = number of rows + number of col */
+
+ mov r7, #0x1
+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
+ bl _i2cRead
+ mul r8, r7, r8
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
+ bl _i2cRead
+ mul r7, r8, r7
+
+ mov PC, r13
+
+/**************************/
+_get_width:
+ mov r13, LR /* Save link register */
+
+ /* Get SDRAM width (SPD offset 13) */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_WIDTH_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ mov PC, r13
+
+/**************************/
+_get_CAL:
+ mov r13, LR /* Save link register */
+
+ /* Set maximum CL supported by DIMM */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
+ bl _i2cRead
+
+ mov PC, r13
+
+/**************************/
+/* R8 - sdram configuration register.
+ * Return value in flag if no-registered then Z-flag is set
+ */
+_is_Registered:
+ mov r13, LR /* Save link register */
+
+ /* Get registered/non registered info from DIMM */
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne regDdr2
+
+regDdr1:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_MODULES_ATTR_OFFSET
+ bl _i2cRead /* result in r7 */
+ tst r7, #0x2
+ b exit
+regDdr2:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_TYPE_INFO_OFFSET
+ bl _i2cRead /* result in r7 */
+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
+ /* or Mini-RDIMM (0x10) */
+exit:
+ mov PC, r13
+
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S
new file mode 100644
index 000000000..e34ebbf29
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S
@@ -0,0 +1,668 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvDramIfBasicAsm.s
+*
+* DESCRIPTION:
+* Memory full detection and best timing configuration is done in
+* C code. C runtime environment requires a stack. This module API
+* initialize DRAM interface chip select 0 for basic functionality for
+* the use of stack.
+* The module API assumes DRAM information is stored in I2C EEPROM reside
+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
+* internal data structure is assumed to be orgenzied in common DRAM
+* vendor SPD structure.
+* NOTE: DFCDL values are assumed to be already initialized prior to
+* this module API activity.
+*
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+/* includes */
+#define MV_ASMLANGUAGE
+#include "mvOsAsm.h"
+#include "mvSysHwConfig.h"
+#include "mvDramIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "mvCpuIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "pci/mvPciRegs.h"
+#include "mvCtrlEnvSpec.h"
+#include "mvCtrlEnvAsm.h"
+#include "cpu/mvCpuArm.h"
+#include "mvCommon.h"
+
+/* defines */
+
+/* locals */
+.data
+.globl _mvDramIfConfig
+
+.text
+
+/*******************************************************************************
+* _mvDramIfConfig - Basic DRAM interface initialization.
+*
+* DESCRIPTION:
+* The function will initialize the following DRAM parameters using the
+* values prepared by mvDramIfDetect routine. Values are located
+* in predefined registers.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+
+_mvDramIfConfig:
+
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_s
+save_on_stack:
+ stmdb sp!, {r1, r2, r3, r4, r7, r11}
+no_stack_s:
+
+ /* 1) Write to SDRAM coniguration register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
+ str r4, [r1]
+
+ /* 2) Write Dunit control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
+ str r4, [r1]
+
+ /* 3) Write SDRAM address control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
+ str r4, [r1]
+
+ /* 4) Write SDRAM bank 0 size register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0))
+ str r4, [r1]
+
+ /* 5) Write SDRAM open pages control register */
+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
+ str r4, [r1]
+
+ /* 6) Write SDRAM timing Low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* 7) Write SDRAM timing High register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to it’s new value. */
+
+ /* 8.1 write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll1:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll1
+
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
+ str r4, [r1]
+
+ /* 8.4 Make the Dunit write the DRAM its new mode */
+ mov r4, #0x3 /* Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll2:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll2
+
+#ifndef DB_FPGA
+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
+ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG)
+ tst r4, #SDRAM_DTYPE_DDR2
+ beq _extModeODTEnd
+#endif /* DB_FPGA */
+
+ /* 9) Write SDRAM Extended mode register This operation should be */
+ /* done for each memory bank */
+ /* write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll3:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll3
+
+ /* Now its safe to write new value to SDRAM Extended Mode register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
+ str r4, [r1]
+
+ /* Go over each of the Banks */
+ ldr r3, =0 /* r3 = DRAM bank Num */
+
+extModeLoop:
+ /* Set the SDRAM Operation Control to each of the DRAM banks */
+ mov r2, r3 /* Do not swap the bank counter value */
+ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG)
+
+ /* Make the Dunit write the DRAM its new mode */
+ mov r4, #0x4 /* Extended Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll4:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll4
+#ifndef DB_FPGA
+ add r3, r3, #1
+ cmp r3, #4 /* 4 = Number of banks */
+ bne extModeLoop
+
+extModeEnd:
+ /* Config DDR2 On Die Termination (ODT) registers */
+ /* Write SDRAM DDR2 ODT control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 ODT control high register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 Dunit ODT control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
+ str r4, [r1]
+
+#endif /* DB_FPGA */
+_extModeODTEnd:
+#ifndef DB_FPGA
+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
+ /* Does Not Work for Address/Control and Data Pads. */
+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r3, r1);
+ /* Read device revision */
+ MV_CTRL_REV_GET_ASM(r2, r1);
+
+ /* Continue if OrionN */
+ ldr r1, =MV_5180_DEV_ID
+ cmp r3, r1
+ bne 1f
+ b glMem2End
+1:
+ /* Continue if Orion1 and device revision B1 */
+ ldr r1, =MV_5181_DEV_ID
+ cmp r3, r1
+ bne 1f
+
+ cmp r2, #MV_5181_B1_REV
+ bge glMem2End
+ b glMem2Start
+1:
+
+ /* Orion NAS */
+ ldr r1, =MV_5182_DEV_ID
+ cmp r3, r1
+ beq glMem2Start
+
+ /* Orion NAS */
+ ldr r1, =MV_5082_DEV_ID
+ cmp r3, r1
+ beq glMem2Start
+
+ /* Orion Shark */
+ ldr r1, =MV_8660_DEV_ID
+ cmp r3, r1
+ beq glMem2Start
+
+ b glMem2End
+
+glMem2Start:
+
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r2, r3, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r3
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r3, r3, r1
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r2, r3, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r3
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26
+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r3, r3, r1
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+glMem2End:
+
+
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */
+ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r2, #SDRAM_DTYPE_DDR2
+ beq ddr1StrengthVal
+
+ddr2StrengthVal:
+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
+ b setDrvStrength
+ddr1StrengthVal:
+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
+
+setDrvStrength:
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+ HTOLL(r3,r1)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r3, r4, r3 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+ HTOLL(r3,r1)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r3, r2, r3 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */
+ /* 88F5082, 88F5181L, 88F6082/L */
+
+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
+ ldr r7, = _cpuARMDDRCLK
+ ldr r4, =_start
+ sub r7, r7, r4
+ add r7, r7, #CFG_MONITOR_BASE
+
+ /* Get the "sample on reset" register for the DDR frequancy */
+ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET)
+ ldr r1, =MSAR_ARMDDRCLCK_MASK
+ and r1, r4, r1
+#if 0 /* YOTAM TO BE FIX */
+ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS
+#endif
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r3, r2);
+
+ /* Continue if TC90 */
+ ldr r2, =MV_1281_DEV_ID
+ cmp r3, r2
+ beq armClkMsb
+
+ /* Continue if Orion2 */
+ ldr r2, =MV_5281_DEV_ID
+ cmp r3, r2
+#if 0 /* YOTAM TO BE FIX */
+ bne 1f
+#endif
+
+armClkMsb:
+#if 0 /* YOTAM TO BE FIX */
+ tst r4, #MSAR_ARMDDRCLCK_H_MASK
+ beq 1f
+ orr r1, r1, #BIT4
+1:
+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
+ mul r1, r4, r1
+ add r7, r7, r1
+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
+ ldr r1, [r7]
+#endif
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r2, #SDRAM_DTYPE_DDR2
+ beq ddr1FtdllVal
+
+ddr2FtdllVal:
+ ldr r2, =MV_5281_DEV_ID
+ cmp r3, r2
+ bne 2f
+ MV_CTRL_REV_GET_ASM(r3, r2)
+ cmp r3, #MV_5281_D0_REV
+ beq orin2_d0_ddr2_ftdll_val
+ cmp r3, #MV_5281_D1_REV
+ beq orin2_d1_ddr2_ftdll_val
+ cmp r3, #MV_5281_D2_REV
+ beq orin2_d1_ddr2_ftdll_val
+ b ddr2_default_val
+
+/* Set Orion 2 D1 ftdll values for DDR2 */
+orin2_d1_ddr2_ftdll_val:
+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1
+ ldr r7, =_250MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ b ddr2_default_val
+
+/* Set Orion 2 D0 ftdll values for DDR2 */
+orin2_d0_ddr2_ftdll_val:
+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0
+ ldr r7, =_250MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ b ddr2_default_val
+2:
+ ldr r2, =MV_5182_DEV_ID
+ cmp r3, r2
+ bne 3f
+
+/* Set Orion nas ftdll values for DDR2 */
+orin_nas_ftdll_val:
+ ldr r4, =FTDLL_DDR2_166MHZ_5182
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+/* default values for all other devices */
+3:
+ddr2_default_val:
+ ldr r4, =FTDLL_DDR2_250MHZ
+ ldr r7, =_250MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_133MHZ
+ ldr r7, =_133MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =0
+ b setFtdllReg
+
+ddr1FtdllVal:
+ ldr r2, =MV_5281_DEV_ID
+ cmp r3, r2
+ bne 2f
+ MV_CTRL_REV_GET_ASM(r3, r2)
+ cmp r3, #MV_5281_D0_REV
+ bge orin2_ddr1_ftdll_val
+ b ddr1_default_val
+
+/* Set Orion 2 D0 and above ftdll values for DDR1 */
+orin2_ddr1_ftdll_val:
+ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ b ddr1_default_val
+2:
+ ldr r2, =MV_5181_DEV_ID
+ cmp r3, r2
+ bne 3f
+ MV_CTRL_REV_GET_ASM(r3, r2)
+ cmp r3, #MV_5181_B1_REV
+ bge orin1_ddr1_ftdll_val
+ b ddr1_default_val
+
+/* Set Orion 1 ftdll values for DDR1 */
+orin1_ddr1_ftdll_val:
+ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+3:
+ddr1_default_val:
+ ldr r4, =FTDLL_DDR1_133MHZ
+ ldr r7, =_133MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+ ldr r4, =FTDLL_DDR1_166MHZ
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+ ldr r4, =FTDLL_DDR1_200MHZ
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+ ldr r4, =0
+
+setFtdllReg:
+
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
+ HTOLL(r4,r1)
+ bic r4, r4, #1
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
+
+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */
+#endif /* DB_FPGA */
+
+restoreTmpRegs:
+ /* Restore the registers we used to save the DDR detect values */
+
+ ldr r4, =DRAM_BUF_REG0_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0)
+
+ ldr r4, =DRAM_BUF_REG1_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1)
+
+ ldr r4, =DRAM_BUF_REG2_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2)
+
+ ldr r4, =DRAM_BUF_REG3_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3)
+
+ ldr r4, =DRAM_BUF_REG4_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4)
+
+ ldr r4, =DRAM_BUF_REG5_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5)
+
+ ldr r4, =DRAM_BUF_REG6_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6)
+
+ ldr r4, =DRAM_BUF_REG7_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7)
+
+ ldr r4, =DRAM_BUF_REG8_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8)
+
+ ldr r4, =DRAM_BUF_REG9_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9)
+
+ ldr r4, =DRAM_BUF_REG10_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10)
+
+
+ /* Restore registers */
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_l
+load_from_stack:
+ ldmia sp!, {r1, r2, r3, r4, r7, r11}
+no_stack_l:
+
+ mov pc, lr
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h
new file mode 100644
index 000000000..a7c66444a
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h
@@ -0,0 +1,192 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvDramIfConfigh
+#define __INCmvDramIfConfigh
+
+/* includes */
+
+/* defines */
+
+/* registers defaults values */
+
+#define SDRAM_CONFIG_DV \
+ (SDRAM_PERR_WRITE | \
+ SDRAM_SRMODE | \
+ SDRAM_SRCLK_GATED)
+
+#define SDRAM_DUNIT_CTRL_LOW_DV \
+ (SDRAM_CTRL_POS_RISE | \
+ SDRAM_CLK1DRV_NORMAL | \
+ SDRAM_LOCKEN_ENABLE)
+
+#define SDRAM_ADDR_CTRL_DV 0
+
+#define SDRAM_TIMING_CTRL_LOW_REG_DV \
+ ((0x2 << SDRAM_TRCD_OFFS) | \
+ (0x2 << SDRAM_TRP_OFFS) | \
+ (0x1 << SDRAM_TWR_OFFS) | \
+ (0x0 << SDRAM_TWTR_OFFS) | \
+ (0x5 << SDRAM_TRAS_OFFS) | \
+ (0x1 << SDRAM_TRRD_OFFS))
+/* TRFC 0x27, TW2W 0x1 */
+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\
+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\
+ ( 0x1 << SDRAM_TW2W_OFFS))
+
+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN
+
+/* DDR2 ODT default register values */
+
+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */
+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */
+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */
+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+
+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000
+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000
+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F
+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440
+
+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C
+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000
+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F
+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404
+
+
+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */
+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \
+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \
+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+
+
+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \
+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \
+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+
+/* DDR SDRAM Mode Register default value */
+#define DDR1_MODE_REG_DV 0x00000000
+#define DDR2_MODE_REG_DV 0x00000400
+
+/* DDR SDRAM Timing parameter default values */
+#define DDR1_TIMING_LOW_DV 0x11602220
+#define DDR1_TIMING_HIGH_DV 0x0000000d
+
+#define DDR2_TIMING_LOW_DV 0x11812220
+#define DDR2_TIMING_HIGH_DV 0x0000030f
+
+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \
+ (0x7F<< 12) | \
+ (0x1 << 22))
+
+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ
+
+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \
+ (0x1 << 12) | \
+ (0x3 << 14) | \
+ (0x1 << 18) | \
+ (0x1 << 22))
+
+
+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \
+ (0x1 << 12) | \
+ (0x1 << 14) | \
+ (0x1 << 16) | \
+ (0x1 << 19) | \
+ (0xF << 20))
+
+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ
+
+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \
+ (0x1 << 12) | \
+ (0x1 << 14) | \
+ (0x1 << 16) | \
+ (0x1 << 19) | \
+ (0xF << 20))
+
+#define FTDLL_DDR2_250MHZ 0x445001
+
+/* Orion 1 B1 and above */
+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001
+
+/* Orion nas */
+#define FTDLL_DDR2_166MHZ_5182 0x597001
+
+/* Orion 2 D0 and above */
+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001
+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001
+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001
+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001
+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001
+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001
+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801
+
+#endif /* __INCmvDramIfh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h
new file mode 100644
index 000000000..e9cd7c4e5
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h
@@ -0,0 +1,306 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDramIfRegsh
+#define __INCmvDramIfRegsh
+
+
+/* DDR SDRAM Controller Address Decode Registers */
+/* SDRAM CSn Base Address Register (SCBAR) */
+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8))
+#define SCBAR_BASE_OFFS 16
+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS)
+#define SCBAR_BASE_ALIGNMENT 0x10000
+
+/* SDRAM CSn Size Register (SCSR) */
+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8))
+#define SCSR_WIN_EN BIT0
+#define SCSR_SIZE_OFFS 16
+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS)
+#define SCSR_SIZE_ALIGNMENT 0x10000
+
+/* configuration register */
+#define SDRAM_CONFIG_REG 0x1400
+#define SDRAM_REFRESH_OFFS 0
+#define SDRAM_REFRESH_MAX 0x3000
+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS)
+#define SDRAM_DWIDTH_OFFS 14
+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS)
+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS)
+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS)
+#define SDRAM_DTYPE_OFFS 16
+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS)
+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS)
+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS)
+#define SDRAM_REGISTERED (1 << 17)
+#define SDRAM_PERR_OFFS 18
+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS)
+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS)
+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS)
+#define SDRAM_DCFG_OFFS 20
+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS)
+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS)
+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS)
+#define SDRAM_SRMODE (1 << 24)
+#define SDRAM_SRCLK_OFFS 25
+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS)
+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS)
+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS)
+#define SDRAM_CATTH_OFFS 26
+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS)
+
+
+/* dunit control register */
+#define SDRAM_DUNIT_CTRL_REG 0x1404
+#define SDRAM_CTRL_POS_OFFS 6
+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS)
+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS)
+#define SDRAM_CLK1DRV_OFFS 12
+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS)
+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS)
+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS)
+#define SDRAM_LOCKEN_OFFS 18
+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS)
+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS)
+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS)
+#define SDRAM_ST_BURST_DEL_OFFS 24
+#define SDRAM_ST_BURST_DEL_MAX 0xf
+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX<<SDRAM_ST_BURST_DEL_OFFS)
+
+/* sdram timing control low register */
+#define SDRAM_TIMING_CTRL_LOW_REG 0x1408
+#define SDRAM_TRCD_OFFS 4
+#define SDRAM_TRCD_MASK (0xF << SDRAM_TRCD_OFFS)
+#define SDRAM_TRP_OFFS 8
+#define SDRAM_TRP_MASK (0xF << SDRAM_TRP_OFFS)
+#define SDRAM_TWR_OFFS 12
+#define SDRAM_TWR_MASK (0xF << SDRAM_TWR_OFFS)
+#define SDRAM_TWTR_OFFS 16
+#define SDRAM_TWTR_MASK (0xF << SDRAM_TWTR_OFFS)
+#define SDRAM_TRAS_OFFS 20
+#define SDRAM_TRAS_MASK (0xF << SDRAM_TRAS_OFFS)
+#define SDRAM_TRRD_OFFS 24
+#define SDRAM_TRRD_MASK (0xF << SDRAM_TRRD_OFFS)
+#define SDRAM_TRTP_OFFS 28
+#define SDRAM_TRTP_MASK (0xF << SDRAM_TRTP_OFFS)
+
+/* sdram timing control high register */
+#define SDRAM_TIMING_CTRL_HIGH_REG 0x140c
+#define SDRAM_TRFC_OFFS 0
+#define SDRAM_TRFC_MASK (0xF << SDRAM_TRFC_OFFS)
+#define SDRAM_TR2R_OFFS 4
+#define SDRAM_TR2R_MASK (0x3 << SDRAM_TR2R_OFFS)
+#define SDRAM_TR2W_W2R_OFFS 6
+#define SDRAM_TR2W_W2R_MASK (0x3 << SDRAM_TR2W_W2R_OFFS)
+#define SDRAM_TRFC_EXT_OFFS 8
+#define SDRAM_TRFC_EXT_MASK (0x1 << SDRAM_TRFC_EXT_OFFS)
+#define SDRAM_TW2W_OFFS 10
+#define SDRAM_TW2W_MASK (0x1 << SDRAM_TW2W_OFFS)
+
+/* address control register */
+#define SDRAM_ADDR_CTRL_REG 0x1410
+#define SDRAM_DSIZE_OFFS 4
+#define SDRAM_DSIZE_MASK (0x3 << SDRAM_DSIZE_OFFS)
+#define SDRAM_DSIZE_128Mb (0x0 << SDRAM_DSIZE_OFFS)
+#define SDRAM_DSIZE_256Mb (0x1 << SDRAM_DSIZE_OFFS)
+#define SDRAM_DSIZE_512Mb (0x2 << SDRAM_DSIZE_OFFS)
+
+/* SDRAM Open Pages Control registers */
+#define SDRAM_OPEN_PAGE_CTRL_REG 0x1414
+#define SDRAM_OPEN_PAGE_EN (0 << 0)
+#define SDRAM_OPEN_PAGE_DIS (1 << 0)
+
+/* sdram opertion register */
+#define SDRAM_OPERATION_REG 0x1418
+#define SDRAM_CMD_OFFS 0
+#define SDRAM_CMD_MASK (0x7 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_NORMAL (0x0 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_REFRESH_ALL (0x2 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_REG_SET_CMD (0x3 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_EXT_MODE_SET (0x4 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_NOP (0x5 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_SLF_RFRSH (0x7 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_EMRS2_CMD (0x8 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_EMRS3_CMD (0x9 << SDRAM_CMD_OFFS)
+
+/* sdram mode register */
+#define SDRAM_MODE_REG 0x141c
+#define SDRAM_BURST_LEN_OFFS 0
+#define SDRAM_BURST_LEN_MASK (0x7 << SDRAM_BURST_LEN_OFFS)
+#define SDRAM_BURST_LEN_4 (0x2 << SDRAM_BURST_LEN_OFFS)
+#define SDRAM_CL_OFFS 4
+#define SDRAM_CL_MASK (0x7 << SDRAM_CL_OFFS)
+#define SDRAM_DDR1_CL_2 (0x2 << SDRAM_CL_OFFS)
+#define SDRAM_DDR1_CL_3 (0x3 << SDRAM_CL_OFFS)
+#define SDRAM_DDR1_CL_4 (0x4 << SDRAM_CL_OFFS)
+#define SDRAM_DDR1_CL_1_5 (0x5 << SDRAM_CL_OFFS)
+#define SDRAM_DDR1_CL_2_5 (0x6 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_3 (0x3 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_4 (0x4 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_5 (0x5 << SDRAM_CL_OFFS)
+#define SDRAM_TM_OFFS 7
+#define SDRAM_TM_MASK (1 << SDRAM_TM_OFFS)
+#define SDRAM_TM_NORMAL (0 << SDRAM_TM_OFFS)
+#define SDRAM_TM_TEST_MODE (1 << SDRAM_TM_OFFS)
+#define SDRAM_DLL_OFFS 8
+#define SDRAM_DLL_MASK (1 << SDRAM_DLL_OFFS)
+#define SDRAM_DLL_NORMAL (0 << SDRAM_DLL_OFFS)
+#define SDRAM_DLL_RESET (1 << SDRAM_DLL_OFFS)
+#define SDRAM_WR_OFFS 11
+#define SDRAM_WR_MAX 7
+#define SDRAM_WR_MASK (SDRAM_WR_MAX << SDRAM_WR_OFFS)
+#define SDRAM_PD_OFFS 12
+#define SDRAM_PD_MASK (1 << SDRAM_PD_OFFS)
+#define SDRAM_PD_FAST_EXIT (0 << SDRAM_PD_OFFS)
+#define SDRAM_PD_SLOW_EXIT (1 << SDRAM_PD_OFFS)
+
+/* DDR SDRAM Extended Mode register (DSEMR) */
+#define SDRAM_EXTENDED_MODE_REG 0x1420
+#define DSEMR_DLL_ENABLE (1 << 0)
+#define DSEMR_DS_OFFS 1
+#define DSEMR_DS_MASK (1 << DSEMR_DS_OFFS)
+#define DSEMR_DS_NORMAL (0 << DSEMR_DS_OFFS)
+#define DSEMR_DS_REDUCED (1 << DSEMR_DS_OFFS)
+#define DSEMR_RTT0_OFFS 2
+#define DSEMR_RTT1_OFFS 6
+#define DSEMR_RTT_ODT_DISABLE ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
+#define DSEMR_RTT_ODT_75_OHM ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
+#define DSEMR_RTT_ODT_150_OHM ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
+#define DSEMR_OCD_OFFS 7
+#define DSEMR_OCD_MASK (0x7 << DSEMR_OCD_OFFS)
+#define DSEMR_OCD_EXIT_CALIB (0 << DSEMR_OCD_OFFS)
+#define DSEMR_OCD_DRIVE1 (1 << DSEMR_OCD_OFFS)
+#define DSEMR_OCD_DRIVE0 (2 << DSEMR_OCD_OFFS)
+#define DSEMR_OCD_ADJUST_MODE (4 << DSEMR_OCD_OFFS)
+#define DSEMR_OCD_CALIB_DEFAULT (7 << DSEMR_OCD_OFFS)
+#define DSEMR_DQS_OFFS 10
+#define DSEMR_DQS_MASK (1 << DSEMR_DQS_OFFS)
+#define DSEMR_DQS_DIFFERENTIAL (0 << DSEMR_DQS_OFFS)
+#define DSEMR_DQS_SINGLE_ENDED (0 << DSEMR_DQS_OFFS)
+#define DSEMR_RDQS_ENABLE (1 << 11)
+#define DSEMR_QOFF_OUTPUT_BUFF_EN (1 << 12)
+
+/* DDR SDRAM Operation Control Register */
+#define SDRAM_OPERATION_CTRL_REG 0x142c
+
+/* Dunit FTDLL Configuration Register */
+#define SDRAM_FTDLL_CONFIG_REG 0x1484
+
+/* Pads Calibration register */
+#define SDRAM_ADDR_CTRL_PADS_CAL_REG 0x14c0
+#define SDRAM_DATA_PADS_CAL_REG 0x14c4
+#define SDRAM_DRVN_OFFS 0
+#define SDRAM_DRVN_MASK (0x3F << SDRAM_DRVN_OFFS)
+#define SDRAM_DRVP_OFFS 6
+#define SDRAM_DRVP_MASK (0x3F << SDRAM_DRVP_OFFS)
+#define SDRAM_PRE_DRIVER_STRENGTH_OFFS 12
+#define SDRAM_PRE_DRIVER_STRENGTH_MASK (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+#define SDRAM_TUNE_EN BIT16
+#define SDRAM_LOCK_OFFS 17
+#define SDRAM_LOCK_MAKS (0x1F << SDRAM_LOCK_OFFS)
+#define SDRAM_LOCKN_OFFS 17
+#define SDRAM_LOCKN_MAKS (0x3F << SDRAM_LOCKN_OFFS)
+#define SDRAM_LOCKP_OFFS 23
+#define SDRAM_LOCKP_MAKS (0x3F << SDRAM_LOCKP_OFFS)
+#define SDRAM_WR_EN (1 << 31)
+
+/* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */
+#define DDR2_SDRAM_ODT_CTRL_LOW_REG 0x1494
+#define DSOCLR_ODT_RD_OFFS(odtNum) (odtNum * 4)
+#define DSOCLR_ODT_RD_MASK(odtNum) (0xf << DSOCLR_ODT_RD_OFFS(odtNum))
+#define DSOCLR_ODT_RD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum))
+#define DSOCLR_ODT_WR_OFFS(odtNum) (16 + (odtNum * 4))
+#define DSOCLR_ODT_WR_MASK(odtNum) (0xf << DSOCLR_ODT_WR_OFFS(odtNum))
+#define DSOCLR_ODT_WD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum))
+
+/* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */
+#define DDR2_SDRAM_ODT_CTRL_HIGH_REG 0x1498
+/* Optional control values to DSOCHR_ODT_EN macro */
+#define DDR2_ODT_CTRL_DUNIT 0
+#define DDR2_ODT_CTRL_NEVER 1
+#define DDR2_ODT_CTRL_ALWAYS 3
+#define DSOCHR_ODT_EN_OFFS(odtNum) (odtNum * 2)
+#define DSOCHR_ODT_EN_MASK(odtNum) (0x3 << DSOCHR_ODT_EN_OFFS(odtNum))
+#define DSOCHR_ODT_EN(odtNum, ctrl) ((1 << ctrl) << DSOCHR_ODT_RD_OFFS(odtNum))
+
+/* DDR2 Dunit ODT Control Register (DDOCR)*/
+#define DDR2_DUNIT_ODT_CONTROL_REG 0x149c
+#define DDOCR_ODT_RD_OFFS 0
+#define DDOCR_ODT_RD_MASK (0xf << DDOCR_ODT_RD_OFFS)
+#define DDOCR_ODT_RD(bank) ((1 << bank) << DDOCR_ODT_RD_OFFS)
+#define DDOCR_ODT_WR_OFFS 4
+#define DDOCR_ODT_WR_MASK (0xf << DDOCR_ODT_WR_OFFS)
+#define DDOCR_ODT_WR(bank) ((1 << bank) << DDOCR_ODT_WR_OFFS)
+#define DSOCR_ODT_EN_OFFS 8
+#define DSOCR_ODT_EN_MASK (0x3 << DSOCR_ODT_EN_OFFS)
+#define DSOCR_ODT_EN(ctrl) ((1 << ctrl) << DSOCR_ODT_EN_OFFS)
+#define DSOCR_ODT_SEL_OFFS 10
+#define DSOCR_ODT_SEL_MASK (0x3 << DSOCR_ODT_SEL_OFFS)
+
+/* DDR SDRAM Initialization Control Register (DSICR) */
+#define DDR_SDRAM_INIT_CTRL_REG 0x1480
+#define DSICR_INIT_EN (1 << 0)
+
+#endif /* __INCmvDramIfRegsh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt
new file mode 100644
index 000000000..38a926440
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.4
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c
new file mode 100644
index 000000000..a214c95cd
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c
@@ -0,0 +1,1855 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#include "ddr2/mvDramIf.h"
+#include "ctrlEnv/sys/mvCpuIf.h"
+
+#include "ddr2/mvDramIfStaticInit.h"
+
+/* #define MV_DEBUG */
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+/* DRAM bank presence encoding */
+#define BANK_PRESENT_CS0 0x1
+#define BANK_PRESENT_CS0_CS1 0x3
+#define BANK_PRESENT_CS0_CS2 0x5
+#define BANK_PRESENT_CS0_CS1_CS2 0x7
+#define BANK_PRESENT_CS0_CS2_CS3 0xd
+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf
+
+/* locals */
+#ifndef MV_STATIC_DRAM_ON_BOARD
+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo);
+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTmode );
+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk);
+static MV_U32 sdramModeRegCalc(MV_U32 minCas);
+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk);
+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1);
+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk);
+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl);
+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk);
+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk);
+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas);
+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas);
+#endif
+MV_32 DRAM_CS_Order[MV_DRAM_MAX_CS] = {N_A
+
+#ifdef MV_INCLUDE_SDRAM_CS1
+ ,N_A
+#endif
+#ifdef MV_INCLUDE_SDRAM_CS2
+ ,N_A
+#endif
+#ifdef MV_INCLUDE_SDRAM_CS3
+ ,N_A
+#endif
+ };
+/* Get DRAM size of CS num */
+MV_U32 mvDramCsSizeGet(MV_U32 csNum)
+{
+ MV_DRAM_BANK_INFO bankInfo;
+ MV_U32 size, deviceW, dimmW;
+#ifdef MV78XX0
+ MV_U32 temp;
+#endif
+
+ if(MV_OK == mvDramBankInfoGet(csNum, &bankInfo))
+ {
+ if (0 == bankInfo.size)
+ return 0;
+
+ /* Note that the Dimm width might be different then the device DRAM width */
+#ifdef MV78XX0
+ temp = MV_REG_READ(SDRAM_CONFIG_REG);
+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64;
+#else
+ deviceW = 16 /* KW family */;
+#endif
+ dimmW = bankInfo.dataWidth - (bankInfo.dataWidth % 16);
+ size = ((bankInfo.size << 20) / (dimmW/deviceW));
+ return size;
+ }
+ else
+ return 0;
+}
+/*******************************************************************************
+* mvDramIfDetect - Prepare DRAM interface configuration values.
+*
+* DESCRIPTION:
+* This function implements the full DRAM detection and timing
+* configuration for best system performance.
+* Since this routine runs from a ROM device (Boot Flash), its stack
+* resides on RAM, that might be the system DRAM. Changing DRAM
+* configuration values while keeping vital data in DRAM is risky. That
+* is why the function does not preform the configuration setting but
+* prepare those in predefined 32bit registers (in this case IDMA
+* registers are used) for other routine to perform the settings.
+* The function will call for board DRAM SPD information for each DRAM
+* chip select. The function will then analyze those SPD parameters of
+* all DRAM banks in order to decide on DRAM configuration compatible
+* for all DRAM banks.
+* The function will set the CPU DRAM address decode registers.
+* Note: This routine prepares values that will overide configuration of
+* mvDramBasicAsmInit().
+*
+* INPUT:
+* forcedCl - Forced CAL Latency. If equal to zero, do not force.
+* eccDisable - Force down the ECC.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable)
+{
+ MV_32 MV_DRAM_CS_order[MV_DRAM_MAX_CS] = {
+ SDRAM_CS0
+#ifdef MV_INCLUDE_SDRAM_CS1
+ ,SDRAM_CS1
+#endif
+#ifdef MV_INCLUDE_SDRAM_CS2
+ ,SDRAM_CS2
+#endif
+#ifdef MV_INCLUDE_SDRAM_CS3
+ ,SDRAM_CS3
+#endif
+ };
+ MV_U32 busClk, deviceW, dimmW;
+ MV_U32 numOfAllDevices = 0;
+ MV_STATUS TTMode;
+#ifndef MV_STATIC_DRAM_ON_BOARD
+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS];
+ MV_U32 size, base = 0, i, j, temp, busClkPs;
+ MV_U8 minCas;
+ MV_CPU_DEC_WIN dramDecWin;
+ dramDecWin.addrWin.baseHigh = 0;
+#endif
+
+ busClk = mvBoardSysClkGet();
+
+ if (0 == busClk)
+ {
+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n");
+ return MV_ERROR;
+ }
+
+#ifndef MV_STATIC_DRAM_ON_BOARD
+
+ busClkPs = 1000000000 / (busClk / 1000); /* in ps units */
+ /* we will use bank 0 as the representative of the all the DRAM banks, */
+ /* since bank 0 must exist. */
+ for(i = 0; i < MV_DRAM_MAX_CS; i++)
+ {
+ /* if Bank exist */
+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i]))
+ {
+ DB(mvOsPrintf("Dram: Find bank %d\n", i));
+ /* check it isn't SDRAM */
+ if(bankInfo[i].memoryType != MEM_TYPE_DDR2)
+ {
+ mvOsOutput("Dram: ERR. SDRAM type not supported !!!\n");
+ return MV_ERROR;
+ }
+
+ /* All banks must support the Mclk freqency */
+ if(bankInfo[i].minCycleTimeAtMaxCasLatPs > busClkPs)
+ {
+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i);
+ return MV_ERROR;
+ }
+
+ /* All banks must support registry in order to activate it */
+ if(bankInfo[i].registeredAddrAndControlInputs !=
+ bankInfo[0].registeredAddrAndControlInputs)
+ {
+ mvOsOutput("Dram: ERR. different Registered settings !!!\n");
+ return MV_ERROR;
+ }
+
+ /* All banks must support same ECC mode */
+ if(bankInfo[i].errorCheckType !=
+ bankInfo[0].errorCheckType)
+ {
+ mvOsOutput("Dram: ERR. different ECC settings !!!\n");
+ return MV_ERROR;
+ }
+
+ }
+ else
+ {
+ if( i == 0 ) /* bank 0 doesn't exist */
+ {
+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n");
+ return MV_ERROR;
+ }
+ else
+ {
+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i));
+ bankInfo[i].size = 0; /* Mark this bank as non exist */
+ }
+ }
+ }
+
+#ifdef MV_INCLUDE_SDRAM_CS2
+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size)
+ {
+ MV_DRAM_CS_order[0] = SDRAM_CS2;
+ MV_DRAM_CS_order[1] = SDRAM_CS3;
+ MV_DRAM_CS_order[2] = SDRAM_CS0;
+ MV_DRAM_CS_order[3] = SDRAM_CS1;
+ DRAM_CS_Order[0] = SDRAM_CS2;
+ DRAM_CS_Order[1] = SDRAM_CS3;
+ DRAM_CS_Order[2] = SDRAM_CS0;
+ DRAM_CS_Order[3] = SDRAM_CS1;
+
+ }
+ else
+#endif
+ {
+ MV_DRAM_CS_order[0] = SDRAM_CS0;
+ MV_DRAM_CS_order[1] = SDRAM_CS1;
+ DRAM_CS_Order[0] = SDRAM_CS0;
+ DRAM_CS_Order[1] = SDRAM_CS1;
+#ifdef MV_INCLUDE_SDRAM_CS2
+ MV_DRAM_CS_order[2] = SDRAM_CS2;
+ MV_DRAM_CS_order[3] = SDRAM_CS3;
+ DRAM_CS_Order[2] = SDRAM_CS2;
+ DRAM_CS_Order[3] = SDRAM_CS3;
+#endif
+ }
+
+ for(j = 0; j < MV_DRAM_MAX_CS; j++)
+ {
+ i = MV_DRAM_CS_order[j];
+
+ if (0 == bankInfo[i].size)
+ continue;
+
+ /* Init the CPU window decode */
+ /* Note that the Dimm width might be different then the device DRAM width */
+#ifdef MV78XX0
+ temp = MV_REG_READ(SDRAM_CONFIG_REG);
+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64;
+#else
+ deviceW = 16 /* KW family */;
+#endif
+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16);
+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW));
+
+ /* We can not change DRAM window settings while excecuting */
+ /* code from it. That is why we skip the DRAM CS[0], saving */
+ /* it to the ROM configuration routine */
+
+ numOfAllDevices += bankInfo[i].numberOfDevices;
+ if (i == MV_DRAM_CS_order[0])
+ {
+ MV_U32 sizeToReg;
+ /* Translate the given window size to register format */
+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT);
+ /* Size parameter validity check. */
+ if (-1 == sizeToReg)
+ {
+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n"
+ ,i);
+ return MV_BAD_PARAM;
+ }
+
+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);)
+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS);
+ sizeToReg |= SCSR_WIN_EN;
+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg);
+ }
+ else
+ {
+ dramDecWin.addrWin.baseLow = base;
+ dramDecWin.addrWin.size = size;
+ dramDecWin.enable = MV_TRUE;
+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size));
+
+ /* Check if the DRAM size is more then 3GByte */
+ if (base < 0xC0000000)
+ {
+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size));
+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin))
+ {
+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i);
+ return MV_ERROR;
+ }
+ }
+ }
+
+ base += size;
+
+ /* update the suportedCasLatencies mask */
+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies;
+ }
+
+ /* calculate minimum CAS */
+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl);
+ if (0 == minCas)
+ {
+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n",
+ (busClk / 1000000));
+
+ minCas = DDR2_CL_4; /* Continue with this CAS */
+ mvOsOutput("Set default CAS latency 4\n");
+ }
+
+ /* calc SDRAM_CONFIG_REG and save it to temp register */
+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+
+ /* check if ECC is enabled by the user */
+ if(eccDisable)
+ {
+ /* turn off ECC*/
+ temp &= ~BIT18;
+ }
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG1, temp);
+
+ /* calc SDRAM_MODE_REG and save it to temp register */
+ temp = sdramModeRegCalc(minCas);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG2, temp);
+
+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */
+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG10, temp);
+
+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */
+ TTMode = MV_FALSE;
+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);)
+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) )
+ {
+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) ||
+ (numOfAllDevices > 18) )
+ {
+ mvOsOutput("Enable 2T ");
+ TTMode = MV_TRUE;
+ }
+ }
+
+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode );
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG3, temp);
+
+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */
+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);)
+ /* check if ECC is enabled by the user */
+ if(eccDisable)
+ {
+ /* turn off sample stage if no ecc */
+ temp &= ~SDRAM__D2P_EN;;
+ }
+ MV_REG_WRITE(DRAM_BUF_REG13, temp);
+
+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */
+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG4, temp);
+
+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */
+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG5, temp);
+
+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */
+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG6, temp);
+
+ sdramDDr2OdtConfig(bankInfo);
+
+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */
+ temp = sdramDdr2TimeLoRegCalc(minCas);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG11, temp);
+
+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */
+ temp = sdramDdr2TimeHiRegCalc(minCas);
+ if(-1 == temp)
+ {
+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n");
+ return MV_ERROR;
+ }
+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);)
+ MV_REG_WRITE(DRAM_BUF_REG12, temp);
+#endif
+
+ /* Note that DDR SDRAM Address/Control and Data pad calibration */
+ /* settings is done in mvSdramIfConfig.s */
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvDramIfBankBaseGet - Get DRAM interface bank base.
+*
+* DESCRIPTION:
+* This function returns the 32 bit base address of a given DRAM bank.
+*
+* INPUT:
+* bankNum - Bank number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* DRAM bank size. If bank is disabled or paramter is invalid, the
+* function returns -1.
+*
+*******************************************************************************/
+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum)
+{
+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n",
+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum)));
+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum);
+}
+
+/*******************************************************************************
+* mvDramIfBankSizeGet - Get DRAM interface bank size.
+*
+* DESCRIPTION:
+* This function returns the size of a given DRAM bank.
+*
+* INPUT:
+* bankNum - Bank number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* DRAM bank size. If bank is disabled the function return '0'. In case
+* or paramter is invalid, the function returns -1.
+*
+*******************************************************************************/
+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum)
+{
+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n",
+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum)));
+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum);
+}
+
+
+/*******************************************************************************
+* mvDramIfSizeGet - Get DRAM interface total size.
+*
+* DESCRIPTION:
+* This function get the DRAM total size.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* DRAM total size. In case or paramter is invalid, the function
+* returns -1.
+*
+*******************************************************************************/
+MV_U32 mvDramIfSizeGet(MV_VOID)
+{
+ MV_U32 size = 0, i;
+
+ for(i = 0; i < MV_DRAM_MAX_CS; i++)
+ size += mvDramIfBankSizeGet(i);
+
+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size));
+ return size;
+}
+
+/*******************************************************************************
+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold.
+*
+* DESCRIPTION:
+* The ECC single bit error threshold is the number of single bit
+* errors to happen before the Dunit generates an interrupt.
+* This function set single bit ECC threshold.
+*
+* INPUT:
+* threshold - threshold.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise.
+*
+*******************************************************************************/
+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold)
+{
+ MV_U32 regVal;
+
+ if (threshold > SECR_THRECC_MAX)
+ {
+ return MV_BAD_PARAM;
+ }
+
+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG);
+ regVal &= ~SECR_THRECC_MASK;
+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK));
+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal);
+
+ return MV_OK;
+}
+
+#ifndef MV_STATIC_DRAM_ON_BOARD
+/*******************************************************************************
+* minCasCalc - Calculate the Minimum CAS latency which can be used.
+*
+* DESCRIPTION:
+* Calculate the minimum CAS latency that can be used, base on the DRAM
+* parameters and the SDRAM bus Clock freq.
+*
+* INPUT:
+* busClk - the DRAM bus Clock.
+* pBankInfo - bank info parameters.
+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* The minimum CAS Latency. The function returns 0 if max CAS latency
+* supported by banks is incompatible with system bus clock frequancy.
+*
+*******************************************************************************/
+
+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl)
+{
+ MV_U32 count = 1, j;
+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */
+ MV_U32 startBit, stopBit;
+ MV_U32 minCas0 = 0, minCas2 = 0;
+
+
+ /* DDR 2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD *
+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD *
+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD *
+ *********************************************************/
+
+
+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */
+ if (forcedCl)
+ {
+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10));
+
+ if (forcedCl == 30)
+ pBankInfo->suportedCasLatencies = 0x08;
+ else if (forcedCl == 40)
+ pBankInfo->suportedCasLatencies = 0x10;
+ else if (forcedCl == 50)
+ pBankInfo->suportedCasLatencies = 0x20;
+ else if (forcedCl == 60)
+ pBankInfo->suportedCasLatencies = 0x40;
+ else
+ {
+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n",
+ (forcedCl / 10), (forcedCl % 10));
+ pBankInfo->suportedCasLatencies = 0x10;
+ }
+
+ return pBankInfo->suportedCasLatencies;
+ }
+
+ /* go over the supported cas mask from Max Cas down and check if the */
+ /* SysClk stands in its time requirments. */
+
+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n",
+ pBankInfo->suportedCasLatencies,busClkPs ));
+ count = 1;
+ for(j = 7; j > 0; j--)
+ {
+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
+ {
+ /* Reset the bits for CL incompatible for the sysClk */
+ switch (count)
+ {
+ case 1:
+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs)
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ case 2:
+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs)
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ case 3:
+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs)
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ default:
+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
+ break;
+ }
+ }
+ }
+
+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n",
+ pBankInfo->suportedCasLatencies ));
+
+ count = 1;
+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n",
+ pBankInfo2->suportedCasLatencies,busClkPs ));
+ for(j = 7; j > 0; j--)
+ {
+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 )
+ {
+ /* Reset the bits for CL incompatible for the sysClk */
+ switch (count)
+ {
+ case 1:
+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs)
+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ case 2:
+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs)
+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ case 3:
+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs)
+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
+ count++;
+ break;
+ default:
+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
+ break;
+ }
+ }
+ }
+
+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n",
+ pBankInfo2->suportedCasLatencies ));
+
+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */
+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */
+
+ for(j = startBit; j <= stopBit ; j++)
+ {
+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
+ {
+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j)));
+ minCas0 = (BIT0 << j);
+ break;
+ }
+ }
+
+ for(j = startBit; j <= stopBit ; j++)
+ {
+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 )
+ {
+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j)));
+ minCas2 = (BIT0 << j);
+ break;
+ }
+ }
+
+ if (minCas2 > minCas0)
+ return minCas2;
+ else
+ return minCas0;
+
+ return 0;
+}
+
+/*******************************************************************************
+* sdramConfigRegCalc - Calculate sdram config register
+*
+* DESCRIPTION: Calculate sdram config register optimized value based
+* on the bank info parameters.
+*
+* INPUT:
+* busClk - the DRAM bus Clock.
+* pBankInfo - sdram bank parameters
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram config reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk)
+{
+ MV_U32 sdramConfig = 0;
+ MV_U32 refreshPeriod;
+
+ busClk /= 1000000; /* we work with busClk in MHz */
+
+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG);
+
+ /* figure out the memory refresh internal */
+ switch (pBankInfo->refreshInterval & 0xf)
+ {
+ case 0x0: /* refresh period is 15.625 usec */
+ refreshPeriod = 15625;
+ break;
+ case 0x1: /* refresh period is 3.9 usec */
+ refreshPeriod = 3900;
+ break;
+ case 0x2: /* refresh period is 7.8 usec */
+ refreshPeriod = 7800;
+ break;
+ case 0x3: /* refresh period is 31.3 usec */
+ refreshPeriod = 31300;
+ break;
+ case 0x4: /* refresh period is 62.5 usec */
+ refreshPeriod = 62500;
+ break;
+ case 0x5: /* refresh period is 125 usec */
+ refreshPeriod = 125000;
+ break;
+ default: /* refresh period undefined */
+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n");
+ return -1;
+ }
+
+ /* Now the refreshPeriod is in register format value */
+ refreshPeriod = (busClk * refreshPeriod) / 1000;
+
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n",
+ refreshPeriod));
+
+ /* make sure the refresh value is only 14 bits */
+ if(refreshPeriod > SDRAM_REFRESH_MAX)
+ {
+ refreshPeriod = SDRAM_REFRESH_MAX;
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n",
+ refreshPeriod));
+ }
+
+ /* Clear the refresh field */
+ sdramConfig &= ~SDRAM_REFRESH_MASK;
+
+ /* Set new value to refresh field */
+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK);
+
+ /* registered DRAM ? */
+ if ( pBankInfo->registeredAddrAndControlInputs )
+ {
+ /* it's registered DRAM, so set the reg. DRAM bit */
+ sdramConfig |= SDRAM_REGISTERED;
+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");)
+ }
+
+ /* ECC and IERR support */
+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */
+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */
+
+ if ( pBankInfo->errorCheckType )
+ {
+ sdramConfig |= SDRAM_ECC_EN;
+ sdramConfig |= SDRAM_IERR_REPORTE;
+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n"));
+ }
+ else
+ {
+ sdramConfig |= SDRAM_ECC_DIS;
+ sdramConfig |= SDRAM_IERR_IGNORE;
+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n"));
+ }
+ /* Set static default settings */
+ sdramConfig |= SDRAM_CONFIG_DV;
+
+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n",
+ sdramConfig));
+
+ return sdramConfig;
+}
+
+/*******************************************************************************
+* sdramModeRegCalc - Calculate sdram mode register
+*
+* DESCRIPTION: Calculate sdram mode register optimized value based
+* on the bank info parameters and the minCas.
+*
+* INPUT:
+* minCas - minimum CAS supported.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram mode reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramModeRegCalc(MV_U32 minCas)
+{
+ MV_U32 sdramMode;
+
+ sdramMode = MV_REG_READ(SDRAM_MODE_REG);
+
+ /* Clear CAS Latency field */
+ sdramMode &= ~SDRAM_CL_MASK;
+
+ DB(mvOsPrintf("DRAM CAS Latency ");)
+
+ switch (minCas)
+ {
+ case DDR2_CL_3:
+ sdramMode |= SDRAM_DDR2_CL_3;
+ DB(mvOsPrintf("3.\n");)
+ break;
+ case DDR2_CL_4:
+ sdramMode |= SDRAM_DDR2_CL_4;
+ DB(mvOsPrintf("4.\n");)
+ break;
+ case DDR2_CL_5:
+ sdramMode |= SDRAM_DDR2_CL_5;
+ DB(mvOsPrintf("5.\n");)
+ break;
+ case DDR2_CL_6:
+ sdramMode |= SDRAM_DDR2_CL_6;
+ DB(mvOsPrintf("6.\n");)
+ break;
+ default:
+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n");
+ return -1;
+ }
+
+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode ));
+
+ return sdramMode;
+}
+/*******************************************************************************
+* sdramExtModeRegCalc - Calculate sdram Extended mode register
+*
+* DESCRIPTION:
+* Return sdram Extended mode register value based
+* on the bank info parameters and bank presence.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* busClk - DRAM frequency
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram Extended mode reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk)
+{
+ MV_U32 populateBanks = 0;
+ int bankNum;
+
+ /* Represent the populate banks in binary form */
+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ if (0 != pBankInfo[bankNum].size)
+ {
+ populateBanks |= (1 << bankNum);
+ }
+ }
+
+ switch(populateBanks)
+ {
+ case(BANK_PRESENT_CS0):
+ case(BANK_PRESENT_CS0_CS1):
+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV;
+
+ case(BANK_PRESENT_CS0_CS2):
+ case(BANK_PRESENT_CS0_CS1_CS2):
+ case(BANK_PRESENT_CS0_CS2_CS3):
+ case(BANK_PRESENT_CS0_CS2_CS3_CS4):
+ if (busClk >= MV_BOARD_SYSCLK_267MHZ)
+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV;
+ else
+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV;
+
+ default:
+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n");
+ return -1;
+ }
+ return 0;
+}
+
+/*******************************************************************************
+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register
+*
+* DESCRIPTION: Calculate sdram dunit control low register optimized value based
+* on the bank info parameters and the minCas.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* minCas - minimum CAS supported.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram dunit control low reg value.
+*
+*******************************************************************************/
+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode)
+{
+ MV_U32 dunitCtrlLow, cl;
+ MV_U32 sbOutR[4]={3,5,7,9} ;
+ MV_U32 sbOutU[4]={1,3,5,7} ;
+
+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG);
+
+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n"));
+
+ /* Clear StBurstOutDel field */
+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK;
+
+ /* Clear StBurstInDel field */
+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK;
+
+ /* Clear CtrlPos field */
+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK;
+
+ /* Clear 2T field */
+ dunitCtrlLow &= ~SDRAM_2T_MASK;
+ if (TTMode == MV_TRUE)
+ {
+ dunitCtrlLow |= SDRAM_2T_MODE;
+ }
+
+ /* For proper sample of read data set the Dunit Control register's */
+ /* stBurstInDel bits [27:24] */
+ /* 200MHz - 267MHz None reg = CL + 1 */
+ /* 200MHz - 267MHz reg = CL + 2 */
+ /* > 267MHz None reg = CL + 2 */
+ /* > 267MHz reg = CL + 3 */
+
+ /* For proper sample of read data set the Dunit Control register's */
+ /* stBurstOutDel bits [23:20] */
+ /********-********-********-********-
+ * CL=3 | CL=4 | CL=5 | CL=6 |
+ *********-********-********-********-
+ Not Reg. * 0001 | 0011 | 0101 | 0111 |
+ *********-********-********-********-
+ Registered * 0011 | 0101 | 0111 | 1001 |
+ *********-********-********-********/
+
+ /* Set Dunit Control low default value */
+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV;
+
+ switch (minCas)
+ {
+ case DDR2_CL_3: cl = 3; break;
+ case DDR2_CL_4: cl = 4; break;
+ case DDR2_CL_5: cl = 5; break;
+ case DDR2_CL_6: cl = 6; break;
+ default:
+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas);
+ return -1;
+ }
+
+ /* registerd DDR SDRAM? */
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ {
+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS;
+ }
+ else
+ {
+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS;
+ }
+
+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk));
+
+ if (busClk <= MV_BOARD_SYSCLK_267MHZ)
+ {
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ cl = cl + 2;
+ else
+ cl = cl + 1;
+ }
+ else
+ {
+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE)
+ cl = cl + 3;
+ else
+ cl = cl + 2;
+ }
+
+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl));
+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS;
+
+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow ));
+
+ return dunitCtrlLow;
+}
+
+/*******************************************************************************
+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register
+*
+* DESCRIPTION: Calculate sdram dunit control high register optimized value based
+* on the bus clock.
+*
+* INPUT:
+* busClk - DRAM frequency.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram dunit control high reg value.
+*
+*******************************************************************************/
+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk)
+{
+ MV_U32 dunitCtrlHigh;
+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG);
+ if(busClk > MV_BOARD_SYSCLK_300MHZ)
+ dunitCtrlHigh |= SDRAM__P2D_EN;
+ else
+ dunitCtrlHigh &= ~SDRAM__P2D_EN;
+
+ if(busClk > MV_BOARD_SYSCLK_267MHZ)
+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN);
+
+ /* If ECC support we turn on D2P sample */
+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */
+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ))
+ dunitCtrlHigh |= SDRAM__D2P_EN;
+
+ return dunitCtrlHigh;
+}
+
+/*******************************************************************************
+* sdramAddrCtrlRegCalc - Calculate sdram address control register
+*
+* DESCRIPTION: Calculate sdram address control register optimized value based
+* on the bank info parameters and the minCas.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram address control reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1)
+{
+ MV_U32 addrCtrl = 0;
+
+ if (pBankInfoDIMM1->size)
+ {
+ switch (pBankInfoDIMM1->sdramWidth)
+ {
+ case 4: /* memory is x4 */
+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n");
+ return -1;
+ break;
+ case 8: /* memory is x8 */
+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3);
+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n"));
+ break;
+ case 16:
+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3);
+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n"));
+ break;
+ default: /* memory width unsupported */
+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n");
+ return -1;
+ }
+ }
+
+ switch (pBankInfo->sdramWidth)
+ {
+ case 4: /* memory is x4 */
+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n");
+ return -1;
+ break;
+ case 8: /* memory is x8 */
+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1);
+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n"));
+ break;
+ case 16:
+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1);
+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n"));
+ break;
+ default: /* memory width unsupported */
+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n");
+ return -1;
+ }
+
+ /* Note that density is in MB units */
+ switch (pBankInfo->deviceDensity)
+ {
+ case 256: /* 256 Mbit */
+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1);
+ break;
+ case 512: /* 512 Mbit */
+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1);
+ break;
+ case 1024: /* 1 Gbit */
+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n"));
+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1);
+ break;
+ case 2048: /* 2 Gbit */
+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n"));
+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1);
+ break;
+ default:
+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n",
+ pBankInfo->deviceDensity);
+ return -1;
+ }
+
+ if (pBankInfoDIMM1->size)
+ {
+ switch (pBankInfoDIMM1->deviceDensity)
+ {
+ case 256: /* 256 Mbit */
+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3);
+ break;
+ case 512: /* 512 Mbit */
+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n"));
+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3);
+ break;
+ case 1024: /* 1 Gbit */
+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n"));
+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3);
+ break;
+ case 2048: /* 2 Gbit */
+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n"));
+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3);
+ break;
+ default:
+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n",
+ pBankInfoDIMM1->deviceDensity);
+ return -1;
+ }
+ }
+ /* SDRAM address control */
+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl));
+
+ return addrCtrl;
+}
+
+/*******************************************************************************
+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register
+*
+* DESCRIPTION:
+* This function calculates sdram timing control low register
+* optimized value based on the bank info parameters and the minCas.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* minCas - minimum CAS supported.
+* busClk - Bus clock
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram timing control low reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk)
+{
+ MV_U32 tRp = 0;
+ MV_U32 tRrd = 0;
+ MV_U32 tRcd = 0;
+ MV_U32 tRas = 0;
+ MV_U32 tWr = 0;
+ MV_U32 tWtr = 0;
+ MV_U32 tRtp = 0;
+ MV_U32 timeCtrlLow = 0;
+
+ MV_U32 bankNum;
+
+ busClk = busClk / 1000000; /* In MHz */
+
+ /* Scan all DRAM banks to find maximum timing values */
+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime);
+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive);
+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay);
+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth);
+ }
+
+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */
+ /* by shifting the data two bits right. */
+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */
+ tRrd = tRrd >> 2;
+ tRcd = tRcd >> 2;
+
+ /* Extract clock cycles from time parameter. We need to round up */
+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp));
+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0);
+ /* JEDEC min reqeirments tRrd = 2 */
+ if (tRrd < 2)
+ tRrd = 2;
+ DB(mvOsPrintf("tRrd = %d ", tRrd));
+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("tRcd = %d ", tRcd));
+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("tRas = %d ", tRas));
+
+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */
+ /* Scan all DRAM banks to find maximum timing values */
+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime);
+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay);
+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay);
+ }
+
+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */
+ /* part by shifting the data two bits right. */
+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */
+ tWtr = tWtr >> 2;
+ tRtp = tRtp >> 2;
+ /* Extract clock cycles from time parameter. We need to round up */
+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0);
+ DB(mvOsPrintf("tWr = %d ", tWr));
+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0);
+ /* JEDEC min reqeirments tWtr = 2 */
+ if (tWtr < 2)
+ tWtr = 2;
+ DB(mvOsPrintf("tWtr = %d ", tWtr));
+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0);
+ /* JEDEC min reqeirments tRtp = 2 */
+ if (tRtp < 2)
+ tRtp = 2;
+ DB(mvOsPrintf("tRtp = %d ", tRtp));
+
+ /* Note: value of 0 in register means one cycle, 1 means two and so on */
+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) |
+ ((tRrd - 1) << SDRAM_TRRD_OFFS) |
+ ((tRcd - 1) << SDRAM_TRCD_OFFS) |
+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)|
+ ((tWr - 1) << SDRAM_TWR_OFFS) |
+ ((tWtr - 1) << SDRAM_TWTR_OFFS) |
+ ((tRtp - 1) << SDRAM_TRTP_OFFS));
+
+ /* Check extended tRas bit */
+ if ((tRas - 1) & BIT4)
+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS);
+
+ return timeCtrlLow;
+}
+
+/*******************************************************************************
+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register
+*
+* DESCRIPTION:
+* This function calculates sdram timing control high register
+* optimized value based on the bank info parameters and the bus clock.
+*
+* INPUT:
+* pBankInfo - sdram bank parameters
+* busClk - Bus clock
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* sdram timing control high reg value.
+*
+*******************************************************************************/
+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk)
+{
+ MV_U32 tRfc;
+ MV_U32 timingHigh;
+ MV_U32 timeNs = 0;
+ MV_U32 bankNum;
+
+ busClk = busClk / 1000000; /* In MHz */
+
+ /* Set DDR timing high register static configuration bits */
+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG);
+
+ /* Set DDR timing high register default value */
+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV;
+
+ /* Clear tRfc field */
+ timingHigh &= ~SDRAM_TRFC_MASK;
+
+ /* Scan all DRAM banks to find maximum timing values */
+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd);
+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n",
+ pBankInfo[bankNum].minRefreshToActiveCmd));
+ }
+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV)
+ {
+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS;
+ }
+
+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0);
+ /* Note: value of 0 in register means one cycle, 1 means two and so on */
+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc));
+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS);
+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc));
+
+ /* SDRAM timing high */
+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh));
+
+ return timingHigh;
+}
+/*******************************************************************************
+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers.
+*
+* DESCRIPTION:
+* This function config DDR2 On Die Termination (ODT) registers.
+*
+* INPUT:
+* pBankInfo - bank info parameters.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* None
+*******************************************************************************/
+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo)
+{
+ MV_U32 populateBanks = 0;
+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl;
+ int bankNum;
+
+ /* Represent the populate banks in binary form */
+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++)
+ {
+ if (0 != pBankInfo[bankNum].size)
+ {
+ populateBanks |= (1 << bankNum);
+ }
+ }
+
+ switch(populateBanks)
+ {
+ case(BANK_PRESENT_CS0):
+ case(BANK_PRESENT_CS0_CS1):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV;
+ break;
+ case(BANK_PRESENT_CS0_CS2):
+ case(BANK_PRESENT_CS0_CS1_CS2):
+ case(BANK_PRESENT_CS0_CS2_CS3):
+ case(BANK_PRESENT_CS0_CS2_CS3_CS4):
+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV;
+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV;
+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV;
+ break;
+ default:
+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"));
+ return;
+ }
+ /* DDR2 SDRAM ODT ctrl low */
+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow));
+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow);
+
+ /* DDR2 SDRAM ODT ctrl high */
+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh));
+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh);
+
+ /* DDR2 DUNIT ODT ctrl */
+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) ||
+ (mvCtrlModelGet() == MV_76100_DEV_ID) ||
+ (mvCtrlModelGet() == MV_78100_DEV_ID) ||
+ (mvCtrlModelGet() == MV_78200_DEV_ID) )
+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */
+
+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl));
+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl);
+ return;
+}
+/*******************************************************************************
+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers.
+*
+* DESCRIPTION:
+* This function config DDR2 DRAM Timing low registers.
+*
+* INPUT:
+* minCas - minimum CAS supported.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* DDR2 sdram timing low reg value.
+*******************************************************************************/
+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas)
+{
+ MV_U8 cl = -1;
+ MV_U32 ddr2TimeLoReg;
+
+ /* read and clear the feilds we are going to set */
+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG);
+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK |
+ SD2TLR_TODT_OFF_RD_MASK |
+ SD2TLR_TODT_ON_CTRL_RD_MASK |
+ SD2TLR_TODT_OFF_CTRL_RD_MASK);
+
+ if( minCas == DDR2_CL_3 )
+ {
+ cl = 3;
+ }
+ else if( minCas == DDR2_CL_4 )
+ {
+ cl = 4;
+ }
+ else if( minCas == DDR2_CL_5 )
+ {
+ cl = 5;
+ }
+ else if( minCas == DDR2_CL_6 )
+ {
+ cl = 6;
+ }
+ else
+ {
+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n",
+ minCas));
+ cl = 4;
+ }
+
+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS);
+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS);
+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS);
+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS);
+
+ /* DDR2 SDRAM timing low */
+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg));
+
+ return ddr2TimeLoReg;
+}
+
+/*******************************************************************************
+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers.
+*
+* DESCRIPTION:
+* This function config DDR2 DRAM Timing high registers.
+*
+* INPUT:
+* minCas - minimum CAS supported.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* DDR2 sdram timing high reg value.
+*******************************************************************************/
+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas)
+{
+ MV_U8 cl = -1;
+ MV_U32 ddr2TimeHiReg;
+
+ /* read and clear the feilds we are going to set */
+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG);
+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK |
+ SD2THR_TODT_OFF_WR_MASK |
+ SD2THR_TODT_ON_CTRL_WR_MASK |
+ SD2THR_TODT_OFF_CTRL_WR_MASK);
+
+ if( minCas == DDR2_CL_3 )
+ {
+ cl = 3;
+ }
+ else if( minCas == DDR2_CL_4 )
+ {
+ cl = 4;
+ }
+ else if( minCas == DDR2_CL_5 )
+ {
+ cl = 5;
+ }
+ else if( minCas == DDR2_CL_6 )
+ {
+ cl = 6;
+ }
+ else
+ {
+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n",
+ minCas);
+ cl = 4;
+ }
+
+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS);
+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS);
+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS);
+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS);
+
+ /* DDR2 SDRAM timin high */
+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg));
+
+ return ddr2TimeHiReg;
+}
+#endif
+
+/*******************************************************************************
+* mvDramIfCalGet - Get CAS Latency
+*
+* DESCRIPTION:
+* This function get the CAS Latency.
+*
+* INPUT:
+* None
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* CAS latency times 10 (to avoid using floating point).
+*
+*******************************************************************************/
+MV_U32 mvDramIfCalGet(void)
+{
+ MV_U32 sdramCasLat, casLatMask;
+
+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK);
+
+ switch (casLatMask)
+ {
+ case SDRAM_DDR2_CL_3:
+ sdramCasLat = 30;
+ break;
+ case SDRAM_DDR2_CL_4:
+ sdramCasLat = 40;
+ break;
+ case SDRAM_DDR2_CL_5:
+ sdramCasLat = 50;
+ break;
+ case SDRAM_DDR2_CL_6:
+ sdramCasLat = 60;
+ break;
+ default:
+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n");
+ return -1;
+ }
+
+ return sdramCasLat;
+}
+
+
+/*******************************************************************************
+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode -
+*
+* DESCRIPTION:
+* add support in power management.
+*
+*
+* INPUT:
+* None
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* None
+*
+*******************************************************************************/
+
+MV_VOID mvDramIfSelfRefreshSet()
+{
+ MV_U32 operReg;
+
+ operReg = MV_REG_READ(SDRAM_OPERATION_REG);
+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH);
+ /* Read until register is reset to 0 */
+ while(MV_REG_READ(SDRAM_OPERATION_REG));
+}
+/*******************************************************************************
+* mvDramIfDimGetSPDversion - return DIMM SPD version.
+*
+* DESCRIPTION:
+* This function prints the DRAM controller information.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum)
+{
+ MV_DIMM_INFO dimmInfo;
+ if (bankNum >= MV_DRAM_MAX_CS )
+ {
+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n"));
+ return ;
+ }
+ memset(&dimmInfo,0,sizeof(dimmInfo));
+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo))
+ {
+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n"));
+ return ;
+ }
+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10;
+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10;
+}
+/*******************************************************************************
+* mvDramIfShow - Show DRAM controller information.
+*
+* DESCRIPTION:
+* This function prints the DRAM controller information.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void mvDramIfShow(void)
+{
+ int i, sdramCasLat, sdramCsSize;
+ MV_U32 Major=0, Minor=0;
+
+ mvOsOutput("DRAM Controller info:\n");
+
+ mvOsOutput("Total DRAM ");
+ mvSizePrint(mvDramIfSizeGet());
+ mvOsOutput("\n");
+
+ for(i = 0; i < MV_DRAM_MAX_CS; i++)
+ {
+ sdramCsSize = mvDramIfBankSizeGet(i);
+ if (sdramCsSize)
+ {
+ if (0 == (i & 1))
+ {
+ mvDramIfDimGetSPDversion(&Major, &Minor,i);
+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor);
+ }
+ mvOsOutput("\tDRAM CS[%d] ", i);
+ mvSizePrint(sdramCsSize);
+ mvOsOutput("\n");
+ }
+ }
+ sdramCasLat = mvDramIfCalGet();
+
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN)
+ {
+ mvOsOutput("ECC enabled, ");
+ }
+ else
+ {
+ mvOsOutput("ECC Disabled, ");
+ }
+
+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED)
+ {
+ mvOsOutput("Registered DIMM\n");
+ }
+ else
+ {
+ mvOsOutput("Non registered DIMM\n");
+ }
+
+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10);
+}
+/*******************************************************************************
+* mvDramIfGetFirstCS - find the DRAM bank on the lower address
+*
+*
+* DESCRIPTION:
+* This function return the fisrt CS on address 0
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* SDRAM_CS0 or SDRAM_CS2
+*
+*******************************************************************************/
+MV_U32 mvDramIfGetFirstCS(void)
+{
+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS];
+
+ if (DRAM_CS_Order[0] == N_A)
+ {
+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]);
+#ifdef MV_INCLUDE_SDRAM_CS2
+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]);
+#endif
+
+#ifdef MV_INCLUDE_SDRAM_CS2
+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size)
+ {
+ DRAM_CS_Order[0] = SDRAM_CS2;
+ DRAM_CS_Order[1] = SDRAM_CS3;
+ DRAM_CS_Order[2] = SDRAM_CS0;
+ DRAM_CS_Order[3] = SDRAM_CS1;
+
+ return SDRAM_CS2;
+ }
+#endif
+ DRAM_CS_Order[0] = SDRAM_CS0;
+ DRAM_CS_Order[1] = SDRAM_CS1;
+#ifdef MV_INCLUDE_SDRAM_CS2
+ DRAM_CS_Order[2] = SDRAM_CS2;
+ DRAM_CS_Order[3] = SDRAM_CS3;
+#endif
+ return SDRAM_CS0;
+ }
+ return DRAM_CS_Order[0];
+}
+/*******************************************************************************
+* mvDramIfGetCSorder -
+*
+*
+* DESCRIPTION:
+* This function return the fisrt CS on address 0
+*
+* INPUT:
+* CS number.
+*
+* OUTPUT:
+* CS order.
+*
+* RETURN:
+* SDRAM_CS0 or SDRAM_CS2
+*
+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine
+*******************************************************************************/
+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder )
+{
+ return DRAM_CS_Order[csOrder];
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h
new file mode 100644
index 000000000..23f2e540c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h
@@ -0,0 +1,172 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvDramIfh
+#define __INCmvDramIfh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* includes */
+#include "ddr2/mvDramIfRegs.h"
+#include "ddr2/mvDramIfConfig.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/* defines */
+/* DRAM Timing parameters */
+#define SDRAM_TWR 15 /* ns tWr */
+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */
+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */
+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */
+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */
+
+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */
+#define ECC_DISABLE 1 /* Force ECC to Disable */
+#define ECC_ENABLE 0 /* Force ECC to ENABLE */
+/* typedefs */
+
+/* enumeration for memory types */
+typedef enum _mvMemoryType
+{
+ MEM_TYPE_SDRAM,
+ MEM_TYPE_DDR1,
+ MEM_TYPE_DDR2
+}MV_MEMORY_TYPE;
+
+/* enumeration for DDR2 supported CAS Latencies */
+typedef enum _mvDimmDdr2Cas
+{
+ DDR2_CL_3 = 0x08,
+ DDR2_CL_4 = 0x10,
+ DDR2_CL_5 = 0x20,
+ DDR2_CL_6 = 0x40,
+ DDR2_CL_FAULT
+} MV_DIMM_DDR2_CAS;
+
+
+typedef struct _mvDramBankInfo
+{
+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */
+
+ /* DIMM dimensions */
+ MV_U32 numOfRowAddr;
+ MV_U32 numOfColAddr;
+ MV_U32 dataWidth;
+ MV_U32 errorCheckType; /* ECC , PARITY..*/
+ MV_U32 sdramWidth; /* 4,8,16 or 32 */
+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
+ MV_U32 burstLengthSupported;
+ MV_U32 numOfBanksOnEachDevice;
+ MV_U32 suportedCasLatencies;
+ MV_U32 refreshInterval;
+
+ /* DIMM timing parameters */
+ MV_U32 minCycleTimeAtMaxCasLatPs;
+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
+ MV_U32 minRowPrechargeTime;
+ MV_U32 minRowActiveToRowActive;
+ MV_U32 minRasToCasDelay;
+ MV_U32 minRasPulseWidth;
+ MV_U32 minWriteRecoveryTime; /* DDR2 only */
+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */
+
+ /* Parameters calculated from the extracted DIMM information */
+ MV_U32 size;
+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */
+ MV_U32 numberOfDevices;
+
+ /* DIMM attributes (MV_TRUE for yes) */
+ MV_BOOL registeredAddrAndControlInputs;
+ MV_BOOL registeredDQMBinputs;
+
+}MV_DRAM_BANK_INFO;
+
+#include "ddr2/spd/mvSpd.h"
+
+/* mvDramIf.h API list */
+MV_VOID mvDramIfBasicAsmInit(MV_VOID);
+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable);
+MV_VOID _mvDramIfConfig(int entryNum);
+
+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum);
+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum);
+MV_U32 mvDramIfSizeGet(MV_VOID);
+MV_U32 mvDramIfCalGet(void);
+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold);
+MV_VOID mvDramIfSelfRefreshSet(void);
+void mvDramIfShow(void);
+MV_U32 mvDramIfGetFirstCS(void);
+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder );
+MV_U32 mvDramCsSizeGet(MV_U32 csNum);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvDramIfh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S
new file mode 100644
index 000000000..76723816d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S
@@ -0,0 +1,986 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define _ASMLANGUAGE
+#define MV_ASMLANGUAGE
+#include "mvSysHwConfig.h"
+#include "mvOsAsm.h"
+#include "boardEnv/mvBoardEnvSpec.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "mvDramIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "ctrlEnv/mvCtrlEnvAsm.h"
+#include "mvCommon.h"
+
+/* defines */
+
+#if defined(MV_STATIC_DRAM_ON_BOARD)
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/******************************************************************************
+*
+*
+*
+*
+*******************************************************************************/
+#if defined(DB_MV78XX0) || defined(DB_MV88F632X)
+/* DDR2 boards 512MB 333MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#elif defined(RD_MV78XX0_AMC)
+/* On board DDR2 512MB 400MHz CL5 */
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#elif defined(RD_MV78XX0_H3C)
+/* DDR2 boards 512MB 333MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#elif defined(RD_MV78XX0_PCAC)
+/* DDR2 boards 256MB 200MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#else
+/* DDR2 MV88F6281 boards 256MB 400MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+#endif /* MV78XX0 */
+
+ .globl _mvDramIfStaticInit
+_mvDramIfStaticInit:
+
+ mov r11, LR /* Save link register */
+ mov r10, r2
+
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+ orr r6, r6, #BIT4 /* Enable 2T mode */
+ bic r6, r6, #BIT6 /* clear ctrlPos */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+#endif
+
+ /*DDR SDRAM Initialization Control */
+ ldr r6, =DSICR_INIT_EN
+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+ and r6, r6, #DSICR_INIT_EN
+ cmp r6, #0
+ bne 2b
+
+ /* If we boot from NAND jump to DRAM address */
+ mov r5, #1
+ ldr r6, =dramBoot1
+ str r5, [r6] /* We started executing from DRAM */
+
+ ldr r6, dramBoot1
+ cmp r6, #0
+ bne 1f
+
+ /* set all dram windows to 0 */
+ mov r6, #0
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1))
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2))
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3))
+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
+
+
+ /* set all dram configuration in temp registers */
+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
+ ldr r6, = STATIC_SDRAM_CONFIG
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
+ ldr r6, = STATIC_SDRAM_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
+ ldr r6, = STATIC_DUNIT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
+ ldr r6, = STATIC_SDRAM_ADDR_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
+ ldr r6, = STATIC_SDRAM_EXT_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11)
+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12)
+#ifndef MV_NAND_BOOT
+ ldr r6, = STATIC_DUNIT_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13)
+#endif
+
+ ldr sp,=0
+ bl _mvDramIfConfig
+ ldr r0, =0
+#ifdef MV78XX0
+ bl _mvDramIfEccMemInit
+#endif
+1:
+ mov r2, r10
+ mov PC, r11 /* r11 is saved link register */
+
+#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */
+
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/*******************************************************************************
+* mvDramIfBasicInit - Basic initialization of DRAM interface
+*
+* DESCRIPTION:
+* The function will initialize the DRAM for basic usage. The function
+* will use the TWSI assembly API to extract DIMM parameters according
+* to which DRAM interface will be initialized.
+* The function referes to the following DRAM parameters:
+* 1) DIMM is registered or not.
+* 2) DIMM width detection.
+* 3) DIMM density.
+*
+* INPUT:
+* r3 - required size for initial DRAM.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+* Note:
+* r4 holds I2C EEPROM address
+* r5 holds SDRAM register base address
+* r7 holds returned values
+* r8 holds SDRAM various configuration registers value.
+* r11 holds return function address.
+*******************************************************************************/
+/* Setting the offsets of the I2C registers */
+#define DIMM_TYPE_OFFSET 2
+#define NUM_OF_ROWS_OFFSET 3
+#define NUM_OF_COLS_OFFSET 4
+#define NUM_OF_RANKS 5
+#define DIMM_CONFIG_TYPE 11
+#define SDRAM_WIDTH_OFFSET 13
+#define NUM_OF_BANKS_OFFSET 17
+#define SUPPORTED_CL_OFFSET 18
+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
+#define SDRAM_MODULES_ATTR_OFFSET 21
+#define RANK_SIZE_OFFSET 31
+
+#define DRAM_DEV_DENSITY_128M 128
+#define DRAM_DEV_DENSITY_256M 256
+#define DRAM_DEV_DENSITY_512M 512
+#define DRAM_DEV_DENSITY_1G 1024
+#define DRAM_DEV_DENSITY_2G 2048
+
+#define DRAM_RANK_DENSITY_128M 0x20
+#define DRAM_RANK_DENSITY_256M 0x40
+#define DRAM_RANK_DENSITY_512M 0x80
+#define DRAM_RANK_DENSITY_1G 0x1
+#define DRAM_RANK_DENSITY_2G 0x2
+
+ .globl _mvDramIfBasicInit
+ .extern _i2cInit
+_mvDramIfBasicInit:
+
+ mov r11, LR /* Save link register */
+
+ /* Set Dunit high control register */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
+#ifdef MV78XX0
+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
+#endif
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
+
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+ orr r6, r6, #BIT4 /* Enable 2T mode */
+ bic r6, r6, #BIT6 /* clear ctrlPos */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+#endif
+
+ /*DDR SDRAM Initialization Control */
+ ldr r6, =DSICR_INIT_EN
+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+ and r6, r6, #DSICR_INIT_EN
+ cmp r6, #0
+ bne 2b
+
+ mov r5, #1
+ ldr r8, =dramBoot1
+ str r5, [r8] /* We started executing from DRAM */
+
+ /* If we boot from NAND jump to DRAM address */
+ ldr r8, dramBoot1
+ cmp r8, #0
+ movne pc, r11
+
+ bl _i2cInit /* Initialize TWSI master */
+
+ /* Check if we have more then 1 dimm */
+ ldr r6, =0
+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
+#ifdef MV78XX0
+ bl _is_Second_Dimm_Exist
+ beq single_dimm
+ ldr r6, =1
+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
+single_dimm:
+ bl _i2cInit /* Initialize TWSI master */
+#endif
+
+ /* Get default SDRAM Config values */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+
+ /* Get registered/non registered info from DIMM */
+ bl _is_Registered
+ beq nonRegistered
+
+setRegistered:
+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
+nonRegistered:
+#ifdef MV78XX0
+ /* Get ECC/non ECC info from DIMM */
+ bl _is_Ecc
+ beq setConfigReg
+
+setEcc:
+ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */
+#endif
+setConfigReg:
+ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1)
+
+ /* Set maximum CL supported by DIMM */
+ bl _get_CAL
+
+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
+ clz r6, r7
+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
+
+casDdr2:
+ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x32 /* Assuming MAX CL = 3 */
+ cmp r6, #3 /* If CL = 3 break */
+ beq casDdr2Cont
+
+ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x42 /* Assuming MAX CL = 4 */
+ cmp r6, #4 /* If CL = 4 break */
+ beq casDdr2Cont
+
+ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x52 /* Assuming MAX CL = 5 */
+ cmp r6, #5 /* If CL = 5 break */
+ beq casDdr2Cont
+
+ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x62 /* Assuming MAX CL = 6 */
+ cmp r6, #6 /* If CL = 5 break */
+ beq casDdr2Cont
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig /* This is an error !! */
+casDdr2Cont:
+
+ /* Get default SDRAM Mode values */
+ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG)
+ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */
+ orr r6, r6, r8
+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2)
+
+ /* Set Dunit control register according to max CL detected */
+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1)
+ tst r6, #SDRAM_REGISTERED
+ beq setDunitReg
+ mov r7, r3
+
+setDunitReg:
+#ifdef MV78XX0
+ /* Set SDRAM Extended Mode register for double DIMM */
+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
+
+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
+ ldr r5, =MSAR_SYSCLCK_MASK
+ and r4, r4, r5
+ ldr r5, =MSAR_SYSCLCK_333
+ cmp r4, r5
+ ble Clock333
+ add r7, r7, #0x10
+Clock333:
+#endif
+
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */
+ orr r6, r6, #BIT4 /* Enable 2T mode */
+ bic r6, r6, #BIT6 /* clear ctrlPos */
+ orr r6, r6, r7, LSL #20
+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3)
+
+ /* Set Dunit high control register */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
+#ifdef MV78XX0
+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
+#endif
+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13)
+
+ /* DIMM density configuration*/
+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
+Density:
+ /* Get bank 0 and 1 density */
+ ldr r6, =0
+ bl _getDensity
+
+ mov r8, r7
+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */
+ /* For example 0x10000000 --> 0x1000 */
+
+ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1))
+ cmp r8, #DRAM_DEV_DENSITY_256M
+ beq get_bank_2_density
+
+ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1))
+ cmp r8, #DRAM_DEV_DENSITY_512M
+ beq get_bank_2_density
+
+ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1))
+ cmp r8, #DRAM_DEV_DENSITY_1G
+ beq get_bank_2_density
+
+ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1))
+ cmp r8, #DRAM_DEV_DENSITY_2G
+ beq get_bank_2_density
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+get_bank_2_density:
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne get_width
+
+ /* Get bank 2 and 3 density */
+ ldr r6, =2
+ bl _getDensity
+
+ mov r8, r7
+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */
+ /* For example 0x10000000 --> 0x1000 */
+
+ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3))
+ cmp r8, #DRAM_DEV_DENSITY_256M
+ beq get_width
+
+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
+ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3))
+ cmp r8, #DRAM_DEV_DENSITY_512M
+ beq get_width
+
+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
+ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3))
+ cmp r8, #DRAM_DEV_DENSITY_1G
+ beq get_width
+
+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
+ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3))
+ cmp r8, #DRAM_DEV_DENSITY_2G
+ beq get_width
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+ /* Get SDRAM width */
+get_width:
+ /* Get bank 0 and 1 width */
+ ldr r6, =0
+ bl _get_width
+
+ cmp r7, #8 /* x8 devices */
+ beq get_bank_2_width
+
+ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */
+ cmp r7, #16
+ beq get_bank_2_width
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+get_bank_2_width:
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne densCont
+
+ /* Get bank 2 and 3 width */
+ ldr r6, =2
+ bl _get_width
+
+ cmp r7, #8 /* x8 devices */
+ beq densCont
+
+ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */
+ cmp r7, #16
+ beq densCont
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+densCont:
+ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4)
+
+ /* Set SDRAM timing control low register */
+ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT
+ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5)
+
+ /* Set SDRAM timing control high register */
+ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT
+
+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
+ ldr r5, =MSAR_SYSCLCK_MASK
+ and r4, r4, r5
+ ldr r5, =MSAR_SYSCLCK_333
+ cmp r4, r5
+ blt timingHighClock333
+ orr r6, r6, #BIT9
+
+timingHighClock333:
+ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
+
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne single_dimm_odt
+
+ /* Set SDRAM ODT control low register for double DIMM*/
+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
+
+ /* Set DUNIT ODT control register for double DIMM */
+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
+
+#ifdef MV78XX0
+ /* Set SDRAM Extended Mode register for double DIMM */
+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
+
+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
+ ldr r5, =MSAR_SYSCLCK_MASK
+ and r4, r4, r5
+ ldr r5, =MSAR_SYSCLCK_267
+ cmp r4, r5
+ beq slow_dram_clock_rtt
+ ldr r5, =MSAR_SYSCLCK_300
+ cmp r4, r5
+ beq slow_dram_clock_rtt
+ ldr r5, =MSAR_SYSCLCK_333
+ cmp r4, r5
+ beq fast_dram_clock_rtt
+ ldr r5, =MSAR_SYSCLCK_400
+ cmp r4, r5
+ beq fast_dram_clock_rtt
+
+ b slow_dram_clock_rtt
+
+fast_dram_clock_rtt:
+ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
+ b odt_config_end
+#endif
+slow_dram_clock_rtt:
+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
+ b odt_config_end
+
+single_dimm_odt:
+ /* Set SDRAM ODT control low register */
+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
+
+ /* Set DUNIT ODT control register */
+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
+
+ /* Set SDRAM Extended Mode register */
+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
+
+odt_config_end:
+ /* SDRAM ODT control high register is left as default */
+ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8)
+
+ /*Read CL and set the DDR2 registers accordingly */
+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2)
+ and r6, r6, #SDRAM_CL_MASK
+ mov r4, r6
+ orr r4, r4, r6, LSL #4
+ orr r4, r4, r6, LSL #8
+ orr r4, r4, r6, LSL #12
+ mov r5, #0x30000
+ add r4, r4, r5
+ sub r4, r4, #0x30
+ /* Set SDRAM Ddr2 Timing Low register */
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11)
+
+ /* Set SDRAM Ddr2 Timing High register */
+ mov r4, r4, LSR #4
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12)
+
+timeParamDone:
+ /* Close all windows */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+
+ /* Set sdram bank 0 size and enable it */
+ ldr r6, =0
+ bl _mvDramIfGetDimmSizeFromSpd
+#ifdef MV78XX0
+ /* Check DRAM width */
+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
+ ldr r5, =SDRAM_DWIDTH_MASK
+ and r4, r4, r5
+ ldr r5, =SDRAM_DWIDTH_64BIT
+ cmp r4, r5
+ beq dram_64bit_width
+ /* Utilize only 32bit width */
+ mov r8, r8, LSR #1
+#else
+ /* Utilize only 16bit width */
+ mov r8, r8, LSR #2
+#endif
+dram_64bit_width:
+ /* Update first dimm size return value R8 */
+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0))
+ ldr r6, =~SCSR_SIZE_MASK
+ and r5, r5, r6
+ orr r5, r5, r8
+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0))
+
+ /* Clear bank 2 size */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ and r6, r6,#~SCSR_SIZE_MASK
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne defualt_order
+
+ /* Set sdram bank 2 size */
+ ldr r6, =2
+ bl _mvDramIfGetDimmSizeFromSpd
+#ifdef MV78XX0
+ /* Check DRAM width */
+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
+ ldr r5, =SDRAM_DWIDTH_MASK
+ and r4, r4, r5
+ ldr r5, =SDRAM_DWIDTH_64BIT
+ cmp r4, r5
+ beq dram_64bit_width2
+ /* Utilize only 32bit width */
+ mov r8, r8, LSR #1
+#else
+ /* Utilize only 16bit width */
+ mov r8, r8, LSR #2
+#endif
+dram_64bit_width2:
+ /* Update first dimm size return value R8 */
+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2))
+ ldr r6, =~SCSR_SIZE_MASK
+ and r5, r5, r6
+ orr r5, r5, r8
+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2))
+
+ /* Close windows 1 and 3 */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+
+ /* Check dimm size for setting dram bank order */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2))
+ and r6, r6,#SCSR_SIZE_MASK
+ and r4, r4,#SCSR_SIZE_MASK
+ cmp r6, r4
+ bge defualt_order
+
+ /* Bank 2 is biger then bank 0 */
+ ldr r6,=0
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2))
+
+ /* Open win 2 */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ orr r6, r6,#1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+
+ ldr sp,=0
+ bl _mvDramIfConfig
+#ifdef MV78XX0
+ /* Init ECC on CS 2 */
+ ldr r0, =2
+ bl _mvDramIfEccMemInit
+#endif
+ mov PC, r11 /* r11 is saved link register */
+
+defualt_order:
+
+ /* Open win 0 */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ orr r6, r6,#1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+
+ ldr sp,=0
+ bl _mvDramIfConfig
+#ifdef MV78XX0
+ /* Init ECC on CS 0 */
+ ldr r0, =0
+ bl _mvDramIfEccMemInit
+#endif
+exit_ddrAutoConfig:
+ mov PC, r11 /* r11 is saved link register */
+
+
+/***************************************************************************************/
+/* r4 holds I2C EEPROM address
+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
+ * r8 holds SDRAM various configuration registers value.
+ * r13 holds Link register
+ */
+/**************************/
+_getDensity:
+ mov r13, LR /* Save link register */
+
+ /* Read SPD rank size from DIMM0 */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+
+ cmp r6, #0
+ beq 1f
+
+ /* Read SPD rank size from DIMM1 */
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
+
+1:
+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
+ bl _i2cRead
+ mov r8, r7 /* r8 save number of rows */
+
+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
+ bl _i2cRead
+ add r8, r8, r7 /* r8 = number of rows + number of col */
+
+ mov r7, #0x1
+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */
+
+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
+ bl _i2cRead
+ mul r8, r7, r8
+
+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
+ bl _i2cRead
+ mul r7, r8, r7
+
+ mov PC, r13
+
+/**************************/
+_get_width:
+ mov r13, LR /* Save link register */
+
+ /* Read SPD rank size from DIMM0 */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+
+ cmp r6, #0
+ beq 1f
+
+ /* Read SPD rank size from DIMM1 */
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
+
+1:
+ /* Get SDRAM width (SPD offset 13) */
+ mov r7, #SDRAM_WIDTH_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ mov PC, r13
+
+/**************************/
+_get_CAL:
+ mov r13, LR /* Save link register */
+
+ /* Set maximum CL supported by DIMM */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
+ bl _i2cRead
+
+ mov PC, r13
+
+/**************************/
+/* R8 - sdram configuration register.
+ * Return value in flag if no-registered then Z-flag is set
+ */
+_is_Registered:
+ mov r13, LR /* Save link register */
+#if defined(MV645xx)
+ /* Get registered/non registered info from DIMM */
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne regDdr2
+
+regDdr1:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_MODULES_ATTR_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x2
+ b exit
+#endif
+regDdr2:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_TYPE_INFO_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
+ /* or Mini-RDIMM (0x10) */
+exit:
+ mov PC, r13
+
+
+/**************************/
+/* Return value in flag if no-Ecc then Z-flag is set */
+_is_Ecc:
+ mov r13, LR /* Save link register */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_CONFIG_TYPE
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x2 /* bit 1 -> Data ECC */
+ mov PC, r13
+
+/**************************/
+/* Return value in flag if no second DIMM then Z-flag is set */
+_is_Second_Dimm_Exist:
+ mov r13, LR /* Save link register */
+
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_TYPE_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */
+ mov PC, r13
+
+/*******************************************************************************
+* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size
+*
+* DESCRIPTION:
+* The function will read the bank 0 dram size(SPD version 1.0 and above )
+*
+* INPUT:
+* r6 - dram bank number.
+*
+* OUTPUT:
+* none
+*/
+_mvDramIfGetDimmSizeFromSpd:
+
+ mov r13, LR /* Save link register */
+
+ /* Read SPD rank size from DIMM0 */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+
+ cmp r6, #0
+ beq 1f
+
+ /* Read SPD rank size from DIMM1 */
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
+
+1:
+ mov r7, #RANK_SIZE_OFFSET /* offset 31 */
+ bl _i2cRead
+
+pass_read:
+ ldr r8, =(0x7 << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_128M
+ beq endDimmSize
+
+ ldr r8, =(0xf << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_256M
+ beq endDimmSize
+
+ ldr r8, =(0x1f << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_512M
+ beq endDimmSize
+
+ ldr r8, =(0x3f << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_1G
+ beq endDimmSize
+
+ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */
+endDimmSize:
+ mov PC, r13
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S
new file mode 100644
index 000000000..88527e58c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S
@@ -0,0 +1,528 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvDramIfBasicAsm.s
+*
+* DESCRIPTION:
+* Memory full detection and best timing configuration is done in
+* C code. C runtime environment requires a stack. This module API
+* initialize DRAM interface chip select 0 for basic functionality for
+* the use of stack.
+* The module API assumes DRAM information is stored in I2C EEPROM reside
+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
+* internal data structure is assumed to be orgenzied in common DRAM
+* vendor SPD structure.
+* NOTE: DFCDL values are assumed to be already initialized prior to
+* this module API activity.
+*
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+/* includes */
+#define _ASMLANGUAGE
+#define MV_ASMLANGUAGE
+#include "mvOsAsm.h"
+#include "mvSysHwConfig.h"
+#include "mvDramIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "mvCommon.h"
+
+/* defines */
+
+/* locals */
+.data
+.globl _mvDramIfConfig
+.text
+.globl _mvDramIfMemInit
+
+/*******************************************************************************
+* _mvDramIfConfig - Basic DRAM interface initialization.
+*
+* DESCRIPTION:
+* The function will initialize the following DRAM parameters using the
+* values prepared by mvDramIfDetect routine. Values are located
+* in predefined registers.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+
+_mvDramIfConfig:
+
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_s
+save_on_stack:
+ stmdb sp!, {r1, r2, r3, r4}
+no_stack_s:
+
+ /* Dunit FTDLL Configuration Register */
+ /* 0) Write to SDRAM FTDLL coniguration register */
+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT;
+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG)
+ str r4, [r1]
+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT;
+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG)
+ str r4, [r1]
+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP;
+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG)
+ str r4, [r1]
+
+ /* 1) Write to SDRAM coniguration register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
+ str r4, [r1]
+
+ /* 2) Write Dunit control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
+ str r4, [r1]
+
+ /* 2) Write Dunit control high register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG)
+ str r4, [r1]
+
+ /* 3) Write SDRAM address control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
+ str r4, [r1]
+#if defined(MV_STATIC_DRAM_ON_BOARD)
+ /* 4) Write SDRAM bank 0 size register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0))
+ str r4, [r1]
+#endif
+
+ /* 5) Write SDRAM open pages control register */
+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
+ str r4, [r1]
+
+ /* 6) Write SDRAM timing Low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* 7) Write SDRAM timing High register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* Config DDR2 On Die Termination (ODT) registers */
+ /* Write SDRAM DDR2 ODT control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 ODT control high register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 Dunit ODT control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
+ str r4, [r1]
+
+ /* Write DDR2 SDRAM timing Low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG)
+ str r4, [r1]
+
+ /* Write DDR2 SDRAM timing High register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG)
+ str r4, [r1]
+
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to its new value. */
+
+ /* 8.1 write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll1:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll1
+
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
+ str r4, [r1]
+
+ /* 8.4 Make the Dunit write the DRAM its new mode */
+ mov r4, #0x3 /* Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll2:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll2
+
+ /* Now its safe to write new value to SDRAM Extended Mode regist */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
+ str r4, [r1]
+
+ /* 9) Write SDRAM Extended mode register This operation should be */
+ /* done for each memory bank */
+ /* write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll3:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll3
+ /* Go over each of the Banks */
+ ldr r3, =0 /* r3 = DRAM bank Num */
+
+extModeLoop:
+ /* Set the SDRAM Operation Control to each of the DRAM banks */
+ mov r4, r3 /* Do not swap the bank counter value */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG)
+
+ /* Make the Dunit write the DRAM its new mode */
+ mov r4, #0x4 /* Extended Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll4:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll4
+
+ add r3, r3, #1
+ cmp r3, #4 /* 4 = Number of banks */
+ bne extModeLoop
+
+extModeEnd:
+cmp sp, #0
+ beq no_stack_l
+ mov r1, LR /* Save link register */
+#if defined(MV78XX0)
+ bl _mvDramIfMemInit
+#endif
+ mov LR,r1 /* restore link register */
+load_from_stack:
+ /* Restore registers */
+ ldmia sp!, {r1, r2, r3, r4}
+no_stack_l:
+
+ mov pc, lr
+
+
+/*******************************************************************************
+* _mvDramIfEccMemInit - Basic DRAM ECC initialization.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */
+#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */
+#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */
+/* XOR engine register offsets macros */
+#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4))
+#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4))
+#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30)
+#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50)
+#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60)
+#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0)
+#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4)
+#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4))
+#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4))
+
+/* XOR Engine Address Decoding Register Map */
+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4)))
+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4)))
+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4)))
+
+.globl _mvDramIfEccMemInit
+/*******************************************************************************
+* _mvDramIfEccMemInit - mem init for dram cs
+*
+* DESCRIPTION:
+* This function will clean the cs by ussing the XOR mem init.
+*
+* INPUT:
+* r0 - dram bank number.
+*
+* OUTPUT:
+* none
+*/
+_mvDramIfEccMemInit:
+
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_s1
+save_on_stack1:
+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
+no_stack_s1:
+
+ ldr r1, = 0
+
+ /* Disable all XOR address decode windows to avoid possible overlap */
+ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)))
+
+ /* Init r5 to first XOR_SIZE_MASK_REG */
+ mov r5, r0, LSL #3
+ add r5, r5,#0x1500
+ add r5, r5,#0x04
+ add r5, r5,#(INTER_REGS_BASE)
+ ldr r6, [r5]
+ HTOLL(r6,r5)
+ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
+
+ mov r5, r0, LSL #3
+ add r5, r5,#0x1500
+ add r5, r5,#(INTER_REGS_BASE)
+ ldr r6, [r5]
+ /* Update destination & size */
+ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0))
+ HTOLL(r6,r5)
+ /* Init r6 to first XOR_BASE_ADDR_REG */
+ ldr r4, = 0xf
+ ldr r5, = 0x1
+ mov r5, r5, LSL r0
+ bic r4, r4, r5
+ mov r4, r4, LSL #8
+
+ orr r6, r6, r4
+ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
+
+ ldr r6, = 0xff0001
+ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))
+
+ /* Configure XOR engine for memory init function. */
+ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
+ and r6, r6, #~0x7 /* Clear operation mode field */
+ orr r6, r6, #0x4 /* Set operation to memory init */
+ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
+
+ /* Set initVal in the XOR Engine Initial Value Registers */
+ ldr r6, = 0xfeedfeed
+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG)
+ ldr r6, = 0xfeedfeed
+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG)
+
+ /* Set block size using DRAM bank size */
+
+ mov r5, r0, LSL #3
+ add r5, r5,#0x1500
+ add r5, r5,#0x04
+ add r5, r5,#(INTER_REGS_BASE)
+
+ ldr r6, [r5]
+ HTOLL(r6,r5)
+ and r6, r6, #SCSR_SIZE_MASK
+ mov r5, r6, LSR #SCSR_SIZE_OFFS
+ add r5, r5, #1
+ mov r6, r5, LSL #SCSR_SIZE_OFFS
+ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0))
+
+ /* Clean interrupt cause*/
+ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG)
+
+ /* Clean error interrupt cause*/
+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG)
+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG)
+
+ /* Start transfer */
+ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
+ orr r6, r6, #0x1 /* Preform start command */
+ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
+
+ /* Wait for engine to finish */
+waitForComplete:
+ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG)
+ and r6, r6, #2
+ cmp r6, #0
+ beq waitForComplete
+
+ /* Clear all error report registers */
+ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG)
+ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG)
+
+ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG)
+
+ cmp sp, #0
+ beq no_stack_l1
+load_from_stack1:
+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
+no_stack_l1:
+ mov pc, lr
+
+
+/*******************************************************************************
+* mvDramIfMemInit - Use XOR to clear all memory.
+*
+* DESCRIPTION:
+* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern.
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+#if defined(MV78XX0)
+
+_mvDramIfMemInit:
+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
+ mov r6, LR /* Save link register */
+ /* Check if dram bank 0 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0))
+ and r3, r0, #SCSR_WIN_EN
+ cmp r3, #0
+ beq no_bank_0
+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0))
+ cmp r0, #0
+ beq no_bank_0
+ mov r0,#0
+ bl _mvDramIfEccMemInit
+
+no_bank_0:
+ /* Check if dram bank 1 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1))
+ and r0, r0, #SCSR_WIN_EN
+ cmp r0, #0
+ beq no_bank_1
+ mov r0,#1
+ bl _mvDramIfEccMemInit
+no_bank_1:
+ /* Check if dram bank 2 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2))
+ and r0, r0, #SCSR_WIN_EN
+ cmp r0, #0
+ beq no_bank_2
+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2))
+ cmp r0, #0
+ beq no_bank_2
+ mov r0,#2
+ bl _mvDramIfEccMemInit
+
+no_bank_2:
+ /* Check if dram bank 3 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3))
+ and r0, r0, #SCSR_WIN_EN
+ cmp r0, #0
+ beq no_bank_3
+ mov r0,#3
+ bl _mvDramIfEccMemInit
+no_bank_3:
+ mov LR ,r6 /* restore link register */
+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
+ mov pc, lr
+#endif
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h
new file mode 100644
index 000000000..6141c46a0
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h
@@ -0,0 +1,157 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvDramIfConfigh
+#define __INCmvDramIfConfigh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* includes */
+
+/* defines */
+
+/* registers defaults values */
+
+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30)
+
+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \
+ (SDRAM_SRCLK_KEPT | \
+ SDRAM_CLK1DRV_NORMAL | \
+ (BIT28 | BIT29))
+
+#define SDRAM_ADDR_CTRL_DV 2
+
+#define SDRAM_TIMING_CTRL_LOW_REG_DV \
+ ((0x2 << SDRAM_TRCD_OFFS) | \
+ (0x2 << SDRAM_TRP_OFFS) | \
+ (0x1 << SDRAM_TWR_OFFS) | \
+ (0x0 << SDRAM_TWTR_OFFS) | \
+ (0x5 << SDRAM_TRAS_OFFS) | \
+ (0x1 << SDRAM_TRRD_OFFS))
+
+/* Note: value of 0 in register means one cycle, 1 means two and so on */
+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \
+ ((0x0 << SDRAM_TR2R_OFFS) | \
+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \
+ (0x1 << SDRAM_TW2W_OFFS))
+
+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN
+
+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */
+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */
+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */
+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
+
+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000
+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000
+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F
+#ifdef MV78XX0
+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040
+#else
+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440
+#endif
+
+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C
+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000
+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F
+#ifdef MV78XX0
+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004
+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044
+#else
+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404
+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444
+#endif
+
+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */
+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \
+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+
+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \
+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+
+/* DDR SDRAM Mode Register default value */
+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC)
+/* DDR SDRAM Timing parameter default values */
+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552
+#define SDRAM_TRFC_DEFAULT_VALUE 0x34
+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE
+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS)
+
+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT)
+
+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800
+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800
+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvDramIfh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h
new file mode 100644
index 000000000..369eda692
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h
@@ -0,0 +1,423 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDramIfRegsh
+#define __INCmvDramIfRegsh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* DDR SDRAM Controller Address Decode Registers */
+ /* SDRAM CSn Base Address Register (SCBAR) */
+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70))
+#define SCBAR_BASE_OFFS 16
+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS)
+#define SCBAR_BASE_ALIGNMENT 0x10000
+
+/* SDRAM CSn Size Register (SCSR) */
+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70))
+#define SCSR_SIZE_OFFS 24
+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS)
+#define SCSR_SIZE_ALIGNMENT 0x1000000
+#define SCSR_WIN_EN BIT0
+
+/* configuration register */
+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400)
+#define SDRAM_REFRESH_OFFS 0
+#define SDRAM_REFRESH_MAX 0x3FFF
+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS)
+#define SDRAM_DWIDTH_OFFS 15
+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS)
+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS)
+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS)
+#define SDRAM_REGISTERED (1 << 17)
+#define SDRAM_ECC_OFFS 18
+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS)
+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS)
+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS)
+#define SDRAM_IERR_OFFS 19
+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS)
+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS)
+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS)
+#define SDRAM_SRMODE_OFFS 24
+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS)
+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS)
+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS)
+
+/* dunit control low register */
+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404)
+#define SDRAM_2T_OFFS 4
+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS)
+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS)
+
+#define SDRAM_SRCLK_OFFS 5
+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS)
+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS)
+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS)
+#define SDRAM_CTRL_POS_OFFS 6
+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS)
+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS)
+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS)
+#define SDRAM_CLK1DRV_OFFS 12
+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS)
+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS)
+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS)
+#define SDRAM_CLK2DRV_OFFS 13
+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS)
+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS)
+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS)
+#define SDRAM_SB_OUT_DEL_OFFS 20
+#define SDRAM_SB_OUT_DEL_MAX 0xf
+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<<SDRAM_SB_OUT_DEL_OFFS)
+#define SDRAM_SB_IN_DEL_OFFS 24
+#define SDRAM_SB_IN_DEL_MAX 0xf
+#define SDRAM_SB_IN_MASK (SDRAM_SB_IN_DEL_MAX<<SDRAM_SB_IN_DEL_OFFS)
+
+/* dunit control hight register */
+#define SDRAM_DUNIT_CTRL_HI_REG (DRAM_BASE + 0x1424)
+#define SDRAM__D2P_OFFS 7
+#define SDRAM__D2P_EN (1 << SDRAM__D2P_OFFS)
+#define SDRAM__P2D_OFFS 8
+#define SDRAM__P2D_EN (1 << SDRAM__P2D_OFFS)
+#define SDRAM__ADD_HALF_FCC_OFFS 9
+#define SDRAM__ADD_HALF_FCC_EN (1 << SDRAM__ADD_HALF_FCC_OFFS)
+#define SDRAM__PUP_ZERO_SKEW_OFFS 10
+#define SDRAM__PUP_ZERO_SKEW_EN (1 << SDRAM__PUP_ZERO_SKEW_OFFS)
+#define SDRAM__WR_MESH_DELAY_OFFS 11
+#define SDRAM__WR_MESH_DELAY_EN (1 << SDRAM__WR_MESH_DELAY_OFFS)
+
+/* sdram timing control low register */
+#define SDRAM_TIMING_CTRL_LOW_REG (DRAM_BASE + 0x1408)
+#define SDRAM_TRCD_OFFS 4
+#define SDRAM_TRCD_MASK (0xF << SDRAM_TRCD_OFFS)
+#define SDRAM_TRP_OFFS 8
+#define SDRAM_TRP_MASK (0xF << SDRAM_TRP_OFFS)
+#define SDRAM_TWR_OFFS 12
+#define SDRAM_TWR_MASK (0xF << SDRAM_TWR_OFFS)
+#define SDRAM_TWTR_OFFS 16
+#define SDRAM_TWTR_MASK (0xF << SDRAM_TWTR_OFFS)
+#define SDRAM_TRAS_OFFS 0
+#define SDRAM_TRAS_MASK (0xF << SDRAM_TRAS_OFFS)
+#define SDRAM_EXT_TRAS_OFFS 20
+#define SDRAM_EXT_TRAS_MASK (0x1 << SDRAM_EXT_TRAS_OFFS)
+#define SDRAM_TRRD_OFFS 24
+#define SDRAM_TRRD_MASK (0xF << SDRAM_TRRD_OFFS)
+#define SDRAM_TRTP_OFFS 28
+#define SDRAM_TRTP_MASK (0xF << SDRAM_TRTP_OFFS)
+#define SDRAM_TRTP_DDR1 (0x1 << SDRAM_TRTP_OFFS)
+
+/* sdram timing control high register */
+#define SDRAM_TIMING_CTRL_HIGH_REG (DRAM_BASE + 0x140c)
+#define SDRAM_TRFC_OFFS 0
+#define SDRAM_TRFC_MASK (0x3F << SDRAM_TRFC_OFFS)
+#define SDRAM_TR2R_OFFS 7
+#define SDRAM_TR2R_MASK (0x3 << SDRAM_TR2R_OFFS)
+#define SDRAM_TR2W_W2R_OFFS 9
+#define SDRAM_TR2W_W2R_MASK (0x3 << SDRAM_TR2W_W2R_OFFS)
+#define SDRAM_TW2W_OFFS 11
+#define SDRAM_TW2W_MASK (0x3 << SDRAM_TW2W_OFFS)
+
+/* sdram DDR2 timing low register (SD2TLR) */
+#define SDRAM_DDR2_TIMING_LO_REG (DRAM_BASE + 0x1428)
+#define SD2TLR_TODT_ON_RD_OFFS 4
+#define SD2TLR_TODT_ON_RD_MASK (0xF << SD2TLR_TODT_ON_RD_OFFS)
+#define SD2TLR_TODT_OFF_RD_OFFS 8
+#define SD2TLR_TODT_OFF_RD_MASK (0xF << SD2TLR_TODT_OFF_RD_OFFS)
+#define SD2TLR_TODT_ON_CTRL_RD_OFFS 12
+#define SD2TLR_TODT_ON_CTRL_RD_MASK (0xF << SD2TLR_TODT_ON_CTRL_RD_OFFS)
+#define SD2TLR_TODT_OFF_CTRL_RD_OFFS 16
+#define SD2TLR_TODT_OFF_CTRL_RD_MASK (0xF << SD2TLR_TODT_OFF_CTRL_RD_OFFS)
+
+/* sdram DDR2 timing high register (SD2TLR) */
+#define SDRAM_DDR2_TIMING_HI_REG (DRAM_BASE + 0x147C)
+#define SD2THR_TODT_ON_WR_OFFS 0
+#define SD2THR_TODT_ON_WR_MASK (0xF << SD2THR_TODT_ON_WR_OFFS)
+#define SD2THR_TODT_OFF_WR_OFFS 4
+#define SD2THR_TODT_OFF_WR_MASK (0xF << SD2THR_TODT_OFF_WR_OFFS)
+#define SD2THR_TODT_ON_CTRL_WR_OFFS 8
+#define SD2THR_TODT_ON_CTRL_WR_MASK (0xF << SD2THR_TODT_ON_CTRL_WR_OFFS)
+#define SD2THR_TODT_OFF_CTRL_WR_OFFS 12
+#define SD2THR_TODT_OFF_CTRL_WR_MASK (0xF << SD2THR_TODT_OFF_CTRL_WR_OFFS)
+
+/* address control register */
+#define SDRAM_ADDR_CTRL_REG (DRAM_BASE + 0x1410)
+#define SDRAM_ADDRSEL_OFFS(cs) (4 * (cs))
+#define SDRAM_ADDRSEL_MASK(cs) (0x3 << SDRAM_ADDRSEL_OFFS(cs))
+#define SDRAM_ADDRSEL_X8(cs) (0x0 << SDRAM_ADDRSEL_OFFS(cs))
+#define SDRAM_ADDRSEL_X16(cs) (0x1 << SDRAM_ADDRSEL_OFFS(cs))
+#define SDRAM_DSIZE_OFFS(cs) (2 + 4 * (cs))
+#define SDRAM_DSIZE_MASK(cs) (0x3 << SDRAM_DSIZE_OFFS(cs))
+#define SDRAM_DSIZE_256Mb(cs) (0x1 << SDRAM_DSIZE_OFFS(cs))
+#define SDRAM_DSIZE_512Mb(cs) (0x2 << SDRAM_DSIZE_OFFS(cs))
+#define SDRAM_DSIZE_1Gb(cs) (0x3 << SDRAM_DSIZE_OFFS(cs))
+#define SDRAM_DSIZE_2Gb(cs) (0x0 << SDRAM_DSIZE_OFFS(cs))
+
+/* SDRAM Open Pages Control registers */
+#define SDRAM_OPEN_PAGE_CTRL_REG (DRAM_BASE + 0x1414)
+#define SDRAM_OPEN_PAGE_EN (0 << 0)
+#define SDRAM_OPEN_PAGE_DIS (1 << 0)
+
+/* sdram opertion register */
+#define SDRAM_OPERATION_REG (DRAM_BASE + 0x1418)
+#define SDRAM_CMD_OFFS 0
+#define SDRAM_CMD_MASK (0xF << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_NORMAL (0x0 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_REFRESH_ALL (0x2 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_REG_SET_CMD (0x3 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_EXT_MODE_SET (0x4 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_NOP (0x5 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_SLF_RFRSH (0x7 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_EMRS2_CMD (0x8 << SDRAM_CMD_OFFS)
+#define SDRAM_CMD_EMRS3_CMD (0x9 << SDRAM_CMD_OFFS)
+
+/* sdram mode register */
+#define SDRAM_MODE_REG (DRAM_BASE + 0x141c)
+#define SDRAM_BURST_LEN_OFFS 0
+#define SDRAM_BURST_LEN_MASK (0x7 << SDRAM_BURST_LEN_OFFS)
+#define SDRAM_BURST_LEN_4 (0x2 << SDRAM_BURST_LEN_OFFS)
+#define SDRAM_CL_OFFS 4
+#define SDRAM_CL_MASK (0x7 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_3 (0x3 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_4 (0x4 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_5 (0x5 << SDRAM_CL_OFFS)
+#define SDRAM_DDR2_CL_6 (0x6 << SDRAM_CL_OFFS)
+
+#define SDRAM_TM_OFFS 7
+#define SDRAM_TM_MASK (1 << SDRAM_TM_OFFS)
+#define SDRAM_TM_NORMAL (0 << SDRAM_TM_OFFS)
+#define SDRAM_TM_TEST_MODE (1 << SDRAM_TM_OFFS)
+#define SDRAM_DLL_OFFS 8
+#define SDRAM_DLL_MASK (1 << SDRAM_DLL_OFFS)
+#define SDRAM_DLL_NORMAL (0 << SDRAM_DLL_OFFS)
+#define SDRAM_DLL_RESET (1 << SDRAM_DLL_OFFS)
+#define SDRAM_WR_OFFS 9
+#define SDRAM_WR_MAX 7
+#define SDRAM_WR_MASK (SDRAM_WR_MAX << SDRAM_WR_OFFS)
+#define SDRAM_WR_2_CYC (1 << SDRAM_WR_OFFS)
+#define SDRAM_WR_3_CYC (2 << SDRAM_WR_OFFS)
+#define SDRAM_WR_4_CYC (3 << SDRAM_WR_OFFS)
+#define SDRAM_WR_5_CYC (4 << SDRAM_WR_OFFS)
+#define SDRAM_WR_6_CYC (5 << SDRAM_WR_OFFS)
+#define SDRAM_PD_OFFS 12
+#define SDRAM_PD_MASK (1 << SDRAM_PD_OFFS)
+#define SDRAM_PD_FAST_EXIT (0 << SDRAM_PD_OFFS)
+#define SDRAM_PD_SLOW_EXIT (1 << SDRAM_PD_OFFS)
+
+/* DDR SDRAM Extended Mode register (DSEMR) */
+#define SDRAM_EXTENDED_MODE_REG (DRAM_BASE + 0x1420)
+#define DSEMR_DLL_ENABLE 0
+#define DSEMR_DLL_DISABLE 1
+#define DSEMR_DS_OFFS 1
+#define DSEMR_DS_MASK (1 << DSEMR_DS_OFFS)
+#define DSEMR_DS_NORMAL (0 << DSEMR_DS_OFFS)
+#define DSEMR_DS_REDUCED (1 << DSEMR_DS_OFFS)
+#define DSEMR_QOFF_OUTPUT_BUFF_EN (0 << 12)
+#define DSEMR_RTT0_OFFS 2
+#define DSEMR_RTT1_OFFS 6
+#define DSEMR_RTT_ODT_DISABLE ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
+#define DSEMR_RTT_ODT_75_OHM ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
+#define DSEMR_RTT_ODT_150_OHM ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
+#define DSEMR_RTT_ODT_50_OHM ((1 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
+#define DSEMR_DQS_OFFS 10
+#define DSEMR_DQS_MASK (1 << DSEMR_DQS_OFFS)
+#define DSEMR_DQS_DIFFERENTIAL (0 << DSEMR_DQS_OFFS)
+#define DSEMR_DQS_SINGLE_ENDED (1 << DSEMR_DQS_OFFS)
+#define DSEMR_RDQS_ENABLE (1 << 11)
+#define DSEMR_QOFF_OUTPUT_BUFF_EN (0 << 12)
+#define DSEMR_QOFF_OUTPUT_BUFF_DIS (1 << 12)
+
+/* DDR SDRAM Operation Control Register */
+#define SDRAM_OPERATION_CTRL_REG (DRAM_BASE + 0x142c)
+
+/* Dunit FTDLL Configuration Register */
+#define SDRAM_FTDLL_CONFIG_LEFT_REG (DRAM_BASE + 0x1484)
+#define SDRAM_FTDLL_CONFIG_RIGHT_REG (DRAM_BASE + 0x161C)
+#define SDRAM_FTDLL_CONFIG_UP_REG (DRAM_BASE + 0x1620)
+
+/* Pads Calibration register */
+#define SDRAM_ADDR_CTRL_PADS_CAL_REG (DRAM_BASE + 0x14c0)
+#define SDRAM_DATA_PADS_CAL_REG (DRAM_BASE + 0x14c4)
+#define SDRAM_DRVN_OFFS 0
+#define SDRAM_DRVN_MASK (0x3F << SDRAM_DRVN_OFFS)
+#define SDRAM_DRVP_OFFS 6
+#define SDRAM_DRVP_MASK (0x3F << SDRAM_DRVP_OFFS)
+#define SDRAM_PRE_DRIVER_STRENGTH_OFFS 12
+#define SDRAM_PRE_DRIVER_STRENGTH_MASK (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
+#define SDRAM_TUNE_EN BIT16
+#define SDRAM_LOCKN_OFFS 17
+#define SDRAM_LOCKN_MAKS (0x3F << SDRAM_LOCKN_OFFS)
+#define SDRAM_LOCKP_OFFS 23
+#define SDRAM_LOCKP_MAKS (0x3F << SDRAM_LOCKP_OFFS)
+#define SDRAM_WR_EN (1 << 31)
+
+/* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */
+#define DDR2_SDRAM_ODT_CTRL_LOW_REG (DRAM_BASE + 0x1494)
+#define DSOCLR_ODT_RD_OFFS(odtNum) (odtNum * 4)
+#define DSOCLR_ODT_RD_MASK(odtNum) (0xf << DSOCLR_ODT_RD_OFFS(odtNum))
+#define DSOCLR_ODT_RD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum))
+#define DSOCLR_ODT_WR_OFFS(odtNum) (16 + (odtNum * 4))
+#define DSOCLR_ODT_WR_MASK(odtNum) (0xf << DSOCLR_ODT_WR_OFFS(odtNum))
+#define DSOCLR_ODT_WR(odtNum, bank) ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum))
+
+/* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */
+#define DDR2_SDRAM_ODT_CTRL_HIGH_REG (DRAM_BASE + 0x1498)
+/* Optional control values to DSOCHR_ODT_EN macro */
+#define DDR2_ODT_CTRL_DUNIT 0
+#define DDR2_ODT_CTRL_NEVER 1
+#define DDR2_ODT_CTRL_ALWAYS 3
+#define DSOCHR_ODT_EN_OFFS(odtNum) (odtNum * 2)
+#define DSOCHR_ODT_EN_MASK(odtNum) (0x3 << DSOCHR_ODT_EN_OFFS(odtNum))
+#define DSOCHR_ODT_EN(odtNum, ctrl) (ctrl << DSOCHR_ODT_EN_OFFS(odtNum))
+
+/* DDR2 Dunit ODT Control Register (DDOCR)*/
+#define DDR2_DUNIT_ODT_CONTROL_REG (DRAM_BASE + 0x149c)
+#define DDOCR_ODT_RD_OFFS 0
+#define DDOCR_ODT_RD_MASK (0xf << DDOCR_ODT_RD_OFFS)
+#define DDOCR_ODT_RD(bank) ((1 << bank) << DDOCR_ODT_RD_OFFS)
+#define DDOCR_ODT_WR_OFFS 4
+#define DDOCR_ODT_WR_MASK (0xf << DDOCR_ODT_WR_OFFS)
+#define DDOCR_ODT_WR(bank) ((1 << bank) << DDOCR_ODT_WR_OFFS)
+#define DSOCR_ODT_EN_OFFS 8
+#define DSOCR_ODT_EN_MASK (0x3 << DSOCR_ODT_EN_OFFS)
+/* For ctrl parameters see DDR2 SDRAM ODT Control (High) Register (0x1498) above. */
+#define DSOCR_ODT_EN(ctrl) (ctrl << DSOCR_ODT_EN_OFFS)
+#define DSOCR_ODT_SEL_DISABLE 0
+#define DSOCR_ODT_SEL_75_OHM 2
+#define DSOCR_ODT_SEL_150_OHM 1
+#define DSOCR_ODT_SEL_50_OHM 3
+#define DSOCR_DQ_ODT_SEL_OFFS 10
+#define DSOCR_DQ_ODT_SEL_MASK (0x3 << DSOCR_DQ_ODT_SEL_OFFS)
+#define DSOCR_DQ_ODT_SEL(odtSel) (odtSel << DSOCR_DQ_ODT_SEL_OFFS)
+#define DSOCR_ST_ODT_SEL_OFFS 12
+#define DSOCR_ST_ODT_SEL_MASK (0x3 << DSOCR_ST_ODT_SEL_OFFS)
+#define DSOCR_ST_ODT_SEL(odtSel) (odtSel << DSOCR_ST_ODT_SEL_OFFS)
+#define DSOCR_ST_ODT_EN (1 << 14)
+
+/* DDR SDRAM Initialization Control Register (DSICR) */
+#define DDR_SDRAM_INIT_CTRL_REG (DRAM_BASE + 0x1480)
+#define DSICR_INIT_EN (1 << 0)
+#define DSICR_T200_SET (1 << 8)
+
+/* sdram extended mode2 register (SEM2R) */
+#define SDRAM_EXTENDED_MODE2_REG (DRAM_BASE + 0x148C)
+#define SEM2R_EMRS2_DDR2_OFFS 0
+#define SEM2R_EMRS2_DDR2_MASK (0x7FFF << SEM2R_EMRS2_DDR2_OFFS)
+
+/* sdram extended mode3 register (SEM3R) */
+#define SDRAM_EXTENDED_MODE3_REG (DRAM_BASE + 0x1490)
+#define SEM3R_EMRS3_DDR2_OFFS 0
+#define SEM3R_EMRS3_DDR2_MASK (0x7FFF << SEM3R_EMRS3_DDR2_OFFS)
+
+/* sdram error registers */
+#define SDRAM_ERROR_CAUSE_REG (DRAM_BASE + 0x14d0)
+#define SDRAM_ERROR_MASK_REG (DRAM_BASE + 0x14d4)
+#define SDRAM_ERROR_DATA_LOW_REG (DRAM_BASE + 0x1444)
+#define SDRAM_ERROR_DATA_HIGH_REG (DRAM_BASE + 0x1440)
+#define SDRAM_ERROR_ADDR_REG (DRAM_BASE + 0x1450)
+#define SDRAM_ERROR_ECC_REG (DRAM_BASE + 0x1448)
+#define SDRAM_CALC_ECC_REG (DRAM_BASE + 0x144c)
+#define SDRAM_ECC_CONTROL_REG (DRAM_BASE + 0x1454)
+#define SDRAM_SINGLE_BIT_ERR_CNTR_REG (DRAM_BASE + 0x1458)
+#define SDRAM_DOUBLE_BIT_ERR_CNTR_REG (DRAM_BASE + 0x145c)
+
+/* SDRAM Error Cause Register (SECR) */
+#define SECR_SINGLE_BIT_ERR BIT0
+#define SECR_DOUBLE_BIT_ERR BIT1
+#define SECR_DATA_PATH_PARITY_ERR BIT2
+/* SDRAM Error Address Register (SEAR) */
+#define SEAR_ERR_TYPE_OFFS 0
+#define SEAR_ERR_TYPE_MASK (1 << SEAR_ERR_TYPE_OFFS)
+#define SEAR_ERR_TYPE_SINGLE 0
+#define SEAR_ERR_TYPE_DOUBLE (1 << SEAR_ERR_TYPE_OFFS)
+#define SEAR_ERR_CS_OFFS 1
+#define SEAR_ERR_CS_MASK (3 << SEAR_ERR_CS_OFFS)
+#define SEAR_ERR_CS(csNum) (csNum << SEAR_ERR_CS_OFFS)
+#define SEAR_ERR_ADDR_OFFS 3
+#define SEAR_ERR_ADDR_MASK (0x1FFFFFFF << SEAR_ERR_ADDR_OFFS)
+
+/* SDRAM ECC Control Register (SECR) */
+#define SECR_FORCEECC_OFFS 0
+#define SECR_FORCEECC_MASK (0xFF << SECR_FORCEECC_OFFS)
+#define SECR_FORCEEN_OFFS 8
+#define SECR_FORCEEN_MASK (1 << SECR_FORCEEN_OFFS)
+#define SECR_ECC_CALC_MASK (0 << SECR_FORCEEN_OFFS)
+#define SECR_ECC_USER_MASK (1 << SECR_FORCEEN_OFFS)
+#define SECR_PERRPROP_EN BIT9
+#define SECR_CNTMODE_OFFS 10
+#define SECR_CNTMODE_MASK (1 << SECR_CNTMODE_OFFS)
+#define SECR_ALL_IN_CS0 (0 << SECR_CNTMODE_OFFS)
+#define SECR_NORMAL_COUNTER (1 << SECR_CNTMODE_OFFS)
+#define SECR_THRECC_OFFS 16
+#define SECR_THRECC_MAX 0xFF
+#define SECR_THRECC_MASK (SECR_THRECC_MAX << SECR_THRECC_OFFS)
+#define SECR_THRECC(threshold) (threshold << SECR_THRECC_OFFS)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvDramIfRegsh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h
new file mode 100644
index 000000000..f3bf83b4e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h
@@ -0,0 +1,179 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvDramIfStaticInith
+#define __INCmvDramIfStaticInith
+
+#ifdef MV_STATIC_DRAM_ON_BOARD
+#define STATIC_DRAM_BANK_1
+#undef STATIC_DRAM_BANK_2
+#undef STATIC_DRAM_BANK_3
+#undef STATIC_DRAM_BANK_4
+
+
+#ifdef MV_DIMM_TS256MLQ72V5U
+#define STATIC_DRAM_BANK_2
+#define STATIC_DRAM_BANK_3
+#undef STATIC_DRAM_BANK_4
+
+#define STATIC_SDRAM_CONFIG_REG 0x4724481A /* offset 0x1400 - DMA reg-0xf1000814 */
+#define STATIC_SDRAM_DUNIT_CTRL_REG 0x37707450 /* offset 0x1404 - DMA reg-0xf100081c */
+#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11A13330 /* offset 0x1408 - DMA reg-0xf1000824 */
+#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000601 /* offset 0x140c - DMA reg-0xf1000828 */
+#define STATIC_SDRAM_ADDR_CTRL_REG 0x00001CB2 /* offset 0x1410 - DMA reg-0xf1000820 */
+#define STATIC_SDRAM_MODE_REG 0x00000642 /* offset 0x141c - DMA reg-0xf1000818 */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000740F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000404 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00074410 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00007441 /* 0x147C */
+
+#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x3FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */
+#define STATIC_SDRAM_RANK1_SIZE_DIMM0 0x3FFF /* size bank1 dimm0 */
+#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x3FFF /* size bank0 dimm1 */
+#define STATIC_SDRAM_RANK1_SIZE_DIMM1 0x0 /* size bank1 dimm1 */
+
+#endif /* TS256MLQ72V5U */
+
+
+#ifdef MV_MT9VDDT3272AG
+/* one DIMM 256M */
+#define STATIC_SDRAM_CONFIG_REG 0x5820040d /* offset 0x1400 - DMA reg-0xf1000814 */
+#define STATIC_SDRAM_DUNIT_CTRL_REG 0xC4000540 /* offset 0x1404 - DMA reg-0xf100081c */
+#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01602220 /* offset 0x1408 - DMA reg-0xf1000824 */
+#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x0000000b /* offset 0x140c - DMA reg-0xf1000828 */
+#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */
+#define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */
+#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0fff /* size bank0 dimm0 - DMA reg-0xf1000810 */
+#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0 /* size bank0 dimm1 */
+
+#endif /* MV_MT9VDDT3272AG */
+
+
+
+#ifdef MV_D27RB12P
+/*
+Two DIMM 512M + ECC enabled, Registered DIMM CAS Latency 2.5
+*/
+
+#define STATIC_SDRAM_CONFIG_REG 0x6826081E /* offset 0x1400 - DMA reg-0xf1000814 */
+#define STATIC_SDRAM_DUNIT_CTRL_REG 0xC5000540 /* offset 0x1404 - DMA reg-0xf100081c */
+#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01501220 /* offset 0x1408 - DMA reg-0xf1000824 */
+#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000009 /* offset 0x140c - DMA reg-0xf1000828 */
+#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */
+#define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */
+#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */
+#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0FFF /* size bank0 dimm1 */
+
+#define STATIC_DRAM_BANK_2
+
+#define STATIC_DRAM_BANK_3
+#define STATIC_DRAM_BANK_4
+
+#endif /* mv_D27RB12P */
+
+#ifdef RD_MV645XX
+
+#define STATIC_MEM_TYPE MEM_TYPE_DDR2
+#define STATIC_DIMM_INFO_BANK0_SIZE 256
+/* DDR2 boards 256 MB*/
+
+#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000fff /* size bank0 dimm0 - DMA reg-0xf1000810 */
+#define STATIC_SDRAM_CONFIG_REG 0x07190618
+#define STATIC_SDRAM_MODE_REG 0x00000432
+#define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440
+#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022
+#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220
+#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330
+#endif /* RD_MV645XX */
+
+#if MV_DIMM_M3783354CZ3_CE6
+
+#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000FFF /* 0x2010 size bank0 dimm0 - DMA reg-0xf1000810 */
+#define STATIC_SDRAM_CONFIG_REG 0x07190618 /* 0x1400 */
+#define STATIC_SDRAM_MODE_REG 0x00000432 /* 0x141c */
+#define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440 /* 0x1404 */
+#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022 /* 0x1410 */
+#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220 /* 0x1408 */
+#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000440 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330 /* 0x147C */
+
+#endif /* MV_DIMM_M3783354CZ3_CE6 */
+
+#endif /* MV_STATIC_DRAM_ON_BOARD */
+#endif /* __INCmvDramIfStaticInith */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c
new file mode 100644
index 000000000..7a26f9059
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c
@@ -0,0 +1,1474 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ddr2/spd/mvSpd.h"
+#include "boardEnv/mvBoardEnvLib.h"
+
+/* #define MV_DEBUG */
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo,
+ MV_DRAM_BANK_INFO *pBankInfo);
+static MV_U32 cas2ps(MV_U8 spd_byte);
+/*******************************************************************************
+* mvDramBankGet - Get the DRAM bank paramters.
+*
+* DESCRIPTION:
+* This function retrieves DRAM bank parameters as described in
+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board
+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data
+* from it. Otherwise, if the DRAM is soldered on board, the function
+* should insert its bank information into MV_DRAM_BANK_INFO struct.
+*
+* INPUT:
+* bankNum - Board DRAM bank number.
+*
+* OUTPUT:
+* pBankInfo - DRAM bank information struct.
+*
+* RETURN:
+* MV_FAIL - Bank parameters could not be read.
+*
+*******************************************************************************/
+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo)
+{
+ MV_DIMM_INFO dimmInfo;
+
+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum));
+ /* zero pBankInfo structure */
+
+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS ))
+ {
+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n"));
+ return MV_BAD_PARAM;
+ }
+ memset(pBankInfo, 0, sizeof(*pBankInfo));
+
+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo))
+ {
+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n"));
+ return MV_FAIL;
+ }
+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1))
+ {
+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n"));
+ return MV_FAIL;
+ }
+ /* convert Dimm info to Bank info */
+ cpyDimm2BankInfo(&dimmInfo, pBankInfo);
+ return MV_OK;
+}
+
+/*******************************************************************************
+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct.
+*
+* DESCRIPTION:
+* Convert a Dimm info struct into a bank info struct.
+*
+* INPUT:
+* pDimmInfo - DIMM information structure.
+*
+* OUTPUT:
+* pBankInfo - DRAM bank information struct.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo,
+ MV_DRAM_BANK_INFO *pBankInfo)
+{
+ pBankInfo->memoryType = pDimmInfo->memoryType;
+
+ /* DIMM dimensions */
+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr;
+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr;
+ pBankInfo->dataWidth = pDimmInfo->dataWidth;
+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType;
+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth;
+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth;
+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice;
+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies;
+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval;
+
+ /* DIMM timing parameters */
+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs;
+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps =
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps;
+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps =
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps;
+
+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime;
+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive;
+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay;
+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth;
+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime;
+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay;
+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay;
+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd;
+
+ /* Parameters calculated from the extracted DIMM information */
+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks;
+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity;
+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices /
+ pDimmInfo->numOfModuleBanks;
+
+ /* DIMM attributes (MV_TRUE for yes) */
+
+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) ||
+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) )
+ {
+ if (pDimmInfo->dimmAttributes & BIT1)
+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE;
+ else
+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE;
+ }
+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */
+ {
+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4))
+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE;
+ else
+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE;
+ }
+
+ return;
+}
+/*******************************************************************************
+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1.
+*
+* DESCRIPTION:
+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise.
+*
+*******************************************************************************/
+MV_STATUS dimmSpdCpy(MV_VOID)
+{
+ MV_U32 i;
+ MV_U32 spdChecksum;
+
+ MV_TWSI_SLAVE twsiSlave;
+ MV_U8 data[SPD_SIZE];
+
+ /* zero dimmInfo structure */
+ memset(data, 0, SPD_SIZE);
+
+ /* read the dimm eeprom */
+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n"));
+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) )
+ {
+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n"));
+ return MV_FAIL;
+ }
+ DB(puts("DRAM: Reading dimm info succeded.\n"));
+
+ /* calculate SPD checksum */
+ spdChecksum = 0;
+
+ for(i = 0 ; i <= 62 ; i++)
+ {
+ spdChecksum += data[i];
+ }
+
+ if ((spdChecksum & 0xff) != data[63])
+ {
+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n",
+ (MV_U32)(spdChecksum & 0xff), data[63]));
+ }
+ else
+ {
+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n"));
+ }
+
+ /* copy the SPD content 1:1 into the DIMM 1 SPD */
+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ for(i = 0 ; i < SPD_SIZE ; i++)
+ {
+ twsiSlave.offset = i;
+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) )
+ {
+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i);
+ return MV_FAIL;
+ }
+ mvOsDelay(5);
+ }
+
+ DB(puts("DRAM: Reading dimm info succeded.\n"));
+ return MV_OK;
+}
+
+/*******************************************************************************
+* dimmSpdGet - Get the SPD parameters.
+*
+* DESCRIPTION:
+* Read the DIMM SPD parameters into given struct parameter.
+*
+* INPUT:
+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
+*
+* OUTPUT:
+* pDimmInfo - DIMM information structure.
+*
+* RETURN:
+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise.
+*
+*******************************************************************************/
+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo)
+{
+ MV_U32 i;
+ MV_U32 density = 1;
+ MV_U32 spdChecksum;
+
+ MV_TWSI_SLAVE twsiSlave;
+ MV_U8 data[SPD_SIZE];
+
+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM))
+ {
+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n"));
+ return MV_BAD_PARAM;
+ }
+
+ /* zero dimmInfo structure */
+ memset(data, 0, SPD_SIZE);
+
+ /* read the dimm eeprom */
+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n"));
+ twsiSlave.slaveAddr.address = (dimmNum == 0) ?
+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR;
+ twsiSlave.slaveAddr.type = ADDR7_BIT;
+ twsiSlave.validOffset = MV_TRUE;
+ twsiSlave.offset = 0;
+ twsiSlave.moreThen256 = MV_FALSE;
+
+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) )
+ {
+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum));
+ return MV_FAIL;
+ }
+ DB(puts("DRAM: Reading dimm info succeded.\n"));
+
+ /* calculate SPD checksum */
+ spdChecksum = 0;
+
+ for(i = 0 ; i <= 62 ; i++)
+ {
+ spdChecksum += data[i];
+ }
+
+ if ((spdChecksum & 0xff) != data[63])
+ {
+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n",
+ (MV_U32)(spdChecksum & 0xff), data[63]));
+ }
+ else
+ {
+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n"));
+ }
+
+ /* copy the SPD content 1:1 into the dimmInfo structure*/
+ for(i = 0 ; i < SPD_SIZE ; i++)
+ {
+ pDimmInfo->spdRawData[i] = data[i];
+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i]));
+ }
+
+ DB(mvOsPrintf("DRAM SPD Information:\n"));
+
+ /* Memory type (DDR / SDRAM) */
+ switch (data[DIMM_MEM_TYPE])
+ {
+ case (DIMM_MEM_TYPE_SDRAM):
+ pDimmInfo->memoryType = MEM_TYPE_SDRAM;
+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n"));
+ break;
+ case (DIMM_MEM_TYPE_DDR1):
+ pDimmInfo->memoryType = MEM_TYPE_DDR1;
+ DB(mvOsPrintf("DRAM Memeory type DDR1\n"));
+ break;
+ case (DIMM_MEM_TYPE_DDR2):
+ pDimmInfo->memoryType = MEM_TYPE_DDR2;
+ DB(mvOsPrintf("DRAM Memeory type DDR2\n"));
+ break;
+ default:
+ mvOsPrintf("ERROR: Undefined memory type!\n");
+ return MV_ERROR;
+ }
+
+
+ /* Number Of Row Addresses */
+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM];
+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr));
+
+ /* Number Of Column Addresses */
+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM];
+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr));
+
+ /* Number Of Module Banks */
+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM];
+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n",
+ pDimmInfo->numOfModuleBanks));
+
+ /* Number of module banks encoded differently for DDR2 */
+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2)
+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1;
+
+ /* Data Width */
+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH];
+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth));
+
+ /* Minimum Cycle Time At Max CasLatancy */
+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]);
+
+ /* Error Check Type */
+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE];
+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n",
+ pDimmInfo->errorCheckType));
+
+ /* Refresh Interval */
+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL];
+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n",
+ pDimmInfo->refreshInterval));
+
+ /* Sdram Width */
+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH];
+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth));
+
+ /* Error Check Data Width */
+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH];
+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n",
+ pDimmInfo->errorCheckDataWidth));
+
+ /* Burst Length Supported */
+ /* SDRAM/DDR1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 *
+ *********************************************************/
+ /* DDR2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD *
+ *********************************************************/
+
+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP];
+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n",
+ pDimmInfo->burstLengthSupported));
+
+ /* Number Of Banks On Each Device */
+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM];
+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n",
+ pDimmInfo->numOfBanksOnEachDevice));
+
+ /* Suported Cas Latencies */
+
+ /* SDRAM:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
+ ********************************************************/
+
+ /* DDR 1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
+ *********************************************************/
+
+ /* DDR 2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD *
+ *********************************************************/
+
+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL];
+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n",
+ pDimmInfo->suportedCasLatencies));
+
+ /* For DDR2 only, get the DIMM type information */
+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2)
+ {
+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION];
+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n",
+ pDimmInfo->dimmTypeInfo));
+ }
+
+ /* SDRAM Modules Attributes */
+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN];
+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n",
+ pDimmInfo->dimmAttributes));
+
+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps =
+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]);
+
+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/
+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps =
+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]);
+
+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME];
+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n",
+ pDimmInfo->minRowPrechargeTime));
+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE];
+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n",
+ pDimmInfo->minRowActiveToRowActive));
+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY];
+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n",
+ pDimmInfo->minRasToCasDelay));
+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH];
+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n",
+ pDimmInfo->minRasPulseWidth));
+
+ /* DIMM Bank Density */
+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY];
+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n",
+ pDimmInfo->dimmBankDensity));
+
+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */
+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME];
+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n",
+ pDimmInfo->minWriteRecoveryTime));
+
+ /* Only DDR2 includes Internal Write To Read Command Delay field. */
+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY];
+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n",
+ pDimmInfo->minWriteToReadCmdDelay));
+
+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */
+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY];
+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n",
+ pDimmInfo->minReadToPrechCmdDelay));
+
+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */
+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD];
+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n",
+ pDimmInfo->minRefreshToActiveCmd));
+
+ /* calculating the sdram density. Representing device density from */
+ /* bit 20 to allow representation of 4GB and above. */
+ /* For example, if density is 512Mbit 0x20000000, will be represent in */
+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */
+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */
+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20));
+ pDimmInfo->deviceDensity = density *
+ pDimmInfo->numOfBanksOnEachDevice *
+ pDimmInfo->sdramWidth;
+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity));
+
+ /* Number of devices includeing Error correction */
+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) *
+ pDimmInfo->numOfModuleBanks;
+ DB(mvOsPrintf("DRAM numberOfDevices %d\n",
+ pDimmInfo->numberOfDevices));
+
+ pDimmInfo->size = 0;
+
+ /* Note that pDimmInfo->size is in MB units */
+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM)
+ {
+ if (pDimmInfo->dimmBankDensity & BIT0)
+ pDimmInfo->size += 1024; /* Equal to 1GB */
+ else if (pDimmInfo->dimmBankDensity & BIT1)
+ pDimmInfo->size += 8; /* Equal to 8MB */
+ else if (pDimmInfo->dimmBankDensity & BIT2)
+ pDimmInfo->size += 16; /* Equal to 16MB */
+ else if (pDimmInfo->dimmBankDensity & BIT3)
+ pDimmInfo->size += 32; /* Equal to 32MB */
+ else if (pDimmInfo->dimmBankDensity & BIT4)
+ pDimmInfo->size += 64; /* Equal to 64MB */
+ else if (pDimmInfo->dimmBankDensity & BIT5)
+ pDimmInfo->size += 128; /* Equal to 128MB */
+ else if (pDimmInfo->dimmBankDensity & BIT6)
+ pDimmInfo->size += 256; /* Equal to 256MB */
+ else if (pDimmInfo->dimmBankDensity & BIT7)
+ pDimmInfo->size += 512; /* Equal to 512MB */
+ }
+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1)
+ {
+ if (pDimmInfo->dimmBankDensity & BIT0)
+ pDimmInfo->size += 1024; /* Equal to 1GB */
+ else if (pDimmInfo->dimmBankDensity & BIT1)
+ pDimmInfo->size += 2048; /* Equal to 2GB */
+ else if (pDimmInfo->dimmBankDensity & BIT2)
+ pDimmInfo->size += 16; /* Equal to 16MB */
+ else if (pDimmInfo->dimmBankDensity & BIT3)
+ pDimmInfo->size += 32; /* Equal to 32MB */
+ else if (pDimmInfo->dimmBankDensity & BIT4)
+ pDimmInfo->size += 64; /* Equal to 64MB */
+ else if (pDimmInfo->dimmBankDensity & BIT5)
+ pDimmInfo->size += 128; /* Equal to 128MB */
+ else if (pDimmInfo->dimmBankDensity & BIT6)
+ pDimmInfo->size += 256; /* Equal to 256MB */
+ else if (pDimmInfo->dimmBankDensity & BIT7)
+ pDimmInfo->size += 512; /* Equal to 512MB */
+ }
+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */
+ {
+ if (pDimmInfo->dimmBankDensity & BIT0)
+ pDimmInfo->size += 1024; /* Equal to 1GB */
+ else if (pDimmInfo->dimmBankDensity & BIT1)
+ pDimmInfo->size += 2048; /* Equal to 2GB */
+ else if (pDimmInfo->dimmBankDensity & BIT2)
+ pDimmInfo->size += 4096; /* Equal to 4GB */
+ else if (pDimmInfo->dimmBankDensity & BIT3)
+ pDimmInfo->size += 8192; /* Equal to 8GB */
+ else if (pDimmInfo->dimmBankDensity & BIT4)
+ pDimmInfo->size += 16384; /* Equal to 16GB */
+ else if (pDimmInfo->dimmBankDensity & BIT5)
+ pDimmInfo->size += 128; /* Equal to 128MB */
+ else if (pDimmInfo->dimmBankDensity & BIT6)
+ pDimmInfo->size += 256; /* Equal to 256MB */
+ else if (pDimmInfo->dimmBankDensity & BIT7)
+ pDimmInfo->size += 512; /* Equal to 512MB */
+ }
+
+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks;
+
+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size));
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* dimmSpdPrint - Print the SPD parameters.
+*
+* DESCRIPTION:
+* Print the Dimm SPD parameters.
+*
+* INPUT:
+* pDimmInfo - DIMM information structure.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_VOID dimmSpdPrint(MV_U32 dimmNum)
+{
+ MV_DIMM_INFO dimmInfo;
+ MV_U32 i, temp = 0;
+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0;
+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift;
+ MV_U32 busClkPs;
+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks,
+ temp_buf[40], *spdRawData;
+
+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */
+
+ spdRawData = dimmInfo.spdRawData;
+
+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo))
+ {
+ mvOsOutput("ERROR: Could not read SPD information!\n");
+ return;
+ }
+
+ /* find Manufactura of Dimm Module */
+ mvOsOutput("\nManufacturer's JEDEC ID Code: ");
+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++)
+ {
+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]);
+ }
+ mvOsOutput("\n");
+
+ /* Manufacturer's Specific Data */
+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++)
+ {
+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i];
+ }
+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf);
+
+ /* Module Part Number */
+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++)
+ {
+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i];
+ }
+ mvOsOutput("Module Part Number: %s\n", temp_buf);
+
+ /* Module Serial Number */
+ for(i = 0; i < sizeof(MV_U32); i++)
+ {
+ temp |= spdRawData[95+i] << 8*i;
+ }
+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp,
+ (long)temp);
+
+ /* find Manufac-Data of Dimm Module */
+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n",
+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf),
+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf));
+ /* find modul_revision of Dimm Module */
+ mvOsOutput("Module Revision: %d.%d\n",
+ spdRawData[62]/10, spdRawData[62]%10);
+
+ /* find manufac_place of Dimm Module */
+ mvOsOutput("manufac_place: %d\n", spdRawData[72]);
+
+ /* go over the first 35 I2C data bytes */
+ for(i = 2 ; i <= 35 ; i++)
+ switch(i)
+ {
+ case 2: /* Memory type (DDR1/2 / SDRAM) */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ mvOsOutput("Dram Type is: SDRAM\n");
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ mvOsOutput("Dram Type is: SDRAM DDR1\n");
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ mvOsOutput("Dram Type is: SDRAM DDR2\n");
+ else
+ mvOsOutput("Dram Type unknown\n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 3: /* Number Of Row Addresses */
+ mvOsOutput("Module Number of row addresses: %d\n",
+ dimmInfo.numOfRowAddr);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 4: /* Number Of Column Addresses */
+ mvOsOutput("Module Number of col addresses: %d\n",
+ dimmInfo.numOfColAddr);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 5: /* Number Of Module Banks */
+ mvOsOutput("Number of Banks on Mod.: %d\n",
+ dimmInfo.numOfModuleBanks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 6: /* Data Width */
+ mvOsOutput("Module Data Width: %d bit\n",
+ dimmInfo.dataWidth);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 8: /* Voltage Interface */
+ switch(spdRawData[i])
+ {
+ case 0x0:
+ mvOsOutput("Module is TTL_5V_TOLERANT\n");
+ break;
+ case 0x1:
+ mvOsOutput("Module is LVTTL\n");
+ break;
+ case 0x2:
+ mvOsOutput("Module is HSTL_1_5V\n");
+ break;
+ case 0x3:
+ mvOsOutput("Module is SSTL_3_3V\n");
+ break;
+ case 0x4:
+ mvOsOutput("Module is SSTL_2_5V\n");
+ break;
+ case 0x5:
+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM)
+ {
+ mvOsOutput("Module is SSTL_1_8V\n");
+ break;
+ }
+ default:
+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n");
+ break;
+ }
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 9: /* Minimum Cycle Time At Max CasLatancy */
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ rightOfPoint = (spdRawData[i] & 0x0f) * 10;
+
+ /* DDR2 addition of right of point */
+ if ((spdRawData[i] & 0x0f) == 0xA)
+ {
+ rightOfPoint = 25;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xB)
+ {
+ rightOfPoint = 33;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xC)
+ {
+ rightOfPoint = 66;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xD)
+ {
+ rightOfPoint = 75;
+ }
+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 10: /* Clock To Data Out */
+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100;
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / div;
+ rightOfPoint = time_tmp % div;
+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 11: /* Error Check Type */
+ mvOsOutput("Error Check Type (0=NONE): %d\n",
+ dimmInfo.errorCheckType);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 12: /* Refresh Interval */
+ mvOsOutput("Refresh Rate: %x\n",
+ dimmInfo.refreshInterval);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 13: /* Sdram Width */
+ mvOsOutput("Sdram Width: %d bits\n",
+ dimmInfo.sdramWidth);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 14: /* Error Check Data Width */
+ mvOsOutput("Error Check Data Width: %d bits\n",
+ dimmInfo.errorCheckDataWidth);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 15: /* Minimum Clock Delay is unsupported */
+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) ||
+ (dimmInfo.memoryType == MEM_TYPE_DDR1))
+ {
+ mvOsOutput("Minimum Clk Delay back to back: %d\n",
+ spdRawData[i]);
+ }
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 16: /* Burst Length Supported */
+ /* SDRAM/DDR1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 *
+ *********************************************************/
+ /* DDR2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD *
+ *********************************************************/
+ mvOsOutput("Burst Length Supported: ");
+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) ||
+ (dimmInfo.memoryType == MEM_TYPE_DDR1))
+ {
+ if (dimmInfo.burstLengthSupported & BIT0)
+ mvOsOutput("1, ");
+ if (dimmInfo.burstLengthSupported & BIT1)
+ mvOsOutput("2, ");
+ }
+ if (dimmInfo.burstLengthSupported & BIT2)
+ mvOsOutput("4, ");
+ if (dimmInfo.burstLengthSupported & BIT3)
+ mvOsOutput("8, ");
+
+ mvOsOutput(" Bit \n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 17: /* Number Of Banks On Each Device */
+ mvOsOutput("Number Of Banks On Each Chip: %d\n",
+ dimmInfo.numOfBanksOnEachDevice);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 18: /* Suported Cas Latencies */
+
+ /* SDRAM:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
+ ********************************************************/
+
+ /* DDR 1:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
+ *********************************************************/
+
+ /* DDR 2:
+ *******-******-******-******-******-******-******-*******
+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+ *******-******-******-******-******-******-******-*******
+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD *
+ *********************************************************/
+
+ mvOsOutput("Suported Cas Latencies: (CL) ");
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ for (k = 0; k <=7; k++)
+ {
+ if (dimmInfo.suportedCasLatencies & (1 << k))
+ mvOsOutput("%d, ", k+1);
+ }
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if (dimmInfo.suportedCasLatencies & BIT0)
+ mvOsOutput("1, ");
+ if (dimmInfo.suportedCasLatencies & BIT1)
+ mvOsOutput("1.5, ");
+ if (dimmInfo.suportedCasLatencies & BIT2)
+ mvOsOutput("2, ");
+ if (dimmInfo.suportedCasLatencies & BIT3)
+ mvOsOutput("2.5, ");
+ if (dimmInfo.suportedCasLatencies & BIT4)
+ mvOsOutput("3, ");
+ if (dimmInfo.suportedCasLatencies & BIT5)
+ mvOsOutput("3.5, ");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ {
+ if (dimmInfo.suportedCasLatencies & BIT2)
+ mvOsOutput("2, ");
+ if (dimmInfo.suportedCasLatencies & BIT3)
+ mvOsOutput("3, ");
+ if (dimmInfo.suportedCasLatencies & BIT4)
+ mvOsOutput("4, ");
+ if (dimmInfo.suportedCasLatencies & BIT5)
+ mvOsOutput("5, ");
+ }
+ else
+ mvOsOutput("?.?, ");
+ mvOsOutput("\n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 20: /* DDR2 DIMM type info */
+ if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ {
+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4))
+ mvOsOutput("Registered DIMM (RDIMM)\n");
+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5))
+ mvOsOutput("Unbuffered DIMM (UDIMM)\n");
+ else
+ mvOsOutput("Unknown DIMM type.\n");
+ }
+
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 21: /* SDRAM Modules Attributes */
+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n");
+
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ if (dimmInfo.dimmAttributes & BIT0)
+ mvOsOutput(" Buffered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Buffered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT1)
+ mvOsOutput(" Registered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Registered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT2)
+ mvOsOutput(" On-Card PLL (clock): Yes \n");
+ else
+ mvOsOutput(" On-Card PLL (clock): No \n");
+
+ if (dimmInfo.dimmAttributes & BIT3)
+ mvOsOutput(" Bufferd DQMB Input: Yes \n");
+ else
+ mvOsOutput(" Bufferd DQMB Inputs: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT4)
+ mvOsOutput(" Registered DQMB Inputs: Yes \n");
+ else
+ mvOsOutput(" Registered DQMB Inputs: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT5)
+ mvOsOutput(" Differential Clock Input: Yes \n");
+ else
+ mvOsOutput(" Differential Clock Input: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT6)
+ mvOsOutput(" redundant Row Addressing: Yes \n");
+ else
+ mvOsOutput(" redundant Row Addressing: No \n");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if (dimmInfo.dimmAttributes & BIT0)
+ mvOsOutput(" Buffered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Buffered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT1)
+ mvOsOutput(" Registered Addr/Control Input: Yes\n");
+ else
+ mvOsOutput(" Registered Addr/Control Input: No\n");
+
+ if (dimmInfo.dimmAttributes & BIT2)
+ mvOsOutput(" On-Card PLL (clock): Yes \n");
+ else
+ mvOsOutput(" On-Card PLL (clock): No \n");
+
+ if (dimmInfo.dimmAttributes & BIT3)
+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n");
+ else
+ mvOsOutput(" FET Switch On-Card Enabled: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT4)
+ mvOsOutput(" FET Switch External Enabled: Yes \n");
+ else
+ mvOsOutput(" FET Switch External Enabled: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT5)
+ mvOsOutput(" Differential Clock Input: Yes \n");
+ else
+ mvOsOutput(" Differential Clock Input: No \n");
+ }
+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */
+ {
+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n",
+ (dimmInfo.dimmAttributes & 0x3) + 1);
+
+ mvOsOutput(" Number of PLLs on the DIMM: %d\n",
+ ((dimmInfo.dimmAttributes) >> 2) & 0x3);
+
+ if (dimmInfo.dimmAttributes & BIT4)
+ mvOsOutput(" FET Switch External Enabled: Yes \n");
+ else
+ mvOsOutput(" FET Switch External Enabled: No \n");
+
+ if (dimmInfo.dimmAttributes & BIT6)
+ mvOsOutput(" Analysis probe installed: Yes \n");
+ else
+ mvOsOutput(" Analysis probe installed: No \n");
+ }
+
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 22: /* Suported AutoPreCharge */
+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n");
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ if ( spdRawData[i] & BIT0 )
+ mvOsOutput(" Early Ras Precharge: Yes \n");
+ else
+ mvOsOutput(" Early Ras Precharge: No \n");
+
+ if ( spdRawData[i] & BIT1 )
+ mvOsOutput(" AutoPreCharge: Yes \n");
+ else
+ mvOsOutput(" AutoPreCharge: No \n");
+
+ if ( spdRawData[i] & BIT2 )
+ mvOsOutput(" Precharge All: Yes \n");
+ else
+ mvOsOutput(" Precharge All: No \n");
+
+ if ( spdRawData[i] & BIT3 )
+ mvOsOutput(" Write 1/ReadBurst: Yes \n");
+ else
+ mvOsOutput(" Write 1/ReadBurst: No \n");
+
+ if ( spdRawData[i] & BIT4 )
+ mvOsOutput(" lower VCC tolerance: 5%%\n");
+ else
+ mvOsOutput(" lower VCC tolerance: 10%%\n");
+
+ if ( spdRawData[i] & BIT5 )
+ mvOsOutput(" upper VCC tolerance: 5%%\n");
+ else
+ mvOsOutput(" upper VCC tolerance: 10%%\n");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if ( spdRawData[i] & BIT0 )
+ mvOsOutput(" Supports Weak Driver: Yes \n");
+ else
+ mvOsOutput(" Supports Weak Driver: No \n");
+
+ if ( !(spdRawData[i] & BIT4) )
+ mvOsOutput(" lower VCC tolerance: 0.2V\n");
+
+ if ( !(spdRawData[i] & BIT5) )
+ mvOsOutput(" upper VCC tolerance: 0.2V\n");
+
+ if ( spdRawData[i] & BIT6 )
+ mvOsOutput(" Concurrent Auto Preharge: Yes \n");
+ else
+ mvOsOutput(" Concurrent Auto Preharge: No \n");
+
+ if ( spdRawData[i] & BIT7 )
+ mvOsOutput(" Supports Fast AP: Yes \n");
+ else
+ mvOsOutput(" Supports Fast AP: No \n");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2)
+ {
+ if ( spdRawData[i] & BIT0 )
+ mvOsOutput(" Supports Weak Driver: Yes \n");
+ else
+ mvOsOutput(" Supports Weak Driver: No \n");
+ }
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 23:
+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ rightOfPoint = (spdRawData[i] & 0x0f) * 10;
+
+ /* DDR2 addition of right of point */
+ if ((spdRawData[i] & 0x0f) == 0xA)
+ {
+ rightOfPoint = 25;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xB)
+ {
+ rightOfPoint = 33;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xC)
+ {
+ rightOfPoint = 66;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xD)
+ {
+ rightOfPoint = 75;
+ }
+
+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy"
+ "(0 = Not supported): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint );
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/
+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100;
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / div;
+ rightOfPoint = time_tmp % div;
+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 25:
+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2;
+ rightOfPoint = (spdRawData[i] & 0x3) * 25;
+ }
+ else /* DDR1 or DDR2 */
+ {
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ rightOfPoint = (spdRawData[i] & 0x0f) * 10;
+
+ /* DDR2 addition of right of point */
+ if ((spdRawData[i] & 0x0f) == 0xA)
+ {
+ rightOfPoint = 25;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xB)
+ {
+ rightOfPoint = 33;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xC)
+ {
+ rightOfPoint = 66;
+ }
+ if ((spdRawData[i] & 0x0f) == 0xD)
+ {
+ rightOfPoint = 75;
+ }
+ }
+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy"
+ "(0 = Not supported): %d.%d [ns]\n",
+ leftOfPoint, rightOfPoint );
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2;
+ rightOfPoint = (spdRawData[i] & 0x3) * 25;
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = 0;
+ rightOfPoint = time_tmp;
+ }
+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n",
+ leftOfPoint, rightOfPoint );
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 27: /* Minimum Row Precharge Time */
+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2;
+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0xff : 0xfc;
+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0x00 : 0x03;
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25;
+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/
+ trp_clocks = (temp + (busClkPs-1)) / busClkPs;
+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = "
+ "in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 28: /* Minimum Row Active to Row Active Time */
+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2;
+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0xff : 0xfc;
+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0x00 : 0x03;
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25;
+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/
+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs;
+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: "
+ "%d.%d = in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 29: /* Minimum Ras-To-Cas Delay */
+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2;
+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0xff : 0xfc;
+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ?
+ 0x00 : 0x03;
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25;
+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/
+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs;
+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = "
+ "in Clk cycles %d\n",
+ leftOfPoint, rightOfPoint, trp_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 30: /* Minimum Ras Pulse Width */
+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs;
+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = "
+ "in Clk cycles %d\n", spdRawData[i], tras_clocks);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 31: /* Module Bank Density */
+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):");
+
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ if (dimmInfo.dimmBankDensity & BIT0)
+ mvOsOutput("1GB, ");
+ if (dimmInfo.dimmBankDensity & BIT1)
+ mvOsOutput("8MB, ");
+ if (dimmInfo.dimmBankDensity & BIT2)
+ mvOsOutput("16MB, ");
+ if (dimmInfo.dimmBankDensity & BIT3)
+ mvOsOutput("32MB, ");
+ if (dimmInfo.dimmBankDensity & BIT4)
+ mvOsOutput("64MB, ");
+ if (dimmInfo.dimmBankDensity & BIT5)
+ mvOsOutput("128MB, ");
+ if (dimmInfo.dimmBankDensity & BIT6)
+ mvOsOutput("256MB, ");
+ if (dimmInfo.dimmBankDensity & BIT7)
+ mvOsOutput("512MB, ");
+ }
+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1)
+ {
+ if (dimmInfo.dimmBankDensity & BIT0)
+ mvOsOutput("1GB, ");
+ if (dimmInfo.dimmBankDensity & BIT1)
+ mvOsOutput("2GB, ");
+ if (dimmInfo.dimmBankDensity & BIT2)
+ mvOsOutput("16MB, ");
+ if (dimmInfo.dimmBankDensity & BIT3)
+ mvOsOutput("32MB, ");
+ if (dimmInfo.dimmBankDensity & BIT4)
+ mvOsOutput("64MB, ");
+ if (dimmInfo.dimmBankDensity & BIT5)
+ mvOsOutput("128MB, ");
+ if (dimmInfo.dimmBankDensity & BIT6)
+ mvOsOutput("256MB, ");
+ if (dimmInfo.dimmBankDensity & BIT7)
+ mvOsOutput("512MB, ");
+ }
+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */
+ {
+ if (dimmInfo.dimmBankDensity & BIT0)
+ mvOsOutput("1GB, ");
+ if (dimmInfo.dimmBankDensity & BIT1)
+ mvOsOutput("2GB, ");
+ if (dimmInfo.dimmBankDensity & BIT2)
+ mvOsOutput("4GB, ");
+ if (dimmInfo.dimmBankDensity & BIT3)
+ mvOsOutput("8GB, ");
+ if (dimmInfo.dimmBankDensity & BIT4)
+ mvOsOutput("16GB, ");
+ if (dimmInfo.dimmBankDensity & BIT5)
+ mvOsOutput("128MB, ");
+ if (dimmInfo.dimmBankDensity & BIT6)
+ mvOsOutput("256MB, ");
+ if (dimmInfo.dimmBankDensity & BIT7)
+ mvOsOutput("512MB, ");
+ }
+ mvOsOutput("\n");
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 32: /* Address And Command Setup Time (measured in ns/1000) */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 33: /* Address And Command Hold Time */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 34: /* Data Input Setup Time */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 35: /* Data Input Hold Time */
+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM)
+ {
+ rightOfPoint = (spdRawData[i] & 0x0f);
+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4;
+ if(leftOfPoint > 7)
+ {
+ leftOfPoint *= -1;
+ }
+ }
+ else /* DDR1 or DDR2 */
+ {
+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) +
+ ((spdRawData[i] & 0x0f));
+ leftOfPoint = time_tmp / 100;
+ rightOfPoint = time_tmp % 100;
+ }
+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+
+ case 36: /* Relevant for DDR2 only: Write Recovery Time */
+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2);
+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25;
+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n",
+ leftOfPoint, rightOfPoint);
+ break;
+/*----------------------------------------------------------------------------*/
+ }
+
+}
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into ps unit values
+ */
+/*******************************************************************************
+* cas2ps - Translate x.y ns parameter to pico-seconds values
+*
+* DESCRIPTION:
+* This function translates x.y nano seconds to its value in pico seconds.
+* For example 3.75ns will return 3750.
+*
+* INPUT:
+* spd_byte - DIMM SPD byte.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* value in pico seconds.
+*
+*******************************************************************************/
+static MV_U32 cas2ps(MV_U8 spd_byte)
+{
+ MV_U32 ns, ns10;
+
+ /* isolate upper nibble */
+ ns = (spd_byte >> 4) & 0x0F;
+ /* isolate lower nibble */
+ ns10 = (spd_byte & 0x0F);
+
+ if( ns10 < 10 ) {
+ ns10 *= 10;
+ }
+ else if( ns10 == 10 )
+ ns10 = 25;
+ else if( ns10 == 11 )
+ ns10 = 33;
+ else if( ns10 == 12 )
+ ns10 = 66;
+ else if( ns10 == 13 )
+ ns10 = 75;
+ else
+ {
+ mvOsOutput("cas2ps Err. unsupported cycle time.\n");
+ }
+
+ return (ns*1000 + ns10*10);
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h
new file mode 100644
index 000000000..f95546624
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h
@@ -0,0 +1,192 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvDram
+#define __INCmvDram
+
+#include "ddr2/mvDramIf.h"
+#include "twsi/mvTwsi.h"
+
+#define MAX_DIMM_NUM 2
+#define SPD_SIZE 128
+
+/* Dimm spd offsets */
+#define DIMM_MEM_TYPE 2
+#define DIMM_ROW_NUM 3
+#define DIMM_COL_NUM 4
+#define DIMM_MODULE_BANK_NUM 5
+#define DIMM_DATA_WIDTH 6
+#define DIMM_VOLT_IF 8
+#define DIMM_MIN_CC_AT_MAX_CAS 9
+#define DIMM_ERR_CHECK_TYPE 11
+#define DIMM_REFRESH_INTERVAL 12
+#define DIMM_SDRAM_WIDTH 13
+#define DIMM_ERR_CHECK_DATA_WIDTH 14
+#define DIMM_MIN_CLK_DEL 15
+#define DIMM_BURST_LEN_SUP 16
+#define DIMM_DEV_BANK_NUM 17
+#define DIMM_SUP_CAL 18
+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */
+#define DIMM_BUF_ADDR_CONT_IN 21
+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23
+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25
+#define DIMM_MIN_ROW_PRECHARGE_TIME 27
+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28
+#define DIMM_MIN_RAS_TO_CAS_DELAY 29
+#define DIMM_MIN_RAS_PULSE_WIDTH 30
+#define DIMM_BANK_DENSITY 31
+#define DIMM_MIN_WRITE_RECOVERY_TIME 36
+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37
+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38
+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42
+#define DIMM_SPD_VERSION 62
+
+/* Dimm Memory Type values */
+#define DIMM_MEM_TYPE_SDRAM 0x4
+#define DIMM_MEM_TYPE_DDR1 0x7
+#define DIMM_MEM_TYPE_DDR2 0x8
+
+#define DIMM_MODULE_MANU_OFFS 64
+#define DIMM_MODULE_MANU_SIZE 8
+#define DIMM_MODULE_VEN_OFFS 73
+#define DIMM_MODULE_VEN_SIZE 25
+#define DIMM_MODULE_ID_OFFS 99
+#define DIMM_MODULE_ID_SIZE 18
+
+/* enumeration for voltage levels. */
+typedef enum _mvDimmVoltageIf
+{
+ TTL_5V_TOLERANT,
+ LVTTL,
+ HSTL_1_5V,
+ SSTL_3_3V,
+ SSTL_2_5V,
+ VOLTAGE_UNKNOWN,
+} MV_DIMM_VOLTAGE_IF;
+
+
+/* enumaration for SDRAM CAS Latencies. */
+typedef enum _mvDimmSdramCas
+{
+ SD_CL_1 =1,
+ SD_CL_2,
+ SD_CL_3,
+ SD_CL_4,
+ SD_CL_5,
+ SD_CL_6,
+ SD_CL_7,
+ SD_FAULT
+}MV_DIMM_SDRAM_CAS;
+
+
+/* DIMM information structure */
+typedef struct _mvDimmInfo
+{
+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */
+
+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */
+
+ /* DIMM dimensions */
+ MV_U32 numOfRowAddr;
+ MV_U32 numOfColAddr;
+ MV_U32 numOfModuleBanks;
+ MV_U32 dataWidth;
+ MV_U32 errorCheckType; /* ECC , PARITY..*/
+ MV_U32 sdramWidth; /* 4,8,16 or 32 */
+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
+ MV_U32 burstLengthSupported;
+ MV_U32 numOfBanksOnEachDevice;
+ MV_U32 suportedCasLatencies;
+ MV_U32 refreshInterval;
+ MV_U32 dimmBankDensity;
+ MV_U32 dimmTypeInfo; /* DDR2 only */
+ MV_U32 dimmAttributes;
+
+ /* DIMM timing parameters */
+ MV_U32 minCycleTimeAtMaxCasLatPs;
+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
+ MV_U32 minRowPrechargeTime;
+ MV_U32 minRowActiveToRowActive;
+ MV_U32 minRasToCasDelay;
+ MV_U32 minRasPulseWidth;
+ MV_U32 minWriteRecoveryTime; /* DDR2 only */
+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */
+
+ /* Parameters calculated from the extracted DIMM information */
+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */
+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */
+ MV_U32 numberOfDevices;
+
+} MV_DIMM_INFO;
+
+
+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo);
+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo);
+MV_VOID dimmSpdPrint(MV_U32 dimmNum);
+MV_STATUS dimmSpdCpy(MV_VOID);
+
+#endif /* __INCmvDram */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c
new file mode 100644
index 000000000..d24e788fc
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c
@@ -0,0 +1,2952 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver
+*
+* DESCRIPTION:
+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet
+* controller. This Gigabit Ethernet Controller driver API controls
+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc').
+* 2) Data flow (i.e. port Send, Receive etc').
+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.)
+* 4) MIB counters support (ethReadMibCounter)
+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.)
+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct.
+* This struct includes configuration information as well as driver
+* internal data needed for its operations.
+*
+* Supported Features:
+* - OS independent. All required OS services are implemented via external
+* OS dependent components (like osLayer or ethOsg)
+* - The user is free from Rx/Tx queue managing.
+* - Simple Gigabit Ethernet port operation API.
+* - Simple Gigabit Ethernet port data flow API.
+* - Data flow and operation API support per queue functionality.
+* - Support cached descriptors for better performance.
+* - PHY access and control API.
+* - Port Configuration API.
+* - Full control over Special and Other Multicast MAC tables.
+*
+*******************************************************************************/
+/* includes */
+#include "mvTypes.h"
+#include "mv802_3.h"
+#include "mvDebug.h"
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "eth-phy/mvEthPhy.h"
+#include "eth/mvEth.h"
+#include "eth/gbe/mvEthGbe.h"
+#include "cpu/mvCpu.h"
+
+#ifdef INCLUDE_SYNC_BARR
+#include "sys/mvCpuIf.h"
+#endif
+
+#ifdef MV_RT_DEBUG
+# define ETH_DEBUG
+#endif
+
+
+/* locals */
+MV_BOOL ethDescInSram;
+MV_BOOL ethDescSwCoher;
+
+/* This array holds the control structure of each port */
+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS];
+
+/* Ethernet Port Local routines */
+
+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue);
+
+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue);
+
+static void ethSetUcastTable(int portNo, int queue);
+
+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue);
+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue);
+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue);
+
+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf);
+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size,
+ MV_ULONG* pPhysAddr, MV_U32 *memHandle);
+
+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize);
+
+static void mvEthPortSgmiiConfig(int port);
+
+
+
+/******************************************************************************/
+/* EthDrv Initialization functions */
+/******************************************************************************/
+
+/*******************************************************************************
+* mvEthHalInit - Initialize the Giga Ethernet unit
+*
+* DESCRIPTION:
+* This function initialize the Giga Ethernet unit.
+* 1) Configure Address decode windows of the unit
+* 2) Set registers to HW default values.
+* 3) Clear and Disable interrupts
+*
+* INPUT: NONE
+*
+* RETURN: NONE
+*
+* NOTE: this function is called once in the boot process.
+*******************************************************************************/
+void mvEthHalInit(void)
+{
+ int port;
+
+ /* Init static data structures */
+ for (port=0; port<MV_ETH_MAX_PORTS; port++)
+ {
+ ethPortCtrl[port] = NULL;
+ }
+ /* Power down all existing ports */
+ for(port=0; port<mvCtrlEthMaxPortGet(); port++)
+ {
+
+#if defined (MV78200)
+ /* Skip ports mapped to another CPU*/
+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(GIGA0+port))
+ {
+ continue;
+ }
+#endif
+
+ /* Skip power down ports */
+ if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port)) continue;
+
+ /* Disable Giga Ethernet Unit interrupts */
+ MV_REG_WRITE(ETH_UNIT_INTR_MASK_REG(port), 0);
+
+ /* Clear ETH_UNIT_INTR_CAUSE_REG register */
+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0);
+
+ }
+
+ mvEthMemAttrGet(&ethDescInSram, &ethDescSwCoher);
+
+#if defined(ETH_DESCR_IN_SRAM)
+ if(ethDescInSram == MV_FALSE)
+ {
+ mvOsPrintf("ethDrv: WARNING! Descriptors will be allocated in DRAM instead of SRAM.\n");
+ }
+#endif /* ETH_DESCR_IN_SRAM */
+}
+
+/*******************************************************************************
+* mvEthMemAttrGet - Define properties (SRAM/DRAM, SW_COHER / HW_COHER / UNCACHED)
+* of of memory location for RX and TX descriptors.
+*
+* DESCRIPTION:
+* This function allocates memory for RX and TX descriptors.
+* - If ETH_DESCR_IN_SRAM defined, allocate from SRAM memory.
+* - If ETH_DESCR_IN_SDRAM defined, allocate from SDRAM memory.
+*
+* INPUT:
+* MV_BOOL* pIsSram - place of descriptors:
+* MV_TRUE - in SRAM
+* MV_FALSE - in DRAM
+* MV_BOOL* pIsSwCoher - cache coherency of descriptors:
+* MV_TRUE - driver is responsible for cache coherency
+* MV_FALSE - driver is not responsible for cache coherency
+*
+* RETURN:
+*
+*******************************************************************************/
+void mvEthMemAttrGet(MV_BOOL* pIsSram, MV_BOOL* pIsSwCoher)
+{
+ MV_BOOL isSram, isSwCoher;
+
+ isSram = MV_FALSE;
+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW)
+ isSwCoher = MV_TRUE;
+#else
+ isSwCoher = MV_FALSE;
+#endif
+
+#if defined(ETH_DESCR_IN_SRAM)
+ if( mvCtrlSramSizeGet() > 0)
+ {
+ isSram = MV_TRUE;
+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW)
+ isSwCoher = MV_TRUE;
+ #else
+ isSwCoher = MV_FALSE;
+ #endif
+ }
+#endif /* ETH_DESCR_IN_SRAM */
+
+ if(pIsSram != NULL)
+ *pIsSram = isSram;
+
+ if(pIsSwCoher != NULL)
+ *pIsSwCoher = isSwCoher;
+}
+
+
+
+/******************************************************************************/
+/* Port Initialization functions */
+/******************************************************************************/
+
+/*******************************************************************************
+* mvEthPortInit - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+* This function initialize the ethernet port.
+* 1) Allocate and initialize internal port Control structure.
+* 2) Create RX and TX descriptor rings for default RX and TX queues
+* 3) Disable RX and TX operations, clear cause registers and
+* mask all interrupts.
+* 4) Set all registers to default values and clean all MAC tables.
+*
+* INPUT:
+* int portNo - Ethernet port number
+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure
+*
+* RETURN:
+* void* - ethernet port handler, that should be passed to the most other
+* functions dealing with this port.
+*
+* NOTE: This function is called once per port when loading the eth module.
+*******************************************************************************/
+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit)
+{
+ int queue, descSize;
+ ETH_PORT_CTRL* pPortCtrl;
+
+ /* Check validity of parameters */
+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) ||
+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) ||
+ (pEthPortInit->maxRxPktSize < 1518) )
+ {
+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo);
+ return NULL;
+ }
+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0)
+ {
+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n",
+ portNo, pEthPortInit->rxDefQ);
+ return NULL;
+ }
+
+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) );
+ if(pPortCtrl == NULL)
+ {
+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n",
+ (int)sizeof(ETH_PORT_CTRL), portNo);
+ return NULL;
+ }
+
+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) );
+ ethPortCtrl[portNo] = pPortCtrl;
+
+ pPortCtrl->portState = MV_UNDEFINED_STATE;
+
+ pPortCtrl->portNo = portNo;
+
+ pPortCtrl->osHandle = pEthPortInit->osHandle;
+
+ /* Copy Configuration parameters */
+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize;
+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ;
+ pPortCtrl->portConfig.ejpMode = 0;
+
+ for( queue=0; queue<MV_ETH_RX_Q_NUM; queue++ )
+ {
+ pPortCtrl->rxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue];
+ }
+ for( queue=0; queue<MV_ETH_TX_Q_NUM; queue++ )
+ {
+ pPortCtrl->txQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue];
+ }
+
+ mvEthPortDisable(pPortCtrl);
+
+ /* Set the board information regarding PHY address */
+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) );
+
+ /* Create all requested RX queues */
+ for(queue=0; queue<MV_ETH_RX_Q_NUM; queue++)
+ {
+ if(pPortCtrl->rxQueueConfig[queue].descrNum == 0)
+ continue;
+
+ /* Allocate memory for RX descriptors */
+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) +
+ CPU_D_CACHE_LINE_SIZE);
+
+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr =
+ ethAllocDescrMemory(pPortCtrl, descSize,
+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr,
+ &pPortCtrl->rxQueue[queue].descBuf.memHandle);
+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize;
+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL)
+ {
+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n",
+ pPortCtrl->portNo, queue, descSize,
+ ethDescInSram ? "SRAM" : "DRAM",
+ pPortCtrl->rxQueueConfig[queue].descrNum);
+ return NULL;
+ }
+
+ ethInitRxDescRing(pPortCtrl, queue);
+ }
+ /* Create TX queues */
+ for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
+ {
+ if(pPortCtrl->txQueueConfig[queue].descrNum == 0)
+ continue;
+
+ /* Allocate memory for TX descriptors */
+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) +
+ CPU_D_CACHE_LINE_SIZE);
+
+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr =
+ ethAllocDescrMemory(pPortCtrl, descSize,
+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr,
+ &pPortCtrl->txQueue[queue].descBuf.memHandle);
+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize;
+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL)
+ {
+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n",
+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM",
+ pPortCtrl->txQueueConfig[queue].descrNum);
+ return NULL;
+ }
+
+ ethInitTxDescRing(pPortCtrl, queue);
+ }
+ mvEthDefaultsSet(pPortCtrl);
+
+ pPortCtrl->portState = MV_IDLE;
+ return pPortCtrl;
+}
+
+/*******************************************************************************
+* ethPortFinish - Finish the Ethernet port driver
+*
+* DESCRIPTION:
+* This function finish the ethernet port.
+* 1) Down ethernet port if needed.
+* 2) Delete RX and TX descriptor rings for all created RX and TX queues
+* 3) Free internal port Control structure.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler
+*
+* RETURN: NONE.
+*
+*******************************************************************************/
+void mvEthPortFinish(void* pPortHndl)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ int queue, portNo = pPortCtrl->portNo;
+
+ if(pPortCtrl->portState == MV_ACTIVE)
+ {
+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n",
+ portNo);
+ mvEthPortDisable(pPortHndl);
+ }
+
+ /* Free all allocated RX queues */
+ for(queue=0; queue<MV_ETH_RX_Q_NUM; queue++)
+ {
+ ethFreeDescrMemory(pPortCtrl, &pPortCtrl->rxQueue[queue].descBuf);
+ }
+
+ /* Free all allocated TX queues */
+ for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
+ {
+ ethFreeDescrMemory(pPortCtrl, &pPortCtrl->txQueue[queue].descBuf);
+ }
+
+ /* Free port control structure */
+ mvOsFree(pPortCtrl);
+
+ ethPortCtrl[portNo] = NULL;
+}
+
+/*******************************************************************************
+* mvEthDefaultsSet - Set defaults to the ethernet port
+*
+* DESCRIPTION:
+* This function set default values to the ethernet port.
+* 1) Clear Cause registers and Mask all interrupts
+* 2) Clear all MAC tables
+* 3) Set defaults to all registers
+* 4) Reset all created RX and TX descriptors ring
+* 5) Reset PHY
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Others - Failure
+* NOTE:
+* This function update all the port configuration except those set
+* Initialy by the OsGlue by MV_ETH_PORT_INIT.
+* This function can be called after portDown to return the port setting
+* to defaults.
+*******************************************************************************/
+MV_STATUS mvEthDefaultsSet(void* pPortHndl)
+{
+ int ethPortNo, queue;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ MV_U32 txPrio;
+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg;
+ MV_BOARD_MAC_SPEED boardMacCfg;
+
+ ethPortNo = pPortCtrl->portNo;
+
+ /* Clear Cause registers */
+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0);
+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0);
+
+ /* Mask all interrupts */
+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0);
+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0);
+
+ portCfgReg = PORT_CONFIG_VALUE;
+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE;
+
+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo);
+
+ if(boardMacCfg == BOARD_MAC_SPEED_100M)
+ {
+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE;
+ }
+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M)
+ {
+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE;
+ }
+ else
+ {
+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE;
+ }
+
+ /* build PORT_SDMA_CONFIG_REG */
+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0);
+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE);
+
+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \
+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) )
+ /* some devices have restricted RX burst size when using HW coherency */
+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE);
+#else
+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE);
+#endif
+
+#if defined(MV_CPU_BE)
+ /* big endian */
+# if defined(MV_ARM)
+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK |
+ ETH_TX_NO_DATA_SWAP_MASK |
+ ETH_DESC_SWAP_MASK);
+# elif defined(MV_PPC)
+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK |
+ ETH_TX_DATA_SWAP_MASK |
+ ETH_NO_DESC_SWAP_MASK);
+# else
+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH"
+# endif /* MV_ARM / MV_PPC */
+
+#else /* MV_CPU_LE */
+ /* little endian */
+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK |
+ ETH_TX_NO_DATA_SWAP_MASK |
+ ETH_NO_DESC_SWAP_MASK);
+#endif /* MV_CPU_BE / MV_CPU_LE */
+
+ pPortCtrl->portRxQueueCmdReg = 0;
+ pPortCtrl->portTxQueueCmdReg = 0;
+
+#if (MV_ETH_VERSION >= 4)
+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE)
+ {
+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK);
+ }
+ else
+ {
+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0)
+ }
+#endif /* (MV_ETH_VERSION >= 4) */
+
+ ethSetUcastTable(ethPortNo, -1);
+ mvEthSetSpecialMcastTable(ethPortNo, -1);
+ mvEthSetOtherMcastTable(ethPortNo, -1);
+
+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK;
+
+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize);
+
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg);
+
+ /* Update value of PortConfig register accordingly with all RxQueue types */
+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ;
+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ;
+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ;
+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ;
+
+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ);
+
+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ);
+
+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ);
+
+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ);
+
+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ);
+
+ /* Assignment of Tx CTRP of given queue */
+ txPrio = 0;
+
+ for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
+ {
+ pQueueCtrl = &pPortCtrl->txQueue[queue];
+
+ if(pQueueCtrl->pFirstDescr != NULL)
+ {
+ ethResetTxDescRing(pPortCtrl, queue);
+
+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue),
+ 0x3fffffff);
+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue),
+ 0x03ffffff);
+ }
+ else
+ {
+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0);
+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0);
+ }
+ }
+
+ /* Assignment of Rx CRDP of given queue */
+ for(queue=0; queue<MV_ETH_RX_Q_NUM; queue++)
+ {
+ ethResetRxDescRing(pPortCtrl, queue);
+ }
+
+ /* Allow receiving packes with odd number of preamble nibbles */
+ portSerialCtrl1Reg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(ethPortNo));
+ portSerialCtrl1Reg |= ETH_EN_MII_ODD_PRE_MASK;
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(ethPortNo), portSerialCtrl1Reg);
+
+ /* Assign port configuration and command. */
+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(ethPortNo), portCfgReg);
+
+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(ethPortNo), portCfgExtReg);
+
+ /* Assign port SDMA configuration */
+ MV_REG_WRITE(ETH_SDMA_CONFIG_REG(ethPortNo), portSdmaCfgReg);
+
+ /* Turn off the port/queue bandwidth limitation */
+ MV_REG_WRITE(ETH_MAX_TRANSMIT_UNIT_REG(ethPortNo), 0x0);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* ethPortUp - Start the Ethernet port RX and TX activity.
+*
+* DESCRIPTION:
+* This routine start Rx and Tx activity:
+*
+* Note: Each Rx and Tx queue descriptor's list must be initialized prior
+* to calling this function (use etherInitTxDescRing for Tx queues and
+* etherInitRxDescRing for Rx queues).
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Others - Failure.
+*
+* NOTE : used for port link up.
+*******************************************************************************/
+MV_STATUS mvEthPortUp(void* pEthPortHndl)
+{
+ int ethPortNo;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+
+ ethPortNo = pPortCtrl->portNo;
+
+ if( (pPortCtrl->portState != MV_ACTIVE) &&
+ (pPortCtrl->portState != MV_PAUSED) )
+ {
+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n",
+ ethPortNo, pPortCtrl->portState);
+ return MV_BAD_STATE;
+ }
+
+ ethPortNo = pPortCtrl->portNo;
+
+ /* Enable port RX. */
+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg);
+
+ /* Enable port TX. */
+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg;
+
+ pPortCtrl->portState = MV_ACTIVE;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* ethPortDown - Stop the Ethernet port activity.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Others - Failure.
+*
+* NOTE : used for port link down.
+*******************************************************************************/
+MV_STATUS mvEthPortDown(void* pEthPortHndl)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ int ethPortNum = pPortCtrl->portNo;
+ unsigned int regData;
+ volatile int uDelay, mDelay;
+
+ /* Stop Rx port activity. Check port Rx activity. */
+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK;
+ if(regData != 0)
+ {
+ /* Issue stop command for active channels only */
+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET));
+ }
+
+ /* Stop Tx port activity. Check port Tx activity. */
+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK;
+ if(regData != 0)
+ {
+ /* Issue stop command for active channels only */
+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum),
+ (regData << ETH_TXQ_DISABLE_OFFSET) );
+ }
+
+ /* Force link down */
+/*
+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum));
+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK);
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData);
+*/
+ /* Wait for all Rx activity to terminate. */
+ mDelay = 0;
+ do
+ {
+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC)
+ {
+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n",
+ ethPortNum, regData);
+ break;
+ }
+ mvOsDelay(1);
+ mDelay++;
+
+ /* Check port RX Command register that all Rx queues are stopped */
+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum));
+ }
+ while(regData & 0xFF);
+
+ /* Wait for all Tx activity to terminate. */
+ mDelay = 0;
+ do
+ {
+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC)
+ {
+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n",
+ ethPortNum, regData);
+ break;
+ }
+ mvOsDelay(1);
+ mDelay++;
+
+ /* Check port TX Command register that all Tx queues are stopped */
+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum));
+ }
+ while(regData & 0xFF);
+
+ /* Double check to Verify that TX FIFO is Empty */
+ mDelay = 0;
+ while(MV_TRUE)
+ {
+ do
+ {
+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC)
+ {
+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n",
+ ethPortNum, regData);
+ break;
+ }
+ mvOsDelay(1);
+ mDelay++;
+
+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum));
+ }
+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) ||
+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) );
+
+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC)
+ break;
+
+ /* Double check */
+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum));
+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) &&
+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) )
+ {
+ break;
+ }
+ else
+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n",
+ ethPortNum, mDelay, regData);
+ }
+
+ /* Do NOT force link down */
+/*
+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum));
+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK);
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData);
+*/
+ /* Wait about 2500 tclk cycles */
+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000));
+ mvOsUDelay(uDelay);
+
+ pPortCtrl->portState = MV_PAUSED;
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* ethPortEnable - Enable the Ethernet port and Start RX and TX.
+*
+* DESCRIPTION:
+* This routine enable the Ethernet port and Rx and Tx activity:
+*
+* Note: Each Rx and Tx queue descriptor's list must be initialized prior
+* to calling this function (use etherInitTxDescRing for Tx queues and
+* etherInitRxDescRing for Rx queues).
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Others - Failure.
+*
+* NOTE: main usage is to enable the port after ifconfig up.
+*******************************************************************************/
+MV_STATUS mvEthPortEnable(void* pEthPortHndl)
+{
+ int ethPortNo;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ MV_U32 portSerialCtrlReg;
+
+ ethPortNo = pPortCtrl->portNo;
+
+ /* Enable port */
+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo));
+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK);
+
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg);
+
+ mvEthMibCountersClear(pEthPortHndl);
+
+ pPortCtrl->portState = MV_PAUSED;
+
+ /* If Link is UP, Start RX and TX traffic */
+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK)
+ return( mvEthPortUp(pEthPortHndl) );
+
+ return MV_NOT_READY;
+}
+
+
+/*******************************************************************************
+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Others - Failure.
+*
+* NOTE: main usage is to disable the port after ifconfig down.
+*******************************************************************************/
+MV_STATUS mvEthPortDisable(void* pEthPortHndl)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ int ethPortNum = pPortCtrl->portNo;
+ unsigned int regData;
+ volatile int mvDelay;
+
+ if(pPortCtrl->portState == MV_ACTIVE)
+ {
+ /* Stop RX and TX activities */
+ mvEthPortDown(pEthPortHndl);
+ }
+
+ /* Reset the Enable bit in the Serial Control Register */
+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum));
+ regData &= ~(ETH_PORT_ENABLE_MASK);
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData);
+
+ /* Wait about 2500 tclk cycles */
+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet()));
+ for(mvDelay; mvDelay>0; mvDelay--);
+
+ pPortCtrl->portState = MV_IDLE;
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership.
+*
+* DESCRIPTION:
+* This routine used to free buffers attached to the Tx ring and should
+* be called only when Giga Ethernet port is Down
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int txQueue - Number of TX queue.
+*
+* OUTPUT:
+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent.
+*
+* RETURN:
+* MV_EMPTY - There is no more buffers in this queue.
+* MV_OK - Buffer detached from the queue and pPktInfo structure
+* filled with relevant information.
+*
+*******************************************************************************/
+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ MV_PKT_INFO* pPktInfo;
+ ETH_TX_DESC* pTxDesc;
+ int port = pPortCtrl->portNo;
+
+ pQueueCtrl = &pPortCtrl->txQueue[txQueue];
+
+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) ||
+ (pQueueCtrl->resource == 0) )
+ {
+ /* Free next descriptor */
+ pQueueCtrl->resource++;
+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr;
+
+ /* pPktInfo is available only in descriptors which are last descriptors */
+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo;
+ if (pPktInfo)
+ pPktInfo->status = pTxDesc->cmdSts;
+
+ pTxDesc->cmdSts = 0x0;
+ pTxDesc->returnInfo = 0x0;
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc);
+
+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl);
+
+ if (pPktInfo)
+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK)
+ return pPktInfo;
+ }
+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue),
+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) );
+ return NULL;
+}
+
+
+
+/*******************************************************************************
+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership.
+*
+* DESCRIPTION:
+* This routine used to free buffers attached to the Rx ring and should
+* be called only when Giga Ethernet port is Down
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int rxQueue - Number of Rx queue.
+*
+* OUTPUT:
+* MV_PKT_INFO *pPktInfo - Pointer to received packet.
+*
+* RETURN:
+* MV_EMPTY - There is no more buffers in this queue.
+* MV_OK - Buffer detached from the queue and pBufInfo structure
+* filled with relevant information.
+*
+*******************************************************************************/
+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ ETH_RX_DESC* pRxDesc;
+ MV_PKT_INFO* pPktInfo;
+ int port = pPortCtrl->portNo;
+
+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue];
+
+ if(pQueueCtrl->resource == 0)
+ {
+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue),
+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) );
+
+ return NULL;
+ }
+ /* Free next descriptor */
+ pQueueCtrl->resource--;
+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr;
+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo;
+
+ pPktInfo->status = pRxDesc->cmdSts;
+ pRxDesc->cmdSts = 0x0;
+ pRxDesc->returnInfo = 0x0;
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc);
+
+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl);
+ return pPktInfo;
+}
+
+
+/******************************************************************************/
+/* Port Configuration functions */
+/******************************************************************************/
+/*******************************************************************************
+* mvEthMruGet - Get MRU configuration for Max Rx packet size.
+*
+* INPUT:
+* MV_U32 maxRxPktSize - max packet size.
+*
+* RETURN: MV_U32 - MRU configuration.
+*
+*******************************************************************************/
+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize)
+{
+ MV_U32 portSerialCtrlReg = 0;
+
+ if(maxRxPktSize > 9192)
+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE;
+ else if(maxRxPktSize > 9022)
+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE;
+ else if(maxRxPktSize > 1552)
+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE;
+ else if(maxRxPktSize > 1522)
+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE;
+ else if(maxRxPktSize > 1518)
+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE;
+ else
+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE;
+
+ return portSerialCtrlReg;
+}
+
+/*******************************************************************************
+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path
+*
+* DESCRIPTION:
+* This routine sets the RX coalescing interrupt mechanism parameter.
+* This parameter is a timeout counter, that counts in 64 tClk
+* chunks, that when timeout event occurs a maskable interrupt occurs.
+* The parameter is calculated using the tCLK frequency of the
+* MV-64xxx chip, and the required number is in micro seconds.
+*
+* INPUT:
+* void* pPortHndl - Ethernet Port handler.
+* MV_U32 uSec - Number of micro seconds between
+* RX interrupts
+*
+* RETURN:
+* None.
+*
+* COMMENT:
+* 1 sec - TCLK_RATE clocks
+* 1 uSec - TCLK_RATE / 1,000,000 clocks
+*
+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64)
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64);
+ MV_U32 portSdmaCfgReg;
+
+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo));
+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK;
+
+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal);
+
+#if (MV_ETH_VERSION >= 2)
+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */
+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK)
+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK;
+#endif /* MV_ETH_VERSION >= 2 */
+
+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg);
+ return coal;
+}
+
+/*******************************************************************************
+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path
+*
+* DESCRIPTION:
+* This routine sets the TX coalescing interrupt mechanism parameter.
+* This parameter is a timeout counter, that counts in 64 tClk
+* chunks, that when timeout event occurs a maskable interrupt
+* occurs.
+* The parameter is calculated using the tCLK frequency of the
+* MV-64xxx chip, and the required number is in micro seconds.
+*
+* INPUT:
+* void* pPortHndl - Ethernet Port handler.
+* MV_U32 uSec - Number of micro seconds between
+* RX interrupts
+*
+* RETURN:
+* None.
+*
+* COMMENT:
+* 1 sec - TCLK_RATE clocks
+* 1 uSec - TCLK_RATE / 1,000,000 clocks
+*
+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64)
+*
+*******************************************************************************/
+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64);
+ MV_U32 regVal;
+
+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo));
+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK;
+ regVal |= ETH_TX_INTR_COAL_MASK(coal);
+
+ /* Set TX Coalescing mechanism */
+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal);
+ return coal;
+}
+
+/*******************************************************************************
+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds
+*
+* DESCRIPTION:
+* This routine gets the RX and TX coalescing interrupt values.
+* The parameter is calculated using the tCLK frequency of the
+* MV-64xxx chip, and the returned numbers are in micro seconds.
+*
+* INPUTs:
+* void* pPortHndl - Ethernet Port handler.
+*
+* OUTPUTs:
+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts
+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts
+*
+* RETURN:
+* MV_STATUS MV_OK - success
+* Others - failure.
+*
+* COMMENT:
+* 1 sec - TCLK_RATE clocks
+* 1 uSec - TCLK_RATE / 1,000,000 clocks
+*
+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64)
+*
+*******************************************************************************/
+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal)
+{
+ MV_U32 regVal, coal, usec;
+
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ /* get TX Coalescing */
+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo));
+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET);
+
+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000);
+ if(pTxCoal != NULL)
+ *pTxCoal = usec;
+
+ /* Get RX Coalescing */
+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo));
+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET);
+
+#if (MV_ETH_VERSION >= 2)
+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK)
+ {
+ /* Add MSB */
+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1);
+ }
+#endif /* MV_ETH_VERSION >= 2 */
+
+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000);
+ if(pRxCoal != NULL)
+ *pRxCoal = usec;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthMaxRxSizeSet -
+*
+* DESCRIPTION:
+* Change maximum receive size of the port. This configuration will take place
+* after next call of ethPortSetDefaults() function.
+*
+* INPUT:
+*
+* RETURN:
+*******************************************************************************/
+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ MV_U32 portSerialCtrlReg;
+
+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK))
+ return MV_BAD_PARAM;
+
+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize;
+
+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo));
+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK;
+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize);
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg);
+
+ return MV_OK;
+}
+
+
+/******************************************************************************/
+/* MAC Filtering functions */
+/******************************************************************************/
+
+/*******************************************************************************
+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port
+*
+* DESCRIPTION:
+* This routine used to free buffers attached to the Rx ring and should
+* be called only when Giga Ethernet port is Down
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* MV_BOOL isPromisc - Promiscous mode
+* MV_TRUE - accept all Broadcast, Multicast
+* and Unicast packets
+* MV_FALSE - accept all Broadcast,
+* specially added Multicast and
+* single Unicast packets
+*
+* RETURN: MV_STATUS MV_OK - Success, Other - Failure
+*
+*******************************************************************************/
+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ int queue;
+ MV_U32 portCfgReg;
+
+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo));
+ /* Set / Clear UPM bit in port configuration register */
+ if(isPromisc)
+ {
+ /* Accept all multicast packets to RX default queue */
+ queue = pPortCtrl->portConfig.rxDefQ;
+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK;
+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount));
+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF);
+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF);
+ }
+ else
+ {
+ /* Reject all Multicast addresses */
+ queue = -1;
+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK;
+ /* Clear all mcastCount */
+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount));
+ }
+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg);
+
+ /* Set Special Multicast and Other Multicast tables */
+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue);
+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue);
+ ethSetUcastTable(pPortCtrl->portNo, queue);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthMacAddrSet - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+* This function Set the port Ethernet MAC address. This address
+* will be used to send Pause frames if enabled. Packets with this
+* address will be accepted and dispatched to default RX queue
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler.
+* char* pAddr - Address to be set
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Other - Faulure
+*
+*******************************************************************************/
+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ unsigned int macH;
+ unsigned int macL;
+
+ if(queue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue);
+ return MV_BAD_PARAM;
+ }
+
+ if(queue != -1)
+ {
+ macL = (pAddr[4] << 8) | (pAddr[5]);
+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) |
+ (pAddr[2] << 8) | (pAddr[3] << 0);
+
+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL);
+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH);
+ }
+
+ /* Accept frames of this address */
+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthMacAddrGet - This function returns the port Unicast address.
+*
+* DESCRIPTION:
+* This function returns the port Ethernet MAC address.
+*
+* INPUT:
+* int portNo - Ethernet port number.
+* char* pAddr - Pointer where address will be written to
+*
+* RETURN: MV_STATUS
+* MV_OK - Success, Other - Faulure
+*
+*******************************************************************************/
+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr)
+{
+ unsigned int macH;
+ unsigned int macL;
+
+ if(pAddr == NULL)
+ {
+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n");
+ return MV_BAD_PARAM;
+ }
+
+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo));
+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo));
+ pAddr[0] = (macH >> 24) & 0xff;
+ pAddr[1] = (macH >> 16) & 0xff;
+ pAddr[2] = (macH >> 8) & 0xff;
+ pAddr[3] = macH & 0xff;
+ pAddr[4] = (macL >> 8) & 0xff;
+ pAddr[5] = macL & 0xff;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* MV_U8* pAddr - Address to calculate CRC-8
+*
+* RETURN: MV_U8 - CRC-8 of this MAC address
+*
+*******************************************************************************/
+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr)
+{
+ unsigned int macH;
+ unsigned int macL;
+ int macArray[48];
+ int crc[8];
+ int i;
+ unsigned char crcResult = 0;
+
+ /* Calculate CRC-8 out of the given address */
+ macH = (pAddr[0] << 8) | (pAddr[1]);
+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) |
+ (pAddr[4] << 8) | (pAddr[5] << 0);
+
+ for(i=0; i<32; i++)
+ macArray[i] = (macL >> i) & 0x1;
+
+ for(i=32; i<48; i++)
+ macArray[i] = (macH >> (i - 32)) & 0x1;
+
+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^
+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^
+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^
+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^
+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0];
+
+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^
+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^
+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^
+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^
+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^
+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^
+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0];
+
+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^
+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^
+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^
+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^
+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^
+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0];
+
+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^
+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^
+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^
+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^
+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^
+ macArray[3] ^ macArray[2] ^ macArray[1];
+
+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^
+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^
+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^
+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^
+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^
+ macArray[3] ^ macArray[2];
+
+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^
+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^
+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^
+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^
+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^
+ macArray[4] ^ macArray[3];
+
+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^
+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^
+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^
+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^
+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^
+ macArray[4];
+
+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^
+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^
+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^
+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^
+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5];
+
+ for(i=0; i<8; i++)
+ crcResult = crcResult | (crc[i] << i);
+
+ return crcResult;
+}
+/*******************************************************************************
+* mvEthMcastAddrSet - Multicast address settings.
+*
+* DESCRIPTION:
+* This API controls the MV device MAC multicast support.
+* The MV device supports multicast using two tables:
+* 1) Special Multicast Table for MAC addresses of the form
+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+* Table entries in the DA-Filter table.
+* In this case, the function calls ethPortSmcAddr() routine to set the
+* Special Multicast Table.
+* 2) Other Multicast Table for multicast of another type. A CRC-8bit
+* is used as an index to the Other Multicast Table entries in the
+* DA-Filter table.
+* In this case, the function calculates the CRC-8bit value and calls
+* ethPortOmcAddr() routine to set the Other Multicast Table.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet port handler.
+* MV_U8* pAddr - Address to be set
+* int queue - RX queue to capture all packets with this
+* Multicast MAC address.
+* -1 means delete this Multicast address.
+*
+* RETURN: MV_STATUS
+* MV_TRUE - Success, Other - Failure
+*
+*******************************************************************************/
+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ unsigned char crcResult = 0;
+
+ if(queue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n",
+ pPortCtrl->portNo, queue);
+ return MV_BAD_PARAM;
+ }
+
+ if((pAddr[0] == 0x01) &&
+ (pAddr[1] == 0x00) &&
+ (pAddr[2] == 0x5E) &&
+ (pAddr[3] == 0x00) &&
+ (pAddr[4] == 0x00))
+ {
+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue);
+ }
+ else
+ {
+ crcResult = mvEthMcastCrc8Get(pAddr);
+
+ /* Check Add counter for this CRC value */
+ if(queue == -1)
+ {
+ if(pPortCtrl->mcastCount[crcResult] == 0)
+ {
+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n",
+ pPortCtrl->portNo, (unsigned)crcResult);
+ return MV_NO_SUCH;
+ }
+
+ pPortCtrl->mcastCount[crcResult]--;
+ if(pPortCtrl->mcastCount[crcResult] != 0)
+ {
+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n",
+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult],
+ (unsigned)crcResult);
+ return MV_NO_CHANGE;
+ }
+ }
+ else
+ {
+ pPortCtrl->mcastCount[crcResult]++;
+ if(pPortCtrl->mcastCount[crcResult] > 1)
+ {
+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n",
+ pPortCtrl->portNo, (unsigned)crcResult);
+ return MV_NO_CHANGE;
+ }
+ }
+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue);
+ }
+ return MV_OK;
+}
+
+/*******************************************************************************
+* ethSetUcastTable - Unicast address settings.
+*
+* DESCRIPTION:
+* Set all entries in the Unicast MAC Table queue==-1 means reject all
+* INPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+static void ethSetUcastTable(int portNo, int queue)
+{
+ int offset;
+ MV_U32 regValue;
+
+ if(queue == -1)
+ {
+ regValue = 0;
+ }
+ else
+ {
+ regValue = (((0x01 | (queue<<1)) << 0) |
+ ((0x01 | (queue<<1)) << 8) |
+ ((0x01 | (queue<<1)) << 16) |
+ ((0x01 | (queue<<1)) << 24));
+ }
+
+ for (offset=0; offset<=0xC; offset+=4)
+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue);
+}
+
+/*******************************************************************************
+* mvEthSetSpecialMcastTable - Special Multicast address settings.
+*
+* DESCRIPTION:
+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all
+* INPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue)
+{
+ int offset;
+ MV_U32 regValue;
+
+ if(queue == -1)
+ {
+ regValue = 0;
+ }
+ else
+ {
+ regValue = (((0x01 | (queue<<1)) << 0) |
+ ((0x01 | (queue<<1)) << 8) |
+ ((0x01 | (queue<<1)) << 16) |
+ ((0x01 | (queue<<1)) << 24));
+ }
+
+ for (offset=0; offset<=0xFC; offset+=4)
+ {
+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) +
+ offset), regValue);
+ }
+}
+
+/*******************************************************************************
+* mvEthSetOtherMcastTable - Other Multicast address settings.
+*
+* DESCRIPTION:
+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all
+* INPUT:
+*
+* RETURN:
+*
+*******************************************************************************/
+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue)
+{
+ int offset;
+ MV_U32 regValue;
+
+ if(queue == -1)
+ {
+ regValue = 0;
+ }
+ else
+ {
+ regValue = (((0x01 | (queue<<1)) << 0) |
+ ((0x01 | (queue<<1)) << 8) |
+ ((0x01 | (queue<<1)) << 16) |
+ ((0x01 | (queue<<1)) << 24));
+ }
+
+ for (offset=0; offset<=0xFC; offset+=4)
+ {
+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) +
+ offset), regValue);
+ }
+}
+
+/*******************************************************************************
+* ethSetUcastAddr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+* This function locates the proper entry in the Unicast table for the
+* specified MAC nibble and sets its properties according to function
+* parameters.
+*
+* INPUT:
+* int ethPortNum - Port number.
+* MV_U8 lastNibble - Unicast MAC Address last nibble.
+* int queue - Rx queue number for this MAC address.
+* value "-1" means remove address
+*
+* OUTPUT:
+* This function add/removes MAC addresses from the port unicast address
+* table.
+*
+* RETURN:
+* MV_TRUE is output succeeded.
+* MV_FALSE if option parameter is invalid.
+*
+*******************************************************************************/
+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue)
+{
+ unsigned int unicastReg;
+ unsigned int tblOffset;
+ unsigned int regOffset;
+
+ /* Locate the Unicast table entry */
+ lastNibble = (0xf & lastNibble);
+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/
+ regOffset = lastNibble % 4; /* Entry offset within the above register */
+
+
+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) +
+ tblOffset));
+
+
+ if(queue == -1)
+ {
+ /* Clear accepts frame bit at specified unicast DA table entry */
+ unicastReg &= ~(0xFF << (8*regOffset));
+ }
+ else
+ {
+ unicastReg &= ~(0xFF << (8*regOffset));
+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset));
+ }
+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset),
+ unicastReg);
+
+ return MV_TRUE;
+}
+
+/*******************************************************************************
+* ethSetSpecialMcastAddr - Special Multicast address settings.
+*
+* DESCRIPTION:
+* This routine controls the MV device special MAC multicast support.
+* The Special Multicast Table for MAC addresses supports MAC of the form
+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+* Table entries in the DA-Filter table.
+* This function set the Special Multicast Table appropriate entry
+* according to the argument given.
+*
+* INPUT:
+* int ethPortNum Port number.
+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits).
+* int queue Rx queue number for this MAC address.
+* int option 0 = Add, 1 = remove address.
+*
+* OUTPUT:
+* See description.
+*
+* RETURN:
+* MV_TRUE is output succeeded.
+* MV_FALSE if option parameter is invalid.
+*
+*******************************************************************************/
+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue)
+{
+ unsigned int smcTableReg;
+ unsigned int tblOffset;
+ unsigned int regOffset;
+
+ /* Locate the SMC table entry */
+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */
+ regOffset = lastByte % 4; /* Entry offset within the above register */
+
+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4));
+
+ if(queue == -1)
+ {
+ /* Clear accepts frame bit at specified Special DA table entry */
+ smcTableReg &= ~(0xFF << (8 * regOffset));
+ }
+ else
+ {
+ smcTableReg &= ~(0xFF << (8 * regOffset));
+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset));
+ }
+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) +
+ tblOffset*4), smcTableReg);
+
+ return MV_TRUE;
+}
+
+/*******************************************************************************
+* ethSetOtherMcastAddr - Multicast address settings.
+*
+* DESCRIPTION:
+* This routine controls the MV device Other MAC multicast support.
+* The Other Multicast Table is used for multicast of another type.
+* A CRC-8bit is used as an index to the Other Multicast Table entries
+* in the DA-Filter table.
+* The function gets the CRC-8bit value from the calling routine and
+* set the Other Multicast Table appropriate entry according to the
+* CRC-8 argument given.
+*
+* INPUT:
+* int ethPortNum Port number.
+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+* int queue Rx queue number for this MAC address.
+*
+* OUTPUT:
+* See description.
+*
+* RETURN:
+* MV_TRUE is output succeeded.
+* MV_FALSE if option parameter is invalid.
+*
+*******************************************************************************/
+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue)
+{
+ unsigned int omcTableReg;
+ unsigned int tblOffset;
+ unsigned int regOffset;
+
+ /* Locate the OMC table entry */
+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */
+ regOffset = crc8 % 4; /* Entry offset within the above register */
+
+ omcTableReg = MV_REG_READ(
+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset));
+
+ if(queue == -1)
+ {
+ /* Clear accepts frame bit at specified Other DA table entry */
+ omcTableReg &= ~(0xFF << (8 * regOffset));
+ }
+ else
+ {
+ omcTableReg &= ~(0xFF << (8 * regOffset));
+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset));
+ }
+
+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset),
+ omcTableReg);
+
+ return MV_TRUE;
+}
+
+
+/******************************************************************************/
+/* MIB Counters functions */
+/******************************************************************************/
+
+
+/*******************************************************************************
+* mvEthMibCounterRead - Read a MIB counter
+*
+* DESCRIPTION:
+* This function reads a MIB counter of a specific ethernet port.
+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or
+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value,
+* so pHigh32 pointer should not be NULL in this case.
+*
+* INPUT:
+* int ethPortNum - Ethernet Port number.
+* unsigned int mibOffset - MIB counter offset.
+*
+* OUTPUT:
+* MV_U32* pHigh32 - pointer to place where 32 most significant bits
+* of the counter will be stored.
+*
+* RETURN:
+* 32 low sgnificant bits of MIB counter value.
+*
+*******************************************************************************/
+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset,
+ MV_U32* pHigh32)
+{
+ int portNo;
+ MV_U32 valLow32, valHigh32;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+
+ portNo = pPortCtrl->portNo;
+
+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset);
+
+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */
+ /* of a 64-bit MIB Counter. */
+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) ||
+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) )
+ {
+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4);
+ if(pHigh32 != NULL)
+ *pHigh32 = valHigh32;
+ }
+ return valLow32;
+}
+
+/*******************************************************************************
+* mvEthMibCountersClear - Clear all MIB counters
+*
+* DESCRIPTION:
+* This function clears all MIB counters
+*
+* INPUT:
+* int ethPortNum - Ethernet Port number.
+*
+*
+* RETURN: void
+*
+*******************************************************************************/
+void mvEthMibCountersClear(void* pPortHandle)
+{
+ int i, portNo;
+ unsigned int dummy;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+
+ portNo = pPortCtrl->portNo;
+
+ /* Perform dummy reads from MIB counters */
+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i<ETH_MIB_LATE_COLLISION; i+=4)
+ dummy = MV_REG_READ((ETH_MIB_COUNTERS_BASE(portNo) + i));
+}
+
+
+/******************************************************************************/
+/* RX Dispatching configuration routines */
+/******************************************************************************/
+
+int mvEthTosToRxqGet(void* pPortHandle, int tos)
+{
+ MV_U32 regValue;
+ int regIdx, regOffs, rxq;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+
+ if(tos > 0xFF)
+ {
+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos);
+ return -1;
+ }
+ regIdx = mvOsDivide(tos>>2, 10);
+ regOffs = mvOsReminder(tos>>2, 10);
+
+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) );
+ rxq = (regValue >> (regOffs*3));
+ rxq &= 0x7;
+
+ return rxq;
+}
+
+/*******************************************************************************
+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue
+*
+* DESCRIPTION:
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int tos - TOS value in the IP header of the packet
+* int rxq - RX Queue for packets with the configured TOS value
+* Negative value (-1) means no special processing for these packets,
+* so they will be processed as regular packets.
+*
+* RETURN: MV_STATUS
+*******************************************************************************/
+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq)
+{
+ MV_U32 regValue;
+ int regIdx, regOffs;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+
+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) )
+ {
+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq);
+ return MV_BAD_PARAM;
+ }
+ if(tos > 0xFF)
+ {
+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos);
+ return MV_BAD_PARAM;
+ }
+ regIdx = mvOsDivide(tos>>2, 10);
+ regOffs = mvOsReminder(tos>>2, 10);
+
+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) );
+ regValue &= ~(0x7 << (regOffs*3));
+ regValue |= (rxq << (regOffs*3));
+
+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue);
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with
+* special priority bits [0-2]
+*
+* DESCRIPTION:
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int bpduQueue - Special queue to capture VLAN tagged packets with special
+* priority.
+* Negative value (-1) means no special processing for these packets,
+* so they will be processed as regular packets.
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_FAIL - Failed.
+*
+*******************************************************************************/
+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ MV_U32 vlanPrioReg;
+
+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue);
+ return MV_BAD_PARAM;
+ }
+ if(vlanPrio >= 8)
+ {
+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio);
+ return MV_BAD_PARAM;
+ }
+
+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo));
+ vlanPrioReg &= ~(0x7 << (vlanPrio*3));
+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3));
+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets.
+*
+* DESCRIPTION:
+* This function defines processing of BPDU packets.
+* BPDU packets can be accepted and captured to one of RX queues
+* or can be processing as regular Multicast packets.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to
+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF,
+* except for the Flow-Control Pause packets).
+* Negative value (-1) means no special processing for BPDU,
+* packets so they will be processed as regular Multicast packets.
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_FAIL - Failed.
+*
+*******************************************************************************/
+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ MV_U32 portCfgReg;
+ MV_U32 portCfgExtReg;
+
+ if(bpduQueue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue);
+ return MV_BAD_PARAM;
+ }
+
+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo));
+
+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo));
+ if(bpduQueue >= 0)
+ {
+ pPortCtrl->portConfig.rxBpduQ = bpduQueue;
+
+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ);
+
+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg);
+
+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK;
+ }
+ else
+ {
+ pPortCtrl->portConfig.rxBpduQ = -1;
+ /* no special processing for BPDU packets */
+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK);
+ }
+
+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvEthArpRxQueue - Configure RX queue to capture ARP packets.
+*
+* DESCRIPTION:
+* This function defines processing of ARP (type=0x0806) packets.
+* ARP packets can be accepted and captured to one of RX queues
+* or can be processed as other Broadcast packets.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int arpQueue - Special queue to capture ARP packets (type=0x806).
+* Negative value (-1) means discard ARP packets
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_FAIL - Failed.
+*
+*******************************************************************************/
+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ MV_U32 portCfgReg;
+
+ if(arpQueue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue);
+ return MV_BAD_PARAM;
+ }
+
+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo));
+
+ if(arpQueue >= 0)
+ {
+ pPortCtrl->portConfig.rxArpQ = arpQueue;
+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ);
+
+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK);
+ }
+ else
+ {
+ pPortCtrl->portConfig.rxArpQ = -1;
+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK;
+ }
+
+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets.
+*
+* DESCRIPTION:
+* This function defines processing of TCP packets.
+* TCP packets can be accepted and captured to one of RX queues
+* or can be processed as regular Unicast packets.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int tcpQueue - Special queue to capture TCP packets. Value "-1"
+* means no special processing for TCP packets,
+* so they will be processed as regular
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_FAIL - Failed.
+*
+*******************************************************************************/
+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ MV_U32 portCfgReg;
+
+ if(tcpQueue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue);
+ return MV_BAD_PARAM;
+ }
+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo));
+
+ if(tcpQueue >= 0)
+ {
+ pPortCtrl->portConfig.rxTcpQ = tcpQueue;
+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ);
+
+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK;
+ }
+ else
+ {
+ pPortCtrl->portConfig.rxTcpQ = -1;
+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK);
+ }
+
+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets.
+*
+* DESCRIPTION:
+* This function defines processing of UDP packets.
+* TCP packets can be accepted and captured to one of RX queues
+* or can be processed as regular Unicast packets.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int udpQueue - Special queue to capture UDP packets. Value "-1"
+* means no special processing for UDP packets,
+* so they will be processed as regular
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_FAIL - Failed.
+*
+*******************************************************************************/
+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ MV_U32 portCfgReg;
+
+ if(udpQueue >= MV_ETH_RX_Q_NUM)
+ {
+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue);
+ return MV_BAD_PARAM;
+ }
+
+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo));
+
+ if(udpQueue >= 0)
+ {
+ pPortCtrl->portConfig.rxUdpQ = udpQueue;
+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK;
+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ);
+
+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK;
+ }
+ else
+ {
+ pPortCtrl->portConfig.rxUdpQ = -1;
+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK;
+ }
+
+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg);
+
+ return MV_OK;
+}
+
+
+/******************************************************************************/
+/* Speed, Duplex, FlowControl routines */
+/******************************************************************************/
+
+/*******************************************************************************
+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port.
+*
+* DESCRIPTION:
+* This function configure the port to work with desirable Duplex and Speed.
+* Changing of these parameters are allowed only when port is disabled.
+* This function disable the port if was enabled, change duplex and speed
+* and, enable the port back if needed.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* ETH_PORT_SPEED speed - Speed of the port.
+* ETH_PORT_SPEED duplex - Duplex of the port.
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_OUT_OF_RANGE - Failed. Port is out of valid range
+* MV_NOT_FOUND - Failed. Port is not initialized.
+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict.
+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex)
+* is not valid
+*
+*******************************************************************************/
+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed,
+ MV_ETH_PORT_DUPLEX duplex)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+ MV_U32 portSerialCtrlReg;
+
+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) )
+ return MV_OUT_OF_RANGE;
+
+ pPortCtrl = ethPortCtrl[port];
+ if(pPortCtrl == NULL)
+ return MV_NOT_FOUND;
+
+ /* Check validity */
+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) )
+ return MV_BAD_PARAM;
+
+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port));
+ /* Set Speed */
+ switch(speed)
+ {
+ case MV_ETH_SPEED_AN:
+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK;
+ break;
+
+ case MV_ETH_SPEED_10:
+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK;
+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK;
+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK;
+ break;
+
+ case MV_ETH_SPEED_100:
+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK;
+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK;
+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK;
+ break;
+
+ case MV_ETH_SPEED_1000:
+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK;
+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK;
+ break;
+
+ default:
+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed);
+ return MV_BAD_VALUE;
+ }
+ /* Set duplex */
+ switch(duplex)
+ {
+ case MV_ETH_DUPLEX_AN:
+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK;
+ break;
+
+ case MV_ETH_DUPLEX_HALF:
+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK;
+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK;
+ break;
+
+ case MV_ETH_DUPLEX_FULL:
+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK;
+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK;
+ break;
+
+ default:
+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex);
+ return MV_BAD_VALUE;
+ }
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthFlowCtrlSet - Set Flow Control of the port.
+*
+* DESCRIPTION:
+* This function configure the port to work with desirable Duplex and
+* Speed. Changing of these parameters are allowed only when port is
+* disabled. This function disable the port if was enabled, change
+* duplex and speed and, enable the port back if needed.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* MV_ETH_PORT_FC flowControl - Flow control of the port.
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_OUT_OF_RANGE - Failed. Port is out of valid range
+* MV_NOT_FOUND - Failed. Port is not initialized.
+* MV_BAD_VALUE - Value flowControl parameters is not valid
+*
+*******************************************************************************/
+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+ MV_U32 portSerialCtrlReg;
+
+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) )
+ return MV_OUT_OF_RANGE;
+
+ pPortCtrl = ethPortCtrl[port];
+ if(pPortCtrl == NULL)
+ return MV_NOT_FOUND;
+
+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port));
+ switch(flowControl)
+ {
+ case MV_ETH_FC_AN_ADV_DIS:
+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK;
+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK;
+ break;
+
+ case MV_ETH_FC_AN_ADV_SYM:
+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK;
+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK;
+ break;
+
+ case MV_ETH_FC_DISABLE:
+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK;
+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK;
+ break;
+
+ case MV_ETH_FC_ENABLE:
+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK;
+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK;
+ break;
+
+ default:
+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl);
+ return MV_BAD_VALUE;
+ }
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthHeaderModeSet - Set port header mode.
+*
+* DESCRIPTION:
+* This function configures the port to work in Marvell-Header mode.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in.
+*
+* RETURN: MV_STATUS
+* MV_OK - Success
+* MV_NOT_SUPPORTED- Feature not supported.
+* MV_OUT_OF_RANGE - Failed. Port is out of valid range
+* MV_NOT_FOUND - Failed. Port is not initialized.
+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid.
+*
+*******************************************************************************/
+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+ MV_U32 mvHeaderReg;
+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM;
+
+ if((port < 0) || (port >= mvCtrlEthMaxPortGet()))
+ return MV_OUT_OF_RANGE;
+
+ pPortCtrl = ethPortCtrl[port];
+ if(pPortCtrl == NULL)
+ return MV_NOT_FOUND;
+
+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port));
+ /* Disable header mode. */
+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK;
+
+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE)
+ {
+ /* Enable Header mode. */
+ mvHeaderReg |= ETH_MVHDR_EN_MASK;
+
+ /* Clear DA-Prefix & MHMask fields.*/
+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK);
+
+ if(numRxQ > 1)
+ {
+ switch (headerMode)
+ {
+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1):
+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2;
+ break;
+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM):
+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI;
+ break;
+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID):
+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI;
+ break;
+ default:
+ break;
+ }
+
+ switch (numRxQ)
+ {
+ case (4):
+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE;
+ break;
+ case (8):
+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg);
+
+ return MV_OK;
+}
+
+#if (MV_ETH_VERSION >= 4)
+/*******************************************************************************
+* mvEthEjpModeSet - Enable / Disable EJP policy for TX.
+*
+* DESCRIPTION:
+* This function
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* MV_BOOL TRUE - enable EJP mode
+* FALSE - disable EJP mode
+*
+* OUTPUT: MV_STATUS
+* MV_OK - Success
+* Other - Failure
+*
+* RETURN: None.
+*
+*******************************************************************************/
+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+
+ if((port < 0) || (port >= mvCtrlEthMaxPortGet()))
+ return MV_OUT_OF_RANGE;
+
+ pPortCtrl = ethPortCtrl[port];
+ if(pPortCtrl == NULL)
+ return MV_NOT_FOUND;
+
+ pPortCtrl->portConfig.ejpMode = mode;
+ if(mode)
+ {
+ /* EJP enabled */
+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK);
+ }
+ else
+ {
+ /* EJP disabled */
+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0);
+ }
+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n",
+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port),
+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port)));
+
+ return MV_OK;
+}
+#endif /* MV_ETH_VERSION >= 4 */
+
+/*******************************************************************************
+* mvEthStatusGet - Get major properties of the port .
+*
+* DESCRIPTION:
+* This function get major properties of the port (link, speed, duplex,
+* flowControl, etc) and return them using the single structure.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+*
+* OUTPUT:
+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status
+* will be placed.
+*
+* RETURN: None.
+*
+*******************************************************************************/
+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+
+ MV_U32 regValue;
+
+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) );
+
+ if(regValue & ETH_GMII_SPEED_1000_MASK)
+ pStatus->speed = MV_ETH_SPEED_1000;
+ else if(regValue & ETH_MII_SPEED_100_MASK)
+ pStatus->speed = MV_ETH_SPEED_100;
+ else
+ pStatus->speed = MV_ETH_SPEED_10;
+
+ if(regValue & ETH_LINK_UP_MASK)
+ pStatus->isLinkUp = MV_TRUE;
+ else
+ pStatus->isLinkUp = MV_FALSE;
+
+ if(regValue & ETH_FULL_DUPLEX_MASK)
+ pStatus->duplex = MV_ETH_DUPLEX_FULL;
+ else
+ pStatus->duplex = MV_ETH_DUPLEX_HALF;
+
+
+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK)
+ pStatus->flowControl = MV_ETH_FC_ENABLE;
+ else
+ pStatus->flowControl = MV_ETH_FC_DISABLE;
+}
+
+
+/******************************************************************************/
+/* PHY Control Functions */
+/******************************************************************************/
+
+
+/*******************************************************************************
+* mvEthPhyAddrSet - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+* This routine set the ethernet port PHY address according to given
+* parameter.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+* int phyAddr - PHY address
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+ unsigned int regData;
+
+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port));
+
+ regData &= ~ETH_PHY_ADDR_MASK;
+ regData |= phyAddr;
+
+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData);
+
+ return;
+}
+
+/*******************************************************************************
+* mvEthPhyAddrGet - Get the ethernet port PHY address.
+*
+* DESCRIPTION:
+* This routine returns the given ethernet port PHY address.
+*
+* INPUT:
+* void* pPortHandle - Pointer to port specific handler;
+*
+*
+* RETURN: int - PHY address.
+*
+*******************************************************************************/
+int mvEthPhyAddrGet(void* pPortHandle)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle;
+ int port = pPortCtrl->portNo;
+ unsigned int regData;
+
+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port));
+
+ return ((regData >> (5 * port)) & 0x1f);
+}
+
+/******************************************************************************/
+/* Descriptor handling Functions */
+/******************************************************************************/
+
+/*******************************************************************************
+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory.
+*
+* DESCRIPTION:
+* This function prepares a Rx chained list of descriptors and packet
+* buffers in a form of a ring. The routine must be called after port
+* initialization routine and before port start routine.
+* The Ethernet SDMA engine uses CPU bus addresses to access the various
+* devices in the system (i.e. DRAM). This function uses the ethernet
+* struct 'virtual to physical' routine (set by the user) to set the ring
+* with physical addresses.
+*
+* INPUT:
+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct.
+* int rxQueue Number of Rx queue.
+* int rxDescNum Number of Rx descriptors
+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr.
+*
+* OUTPUT:
+* The routine updates the Ethernet port control struct with information
+* regarding the Rx descriptors and buffers.
+*
+* RETURN: None
+*
+*******************************************************************************/
+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue)
+{
+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc;
+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum;
+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue];
+
+ /* Make sure descriptor address is cache line size aligned */
+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr,
+ CPU_D_CACHE_LINE_SIZE);
+
+ pRxDesc = (ETH_RX_DESC*)pRxDescBase;
+ pRxPrevDesc = pRxDesc;
+
+ /* initialize the Rx descriptors ring */
+ for (ix=0; ix<rxDescNum; ix++)
+ {
+ pRxDesc->bufSize = 0x0;
+ pRxDesc->byteCnt = 0x0;
+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST;
+ pRxDesc->bufPtr = 0x0;
+ pRxDesc->returnInfo = 0x0;
+ pRxPrevDesc = pRxDesc;
+ if(ix == (rxDescNum-1))
+ {
+ /* Closing Rx descriptors ring */
+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase);
+ }
+ else
+ {
+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE);
+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc);
+ }
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc);
+ }
+
+ pQueueCtrl->pCurrentDescr = pRxDescBase;
+ pQueueCtrl->pUsedDescr = pRxDescBase;
+
+ pQueueCtrl->pFirstDescr = pRxDescBase;
+ pQueueCtrl->pLastDescr = pRxDesc;
+ pQueueCtrl->resource = 0;
+}
+
+void ethResetRxDescRing(void* pPortHndl, int queue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue];
+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr;
+
+ pQueueCtrl->resource = 0;
+ if(pQueueCtrl->pFirstDescr != NULL)
+ {
+ while(MV_TRUE)
+ {
+ pRxDesc->bufSize = 0x0;
+ pRxDesc->byteCnt = 0x0;
+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST;
+ pRxDesc->bufPtr = 0x0;
+ pRxDesc->returnInfo = 0x0;
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc);
+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr)
+ break;
+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl);
+ }
+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr;
+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr;
+
+ /* Update RX Command register */
+ pPortCtrl->portRxQueueCmdReg |= (1 << queue);
+
+ /* update HW */
+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue),
+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) );
+ }
+ else
+ {
+ /* Update RX Command register */
+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue);
+
+ /* update HW */
+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0);
+ }
+}
+
+/*******************************************************************************
+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory.
+*
+* DESCRIPTION:
+* This function prepares a Tx chained list of descriptors and packet
+* buffers in a form of a ring. The routine must be called after port
+* initialization routine and before port start routine.
+* The Ethernet SDMA engine uses CPU bus addresses to access the various
+* devices in the system (i.e. DRAM). This function uses the ethernet
+* struct 'virtual to physical' routine (set by the user) to set the ring
+* with physical addresses.
+*
+* INPUT:
+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct.
+* int txQueue Number of Tx queue.
+* int txDescNum Number of Tx descriptors
+* int txBuffSize Size of Tx buffer
+* MV_U8* pTxDescBase Tx descriptors memory area base addr.
+*
+* OUTPUT:
+* The routine updates the Ethernet port control struct with information
+* regarding the Tx descriptors and buffers.
+*
+* RETURN: None.
+*
+*******************************************************************************/
+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue)
+{
+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc;
+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum;
+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue];
+
+ /* Make sure descriptor address is cache line size aligned */
+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr,
+ CPU_D_CACHE_LINE_SIZE);
+
+ pTxDesc = (ETH_TX_DESC*)pTxDescBase;
+ pTxPrevDesc = pTxDesc;
+
+ /* initialize the Tx descriptors ring */
+ for (ix=0; ix<txDescNum; ix++)
+ {
+ pTxDesc->byteCnt = 0x0000;
+ pTxDesc->L4iChk = 0x0000;
+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST;
+ pTxDesc->bufPtr = 0x0;
+ pTxDesc->returnInfo = 0x0;
+
+ pTxPrevDesc = pTxDesc;
+
+ if(ix == (txDescNum-1))
+ {
+ /* Closing Tx descriptors ring */
+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase);
+ }
+ else
+ {
+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE);
+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc);
+ }
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc);
+ }
+
+ pQueueCtrl->pCurrentDescr = pTxDescBase;
+ pQueueCtrl->pUsedDescr = pTxDescBase;
+
+ pQueueCtrl->pFirstDescr = pTxDescBase;
+ pQueueCtrl->pLastDescr = pTxDesc;
+ /* Leave one TX descriptor out of use */
+ pQueueCtrl->resource = txDescNum - 1;
+}
+
+void ethResetTxDescRing(void* pPortHndl, int queue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue];
+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr;
+
+ pQueueCtrl->resource = 0;
+ if(pQueueCtrl->pFirstDescr != NULL)
+ {
+ while(MV_TRUE)
+ {
+ pTxDesc->byteCnt = 0x0000;
+ pTxDesc->L4iChk = 0x0000;
+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST;
+ pTxDesc->bufPtr = 0x0;
+ pTxDesc->returnInfo = 0x0;
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc);
+ pQueueCtrl->resource++;
+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr)
+ break;
+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl);
+ }
+ /* Leave one TX descriptor out of use */
+ pQueueCtrl->resource--;
+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr;
+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr;
+
+ /* Update TX Command register */
+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue);
+ /* update HW */
+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue),
+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) );
+ }
+ else
+ {
+ /* Update TX Command register */
+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue));
+ /* update HW */
+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 );
+ }
+}
+
+/*******************************************************************************
+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors.
+*
+* DESCRIPTION:
+* This function allocates memory for RX and TX descriptors.
+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM.
+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM.
+*
+* INPUT:
+* int size - size of memory should be allocated.
+*
+* RETURN: None
+*
+*******************************************************************************/
+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize,
+ MV_ULONG* pPhysAddr, MV_U32 *memHandle)
+{
+ MV_U8* pVirt;
+
+#if defined(ETH_DESCR_IN_SRAM)
+ if(ethDescInSram == MV_TRUE)
+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr);
+ else
+#endif /* ETH_DESCR_IN_SRAM */
+ {
+#ifdef ETH_DESCR_UNCACHED
+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize,
+ pPhysAddr,memHandle);
+#else
+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize,
+ pPhysAddr, memHandle);
+#endif /* ETH_DESCR_UNCACHED */
+ }
+ memset(pVirt, 0, descSize);
+
+ return pVirt;
+}
+
+/*******************************************************************************
+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors.
+*
+* DESCRIPTION:
+* This function frees memory allocated for RX and TX descriptors.
+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function.
+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function.
+*
+* INPUT:
+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX
+* desriptors.
+*
+* RETURN: None
+*
+*******************************************************************************/
+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf)
+{
+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) )
+ return;
+
+#if defined(ETH_DESCR_IN_SRAM)
+ if( ethDescInSram )
+ {
+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr);
+ return;
+ }
+#endif /* ETH_DESCR_IN_SRAM */
+
+#ifdef ETH_DESCR_UNCACHED
+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr,
+ pDescBuf->bufVirtPtr,pDescBuf->memHandle);
+#else
+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr,
+ pDescBuf->bufVirtPtr,pDescBuf->memHandle);
+#endif /* ETH_DESCR_UNCACHED */
+}
+
+/******************************************************************************/
+/* Other Functions */
+/******************************************************************************/
+
+void mvEthPortPowerUp(int port)
+{
+ MV_U32 regVal;
+
+ /* MAC Cause register should be cleared */
+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0);
+
+ if (mvBoardIsPortInSgmii(port))
+ mvEthPortSgmiiConfig(port);
+
+ /* Cancel Port Reset */
+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port));
+ regVal &= (~ETH_PORT_RESET_MASK);
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal);
+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0);
+}
+
+void mvEthPortPowerDown(int port)
+{
+ MV_U32 regVal;
+
+ /* Port must be DISABLED */
+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port));
+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0)
+ {
+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n",
+ port, regVal);
+ return;
+ }
+
+ /* Port Reset (Read after write the register as a precaution) */
+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port));
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK);
+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0);
+}
+
+static void mvEthPortSgmiiConfig(int port)
+{
+ MV_U32 regVal;
+
+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port));
+
+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */);
+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK);
+
+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal);
+}
+
+
+
+
+
+
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c
new file mode 100644
index 000000000..f53347599
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c
@@ -0,0 +1,748 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvEthDebug.c - Source file for user friendly debug functions
+*
+* DESCRIPTION:
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+#include "mvOs.h"
+#include "mvCommon.h"
+#include "mvTypes.h"
+#include "mv802_3.h"
+#include "mvDebug.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "eth-phy/mvEthPhy.h"
+#include "eth/mvEth.h"
+#include "eth/gbe/mvEthDebug.h"
+
+/* #define mvOsPrintf printf */
+
+void mvEthPortShow(void* pHndl);
+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode);
+
+/******************************************************************************/
+/* Debug functions */
+/******************************************************************************/
+void ethRxCoal(int port, int usec)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthRxCoalSet(pHndl, usec);
+ }
+}
+
+void ethTxCoal(int port, int usec)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthTxCoalSet(pHndl, usec);
+ }
+}
+
+#if (MV_ETH_VERSION >= 4)
+void ethEjpModeSet(int port, int mode)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthEjpModeSet(pHndl, mode);
+ }
+}
+#endif /* (MV_ETH_VERSION >= 4) */
+
+void ethBpduRxQ(int port, int bpduQueue)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthBpduRxQueue(pHndl, bpduQueue);
+ }
+}
+
+void ethArpRxQ(int port, int arpQueue)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthArpRxQueue(pHndl, arpQueue);
+ }
+}
+
+void ethTcpRxQ(int port, int tcpQueue)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthTcpRxQueue(pHndl, tcpQueue);
+ }
+}
+
+void ethUdpRxQ(int port, int udpQueue)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthUdpRxQueue(pHndl, udpQueue);
+ }
+}
+
+void ethTxPolicyRegs(int port)
+{
+ int queue;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port);
+
+ if(pPortCtrl == NULL)
+ {
+ return;
+ }
+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ",
+ port, pPortCtrl->portConfig.ejpMode);
+ for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
+ {
+ if(pPortCtrl->txQueueConfig[queue].descrNum > 0)
+ mvOsPrintf("%d, ", queue);
+ }
+ mvOsPrintf("\n");
+
+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port);
+
+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
+ ETH_TX_QUEUE_COMMAND_REG(port),
+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) );
+
+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n",
+ ETH_TX_FIXED_PRIO_CFG_REG(port),
+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) );
+
+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n",
+ ETH_TX_TOKEN_RATE_CFG_REG(port),
+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) );
+
+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n",
+ ETH_MAX_TRANSMIT_UNIT_REG(port),
+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) );
+
+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n",
+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port),
+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) );
+
+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n",
+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port),
+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) );
+
+ for(queue=0; queue<MV_ETH_MAX_TXQ; queue++)
+ {
+ mvOsPrintf("\n\t TX policy Port #%d, Queue #%d configuration registers\n", port, queue);
+
+ mvOsPrintf("ETH_TXQ_TOKEN_COUNT_REG : 0x%X = 0x%08x\n",
+ ETH_TXQ_TOKEN_COUNT_REG(port, queue),
+ MV_REG_READ( ETH_TXQ_TOKEN_COUNT_REG(port, queue) ) );
+
+ mvOsPrintf("ETH_TXQ_TOKEN_CFG_REG : 0x%X = 0x%08x\n",
+ ETH_TXQ_TOKEN_CFG_REG(port, queue),
+ MV_REG_READ( ETH_TXQ_TOKEN_CFG_REG(port, queue) ) );
+
+ mvOsPrintf("ETH_TXQ_ARBITER_CFG_REG : 0x%X = 0x%08x\n",
+ ETH_TXQ_ARBITER_CFG_REG(port, queue),
+ MV_REG_READ( ETH_TXQ_ARBITER_CFG_REG(port, queue) ) );
+ }
+ mvOsPrintf("\n");
+}
+
+/* Print important registers of Ethernet port */
+void ethPortRegs(int port)
+{
+ mvOsPrintf("\n\t ethGiga #%d port Registers:\n", port);
+
+ mvOsPrintf("ETH_PORT_STATUS_REG : 0x%X = 0x%08x\n",
+ ETH_PORT_STATUS_REG(port),
+ MV_REG_READ( ETH_PORT_STATUS_REG(port) ) );
+
+ mvOsPrintf("ETH_PORT_SERIAL_CTRL_REG : 0x%X = 0x%08x\n",
+ ETH_PORT_SERIAL_CTRL_REG(port),
+ MV_REG_READ( ETH_PORT_SERIAL_CTRL_REG(port) ) );
+
+ mvOsPrintf("ETH_PORT_CONFIG_REG : 0x%X = 0x%08x\n",
+ ETH_PORT_CONFIG_REG(port),
+ MV_REG_READ( ETH_PORT_CONFIG_REG(port) ) );
+
+ mvOsPrintf("ETH_PORT_CONFIG_EXTEND_REG : 0x%X = 0x%08x\n",
+ ETH_PORT_CONFIG_EXTEND_REG(port),
+ MV_REG_READ( ETH_PORT_CONFIG_EXTEND_REG(port) ) );
+
+ mvOsPrintf("ETH_SDMA_CONFIG_REG : 0x%X = 0x%08x\n",
+ ETH_SDMA_CONFIG_REG(port),
+ MV_REG_READ( ETH_SDMA_CONFIG_REG(port) ) );
+
+ mvOsPrintf("ETH_TX_FIFO_URGENT_THRESH_REG : 0x%X = 0x%08x\n",
+ ETH_TX_FIFO_URGENT_THRESH_REG(port),
+ MV_REG_READ( ETH_TX_FIFO_URGENT_THRESH_REG(port) ) );
+
+ mvOsPrintf("ETH_RX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
+ ETH_RX_QUEUE_COMMAND_REG(port),
+ MV_REG_READ( ETH_RX_QUEUE_COMMAND_REG(port) ) );
+
+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
+ ETH_TX_QUEUE_COMMAND_REG(port),
+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) );
+
+ mvOsPrintf("ETH_INTR_CAUSE_REG : 0x%X = 0x%08x\n",
+ ETH_INTR_CAUSE_REG(port),
+ MV_REG_READ( ETH_INTR_CAUSE_REG(port) ) );
+
+ mvOsPrintf("ETH_INTR_EXTEND_CAUSE_REG : 0x%X = 0x%08x\n",
+ ETH_INTR_CAUSE_EXT_REG(port),
+ MV_REG_READ( ETH_INTR_CAUSE_EXT_REG(port) ) );
+
+ mvOsPrintf("ETH_INTR_MASK_REG : 0x%X = 0x%08x\n",
+ ETH_INTR_MASK_REG(port),
+ MV_REG_READ( ETH_INTR_MASK_REG(port) ) );
+
+ mvOsPrintf("ETH_INTR_EXTEND_MASK_REG : 0x%X = 0x%08x\n",
+ ETH_INTR_MASK_EXT_REG(port),
+ MV_REG_READ( ETH_INTR_MASK_EXT_REG(port) ) );
+
+ mvOsPrintf("ETH_RX_DESCR_STAT_CMD_REG : 0x%X = 0x%08x\n",
+ ETH_RX_DESCR_STAT_CMD_REG(port, 0),
+ MV_REG_READ( ETH_RX_DESCR_STAT_CMD_REG(port, 0) ) );
+
+ mvOsPrintf("ETH_RX_BYTE_COUNT_REG : 0x%X = 0x%08x\n",
+ ETH_RX_BYTE_COUNT_REG(port, 0),
+ MV_REG_READ( ETH_RX_BYTE_COUNT_REG(port, 0) ) );
+
+ mvOsPrintf("ETH_RX_BUF_PTR_REG : 0x%X = 0x%08x\n",
+ ETH_RX_BUF_PTR_REG(port, 0),
+ MV_REG_READ( ETH_RX_BUF_PTR_REG(port, 0) ) );
+
+ mvOsPrintf("ETH_RX_CUR_DESC_PTR_REG : 0x%X = 0x%08x\n",
+ ETH_RX_CUR_DESC_PTR_REG(port, 0),
+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, 0) ) );
+}
+
+
+/* Print Giga Ethernet UNIT registers */
+void ethRegs(int port)
+{
+ mvOsPrintf("ETH_PHY_ADDR_REG : 0x%X = 0x%08x\n",
+ ETH_PHY_ADDR_REG(port),
+ MV_REG_READ(ETH_PHY_ADDR_REG(port)) );
+
+ mvOsPrintf("ETH_UNIT_INTR_CAUSE_REG : 0x%X = 0x%08x\n",
+ ETH_UNIT_INTR_CAUSE_REG(port),
+ MV_REG_READ( ETH_UNIT_INTR_CAUSE_REG(port)) );
+
+ mvOsPrintf("ETH_UNIT_INTR_MASK_REG : 0x%X = 0x%08x\n",
+ ETH_UNIT_INTR_MASK_REG(port),
+ MV_REG_READ( ETH_UNIT_INTR_MASK_REG(port)) );
+
+ mvOsPrintf("ETH_UNIT_ERROR_ADDR_REG : 0x%X = 0x%08x\n",
+ ETH_UNIT_ERROR_ADDR_REG(port),
+ MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(port)) );
+
+ mvOsPrintf("ETH_UNIT_INT_ADDR_ERROR_REG : 0x%X = 0x%08x\n",
+ ETH_UNIT_INT_ADDR_ERROR_REG(port),
+ MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(port)) );
+
+}
+
+/******************************************************************************/
+/* MIB Counters functions */
+/******************************************************************************/
+
+/*******************************************************************************
+* ethClearMibCounters - Clear all MIB counters
+*
+* DESCRIPTION:
+* This function clears all MIB counters of a specific ethernet port.
+* A read from the MIB counter will reset the counter.
+*
+* INPUT:
+* int port - Ethernet Port number.
+*
+* RETURN: None
+*
+*******************************************************************************/
+void ethClearCounters(int port)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ mvEthMibCountersClear(pHndl);
+
+ return;
+}
+
+
+/* Print counters of the Ethernet port */
+void ethPortCounters(int port)
+{
+ MV_U32 regValue, regValHigh;
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl == NULL)
+ return;
+
+ mvOsPrintf("\n\t Port #%d MIB Counters\n\n", port);
+
+ mvOsPrintf("GoodFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_RECEIVED, NULL));
+ mvOsPrintf("BadFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FRAMES_RECEIVED, NULL));
+ mvOsPrintf("BroadcastFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_RECEIVED, NULL));
+ mvOsPrintf("MulticastFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_RECEIVED, NULL));
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW,
+ &regValHigh);
+ mvOsPrintf("GoodOctetsReceived = 0x%08x%08x\n",
+ regValHigh, regValue);
+
+ mvOsPrintf("\n");
+ mvOsPrintf("GoodFramesSent = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_SENT, NULL));
+ mvOsPrintf("BroadcastFramesSent = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_SENT, NULL));
+ mvOsPrintf("MulticastFramesSent = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_SENT, NULL));
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_SENT_LOW,
+ &regValHigh);
+ mvOsPrintf("GoodOctetsSent = 0x%08x%08x\n", regValHigh, regValue);
+
+
+ mvOsPrintf("\n\t FC Control Counters\n");
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNREC_MAC_CONTROL_RECEIVED, NULL);
+ mvOsPrintf("UnrecogMacControlReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FC_RECEIVED, NULL);
+ mvOsPrintf("GoodFCFramesReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FC_RECEIVED, NULL);
+ mvOsPrintf("BadFCFramesReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FC_SENT, NULL);
+ mvOsPrintf("FCFramesSent = %u\n", regValue);
+
+
+ mvOsPrintf("\n\t RX Errors\n");
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_OCTETS_RECEIVED, NULL);
+ mvOsPrintf("BadOctetsReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNDERSIZE_RECEIVED, NULL);
+ mvOsPrintf("UndersizeFramesReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FRAGMENTS_RECEIVED, NULL);
+ mvOsPrintf("FragmentsReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_OVERSIZE_RECEIVED, NULL);
+ mvOsPrintf("OversizeFramesReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_JABBER_RECEIVED, NULL);
+ mvOsPrintf("JabbersReceived = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_MAC_RECEIVE_ERROR, NULL);
+ mvOsPrintf("MacReceiveErrors = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_CRC_EVENT, NULL);
+ mvOsPrintf("BadCrcReceived = %u\n", regValue);
+
+ mvOsPrintf("\n\t TX Errors\n");
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR, NULL);
+ mvOsPrintf("TxMacErrors = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_EXCESSIVE_COLLISION, NULL);
+ mvOsPrintf("TxExcessiveCollisions = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_COLLISION, NULL);
+ mvOsPrintf("TxCollisions = %u\n", regValue);
+
+ regValue = mvEthMibCounterRead(pHndl, ETH_MIB_LATE_COLLISION, NULL);
+ mvOsPrintf("TxLateCollisions = %u\n", regValue);
+
+
+ mvOsPrintf("\n");
+ regValue = MV_REG_READ( ETH_RX_DISCARD_PKTS_CNTR_REG(port));
+ mvOsPrintf("Rx Discard packets counter = %u\n", regValue);
+
+ regValue = MV_REG_READ(ETH_RX_OVERRUN_PKTS_CNTR_REG(port));
+ mvOsPrintf("Rx Overrun packets counter = %u\n", regValue);
+}
+
+/* Print RMON counters of the Ethernet port */
+void ethPortRmonCounters(int port)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl == NULL)
+ return;
+
+ mvOsPrintf("\n\t Port #%d RMON MIB Counters\n\n", port);
+
+ mvOsPrintf("64 ByteFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_64_OCTETS, NULL));
+ mvOsPrintf("65...127 ByteFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_65_TO_127_OCTETS, NULL));
+ mvOsPrintf("128...255 ByteFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_128_TO_255_OCTETS, NULL));
+ mvOsPrintf("256...511 ByteFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_256_TO_511_OCTETS, NULL));
+ mvOsPrintf("512...1023 ByteFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_512_TO_1023_OCTETS, NULL));
+ mvOsPrintf("1024...Max ByteFramesReceived = %u\n",
+ mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_1024_TO_MAX_OCTETS, NULL));
+}
+
+/* Print port information */
+void ethPortStatus(int port)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthPortShow(pHndl);
+ }
+}
+
+/* Print port queues information */
+void ethPortQueues(int port, int rxQueue, int txQueue, int mode)
+{
+ void* pHndl;
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvEthQueuesShow(pHndl, rxQueue, txQueue, mode);
+ }
+}
+
+void ethUcastSet(int port, char* macStr, int queue)
+{
+ void* pHndl;
+ MV_U8 macAddr[MV_MAC_ADDR_SIZE];
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvMacStrToHex(macStr, macAddr);
+ mvEthMacAddrSet(pHndl, macAddr, queue);
+ }
+}
+
+
+void ethPortUcastShow(int port)
+{
+ MV_U32 unicastReg, macL, macH;
+ int i, j;
+
+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(port));
+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(port));
+
+ mvOsPrintf("\n\t Port #%d Unicast MAC table: %02x:%02x:%02x:%02x:%02x:%02x\n\n",
+ port, ((macH >> 24) & 0xff), ((macH >> 16) & 0xff),
+ ((macH >> 8) & 0xff), (macH & 0xff),
+ ((macL >> 8) & 0xff), (macL & 0xff) );
+
+ for (i=0; i<4; i++)
+ {
+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4));
+ for(j=0; j<4; j++)
+ {
+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF;
+
+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j,
+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7);
+ }
+ }
+}
+
+void ethMcastAdd(int port, char* macStr, int queue)
+{
+ void* pHndl;
+ MV_U8 macAddr[MV_MAC_ADDR_SIZE];
+
+ pHndl = mvEthPortHndlGet(port);
+ if(pHndl != NULL)
+ {
+ mvMacStrToHex(macStr, macAddr);
+ mvEthMcastAddrSet(pHndl, macAddr, queue);
+ }
+}
+
+void ethPortMcast(int port)
+{
+ int tblIdx, regIdx;
+ MV_U32 regVal;
+
+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n",
+ port);
+
+ for(tblIdx=0; tblIdx<(256/4); tblIdx++)
+ {
+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4));
+ for(regIdx=0; regIdx<4; regIdx++)
+ {
+ if((regVal & (0x01 << (regIdx*8))) != 0)
+ {
+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n",
+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07));
+ }
+ }
+ }
+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port);
+ for(tblIdx=0; tblIdx<(256/4); tblIdx++)
+ {
+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4));
+ for(regIdx=0; regIdx<4; regIdx++)
+ {
+ if((regVal & (0x01 << (regIdx*8))) != 0)
+ {
+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n",
+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07));
+ }
+ }
+ }
+}
+
+
+/* Print status of Ethernet port */
+void mvEthPortShow(void* pHndl)
+{
+ MV_U32 regValue, rxCoal, txCoal;
+ int speed, queue, port;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl;
+
+ port = pPortCtrl->portNo;
+
+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) );
+
+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n",
+ port, ETH_PORT_STATUS_REG(port), regValue);
+
+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n",
+ ethDescInSram, ethDescSwCoher);
+
+ if(regValue & ETH_GMII_SPEED_1000_MASK)
+ speed = 1000;
+ else if(regValue & ETH_MII_SPEED_100_MASK)
+ speed = 100;
+ else
+ speed = 10;
+
+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal);
+
+ /* Link, Speed, Duplex, FlowControl */
+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s",
+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN",
+ speed,
+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF",
+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE");
+
+ mvOsPrintf("\n");
+
+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n",
+ rxCoal, txCoal);
+
+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n",
+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ,
+ pPortCtrl->portConfig.rxBpduQ,
+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ);
+
+ /* Print all RX and TX queues */
+ for(queue=0; queue<MV_ETH_RX_Q_NUM; queue++)
+ {
+ mvOsPrintf("RX Queue #%d: base=0x%lx, free=%d\n",
+ queue, (MV_ULONG)pPortCtrl->rxQueue[queue].pFirstDescr,
+ mvEthRxResourceGet(pPortCtrl, queue) );
+ }
+ mvOsPrintf("\n");
+ for(queue=0; queue<MV_ETH_TX_Q_NUM; queue++)
+ {
+ mvOsPrintf("TX Queue #%d: base=0x%lx, free=%d\n",
+ queue, (MV_ULONG)pPortCtrl->txQueue[queue].pFirstDescr,
+ mvEthTxResourceGet(pPortCtrl, queue) );
+ }
+}
+
+/* Print RX and TX queue of the Ethernet port */
+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode)
+{
+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl;
+ ETH_QUEUE_CTRL *pQueueCtrl;
+ MV_U32 regValue;
+ ETH_RX_DESC *pRxDescr;
+ ETH_TX_DESC *pTxDescr;
+ int i, port = pPortCtrl->portNo;
+
+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) )
+ {
+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]);
+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue);
+
+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n",
+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue),
+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue)));
+
+
+ if(pQueueCtrl->pFirstDescr != NULL)
+ {
+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n",
+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr,
+ pQueueCtrl->resource);
+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n",
+ (MV_ULONG)pQueueCtrl->pCurrentDescr,
+ (MV_ULONG)pQueueCtrl->pUsedDescr);
+
+ if(mode == 1)
+ {
+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr;
+ i = 0;
+ do
+ {
+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n",
+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr),
+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize,
+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo,
+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo);
+
+ ETH_DESCR_INV(pPortCtrl, pRxDescr);
+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl);
+ i++;
+ } while (pRxDescr != pQueueCtrl->pFirstDescr);
+ }
+ }
+ else
+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue);
+ }
+
+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) )
+ {
+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]);
+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue);
+
+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue));
+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n",
+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue);
+
+ if(pQueueCtrl->pFirstDescr != NULL)
+ {
+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n",
+ (MV_ULONG)pQueueCtrl->pFirstDescr,
+ (MV_ULONG)pQueueCtrl->pLastDescr,
+ pQueueCtrl->resource);
+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n",
+ (MV_ULONG)pQueueCtrl->pCurrentDescr,
+ (MV_ULONG)pQueueCtrl->pUsedDescr);
+
+ if(mode == 1)
+ {
+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr;
+ i = 0;
+ do
+ {
+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n",
+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr),
+ pTxDescr->cmdSts, pTxDescr->byteCnt,
+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo,
+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0);
+
+ ETH_DESCR_INV(pPortCtrl, pTxDescr);
+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl);
+ i++;
+ } while (pTxDescr != pQueueCtrl->pFirstDescr);
+ }
+ }
+ else
+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue);
+ }
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h
new file mode 100644
index 000000000..f026f966d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h
@@ -0,0 +1,146 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __MV_ETH_DEBUG_H__
+#define __MV_ETH_DEBUG_H__
+
+#if 0
+/*
+ ** Externs
+ */
+void ethBpduRxQ(int port, int bpduQueue);
+void ethArpRxQ(int port, int bpduQueue);
+void ethTcpRxQ(int port, int bpduQueue);
+void ethUdpRxQ(int port, int bpduQueue);
+void ethMcastAdd(int port, char* macStr, int queue);
+
+#ifdef INCLUDE_MULTI_QUEUE
+void ethRxPolicy( int port);
+void ethTxPolicy( int port);
+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr);
+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode);
+void ethRxPolQ(int port, int rxQueue, int rxQuota);
+#endif /* INCLUDE_MULTI_QUEUE */
+
+void print_egiga_stat(void *sc, unsigned int port);
+void ethPortStatus (int port);
+void ethPortQueues( int port, int rxQueue, int txQueue, int mode);
+void ethPortMcast(int port);
+void ethPortRegs(int port);
+void ethPortCounters(int port);
+void ethPortRmonCounters(int port);
+void ethRxCoal(int port, int usec);
+void ethTxCoal(int port, int usec);
+
+void ethRegs(int port);
+void ethClearCounters(int port);
+void ethUcastSet(int port, char* macStr, int queue);
+void ethPortUcastShow(int port);
+
+#ifdef CONFIG_MV_ETH_HEADER
+void run_com_header(const char *buffer);
+#endif
+
+#ifdef INCLUDE_MULTI_QUEUE
+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode);
+void ethRxPolQ(int port, int queue, int quota);
+void ethRxPolicy(int port);
+void ethTxPolDef(int port, int txQ, char* headerHexStr);
+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr);
+void ethTxPolicy(int port);
+#endif /* INCLUDE_MULTI_QUEUE */
+
+#if (MV_ETH_VERSION >= 4)
+void ethEjpModeSet(int port, int mode)
+#endif
+#endif /* 0 */
+
+
+
+
+void ethRxCoal(int port, int usec);
+void ethTxCoal(int port, int usec);
+#if (MV_ETH_VERSION >= 4)
+void ethEjpModeSet(int port, int mode);
+#endif /* (MV_ETH_VERSION >= 4) */
+
+void ethBpduRxQ(int port, int bpduQueue);
+void ethArpRxQ(int port, int arpQueue);
+void ethTcpRxQ(int port, int tcpQueue);
+void ethUdpRxQ(int port, int udpQueue);
+void ethTxPolicyRegs(int port);
+void ethPortRegs(int port);
+void ethRegs(int port);
+void ethClearCounters(int port);
+void ethPortCounters(int port);
+void ethPortRmonCounters(int port);
+void ethPortStatus(int port);
+void ethPortQueues(int port, int rxQueue, int txQueue, int mode);
+void ethUcastSet(int port, char* macStr, int queue);
+void ethPortUcastShow(int port);
+void ethMcastAdd(int port, char* macStr, int queue);
+void ethPortMcast(int port);
+void mvEthPortShow(void* pHndl);
+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode);
+
+#endif
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h
new file mode 100644
index 000000000..f4cae5078
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h
@@ -0,0 +1,751 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller
+*
+* DESCRIPTION:
+* This header file contains macros typedefs and function declaration specific to
+* the Marvell Gigabit Ethernet Controller.
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+#ifndef __mvEthGbe_h__
+#define __mvEthGbe_h__
+
+extern MV_BOOL ethDescInSram;
+extern MV_BOOL ethDescSwCoher;
+extern ETH_PORT_CTRL* ethPortCtrl[];
+
+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc)
+{
+#if defined (ETH_DESCR_IN_SRAM)
+ if( ethDescInSram )
+ return mvSramVirtToPhy(pDesc);
+ else
+#endif /* ETH_DESCR_IN_SRAM */
+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr));
+}
+/* Return port handler */
+#define mvEthPortHndlGet(port) ethPortCtrl[port]
+
+/* Used as WA for HW/SW race on TX */
+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep)
+{
+ int deep = 0;
+ MV_U32 txCurrReg, txEnReg;
+ ETH_TX_DESC* pTxLastDesc;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo));
+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0)
+ {
+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg;
+ return 0;
+ }
+
+ pQueueCtrl = &pPortCtrl->txQueue[queue];
+ pTxLastDesc = pQueueCtrl->pCurrentDescr;
+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue));
+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg)
+ {
+ /* All descriptors are processed, no chance for race */
+ return 0;
+ }
+
+ /* Check distance betwee HW and SW location: */
+ /* If distance between HW and SW pointers is less than max_deep descriptors */
+ /* Race condition is possible, so wait end of TX and restart TXQ */
+ while(deep < max_deep)
+ {
+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl);
+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg)
+ {
+ int count = 0;
+
+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0)
+ {
+ count++;
+ if(count > 10000)
+ {
+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n",
+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) );
+ break;
+ }
+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo));
+ }
+
+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg;
+ return count;
+ }
+ deep++;
+ }
+ /* Distance between HW and SW pointers is more than max_deep descriptors, */
+ /* So NO race condition - do nothing */
+ return -1;
+}
+
+
+/* defines */
+#define ETH_CSUM_MIN_BYTE_COUNT 72
+
+/* Tailgate and Kirwood have only 2K TX FIFO */
+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4)
+#define ETH_CSUM_MAX_BYTE_COUNT 1600
+#else
+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024
+#endif /* MV_ETH_VERSION */
+
+#define ETH_MV_HEADER_SIZE 2
+#define ETH_MV_TX_EN
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define MIN_TX_BUFF_LOAD 8
+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD)
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE \
+ ETH_DEF_RX_QUEUE_MASK(0) | \
+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \
+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \
+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \
+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \
+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE 0
+
+#define PORT_SERIAL_CONTROL_VALUE \
+ ETH_DISABLE_FC_AUTO_NEG_MASK | \
+ BIT9 | \
+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \
+ ETH_MAX_RX_PACKET_1552BYTE | \
+ ETH_SET_FULL_DUPLEX_MASK
+
+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \
+ ETH_FORCE_LINK_PASS_MASK | \
+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \
+ ETH_DISABLE_FC_AUTO_NEG_MASK | \
+ BIT9 | \
+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \
+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \
+ ETH_SET_FULL_DUPLEX_MASK | \
+ ETH_SET_MII_SPEED_100_MASK | \
+ ETH_MAX_RX_PACKET_1552BYTE
+
+
+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \
+ ETH_FORCE_LINK_PASS_MASK | \
+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \
+ ETH_DISABLE_FC_AUTO_NEG_MASK | \
+ BIT9 | \
+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \
+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \
+ ETH_SET_FULL_DUPLEX_MASK | \
+ ETH_SET_GMII_SPEED_1000_MASK | \
+ ETH_MAX_RX_PACKET_1552BYTE
+
+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \
+ ETH_DISABLE_FC_AUTO_NEG_MASK | \
+ BIT9 | \
+ ETH_IN_BAND_AN_EN_MASK | \
+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \
+ ETH_MAX_RX_PACKET_1552BYTE
+
+/* Function headers: */
+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue);
+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue);
+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue);
+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue);
+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr);
+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue);
+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode);
+/* Interrupt Coalesting functions */
+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec);
+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec);
+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal);
+
+/******************************************************************************/
+/* Data Flow functions */
+/******************************************************************************/
+static INLINE void mvEthPortTxRestart(void* pPortHndl)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg;
+}
+
+/* Get number of Free resources in specific TX queue */
+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ return (pPortCtrl->txQueue[txQueue].resource);
+}
+
+/* Get number of Free resources in specific RX queue */
+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ return (pPortCtrl->rxQueue[rxQueue].resource);
+}
+
+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ if(pPortCtrl->txQueue[txQueue].resource == 0)
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+
+/* Get number of Free resources in specific RX queue */
+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue];
+
+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) &&
+ (pQueueCtrl->resource != 0) )
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+
+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue];
+
+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) &&
+ (pQueueCtrl->resource != 0) )
+ {
+ return MV_TRUE;
+ }
+ return MV_FALSE;
+}
+
+/* Get number of Free resources in specific RX queue */
+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue)
+{
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl;
+
+ if(pPortCtrl->rxQueue[rxQueue].resource == 0)
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+
+/*******************************************************************************
+* mvEthPortTx - Send an Ethernet packet
+*
+* DESCRIPTION:
+* This routine send a given packet described by pPktInfo parameter.
+* Single buffer only.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int txQueue - Number of Tx queue.
+* MV_PKT_INFO *pPktInfo - User packet to send.
+*
+* RETURN:
+* MV_NO_RESOURCE - No enough resources to send this packet.
+* MV_ERROR - Unexpected Fatal error.
+* MV_OK - Packet send successfully.
+*
+*******************************************************************************/
+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo)
+{
+ ETH_TX_DESC* pTxCurrDesc;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ int portNo;
+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags;
+
+#ifdef ETH_DEBUG
+ if(pPortCtrl->portState != MV_ACTIVE)
+ return MV_BAD_STATE;
+#endif /* ETH_DEBUG */
+
+ portNo = pPortCtrl->portNo;
+ pQueueCtrl = &pPortCtrl->txQueue[txQueue];
+
+ /* Get the Tx Desc ring indexes */
+ pTxCurrDesc = pQueueCtrl->pCurrentDescr;
+
+ /* Check if there is enough resources to send the packet */
+ if(pQueueCtrl->resource == 0)
+ return MV_NO_RESOURCE;
+
+ pTxCurrDesc->byteCnt = pBufInfo->dataSize;
+
+ /* Flash Buffer */
+ if(pPktInfo->pktSize != 0)
+ {
+#ifdef MV_NETBSD
+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr;
+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize);
+#else
+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize);
+#endif
+ pPktInfo->pktSize = 0;
+ }
+ else
+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr;
+
+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo;
+
+ /* There is only one buffer in the packet */
+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */
+ pTxCurrDesc->cmdSts = pPktInfo->status |
+ ETH_BUFFER_OWNED_BY_DMA |
+ ETH_TX_GENERATE_CRC_MASK |
+ ETH_TX_ENABLE_INTERRUPT_MASK |
+ ETH_TX_ZERO_PADDING_MASK |
+ ETH_TX_FIRST_DESC_MASK |
+ ETH_TX_LAST_DESC_MASK;
+
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc);
+
+ pQueueCtrl->resource--;
+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl);
+
+ /* Apply send command */
+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg;
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvEthPortSgTx - Send an Ethernet packet
+*
+* DESCRIPTION:
+* This routine send a given packet described by pBufInfo parameter. It
+* supports transmitting of a packet spaned over multiple buffers.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int txQueue - Number of Tx queue.
+* MV_PKT_INFO *pPktInfo - User packet to send.
+*
+* RETURN:
+* MV_NO_RESOURCE - No enough resources to send this packet.
+* MV_ERROR - Unexpected Fatal error.
+* MV_OK - Packet send successfully.
+*
+*******************************************************************************/
+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo)
+{
+ ETH_TX_DESC* pTxFirstDesc;
+ ETH_TX_DESC* pTxCurrDesc;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ int portNo, bufCount;
+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags;
+ MV_U8* pTxBuf;
+
+#ifdef ETH_DEBUG
+ if(pPortCtrl->portState != MV_ACTIVE)
+ return MV_BAD_STATE;
+#endif /* ETH_DEBUG */
+
+ portNo = pPortCtrl->portNo;
+ pQueueCtrl = &pPortCtrl->txQueue[txQueue];
+
+ /* Get the Tx Desc ring indexes */
+ pTxCurrDesc = pQueueCtrl->pCurrentDescr;
+
+ /* Check if there is enough resources to send the packet */
+ if(pQueueCtrl->resource < pPktInfo->numFrags)
+ return MV_NO_RESOURCE;
+
+ /* Remember first desc */
+ pTxFirstDesc = pTxCurrDesc;
+
+ bufCount = 0;
+ while(MV_TRUE)
+ {
+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD)
+ {
+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */
+ /* to 64-bit boundary. Two options here: */
+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */
+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */
+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */
+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC;
+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize);
+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf);
+ }
+ else
+ {
+ /* Flash Buffer */
+#ifdef MV_NETBSD
+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr;
+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize);
+#else
+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize);
+#endif
+ }
+
+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize;
+ bufCount++;
+
+ if(bufCount >= pPktInfo->numFrags)
+ break;
+
+ if(bufCount > 1)
+ {
+ /* There is middle buffer of the packet Not First and Not Last */
+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA;
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc);
+ }
+ /* Go to next descriptor and next buffer */
+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl);
+ }
+ /* Set last desc with DMA ownership and interrupt enable. */
+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo;
+ if(bufCount == 1)
+ {
+ /* There is only one buffer in the packet */
+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */
+ pTxCurrDesc->cmdSts = pPktInfo->status |
+ ETH_BUFFER_OWNED_BY_DMA |
+ ETH_TX_GENERATE_CRC_MASK |
+ ETH_TX_ENABLE_INTERRUPT_MASK |
+ ETH_TX_ZERO_PADDING_MASK |
+ ETH_TX_FIRST_DESC_MASK |
+ ETH_TX_LAST_DESC_MASK;
+
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc);
+ }
+ else
+ {
+ /* Last but not First */
+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA |
+ ETH_TX_ENABLE_INTERRUPT_MASK |
+ ETH_TX_ZERO_PADDING_MASK |
+ ETH_TX_LAST_DESC_MASK;
+
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc);
+
+ /* Update First when more than one buffer in the packet */
+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */
+ pTxFirstDesc->cmdSts = pPktInfo->status |
+ ETH_BUFFER_OWNED_BY_DMA |
+ ETH_TX_GENERATE_CRC_MASK |
+ ETH_TX_FIRST_DESC_MASK;
+
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc);
+ }
+ /* Update txQueue state */
+ pQueueCtrl->resource -= bufCount;
+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl);
+
+ /* Apply send command */
+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvEthPortTxDone - Free all used Tx descriptors and mBlks.
+*
+* DESCRIPTION:
+* This routine returns the transmitted packet information to the caller.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int txQueue - Number of Tx queue.
+*
+* OUTPUT:
+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent.
+*
+* RETURN:
+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress.
+* MV_EMPTY - No transmitted packets to return. TX Queue is empty.
+* MV_ERROR - Unexpected Fatal error.
+* MV_OK - There is transmitted packet in the queue,
+* 'pPktInfo' filled with relevant information.
+*
+*******************************************************************************/
+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue)
+{
+ ETH_TX_DESC* pTxCurrDesc;
+ ETH_TX_DESC* pTxUsedDesc;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ MV_PKT_INFO* pPktInfo;
+ MV_U32 commandStatus;
+
+ pQueueCtrl = &pPortCtrl->txQueue[txQueue];
+
+ pTxUsedDesc = pQueueCtrl->pUsedDescr;
+ pTxCurrDesc = pQueueCtrl->pCurrentDescr;
+
+ while(MV_TRUE)
+ {
+ /* No more used descriptors */
+ commandStatus = pTxUsedDesc->cmdSts;
+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA))
+ {
+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc);
+ return NULL;
+ }
+ if( (pTxUsedDesc == pTxCurrDesc) &&
+ (pQueueCtrl->resource != 0) )
+ {
+ return NULL;
+ }
+ pQueueCtrl->resource++;
+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl);
+ if(commandStatus & (ETH_TX_LAST_DESC_MASK))
+ {
+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo;
+ pPktInfo->status = commandStatus;
+ return pPktInfo;
+ }
+ pTxUsedDesc = pQueueCtrl->pUsedDescr;
+ }
+}
+
+/*******************************************************************************
+* mvEthPortRx - Get new received packets from Rx queue.
+*
+* DESCRIPTION:
+* This routine returns the received data to the caller. There is no
+* data copying during routine operation. All information is returned
+* using pointer to packet information struct passed from the caller.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int rxQueue - Number of Rx queue.
+*
+* OUTPUT:
+* MV_PKT_INFO *pPktInfo - Pointer to received packet.
+*
+* RETURN:
+* MV_NO_RESOURCE - No free resources in RX queue.
+* MV_ERROR - Unexpected Fatal error.
+* MV_OK - New packet received and 'pBufInfo' structure filled
+* with relevant information.
+*
+*******************************************************************************/
+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue)
+{
+ ETH_RX_DESC *pRxCurrDesc;
+ MV_U32 commandStatus;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ MV_PKT_INFO* pPktInfo;
+
+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]);
+
+ /* Check resources */
+ if(pQueueCtrl->resource == 0)
+ {
+ mvOsPrintf("ethPortRx: no more resources\n");
+ return NULL;
+ }
+ while(MV_TRUE)
+ {
+ /* Get the Rx Desc ring 'curr and 'used' indexes */
+ pRxCurrDesc = pQueueCtrl->pCurrentDescr;
+
+ commandStatus = pRxCurrDesc->cmdSts;
+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA))
+ {
+ /* Nothing to receive... */
+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc);
+ return NULL;
+ }
+
+ /* Valid RX only if FIRST and LAST bits are set */
+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) ==
+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) )
+ {
+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo;
+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4;
+ pPktInfo->status = commandStatus;
+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK;
+
+ pQueueCtrl->resource--;
+ /* Update 'curr' in data structure */
+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl);
+
+#ifdef INCLUDE_SYNC_BARR
+ mvCpuIfSyncBarr(DRAM_TARGET);
+#endif
+ return pPktInfo;
+ }
+ else
+ {
+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr;
+
+#ifdef ETH_DEBUG
+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: "
+ "status=0x%08x, byteCnt=%d, pData=0x%x\n",
+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr);
+#endif /* ETH_DEBUG */
+
+ /* move buffer from pCurrentDescr position to pUsedDescr position */
+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr;
+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo;
+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK;
+
+ /* Return the descriptor to DMA ownership */
+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA |
+ ETH_RX_ENABLE_INTERRUPT_MASK;
+
+ /* Flush descriptor and CPU pipe */
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc);
+
+ /* Move the used descriptor pointer to the next descriptor */
+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl);
+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl);
+ }
+ }
+}
+
+/*******************************************************************************
+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring.
+*
+* DESCRIPTION:
+* This routine returns a Rx buffer back to the Rx ring.
+*
+* INPUT:
+* void* pEthPortHndl - Ethernet Port handler.
+* int rxQueue - Number of Rx queue.
+* MV_PKT_INFO *pPktInfo - Pointer to received packet.
+*
+* RETURN:
+* MV_ERROR - Unexpected Fatal error.
+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be
+* returned to this queue.
+* MV_FULL - Buffer returned successfully and RX queue became full.
+* More buffers should not be returned at the time.
+* MV_OK - Buffer returned successfully and there are more free
+* places in the queue.
+*
+*******************************************************************************/
+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo)
+{
+ ETH_RX_DESC* pRxUsedDesc;
+ ETH_QUEUE_CTRL* pQueueCtrl;
+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl;
+
+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue];
+
+ /* Get 'used' Rx descriptor */
+ pRxUsedDesc = pQueueCtrl->pUsedDescr;
+
+ /* Check that ring is not FULL */
+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) &&
+ (pQueueCtrl->resource != 0) )
+ {
+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n",
+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource,
+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr);
+ return MV_OUT_OF_RANGE;
+ }
+
+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr;
+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo;
+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK;
+
+ /* Invalidate data buffer accordingly with pktSize */
+ if(pPktInfo->pktSize != 0)
+ {
+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize);
+ pPktInfo->pktSize = 0;
+ }
+
+ /* Return the descriptor to DMA ownership */
+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK;
+
+ /* Flush descriptor and CPU pipe */
+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc);
+
+ pQueueCtrl->resource++;
+
+ /* Move the used descriptor pointer to the next descriptor */
+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl);
+
+ /* If ring became Full return MV_FULL */
+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr)
+ return MV_FULL;
+
+ return MV_OK;
+}
+
+
+#endif /* __mvEthGbe_h__ */
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h
new file mode 100644
index 000000000..7b9f0520f
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h
@@ -0,0 +1,700 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCmvEthRegsh
+#define __INCmvEthRegsh
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+
+/****************************************/
+/* Ethernet Unit Registers */
+/****************************************/
+#define ETH_REG_BASE MV_ETH_REG_BASE
+
+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000)
+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004)
+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008)
+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c)
+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014)
+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080)
+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084)
+
+
+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094)
+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098)
+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0)
+
+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400)
+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404)
+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408)
+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c)
+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410)
+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414)
+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418)
+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c)
+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2))
+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c)
+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440)
+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444)
+
+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680)
+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448)
+
+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c)
+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450)
+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454)
+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458)
+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c)
+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460)
+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464)
+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468)
+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c)
+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474)
+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c)
+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484)
+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488)
+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494)
+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc)
+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0)
+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4)
+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8)
+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec)
+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780)
+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4))
+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4))
+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4))
+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4))
+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2))
+
+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4))
+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4))
+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4))
+
+#if (MV_ETH_VERSION >= 4)
+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4)
+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8)
+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8)
+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0)
+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4)
+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8)
+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0)
+#endif /* MV_ETH_VERSION >= 4 */
+
+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000)
+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400)
+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500)
+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600)
+
+/* Phy address register definitions */
+#define ETH_PHY_ADDR_OFFS 0
+#define ETH_PHY_ADDR_MASK (0x1f <<ETH_PHY_ADDR_OFFS)
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
+#define ETH_MIB_FRAMES_64_OCTETS 0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT 0x40
+#define ETH_MIB_EXCESSIVE_COLLISION 0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT 0x54
+#define ETH_MIB_GOOD_FC_RECEIVED 0x58
+#define ETH_MIB_BAD_FC_RECEIVED 0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
+#define ETH_MIB_OVERSIZE_RECEIVED 0x68
+#define ETH_MIB_JABBER_RECEIVED 0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
+#define ETH_MIB_BAD_CRC_EVENT 0x74
+#define ETH_MIB_COLLISION 0x78
+#define ETH_MIB_LATE_COLLISION 0x7c
+
+
+/****************************************/
+/* Ethernet Unit Register BITs */
+/****************************************/
+
+#define ETH_RXQ_ENABLE_OFFSET 0
+#define ETH_RXQ_ENABLE_MASK (0x000000FF << ETH_RXQ_ENABLE_OFFSET)
+
+#define ETH_RXQ_DISABLE_OFFSET 8
+#define ETH_RXQ_DISABLE_MASK (0x000000FF << ETH_RXQ_DISABLE_OFFSET)
+
+/***** BITs of Transmit Queue Command (TQC) register *****/
+#define ETH_TXQ_ENABLE_OFFSET 0
+#define ETH_TXQ_ENABLE_MASK (0x000000FF << ETH_TXQ_ENABLE_OFFSET)
+
+#define ETH_TXQ_DISABLE_OFFSET 8
+#define ETH_TXQ_DISABLE_MASK (0x000000FF << ETH_TXQ_DISABLE_OFFSET)
+
+#if (MV_ETH_VERSION >= 4)
+#define ETH_TX_EJP_RESET_BIT 0
+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT)
+
+#define ETH_TX_EJP_ENABLE_BIT 2
+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT)
+
+#define ETH_TX_LEGACY_WRR_BIT 3
+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT)
+#endif /* (MV_ETH_VERSION >= 4) */
+
+/***** BITs of Ethernet Port Status reg (PSR) *****/
+#define ETH_LINK_UP_BIT 1
+#define ETH_LINK_UP_MASK (1<<ETH_LINK_UP_BIT)
+
+#define ETH_FULL_DUPLEX_BIT 2
+#define ETH_FULL_DUPLEX_MASK (1<<ETH_FULL_DUPLEX_BIT)
+
+#define ETH_ENABLE_RCV_FLOW_CTRL_BIT 3
+#define ETH_ENABLE_RCV_FLOW_CTRL_MASK (1<<ETH_ENABLE_RCV_FLOW_CTRL_BIT)
+
+#define ETH_GMII_SPEED_1000_BIT 4
+#define ETH_GMII_SPEED_1000_MASK (1<<ETH_GMII_SPEED_1000_BIT)
+
+#define ETH_MII_SPEED_100_BIT 5
+#define ETH_MII_SPEED_100_MASK (1<<ETH_MII_SPEED_100_BIT)
+
+#define ETH_TX_IN_PROGRESS_BIT 7
+#define ETH_TX_IN_PROGRESS_MASK (1<<ETH_TX_IN_PROGRESS_BIT)
+
+#define ETH_TX_FIFO_EMPTY_BIT 10
+#define ETH_TX_FIFO_EMPTY_MASK (1<<ETH_TX_FIFO_EMPTY_BIT)
+
+/***** BITs of Ethernet Port Status 1 reg (PS1R) *****/
+#define ETH_AUTO_NEG_DONE_BIT 4
+#define ETH_AUTO_NEG_DONE_MASK (1<<ETH_AUTO_NEG_DONE_BIT)
+
+#define ETH_SERDES_PLL_LOCKED_BIT 6
+#define ETH_SERDES_PLL_LOCKED_MASK (1<<ETH_SERDES_PLL_LOCKED_BIT)
+
+/***** BITs of Port Configuration reg (PxCR) *****/
+#define ETH_UNICAST_PROMISCUOUS_MODE_BIT 0
+#define ETH_UNICAST_PROMISCUOUS_MODE_MASK (1<<ETH_UNICAST_PROMISCUOUS_MODE_BIT)
+
+#define ETH_DEF_RX_QUEUE_OFFSET 1
+#define ETH_DEF_RX_QUEUE_ALL_MASK (0x7<<ETH_DEF_RX_QUEUE_OFFSET)
+#define ETH_DEF_RX_QUEUE_MASK(queue) ((queue)<<ETH_DEF_RX_QUEUE_OFFSET)
+
+#define ETH_DEF_RX_ARP_QUEUE_OFFSET 4
+#define ETH_DEF_RX_ARP_QUEUE_ALL_MASK (0x7<<ETH_DEF_RX_ARP_QUEUE_OFFSET)
+#define ETH_DEF_RX_ARP_QUEUE_MASK(queue) ((queue)<<ETH_DEF_RX_ARP_QUEUE_OFFSET)
+
+#define ETH_REJECT_NOT_IP_ARP_BCAST_BIT 7
+#define ETH_REJECT_NOT_IP_ARP_BCAST_MASK (1<<ETH_REJECT_NOT_IP_ARP_BCAST_BIT)
+
+#define ETH_REJECT_IP_BCAST_BIT 8
+#define ETH_REJECT_IP_BCAST_MASK (1<<ETH_REJECT_IP_BCAST_BIT)
+
+#define ETH_REJECT_ARP_BCAST_BIT 9
+#define ETH_REJECT_ARP_BCAST_MASK (1<<ETH_REJECT_ARP_BCAST_BIT)
+
+#define ETH_TX_NO_SET_ERROR_SUMMARY_BIT 12
+#define ETH_TX_NO_SET_ERROR_SUMMARY_MASK (1<<ETH_TX_NO_SET_ERROR_SUMMARY_BIT)
+
+#define ETH_CAPTURE_TCP_FRAMES_ENABLE_BIT 14
+#define ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK (1<<ETH_CAPTURE_TCP_FRAMES_ENABLE_BIT)
+
+#define ETH_CAPTURE_UDP_FRAMES_ENABLE_BIT 15
+#define ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK (1<<ETH_CAPTURE_UDP_FRAMES_ENABLE_BIT)
+
+#define ETH_DEF_RX_TCP_QUEUE_OFFSET 16
+#define ETH_DEF_RX_TCP_QUEUE_ALL_MASK (0x7<<ETH_DEF_RX_TCP_QUEUE_OFFSET)
+#define ETH_DEF_RX_TCP_QUEUE_MASK(queue) ((queue)<<ETH_DEF_RX_TCP_QUEUE_OFFSET)
+
+#define ETH_DEF_RX_UDP_QUEUE_OFFSET 19
+#define ETH_DEF_RX_UDP_QUEUE_ALL_MASK (0x7<<ETH_DEF_RX_UDP_QUEUE_OFFSET)
+#define ETH_DEF_RX_UDP_QUEUE_MASK(queue) ((queue)<<ETH_DEF_RX_UDP_QUEUE_OFFSET)
+
+#define ETH_DEF_RX_BPDU_QUEUE_OFFSET 22
+#define ETH_DEF_RX_BPDU_QUEUE_ALL_MASK (0x7<<ETH_DEF_RX_BPDU_QUEUE_OFFSET)
+#define ETH_DEF_RX_BPDU_QUEUE_MASK(queue) ((queue)<<ETH_DEF_RX_BPDU_QUEUE_OFFSET)
+
+#define ETH_RX_CHECKSUM_MODE_OFFSET 25
+#define ETH_RX_CHECKSUM_NO_PSEUDO_HDR (0<<ETH_RX_CHECKSUM_MODE_OFFSET)
+#define ETH_RX_CHECKSUM_WITH_PSEUDO_HDR (1<<ETH_RX_CHECKSUM_MODE_OFFSET)
+
+/***** BITs of Port Configuration Extend reg (PxCXR) *****/
+#define ETH_CAPTURE_SPAN_BPDU_ENABLE_BIT 1
+#define ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK (1<<ETH_CAPTURE_SPAN_BPDU_ENABLE_BIT)
+
+#define ETH_TX_DISABLE_GEN_CRC_BIT 3
+#define ETH_TX_DISABLE_GEN_CRC_MASK (1<<ETH_TX_DISABLE_GEN_CRC_BIT)
+
+/***** BITs of Tx/Rx queue command reg (RQCR/TQCR) *****/
+#define ETH_QUEUE_ENABLE_OFFSET 0
+#define ETH_QUEUE_ENABLE_ALL_MASK (0xFF<<ETH_QUEUE_ENABLE_OFFSET)
+#define ETH_QUEUE_ENABLE_MASK(queue) (1<<((queue)+ETH_QUEUE_ENABLE_OFFSET))
+
+#define ETH_QUEUE_DISABLE_OFFSET 8
+#define ETH_QUEUE_DISABLE_ALL_MASK (0xFF<<ETH_QUEUE_DISABLE_OFFSET)
+#define ETH_QUEUE_DISABLE_MASK(queue) (1<<((queue)+ETH_QUEUE_DISABLE_OFFSET))
+
+
+/***** BITs of Port Sdma Configuration reg (SDCR) *****/
+#define ETH_RX_FRAME_INTERRUPT_BIT 0
+#define ETH_RX_FRAME_INTERRUPT_MASK (1<<ETH_RX_FRAME_INTERRUPT_BIT)
+
+#define ETH_BURST_SIZE_1_64BIT_VALUE 0
+#define ETH_BURST_SIZE_2_64BIT_VALUE 1
+#define ETH_BURST_SIZE_4_64BIT_VALUE 2
+#define ETH_BURST_SIZE_8_64BIT_VALUE 3
+#define ETH_BURST_SIZE_16_64BIT_VALUE 4
+
+#define ETH_RX_BURST_SIZE_OFFSET 1
+#define ETH_RX_BURST_SIZE_ALL_MASK (0x7<<ETH_RX_BURST_SIZE_OFFSET)
+#define ETH_RX_BURST_SIZE_MASK(burst) ((burst)<<ETH_RX_BURST_SIZE_OFFSET)
+
+#define ETH_RX_NO_DATA_SWAP_BIT 4
+#define ETH_RX_NO_DATA_SWAP_MASK (1<<ETH_RX_NO_DATA_SWAP_BIT)
+#define ETH_RX_DATA_SWAP_MASK (0<<ETH_RX_NO_DATA_SWAP_BIT)
+
+#define ETH_TX_NO_DATA_SWAP_BIT 5
+#define ETH_TX_NO_DATA_SWAP_MASK (1<<ETH_TX_NO_DATA_SWAP_BIT)
+#define ETH_TX_DATA_SWAP_MASK (0<<ETH_TX_NO_DATA_SWAP_BIT)
+
+#define ETH_DESC_SWAP_BIT 6
+#define ETH_DESC_SWAP_MASK (1<<ETH_DESC_SWAP_BIT)
+#define ETH_NO_DESC_SWAP_MASK (0<<ETH_DESC_SWAP_BIT)
+
+#define ETH_RX_INTR_COAL_OFFSET 7
+#define ETH_RX_INTR_COAL_ALL_MASK (0x3fff<<ETH_RX_INTR_COAL_OFFSET)
+#define ETH_RX_INTR_COAL_MASK(value) (((value)<<ETH_RX_INTR_COAL_OFFSET) \
+ & ETH_RX_INTR_COAL_ALL_MASK)
+
+#define ETH_TX_BURST_SIZE_OFFSET 22
+#define ETH_TX_BURST_SIZE_ALL_MASK (0x7<<ETH_TX_BURST_SIZE_OFFSET)
+#define ETH_TX_BURST_SIZE_MASK(burst) ((burst)<<ETH_TX_BURST_SIZE_OFFSET)
+
+#define ETH_RX_INTR_COAL_MSB_BIT 25
+#define ETH_RX_INTR_COAL_MSB_MASK (1<<ETH_RX_INTR_COAL_MSB_BIT)
+
+/* BITs Port #x Tx FIFO Urgent Threshold (PxTFUT) */
+#define ETH_TX_INTR_COAL_OFFSET 4
+#define ETH_TX_INTR_COAL_ALL_MASK (0x3fff << ETH_TX_INTR_COAL_OFFSET)
+#define ETH_TX_INTR_COAL_MASK(value) (((value) << ETH_TX_INTR_COAL_OFFSET) \
+ & ETH_TX_INTR_COAL_ALL_MASK)
+
+/* BITs of Port Serial Control reg (PSCR) */
+#define ETH_PORT_ENABLE_BIT 0
+#define ETH_PORT_ENABLE_MASK (1<<ETH_PORT_ENABLE_BIT)
+
+#define ETH_FORCE_LINK_PASS_BIT 1
+#define ETH_FORCE_LINK_PASS_MASK (1<<ETH_FORCE_LINK_PASS_BIT)
+
+#define ETH_DISABLE_DUPLEX_AUTO_NEG_BIT 2
+#define ETH_DISABLE_DUPLEX_AUTO_NEG_MASK (1<<ETH_DISABLE_DUPLEX_AUTO_NEG_BIT)
+
+#define ETH_DISABLE_FC_AUTO_NEG_BIT 3
+#define ETH_DISABLE_FC_AUTO_NEG_MASK (1<<ETH_DISABLE_FC_AUTO_NEG_BIT)
+
+#define ETH_ADVERTISE_SYM_FC_BIT 4
+#define ETH_ADVERTISE_SYM_FC_MASK (1<<ETH_ADVERTISE_SYM_FC_BIT)
+
+#define ETH_TX_FC_MODE_OFFSET 5
+#define ETH_TX_FC_MODE_MASK (3<<ETH_TX_FC_MODE_OFFSET)
+#define ETH_TX_FC_NO_PAUSE (0<<ETH_TX_FC_MODE_OFFSET)
+#define ETH_TX_FC_SEND_PAUSE (1<<ETH_TX_FC_MODE_OFFSET)
+
+#define ETH_TX_BP_MODE_OFFSET 7
+#define ETH_TX_BP_MODE_MASK (3<<ETH_TX_BP_MODE_OFFSET)
+#define ETH_TX_BP_NO_JAM (0<<ETH_TX_BP_MODE_OFFSET)
+#define ETH_TX_BP_SEND_JAM (1<<ETH_TX_BP_MODE_OFFSET)
+
+#define ETH_DO_NOT_FORCE_LINK_FAIL_BIT 10
+#define ETH_DO_NOT_FORCE_LINK_FAIL_MASK (1<<ETH_DO_NOT_FORCE_LINK_FAIL_BIT)
+
+#define ETH_RETRANSMIT_FOREVER_BIT 11
+#define ETH_RETRANSMIT_FOREVER_MASK (1<<ETH_RETRANSMIT_FOREVER_BIT)
+
+#define ETH_DISABLE_SPEED_AUTO_NEG_BIT 13
+#define ETH_DISABLE_SPEED_AUTO_NEG_MASK (1<<ETH_DISABLE_SPEED_AUTO_NEG_BIT)
+
+#define ETH_DTE_ADVERT_BIT 14
+#define ETH_DTE_ADVERT_MASK (1<<ETH_DTE_ADVERT_BIT)
+
+#define ETH_MII_PHY_MODE_BIT 15
+#define ETH_MII_PHY_MODE_MAC (0<<ETH_MII_PHY_MODE_BIT)
+#define ETH_MII_PHY_MODE_PHY (1<<ETH_MII_PHY_MODE_BIT)
+
+#define ETH_MII_SOURCE_SYNCH_BIT 16
+#define ETH_MII_STANDARD_SYNCH (0<<ETH_MII_SOURCE_SYNCH_BIT)
+#define ETH_MII_400Mbps_SYNCH (1<<ETH_MII_SOURCE_CLK_BIT)
+
+#define ETH_MAX_RX_PACKET_SIZE_OFFSET 17
+#define ETH_MAX_RX_PACKET_SIZE_MASK (7<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+#define ETH_MAX_RX_PACKET_1518BYTE (0<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+#define ETH_MAX_RX_PACKET_1522BYTE (1<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+#define ETH_MAX_RX_PACKET_1552BYTE (2<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+#define ETH_MAX_RX_PACKET_9022BYTE (3<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+#define ETH_MAX_RX_PACKET_9192BYTE (4<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+#define ETH_MAX_RX_PACKET_9700BYTE (5<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
+
+#define ETH_SET_FULL_DUPLEX_BIT 21
+#define ETH_SET_FULL_DUPLEX_MASK (1<<ETH_SET_FULL_DUPLEX_BIT)
+
+#define ETH_SET_FLOW_CTRL_BIT 22
+#define ETH_SET_FLOW_CTRL_MASK (1<<ETH_SET_FLOW_CTRL_BIT)
+
+#define ETH_SET_GMII_SPEED_1000_BIT 23
+#define ETH_SET_GMII_SPEED_1000_MASK (1<<ETH_SET_GMII_SPEED_1000_BIT)
+
+#define ETH_SET_MII_SPEED_100_BIT 24
+#define ETH_SET_MII_SPEED_100_MASK (1<<ETH_SET_MII_SPEED_100_BIT)
+
+/* BITs of Port Serial Control 1 reg (PSC1R) */
+#define ETH_PSC_ENABLE_BIT 2
+#define ETH_PSC_ENABLE_MASK (1<<ETH_PSC_ENABLE_BIT)
+
+#define ETH_RGMII_ENABLE_BIT 3
+#define ETH_RGMII_ENABLE_MASK (1<<ETH_RGMII_ENABLE_BIT)
+
+#define ETH_PORT_RESET_BIT 4
+#define ETH_PORT_RESET_MASK (1<<ETH_PORT_RESET_BIT)
+
+#define ETH_INBAND_AUTO_NEG_ENABLE_BIT 6
+#define ETH_INBAND_AUTO_NEG_ENABLE_MASK (1<<ETH_INBAND_AUTO_NEG_ENABLE_BIT)
+
+#define ETH_INBAND_AUTO_NEG_BYPASS_BIT 7
+#define ETH_INBAND_AUTO_NEG_BYPASS_MASK (1<<ETH_INBAND_AUTO_NEG_BYPASS_BIT)
+
+#define ETH_INBAND_AUTO_NEG_START_BIT 8
+#define ETH_INBAND_AUTO_NEG_START_MASK (1<<ETH_INBAND_AUTO_NEG_START_BIT)
+
+#define ETH_PORT_TYPE_BIT 11
+#define ETH_PORT_TYPE_1000BasedX_MASK (1<<ETH_PORT_TYPE_BIT)
+
+#define ETH_SGMII_MODE_BIT 12
+#define ETH_1000BaseX_MODE_MASK (0<<ETH_SGMII_MODE_BIT)
+#define ETH_SGMII_MODE_MASK (1<<ETH_SGMII_MODE_BIT)
+
+#define ETH_MGMII_MODE_BIT 13
+
+#define ETH_EN_MII_ODD_PRE_BIT 22
+#define ETH_EN_MII_ODD_PRE_MASK (1<<ETH_EN_MII_ODD_PRE_BIT)
+
+/* BITs of SDMA Descriptor Command/Status field */
+#if defined(MV_CPU_BE)
+typedef struct _ethRxDesc
+{
+ MV_U16 byteCnt ; /* Descriptor buffer byte count */
+ MV_U16 bufSize ; /* Buffer size */
+ MV_U32 cmdSts ; /* Descriptor command status */
+ MV_U32 nextDescPtr; /* Next descriptor pointer */
+ MV_U32 bufPtr ; /* Descriptor buffer pointer */
+ MV_ULONG returnInfo ; /* User resource return information */
+} ETH_RX_DESC;
+
+typedef struct _ethTxDesc
+{
+ MV_U16 byteCnt ; /* Descriptor buffer byte count */
+ MV_U16 L4iChk ; /* CPU provided TCP Checksum */
+ MV_U32 cmdSts ; /* Descriptor command status */
+ MV_U32 nextDescPtr; /* Next descriptor pointer */
+ MV_U32 bufPtr ; /* Descriptor buffer pointer */
+ MV_ULONG returnInfo ; /* User resource return information */
+ MV_U8* alignBufPtr; /* Pointer to 8 byte aligned buffer */
+} ETH_TX_DESC;
+
+#elif defined(MV_CPU_LE)
+
+typedef struct _ethRxDesc
+{
+ MV_U32 cmdSts ; /* Descriptor command status */
+ MV_U16 bufSize ; /* Buffer size */
+ MV_U16 byteCnt ; /* Descriptor buffer byte count */
+ MV_U32 bufPtr ; /* Descriptor buffer pointer */
+ MV_U32 nextDescPtr; /* Next descriptor pointer */
+ MV_ULONG returnInfo ; /* User resource return information */
+} ETH_RX_DESC;
+
+typedef struct _ethTxDesc
+{
+ MV_U32 cmdSts ; /* Descriptor command status */
+ MV_U16 L4iChk ; /* CPU provided TCP Checksum */
+ MV_U16 byteCnt ; /* Descriptor buffer byte count */
+ MV_U32 bufPtr ; /* Descriptor buffer pointer */
+ MV_U32 nextDescPtr; /* Next descriptor pointer */
+ MV_ULONG returnInfo ; /* User resource return information */
+ MV_U8* alignBufPtr; /* Pointer to 32 byte aligned buffer */
+} ETH_TX_DESC;
+
+#else
+#error "MV_CPU_BE or MV_CPU_LE must be defined"
+#endif /* MV_CPU_BE || MV_CPU_LE */
+
+/* Buffer offset from buffer pointer */
+#define ETH_RX_BUF_OFFSET 0x2
+
+
+/* Tx & Rx descriptor bits */
+#define ETH_ERROR_SUMMARY_BIT 0
+#define ETH_ERROR_SUMMARY_MASK (1<<ETH_ERROR_SUMMARY_BIT)
+
+#define ETH_BUFFER_OWNER_BIT 31
+#define ETH_BUFFER_OWNED_BY_DMA (1<<ETH_BUFFER_OWNER_BIT)
+#define ETH_BUFFER_OWNED_BY_HOST (0<<ETH_BUFFER_OWNER_BIT)
+
+/* Tx descriptor bits */
+#define ETH_TX_ERROR_CODE_OFFSET 1
+#define ETH_TX_ERROR_CODE_MASK (3<<ETH_TX_ERROR_CODE_OFFSET)
+#define ETH_TX_LATE_COLLISION_ERROR (0<<ETH_TX_ERROR_CODE_OFFSET)
+#define ETH_TX_UNDERRUN_ERROR (1<<ETH_TX_ERROR_CODE_OFFSET)
+#define ETH_TX_EXCESSIVE_COLLISION_ERROR (2<<ETH_TX_ERROR_CODE_OFFSET)
+
+#define ETH_TX_LLC_SNAP_FORMAT_BIT 9
+#define ETH_TX_LLC_SNAP_FORMAT_MASK (1<<ETH_TX_LLC_SNAP_FORMAT_BIT)
+
+#define ETH_TX_IP_FRAG_BIT 10
+#define ETH_TX_IP_FRAG_MASK (1<<ETH_TX_IP_FRAG_BIT)
+#define ETH_TX_IP_FRAG (0<<ETH_TX_IP_FRAG_BIT)
+#define ETH_TX_IP_NO_FRAG (1<<ETH_TX_IP_FRAG_BIT)
+
+#define ETH_TX_IP_HEADER_LEN_OFFSET 11
+#define ETH_TX_IP_HEADER_LEN_ALL_MASK (0xF<<ETH_TX_IP_HEADER_LEN_OFFSET)
+#define ETH_TX_IP_HEADER_LEN_MASK(len) ((len)<<ETH_TX_IP_HEADER_LEN_OFFSET)
+
+#define ETH_TX_VLAN_TAGGED_FRAME_BIT 15
+#define ETH_TX_VLAN_TAGGED_FRAME_MASK (1<<ETH_TX_VLAN_TAGGED_FRAME_BIT)
+
+#define ETH_TX_L4_TYPE_BIT 16
+#define ETH_TX_L4_TCP_TYPE (0<<ETH_TX_L4_TYPE_BIT)
+#define ETH_TX_L4_UDP_TYPE (1<<ETH_TX_L4_TYPE_BIT)
+
+#define ETH_TX_GENERATE_L4_CHKSUM_BIT 17
+#define ETH_TX_GENERATE_L4_CHKSUM_MASK (1<<ETH_TX_GENERATE_L4_CHKSUM_BIT)
+
+#define ETH_TX_GENERATE_IP_CHKSUM_BIT 18
+#define ETH_TX_GENERATE_IP_CHKSUM_MASK (1<<ETH_TX_GENERATE_IP_CHKSUM_BIT)
+
+#define ETH_TX_ZERO_PADDING_BIT 19
+#define ETH_TX_ZERO_PADDING_MASK (1<<ETH_TX_ZERO_PADDING_BIT)
+
+#define ETH_TX_LAST_DESC_BIT 20
+#define ETH_TX_LAST_DESC_MASK (1<<ETH_TX_LAST_DESC_BIT)
+
+#define ETH_TX_FIRST_DESC_BIT 21
+#define ETH_TX_FIRST_DESC_MASK (1<<ETH_TX_FIRST_DESC_BIT)
+
+#define ETH_TX_GENERATE_CRC_BIT 22
+#define ETH_TX_GENERATE_CRC_MASK (1<<ETH_TX_GENERATE_CRC_BIT)
+
+#define ETH_TX_ENABLE_INTERRUPT_BIT 23
+#define ETH_TX_ENABLE_INTERRUPT_MASK (1<<ETH_TX_ENABLE_INTERRUPT_BIT)
+
+#define ETH_TX_AUTO_MODE_BIT 30
+#define ETH_TX_AUTO_MODE_MASK (1<<ETH_TX_AUTO_MODE_BIT)
+
+
+/* Rx descriptor bits */
+#define ETH_RX_ERROR_CODE_OFFSET 1
+#define ETH_RX_ERROR_CODE_MASK (3<<ETH_RX_ERROR_CODE_OFFSET)
+#define ETH_RX_CRC_ERROR (0<<ETH_RX_ERROR_CODE_OFFSET)
+#define ETH_RX_OVERRUN_ERROR (1<<ETH_RX_ERROR_CODE_OFFSET)
+#define ETH_RX_MAX_FRAME_LEN_ERROR (2<<ETH_RX_ERROR_CODE_OFFSET)
+#define ETH_RX_RESOURCE_ERROR (3<<ETH_RX_ERROR_CODE_OFFSET)
+
+#define ETH_RX_L4_CHECKSUM_OFFSET 3
+#define ETH_RX_L4_CHECKSUM_MASK (0xffff<<ETH_RX_L4_CHECKSUM_OFFSET)
+
+#define ETH_RX_VLAN_TAGGED_FRAME_BIT 19
+#define ETH_RX_VLAN_TAGGED_FRAME_MASK (1<<ETH_RX_VLAN_TAGGED_FRAME_BIT)
+
+#define ETH_RX_BPDU_FRAME_BIT 20
+#define ETH_RX_BPDU_FRAME_MASK (1<<ETH_RX_BPDU_FRAME_BIT)
+
+#define ETH_RX_L4_TYPE_OFFSET 21
+#define ETH_RX_L4_TYPE_MASK (3<<ETH_RX_L4_TYPE_OFFSET)
+#define ETH_RX_L4_TCP_TYPE (0<<ETH_RX_L4_TYPE_OFFSET)
+#define ETH_RX_L4_UDP_TYPE (1<<ETH_RX_L4_TYPE_OFFSET)
+#define ETH_RX_L4_OTHER_TYPE (2<<ETH_RX_L4_TYPE_OFFSET)
+
+#define ETH_RX_NOT_LLC_SNAP_FORMAT_BIT 23
+#define ETH_RX_NOT_LLC_SNAP_FORMAT_MASK (1<<ETH_RX_NOT_LLC_SNAP_FORMAT_BIT)
+
+#define ETH_RX_IP_FRAME_TYPE_BIT 24
+#define ETH_RX_IP_FRAME_TYPE_MASK (1<<ETH_RX_IP_FRAME_TYPE_BIT)
+
+#define ETH_RX_IP_HEADER_OK_BIT 25
+#define ETH_RX_IP_HEADER_OK_MASK (1<<ETH_RX_IP_HEADER_OK_BIT)
+
+#define ETH_RX_LAST_DESC_BIT 26
+#define ETH_RX_LAST_DESC_MASK (1<<ETH_RX_LAST_DESC_BIT)
+
+#define ETH_RX_FIRST_DESC_BIT 27
+#define ETH_RX_FIRST_DESC_MASK (1<<ETH_RX_FIRST_DESC_BIT)
+
+#define ETH_RX_UNKNOWN_DA_BIT 28
+#define ETH_RX_UNKNOWN_DA_MASK (1<<ETH_RX_UNKNOWN_DA_BIT)
+
+#define ETH_RX_ENABLE_INTERRUPT_BIT 29
+#define ETH_RX_ENABLE_INTERRUPT_MASK (1<<ETH_RX_ENABLE_INTERRUPT_BIT)
+
+#define ETH_RX_L4_CHECKSUM_OK_BIT 30
+#define ETH_RX_L4_CHECKSUM_OK_MASK (1<<ETH_RX_L4_CHECKSUM_OK_BIT)
+
+/* Rx descriptor bufSize field */
+#define ETH_RX_IP_FRAGMENTED_FRAME_BIT 2
+#define ETH_RX_IP_FRAGMENTED_FRAME_MASK (1<<ETH_RX_IP_FRAGMENTED_FRAME_BIT)
+
+#define ETH_RX_BUFFER_MASK 0xFFF8
+
+
+/* Ethernet Cause Register BITs */
+#define ETH_CAUSE_RX_READY_SUM_BIT 0
+#define ETH_CAUSE_EXTEND_BIT 1
+
+#define ETH_CAUSE_RX_READY_OFFSET 2
+#define ETH_CAUSE_RX_READY_BIT(queue) (ETH_CAUSE_RX_READY_OFFSET + (queue))
+#define ETH_CAUSE_RX_READY_MASK(queue) (1 << (ETH_CAUSE_RX_READY_BIT(queue)))
+
+#define ETH_CAUSE_RX_ERROR_SUM_BIT 10
+#define ETH_CAUSE_RX_ERROR_OFFSET 11
+#define ETH_CAUSE_RX_ERROR_BIT(queue) (ETH_CAUSE_RX_ERROR_OFFSET + (queue))
+#define ETH_CAUSE_RX_ERROR_MASK(queue) (1 << (ETH_CAUSE_RX_ERROR_BIT(queue)))
+
+#define ETH_CAUSE_TX_END_BIT 19
+#define ETH_CAUSE_SUM_BIT 31
+
+/* Ethernet Cause Extended Register BITs */
+#define ETH_CAUSE_TX_BUF_OFFSET 0
+#define ETH_CAUSE_TX_BUF_BIT(queue) (ETH_CAUSE_TX_BUF_OFFSET + (queue))
+#define ETH_CAUSE_TX_BUF_MASK(queue) (1 << (ETH_CAUSE_TX_BUF_BIT(queue)))
+
+#define ETH_CAUSE_TX_ERROR_OFFSET 8
+#define ETH_CAUSE_TX_ERROR_BIT(queue) (ETH_CAUSE_TX_ERROR_OFFSET + (queue))
+#define ETH_CAUSE_TX_ERROR_MASK(queue) (1 << (ETH_CAUSE_TX_ERROR_BIT(queue)))
+
+#define ETH_CAUSE_PHY_STATUS_CHANGE_BIT 16
+#define ETH_CAUSE_RX_OVERRUN_BIT 18
+#define ETH_CAUSE_TX_UNDERRUN_BIT 19
+#define ETH_CAUSE_LINK_STATE_CHANGE_BIT 20
+#define ETH_CAUSE_INTERNAL_ADDR_ERR_BIT 23
+#define ETH_CAUSE_EXTEND_SUM_BIT 31
+
+/* Marvell Header Register */
+/* Marvell Header register bits */
+#define ETH_MVHDR_EN_BIT 0
+#define ETH_MVHDR_EN_MASK (1 << ETH_MVHDR_EN_BIT)
+
+#define ETH_MVHDR_DAPREFIX_BIT 1
+#define ETH_MVHDR_DAPREFIX_MASK (0x3 << ETH_MVHDR_DAPREFIX_BIT)
+#define ETH_MVHDR_DAPREFIX_PRI_1_2 (0x1 << ETH_MVHDR_DAPREFIX_BIT)
+#define ETH_MVHDR_DAPREFIX_DBNUM_PRI (0x2 << ETH_MVHDR_DAPREFIX_BIT)
+#define ETH_MVHDR_DAPREFIX_SPID_PRI (0x3 << ETH_MVHDR_DAPREFIX_BIT)
+
+#define ETH_MVHDR_MHMASK_BIT 8
+#define ETH_MVHDR_MHMASK_MASK (0x3 << ETH_MVHDR_MHMASK_BIT)
+#define ETH_MVHDR_MHMASK_8_QUEUE (0x0 << ETH_MVHDR_MHMASK_BIT)
+#define ETH_MVHDR_MHMASK_4_QUEUE (0x1 << ETH_MVHDR_MHMASK_BIT)
+#define ETH_MVHDR_MHMASK_2_QUEUE (0x3 << ETH_MVHDR_MHMASK_BIT)
+
+
+/* Relevant for 6183 ONLY */
+#define ETH_UNIT_PORTS_PADS_CALIB_0_REG (MV_ETH_REG_BASE(0) + 0x0A0)
+#define ETH_UNIT_PORTS_PADS_CALIB_1_REG (MV_ETH_REG_BASE(0) + 0x0A4)
+#define ETH_UNIT_PORTS_PADS_CALIB_2_REG (MV_ETH_REG_BASE(0) + 0x0A8)
+/* Ethernet Unit Ports Pads Calibration_REG (ETH_UNIT_PORTS_PADS_CALIB_x_REG) */
+#define ETH_ETHERNET_PAD_CLIB_DRVN_OFFS 0
+#define ETH_ETHERNET_PAD_CLIB_DRVN_MASK (0x1F << ETH_ETHERNET_PAD_CLIB_DRVN_OFFS)
+
+#define ETH_ETHERNET_PAD_CLIB_DRVP_OFFS 5
+#define ETH_ETHERNET_PAD_CLIB_DRVP_MASK (0x1F << ETH_ETHERNET_PAD_CLIB_DRVP_OFFS)
+
+#define ETH_ETHERNET_PAD_CLIB_TUNEEN_OFFS 16
+#define ETH_ETHERNET_PAD_CLIB_TUNEEN_MASK (0x1 << ETH_ETHERNET_PAD_CLIB_TUNEEN_OFFS)
+
+#define ETH_ETHERNET_PAD_CLIB_LOCKN_OFFS 17
+#define ETH_ETHERNET_PAD_CLIB_LOCKN_MASK (0x1F << ETH_ETHERNET_PAD_CLIB_LOCKN_OFFS)
+
+#define ETH_ETHERNET_PAD_CLIB_OFFST_OFFS 24
+#define ETH_ETHERNET_PAD_CLIB_OFFST_MASK (0x1F << ETH_ETHERNET_PAD_CLIB_OFFST_OFFS)
+
+#define ETH_ETHERNET_PAD_CLIB_WR_EN_OFFS 31
+#define ETH_ETHERNET_PAD_CLIB_WR_EN_MASK (0x1 << ETH_ETHERNET_PAD_CLIB_WR_EN_OFFS)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvEthRegsh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvCompVer.txt
new file mode 100644
index 000000000..38a926440
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.4
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h
new file mode 100644
index 000000000..c42ed1a65
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h
@@ -0,0 +1,356 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvEth.h - Header File for : Ethernet Controller
+*
+* DESCRIPTION:
+* This header file contains macros typedefs and function declaration for
+* Marvell Gigabit Ethernet Controllers.
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+#ifndef __mvEth_h__
+#define __mvEth_h__
+
+/* includes */
+#include "mvTypes.h"
+#include "mv802_3.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+#include "eth/gbe/mvEthRegs.h"
+#include "mvSysHwConfig.h"
+
+/* defines */
+
+#define MV_ETH_EXTRA_FRAGS_NUM 2
+
+
+typedef enum
+{
+ MV_ETH_SPEED_AN,
+ MV_ETH_SPEED_10,
+ MV_ETH_SPEED_100,
+ MV_ETH_SPEED_1000
+
+} MV_ETH_PORT_SPEED;
+
+typedef enum
+{
+ MV_ETH_DUPLEX_AN,
+ MV_ETH_DUPLEX_HALF,
+ MV_ETH_DUPLEX_FULL
+
+} MV_ETH_PORT_DUPLEX;
+
+typedef enum
+{
+ MV_ETH_FC_AN_ADV_DIS,
+ MV_ETH_FC_AN_ADV_SYM,
+ MV_ETH_FC_DISABLE,
+ MV_ETH_FC_ENABLE
+
+} MV_ETH_PORT_FC;
+
+typedef enum
+{
+ MV_ETH_PRIO_FIXED = 0, /* Fixed priority mode */
+ MV_ETH_PRIO_WRR = 1 /* Weighted round robin priority mode */
+} MV_ETH_PRIO_MODE;
+
+/* Ethernet port specific infomation */
+typedef struct
+{
+ int maxRxPktSize;
+ int rxDefQ;
+ int rxBpduQ;
+ int rxArpQ;
+ int rxTcpQ;
+ int rxUdpQ;
+ int ejpMode;
+} MV_ETH_PORT_CFG;
+
+typedef struct
+{
+ int descrNum;
+} MV_ETH_RX_Q_CFG;
+
+typedef struct
+{
+ int descrNum;
+ MV_ETH_PRIO_MODE prioMode;
+ int quota;
+} MV_ETH_TX_Q_CFG;
+
+typedef struct
+{
+ int maxRxPktSize;
+ int rxDefQ;
+ int txDescrNum[MV_ETH_TX_Q_NUM];
+ int rxDescrNum[MV_ETH_RX_Q_NUM];
+ void *osHandle;
+} MV_ETH_PORT_INIT;
+
+typedef struct
+{
+ MV_BOOL isLinkUp;
+ MV_ETH_PORT_SPEED speed;
+ MV_ETH_PORT_DUPLEX duplex;
+ MV_ETH_PORT_FC flowControl;
+
+} MV_ETH_PORT_STATUS;
+
+typedef enum
+{
+ MV_ETH_DISABLE_HEADER_MODE = 0,
+ MV_ETH_ENABLE_HEADER_MODE_PRI_2_1 = 1,
+ MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM = 2,
+ MV_ETH_ENABLE_HEADER_MODE_PRI_SPID = 3
+} MV_ETH_HEADER_MODE;
+
+
+/* ethernet.h API list */
+void mvEthHalInit(void);
+void mvEthMemAttrGet(MV_BOOL* pIsSram, MV_BOOL* pIsSwCoher);
+
+/* Port Initalization routines */
+void* mvEthPortInit (int port, MV_ETH_PORT_INIT *pPortInit);
+void ethResetTxDescRing(void* pPortHndl, int queue);
+void ethResetRxDescRing(void* pPortHndl, int queue);
+
+void* mvEthPortHndlGet(int port);
+
+void mvEthPortFinish(void* pEthPortHndl);
+MV_STATUS mvEthPortDown(void* pEthPortHndl);
+MV_STATUS mvEthPortDisable(void* pEthPortHndl);
+MV_STATUS mvEthPortUp(void* pEthPortHndl);
+MV_STATUS mvEthPortEnable(void* pEthPortHndl);
+
+/* Port data flow routines */
+MV_PKT_INFO *mvEthPortForceTxDone(void* pEthPortHndl, int txQueue);
+MV_PKT_INFO *mvEthPortForceRx(void* pEthPortHndl, int rxQueue);
+
+/* Port Configuration routines */
+MV_STATUS mvEthDefaultsSet(void* pEthPortHndl);
+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize);
+
+/* Port RX MAC Filtering control routines */
+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr);
+MV_STATUS mvEthRxFilterModeSet(void* pPortHndl, MV_BOOL isPromisc);
+MV_STATUS mvEthMacAddrSet(void* pPortHandle, MV_U8* pMacAddr, int queue);
+MV_STATUS mvEthMcastAddrSet(void* pPortHandle, MV_U8 *pAddr, int queue);
+
+/* MIB Counters APIs */
+MV_U32 mvEthMibCounterRead(void* pPortHndl, unsigned int mibOffset,
+ MV_U32* pHigh32);
+void mvEthMibCountersClear(void* pPortHandle);
+
+/* TX Scheduling configuration routines */
+MV_STATUS mvEthTxQueueConfig(void* pPortHandle, int txQueue,
+ MV_ETH_PRIO_MODE txPrioMode, int txQuota);
+
+/* RX Dispatching configuration routines */
+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue);
+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue);
+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq);
+int mvEthTosToRxqGet(void* pPortHandle, int tos);
+
+/* Speed, Duplex, FlowControl routines */
+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed,
+ MV_ETH_PORT_DUPLEX duplex);
+
+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl);
+
+#if (MV_ETH_VERSION >= 4)
+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode);
+#endif /* (MV_ETH_VERSION >= 4) */
+
+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus);
+
+/* Marvell Header control */
+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode);
+
+/* PHY routines */
+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr);
+int mvEthPhyAddrGet(void* pPortHandle);
+
+/* Power management routines */
+void mvEthPortPowerDown(int port);
+void mvEthPortPowerUp(int port);
+
+/******************** ETH PRIVATE ************************/
+
+/*#define UNCACHED_TX_BUFFERS*/
+/*#define UNCACHED_RX_BUFFERS*/
+
+
+/* Port attributes */
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define ETH_RX_DESC_ALIGNED_SIZE 32
+#define ETH_TX_DESC_ALIGNED_SIZE 32
+
+#define TX_DISABLE_TIMEOUT_MSEC 1000
+#define RX_DISABLE_TIMEOUT_MSEC 1000
+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000
+#define PORT_DISABLE_WAIT_TCLOCKS 5000
+
+/* Macros that save access to desc in order to find next desc pointer */
+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \
+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \
+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \
+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE)
+
+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \
+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \
+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \
+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE)
+
+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \
+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \
+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \
+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE)
+
+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \
+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \
+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \
+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE)
+
+
+/* Queue specific information */
+typedef struct
+{
+ void* pFirstDescr;
+ void* pLastDescr;
+ void* pCurrentDescr;
+ void* pUsedDescr;
+ int resource;
+ MV_BUF_INFO descBuf;
+} ETH_QUEUE_CTRL;
+
+
+/* Ethernet port specific infomation */
+typedef struct _ethPortCtrl
+{
+ int portNo;
+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */
+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */
+
+ MV_ETH_PORT_CFG portConfig;
+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM];
+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM];
+
+ /* Register images - For DP */
+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */
+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */
+
+ MV_STATE portState;
+
+ MV_U8 mcastCount[256];
+ MV_U32* hashPtr;
+ void *osHandle;
+} ETH_PORT_CTRL;
+
+/************** MACROs ****************/
+
+/* MACROs to Flush / Invalidate TX / RX Buffers */
+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS)
+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \
+ mvOsCacheClear(NULL, (pAddr), (size)); \
+ /*CPU_PIPE_FLUSH;*/
+#else
+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \
+ mvOsIoVirtToPhy(NULL, (pAddr));
+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */
+
+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) )
+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \
+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \
+ /*CPU_PIPE_FLUSH;*/
+#else
+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size)
+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */
+
+#ifdef ETH_DESCR_UNCACHED
+
+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr)
+#define ETH_DESCR_INV(pPortCtrl, pDescr)
+
+#else
+
+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \
+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr))
+
+#define ETH_DESCR_INV(pPortCtrl, pDescr) \
+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr))
+
+#endif /* ETH_DESCR_UNCACHED */
+
+#include "eth/gbe/mvEthGbe.h"
+
+#endif /* __mvEth_h__ */
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt
new file mode 100644
index 000000000..38a926440
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.4
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c
new file mode 100644
index 000000000..889d4d9e9
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c
@@ -0,0 +1,362 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "gpp/mvGpp.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value);
+
+/*******************************************************************************
+* mvGppTypeSet - Enable a GPP (OUT) pin
+*
+* DESCRIPTION:
+*
+* INPUT:
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the type
+* of corresponding GPP will be set. Other GPPs are ignored.
+* value - 32bit value that describes GPP type per pin.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Set GPP8 to input and GPP15 to output.
+* mvGppTypeSet(0, (GPP8 | GPP15),
+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) );
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value)
+{
+ if (group >= MV_GPP_MAX_GROUP)
+ {
+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n"));
+ return MV_BAD_PARAM;
+ }
+
+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value);
+
+ /* Workaround for Erratum FE-MISC-70*/
+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1))
+ {
+ mask &= 0x2;
+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value);
+ } /*End of WA*/
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms
+*
+* DESCRIPTION:
+*
+* INPUT:
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the type
+* of corresponding GPP will be set. Other GPPs are ignored.
+* value - 32bit value that describes GPP blink per pin.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Set GPP8 to be static and GPP15 to be blinking.
+* mvGppBlinkEn(0, (GPP8 | GPP15),
+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) );
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value)
+{
+ if (group >= MV_GPP_MAX_GROUP)
+ {
+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n"));
+ return MV_BAD_PARAM;
+ }
+
+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value);
+
+ return MV_OK;
+
+}
+/*******************************************************************************
+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode
+*
+* DESCRIPTION:
+*
+* INPUT:
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the type
+* of corresponding GPP will be set. Other GPPs are ignored.
+* value - 32bit value that describes GPP polarity per pin.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Set GPP8 to the actual pin value and GPP15 to be inverted.
+* mvGppPolaritySet(0, (GPP8 | GPP15),
+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) );
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value)
+{
+ if (group >= MV_GPP_MAX_GROUP)
+ {
+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n"));
+ return MV_BAD_PARAM;
+ }
+
+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value);
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the
+* returned value is valid for it.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Get GPP8 and GPP15 value.
+* mvGppPolarityGet(0, (GPP8 | GPP15));
+*
+* RETURN:
+* 32bit value that describes GPP polatity mode per pin.
+*
+*******************************************************************************/
+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask)
+{
+ MV_U32 regVal;
+
+ if (group >= MV_GPP_MAX_GROUP)
+ {
+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n"));
+ return MV_ERROR;
+ }
+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group));
+
+ return (regVal & mask);
+}
+
+/*******************************************************************************
+* mvGppValueGet - Get a GPP Pin list value.
+*
+* DESCRIPTION:
+* This function get GPP value.
+*
+* INPUT:
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the
+* returned value is valid for it.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Get GPP8 and GPP15 value.
+* mvGppValueGet(0, (GPP8 | GPP15));
+*
+* RETURN:
+* 32bit value that describes GPP activity mode per pin.
+*
+*******************************************************************************/
+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask)
+{
+ MV_U32 gppData;
+
+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group));
+
+ gppData &= mask;
+
+ return gppData;
+
+}
+
+/*******************************************************************************
+* mvGppValueSet - Set a GPP Pin list value.
+*
+* DESCRIPTION:
+* This function set value for given GPP pin list.
+*
+* INPUT:
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the
+* value of corresponding GPP will be set accordingly. Other GPP
+* are not affected.
+* value - 32bit value that describes GPP value per pin.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Set GPP8 value of '0' and GPP15 value of '1'.
+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) );
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value)
+{
+ MV_U32 outEnable, tmp;
+ MV_U32 i;
+
+ if (group >= MV_GPP_MAX_GROUP)
+ {
+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n"));
+ return MV_BAD_PARAM;
+ }
+
+ /* verify that the gpp pin is configured as output */
+ /* Note that in the register out enabled -> bit = '0'. */
+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group));
+
+ /* Workaround for Erratum FE-MISC-70*/
+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1))
+ {
+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0));
+ outEnable &= 0xfffffffd;
+ outEnable |= (tmp & 0x2);
+ } /*End of WA*/
+
+ for (i = 0 ; i < 32 ;i++)
+ {
+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i)))
+ {
+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\
+ "value to GPP %d in input mode.\n", i);
+ return MV_ERROR;
+ }
+ }
+
+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value);
+
+ return MV_OK;
+
+}
+/*******************************************************************************
+* gppRegSet - Set a specific GPP pin on a specific GPP register
+*
+* DESCRIPTION:
+* This function set a specific GPP pin on a specific GPP register
+*
+* INPUT:
+* regOffs - GPP Register offset
+* group - GPP group number
+* mask - 32bit mask value. Each set bit in the mask means that the
+* value of corresponding GPP will be set accordingly. Other GPP
+* are not affected.
+* value - 32bit value that describes GPP value per pin.
+*
+* OUTPUT:
+* None.
+*
+* EXAMPLE:
+* Set GPP8 value of '0' and GPP15 value of '1'.
+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) );
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value)
+{
+ MV_U32 gppData;
+
+ gppData = MV_REG_READ(regOffs);
+
+ gppData &= ~mask;
+
+ gppData |= (value & mask);
+
+ MV_REG_WRITE(regOffs, gppData);
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h
new file mode 100644
index 000000000..526d324fd
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h
@@ -0,0 +1,118 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvGppH
+#define __INCmvGppH
+
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "gpp/mvGppRegs.h"
+
+/* These macros describes the GPP type. Each of the GPPs pins can */
+/* be assigned to act as a general purpose input or output pin. */
+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */
+#define MV_GPP_OUT 0 /* GPP output */
+
+
+/* These macros describes the GPP Out Enable. */
+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/
+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/
+
+/* These macros describes the GPP Out Blinking. */
+/* When set and the corresponding bit in GPIO Data Out Enable Control */
+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */
+/* 2^24 TCLK clocks). */
+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/
+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/
+
+
+/* These macros describes the GPP Polarity. */
+/* When set to 1 GPIO Data In Register reflects the inverted value of the */
+/* corresponding pin. */
+
+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/
+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/
+
+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */
+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value);
+
+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */
+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value);
+
+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */
+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value);
+
+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */
+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask);
+
+/* mvGppValueGet - Get a GPP Pin list value.*/
+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask);
+
+
+/* mvGppValueSet - Set a GPP Pin list value. */
+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value);
+
+#endif /* #ifndef __INCmvGppH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h
new file mode 100644
index 000000000..b6fec34fa
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h
@@ -0,0 +1,116 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvGppRegsH
+#define __INCmvGppRegsH
+
+#define MV_GPP0 BIT0
+#define MV_GPP1 BIT1
+#define MV_GPP2 BIT2
+#define MV_GPP3 BIT3
+#define MV_GPP4 BIT4
+#define MV_GPP5 BIT5
+#define MV_GPP6 BIT6
+#define MV_GPP7 BIT7
+#define MV_GPP8 BIT8
+#define MV_GPP9 BIT9
+#define MV_GPP10 BIT10
+#define MV_GPP11 BIT11
+#define MV_GPP12 BIT12
+#define MV_GPP13 BIT13
+#define MV_GPP14 BIT14
+#define MV_GPP15 BIT15
+#define MV_GPP16 BIT16
+#define MV_GPP17 BIT17
+#define MV_GPP18 BIT18
+#define MV_GPP19 BIT19
+#define MV_GPP20 BIT20
+#define MV_GPP21 BIT21
+#define MV_GPP22 BIT22
+#define MV_GPP23 BIT23
+#define MV_GPP24 BIT24
+#define MV_GPP25 BIT25
+#define MV_GPP26 BIT26
+#define MV_GPP27 BIT27
+#define MV_GPP28 BIT28
+#define MV_GPP29 BIT29
+#define MV_GPP30 BIT30
+#define MV_GPP31 BIT31
+
+
+/* registers offsets */
+
+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140)
+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144)
+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148)
+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c)
+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150)
+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154)
+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158)
+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c)
+
+#define GPP_DATA_OUT_SET_REG 0x10120
+#define GPP_DATA_OUT_CLEAR_REG 0x10124
+
+#endif /* #ifndef __INCmvGppRegsH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt
new file mode 100644
index 000000000..85bfa612c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.3
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c
new file mode 100644
index 000000000..672d3e31f
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c
@@ -0,0 +1,669 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "mvPciIf.h"
+#include "ctrlEnv/sys/mvSysPex.h"
+
+#if defined(MV_INCLUDE_PCI)
+#include "ctrlEnv/sys/mvSysPci.h"
+#endif
+
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+
+/*******************************************************************************
+* mvPciInit - Initialize PCI interfaces
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
+*
+*******************************************************************************/
+
+
+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+
+ MV_PCI_MOD pciMod;
+
+ if (PCI_IF_MODE_HOST == pciIfmode)
+ {
+ pciMod = MV_PCI_MOD_HOST;
+ }
+ else if (PCI_IF_MODE_DEVICE == pciIfmode)
+ {
+ pciMod = MV_PCI_MOD_DEVICE;
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Bus %d mode %d neither host nor device!\n",
+ __FUNCTION__, pciIf, pciIfmode);
+ return MV_FAIL;
+ }
+
+ return mvPciInit(pciIf - MV_PCI_START_IF, pciMod);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+
+ MV_PEX_TYPE pexType;
+
+ if (PCI_IF_MODE_HOST == pciIfmode)
+ {
+ pexType = MV_PEX_ROOT_COMPLEX;
+ }
+ else if (PCI_IF_MODE_DEVICE == pciIfmode)
+ {
+ pexType = MV_PEX_END_POINT;
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Bus %d type %d neither root complex nor" \
+ " end point\n", __FUNCTION__, pciIf, pciIfmode);
+ return MV_FAIL;
+ }
+ return mvPexInit(pciIf - MV_PEX_START_IF, pexType);
+
+ #else
+ return MV_OK;
+ #endif
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return MV_FAIL;
+
+}
+
+/* PCI configuration space read write */
+
+/*******************************************************************************
+* mvPciConfigRead - Read from configuration space
+*
+* DESCRIPTION:
+* This function performs a 32 bit read from PCI configuration space.
+* It supports both type 0 and type 1 of Configuration Transactions
+* (local and over bridge). In order to read from local bus segment, use
+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers
+* will result configuration transaction of type 1 (over bridge).
+*
+* INPUT:
+* pciIf - PCI interface number.
+* bus - PCI segment bus number.
+* dev - PCI device number.
+* func - Function number.
+* regOffs - Register offset.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit register data, 0xffffffff on error
+*
+*******************************************************************************/
+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
+ MV_U32 regOff)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciConfigRead(pciIf - MV_PCI_START_IF,
+ bus,
+ dev,
+ func,
+ regOff);
+ #else
+ return 0xffffffff;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexConfigRead(pciIf - MV_PEX_START_IF,
+ bus,
+ dev,
+ func,
+ regOff);
+ #else
+ return 0xffffffff;
+ #endif
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return 0;
+
+}
+
+/*******************************************************************************
+* mvPciConfigWrite - Write to configuration space
+*
+* DESCRIPTION:
+* This function performs a 32 bit write to PCI configuration space.
+* It supports both type 0 and type 1 of Configuration Transactions
+* (local and over bridge). In order to write to local bus segment, use
+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers
+* will result configuration transaction of type 1 (over bridge).
+*
+* INPUT:
+* pciIf - PCI interface number.
+* bus - PCI segment bus number.
+* dev - PCI device number.
+* func - Function number.
+* regOffs - Register offset.
+* data - 32bit data.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciConfigWrite(pciIf - MV_PCI_START_IF,
+ bus,
+ dev,
+ func,
+ regOff,
+ data);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexConfigWrite(pciIf - MV_PEX_START_IF,
+ bus,
+ dev,
+ func,
+ regOff,
+ data);
+ #else
+ return MV_OK;
+ #endif
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return MV_FAIL;
+
+}
+
+/*******************************************************************************
+* mvPciMasterEnable - Enable/disale PCI interface master transactions.
+*
+* DESCRIPTION:
+* This function performs read modified write to PCI command status
+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI
+* master is allowed to gain ownership on the bus, otherwise it is
+* incapable to do so.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable)
+{
+
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciMasterEnable(pciIf - MV_PCI_START_IF,
+ enable);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexMasterEnable(pciIf - MV_PEX_START_IF,
+ enable);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return MV_FAIL;
+
+}
+
+
+/*******************************************************************************
+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.
+*
+* DESCRIPTION:
+* This function performs read modified write to PCI command status
+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set,
+* the PCI slave is allowed to respond to PCI IO space access (bit 0)
+* and PCI memory space access (bit 1).
+*
+* INPUT:
+* pciIf - PCI interface number.
+* dev - PCI device number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, MV_BOOL enable)
+{
+
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciSlaveEnable(pciIf - MV_PCI_START_IF,bus,dev,
+ enable);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexSlaveEnable(pciIf - MV_PEX_START_IF,bus,dev,
+ enable);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return MV_FAIL;
+
+}
+
+/*******************************************************************************
+* mvPciLocalBusNumSet - Set PCI interface local bus number.
+*
+* DESCRIPTION:
+* This function sets given PCI interface its local bus number.
+* Note: In case the PCI interface is PCI-X, the information is read-only.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* busNum - Bus number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_NOT_ALLOWED in case PCI interface is PCI-X.
+* MV_BAD_PARAM on bad parameters ,
+* otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciLocalBusNumSet(pciIf - MV_PCI_START_IF,
+ busNum);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexLocalBusNumSet(pciIf - MV_PEX_START_IF,
+ busNum);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return MV_FAIL;
+
+}
+
+/*******************************************************************************
+* mvPciLocalBusNumGet - Get PCI interface local bus number.
+*
+* DESCRIPTION:
+* This function gets the local bus number of a given PCI interface.
+*
+* INPUT:
+* pciIf - PCI interface number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Local bus number.0xffffffff on Error
+*
+*******************************************************************************/
+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciLocalBusNumGet(pciIf - MV_PCI_START_IF);
+ #else
+ return 0xFFFFFFFF;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexLocalBusNumGet(pciIf - MV_PEX_START_IF);
+ #else
+ return 0xFFFFFFFF;
+ #endif
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n",__FUNCTION__, pciIf);
+ }
+
+ return 0;
+
+}
+
+
+/*******************************************************************************
+* mvPciLocalDevNumSet - Set PCI interface local device number.
+*
+* DESCRIPTION:
+* This function sets given PCI interface its local device number.
+* Note: In case the PCI interface is PCI-X, the information is read-only.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* devNum - Device number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters ,
+* otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciLocalDevNumSet(pciIf - MV_PCI_START_IF,
+ devNum);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexLocalDevNumSet(pciIf - MV_PEX_START_IF,
+ devNum);
+ #else
+ return MV_OK;
+ #endif
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return MV_FAIL;
+
+}
+
+/*******************************************************************************
+* mvPciLocalDevNumGet - Get PCI interface local device number.
+*
+* DESCRIPTION:
+* This function gets the local device number of a given PCI interface.
+*
+* INPUT:
+* pciIf - PCI interface number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Local device number. 0xffffffff on Error
+*
+*******************************************************************************/
+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf)
+{
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PCI)
+ return mvPciLocalDevNumGet(pciIf - MV_PCI_START_IF);
+ #else
+ return 0xFFFFFFFF;
+ #endif
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ #if defined(MV_INCLUDE_PEX)
+ return mvPexLocalDevNumGet(pciIf - MV_PEX_START_IF);
+ #else
+ return 0xFFFFFFFF;
+ #endif
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return 0;
+
+}
+
+/*******************************************************************************
+* mvPciIfTypeGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+
+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf)
+{
+
+ if ((pciIf >= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF))
+ {
+ return PCI_IF_TYPE_CONVEN_PCIX;
+ }
+ else if ((pciIf >= MV_PEX_START_IF) &&
+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF))
+ {
+ return PCI_IF_TYPE_PEX;
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return 0xffffffff;
+
+}
+
+/*******************************************************************************
+* mvPciIfTypeGet -
+*
+* DESCRIPTION:
+*
+* INPUT:
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+*
+*******************************************************************************/
+
+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf)
+{
+
+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf);
+
+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType)
+ {
+ return (pciIf - MV_PCI_START_IF);
+ }
+ else if (PCI_IF_TYPE_PEX == pciIfType)
+ {
+ return (pciIf - MV_PEX_START_IF);
+
+ }
+ else
+ {
+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf);
+ }
+
+ return 0xffffffff;
+
+}
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h
new file mode 100644
index 000000000..9c2d1604e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h
@@ -0,0 +1,134 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCPCIIFH
+#define __INCPCIIFH
+
+#include "mvSysHwConfig.h"
+#include "pci-if/mvPciIfRegs.h"
+#if defined(MV_INCLUDE_PEX)
+#include "pex/mvPex.h"
+#endif
+#if defined(MV_INCLUDE_PCI)
+#include "pci/mvPci.h"
+#endif
+#include "ctrlEnv/mvCtrlEnvLib.h"
+#include "ctrlEnv/mvCtrlEnvAddrDec.h"
+
+typedef enum _mvPCIIfType
+{
+ PCI_IF_TYPE_CONVEN_PCIX,
+ PCI_IF_TYPE_PEX
+
+}PCI_IF_TYPE;
+
+typedef enum _mvPCIIfMode
+{
+ PCI_IF_MODE_HOST,
+ PCI_IF_MODE_DEVICE
+}PCI_IF_MODE;
+
+
+/* Global Functions prototypes */
+
+/* mvPciIfInit - Initialize PCI interfaces*/
+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode);
+
+/* mvPciIfConfigRead - Read from configuration space */
+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func,MV_U32 regOff);
+
+/* mvPciIfConfigWrite - Write to configuration space */
+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data);
+
+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/
+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable);
+
+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/
+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev,
+ MV_BOOL enable);
+
+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/
+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum);
+
+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/
+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf);
+
+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/
+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum);
+
+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/
+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf);
+
+/* mvPciIfTypeGet - Get PCI If type*/
+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf);
+
+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf);
+
+/* mvPciIfAddrDecShow - Display address decode windows attributes */
+MV_VOID mvPciIfAddrDecShow(MV_VOID);
+
+#endif /* #ifndef __INCPCIIFH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h
new file mode 100644
index 000000000..08d4d2d90
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h
@@ -0,0 +1,245 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCPCIIFREGSH
+#define __INCPCIIFREGSH
+
+
+/* defines */
+#define MAX_PCI_DEVICES 32
+#define MAX_PCI_FUNCS 8
+#define MAX_PCI_BUSSES 128
+
+/***************************************/
+/* PCI Configuration registers */
+/***************************************/
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers */
+/*********************************************/
+
+
+/* Standard registers */
+#define PCI_DEVICE_AND_VENDOR_ID 0x000
+#define PCI_STATUS_AND_COMMAND 0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C
+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2))
+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
+#define PCI_CAPABILTY_LIST_POINTER 0x034
+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
+
+
+/* PCI Device and Vendor ID Register (PDVIR) */
+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */
+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS)
+
+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */
+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS)
+
+/* PCI Status and Command Register (PSCR) */
+#define PSCR_IO_EN BIT0 /* IO Enable */
+#define PSCR_MEM_EN BIT1 /* Memory Enable */
+#define PSCR_MASTER_EN BIT2 /* Master Enable */
+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */
+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */
+#define PSCR_VGA BIT5 /* VGA Palette Snoops */
+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */
+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/
+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */
+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/
+#define PSCR_CAP_LIST BIT20 /* Capability List Support */
+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */
+#define PSCR_UDF_EN BIT22 /* User definable features */
+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */
+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */
+
+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */
+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS)
+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS)
+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS)
+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS)
+
+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */
+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */
+#define PSCR_MABORT BIT29 /* Recieved Master Abort */
+#define PSCR_SYSERR BIT30 /* Signalled system error */
+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */
+
+/* PCI configuration register offset=0x08 fields
+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */
+
+#define PCCRIR_REVID_OFFS 0 /* Revision ID */
+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
+
+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */
+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS)
+
+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/
+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS)
+
+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/
+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS)
+
+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/
+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS)
+
+/* PCI configuration register offset=0x0C fields
+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */
+
+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */
+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS)
+
+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */
+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS)
+
+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */
+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS)
+
+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */
+
+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */
+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS)
+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS)
+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS)
+
+
+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */
+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS)
+
+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */
+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */
+
+
+/* PCI Bar Base Low Register (PBBLR) */
+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */
+
+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */
+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS)
+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS)
+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS)
+
+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */
+
+
+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to
+ address bits [31:4] */
+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS)
+
+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to
+ address bits [31:2] */
+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS)
+
+
+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */
+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS)
+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS)
+
+
+/* PCI Bar Base High Fegister (PBBHR) */
+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */
+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS)
+
+
+/* PCI configuration register offset=0x2C fields
+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */
+
+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */
+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS)
+
+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */
+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS)
+
+/* PCI configuration register offset=0x30 fields
+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */
+
+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */
+
+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */
+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS)
+
+/* PCI configuration register offset=0x34 fields
+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */
+
+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */
+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS)
+
+/* PCI configuration register offset=0x3C fields
+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */
+
+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */
+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS)
+
+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */
+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS)
+
+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */
+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS)
+
+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */
+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS)
+
+#endif /* #ifndef __INCPCIIFREGSH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c
new file mode 100644
index 000000000..f2169793b
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c
@@ -0,0 +1,1006 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/* includes */
+#include "mvPciUtils.h"
+
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/* #define MV_DEBUG */
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+ #define mvOsPrintf printf
+#else
+ #define DB(x)
+#endif
+
+/*
+This module only support scanning of Header type 00h of pci devices
+There is no suppotr for Header type 01h of pci devices ( PCI bridges )
+*/
+
+
+static MV_STATUS pciDetectDevice(MV_U32 pciIf,
+ MV_U32 bus,
+ MV_U32 dev,
+ MV_U32 func,
+ MV_PCI_DEVICE *pPciAgent);
+
+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf,
+ MV_U32 bus,
+ MV_U32 dev,
+ MV_U32 func,
+ MV_PCI_DEVICE *pPciAgent);
+
+
+
+
+
+
+/*******************************************************************************
+* mvPciScan - Scan a PCI interface bus
+*
+* DESCRIPTION:
+* Performs a full scan on a PCI interface and returns all possible details
+* on the agents found on the bus.
+*
+* INPUT:
+* pciIf - PCI Interface
+* pPciAgents - Pointer to an Array of the pci agents to be detected
+* pPciAgentsNum - pPciAgents array maximum number of elements
+*
+* OUTPUT:
+* pPciAgents - Array of the pci agents detected on the bus
+* pPciAgentsNum - Number of pci agents detected on the bus
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+
+MV_STATUS mvPciScan(MV_U32 pciIf,
+ MV_PCI_DEVICE *pPciAgents,
+ MV_U32 *pPciAgentsNum)
+{
+
+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0;
+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf);
+ MV_PCI_DEVICE *pPciDevice;
+ MV_PCI_DEVICE *pMainDevice;
+
+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf));
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPexMaxIfGet())
+ {
+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf));
+ return MV_BAD_PARAM;
+ }
+ if (NULL == pPciAgents)
+ {
+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n"));
+ return MV_BAD_PARAM;
+ }
+ if (NULL == pPciAgentsNum)
+ {
+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n"));
+ return MV_BAD_PARAM;
+ }
+
+
+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf));
+ /* Master enable the MV PCI master */
+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE))
+ {
+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n"));
+ return MV_ERROR;
+
+ }
+
+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf));
+
+ /* go through all busses */
+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++)
+ {
+ /* go through all possible devices on the local bus */
+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++)
+ {
+ /* always start with function equal to zero */
+ funcIndex=0;
+
+ pPciDevice=&pPciAgents[detectedDevNum];
+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex));
+
+ if (MV_ERROR == pciDetectDevice(pciIf,
+ busIndex,
+ devIndex,
+ funcIndex,
+ pPciDevice))
+ {
+ /* no device detected , try the next address */
+ continue;
+ }
+
+ /* We are here ! means we have detected a device*/
+ /* always we start with only one function per device */
+ pMainDevice = pPciDevice;
+ pPciDevice->funtionsNum = 1;
+
+
+ /* move on */
+ detectedDevNum++;
+
+
+ /* check if we have no more room for a new device */
+ if (detectedDevNum == *pPciAgentsNum)
+ {
+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n"));
+ return MV_ERROR;
+ }
+
+ /* check the detected device if it is a multi functional device then
+ scan all device functions*/
+ if (pPciDevice->isMultiFunction == MV_TRUE)
+ {
+ /* start with function number 1 because we have already detected
+ function 0 */
+ for (funcIndex=1; funcIndex<MAX_PCI_FUNCS ; funcIndex++)
+ {
+ pPciDevice=&pPciAgents[detectedDevNum];
+
+ if (MV_ERROR == pciDetectDevice(pciIf,
+ busIndex,
+ devIndex,
+ funcIndex,
+ pPciDevice))
+ {
+ /* no device detected means no more functions !*/
+ continue;
+ }
+ /* We are here ! means we have detected a device */
+
+ /* move on */
+ pMainDevice->funtionsNum++;
+ detectedDevNum++;
+
+ /* check if we have no more room for a new device */
+ if (detectedDevNum == *pPciAgentsNum)
+ {
+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n"));
+ return MV_ERROR;
+ }
+
+
+ }
+ }
+
+ }
+
+ }
+
+ /* return the number of devices actually detected on the bus ! */
+ *pPciAgentsNum = detectedDevNum;
+
+ return MV_OK;
+
+}
+
+
+/*******************************************************************************
+* pciDetectDevice - Detect a pci device parameters
+*
+* DESCRIPTION:
+* This function detect if a pci agent exist on certain address !
+* and if exists then it fills all possible information on the
+* agent
+*
+* INPUT:
+* pciIf - PCI Interface
+* bus - Bus number
+* dev - Device number
+* func - Function number
+*
+*
+*
+* OUTPUT:
+* pPciAgent - pointer to the pci agent filled with its information
+*
+* RETURN:
+* MV_ERROR if no device , MV_OK otherwise
+*
+*******************************************************************************/
+
+static MV_STATUS pciDetectDevice(MV_U32 pciIf,
+ MV_U32 bus,
+ MV_U32 dev,
+ MV_U32 func,
+ MV_PCI_DEVICE *pPciAgent)
+{
+ MV_U32 pciData;
+
+ /* no Parameters checking ! because it is static function and it is assumed
+ that all parameters were checked in the calling function */
+
+
+ /* Try read the PCI Vendor ID and Device ID */
+
+ /* We will scan only ourselves and the PCI slots that exist on the
+ board, because we may have a case that we have one slot that has
+ a Cardbus connector, and because CardBus answers all IDsels we want
+ to scan only this slot and ourseleves.
+
+ */
+ #if defined(MV_INCLUDE_PCI)
+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) &&
+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) &&
+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) &&
+ (DB_88F5181_DDR1_MNG != mvBoardIdGet()))
+ {
+
+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE)
+ {
+ return MV_ERROR;
+ }
+ }
+ #endif /* defined(MV_INCLUDE_PCI) */
+
+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID);
+
+ if (PCI_ERROR_CODE == pciData)
+ {
+ /* no device exist */
+ return MV_ERROR;
+ }
+
+ /* we are here ! means a device is detected */
+
+ /* fill basic information */
+ pPciAgent->busNumber=bus;
+ pPciAgent->deviceNum=dev;
+ pPciAgent->function=func;
+
+ /* Fill the PCI Vendor ID and Device ID */
+
+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS;
+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS;
+
+ /* Read Status and command */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_STATUS_AND_COMMAND);
+
+
+ /* Fill related Status and Command information*/
+
+ if (pciData & PSCR_TAR_FAST_BB)
+ {
+ pPciAgent->isFastB2BCapable = MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->isFastB2BCapable = MV_FALSE;
+ }
+
+ if (pciData & PSCR_CAP_LIST)
+ {
+ pPciAgent->isCapListSupport=MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->isCapListSupport=MV_FALSE;
+ }
+
+ if (pciData & PSCR_66MHZ_EN)
+ {
+ pPciAgent->is66MHZCapable=MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->is66MHZCapable=MV_FALSE;
+ }
+
+ /* Read Class Code and Revision */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_CLASS_CODE_AND_REVISION_ID);
+
+
+ pPciAgent->baseClassCode =
+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS;
+
+ pPciAgent->subClassCode =
+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS;
+
+ pPciAgent->progIf =
+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS;
+
+ pPciAgent->revisionID =
+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
+
+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE);
+
+
+
+ pPciAgent->pciCacheLine=
+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS;
+ pPciAgent->pciLatencyTimer=
+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS;
+
+ switch (pciData & PBHTLTCLR_HEADER_MASK)
+ {
+ case PBHTLTCLR_HEADER_STANDARD:
+
+ pPciAgent->pciHeader=MV_PCI_STANDARD;
+ break;
+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE:
+
+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE;
+ break;
+
+ }
+
+ if (pciData & PBHTLTCLR_MULTI_FUNC)
+ {
+ pPciAgent->isMultiFunction=MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->isMultiFunction=MV_FALSE;
+ }
+
+ if (pciData & PBHTLTCLR_BISTCAP)
+ {
+ pPciAgent->isBISTCapable=MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->isBISTCapable=MV_FALSE;
+ }
+
+
+ /* read this device pci bars */
+
+ pciDetectDeviceBars(pciIf,
+ bus,dev,func,
+ pPciAgent);
+
+
+ /* check if we are bridge*/
+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&&
+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE))
+ {
+
+ /* Read P2P_BUSSES_NUM */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_BUSSES_NUM);
+
+ pPciAgent->p2pPrimBusNum =
+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS;
+
+ pPciAgent->p2pSecBusNum =
+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS;
+
+ pPciAgent->p2pSubBusNum =
+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS;
+
+ pPciAgent->p2pSecLatencyTimer =
+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS;
+
+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_IO_BASE_LIMIT_SEC_STATUS);
+
+ pPciAgent->p2pSecStatus =
+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS;
+
+
+ pPciAgent->p2pIObase =
+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS;
+
+ /* clear low address (should be zero)*/
+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK;
+
+ pPciAgent->p2pIOLimit =
+ (pciData & PIBLSS_IO_LIMIT_MASK);
+
+ /* fill low address with 0xfff */
+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK;
+
+
+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS)
+ {
+ case PIBLSS_ADD_CAP_16BIT:
+
+ pPciAgent->bIO32 = MV_FALSE;
+
+ break;
+ case PIBLSS_ADD_CAP_32BIT:
+
+ pPciAgent->bIO32 = MV_TRUE;
+
+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_IO_BASE_LIMIT_UPPER_16);
+
+ pPciAgent->p2pIObase |=
+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS;
+
+
+ pPciAgent->p2pIOLimit |=
+ (pciData & PRBU_IO_UPP_LIMIT_MASK);
+
+ break;
+
+ }
+
+
+ /* Read P2P_MEM_BASE_LIMIT */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_MEM_BASE_LIMIT);
+
+ pPciAgent->p2pMemBase =
+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS;
+
+ /* clear low address */
+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK;
+
+ pPciAgent->p2pMemLimit =
+ (pciData & PMBL_MEM_LIMIT_MASK);
+
+ /* add 0xfffff */
+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK;
+
+
+ /* Read P2P_PREF_MEM_BASE_LIMIT */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_PREF_MEM_BASE_LIMIT);
+
+
+ pPciAgent->p2pPrefMemBase =
+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS;
+
+ /* get high address only */
+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK;
+
+
+
+ pPciAgent->p2pPrefMemLimit =
+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK);
+
+ /* add 0xfffff */
+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK;
+
+ switch (pciData & PRMBL_ADD_CAP_MASK)
+ {
+ case PRMBL_ADD_CAP_32BIT:
+
+ pPciAgent->bPrefMem64 = MV_FALSE;
+
+ /* Read P2P_PREF_BASE_UPPER_32 */
+ pPciAgent->p2pPrefBaseUpper32Bits = 0;
+
+ /* Read P2P_PREF_LIMIT_UPPER_32 */
+ pPciAgent->p2pPrefLimitUpper32Bits = 0;
+
+ break;
+ case PRMBL_ADD_CAP_64BIT:
+
+ pPciAgent->bPrefMem64 = MV_TRUE;
+
+ /* Read P2P_PREF_BASE_UPPER_32 */
+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_PREF_BASE_UPPER_32);
+
+ /* Read P2P_PREF_LIMIT_UPPER_32 */
+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ P2P_PREF_LIMIT_UPPER_32);
+
+ break;
+
+ }
+
+ }
+ else /* no bridge */
+ {
+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID);
+
+
+ pPciAgent->subSysVenID =
+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS;
+ pPciAgent->subSysID =
+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS;
+
+
+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_EXPANSION_ROM_BASE_ADDR_REG);
+
+
+ if (pciData & PERBAR_EXPROMEN)
+ {
+ pPciAgent->isExpRom = MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->isExpRom = MV_FALSE;
+ }
+
+ pPciAgent->expRomAddr =
+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS;
+
+ }
+
+
+ if (MV_TRUE == pPciAgent->isCapListSupport)
+ {
+ /* Read PCI_CAPABILTY_LIST_POINTER */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_CAPABILTY_LIST_POINTER);
+
+ pPciAgent->capListPointer =
+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS;
+
+ }
+
+ /* Read PCI_INTERRUPT_PIN_AND_LINE */
+ pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_INTERRUPT_PIN_AND_LINE);
+
+
+ pPciAgent->irqLine=
+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS;
+
+ pPciAgent->intPin=
+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS;
+
+ pPciAgent->minGrant=
+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS;
+ pPciAgent->maxLatency=
+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS;
+
+ mvPciClassNameGet(pPciAgent->baseClassCode,
+ (MV_8 *)pPciAgent->type);
+
+ return MV_OK;
+
+
+}
+
+/*******************************************************************************
+* pciDetectDeviceBars - Detect a pci device bars
+*
+* DESCRIPTION:
+* This function detects all pci agent bars
+*
+* INPUT:
+* pciIf - PCI Interface
+* bus - Bus number
+* dev - Device number
+* func - Function number
+*
+*
+*
+* OUTPUT:
+* pPciAgent - pointer to the pci agent filled with its information
+*
+* RETURN:
+* detected bars number
+*
+*******************************************************************************/
+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf,
+ MV_U32 bus,
+ MV_U32 dev,
+ MV_U32 func,
+ MV_PCI_DEVICE *pPciAgent)
+{
+ MV_U32 pciData,barIndex,detectedBar=0;
+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0;
+ MV_U32 pciMaxBars=0;
+
+ pPciAgent->barsNum=0;
+
+ /* check if we are bridge*/
+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&&
+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE))
+ {
+ pciMaxBars = 2;
+ }
+ else /* no bridge */
+ {
+ pciMaxBars = 6;
+ }
+
+ /* read this device pci bars */
+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ )
+ {
+ /* Read PCI_MEMORY_BAR_BASE_ADDR */
+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex));
+
+ pPciAgent->pciBar[detectedBar].barOffset =
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex);
+
+ /* check if the bar is 32bit or 64bit bar */
+ switch (pciData & PBBLR_TYPE_MASK)
+ {
+ case PBBLR_TYPE_32BIT_ADDR:
+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR;
+ break;
+ case PBBLR_TYPE_64BIT_ADDR:
+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR;
+ break;
+
+ }
+
+ /* check if it is memory or IO bar */
+ if (pciData & PBBLR_IOSPACE)
+ {
+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR;
+ }
+ else
+ {
+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR;
+ }
+
+ /* if it is memory bar then check if it is prefetchable */
+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)
+ {
+ if (pciData & PBBLR_PREFETCH_EN)
+ {
+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE;
+ }
+ else
+ {
+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE;
+ }
+
+ pPciAgent->pciBar[detectedBar].barBaseLow =
+ pciData & PBBLR_MEM_BASE_MASK;
+
+
+ }
+ else /* IO Bar */
+ {
+ pPciAgent->pciBar[detectedBar].barBaseLow =
+ pciData & PBBLR_IO_BASE_MASK;
+
+ }
+
+ pPciAgent->pciBar[detectedBar].barBaseHigh=0;
+
+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType)
+ {
+ barIndex++;
+
+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh =
+ mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex));
+
+
+ }
+
+ /* calculating full base address (64bit) */
+ pPciAgent->pciBar[detectedBar].barBaseAddr =
+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh;
+
+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32;
+
+ pPciAgent->pciBar[detectedBar].barBaseAddr |=
+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow;
+
+
+
+ /* get the sizes of the the bar */
+
+ pPciAgent->pciBar[detectedBar].barSizeHigh=0;
+
+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) &&
+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping))
+
+ {
+ /* write oxffffffff to the bar to get the size */
+ /* start with sizelow ( original value was saved in tmpBaseLow ) */
+ mvPciIfConfigWrite(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1),
+ 0xffffffff);
+
+ /* read size */
+ pPciAgent->pciBar[detectedBar].barSizeLow =
+ mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1));
+
+
+
+ /* restore original value */
+ mvPciIfConfigWrite(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1),
+ tmpBaseLow);
+
+
+ /* now do the same for BaseHigh */
+
+ /* write oxffffffff to the bar to get the size */
+ mvPciIfConfigWrite(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex),
+ 0xffffffff);
+
+ /* read size */
+ pPciAgent->pciBar[detectedBar].barSizeHigh =
+ mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex));
+
+ /* restore original value */
+ mvPciIfConfigWrite(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex),
+ tmpBaseHigh);
+
+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&&
+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh))
+ {
+ /* this bar is not applicable for this device,
+ ignore all previous settings and check the next bar*/
+
+ /* we though this was a 64bit bar , and it seems this
+ was wrong ! so decrement barIndex */
+ barIndex--;
+ continue;
+ }
+
+ /* calculate the full 64 bit size */
+
+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh)
+ {
+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK;
+
+ pPciAgent->pciBar[detectedBar].barSizeLow =
+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1;
+
+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0;
+
+ }
+ else
+ {
+
+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK;
+
+ pPciAgent->pciBar[detectedBar].barSizeLow =
+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1;
+
+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0;
+
+ }
+
+
+
+ }
+ else /* 32bit bar */
+ {
+ /* write oxffffffff to the bar to get the size */
+ mvPciIfConfigWrite(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex),
+ 0xffffffff);
+
+ /* read size */
+ pPciAgent->pciBar[detectedBar].barSizeLow =
+ mvPciIfConfigRead(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex));
+
+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow)
+ {
+ /* this bar is not applicable for this device,
+ ignore all previous settings and check the next bar*/
+ continue;
+ }
+
+
+ /* restore original value */
+ mvPciIfConfigWrite(pciIf,
+ bus,dev,func,
+ PCI_MEMORY_BAR_BASE_ADDR(barIndex),
+ tmpBaseLow);
+
+ /* calculate size low */
+
+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)
+ {
+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK;
+ }
+ else
+ {
+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK;
+ }
+
+ pPciAgent->pciBar[detectedBar].barSizeLow =
+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1;
+
+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0;
+ pPciAgent->pciBar[detectedBar].barSize =
+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow;
+
+
+ }
+
+ /* we are here ! this means we have already detected a bar for
+ this device , now move on */
+
+ detectedBar++;
+ pPciAgent->barsNum++;
+ }
+
+ return detectedBar;
+}
+
+
+/*******************************************************************************
+* mvPciClassNameGet - get PCI class name
+*
+* DESCRIPTION:
+* This function returns the PCI class name
+*
+* INPUT:
+* baseClassCode - Base Class Code.
+*
+* OUTPUT:
+* pType - the class name
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType)
+{
+
+ switch(baseClassCode)
+ {
+ case 0x0:
+ strcpy(pType,"Old generation device");
+ break;
+ case 0x1:
+ strcpy(pType,"Mass storage controller");
+ break;
+ case 0x2:
+ strcpy(pType,"Network controller");
+ break;
+ case 0x3:
+ strcpy(pType,"Display controller");
+ break;
+ case 0x4:
+ strcpy(pType,"Multimedia device");
+ break;
+ case 0x5:
+ strcpy(pType,"Memory controller");
+ break;
+ case 0x6:
+ strcpy(pType,"Bridge Device");
+ break;
+ case 0x7:
+ strcpy(pType,"Simple Communication controllers");
+ break;
+ case 0x8:
+ strcpy(pType,"Base system peripherals");
+ break;
+ case 0x9:
+ strcpy(pType,"Input Devices");
+ break;
+ case 0xa:
+ strcpy(pType,"Docking stations");
+ break;
+ case 0xb:
+ strcpy(pType,"Processors");
+ break;
+ case 0xc:
+ strcpy(pType,"Serial bus controllers");
+ break;
+ case 0xd:
+ strcpy(pType,"Wireless controllers");
+ break;
+ case 0xe:
+ strcpy(pType,"Intelligent I/O controllers");
+ break;
+ case 0xf:
+ strcpy(pType,"Satellite communication controllers");
+ break;
+ case 0x10:
+ strcpy(pType,"Encryption/Decryption controllers");
+ break;
+ case 0x11:
+ strcpy(pType,"Data acquisition and signal processing controllers");
+ break;
+ default:
+ strcpy(pType,"Unknown device");
+ break;
+ }
+
+ return MV_OK;
+
+}
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h
new file mode 100644
index 000000000..2ee0b1738
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h
@@ -0,0 +1,323 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvPciUtilsh
+#define __INCmvPciUtilsh
+
+/*
+This module only support scanning of Header type 00h of pci devices
+There is no suppotr for Header type 01h of pci devices ( PCI bridges )
+*/
+
+/* includes */
+#include "mvSysHwConfig.h"
+#include "pci-if/mvPciIf.h"
+#include "pci/mvPciRegs.h"
+
+
+
+/* PCI base address low bar mask */
+#define PCI_ERROR_CODE 0xffffffff
+
+#define PCI_BRIDGE_CLASS 0x6
+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4
+
+
+#define P2P_BUSSES_NUM 0x18
+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C
+#define P2P_MEM_BASE_LIMIT 0x20
+#define P2P_PREF_MEM_BASE_LIMIT 0x24
+#define P2P_PREF_BASE_UPPER_32 0x28
+#define P2P_PREF_LIMIT_UPPER_32 0x2C
+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30
+#define P2P_EXP_ROM 0x38
+
+/* P2P_BUSSES_NUM (PBM) */
+
+#define PBM_PRIME_BUS_NUM_OFFS 0
+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS)
+
+#define PBM_SEC_BUS_NUM_OFFS 8
+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS)
+
+#define PBM_SUB_BUS_NUM_OFFS 16
+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS)
+
+#define PBM_SEC_LAT_TMR_OFFS 24
+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS)
+
+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */
+
+#define PIBLSS_IO_BASE_OFFS 0
+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS)
+
+#define PIBLSS_ADD_CAP_OFFS 0
+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS)
+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS)
+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS)
+
+#define PIBLSS_LOW_ADDR_OFFS 0
+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS)
+
+#define PIBLSS_HIGH_ADDR_OFFS 12
+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS)
+
+#define PIBLSS_IO_LIMIT_OFFS 8
+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS)
+
+#define PIBLSS_SEC_STATUS_OFFS 16
+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS)
+
+
+/* P2P_MEM_BASE_LIMIT (PMBL)*/
+
+#define PMBL_MEM_BASE_OFFS 0
+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS)
+
+#define PMBL_MEM_LIMIT_OFFS 16
+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS)
+
+
+#define PMBL_LOW_ADDR_OFFS 0
+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS)
+
+#define PMBL_HIGH_ADDR_OFFS 20
+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS)
+
+
+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */
+
+#define PRMBL_PREF_MEM_BASE_OFFS 0
+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS)
+
+#define PRMBL_PREF_MEM_LIMIT_OFFS 16
+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<<PRMBL_PREF_MEM_LIMIT_OFFS)
+
+#define PRMBL_LOW_ADDR_OFFS 0
+#define PRMBL_LOW_ADDR_MASK (0xFFFFF << PRMBL_LOW_ADDR_OFFS)
+
+#define PRMBL_HIGH_ADDR_OFFS 20
+#define PRMBL_HIGH_ADDR_MASK (0xFFF << PRMBL_HIGH_ADDR_OFFS)
+
+#define PRMBL_ADD_CAP_OFFS 0
+#define PRMBL_ADD_CAP_MASK (0xf << PRMBL_ADD_CAP_OFFS)
+#define PRMBL_ADD_CAP_32BIT (0x0 << PRMBL_ADD_CAP_OFFS)
+#define PRMBL_ADD_CAP_64BIT (0x1 << PRMBL_ADD_CAP_OFFS)
+
+/* P2P_IO_BASE_LIMIT_UPPER_16 (PIBLU) */
+
+#define PRBU_IO_UPP_BASE_OFFS 0
+#define PRBU_IO_UPP_BASE_MASK (0xffff << PRBU_IO_UPP_BASE_OFFS)
+
+#define PRBU_IO_UPP_LIMIT_OFFS 16
+#define PRBU_IO_UPP_LIMIT_MASK (0xffff << PRBU_IO_UPP_LIMIT_OFFS)
+
+
+/* typedefs */
+
+typedef enum _mvPciBarMapping
+{
+ PCI_MEMORY_BAR,
+ PCI_IO_BAR,
+ PCI_NO_MAPPING
+}MV_PCI_BAR_MAPPING;
+
+typedef enum _mvPciBarType
+{
+ PCI_32BIT_BAR,
+ PCI_64BIT_BAR
+}MV_PCI_BAR_TYPE;
+
+typedef enum _mvPciIntPin
+{
+ MV_PCI_INTA = 1,
+ MV_PCI_INTB = 2,
+ MV_PCI_INTC = 3,
+ MV_PCI_INTD = 4
+}MV_PCI_INT_PIN;
+
+typedef enum _mvPciHeader
+{
+ MV_PCI_STANDARD,
+ MV_PCI_PCI2PCI_BRIDGE
+
+}MV_PCI_HEADER;
+
+
+/* BAR structure */
+typedef struct _pciBar
+{
+ MV_U32 barOffset;
+ MV_U32 barBaseLow;
+ MV_U32 barBaseHigh;
+ MV_U32 barSizeLow;
+ MV_U32 barSizeHigh;
+ /* The 'barBaseAddr' is a 64-bit variable
+ that will contain the TOTAL base address
+ value achived by combining both the 'barBaseLow'
+ and the 'barBaseHigh' parameters as follows:
+
+ BIT: 63 31 0
+ | | |
+ barBaseHigh barBaseLow */
+ MV_U64 barBaseAddr;
+ /* The 'barSize' is a 64-bit variable
+ that will contain the TOTAL size achived
+ by combining both the 'barSizeLow' and
+ the 'barSizeHigh' parameters as follows:
+
+ BIT: 63 31 0
+ | | |
+ barSizeHigh barSizeLow
+
+ NOTE: The total size described above
+ is AFTER the size calculation as
+ described in PCI spec rev2.2 */
+ MV_U64 barSize;
+ MV_BOOL isPrefetchable;
+ MV_PCI_BAR_TYPE barType;
+ MV_PCI_BAR_MAPPING barMapping;
+
+
+} PCI_BAR;
+
+/* Device information structure */
+typedef struct _mvPciDevice
+{
+ /* Device specific information */
+ MV_U32 busNumber; /* Pci agent bus number */
+ MV_U32 deviceNum; /* Pci agent device number */
+ MV_U32 function; /* Pci agent function number */
+
+ MV_U32 venID; /* Pci agent Vendor ID */
+ MV_U32 deviceID; /* Pci agent Device ID */
+
+ MV_BOOL isFastB2BCapable; /* Capability of Fast Back to Back
+ transactions */
+ MV_BOOL isCapListSupport; /* Support of Capability list */
+ MV_BOOL is66MHZCapable; /* 66MHZ support */
+
+ MV_U32 baseClassCode; /* Pci agent base Class Code */
+ MV_U32 subClassCode; /* Pci agent sub Class Code */
+ MV_U32 progIf; /* Pci agent Programing interface */
+ MV_U32 revisionID;
+
+ PCI_BAR pciBar[6]; /* Pci agent bar list */
+
+ MV_U32 p2pPrimBusNum; /* P2P Primary Bus number*/
+ MV_U32 p2pSecBusNum; /* P2P Secondary Bus Number*/
+ MV_U32 p2pSubBusNum; /* P2P Subordinate bus Number */
+ MV_U32 p2pSecLatencyTimer; /* P2P Econdary Latency Timer*/
+ MV_U32 p2pIObase; /* P2P IO Base */
+ MV_U32 p2pIOLimit; /* P2P IO Linit */
+ MV_BOOL bIO32;
+ MV_U32 p2pSecStatus; /* P2P Secondary Status */
+ MV_U32 p2pMemBase; /* P2P Memory Space */
+ MV_U32 p2pMemLimit; /* P2P Memory Limit*/
+ MV_U32 p2pPrefMemBase; /* P2P Prefetchable Mem Base*/
+ MV_U32 p2pPrefMemLimit; /* P2P Prefetchable Memory Limit*/
+ MV_BOOL bPrefMem64;
+ MV_U32 p2pPrefBaseUpper32Bits;/* P2P Prefetchable upper 32 bits*/
+ MV_U32 p2pPrefLimitUpper32Bits;/* P2P prefetchable limit upper 32*/
+
+
+ MV_U32 pciCacheLine; /* Pci agent cache line */
+ MV_U32 pciLatencyTimer; /* Pci agent Latency timer */
+ MV_PCI_HEADER pciHeader; /* Pci agent header type*/
+ MV_BOOL isMultiFunction; /* Multi function support */
+ MV_BOOL isBISTCapable; /* Self test capable */
+
+ MV_U32 subSysID; /* Sub System ID */
+ MV_U32 subSysVenID; /* Sub System Vendor ID */
+
+ MV_BOOL isExpRom; /* Expantion Rom support */
+ MV_U32 expRomAddr; /* Expantion Rom pointer */
+
+ MV_U32 capListPointer; /* Capability list pointer */
+
+ MV_U32 irqLine; /* IRQ line */
+ MV_PCI_INT_PIN intPin; /* Interrupt pin */
+ MV_U32 minGrant; /* Minimum grant*/
+ MV_U32 maxLatency; /* Maximum latency*/
+
+ MV_U32 funtionsNum; /* pci agent total functions number */
+
+ MV_U32 barsNum;
+ MV_U8 type[60]; /* class name of the pci agent */
+
+
+} MV_PCI_DEVICE;
+
+/* PCI gloabl functions */
+MV_STATUS mvPciClassNameGet(MV_U32 classCode, MV_8 *pType);
+
+
+/* Performs a full scan on both PCIs and returns all possible details on the
+ agents found on the bus. */
+MV_STATUS mvPciScan(MV_U32 pciIf,
+ MV_PCI_DEVICE *pPciAgents,
+ MV_U32 *pPciAgentsNum);
+
+
+#endif /* #ifndef __INCmvPciUtilsh */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt
new file mode 100644
index 000000000..7b6fe369c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.2
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c
new file mode 100644
index 000000000..4a087343d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c
@@ -0,0 +1,1047 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "pci/mvPci.h"
+
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+
+
+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod)
+{
+ if (MV_PCI_MOD_HOST == pciIfmod)
+ {
+
+ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf));
+ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf));
+
+ /* Local device master Enable */
+ mvPciMasterEnable(pciIf, MV_TRUE);
+
+ /* Local device slave Enable */
+ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf),
+ mvPciLocalDevNumGet(pciIf), MV_TRUE);
+ }
+ /* enable CPU-2-PCI ordering */
+ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN);
+}
+
+/*******************************************************************************
+* mvPciCommandSet - Set PCI comman register value.
+*
+* DESCRIPTION:
+* This function sets a given PCI interface with its command register
+* value.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* command - 32bit value to be written to comamnd register.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command)
+{
+ MV_U32 locBusNum, locDevNum, regVal;
+
+ locBusNum = mvPciLocalBusNumGet(pciIf);
+ locDevNum = mvPciLocalDevNumGet(pciIf);
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf);
+ return MV_BAD_PARAM;
+ }
+
+ /* Set command register */
+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command);
+
+ /* Upodate device max outstanding split tarnsaction */
+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) &&
+ (command & PCR_PCI_TO_CPU_ORDER_EN))
+ {
+ /* Read PCI-X command register */
+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND);
+
+ /* clear bits 22:20 */
+ regVal &= 0xff8fffff;
+
+ /* set reset value */
+ regVal |= (0x3 << 20);
+
+ /* Write back the value */
+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal);
+ }
+
+ return MV_OK;
+
+
+}
+
+
+/*******************************************************************************
+* mvPciModeGet - Get PCI interface mode.
+*
+* DESCRIPTION:
+* This function returns the given PCI interface mode.
+*
+* INPUT:
+* pciIf - PCI interface number.
+*
+* OUTPUT:
+* pPciMode - Pointer to PCI mode structure.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode)
+{
+ MV_U32 pciMode;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf);
+ return MV_BAD_PARAM;
+ }
+ if (NULL == pPciMode)
+ {
+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n");
+ return MV_BAD_PARAM;
+ }
+
+ /* Read pci mode register */
+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf));
+
+ switch (pciMode & PMR_PCI_MODE_MASK)
+ {
+ case PMR_PCI_MODE_CONV:
+ pPciMode->pciType = MV_PCI_CONV;
+
+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN)
+ {
+ pPciMode->pciSpeed = 66000000; /* 66MHZ */
+ }
+ else
+ {
+ pPciMode->pciSpeed = 33000000; /* 33MHZ */
+ }
+
+ break;
+
+ case PMR_PCI_MODE_PCIX_66MHZ:
+ pPciMode->pciType = MV_PCIX;
+ pPciMode->pciSpeed = 66000000; /* 66MHZ */
+ break;
+
+ case PMR_PCI_MODE_PCIX_100MHZ:
+ pPciMode->pciType = MV_PCIX;
+ pPciMode->pciSpeed = 100000000; /* 100MHZ */
+ break;
+
+ case PMR_PCI_MODE_PCIX_133MHZ:
+ pPciMode->pciType = MV_PCIX;
+ pPciMode->pciSpeed = 133000000; /* 133MHZ */
+ break;
+
+ default:
+ {
+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n");
+ return MV_ERROR;
+ }
+ }
+
+ switch (pciMode & PMR_PCI_64_MASK)
+ {
+ case PMR_PCI_64_64BIT:
+ pPciMode->pciWidth = MV_PCI_64;
+ break;
+
+ case PMR_PCI_64_32BIT:
+ pPciMode->pciWidth = MV_PCI_32;
+ break;
+
+ default:
+ {
+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n");
+ return MV_ERROR;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPciRetrySet - Set PCI retry counters
+*
+* DESCRIPTION:
+* This function specifies the number of times the PCI controller
+* retries a transaction before it quits.
+* Applies to the PCI Master when acting as a requester.
+* Applies to the PCI slave when acting as a completer (PCI-X mode).
+* A 0x00 value means a "retry forever".
+*
+* INPUT:
+* pciIf - PCI interface number.
+* counter - Number of times PCI controller retry. Use counter value
+* up to PRR_RETRY_CNTR_MAX.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter)
+{
+ MV_U32 pciRetry;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf);
+ return MV_BAD_PARAM;
+ }
+
+ if (counter >= PRR_RETRY_CNTR_MAX)
+ {
+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter);
+ return MV_BAD_PARAM;
+
+ }
+
+ /* Reading PCI retry register */
+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf));
+
+ pciRetry &= ~PRR_RETRY_CNTR_MASK;
+
+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS);
+
+ /* write new value */
+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPciDiscardTimerSet - Set PCI discard timer
+*
+* DESCRIPTION:
+* This function set PCI discard timer.
+* In conventional PCI mode:
+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed
+* read buffers (non-completed delayed read) before invalidate the buffer.
+* Set to '0' to disable the timer. The PCI slave waits for delayed
+* read completion forever.
+* In PCI-X mode:
+* Specifies the number of PCLK cycles the PCI master waits for split
+* completion transaction, before it invalidates the pre-allocated read
+* buffer.
+* Set to '0' to disable the timer. The PCI master waits for split
+* completion forever.
+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK,
+* unless using the "wait for ever" setting 0x0.
+* NOTE: Must not be updated while there are pending read requests.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* pClkCycles - Number of PCI clock cycles.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles)
+{
+ MV_U32 pciDiscardTimer;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n",
+ pciIf);
+ return MV_BAD_PARAM;
+ }
+
+ if (pClkCycles >= PDTR_TIMER_MIN)
+ {
+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n",
+ pClkCycles);
+ return MV_BAD_PARAM;
+
+ }
+
+ /* Read PCI Discard Timer */
+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf));
+
+ pciDiscardTimer &= ~PDTR_TIMER_MASK;
+
+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS);
+
+ /* Write new value */
+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer);
+
+ return MV_OK;
+
+}
+
+/* PCI Arbiter routines */
+
+/*******************************************************************************
+* mvPciArbEnable - PCI arbiter enable/disable
+*
+* DESCRIPTION:
+* This fuction enable/disables a given PCI interface arbiter.
+* NOTE: Arbiter setting can not be changed while in work. It should only
+* be set once.
+* INPUT:
+* pciIf - PCI interface number.
+* enable - Enable/disable parameter. If enable = MV_TRUE then enable.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable)
+{
+ MV_U32 regVal;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf);
+ return MV_ERROR;
+ }
+
+ /* Set PCI Arbiter Control register according to default configuration */
+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
+
+ /* Make sure arbiter disabled before changing its values */
+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
+
+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK;
+
+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */
+
+ if (MV_TRUE == enable)
+ {
+ regVal |= PACR_ARB_ENABLE;
+ }
+ else
+ {
+ regVal &= ~PACR_ARB_ENABLE;
+ }
+
+ /* Write to register */
+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPciArbParkDis - Disable arbiter parking on agent
+*
+* DESCRIPTION:
+* This function disables the PCI arbiter from parking on the given agent
+* list.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* pciAgentMask - When a bit in the mask is set to '1', parking on
+* the associated PCI master is disabled. Mask bit
+* refers to bit 0 - 6. For example disable parking on PCI
+* agent 3 set pciAgentMask 0x4 (bit 3 is set).
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask)
+{
+ MV_U32 pciArbiterCtrl;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf);
+ return MV_ERROR;
+ }
+
+ /* Reading Arbiter Control register */
+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
+
+ /* Arbiter must be disabled before changing parking */
+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
+
+ /* do the change */
+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK;
+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS);
+
+ /* writing new value ( if th earbiter was enabled before the change */
+ /* here it will be reenabled */
+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection
+*
+* DESCRIPTION:
+* This function sets the maximum number of cycles that the arbiter
+* waits for a PCI master to respond to its grant assertion. If a
+* PCI agent fails to respond within this time, the PCI arbiter aborts
+* the transaction and performs a new arbitration cycle.
+* NOTE: Value must be greater than '1' for conventional PCI and
+* greater than '5' for PCI-X.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken
+* master detection is disabled.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles)
+{
+ MV_U32 pciArbiterCtrl;
+ MV_U32 pciMode;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n",
+ pciIf);
+ return MV_BAD_PARAM;
+ }
+
+ /* Checking PCI mode and if pClkCycles is legal value */
+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf));
+ pciMode &= PMR_PCI_MODE_MASK;
+
+ if (PMR_PCI_MODE_CONV == pciMode)
+ {
+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN)
+ return MV_ERROR;
+ }
+ else
+ {
+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN)
+ return MV_ERROR;
+ }
+
+ pClkCycles <<= PACR_BROKEN_VAL_OFFS;
+
+ /* Reading Arbiter Control register */
+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK;
+ pciArbiterCtrl |= pClkCycles;
+
+ /* Arbiter must be disabled before changing broken detection */
+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
+
+ /* writing new value ( if th earbiter was enabled before the change */
+ /* here it will be reenabled */
+
+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl);
+
+ return MV_OK;
+}
+
+/* PCI configuration space read write */
+
+/*******************************************************************************
+* mvPciConfigRead - Read from configuration space
+*
+* DESCRIPTION:
+* This function performs a 32 bit read from PCI configuration space.
+* It supports both type 0 and type 1 of Configuration Transactions
+* (local and over bridge). In order to read from local bus segment, use
+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers
+* will result configuration transaction of type 1 (over bridge).
+*
+* INPUT:
+* pciIf - PCI interface number.
+* bus - PCI segment bus number.
+* dev - PCI device number.
+* func - Function number.
+* regOffs - Register offset.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit register data, 0xffffffff on error
+*
+*******************************************************************************/
+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
+ MV_U32 regOff)
+{
+ MV_U32 pciData = 0;
+
+ /* Parameter checking */
+ if (PCI_DEFAULT_IF != pciIf)
+ {
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+ if (dev >= MAX_PCI_DEVICES)
+ {
+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev));
+ return 0xFFFFFFFF;
+ }
+
+ if (func >= MAX_PCI_FUNCS)
+ {
+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func));
+ return 0xFFFFFFFF;
+ }
+
+ if (bus >= MAX_PCI_BUSSES)
+ {
+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus));
+ return MV_ERROR;
+ }
+
+
+ /* Creating PCI address to be passed */
+ pciData |= (bus << PCAR_BUS_NUM_OFFS);
+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS);
+ pciData |= (func << PCAR_FUNC_NUM_OFFS);
+ pciData |= (regOff & PCAR_REG_NUM_MASK);
+
+ pciData |= PCAR_CONFIG_EN;
+
+ /* Write the address to the PCI configuration address register */
+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData);
+
+ /* In order to let the PCI controller absorbed the address of the read */
+ /* transaction we perform a validity check that the address was written */
+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf)))
+ {
+ return MV_ERROR;
+ }
+ /* Read the Data returned in the PCI Data register */
+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf));
+
+ return pciData;
+}
+
+/*******************************************************************************
+* mvPciConfigWrite - Write to configuration space
+*
+* DESCRIPTION:
+* This function performs a 32 bit write to PCI configuration space.
+* It supports both type 0 and type 1 of Configuration Transactions
+* (local and over bridge). In order to write to local bus segment, use
+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers
+* will result configuration transaction of type 1 (over bridge).
+*
+* INPUT:
+* pciIf - PCI interface number.
+* bus - PCI segment bus number.
+* dev - PCI device number.
+* func - Function number.
+* regOffs - Register offset.
+* data - 32bit data.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data)
+{
+ MV_U32 pciData = 0;
+
+ /* Parameter checking */
+ if (PCI_DEFAULT_IF != pciIf)
+ {
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n",
+ pciIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+ if (dev >= MAX_PCI_DEVICES)
+ {
+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev);
+ return MV_BAD_PARAM;
+ }
+
+ if (func >= MAX_PCI_FUNCS)
+ {
+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func);
+ return MV_ERROR;
+ }
+
+ if (bus >= MAX_PCI_BUSSES)
+ {
+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus);
+ return MV_ERROR;
+ }
+
+ /* Creating PCI address to be passed */
+ pciData |= (bus << PCAR_BUS_NUM_OFFS);
+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS);
+ pciData |= (func << PCAR_FUNC_NUM_OFFS);
+ pciData |= (regOff & PCAR_REG_NUM_MASK);
+
+ pciData |= PCAR_CONFIG_EN;
+
+ /* Write the address to the PCI configuration address register */
+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData);
+
+ /* In order to let the PCI controller absorbed the address of the read */
+ /* transaction we perform a validity check that the address was written */
+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf)))
+ {
+ return MV_ERROR;
+ }
+
+ /* Write the Data passed to the PCI Data register */
+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPciMasterEnable - Enable/disale PCI interface master transactions.
+*
+* DESCRIPTION:
+* This function performs read modified write to PCI command status
+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI
+* master is allowed to gain ownership on the bus, otherwise it is
+* incapable to do so.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable)
+{
+ MV_U32 pciCommandStatus;
+ MV_U32 RegOffs;
+ MV_U32 localBus;
+ MV_U32 localDev;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf);
+ return MV_ERROR;
+ }
+
+ localBus = mvPciLocalBusNumGet(pciIf);
+ localDev = mvPciLocalDevNumGet(pciIf);
+
+ RegOffs = PCI_STATUS_AND_COMMAND;
+
+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs);
+
+ if (MV_TRUE == enable)
+ {
+ pciCommandStatus |= PSCR_MASTER_EN;
+ }
+ else
+ {
+ pciCommandStatus &= ~PSCR_MASTER_EN;
+ }
+
+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.
+*
+* DESCRIPTION:
+* This function performs read modified write to PCI command status
+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set,
+* the PCI slave is allowed to respond to PCI IO space access (bit 0)
+* and PCI memory space access (bit 1).
+*
+* INPUT:
+* pciIf - PCI interface number.
+* dev - PCI device number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable)
+{
+ MV_U32 pciCommandStatus;
+ MV_U32 RegOffs;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf);
+ return MV_BAD_PARAM;
+ }
+ if (dev >= MAX_PCI_DEVICES)
+ {
+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev);
+ return MV_BAD_PARAM;
+
+ }
+
+ RegOffs = PCI_STATUS_AND_COMMAND;
+
+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs);
+
+ if (MV_TRUE == enable)
+ {
+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN);
+ }
+ else
+ {
+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN);
+ }
+
+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPciLocalBusNumSet - Set PCI interface local bus number.
+*
+* DESCRIPTION:
+* This function sets given PCI interface its local bus number.
+* Note: In case the PCI interface is PCI-X, the information is read-only.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* busNum - Bus number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_NOT_ALLOWED in case PCI interface is PCI-X.
+* MV_BAD_PARAM on bad parameters ,
+* otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum)
+{
+ MV_U32 pciP2PConfig;
+ MV_PCI_MODE pciMode;
+ MV_U32 localBus;
+ MV_U32 localDev;
+
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf);
+ return MV_BAD_PARAM;
+ }
+ if (busNum >= MAX_PCI_BUSSES)
+ {
+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum);
+ return MV_ERROR;
+
+ }
+
+ localBus = mvPciLocalBusNumGet(pciIf);
+ localDev = mvPciLocalDevNumGet(pciIf);
+
+
+ /* PCI interface mode */
+ mvPciModeGet(pciIf, &pciMode);
+
+ /* if PCI type is PCI-X then it is not allowed to change the dev number */
+ if (MV_PCIX == pciMode.pciType)
+ {
+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS );
+
+ pciP2PConfig &= ~PXS_BN_MASK;
+
+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK;
+
+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig );
+
+ }
+ else
+ {
+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
+
+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK;
+
+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK;
+
+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig);
+
+ }
+
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPciLocalBusNumGet - Get PCI interface local bus number.
+*
+* DESCRIPTION:
+* This function gets the local bus number of a given PCI interface.
+*
+* INPUT:
+* pciIf - PCI interface number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Local bus number.0xffffffff on Error
+*
+*******************************************************************************/
+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf)
+{
+ MV_U32 pciP2PConfig;
+
+ /* Parameter checking */
+ if (PCI_DEFAULT_IF != pciIf)
+ {
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n",
+ pciIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
+ pciP2PConfig &= PPCR_BUS_NUM_MASK;
+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS);
+}
+
+
+/*******************************************************************************
+* mvPciLocalDevNumSet - Set PCI interface local device number.
+*
+* DESCRIPTION:
+* This function sets given PCI interface its local device number.
+* Note: In case the PCI interface is PCI-X, the information is read-only.
+*
+* INPUT:
+* pciIf - PCI interface number.
+* devNum - Device number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters ,
+* otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum)
+{
+ MV_U32 pciP2PConfig;
+ MV_PCI_MODE pciMode;
+ MV_U32 localBus;
+ MV_U32 localDev;
+
+ /* Parameter checking */
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf);
+ return MV_BAD_PARAM;
+ }
+ if (devNum >= MAX_PCI_DEVICES)
+ {
+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n",
+ devNum);
+ return MV_BAD_PARAM;
+
+ }
+
+ localBus = mvPciLocalBusNumGet(pciIf);
+ localDev = mvPciLocalDevNumGet(pciIf);
+
+ /* PCI interface mode */
+ mvPciModeGet(pciIf, &pciMode);
+
+ /* if PCI type is PCIX then it is not allowed to change the dev number */
+ if (MV_PCIX == pciMode.pciType)
+ {
+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS );
+
+ pciP2PConfig &= ~PXS_DN_MASK;
+
+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK;
+
+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig );
+ }
+ else
+ {
+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
+
+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK;
+
+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK;
+
+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig);
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPciLocalDevNumGet - Get PCI interface local device number.
+*
+* DESCRIPTION:
+* This function gets the local device number of a given PCI interface.
+*
+* INPUT:
+* pciIf - PCI interface number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Local device number. 0xffffffff on Error
+*
+*******************************************************************************/
+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf)
+{
+ MV_U32 pciP2PConfig;
+
+ /* Parameter checking */
+
+ if (PCI_DEFAULT_IF != pciIf)
+ {
+ if (pciIf >= mvCtrlPciMaxIfGet())
+ {
+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n",
+ pciIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
+
+ pciP2PConfig &= PPCR_DEV_NUM_MASK;
+
+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS);
+}
+
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h
new file mode 100644
index 000000000..474633627
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h
@@ -0,0 +1,185 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __INCPCIH
+#define __INCPCIH
+
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "pci/mvPciRegs.h"
+
+
+/* NOTE not supported in this driver:
+
+ Built In Self Test (BIST)
+ Vital Product Data (VPD)
+ Message Signaled Interrupt (MSI)
+ Power Management
+ Compact PCI Hot Swap
+ Header retarget
+
+Registers not supported:
+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0)
+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C)
+*/
+
+/* defines */
+/* The number of supported PCI interfaces depend on Marvell controller */
+/* device number. This device number ID is located on the PCI unit */
+/* configuration header. This creates a loop where calling PCI */
+/* configuration read/write routine results a call to get PCI configuration */
+/* information etc. This macro defines a default PCI interface. This PCI */
+/* interface is sure to exist. */
+#define PCI_DEFAULT_IF 0
+
+
+/* typedefs */
+/* The Marvell controller supports both conventional PCI and PCI-X. */
+/* This enumeration describes the PCI type. */
+typedef enum _mvPciType
+{
+ MV_PCI_CONV, /* Conventional PCI */
+ MV_PCIX /* PCI-X */
+}MV_PCI_TYPE;
+
+typedef enum _mvPciMod
+{
+ MV_PCI_MOD_HOST,
+ MV_PCI_MOD_DEVICE
+}MV_PCI_MOD;
+
+
+/* The Marvell controller supports both PCI width of 32 and 64 bit. */
+/* This enumerator describes PCI width */
+typedef enum _mvPciWidth
+{
+ MV_PCI_32, /* PCI width 32bit */
+ MV_PCI_64 /* PCI width 64bit */
+}MV_PCI_WIDTH;
+
+/* This structure describes the PCI unit configured type, speed and width. */
+typedef struct _mvPciMode
+{
+ MV_PCI_TYPE pciType; /* PCI type */
+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */
+ MV_PCI_WIDTH pciWidth; /* PCI bus width */
+}MV_PCI_MODE;
+
+/* mvPciInit - Initialize PCI interfaces*/
+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod);
+
+/* mvPciCommandSet - Set PCI comman register value.*/
+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command);
+
+/* mvPciModeGet - Get PCI interface mode.*/
+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode);
+
+/* mvPciRetrySet - Set PCI retry counters*/
+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter);
+
+/* mvPciDiscardTimerSet - Set PCI discard timer*/
+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles);
+
+/* mvPciArbEnable - PCI arbiter enable/disable*/
+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable);
+
+/* mvPciArbParkDis - Disable arbiter parking on agent */
+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask);
+
+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */
+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles);
+
+/* mvPciConfigRead - Read from configuration space */
+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func,MV_U32 regOff);
+
+/* mvPciConfigWrite - Write to configuration space */
+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data);
+
+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/
+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable);
+
+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/
+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable);
+
+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/
+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum);
+
+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/
+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf);
+
+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/
+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum);
+
+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/
+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf);
+
+
+#endif /* #ifndef __INCPCIH */
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h
new file mode 100644
index 000000000..89d0ef12d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h
@@ -0,0 +1,411 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCPCIREGSH
+#define __INCPCIREGSH
+
+
+#include "pci-if/mvPciIfRegs.h"
+/* defines */
+#define MAX_PCI_DEVICES 32
+#define MAX_PCI_FUNCS 8
+#define MAX_PCI_BUSSES 128
+
+/* enumerators */
+
+/* This enumerator described the possible PCI slave targets. */
+/* PCI slave targets are designated memory/IO address spaces that the */
+/* PCI slave targets can access. They are also refered as "targets" */
+/* this enumeratoe order is determined by the content of :
+ PCI_BASE_ADDR_ENABLE_REG */
+
+
+/* registers offsetes defines */
+
+
+
+/*************************/
+/* PCI control registers */
+/*************************/
+/* maen : should add new registers */
+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80))
+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80))
+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80))
+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80))
+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80))
+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80))
+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \
+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10))
+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \
+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10))
+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \
+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10))
+
+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80))
+
+/* PCI Dll Control (PDC)*/
+#define PDC_DLL_EN BIT0
+
+
+/* PCI Command Register (PCR) */
+#define PCR_MASTER_BYTE_SWAP_EN BIT0
+#define PCR_MASTER_WR_COMBINE_EN BIT4
+#define PCR_MASTER_RD_COMBINE_EN BIT5
+#define PCR_MASTER_WR_TRIG_WHOLE BIT6
+#define PCR_MASTER_RD_TRIG_WHOLE BIT7
+#define PCR_MASTER_MEM_RD_LINE_EN BIT8
+#define PCR_MASTER_MEM_RD_MULT_EN BIT9
+#define PCR_MASTER_WORD_SWAP_EN BIT10
+#define PCR_SLAVE_WORD_SWAP_EN BIT11
+#define PCR_NS_ACCORDING_RCV_TRANS BIT14
+#define PCR_MASTER_PCIX_REQ64N_EN BIT15
+#define PCR_SLAVE_BYTE_SWAP_EN BIT16
+#define PCR_MASTER_DAC_EN BIT17
+#define PCR_MASTER_M64_ALLIGN BIT18
+#define PCR_ERRORS_PROPAGATION_EN BIT19
+#define PCR_SLAVE_SWAP_ENABLE BIT20
+#define PCR_MASTER_SWAP_ENABLE BIT21
+#define PCR_MASTER_INT_SWAP_EN BIT22
+#define PCR_LOOP_BACK_ENABLE BIT23
+#define PCR_SLAVE_INTREG_SWAP_OFFS 24
+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3
+#define PCR_SLAVE_INTREG_BYTE_SWAP \
+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
+#define PCR_SLAVE_INTREG_NO_SWAP \
+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
+#define PCR_SLAVE_INTREG_BYTE_WORD \
+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
+#define PCR_SLAVE_INTREG_WORD_SWAP \
+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
+#define PCR_RESET_REASSERTION_EN BIT26
+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28
+#define PCR_CPU_TO_PCI_ORDER_EN BIT29
+#define PCR_PCI_TO_CPU_ORDER_EN BIT30
+
+/* PCI Mode Register (PMR) */
+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */
+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS)
+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS)
+
+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */
+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS)
+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS)
+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS)
+
+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */
+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS)
+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS)
+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS)
+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS)
+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS)
+
+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */
+
+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */
+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS)
+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS)
+
+
+/* PCI Retry Register (PRR) */
+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */
+#define PRR_RETRY_CNTR_MAX 0xff
+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS)
+
+
+/* PCI Discard Timer Register (PDTR) */
+#define PDTR_TIMER_OFFS 0 /* Timer */
+#define PDTR_TIMER_MAX 0xffff
+#define PDTR_TIMER_MIN 0x7F
+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS)
+
+
+/* PCI Arbiter Control Register (PACR) */
+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */
+
+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */
+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS)
+#define PACR_BROKEN_VAL_CONV_MIN 0x2
+#define PACR_BROKEN_VAL_PCIX_MIN 0x6
+
+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */
+#define PACR_PARK_DIS_MAX_AGENT 0x3f
+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<<PACR_PARK_DIS_OFFS)
+#define PACR_PARK_DIS(agent) ((1 << (agent)) << PACR_PARK_DIS_OFFS)
+
+#define PACR_ARB_ENABLE BIT31 /* Enable Internal Arbiter */
+
+
+/* PCI P2P Configuration Register (PPCR) */
+#define PPCR_2ND_BUS_L_OFFS 0 /* 2nd PCI Interface Bus Range Lower */
+#define PPCR_2ND_BUS_L_MASK (0xff << PPCR_2ND_BUS_L_OFFS)
+
+#define PPCR_2ND_BUS_H_OFFS 8 /* 2nd PCI Interface Bus Range Upper */
+#define PPCR_2ND_BUS_H_MASK (0xff << PPCR_2ND_BUS_H_OFFS)
+
+#define PPCR_BUS_NUM_OFFS 16 /* The PCI interface's Bus number */
+#define PPCR_BUS_NUM_MASK (0xff << PPCR_BUS_NUM_OFFS)
+
+#define PPCR_DEV_NUM_OFFS 24 /* The PCI interface’s Device number */
+#define PPCR_DEV_NUM_MASK (0xff << PPCR_DEV_NUM_OFFS)
+
+
+/* PCI Access Control Base Low Register (PACBLR) */
+#define PACBLR_EN BIT0 /* Access control window enable */
+
+#define PACBLR_ACCPROT BIT4 /* Access Protect */
+#define PACBLR_WRPROT BIT5 /* Write Protect */
+
+#define PACBLR_PCISWAP_OFFS 6 /* PCI slave Data Swap Control */
+#define PACBLR_PCISWAP_MASK (0x3 << PACBLR_PCISWAP_OFFS)
+#define PACBLR_PCISWAP_BYTE (0x0 << PACBLR_PCISWAP_OFFS)
+#define PACBLR_PCISWAP_NO_SWAP (0x1 << PACBLR_PCISWAP_OFFS)
+#define PACBLR_PCISWAP_BYTE_WORD (0x2 << PACBLR_PCISWAP_OFFS)
+#define PACBLR_PCISWAP_WORD (0x3 << PACBLR_PCISWAP_OFFS)
+
+#define PACBLR_RDMBURST_OFFS 8 /* Read Max Burst */
+#define PACBLR_RDMBURST_MASK (0x3 << PACBLR_RDMBURST_OFFS)
+#define PACBLR_RDMBURST_32BYTE (0x0 << PACBLR_RDMBURST_OFFS)
+#define PACBLR_RDMBURST_64BYTE (0x1 << PACBLR_RDMBURST_OFFS)
+#define PACBLR_RDMBURST_128BYTE (0x2 << PACBLR_RDMBURST_OFFS)
+
+#define PACBLR_RDSIZE_OFFS 10 /* Typical PCI read transaction Size. */
+#define PACBLR_RDSIZE_MASK (0x3 << PACBLR_RDSIZE_OFFS)
+#define PACBLR_RDSIZE_32BYTE (0x0 << PACBLR_RDSIZE_OFFS)
+#define PACBLR_RDSIZE_64BYTE (0x1 << PACBLR_RDSIZE_OFFS)
+#define PACBLR_RDSIZE_128BYTE (0x2 << PACBLR_RDSIZE_OFFS)
+#define PACBLR_RDSIZE_256BYTE (0x3 << PACBLR_RDSIZE_OFFS)
+
+#define PACBLR_BASE_L_OFFS 12 /* Corresponds to address bits [31:12] */
+#define PACBLR_BASE_L_MASK (0xfffff << PACBLR_BASE_L_OFFS)
+#define PACBLR_BASE_L_ALIGNMENT (1 << PACBLR_BASE_L_OFFS)
+#define PACBLR_BASE_ALIGN_UP(base) \
+ ((base+PACBLR_BASE_L_ALIGNMENT)&PACBLR_BASE_L_MASK)
+#define PACBLR_BASE_ALIGN_DOWN(base) (base & PACBLR_BASE_L_MASK)
+
+
+/* PCI Access Control Base High Register (PACBHR) */
+#define PACBHR_BASE_H_OFFS 0 /* Corresponds to address bits [63:32] */
+#define PACBHR_CTRL_BASE_H_MASK (0xffffffff << PACBHR_BASE_H_OFFS)
+
+/* PCI Access Control Size Register (PACSR) */
+#define PACSR_WRMBURST_OFFS 8 /* Write Max Burst */
+#define PACSR_WRMBURST_MASK (0x3 << PACSR_WRMBURST_OFFS)
+#define PACSR_WRMBURST_32BYTE (0x0 << PACSR_WRMBURST_OFFS)
+#define PACSR_WRMBURST_64BYTE (0x1 << PACSR_WRMBURST_OFFS)
+#define PACSR_WRMBURST_128BYTE (0x2 << PACSR_WRMBURST_OFFS)
+
+#define PACSR_PCI_ORDERING BIT11 /* PCI Ordering required */
+
+#define PACSR_SIZE_OFFS 12 /* PCI access window size */
+#define PACSR_SIZE_MASK (0xfffff << PACSR_SIZE_OFFS)
+#define PACSR_SIZE_ALIGNMENT (1 << PACSR_SIZE_OFFS)
+#define PACSR_SIZE_ALIGN_UP(size) \
+ ((size+PACSR_SIZE_ALIGNMENT)&PACSR_SIZE_MASK)
+#define PACSR_SIZE_ALIGN_DOWN(size) (size & PACSR_SIZE_MASK)
+
+
+/***************************************/
+/* PCI Configuration Access Registers */
+/***************************************/
+
+#define PCI_CONFIG_ADDR_REG(pciIf) (0x30C78 - ((pciIf) * 0x80) )
+#define PCI_CONFIG_DATA_REG(pciIf) (0x30C7C - ((pciIf) * 0x80) )
+#define PCI_INT_ACK_REG(pciIf) (0x30C34 + ((pciIf) * 0x80) )
+
+/* PCI Configuration Address Register (PCAR) */
+#define PCAR_REG_NUM_OFFS 2
+#define PCAR_REG_NUM_MASK (0x3F << PCAR_REG_NUM_OFFS)
+
+#define PCAR_FUNC_NUM_OFFS 8
+#define PCAR_FUNC_NUM_MASK (0x7 << PCAR_FUNC_NUM_OFFS)
+
+#define PCAR_DEVICE_NUM_OFFS 11
+#define PCAR_DEVICE_NUM_MASK (0x1F << PCAR_DEVICE_NUM_OFFS)
+
+#define PCAR_BUS_NUM_OFFS 16
+#define PCAR_BUS_NUM_MASK (0xFF << PCAR_BUS_NUM_OFFS)
+
+#define PCAR_CONFIG_EN BIT31
+
+
+/***************************************/
+/* PCI Configuration registers */
+/***************************************/
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers */
+/*********************************************/
+
+/* Marvell Specific */
+#define PCI_SCS0_BASE_ADDR_LOW 0x010
+#define PCI_SCS0_BASE_ADDR_HIGH 0x014
+#define PCI_SCS1_BASE_ADDR_LOW 0x018
+#define PCI_SCS1_BASE_ADDR_HIGH 0x01C
+#define PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_L 0x020
+#define PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_H 0x024
+
+/* capability list */
+#define PCI_POWER_MNG_CAPABILITY 0x040
+#define PCI_POWER_MNG_STATUS_CONTROL 0x044
+#define PCI_VPD_ADDRESS_REG 0x048
+#define PCI_VPD_DATA_REG 0x04c
+#define PCI_MSI_MESSAGE_CONTROL 0x050
+#define PCI_MSI_MESSAGE_ADDR 0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058
+#define PCI_MSI_MESSAGE_DATA 0x05c
+#define PCIX_COMMAND 0x060
+#define PCIX_STATUS 0x064
+#define PCI_COMPACT_PCI_HOT_SWAP 0x068
+
+
+/*********************************************/
+/* PCI Configuration, Function 1, Registers */
+/*********************************************/
+
+#define PCI_SCS2_BASE_ADDR_LOW 0x10
+#define PCI_SCS2_BASE_ADDR_HIGH 0x14
+#define PCI_SCS3_BASE_ADDR_LOW 0x18
+#define PCI_SCS3_BASE_ADDR_HIGH 0x1c
+
+
+/***********************************************/
+/* PCI Configuration, Function 2, Registers */
+/***********************************************/
+
+#define PCI_DEVCS0_BASE_ADDR_LOW 0x10
+#define PCI_DEVCS0_BASE_ADDR_HIGH 0x14
+#define PCI_DEVCS1_BASE_ADDR_LOW 0x18
+#define PCI_DEVCS1_BASE_ADDR_HIGH 0x1c
+#define PCI_DEVCS2_BASE_ADDR_LOW 0x20
+#define PCI_DEVCS2_BASE_ADDR_HIGH 0x24
+
+/***********************************************/
+/* PCI Configuration, Function 3, Registers */
+/***********************************************/
+
+#define PCI_BOOTCS_BASE_ADDR_LOW 0x18
+#define PCI_BOOTCS_BASE_ADDR_HIGH 0x1c
+
+/***********************************************/
+/* PCI Configuration, Function 4, Registers */
+/***********************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x10
+#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x14
+#define PCI_P2P_IO_BASE_ADDR 0x20
+#define PCI_INTER_REGS_IO_MAPPED_BASE_ADDR 0x24
+
+/* PCIX_STATUS register fields (PXS) */
+
+#define PXS_FN_OFFS 0 /* Description Number */
+#define PXS_FN_MASK (0x7 << PXS_FN_OFFS)
+
+#define PXS_DN_OFFS 3 /* Device Number */
+#define PXS_DN_MASK (0x1f << PXS_DN_OFFS)
+
+#define PXS_BN_OFFS 8 /* Bus Number */
+#define PXS_BN_MASK (0xff << PXS_BN_OFFS)
+
+
+/* PCI Error Report Register Map */
+#define PCI_SERRN_MASK_REG(pciIf) (0x30c28 + (pciIf * 0x80))
+#define PCI_CAUSE_REG(pciIf) (0x31d58 + (pciIf * 0x80))
+#define PCI_MASK_REG(pciIf) (0x31d5C + (pciIf * 0x80))
+#define PCI_ERROR_ADDR_LOW_REG(pciIf) (0x31d40 + (pciIf * 0x80))
+#define PCI_ERROR_ADDR_HIGH_REG(pciIf) (0x31d44 + (pciIf * 0x80))
+#define PCI_ERROR_ATTRIBUTE_REG(pciIf) (0x31d48 + (pciIf * 0x80))
+#define PCI_ERROR_COMMAND_REG(pciIf) (0x31d50 + (pciIf * 0x80))
+
+/* PCI Interrupt Cause Register (PICR) */
+#define PICR_ERR_SEL_OFFS 27
+#define PICR_ERR_SEL_MASK (0x1f << PICR_ERR_SEL_OFFS)
+
+/* PCI Error Command Register (PECR) */
+#define PECR_ERR_CMD_OFFS 0
+#define PECR_ERR_CMD_MASK (0xf << PECR_ERR_CMD_OFFS)
+#define PECR_DAC BIT4
+
+
+/* defaults */
+/* Set bits means value is about to change according to new value */
+#define PCI_COMMAND_DEFAULT_MASK 0xffffdff1
+#define PCI_COMMAND_DEFAULT \
+ (PCR_MASTER_WR_TRIG_WHOLE | \
+ PCR_MASTER_RD_TRIG_WHOLE | \
+ PCR_MASTER_MEM_RD_LINE_EN | \
+ PCR_MASTER_MEM_RD_MULT_EN | \
+ PCR_NS_ACCORDING_RCV_TRANS | \
+ PCR_MASTER_PCIX_REQ64N_EN | \
+ PCR_MASTER_DAC_EN | \
+ PCR_MASTER_M64_ALLIGN | \
+ PCR_ERRORS_PROPAGATION_EN)
+
+
+#define PCI_ARBITER_CTRL_DEFAULT_MASK 0x801fc07a
+#define PCI_ARBITER_CTRL_DEFAULT \
+ (PACR_BROKEN_VAL_PCIX_MIN << PACR_BROKEN_VAL_OFFS)
+
+
+#endif /* #ifndef __INCPCIREGSH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt
new file mode 100644
index 000000000..38a926440
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.4
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c
new file mode 100644
index 000000000..068aac2bf
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c
@@ -0,0 +1,1143 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "pex/mvPex.h"
+
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/* defines */
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType)
+{
+ MV_PEX_MODE pexMode;
+ MV_U32 regVal;
+ MV_U32 status;
+
+ /* First implement Guideline (GL# PCI Express-2) Wrong Default Value */
+ /* to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 */
+ /* and 88F5281-B0 and above, 88F5182, 88F5082, 88F5181L, 88F6082/L */
+
+ if ((mvCtrlModelGet() != MV_1281_DEV_ID) &&
+ (mvCtrlModelGet() != MV_6281_DEV_ID) &&
+ (mvCtrlModelGet() != MV_6192_DEV_ID) &&
+ (mvCtrlModelGet() != MV_6190_DEV_ID) &&
+ (mvCtrlModelGet() != MV_6180_DEV_ID) &&
+ (mvCtrlModelGet() != MV_6183_DEV_ID) &&
+ (mvCtrlModelGet() != MV_6183L_DEV_ID) &&
+ (mvCtrlModelGet() != MV_78100_DEV_ID) &&
+ (mvCtrlModelGet() != MV_78200_DEV_ID) &&
+ (mvCtrlModelGet() != MV_76100_DEV_ID) &&
+ (mvCtrlModelGet() != MV_78XX0_DEV_ID))
+ {
+
+ /* Read current value of TXAMP */
+ MV_REG_WRITE(0x41b00, 0x80820000); /* Write the read command */
+
+ regVal = MV_REG_READ(0x41b00); /* Extract the data */
+
+ /* Prepare new data for write */
+ regVal &= ~0x7; /* Clear bits [2:0] */
+ regVal |= 0x4; /* Set the new value */
+ regVal &= ~0x80000000; /* Set "write" command */
+ MV_REG_WRITE(0x41b00, regVal); /* Write the write command */
+
+ }
+ else
+ {
+ /* Implement 1.0V termination GL for 88F1281 device only */
+ /* BIT0 - Common mode feedback */
+ /* BIT3 - TxBuf, extra drive for 1.0V termination */
+ if (mvCtrlModelGet() == MV_1281_DEV_ID)
+ {
+ MV_REG_WRITE(0x41b00, 0x80860000); /* Write the read command */
+ regVal = MV_REG_READ(0x41b00); /* Extract the data */
+ regVal |= (BIT0 | BIT3);
+ regVal &= ~0x80000000; /* Set "write" command */
+ MV_REG_WRITE(0x41b00, regVal); /* Write the write command */
+
+ MV_REG_WRITE(0x31b00, 0x80860000); /* Write the read command */
+ regVal = MV_REG_READ(0x31b00); /* Extract the data */
+ regVal |= (BIT0 | BIT3);
+ regVal &= ~0x80000000; /* Set "write" command */
+ MV_REG_WRITE(0x31b00, regVal); /* Write the write command */
+ }
+ }
+
+ if( mvPexModeGet(pexIf, &pexMode) != MV_OK)
+ {
+ mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n",pexMode.pexType);
+ return MV_ERROR;
+ }
+
+ /* Check that required PEX type is the one set in reset time */
+ if (pexType != pexMode.pexType)
+ {
+ /* No Link. Shut down the Phy */
+ mvPexPowerDown(pexIf);
+ mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n",pexType,pexMode.pexType);
+ return MV_ERROR;
+ }
+
+ if (MV_PEX_ROOT_COMPLEX == pexType)
+ {
+ mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf));
+ mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf));
+
+ /* Local device master Enable */
+ mvPexMasterEnable(pexIf, MV_TRUE);
+
+ /* Local device slave Enable */
+ mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf),
+ mvPexLocalDevNumGet(pexIf), MV_TRUE);
+ /* Interrupt disable */
+ status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND));
+ status |= PXSAC_INT_DIS;
+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status);
+ }
+
+ /* now wait 500 ms to be sure the link is valid (spec compliant) */
+ mvOsDelay(500);
+ /* Check if we have link */
+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN)
+ {
+ mvOsPrintf("PEX%d interface detected no Link.\n",pexIf);
+ return MV_NO_SUCH;
+ }
+
+ if (MV_PEX_WITDH_X1 == pexMode.pexWidth)
+ {
+ mvOsPrintf("PEX%d interface detected Link X1\n",pexIf);
+ }
+ else
+ {
+ mvOsPrintf("PEX%d interface detected Link X4\n",pexIf);
+ }
+
+#ifdef PCIE_VIRTUAL_BRIDGE_SUPPORT
+ mvPexVrtBrgInit(pexIf);
+#endif
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPexModeGet - Get Pex Mode
+*
+* DESCRIPTION:
+*
+* INPUT:
+* pexIf - PEX interface number.
+*
+* OUTPUT:
+* pexMode - Pex mode structure
+*
+* RETURN:
+* MV_OK on success , MV_ERROR otherwise
+*
+*******************************************************************************/
+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode)
+{
+ MV_U32 pexData;
+
+ /* Parameter checking */
+ if (PEX_DEFAULT_IF != pexIf)
+ {
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf);
+ return MV_ERROR;
+ }
+ }
+
+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf));
+
+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK)
+ {
+ case PXCR_DEV_TYPE_CTRL_CMPLX:
+ pexMode->pexType = MV_PEX_ROOT_COMPLEX;
+ break;
+ case PXCR_DEV_TYPE_CTRL_POINT:
+ pexMode->pexType = MV_PEX_END_POINT;
+ break;
+
+ }
+
+ /* Check if we have link */
+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN)
+ {
+ pexMode->pexLinkUp = MV_FALSE;
+
+ /* If there is no link, the auto negotiation data is worthless */
+ pexMode->pexWidth = MV_PEX_WITDH_INVALID;
+ }
+ else
+ {
+ pexMode->pexLinkUp = MV_TRUE;
+
+ /* We have link. The link width is now valid */
+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG));
+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >>
+ PXLCSR_NEG_LNK_WDTH_OFFS);
+ }
+
+ return MV_OK;
+}
+
+
+/* PEX configuration space read write */
+
+/*******************************************************************************
+* mvPexConfigRead - Read from configuration space
+*
+* DESCRIPTION:
+* This function performs a 32 bit read from PEX configuration space.
+* It supports both type 0 and type 1 of Configuration Transactions
+* (local and over bridge). In order to read from local bus segment, use
+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
+* will result configuration transaction of type 1 (over bridge).
+*
+* INPUT:
+* pexIf - PEX interface number.
+* bus - PEX segment bus number.
+* dev - PEX device number.
+* func - Function number.
+* regOffs - Register offset.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit register data, 0xffffffff on error
+*
+*******************************************************************************/
+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
+ MV_U32 regOff)
+{
+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT)
+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff);
+}
+
+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
+ MV_U32 regOff)
+{
+#endif
+ MV_U32 pexData = 0;
+ MV_U32 localDev,localBus;
+
+ /* Parameter checking */
+ if (PEX_DEFAULT_IF != pexIf)
+ {
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+ if (dev >= MAX_PEX_DEVICES)
+ {
+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev));
+ return 0xFFFFFFFF;
+ }
+
+ if (func >= MAX_PEX_FUNCS)
+ {
+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func));
+ return 0xFFFFFFFF;
+ }
+
+ if (bus >= MAX_PEX_BUSSES)
+ {
+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus));
+ return MV_ERROR;
+ }
+
+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n",
+ pexIf, bus, dev, func, regOff));
+
+ localDev = mvPexLocalDevNumGet(pexIf);
+ localBus = mvPexLocalBusNumGet(pexIf);
+
+ /* Speed up the process. In case on no link, return MV_ERROR */
+ if ((dev != localDev) || (bus != localBus))
+ {
+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf));
+
+ if ((pexData & PXSR_DL_DOWN))
+ {
+ return MV_ERROR;
+ }
+ }
+
+ /* in PCI Express we have only one device number */
+ /* and this number is the first number we encounter
+ else that the localDev*/
+ /* spec pex define return on config read/write on any device */
+ if (bus == localBus)
+ {
+ if (localDev == 0)
+ {
+ /* if local dev is 0 then the first number we encounter
+ after 0 is 1 */
+ if ((dev != 1)&&(dev != localDev))
+ {
+ return MV_ERROR;
+ }
+ }
+ else
+ {
+ /* if local dev is not 0 then the first number we encounter
+ is 0 */
+
+ if ((dev != 0)&&(dev != localDev))
+ {
+ return MV_ERROR;
+ }
+ }
+ if(func != 0 ) /* i.e bridge */
+ {
+ return MV_ERROR;
+ }
+ }
+
+
+ /* Creating PEX address to be passed */
+ pexData = (bus << PXCAR_BUS_NUM_OFFS);
+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS);
+ pexData |= (func << PXCAR_FUNC_NUM_OFFS);
+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */
+ /* extended register space */
+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >>
+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
+
+ pexData |= PXCAR_CONFIG_EN;
+
+ /* Write the address to the PEX configuration address register */
+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData);
+
+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData));
+
+
+ /* In order to let the PEX controller absorbed the address of the read */
+ /* transaction we perform a validity check that the address was written */
+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf)))
+ {
+ return MV_ERROR;
+ }
+
+ /* cleaning Master Abort */
+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND),
+ PXSAC_MABORT);
+#if 0
+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */
+ /* This guideline is relevant for all devices except of the following devices:
+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above
+ 88F6183 A0 and above, 88F6183L */
+ if ( ( (dev != localDev) || (bus != localBus) ) &&
+ (
+ !(MV_5281_DEV_ID == mvCtrlModelGet())&&
+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&&
+ !(MV_1281_DEV_ID == mvCtrlModelGet())&&
+ !(MV_6183_DEV_ID == mvCtrlModelGet())&&
+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&&
+ !(MV_6281_DEV_ID == mvCtrlModelGet())&&
+ !(MV_6192_DEV_ID == mvCtrlModelGet())&&
+ !(MV_6190_DEV_ID == mvCtrlModelGet())&&
+ !(MV_6180_DEV_ID == mvCtrlModelGet())&&
+ !(MV_78XX0_DEV_ID == mvCtrlModelGet())
+ ))
+ {
+
+ /* PCI-Express configuration read work-around */
+
+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar
+ and read the data from there */
+ /*
+ Need to configure the 2 free Punit (AHB to MBus bridge)
+ address decoding windows:
+ Configure the flash Window to handle Configuration space requests
+ for PEX0/1:
+ 1. write 0x7931/0x7941 to the flash window and the size,
+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn
+ 2. write base to flash window
+
+ Configuration transactions from the CPU should write/read the data
+ to/from address of the form:
+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1)
+ addr[27:24] = extended register number
+ addr[23:16] = bus number
+ addr[15:11] = device number
+ addr[10:8] = function number
+ addr[7:0] = register number
+ */
+
+ #include "ctrlEnv/sys/mvAhbToMbus.h"
+ {
+ MV_U32 winNum;
+ MV_AHB_TO_MBUS_DEC_WIN originWin;
+ MV_U32 pciAddr=0;
+ MV_U32 remapLow=0,remapHigh=0;
+
+ /*
+ We will use DEV_CS2\Flash window for this workarround
+ */
+
+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET);
+
+ /* save remap values if exist */
+ if ((1 == winNum)||(0 == winNum))
+ {
+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum));
+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum));
+
+ }
+
+
+ /* save the original window values */
+ mvAhbToMbusWinGet(winNum,&originWin);
+
+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES)
+ {
+ /* set the window as xbar window */
+ if (pexIf)
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum),
+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16));
+ }
+ else
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum),
+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16));
+ }
+
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum),
+ originWin.addrWin.baseLow);
+
+ /*pciAddr = originWin.addrWin.baseLow;*/
+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(
+ (MV_U32)originWin.addrWin.baseLow);
+
+ }
+ else
+ {
+ /* set the window as xbar window */
+ if (pexIf)
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum),
+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16));
+ }
+ else
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum),
+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16));
+ }
+
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum),
+ PEX_CONFIG_RW_WA_BASE);
+
+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE);
+ }
+
+
+ /* remap should be as base */
+ if ((1 == winNum)||(0 == winNum))
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr);
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0);
+
+ }
+
+ /* extended register space */
+ pciAddr |= (bus << 16);
+ pciAddr |= (dev << 11);
+ pciAddr |= (func << 8);
+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */
+
+ pexData = *(MV_U32*)pciAddr;
+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */
+
+ /* restore the original window values */
+ mvAhbToMbusWinSet(winNum,&originWin);
+
+ /* restore original remap values*/
+ if ((1 == winNum)||(0 == winNum))
+ {
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow);
+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh);
+
+ }
+ }
+ }
+ else
+#endif
+ {
+ /* Read the Data returned in the PEX Data register */
+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf));
+
+ }
+
+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData));
+
+ return pexData;
+
+}
+
+/*******************************************************************************
+* mvPexConfigWrite - Write to configuration space
+*
+* DESCRIPTION:
+* This function performs a 32 bit write to PEX configuration space.
+* It supports both type 0 and type 1 of Configuration Transactions
+* (local and over bridge). In order to write to local bus segment, use
+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
+* will result configuration transaction of type 1 (over bridge).
+*
+* INPUT:
+* pexIf - PEX interface number.
+* bus - PEX segment bus number.
+* dev - PEX device number.
+* func - Function number.
+* regOffs - Register offset.
+* data - 32bit data.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data)
+{
+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT)
+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data);
+}
+
+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data)
+{
+#endif
+ MV_U32 pexData = 0;
+ MV_U32 localDev,localBus;
+
+ /* Parameter checking */
+ if (PEX_DEFAULT_IF != pexIf)
+ {
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n",
+ pexIf);
+ return MV_ERROR;
+ }
+ }
+
+ if (dev >= MAX_PEX_DEVICES)
+ {
+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev);
+ return MV_BAD_PARAM;
+ }
+
+ if (func >= MAX_PEX_FUNCS)
+ {
+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func);
+ return MV_ERROR;
+ }
+
+ if (bus >= MAX_PEX_BUSSES)
+ {
+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus);
+ return MV_ERROR;
+ }
+
+
+
+ localDev = mvPexLocalDevNumGet(pexIf);
+ localBus = mvPexLocalBusNumGet(pexIf);
+
+
+ /* in PCI Express we have only one device number other than ourselves*/
+ /* and this number is the first number we encounter
+ else than the localDev that can be any valid dev number*/
+ /* pex spec define return on config read/write on any device */
+ if (bus == localBus)
+ {
+
+ if (localDev == 0)
+ {
+ /* if local dev is 0 then the first number we encounter
+ after 0 is 1 */
+ if ((dev != 1)&&(dev != localDev))
+ {
+ return MV_ERROR;
+ }
+
+ }
+ else
+ {
+ /* if local dev is not 0 then the first number we encounter
+ is 0 */
+
+ if ((dev != 0)&&(dev != localDev))
+ {
+ return MV_ERROR;
+ }
+ }
+
+
+ }
+
+ /* if we are not accessing ourselves , then check the link */
+ if ((dev != localDev) || (bus != localBus) )
+ {
+ /* workarround */
+ /* when no link return MV_ERROR */
+
+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf));
+
+ if ((pexData & PXSR_DL_DOWN))
+ {
+ return MV_ERROR;
+ }
+
+ }
+
+ pexData =0;
+
+ /* Creating PEX address to be passed */
+ pexData |= (bus << PXCAR_BUS_NUM_OFFS);
+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS);
+ pexData |= (func << PXCAR_FUNC_NUM_OFFS);
+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */
+ /* extended register space */
+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >>
+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
+ pexData |= PXCAR_CONFIG_EN;
+
+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n",
+ pexIf,bus,func,dev,regOff,data,pexData) );
+
+ /* Write the address to the PEX configuration address register */
+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData);
+
+ /* Clear CPU pipe. Important where CPU can perform OOO execution */
+ CPU_PIPE_FLUSH;
+
+ /* In order to let the PEX controller absorbed the address of the read */
+ /* transaction we perform a validity check that the address was written */
+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf)))
+ {
+ return MV_ERROR;
+ }
+
+ /* Write the Data passed to the PEX Data register */
+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data);
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvPexMasterEnable - Enable/disale PEX interface master transactions.
+*
+* DESCRIPTION:
+* This function performs read modified write to PEX command status
+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX
+* master is allowed to gain ownership on the bus, otherwise it is
+* incapable to do so.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable)
+{
+ MV_U32 pexCommandStatus;
+ MV_U32 localBus;
+ MV_U32 localDev;
+
+ /* Parameter checking */
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_ERROR;
+ }
+
+ localBus = mvPexLocalBusNumGet(pexIf);
+ localDev = mvPexLocalDevNumGet(pexIf);
+
+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,
+ PEX_STATUS_AND_COMMAND));
+
+
+ if (MV_TRUE == enable)
+ {
+ pexCommandStatus |= PXSAC_MASTER_EN;
+ }
+ else
+ {
+ pexCommandStatus &= ~PXSAC_MASTER_EN;
+ }
+
+
+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND),
+ pexCommandStatus);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.
+*
+* DESCRIPTION:
+* This function performs read modified write to PEX command status
+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set,
+* the PEX slave is allowed to respond to PEX IO space access (bit 0)
+* and PEX memory space access (bit 1).
+*
+* INPUT:
+* pexIf - PEX interface number.
+* dev - PEX device number.
+* enable - Enable/disable parameter.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable)
+{
+ MV_U32 pexCommandStatus;
+ MV_U32 RegOffs;
+
+ /* Parameter checking */
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+ if (dev >= MAX_PEX_DEVICES)
+ {
+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev);
+ return MV_BAD_PARAM;
+
+ }
+
+
+ RegOffs = PEX_STATUS_AND_COMMAND;
+
+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs);
+
+ if (MV_TRUE == enable)
+ {
+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN);
+ }
+ else
+ {
+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN);
+ }
+
+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus);
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvPexLocalBusNumSet - Set PEX interface local bus number.
+*
+* DESCRIPTION:
+* This function sets given PEX interface its local bus number.
+* Note: In case the PEX interface is PEX-X, the information is read-only.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* busNum - Bus number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_NOT_ALLOWED in case PEX interface is PEX-X.
+* MV_BAD_PARAM on bad parameters ,
+* otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum)
+{
+ MV_U32 pexStatus;
+ MV_U32 localBus;
+ MV_U32 localDev;
+
+
+ /* Parameter checking */
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf);
+ return MV_BAD_PARAM;
+ }
+ if (busNum >= MAX_PEX_BUSSES)
+ {
+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum);
+ return MV_ERROR;
+
+ }
+
+ localBus = mvPexLocalBusNumGet(pexIf);
+ localDev = mvPexLocalDevNumGet(pexIf);
+
+
+
+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf));
+
+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK;
+
+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
+
+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus);
+
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPexLocalBusNumGet - Get PEX interface local bus number.
+*
+* DESCRIPTION:
+* This function gets the local bus number of a given PEX interface.
+*
+* INPUT:
+* pexIf - PEX interface number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Local bus number.0xffffffff on Error
+*
+*******************************************************************************/
+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf)
+{
+ MV_U32 pexStatus;
+
+ /* Parameter checking */
+ if (PEX_DEFAULT_IF != pexIf)
+ {
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+
+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf));
+
+ pexStatus &= PXSR_PEX_BUS_NUM_MASK;
+
+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS);
+
+}
+
+
+/*******************************************************************************
+* mvPexLocalDevNumSet - Set PEX interface local device number.
+*
+* DESCRIPTION:
+* This function sets given PEX interface its local device number.
+* Note: In case the PEX interface is PEX-X, the information is read-only.
+*
+* INPUT:
+* pexIf - PEX interface number.
+* devNum - Device number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_NOT_ALLOWED in case PEX interface is PEX-X.
+* MV_BAD_PARAM on bad parameters ,
+* otherwise MV_OK
+*
+*******************************************************************************/
+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum)
+{
+ MV_U32 pexStatus;
+ MV_U32 localBus;
+ MV_U32 localDev;
+
+ /* Parameter checking */
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf);
+ return MV_BAD_PARAM;
+ }
+ if (devNum >= MAX_PEX_DEVICES)
+ {
+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n",
+ devNum);
+ return MV_BAD_PARAM;
+
+ }
+
+ localBus = mvPexLocalBusNumGet(pexIf);
+ localDev = mvPexLocalDevNumGet(pexIf);
+
+
+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf));
+
+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK;
+
+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
+
+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus);
+
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvPexLocalDevNumGet - Get PEX interface local device number.
+*
+* DESCRIPTION:
+* This function gets the local device number of a given PEX interface.
+*
+* INPUT:
+* pexIf - PEX interface number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Local device number. 0xffffffff on Error
+*
+*******************************************************************************/
+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf)
+{
+ MV_U32 pexStatus;
+
+ /* Parameter checking */
+
+ if (PEX_DEFAULT_IF != pexIf)
+ {
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n",
+ pexIf);
+ return 0xFFFFFFFF;
+ }
+ }
+
+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf));
+
+ pexStatus &= PXSR_PEX_DEV_NUM_MASK;
+
+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS);
+}
+
+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value)
+{
+
+ MV_U32 regAddr;
+ if (pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf);
+ return;
+ }
+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16));
+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr);
+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf));
+}
+
+
+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value)
+{
+
+ MV_U32 regAddr;
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf);
+ return;
+ }
+ regAddr = (((regOffset & 0x3fff) << 16) | value);
+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr);
+}
+
+/*******************************************************************************
+* mvPexActiveStateLinkPMEnable
+*
+* DESCRIPTION:
+* Enable Active Link State Power Management
+*
+* INPUT:
+* pexIf - PEX interface number.
+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* MV_OK on success , MV_ERROR otherwise
+*
+*******************************************************************************/
+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable)
+{
+ MV_U32 reg;
+
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_ERROR;
+ }
+
+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK;
+ if(enable == MV_TRUE)
+ reg |= PXPMER_L1_ASPM_EN_MASK;
+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg);
+
+ /* Enable / Disable L0/1 entry */
+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG))
+ & ~PXLCSR_ASPM_CNT_MASK;
+ if(enable == MV_TRUE)
+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP;
+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg);
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvPexForceX1
+*
+* DESCRIPTION:
+* shut down lanes 1-3 if recognize that attached to an x1 end-point
+* INPUT:
+* pexIf - PEX interface number.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* MV_OK on success , MV_ERROR otherwise
+*
+*******************************************************************************/
+MV_U32 mvPexForceX1(MV_U32 pexIf)
+{
+ MV_U32 regData = 0;
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_BAD_PARAM;
+ }
+
+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ;
+ regData |= PXCR_CONF_LINK_X1;
+
+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData);
+ return MV_OK;
+}
+
+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf)
+{
+ if(pexIf >= mvCtrlPexMaxIfGet())
+ {
+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf);
+ return MV_FALSE;
+ }
+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf);
+}
+
+
+MV_VOID mvPexPowerDown(MV_U32 pexIf)
+{
+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) ||
+ (mvCtrlModelGet() == MV_76100_DEV_ID) ||
+ (mvCtrlModelGet() == MV_78100_DEV_ID) ||
+ (mvCtrlModelGet() == MV_78200_DEV_ID) )
+ {
+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE);
+ }
+ else
+ {
+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087);
+ }
+}
+
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h
new file mode 100644
index 000000000..d8f1cdd9f
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h
@@ -0,0 +1,168 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCPEXH
+#define __INCPEXH
+
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "pex/mvPexRegs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+
+
+
+/* NOTE not supported in this driver:*/
+
+
+/* defines */
+/* The number of supported PEX interfaces depend on Marvell controller */
+/* device number. This device number ID is located on the PEX unit */
+/* configuration header. This creates a loop where calling PEX */
+/* configuration read/write routine results a call to get PEX configuration */
+/* information etc. This macro defines a default PEX interface. This PEX */
+/* interface is sure to exist. */
+#define PEX_DEFAULT_IF 0
+
+
+/* typedefs */
+/* The Marvell controller supports both root complex and end point devices */
+/* This enumeration describes the PEX type. */
+typedef enum _mvPexType
+{
+ MV_PEX_ROOT_COMPLEX, /* root complex device */
+ MV_PEX_END_POINT /* end point device */
+}MV_PEX_TYPE;
+
+typedef enum _mvPexWidth
+{
+ MV_PEX_WITDH_X1 = 1,
+ MV_PEX_WITDH_X2,
+ MV_PEX_WITDH_X3,
+ MV_PEX_WITDH_X4,
+ MV_PEX_WITDH_INVALID
+}MV_PEX_WIDTH;
+
+/* PEX Bar attributes */
+typedef struct _mvPexMode
+{
+ MV_PEX_TYPE pexType;
+ MV_PEX_WIDTH pexWidth;
+ MV_BOOL pexLinkUp;
+}MV_PEX_MODE;
+
+
+
+/* Global Functions prototypes */
+/* mvPexInit - Initialize PEX interfaces*/
+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType);
+
+/* mvPexModeGet - Get Pex If mode */
+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode);
+
+/* mvPexConfigRead - Read from configuration space */
+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func,MV_U32 regOff);
+
+/* mvPexConfigWrite - Write to configuration space */
+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data);
+
+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/
+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable);
+
+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/
+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable);
+
+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/
+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum);
+
+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/
+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf);
+
+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/
+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum);
+
+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/
+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf);
+/* mvPexForceX1 - Force PEX interface to X1 mode. */
+MV_U32 mvPexForceX1(MV_U32 pexIf);
+
+/* mvPexIsPowerUp - Is PEX interface Power up? */
+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf);
+
+/* mvPexPowerDown - Power Down */
+MV_VOID mvPexPowerDown(MV_U32 pexIf);
+
+/* mvPexPowerUp - Power Up */
+MV_VOID mvPexPowerUp(MV_U32 pexIf);
+
+/* mvPexPhyRegRead - Pex phy read */
+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value);
+
+/* mvPexPhyRegWrite - Pex phy write */
+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value);
+
+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable);
+
+#endif /* #ifndef __INCPEXH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h
new file mode 100644
index 000000000..8ac169836
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h
@@ -0,0 +1,751 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCPEXREGSH
+#define __INCPEXREGSH
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines */
+#define MAX_PEX_DEVICES 32
+#define MAX_PEX_FUNCS 8
+#define MAX_PEX_BUSSES 256
+
+
+
+/*********************************************************/
+/* PCI Express Configuration Cycles Generation Registers */
+/*********************************************************/
+
+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8)
+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC)
+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00)
+/* PCI Express Configuration Address Register */
+/* PEX_CFG_ADDR_REG (PXCAR)*/
+
+#define PXCAR_REG_NUM_OFFS 2
+#define PXCAR_REG_NUM_MAX 0x3F
+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
+#define PXCAR_FUNC_NUM_OFFS 8
+#define PXCAR_FUNC_NUM_MAX 0x7
+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
+#define PXCAR_DEVICE_NUM_OFFS 11
+#define PXCAR_DEVICE_NUM_MAX 0x1F
+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
+#define PXCAR_BUS_NUM_OFFS 16
+#define PXCAR_BUS_NUM_MAX 0xFF
+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
+#define PXCAR_EXT_REG_NUM_OFFS 24
+#define PXCAR_EXT_REG_NUM_MAX 0xF
+
+/* in pci express register address is now the legacy register address (8 bits)
+with the new extended register address (more 4 bits) , below is the mask of
+the upper 4 bits of the full register address */
+
+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS)
+#define PXCAR_CONFIG_EN BIT31
+
+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
+
+/* The traditional PCI spec defined 6-bit field to describe register offset.*/
+/* The new PCI Express extend the register offset by an extra 4-bits. */
+/* The below macro assign 10-bit register offset into the apprpreate */
+/* fields in the CFG_ADDR_REG */
+#define PXCAR_REG_OFFS_SET(regOffs) \
+ ( (regOff & PXCAR_REG_NUM_MASK) | \
+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) )
+
+/***********************************/
+/* PCI Express Interrupt registers */
+/***********************************/
+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900)
+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910)
+
+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */
+ /* <DLDown> of the PCI Express */
+/* PCI Express Interrupt Cause */
+/* PEX_INT_CAUSE_REG (PXICR)*/
+/* PEX_INT_MASK_REG*/
+/*
+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets
+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has
+no affect. Bits[24:27} are set and cleared upon reception of interrupt
+emulation messages.
+
+Mask bit per cause bit. If a bit is set to 1, the corresponding event is
+enabled. Mask does not affect setting of the Interrupt Cause register bits;
+it only affects the assertion of the interrupt .*/
+
+
+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction
+ while master is disabled */
+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to
+ PCI Express internal register*/
+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */
+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */
+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */
+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/
+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/
+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/
+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/
+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/
+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */
+
+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */
+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/
+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/
+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/
+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/
+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/
+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/
+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/
+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/
+#define PXICR_RCV_INTA BIT24 /* IntA status.*/
+#define PXICR_RCV_INTB BIT25 /* IntB status.*/
+#define PXICR_RCV_INTC BIT26 /* IntC status.*/
+#define PXICR_RCV_INTD BIT27 /* IntD status.*/
+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */
+
+
+/********************************************/
+/* PCI Express Control and Status Registers */
+/********************************************/
+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00)
+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04)
+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10)
+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18)
+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20)
+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30)
+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40)
+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0)
+
+
+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50)
+/* PCI Express Control Register */
+/* PEX_CTRL_REG (PXCR) */
+
+#define PXCR_CONF_LINK_OFFS 0
+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS)
+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS)
+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS)
+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/
+#define PXCR_DEV_TYPE_CTRL_MASK BIT1
+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS)
+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS)
+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping
+ to Memory Space Enable */
+
+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping
+ to Memory Space Enable*/
+
+#define PXCR_RSRV1_OFFS 5
+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS)
+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS)
+
+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/
+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS)
+
+
+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/
+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS)
+
+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/
+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */
+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/
+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/
+
+/* PCI Express Status Register */
+/* PEX_STATUS_REG (PXSR) */
+
+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/
+
+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
+
+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
+
+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/
+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/
+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/
+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/
+
+
+/* PCI Express Completion Timeout Register */
+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/
+
+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */
+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS)
+
+/* PCI Express Power Management Extended Register */
+/* PEX_PWR_MNG_EXT_REG (PXPMER) */
+
+#define PXPMER_L1_ASPM_EN_OFFS 1
+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS)
+
+/* PCI Express Flow Control Register */
+/* PEX_FLOW_CTRL_REG (PXFCR)*/
+
+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit
+ Initial Value.*/
+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS)
+
+
+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers
+ Flow Control Credit Initial Value*/
+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS)
+
+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control
+ Credit Initial Value Infinite*/
+
+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS)
+
+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */
+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS)
+
+/* PCI Express Acknowledge Timers (4X) Register */
+/* PEX_ACK_TMR_4X_REG (PXAT4R) */
+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */
+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS)
+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */
+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS)
+
+/* PCI Express Acknowledge Timers (1X) Register */
+/* PEX_ACK_TMR_1X_REG (PXAT1R) */
+
+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout
+ Value for 1X Link*/
+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS)
+
+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout
+ Value for 1X*/
+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS)
+
+
+/* PCI Express TL Control Register */
+/* PEX_TL_CTRL_REG (PXTCR) */
+
+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/
+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS)
+
+/* PCI Express Debug MAC Control Register */
+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */
+
+#define PXDMCR_LINKUP BIT4
+
+
+
+/**********************************************/
+/* PCI Express Configuration Header Registers */
+/**********************************************/
+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg))
+
+#define PEX_DEVICE_AND_VENDOR_ID 0x000
+#define PEX_STATUS_AND_COMMAND 0x004
+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008
+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C
+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2))
+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8)
+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8)
+#define PEX_BAR0_INTER_REG 0x010
+#define PEX_BAR0_INTER_REG_HIGH 0x014
+#define PEX_BAR1_REG 0x018
+#define PEX_BAR1_REG_HIGH 0x01C
+#define PEX_BAR2_REG 0x020
+#define PEX_BAR2_REG_HIGH 0x024
+
+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C
+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030
+#define PEX_CAPABILTY_LIST_POINTER 0x034
+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C
+
+/* capability list */
+#define PEX_POWER_MNG_CAPABILITY 0x040
+#define PEX_POWER_MNG_STATUS_CONTROL 0x044
+
+#define PEX_MSI_MESSAGE_CONTROL 0x050
+#define PEX_MSI_MESSAGE_ADDR 0x054
+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058
+#define PEX_MSI_MESSAGE_DATA 0x05C
+
+#define PEX_CAPABILITY_REG 0x60
+#define PEX_DEV_CAPABILITY_REG 0x64
+#define PEX_DEV_CTRL_STAT_REG 0x68
+#define PEX_LINK_CAPABILITY_REG 0x6C
+#define PEX_LINK_CTRL_STAT_REG 0x70
+
+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100
+#define PEX_UNCORRECT_ERR_STAT_REG 0x104
+#define PEX_UNCORRECT_ERR_MASK_REG 0x108
+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C
+#define PEX_CORRECT_ERR_STAT_REG 0x110
+#define PEX_CORRECT_ERR_MASK_REG 0x114
+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118
+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C
+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120
+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124
+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128
+
+
+
+/* PCI Express Device and Vendor ID Register*/
+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/
+
+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */
+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS)
+
+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */
+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS)
+
+
+/* PCI Express Command and Status Register*/
+/*PEX_STATUS_AND_COMMAND (PXSAC)*/
+
+#define PXSAC_IO_EN BIT0 /* IO Enable */
+#define PXSAC_MEM_EN BIT1 /* Memory Enable */
+#define PXSAC_MASTER_EN BIT2 /* Master Enable */
+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */
+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */
+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */
+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */
+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */
+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */
+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */
+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */
+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */
+#define PXSAC_SYSERR BIT30 /* Signalled system error */
+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */
+
+
+/* PCI Express Class Code and Revision ID Register*/
+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/
+
+#define PXCCARI_REVID_OFFS 0 /* Revision ID */
+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS)
+
+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */
+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS)
+
+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/
+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS)
+
+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/
+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS)
+
+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/
+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS)
+
+
+/* PCI Express BIST, Header Type and Cache Line Size Register*/
+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/
+
+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */
+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS)
+
+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */
+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS)
+
+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */
+
+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */
+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS)
+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS)
+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS)
+
+
+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */
+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS)
+
+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */
+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */
+#define PXBHTLTCL_BISTCAP_OFFS 31
+#define PXBHTLTCL_BISTCAP_MASK BIT31
+#define PXBHTLTCL_BISTCAP_VAL 0
+
+
+/* PCI Express Subsystem Device and Vendor ID */
+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/
+
+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */
+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS)
+
+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */
+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS)
+
+
+/* PCI Express Capability List Pointer Register*/
+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/
+
+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */
+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS)
+
+/* PCI Express Interrupt Pin and Line Register */
+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/
+
+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */
+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS)
+
+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */
+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS)
+
+
+/* PCI Express Power Management Capability Header Register*/
+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/
+
+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */
+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS)
+
+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */
+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS)
+
+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/
+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS)
+
+#define PXPMC_DSI BIT21/* Device Specific Initialization */
+
+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */
+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS)
+
+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/
+
+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/
+
+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/
+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS)
+
+/* PCI Express Power Management Control and Status Register*/
+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/
+
+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */
+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS)
+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS)
+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS)
+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS)
+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS)
+
+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */
+
+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/
+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS)
+
+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */
+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS)
+
+#define PXPMSC_PME_STAT BIT15/* PME Status */
+
+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */
+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS)
+
+
+/* PCI Express MSI Message Control Register*/
+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/
+
+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */
+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS)
+
+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */
+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS)
+
+#define PXMMC_MSI_EN BIT18 /* MSI Enable */
+
+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */
+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS)
+
+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */
+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS)
+
+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */
+
+
+/* PCI Express MSI Message Address Register*/
+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/
+
+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to
+ Address[31:2] of the MSI MWr TLP*/
+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS)
+
+
+/* PCI Express MSI Message Address (High) Register */
+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/
+
+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to
+ Address[63:32] of the MSI MWr TLP*/
+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS )
+
+
+/* PCI Express MSI Message Data Register*/
+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/
+
+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */
+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS )
+
+
+/* PCI Express Capability Register*/
+/*PEX_CAPABILITY_REG (PXCR)*/
+
+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/
+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS)
+
+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/
+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS)
+
+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/
+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS)
+
+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/
+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS)
+
+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/
+
+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/
+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS)
+
+
+/* PCI Express Device Capabilities Register */
+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/
+
+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/
+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS)
+
+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/
+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS)
+
+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/
+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS)
+
+
+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/
+#define PXDCR_ATT_BUT_PRS_MASK BIT12
+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12
+
+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/
+#define PXDCR_ATT_IND_PRS_MASK BIT13
+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13
+
+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/
+#define PXDCR_PWR_IND_PRS_MASK BIT14
+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14
+
+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit
+ Value*/
+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS)
+
+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit
+ Scale */
+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS)
+
+/* PCI Express Device Control Status Register */
+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/
+
+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/
+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/
+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/
+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR)
+ Reporting Enable*/
+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/
+
+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/
+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS)
+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS)
+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/
+
+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/
+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS)
+
+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/
+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/
+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/
+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */
+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/
+
+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/
+#define PXDCSR_TRANS_PEND_MASK BIT21
+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS)
+
+
+/* PCI Express Link Capabilities Register*/
+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/
+
+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/
+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS)
+
+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/
+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS)
+
+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/
+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS)
+
+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/
+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS)
+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS)
+
+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */
+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS)
+
+/* PCI Express Link Control Status Register */
+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/
+
+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */
+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS)
+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS)
+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS)
+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS)
+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS)
+
+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */
+#define PXLCSR_RCB_MASK BIT3
+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS)
+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS)
+
+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */
+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */
+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */
+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */
+
+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */
+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS)
+
+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */
+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS)
+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS)
+
+#define PXLCSR_LNK_TRN BIT27 /* Link Training */
+
+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */
+#define PXLCSR_SLT_CLK_CFG_MASK BIT28
+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS)
+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS)
+
+/* PCI Express Advanced Error Report Header Register */
+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/
+
+/* PCI Express Uncorrectable Error Status Register*/
+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/
+
+/* PCI Express Uncorrectable Error Mask Register */
+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/
+
+/* PCI Express Uncorrectable Error Severity Register */
+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/
+
+/* PCI Express Correctable Error Status Register */
+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/
+
+/* PCI Express Correctable Error Mask Register */
+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/
+
+/* PCI Express Advanced Error Capability and Control Register*/
+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/
+
+/* PCI Express Header Log First DWORD Register*/
+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/
+
+/* PCI Express Header Log Second DWORD Register*/
+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/
+
+/* PCI Express Header Log Third DWORD Register*/
+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/
+
+/* PCI Express Header Log Fourth DWORD Register*/
+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* #ifndef __INCPEXREGSH */
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c
new file mode 100644
index 000000000..19c871ae4
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c
@@ -0,0 +1,313 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "mvPex.h"
+
+//#define MV_DEBUG
+/* defines */
+#ifdef MV_DEBUG
+ #define DB(x) x
+#else
+ #define DB(x)
+#endif
+
+/* locals */
+typedef struct
+{
+ MV_U32 data;
+ MV_U32 mask;
+}PEX_HEADER_DATA;
+
+/* local function forwad decleration */
+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
+ MV_U32 regOff);
+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data);
+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev);
+
+
+PEX_HEADER_DATA configHdr[16] =
+{
+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */
+{0x00100007, 0x0000ffff}, /*[status register, command register] */
+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */
+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */
+{0x00000000, 0x00000000}, /*[base address 0] */
+{0x00000000, 0x00000000}, /*[base address 1] */
+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */
+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */
+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */
+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */
+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */
+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */
+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */
+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */
+{0x00000000, 0x00000000}, /*[expansion ROM base address] */
+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */
+};
+
+
+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \
+ (data & configHdr[offset/4].mask))
+#define HEADER_READ(offset) configHdr[offset/4].data
+
+/*******************************************************************************
+* mvVrtBrgPexInit - Initialize PEX interfaces
+*
+* DESCRIPTION:
+*
+* This function is responsible of intialization of the Pex Interface , It
+* configure the Pex Bars and Windows in the following manner:
+*
+* Assumptions :
+* Bar0 is always internal registers bar
+* Bar1 is always the DRAM bar
+* Bar2 is always the Device bar
+*
+* 1) Sets the Internal registers bar base by obtaining the base from
+* the CPU Interface
+* 2) Sets the DRAM bar base and size by getting the base and size from
+* the CPU Interface when the size is the sum of all enabled DRAM
+* chip selects and the base is the base of CS0 .
+* 3) Sets the Device bar base and size by getting these values from the
+* CPU Interface when the base is the base of the lowest base of the
+* Device chip selects, and the
+*
+*
+* INPUT:
+*
+* pexIf - PEX interface number.
+*
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
+*
+*******************************************************************************/
+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf)
+{
+ /* reset PEX tree to recover previous U-boot/Boot configurations */
+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
+
+
+ resetPexConfig(pexIf, localBus, 1);
+ return MV_OK;
+}
+
+
+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
+ MV_U32 regOff)
+{
+
+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
+ MV_U32 val;
+ if(bus == localBus)
+ {
+ if(dev > 1)
+ {
+/* on the local device allow only device #0 & #1 */
+ return 0xffffffff;
+ }
+ else
+ if (dev == localDev)
+ {
+ /* read the memory controller registers */
+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
+ }
+ else
+ {
+ /* access the virtual brg header */
+ return HEADER_READ(regOff);
+ }
+ }
+ else
+ if(bus == (localBus + 1))
+ {
+ /* access the device behind the virtual bridge */
+ if((dev == localDev) || (dev > 1))
+ {
+ return 0xffffffff;
+ }
+ else
+ {
+ /* access the device behind the virtual bridge, in this case
+ * change the bus number to the local bus number in order to
+ * generate type 0 config cycle
+ */
+ mvPexLocalBusNumSet(pexIf, bus);
+ mvPexLocalDevNumSet(pexIf, 1);
+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff);
+ mvPexLocalBusNumSet(pexIf, localBus);
+ mvPexLocalDevNumSet(pexIf, localDev);
+ return val;
+ }
+ }
+ /* for all other devices use the HW function to get the
+ * requested registers
+ */
+ mvPexLocalDevNumSet(pexIf, 1);
+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
+ mvPexLocalDevNumSet(pexIf, localDev);
+ return val;
+}
+
+
+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data)
+{
+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
+ MV_STATUS status;
+
+ if(bus == localBus)
+ {
+ if(dev > 1)
+ {
+ /* on the local device allow only device #0 & #1 */
+ return MV_ERROR;
+ }
+ else
+ if (dev == localDev)
+ {
+ /* read the memory controller registers */
+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
+ }
+ else
+ {
+ /* access the virtual brg header */
+ HEADER_WRITE(data, regOff);
+ return MV_OK;
+ }
+ }
+ else
+ if(bus == (localBus + 1))
+ {
+ /* access the device behind the virtual bridge */
+ if((dev == localDev) || (dev > 1))
+ {
+ return MV_ERROR;
+ }
+ else
+ {
+ /* access the device behind the virtual bridge, in this case
+ * change the bus number to the local bus number in order to
+ * generate type 0 config cycle
+ */
+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data);
+ mvPexLocalBusNumSet(pexIf, bus);
+ mvPexLocalDevNumSet(pexIf, 1);
+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data);
+ mvPexLocalBusNumSet(pexIf, localBus);
+ mvPexLocalDevNumSet(pexIf, localDev);
+ return status;
+
+ }
+ }
+ /* for all other devices use the HW function to get the
+ * requested registers
+ */
+ mvPexLocalDevNumSet(pexIf, 1);
+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
+ mvPexLocalDevNumSet(pexIf, localDev);
+ return status;
+}
+
+
+
+
+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev)
+{
+ MV_U32 tData;
+ MV_U32 i;
+
+ /* restore the PEX configuration to initialization state */
+ /* in case PEX P2P call recursive and reset config */
+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0);
+ if(tData != 0xffffffff)
+ {
+ /* agent had been found - check whether P2P */
+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8);
+ if((tData & 0xffff0000) == 0x06040000)
+ {/* P2P */
+ /* get the sec bus and the subordinate */
+ MV_U32 secBus;
+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18);
+ secBus = ((tData >> 8) & 0xff);
+ /* now scan on sec bus */
+ for(i = 0;i < 0xff;i++)
+ {
+ resetPexConfig(pexIf, secBus, i);
+ }
+ /* now reset this device */
+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0);
+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
+ }
+ }
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h
new file mode 100644
index 000000000..82eb72d50
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h
@@ -0,0 +1,82 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCVRTBRGPEXH
+#define __INCVRTBRGPEXH
+
+
+/* Global Functions prototypes */
+/* mvPexInit - Initialize PEX interfaces*/
+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf);
+
+/* mvPexConfigRead - Read from configuration space */
+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func,MV_U32 regOff);
+
+/* mvPexConfigWrite - Write to configuration space */
+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
+ MV_U32 func, MV_U32 regOff, MV_U32 data);
+
+
+#endif /* #ifndef __INCPEXH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt
new file mode 100644
index 000000000..85bfa612c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.3
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c
new file mode 100644
index 000000000..6c5bc191c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c
@@ -0,0 +1,1522 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "mvOs.h"
+#include "sflash/mvSFlash.h"
+#include "sflash/mvSFlashSpec.h"
+#include "spi/mvSpi.h"
+#include "spi/mvSpiCmnd.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/*#define MV_DEBUG*/
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+/* Globals */
+static MV_SFLASH_DEVICE_PARAMS sflash[] = {
+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */
+ {
+ MV_M25P_WREN_CMND_OPCD,
+ MV_M25P_WRDI_CMND_OPCD,
+ MV_M25P_RDID_CMND_OPCD,
+ MV_M25P_RDSR_CMND_OPCD,
+ MV_M25P_WRSR_CMND_OPCD,
+ MV_M25P_READ_CMND_OPCD,
+ MV_M25P_FAST_RD_CMND_OPCD,
+ MV_M25P_PP_CMND_OPCD,
+ MV_M25P_SE_CMND_OPCD,
+ MV_M25P_BE_CMND_OPCD,
+ MV_M25P_RES_CMND_OPCD,
+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
+ MV_M25P32_SECTOR_SIZE,
+ MV_M25P32_SECTOR_NUMBER,
+ MV_M25P_PAGE_SIZE,
+ "ST M25P32",
+ MV_M25PXXX_ST_MANF_ID,
+ MV_M25P32_DEVICE_ID,
+ MV_M25P32_MAX_SPI_FREQ,
+ MV_M25P32_MAX_FAST_SPI_FREQ,
+ MV_M25P32_FAST_READ_DUMMY_BYTES
+ },
+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */
+ {
+ MV_M25P_WREN_CMND_OPCD,
+ MV_M25P_WRDI_CMND_OPCD,
+ MV_M25P_RDID_CMND_OPCD,
+ MV_M25P_RDSR_CMND_OPCD,
+ MV_M25P_WRSR_CMND_OPCD,
+ MV_M25P_READ_CMND_OPCD,
+ MV_M25P_FAST_RD_CMND_OPCD,
+ MV_M25P_PP_CMND_OPCD,
+ MV_M25P_SE_CMND_OPCD,
+ MV_M25P_BE_CMND_OPCD,
+ MV_M25P_RES_CMND_OPCD,
+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
+ MV_M25P64_SECTOR_SIZE,
+ MV_M25P64_SECTOR_NUMBER,
+ MV_M25P_PAGE_SIZE,
+ "ST M25P64",
+ MV_M25PXXX_ST_MANF_ID,
+ MV_M25P64_DEVICE_ID,
+ MV_M25P64_MAX_SPI_FREQ,
+ MV_M25P64_MAX_FAST_SPI_FREQ,
+ MV_M25P64_FAST_READ_DUMMY_BYTES
+ },
+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */
+ {
+ MV_M25P_WREN_CMND_OPCD,
+ MV_M25P_WRDI_CMND_OPCD,
+ MV_M25P_RDID_CMND_OPCD,
+ MV_M25P_RDSR_CMND_OPCD,
+ MV_M25P_WRSR_CMND_OPCD,
+ MV_M25P_READ_CMND_OPCD,
+ MV_M25P_FAST_RD_CMND_OPCD,
+ MV_M25P_PP_CMND_OPCD,
+ MV_M25P_SE_CMND_OPCD,
+ MV_M25P_BE_CMND_OPCD,
+ MV_M25P_RES_CMND_OPCD,
+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */
+ MV_M25P128_SECTOR_SIZE,
+ MV_M25P128_SECTOR_NUMBER,
+ MV_M25P_PAGE_SIZE,
+ "ST M25P128",
+ MV_M25PXXX_ST_MANF_ID,
+ MV_M25P128_DEVICE_ID,
+ MV_M25P128_MAX_SPI_FREQ,
+ MV_M25P128_MAX_FAST_SPI_FREQ,
+ MV_M25P128_FAST_READ_DUMMY_BYTES
+ },
+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */
+ {
+ MV_MX25L_WREN_CMND_OPCD,
+ MV_MX25L_WRDI_CMND_OPCD,
+ MV_MX25L_RDID_CMND_OPCD,
+ MV_MX25L_RDSR_CMND_OPCD,
+ MV_MX25L_WRSR_CMND_OPCD,
+ MV_MX25L_READ_CMND_OPCD,
+ MV_MX25L_FAST_RD_CMND_OPCD,
+ MV_MX25L_PP_CMND_OPCD,
+ MV_MX25L_SE_CMND_OPCD,
+ MV_MX25L_BE_CMND_OPCD,
+ MV_MX25L_RES_CMND_OPCD,
+ MV_MX25L_DP_CMND_OPCD,
+ MV_MX25L6405_SECTOR_SIZE,
+ MV_MX25L6405_SECTOR_NUMBER,
+ MV_MXIC_PAGE_SIZE,
+ "MXIC MX25L6405",
+ MV_MXIC_MANF_ID,
+ MV_MX25L6405_DEVICE_ID,
+ MV_MX25L6405_MAX_SPI_FREQ,
+ MV_MX25L6405_MAX_FAST_SPI_FREQ,
+ MV_MX25L6405_FAST_READ_DUMMY_BYTES
+ },
+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */
+ {
+ MV_S25FL_WREN_CMND_OPCD,
+ MV_S25FL_WRDI_CMND_OPCD,
+ MV_S25FL_RDID_CMND_OPCD,
+ MV_S25FL_RDSR_CMND_OPCD,
+ MV_S25FL_WRSR_CMND_OPCD,
+ MV_S25FL_READ_CMND_OPCD,
+ MV_S25FL_FAST_RD_CMND_OPCD,
+ MV_S25FL_PP_CMND_OPCD,
+ MV_S25FL_SE_CMND_OPCD,
+ MV_S25FL_BE_CMND_OPCD,
+ MV_S25FL_RES_CMND_OPCD,
+ MV_S25FL_DP_CMND_OPCD,
+ MV_S25FL128_SECTOR_SIZE,
+ MV_S25FL128_SECTOR_NUMBER,
+ MV_S25FL_PAGE_SIZE,
+ "SPANSION S25FL128",
+ MV_SPANSION_MANF_ID,
+ MV_S25FL128_DEVICE_ID,
+ MV_S25FL128_MAX_SPI_FREQ,
+ MV_M25P128_MAX_FAST_SPI_FREQ,
+ MV_M25P128_FAST_READ_DUMMY_BYTES
+ }
+};
+
+/* Static Functions */
+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo);
+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg);
+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr);
+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo);
+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \
+ MV_U8* pPageBuff, MV_U32 buffSize);
+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \
+ MV_U8* manId, MV_U16* devId);
+
+/*******************************************************************************
+* mvWriteEnable - serialize the write enable sequence
+*
+* DESCRIPTION:
+* transmit the sequence for write enable
+*
+********************************************************************************/
+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo)
+{
+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH];
+
+
+ cmd[0] = sflash[pFlinfo->index].opcdWREN;
+
+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0);
+}
+
+/*******************************************************************************
+* mvStatusRegGet - Retrieve the value of the status register
+*
+* DESCRIPTION:
+* perform the RDSR sequence to get the 8bit status register
+*
+********************************************************************************/
+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH];
+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH];
+
+
+
+
+ cmd[0] = sflash[pFlinfo->index].opcdRDSR;
+
+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr,
+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK)
+ return ret;
+
+ *pStatReg = sr[0];
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared
+*
+* DESCRIPTION:
+* Block waiting for the WIP (write in progress) to be cleared
+*
+********************************************************************************/
+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo)
+{
+ MV_STATUS ret;
+ MV_U32 i;
+ MV_U8 stat;
+
+ for (i=0; i<MV_SFLASH_MAX_WAIT_LOOP; i++)
+ {
+ if ((ret = mvStatusRegGet(pFlinfo, &stat)) != MV_OK)
+ return ret;
+
+ if ((stat & MV_SFLASH_STATUS_REG_WIP_MASK) == 0)
+ return MV_OK;
+ }
+
+ DB(mvOsPrintf("%s WARNING: Write Timeout!\n", __FUNCTION__);)
+ return MV_TIMEOUT;
+}
+
+/*******************************************************************************
+* mvWaitOnChipEraseDone - Block waiting for the WIP (write in progress) to be
+* cleared after a chip erase command which is supposed
+* to take about 2:30 minutes
+*
+* DESCRIPTION:
+* Block waiting for the WIP (write in progress) to be cleared
+*
+********************************************************************************/
+static MV_STATUS mvWaitOnChipEraseDone(MV_SFLASH_INFO * pFlinfo)
+{
+ MV_STATUS ret;
+ MV_U32 i;
+ MV_U8 stat;
+
+ for (i=0; i<MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP; i++)
+ {
+ if ((ret = mvStatusRegGet(pFlinfo, &stat)) != MV_OK)
+ return ret;
+
+ if ((stat & MV_SFLASH_STATUS_REG_WIP_MASK) == 0)
+ return MV_OK;
+ }
+
+ DB(mvOsPrintf("%s WARNING: Write Timeout!\n", __FUNCTION__);)
+ return MV_TIMEOUT;
+}
+
+/*******************************************************************************
+* mvStatusRegSet - Set the value of the 8bit status register
+*
+* DESCRIPTION:
+* Set the value of the 8bit status register
+*
+********************************************************************************/
+static MV_STATUS mvStatusRegSet(MV_SFLASH_INFO * pFlinfo, MV_U8 sr)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_WRSR_CMND_LENGTH];
+
+
+ /* Issue the Write enable command prior the WRSR command */
+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK)
+ return ret;
+
+ /* Write the SR with the new values */
+ cmd[0] = sflash[pFlinfo->index].opcdWRSR;
+ cmd[1] = sr;
+
+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK)
+ return ret;
+
+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK)
+ return ret;
+
+ mvOsDelay(1);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashPageWr - Write up to 256 Bytes in the same page
+*
+* DESCRIPTION:
+* Write a buffer up to the page size in length provided that the whole address
+* range is within the same page (alligned to page bounderies)
+*
+*******************************************************************************/
+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pPageBuff, MV_U32 buffSize)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH];
+
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* check that we do not cross the page bounderies */
+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) >
+ sflash[pFlinfo->index].pageSize)
+ {
+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);)
+ return MV_OUT_OF_RANGE;
+ }
+
+ /* Issue the Write enable command prior the page program command */
+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK)
+ return ret;
+
+ cmd[0] = sflash[pFlinfo->index].opcdPP;
+ cmd[1] = ((offset >> 16) & 0xFF);
+ cmd[2] = ((offset >> 8) & 0xFF);
+ cmd[3] = (offset & 0xFF);
+
+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK)
+ return ret;
+
+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK)
+ return ret;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from
+* the device using the default RDID opcode and the default WREN opcode.
+*
+* DESCRIPTION:
+* This is used to detect a generic device that uses the default opcodes
+* for the WREN and RDID.
+*
+********************************************************************************/
+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId)
+{
+ MV_STATUS ret;
+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH];
+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH];
+
+
+
+ /* Use the default RDID opcode to read the IDs */
+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */
+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK)
+ return ret;
+
+ *manId = id[0];
+ *devId = 0;
+ *devId |= (id[1] << 8);
+ *devId |= id[2];
+
+ return MV_OK;
+}
+
+/*
+#####################################################################################
+#####################################################################################
+*/
+
+/*******************************************************************************
+* mvSFlashInit - Initialize the serial flash device
+*
+* DESCRIPTION:
+* Perform the neccessary initialization and configuration
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* pFlinfo->baseAddr: base address in fast mode.
+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI
+* flash device does not support read Id command with
+* the standard opcode, then the user should supply this
+* as an input to skip the autodetection process!!!!
+*
+* OUTPUT:
+* pFlinfo: pointer to the Flash information structure after detection
+* pFlinfo->manufacturerId: Manufacturer ID
+* pFlinfo->deviceId: Device ID
+* pFlinfo->sectorSize: size of the sector (all sectors are the same).
+* pFlinfo->sectorNumber: number of sectors.
+* pFlinfo->pageSize: size of the page.
+* pFlinfo->index: Index of the detected flash in the sflash tabel
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo)
+{
+ MV_STATUS ret;
+ MV_U8 manf;
+ MV_U16 dev;
+ MV_U32 indx;
+ MV_BOOL detectFlag = MV_FALSE;
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */
+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK)
+ {
+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__);
+ return ret;
+ }
+
+ /* First try to read the Manufacturer and Device IDs */
+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK)
+ {
+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__);
+ return ret;
+ }
+
+ /* loop over the whole table and look for the appropriate SFLASH */
+ for (indx=0; indx<MV_ARRAY_SIZE(sflash); indx++)
+ {
+ if ((manf == sflash[indx].manufacturerId) && (dev == sflash[indx].deviceId))
+ {
+ pFlinfo->manufacturerId = manf;
+ pFlinfo->deviceId = dev;
+ pFlinfo->index = indx;
+ detectFlag = MV_TRUE;
+ }
+ }
+
+ if(!detectFlag)
+ {
+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__);
+ return MV_FAIL;
+ }
+
+ /* fill the info based on the model detected */
+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize;
+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber;
+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize;
+
+ /* Set the SPI frequency to the MAX allowed for the device for best performance */
+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK)
+ {
+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__);
+ return ret;
+ }
+
+ /* As default lock the SR */
+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK)
+ return ret;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashSectorErase - Erasse a single sector of the serial flash
+*
+* DESCRIPTION:
+* Issue the erase sector command and address
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* secNumber: sector Number to erase (0 -> (sectorNumber-1))
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH];
+
+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize);
+#if 0
+ MV_U32 i;
+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr);
+ MV_U32 erasedWord = 0xFFFFFFFF;
+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32));
+ MV_BOOL eraseNeeded = MV_FALSE;
+#endif
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* check that the sector number is valid */
+ if (secNumber >= pFlinfo->sectorNumber)
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* we don't want to access SPI in direct mode from in-direct API,
+ becasue of timing issue between CS asserts. */
+#if 0
+ /* First compare to FF and check if erase is needed */
+ for (i=0; i<wordsPerSector; i++)
+ {
+ if (memcmp(pW, &erasedWord, sizeof(MV_U32)) != 0)
+ {
+ eraseNeeded = MV_TRUE;
+ break;
+ }
+
+ ++pW;
+ }
+ if (!eraseNeeded)
+ return MV_OK;
+#endif
+
+ cmd[0] = sflash[pFlinfo->index].opcdSE;
+ cmd[1] = ((secAddr >> 16) & 0xFF);
+ cmd[2] = ((secAddr >> 8) & 0xFF);
+ cmd[3] = (secAddr & 0xFF);
+
+ /* Issue the Write enable command prior the sector erase command */
+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK)
+ return ret;
+
+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK)
+ return ret;
+
+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK)
+ return ret;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashChipErase - Erasse the whole serial flash
+*
+* DESCRIPTION:
+* Issue the bulk (chip) erase command
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH];
+
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ cmd[0] = sflash[pFlinfo->index].opcdBE;
+
+ /* Issue the Write enable command prior the Bulk erase command */
+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK)
+ return ret;
+
+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK)
+ return ret;
+
+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK)
+ return ret;
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashBlockRd - Read from the serial flash
+*
+* DESCRIPTION:
+* Issue the read command and address then perfom the needed read
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* offset: byte offset with the flash to start reading from
+* pReadBuff: pointer to the buffer to read the data in
+* buffSize: size of the buffer to read.
+*
+* OUTPUT:
+* pReadBuff: pointer to the buffer containing the read data
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pReadBuff, MV_U32 buffSize)
+{
+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH];
+
+
+ /* check for NULL pointer */
+ if ((pFlinfo == NULL) || (pReadBuff == NULL))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ cmd[0] = sflash[pFlinfo->index].opcdREAD;
+ cmd[1] = ((offset >> 16) & 0xFF);
+ cmd[2] = ((offset >> 8) & 0xFF);
+ cmd[3] = (offset & 0xFF);
+
+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0);
+}
+
+/*******************************************************************************
+* mvSFlashFastBlockRd - Fast read from the serial flash
+*
+* DESCRIPTION:
+* Issue the fast read command and address then perfom the needed read
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* offset: byte offset with the flash to start reading from
+* pReadBuff: pointer to the buffer to read the data in
+* buffSize: size of the buffer to read.
+*
+* OUTPUT:
+* pReadBuff: pointer to the buffer containing the read data
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pReadBuff, MV_U32 buffSize)
+{
+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH];
+ MV_STATUS ret;
+
+ /* check for NULL pointer */
+ if ((pFlinfo == NULL) || (pReadBuff == NULL))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* Set the SPI frequency to the MAX allowed for fast-read operations */
+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq);
+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK)
+ {
+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__);
+ return ret;
+ }
+
+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD;
+ cmd[1] = ((offset >> 16) & 0xFF);
+ cmd[2] = ((offset >> 8) & 0xFF);
+ cmd[3] = (offset & 0xFF);
+
+
+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize,
+ sflash[pFlinfo->index].spiFastRdDummyBytes);
+
+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */
+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK)
+ {
+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__);
+ return ret;
+ }
+
+ return ret;
+}
+
+
+/*******************************************************************************
+* mvSFlashBlockWr - Write a buffer with any size
+*
+* DESCRIPTION:
+* write regardless of the page boundaries and size limit per Page
+* program command
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* offset: byte offset within the flash region
+* pWriteBuff: pointer to the buffer holding the data to program
+* buffSize: size of the buffer to write
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pWriteBuff, MV_U32 buffSize)
+{
+ MV_STATUS ret;
+ MV_U32 data2write = buffSize;
+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE));
+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0);
+ MV_U32 writeOffset = offset;
+
+ /* check for NULL pointer */
+#ifndef CONFIG_MARVELL
+ if(NULL == pWriteBuff)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+#endif
+
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* check that the buffer size does not exceed the flash size */
+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo))
+ {
+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);)
+ return MV_OUT_OF_RANGE;
+ }
+
+ /* check if the total block size is less than the first chunk remainder */
+ if (data2write < preAllSz)
+ preAllSz = data2write;
+
+ /* check if programing does not start at a 64byte alligned offset */
+ if (preAllSz)
+ {
+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK)
+ return ret;
+
+ /* increment pointers and counters */
+ writeOffset += preAllSz;
+ data2write -= preAllSz;
+ pWriteBuff += preAllSz;
+ }
+
+ /* program the data that fits in complete page chunks */
+ while (data2write >= sflash[pFlinfo->index].pageSize)
+ {
+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK)
+ return ret;
+
+ /* increment pointers and counters */
+ writeOffset += sflash[pFlinfo->index].pageSize;
+ data2write -= sflash[pFlinfo->index].pageSize;
+ pWriteBuff += sflash[pFlinfo->index].pageSize;
+ }
+
+ /* program the last partial chunk */
+ if (data2write)
+ {
+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK)
+ return ret;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashIdGet - Get the manufacturer and device IDs.
+*
+* DESCRIPTION:
+* Get the Manufacturer and device IDs from the serial flash through
+* writing the RDID command then reading 3 bytes of data. In case that
+* this command was called for the first time in order to detect the
+* manufacturer and device IDs, then the default RDID opcode will be used
+* unless the device index is indicated by the user (in case the SPI flash
+* does not use the default RDID opcode).
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* pManId: pointer to the 8bit variable to hold the manufacturing ID
+* pDevId: pointer to the 16bit variable to hold the device ID
+*
+* OUTPUT:
+* pManId: pointer to the 8bit variable holding the manufacturing ID
+* pDevId: pointer to the 16bit variable holding the device ID
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH];
+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH];
+
+
+
+ /* check for NULL pointer */
+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId);
+ else
+ cmd[0] = sflash[pFlinfo->index].opcdRDID;
+
+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK)
+ return ret;
+
+ *pManId = id[0];
+ *pDevId = 0;
+ *pDevId |= (id[1] << 8);
+ *pDevId |= id[2];
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashWpRegionSet - Set the Write-Protected region
+*
+* DESCRIPTION:
+* Set the Write-Protected region
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* wpRegion: which region will be protected
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion)
+{
+ MV_U8 wpMask;
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* Check if the chip is an ST flash; then WP supports only 3 bits */
+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID)
+ {
+ switch (wpRegion)
+ {
+ case MV_WP_NONE:
+ wpMask = MV_M25P_STATUS_BP_NONE;
+ break;
+
+ case MV_WP_UPR_1OF128:
+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);)
+ return MV_NOT_SUPPORTED;
+
+ case MV_WP_UPR_1OF64:
+ wpMask = MV_M25P_STATUS_BP_1_OF_64;
+ break;
+
+ case MV_WP_UPR_1OF32:
+ wpMask = MV_M25P_STATUS_BP_1_OF_32;
+ break;
+
+ case MV_WP_UPR_1OF16:
+ wpMask = MV_M25P_STATUS_BP_1_OF_16;
+ break;
+
+ case MV_WP_UPR_1OF8:
+ wpMask = MV_M25P_STATUS_BP_1_OF_8;
+ break;
+
+ case MV_WP_UPR_1OF4:
+ wpMask = MV_M25P_STATUS_BP_1_OF_4;
+ break;
+
+ case MV_WP_UPR_1OF2:
+ wpMask = MV_M25P_STATUS_BP_1_OF_2;
+ break;
+
+ case MV_WP_ALL:
+ wpMask = MV_M25P_STATUS_BP_ALL;
+ break;
+
+ default:
+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+ }
+ /* check if the manufacturer is MXIC then the WP is 4bits */
+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID)
+ {
+ switch (wpRegion)
+ {
+ case MV_WP_NONE:
+ wpMask = MV_MX25L_STATUS_BP_NONE;
+ break;
+
+ case MV_WP_UPR_1OF128:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_128;
+ break;
+
+ case MV_WP_UPR_1OF64:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_64;
+ break;
+
+ case MV_WP_UPR_1OF32:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_32;
+ break;
+
+ case MV_WP_UPR_1OF16:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_16;
+ break;
+
+ case MV_WP_UPR_1OF8:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_8;
+ break;
+
+ case MV_WP_UPR_1OF4:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_4;
+ break;
+
+ case MV_WP_UPR_1OF2:
+ wpMask = MV_MX25L_STATUS_BP_1_OF_2;
+ break;
+
+ case MV_WP_ALL:
+ wpMask = MV_MX25L_STATUS_BP_ALL;
+ break;
+
+ default:
+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+ }
+ /* check if the manufacturer is SPANSION then the WP is 4bits */
+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID)
+ {
+ switch (wpRegion)
+ {
+ case MV_WP_NONE:
+ wpMask = MV_S25FL_STATUS_BP_NONE;
+ break;
+
+ case MV_WP_UPR_1OF128:
+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);)
+ return MV_NOT_SUPPORTED;
+
+ case MV_WP_UPR_1OF64:
+ wpMask = MV_S25FL_STATUS_BP_1_OF_64;
+ break;
+
+ case MV_WP_UPR_1OF32:
+ wpMask = MV_S25FL_STATUS_BP_1_OF_32;
+ break;
+
+ case MV_WP_UPR_1OF16:
+ wpMask = MV_S25FL_STATUS_BP_1_OF_16;
+ break;
+
+ case MV_WP_UPR_1OF8:
+ wpMask = MV_S25FL_STATUS_BP_1_OF_8;
+ break;
+
+ case MV_WP_UPR_1OF4:
+ wpMask = MV_S25FL_STATUS_BP_1_OF_4;
+ break;
+
+ case MV_WP_UPR_1OF2:
+ wpMask = MV_S25FL_STATUS_BP_1_OF_2;
+ break;
+
+ case MV_WP_ALL:
+ wpMask = MV_S25FL_STATUS_BP_ALL;
+ break;
+
+
+ default:
+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+ }
+ else
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* Verify that the SRWD bit is always set - register is s/w locked */
+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK;
+
+ return mvStatusRegSet(pFlinfo, wpMask);
+}
+
+/*******************************************************************************
+* mvSFlashWpRegionGet - Get the Write-Protected region configured
+*
+* DESCRIPTION:
+* Get from the chip the Write-Protected region configured
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* pWpRegion: pointer to the variable to return the WP region in
+*
+* OUTPUT:
+* wpRegion: pointer to the variable holding the WP region configured
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion)
+{
+ MV_STATUS ret;
+ MV_U8 reg;
+
+ /* check for NULL pointer */
+ if ((pFlinfo == NULL) || (pWpRegion == NULL))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ if ((ret = mvStatusRegGet(pFlinfo, &reg)) != MV_OK)
+ return ret;
+
+ /* Check if the chip is an ST flash; then WP supports only 3 bits */
+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID)
+ {
+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK))
+ {
+ case MV_M25P_STATUS_BP_NONE:
+ *pWpRegion = MV_WP_NONE;
+ break;
+
+ case MV_M25P_STATUS_BP_1_OF_64:
+ *pWpRegion = MV_WP_UPR_1OF64;
+ break;
+
+ case MV_M25P_STATUS_BP_1_OF_32:
+ *pWpRegion = MV_WP_UPR_1OF32;
+ break;
+
+ case MV_M25P_STATUS_BP_1_OF_16:
+ *pWpRegion = MV_WP_UPR_1OF16;
+ break;
+
+ case MV_M25P_STATUS_BP_1_OF_8:
+ *pWpRegion = MV_WP_UPR_1OF8;
+ break;
+
+ case MV_M25P_STATUS_BP_1_OF_4:
+ *pWpRegion = MV_WP_UPR_1OF4;
+ break;
+
+ case MV_M25P_STATUS_BP_1_OF_2:
+ *pWpRegion = MV_WP_UPR_1OF2;
+ break;
+
+ case MV_M25P_STATUS_BP_ALL:
+ *pWpRegion = MV_WP_ALL;
+ break;
+
+ default:
+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);)
+ return MV_BAD_VALUE;
+ }
+ }
+ /* check if the manufacturer is MXIC then the WP is 4bits */
+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID)
+ {
+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK))
+ {
+ case MV_MX25L_STATUS_BP_NONE:
+ *pWpRegion = MV_WP_NONE;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_128:
+ *pWpRegion = MV_WP_UPR_1OF128;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_64:
+ *pWpRegion = MV_WP_UPR_1OF64;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_32:
+ *pWpRegion = MV_WP_UPR_1OF32;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_16:
+ *pWpRegion = MV_WP_UPR_1OF16;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_8:
+ *pWpRegion = MV_WP_UPR_1OF8;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_4:
+ *pWpRegion = MV_WP_UPR_1OF4;
+ break;
+
+ case MV_MX25L_STATUS_BP_1_OF_2:
+ *pWpRegion = MV_WP_UPR_1OF2;
+ break;
+
+ case MV_MX25L_STATUS_BP_ALL:
+ *pWpRegion = MV_WP_ALL;
+ break;
+
+ default:
+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);)
+ return MV_BAD_VALUE;
+ }
+ }
+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */
+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID)
+ {
+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK))
+ {
+ case MV_S25FL_STATUS_BP_NONE:
+ *pWpRegion = MV_WP_NONE;
+ break;
+
+ case MV_S25FL_STATUS_BP_1_OF_64:
+ *pWpRegion = MV_WP_UPR_1OF64;
+ break;
+
+ case MV_S25FL_STATUS_BP_1_OF_32:
+ *pWpRegion = MV_WP_UPR_1OF32;
+ break;
+
+ case MV_S25FL_STATUS_BP_1_OF_16:
+ *pWpRegion = MV_WP_UPR_1OF16;
+ break;
+
+ case MV_S25FL_STATUS_BP_1_OF_8:
+ *pWpRegion = MV_WP_UPR_1OF8;
+ break;
+
+ case MV_S25FL_STATUS_BP_1_OF_4:
+ *pWpRegion = MV_WP_UPR_1OF4;
+ break;
+
+ case MV_S25FL_STATUS_BP_1_OF_2:
+ *pWpRegion = MV_WP_UPR_1OF2;
+ break;
+
+ case MV_S25FL_STATUS_BP_ALL:
+ *pWpRegion = MV_WP_ALL;
+ break;
+
+ default:
+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);)
+ return MV_BAD_VALUE;
+ }
+ }
+ else
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp
+* pin should be low to take effect
+*
+* DESCRIPTION:
+* Lock the access to the Status Register for writing. This will
+* cause the flash to enter the hardware protection mode if the W/Vpp
+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but
+* the register will continue to be writable if WREN sequence was used.
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock)
+{
+ MV_STATUS ret;
+ MV_U8 reg;
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ if ((ret = mvStatusRegGet(pFlinfo, &reg)) != MV_OK)
+ return ret;
+
+ if (srLock)
+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK;
+ else
+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK;
+
+ return mvStatusRegSet(pFlinfo, reg);
+}
+
+/*******************************************************************************
+* mvSFlashSizeGet - Get the size of the SPI flash
+*
+* DESCRIPTION:
+* based on the sector number and size of each sector calculate the total
+* size of the flash memory.
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Size of the flash in bytes.
+*
+*
+*******************************************************************************/
+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo)
+{
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return 0;
+ }
+
+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber);
+}
+
+/*******************************************************************************
+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode
+*
+* DESCRIPTION:
+* Enter a special power save mode.
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Size of the flash in bytes.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH];
+
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return 0;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* check that power save mode is supported in the specific device */
+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD)
+ {
+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);)
+ return MV_NOT_SUPPORTED;
+ }
+
+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave;
+
+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK)
+ return ret;
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode
+*
+* DESCRIPTION:
+* Exit the deep power save mode.
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Size of the flash in bytes.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo)
+{
+ MV_STATUS ret;
+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH];
+
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return 0;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return MV_BAD_PARAM;
+ }
+
+ /* check that power save mode is supported in the specific device */
+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD)
+ {
+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);)
+ return MV_NOT_SUPPORTED;
+ }
+
+ cmd[0] = sflash[pFlinfo->index].opcdRES;
+
+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK)
+ return ret;
+
+ /* add the delay needed for the device to wake up */
+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvSFlashModelGet - Retreive the string with the device manufacturer and model
+*
+* DESCRIPTION:
+* Retreive the string with the device manufacturer and model
+*
+* INPUT:
+* pFlinfo: pointer to the Flash information structure
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* pointer to the string indicating the device manufacturer and model
+*
+*
+*******************************************************************************/
+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo)
+{
+ static const MV_8 * unknModel = (const MV_8 *)"Unknown";
+
+ /* check for NULL pointer */
+ if (pFlinfo == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return 0;
+ }
+
+ /* Protection - check if the model was detected */
+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash))
+ {
+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);)
+ return unknModel;
+ }
+
+ return sflash[pFlinfo->index].deviceModel;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h
new file mode 100644
index 000000000..f441a5cf5
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h
@@ -0,0 +1,166 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSFlashH
+#define __INCmvSFlashH
+
+#include "mvTypes.h"
+
+/* MCAROS */
+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1)
+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0])))
+
+/* Constants */
+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF
+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/
+#define MV_SFLASH_BASIC_SPI_FREQ 10000000
+/* enumerations */
+typedef enum
+{
+ MV_WP_NONE, /* Unprotect the whole chip */
+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */
+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */
+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */
+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */
+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */
+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */
+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */
+ MV_WP_ALL /* Write protect the whole chip */
+} MV_SFLASH_WP_REGION;
+
+/* Type Definitions */
+typedef struct
+{
+ MV_U8 opcdWREN; /* Write enable opcode */
+ MV_U8 opcdWRDI; /* Write disable opcode */
+ MV_U8 opcdRDID; /* Read ID opcode */
+ MV_U8 opcdRDSR; /* Read Status Register opcode */
+ MV_U8 opcdWRSR; /* Write Status register opcode */
+ MV_U8 opcdREAD; /* Read opcode */
+ MV_U8 opcdFSTRD; /* Fast Read opcode */
+ MV_U8 opcdPP; /* Page program opcode */
+ MV_U8 opcdSE; /* Sector erase opcode */
+ MV_U8 opcdBE; /* Bulk erase opcode */
+ MV_U8 opcdRES; /* Read electronic signature */
+ MV_U8 opcdPwrSave; /* Go into power save mode */
+ MV_U32 sectorSize; /* Size of each sector */
+ MV_U32 sectorNumber; /* Number of sectors */
+ MV_U32 pageSize; /* size of each page */
+ const char * deviceModel; /* string with the device model */
+ MV_U32 manufacturerId; /* The manufacturer ID */
+ MV_U32 deviceId; /* Device ID */
+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */
+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */
+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */
+} MV_SFLASH_DEVICE_PARAMS;
+
+typedef struct
+{
+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */
+ MV_U8 manufacturerId; /* Manufacturer ID */
+ MV_U16 deviceId; /* Device ID */
+ MV_U32 sectorSize; /* Size of each sector - all the same */
+ MV_U32 sectorNumber; /* Number of sectors */
+ MV_U32 pageSize; /* Page size - affect allignment */
+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */
+} MV_SFLASH_INFO;
+
+/* Function Prototypes */
+/* Init */
+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo);
+
+/* erase */
+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber);
+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo);
+
+/* Read */
+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pReadBuff, MV_U32 buffSize);
+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pReadBuff, MV_U32 buffSize);
+
+/* write regardless of the page boundaries and size limit per Page program command */
+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset,
+ MV_U8* pWriteBuff, MV_U32 buffSize);
+/* Get IDs */
+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId);
+
+/* Set and Get the Write Protection region - if the Status register is not locked */
+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion);
+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion);
+
+/* Lock the status register for writing - W/Vpp pin should be low to take effect */
+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock);
+
+/* Get the regions sizes */
+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo);
+
+/* Cause the falsh device to go into power save mode */
+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo);
+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo);
+
+/* Retreive the string with the device manufacturer and model */
+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo);
+
+#endif /* __INCmvSFlashH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h
new file mode 100644
index 000000000..eeb44262e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h
@@ -0,0 +1,233 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSFlashSpecH
+#define __INCmvSFlashSpecH
+
+/* Constants */
+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */
+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */
+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */
+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */
+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */
+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */
+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */
+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */
+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */
+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */
+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */
+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */
+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */
+
+/* Status Register Bit Masks */
+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */
+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */
+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */
+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET)
+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET)
+
+#define MV_SFLASH_MAX_WAIT_LOOP 1000000
+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000
+
+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */
+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */
+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00
+
+/********************************/
+/* ST M25Pxxx Device Specific */
+/********************************/
+
+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
+#define MV_M25PXXX_ST_MANF_ID 0x20
+#define MV_M25P32_DEVICE_ID 0x2016
+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */
+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1
+#define MV_M25P64_DEVICE_ID 0x2017
+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */
+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1
+#define MV_M25P128_DEVICE_ID 0x2018
+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */
+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1
+
+
+/* Sector Sizes and population per device model*/
+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */
+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */
+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */
+#define MV_M25P32_SECTOR_NUMBER 64
+#define MV_M25P64_SECTOR_NUMBER 128
+#define MV_M25P128_SECTOR_NUMBER 64
+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */
+
+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */
+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */
+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */
+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */
+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */
+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */
+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */
+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */
+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */
+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */
+
+/* Status Register Write Protect Bit Masks - 3bits */
+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+
+/************************************/
+/* MXIC MX25L6405 Device Specific */
+/************************************/
+
+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
+#define MV_MXIC_MANF_ID 0xC2
+#define MV_MX25L6405_DEVICE_ID 0x2017
+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */
+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */
+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1
+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */
+
+/* Sector Sizes and population per device model*/
+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */
+#define MV_MX25L6405_SECTOR_NUMBER 128
+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */
+
+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */
+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */
+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */
+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */
+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */
+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */
+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */
+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */
+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */
+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */
+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */
+
+/* Status Register Write Protect Bit Masks - 4bits */
+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
+
+/************************************/
+/* SPANSION S25FL128P Device Specific */
+/************************************/
+
+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */
+#define MV_SPANSION_MANF_ID 0x01
+#define MV_S25FL128_DEVICE_ID 0x2018
+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */
+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */
+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1
+
+/* Sector Sizes and population per device model*/
+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */
+#define MV_S25FL128_SECTOR_NUMBER 64
+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */
+
+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */
+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */
+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */
+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */
+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */
+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */
+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */
+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */
+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */
+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */
+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */
+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */
+
+/* Status Register Write Protect Bit Masks - 4bits */
+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET)
+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET)
+
+#endif /* __INCmvSFlashSpecH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt
new file mode 100644
index 000000000..85bfa612c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.3
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c
new file mode 100644
index 000000000..39e0b720d
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c
@@ -0,0 +1,576 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "spi/mvSpi.h"
+#include "spi/mvSpiSpec.h"
+
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+/* #define MV_DEBUG */
+#ifdef MV_DEBUG
+#define DB(x) x
+#define mvOsPrintf printf
+#else
+#define DB(x)
+#endif
+
+
+/*******************************************************************************
+* mvSpi16bitDataTxRx - Transmt and receive data
+*
+* DESCRIPTION:
+* Tx data and block waiting for data to be transmitted
+*
+********************************************************************************/
+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData)
+{
+ MV_U32 i;
+ MV_BOOL ready = MV_FALSE;
+
+ /* First clear the bit in the interrupt cause register */
+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0);
+
+ /* Transmit data */
+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData));
+
+ /* wait with timeout for memory ready */
+ for (i=0; i<MV_SPI_WAIT_RDY_MAX_LOOP; i++)
+ {
+ if (MV_REG_READ(MV_SPI_INT_CAUSE_REG))
+ {
+ ready = MV_TRUE;
+ break;
+ }
+#ifdef MV_SPI_SLEEP_ON_WAIT
+ mvOsSleep(1);
+#endif /* MV_SPI_SLEEP_ON_WAIT */
+ }
+
+ if (!ready)
+ return MV_TIMEOUT;
+
+ /* check that the RX data is needed */
+ if (pRxData)
+ {
+ if ((MV_U32)pRxData & 0x1) /* check if address is not alligned to 16bit */
+ {
+#if defined(MV_CPU_LE)
+ /* perform the data write to the buffer in two stages with 8bit each */
+ MV_U8 * bptr = (MV_U8*)pRxData;
+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG));
+ *bptr = (data & 0xFF);
+ ++bptr;
+ *bptr = ((data >> 8) & 0xFF);
+
+#elif defined(MV_CPU_BE)
+
+ /* perform the data write to the buffer in two stages with 8bit each */
+ MV_U8 * bptr = (MV_U8 *)pRxData;
+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG));
+ *bptr = ((data >> 8) & 0xFF);
+ ++bptr;
+ *bptr = (data & 0xFF);
+
+#else
+ #error "CPU endianess isn't defined!\n"
+#endif
+
+ }
+ else
+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG));
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvSpi8bitDataTxRx - Transmt and receive data (8bits)
+*
+* DESCRIPTION:
+* Tx data and block waiting for data to be transmitted
+*
+********************************************************************************/
+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData)
+{
+ MV_U32 i;
+ MV_BOOL ready = MV_FALSE;
+
+ /* First clear the bit in the interrupt cause register */
+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0);
+
+ /* Transmit data */
+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData);
+
+ /* wait with timeout for memory ready */
+ for (i=0; i<MV_SPI_WAIT_RDY_MAX_LOOP; i++)
+ {
+ if (MV_REG_READ(MV_SPI_INT_CAUSE_REG))
+ {
+ ready = MV_TRUE;
+ break;
+ }
+#ifdef MV_SPI_SLEEP_ON_WAIT
+ mvOsSleep(1);
+#endif /* MV_SPI_SLEEP_ON_WAIT */
+ }
+
+ if (!ready)
+ return MV_TIMEOUT;
+
+ /* check that the RX data is needed */
+ if (pRxData)
+ *pRxData = MV_REG_READ(MV_SPI_DATA_IN_REG);
+
+ return MV_OK;
+}
+
+/*
+#####################################################################################
+#####################################################################################
+*/
+
+/*******************************************************************************
+* mvSpiInit - Initialize the SPI controller
+*
+* DESCRIPTION:
+* Perform the neccessary initialization in order to be able to send an
+* receive over the SPI interface.
+*
+* INPUT:
+* serialBaudRate: Baud rate (SPI clock frequency)
+* use16BitMode: Whether to use 2bytes (MV_TRUE) or 1bytes (MV_FALSE)
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiInit (MV_U32 serialBaudRate)
+{
+ MV_STATUS ret;
+
+ /* Set the serial clock */
+ if ((ret = mvSpiBaudRateSet(serialBaudRate)) != MV_OK)
+ return ret;
+
+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/
+ mvMPPConfigToSPI();
+
+ /* Configure the default SPI mode to be 16bit */
+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* Fix ac timing on SPI in 6183, 6183L and 78x00 only */
+ if ( (mvCtrlModelGet() == MV_6183_DEV_ID) ||
+ (mvCtrlModelGet() == MV_6183L_DEV_ID) ||
+ (mvCtrlModelGet() == MV_78100_DEV_ID) ||
+ (mvCtrlModelGet() == MV_78200_DEV_ID) ||
+ (mvCtrlModelGet() == MV_76100_DEV_ID))
+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, BIT14);
+
+ /* Verify that the CS is deasserted */
+ mvSpiCsDeassert();
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSpiBaudRateSet - Set the Frequency of the SPI clock
+*
+* DESCRIPTION:
+* Set the Prescale bits to adapt to the requested baud rate (the clock
+* used for thr SPI).
+*
+* INPUT:
+* serialBaudRate: Baud rate (SPI clock frequency)
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiBaudRateSet (MV_U32 serialBaudRate)
+{
+ MV_U8 i;
+ /* MV_U8 preScale[32] = {1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30};
+ */
+ MV_U8 preScale[14] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30};
+ MV_U8 bestPrescaleIndx = 100;
+ MV_U32 minBaudOffset = 0xFFFFFFFF;
+ MV_U32 cpuClk = mvBoardTclkGet(); /*mvCpuPclkGet();*/
+ MV_U32 tempReg;
+
+ /* Find the best prescale configuration - less or equal */
+ for (i=0; i<14; i++)
+ {
+ /* check for higher - irrelevent */
+ if ((cpuClk / preScale[i]) > serialBaudRate)
+ continue;
+
+ /* check for exact fit */
+ if ((cpuClk / preScale[i]) == serialBaudRate)
+ {
+ bestPrescaleIndx = i;
+ break;
+ }
+
+ /* check if this is better than the previous one */
+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset)
+ {
+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i]));
+ bestPrescaleIndx = i;
+ }
+ }
+
+ if (bestPrescaleIndx > 14)
+ {
+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__);
+ return MV_OUT_OF_RANGE;
+ }
+
+ /* configure the Prescale */
+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG);
+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12));
+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer
+*
+* DESCRIPTION:
+* Assert The chip select - used to select an external SPI device
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Success or Error code.
+*
+********************************************************************************/
+MV_VOID mvSpiCsAssert(MV_VOID)
+{
+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/
+ mvMPPConfigToSPI();
+ mvOsUDelay(1);
+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK);
+}
+
+/*******************************************************************************
+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a
+* SPI transfer sequence
+*
+* DESCRIPTION:
+* DeAssert the chip select pin
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Success or Error code.
+*
+********************************************************************************/
+MV_VOID mvSpiCsDeassert(MV_VOID)
+{
+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK);
+
+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/
+ mvMPPConfigToDefault();
+}
+
+/*******************************************************************************
+* mvSpiRead - Read a buffer over the SPI interface
+*
+* DESCRIPTION:
+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the
+* buffer size is odd, then the last chunk will be 8bits. Chip select is not
+* handled at this level.
+*
+* INPUT:
+* pRxBuff: Pointer to the buffer to hold the received data
+* buffSize: length of the pRxBuff
+*
+* OUTPUT:
+* pRxBuff: Pointer to the buffer with the received data
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize)
+{
+ MV_STATUS ret;
+ MV_U32 bytesLeft = buffSize;
+ MV_U16* rxPtr = (MV_U16*)pRxBuff;
+
+ /* check for null parameters */
+ if (pRxBuff == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check that the buffer pointer and the buffer size are 16bit aligned */
+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0))
+ {
+ /* Verify that the SPI mode is in 16bit mode */
+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* TX/RX as long we have complete 16bit chunks */
+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE)
+ {
+ /* Transmitted and wait for the transfer to be completed */
+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK)
+ return ret;
+
+ /* increment the pointers */
+ rxPtr++;
+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE;
+ }
+
+ }
+ else
+ {
+ /* Verify that the SPI mode is in 8bit mode */
+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* TX/RX in 8bit chanks */
+ while (bytesLeft > 0)
+ {
+ /* Transmitted and wait for the transfer to be completed */
+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK)
+ return ret;
+ /* increment the pointers */
+ pRxBuff++;
+ bytesLeft--;
+ }
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvSpiWrite - Transmit a buffer over the SPI interface
+*
+* DESCRIPTION:
+* Transmit a buffer over the SPI interface in 16bit chunks. If the
+* buffer size is odd, then the last chunk will be 8bits. No chip select
+* action is taken.
+*
+* INPUT:
+* pTxBuff: Pointer to the buffer holding the TX data
+* buffSize: length of the pTxBuff
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize)
+{
+ MV_STATUS ret;
+ MV_U32 bytesLeft = buffSize;
+ MV_U16* txPtr = (MV_U16*)pTxBuff;
+
+ /* check for null parameters */
+ if (pTxBuff == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check that the buffer pointer and the buffer size are 16bit aligned */
+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0))
+ {
+ /* Verify that the SPI mode is in 16bit mode */
+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* TX/RX as long we have complete 16bit chunks */
+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE)
+ {
+ /* Transmitted and wait for the transfer to be completed */
+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK)
+ return ret;
+
+ /* increment the pointers */
+ txPtr++;
+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE;
+ }
+ }
+ else
+ {
+
+ /* Verify that the SPI mode is in 8bit mode */
+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* TX/RX in 8bit chanks */
+ while (bytesLeft > 0)
+ {
+ /* Transmitted and wait for the transfer to be completed */
+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK)
+ return ret;
+
+ /* increment the pointers */
+ pTxBuff++;
+ bytesLeft--;
+ }
+ }
+
+ return MV_OK;
+}
+
+
+/*******************************************************************************
+* mvSpiReadWrite - Read and Write a buffer simultanuosely
+*
+* DESCRIPTION:
+* Transmit and receive a buffer over the SPI in 16bit chunks. If the
+* buffer size is odd, then the last chunk will be 8bits. The SPI chip
+* select is not handled implicitely.
+*
+* INPUT:
+* pRxBuff: Pointer to the buffer to write the RX info in
+* pTxBuff: Pointer to the buffer holding the TX info
+* buffSize: length of both the pTxBuff and pRxBuff
+*
+* OUTPUT:
+* pRxBuff: Pointer of the buffer holding the RX data
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize)
+{
+ MV_STATUS ret;
+ MV_U32 bytesLeft = buffSize;
+ MV_U16* txPtr = (MV_U16*)pTxBuff;
+ MV_U16* rxPtr = (MV_U16*)pRxBuff;
+
+ /* check for null parameters */
+ if ((pRxBuff == NULL) || (pTxBuff == NULL))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* Check that the buffer pointer and the buffer size are 16bit aligned */
+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0))
+ {
+ /* Verify that the SPI mode is in 16bit mode */
+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* TX/RX as long we have complete 16bit chunks */
+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE)
+ {
+ /* Transmitted and wait for the transfer to be completed */
+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK)
+ return ret;
+
+ /* increment the pointers */
+ txPtr++;
+ rxPtr++;
+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE;
+ }
+ }
+ else
+ {
+ /* Verify that the SPI mode is in 8bit mode */
+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK);
+
+ /* TX/RX in 8bit chanks */
+ while (bytesLeft > 0)
+ {
+ /* Transmitted and wait for the transfer to be completed */
+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK)
+ return ret;
+ pRxBuff++;
+ pTxBuff++;
+ bytesLeft--;
+ }
+ }
+
+ return MV_OK;
+}
+
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h
new file mode 100644
index 000000000..74859f03e
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h
@@ -0,0 +1,94 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSpihH
+#define __INCmvSpihH
+
+#include "mvCommon.h"
+#include "mvOs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+
+/* Function Prototypes */
+/* Init */
+MV_STATUS mvSpiInit (MV_U32 serialBaudRate);
+
+/* Set the Frequency of the Spi clock */
+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate);
+
+/* Assert the SPI chip select */
+MV_VOID mvSpiCsAssert (MV_VOID);
+
+/* De-assert the SPI chip select */
+MV_VOID mvSpiCsDeassert (MV_VOID);
+
+/* Simultanuous Read and write */
+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize);
+
+/* serialize a buffer on the TX line - Rx is ignored */
+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize);
+
+/* read from the RX line by writing dummy values to the TX line */
+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize);
+
+#endif /* __INCmvSpihH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c
new file mode 100644
index 000000000..a5d5a6478
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c
@@ -0,0 +1,249 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "spi/mvSpi.h"
+#include "spi/mvSpiSpec.h"
+
+/*#define MV_DEBUG*/
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+
+/*******************************************************************************
+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely
+*
+* DESCRIPTION:
+* Transmit and receive a buffer over the SPI in 16bit chunks. If the
+* buffer size is odd, then the last chunk will be 8bits.
+*
+* INPUT:
+* pRxBuff: Pointer to the buffer to write the RX info in
+* pTxBuff: Pointer to the buffer holding the TX info
+* buffSize: length of both the pTxBuff and pRxBuff
+*
+* OUTPUT:
+* pRxBuff: Pointer of the buffer holding the RX data
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize)
+{
+ MV_STATUS ret;
+
+ /* check for null parameters */
+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* First assert the chip select */
+ mvSpiCsAssert();
+
+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize);
+
+ /* Finally deassert the chip select */
+ mvSpiCsDeassert();
+
+ return ret;
+}
+
+/*******************************************************************************
+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line
+*
+* DESCRIPTION:
+* Assert the chip select line. Transmit the command buffer followed by
+* the data buffer. Then deassert the CS line.
+*
+* INPUT:
+* pCmndBuff: Pointer to the command buffer to transmit
+* cmndSize: length of the command size
+* pTxDataBuff: Pointer to the data buffer to transmit
+* txDataSize: length of the data buffer
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff,
+ MV_U32 txDataSize)
+{
+ MV_STATUS ret = MV_OK, tempRet;
+
+ /* check for null parameters */
+#ifndef CONFIG_MARVELL
+ if(NULL == pTxDataBuff)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+#endif
+
+ if (pCmndBuff == NULL)
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* First assert the chip select */
+ mvSpiCsAssert();
+
+ /* first write the command */
+ if ((cmndSize) && (pCmndBuff != NULL))
+ {
+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK)
+ ret = tempRet;
+ }
+
+ /* Then write the data buffer */
+#ifndef CONFIG_MARVELL
+ if (txDataSize)
+#else
+ if ((txDataSize) && (pTxDataBuff != NULL))
+#endif
+ {
+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK)
+ ret = tempRet;
+ }
+
+ /* Finally deassert the chip select */
+ mvSpiCsDeassert();
+
+ return ret;
+}
+
+/*******************************************************************************
+* mvSpiWriteThenRead - Serialize a command then read a data buffer
+*
+* DESCRIPTION:
+* Assert the chip select line. Transmit the command buffer then read
+* the data buffer. Then deassert the CS line.
+*
+* INPUT:
+* pCmndBuff: Pointer to the command buffer to transmit
+* cmndSize: length of the command size
+* pRxDataBuff: Pointer to the buffer to read the data in
+* txDataSize: length of the data buffer
+*
+* OUTPUT:
+* pRxDataBuff: Pointer to the buffer holding the data
+*
+* RETURN:
+* Success or Error code.
+*
+*
+*******************************************************************************/
+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff,
+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead)
+{
+ MV_STATUS ret = MV_OK, tempRet;
+ MV_U8 dummyByte;
+
+ /* check for null parameters */
+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL))
+ {
+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__);
+ return MV_BAD_PARAM;
+ }
+
+ /* First assert the chip select */
+ mvSpiCsAssert();
+
+ /* first write the command */
+ if ((cmndSize) && (pCmndBuff != NULL))
+ {
+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK)
+ ret = tempRet;
+ }
+
+ /* Read dummy bytes before real data. */
+ while(dummyBytesToRead)
+ {
+ mvSpiRead(&dummyByte,1);
+ dummyBytesToRead--;
+ }
+
+ /* Then write the data buffer */
+ if ((rxDataSize) && (pRxDataBuff != NULL))
+ {
+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK)
+ ret = tempRet;
+ }
+
+ /* Finally deassert the chip select */
+ mvSpiCsDeassert();
+
+ return ret;
+}
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h
new file mode 100644
index 000000000..329e26b7c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h
@@ -0,0 +1,82 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSpiCmndhH
+#define __INCmvSpiCmndhH
+
+#include "mvTypes.h"
+
+/* Function Prototypes */
+
+/* Simultanuous Read and write */
+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize);
+
+/* write command - write a command and then write data */
+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize);
+
+/* read command - write a command and then read data by writing dummy data */
+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff,
+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead);
+
+#endif /* __INCmvSpiCmndhH */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h
new file mode 100644
index 000000000..658159abb
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h
@@ -0,0 +1,98 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __INCmvSpiSpecH
+#define __INCmvSpiSpecH
+
+/* Constants */
+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000
+#define MV_SPI_16_BIT_CHUNK_SIZE 2
+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF
+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF
+
+/* Marvell Flash Device Controller Registers */
+#define MV_SPI_CTRLR_OFST 0x10600
+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00)
+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04)
+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08)
+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c)
+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10)
+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14)
+
+/* Serial Memory Interface Control Register Masks */
+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */
+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */
+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET)
+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET)
+
+/* Serial Memory Interface Configuration Register Masks */
+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */
+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */
+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */
+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET)
+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET)
+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET)
+
+#endif /* __INCmvSpiSpecH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt
new file mode 100644
index 000000000..40531164c
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt
@@ -0,0 +1,4 @@
+Global HAL Version: FEROCEON_HAL_3_1_7
+Unit HAL Version: 3.1.5
+Description: This component includes an implementation of the unit HAL drivers
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c
new file mode 100644
index 000000000..0bf8b7571
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c
@@ -0,0 +1,1023 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include "mvTwsi.h"
+#include "mvTwsiSpec.h"
+#include "cpu/mvCpu.h"
+
+
+/*#define MV_DEBUG*/
+#ifdef MV_DEBUG
+#define DB(x) x
+#else
+#define DB(x)
+#endif
+
+static MV_VOID twsiIntFlgClr(MV_U8 chanNum);
+static MV_BOOL twsiMainIntGet(MV_U8 chanNum);
+static MV_VOID twsiAckBitSet(MV_U8 chanNum);
+static MV_U32 twsiStsGet(MV_U8 chanNum);
+static MV_VOID twsiReset(MV_U8 chanNum);
+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command);
+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command);
+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize);
+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize);
+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256);
+
+
+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString)
+{
+ if(timeout >= TWSI_TIMEOUT_VALUE)
+ {
+ DB(mvOsPrintf("%s",pString));
+ return MV_TRUE;
+ }
+ return MV_FALSE;
+
+}
+/*******************************************************************************
+* mvTwsiStartBitSet - Set start bit on the bus
+*
+* DESCRIPTION:
+* This routine sets the start bit on the TWSI bus.
+* The routine first checks for interrupt flag condition, then it sets
+* the start bit in the TWSI Control register.
+* If the interrupt flag condition check previously was set, the function
+* will clear it.
+* The function then wait for the start bit to be cleared by the HW.
+* Then it waits for the interrupt flag to be set and eventually, the
+* TWSI status is checked to be 0x8 or 0x10(repeated start bit).
+*
+* INPUT:
+* chanNum - TWSI channel.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK is start bit was set successfuly on the bus.
+* MV_FAIL if interrupt flag was set before setting start bit.
+*
+*******************************************************************************/
+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum)
+{
+ MV_BOOL isIntFlag = MV_FALSE;
+ MV_U32 timeout, temp;
+
+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n"));
+ /* check Int flag */
+ if(twsiMainIntGet(chanNum))
+ isIntFlag = MV_TRUE;
+ /* set start Bit */
+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT);
+
+ /* in case that the int flag was set before i.e. repeated start bit */
+ if(isIntFlag){
+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n"));
+ twsiIntFlgClr(chanNum);
+ }
+
+ /* wait for interrupt */
+ timeout = 0;
+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n"))
+ return MV_TIMEOUT;
+
+
+ /* check that start bit went down */
+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0)
+ {
+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n");
+ return MV_FAIL;
+ }
+
+ /* check the status */
+ temp = twsiStsGet(chanNum);
+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA ))
+ {
+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp);
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+
+}
+
+/*******************************************************************************
+* mvTwsiStopBitSet - Set stop bit on the bus
+*
+* DESCRIPTION:
+* This routine set the stop bit on the TWSI bus.
+* The function then wait for the stop bit to be cleared by the HW.
+* Finally the function checks for status of 0xF8.
+*
+* INPUT:
+* chanNum - TWSI channel
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE is stop bit was set successfuly on the bus.
+*
+*******************************************************************************/
+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum)
+{
+ MV_U32 timeout, temp;
+
+ /* Generate stop bit */
+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT);
+
+ twsiIntFlgClr(chanNum);
+
+ /* wait for stop bit to come down */
+ timeout = 0;
+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n"))
+ return MV_TIMEOUT;
+
+ /* check that the stop bit went down */
+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0)
+ {
+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n");
+ return MV_FAIL;
+ }
+
+ /* check the status */
+ temp = twsiStsGet(chanNum);
+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){
+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp);
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* twsiMainIntGet - Get twsi bit from main Interrupt cause.
+*
+* DESCRIPTION:
+* This routine returns the twsi interrupt flag value.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise.
+*
+*******************************************************************************/
+static MV_BOOL twsiMainIntGet(MV_U8 chanNum)
+{
+ MV_U32 temp;
+
+ /* get the int flag bit */
+
+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG);
+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum))
+ return MV_TRUE;
+
+ return MV_FALSE;
+}
+/*******************************************************************************
+* twsiIntFlgClr - Clear Interrupt flag.
+*
+* DESCRIPTION:
+* This routine clears the interrupt flag. It does NOT poll the interrupt
+* to make sure the clear. After clearing the interrupt, it waits for at
+* least 1 miliseconds.
+*
+* INPUT:
+* chanNum - TWSI channel
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static MV_VOID twsiIntFlgClr(MV_U8 chanNum)
+{
+ MV_U32 temp;
+
+ /* wait for 1 mili to prevent TWSI register write after write problems */
+ mvOsDelay(1);
+ /* clear the int flag bit */
+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET));
+
+ /* wait for 1 mili sec for the clear to take effect */
+ mvOsDelay(1);
+
+ return;
+}
+
+
+/*******************************************************************************
+* twsiAckBitSet - Set acknowledge bit on the bus
+*
+* DESCRIPTION:
+* This routine set the acknowledge bit on the TWSI bus.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+static MV_VOID twsiAckBitSet(MV_U8 chanNum)
+{
+ MV_U32 temp;
+
+ /*Set the Ack bit */
+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK);
+
+ /* Add delay of 1ms */
+ mvOsDelay(1);
+ return;
+}
+
+
+/*******************************************************************************
+* twsiInit - Initialize TWSI interface
+*
+* DESCRIPTION:
+* This routine:
+* -Reset the TWSI.
+* -Initialize the TWSI clock baud rate according to given frequancy
+* parameter based on Tclk frequancy and enables TWSI slave.
+* -Set the ack bit.
+* -Assign the TWSI slave address according to the TWSI address Type.
+*
+*
+* INPUT:
+* chanNum - TWSI channel
+* frequancy - TWSI frequancy in KHz. (up to 100KHZ)
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* Actual frequancy.
+*
+*******************************************************************************/
+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable)
+{
+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff;
+ MV_U32 power;
+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val;
+
+ if(frequancy > 100000)
+ {
+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n");
+ }
+
+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy));
+ /* Calucalte N and M for the TWSI clock baud rate */
+ for(n = 0 ; n < 8 ; n++)
+ {
+ for(m = 0 ; m < 16 ; m++)
+ {
+ power = 2 << n; /* power = 2^(n+1) */
+ freq = Tclk/(10*(m+1)*power);
+ margin = MV_ABS(frequancy - freq);
+ if(margin < minMargin)
+ {
+ minMargin = margin;
+ actualFreq = freq;
+ actualN = n;
+ actualM = m;
+ }
+ }
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq));
+ /* Reset the TWSI logic */
+ twsiReset(chanNum);
+
+ /* Set the baud rate */
+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS);
+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val);
+
+ /* Enable the TWSI and slave */
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK);
+
+ /* set the TWSI slave address */
+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */
+ {
+ /* writing the 2 most significant bits of the 10 bit address*/
+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS );
+ /* bits 7:3 must be 0x11110 */
+ val |= TWSI_SLAVE_ADDR_10BIT_CONST;
+ /* set GCE bit */
+ if(generalCallEnable)
+ val |= TWSI_SLAVE_ADDR_GCE_ENA;
+ /* write slave address */
+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val);
+
+ /* writing the 8 least significant bits of the 10 bit address*/
+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK;
+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val);
+ }
+ else /*7 bit address*/
+ {
+ /* set the 7 Bits address */
+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0);
+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK;
+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val);
+ }
+
+ /* unmask twsi int */
+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA);
+ /* Add delay of 1ms */
+ mvOsDelay(1);
+
+ return actualFreq;
+}
+
+
+/*******************************************************************************
+* twsiStsGet - Get the TWSI status value.
+*
+* DESCRIPTION:
+* This routine returns the TWSI status value.
+*
+* INPUT:
+* chanNum - TWSI channel
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_U32 - the TWSI status.
+*
+*******************************************************************************/
+static MV_U32 twsiStsGet(MV_U8 chanNum)
+{
+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum));
+
+}
+
+/*******************************************************************************
+* twsiReset - Reset the TWSI.
+*
+* DESCRIPTION:
+* Resets the TWSI logic and sets all TWSI registers to their reset values.
+*
+* INPUT:
+* chanNum - TWSI channel
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None
+*
+*******************************************************************************/
+static MV_VOID twsiReset(MV_U8 chanNum)
+{
+ /* Reset the TWSI logic */
+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0);
+
+ /* wait for 2 mili sec */
+ mvOsDelay(2);
+
+ return;
+}
+
+
+
+
+/******************************* POLICY ****************************************/
+
+
+
+/*******************************************************************************
+* mvTwsiAddrSet - Set address on TWSI bus.
+*
+* DESCRIPTION:
+* This function Set address (7 or 10 Bit address) on the Twsi Bus.
+*
+* INPUT:
+* chanNum - TWSI channel
+* pTwsiAddr - twsi address.
+* command - read / write .
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK - if setting the address completed succesfully.
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command)
+{
+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\
+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") ));
+ /* 10 Bit address */
+ if(pTwsiAddr->type == ADDR10_BIT)
+ {
+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command);
+ }
+ /* 7 Bit address */
+ else
+ {
+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command);
+ }
+
+}
+
+/*******************************************************************************
+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus.
+*
+* DESCRIPTION:
+* There are two address phases:
+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB
+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit
+* to the Data register. Then it clears interrupt flag which drive
+* the address on the TWSI bus. The function then waits for interrupt
+* flag to be active and status 0x18 (write) or 0x40 (read) to be set.
+* 2) write the rest of 10-bit address to data register and clears
+* interrupt flag which drive the address on the TWSI bus. The
+* function then waits for interrupt flag to be active and status
+* 0xD0 (write) or 0xE0 (read) to be set.
+*
+* INPUT:
+* chanNum - TWSI channel
+* deviceAddress - twsi address.
+* command - read / write .
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK - if setting the address completed succesfully.
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command)
+{
+ MV_U32 val,timeout;
+
+ /* writing the 2 most significant bits of the 10 bit address*/
+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS );
+ /* bits 7:3 must be 0x11110 */
+ val |= TWSI_DATA_ADDR_10BIT_CONST;
+ /* set command */
+ val |= command;
+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val);
+ /* WA add a delay */
+ mvOsDelay(1);
+
+ /* clear Int flag */
+ twsiIntFlgClr(chanNum);
+
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n"))
+ return MV_TIMEOUT;
+
+ /* check the status */
+ val = twsiStsGet(chanNum);
+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) ||
+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) ))
+ {
+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\
+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") );
+ return MV_FAIL;
+ }
+
+ /* set 8 LSB of the address */
+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK;
+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val);
+
+ /* clear Int flag */
+ twsiIntFlgClr(chanNum);
+
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n"))
+ return MV_TIMEOUT;
+
+ /* check the status */
+ val = twsiStsGet(chanNum);
+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) ||
+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) ))
+ {
+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\
+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") );
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus.
+*
+* DESCRIPTION:
+* This function writes 7 bit address plus a write or read bit to the
+* Data register. Then it clears interrupt flag which drive the address on
+* the TWSI bus. The function then waits for interrupt flag to be active
+* and status 0x18 (write) or 0x40 (read) to be set.
+*
+* INPUT:
+* chanNum - TWSI channel
+* deviceAddress - twsi address.
+* command - read / write .
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK - if setting the address completed succesfully.
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command)
+{
+ MV_U32 val,timeout;
+
+ /* set the address */
+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK;
+ /* set command */
+ val |= command;
+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val);
+ /* WA add a delay */
+ mvOsDelay(1);
+
+ /* clear Int flag */
+ twsiIntFlgClr(chanNum);
+
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n"))
+ return MV_TIMEOUT;
+
+ /* check the status */
+ val = twsiStsGet(chanNum);
+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) ||
+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) ))
+ {
+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't
+ want error messeges in case DIMM doesn't exist. */
+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\
+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") ));
+ return MV_FAIL;
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* twsiDataWrite - Trnasmit a data block over TWSI bus.
+*
+* DESCRIPTION:
+* This function writes a given data block to TWSI bus in 8 bit granularity.
+* first The function waits for interrupt flag to be active then
+* For each 8-bit data:
+* The function writes data to data register. It then clears
+* interrupt flag which drives the data on the TWSI bus.
+* The function then waits for interrupt flag to be active and status
+* 0x28 to be set.
+*
+*
+* INPUT:
+* chanNum - TWSI channel
+* pBlock - Data block.
+* blockSize - number of chars in pBlock.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK - if transmiting the block completed succesfully,
+* MV_BAD_PARAM - if pBlock is NULL,
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize)
+{
+ MV_U32 timeout, temp, blockSizeWr = blockSize;
+
+ if(NULL == pBlock)
+ return MV_BAD_PARAM;
+
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n"))
+ return MV_TIMEOUT;
+
+ while(blockSizeWr)
+ {
+ /* write the data*/
+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock);
+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\
+ blockSize - blockSizeWr, *pBlock));
+ pBlock++;
+ blockSizeWr--;
+
+ twsiIntFlgClr(chanNum);
+
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n"))
+ return MV_TIMEOUT;
+
+ /* check the status */
+ temp = twsiStsGet(chanNum);
+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC)
+ {
+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp);
+ return MV_FAIL;
+ }
+
+ }
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* twsiDataReceive - Receive data block from TWSI bus.
+*
+* DESCRIPTION:
+* This function receive data block from TWSI bus in 8bit granularity
+* into pBlock buffer.
+* first The function waits for interrupt flag to be active then
+* For each 8-bit data:
+* It clears the interrupt flag which allows the next data to be
+* received from TWSI bus.
+* The function waits for interrupt flag to be active,
+* and status reg is 0x50.
+* Then the function reads data from data register, and copies it to
+* the given buffer.
+*
+* INPUT:
+* chanNum - TWSI channel
+* blockSize - number of bytes to read.
+*
+* OUTPUT:
+* pBlock - Data block.
+*
+* RETURN:
+* MV_OK - if receive transaction completed succesfully,
+* MV_BAD_PARAM - if pBlock is NULL,
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize)
+{
+ MV_U32 timeout, temp, blockSizeRd = blockSize;
+ if(NULL == pBlock)
+ return MV_BAD_PARAM;
+
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n"))
+ return MV_TIMEOUT;
+
+ while(blockSizeRd)
+ {
+ if(blockSizeRd == 1)
+ {
+ /* clear ack and Int flag */
+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum));
+ temp &= ~(TWSI_CONTROL_ACK);
+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp);
+ }
+ twsiIntFlgClr(chanNum);
+ /* wait for Int to be Set */
+ timeout = 0;
+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE));
+
+ /* check for timeout */
+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n"))
+ return MV_TIMEOUT;
+
+ /* check the status */
+ temp = twsiStsGet(chanNum);
+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1))
+ {
+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp);
+ return MV_FAIL;
+ }
+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1))
+ {
+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp);
+ return MV_FAIL;
+ }
+
+ /* read the data*/
+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum));
+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\
+ blockSize - blockSizeRd,*pBlock));
+ pBlock++;
+ blockSizeRd--;
+ }
+
+ return MV_OK;
+}
+
+
+
+/*******************************************************************************
+* twsiTargetOffsSet - Set TWST target offset on TWSI bus.
+*
+* DESCRIPTION:
+* The function support TWSI targets that have inside address space (for
+* example EEPROMs). The function:
+* 1) Convert the given offset into pBlock and size.
+* in case the offset should be set to a TWSI slave which support
+* more then 256 bytes offset, the offset setting will be done
+* in 2 transactions.
+* 2) Use twsiDataTransmit to place those on the bus.
+*
+* INPUT:
+* chanNum - TWSI channel
+* offset - offset to be set on the EEPROM device.
+* moreThen256 - whether the EEPROM device support more then 256 byte offset.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* MV_OK - if setting the offset completed succesfully.
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256)
+{
+ MV_U8 offBlock[2];
+ MV_U32 offSize;
+
+ if(moreThen256 == MV_TRUE)
+ {
+ offBlock[0] = (offset >> 8) & 0xff;
+ offBlock[1] = offset & 0xff;
+ offSize = 2;
+ }
+ else
+ {
+ offBlock[0] = offset & 0xff;
+ offSize = 1;
+ }
+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\
+ offSize,offBlock[0],offBlock[1]));
+ return twsiDataTransmit(chanNum, offBlock, offSize);
+
+}
+
+/*******************************************************************************
+* mvTwsiRead - Read data block from a TWSI Slave.
+*
+* DESCRIPTION:
+* The function calls the following functions:
+* -) mvTwsiStartBitSet();
+* if(EEPROM device)
+* -) mvTwsiAddrSet(w);
+* -) twsiTargetOffsSet();
+* -) mvTwsiStartBitSet();
+* -) mvTwsiAddrSet(r);
+* -) twsiDataReceive();
+* -) mvTwsiStopBitSet();
+*
+* INPUT:
+* chanNum - TWSI channel
+* pTwsiSlave - Twsi Slave structure.
+* blockSize - number of bytes to read.
+*
+* OUTPUT:
+* pBlock - Data block.
+*
+* RETURN:
+* MV_OK - if EEPROM read transaction completed succesfully,
+* MV_BAD_PARAM - if pBlock is NULL,
+* MV_FAIL otherwmise.
+*
+*******************************************************************************/
+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize)
+{
+ if((NULL == pBlock) || (NULL == pTwsiSlave))
+ return MV_BAD_PARAM;
+ if(MV_OK != mvTwsiStartBitSet(chanNum))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n"));
+
+ /* in case offset exsist (i.e. eeprom ) */
+ if(MV_TRUE == pTwsiSlave->validOffset)
+ {
+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n"));
+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n"));
+ if(MV_OK != mvTwsiStartBitSet(chanNum))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n"));
+ }
+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n"));
+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n"));
+
+ if(MV_OK != mvTwsiStopBitSet(chanNum))
+ {
+ return MV_FAIL;
+ }
+
+ twsiAckBitSet(chanNum);
+
+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n"));
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* mvTwsiWrite - Write data block to a TWSI Slave.
+*
+* DESCRIPTION:
+* The function calls the following functions:
+* -) mvTwsiStartBitSet();
+* -) mvTwsiAddrSet();
+* -)if(EEPROM device)
+* -) twsiTargetOffsSet();
+* -) twsiDataTransmit();
+* -) mvTwsiStopBitSet();
+*
+* INPUT:
+* chanNum - TWSI channel
+* eepromAddress - eeprom address.
+* blockSize - number of bytes to write.
+* pBlock - Data block.
+*
+* OUTPUT:
+* None
+*
+* RETURN:
+* MV_OK - if EEPROM read transaction completed succesfully.
+* MV_BAD_PARAM - if pBlock is NULL,
+* MV_FAIL otherwmise.
+*
+* NOTE: Part of the EEPROM, required that the offset will be aligned to the
+* max write burst supported.
+*******************************************************************************/
+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize)
+{
+ if((NULL == pBlock) || (NULL == pTwsiSlave))
+ return MV_BAD_PARAM;
+
+ if(MV_OK != mvTwsiStartBitSet(chanNum))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+
+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n"));
+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n"));
+
+ /* in case offset exsist (i.e. eeprom ) */
+ if(MV_TRUE == pTwsiSlave->validOffset)
+ {
+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n"));
+ }
+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize))
+ {
+ mvTwsiStopBitSet(chanNum);
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n"));
+ if(MV_OK != mvTwsiStopBitSet(chanNum))
+ {
+ return MV_FAIL;
+ }
+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n"));
+
+ return MV_OK;
+}
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h
new file mode 100644
index 000000000..bd5b6d009
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h
@@ -0,0 +1,121 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __INCmvTwsiH
+#define __INCmvTwsiH
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* need to update this includes */
+#include "twsi/mvTwsiSpec.h"
+#include "ctrlEnv/mvCtrlEnvLib.h"
+
+
+/* The TWSI interface supports both 7-bit and 10-bit addressing. */
+/* This enumerator describes addressing type. */
+typedef enum _mvTwsiAddrType
+{
+ ADDR7_BIT, /* 7 bit address */
+ ADDR10_BIT /* 10 bit address */
+}MV_TWSI_ADDR_TYPE;
+
+/* This structure describes TWSI address. */
+typedef struct _mvTwsiAddr
+{
+ MV_U32 address; /* address */
+ MV_TWSI_ADDR_TYPE type; /* Address type */
+}MV_TWSI_ADDR;
+
+/* This structure describes a TWSI slave. */
+typedef struct _mvTwsiSlave
+{
+ MV_TWSI_ADDR slaveAddr;
+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */
+ MV_U32 offset; /* offset in the slave. */
+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */
+}MV_TWSI_SLAVE;
+
+/* This enumerator describes TWSI protocol commands. */
+typedef enum _mvTwsiCmd
+{
+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */
+ MV_TWSI_READ /* TWSI read command - 1 according to spec */
+}MV_TWSI_CMD;
+
+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum);
+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum);
+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command);
+
+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable);
+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize);
+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvTwsiH */
+
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S
new file mode 100644
index 000000000..9d81ef2a6
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S
@@ -0,0 +1,457 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#define MV_ASMLANGUAGE
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "boardEnv/mvBoardEnvSpec.h"
+#include "mvOsAsm.h"
+#include "mvTwsiSpec.h"
+#include "mvSysHwConfig.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "mvCommon.h"
+
+#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL
+
+/* defines */
+/* defines */
+
+
+ .data
+ .global _i2cInit
+ .global _i2cRead
+
+ .text
+
+/*******************************************************************************
+* _i2cInit - Initialize TWSI interface
+*
+* DESCRIPTION:
+* The function performs TWSI interface initialization. It resets the
+* TWSI state machine and initialize its clock to 100KHz assuming Tclock
+* of 133MHz.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+_i2cInit:
+ mov r9, LR /* Save link register */
+ mov r0, #0 /* Make sure r0 is zero */
+
+ /* Reset the i2c Mechanism first */
+ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH))
+
+ bl _twsiDelay
+ bl _twsiDelay
+
+ /* Initializing the I2C mechanism. Assuming Tclock frequency */
+ /* of 166MHz. The I2C frequency in that case will be 100KHz. */
+ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */
+ /* value of 0x2b (freq of ==> 100KHz */
+ /* see spec for more details about the calculation of this value) */
+ mov r6, #(9 << 3 | 3)
+ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+
+ /* Enable the I2C master */
+ /* Enable TWSI interrupt in main mask reg */
+ mov r6, #0xC4
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+ /* Let the slow TWSI machine get used to the idea that it is enabled */
+ bl _twsiDelay
+
+
+ mov PC, r9 /* r9 is saved link register */
+
+/*******************************************************************************
+* _twsiDelay - Perform delay.
+*
+* DESCRIPTION:
+* The function performs a delay to enable TWSI logic to stable.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+_twsiDelay:
+ mov r10, #0x100000 /*was 0x400*/
+
+_twsiDelayLoop:
+ subs r10, r10, #1
+ bne _twsiDelayLoop
+
+ mov PC, LR
+
+/*******************************************************************************
+* _i2cRead - Read byte from I2C EEPROM device.
+*
+* DESCRIPTION:
+* The function returns a byte from I2C EEPROM device.
+* The EEPROM device is 7-bit address type.
+*
+* INPUT:
+* r4 has the DIMM0 base address with shift 1 bit to the left
+* r7 has the EEPROM offset
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* r4 returns '0' if address can not be read.
+* r7 has byte value in case read is successful.
+*
+*******************************************************************************/
+_i2cRead:
+ mov r9, LR /* Save link register */
+
+ /* Transmit the device address and desired offset within the EEPROM. */
+
+ /* Generate Start Bit */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ orr r6, r6, #TWSI_CONTROL_START_BIT
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+ /* Wait for the interrupt flag (bit3) to be set */
+ mov r10, #0x50000
+loop_1:
+ subs r10, r10, #1
+ beq loop_1_timeout
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_1
+
+loop_1_timeout:
+
+ /* Wait for the start bit to be reset by HW */
+ mov r10, #0x50000
+loop_2:
+ subs r10, r10, #1
+ beq loop_2_timeout
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ tst r6, #TWSI_CONTROL_START_BIT
+ bne loop_2
+
+loop_2_timeout:
+
+ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */
+ mov r10, #0x50000
+loop_3:
+ subs r10, r10, #1
+ beq loop_3_timeout
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x08
+ bne loop_3
+
+loop_3_timeout:
+
+ /* writing the address of (DIMM0/1 << 1) with write indication */
+ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */
+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
+
+ bl _twsiDelay
+ /* Clear the interrupt flag */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Waiting for the interrupt flag to be set which means that the
+ address has been transmitted */
+loop_4:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_4 /* if tst = 0, then the bit is not set yet */
+
+ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */
+ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */
+
+loop_5:
+ subs r10, r10, #1 /* timeout count down */
+ bne testStatus
+ mov r4, #0 /* r4 = 0 -> operation failed */
+ b exit_i2cRead /* Exit if timeout (No DIMM) */
+
+testStatus:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x18
+ bne loop_5
+
+
+ /* check if the offset is bigger than 256 byte*/
+ tst r7, #0x80000000
+ bne great_than_256
+
+ /* Write the offset to be read from the DIMM EEPROM */
+ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
+
+ b after_offset
+
+great_than_256:
+ mov r10, r7, LSR #8
+ and r10, r10, #0xff
+ /* Write the offset0 to be read from the EEPROM */
+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
+
+ /* Clear the interrupt flag ==> signaling that the address can now
+ be transmited */
+
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt to be set again ==> address has transmited */
+loop_6_1:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_6_1
+
+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
+loop_7_1:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x28
+ bne loop_7_1
+
+
+ mov r10, r7
+ and r10, r10, #0xff
+ /* Write the offset1 to be read from the EEPROM */
+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
+
+
+
+after_offset:
+
+ /* Clear the interrupt flag ==> signaling that the address can now
+ be transmited */
+
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt to be set again ==> address has transmited */
+loop_6:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_6
+
+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
+loop_7:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x28
+ bne loop_7
+
+ /* Retransmit the device address with read indication to get the data */
+
+ /* generate a repeated start bit */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ orr r6, r6, #TWSI_CONTROL_START_BIT
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+
+ /* Clear the interrupt flag ==> the start bit will be transmitted. */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt flag (bit3) to be set */
+loop_9:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_9
+
+ /* Wait for the start bit to be reset by HW */
+loop_8:
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ tst r6, #TWSI_CONTROL_START_BIT
+ bne loop_8
+
+ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */
+loop_10:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x10
+ bne loop_10
+
+ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */
+ mov r6, r4, LSL #1
+ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */
+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
+
+ /* Clear the interrupt flag ==> the address will be transmitted */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt flag (bit3) to be set as a result of
+ transmitting the address. */
+loop_11:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_11
+
+ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */
+loop_12:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x40
+ bne loop_12
+
+ /* Clear the interrupt flag and the Acknoledge bit */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK)
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt flag (bit3) to be set */
+loop_14:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_14
+
+ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */
+loop_15:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x58
+ bne loop_15
+
+ /* Store the data in r7. */
+ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
+
+ /* Generate stop bit */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ orr r6, r6, #TWSI_CONTROL_STOP_BIT
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+
+ /* Clear the interrupt flag */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the stop bit to be reset by HW */
+loop_16:
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ tst r6, #TWSI_CONTROL_INT_FLAG_SET
+ bne loop_16
+
+exit_i2cRead:
+ mov PC, r9 /* r9 is saved link register */
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h
new file mode 100644
index 000000000..d0c2b9e7b
--- /dev/null
+++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h
@@ -0,0 +1,160 @@
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+/****************************************/
+/* TWSI Registers */
+/****************************************/
+#ifndef __INCmvTwsiSpech
+#define __INCmvTwsiSpech
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* defines */
+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00)
+
+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0
+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1
+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS)
+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7
+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300
+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0
+
+
+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10)
+#define TWSI_EXTENDED_SLAVE_OFFS 0
+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS)
+
+
+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04)
+#define TWSI_DATA_COMMAND_OFFS 0x0
+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS)
+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS)
+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS)
+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1
+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS)
+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7
+#define TWSI_DATA_ADDR_10BIT_MASK 0x300
+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0
+
+
+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08)
+#define TWSI_CONTROL_ACK BIT2
+#define TWSI_CONTROL_INT_FLAG_SET BIT3
+#define TWSI_CONTROL_STOP_BIT BIT4
+#define TWSI_CONTROL_START_BIT BIT5
+#define TWSI_CONTROL_ENA BIT6
+#define TWSI_CONTROL_INT_ENA BIT7
+
+
+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c)
+#define TWSI_BAUD_RATE_N_OFFS 0
+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS)
+#define TWSI_BAUD_RATE_M_OFFS 3
+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS)
+
+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c)
+
+/* defines */
+#define TWSI_TIMEOUT_VALUE 0x500
+
+/* TWSI status codes */
+#define TWSI_BUS_ERROR 0x00
+#define TWSI_START_CON_TRA 0x08
+#define TWSI_REPEATED_START_CON_TRA 0x10
+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18
+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20
+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28
+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30
+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38
+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40
+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48
+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50
+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58
+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60
+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68
+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70
+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78
+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80
+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88
+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90
+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98
+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0
+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8
+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0
+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8
+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0
+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8
+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0
+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8
+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0
+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8
+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __INCmvTwsiSpech */