diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-10-05 10:12:53 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-10-05 10:12:53 +0000 |
| commit | 5c105d9f3fd086aff195d3849dcf847d6b0bd927 (patch) | |
| tree | 1229a11f725bfa58aa7c57a76898553bb5f6654a /target/linux/coldfire | |
| download | openwrt-5c105d9f3fd086aff195d3849dcf847d6b0bd927.tar.gz openwrt-5c105d9f3fd086aff195d3849dcf847d6b0bd927.zip | |
branch Attitude Adjustment
git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@33625 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/coldfire')
59 files changed, 91653 insertions, 0 deletions
diff --git a/target/linux/coldfire/Makefile b/target/linux/coldfire/Makefile new file mode 100644 index 000000000..22e683fd0 --- /dev/null +++ b/target/linux/coldfire/Makefile @@ -0,0 +1,23 @@ +# +# Copyright (C) 2009-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=m68k +BOARD:=coldfire +BOARDNAME:=Freescale Coldfire v4e +FEATURES:=squashfs broken +MAINTAINER:=Imre Kaloz <kaloz@openwrt.org> + +LINUX_VERSION:=2.6.38.8 + +include $(INCLUDE_DIR)/target.mk + +define Target/Description + Build firmware images for ColdFire v4e boards +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/coldfire/config-default b/target/linux/coldfire/config-default new file mode 100644 index 000000000..efdf78090 --- /dev/null +++ b/target/linux/coldfire/config-default @@ -0,0 +1,116 @@ +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_START=0xff800000 +# CONFIG_MTD_PHYSMAP_COMPAT=y +# CONFIG_MTD_PHYSMAP_LEN=0x400000 +# CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_DMADEVICES=y +CONFIG_CFDMA=y +CONFIG_FEC_548x_SHARED_PHY=y +CONFIG_FPU=y +# CONFIG_M5474LITE is not set +CONFIG_M5484LITE=y +# CONFIG_M5441X is not set +# CONFIG_VDSO is not set +CONFIG_BROADCOM5222_PHY=y +# CONFIG_8139TOO is not set +CONFIG_ADVANCED=y +# CONFIG_AMIGA is not set +# CONFIG_APOLLO is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_ARCH_SUPPORTS_AOUT=y +# CONFIG_ATARI is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BITREVERSE=y +# CONFIG_BOOTPARAM is not set +CONFIG_BOUNCE=y +CONFIG_CFV4E=y +CONFIG_CLASSIC_RCU=y +# CONFIG_COLDFIRE_EDMA is not set +# CONFIG_COLDFIRE_WATCHDOG is not set +CONFIG_COLDFIRE=y +CONFIG_FEC_548x_AUTO_NEGOTIATION=y +CONFIG_FEC_548x_ENABLE_FEC2=y +CONFIG_FEC_548x=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_IOMAP=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GEN_RTC is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_IDE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HP300 is not set +CONFIG_HW_RANDOM=y +# CONFIG_IDE is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LEDS_ALIX is not set +# CONFIG_M5445X is not set +# CONFIG_M5475AFE is not set +# CONFIG_M5475BFE is not set +# CONFIG_M5475CFE is not set +# CONFIG_M5475DFE is not set +# CONFIG_M5475EFE is not set +# CONFIG_M5475FFE is not set +CONFIG_M547X_8X=y +# CONFIG_M547X is not set +# CONFIG_M5485AFE is not set +# CONFIG_M5485BFE is not set +# CONFIG_M5485CFE is not set +# CONFIG_M5485DFE is not set +# CONFIG_M5485EFE is not set +# CONFIG_M5485FFE is not set +CONFIG_M548X=y +# CONFIG_M68020 is not set +# CONFIG_M68030 is not set +# CONFIG_M68040 is not set +# CONFIG_M68060 is not set +# CONFIG_M68KFPU_EMU is not set +CONFIG_M68K=y +# CONFIG_MAC is not set +CONFIG_MCD_DMA=y +CONFIG_MCFCLK=200000000 +CONFIG_MCF_USER_HALT=y +# CONFIG_MEMSTICK is not set +CONFIG_MMU_CFV4E=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_NATIONAL8364x_PHY is not set +# CONFIG_NATIONAL8384x_PHY is not set +# CONFIG_NE2K_PCI is not set +CONFIG_NEED_MULTIPLE_NODES=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NO_DMA is not set +# CONFIG_NO_IOPORT is not set +CONFIG_NOR_FLASH_BASE=0xE0000000 +CONFIG_PCI=y +CONFIG_PCI_LEGACY=y +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PROC_HARDWARE is not set +# CONFIG_Q40 is not set +# CONFIG_R6040 is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_RMW_INSNS is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SDRAM_BASE=0x00000000 +CONFIG_SDRAM_SIZE=0x04000000 +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_COLDFIRE_IRDA is not set +CONFIG_SERIAL_COLDFIRE=y +# CONFIG_SERIAL_CONSOLE is not set +CONFIG_SERIAL_MCF=y +# CONFIG_SERIAL_COLDFIRE_EDMA is not set +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +CONFIG_SINGLE_MEMORY_CHUNK=y +CONFIG_SLABINFO=y +# CONFIG_SUN3 is not set +# CONFIG_SUN3X is not set +CONFIG_TIME_LOW_RES=y +CONFIG_UID16=y +# CONFIG_VGASTATE is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VME is not set diff --git a/target/linux/coldfire/image/Makefile b/target/linux/coldfire/image/Makefile new file mode 100644 index 000000000..94e28b2cb --- /dev/null +++ b/target/linux/coldfire/image/Makefile @@ -0,0 +1,34 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +JFFS2_BLOCKSIZE=128k + +define Image/Prepare +endef + +define Image/BuildKernel + $(TARGET_CROSS)objcopy -O binary -R .bss -R .note -R .comment \ + -R .note.gnu.build-id -S $(LINUX_DIR)/vmlinux $(KDIR)/vmlinux.bin + mkimage -A m68k -O linux -T kernel -a 0x00020000 -e 0x00020000 \ + -C none -n 'M68K OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR)/vmlinux.bin $(BIN_DIR)/$(IMG_PREFIX)-uImage +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) +endef + +define Image/Build/jffs2-128k +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/coldfire/patches/001-Coldfire-architecture-support-in-Linux-2.6.38.patch b/target/linux/coldfire/patches/001-Coldfire-architecture-support-in-Linux-2.6.38.patch new file mode 100644 index 000000000..6b889914a --- /dev/null +++ b/target/linux/coldfire/patches/001-Coldfire-architecture-support-in-Linux-2.6.38.patch @@ -0,0 +1,11199 @@ +From c462e1a613c8f84bb503189b0796d036dd1e5376 Mon Sep 17 00:00:00 2001 +From: Jason Jin <jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 09:59:35 +0800 +Subject: [PATCH 01/52] Coldfire architecture support in Linux 2.6.38 + +Coldfire architecture support in Linux 2.6.38. + +Signed-off-by: Alison Wang <b18965@freescale.com> +Signed-off-by: Jason Jin <jason.jin@freescale.com> +--- + arch/m68k/Kconfig | 279 +++++++++- + arch/m68k/Kconfig.debug | 9 + + arch/m68k/Makefile | 48 ++- + arch/m68k/boot/Makefile | 68 +++ + arch/m68k/coldfire/Makefile | 10 + + arch/m68k/coldfire/common/Makefile | 7 + + arch/m68k/coldfire/common/cache.c | 45 ++ + arch/m68k/coldfire/common/clk.c | 51 ++ + arch/m68k/coldfire/common/entry.S | 745 ++++++++++++++++++++++++ + arch/m68k/coldfire/common/head.S | 466 +++++++++++++++ + arch/m68k/coldfire/common/ints.c | 544 ++++++++++++++++++ + arch/m68k/coldfire/common/muldi3.S | 73 +++ + arch/m68k/coldfire/common/signal.c | 991 ++++++++++++++++++++++++++++++++ + arch/m68k/coldfire/common/traps.c | 457 +++++++++++++++ + arch/m68k/include/asm/atomic.h | 33 +- + arch/m68k/include/asm/bitops_mm.h | 12 +- + arch/m68k/include/asm/bootinfo.h | 42 ++ + arch/m68k/include/asm/cacheflush_mm.h | 14 +- + arch/m68k/include/asm/cf-sram.h | 21 + + arch/m68k/include/asm/cf_bitops.h | 443 ++++++++++++++ + arch/m68k/include/asm/cf_cacheflush.h | 20 + + arch/m68k/include/asm/cf_entry.h | 153 +++++ + arch/m68k/include/asm/cf_io.h | 185 ++++++ + arch/m68k/include/asm/cf_pgalloc.h | 112 ++++ + arch/m68k/include/asm/cf_pgtable.h | 364 ++++++++++++ + arch/m68k/include/asm/cf_raw_io.h | 188 ++++++ + arch/m68k/include/asm/cf_tlbflush.h | 66 +++ + arch/m68k/include/asm/cf_uaccess.h | 262 +++++++++ + arch/m68k/include/asm/cf_virtconvert.h | 63 ++ + arch/m68k/include/asm/cfcache.h | 146 +++++ + arch/m68k/include/asm/cfmmu.h | 112 ++++ + arch/m68k/include/asm/coldfire.h | 70 ++- + arch/m68k/include/asm/delay_mm.h | 42 ++- + arch/m68k/include/asm/div64.h | 11 +- + arch/m68k/include/asm/dma.h | 109 ++++- + arch/m68k/include/asm/elf.h | 70 +++- + arch/m68k/include/asm/io_mm.h | 234 ++++++-- + arch/m68k/include/asm/irq.h | 14 +- + arch/m68k/include/asm/machdep.h | 15 +- + arch/m68k/include/asm/mcfdspi.h | 59 ++ + arch/m68k/include/asm/mcfsim.h | 121 ++++ + arch/m68k/include/asm/mcfuart.h | 64 ++ + arch/m68k/include/asm/mmu.h | 15 +- + arch/m68k/include/asm/mmu_context.h | 184 ++++++- + arch/m68k/include/asm/page.h | 10 +- + arch/m68k/include/asm/page_mm.h | 61 ++ + arch/m68k/include/asm/page_offset.h | 21 +- + arch/m68k/include/asm/pgalloc.h | 12 +- + arch/m68k/include/asm/pgtable_mm.h | 36 ++- + arch/m68k/include/asm/processor.h | 45 ++- + arch/m68k/include/asm/ptrace.h | 48 ++- + arch/m68k/include/asm/raw_io.h | 15 +- + arch/m68k/include/asm/segment.h | 17 + + arch/m68k/include/asm/setup.h | 36 ++ + arch/m68k/include/asm/signal.h | 10 +- + arch/m68k/include/asm/string.h | 20 +- + arch/m68k/include/asm/swab.h | 15 +- + arch/m68k/include/asm/system_mm.h | 23 +- + arch/m68k/include/asm/tlbflush.h | 24 +- + arch/m68k/include/asm/uaccess_mm.h | 80 ++-- + arch/m68k/include/asm/unistd.h | 11 +- + arch/m68k/include/asm/virtconvert.h | 11 + + arch/m68k/kernel/Makefile | 23 +- + arch/m68k/kernel/asm-offsets.c | 28 + + arch/m68k/kernel/dma.c | 47 ++- + arch/m68k/kernel/process.c | 66 +++ + arch/m68k/kernel/setup.c | 72 ++- + arch/m68k/kernel/sys_m68k.c | 80 +++ + arch/m68k/kernel/time.c | 142 +++++- + arch/m68k/kernel/vmlinux-cf.lds | 142 +++++ + arch/m68k/kernel/vmlinux.lds.S | 12 +- + arch/m68k/lib/checksum.c | 129 +++++ + arch/m68k/lib/muldi3.c | 13 + + arch/m68k/lib/string.c | 68 +++ + arch/m68k/lib/uaccess.c | 247 ++++++++ + arch/m68k/mm/Makefile | 2 + + arch/m68k/mm/cache.c | 19 + + arch/m68k/mm/cf-mmu.c | 311 ++++++++++ + arch/m68k/mm/cf-sram.c | 80 +++ + arch/m68k/mm/hwtest.c | 10 + + arch/m68k/mm/init.c | 15 +- + arch/m68k/mm/kmap.c | 82 +++- + arch/m68k/mm/memory.c | 17 + + fs/namespace.c | 8 + + include/linux/fsl_devices.h | 14 +- + 85 files changed, 8962 insertions(+), 197 deletions(-) + create mode 100644 arch/m68k/boot/Makefile + create mode 100644 arch/m68k/coldfire/Makefile + create mode 100644 arch/m68k/coldfire/common/Makefile + create mode 100644 arch/m68k/coldfire/common/cache.c + create mode 100644 arch/m68k/coldfire/common/clk.c + create mode 100644 arch/m68k/coldfire/common/entry.S + create mode 100644 arch/m68k/coldfire/common/head.S + create mode 100644 arch/m68k/coldfire/common/ints.c + create mode 100644 arch/m68k/coldfire/common/muldi3.S + create mode 100644 arch/m68k/coldfire/common/signal.c + create mode 100644 arch/m68k/coldfire/common/traps.c + create mode 100644 arch/m68k/include/asm/cf-sram.h + create mode 100644 arch/m68k/include/asm/cf_bitops.h + create mode 100644 arch/m68k/include/asm/cf_cacheflush.h + create mode 100644 arch/m68k/include/asm/cf_entry.h + create mode 100644 arch/m68k/include/asm/cf_io.h + create mode 100644 arch/m68k/include/asm/cf_pgalloc.h + create mode 100644 arch/m68k/include/asm/cf_pgtable.h + create mode 100644 arch/m68k/include/asm/cf_raw_io.h + create mode 100644 arch/m68k/include/asm/cf_tlbflush.h + create mode 100644 arch/m68k/include/asm/cf_uaccess.h + create mode 100644 arch/m68k/include/asm/cf_virtconvert.h + create mode 100644 arch/m68k/include/asm/cfcache.h + create mode 100644 arch/m68k/include/asm/cfmmu.h + create mode 100644 arch/m68k/include/asm/mcfdspi.h + create mode 100644 arch/m68k/kernel/vmlinux-cf.lds + create mode 100644 arch/m68k/mm/cf-mmu.c + create mode 100644 arch/m68k/mm/cf-sram.c + +--- a/arch/m68k/Kconfig ++++ b/arch/m68k/Kconfig +@@ -9,6 +9,14 @@ config MMU + bool + default y + ++config GENERIC_TIME ++ bool "Enable generic timer" ++ default n ++ ++config GENERIC_CLOCKEVENTS ++ bool "Enable generic clockevents" ++ default n ++ + config RWSEM_GENERIC_SPINLOCK + bool + default y +@@ -34,7 +42,7 @@ config GENERIC_CALIBRATE_DELAY + + config TIME_LOW_RES + bool +- default y ++ default n + + config GENERIC_IOMAP + bool +@@ -46,7 +54,7 @@ config ARCH_MAY_HAVE_PC_FDC + default y + + config NO_IOPORT +- def_bool y ++ def_bool !(M5445X || M547X_8X || M5441X) + + config NO_DMA + def_bool SUN3 +@@ -105,6 +113,35 @@ config PCMCIA + To compile this driver as modules, choose M here: the + modules will be called pcmcia_core and ds. + ++config COLDFIRE ++ bool "ColdFire V4e support" ++ default y ++ select CFV4E ++ help ++ Say Y if you want to build a kernel to run on one of the ColdFire ++ V4e boards. ++ ++config CFV4E ++ bool ++ depends on COLDFIRE ++ select MMU_CFV4E if MMU ++ default y ++ ++config FPU ++ bool "ColdFire V4e FPU support" ++ default n ++ help ++ This enables support for CFV4E FPU feature. ++ ++config MCD_DMA ++ bool "ColdFire MCD DMA support" ++ depends on M547X_8X ++ default y ++ help ++ This enables support for the ColdFire 547x/548x family ++ multichannel DMA support. Many drivers need it. ++ If you want it, say Y ++ + config AMIGA + bool "Amiga support" + select MMU_MOTOROLA if MMU +@@ -122,6 +159,16 @@ config ATARI + this kernel on an Atari, say Y here and browse the material + available in <file:Documentation/m68k>; otherwise say N. + ++config PCI ++ bool "PCI bus support" ++ depends on M54455 || M547X_8X ++ default n ++ help ++ Find out whether you have a PCI motherboard. PCI is the name of a ++ bus system, i.e. the way the CPU talks to the other stuff inside ++ your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or ++ VESA. If you have PCI, say Y, otherwise N. ++ + config MAC + bool "Macintosh support" + select MMU_MOTOROLA if MMU +@@ -276,6 +323,147 @@ config M68060 + If you anticipate running this kernel on a computer with a MC68060 + processor, say Y. Otherwise, say N. + ++config M5445X ++ bool "MCF5445x support" ++ depends on COLDFIRE ++ select GENERIC_TIME ++ select USB_EHCI_FSL ++ select HAVE_FSL_USB_DR ++ help ++ This option will add support for the MCF544x processor with mmu. ++ ++config M54451 ++ bool ++ depends on M5445X ++ default n ++ ++config M54455 ++ bool ++ depends on M5445X ++ default n ++ ++choice ++ prompt "Model" ++ depends on M5445X ++ default M54451EVB ++ config M54451EVB ++ bool "M54451EVB" ++ select M54451 ++ config M54455EVB ++ bool "M54455EVB" ++ select M54455 ++endchoice ++ ++config HAVE_FSL_USB_DR ++ bool ++ default n ++ ++config M547X_8X ++ bool "MCF547x/MCF548x support" ++ depends on COLDFIRE ++ help ++ This option will add support for the MCF547x/MCF548x processor with mmu. ++ ++config M547X ++ bool ++ depends on M547X_8X ++ default n ++ ++config M548X ++ bool ++ depends on M547X_8X ++ default n ++ ++choice ++ prompt "Model" ++ depends on M547X_8X ++ default M5485CFE ++ ++config M5474LITE ++ bool "MCF5474LITE" ++ select M547X ++config M5475AFE ++ bool "MCF5475AFE" ++ select M547X ++config M5475BFE ++ bool "MCF5475BFE" ++ select M547X ++config M5475CFE ++ bool "MCF5475CFE" ++ select M547X ++config M5475DFE ++ bool "MCF5475DFE" ++ select M547X ++config M5475EFE ++ bool "MCF5475EFE" ++ select M547X ++config M5475FFE ++ bool "MCF5475FFE" ++ select M547X ++config M5484LITE ++ bool "MCF5484LITE" ++ select M548X ++config M5485AFE ++ bool "MCF5485AFE" ++ select M548X ++config M5485BFE ++ bool "MCF5485BFE" ++ select M548X ++config M5485CFE ++ bool "MCF5485CFE" ++ select M548X ++config M5485DFE ++ bool "MCF5485DFE" ++ select M548X ++config M5485EFE ++ bool "MCF5485EFE" ++ select M548X ++config M5485FFE ++ bool "MCF5485FFE" ++ select M548X ++ ++endchoice ++ ++config M5441X ++ bool "MCF5441x support" ++ depends on COLDFIRE ++ select GENERIC_TIME ++ select USB_EHCI_FSL ++ select HAVE_FSL_USB_DR ++ help ++ This option will add support for the MCF5441x processor with mmu. ++ ++config M54418 ++ bool ++ depends on M5441X ++ default n ++choice ++ prompt "Model" ++ depends on M5441X ++ default M54418EVB ++ config M54418EVB ++ bool "M54418EVB" ++ select M54418 ++endchoice ++ ++config MCFCLK ++ int ++ default 240000000 if M54451EVB ++ default 266666666 if M54455EVB ++ default 266000000 if M547X ++ default 200000000 if M548X ++ default 250000000 if M54418EVB && !USB_M5441X_PLLCLK ++ default 150000000 if M54418EVB && USB_M5441X_PLLCLK ++ help ++ Coldfire System clock. ++ ++config MCF_USER_HALT ++ bool "Coldfire User Halt Enable" ++ depends on M5445X || M547X_8X || M5441X ++ default n ++ help ++ Enables the HALT instruction in User Mode. ++ + config MMU_MOTOROLA + bool + +@@ -283,6 +471,81 @@ config MMU_SUN3 + bool + depends on MMU && !MMU_MOTOROLA + ++config MMU_CFV4E ++ bool ++ ++config SDRAM_BASE ++ hex ++ depends on COLDFIRE ++ default 0x40000000 if M5445X ++ default 0x00000000 if M547X_8X ++ default 0x40000000 if M5441X ++ ++config SDRAM_SIZE ++ hex ++ depends on COLDFIRE ++ default 0x08000000 if M54451EVB ++ default 0x10000000 if M54455EVB ++ default 0x04000000 if M547X_8X ++ default 0x08000000 if M54418EVB ++ ++config NOR_FLASH_BASE ++ hex "NOR Flash Base Address" ++ depends on COLDFIRE ++ default 0x00000000 if M54451EVB ++ default 0x00000000 if M54455EVB ++ default 0xE0000000 if M5475CFE ++ default 0xE0000000 if M5485CFE ++ default 0xFF800000 if M5484LITE ++ default 0xFF800000 if M5474LITE ++ default 0x00000000 if M54418EVB ++ ++config DMA_BASE ++ hex ++ depends on COLDFIRE ++ default 0xef000000 if M5445X ++ default 0xef000000 if M547X_8X ++ default 0xdf000000 if M5441X ++ ++config DMA_SIZE ++ hex ++ depends on COLDFIRE ++ default 0x1000000 if M5445X ++ default 0x800000 if M547X_8X ++ default 0x1000000 if M5441X ++ ++config SRAM ++ bool "SRAM allocation APIs support on mcfv4 platform" ++ depends on COLDFIRE && (M5445X || M5441X) ++ default y ++ select GENERIC_ALLOCATOR ++ ++config SRAM_BASE ++ hex ++ depends on COLDFIRE && SRAM ++ default 0x8ff00000 if M5445X ++ default 0x8ff00000 if M5441X ++ ++config SRAM_SIZE ++ hex ++ depends on COLDFIRE && SRAM ++ default 0x8000 if M5445X ++ default 0x10000 if M5441X ++ ++config SRAM_ALLOC_GRANULARITY ++ hex ++ depends on SRAM ++ default 0x200 if (M5445X || M5441X) ++ ++config VDSO ++ bool "Support VDSO page" ++ depends on MMU ++ default n ++ help ++ This will enable support for the kernel mapping a vDSO page ++ in process space, and subsequently handing down the entry point ++ to the libc through the ELF auxiliary vector. ++ + config M68KFPU_EMU + bool "Math emulation support (EXPERIMENTAL)" + depends on EXPERIMENTAL +@@ -449,6 +712,14 @@ config ZONE_DMA + source "drivers/pci/Kconfig" + + source "drivers/zorro/Kconfig" ++endmenu ++ ++menu "Power management options" ++ ++config PM ++ bool "Power Management support" ++ help ++ Support processor power management modes + + endmenu + +@@ -583,7 +854,7 @@ config DN_SERIAL + + config SERIAL_CONSOLE + bool "Support for serial port console" +- depends on (AMIGA || ATARI || SUN3 || SUN3X || VME || APOLLO) && (ATARI_MFPSER=y || ATARI_MIDI=y || AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y || SERIAL=y || MVME147_SCC || SERIAL167 || MVME162_SCC || BVME6000_SCC || DN_SERIAL) ++ depends on (AMIGA || ATARI || SUN3 || SUN3X || VME || APOLLO || COLDFIRE) && (ATARI_MFPSER=y || ATARI_MIDI=y || AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y || SERIAL=y || MVME147_SCC || SERIAL167 || MVME162_SCC || BVME6000_SCC || DN_SERIAL || SERIAL_COLDFIRE) + ---help--- + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all +@@ -606,6 +877,8 @@ config SERIAL_CONSOLE + + endmenu + ++source "kernel/time/Kconfig" ++ + source "fs/Kconfig" + + source "arch/m68k/Kconfig.debug" +--- a/arch/m68k/Kconfig.debug ++++ b/arch/m68k/Kconfig.debug +@@ -2,4 +2,13 @@ menu "Kernel hacking" + + source "lib/Kconfig.debug" + ++config BOOTPARAM ++ bool 'Compiled-in Kernel Boot Parameter' ++ depends on COLDFIRE ++ ++config BOOTPARAM_STRING ++ string 'Kernel Boot Parameter' ++ default 'console=ttyS0,115200' ++ depends on BOOTPARAM ++ + endmenu +--- a/arch/m68k/Makefile ++++ b/arch/m68k/Makefile +@@ -1,6 +1,8 @@ + # + # m68k/Makefile + # ++# Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++# + # This file is included by the global makefile so that you can add your own + # architecture-specific flags and dependencies. Remember to do have actions + # for "archclean" and "archdep" for cleaning up and making dependencies for +@@ -10,13 +12,13 @@ + # License. See the file "COPYING" in the main directory of this archive + # for more details. + # +-# Copyright (C) 1994 by Hamish Macdonald +-# + +-KBUILD_DEFCONFIG := multi_defconfig ++KBUILD_DEFCONFIG := amiga_defconfig#multi_defconfig + + # override top level makefile ++ifndef CONFIG_COLDFIRE + AS += -m68020 ++endif + LDFLAGS := -m m68kelf + KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds + ifneq ($(SUBARCH),$(ARCH)) +@@ -30,12 +32,18 @@ ifdef CONFIG_SUN3 + LDFLAGS_vmlinux = -N + endif + ++ifdef CONFIG_COLDFIRE ++OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment -S ++# LDFLAGS_vmlinux = --verbose ++endif ++ + CHECKFLAGS += -D__mc68000__ + + # without -fno-strength-reduce the 53c7xx.c driver fails ;-( + KBUILD_CFLAGS += -pipe -fno-strength-reduce -ffixed-a2 + + # enable processor switch if compiled only for a single cpu ++ifndef CONFIG_COLDFIRE + ifndef CONFIG_M68020 + ifndef CONFIG_M68030 + +@@ -49,6 +57,22 @@ endif + + endif + endif ++endif ++ ++ifdef CONFIG_M5445X ++KBUILD_CFLAGS += -march=isac -mcpu=54455 -msoft-float -g ++KBUILD_AFLAGS += -march=isac -mcpu=54455 -msoft-float ++endif ++ ++ifdef CONFIG_M547X_8X ++KBUILD_CFLAGS += -mcfv4e -g ++KBUILD_AFLAGS += -mcfv4e ++endif ++ ++ifdef CONFIG_M5441X ++KBUILD_CFLAGS += -march=isac -mcpu=54418 -msoft-float -g ++KBUILD_AFLAGS += -march=isac -mcpu=54418 -msoft-float ++endif + + ifdef CONFIG_KGDB + # If configured for kgdb support, include debugging infos and keep the +@@ -57,8 +81,12 @@ KBUILD_CFLAGS := $(subst -fomit-frame-po + endif + + ifndef CONFIG_SUN3 ++ifndef CONFIG_COLDFIRE + head-y := arch/m68k/kernel/head.o + else ++head-y := arch/m68k/coldfire/common/head.o ++endif ++else + head-y := arch/m68k/kernel/sun3-head.o + endif + +@@ -79,7 +107,20 @@ core-$(CONFIG_SUN3) += arch/m68k/sun3/ + core-$(CONFIG_M68040) += arch/m68k/fpsp040/ + core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ + core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ ++core-$(CONFIG_COLDFIRE) += arch/m68k/coldfire/ ++ ++ifdef CONFIG_COLDFIRE ++boot := arch/m68k/boot ++ ++all: uImage + ++zImage zImage.srec uImage uImage.srec vmlinux.srec: vmlinux ++ $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ ++ ++archclean: ++ $(Q)$(MAKE) $(clean)=$(boot) ++ ++else + all: zImage + + lilo: vmlinux +@@ -117,6 +158,7 @@ endif + + archclean: + rm -f vmlinux.gz vmlinux.bz2 ++endif + + install: + sh $(srctree)/arch/m68k/install.sh $(KERNELRELEASE) vmlinux.gz System.map "$(INSTALL_PATH)" +--- /dev/null ++++ b/arch/m68k/boot/Makefile +@@ -0,0 +1,68 @@ ++# ++# arch/m68k/boot/Makefile ++# ++# Based on arch/sh/boot/Makefile by Stuart Menefy ++# ++# Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++# by Kurt Mahan <kmahan@freescale.com> ++# ++# This file is subject to the terms and conditions of the GNU General Public ++# License. See the file "COPYING" in the main directory of this archive ++# for more details. ++# ++ ++MKIMAGE := $(srctree)/scripts/mkuboot.sh ++ ++# ++# Assign safe dummy values if these variables are not defined, ++# in order to suppress error message. ++# ++CONFIG_SDRAM_BASE ?= 0x40000000 ++CONFIG_IMG_START ?= 0x00020000 ++ ++export CONFIG_SDRAM_BASE CONFIG_IMG_START ++ ++targets := zImage zImage.srec vmlinux.srec uImage uImage.srec ++ ++$(obj)/zImage: $(obj)/vmlinux.bin FORCE ++ $(call if_changed,gzip) ++ @echo ' Image $@ is ready' ++ ++OBJCOPYFLAGS_zImage.srec := -I binary -O srec ++$(obj)/zImage.srec: $(obj)/zImage ++ $(call if_changed,objcopy) ++ ++KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \ ++ $$[$(CONFIG_SDRAM_BASE) + \ ++ $(CONFIG_IMG_START)]') ++ ++KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \ ++ $$[$(CONFIG_SDRAM_BASE) + \ ++ $(CONFIG_IMG_START)]') ++ ++quiet_cmd_uimage = UIMAGE $@ ++ cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A m68k -O linux -T kernel \ ++ -C gzip -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \ ++ -n 'Linux-$(KERNELRELEASE)' -d $< $@ ++ ++$(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE ++ $(call if_changed,uimage) ++ @echo ' Image $@ is ready' ++ ++$(obj)/vmlinux.bin: vmlinux FORCE ++ $(call if_changed,objcopy) ++ ++$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE ++ $(call if_changed,gzip) ++ ++OBJCOPYFLAGS_vmlinux.srec := -I binary -O srec ++$(obj)/vmlinux.srec: $(obj)/vmlinux.bin ++ $(call if_changed,objcopy) ++ ++OBJCOPYFLAGS_uImage.srec := -I binary -O srec ++$(obj)/uImage.srec: $(obj)/uImage ++ $(call if_changed,objcopy) ++ ++clean-files += uImage uImage.srec \ ++ zImage zImage.srec \ ++ vmlinux.srec vmlinux.bin vmlinux.bin.gz +--- /dev/null ++++ b/arch/m68k/coldfire/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for Linux arch/m68k/coldfire source directory ++# ++ ++obj-y += common/ ++obj-$(CONFIG_VDSO) += vdso/ ++ ++obj-$(CONFIG_M5445X) += m5445x/ ++obj-$(CONFIG_M547X_8X) += m547x/ ++obj-$(CONFIG_M5441X) += m5441x/ +--- /dev/null ++++ b/arch/m68k/coldfire/common/Makefile +@@ -0,0 +1,7 @@ ++# ++# Makefile for Linux arch/m68k/coldfire/common source directory ++# ++ ++obj-y:= entry.o cache.o signal.o muldi3.o traps.o ints.o clk.o ++extra-y:= head.o ++ +--- /dev/null ++++ b/arch/m68k/coldfire/common/cache.c +@@ -0,0 +1,45 @@ ++/* ++ * linux/arch/m68k/coldfire/cache.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Kurt Mahan kmahan@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/interrupt.h> ++#include <asm/cfcache.h> ++#include <asm/coldfire.h> ++#include <asm/system.h> ++ ++/* Cache Control Reg shadow reg */ ++unsigned long shadow_cacr; ++ ++/** ++ * cacr_set - Set the Cache Control Register ++ * @x Value to set ++ */ ++void cacr_set(unsigned long x) ++{ ++ shadow_cacr = x; ++ ++ __asm__ __volatile__ ("movec %0, %%cacr" ++ : /* no outputs */ ++ : "r" (shadow_cacr)); ++} ++ ++/** ++ * cacr_get - Get the current value of the Cache Control Register ++ * ++ * @return CACR value ++ */ ++unsigned long cacr_get(void) ++{ ++ return shadow_cacr; ++} +--- /dev/null ++++ b/arch/m68k/coldfire/common/clk.c +@@ -0,0 +1,51 @@ ++/***************************************************************************/ ++ ++/* ++ * clk.c -- general ColdFire CPU kernel clk handling ++ * ++ * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com) ++ * Copyright (C) 2011 Freescale Semiconductore, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++*/ ++ ++/***************************************************************************/ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/clk.h> ++#include <asm/coldfire.h> ++ ++/***************************************************************************/ ++ ++struct clk *clk_get(struct device *dev, const char *id) ++{ ++ return NULL; ++} ++EXPORT_SYMBOL(clk_get); ++ ++int clk_enable(struct clk *clk) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(clk_enable); ++ ++void clk_disable(struct clk *clk) ++{ ++} ++EXPORT_SYMBOL(clk_disable); ++ ++void clk_put(struct clk *clk) ++{ ++} ++EXPORT_SYMBOL(clk_put); ++ ++unsigned long clk_get_rate(struct clk *clk) ++{ ++ return MCF_CLK; ++} ++EXPORT_SYMBOL(clk_get_rate); ++/***************************************************************************/ +--- /dev/null ++++ b/arch/m68k/coldfire/common/entry.S +@@ -0,0 +1,745 @@ ++/* ++ * arch/m68k/coldfire/entry.S ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Kurt Mahan kmahan@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * Based on: ++ * ++ * arch/m68knommu/platform/5307/entry.S & ++ * arch/m68k/kernel/entry.S ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file README.legal in the main directory of this archive ++ * for more details. ++ */ ++ ++#include <linux/sys.h> ++#include <linux/linkage.h> ++#include <asm/cf_entry.h> ++#include <asm/errno.h> ++#include <asm/setup.h> ++#include <asm/segment.h> ++#include <asm/traps.h> ++#include <asm/unistd.h> ++#include <asm/asm-offsets.h> ++ ++/* ++ * TASK_INFO: ++ * ++ * - TINFO_PREEMPT (struct thread_info / preempt_count) ++ * Used to keep track of preemptability ++ * - TINFO_FLAGS (struct thread_info / flags - include/asm-m68k/thread_info.h) ++ * Various bit flags that are checked for scheduling/tracing ++ * Bits 0-7 are checked every exception exit ++ * 8-15 are checked every syscall exit ++ * ++ * TIF_SIGPENDING 6 ++ * TIF_NEED_RESCHED 7 ++ * TIF_DELAYED_TRACE 14 ++ * TIF_SYSCALL_TRACE 15 ++ * TIF_MEMDIE 16 (never checked here) ++ */ ++ ++.bss ++ ++sw_ksp: ++.long 0 ++ ++sw_usp: ++.long 0 ++ ++.text ++ ++.globl system_call ++.globl buserr ++.globl trap ++.globl resume ++.globl ret_from_exception ++.globl ret_from_signal ++.globl sys_call_table ++.globl ret_from_interrupt ++.globl inthandler ++ ++ENTRY(buserr) ++#ifdef CONFIG_COLDFIRE_FOO ++ movew #0x2700,%sr /* lock interrupts */ ++#endif ++ SAVE_ALL_INT ++#ifdef CONFIG_COLDFIRE_FOO ++ movew PT_0FF_SR(%sp),%d3 /* get original %sr */ ++ oril #0x2000,%d3 /* set supervisor mode in it */ ++ movew %d3,%sr /* recover irq state */ ++#endif ++ GET_CURRENT(%d0) ++ movel %sp,%sp@- /* stack frame pointer argument */ ++ jsr buserr_c ++ addql #4,%sp ++ jra .Lret_from_exception ++ ++ENTRY(trap) ++ SAVE_ALL_INT ++ GET_CURRENT(%d0) ++ movel %sp,%sp@- /* stack frame pointer argument */ ++ jsr trap_c ++ addql #4,%sp ++ jra .Lret_from_exception ++ ++ /* After a fork we jump here directly from resume, ++ %d1 contains the previous task schedule_tail */ ++ENTRY(ret_from_fork) ++ movel %d1,%sp@- ++ jsr schedule_tail ++ addql #4,%sp ++ jra .Lret_from_exception ++ ++do_trace_entry: ++ movel #-ENOSYS,%d1 /* needed for strace */ ++ movel %d1,%sp@(PT_OFF_D0) ++ subql #4,%sp ++ SAVE_SWITCH_STACK ++ jbsr syscall_trace ++ RESTORE_SWITCH_STACK ++ addql #4,%sp ++ movel %sp@(PT_OFF_ORIG_D0),%d0 ++ cmpl #NR_syscalls,%d0 ++ jcs syscall ++badsys: ++ movel #-ENOSYS,%d1 ++ movel %d1,%sp@(PT_OFF_D0) ++ jra ret_from_exception ++ ++do_trace_exit: ++ subql #4,%sp ++ SAVE_SWITCH_STACK ++ jbsr syscall_trace ++ RESTORE_SWITCH_STACK ++ addql #4,%sp ++ jra .Lret_from_exception ++ ++ENTRY(ret_from_signal) ++ RESTORE_SWITCH_STACK ++ addql #4,%sp ++ jra .Lret_from_exception ++ ++ENTRY(system_call) ++ SAVE_ALL_SYS ++ ++ GET_CURRENT(%d1) ++ /* save top of frame */ ++ movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0) ++ ++ /* syscall trace */ ++ tstb %curptr@(TASK_INFO+TINFO_FLAGS+2) ++ jmi do_trace_entry /* SYSCALL_TRACE is set */ ++ cmpl #NR_syscalls,%d0 ++ jcc badsys ++syscall: ++ movel #sys_call_table,%a0 ++ asll #2,%d0 ++ addl %d0,%a0 ++ movel %a0@,%a0 ++ jsr %a0@ ++ movel %d0,%sp@(PT_OFF_D0) /* save the return value */ ++ret_from_syscall: ++ movew %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0 ++ jne syscall_exit_work /* flags set so process */ ++1: RESTORE_ALL ++ ++syscall_exit_work: ++ btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel */ ++ bnes 1b /* if so, skip resched, signals */ ++ ++ btstl #15,%d0 /* check if SYSCALL_TRACE */ ++ jne do_trace_exit ++ btstl #14,%d0 /* check if DELAYED_TRACE */ ++ jne do_delayed_trace ++ btstl #6,%d0 /* check if SIGPENDING */ ++ jne do_signal_return ++ pea resume_userspace ++ jra schedule ++ ++ENTRY(ret_from_exception) ++.Lret_from_exception: ++ btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel */ ++ bnes 1f /* if so, skip resched, signals */ ++ movel %d0,%sp@- /* Only allow interrupts when we are */ ++ move %sr,%d0 /* last one on the kernel stack, */ ++ andl #ALLOWINT,%d0 /* otherwise stack overflow can occur */ ++ move %d0,%sr /* during heavy interrupt load. */ ++ movel %sp@+,%d0 ++ ++resume_userspace: ++ moveb %curptr@(TASK_INFO+TINFO_FLAGS+3),%d0 ++ jne exit_work /* SIGPENDING and/or NEED_RESCHED set */ ++1: RESTORE_ALL ++ ++exit_work: ++ /* save top of frame */ ++ movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0) ++ btstl #6,%d0 /* check for SIGPENDING in flags */ ++ jne do_signal_return ++ pea resume_userspace ++ jra schedule ++ ++do_signal_return: ++ subql #4,%sp /* dummy return address */ ++ SAVE_SWITCH_STACK ++ pea %sp@(SWITCH_STACK_SIZE) ++ clrl %sp@- ++ bsrl do_signal ++ addql #8,%sp ++ RESTORE_SWITCH_STACK ++ addql #4,%sp ++ jbra resume_userspace ++ ++do_delayed_trace: ++ bclr #7,%sp@(PT_OFF_SR) /* clear trace bit in SR */ ++ pea 1 /* send SIGTRAP */ ++ movel %curptr,%sp@- ++ pea LSIGTRAP ++ jbsr send_sig ++ addql #8,%sp ++ addql #4,%sp ++ jbra resume_userspace ++ ++/* ++ * This is the interrupt handler (for all hardware interrupt ++ * sources). It figures out the vector number and calls the appropriate ++ * interrupt service routine directly. ++ */ ++ENTRY(inthandler) ++ SAVE_ALL_INT ++ GET_CURRENT(%d0) ++ movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 ++ addil #0x10000,%d0 ++ movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT) ++ /* put exception # in d0 */ ++ movel %sp@(PT_VECTOR),%d0 ++ swap %d0 /* extract bits 25:18 */ ++ lsrl #2,%d0 ++ andl #0x0ff,%d0 ++ ++ movel %sp,%sp@- ++ movel %d0,%sp@- /* put vector # on stack */ ++auto_irqhandler_fixup = . + 2 ++ jbsr process_int /* process the IRQ */ ++ addql #8,%sp /* pop parameters off stack */ ++ ++ret_from_interrupt: ++ ++ movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 ++ subil #0x10000,%d0 ++ movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT) ++ jeq ret_from_last_interrupt ++2: RESTORE_ALL ++ ++ ALIGN ++ret_from_last_interrupt: ++ moveb %sp@(PT_OFF_SR),%d0 ++ andl #(~ALLOWINT>>8)&0xff,%d0 ++ jne 2b ++ ++ /* check if we need to do software interrupts */ ++ tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING ++ jeq .Lret_from_exception ++ pea ret_from_exception ++ jra do_softirq ++ ++ENTRY(user_inthandler) ++ SAVE_ALL_INT ++ GET_CURRENT(%d0) ++ movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 ++ addil #0x10000,%d0 ++ movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT) ++ /* put exception # in d0 */ ++ movel %sp@(PT_VECTOR),%d0 ++user_irqvec_fixup = . + 2 ++ swap %d0 /* extract bits 25:18 */ ++ lsrl #2,%d0 ++ andl #0x0ff,%d0 ++ ++ movel %sp,%sp@- ++ movel %d0,%sp@- /* put vector # on stack */ ++user_irqhandler_fixup = . + 2 ++ jbsr process_int /* process the IRQ */ ++ addql #8,%sp /* pop parameters off stack */ ++ ++ movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 ++ subil #0x10000,%d0 ++ movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT) ++ jeq ret_from_last_interrupt ++ RESTORE_ALL ++ ++/* Handler for uninitialized and spurious interrupts */ ++ ++ENTRY(bad_inthandler) ++ SAVE_ALL_INT ++ GET_CURRENT(%d0) ++ movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 ++ addil #0x10000,%d0 ++ movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT) ++ ++ movel %sp,%sp@- ++ jsr handle_badint ++ addql #4,%sp ++ ++ movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 ++ subil #0x10000,%d0 ++ movel %d0,%curptr@(TASK_INFO+TINFO_PREEMPT) ++ jeq ret_from_last_interrupt ++ RESTORE_ALL ++ ++ENTRY(sys_fork) ++ SAVE_SWITCH_STACK ++ pea %sp@(SWITCH_STACK_SIZE) ++ jbsr m68k_fork ++ addql #4,%sp ++ RESTORE_SWITCH_STACK ++ rts ++ ++ENTRY(sys_clone) ++ SAVE_SWITCH_STACK ++ pea %sp@(SWITCH_STACK_SIZE) ++ jbsr m68k_clone ++ addql #4,%sp ++ RESTORE_SWITCH_STACK ++ rts ++ ++ENTRY(sys_vfork) ++ SAVE_SWITCH_STACK ++ pea %sp@(SWITCH_STACK_SIZE) ++ jbsr m68k_vfork ++ addql #4,%sp ++ RESTORE_SWITCH_STACK ++ rts ++ ++ENTRY(sys_sigsuspend) ++ SAVE_SWITCH_STACK ++ pea %sp@(SWITCH_STACK_SIZE) ++ jbsr do_sigsuspend ++ addql #4,%sp ++ RESTORE_SWITCH_STACK ++ rts ++ ++ENTRY(sys_sigreturn) ++ SAVE_SWITCH_STACK ++ jbsr do_sigreturn ++ RESTORE_SWITCH_STACK ++ rts ++ ++ENTRY(sys_rt_sigreturn) ++ SAVE_SWITCH_STACK ++ jbsr do_rt_sigreturn ++ RESTORE_SWITCH_STACK ++ rts ++ ++resume: ++ /* ++ * Beware - when entering resume, prev (the current task) is ++ * in a0, next (the new task) is in a1,so don't change these ++ * registers until their contents are no longer needed. ++ */ ++ ++ /* save sr */ ++ movew %sr,%d0 ++ movew %d0,%a0@(TASK_THREAD+THREAD_SR) ++ ++ /* save usp */ ++ /* Save USP via %a1 (which is saved/restored from %d0) */ ++ movel %a1,%d0 ++ movel %usp,%a1 ++ movel %a1,%a0@(TASK_THREAD+THREAD_USP) ++ movel %d0,%a1 ++ ++ /* save non-scratch registers on stack */ ++ SAVE_SWITCH_STACK ++ ++ /* save current kernel stack pointer */ ++ movel %sp,%a0@(TASK_THREAD+THREAD_KSP) ++#ifdef CONFIG_FPU ++ /* save floating point context */ ++ fsave %a0@(TASK_THREAD+THREAD_FPSTATE) ++ ++1: tstb %a0@(TASK_THREAD+THREAD_FPSTATE) ++ jeq 3f ++2: ++ fmovemd %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG) ++3: ++#endif ++ /* Return previous task in %d1 */ ++ movel %curptr,%d1 ++ ++ /* switch to new task (a1 contains new task) */ ++ movel %a1,%curptr ++#ifdef CONFIG_FPU ++ /* restore floating point context */ ++1: tstb %a1@(TASK_THREAD+THREAD_FPSTATE) ++ jeq 3f ++2: ++ fmovemd %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7 ++/* frestore %a1@(TASK_THREAD+THREAD_FPCNTL)*/ ++3: frestore %a1@(TASK_THREAD+THREAD_FPSTATE) ++#endif ++ /* restore the kernel stack pointer */ ++ movel %a1@(TASK_THREAD+THREAD_KSP),%sp ++ ++ /* restore non-scratch registers */ ++ RESTORE_SWITCH_STACK ++ ++ /* restore user stack pointer */ ++ movel %a1@(TASK_THREAD+THREAD_USP),%a0 ++ movel %a0,%usp ++ ++ /* restore status register */ ++ movew %a1@(TASK_THREAD+THREAD_SR),%d0 ++ movew %d0,%sr ++ ++ rts ++ ++.data ++ALIGN ++sys_call_table: ++ .long sys_ni_syscall /* 0 - old "setup()" system call*/ ++ .long sys_exit ++ .long sys_fork ++ .long sys_read ++ .long sys_write ++ .long sys_open /* 5 */ ++ .long sys_close ++ .long sys_waitpid ++ .long sys_creat ++ .long sys_link ++ .long sys_unlink /* 10 */ ++ .long sys_execve ++ .long sys_chdir ++ .long sys_time ++ .long sys_mknod ++ .long sys_chmod /* 15 */ ++ .long sys_chown16 ++ .long sys_ni_syscall /* old break syscall holder */ ++ .long sys_stat ++ .long sys_lseek ++ .long sys_getpid /* 20 */ ++ .long sys_mount ++ .long sys_oldumount ++ .long sys_setuid16 ++ .long sys_getuid16 ++ .long sys_stime /* 25 */ ++ .long sys_ptrace ++ .long sys_alarm ++ .long sys_fstat ++ .long sys_pause ++ .long sys_utime /* 30 */ ++ .long sys_ni_syscall /* old stty syscall holder */ ++ .long sys_ni_syscall /* old gtty syscall holder */ ++ .long sys_access ++ .long sys_nice ++ .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */ ++ .long sys_sync ++ .long sys_kill ++ .long sys_rename ++ .long sys_mkdir ++ .long sys_rmdir /* 40 */ ++ .long sys_dup ++ .long sys_pipe ++ .long sys_times ++ .long sys_ni_syscall /* old prof syscall holder */ ++ .long sys_brk /* 45 */ ++ .long sys_setgid16 ++ .long sys_getgid16 ++ .long sys_signal ++ .long sys_geteuid16 ++ .long sys_getegid16 /* 50 */ ++ .long sys_acct ++ .long sys_umount /* recycled never used phys() */ ++ .long sys_ni_syscall /* old lock syscall holder */ ++ .long sys_ioctl ++ .long sys_fcntl /* 55 */ ++ .long sys_ni_syscall /* old mpx syscall holder */ ++ .long sys_setpgid ++ .long sys_ni_syscall /* old ulimit syscall holder */ ++ .long sys_ni_syscall ++ .long sys_umask /* 60 */ ++ .long sys_chroot ++ .long sys_ustat ++ .long sys_dup2 ++ .long sys_getppid ++ .long sys_getpgrp /* 65 */ ++ .long sys_setsid ++ .long sys_sigaction ++ .long sys_sgetmask ++ .long sys_ssetmask ++ .long sys_setreuid16 /* 70 */ ++ .long sys_setregid16 ++ .long sys_sigsuspend ++ .long sys_sigpending ++ .long sys_sethostname ++ .long sys_setrlimit /* 75 */ ++ .long sys_old_getrlimit ++ .long sys_getrusage ++ .long sys_gettimeofday ++ .long sys_settimeofday ++ .long sys_getgroups16 /* 80 */ ++ .long sys_setgroups16 ++ .long old_select ++ .long sys_symlink ++ .long sys_lstat ++ .long sys_readlink /* 85 */ ++ .long sys_uselib ++ .long sys_swapon ++ .long sys_reboot ++ .long sys_old_readdir ++ .long old_mmap /* 90 */ ++ .long sys_munmap ++ .long sys_truncate ++ .long sys_ftruncate ++ .long sys_fchmod ++ .long sys_fchown16 /* 95 */ ++ .long sys_getpriority ++ .long sys_setpriority ++ .long sys_ni_syscall /* old profil syscall holder */ ++ .long sys_statfs ++ .long sys_fstatfs /* 100 */ ++ .long sys_ni_syscall /* ioperm for i386 */ ++ .long sys_socketcall ++ .long sys_syslog ++ .long sys_setitimer ++ .long sys_getitimer /* 105 */ ++ .long sys_newstat ++ .long sys_newlstat ++ .long sys_newfstat ++ .long sys_ni_syscall ++ .long sys_ni_syscall /* 110 */ /* iopl for i386 */ ++ .long sys_vhangup ++ .long sys_ni_syscall /* obsolete idle() syscall */ ++ .long sys_ni_syscall /* vm86old for i386 */ ++ .long sys_wait4 ++ .long sys_swapoff /* 115 */ ++ .long sys_sysinfo ++ .long sys_ipc ++ .long sys_fsync ++ .long sys_sigreturn ++ .long sys_clone /* 120 */ ++ .long sys_setdomainname ++ .long sys_newuname ++ .long sys_cacheflush /* modify_ldt for i386 */ ++ .long sys_adjtimex ++ .long sys_mprotect /* 125 */ ++ .long sys_sigprocmask ++ .long sys_ni_syscall /* old "create_module" */ ++ .long sys_init_module ++ .long sys_delete_module ++ .long sys_ni_syscall /* 130 - old "get_kernel_syms" */ ++ .long sys_quotactl ++ .long sys_getpgid ++ .long sys_fchdir ++ .long sys_bdflush ++ .long sys_sysfs /* 135 */ ++ .long sys_personality ++ .long sys_ni_syscall /* for afs_syscall */ ++ .long sys_setfsuid16 ++ .long sys_setfsgid16 ++ .long sys_llseek /* 140 */ ++ .long sys_getdents ++ .long sys_select ++ .long sys_flock ++ .long sys_msync ++ .long sys_readv /* 145 */ ++ .long sys_writev ++ .long sys_getsid ++ .long sys_fdatasync ++ .long sys_sysctl ++ .long sys_mlock /* 150 */ ++ .long sys_munlock ++ .long sys_mlockall ++ .long sys_munlockall ++ .long sys_sched_setparam ++ .long sys_sched_getparam /* 155 */ ++ .long sys_sched_setscheduler ++ .long sys_sched_getscheduler ++ .long sys_sched_yield ++ .long sys_sched_get_priority_max ++ .long sys_sched_get_priority_min /* 160 */ ++ .long sys_sched_rr_get_interval ++ .long sys_nanosleep ++ .long sys_mremap ++ .long sys_setresuid16 ++ .long sys_getresuid16 /* 165 */ ++ .long sys_getpagesize ++ .long sys_ni_syscall /* old sys_query_module */ ++ .long sys_poll ++ .long sys_nfsservctl ++ .long sys_setresgid16 /* 170 */ ++ .long sys_getresgid16 ++ .long sys_prctl ++ .long sys_rt_sigreturn ++ .long sys_rt_sigaction ++ .long sys_rt_sigprocmask /* 175 */ ++ .long sys_rt_sigpending ++ .long sys_rt_sigtimedwait ++ .long sys_rt_sigqueueinfo ++ .long sys_rt_sigsuspend ++ .long sys_pread64 /* 180 */ ++ .long sys_pwrite64 ++ .long sys_lchown16; ++ .long sys_getcwd ++ .long sys_capget ++ .long sys_capset /* 185 */ ++ .long sys_sigaltstack ++ .long sys_sendfile ++ .long sys_ni_syscall /* streams1 */ ++ .long sys_ni_syscall /* streams2 */ ++ .long sys_vfork /* 190 */ ++ .long sys_getrlimit ++ .long sys_mmap2 ++ .long sys_truncate64 ++ .long sys_ftruncate64 ++ .long sys_stat64 /* 195 */ ++ .long sys_lstat64 ++ .long sys_fstat64 ++ .long sys_chown ++ .long sys_getuid ++ .long sys_getgid /* 200 */ ++ .long sys_geteuid ++ .long sys_getegid ++ .long sys_setreuid ++ .long sys_setregid ++ .long sys_getgroups /* 205 */ ++ .long sys_setgroups ++ .long sys_fchown ++ .long sys_setresuid ++ .long sys_getresuid ++ .long sys_setresgid /* 210 */ ++ .long sys_getresgid ++ .long sys_lchown ++ .long sys_setuid ++ .long sys_setgid ++ .long sys_setfsuid /* 215 */ ++ .long sys_setfsgid ++ .long sys_pivot_root ++ .long sys_ni_syscall ++ .long sys_ni_syscall ++ .long sys_getdents64 /* 220 */ ++ .long sys_gettid ++ .long sys_tkill ++ .long sys_setxattr ++ .long sys_lsetxattr ++ .long sys_fsetxattr /* 225 */ ++ .long sys_getxattr ++ .long sys_lgetxattr ++ .long sys_fgetxattr ++ .long sys_listxattr ++ .long sys_llistxattr /* 230 */ ++ .long sys_flistxattr ++ .long sys_removexattr ++ .long sys_lremovexattr ++ .long sys_fremovexattr ++ .long sys_futex /* 235 */ ++ .long sys_sendfile64 ++ .long sys_mincore ++ .long sys_madvise ++ .long sys_fcntl64 ++ .long sys_readahead /* 240 */ ++ .long sys_io_setup ++ .long sys_io_destroy ++ .long sys_io_getevents ++ .long sys_io_submit ++ .long sys_io_cancel /* 245 */ ++ .long sys_fadvise64 ++ .long sys_exit_group ++ .long sys_lookup_dcookie ++ .long sys_epoll_create ++ .long sys_epoll_ctl /* 250 */ ++ .long sys_epoll_wait ++ .long sys_remap_file_pages ++ .long sys_set_tid_address ++ .long sys_timer_create ++ .long sys_timer_settime /* 255 */ ++ .long sys_timer_gettime ++ .long sys_timer_getoverrun ++ .long sys_timer_delete ++ .long sys_clock_settime ++ .long sys_clock_gettime /* 260 */ ++ .long sys_clock_getres ++ .long sys_clock_nanosleep ++ .long sys_statfs64 ++ .long sys_fstatfs64 ++ .long sys_tgkill /* 265 */ ++ .long sys_utimes ++ .long sys_fadvise64_64 ++ .long sys_mbind ++ .long sys_get_mempolicy ++ .long sys_set_mempolicy /* 270 */ ++ .long sys_mq_open ++ .long sys_mq_unlink ++ .long sys_mq_timedsend ++ .long sys_mq_timedreceive ++ .long sys_mq_notify /* 275 */ ++ .long sys_mq_getsetattr ++ .long sys_waitid ++ .long sys_ni_syscall /* for sys_vserver */ ++ .long sys_add_key ++ .long sys_request_key /* 280 */ ++ .long sys_keyctl ++ .long sys_ioprio_set ++ .long sys_ioprio_get ++ .long sys_inotify_init ++ .long sys_inotify_add_watch /* 285 */ ++ .long sys_inotify_rm_watch ++ .long sys_migrate_pages ++ .long sys_openat ++ .long sys_mkdirat ++ .long sys_mknodat /* 290 */ ++ .long sys_fchownat ++ .long sys_futimesat ++ .long sys_fstatat64 ++ .long sys_unlinkat ++ .long sys_renameat /* 295 */ ++ .long sys_linkat ++ .long sys_symlinkat ++ .long sys_readlinkat ++ .long sys_fchmodat ++ .long sys_faccessat /* 300 */ ++ .long sys_ni_syscall /* Reserved for pselect6 */ ++ .long sys_ni_syscall /* Reserved for ppoll */ ++ .long sys_unshare ++ .long sys_set_robust_list ++ .long sys_get_robust_list /* 305 */ ++ .long sys_splice ++ .long sys_sync_file_range ++ .long sys_tee ++ .long sys_vmsplice ++ .long sys_move_pages /* 310 */ ++ .long sys_sched_setaffinity ++ .long sys_sched_getaffinity ++ .long sys_kexec_load ++ .long sys_getcpu ++ .long sys_epoll_pwait /* 315 */ ++ .long sys_utimensat ++ .long sys_signalfd ++ .long sys_timerfd_create ++ .long sys_eventfd ++ .long sys_fallocate /* 320 */ ++ .long sys_timerfd_settime ++ .long sys_timerfd_gettime ++ .long sys_signalfd4 ++ .long sys_eventfd2 ++ .long sys_epoll_create1 /* 325 */ ++ .long sys_dup3 ++ .long sys_pipe2 ++ .long sys_inotify_init1 ++ .long sys_preadv ++ .long sys_pwritev /* 330 */ ++ .long sys_rt_tgsigqueueinfo ++ .long sys_perf_event_open ++ .long sys_get_thread_area ++ .long sys_set_thread_area ++ .long sys_atomic_cmpxchg_32 /* 335 */ ++ .long sys_atomic_barrier ++ .long sys_fanotify_init ++ .long sys_fanotify_mark ++ .long sys_prlimit64 +--- /dev/null ++++ b/arch/m68k/coldfire/common/head.S +@@ -0,0 +1,466 @@ ++/* ++ * head.S is the MMU enabled ColdFire specific initial boot code ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Kurt Mahan kmahan@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Parts of this code came from arch/m68k/kernel/head.S ++ */ ++#include <linux/linkage.h> ++#include <linux/init.h> ++#include <asm/bootinfo.h> ++#include <asm/setup.h> ++#include <asm/entry.h> ++#include <asm/pgtable.h> ++#include <asm/page.h> ++#include <asm/coldfire.h> ++#include <asm/cfcache.h> ++ ++#define DEBUG ++ ++.globl kernel_pg_dir ++.globl availmem ++.globl set_context ++.globl set_fpga ++ ++#ifdef DEBUG ++/* When debugging use readable names for labels */ ++#ifdef __STDC__ ++#define L(name) .head.S.##name ++#else ++#define L(name) .head.S./**/name ++#endif ++#else ++#ifdef __STDC__ ++#define L(name) .L##name ++#else ++#define L(name) .L/**/name ++#endif ++#endif ++ ++/* The __INITDATA stuff is a no-op when ftrace or kgdb are turned on */ ++#ifndef __INITDATA ++#define __INITDATA .data ++#define __FINIT .previous ++#endif ++ ++/* ++ * Kernel mapped to physical ram address. ++ * ++ * M5445x: ++ * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs ++ * Data[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached ++ * Code[0]: Not Mapped ++ * Code[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached ++ * ++ * M547x/M548x ++ * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs ++ * Data[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - uncached ++ * Code[0]: Not Mapped ++ * Code[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - cached ++ * ++ * M5441X: ++ * Data[0]: 0xE0000000 -> 0xFFFFFFFF System regs ++ * Data[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached ++ * Code[0]: Not Mapped ++ * Code[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached ++ */ ++#if defined(CONFIG_M5445X) ++#define ACR0_DEFAULT #0xF00FA048 /* System Regs uncached/precise */ ++#define ACR1_DEFAULT #0x400FA028 /* SDRAM cached/copyback */ ++#define ACR2_DEFAULT #0x00000000 /* Not mapped */ ++#define ACR3_DEFAULT #0x400FA028 /* SDRAM cached/copyback */ ++#elif defined(CONFIG_M547X_8X) ++#define ACR0_DEFAULT #0xF00FA048 /* System Regs */ ++#define ACR1_DEFAULT #0x000FA028 /* SDRAM cached/copy-back */ ++#define ACR2_DEFAULT #0x00000000 /* Not mapped */ ++#define ACR3_DEFAULT #0x000FA028 /* Instruction cached/copy-back */ ++#elif defined(CONFIG_M5441X) ++#define ACR0_DEFAULT #0xE01FA048 /* System Regs */ ++#define ACR1_DEFAULT #0x400FA028 /* SDRAM cached/copyback */ ++#define ACR4_DEFAULT #0x00000000 /* Not mapped */ ++#define ACR5_DEFAULT #0x00000000 /* Not mapped */ ++#define ACR2_DEFAULT #0x00000000 /* Not mapped */ ++#define ACR3_DEFAULT #0x400FA028 /* Instruction cached/copy-back */ ++#define ACR6_DEFAULT #0x00000000 /* Not mapped */ ++#define ACR7_DEFAULT #0x00000000 /* Not mapped */ ++#endif ++ ++/* ACR mapping for FPGA (maps 0) */ ++#define ACR0_FPGA #0x000FA048 /* ACR0 enable FPGA */ ++ ++/* Several macros to make the writing of subroutines easier: ++ * - func_start marks the beginning of the routine which setups the frame ++ * register and saves the registers, it also defines another macro ++ * to automatically restore the registers again. ++ * - func_return marks the end of the routine and simply calls the prepared ++ * macro to restore registers and jump back to the caller. ++ * - func_define generates another macro to automatically put arguments ++ * onto the stack call the subroutine and cleanup the stack again. ++ */ ++ ++.macro load_symbol_address symbol,register ++ movel #\symbol,\register ++.endm ++ ++.macro func_start name,saveregs,savesize,stack=0 ++L(\name): ++ linkw %a6,#-\stack ++ subal #(\savesize),%sp ++ moveml \saveregs,%sp@ ++.set stackstart,-\stack ++ ++.macro func_return_\name ++ moveml %sp@,\saveregs ++ addal #(\savesize),%sp ++ unlk %a6 ++ rts ++.endm ++.endm ++ ++.macro func_return name ++ func_return_\name ++.endm ++ ++.macro func_call name ++ jbsr L(\name) ++.endm ++ ++.macro move_stack nr,arg1,arg2,arg3,arg4 ++.if \nr ++ move_stack "(\nr-1)",\arg2,\arg3,\arg4 ++ movel \arg1,%sp@- ++.endif ++.endm ++ ++.macro func_define name,nr=0 ++.macro \name arg1,arg2,arg3,arg4 ++ move_stack \nr,\arg1,\arg2,\arg3,\arg4 ++ func_call \name ++.if \nr ++ lea %sp@(\nr*4),%sp ++.endif ++.endm ++.endm ++ ++func_define serial_putc,1 ++ ++.macro putc ch ++ pea \ch ++ func_call serial_putc ++ addql #4,%sp ++.endm ++ ++.macro dputc ch ++#ifdef DEBUG ++ putc \ch ++#endif ++.endm ++ ++func_define putn,1 ++ ++.macro dputn nr ++#ifdef DEBUG ++ putn \nr ++#endif ++.endm ++ ++/* ++ mmu_map - creates a new TLB entry ++ ++ virt_addr Must be on proper boundary ++ phys_addr Must be on proper boundary ++ itlb MMUOR_ITLB if instruction TLB or 0 ++ asid address space ID ++ shared_global MMUTR_SG if shared between different ASIDs or 0 ++ size_code MMUDR_SZ1M 1 MB ++ MMUDR_SZ4K 4 KB ++ MMUDR_SZ8K 8 KB ++ MMUDR_SZ16M 16 MB ++ cache_mode MMUDR_INC instruction non-cacheable ++ MMUDR_IC instruction cacheable ++ MMUDR_DWT data writethrough ++ MMUDR_DCB data copyback ++ MMUDR_DNCP data non-cacheable, precise ++ MMUDR_DNCIP data non-cacheable, imprecise ++ super_prot MMUDR_SP if user mode generates exception or 0 ++ readable MMUDR_R if permits read access (data TLB) or 0 ++ writable MMUDR_W if permits write access (data TLB) or 0 ++ executable MMUDR_X if permits execute access (instruction TLB) or 0 ++ locked MMUDR_LK prevents TLB entry from being replaced or 0 ++ temp_data_reg a data register to use for temporary values ++*/ ++.macro mmu_map virt_addr,phys_addr,itlb,asid,shared_global,size_code, \ ++ cache_mode,super_prot,readable,writable,executable,locked,temp_data_reg ++ /* Set up search of TLB. */ ++ movel #(\virt_addr+1), \temp_data_reg ++ movel \temp_data_reg, MMUAR ++ /* Search. */ ++ movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg ++ movew \temp_data_reg, (MMUOR) ++ /* Set up tag value. */ ++ movel #(\virt_addr + \asid + \shared_global + MMUTR_V), \temp_data_reg ++ movel \temp_data_reg, MMUTR ++ /* Set up data value. */ ++ movel #(\phys_addr + \size_code + \cache_mode + \super_prot + \ ++ \readable + \writable + \executable + \locked), \temp_data_reg ++ movel \temp_data_reg, MMUDR ++ /* Save it. */ ++ movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg ++ movew \temp_data_reg, (MMUOR) ++.endm /* mmu_map */ ++ ++.macro mmu_unmap virt_addr,itlb,temp_data_reg ++ /* Set up search of TLB. */ ++ movel #(\virt_addr+1), \temp_data_reg ++ movel \temp_data_reg, MMUAR ++ /* Search. */ ++ movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg ++ movew \temp_data_reg, (MMUOR) ++ /* Test for hit. */ ++ movel MMUSR,\temp_data_reg ++ btst #MMUSR_HITN,\temp_data_reg ++ beq 1f ++ /* Read the TLB. */ ++ movel #(MMUOR_RW + MMUOR_ACC +\itlb), \temp_data_reg ++ movew \temp_data_reg, (MMUOR) ++ movel MMUSR,\temp_data_reg ++ /* Set up tag value. */ ++ movel #0, \temp_data_reg ++ movel \temp_data_reg, MMUTR ++ /* Set up data value. */ ++ movel #0, \temp_data_reg ++ movel \temp_data_reg, MMUDR ++ /* Save it. */ ++ movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg ++ movew \temp_data_reg, (MMUOR) ++1: ++.endm /* mmu_unmap */ ++ ++/* .text */ ++.section ".text.head","ax" ++ENTRY(_stext) ++/* Version numbers of the bootinfo interface -- if we later pass info ++ * from boot ROM we might want to put something real here. ++ * ++ * The area from _stext to _start will later be used as kernel pointer table ++ */ ++ bras 1f /* Jump over bootinfo version numbers */ ++ ++ .long BOOTINFOV_MAGIC ++ .long 0 ++1: jmp __start ++ ++.equ kernel_pg_dir,_stext ++.equ .,_stext+0x1000 ++ ++ENTRY(_start) ++ jra __start ++__INIT ++ENTRY(__start) ++/* Save the location of u-boot info - cmd line, bd_info, etc. */ ++ movel %a7,%a4 /* Don't use %a4 before cf_early_init */ ++ addl #0x00000004,%a4 /* offset past top */ ++ addl #(PAGE_OFFSET-CONFIG_SDRAM_BASE),%a4 /* high mem offset */ ++ ++/* Setup initial stack pointer */ ++ movel #CONFIG_SDRAM_BASE+0x1000,%sp ++ ++/* Setup usp */ ++ subl %a0,%a0 ++ movel %a0,%usp ++ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++#if defined(CONFIG_SRAM) ++ movel #(CONFIG_SRAM_BASE+0x221), %d0 ++#else ++ movel #0x80000000, %d0 ++#endif ++ ++#ifdef CONFIG_M5441X ++ movec %d0, %rambar ++#else ++ movec %d0, %rambar1 ++#endif ++#elif defined(CONFIG_M547X_8X) ++ movel #MCF_MBAR, %d0 ++ movec %d0, %mbar ++ move.l #(MCF_RAMBAR0 + 0x21), %d0 ++ movec %d0, %rambar0 ++ move.l #(MCF_RAMBAR1 + 0x21), %d0 ++ movec %d0, %rambar1 ++#endif ++ ++ movew #0x2700,%sr ++ ++/* reset cache */ ++ movel #(CF_CACR_ICINVA + CF_CACR_DCINVA),%d0 ++ movecl %d0,%cacr ++ ++ movel #(MMU_BASE+1),%d0 ++ movecl %d0,%mmubar ++ movel #MMUOR_CA,%a0 /* Clear tlb entries */ ++ movew %a0,(MMUOR) ++ movel #(MMUOR_CA + MMUOR_ITLB),%a0 /* Use ITLB for searches */ ++ movew %a0,(MMUOR) ++ movel #0,%a0 /* Clear Addr Space User ID */ ++ movecl %a0,%asid ++ ++/* setup ACRs */ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) || defined(CONFIG_M5441X) ++ movel ACR0_DEFAULT, %d0 /* ACR0 (DATA) setup */ ++ movec %d0, %acr0 ++ nop ++ movel ACR1_DEFAULT, %d0 /* ACR1 (DATA) setup */ ++ movec %d0, %acr1 ++ nop ++ movel ACR2_DEFAULT, %d0 /* ACR2 (CODE) setup */ ++ movec %d0, %acr2 ++ nop ++ movel ACR3_DEFAULT, %d0 /* ACR3 (CODE) setup */ ++ movec %d0, %acr3 ++ nop ++#endif ++ /* Turn on MMU */ ++ movel #(MMUCR_EN),%a0 ++ movel %a0,MMUCR ++ nop /* This synchs the pipeline after a write to MMUCR */ ++ ++ movel #__running_high,%a0 /* Get around PC-relative addressing. */ ++ jmp %a0@ ++ ++ENTRY(__running_high) ++ load_symbol_address _stext,%sp ++ movel L(memory_start),%a0 ++ movel %a0,availmem ++ load_symbol_address L(phys_kernel_start),%a0 ++ load_symbol_address _stext,%a1 ++ subl #_stext,%a1 ++ addl #PAGE_OFFSET,%a1 ++ movel %a1,%a0@ ++ ++/* zero bss */ ++ lea _sbss,%a0 ++ lea _ebss,%a1 ++ clrl %d0 ++_loop_bss: ++ movel %d0,(%a0)+ ++ cmpl %a0,%a1 ++ bne _loop_bss ++ ++/* create dma memory mirror TLB mapping */ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ mmu_map CONFIG_DMA_BASE, \ ++ CONFIG_SDRAM_BASE, 0, 0, \ ++ MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ ++ 0, MMUDR_LK, %d0 ++#elif defined(CONFIG_M547X_8X) ++ mmu_map (CONFIG_DMA_BASE + 0*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 0*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 1*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 1*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 2*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 2*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 3*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 3*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 4*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 4*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 5*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 5*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 6*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 6*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++ mmu_map (CONFIG_DMA_BASE + 7*1024*1024), \ ++ (CONFIG_SDRAM_BASE + 7*1024*1024), 0, 0, \ ++ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ ++ MMUDR_W, 0, MMUDR_LK, %d0 ++#endif ++ ++/* Setup initial stack pointer */ ++ lea init_task,%a2 ++ lea init_thread_union+THREAD_SIZE,%sp ++ subl %a6,%a6 /* clear a6 for gdb */ ++ ++#ifdef CONFIG_MCF_USER_HALT ++/* Setup debug control reg to allow halts from user space */ ++ lea wdbg_uhe,%a0 ++ wdebug (%a0) ++#endif ++ ++ movel %a4,uboot_info_stk /* save uboot info to variable */ ++ jsr cf_early_init ++ jmp start_kernel ++ ++.section ".text.head","ax" ++set_context: ++func_start set_context,%d0,(1*4) ++ movel 12(%sp),%d0 ++ movec %d0,%asid ++func_return set_context ++ ++#ifdef CONFIG_M54455 ++/* ++ * set_fpga(addr,val) on the M5445X ++ * ++ * Map in 0x00000000 -> 0x0fffffff and then do the write. ++ */ ++set_fpga: ++ movew %sr,%d1 ++ movew #0x2700,%sr ++ movel ACR0_FPGA, %d0 ++ movec %d0, %acr0 ++ nop ++ moveal 4(%sp),%a0 ++ movel 8(%sp),%a0@ ++ movel ACR0_DEFAULT, %d0 ++ movec %d0, %acr0 ++ nop ++ movew %d1,%sr ++ rts ++#endif ++ ++ .data ++ .align 4 ++ ++availmem: ++ .long 0 ++L(phys_kernel_start): ++ .long PAGE_OFFSET ++L(kernel_end): ++ .long 0 ++L(memory_start): ++ .long PAGE_OFFSET_RAW ++ ++#ifdef CONFIG_MCF_USER_HALT ++/* ++ * Enable User Halt Enable in the debug control register. ++ */ ++wdbg_uhe: ++ .word 0x2c80 /* DR0 */ ++ .word 0x00b0 /* 31:16 */ ++ .word 0x0400 /* 15:0 -- enable UHE */ ++ .word 0x0000 /* unused */ ++#endif ++ ++ +--- /dev/null ++++ b/arch/m68k/coldfire/common/ints.c +@@ -0,0 +1,544 @@ ++/* ++ * linux/arch/m68k/coldfire/ints.c -- General interrupt handling code ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Kurt Mahan kmahan@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * Based on: ++ * linux/arch/m68k/kernel/ints.c & ++ * linux/arch/m68knommu/5307/ints.c ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#include <linux/module.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/sched.h> ++#include <linux/kernel_stat.h> ++#include <linux/errno.h> ++#include <linux/seq_file.h> ++#include <linux/interrupt.h> ++ ++#include <asm/system.h> ++#include <asm/irq.h> ++#include <asm/traps.h> ++#include <asm/page.h> ++#include <asm/machdep.h> ++#include <asm/irq_regs.h> ++ ++#include <asm/mcfsim.h> ++ ++/* ++ * IRQ Handler lists. ++ */ ++static struct irq_node *irq_list[SYS_IRQS]; ++static struct irq_controller *irq_controller[SYS_IRQS]; ++static int irq_depth[SYS_IRQS]; ++ ++#define POOL_SIZE SYS_IRQS ++static struct irq_node pool[POOL_SIZE]; ++static struct irq_node *get_irq_node(void); ++ ++/* The number of spurious interrupts */ ++unsigned int num_spurious; ++asmlinkage void handle_badint(struct pt_regs *regs); ++ ++/* ++ * process_int(unsigned long vec, struct pt_regs *fp) ++ * ++ * Process an interrupt. Called from entry.S. ++ */ ++asmlinkage void process_int(unsigned long vec, struct pt_regs *fp) ++{ ++ struct pt_regs *old_regs; ++ struct irq_node *node; ++ old_regs = set_irq_regs(fp); ++ kstat_cpu(0).irqs[vec]++; ++ ++ node = irq_list[vec]; ++ if (!node) ++ handle_badint(fp); ++ else { ++ do { ++ node->handler(vec, node->dev_id); ++ node = node->next; ++ } while (node); ++ } ++ ++ set_irq_regs(old_regs); ++} ++ ++/* ++ * show_interrupts( struct seq_file *p, void *v) ++ * ++ * Called to show all the current interrupt information. ++ */ ++int show_interrupts(struct seq_file *p, void *v) ++{ ++ struct irq_controller *contr; ++ struct irq_node *node; ++ int i = *(loff_t *) v; ++ ++ if ((i < NR_IRQS) && (irq_list[i])) { ++ contr = irq_controller[i]; ++ node = irq_list[i]; ++ seq_printf(p, "%-8s %3u: %10u %s", contr->name, i, ++ kstat_cpu(0).irqs[i], node->devname); ++ while ((node = node->next)) ++ seq_printf(p, ", %s", node->devname); ++ ++ seq_printf(p, "\n"); ++ } ++ ++ return 0; ++} ++ ++/* ++ * get_irq_node(void) ++ * ++ * Get an irq node from the pool. ++ */ ++struct irq_node *get_irq_node(void) ++{ ++ struct irq_node *p = pool; ++ int i; ++ ++ for (i = 0; i < POOL_SIZE; i++, p++) { ++ if (!p->handler) { ++ memset(p, 0, sizeof(struct irq_node)); ++ return p; ++ } ++ } ++ printk(KERN_INFO "%s(%s:%d): No more irq nodes, I suggest you \ ++ increase POOL_SIZE", __func__, __FILE__, __LINE__); ++ return NULL; ++} ++ ++void init_irq_proc(void) ++{ ++ /* Insert /proc/irq driver here */ ++} ++ ++int setup_irq(unsigned int irq, struct irq_node *node) ++{ ++ struct irq_controller *contr; ++ struct irq_node **prev; ++ unsigned long flags; ++ ++ if (irq >= NR_IRQS || !irq_controller[irq]) { ++ printk("%s: Incorrect IRQ %d from %s\n", ++ __func__, irq, node->devname); ++ return -ENXIO; ++ } ++ ++ contr = irq_controller[irq]; ++ spin_lock_irqsave(&contr->lock, flags); ++ ++ prev = irq_list + irq; ++ if (*prev) { ++ /* Can't share interrupts unless both agree to */ ++ if (!((*prev)->flags & node->flags & IRQF_SHARED)) { ++ spin_unlock_irqrestore(&contr->lock, flags); ++ printk(KERN_INFO "%s: -BUSY-Incorrect IRQ %d\n", ++ __func__, irq); ++ return -EBUSY; ++ } ++ while (*prev) ++ prev = &(*prev)->next; ++ } ++ ++ if (!irq_list[irq]) { ++ if (contr->startup) ++ contr->startup(irq); ++ else ++ contr->enable(irq); ++ } ++ node->next = NULL; ++ *prev = node; ++ ++ spin_unlock_irqrestore(&contr->lock, flags); ++ ++ return 0; ++} ++ ++int request_irq(unsigned int irq, ++ irq_handler_t handler, ++ unsigned long flags, const char *devname, void *dev_id) ++{ ++ struct irq_node *node = get_irq_node(); ++ int res; ++ ++ if (!node) { ++ printk(KERN_INFO "%s:get_irq_node error %x\n", ++ __func__, (unsigned int) node); ++ return -ENOMEM; ++ } ++ node->handler = handler; ++ node->flags = flags; ++ node->dev_id = dev_id; ++ node->devname = devname; ++ ++ res = setup_irq(irq, node); ++ if (res) ++ node->handler = NULL; ++ ++ return res; ++} ++EXPORT_SYMBOL(request_irq); ++ ++void free_irq(unsigned int irq, void *dev_id) ++{ ++ struct irq_controller *contr; ++ struct irq_node **p, *node; ++ unsigned long flags; ++ ++ if (irq >= NR_IRQS || !irq_controller[irq]) { ++ printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __func__, irq); ++ return; ++ } ++ ++ contr = irq_controller[irq]; ++ spin_lock_irqsave(&contr->lock, flags); ++ ++ p = irq_list + irq; ++ while ((node = *p)) { ++ if (node->dev_id == dev_id) ++ break; ++ p = &node->next; ++ } ++ ++ if (node) { ++ *p = node->next; ++ node->handler = NULL; ++ } else ++ printk(KERN_DEBUG "%s: Removing probably wrong IRQ %d\n", ++ __func__, irq); ++ ++ if (!irq_list[irq]) { ++ if (contr->shutdown) ++ contr->shutdown(irq); ++ else ++ contr->disable(irq); ++ } ++ ++ spin_unlock_irqrestore(&contr->lock, flags); ++} ++EXPORT_SYMBOL(free_irq); ++ ++void enable_irq(unsigned int irq) ++{ ++ struct irq_controller *contr; ++ unsigned long flags; ++ ++ if (irq >= NR_IRQS || !irq_controller[irq]) { ++ printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __func__, irq); ++ return; ++ } ++ ++ contr = irq_controller[irq]; ++ spin_lock_irqsave(&contr->lock, flags); ++ if (irq_depth[irq]) { ++ if (!--irq_depth[irq]) { ++ if (contr->enable) ++ contr->enable(irq); ++ } ++ } else ++ WARN_ON(1); ++ spin_unlock_irqrestore(&contr->lock, flags); ++} ++EXPORT_SYMBOL(enable_irq); ++ ++void disable_irq(unsigned int irq) ++{ ++ struct irq_controller *contr; ++ unsigned long flags; ++ ++ if (irq >= NR_IRQS || !irq_controller[irq]) { ++ printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __func__, irq); ++ return; ++ } ++ ++ contr = irq_controller[irq]; ++ spin_lock_irqsave(&contr->lock, flags); ++ if (!irq_depth[irq]++) { ++ if (contr->disable) ++ contr->disable(irq); ++ } ++ spin_unlock_irqrestore(&contr->lock, flags); ++} ++EXPORT_SYMBOL(disable_irq); ++ ++void disable_irq_nosync(unsigned int irq) __attribute__((alias("disable_irq"))); ++EXPORT_SYMBOL(disable_irq_nosync); ++ ++ ++unsigned long probe_irq_on(void) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(probe_irq_on); ++ ++int probe_irq_off(unsigned long irqs) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(probe_irq_off); ++ ++asmlinkage void handle_badint(struct pt_regs *regs) ++{ ++ kstat_cpu(0).irqs[0]++; ++ num_spurious++; ++ printk(KERN_DEBUG "unexpected interrupt from %u\n", regs->vector); ++} ++EXPORT_SYMBOL(handle_badint); ++ ++unsigned int irq_canonicalize(unsigned int irq) ++{ ++#ifdef CONFIG_Q40 ++ if (MACH_IS_Q40 && irq == 11) ++ irq = 10; ++#endif ++ return irq; ++} ++EXPORT_SYMBOL(irq_canonicalize); ++ ++#ifdef CONFIG_M5445X ++/* ++ * M5445X Implementation ++ */ ++void m5445x_irq_enable(unsigned int irq) ++{ ++ /* enable the interrupt hardware */ ++ if (irq < 64) ++ return; ++ ++ /* adjust past non-hardware ints */ ++ irq -= 64; ++ ++ /* check for eport */ ++ if ((irq > 0) && (irq < 8)) { ++ /* enable eport */ ++ MCF_EPORT_EPPAR &= ~(3 << (irq*2)); /* level */ ++ MCF_EPORT_EPDDR &= ~(1 << irq); /* input */ ++ MCF_EPORT_EPIER |= 1 << irq; /* irq enabled */ ++ } ++ ++ if (irq < 64) { ++ /* controller 0 */ ++ MCF_INTC0_ICR(irq) = 0x02; ++ MCF_INTC0_CIMR = irq; ++ } else { ++ /* controller 1 */ ++ irq -= 64; ++ MCF_INTC1_ICR(irq) = 0x02; ++ MCF_INTC1_CIMR = irq; ++ } ++} ++ ++void m5445x_irq_disable(unsigned int irq) ++{ ++ /* disable the interrupt hardware */ ++ if (irq < 64) ++ return; ++ ++ /* adjust past non-hardware ints */ ++ irq -= 64; ++ ++ /* check for eport */ ++ if ((irq > 0) && (irq < 8)) { ++ /* disable eport */ ++ MCF_EPORT_EPIER &= ~(1 << irq); ++ } ++ ++ if (irq < 64) { ++ /* controller 0 */ ++ MCF_INTC0_ICR(irq) = 0x00; ++ MCF_INTC0_SIMR = irq; ++ } else { ++ /* controller 1 */ ++ irq -= 64; ++ MCF_INTC1_ICR(irq) = 0x00; ++ MCF_INTC1_SIMR = irq; ++ } ++} ++#elif defined(CONFIG_M547X_8X) ++/* ++ * M547X_8X Implementation ++ */ ++void m547x_8x_irq_enable(unsigned int irq) ++{ ++ /* enable the interrupt hardware */ ++ if (irq < 64) ++ return; ++ ++ /* adjust past non-hardware ints */ ++ irq -= 64; ++ ++ /* check for eport */ ++ if ((irq > 0) && (irq < 8)) { ++ /* enable eport */ ++ MCF_EPPAR &= ~(3 << (irq*2)); ++ /* level */ ++ MCF_EPDDR &= ~(1 << irq); ++ /* input */ ++ MCF_EPIER |= 1 << irq; ++ /* irq enabled */ ++ } ++ ++ if (irq < 32) { ++ /* *grumble* don't set low bit of IMRL */ ++ MCF_IMRL &= (~(1 << irq) & 0xfffffffe); ++ } else { ++ MCF_IMRH &= ~(1 << (irq - 32)); ++ } ++} ++ ++void m547x_8x_irq_disable(unsigned int irq) ++{ ++ /* disable the interrupt hardware */ ++ if (irq < 64) ++ return; ++ ++ /* adjust past non-hardware ints */ ++ irq -= 64; ++ ++ /* check for eport */ ++ if ((irq > 0) && (irq < 8)) { ++ /* disable eport */ ++ MCF_EPIER &= ~(1 << irq); ++ } ++ ++ if (irq < 32) ++ MCF_IMRL |= (1 << irq); ++ else ++ MCF_IMRH |= (1 << (irq - 32)); ++} ++ ++#elif defined(CONFIG_M5441X) ++/* ++ * M5441X Implementation ++ */ ++void m5441x_irq_enable(unsigned int irq) ++{ ++ /* enable the interrupt hardware */ ++ if (irq < 64) ++ return; ++ ++ /* adjust past non-hardware ints */ ++ irq -= 64; ++ ++ /* check for eport */ ++ if ((irq > 0) && (irq < 8)) { ++ /* enable eport */ ++ MCF_EPORT_EPPAR &= ~(3 << (irq*2)); /* level */ ++ MCF_EPORT_EPIER |= 1 << irq; /* irq enabled */ ++ } ++ ++ if (irq < 64) { ++ /* controller 0 */ ++ MCF_INTC0_ICR(irq) = 0x02; ++ MCF_INTC0_CIMR = irq; ++ } else if (irq >= 64 && irq < 128) { ++ /* controller 1 */ ++ irq -= 64; ++ MCF_INTC1_ICR(irq) = 0x02; ++ MCF_INTC1_CIMR = irq; ++ } else if (irq >= 128 && irq < 192) { ++ /* controller 2 */ ++ irq -= 128; ++ MCF_INTC2_ICR(irq) = 0x02; ++ MCF_INTC2_CIMR = irq; ++ } else { ++ /* invalid irq number */ ++ return; ++ } ++} ++ ++void m5441x_irq_disable(unsigned int irq) ++{ ++ /* disable the interrupt hardware */ ++ if (irq < 64) ++ return; ++ ++ /* adjust past non-hardware ints */ ++ irq -= 64; ++ ++ /* check for eport */ ++ if ((irq > 0) && (irq < 8)) { ++ /* disable eport */ ++ MCF_EPORT_EPIER &= ~(1 << irq); ++ } ++ ++ if (irq < 64) { ++ /* controller 0 */ ++ MCF_INTC0_ICR(irq) = 0x00; ++ MCF_INTC0_SIMR = irq; ++ } else if (irq >= 64 && irq < 128) { ++ /* controller 1 */ ++ irq -= 64; ++ MCF_INTC1_ICR(irq) = 0x00; ++ MCF_INTC1_SIMR = irq; ++ } else if (irq >= 128 && irq < 192) { ++ /* controller 2 */ ++ irq -= 128; ++ MCF_INTC2_ICR(irq) = 0x00; ++ MCF_INTC2_SIMR = irq; ++ } ++} ++#endif ++ ++/* ++ * IRQ Controller ++ */ ++#if defined(CONFIG_M5445X) ++static struct irq_controller m5445x_irq_controller = { ++ .name = "M5445X", ++ .lock = __SPIN_LOCK_UNLOCKED(m5445x_irq_controller.lock), ++ .enable = m5445x_irq_enable, ++ .disable = m5445x_irq_disable, ++}; ++#elif defined(CONFIG_M547X_8X) ++static struct irq_controller m547x_8x_irq_controller = { ++ .name = "M547X_8X", ++ .lock = __SPIN_LOCK_UNLOCKED(m547x_8x_irq_controller.lock), ++ .enable = m547x_8x_irq_enable, ++ .disable = m547x_8x_irq_disable, ++}; ++#elif defined(CONFIG_M5441X) ++static struct irq_controller m5441x_irq_controller = { ++ .name = "M5441X", ++ .lock = __SPIN_LOCK_UNLOCKED(m5441x_irq_controller.lock), ++ .enable = m5441x_irq_enable, ++ .disable = m5441x_irq_disable, ++}; ++#else ++# error No IRQ controller defined ++#endif ++ ++/* ++ * void init_IRQ(void) ++ * ++ * This function should be called during kernel startup to initialize ++ * the IRQ handling routines. ++ */ ++void __init init_IRQ(void) ++{ ++ int i; ++ ++#if defined(CONFIG_M5445X) ++ for (i = 0; i < SYS_IRQS; i++) ++ irq_controller[i] = &m5445x_irq_controller; ++#elif defined(CONFIG_M547X_8X) ++ for (i = 0; i < SYS_IRQS; i++) ++ irq_controller[i] = &m547x_8x_irq_controller; ++#elif defined(CONFIG_M5441X) ++ for (i = 0; i < SYS_IRQS; i++) ++ irq_controller[i] = &m5441x_irq_controller; ++#endif ++} +--- /dev/null ++++ b/arch/m68k/coldfire/common/muldi3.S +@@ -0,0 +1,73 @@ ++/* ++ * Coldfire muldi3 assembly verion ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/linkage.h> ++.globl __muldi3 ++ ++ENTRY(__muldi3) ++ linkw %fp,#0 ++ lea %sp@(-32),%sp ++ moveml %d2-%d7/%a2-%a3,%sp@ ++ moveal %fp@(8), %a2 ++ moveal %fp@(12), %a3 ++ moveal %fp@(16), %a0 ++ moveal %fp@(20),%a1 ++ movel %a3,%d2 ++ andil #65535,%d2 ++ movel %a3,%d3 ++ clrw %d3 ++ swap %d3 ++ movel %a1,%d0 ++ andil #65535,%d0 ++ movel %a1,%d1 ++ clrw %d1 ++ swap %d1 ++ movel %d2,%d7 ++ mulsl %d0,%d7 ++ movel %d2,%d4 ++ mulsl %d1,%d4 ++ movel %d3,%d2 ++ mulsl %d0,%d2 ++ mulsl %d1,%d3 ++ movel %d7,%d0 ++ clrw %d0 ++ swap %d0 ++ addl %d0,%d4 ++ addl %d2,%d4 ++ cmpl %d4,%d2 ++ blss 1f ++ addil #65536,%d3 ++1: ++ movel %d4,%d0 ++ clrw %d0 ++ swap %d0 ++ movel %d3,%d5 ++ addl %d0,%d5 ++ movew %d4,%d6 ++ swap %d6 ++ movew %d7,%d6 ++ movel %d5,%d0 ++ movel %d6,%d1 ++ movel %a3,%d2 ++ movel %a0,%d3 ++ mulsl %d3,%d2 ++ movel %a2,%d3 ++ movel %a1,%d4 ++ mulsl %d4,%d3 ++ addl %d3,%d2 ++ movel %d2,%d0 ++ addl %d5,%d0 ++ moveml %sp@, %d2-%d7/%a2-%a3 ++ lea %sp@(32),%sp ++ unlk %fp ++ rts +--- /dev/null ++++ b/arch/m68k/coldfire/common/signal.c +@@ -0,0 +1,991 @@ ++/* ++ * linux/arch/m68k/kernel/signal.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Derived from m68k/kernel/signal.c and the original authors are credited ++ * there. ++ */ ++ ++#include <linux/sched.h> ++#include <linux/mm.h> ++#include <linux/kernel.h> ++#include <linux/signal.h> ++#include <linux/syscalls.h> ++#include <linux/errno.h> ++#include <linux/wait.h> ++#include <linux/ptrace.h> ++#include <linux/unistd.h> ++#include <linux/stddef.h> ++#include <linux/highuid.h> ++#include <linux/personality.h> ++#include <linux/tty.h> ++#include <linux/binfmts.h> ++ ++#include <asm/setup.h> ++#include <asm/uaccess.h> ++#include <asm/cf_pgtable.h> ++#include <asm/traps.h> ++#include <asm/ucontext.h> ++#include <asm/cacheflush.h> ++ ++#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) ++ ++asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs); ++ ++const int frame_extra_sizes[16] = { ++ [1] = -1, ++ [2] = -1, ++ [3] = -1, ++ [4] = 0, ++ [5] = 1, ++ [6] = 1, ++ [7] = 2, ++ [8] = 3, ++ [9] = -1, ++ [10] = -1, ++ [11] = -1, ++ [12] = -1, ++ [13] = -1, ++ [14] = -1, ++ [15] = -1, ++}; ++ ++/* ++ * Atomically swap in the new signal mask, and wait for a signal. ++ */ ++asmlinkage int do_sigsuspend(struct pt_regs *regs) ++{ ++ old_sigset_t mask = regs->d3; ++ sigset_t saveset; ++ ++ mask &= _BLOCKABLE; ++ spin_lock_irq(¤t->sighand->siglock); ++ saveset = current->blocked; ++ siginitset(¤t->blocked, mask); ++ recalc_sigpending(); ++ spin_unlock_irq(¤t->sighand->siglock); ++ ++ regs->d0 = -EINTR; ++ while (1) { ++ current->state = TASK_INTERRUPTIBLE; ++ schedule(); ++ if (do_signal(&saveset, regs)) ++ return -EINTR; ++ } ++} ++ ++asmlinkage int ++do_rt_sigsuspend(struct pt_regs *regs) ++{ ++ sigset_t __user *unewset = (sigset_t __user *)regs->d1; ++ size_t sigsetsize = (size_t)regs->d2; ++ sigset_t saveset, newset; ++ ++ /* XXX: Don't preclude handling different sized sigset_t's. */ ++ if (sigsetsize != sizeof(sigset_t)) ++ return -EINVAL; ++ ++ if (copy_from_user(&newset, unewset, sizeof(newset))) ++ return -EFAULT; ++ sigdelsetmask(&newset, ~_BLOCKABLE); ++ ++ spin_lock_irq(¤t->sighand->siglock); ++ saveset = current->blocked; ++ current->blocked = newset; ++ recalc_sigpending(); ++ spin_unlock_irq(¤t->sighand->siglock); ++ ++ regs->d0 = -EINTR; ++ while (1) { ++ current->state = TASK_INTERRUPTIBLE; ++ schedule(); ++ if (do_signal(&saveset, regs)) ++ return -EINTR; ++ } ++} ++ ++asmlinkage int ++sys_sigaction(int sig, const struct old_sigaction __user *act, ++ struct old_sigaction __user *oact) ++{ ++ struct k_sigaction new_ka, old_ka; ++ int ret; ++ ++ if (act) { ++ old_sigset_t mask; ++ if (!access_ok(VERIFY_READ, act, sizeof(*act)) || ++ __get_user(new_ka.sa.sa_handler, &act->sa_handler) || ++ __get_user(new_ka.sa.sa_restorer, &act->sa_restorer)) ++ return -EFAULT; ++ __get_user(new_ka.sa.sa_flags, &act->sa_flags); ++ __get_user(mask, &act->sa_mask); ++ siginitset(&new_ka.sa.sa_mask, mask); ++ } ++ ++ ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); ++ ++ if (!ret && oact) { ++ if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) || ++ __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || ++ __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer)) ++ return -EFAULT; ++ __put_user(old_ka.sa.sa_flags, &oact->sa_flags); ++ __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask); ++ } ++ ++ return ret; ++} ++ ++asmlinkage int ++sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss) ++{ ++ return do_sigaltstack(uss, uoss, rdusp()); ++} ++ ++ ++/* ++ * Do a signal return; undo the signal stack. ++ * ++ * Keep the return code on the stack quadword aligned! ++ * That makes the cache flush below easier. ++ */ ++ ++struct sigframe { ++ char __user *pretcode; ++ int sig; ++ int code; ++ struct sigcontext __user *psc; ++ char retcode[8]; ++ unsigned long extramask[_NSIG_WORDS-1]; ++ struct sigcontext sc; ++}; ++ ++struct rt_sigframe { ++ char __user *pretcode; ++ int sig; ++ struct siginfo __user *pinfo; ++ void __user *puc; ++ char retcode[8]; ++ struct siginfo info; ++ struct ucontext uc; ++}; ++ ++#define FPCONTEXT_SIZE 216 ++#define uc_fpstate uc_filler[0] ++#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4] ++#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1] ++ ++#ifdef CONFIG_FPU ++static unsigned char fpu_version; /* version num of fpu, set by setup_frame */ ++ ++static inline int restore_fpu_state(struct sigcontext *sc) ++{ ++ int err = 1; ++ ++ if (FPU_IS_EMU) { ++ /* restore registers */ ++ memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12); ++ memcpy(current->thread.fp, sc->sc_fpregs, 24); ++ return 0; ++ } ++ ++ if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { ++ /* Verify the frame format. */ ++ if (!CPU_IS_060 && (sc->sc_fpstate[0] != fpu_version)) ++ goto out; ++ if (CPU_IS_020_OR_030) { ++ if (m68k_fputype & FPU_68881 && ++ !(sc->sc_fpstate[1] == 0x18 || ++ sc->sc_fpstate[1] == 0xb4)) ++ goto out; ++ if (m68k_fputype & FPU_68882 && ++ !(sc->sc_fpstate[1] == 0x38 || ++ sc->sc_fpstate[1] == 0xd4)) ++ goto out; ++ } else if (CPU_IS_040) { ++ if (!(sc->sc_fpstate[1] == 0x00 || ++ sc->sc_fpstate[1] == 0x28 || ++ sc->sc_fpstate[1] == 0x60)) ++ goto out; ++ } else if (CPU_IS_060) { ++ if (!(sc->sc_fpstate[3] == 0x00 || ++ sc->sc_fpstate[3] == 0x60 || ++ sc->sc_fpstate[3] == 0xe0)) ++ goto out; ++ } else if (CPU_IS_CFV4E) { ++ pr_debug("restore v4e fpu state at %s\n", __func__); ++ } else ++ goto out; ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("fmovem %0,%/fp0-%/fp1\n\t" ++ QCHIP_RESTORE_DIRECTIVE ++ : /* no outputs */ ++ : "m" (sc->sc_fpregs[0][0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %0,%/fpcr" ++ : : "m" (sc->sc_fpcntl[0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %0,%/fpsr" ++ : : "m" (sc->sc_fpcntl[1]) ++ : "memory"); ++ __asm__ volatile ("fmovel %0,%/fpiar" ++ : : "m" (sc->sc_fpcntl[2]) ++ : "memory"); ++ ++#endif ++ } ++ ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("frestore %0\n\t" ++ QCHIP_RESTORE_DIRECTIVE : : "m" (*sc->sc_fpstate)); ++#endif ++ err = 0; ++ ++out: ++ return err; ++} ++ ++static inline int rt_restore_fpu_state(struct ucontext __user *uc) ++{ ++ unsigned char fpstate[FPCONTEXT_SIZE]; ++ int context_size = CPU_IS_060 ? 8 : 0; ++ fpregset_t fpregs; ++ int err = 1; ++ ++ if (FPU_IS_EMU) { ++ /* restore fpu control register */ ++ if (__copy_from_user(current->thread.fpcntl, ++ uc->uc_mcontext.fpregs.f_fpcntl, 12)) ++ goto out; ++ /* restore all other fpu register */ ++ if (__copy_from_user(current->thread.fp, ++ uc->uc_mcontext.fpregs.f_fpregs, 96)) ++ goto out; ++ return 0; ++ } ++ ++ if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate)) ++ goto out; ++ if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { ++ if (!CPU_IS_060) ++ context_size = fpstate[1]; ++ /* Verify the frame format. */ ++ if (!CPU_IS_060 && (fpstate[0] != fpu_version)) ++ goto out; ++ if (CPU_IS_020_OR_030) { ++ if (m68k_fputype & FPU_68881 && ++ !(context_size == 0x18 || context_size == 0xb4)) ++ goto out; ++ if (m68k_fputype & FPU_68882 && ++ !(context_size == 0x38 || context_size == 0xd4)) ++ goto out; ++ } else if (CPU_IS_040) { ++ if (!(context_size == 0x00 || ++ context_size == 0x28 || ++ context_size == 0x60)) ++ goto out; ++ } else if (CPU_IS_060) { ++ if (!(fpstate[3] == 0x00 || ++ fpstate[3] == 0x60 || ++ fpstate[3] == 0xe0)) ++ goto out; ++ } else if (CPU_IS_CFV4E) { ++ pr_debug("restore coldfire rt v4e fpu" ++ " state at %s\n", __func__); ++ } else ++ goto out; ++ if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs, ++ sizeof(fpregs))) ++ goto out; ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("fmovem %0,%/fp0-%/fp7\n\t" ++ QCHIP_RESTORE_DIRECTIVE ++ : /* no outputs */ ++ : "m" (fpregs.f_fpregs[0][0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %0,%/fpcr" ++ : : "m" (fpregs.f_fpcntl[0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %0,%/fpsr" ++ : : "m" (fpregs.f_fpcntl[1]) ++ : "memory"); ++ __asm__ volatile ("fmovel %0,%/fpiar" ++ : : "m" (fpregs.f_fpcntl[2]) ++ : "memory"); ++#endif ++ } ++ if (context_size && ++ __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1, ++ context_size)) ++ goto out; ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("frestore %0\n\t" ++ QCHIP_RESTORE_DIRECTIVE : : "m" (*fpstate)); ++#endif ++ err = 0; ++ ++out: ++ return err; ++} ++#endif ++ ++static inline int ++restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, ++ void __user *fp, int *pd0) ++{ ++ int fsize, formatvec; ++ struct sigcontext context; ++ int err = 0; ++ ++ /* get previous context */ ++ if (copy_from_user(&context, usc, sizeof(context))) ++ goto badframe; ++ ++ /* restore passed registers */ ++ regs->d1 = context.sc_d1; ++ regs->a0 = context.sc_a0; ++ regs->a1 = context.sc_a1; ++ regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff); ++ regs->pc = context.sc_pc; ++ regs->orig_d0 = -1; /* disable syscall checks */ ++ wrusp(context.sc_usp); ++ formatvec = context.sc_formatvec; ++ regs->format = formatvec >> 12; ++ regs->vector = formatvec & 0xfff; ++ ++#ifdef CONFIG_FPU ++ err = restore_fpu_state(&context); ++#endif ++ ++ fsize = frame_extra_sizes[regs->format]; ++ if (fsize < 0) { ++ /* ++ * user process trying to return with weird frame format ++ */ ++#ifdef DEBUG ++ printk(KERN_DEBUG "user process returning with weird \ ++ frame format\n"); ++#endif ++ goto badframe; ++ } ++ ++ /* OK. Make room on the supervisor stack for the extra junk, ++ * if necessary. ++ */ ++ ++ { ++ struct switch_stack *sw = (struct switch_stack *)regs - 1; ++ regs->d0 = context.sc_d0; ++#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) ++ __asm__ __volatile__ ++ (" movel %0,%/sp\n\t" ++ " bra ret_from_signal\n" ++ "4:\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 2b,4b\n" ++ ".previous" ++ : /* no outputs, it doesn't ever return */ ++ : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), ++ "n" (frame_offset), "a" (fp) ++ : "a0"); ++#undef frame_offset ++ /* ++ * If we ever get here an exception occurred while ++ * building the above stack-frame. ++ */ ++ goto badframe; ++ } ++ ++ *pd0 = context.sc_d0; ++ return err; ++ ++badframe: ++ return 1; ++} ++ ++static inline int ++rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, ++ struct ucontext __user *uc, int *pd0) ++{ ++ int fsize, temp; ++ greg_t __user *gregs = uc->uc_mcontext.gregs; ++ unsigned long usp; ++ int err; ++ ++ err = __get_user(temp, &uc->uc_mcontext.version); ++ if (temp != MCONTEXT_VERSION) ++ goto badframe; ++ /* restore passed registers */ ++ err |= __get_user(regs->d0, &gregs[0]); ++ err |= __get_user(regs->d1, &gregs[1]); ++ err |= __get_user(regs->d2, &gregs[2]); ++ err |= __get_user(regs->d3, &gregs[3]); ++ err |= __get_user(regs->d4, &gregs[4]); ++ err |= __get_user(regs->d5, &gregs[5]); ++ err |= __get_user(sw->d6, &gregs[6]); ++ err |= __get_user(sw->d7, &gregs[7]); ++ err |= __get_user(regs->a0, &gregs[8]); ++ err |= __get_user(regs->a1, &gregs[9]); ++ err |= __get_user(regs->a2, &gregs[10]); ++ err |= __get_user(sw->a3, &gregs[11]); ++ err |= __get_user(sw->a4, &gregs[12]); ++ err |= __get_user(sw->a5, &gregs[13]); ++ err |= __get_user(sw->a6, &gregs[14]); ++ err |= __get_user(usp, &gregs[15]); ++ wrusp(usp); ++ err |= __get_user(regs->pc, &gregs[16]); ++ err |= __get_user(temp, &gregs[17]); ++ regs->sr = (regs->sr & 0xff00) | (temp & 0xff); ++ regs->orig_d0 = -1; /* disable syscall checks */ ++ err |= __get_user(temp, &uc->uc_formatvec); ++ regs->format = temp >> 12; ++ regs->vector = temp & 0xfff; ++ ++#ifdef CONFIG_FPU ++ err |= rt_restore_fpu_state(uc); ++#endif ++ ++ if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT) ++ goto badframe; ++ ++ fsize = frame_extra_sizes[regs->format]; ++ if (fsize < 0) { ++ /* ++ * user process trying to return with weird frame format ++ */ ++#ifdef DEBUG ++ printk(KERN_DEBUG "user process returning with weird \ ++ frame format\n"); ++#endif ++ goto badframe; ++ } ++ ++ /* OK. Make room on the supervisor stack for the extra junk, ++ * if necessary. ++ */ ++ ++ { ++#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack)) ++ __asm__ __volatile__ ++ (" movel %0,%/sp\n\t" ++ " bra ret_from_signal\n" ++ "4:\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 2b,4b\n" ++ ".previous" ++ : /* no outputs, it doesn't ever return */ ++ : "a" (sw), "d" (fsize), "d" (frame_offset/4-1), ++ "n" (frame_offset), "a" (&uc->uc_extra) ++ : "a0"); ++#undef frame_offset ++ /* ++ * If we ever get here an exception occurred while ++ * building the above stack-frame. ++ */ ++ goto badframe; ++ } ++ ++ *pd0 = regs->d0; ++ return err; ++ ++badframe: ++ return 1; ++} ++ ++asmlinkage int do_sigreturn(unsigned long __unused) ++{ ++ struct switch_stack *sw = (struct switch_stack *) &__unused; ++ struct pt_regs *regs = (struct pt_regs *) (sw + 1); ++ unsigned long usp = rdusp(); ++ struct sigframe __user *frame = (struct sigframe __user *)(usp - 4); ++ sigset_t set; ++ int d0; ++ ++ if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) ++ goto badframe; ++ if (__get_user(set.sig[0], &frame->sc.sc_mask) || ++ (_NSIG_WORDS > 1 && ++ __copy_from_user(&set.sig[1], &frame->extramask, ++ sizeof(frame->extramask)))) ++ goto badframe; ++ ++ sigdelsetmask(&set, ~_BLOCKABLE); ++ spin_lock_irq(¤t->sighand->siglock); ++ current->blocked = set; ++ recalc_sigpending(); ++ spin_unlock_irq(¤t->sighand->siglock); ++ ++ if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0)) ++ goto badframe; ++ return d0; ++ ++badframe: ++ force_sig(SIGSEGV, current); ++ return 0; ++} ++ ++asmlinkage int do_rt_sigreturn(unsigned long __unused) ++{ ++ struct switch_stack *sw = (struct switch_stack *) &__unused; ++ struct pt_regs *regs = (struct pt_regs *) (sw + 1); ++ unsigned long usp = rdusp(); ++ struct rt_sigframe __user *frame = ++ (struct rt_sigframe __user *)(usp - 4); ++ sigset_t set; ++ int d0; ++ ++ if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) ++ goto badframe; ++ if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) ++ goto badframe; ++ ++ sigdelsetmask(&set, ~_BLOCKABLE); ++ spin_lock_irq(¤t->sighand->siglock); ++ current->blocked = set; ++ recalc_sigpending(); ++ spin_unlock_irq(¤t->sighand->siglock); ++ ++ if (rt_restore_ucontext(regs, sw, &frame->uc, &d0)) ++ goto badframe; ++ return d0; ++ ++badframe: ++ force_sig(SIGSEGV, current); ++ return 0; ++} ++ ++#ifdef CONFIG_FPU ++/* ++ * Set up a signal frame. ++ */ ++ ++static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs) ++{ ++ if (FPU_IS_EMU) { ++ /* save registers */ ++ memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12); ++ memcpy(sc->sc_fpregs, current->thread.fp, 24); ++ return; ++ } ++ ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("fsave %0\n\t" ++ QCHIP_RESTORE_DIRECTIVE ++ : : "m" (*sc->sc_fpstate) : "memory"); ++#endif ++ ++ if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) { ++ fpu_version = sc->sc_fpstate[0]; ++ if (CPU_IS_020_OR_030 && ++ regs->vector >= (VEC_FPBRUC * 4) && ++ regs->vector <= (VEC_FPNAN * 4)) { ++ /* Clear pending exception in 68882 idle frame */ ++ if (*(unsigned short *) sc->sc_fpstate == 0x1f38) ++ sc->sc_fpstate[0x38] |= 1 << 3; ++ } ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("fmovemd %/fp0-%/fp1,%0" ++ : : "m" (sc->sc_fpregs[0][0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %/fpcr,%0" ++ : : "m" (sc->sc_fpcntl[0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %/fpsr,%0" ++ : : "m" (sc->sc_fpcntl[1]) ++ : "memory"); ++ __asm__ volatile ("fmovel %/fpiar,%0" ++ : : "m" (sc->sc_fpcntl[2]) ++ : "memory"); ++ ++#endif ++ } ++} ++ ++static inline int rt_save_fpu_state(struct ucontext __user *uc, ++ struct pt_regs *regs) ++{ ++ unsigned char fpstate[FPCONTEXT_SIZE]; ++ int context_size = CPU_IS_060 ? 8 : 0; ++ int err = 0; ++ ++ if (FPU_IS_EMU) { ++ /* save fpu control register */ ++ err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl, ++ current->thread.fpcntl, 12); ++ /* save all other fpu register */ ++ err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs, ++ current->thread.fp, 96); ++ return err; ++ } ++ ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("fsave %0\n\t" ++ QCHIP_RESTORE_DIRECTIVE ++ : : "m" (*fpstate) : "memory"); ++#endif ++ err |= __put_user(*(long *)fpstate, (long *)&uc->uc_fpstate); ++ if (CPU_IS_060 ? fpstate[2] : fpstate[0]) { ++ fpregset_t fpregs; ++ if (!CPU_IS_060) ++ context_size = fpstate[1]; ++ fpu_version = fpstate[0]; ++#ifdef CONFIG_CFV4E ++ __asm__ volatile ("fmovemd %/fp0-%/fp7,%0" ++ : : "m" (fpregs.f_fpregs[0][0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %/fpcr,%0" ++ : : "m" (fpregs.f_fpcntl[0]) ++ : "memory"); ++ __asm__ volatile ("fmovel %/fpsr,%0" ++ : : "m" (fpregs.f_fpcntl[1]) ++ : "memory"); ++ __asm__ volatile ("fmovel %/fpiar,%0" ++ : : "m" (fpregs.f_fpcntl[2]) ++ : "memory"); ++#endif ++ err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs, ++ sizeof(fpregs)); ++ } ++ if (context_size) ++ err |= copy_to_user((long *)&uc->uc_fpstate + 1, fpstate + 4, ++ context_size); ++ return err; ++ ++ ++ return err; ++} ++#endif ++ ++static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs, ++ unsigned long mask) ++{ ++ sc->sc_mask = mask; ++ sc->sc_usp = rdusp(); ++ sc->sc_d0 = regs->d0; ++ sc->sc_d1 = regs->d1; ++ sc->sc_a0 = regs->a0; ++ sc->sc_a1 = regs->a1; ++ sc->sc_sr = regs->sr; ++ sc->sc_pc = regs->pc; ++ sc->sc_formatvec = regs->format << 12 | regs->vector; ++#ifdef CONFIG_FPU ++ save_fpu_state(sc, regs); ++#endif ++} ++ ++static inline int rt_setup_ucontext(struct ucontext __user *uc, ++ struct pt_regs *regs) ++{ ++ struct switch_stack *sw = (struct switch_stack *)regs - 1; ++ greg_t __user *gregs = uc->uc_mcontext.gregs; ++ int err = 0; ++ ++ err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); ++ err |= __put_user(regs->d0, &gregs[0]); ++ err |= __put_user(regs->d1, &gregs[1]); ++ err |= __put_user(regs->d2, &gregs[2]); ++ err |= __put_user(regs->d3, &gregs[3]); ++ err |= __put_user(regs->d4, &gregs[4]); ++ err |= __put_user(regs->d5, &gregs[5]); ++ err |= __put_user(sw->d6, &gregs[6]); ++ err |= __put_user(sw->d7, &gregs[7]); ++ err |= __put_user(regs->a0, &gregs[8]); ++ err |= __put_user(regs->a1, &gregs[9]); ++ err |= __put_user(regs->a2, &gregs[10]); ++ err |= __put_user(sw->a3, &gregs[11]); ++ err |= __put_user(sw->a4, &gregs[12]); ++ err |= __put_user(sw->a5, &gregs[13]); ++ err |= __put_user(sw->a6, &gregs[14]); ++ err |= __put_user(rdusp(), &gregs[15]); ++ err |= __put_user(regs->pc, &gregs[16]); ++ err |= __put_user(regs->sr, &gregs[17]); ++ err |= __put_user((regs->format << 12) | regs->vector, ++ &uc->uc_formatvec); ++#ifdef CONFIG_FPU ++ err |= rt_save_fpu_state(uc, regs); ++#endif ++ return err; ++} ++ ++static inline void push_cache(unsigned long vaddr) ++{ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ pgd_t *pdir; ++ pmd_t *pmdp; ++ pte_t *ptep; ++ unsigned long paddr; ++ ++ pdir = pgd_offset(current->mm, vaddr); ++ pmdp = pmd_offset(pdir, vaddr); ++ ptep = pte_offset_map(pmdp, vaddr); ++ paddr = ((pte_val(*ptep) & PAGE_MASK) | (vaddr & ~PAGE_MASK)); ++ cf_icache_flush_range(paddr, paddr + 8); ++#elif defined(CONFIG_M547X_8X) ++ flush_icache_range(vaddr, vaddr + 8); ++#endif ++} ++ ++static inline void __user * ++get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) ++{ ++ unsigned long usp; ++ ++ /* Default to using normal stack. */ ++ usp = rdusp(); ++ ++ /* This is the X/Open sanctioned signal stack switching. */ ++ if (ka->sa.sa_flags & SA_ONSTACK) { ++ if (!sas_ss_flags(usp)) ++ usp = current->sas_ss_sp + current->sas_ss_size; ++ } ++ return (void __user *)((usp - frame_size) & -8UL); ++} ++ ++static void setup_frame(int sig, struct k_sigaction *ka, ++ sigset_t *set, struct pt_regs *regs) ++{ ++ struct sigframe __user *frame; ++ int fsize = frame_extra_sizes[regs->format]; ++ struct sigcontext context; ++ int err = 0; ++ ++ if (fsize < 0) { ++#ifdef DEBUG ++ printk(KERN_DEBUG "setup_frame: Unknown frame format %#x\n", ++ regs->format); ++#endif ++ goto give_sigsegv; ++ } ++ ++ frame = get_sigframe(ka, regs, sizeof(*frame)); ++ ++ err |= __put_user((current_thread_info()->exec_domain ++ && current_thread_info()->exec_domain->signal_invmap ++ && sig < 32 ++ ? current_thread_info()->exec_domain->signal_invmap[sig] ++ : sig), ++ &frame->sig); ++ ++ err |= __put_user(regs->vector, &frame->code); ++ err |= __put_user(&frame->sc, &frame->psc); ++ ++ if (_NSIG_WORDS > 1) ++ err |= copy_to_user(frame->extramask, &set->sig[1], ++ sizeof(frame->extramask)); ++ ++ setup_sigcontext(&context, regs, set->sig[0]); ++ err |= copy_to_user(&frame->sc, &context, sizeof(context)); ++ ++ /* Set up to return from userspace. */ ++ err |= __put_user(frame->retcode, &frame->pretcode); ++ /* moveq #,d0; trap #0 */ ++ err |= __put_user(0x70004e40 + (__NR_sigreturn << 16), ++ (long __user *)(frame->retcode)); ++ ++ if (err) ++ goto give_sigsegv; ++ ++ push_cache((unsigned long) &frame->retcode); ++ ++ /* Set up registers for signal handler */ ++ wrusp((unsigned long) frame); ++ regs->pc = (unsigned long) ka->sa.sa_handler; ++ ++adjust_stack: ++ /* Prepare to skip over the extra stuff in the exception frame. */ ++ if (regs->stkadj) { ++ struct pt_regs *tregs = ++ (struct pt_regs *)((ulong)regs + regs->stkadj); ++#ifdef DEBUG ++ printk(KERN_DEBUG "Performing stackadjust=%04x\n", ++ regs->stkadj); ++#endif ++ /* This must be copied with decreasing addresses to ++ handle overlaps. */ ++ tregs->vector = 0; ++ tregs->format = 0; ++ tregs->pc = regs->pc; ++ tregs->sr = regs->sr; ++ } ++ return; ++ ++give_sigsegv: ++ force_sigsegv(sig, current); ++ goto adjust_stack; ++} ++ ++static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, ++ sigset_t *set, struct pt_regs *regs) ++{ ++ struct rt_sigframe __user *frame; ++ int fsize = frame_extra_sizes[regs->format]; ++ int err = 0; ++ ++ if (fsize < 0) { ++#ifdef DEBUG ++ printk(KERN_DEBUG "setup_frame: Unknown frame format %#x\n", ++ regs->format); ++#endif ++ goto give_sigsegv; ++ } ++ ++ frame = get_sigframe(ka, regs, sizeof(*frame)); ++ ++ if (fsize) { ++ err |= copy_to_user(&frame->uc.uc_extra, regs + 1, fsize); ++ regs->stkadj = fsize; ++ } ++ ++ err |= __put_user((current_thread_info()->exec_domain ++ && current_thread_info()->exec_domain->signal_invmap ++ && sig < 32 ++ ? current_thread_info()->exec_domain->signal_invmap[sig] ++ : sig), ++ &frame->sig); ++ err |= __put_user(&frame->info, &frame->pinfo); ++ err |= __put_user(&frame->uc, &frame->puc); ++ err |= copy_siginfo_to_user(&frame->info, info); ++ ++ /* Create the ucontext. */ ++ err |= __put_user(0, &frame->uc.uc_flags); ++ err |= __put_user(NULL, &frame->uc.uc_link); ++ err |= __put_user((void __user *)current->sas_ss_sp, ++ &frame->uc.uc_stack.ss_sp); ++ err |= __put_user(sas_ss_flags(rdusp()), ++ &frame->uc.uc_stack.ss_flags); ++ err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); ++ err |= rt_setup_ucontext(&frame->uc, regs); ++ err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); ++ ++ /* Set up to return from userspace. */ ++ err |= __put_user(frame->retcode, &frame->pretcode); ++ ++ /* movel #__NR_rt_sigreturn(0xAD),d0; trap #0 */ ++ err |= __put_user(0x203c0000, (long *)(frame->retcode + 0)); ++ err |= __put_user(0x00ad4e40, (long *)(frame->retcode + 4)); ++ ++ if (err) ++ goto give_sigsegv; ++ ++ push_cache((unsigned long) &frame->retcode); ++ ++ /* Set up registers for signal handler */ ++ wrusp((unsigned long) frame); ++ regs->pc = (unsigned long) ka->sa.sa_handler; ++ ++adjust_stack: ++ /* Prepare to skip over the extra stuff in the exception frame. */ ++ if (regs->stkadj) { ++ struct pt_regs *tregs = ++ (struct pt_regs *)((ulong)regs + regs->stkadj); ++#ifdef DEBUG ++ printk(KERN_DEBUG "Performing stackadjust=%04x\n", ++ regs->stkadj); ++#endif ++ /* This must be copied with decreasing addresses to ++ handle overlaps. */ ++ tregs->vector = 0; ++ tregs->format = 0; ++ tregs->pc = regs->pc; ++ tregs->sr = regs->sr; ++ } ++ return; ++ ++give_sigsegv: ++ force_sigsegv(sig, current); ++ goto adjust_stack; ++} ++ ++static inline void ++handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) ++{ ++ switch (regs->d0) { ++ case -ERESTARTNOHAND: ++ if (!has_handler) ++ goto do_restart; ++ regs->d0 = -EINTR; ++ break; ++ ++ case -ERESTARTSYS: ++ if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { ++ regs->d0 = -EINTR; ++ break; ++ } ++ /* fallthrough */ ++ case -ERESTARTNOINTR: ++do_restart: ++ regs->d0 = regs->orig_d0; ++ regs->pc -= 2; ++ break; ++ } ++} ++ ++/* ++ * OK, we're invoking a handler ++ */ ++static void ++handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info, ++ sigset_t *oldset, struct pt_regs *regs) ++{ ++ /* are we from a system call? */ ++ if (regs->orig_d0 >= 0) ++ /* If so, check system call restarting.. */ ++ handle_restart(regs, ka, 1); ++ ++ /* set up the stack frame */ ++ if (ka->sa.sa_flags & SA_SIGINFO) ++ setup_rt_frame(sig, ka, info, oldset, regs); ++ else ++ setup_frame(sig, ka, oldset, regs); ++ ++ if (ka->sa.sa_flags & SA_ONESHOT) ++ ka->sa.sa_handler = SIG_DFL; ++ ++ spin_lock_irq(¤t->sighand->siglock); ++ sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); ++ if (!(ka->sa.sa_flags & SA_NODEFER)) ++ sigaddset(¤t->blocked, sig); ++ recalc_sigpending(); ++ spin_unlock_irq(¤t->sighand->siglock); ++} ++ ++/* ++ * Note that 'init' is a special process: it doesn't get signals it doesn't ++ * want to handle. Thus you cannot kill init even with a SIGKILL even by ++ * mistake. ++ */ ++asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) ++{ ++ siginfo_t info; ++ struct k_sigaction ka; ++ int signr; ++ ++ current->thread.esp0 = (unsigned long) regs; ++ ++ if (!oldset) ++ oldset = ¤t->blocked; ++ ++ signr = get_signal_to_deliver(&info, &ka, regs, NULL); ++ if (signr > 0) { ++ /* Whee! Actually deliver the signal. */ ++ handle_signal(signr, &ka, &info, oldset, regs); ++ return 1; ++ } ++ ++ /* Did we come from a system call? */ ++ if (regs->orig_d0 >= 0) ++ /* Restart the system call - no handlers present */ ++ handle_restart(regs, NULL, 0); ++ ++ return 0; ++} +--- /dev/null ++++ b/arch/m68k/coldfire/common/traps.c +@@ -0,0 +1,457 @@ ++/* ++ * linux/arch/m68knommu/kernel/traps.c ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++/* ++ * Sets up all exception vectors ++ */ ++#include <linux/sched.h> ++#include <linux/signal.h> ++#include <linux/kernel.h> ++#include <linux/mm.h> ++#include <linux/module.h> ++#include <linux/types.h> ++#include <linux/a.out.h> ++#include <linux/user.h> ++#include <linux/string.h> ++#include <linux/linkage.h> ++#include <linux/init.h> ++#include <linux/ptrace.h> ++#include <linux/kallsyms.h> ++ ++#include <asm/setup.h> ++#include <asm/fpu.h> ++#include <asm/system.h> ++#include <asm/uaccess.h> ++#include <asm/traps.h> ++#include <asm/pgtable.h> ++#include <asm/machdep.h> ++#include <asm/siginfo.h> ++ ++static char const * const vec_names[] = { ++ "RESET SP", "RESET PC", "BUS ERROR", "ADDRESS ERROR", ++ "ILLEGAL INSTRUCTION", "ZERO DIVIDE", "CHK", "TRAPcc", ++ "PRIVILEGE VIOLATION", "TRACE", "LINE 1010", "LINE 1111", ++ "UNASSIGNED RESERVED 12", "COPROCESSOR PROTOCOL VIOLATION", ++ "FORMAT ERROR", "UNINITIALIZED INTERRUPT", ++ "UNASSIGNED RESERVED 16", "UNASSIGNED RESERVED 17", ++ "UNASSIGNED RESERVED 18", "UNASSIGNED RESERVED 19", ++ "UNASSIGNED RESERVED 20", "UNASSIGNED RESERVED 21", ++ "UNASSIGNED RESERVED 22", "UNASSIGNED RESERVED 23", ++ "SPURIOUS INTERRUPT", "LEVEL 1 INT", "LEVEL 2 INT", "LEVEL 3 INT", ++ "LEVEL 4 INT", "LEVEL 5 INT", "LEVEL 6 INT", "LEVEL 7 INT", ++ "SYSCALL", "TRAP #1", "TRAP #2", "TRAP #3", ++ "TRAP #4", "TRAP #5", "TRAP #6", "TRAP #7", ++ "TRAP #8", "TRAP #9", "TRAP #10", "TRAP #11", ++ "TRAP #12", "TRAP #13", "TRAP #14", "TRAP #15", ++ "FPCP BSUN", "FPCP INEXACT", "FPCP DIV BY 0", "FPCP UNDERFLOW", ++ "FPCP OPERAND ERROR", "FPCP OVERFLOW", "FPCP SNAN", ++ "FPCP UNSUPPORTED OPERATION", ++ "MMU CONFIGURATION ERROR" ++}; ++ ++asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, ++ unsigned long error_code); ++asmlinkage void trap_c(struct frame *fp); ++extern void __init coldfire_trap_init(void); ++ ++void __init trap_init(void) ++{ ++ coldfire_trap_init(); ++} ++ ++/* The following table converts the FS encoding of a ColdFire ++ exception stack frame into the error_code value needed by ++ do_fault. */ ++ ++static const unsigned char fs_err_code[] = { ++ 0, /* 0000 */ ++ 0, /* 0001 */ ++ 0, /* 0010 */ ++ 0, /* 0011 */ ++ 1, /* 0100 */ ++ 0, /* 0101 */ ++ 0, /* 0110 */ ++ 0, /* 0111 */ ++ 2, /* 1000 */ ++ 3, /* 1001 */ ++ 2, /* 1010 */ ++ 0, /* 1011 */ ++ 1, /* 1100 */ ++ 1, /* 1101 */ ++ 0, /* 1110 */ ++ 0 /* 1111 */ ++}; ++ ++#ifdef DEBUG ++static const char *fs_err_msg[16] = { ++ "Normal", ++ "Reserved", ++ "Interrupt during debug service routine", ++ "Reserved", ++ "X Protection", ++ "TLB X miss (opword)", ++ "TLB X miss (ext. word)", ++ "IFP in emulator mode", ++ "W Protection", ++ "Write error", ++ "TLB W miss", ++ "Reserved", ++ "R Protection", ++ "R/RMW Protection", ++ "TLB R miss", ++ "OEP in emulator mode", ++}; ++#endif ++ ++static inline void access_errorCF(struct frame *fp) ++{ ++ unsigned long int mmusr, complainingAddress; ++ unsigned int err_code, fs; ++ int need_page_fault; ++ ++ mmusr = fp->ptregs.mmusr; ++ complainingAddress = fp->ptregs.mmuar; ++#ifdef DEBUG ++ printk(KERN_DEBUG "pc %#lx, mmusr %#lx, complainingAddress %#lx\n", \ ++ fp->ptregs.pc, mmusr, complainingAddress); ++#endif ++ ++ /* ++ * error_code: ++ * bit 0 == 0 means no page found, 1 means protection fault ++ * bit 1 == 0 means read, 1 means write ++ */ ++ ++ fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1; ++ switch (fs) { ++ case 5: /* 0101 TLB opword X miss */ ++ need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 0); ++ complainingAddress = fp->ptregs.pc; ++ break; ++ case 6: /* 0110 TLB extension word X miss */ ++ need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 1); ++ complainingAddress = fp->ptregs.pc + sizeof(long); ++ break; ++ case 10: /* 1010 TLB W miss */ ++ need_page_fault = cf_tlb_miss(&fp->ptregs, 1, 1, 0); ++ break; ++ case 14: /* 1110 TLB R miss */ ++ need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 1, 0); ++ break; ++ default: ++ /* 0000 Normal */ ++ /* 0001 Reserved */ ++ /* 0010 Interrupt during debug service routine */ ++ /* 0011 Reserved */ ++ /* 0100 X Protection */ ++ /* 0111 IFP in emulator mode */ ++ /* 1000 W Protection*/ ++ /* 1001 Write error*/ ++ /* 1011 Reserved*/ ++ /* 1100 R Protection*/ ++ /* 1101 R Protection*/ ++ /* 1111 OEP in emulator mode*/ ++ need_page_fault = 1; ++ break; ++ } ++ ++ if (need_page_fault) { ++ err_code = fs_err_code[fs]; ++ if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */ ++ err_code |= 2; /* bit1 - write, bit0 - protection */ ++ do_page_fault(&fp->ptregs, complainingAddress, err_code); ++ } ++} ++ ++void die_if_kernel(char *str, struct pt_regs *fp, int nr) ++{ ++ if (!(fp->sr & PS_S)) ++ return; ++ ++ console_verbose(); ++ printk(KERN_EMERG "%s: %08x\n", str, nr); ++ printk(KERN_EMERG "PC: [<%08lx>]", fp->pc); ++ print_symbol(" %s", fp->pc); ++ printk(KERN_EMERG "\nSR: %04x SP: %p a2: %08lx\n", ++ fp->sr, fp, fp->a2); ++ printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", ++ fp->d0, fp->d1, fp->d2, fp->d3); ++ printk(KERN_EMERG "d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n", ++ fp->d4, fp->d5, fp->a0, fp->a1); ++ ++ printk(KERN_EMERG "Process %s (pid: %d, stackpage=%08lx)\n", ++ current->comm, current->pid, PAGE_SIZE+(unsigned long)current); ++ show_stack(NULL, (unsigned long *)fp); ++ do_exit(SIGSEGV); ++} ++ ++asmlinkage void buserr_c(struct frame *fp) ++{ ++ unsigned int fs; ++ ++ /* Only set esp0 if coming from user mode */ ++ if (user_mode(&fp->ptregs)) ++ current->thread.esp0 = (unsigned long) fp; ++ ++ fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1; ++#if defined(DEBUG) ++ printk(KERN_DEBUG "*** Bus Error *** (%x)%s\n", fs, ++ fs_err_msg[fs & 0xf]); ++#endif ++ switch (fs) { ++ case 0x5: ++ case 0x6: ++ case 0x7: ++ case 0x9: ++ case 0xa: ++ case 0xd: ++ case 0xe: ++ case 0xf: ++ access_errorCF(fp); ++ break; ++ default: ++ die_if_kernel("bad frame format", &fp->ptregs, 0); ++#if defined(DEBUG) ++ printk(KERN_DEBUG "Unknown SIGSEGV - 4\n"); ++#endif ++ force_sig(SIGSEGV, current); ++ } ++} ++ ++void show_trace(unsigned long *stack) ++{ ++ unsigned long *endstack; ++ unsigned long addr; ++ int i; ++ ++ printk(KERN_INFO "Call Trace:"); ++ addr = (unsigned long)stack + THREAD_SIZE - 1; ++ endstack = (unsigned long *)(addr & -THREAD_SIZE); ++ i = 0; ++ while (stack + 1 <= endstack) { ++ addr = *stack++; ++ /* ++ * If the address is either in the text segment of the ++ * kernel, or in the region which contains vmalloc'ed ++ * memory, it *may* be the address of a calling ++ * routine; if so, print it so that someone tracing ++ * down the cause of the crash will be able to figure ++ * out the call path that was taken. ++ */ ++ if (__kernel_text_address(addr)) { ++#ifndef CONFIG_KALLSYMS ++ if (i % 5 == 0) ++ printk("\n "); ++#endif ++ printk(" [<%08lx>] %pS\n", addr, (void *)addr); ++ i++; ++ } ++ } ++ printk(KERN_INFO "\n"); ++} ++ ++int kstack_depth_to_print = 48; ++void show_stack(struct task_struct *task, unsigned long *stack) ++{ ++ unsigned long *p; ++ unsigned long *endstack; ++ int i; ++ ++ if (!stack) { ++ if (task) ++ stack = (unsigned long *)task->thread.esp0; ++ else ++ stack = (unsigned long *)&stack; ++ } ++ endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) ++ & -THREAD_SIZE); ++ ++ printk(KERN_INFO "Stack from %08lx:", (unsigned long)stack); ++ p = stack; ++ for (i = 0; i < kstack_depth_to_print; i++) { ++ if (p + 1 > endstack) ++ break; ++ if (i % 8 == 0) ++ printk("\n "); ++ printk(" %08lx", *p++); ++ } ++ printk("\n"); ++ show_trace(stack); ++} ++ ++void bad_super_trap(struct frame *fp) ++{ ++ console_verbose(); ++ if (fp->ptregs.vector < sizeof(vec_names)/sizeof(vec_names[0])) ++ printk(KERN_WARNING "*** %s *** FORMAT=%X\n", ++ vec_names[fp->ptregs.vector], ++ fp->ptregs.format); ++ else ++ printk(KERN_WARNING "*** Exception %d *** FORMAT=%X\n", ++ fp->ptregs.vector, ++ fp->ptregs.format); ++ printk(KERN_WARNING "Current process id is %d\n", current->pid); ++ die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0); ++} ++ ++asmlinkage void trap_c(struct frame *fp) ++{ ++ int sig; ++ siginfo_t info; ++ ++ if (fp->ptregs.sr & PS_S) { ++ if (fp->ptregs.vector == VEC_TRACE) { ++ /* traced a trapping instruction */ ++ current->ptrace |= PT_DTRACE; ++ } else ++ bad_super_trap(fp); ++ return; ++ } ++ ++ /* send the appropriate signal to the user program */ ++ switch (fp->ptregs.vector) { ++ case VEC_ADDRERR: ++ info.si_code = BUS_ADRALN; ++ sig = SIGBUS; ++ break; ++ case VEC_ILLEGAL: ++ case VEC_LINE10: ++ case VEC_LINE11: ++ info.si_code = ILL_ILLOPC; ++ sig = SIGILL; ++ break; ++ case VEC_PRIV: ++ info.si_code = ILL_PRVOPC; ++ sig = SIGILL; ++ break; ++ case VEC_COPROC: ++ info.si_code = ILL_COPROC; ++ sig = SIGILL; ++ break; ++ case VEC_TRAP1: /* gdbserver breakpoint */ ++ fp->ptregs.pc -= 2; ++ info.si_code = TRAP_TRACE; ++ sig = SIGTRAP; ++ break; ++ case VEC_TRAP2: ++ case VEC_TRAP3: ++ case VEC_TRAP4: ++ case VEC_TRAP5: ++ case VEC_TRAP6: ++ case VEC_TRAP7: ++ case VEC_TRAP8: ++ case VEC_TRAP9: ++ case VEC_TRAP10: ++ case VEC_TRAP11: ++ case VEC_TRAP12: ++ case VEC_TRAP13: ++ case VEC_TRAP14: ++ info.si_code = ILL_ILLTRP; ++ sig = SIGILL; ++ break; ++ case VEC_FPBRUC: ++ case VEC_FPOE: ++ case VEC_FPNAN: ++ info.si_code = FPE_FLTINV; ++ sig = SIGFPE; ++ break; ++ case VEC_FPIR: ++ info.si_code = FPE_FLTRES; ++ sig = SIGFPE; ++ break; ++ case VEC_FPDIVZ: ++ info.si_code = FPE_FLTDIV; ++ sig = SIGFPE; ++ break; ++ case VEC_FPUNDER: ++ info.si_code = FPE_FLTUND; ++ sig = SIGFPE; ++ break; ++ case VEC_FPOVER: ++ info.si_code = FPE_FLTOVF; ++ sig = SIGFPE; ++ break; ++ case VEC_ZERODIV: ++ info.si_code = FPE_INTDIV; ++ sig = SIGFPE; ++ break; ++ case VEC_CHK: ++ case VEC_TRAP: ++ info.si_code = FPE_INTOVF; ++ sig = SIGFPE; ++ break; ++ case VEC_TRACE: /* ptrace single step */ ++ info.si_code = TRAP_TRACE; ++ sig = SIGTRAP; ++ break; ++ case VEC_TRAP15: /* breakpoint */ ++ info.si_code = TRAP_BRKPT; ++ sig = SIGTRAP; ++ break; ++ default: ++ info.si_code = ILL_ILLOPC; ++ sig = SIGILL; ++ break; ++ } ++ info.si_signo = sig; ++ info.si_errno = 0; ++ switch (fp->ptregs.format) { ++ default: ++ info.si_addr = (void *) fp->ptregs.pc; ++ break; ++ case 2: ++ info.si_addr = (void *) fp->un.fmt2.iaddr; ++ break; ++ case 7: ++ info.si_addr = (void *) fp->un.fmt7.effaddr; ++ break; ++ case 9: ++ info.si_addr = (void *) fp->un.fmt9.iaddr; ++ break; ++ case 10: ++ info.si_addr = (void *) fp->un.fmta.daddr; ++ break; ++ case 11: ++ info.si_addr = (void *) fp->un.fmtb.daddr; ++ break; ++ } ++ force_sig_info(sig, &info, current); ++} ++ ++asmlinkage void set_esp0(unsigned long ssp) ++{ ++ current->thread.esp0 = ssp; ++} ++ ++/* ++ * The architecture-independent backtrace generator ++ */ ++void dump_stack(void) ++{ ++ unsigned long stack; ++ ++ show_stack(current, &stack); ++} ++EXPORT_SYMBOL(dump_stack); ++ ++#ifdef CONFIG_M68KFPU_EMU ++asmlinkage void fpemu_signal(int signal, int code, void *addr) ++{ ++ siginfo_t info; ++ ++ info.si_signo = signal; ++ info.si_errno = 0; ++ info.si_code = code; ++ info.si_addr = addr; ++ force_sig_info(signal, &info, current); ++} ++#endif +--- a/arch/m68k/include/asm/atomic.h ++++ b/arch/m68k/include/asm/atomic.h +@@ -1,3 +1,11 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ + #ifndef __ARCH_M68K_ATOMIC__ + #define __ARCH_M68K_ATOMIC__ + +@@ -30,12 +38,20 @@ + + static inline void atomic_add(int i, atomic_t *v) + { +- __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI (i)); ++#ifndef CONFIG_COLDFIRE ++ __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI(i)); ++#else ++ __asm__ __volatile__("addl %1,%0" : "=m" (*v) : ASM_DI(i), "m" (*v)); ++#endif + } + + static inline void atomic_sub(int i, atomic_t *v) + { +- __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI (i)); ++#ifndef CONFIG_COLDFIRE ++ __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI(i)); ++#else ++ __asm__ __volatile__("subl %1,%0" : "=m" (*v) : ASM_DI(i), "m" (*v)); ++#endif + } + + static inline void atomic_inc(atomic_t *v) +@@ -55,6 +71,14 @@ static inline int atomic_dec_and_test(at + return c != 0; + } + ++static inline int atomic_dec_and_test_lt(volatile atomic_t *v) ++{ ++ char c; ++ __asm__ __volatile__("subql #1,%1; slt %0" : "=d" (c), "=m" (*v) ++ : "m" (*v)); ++ return c != 0 ; ++} ++ + static inline int atomic_inc_and_test(atomic_t *v) + { + char c; +@@ -167,9 +191,14 @@ static inline int atomic_sub_and_test(in + static inline int atomic_add_negative(int i, atomic_t *v) + { + char c; ++#ifndef CONFIG_COLDFIRE + __asm__ __volatile__("addl %2,%1; smi %0" + : "=d" (c), "+m" (*v) + : "id" (i)); ++#else ++ __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "=m" (*v) ++ : "d" (i) , "m" (*v)); ++#endif + return c != 0; + } + +--- a/arch/m68k/include/asm/bitops_mm.h ++++ b/arch/m68k/include/asm/bitops_mm.h +@@ -1,12 +1,18 @@ +-#ifndef _M68K_BITOPS_H +-#define _M68K_BITOPS_H + /* + * Copyright 1992, Linus Torvalds. + * ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ ++#ifndef _M68K_BITOPS_H ++#define _M68K_BITOPS_H ++ ++#ifdef CONFIG_COLDFIRE ++#include <asm/cf_bitops.h> ++#else + + #ifndef _LINUX_BITOPS_H + #error only <linux/bitops.h> can be included directly +@@ -463,4 +469,6 @@ static inline unsigned long generic_find + + #endif /* __KERNEL__ */ + ++#endif /* CONFIG_COLDFIRE */ ++ + #endif /* _M68K_BITOPS_H */ +--- a/arch/m68k/include/asm/bootinfo.h ++++ b/arch/m68k/include/asm/bootinfo.h +@@ -2,6 +2,7 @@ + ** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure + ** + ** Copyright 1992 by Greg Harp ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. + ** + ** This file is subject to the terms and conditions of the GNU General Public + ** License. See the file COPYING in the main directory of this archive +@@ -24,6 +25,47 @@ + #ifndef _M68K_BOOTINFO_H + #define _M68K_BOOTINFO_H + ++#ifndef __ASSEMBLY__ ++/* ++ * UBoot Support ++ * ++ * bd_info structure from uboot1.3.2/arch/m68k/include/asm/u-boot.h ++ */ ++struct bd_info { ++ unsigned long bi_memstart; /* start of DRAM memory */ ++ unsigned long bi_memsize; /* size of DRAM memory in bytes */ ++ unsigned long bi_flashstart; /* start of FLASH memory */ ++ unsigned long bi_flashsize; /* size of FLASH memory */ ++ unsigned long bi_flashoffset; /* reserved area for startup monitor */ ++ unsigned long bi_sramstart; /* start of SRAM memory */ ++ unsigned long bi_sramsize; /* size of SRAM memory */ ++ unsigned long bi_mbar_base; /* base of internal registers */ ++ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ ++ unsigned long bi_boot_params; /* where this board expects params */ ++ unsigned long bi_ip_addr; /* IP Address */ ++ unsigned char bi_enet0addr[6]; /* Ethernet 0 mac address */ ++ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ ++ unsigned long bi_intfreq; /* Internal Freq, in MHz */ ++ unsigned long bi_busfreq; /* Bus Freq, in MHz */ ++#ifdef UBOOT_EXTRA_CLOCK ++ unsigned long bi_inpfreq; /* input Freq in MHz */ ++ unsigned long bi_vcofreq; /* vco Freq in MHz */ ++ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ ++#endif ++ unsigned long bi_baudrate; /* Console Baudrate */ ++ unsigned char bi_enet1addr[6]; /* eth1 mac address */ ++ unsigned char bi_enet2addr[6]; /* eth2 mac address */ ++ unsigned char bi_enet3addr[6]; /* eth3 mac address */ ++}; ++ ++struct uboot_record { ++ struct bd_info *bdi; ++ unsigned long initrd_start; ++ unsigned long initrd_end; ++ unsigned long cmd_line_start; ++ unsigned long cmd_line_stop; ++}; ++#endif /* __ASSEMBLY__ */ + + /* + * Bootinfo definitions +--- a/arch/m68k/include/asm/cacheflush_mm.h ++++ b/arch/m68k/include/asm/cacheflush_mm.h +@@ -1,3 +1,11 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ + #ifndef _M68K_CACHEFLUSH_H + #define _M68K_CACHEFLUSH_H + +@@ -6,6 +14,10 @@ + /* cache code */ + #define FLUSH_I_AND_D (0x00000808) + #define FLUSH_I (0x00000008) ++#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 ++#ifdef CONFIG_COLDFIRE ++#include <asm/cf_cacheflush.h> ++#else /* !CONFIG_COLDFIRE */ + + /* + * Cache handling functions +@@ -128,7 +140,6 @@ static inline void __flush_page_to_ram(v + } + } + +-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 + #define flush_dcache_page(page) __flush_page_to_ram(page_address(page)) + #define flush_dcache_mmap_lock(mapping) do { } while (0) + #define flush_dcache_mmap_unlock(mapping) do { } while (0) +@@ -154,4 +165,5 @@ static inline void copy_from_user_page(s + memcpy(dst, src, len); + } + ++#endif /* !CONFIG_COLDFIRE */ + #endif /* _M68K_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf-sram.h +@@ -0,0 +1,21 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Lanttor.Guo@freescale.com ++ * ++ * Providing on-chip SRAM allocation and free APIs to kernel ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef CF_SRAM_H ++#define CF_SRAM_H ++ ++extern int declare_sram_pool(void *start, size_t size); ++ ++extern void *sram_alloc(size_t len); ++extern void sram_free(void *addr, size_t len); ++ ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/cf_bitops.h +@@ -0,0 +1,443 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++#ifndef __CF_BITOPS__ ++#define __CF_BITOPS__ ++ ++#ifndef _LINUX_BITOPS_H ++#error only <linux/bitops.h> can be included directly ++#endif ++ ++#include <linux/compiler.h> ++ ++#define test_and_set_bit(nr, vaddr) \ ++ (__builtin_constant_p(nr) ? \ ++ __constant_coldfire_test_and_set_bit(nr, vaddr) : \ ++ __generic_coldfire_test_and_set_bit(nr, vaddr)) ++ ++static inline int __constant_coldfire_test_and_set_bit(int nr, ++ volatile void *vaddr) ++{ ++ char retval; ++ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; ++ __asm__ __volatile__ ("bset %2,(%4); sne %0" ++ : "=d" (retval), "=m" (*p) ++ : "di" (nr & 7), "m" (*p), "a" (p)); ++ return retval; ++} ++ ++static inline int __generic_coldfire_test_and_set_bit(int nr, ++ volatile void *vaddr) ++{ ++ char retval; ++ ++ __asm__ __volatile__ ("bset %2,%1; sne %0" ++ : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) ++ : "d" (nr) ++ : "memory"); ++ return retval; ++} ++#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr) ++ ++#define set_bit(nr, vaddr) \ ++ (__builtin_constant_p(nr) ? \ ++ __constant_coldfire_set_bit(nr, vaddr) : \ ++ __generic_coldfire_set_bit(nr, vaddr)) ++ ++static inline void __constant_coldfire_set_bit(int nr, ++ volatile void *vaddr) ++{ ++ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; ++ __asm__ __volatile__ ("bset %1,(%3)" ++ : "=m" (*p) : "di" (nr & 7), "m" (*p), "a" (p)); ++} ++ ++static inline void __generic_coldfire_set_bit(int nr, ++ volatile void *vaddr) ++{ ++ __asm__ __volatile__ ("bset %1,%0" ++ : "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) ++ : "d" (nr) ++ : "memory"); ++} ++#define __set_bit(nr, vaddr) set_bit(nr, vaddr) ++ ++#define test_and_clear_bit(nr, vaddr) \ ++ (__builtin_constant_p(nr) ? \ ++ __constant_coldfire_test_and_clear_bit(nr, vaddr) : \ ++ __generic_coldfire_test_and_clear_bit(nr, vaddr)) ++ ++static inline int __constant_coldfire_test_and_clear_bit(int nr, ++ volatile void *vaddr) ++{ ++ char retval; ++ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; ++ ++ __asm__ __volatile__ ("bclr %2,(%4); sne %0" ++ : "=d" (retval), "=m" (*p) ++ : "id" (nr & 7), "m" (*p), "a" (p)); ++ ++ return retval; ++} ++ ++static inline int __generic_coldfire_test_and_clear_bit(int nr, ++ volatile void *vaddr) ++{ ++ char retval; ++ ++ __asm__ __volatile__ ("bclr %2,%1; sne %0" ++ : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) ++ : "d" (nr & 7) ++ : "memory"); ++ ++ return retval; ++} ++#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr) ++ ++/* ++ * clear_bit() doesn't provide any barrier for the compiler. ++ */ ++#define smp_mb__before_clear_bit() barrier() ++#define smp_mb__after_clear_bit() barrier() ++ ++#define clear_bit(nr, vaddr) \ ++ (__builtin_constant_p(nr) ? \ ++ __constant_coldfire_clear_bit(nr, vaddr) : \ ++ __generic_coldfire_clear_bit(nr, vaddr)) ++ ++static inline void __constant_coldfire_clear_bit(int nr, ++ volatile void *vaddr) ++{ ++ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; ++ __asm__ __volatile__ ("bclr %1,(%3)" ++ : "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p)); ++} ++ ++static inline void __generic_coldfire_clear_bit(int nr, ++ volatile void *vaddr) ++{ ++ __asm__ __volatile__ ("bclr %1,%0" ++ : "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) ++ : "d" (nr) ++ : "memory"); ++} ++#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr) ++ ++#define test_and_change_bit(nr, vaddr) \ ++ (__builtin_constant_p(nr) ? \ ++ __constant_coldfire_test_and_change_bit(nr, vaddr) : \ ++ __generic_coldfire_test_and_change_bit(nr, vaddr)) ++ ++static inline int __constant_coldfire_test_and_change_bit(int nr, ++ volatile void *vaddr) ++{ ++ char retval; ++ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; ++ ++ __asm__ __volatile__ ("bchg %2,(%4); sne %0" ++ : "=d" (retval), "=m" (*p) ++ : "id" (nr & 7), "m" (*p), "a" (p)); ++ ++ return retval; ++} ++ ++static inline int __generic_coldfire_test_and_change_bit(int nr, ++ volatile void *vaddr) ++{ ++ char retval; ++ ++ __asm__ __volatile__ ("bchg %2,%1; sne %0" ++ : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) ++ : "id" (nr) ++ : "memory"); ++ ++ return retval; ++} ++#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr) ++#define __change_bit(nr, vaddr) change_bit(nr, vaddr) ++ ++#define change_bit(nr, vaddr) \ ++ (__builtin_constant_p(nr) ? \ ++ __constant_coldfire_change_bit(nr, vaddr) : \ ++ __generic_coldfire_change_bit(nr, vaddr)) ++ ++static inline void __constant_coldfire_change_bit(int nr, ++ volatile void *vaddr) ++{ ++ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; ++ __asm__ __volatile__ ("bchg %1,(%3)" ++ : "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p)); ++} ++ ++static inline void __generic_coldfire_change_bit(int nr, ++ volatile void *vaddr) ++{ ++ __asm__ __volatile__ ("bchg %1,%0" ++ : "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) ++ : "d" (nr) ++ : "memory"); ++} ++ ++static inline int test_bit(int nr, const unsigned long *vaddr) ++{ ++ return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0; ++} ++ ++static inline unsigned long ffz(unsigned long word) ++{ ++ unsigned long result = 0; ++ ++ while (word & 1) { ++ result++; ++ word >>= 1; ++ } ++ return result; ++} ++ ++/* find_next_zero_bit() finds the first zero bit in a bit string of length ++ * 'size' bits, starting the search at bit 'offset'. This is largely based ++ * on Linus's ALPHA routines. ++ */ ++static inline unsigned long find_next_zero_bit(void *addr, ++ unsigned long size, unsigned long offset) ++{ ++ unsigned long *p = ((unsigned long *) addr) + (offset >> 5); ++ unsigned long result = offset & ~31UL; ++ unsigned long tmp; ++ ++ if (offset >= size) ++ return size; ++ size -= result; ++ offset &= 31UL; ++ if (offset) { ++ tmp = *(p++); ++ tmp |= ~0UL >> (32-offset); ++ if (size < 32) ++ goto found_first; ++ if (~tmp) ++ goto found_middle; ++ size -= 32; ++ result += 32; ++ } ++ while (size & ~31UL) { ++ tmp = *(p++); ++ if (~tmp) ++ goto found_middle; ++ result += 32; ++ size -= 32; ++ } ++ if (!size) ++ return result; ++ tmp = *p; ++ ++found_first: ++ tmp |= ~0UL >> size; ++found_middle: ++ return result + ffz(tmp); ++} ++ ++#define find_first_zero_bit(addr, size) find_next_zero_bit(((void *)addr), \ ++ (size), 0) ++ ++/* Ported from included/linux/bitops.h */ ++static inline int ffs(int x) ++{ ++ int r = 1; ++ ++ if (!x) ++ return 0; ++ if (!(x & 0xffff)) { ++ x >>= 16; ++ r += 16; ++ } ++ if (!(x & 0xff)) { ++ x >>= 8; ++ r += 8; ++ } ++ if (!(x & 0xf)) { ++ x >>= 4; ++ r += 4; ++ } ++ if (!(x & 3)) { ++ x >>= 2; ++ r += 2; ++ } ++ if (!(x & 1)) { ++ x >>= 1; ++ r += 1; ++ } ++ return r; ++} ++#define __ffs(x) (ffs(x) - 1) ++ ++/* find_next_bit - find the next set bit in a memory region ++ * (from asm-ppc/bitops.h) ++ */ ++static inline unsigned long find_next_bit(const unsigned long *addr, ++ unsigned long size, unsigned long offset) ++{ ++ unsigned int *p = ((unsigned int *) addr) + (offset >> 5); ++ unsigned int result = offset & ~31UL; ++ unsigned int tmp; ++ ++ if (offset >= size) ++ return size; ++ size -= result; ++ offset &= 31UL; ++ if (offset) { ++ tmp = *p++; ++ tmp &= ~0UL << offset; ++ if (size < 32) ++ goto found_first; ++ if (tmp) ++ goto found_middle; ++ size -= 32; ++ result += 32; ++ } ++ while (size >= 32) { ++ tmp = *p++; ++ if (tmp != 0) ++ goto found_middle; ++ result += 32; ++ size -= 32; ++ } ++ if (!size) ++ return result; ++ tmp = *p; ++ ++found_first: ++ tmp &= ~0UL >> (32 - size); ++ if (tmp == 0UL) /* Are any bits set? */ ++ return result + size; /* Nope. */ ++found_middle: ++ return result + __ffs(tmp); ++} ++ ++#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) ++ ++#ifdef __KERNEL__ ++ ++/* Ported from include/linux/bitops.h */ ++static inline int fls(int x) ++{ ++ int r = 32; ++ ++ if (!x) ++ return 0; ++ if (!(x & 0xffff0000u)) { ++ x <<= 16; ++ r -= 16; ++ } ++ if (!(x & 0xff000000u)) { ++ x <<= 8; ++ r -= 8; ++ } ++ if (!(x & 0xf0000000u)) { ++ x <<= 4; ++ r -= 4; ++ } ++ if (!(x & 0xc0000000u)) { ++ x <<= 2; ++ r -= 2; ++ } ++ if (!(x & 0x80000000u)) { ++ x <<= 1; ++ r -= 1; ++ } ++ return r; ++} ++ ++static inline int __fls(int x) ++{ ++ return fls(x) - 1; ++} ++ ++#include <asm-generic/bitops/fls64.h> ++#include <asm-generic/bitops/sched.h> ++#include <asm-generic/bitops/hweight.h> ++#include <asm-generic/bitops/lock.h> ++ ++#define minix_find_first_zero_bit(addr, size) find_next_zero_bit((addr), \ ++ (size), 0) ++#define minix_test_and_set_bit(nr, addr) test_and_set_bit((nr), \ ++ (unsigned long *)(addr)) ++#define minix_set_bit(nr, addr) set_bit((nr), \ ++ (unsigned long *)(addr)) ++#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit((nr), \ ++ (unsigned long *)(addr)) ++ ++static inline int minix_test_bit(int nr, const volatile unsigned long *vaddr) ++{ ++ int *a = (int *)vaddr; ++ int mask; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ return ((mask & *a) != 0); ++} ++ ++#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 24, \ ++ (unsigned long *)(addr)) ++#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, \ ++ (unsigned long *)(addr)) ++#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 24, \ ++ (unsigned long *)(addr)) ++#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, \ ++ (unsigned long *)(addr)) ++ ++static inline int ext2_test_bit(int nr, const void *vaddr) ++{ ++ const unsigned char *p = vaddr; ++ return (p[nr >> 3] & (1U << (nr & 7))) != 0; ++} ++ ++static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) ++{ ++ const unsigned long *p = vaddr, *addr = vaddr; ++ int res; ++ ++ if (!size) ++ return 0; ++ ++ size = (size >> 5) + ((size & 31) > 0); ++ while (*p++ == ~0UL) { ++ if (--size == 0) ++ return (p - addr) << 5; ++ } ++ ++ --p; ++ for (res = 0; res < 32; res++) ++ if (!ext2_test_bit(res, p)) ++ break; ++ return (p - addr) * 32 + res; ++} ++ ++static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size, ++ unsigned offset) ++{ ++ const unsigned long *addr = vaddr; ++ const unsigned long *p = addr + (offset >> 5); ++ int bit = offset & 31UL, res; ++ ++ if (offset >= size) ++ return size; ++ ++ if (bit) { ++ /* Look for zero in first longword */ ++ for (res = bit; res < 32; res++) ++ if (!ext2_test_bit(res, p)) ++ return (p - addr) * 32 + res; ++ p++; ++ } ++ /* No zero yet, search remaining full bytes for a zero */ ++ res = ext2_find_first_zero_bit(p, size - 32 * (p - addr)); ++ return (p - addr) * 32 + res; ++} ++ ++#endif /* KERNEL */ ++ ++#endif /* __CF_BITOPS__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_cacheflush.h +@@ -0,0 +1,20 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef M68K_CF_CACHEFLUSH_H ++#define M68K_CF_CACHEFLUSH_H ++ ++#ifdef CONFIG_M5445X ++#include "cf_5445x_cacheflush.h" ++#elif defined(CONFIG_M5441X) ++#include "cf_5441x_cacheflush.h" ++#elif defined(CONFIG_M547X_8X) ++#include "cf_548x_cacheflush.h" ++#endif ++ ++#endif /* M68K_CF_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_entry.h +@@ -0,0 +1,153 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef __CF_M68K_ENTRY_H ++#define __CF_M68K_ENTRY_H ++ ++#include <asm/setup.h> ++#include <asm/page.h> ++#include <asm/coldfire.h> ++#include <asm/cfmmu.h> ++ ++/* ++ * Stack layout in 'ret_from_exception': ++ * ++ * This allows access to the syscall arguments in registers d1-d5 ++ * ++ * 0(sp) - d1 ++ * 4(sp) - d2 ++ * 8(sp) - d3 ++ * C(sp) - d4 ++ * 10(sp) - d5 ++ * 14(sp) - a0 ++ * 18(sp) - a1 ++ * 1C(sp) - a2 ++ * 20(sp) - d0 ++ * 24(sp) - orig_d0 ++ * 28(sp) - stack adjustment ++ * 2C(sp) - sr ++ * 2E(sp) - pc ++ * 32(sp) - format & vector ++ * 36(sp) - MMUSR ++ * 3A(sp) - MMUAR ++ */ ++ ++/* ++ * 97/05/14 Andreas: Register %a2 is now set to the current task throughout ++ * the whole kernel. ++ */ ++ ++/* the following macro is used when enabling interrupts */ ++/* portable version */ ++#define ALLOWINT (~0x700) ++#define MAX_NOINT_IPL 0 ++ ++#ifdef __ASSEMBLY__ ++ ++#define curptr a2 ++ ++LFLUSH_I_AND_D = 0x00000808 ++LSIGTRAP = 5 ++ ++/* process bits for task_struct.ptrace */ ++PT_TRACESYS_OFF = 3 ++PT_TRACESYS_BIT = 1 ++PT_PTRACED_OFF = 3 ++PT_PTRACED_BIT = 0 ++PT_DTRACE_OFF = 3 ++PT_DTRACE_BIT = 2 ++ ++#define SAVE_ALL_INT save_all_int ++#define SAVE_ALL_SYS save_all_sys ++#define RESTORE_ALL restore_all ++/* ++ * This defines the normal kernel pt-regs layout. ++ * ++ * regs a3-a6 and d6-d7 are preserved by C code ++ * the kernel doesn't mess with usp unless it needs to ++ */ ++ ++/* ++ * a -1 in the orig_d0 field signifies ++ * that the stack frame is NOT for syscall ++ */ ++.macro save_all_int ++ movel MMUSR, % sp@ - ++ movel MMUAR, % sp@ - ++ clrl % sp@ - | stk_adj ++ pea - 1 : w | orig d0 ++ movel % d0, % sp@ - | d0 ++ subal #(8*4), % sp ++ moveml % d1-%d5/%a0-%a1/%curptr, % sp@ ++.endm ++ ++.macro save_all_sys ++ movel MMUSR, % sp@- ++ movel MMUAR, % sp@- ++ clrl % sp@ - | stk_adj ++ movel % d0, % sp@ - | orig d0 ++ movel % d0, % sp@ - | d0 ++ subal #(8*4), % sp ++ moveml % d1-%d5/%a0-%a1/%curptr, % sp@ ++.endm ++ ++.macro restore_all ++ moveml % sp@, % a0-%a1/%curptr/%d1-%d5 ++ addal #(8*4), % sp ++ movel % sp@+, % d0 | d0 ++ addql #4, % sp | orig d0 ++ addl % sp@+, % sp | stk_adj ++ addql #8, % sp | MMUAR & MMUSR ++ rte ++.endm ++ ++#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */ ++ ++#define SAVE_SWITCH_STACK save_switch_stack ++#define RESTORE_SWITCH_STACK restore_switch_stack ++#define GET_CURRENT(tmp) get_current tmp ++ ++.macro save_switch_stack ++ subal #(6*4), % sp ++ moveml % a3-%a6/%d6-%d7, % sp@ ++.endm ++ ++.macro restore_switch_stack ++ moveml % sp@, % a3-%a6/%d6-%d7 ++ addal #(6*4), % sp ++.endm ++ ++.macro get_current reg = % d0 ++ movel % sp, \reg ++ andl #-THREAD_SIZE, \reg ++ movel \reg, % curptr ++ movel % curptr@, % curptr ++.endm ++ ++#else /* C source */ ++ ++#define STR(X) STR1(X) ++#define STR1(X) #X ++ ++#define PT_OFF_ORIG_D0 0x24 ++#define PT_OFF_FORMATVEC 0x32 ++#define PT_OFF_SR 0x2C ++#define SAVE_ALL_INT \ ++ "clrl %%sp@-;" /* stk_adj */ \ ++ "pea -1:w;" /* orig d0 = -1 */ \ ++ "movel %%d0,%%sp@-;" /* d0 */ \ ++ "subal #(8*4),%sp" \ ++ "moveml %%d1-%%d5/%%a0-%%a2,%%sp@" ++#define GET_CURRENT(tmp) \ ++ "movel %%sp,"#tmp"\n\t" \ ++ "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \ ++ "movel "#tmp",%%a2\n\t" ++ ++#endif ++ ++#endif /* __CF_M68K_ENTRY_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_io.h +@@ -0,0 +1,185 @@ ++/* ++ * linux/include/asm-m68k/cf_io.h ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * 9/30/08 JKM - Separated Coldfire pieces out from m68k. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef __CF_IO__ ++#define __CF_IO__ ++ ++#ifdef __KERNEL__ ++ ++#include <linux/compiler.h> ++#include <asm/raw_io.h> ++#include <asm/virtconvert.h> ++ ++#include <asm-generic/iomap.h> ++ ++#define readb_relaxed(addr) readb(addr) ++#define readw_relaxed(addr) readw(addr) ++#define readl_relaxed(addr) readl(addr) ++ ++#ifdef CONFIG_PCI ++ ++/* ++ * IO space in Coldfire ++ */ ++#define inb_p inb ++#define inw_p inw ++#define inl_p inl ++#define outb_p outb ++#define outw_p outw ++#define outl_p outl ++ ++#ifndef CONFIG_COLDFIRE ++#define inb(port) in_8(port) ++#define outb(val, port) out_8((port), (val)) ++#define inw(port) in_le16(port) ++#define outw(val, port) out_le16((port), (val)) ++#define inl(port) in_le32(port) ++#define outl(val, port) out_le32((port), (val)) ++#define insb(port, buf, nr) \ ++ raw_insb((u8 *)(port), (u8 *)(buf), (nr)) ++#define outsb(port, buf, nr) \ ++ raw_outsb((u8 *)(port), (u8 *)(buf), (nr)) ++#define insw(port, buf, nr) \ ++ raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)) ++#define outsw(port, buf, nr) \ ++ raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)) ++#define insl(port, buf, nr) \ ++ raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) ++#define outsl(port, buf, nr) \ ++ raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) ++#else ++#define inb(port) pci_inb(port) ++#define outb(val, port) pci_outb((val), (port)) ++#define inw(port) pci_inw(port) ++#define outw(val, port) pci_outw((val), (port)) ++#define insb(a, b, c) \ ++ pci_insb((volatile unsigned char *)a, (unsigned char *)b, c) ++#define insw(a, b, c) \ ++ pci_insw((volatile unsigned short *)a, (unsigned short *)b, c) ++#define insl(a, b, c) \ ++ pci_insl((volatile unsigned long *)a, (unsigned long *)b, c) ++#define outsb(a, b, c) \ ++ pci_outsb((volatile unsigned char *)a, (const unsigned char *)b, c) ++#define outsw(a, b, c) \ ++ pci_outsw((volatile unsigned short *)a, (const unsigned short *)b, c) ++#define outsl(a, b, c) \ ++ pci_outsl((volatile unsigned long *)a, (const unsigned long *)b, c) ++#define inl(port) pci_inl(port) ++#define outl(val, port) pci_outl((val), (port)) ++#endif ++ ++#else ++/* no pci */ ++ ++#define inb(port) in_8(port) ++#define outb(val, port) out_8((port), (val)) ++#define inw(port) in_le16(port) ++#define outw(val, port) out_le16((port), (val)) ++#define inl(port) in_le32(port) ++#define outl(val, port) out_le32((port), (val)) ++#define insb(port, buf, nr) \ ++ raw_insb((u8 *)(port), (u8 *)(buf), (nr)) ++#define outsb(port, buf, nr) \ ++ raw_outsb((u8 *)(port), (u8 *)(buf), (nr)) ++#define insw(port, buf, nr) \ ++ raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)) ++#define outsw(port, buf, nr) \ ++ raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)) ++#define insl(port, buf, nr) \ ++ raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) ++#define outsl(port, buf, nr) \ ++ raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) ++ ++#endif /* CONFIG_PCI */ ++ ++#define mmiowb() ++ ++static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) ++{ ++ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); ++} ++static inline void __iomem *ioremap_nocache(unsigned long physaddr, ++ unsigned long size) ++{ ++ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); ++} ++static inline void __iomem *ioremap_writethrough(unsigned long physaddr, ++ unsigned long size) ++{ ++ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); ++} ++static inline void __iomem *ioremap_fullcache(unsigned long physaddr, ++ unsigned long size) ++{ ++ return __ioremap(physaddr, size, IOMAP_FULL_CACHING); ++} ++ ++static inline void memset_io(volatile void __iomem *addr, ++ unsigned char val, int count) ++{ ++ __builtin_memset((void __force *) addr, val, count); ++} ++static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, ++ int count) ++{ ++ __builtin_memcpy(dst, (void __force *) src, count); ++} ++static inline void memcpy_toio(volatile void __iomem *dst, ++ const void *src, int count) ++{ ++ __builtin_memcpy((void __force *) dst, src, count); ++} ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#endif /* __KERNEL__ */ ++ ++#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1 ++ ++/* ++ * Convert a physical pointer to a virtual kernel pointer for /dev/mem ++ * access ++ */ ++#define xlate_dev_mem_ptr(p) __va(p) ++ ++/* ++ * Convert a virtual cached pointer to an uncached pointer ++ */ ++#define xlate_dev_kmem_ptr(p) p ++ ++#define __raw_readb(addr) \ ++ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) ++#define __raw_readw(addr) \ ++ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) ++#define __raw_readl(addr) \ ++ ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; }) ++#define __raw_writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) ++#define __raw_writew(b, addr) \ ++ (void)((*(volatile unsigned short *) (addr)) = (b)) ++#define __raw_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) ++ ++#define memset_io(a, b, c) memset((void *)(a), (b), (c)) ++#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) ++#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) ++ ++#if !defined(readb) ++#define readb(addr) \ ++ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) ++#define readw(addr) \ ++ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) ++#define readl(addr) \ ++ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) ++#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) ++#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) ++#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) ++#endif /* readb */ ++ ++#endif /* _IO_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_pgalloc.h +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef M68K_CF_PGALLOC_H ++#define M68K_CF_PGALLOC_H ++#include <linux/highmem.h> ++#include <asm/coldfire.h> ++#include <asm/page.h> ++#include <asm/cf_tlbflush.h> ++#include <asm/cf_cacheflush.h> ++ ++extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) ++{ ++ free_page((unsigned long) pte); ++} ++ ++extern const char bad_pmd_string[]; ++ ++extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, ++ unsigned long address) ++{ ++ unsigned long page = __get_free_page(GFP_KERNEL|__GFP_REPEAT); ++ ++ if (!page) ++ return NULL; ++ ++ memset((void *)page, 0, PAGE_SIZE); ++ return (pte_t *) (page); ++} ++ ++extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address) ++{ ++ return (pmd_t *) pgd; ++} ++ ++#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); }) ++#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); }) ++ ++#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr) ++ ++#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \ ++ (unsigned long)(page_address(page))) ++ ++#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte)) ++ ++#define pmd_pgtable(pmd) pmd_page(pmd) ++ ++static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page, ++ unsigned long address) ++{ ++ __free_page(page); ++} ++ ++#define __pmd_free_tlb(tlb, pmd, address) do { } while (0) ++ ++static inline struct page *pte_alloc_one(struct mm_struct *mm, ++ unsigned long address) ++{ ++ struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0); ++ pte_t *pte; ++ ++ if (!page) ++ return NULL; ++ ++ pte = kmap(page); ++ if (pte) { ++ clear_page(pte); ++ __flush_page_to_ram(pte); ++ flush_tlb_kernel_page(pte); ++ nocache_page(pte); ++ } ++ kunmap(page); ++ ++ return page; ++} ++ ++extern inline void pte_free(struct mm_struct *mm, struct page *page) ++{ ++ __free_page(page); ++} ++ ++/* ++ * In our implementation, each pgd entry contains 1 pmd that is never allocated ++ * or freed. pgd_present is always 1, so this should never be called. -NL ++ */ ++#define pmd_free(mm, pmd) BUG() ++ ++extern inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) ++{ ++ free_page((unsigned long) pgd); ++} ++ ++extern inline pgd_t *pgd_alloc(struct mm_struct *mm) ++{ ++ pgd_t *new_pgd; ++ ++ new_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_NOWARN); ++ if (!new_pgd) ++ return NULL; ++ memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE); ++ memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT); ++ return new_pgd; ++} ++ ++#define pgd_populate(mm, pmd, pte) BUG() ++ ++#endif /* M68K_CF_PGALLOC_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_pgtable.h +@@ -0,0 +1,364 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef _CF_PGTABLE_H ++#define _CF_PGTABLE_H ++ ++#include <asm/cfmmu.h> ++#include <asm/page.h> ++ ++#ifndef __ASSEMBLY__ ++#include <asm/virtconvert.h> ++#include <linux/linkage.h> ++ ++/* For virtual address to physical address conversion */ ++#define VTOP(addr) __pa(addr) ++#define PTOV(addr) __va(addr) ++ ++ ++#endif /* !__ASSEMBLY__ */ ++ ++/* Page protection values within PTE. */ ++ ++/* MMUDR bits, in proper place. */ ++#define CF_PAGE_LOCKED (0x00000002) ++#define CF_PAGE_EXEC (0x00000004) ++#define CF_PAGE_WRITABLE (0x00000008) ++#define CF_PAGE_READABLE (0x00000010) ++#define CF_PAGE_SYSTEM (0x00000020) ++#define CF_PAGE_COPYBACK (0x00000040) ++#define CF_PAGE_NOCACHE (0x00000080) ++ ++#define CF_CACHEMASK (~0x00000040) ++#define CF_PAGE_MMUDR_MASK (0x000000fe) ++ ++#define _PAGE_NOCACHE030 (CF_PAGE_NOCACHE) ++ ++/* MMUTR bits, need shifting down. */ ++#define CF_PAGE_VALID (0x00000400) ++#define CF_PAGE_SHARED (0x00000800) ++ ++#define CF_PAGE_MMUTR_MASK (0x00000c00) ++#define CF_PAGE_MMUTR_SHIFT (10) ++#define CF_ASID_MMU_SHIFT (2) ++ ++/* Fake bits, not implemented in CF, will get masked out before ++ hitting hardware, and might go away altogether once this port is ++ complete. */ ++#if PAGE_SHIFT < 13 ++#error COLDFIRE Error: Pages must be at least 8k in size ++#endif ++#define CF_PAGE_ACCESSED (0x00001000) ++#define CF_PAGE_FILE (0x00000200) ++#define CF_PAGE_DIRTY (0x00000001) ++ ++#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */ ++#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */ ++#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */ ++#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */ ++#define _DESCTYPE_MASK 0x003 ++#define _CACHEMASK040 (~0x060) ++#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ ++ ++ ++/* Externally used page protection values. */ ++#define _PAGE_PRESENT (CF_PAGE_VALID) ++#define _PAGE_ACCESSED (CF_PAGE_ACCESSED) ++#define _PAGE_DIRTY (CF_PAGE_DIRTY) ++#define _PAGE_READWRITE (CF_PAGE_WRITABLE \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_SHARED \ ++ | CF_PAGE_SYSTEM) ++ ++/* Compound page protection values. */ ++#define PAGE_NONE __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED) ++ ++#define PAGE_SHARED __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_ACCESSED) ++ ++#define PAGE_INIT __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_EXEC \ ++ | CF_PAGE_SYSTEM \ ++ | CF_PAGE_SHARED) ++ ++#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_EXEC \ ++ | CF_PAGE_SYSTEM \ ++ | CF_PAGE_SHARED \ ++ | CF_PAGE_ACCESSED) ++ ++#define PAGE_COPY __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_READABLE) ++ ++/* ++ * Page protections for initialising protection_map. See mm/mmap.c ++ * for use. In general, the bit positions are xwr, and P-items are ++ * private, the S-items are shared. ++ */ ++ ++#define __P000 PAGE_NONE ++#define __P100 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_EXEC) ++#define __P010 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_ACCESSED) ++#define __P110 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_EXEC) ++#define __P001 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_READABLE) ++#define __P101 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_EXEC) ++#define __P011 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_ACCESSED) ++#define __P111 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_EXEC) ++ ++#define __S000 PAGE_NONE ++#define __S100 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_EXEC) ++#define __S010 PAGE_SHARED ++#define __S110 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_EXEC) ++#define __S001 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_READABLE) ++#define __S101 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_EXEC) ++#define __S011 PAGE_SHARED ++#define __S111 __pgprot(CF_PAGE_VALID \ ++ | CF_PAGE_ACCESSED \ ++ | CF_PAGE_READABLE \ ++ | CF_PAGE_WRITABLE \ ++ | CF_PAGE_EXEC) ++ ++#define PTE_MASK PAGE_MASK ++#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY) ++ ++#ifndef __ASSEMBLY__ ++ ++/* ++ * Conversion functions: convert a page and protection to a page entry, ++ * and a page entry and page directory to the page they refer to. ++ */ ++#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) ++ ++extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) ++{ ++ pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); ++ return pte; ++} ++ ++#define pmd_set(pmdp, ptep) do {} while (0) ++ ++static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) ++{ ++ pgd_val(*pgdp) = virt_to_phys(pmdp); ++} ++ ++#define __pte_page(pte) \ ++ ((unsigned long) ((pte_val(pte) & CF_PAGE_PGNUM_MASK) + PAGE_OFFSET)) ++#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd))) ++ ++extern inline int pte_none(pte_t pte) ++{ ++ return !pte_val(pte); ++} ++extern inline int pte_present(pte_t pte) ++{ ++ return pte_val(pte) & CF_PAGE_VALID; ++} ++extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, ++ pte_t *ptep) ++{ ++ pte_val(*ptep) = 0; ++} ++ ++#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) ++#define pte_page(pte) virt_to_page(__pte_page(pte)) ++ ++extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); } ++#define pmd_none(pmd) pmd_none2(&(pmd)) ++extern inline int pmd_bad2(pmd_t *pmd) { return 0; } ++#define pmd_bad(pmd) pmd_bad2(&(pmd)) ++#define pmd_present(pmd) (!pmd_none2(&(pmd))) ++extern inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; } ++ ++extern inline int pgd_none(pgd_t pgd) { return 0; } ++extern inline int pgd_bad(pgd_t pgd) { return 0; } ++extern inline int pgd_present(pgd_t pgd) { return 1; } ++extern inline void pgd_clear(pgd_t *pgdp) {} ++ ++ ++#define pte_ERROR(e) \ ++ printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ ++ __FILE__, __LINE__, pte_val(e)) ++#define pmd_ERROR(e) \ ++ printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \ ++ __FILE__, __LINE__, pmd_val(e)) ++#define pgd_ERROR(e) \ ++ printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ ++ __FILE__, __LINE__, pgd_val(e)) ++ ++ ++/* ++ * The following only work if pte_present() is true. ++ * Undefined behaviour if not... ++ * [we have the full set here even if they don't change from m68k] ++ */ ++extern inline int pte_read(pte_t pte) \ ++ { return pte_val(pte) & CF_PAGE_READABLE; } ++extern inline int pte_write(pte_t pte) \ ++ { return pte_val(pte) & CF_PAGE_WRITABLE; } ++extern inline int pte_exec(pte_t pte) \ ++ { return pte_val(pte) & CF_PAGE_EXEC; } ++extern inline int pte_dirty(pte_t pte) \ ++ { return pte_val(pte) & CF_PAGE_DIRTY; } ++extern inline int pte_young(pte_t pte) \ ++ { return pte_val(pte) & CF_PAGE_ACCESSED; } ++extern inline int pte_file(pte_t pte) \ ++ { return pte_val(pte) & CF_PAGE_FILE; } ++static inline int pte_special(pte_t pte) { return 0; } ++ ++ ++extern inline pte_t pte_wrprotect(pte_t pte) \ ++ { pte_val(pte) &= ~CF_PAGE_WRITABLE; return pte; } ++extern inline pte_t pte_rdprotect(pte_t pte) \ ++ { pte_val(pte) &= ~CF_PAGE_READABLE; return pte; } ++extern inline pte_t pte_exprotect(pte_t pte) \ ++ { pte_val(pte) &= ~CF_PAGE_EXEC; return pte; } ++extern inline pte_t pte_mkclean(pte_t pte) \ ++ { pte_val(pte) &= ~CF_PAGE_DIRTY; return pte; } ++extern inline pte_t pte_mkold(pte_t pte) \ ++ { pte_val(pte) &= ~CF_PAGE_ACCESSED; return pte; } ++extern inline pte_t pte_mkwrite(pte_t pte) \ ++ { pte_val(pte) |= CF_PAGE_WRITABLE; return pte; } ++extern inline pte_t pte_mkread(pte_t pte) \ ++ { pte_val(pte) |= CF_PAGE_READABLE; return pte; } ++extern inline pte_t pte_mkexec(pte_t pte) \ ++ { pte_val(pte) |= CF_PAGE_EXEC; return pte; } ++extern inline pte_t pte_mkdirty(pte_t pte) \ ++ { pte_val(pte) |= CF_PAGE_DIRTY; return pte; } ++extern inline pte_t pte_mkyoung(pte_t pte) \ ++ { pte_val(pte) |= CF_PAGE_ACCESSED; return pte; } ++extern inline pte_t pte_mknocache(pte_t pte) \ ++ { pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); return pte; } ++extern inline pte_t pte_mkcache(pte_t pte) \ ++ { pte_val(pte) &= ~CF_PAGE_NOCACHE; return pte; } ++static inline pte_t pte_mkspecial(pte_t pte) { return pte; } ++ ++ ++#define swapper_pg_dir kernel_pg_dir ++extern pgd_t kernel_pg_dir[PTRS_PER_PGD]; ++ ++/* Find an entry in a pagetable directory. */ ++#define pgd_index(address) ((address) >> PGDIR_SHIFT) ++ ++#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) ++ ++/* Find an entry in a kernel pagetable directory. */ ++#define pgd_offset_k(address) pgd_offset(&init_mm, address) ++ ++/* Find an entry in the second-level pagetable. */ ++extern inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address) ++{ ++ return (pmd_t *) pgd; ++} ++ ++/* Find an entry in the third-level pagetable. */ ++#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) ++#define pte_offset_kernel(dir, address) ((pte_t *) __pmd_page(*(dir)) + \ ++ __pte_offset(address)) ++ ++/* Disable caching for page at given kernel virtual address. */ ++static inline void nocache_page(void *vaddr) ++{ ++ pgd_t *dir; ++ pmd_t *pmdp; ++ pte_t *ptep; ++ unsigned long addr = (unsigned long)vaddr; ++ ++ dir = pgd_offset_k(addr); ++ pmdp = pmd_offset(dir, addr); ++ ptep = pte_offset_kernel(pmdp, addr); ++ *ptep = pte_mknocache(*ptep); ++} ++ ++/* Enable caching for page at given kernel virtual address. */ ++static inline void cache_page(void *vaddr) ++{ ++ pgd_t *dir; ++ pmd_t *pmdp; ++ pte_t *ptep; ++ unsigned long addr = (unsigned long)vaddr; ++ ++ dir = pgd_offset_k(addr); ++ pmdp = pmd_offset(dir, addr); ++ ptep = pte_offset_kernel(pmdp, addr); ++ *ptep = pte_mkcache(*ptep); ++} ++ ++#define PTE_FILE_MAX_BITS 21 ++#define PTE_FILE_SHIFT 11 ++ ++static inline unsigned long pte_to_pgoff(pte_t pte) ++{ ++ return pte_val(pte) >> PTE_FILE_SHIFT; ++} ++ ++static inline pte_t pgoff_to_pte(unsigned pgoff) ++{ ++ pte_t pte = __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE); ++ return pte; ++} ++ ++/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ ++#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ ++ (offset << PTE_FILE_SHIFT) }) ++#define __swp_type(x) ((x).val & 0xFF) ++#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT) ++#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) ++#define __swp_entry_to_pte(x) (__pte((x).val)) ++ ++#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) ++ ++#define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) + \ ++ __pte_offset(address)) ++#define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address) ++#define pte_unmap(pte) do { } while (0) ++#define pte_unmap_nested(pte) kunmap(pte) ++ ++#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) ++#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) ++ ++ ++#endif /* !__ASSEMBLY__ */ ++#endif /* !_CF_PGTABLE_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_raw_io.h +@@ -0,0 +1,188 @@ ++/* ++ * linux/include/asm-m68k/cf_raw_io.h ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * 09/30/08 JKM: split Coldfire pieces into separate file ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++#ifndef __CF_RAW_IO__ ++#define __CF_RAW_IO__ ++ ++#ifdef __KERNEL__ ++ ++#include <asm/types.h> ++ ++/* Values for nocacheflag and cmode */ ++#define IOMAP_FULL_CACHING 0 ++#define IOMAP_NOCACHE_SER 1 ++#define IOMAP_NOCACHE_NONSER 2 ++#define IOMAP_WRITETHROUGH 3 ++ ++extern void iounmap(void __iomem *addr); ++ ++extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size, ++ int cacheflag); ++extern void __iounmap(void *addr, unsigned long size); ++ ++ ++/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates ++ * two accesses to memory, which may be undesirable for some devices. ++ */ ++#define in_8(addr) \ ++ ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; }) ++#define in_be16(addr) \ ++ ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; }) ++#define in_be32(addr) \ ++ ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; }) ++#define in_le16(addr) \ ++ ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; }) ++#define in_le32(addr) \ ++ ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; }) ++ ++#define out_8(addr, b) (void)((*(__force volatile u8 *) (addr)) = (b)) ++#define out_be16(addr, w) (void)((*(__force volatile u16 *) (addr)) = (w)) ++#define out_be32(addr, l) (void)((*(__force volatile u32 *) (addr)) = (l)) ++#define out_le16(addr, w) \ ++ (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w)) ++#define out_le32(addr, l) \ ++ (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l)) ++ ++ ++#ifdef CONFIG_PCI ++/* pci */ ++unsigned char pci_inb(long addr); ++unsigned short pci_inw(long addr); ++unsigned long pci_inl(long addr); ++ ++void pci_outb(unsigned char val, long addr); ++void pci_outw(unsigned short val, long addr); ++void pci_outl(unsigned long val, long addr); ++ ++void pci_insb(volatile unsigned char *addr, ++ unsigned char *buf, int len); ++void pci_insw(volatile unsigned short *addr, ++ unsigned short *buf, int len); ++void pci_insl(volatile unsigned long *addr, ++ unsigned long *buf, int len); ++ ++void pci_outsb(volatile unsigned char *addr, ++ const unsigned char *buf, int len); ++void pci_outsw(volatile unsigned short *addr, ++ const unsigned short *buf, int len); ++void pci_outsl(volatile unsigned long *addr, ++ const unsigned long *buf, int len); ++ ++unsigned short pci_raw_inw(long addr); ++unsigned long pci_raw_inl(long addr); ++void pci_raw_outw(unsigned short val, long addr); ++void pci_raw_outl(unsigned long val, long addr); ++ ++#define raw_inb(port) pci_inb((long)((volatile unsigned char *)(port))) ++#define raw_inw(port) pci_raw_inw((long)((volatile unsigned short *)(port))) ++#define raw_inl(port) pci_raw_inl((long)((volatile unsigned long *)(port))) ++ ++#define raw_outb(val, port) \ ++ pci_outb((val), (long)((volatile unsigned char *)(port))) ++#define raw_outw(val, port) \ ++ pci_raw_outw((val), (long)((volatile unsigned short *)(port))) ++#define raw_outl(val, port) \ ++ pci_raw_outl((val), (long)((volatile unsigned long *)(port))) ++ ++#define swap_inw(port) pci_inw((long)((volatile unsigned short *)(port))) ++#define swap_outw(val, port) \ ++ pci_outw((val), (long)((volatile unsigned short *)(port))) ++ ++#else ++/* non-pci */ ++#define raw_inb in_8 ++#define raw_inw in_be16 ++#define raw_inl in_be32 ++ ++#define raw_outb(val, port) out_8((port), (val)) ++#define raw_outw(val, port) out_be16((port), (val)) ++#define raw_outl(val, port) out_be32((port), (val)) ++ ++#define swap_inw(port) in_le16((port)) ++#define swap_outw(val, port) out_le16((port), (val)) ++#endif ++ ++static inline void raw_insb(volatile u8 __iomem *port, ++ u8 *buf, unsigned int len) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < len; i++) ++ *buf++ = in_8(port); ++} ++ ++static inline void raw_outsb(volatile u8 __iomem *port, const u8 *buf, ++ unsigned int len) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < len; i++) ++ out_8(port, *buf++); ++} ++ ++static inline void raw_insw(volatile u16 *port, u16 *buf, unsigned int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++) ++ *buf++ = raw_inw(port); ++} ++ ++static inline void raw_outsw(volatile u16 *port, const u16 *buf, ++ unsigned int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++, buf++) ++ raw_outw(*buf, port); ++} ++ ++static inline void raw_insl(volatile u32 *port, u32 *buf, unsigned int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++) ++ *buf++ = raw_inl(port); ++} ++ ++static inline void raw_outsl(volatile u32 *port, const u32 *buf, ++ unsigned int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++, buf++) ++ raw_outl(*buf, port); ++} ++ ++static inline void raw_insw_swapw(volatile u16 *port, u16 *buf, ++ unsigned int nr) ++{ ++#ifdef UNDEF ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++) ++ *buf++ = in_le16(port); ++#endif ++} ++ ++static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf, ++ unsigned int nr) ++{ ++#ifdef UNDEF ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++, buf++) ++ out_le16(port, *buf); ++#endif ++} ++ ++#endif /* __KERNEL__ */ ++ ++#endif /* __CF_RAW_IO__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_tlbflush.h +@@ -0,0 +1,66 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++#ifndef M68K_CF_TLBFLUSH_H ++#define M68K_CF_TLBFLUSH_H ++ ++#include <asm/coldfire.h> ++ ++/* Flush all userspace mappings. */ ++static inline void flush_tlb_all(void) ++{ ++ preempt_disable(); ++ *MMUOR = MMUOR_CNL; ++ preempt_enable(); ++} ++ ++/* Clear user TLB entries within the context named in mm */ ++static inline void flush_tlb_mm(struct mm_struct *mm) ++{ ++ preempt_disable(); ++ *MMUOR = MMUOR_CNL; ++ preempt_enable(); ++} ++ ++/* Flush a single TLB page. */ ++static inline void flush_tlb_page(struct vm_area_struct *vma, ++ unsigned long addr) ++{ ++ preempt_disable(); ++ *MMUOR = MMUOR_CNL; ++ preempt_enable(); ++} ++/* Flush a range of pages from TLB. */ ++ ++static inline void flush_tlb_range(struct vm_area_struct *mm, ++ unsigned long start, unsigned long end) ++{ ++ preempt_disable(); ++ *MMUOR = MMUOR_CNL; ++ preempt_enable(); ++} ++ ++/* Flush kernel page from TLB. */ ++static inline void flush_tlb_kernel_page(void *addr) ++{ ++ preempt_disable(); ++ *MMUOR = MMUOR_CNL; ++ preempt_enable(); ++} ++ ++static inline void flush_tlb_kernel_range(unsigned long start, ++ unsigned long end) ++{ ++ flush_tlb_all(); ++} ++ ++extern inline void flush_tlb_pgtables(struct mm_struct *mm, ++ unsigned long start, unsigned long end) ++{ ++} ++ ++#endif /* M68K_CF_TLBFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_uaccess.h +@@ -0,0 +1,262 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++#ifndef __M68K_CF_UACCESS_H ++#define __M68K_CF_UACCESS_H ++ ++/* ++ * User space memory access functions ++ */ ++ ++/* The "moves" command is not available in the CF instruction set. */ ++#include <linux/compiler.h> ++#include <linux/errno.h> ++#include <linux/types.h> ++#include <linux/sched.h> ++#include <asm/segment.h> ++ ++#define VERIFY_READ 0 ++#define VERIFY_WRITE 1 ++ ++/* We let the MMU do all checking */ ++#define access_ok(type, addr, size) 1 ++ ++/* ++ * The exception table consists of pairs of addresses: the first is the ++ * address of an instruction that is allowed to fault, and the second is ++ * the address at which the program should continue. No registers are ++ * modified, so it is entirely up to the continuation code to figure out ++ * what to do. ++ * ++ * All the routines below use bits of fixup code that are out of line ++ * with the main instruction path. This means when everything is well, ++ * we don't even have to jump over them. Further, they do not intrude ++ * on our cache or tlb entries. ++ */ ++ ++struct exception_table_entry { ++ unsigned long insn, fixup; ++}; ++ ++extern int __put_user_bad(void); ++extern int __get_user_bad(void); ++ ++#define __put_user_asm(res, x, ptr, bwl, reg, err) \ ++asm volatile ("\n" \ ++ "1: move."#bwl" %2,%1\n" \ ++ "2:\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "10: moveq.l %3,%0\n" \ ++ " jra 2b\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 1b,10b\n" \ ++ " .long 2b,10b\n" \ ++ " .previous" \ ++ : "+d" (res), "=m" (*(ptr)) \ ++ : #reg(x), "i" (err)) ++ ++/* ++ * These are the main single-value transfer routines. They automatically ++ * use the right size if we just have the right pointer type. ++ */ ++ ++#define __put_user(x, ptr) \ ++({ \ ++ typeof(*(ptr)) __pu_val = (x); \ ++ int __pu_err = 0; \ ++ __chk_user_ptr(ptr); \ ++ switch (sizeof(*(ptr))) { \ ++ case 1: \ ++ __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \ ++ break; \ ++ case 2: \ ++ __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \ ++ break; \ ++ case 4: \ ++ __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \ ++ break; \ ++ case 8: \ ++ { \ ++ const void __user *__pu_ptr = (ptr); \ ++ asm volatile ("\n" \ ++ "1: move.l %2,(%1)+\n" \ ++ "2: move.l %R2,(%1)\n" \ ++ "3:\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "10: movel %3,%0\n" \ ++ " jra 3b\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 1b,10b\n" \ ++ " .long 2b,10b\n" \ ++ " .long 3b,10b\n" \ ++ " .previous" \ ++ : "+d" (__pu_err), "+a" (__pu_ptr) \ ++ : "r" (__pu_val), "i" (-EFAULT) \ ++ : "memory"); \ ++ break; \ ++ } \ ++ default: \ ++ __pu_err = __put_user_bad(); \ ++ break; \ ++ } \ ++ __pu_err; \ ++}) ++#define put_user(x, ptr) __put_user(x, ptr) ++ ++ ++#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \ ++ type __gu_val; \ ++ asm volatile ("\n" \ ++ "1: move."#bwl" %2,%1\n" \ ++ "2:\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "10: move.l %3,%0\n" \ ++ " subl %1,%1\n" \ ++ " jra 2b\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 1b,10b\n" \ ++ " .previous" \ ++ : "+d" (res), "=&" #reg(__gu_val) \ ++ : "m" (*(ptr)), "i" (err)); \ ++ (x) = (typeof(*(ptr)))(unsigned long)__gu_val; \ ++}) ++ ++#define __get_user(x, ptr) \ ++({ \ ++ int __gu_err = 0; \ ++ __chk_user_ptr(ptr); \ ++ switch (sizeof(*(ptr))) { \ ++ case 1: \ ++ __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \ ++ break; \ ++ case 2: \ ++ __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \ ++ break; \ ++ case 4: \ ++ __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \ ++ break; \ ++/* case 8: disabled because gcc-4.1 has a broken typeof \ ++ { \ ++ const void *__gu_ptr = (ptr); \ ++ u64 __gu_val; \ ++ asm volatile ("\n" \ ++ "1: move.l (%2)+,%1\n" \ ++ "2: move.l (%2),%R1\n" \ ++ "3:\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "10: move.l %3,%0\n" \ ++ " subl %1,%1\n" \ ++ " subl %R1,%R1\n" \ ++ " jra 3b\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 1b,10b\n" \ ++ " .long 2b,10b\n" \ ++ " .previous" \ ++ : "+d" (__gu_err), "=&r" (__gu_val), \ ++ "+a" (__gu_ptr) \ ++ : "i" (-EFAULT) \ ++ : "memory"); \ ++ (x) = (typeof(*(ptr)))__gu_val; \ ++ break; \ ++ } */ \ ++ default : \ ++ __gu_err = __get_user_bad(); \ ++ break; \ ++ } \ ++ __gu_err; \ ++}) ++#define get_user(x, ptr) __get_user(x, ptr) ++ ++unsigned long __generic_copy_from_user(void *to, const void __user *from, ++ unsigned long n); ++unsigned long __generic_copy_to_user(void __user *to, const void *from, ++ unsigned long n); ++ ++#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\ ++ asm volatile ("\n" \ ++ "1: move."#s1" (%2)+,%3\n" \ ++ " move."#s1" %3,(%1)+\n" \ ++ "2: move."#s2" (%2)+,%3\n" \ ++ " move."#s2" %3,(%1)+\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ "3: move."#s3" (%2)+,%3\n" \ ++ " move."#s3" %3,(%1)+\n" \ ++ " .endif\n" \ ++ "4:\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 1b,10f\n" \ ++ " .long 2b,20f\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ " .long 3b,30f\n" \ ++ " .endif\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "10: clr."#s1" (%1)+\n" \ ++ "20: clr."#s2" (%1)+\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ "30: clr."#s3" (%1)+\n" \ ++ " .endif\n" \ ++ " moveq.l #"#n",%0\n" \ ++ " jra 4b\n" \ ++ " .previous\n" \ ++ : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \ ++ : : "memory") ++ ++#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ ++ asm volatile ("\n" \ ++ " move."#s1" (%2)+,%3\n" \ ++ "11: move."#s1" %3,(%1)+\n" \ ++ "12: move."#s2" (%2)+,%3\n" \ ++ "21: move."#s2" %3,(%1)+\n" \ ++ "22:\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ " move."#s3" (%2)+,%3\n" \ ++ "31: move."#s3" %3,(%1)+\n" \ ++ "32:\n" \ ++ " .endif\n" \ ++ "4:\n" \ ++ "\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 11b,5f\n" \ ++ " .long 12b,5f\n" \ ++ " .long 21b,5f\n" \ ++ " .long 22b,5f\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ " .long 31b,5f\n" \ ++ " .long 32b,5f\n" \ ++ " .endif\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "5: moveq.l #"#n",%0\n" \ ++ " jra 4b\n" \ ++ " .previous\n" \ ++ : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \ ++ : : "memory") ++ ++#endif /* _M68K_CF_UACCESS_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cf_virtconvert.h +@@ -0,0 +1,63 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++#ifndef __CF_VIRTCONVERT__ ++#define __CF_VIRTCONVERT__ ++ ++/* ++ * Macros used for converting between virtual and physical mappings. ++ * ++ * Coldfire Specific ++ */ ++ ++#ifdef __KERNEL__ ++ ++#include <linux/compiler.h> ++#include <linux/mmzone.h> ++#include <asm/setup.h> ++#include <asm/page.h> ++ ++/* ++ * Change virtual addresses to physical addresses and vv. ++ */ ++static inline unsigned long virt_to_phys(void *address) ++{ ++ return __pa(address); ++} ++ ++static inline void *phys_to_virt(unsigned long address) ++{ ++ return __va(address); ++} ++ ++/* Permanent address of a page. */ ++#ifdef CONFIG_SINGLE_MEMORY_CHUNK ++#define page_to_phys(page) \ ++ __pa(PAGE_OFFSET + \ ++ (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT)) ++#else ++#define page_to_phys(_page) ({ \ ++ struct page *__page = _page; \ ++ struct pglist_data *pgdat; \ ++ pgdat = pg_data_table[page_to_nid(__page)]; \ ++ page_to_pfn(__page) << PAGE_SHIFT; \ ++}) ++#endif ++ ++/* ++ * IO bus memory addresses are 1:1 with the physical address, ++ */ ++#ifdef CONFIG_PCI ++#define virt_to_bus(a) (a + PCI_DMA_BASE) ++#define bus_to_virt(a) (a - PCI_DMA_BASE) ++#else ++#define virt_to_bus(a) (a) ++#define bus_to_virt(a) (a) ++#endif ++ ++#endif /* __KERNEL__ */ ++#endif /* __CF_VIRTCONVERT__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/cfcache.h +@@ -0,0 +1,146 @@ ++/* ++ * include/asm-m68k/cfcache.h - Coldfire Cache Controller ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef CF_CFCACHE_H ++#define CF_CFCACHE_H ++ ++/* ++ * CACR Cache Control Register ++ */ ++#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */ ++#define CF_CACR_DW (0x40000000) /* Data default Write-protect */ ++#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */ ++#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */ ++#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */ ++#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */ ++#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */ ++#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */ ++#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */ ++#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */ ++#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */ ++#define CF_CACR_IVO (0x00100000) /* Invalidate only */ ++#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */ ++#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */ ++#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */ ++#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */ ++#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */ ++#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */ ++#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */ ++#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */ ++#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */ ++#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */ ++#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */ ++ ++#ifdef CONFIG_M5445X ++/* ++ * M5445x Cache Configuration ++ * - cache line size is 16 bytes ++ * - cache is 4-way set associative ++ * - each cache has 256 sets (64k / 16bytes / 4way) ++ * - I-Cache size is 16KB ++ * - D-Cache size is 16KB ++ */ ++#define ICACHE_SIZE 0x4000 /* instruction - 16k */ ++#define DCACHE_SIZE 0x4000 /* data - 16k */ ++ ++#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ ++#define CACHE_SETS 0x0100 /* 256 sets */ ++#define CACHE_WAYS 0x0004 /* 4 way */ ++ ++#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ ++ CF_CACR_BCINVA+ \ ++ CF_CACR_ICINVA) ++ ++#ifndef CONFIG_M5445X_DISABLE_CACHE ++#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ ++ CF_CACR_BEC+ \ ++ CF_CACR_IEC+ \ ++ CF_CACR_DESB+ \ ++ CF_CACR_EUSP) ++#else ++/* cache disabled for testing */ ++#define CACHE_INITIAL_MODE (CF_CACR_EUSP) ++#endif /* CONFIG_M5445X_DISABLE_CACHE */ ++ ++#elif defined(CONFIG_M547X_8X) ++/* ++ * * M547x/M548x Cache Configuration ++ * * - cache line size is 16 bytes ++ * * - cache is 4-way set associative ++ * * - each cache has 512 sets (128k / 16bytes / 4way) ++ * * - I-Cache size is 32KB ++ * * - D-Cache size is 32KB ++ * */ ++#define ICACHE_SIZE 0x8000 /* instruction - 32k */ ++#define DCACHE_SIZE 0x8000 /* data - 32k */ ++ ++#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ ++#define CACHE_SETS 0x0200 /* 512 sets */ ++#define CACHE_WAYS 0x0004 /* 4 way */ ++ ++/* in for the old cpushl caching code */ ++#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS) ++#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS) ++#define LAST_DCACHE_ADDR _DCACHE_SET_MASK ++#define LAST_ICACHE_ADDR _ICACHE_SET_MASK ++ ++#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ ++ CF_CACR_BCINVA+ \ ++ CF_CACR_ICINVA) ++ ++#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ ++ CF_CACR_BEC+ \ ++ CF_CACR_IEC+ \ ++ CF_CACR_DESB+ \ ++ CF_CACR_EUSP) ++#elif defined(CONFIG_M5441X) ++/* ++ * M5441x Cache Configuration ++ * - cache line size is 16 bytes ++ * - cache is 4-way set associative ++ * - each cache has 128 sets (8k / 16bytes / 4way) ++ * - I-Cache size is 8KB ++ * - D-Cache size is 8KB ++ */ ++#define ICACHE_SIZE 0x2000 /* instruction - 8k */ ++#define DCACHE_SIZE 0x2000 /* data - 8k */ ++ ++#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ ++#define CACHE_SETS 0x0080 /* 128 sets */ ++#define CACHE_WAYS 0x0004 /* 4 way */ ++ ++#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ ++ CF_CACR_BCINVA+ \ ++ CF_CACR_ICINVA) ++ ++#ifndef CONFIG_M5441X_DISABLE_CACHE ++#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ ++ CF_CACR_BEC+ \ ++ CF_CACR_IEC+ \ ++ CF_CACR_DESB+ \ ++ CF_CACR_DDCM_01+ \ ++ CF_CACR_EUSP) ++#else ++/* cache disabled for testing */ ++#define CACHE_INITIAL_MODE (CF_CACR_EUSP) ++#endif /* CONFIG_M5441X_DISABLE_CACHE */ ++ ++#endif ++ ++#ifndef __ASSEMBLY__ ++ ++extern unsigned long shadow_cacr; ++extern void cacr_set(unsigned long x); ++ ++#endif /* !__ASSEMBLY__ */ ++ ++#endif /* CF_CACHE_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/cfmmu.h +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Definitions for Coldfire V4e MMU ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++#include <asm/movs.h> ++ ++#ifndef __CF_MMU_H__ ++#define __CF_MMU_H__ ++ ++ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) ++#define MMU_BASE 0xE8000000 ++#elif defined(CONFIG_M5441X) ++#define MMU_BASE 0xD8000000 ++#endif ++ ++#define MMUCR (MMU_BASE+0x00) ++#define MMUCR_ASMN 1 ++#define MMUCR_ASM (1<<MMUCR_ASMN) ++#define MMUCR_ENN 0 ++#define MMUCR_EN (1<<MMUCR_ENN) ++ ++#define MMUOR REG16(MMU_BASE+0x04+0x02) ++#define MMUOR_AAN 16 ++#define MMUOR_AA (0xffff<<MMUOR_AAN) ++#define MMUOR_STLBN 8 ++#define MMUOR_STLB (1<<MMUOR_STLBN) ++#define MMUOR_CAN 7 ++#define MMUOR_CA (1<<MMUOR_CAN) ++#define MMUOR_CNLN 6 ++#define MMUOR_CNL (1<<MMUOR_CNLN) ++#define MMUOR_CASN 5 ++#define MMUOR_CAS (1<<MMUOR_CASN) ++#define MMUOR_ITLBN 4 ++#define MMUOR_ITLB (1<<MMUOR_ITLBN) ++#define MMUOR_ADRN 3 ++#define MMUOR_ADR (1<<MMUOR_ADRN) ++#define MMUOR_RWN 2 ++#define MMUOR_RW (1<<MMUOR_RWN) ++#define MMUOR_ACCN 1 ++#define MMUOR_ACC (1<<MMUOR_ACCN) ++#define MMUOR_UAAN 0 ++#define MMUOR_UAA (1<<MMUOR_UAAN) ++ ++#define MMUSR REG32(MMU_BASE+0x08) ++#define MMUSR_SPFN 5 ++#define MMUSR_SPF (1<<MMUSR_SPFN) ++#define MMUSR_RFN 4 ++#define MMUSR_RF (1<<MMUSR_RFN) ++#define MMUSR_WFN 3 ++#define MMUSR_WF (1<<MMUSR_WFN) ++#define MMUSR_HITN 1 ++#define MMUSR_HIT (1<<MMUSR_HITN) ++ ++#define MMUAR REG32(MMU_BASE+0x10) ++#define MMUAR_VPN 1 ++#define MMUAR_VP (0xfffffffe) ++#define MMUAR_SN 0 ++#define MMUAR_S (1<<MMUAR_SN) ++ ++#define MMUTR REG32(MMU_BASE+0x14) ++#define MMUTR_VAN 10 ++#define MMUTR_VA (0xfffffc00) ++#define MMUTR_IDN 2 ++#define MMUTR_ID (0xff<<MMUTR_IDN) ++#define MMUTR_SGN 1 ++#define MMUTR_SG (1<<MMUTR_SGN) ++#define MMUTR_VN 0 ++#define MMUTR_V (1<<MMUTR_VN) ++ ++#define MMUDR REG32(MMU_BASE+0x18) ++#define MMUDR_PAN 10 ++#define MMUDR_PA (0xfffffc00) ++#define MMUDR_SZN 8 ++#define MMUDR_SZ_MASK (0x2<<MMUDR_SZN) ++#define MMUDR_SZ1M (0<<MMUDR_SZN) ++#define MMUDR_SZ4K (1<<MMUDR_SZN) ++#define MMUDR_SZ8K (2<<MMUDR_SZN) ++#define MMUDR_SZ16M (3<<MMUDR_SZN) ++#define MMUDR_CMN 6 ++#define MMUDR_INC (2<<MMUDR_CMN) ++#define MMUDR_IC (0<<MMUDR_CMN) ++#define MMUDR_DWT (0<<MMUDR_CMN) ++#define MMUDR_DCB (1<<MMUDR_CMN) ++#define MMUDR_DNCP (2<<MMUDR_CMN) ++#define MMUDR_DNCIP (3<<MMUDR_CMN) ++#define MMUDR_SPN 5 ++#define MMUDR_SP (1<<MMUDR_SPN) ++#define MMUDR_RN 4 ++#define MMUDR_R (1<<MMUDR_RN) ++#define MMUDR_WN 3 ++#define MMUDR_W (1<<MMUDR_WN) ++#define MMUDR_XN 2 ++#define MMUDR_X (1<<MMUDR_XN) ++#define MMUDR_LKN 1 ++#define MMUDR_LK (1<<MMUDR_LKN) ++ ++ ++#ifndef __ASSEMBLY__ ++#define CF_PMEGS_NUM 256 ++#define CF_INVALID_CONTEXT 255 ++#define CF_PAGE_PGNUM_MASK (PAGE_MASK) ++ ++extern int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, ++ int extension_word); ++#endif /* __ASSEMBLY__*/ ++ ++#endif /* !__CF_MMU_H__ */ +--- a/arch/m68k/include/asm/coldfire.h ++++ b/arch/m68k/include/asm/coldfire.h +@@ -5,6 +5,13 @@ + * + * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo (www.lineo.com) ++ * ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Right Reserved. ++ * Shrek Wu b16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + /****************************************************************************/ +@@ -19,27 +26,78 @@ + * here. Also the peripheral clock (bus clock) divide ratio is set + * at config time too. + */ ++/*FIXME Jason*/ ++#if 0 + #ifdef CONFIG_CLOCK_SET + #define MCF_CLK CONFIG_CLOCK_FREQ + #define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) + #else + #error "Don't know what your ColdFire CPU clock frequency is??" + #endif ++#endif ++ ++ ++#define MCF_CLK CONFIG_MCFCLK ++#define MCF_BUSCLK (CONFIG_MCFCLK/2) ++ ++ ++#if defined(CONFIG_M520x) ++#define MCF_IPSBAR 0xFC000000 ++#else ++#define MCF_IPSBAR 0x40000000 ++#endif + ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++#define MCF_MBAR 0x0 ++/* ++ * Even though RAMBAR1 macro should be in the 0x8xxxxxxx range, ++ * here set the CONFIG_SDRAM_BASE value to it to use ++ * SDRAM memory, not SRAM memory. ++ */ ++#define MCF_RAMBAR1 (CONFIG_SDRAM_BASE) ++#elif defined(CONFIG_M547X_8X) ++#define MCF_MBAR 0xF0000000 ++#define MCF_MMUBAR 0xF1000000 ++#define MCF_RAMBAR0 0xF3000000 ++#define MCF_RAMBAR1 0xF3001000 ++#else + /* + * Define the processor support peripherals base address. + * This is generally setup by the boards start up code. + */ + #define MCF_MBAR 0x10000000 + #define MCF_MBAR2 0x80000000 +-#if defined(CONFIG_M54xx) +-#define MCF_IPSBAR MCF_MBAR +-#elif defined(CONFIG_M520x) +-#define MCF_IPSBAR 0xFC000000 +-#else +-#define MCF_IPSBAR 0x40000000 + #endif + ++#ifdef __ASSEMBLY__ ++#define REG32 ++#define REG16 ++#define REG08 ++#else /* __ASSEMBLY__ */ ++#define REG32(x) ((volatile unsigned long *)(x)) ++#define REG16(x) ((volatile unsigned short *)(x)) ++#define REG08(x) ((volatile unsigned char *)(x)) ++ ++#define MCF_REG32(x) (*(volatile unsigned long *)(MCF_MBAR+(x))) ++#define MCF_REG16(x) (*(volatile unsigned short *)(MCF_MBAR+(x))) ++#define MCF_REG08(x) (*(volatile unsigned char *)(MCF_MBAR+(x))) ++ ++void cacr_set(unsigned long); ++unsigned long cacr_get(void); ++ ++#define coldfire_enable_irq0(irq) MCF_INTC0_CIMR = (irq); ++ ++#define coldfire_enable_irq1(irq) MCF_INTC1_CIMR = (irq); ++ ++#define coldfire_disable_irq0(irq) MCF_INTC0_SIMR = (irq); ++ ++#define coldfire_disable_irq1(irq) MCF_INTC1_SIMR = (irq); ++ ++#define getiprh() MCF_INTC0_IPRH ++ ++#endif /* __ASSEMBLY__ */ ++ ++ + #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M520x) + #undef MCF_MBAR +--- a/arch/m68k/include/asm/delay_mm.h ++++ b/arch/m68k/include/asm/delay_mm.h +@@ -1,18 +1,41 @@ +-#ifndef _M68K_DELAY_H +-#define _M68K_DELAY_H +- +-#include <asm/param.h> +- + /* + * Copyright (C) 1994 Hamish Macdonald + * ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * + * Delay routines, using a pre-computed "loops_per_jiffy" value. + */ + ++#ifndef _M68K_DELAY_H ++#define _M68K_DELAY_H ++ ++#include <asm/param.h> ++ + static inline void __delay(unsigned long loops) + { ++#if defined(CONFIG_COLDFIRE) ++ /* The coldfire runs this loop at significantly different speeds ++ * depending upon long word alignment or not. We'll pad it to ++ * long word alignment which is the faster version. ++ * The 0x4a8e is of course a 'tstl %fp' instruction. This is better ++ * than using a NOP (0x4e71) instruction because it executes in one ++ * cycle not three and doesn't allow for an arbitary delay waiting ++ * for bus cycles to finish. Also fp/a6 isn't likely to cause a ++ * stall waiting for the register to become valid if such is added ++ * to the coldfire at some stage. ++ */ ++ __asm__ __volatile__ (".balignw 4, 0x4a8e\n\t" ++ "1: subql #1, %0\n\t" ++ "jcc 1b" ++ : "=d" (loops) : "0" (loops)); ++#else + __asm__ __volatile__ ("1: subql #1,%0; jcc 1b" + : "=d" (loops) : "0" (loops)); ++#endif + } + + extern void __bad_udelay(void); +@@ -26,12 +49,17 @@ extern void __bad_udelay(void); + */ + static inline void __const_udelay(unsigned long xloops) + { ++#if defined(CONFIG_COLDFIRE) ++ ++ __delay(((((unsigned long long) xloops * loops_per_jiffy))>>32)*HZ); ++#else + unsigned long tmp; + + __asm__ ("mulul %2,%0:%1" + : "=d" (xloops), "=d" (tmp) + : "d" (xloops), "1" (loops_per_jiffy)); + __delay(xloops * HZ); ++#endif + } + + static inline void __udelay(unsigned long usecs) +@@ -46,12 +74,16 @@ static inline void __udelay(unsigned lon + static inline unsigned long muldiv(unsigned long a, unsigned long b, + unsigned long c) + { ++#if defined(CONFIG_COLDFIRE) ++ return (long)(((unsigned long long)a * b)/c); ++#else + unsigned long tmp; + + __asm__ ("mulul %2,%0:%1; divul %3,%0:%1" + : "=d" (tmp), "=d" (a) + : "d" (b), "d" (c), "1" (a)); + return a; ++#endif + } + + #endif /* defined(_M68K_DELAY_H) */ +--- a/arch/m68k/include/asm/div64.h ++++ b/arch/m68k/include/asm/div64.h +@@ -1,12 +1,17 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_DIV64_H + #define _M68K_DIV64_H + +-#ifdef CONFIG_MMU +- ++#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE) + #include <linux/types.h> + + /* n = n / base; return rem; */ +- + #define do_div(n, base) ({ \ + union { \ + unsigned long n32[2]; \ +--- a/arch/m68k/include/asm/dma.h ++++ b/arch/m68k/include/asm/dma.h +@@ -1,7 +1,10 @@ +-#ifndef _M68K_DMA_H +-#define _M68K_DMA_H 1 +- +-#ifdef CONFIG_COLDFIRE ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + /* + * ColdFire DMA Model: + * ColdFire DMA supports two forms of DMA: Single and Dual address. Single +@@ -25,6 +28,11 @@ + * Arthur Shipkowski (art@videon-central.com) + */ + ++#ifndef _M68K_DMA_H ++#define _M68K_DMA_H 1 ++ ++#ifdef CONFIG_COLDFIRE ++ + #include <asm/coldfire.h> + #include <asm/mcfsim.h> + #include <asm/mcfdma.h> +@@ -479,13 +487,106 @@ static __inline__ int get_dma_residue(un + + /* it's useless on the m68k, but unfortunately needed by the new + bootmem allocator (but this should do it for this) */ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) ++#define MAX_DMA_ADDRESS 0xefffffff ++#elif defined(CONFIG_M5441X) ++#define MAX_DMA_ADDRESS 0xdfffffff ++#else + #define MAX_DMA_ADDRESS PAGE_OFFSET ++#endif + ++#ifndef CONFIG_COLDFIRE + #define MAX_DMA_CHANNELS 8 + + extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ + extern void free_dma(unsigned int dmanr); /* release it again */ + ++#else /* not (defined(CONFIG_MCF5474) || defined(CONFIG_MCF5484) ++ || defined(CONFIG_MCF5475) || defined(CONFIG_MCF5485)) */ ++/************************************************ ++ * Multichannel DMA definitions * ++ ************************************************/ ++#ifdef CONFIG_MCD_DMA ++#include <asm/MCD_dma.h> ++#include <asm/m5485dma.h> ++ ++struct scatterlist; ++ ++#define MAX_DMA_CHANNELS NCHANNELS ++/* ++ * identifiers for each initiator/requestor ++ */ ++#define DMA_ALWAYS (0) ++#define DMA_DSPI_RX (1) ++#define DMA_DSPI_TX (2) ++#define DMA_DREQ0 (3) ++#define DMA_PSC0_RX (4) ++#define DMA_PSC0_TX (5) ++#define DMA_USBEP0 (6) ++#define DMA_USBEP1 (7) ++#define DMA_USBEP2 (8) ++#define DMA_USBEP3 (9) ++#define DMA_PCI_TX (10) ++#define DMA_PCI_RX (11) ++#define DMA_PSC1_RX (12) ++#define DMA_PSC1_TX (13) ++#define DMA_I2C_RX (14) ++#define DMA_I2C_TX (15) ++#define DMA_FEC0_RX (16) ++#define DMA_FEC0_TX (17) ++#define DMA_FEC1_RX (18) ++#define DMA_FEC1_TX (19) ++#define DMA_DREQ1 (20) ++#define DMA_CTM0 (21) ++#define DMA_CTM1 (22) ++#define DMA_CTM2 (23) ++#define DMA_CTM3 (24) ++#define DMA_CTM4 (25) ++#define DMA_CTM5 (26) ++#define DMA_CTM6 (27) ++#define DMA_CTM7 (28) ++#define DMA_USBEP4 (29) ++#define DMA_USBEP5 (30) ++#define DMA_USBEP6 (31) ++#define DMA_PSC2_RX (32) ++#define DMA_PSC2_TX (33) ++#define DMA_PSC3_RX (34) ++#define DMA_PSC3_TX (35) ++#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX) ++#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX) ++ ++int dma_set_initiator(int); ++unsigned int dma_get_initiator(int); ++void dma_remove_initiator(int); ++int dma_set_channel(int); ++int dma_get_channel(int); ++void dma_remove_channel(int); ++int dma_set_channel_fec(int requestor); ++int dma_connect(int channel, int address); ++int dma_disconnect(int channel); ++void dma_remove_channel_by_number(int channel); ++int dma_init(void); ++#endif ++ ++extern spinlock_t dma_spin_lock; ++ ++static inline unsigned long claim_dma_lock(void) ++{ ++ unsigned long flags; ++ spin_lock_irqsave(&dma_spin_lock, flags); ++ return flags; ++} ++ ++static inline void release_dma_lock(unsigned long flags) ++{ ++ spin_unlock_irqrestore(&dma_spin_lock, flags); ++} ++#endif ++ ++#ifdef CONFIG_PCI ++extern int isa_dma_bridge_buggy; ++#else + #define isa_dma_bridge_buggy (0) ++#endif + + #endif /* _M68K_DMA_H */ +--- a/arch/m68k/include/asm/elf.h ++++ b/arch/m68k/include/asm/elf.h +@@ -1,10 +1,17 @@ +-#ifndef __ASMm68k_ELF_H +-#define __ASMm68k_ELF_H +- ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + /* + * ELF register definitions.. + */ + ++#ifndef __ASMm68k_ELF_H ++#define __ASMm68k_ELF_H ++ + #include <asm/ptrace.h> + #include <asm/user.h> + +@@ -34,6 +41,26 @@ + #define R_68K_GLOB_DAT 20 + #define R_68K_JMP_SLOT 21 + #define R_68K_RELATIVE 22 ++/* TLS static relocations */ ++#define R_68K_TLS_GD32 25 ++#define R_68K_TLS_GD16 26 ++#define R_68K_TLS_GD8 27 ++#define R_68K_TLS_LDM32 28 ++#define R_68K_TLS_LDM16 29 ++#define R_68K_TLS_LDM8 30 ++#define R_68K_TLS_LDO32 31 ++#define R_68K_TLS_LDO16 32 ++#define R_68K_TLS_LDO8 33 ++#define R_68K_TLS_IE32 34 ++#define R_68K_TLS_IE16 35 ++#define R_68K_TLS_IE8 36 ++#define R_68K_TLS_LE32 37 ++#define R_68K_TLS_LE16 38 ++#define R_68K_TLS_LE8 39 ++/* TLS dynamic relocations */ ++#define R_68K_TLS_DTPMOD32 40 ++#define R_68K_TLS_DTPREL32 41 ++#define R_68K_TLS_TPREL32 42 + + typedef unsigned long elf_greg_t; + +@@ -59,7 +86,7 @@ typedef struct user_m68kfp_struct elf_fp + is actually used on ASV. */ + #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 + +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + #define ELF_EXEC_PAGESIZE 4096 + #else + #define ELF_EXEC_PAGESIZE 8192 +@@ -70,8 +97,10 @@ typedef struct user_m68kfp_struct elf_fp + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + #define ELF_ET_DYN_BASE 0xD0000000UL ++#elif defined(CONFIG_COLDFIRE) ++#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x10000000) + #else + #define ELF_ET_DYN_BASE 0x0D800000UL + #endif +@@ -115,4 +144,35 @@ typedef struct user_m68kfp_struct elf_fp + + #define SET_PERSONALITY(ex) set_personality(PER_LINUX) + ++/* ++ * VDSO ++ */ ++#ifdef CONFIG_VDSO ++extern unsigned int vdso_enabled; ++ ++#define VDSO_BASE ((unsigned long)current->mm->context.vdso) ++#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x)) ++ ++#define VDSO_AUX_ENT \ ++ if (vdso_enabled) \ ++ NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE); ++ ++/* additional pages */ ++#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 ++ ++struct linux_binprm; ++extern int arch_setup_additional_pages(struct linux_binprm *bprm, ++ int executable_stack); ++ ++#else ++/* no VDSO_AUX_ENT */ ++#define VDSO_AUX_ENT ++#endif ++ ++#define ARCH_DLINFO \ ++do { \ ++ /* vdso entry */ \ ++ VDSO_AUX_ENT; \ ++} while (0); ++ + #endif +--- a/arch/m68k/include/asm/io_mm.h ++++ b/arch/m68k/include/asm/io_mm.h +@@ -1,23 +1,36 @@ + /* + * linux/include/asm-m68k/io.h + * ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * + * 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other + * IO access + * - added Q40 support + * - added skeleton for GG-II and Amiga PCMCIA + * 2/3/01 RZ: - moved a few more defs into raw_io.h + * +- * inX/outX should not be used by any driver unless it does +- * ISA access. Other drivers should use function defined in raw_io.h ++ * inX/outX/readX/writeX should not be used by any driver unless it does ++ * ISA or PCI access. Other drivers should use function defined in raw_io.h + * or define its own macros on top of these. + * +- * inX(),outX() are for ISA I/O ++ * inX(),outX() are for PCI and ISA I/O ++ * readX(),writeX() are for PCI memory + * isa_readX(),isa_writeX() are for ISA memory ++ * ++ * moved mem{cpy,set}_*io inside CONFIG_PCI + */ + + #ifndef _IO_H + #define _IO_H + ++#ifdef CONFIG_COLDFIRE ++#include <asm/cf_io.h> ++#else ++ + #ifdef __KERNEL__ + + #include <linux/compiler.h> +@@ -49,6 +62,27 @@ + #define MULTI_ISA 0 + #endif /* Q40 */ + ++/* GG-II Zorro to ISA bridge */ ++#ifdef CONFIG_GG2 ++ ++extern unsigned long gg2_isa_base; ++#define GG2_ISA_IO_B(ioaddr) \ ++ (gg2_isa_base + 1 + ((unsigned long)(ioaddr) * 4)) ++#define GG2_ISA_IO_W(ioaddr) \ ++ (gg2_isa_base + ((unsigned long)(ioaddr) * 4)) ++#define GG2_ISA_MEM_B(madr) \ ++ (gg2_isa_base + 1 + (((unsigned long)(madr) * 4) & 0xfffff)) ++#define GG2_ISA_MEM_W(madr) \ ++ (gg2_isa_base + (((unsigned long)(madr) * 4) & 0xfffff)) ++ ++#ifndef MULTI_ISA ++#define MULTI_ISA 0 ++#else ++#undef MULTI_ISA ++#define MULTI_ISA 1 ++#endif ++#endif /* GG2 */ ++ + #ifdef CONFIG_AMIGA_PCMCIA + #include <asm/amigayle.h> + +@@ -71,17 +105,22 @@ + #undef MULTI_ISA + #endif + +-#define ISA_TYPE_Q40 (1) +-#define ISA_TYPE_AG (2) ++#define Q40_ISA (1) ++#define GG2_ISA (2) ++#define AG_ISA (3) + + #if defined(CONFIG_Q40) && !defined(MULTI_ISA) +-#define ISA_TYPE ISA_TYPE_Q40 ++#define ISA_TYPE Q40_ISA + #define ISA_SEX 0 + #endif + #if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA) +-#define ISA_TYPE ISA_TYPE_AG ++#define ISA_TYPE AG_ISA + #define ISA_SEX 1 + #endif ++#if defined(CONFIG_GG2) && !defined(MULTI_ISA) ++#define ISA_TYPE GG2_ISA ++#define ISA_SEX 0 ++#endif + + #ifdef MULTI_ISA + extern int isa_type; +@@ -98,65 +137,72 @@ extern int isa_sex; + + static inline u8 __iomem *isa_itb(unsigned long addr) + { +- switch(ISA_TYPE) +- { ++ switch (ISA_TYPE) { + #ifdef CONFIG_Q40 +- case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr); ++ case Q40_ISA: return (u8 __iomem *)Q40_ISA_IO_B(addr); ++#endif ++#ifdef CONFIG_GG2 ++ case GG2_ISA: return (u8 __iomem *)GG2_ISA_IO_B(addr); + #endif + #ifdef CONFIG_AMIGA_PCMCIA +- case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr); ++ case AG_ISA: return (u8 __iomem *)AG_ISA_IO_B(addr); + #endif +- default: return NULL; /* avoid warnings, just in case */ +- } ++ default: return NULL; /* avoid warnings, just in case */ ++ } + } + static inline u16 __iomem *isa_itw(unsigned long addr) + { +- switch(ISA_TYPE) +- { ++ switch (ISA_TYPE) { + #ifdef CONFIG_Q40 +- case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr); ++ case Q40_ISA: return (u16 __iomem *)Q40_ISA_IO_W(addr); ++#endif ++#ifdef CONFIG_GG2 ++ case GG2_ISA: return (u16 __iomem *)GG2_ISA_IO_W(addr); + #endif + #ifdef CONFIG_AMIGA_PCMCIA +- case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr); ++ case AG_ISA: return (u16 __iomem *)AG_ISA_IO_W(addr); + #endif +- default: return NULL; /* avoid warnings, just in case */ +- } ++ default: return NULL; /* avoid warnings, just in case */ ++ } + } + static inline u32 __iomem *isa_itl(unsigned long addr) + { +- switch(ISA_TYPE) +- { ++ switch (ISA_TYPE) { + #ifdef CONFIG_AMIGA_PCMCIA +- case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr); ++ case AG_ISA: return (u32 __iomem *)AG_ISA_IO_W(addr); + #endif +- default: return 0; /* avoid warnings, just in case */ +- } ++ default: return 0; /* avoid warnings, just in case */ ++ } + } + static inline u8 __iomem *isa_mtb(unsigned long addr) + { +- switch(ISA_TYPE) +- { ++ switch (ISA_TYPE) { + #ifdef CONFIG_Q40 +- case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr); ++ case Q40_ISA: return (u8 __iomem *)Q40_ISA_MEM_B(addr); ++#endif ++#ifdef CONFIG_GG2 ++ case GG2_ISA: return (u8 __iomem *)GG2_ISA_MEM_B(addr); + #endif + #ifdef CONFIG_AMIGA_PCMCIA +- case ISA_TYPE_AG: return (u8 __iomem *)addr; ++ case AG_ISA: return (u8 __iomem *)addr; + #endif +- default: return NULL; /* avoid warnings, just in case */ +- } ++ default: return NULL; /* avoid warnings, just in case */ ++ } + } + static inline u16 __iomem *isa_mtw(unsigned long addr) + { +- switch(ISA_TYPE) +- { ++ switch (ISA_TYPE) { + #ifdef CONFIG_Q40 +- case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr); ++ case Q40_ISA: return (u16 __iomem *)Q40_ISA_MEM_W(addr); ++#endif ++#ifdef CONFIG_GG2 ++ case GG2_ISA: return (u16 __iomem *)GG2_ISA_MEM_W(addr); + #endif + #ifdef CONFIG_AMIGA_PCMCIA +- case ISA_TYPE_AG: return (u16 __iomem *)addr; ++ case AG_ISA: return (u16 __iomem *)addr; + #endif +- default: return NULL; /* avoid warnings, just in case */ +- } ++ default: return NULL; /* avoid warnings, just in case */ ++ } + } + + +@@ -167,27 +213,30 @@ static inline u16 __iomem *isa_mtw(unsig + #define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val))) + #define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val))) + +-#define isa_readb(p) in_8(isa_mtb((unsigned long)(p))) +-#define isa_readw(p) \ +- (ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \ +- : in_le16(isa_mtw((unsigned long)(p)))) +-#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val)) +-#define isa_writew(val,p) \ +- (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \ +- : out_le16(isa_mtw((unsigned long)(p)),(val))) +- ++#define isa_readb(p) in_8(isa_mtb(p)) ++#define isa_readw(p) (ISA_SEX ? in_be16(isa_mtw(p)) : in_le16(isa_mtw(p))) ++#define isa_writeb(val, p) out_8(isa_mtb(p), (val)) ++#define isa_writew(val, p) \ ++ (ISA_SEX ? out_be16(isa_mtw(p), (val)) : out_le16(isa_mtw(p), (val))) + static inline void isa_delay(void) + { +- switch(ISA_TYPE) +- { ++ switch (ISA_TYPE) { + #ifdef CONFIG_Q40 +- case ISA_TYPE_Q40: isa_outb(0,0x80); break; ++ case Q40_ISA: ++ isa_outb(0, 0x80); ++ break; ++#endif ++#ifdef CONFIG_GG2 ++ case GG2_ISA: ++ break; + #endif + #ifdef CONFIG_AMIGA_PCMCIA +- case ISA_TYPE_AG: break; ++ case AG_ISA: ++ break; + #endif +- default: break; /* avoid warnings */ +- } ++ default: ++ break; /* avoid warnings */ ++ } + } + + #define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;}) +@@ -216,7 +265,10 @@ static inline void isa_delay(void) + (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \ + raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1)) + ++#endif /* CONFIG_ISA */ + ++ ++#if defined(CONFIG_ISA) && !defined(CONFIG_PCI) + #define inb isa_inb + #define inb_p isa_inb_p + #define outb isa_outb +@@ -239,9 +291,80 @@ static inline void isa_delay(void) + #define readw isa_readw + #define writeb isa_writeb + #define writew isa_writew ++#endif /* CONFIG_ISA */ ++ ++#if defined(CONFIG_PCI) ++ ++#define readl(addr) in_le32(addr) ++#define writel(val, addr) out_le32((addr), (val)) ++ ++/* those can be defined for both ISA and PCI - it won't work though */ ++#define readb(addr) in_8(addr) ++#define readw(addr) in_le16(addr) ++#define writeb(val, addr) out_8((addr), (val)) ++#define writew(val, addr) out_le16((addr), (val)) ++ ++#define readb_relaxed(addr) readb(addr) ++#define readw_relaxed(addr) readw(addr) ++#define readl_relaxed(addr) readl(addr) ++ ++#ifndef CONFIG_ISA ++#define inb(port) in_8(port) ++#define outb(val, port) out_8((port), (val)) ++#define inw(port) in_le16(port) ++#define outw(val, port) out_le16((port), (val)) ++#define inl(port) in_le32(port) ++#define outl(val, port) out_le32((port), (val)) ++#define insb(port, buf, nr) \ ++ raw_insb((u8 *)(port), (u8 *)(buf), (nr)) ++#define outsb(port, buf, nr) \ ++ raw_outsb((u8 *)(port), (u8 *)(buf), (nr)) ++#define insw(port, buf, nr) \ ++ raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)) ++#define outsw(port, buf, nr) \ ++ raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)) ++#define insl(port, buf, nr) \ ++ raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) ++#define outsl(port, buf, nr) \ ++ raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) ++ ++#define __raw_readb readb ++#define __raw_readw readw ++#define __raw_readl readl ++#define __raw_writeb writeb ++#define __raw_writew writew ++#define __raw_writel writel + +-#else /* CONFIG_ISA */ ++#else ++/* ++ * kernel with both ISA and PCI compiled in, those have ++ * conflicting defs for in/out. Simply consider port < 1024 ++ * ISA and everything else PCI. read,write not defined ++ * in this case ++ */ ++#define inb(port) ((port) < 1024 ? isa_inb(port) : in_8(port)) ++#define inb_p(port) ((port) < 1024 ? isa_inb_p(port) : in_8(port)) ++#define inw(port) ((port) < 1024 ? isa_inw(port) : in_le16(port)) ++#define inw_p(port) ((port) < 1024 ? isa_inw_p(port) : in_le16(port)) ++#define inl(port) ((port) < 1024 ? isa_inl(port) : in_le32(port)) ++#define inl_p(port) ((port) < 1024 ? isa_inl_p(port) : in_le32(port)) ++ ++#define outb(val, port) (((port) < 1024) ? isa_outb((val), (port)) ++ : out_8((port), (val))) ++#define outb_p(val, port) (((port) < 1024) ? isa_outb_p((val), (port)) ++ : out_8((port), (val))) ++#define outw(val, port) (((port) < 1024) ? isa_outw((val), (port)) ++ : out_le16((port), (val))) ++#define outw_p(val, port) (((port) < 1024) ? isa_outw_p((val), (port)) ++ : out_le16((port), (val))) ++#define outl(val, port) (((port) < 1024) ? isa_outl((val), (port)) ++ : out_le32((port), (val))) ++#define outl_p(val, port) (((port) < 1024) ? isa_outl_p((val), (port)) ++ : out_le32((port), (val))) ++#endif ++#endif /* CONFIG_PCI */ + ++#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI) + /* + * We need to define dummy functions for GENERIC_IOMAP support. + */ +@@ -272,11 +395,11 @@ static inline void isa_delay(void) + #define writeb(val,addr) out_8((addr),(val)) + #define readw(addr) in_le16(addr) + #define writew(val,addr) out_le16((addr),(val)) +- +-#endif /* CONFIG_ISA */ +- ++#endif ++#if !defined(CONFIG_PCI) + #define readl(addr) in_le32(addr) + #define writel(val,addr) out_le32((addr),(val)) ++#endif + + #define mmiowb() + +@@ -333,4 +456,5 @@ static inline void memcpy_toio(volatile + */ + #define xlate_dev_kmem_ptr(p) p + ++#endif /* CONFIG_COLDFIRE */ + #endif /* _IO_H */ +--- a/arch/m68k/include/asm/irq.h ++++ b/arch/m68k/include/asm/irq.h +@@ -1,14 +1,20 @@ +-#ifndef _M68K_IRQ_H_ +-#define _M68K_IRQ_H_ +- + /* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * + * This should be the same as the max(NUM_X_SOURCES) for all the + * different m68k hosts compiled into the kernel. + * Currently the Atari has 72 and the Amiga 24, but if both are + * supported in the kernel it is better to make room for 72. + */ ++#ifndef _M68K_IRQ_H_ ++#define _M68K_IRQ_H_ + #if defined(CONFIG_COLDFIRE) +-#define NR_IRQS 256 ++#define SYS_IRQS 256 ++#define NR_IRQS SYS_IRQS + #elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X) + #define NR_IRQS 200 + #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) +--- a/arch/m68k/include/asm/machdep.h ++++ b/arch/m68k/include/asm/machdep.h +@@ -1,6 +1,12 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_MACHDEP_H + #define _M68K_MACHDEP_H +- + #include <linux/seq_file.h> + #include <linux/interrupt.h> + +@@ -42,4 +48,11 @@ extern irqreturn_t arch_timer_interrupt( + extern void config_BSP(char *command, int len); + extern void do_IRQ(int irq, struct pt_regs *fp); + ++#ifdef CONFIG_COLDFIRE ++extern void __init config_coldfire(void); ++extern void __init mmu_context_init(void); ++extern irq_handler_t mach_default_handler; ++extern void (*mach_tick)(void); ++#endif ++ + #endif /* _M68K_MACHDEP_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcfdspi.h +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * ++ * This file is based on mcfqspi.h ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.001 25 March 2008 Andrey Butok ++ * Initial Release - developed on uClinux with 2.6.23 kernel. ++ * ++ */ ++ ++#ifndef MCFDSPI_H_ ++#define MCFDSPI_H_ ++ ++struct coldfire_dspi_chip { ++ u8 mode; ++ u8 bits_per_word; ++ u16 void_write_data; ++ /* Only used in master mode */ ++ u8 dbr; /* Double baud rate */ ++ u8 pbr; /* Baud rate prescaler */ ++ u8 br; /* Baud rate scaler */ ++ u8 pcssck; /* PCS to SCK delay prescaler */ ++ u8 pasc; /* After SCK delay prescaler */ ++ u8 pdt; /* Delay after transfer prescaler */ ++ u8 cssck; /* PCS to SCK delay scaler */ ++ u8 asc; /* After SCK delay scaler */ ++ u8 dt; /* Delay after transfer scaler */ ++}; ++ ++struct coldfire_spi_master { ++ u16 bus_num; ++ u16 num_chipselect; ++ u8 irq_source; ++ u32 irq_vector; ++ u32 irq_mask; ++ u8 irq_lp; ++ u8 par_val; ++ u16 par_val16; ++ u32 *irq_list; ++ void (*cs_control)(u8 cs, u8 command); ++}; ++#endif /*MCFDSPI_H_*/ +--- a/arch/m68k/include/asm/mcfsim.h ++++ b/arch/m68k/include/asm/mcfsim.h +@@ -5,6 +5,12 @@ + * + * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + /****************************************************************************/ +@@ -45,5 +51,120 @@ + #include <asm/m54xxsim.h> + #endif + ++#if defined(CONFIG_COLDFIRE) ++#include <asm/coldfire.h> ++#endif ++ ++#if defined(CONFIG_M5445X) ++#include <asm/mcf5445x_intc.h> ++#include <asm/mcf5445x_gpio.h> ++#include <asm/mcf5445x_ccm.h> ++#include <asm/mcf5445x_eport.h> ++#include <asm/mcf5445x_fbcs.h> ++#include <asm/mcf5445x_xbs.h> ++#include <asm/mcf5445x_dtim.h> ++#include <asm/mcf5445x_rtc.h> ++#include <asm/mcf5445x_scm.h> ++#elif defined(CONFIG_M547X_8X) ++#include <asm/m5485sim.h> ++#include <asm/m5485gpio.h> ++#include <asm/m5485gpt.h> ++#elif defined(CONFIG_M5441X) ++#include <asm/mcf5441x_intc.h> ++#include <asm/mcf5441x_gpio.h> ++#include <asm/mcf5441x_ccm.h> ++#include <asm/mcf5441x_eport.h> ++#include <asm/mcf5441x_fbcs.h> ++#include <asm/mcf5441x_xbs.h> ++#include <asm/mcf5441x_dtim.h> ++#include <asm/mcf5441x_rtc.h> ++#include <asm/mcf5441x_scm.h> ++#include <asm/mcf5441x_pm.h> ++#include <asm/mcf5441x_flexcan.h> ++#include <asm/mcf5441x_clock.h> ++#endif ++ ++/* ++ * Define the base address of the SIM within the MBAR address space. ++ */ ++#define MCFSIM_BASE 0x0 /* Base address of SIM */ ++ ++ ++/* ++ * Bit definitions for the ICR family of registers. ++ */ ++#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ ++#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ ++#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ ++#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ ++#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ ++#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ ++#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ ++#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ ++#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ ++ ++#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ ++#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ ++#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ ++#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ ++ ++/* ++ * Bit definitions for the Interrupt Mask register (IMR). ++ */ ++#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */ ++#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */ ++#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */ ++#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */ ++#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */ ++#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */ ++#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */ ++ ++#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */ ++#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */ ++#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */ ++#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */ ++#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */ ++#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */ ++ ++#if defined(CONFIG_M5206e) ++#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */ ++#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */ ++#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) ++#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */ ++#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */ ++#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */ ++#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */ ++#endif ++ ++/* ++ * Mask for all of the SIM devices. Some parts have more or less ++ * SIM devices. This is a catchall for the sandard set. ++ */ ++#ifndef MCFSIM_IMR_MASKALL ++#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ ++#endif ++ ++ ++/* ++ * PIT interrupt settings, if not found in mXXXXsim.h file. ++ */ ++#ifndef ICR_INTRCONF ++#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */ ++#endif ++#ifndef MCFPIT_IMR ++#define MCFPIT_IMR MCFINTC_IMRH ++#endif ++#ifndef MCFPIT_IMR_IBIT ++#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32)) ++#endif ++ ++ ++#ifndef __ASSEMBLY__ ++/* ++ * Definition for the interrupt auto-vectoring support. ++ */ ++extern void mcf_autovector(unsigned int vec); ++#endif /* __ASSEMBLY__ */ ++ + /****************************************************************************/ + #endif /* mcfsim_h */ +--- a/arch/m68k/include/asm/mcfuart.h ++++ b/arch/m68k/include/asm/mcfuart.h +@@ -5,6 +5,11 @@ + * + * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + /****************************************************************************/ +@@ -12,6 +17,59 @@ + #define mcfuart_h + /****************************************************************************/ + ++#if defined(CONFIG_M5445X) ++#include <asm/mcf5445x_intc.h> ++#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ ++#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ ++#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ ++#define MCFINT_VECBASE 64 ++#define MCFINT_UART0 26 ++#define MCFINT_UART1 27 ++#elif defined(CONFIG_M547X_8X) ++#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ ++#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ ++#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ ++#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ ++#define MCFINT_VECBASE 64 ++#define MCFINT_UART0 35 ++#define MCFINT_UART1 34 ++#define MCFINT_UART2 33 ++#define MCFINT_UART3 32 ++#elif defined(CONFIG_M5441X) ++#define MCFUART_BASE0 0xfc060000 /* Base address of UART1 */ ++#define MCFUART_BASE1 0xfc064000 /* Base address of UART2 */ ++#define MCFUART_BASE2 0xfc068000 /* Base address of UART3 */ ++#define MCFUART_BASE3 0xfc06C000 /* Base address of UART4 */ ++#define MCFUART_BASE4 0xec060000 ++#define MCFUART_BASE5 0xec064000 ++#define MCFUART_BASE6 0xec068000 ++#define MCFUART_BASE7 0xec06C000 ++#define MCFUART_BASE8 0xec070000 ++#define MCFUART_BASE9 0xec074000 ++ ++#define MCFINT0_VECBASE 64 ++#define MCFINT1_VECBASE (64 + 64) ++#define MCFINT_UART0 26 ++#define MCFINT_UART1 27 ++#define MCFINT_UART2 28 ++#define MCFINT_UART3 29 ++#define MCFINT_UART4 48 ++#define MCFINT_UART5 49 ++#define MCFINT_UART6 50 ++#define MCFINT_UART7 51 ++#define MCFINT_UART8 52 ++#define MCFINT_UART9 53 ++#endif ++ ++#if defined(CONFIG_M5441X) ++#define MAX_PORT_NUM 10 ++#elif defined(CONFIG_M547X_8X) ++#define MAX_PORT_NUM 4 ++#else ++#define MAX_PORT_NUM 3 ++#endif ++ ++#ifndef __ASSEMBLY__ + #include <linux/serial_core.h> + #include <linux/platform_device.h> + +@@ -21,6 +79,7 @@ struct mcf_platform_uart { + unsigned int irq; /* Interrupt vector */ + unsigned int uartclk; /* UART clock rate */ + }; ++#endif + + /* + * Define the ColdFire UART register set addresses. +@@ -94,6 +153,11 @@ struct mcf_platform_uart { + #define MCFUART_USR_RXFULL 0x02 /* Receiver full */ + #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ + ++#if defined(CONFIG_M547X_8X) ++#define MCFUART_USR_TXREADY_BN 0x0a ++#define MCFUART_USR_TXEMPTY_BN 0x0b ++#endif ++ + #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ + MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) + +--- a/arch/m68k/include/asm/mmu.h ++++ b/arch/m68k/include/asm/mmu.h +@@ -1,9 +1,22 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef __MMU_H + #define __MMU_H +- + #ifdef CONFIG_MMU ++#ifdef CONFIG_VDSO ++typedef struct { ++ unsigned long id; ++ void *vdso; ++} mm_context_t; ++#else + /* Default "unsigned long" context */ + typedef unsigned long mm_context_t; ++#endif + #else + typedef struct { + unsigned long end_brk; +--- a/arch/m68k/include/asm/mmu_context.h ++++ b/arch/m68k/include/asm/mmu_context.h +@@ -1,14 +1,21 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef __M68K_MMU_CONTEXT_H + #define __M68K_MMU_CONTEXT_H +- + #include <asm-generic/mm_hooks.h> ++#include <asm-generic/pgtable.h> + + static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) + { + } + + #ifdef CONFIG_MMU +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + + #include <asm/setup.h> + #include <asm/page.h> +@@ -103,7 +110,7 @@ static inline void activate_mm(struct mm + switch_mm_0460(next_mm); + } + +-#else /* CONFIG_SUN3 */ ++#elif defined(CONFIG_SUN3) + #include <asm/sun3mmu.h> + #include <linux/sched.h> + +@@ -151,7 +158,178 @@ static inline void activate_mm(struct mm + activate_context(next_mm); + } + ++#else /* CONFIG_COLDFIRE */ ++ ++#include <asm/coldfire.h> ++#include <asm/atomic.h> ++#include <asm/bitops.h> ++#include <asm/mmu.h> ++ ++#define NO_CONTEXT 256 ++#define LAST_CONTEXT 255 ++#define FIRST_CONTEXT 1 ++ ++#ifdef CONFIG_VDSO ++#define cpu_context(mm) ((mm)->context.id) ++#else ++#define cpu_context(mm) ((mm)->context) ++#endif ++ ++#ifdef CONFIG_VDSO ++extern void set_context(unsigned long context, pgd_t *pgd); ++#else ++extern void set_context(mm_context_t context, pgd_t *pgd); + #endif ++extern unsigned long context_map[]; ++#ifdef CONFIG_VDSO ++extern unsigned long next_mmu_context; ++#else ++extern mm_context_t next_mmu_context; ++#endif ++ ++extern atomic_t nr_free_contexts; ++extern struct mm_struct *context_mm[LAST_CONTEXT+1]; ++extern void steal_context(void); ++ ++static inline void get_mmu_context(struct mm_struct *mm) ++{ ++#ifdef CONFIG_VDSO ++ unsigned long ctx; ++#else ++ mm_context_t ctx; ++#endif ++ ++ if (cpu_context(mm) != NO_CONTEXT) ++ return; ++ while (atomic_dec_and_test_lt(&nr_free_contexts)) { ++ atomic_inc(&nr_free_contexts); ++ steal_context(); ++ } ++ ctx = next_mmu_context; ++ while (test_and_set_bit(ctx, context_map)) { ++ ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); ++ if (ctx > LAST_CONTEXT) ++ ctx = 0; ++ } ++ next_mmu_context = (ctx + 1) & LAST_CONTEXT; ++ cpu_context(mm) = ctx; ++ context_mm[ctx] = mm; ++} ++ ++/* ++ * Set up the context for a new address space. ++ */ ++#define init_new_context(tsk, mm) ((cpu_context(mm) = NO_CONTEXT), 0) ++/* #define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0) */ ++ ++/* ++ * We're finished using the context for an address space. ++ */ ++static inline void destroy_context(struct mm_struct *mm) ++{ ++ if (cpu_context(mm) != NO_CONTEXT) { ++ clear_bit(cpu_context(mm), context_map); ++ cpu_context(mm) = NO_CONTEXT; ++ atomic_inc(&nr_free_contexts); ++ } ++} ++ ++static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, ++ struct task_struct *tsk) ++{ ++ get_mmu_context(tsk->mm); ++ set_context(cpu_context(tsk->mm), next->pgd); ++} ++ ++/* ++ * After we have set current->mm to a new value, this activates ++ * the context for the new mm so we see the new mappings. ++ */ ++static inline void activate_mm(struct mm_struct *active_mm, ++ struct mm_struct *mm) ++{ ++ get_mmu_context(mm); ++ set_context(cpu_context(mm), mm->pgd); ++} ++ ++#define deactivate_mm(tsk, mm) do { } while (0) ++ ++extern void mmu_context_init(void); ++#if defined(CONFIG_M547X_8X) ++#define prepare_arch_switch(next) load_ksp_mmu(next) ++ ++static inline void load_ksp_mmu(struct task_struct *task) ++{ ++ unsigned long flags; ++ struct mm_struct *mm; ++ int asid; ++ pgd_t *pgd; ++ pmd_t *pmd; ++ pte_t *pte; ++ unsigned long mmuar; ++ ++ local_irq_save(flags); ++ mmuar = task->thread.ksp; ++ ++ /* Search for a valid TLB entry, if one is found, don't remap */ ++ *MMUAR = mmuar; ++ *MMUOR = MMUOR_STLB | MMUOR_ADR; ++ if ((*MMUSR) & MMUSR_HIT) ++ goto end; ++ ++ if (mmuar >= PAGE_OFFSET) { ++ mm = &init_mm; ++ } else { ++ printk(KERN_INFO "load_ksp_mmu: non-kernel" ++ " mm found: 0x%08x\n", ++ (unsigned int) task->mm); ++ mm = task->mm; ++ } ++ ++ if (!mm) ++ goto bug; ++ ++ pgd = pgd_offset(mm, mmuar); ++ if (pgd_none(*pgd)) ++ goto bug; ++ ++ pmd = pmd_offset(pgd, mmuar); ++ if (pmd_none(*pmd)) ++ goto bug; ++ ++ pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar) ++ : pte_offset_map(pmd, mmuar); ++ if (pte_none(*pte) || !pte_present(*pte)) ++ goto bug; ++ ++ set_pte(pte, pte_mkyoung(*pte)); ++ asid = cpu_context(mm) & 0xff; ++ if (!pte_dirty(*pte) && mmuar <= PAGE_OFFSET) ++ set_pte(pte, pte_wrprotect(*pte)); ++ ++ *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT) ++ | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK) ++ >> CF_PAGE_MMUTR_SHIFT) ++ | MMUTR_V; ++ ++ *MMUDR = (pte_val(*pte) & PAGE_MASK) ++ | ((pte->pte) & CF_PAGE_MMUDR_MASK) ++ | MMUDR_SZ8K | MMUDR_X; ++ ++ *MMUOR = MMUOR_ACC | MMUOR_UAA; ++ asm ("nop"); ++ ++ goto end; ++ ++bug: ++ printk(KERN_ERR "ksp load failed: mm=0x%08x ksp=0x%08x\n", ++ (unsigned int) mm, (unsigned int) mmuar); ++end: ++ local_irq_restore(flags); ++} ++#endif /* CONFIG_M547X_8X */ ++#endif /* CONFIG_COLDFIRE */ ++ + #else /* !CONFIG_MMU */ + + static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) +--- a/arch/m68k/include/asm/page.h ++++ b/arch/m68k/include/asm/page.h +@@ -1,12 +1,18 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_PAGE_H + #define _M68K_PAGE_H +- + #include <linux/const.h> + #include <asm/setup.h> + #include <asm/page_offset.h> + + /* PAGE_SHIFT determines the page size */ +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + #define PAGE_SHIFT (12) + #else + #define PAGE_SHIFT (13) +--- a/arch/m68k/include/asm/page_mm.h ++++ b/arch/m68k/include/asm/page_mm.h +@@ -1,5 +1,17 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_PAGE_MM_H + #define _M68K_PAGE_MM_H ++#if PAGE_SHIFT < 13 ++#define THREAD_SIZE (8192) ++#else ++#define THREAD_SIZE PAGE_SIZE ++#endif + + #ifndef __ASSEMBLY__ + +@@ -70,6 +82,49 @@ extern unsigned long m68k_memoffset; + + #define WANT_PAGE_VIRTUAL + ++#if defined(CONFIG_COLDFIRE) ++extern unsigned long cf_dma_base; ++extern unsigned long cf_dma_end; ++ ++static inline unsigned long ___pa(void *vaddr) ++{ ++#if CONFIG_SDRAM_BASE != PAGE_OFFSET ++ return ((unsigned long)vaddr & 0x0fffffff) + CONFIG_SDRAM_BASE; ++#else ++ if ((unsigned long)vaddr >= CONFIG_DMA_BASE && ++ (unsigned long)vaddr < (CONFIG_DMA_BASE + CONFIG_DMA_SIZE)) { ++ /* address is in carved out DMA range */ ++ return ((unsigned long)vaddr - CONFIG_DMA_BASE) ++ + CONFIG_SDRAM_BASE; ++ } else if ((unsigned long)vaddr >= PAGE_OFFSET && ++ (unsigned long)vaddr < (PAGE_OFFSET + CONFIG_SDRAM_SIZE)) { ++ /* normal mapping */ ++ return ((unsigned long)vaddr - PAGE_OFFSET) + CONFIG_SDRAM_BASE; ++ } ++ ++ return (unsigned long)vaddr; ++#endif ++} ++#define __pa(vaddr) ___pa((void *)(vaddr)) ++ ++static inline void *__va(unsigned long paddr) ++{ ++#if CONFIG_SDRAM_BASE != PAGE_OFFSET ++ return (void *)((paddr & 0x0fffffff) + PAGE_OFFSET); ++#else ++ if (paddr >= cf_dma_base && paddr <= cf_dma_end) { ++ /* mapped address for DMA */ ++ return (void *)((paddr - CONFIG_SDRAM_BASE) + CONFIG_DMA_BASE); ++ } else if (paddr >= cf_dma_end && ++ paddr < (CONFIG_SDRAM_BASE + CONFIG_SDRAM_SIZE)) { ++ /* normal mapping */ ++ return (void *)((paddr - CONFIG_SDRAM_BASE) + PAGE_OFFSET); ++ } ++ return (void *)paddr; ++#endif ++} ++ ++#else + static inline unsigned long ___pa(void *vaddr) + { + unsigned long paddr; +@@ -91,6 +146,7 @@ static inline void *__va(unsigned long p + : "0" (paddr), "i" (m68k_fixup_memoffset)); + return vaddr; + } ++#endif + + #else /* !CONFIG_SUN3 */ + /* This #define is a horrible hack to suppress lots of warnings. --m */ +@@ -176,4 +232,9 @@ static inline __attribute_const__ int __ + #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + ++#ifdef CONFIG_VDSO ++/* vDSO support */ ++#define __HAVE_ARCH_GATE_AREA ++#endif ++ + #endif /* _M68K_PAGE_MM_H */ +--- a/arch/m68k/include/asm/page_offset.h ++++ b/arch/m68k/include/asm/page_offset.h +@@ -1,10 +1,21 @@ +-/* This handles the memory map.. */ +- ++/* ++ * Page and physical memory maps. ++ * ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifdef CONFIG_MMU +-#ifndef CONFIG_SUN3 +-#define PAGE_OFFSET_RAW 0x00000000 +-#else ++#if defined(CONFIG_SUN3) + #define PAGE_OFFSET_RAW 0x0E000000 ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) \ ++ || defined(CONFIG_M5441X) ++#define PHYS_OFFSET CONFIG_SDRAM_BASE ++#define PAGE_OFFSET_RAW (PHYS_OFFSET) ++#else ++#define PAGE_OFFSET_RAW 0x00000000 + #endif + #else + #define PAGE_OFFSET_RAW CONFIG_RAMBASE +--- a/arch/m68k/include/asm/pgalloc.h ++++ b/arch/m68k/include/asm/pgalloc.h +@@ -1,14 +1,22 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef M68K_PGALLOC_H + #define M68K_PGALLOC_H +- + #include <linux/mm.h> + #include <linux/highmem.h> + #include <asm/setup.h> + + #ifdef CONFIG_MMU + #include <asm/virtconvert.h> +-#ifdef CONFIG_SUN3 ++#if defined(CONFIG_SUN3) + #include <asm/sun3_pgalloc.h> ++#elif defined(CONFIG_COLDFIRE) ++#include <asm/cf_pgalloc.h> + #else + #include <asm/motorola_pgalloc.h> + #endif +--- a/arch/m68k/include/asm/pgtable_mm.h ++++ b/arch/m68k/include/asm/pgtable_mm.h +@@ -1,6 +1,12 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_PGTABLE_H + #define _M68K_PGTABLE_H +- + #include <asm-generic/4level-fixup.h> + + #include <asm/setup.h> +@@ -40,6 +46,8 @@ + /* PGDIR_SHIFT determines what a third-level page table entry can map */ + #ifdef CONFIG_SUN3 + #define PGDIR_SHIFT 17 ++#elif defined(CONFIG_COLDFIRE) ++#define PGDIR_SHIFT 22 + #else + #define PGDIR_SHIFT 25 + #endif +@@ -54,6 +62,10 @@ + #define PTRS_PER_PTE 16 + #define PTRS_PER_PMD 1 + #define PTRS_PER_PGD 2048 ++#elif defined(CONFIG_COLDFIRE) ++#define PTRS_PER_PTE 512 ++#define PTRS_PER_PMD 1 ++#define PTRS_PER_PGD 1024 + #else + #define PTRS_PER_PTE 1024 + #define PTRS_PER_PMD 8 +@@ -66,6 +78,18 @@ + #ifdef CONFIG_SUN3 + #define KMAP_START 0x0DC00000 + #define KMAP_END 0x0E000000 ++#elif defined(CONFIG_COLDFIRE) ++#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) ++#define VMALLOC_START 0xc0000000 ++#define VMALLOC_END 0xcfffffff ++#define KMAP_START (VMALLOC_END + 1) ++#define KMAP_END (0xe8000000 - 1) ++#elif defined(CONFIG_M5441X) ++#define VMALLOC_START 0xc0000000 ++#define VMALLOC_END 0xcfffffff ++#define KMAP_START (VMALLOC_END + 1) ++#define KMAP_END (0xd8000000 - 1) ++#endif + #else + #define KMAP_START 0xd0000000 + #define KMAP_END 0xf0000000 +@@ -79,9 +103,11 @@ + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ ++#if !defined(CONFIG_COLDFIRE) + #define VMALLOC_OFFSET (8*1024*1024) + #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) + #define VMALLOC_END KMAP_START ++#endif + #else + extern unsigned long m68k_vmalloc_end; + #define VMALLOC_START 0x0f800000 +@@ -130,6 +156,8 @@ static inline void update_mmu_cache(stru + + #ifdef CONFIG_SUN3 + #include <asm/sun3_pgtable.h> ++#elif defined(CONFIG_COLDFIRE) ++#include <asm/cf_pgtable.h> + #else + #include <asm/motorola_pgtable.h> + #endif +@@ -143,6 +171,10 @@ static inline void update_mmu_cache(stru + #else + # define __SUN3_PAGE_NOCACHE 0 + #endif ++ ++#ifdef CONFIG_COLDFIRE ++# define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE)) ++#else /* CONFIG_COLDFIRE */ + #define pgprot_noncached(prot) \ + (MMU_IS_SUN3 \ + ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \ +@@ -151,7 +183,7 @@ static inline void update_mmu_cache(stru + : (MMU_IS_040 || MMU_IS_060) \ + ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \ + : (prot))) +- ++#endif /* CONFIG_COLDFIRE */ + #include <asm-generic/pgtable.h> + #endif /* !__ASSEMBLY__ */ + +--- a/arch/m68k/include/asm/processor.h ++++ b/arch/m68k/include/asm/processor.h +@@ -2,6 +2,11 @@ + * include/asm-m68k/processor.h + * + * Copyright (C) 1995 Hamish Macdonald ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + #ifndef __ASM_M68K_PROCESSOR_H +@@ -23,6 +28,10 @@ static inline unsigned long rdusp(void) + #ifdef CONFIG_COLDFIRE_SW_A7 + extern unsigned int sw_usp; + return sw_usp; ++#elif defined(CONFIG_COLDFIRE) ++ unsigned long usp; ++ __asm__ __volatile__("movel %/usp,%0" : "=a" (usp)); ++ return usp; + #else + register unsigned long usp __asm__("a0"); + /* move %usp,%a0 */ +@@ -36,6 +45,8 @@ static inline void wrusp(unsigned long u + #ifdef CONFIG_COLDFIRE_SW_A7 + extern unsigned int sw_usp; + sw_usp = usp; ++#elif defined(CONFIG_COLDFIRE) ++ __asm__ __volatile__("movel %0,%/usp" : : "a" (usp)); + #else + register unsigned long a0 __asm__("a0") = usp; + /* move %a0,%usp */ +@@ -48,11 +59,17 @@ static inline void wrusp(unsigned long u + * so don't change it unless you know what you are doing. + */ + #ifdef CONFIG_MMU +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + #define TASK_SIZE (0xF0000000UL) ++#elif defined(CONFIG_COLDFIRE) ++#define TASK_SIZE (0xC0000000UL) ++#else /* CONFIG_SUN3 */ ++#ifdef __ASSEMBLY__ ++#define TASK_SIZE (0x0E000000) + #else + #define TASK_SIZE (0x0E000000UL) + #endif ++#endif + #else + #define TASK_SIZE (0xFFFFFFFFUL) + #endif +@@ -66,8 +83,10 @@ static inline void wrusp(unsigned long u + * space during mmap's. + */ + #ifdef CONFIG_MMU +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + #define TASK_UNMAPPED_BASE 0xC0000000UL ++#elif defined(CONFIG_COLDFIRE) ++#define TASK_UNMAPPED_BASE 0x60000000UL + #else + #define TASK_UNMAPPED_BASE 0x0A000000UL + #endif +@@ -80,7 +99,11 @@ struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned short sr; /* saved status register */ ++#ifndef CONFIG_COLDFIRE + unsigned short fs; /* saved fs (sfc, dfc) */ ++#else ++ mm_segment_t fs; ++#endif + unsigned long crp[2]; /* cpu root pointer */ + unsigned long esp0; /* points to SR of stack frame */ + unsigned long faddr; /* info about last fault */ +@@ -102,6 +125,7 @@ struct thread_struct { + /* + * Do necessary setup to start up a newly executed thread. + */ ++#ifndef CONFIG_COLDFIRE + static inline void start_thread(struct pt_regs * regs, unsigned long pc, + unsigned long usp) + { +@@ -112,7 +136,24 @@ static inline void start_thread(struct p + regs->sr &= ~0x2000; + wrusp(usp); + } ++#else ++/* ++ * Do necessary setup to start up a newly executed thread. ++ * ++ * pass the data segment into user programs if it exists, ++ * it can't hurt anything as far as I can tell ++ */ ++#define start_thread(_regs, _pc, _usp) \ ++do { \ ++ set_fs(USER_DS); /* reads from user space */ \ ++ (_regs)->pc = (_pc); \ ++ if (current->mm) \ ++ (_regs)->d5 = current->mm->start_data; \ ++ (_regs)->sr &= ~0x2000; \ ++ wrusp(_usp); \ ++} while (0) + ++#endif + #else + + /* +--- a/arch/m68k/include/asm/ptrace.h ++++ b/arch/m68k/include/asm/ptrace.h +@@ -1,3 +1,10 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_PTRACE_H + #define _M68K_PTRACE_H + +@@ -27,27 +34,38 @@ + stack during a system call. */ + + struct pt_regs { +- long d1; +- long d2; +- long d3; +- long d4; +- long d5; +- long a0; +- long a1; +- long a2; +- long d0; +- long orig_d0; +- long stkadj; ++ long d1; ++ long d2; ++ long d3; ++ long d4; ++ long d5; ++ long a0; ++ long a1; ++ long a2; ++ long d0; ++ long orig_d0; ++ long stkadj; + #ifdef CONFIG_COLDFIRE ++#if 0 + unsigned format : 4; /* frame format specifier */ + unsigned vector : 12; /* vector offset */ + unsigned short sr; + unsigned long pc; ++#endif ++/*FROM BSP*/ ++ unsigned long mmuar; ++ unsigned long mmusr; ++ unsigned format:4; /* frame format specifier */ ++ unsigned fs2:2; ++ unsigned vector:8; ++ unsigned fs1:2; ++ unsigned short sr; ++ unsigned long pc; + #else +- unsigned short sr; +- unsigned long pc; +- unsigned format : 4; /* frame format specifier */ +- unsigned vector : 12; /* vector offset */ ++ unsigned short sr; ++ unsigned long pc; ++ unsigned format:4; /* frame format specifier */ ++ unsigned vector:12; /* vector offset */ + #endif + }; + +--- a/arch/m68k/include/asm/raw_io.h ++++ b/arch/m68k/include/asm/raw_io.h +@@ -3,11 +3,19 @@ + * + * 10/20/00 RZ: - created from bits of io.h and ide.h to cleanup namespace + * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ +- + #ifndef _RAW_IO_H + #define _RAW_IO_H + ++#ifdef CONFIG_COLDFIRE ++#include <asm/cf_raw_io.h> ++#else ++ + #ifdef __KERNEL__ + + #include <asm/types.h> +@@ -60,6 +68,9 @@ extern void __iounmap(void *addr, unsign + #define __raw_writew(val,addr) out_be16((addr),(val)) + #define __raw_writel(val,addr) out_be32((addr),(val)) + ++#define swap_inw(port) in_le16((port)) ++#define swap_outw(val, port) out_le16((port), (val)) ++ + static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len) + { + unsigned int i; +@@ -344,4 +355,6 @@ static inline void raw_outsw_swapw(volat + + #endif /* __KERNEL__ */ + ++#endif /* CONFIG_COLDFIRE */ ++ + #endif /* _RAW_IO_H */ +--- a/arch/m68k/include/asm/segment.h ++++ b/arch/m68k/include/asm/segment.h +@@ -1,3 +1,10 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_SEGMENT_H + #define _M68K_SEGMENT_H + +@@ -29,6 +36,7 @@ typedef struct { + * Get/set the SFC/DFC registers for MOVES instructions + */ + ++#ifndef CONFIG_COLDFIRE + static inline mm_segment_t get_fs(void) + { + #ifdef CONFIG_MMU +@@ -56,6 +64,15 @@ static inline void set_fs(mm_segment_t v + #endif + } + ++#else /* CONFIG_COLDFIRE */ ++ ++#include <asm/current.h> ++#define get_fs() (current->thread.fs) ++#define set_fs(val) (current->thread.fs = (val)) ++#define get_ds() (KERNEL_DS) ++ ++#endif /* CONFIG_COLDFIRE */ ++ + #define segment_eq(a,b) ((a).seg == (b).seg) + + #endif /* __ASSEMBLY__ */ +--- a/arch/m68k/include/asm/setup.h ++++ b/arch/m68k/include/asm/setup.h +@@ -2,6 +2,7 @@ + ** asm/setup.h -- Definition of the Linux/m68k setup information + ** + ** Copyright 1992 by Greg Harp ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. + ** + ** This file is subject to the terms and conditions of the GNU General Public + ** License. See the file COPYING in the main directory of this archive +@@ -40,6 +41,7 @@ + #define MACH_HP300 9 + #define MACH_Q40 10 + #define MACH_SUN3X 11 ++#define MACH_CFMMU 12 + + #define COMMAND_LINE_SIZE 256 + +@@ -189,6 +191,14 @@ extern unsigned long m68k_machtype; + # define MACH_TYPE (MACH_SUN3X) + #endif + ++#if !defined(CONFIG_COLDFIRE) ++# define MACH_IS_COLDFIRE (0) ++#else ++# define CONFIG_COLDFIRE_ONLY ++# define MACH_IS_COLDFIRE (1) ++# define MACH_TYPE (MACH_CFMMU) ++#endif ++ + #ifndef MACH_TYPE + # define MACH_TYPE (m68k_machtype) + #endif +@@ -211,23 +221,31 @@ extern unsigned long m68k_machtype; + #define CPUB_68030 1 + #define CPUB_68040 2 + #define CPUB_68060 3 ++#define CPUB_CFV4E 4 + + #define CPU_68020 (1<<CPUB_68020) + #define CPU_68030 (1<<CPUB_68030) + #define CPU_68040 (1<<CPUB_68040) + #define CPU_68060 (1<<CPUB_68060) ++#define CPU_CFV4E (1<<CPUB_CFV4E) + + #define FPUB_68881 0 + #define FPUB_68882 1 + #define FPUB_68040 2 /* Internal FPU */ + #define FPUB_68060 3 /* Internal FPU */ + #define FPUB_SUNFPA 4 /* Sun-3 FPA */ ++#define FPUB_CFV4E 5 + + #define FPU_68881 (1<<FPUB_68881) + #define FPU_68882 (1<<FPUB_68882) + #define FPU_68040 (1<<FPUB_68040) + #define FPU_68060 (1<<FPUB_68060) + #define FPU_SUNFPA (1<<FPUB_SUNFPA) ++#ifdef CONFIG_M547X_8X ++#define FPU_CFV4E (1<<FPUB_CFV4E) ++#else ++#define FPU_CFV4E 0 ++#endif + + #define MMUB_68851 0 + #define MMUB_68030 1 /* Internal MMU */ +@@ -235,6 +253,7 @@ extern unsigned long m68k_machtype; + #define MMUB_68060 3 /* Internal MMU */ + #define MMUB_APOLLO 4 /* Custom Apollo */ + #define MMUB_SUN3 5 /* Custom Sun-3 */ ++#define MMUB_CFV4E 6 + + #define MMU_68851 (1<<MMUB_68851) + #define MMU_68030 (1<<MMUB_68030) +@@ -242,6 +261,7 @@ extern unsigned long m68k_machtype; + #define MMU_68060 (1<<MMUB_68060) + #define MMU_SUN3 (1<<MMUB_SUN3) + #define MMU_APOLLO (1<<MMUB_APOLLO) ++#define MMU_CFV4E (1<<MMUB_CFV4E) + + #ifdef __KERNEL__ + +@@ -341,6 +361,14 @@ extern int m68k_is040or060; + # endif + #endif + ++#if !defined(CONFIG_CFV4E) ++# define CPU_IS_COLDFIRE (0) ++#else ++# define CPU_IS_COLDFIRE (m68k_cputype & CPU_CFV4E) ++# define CPU_IS_CFV4E (m68k_cputype & CPU_CFV4E) ++# define MMU_IS_CFV4E (m68k_mmutype & MMU_CFV4E) ++#endif ++ + #define CPU_TYPE (m68k_cputype) + + #ifdef CONFIG_M68KFPU_EMU +@@ -371,6 +399,14 @@ extern int m68k_realnum_memory; /* real + extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ + #endif + ++#ifdef CONFIG_CFV4E ++#define QCHIP_RESTORE_DIRECTIVE ".chip 547x" ++#define CHIP_RESTORE_DIRECTIVE .chip 547x ++#else ++#define QCHIP_RESTORE_DIRECTIVE ".chip 68k" ++#define CHIP_RESTORE_DIRECTIVE .chip 68k ++#endif ++ + #endif /* __KERNEL__ */ + + #endif /* _M68K_SETUP_H */ +--- a/arch/m68k/include/asm/signal.h ++++ b/arch/m68k/include/asm/signal.h +@@ -1,6 +1,12 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_SIGNAL_H + #define _M68K_SIGNAL_H +- + #include <linux/types.h> + + /* Avoid too many header ordering problems. */ +@@ -150,7 +156,7 @@ typedef struct sigaltstack { + #ifdef __KERNEL__ + #include <asm/sigcontext.h> + +-#ifndef __uClinux__ ++#ifndef CONFIG_COLDFIRE /*FIXME Jason*/ + #define __HAVE_ARCH_SIG_BITOPS + + static inline void sigaddset(sigset_t *set, int _sig) +--- a/arch/m68k/include/asm/string.h ++++ b/arch/m68k/include/asm/string.h +@@ -1,6 +1,12 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_STRING_H_ + #define _M68K_STRING_H_ +- + #include <linux/types.h> + #include <linux/compiler.h> + +@@ -81,6 +87,18 @@ static inline char *strncpy(char *dest, + strcpy(__d + strlen(__d), (s)); \ + }) + ++#define __HAVE_ARCH_STRCHR ++static inline char *strchr(const char *s, int c) ++{ ++ char sc, ch = c; ++ ++ for (; (sc = *s++) != ch; ) { ++ if (!sc) ++ return NULL; ++ } ++ return (char *)s - 1; ++} ++ + #ifndef CONFIG_COLDFIRE + #define __HAVE_ARCH_STRCMP + static inline int strcmp(const char *cs, const char *ct) +--- a/arch/m68k/include/asm/swab.h ++++ b/arch/m68k/include/asm/swab.h +@@ -1,11 +1,18 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_SWAB_H + #define _M68K_SWAB_H +- + #include <linux/types.h> + #include <linux/compiler.h> + + #define __SWAB_64_THRU_32__ + ++#if defined(__GNUC__) + #if defined (__mcfisaaplus__) || defined (__mcfisac__) + static inline __attribute_const__ __u32 __arch_swab32(__u32 val) + { +@@ -23,5 +30,11 @@ static inline __attribute_const__ __u32 + } + #define __arch_swab32 __arch_swab32 + #endif ++#endif ++ ++#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) ++# define __BYTEORDER_HAS_U64__ ++# define __SWAB_64_THRU_32__ ++#endif + + #endif /* _M68K_SWAB_H */ +--- a/arch/m68k/include/asm/system_mm.h ++++ b/arch/m68k/include/asm/system_mm.h +@@ -1,14 +1,35 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_SYSTEM_H + #define _M68K_SYSTEM_H +- + #include <linux/linkage.h> + #include <linux/kernel.h> + #include <linux/irqflags.h> + #include <asm/segment.h> + #include <asm/entry.h> ++#include <asm/cfcache.h> + + #ifdef __KERNEL__ + ++#ifdef CONFIG_COLDFIRE ++#define FLUSH_BC (0x00040000) ++ ++#define finish_arch_switch(prev) do { \ ++ unsigned long tmpreg; \ ++ asm volatile ("move.l %2,%0\n" \ ++ "orl %1,%0\n" \ ++ "movec %0,%%cacr" \ ++ : "=&d" (tmpreg) \ ++ : "id" (FLUSH_BC), "m" (shadow_cacr)); \ ++ } while (0) ++ ++#endif ++ + /* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. This +--- a/arch/m68k/include/asm/tlbflush.h ++++ b/arch/m68k/include/asm/tlbflush.h +@@ -1,8 +1,14 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _M68K_TLBFLUSH_H + #define _M68K_TLBFLUSH_H +- + #ifdef CONFIG_MMU +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + + #include <asm/current.h> + +@@ -92,7 +98,12 @@ static inline void flush_tlb_kernel_rang + flush_tlb_all(); + } + +-#else ++static inline void flush_tlb_pgtables(struct mm_struct *mm, ++ unsigned long start, unsigned long end) ++{ ++} ++ ++#elif defined(CONFIG_SUN3) + + + /* Reserved PMEGs. */ +@@ -214,6 +225,13 @@ static inline void flush_tlb_kernel_page + sun3_put_segmap (addr & ~(SUN3_PMEG_SIZE - 1), SUN3_INVALID_PMEG); + } + ++static inline void flush_tlb_pgtables(struct mm_struct *mm, ++ unsigned long start, unsigned long end) ++{ ++} ++ ++#else /* CONFIG_COLDFIRE */ ++#include <asm/cf_tlbflush.h> + #endif + + #else /* !CONFIG_MMU */ +--- a/arch/m68k/include/asm/uaccess_mm.h ++++ b/arch/m68k/include/asm/uaccess_mm.h +@@ -1,6 +1,15 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef __M68K_UACCESS_H + #define __M68K_UACCESS_H +- ++#ifdef CONFIG_COLDFIRE ++#include <asm/cf_uaccess.h> ++#else + /* + * User space memory access functions + */ +@@ -219,6 +228,41 @@ unsigned long __generic_copy_to_user(voi + : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \ + : : "memory") + ++#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ ++ asm volatile ("\n" \ ++ " move."#s1" (%2)+,%3\n" \ ++ "11: moves."#s1" %3,(%1)+\n" \ ++ "12: move."#s2" (%2)+,%3\n" \ ++ "21: moves."#s2" %3,(%1)+\n" \ ++ "22:\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ " move."#s3" (%2)+,%3\n" \ ++ "31: moves."#s3" %3,(%1)+\n" \ ++ "32:\n" \ ++ " .endif\n" \ ++ "4:\n" \ ++ "\n" \ ++ " .section __ex_table,\"a\"\n" \ ++ " .align 4\n" \ ++ " .long 11b,5f\n" \ ++ " .long 12b,5f\n" \ ++ " .long 21b,5f\n" \ ++ " .long 22b,5f\n" \ ++ " .ifnc \""#s3"\",\"\"\n" \ ++ " .long 31b,5f\n" \ ++ " .long 32b,5f\n" \ ++ " .endif\n" \ ++ " .previous\n" \ ++ "\n" \ ++ " .section .fixup,\"ax\"\n" \ ++ " .even\n" \ ++ "5: moveq.l #"#n",%0\n" \ ++ " jra 4b\n" \ ++ " .previous\n" \ ++ : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \ ++ : : "memory") ++ ++#endif /* CONFIG_COLDFIRE */ + static __always_inline unsigned long + __constant_copy_from_user(void *to, const void __user *from, unsigned long n) + { +@@ -266,40 +310,6 @@ __constant_copy_from_user(void *to, cons + return res; + } + +-#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ +- asm volatile ("\n" \ +- " move."#s1" (%2)+,%3\n" \ +- "11: moves."#s1" %3,(%1)+\n" \ +- "12: move."#s2" (%2)+,%3\n" \ +- "21: moves."#s2" %3,(%1)+\n" \ +- "22:\n" \ +- " .ifnc \""#s3"\",\"\"\n" \ +- " move."#s3" (%2)+,%3\n" \ +- "31: moves."#s3" %3,(%1)+\n" \ +- "32:\n" \ +- " .endif\n" \ +- "4:\n" \ +- "\n" \ +- " .section __ex_table,\"a\"\n" \ +- " .align 4\n" \ +- " .long 11b,5f\n" \ +- " .long 12b,5f\n" \ +- " .long 21b,5f\n" \ +- " .long 22b,5f\n" \ +- " .ifnc \""#s3"\",\"\"\n" \ +- " .long 31b,5f\n" \ +- " .long 32b,5f\n" \ +- " .endif\n" \ +- " .previous\n" \ +- "\n" \ +- " .section .fixup,\"ax\"\n" \ +- " .even\n" \ +- "5: moveq.l #"#n",%0\n" \ +- " jra 4b\n" \ +- " .previous\n" \ +- : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \ +- : : "memory") +- + static __always_inline unsigned long + __constant_copy_to_user(void __user *to, const void *from, unsigned long n) + { +--- a/arch/m68k/include/asm/unistd.h ++++ b/arch/m68k/include/asm/unistd.h +@@ -1,6 +1,12 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef _ASM_M68K_UNISTD_H_ + #define _ASM_M68K_UNISTD_H_ +- + /* + * This file contains the system call numbers. + */ +@@ -343,10 +349,11 @@ + #define __NR_fanotify_init 337 + #define __NR_fanotify_mark 338 + #define __NR_prlimit64 339 ++#define __NR_recvmmsg 340 + + #ifdef __KERNEL__ + +-#define NR_syscalls 340 ++#define NR_syscalls 341 + + #define __ARCH_WANT_IPC_PARSE_VERSION + #define __ARCH_WANT_OLD_READDIR +--- a/arch/m68k/include/asm/virtconvert.h ++++ b/arch/m68k/include/asm/virtconvert.h +@@ -1,5 +1,15 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + #ifndef __VIRT_CONVERT__ + #define __VIRT_CONVERT__ ++#ifdef CONFIG_COLDFIRE ++#include <asm/cf_virtconvert.h> ++#else + + /* + * Macros used for converting between virtual and physical mappings. +@@ -45,3 +55,4 @@ static inline void *phys_to_virt(unsigne + + #endif + #endif ++#endif +--- a/arch/m68k/kernel/Makefile ++++ b/arch/m68k/kernel/Makefile +@@ -2,16 +2,27 @@ + # Makefile for the linux kernel. + # + +-ifndef CONFIG_SUN3 +- extra-y := head.o ++ifdef CONFIG_SUN3 ++ extra-y := sun3-head.o vmlinux.lds ++ obj-y := entry.o signal.o ints.o time.o + else +- extra-y := sun3-head.o ++ifndef CONFIG_COLDFIRE ++ extra-y := head.o vmlinux.lds ++ obj-y := entry.o signal.o traps.o ints.o time.o ++else # CONFIG_COLDFIRE ++ extra-y := vmlinux.lds ++ obj-y := time.o ++ ifdef CONFIG_M547X_8X ++ obj-$(CONFIG_PCI) += bios32_mcf548x.o ++ endif ++endif + endif +-extra-y += vmlinux.lds + +-obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \ +- sys_m68k.o time.o setup.o m68k_ksyms.o devres.o ++obj-y += process.o ptrace.o module.o \ ++ sys_m68k.o setup.o m68k_ksyms.o devres.o# semaphore.o + + devres-y = ../../../kernel/irq/devres.o + + obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo ++ ++EXTRA_AFLAGS := -traditional +--- a/arch/m68k/kernel/asm-offsets.c ++++ b/arch/m68k/kernel/asm-offsets.c +@@ -2,6 +2,15 @@ + * This program is used to generate definitions needed by + * assembly language modules. + * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * Add Codlfire support ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the +@@ -22,6 +31,9 @@ + int main(void) + { + /* offsets into the task struct */ ++ DEFINE(TASK_STATE, offsetof(struct task_struct, state)); ++ DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags)); ++ DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace)); + DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); + DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info)); + DEFINE(TASK_MM, offsetof(struct task_struct, mm)); +@@ -43,6 +55,7 @@ int main(void) + /* offsets into the thread_info struct */ + DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags)); ++ DEFINE(TINFO_TP_VALUE, offsetof(struct thread_info, tp_value)); + + /* offsets into the pt_regs */ + DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0)); +@@ -57,8 +70,23 @@ int main(void) + DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2)); + DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc)); + DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr)); ++#ifdef CONFIG_COLDFIRE ++ /* Need to get the context out of struct mm for ASID setting */ ++ DEFINE(MM_CONTEXT, offsetof(struct mm_struct, context)); ++ /* Coldfire exception frame has vector *before* pc */ ++ DEFINE(PT_VECTOR, offsetof(struct pt_regs, pc) - 4); ++#else + /* bitfields are a bit difficult */ + DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4); ++#endif ++ ++ /* offsets into the irq_handler struct */ ++ DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler)); ++ DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id)); ++ DEFINE(IRQ_NEXT, offsetof(struct irq_node, next)); ++ ++ /* offsets into the kernel_stat struct */ ++ DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs)); + + /* offsets into the irq_cpustat_t struct */ + DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); +--- a/arch/m68k/kernel/dma.c ++++ b/arch/m68k/kernel/dma.c +@@ -1,4 +1,7 @@ + /* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. +@@ -12,12 +15,25 @@ + #include <linux/scatterlist.h> + #include <linux/slab.h> + #include <linux/vmalloc.h> +- ++#include <linux/pci.h> + #include <asm/pgalloc.h> + + void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t flag) + { ++#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) || \ ++ defined(CONFIG_M5441X) ++ /* ++ * On the M5445x platform the memory allocated with GFP_DMA ++ * is guaranteed to be DMA'able. ++ */ ++ void *addr; ++ ++ size = PAGE_ALIGN(size); ++ addr = kmalloc(size, GFP_DMA); ++ *handle = virt_to_phys(addr); ++ return addr; ++#else + struct page *page, **map; + pgprot_t pgprot; + void *addr; +@@ -56,6 +72,7 @@ void *dma_alloc_coherent(struct device * + kfree(map); + + return addr; ++#endif + } + EXPORT_SYMBOL(dma_alloc_coherent); + +@@ -63,7 +80,12 @@ void dma_free_coherent(struct device *de + void *addr, dma_addr_t handle) + { + pr_debug("dma_free_coherent: %p, %x\n", addr, handle); ++#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) || \ ++ defined(CONFIG_M5441X) ++ kfree((void *)handle); ++#else + vfree(addr); ++#endif + } + EXPORT_SYMBOL(dma_free_coherent); + +@@ -77,6 +99,9 @@ void dma_sync_single_for_device(struct d + case DMA_FROM_DEVICE: + cache_clear(handle, size); + break; ++ case PCI_DMA_BIDIRECTIONAL: ++ flush_dcache(); ++ break; + default: + if (printk_ratelimit()) + printk("dma_sync_single_for_device: unsupported dir %u\n", dir); +@@ -89,16 +114,23 @@ void dma_sync_sg_for_device(struct devic + enum dma_data_direction dir) + { + int i; ++#ifdef CONFIG_COLDFIRE ++ struct scatterlist *_sg; + ++ for_each_sg(sg, _sg, nents, i) ++ dma_sync_single_for_device(dev, _sg->dma_address, ++ _sg->length, dir); ++#else + for (i = 0; i < nents; sg++, i++) + dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); ++#endif + } + EXPORT_SYMBOL(dma_sync_sg_for_device); + + dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size, + enum dma_data_direction dir) + { +- dma_addr_t handle = virt_to_bus(addr); ++ dma_addr_t handle = (dma_addr_t)virt_to_bus(addr); + + dma_sync_single_for_device(dev, handle, size, dir); + return handle; +@@ -120,10 +152,19 @@ int dma_map_sg(struct device *dev, struc + enum dma_data_direction dir) + { + int i; +- ++#ifdef CONFIG_COLDFIRE ++ struct scatterlist *_sg; ++#endif ++#ifndef CONFIG_COLDFIRE + for (i = 0; i < nents; sg++, i++) { + sg->dma_address = sg_phys(sg); + dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); ++#else ++ for_each_sg(sg, _sg, nents, i) { ++ _sg->dma_address = sg_phys(_sg); ++ dma_sync_single_for_device(dev, _sg->dma_address, ++ _sg->length, dir); ++#endif + } + return nents; + } +--- a/arch/m68k/kernel/process.c ++++ b/arch/m68k/kernel/process.c +@@ -4,6 +4,15 @@ + * Copyright (C) 1995 Hamish Macdonald + * + * 68060 fixes by Jesper Skov ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt.Mahan@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + /* +@@ -185,12 +194,21 @@ EXPORT_SYMBOL(kernel_thread); + void flush_thread(void) + { + unsigned long zero = 0; ++#if !defined(CONFIG_COLDFIRE) + set_fs(USER_DS); + current->thread.fs = __USER_DS; + if (!FPU_IS_EMU) + asm volatile (".chip 68k/68881\n\t" + "frestore %0@\n\t" + ".chip 68k" : : "a" (&zero)); ++#else ++ set_fs(USER_DS); ++ current->thread.fs = USER_DS; ++#if defined(CONFIG_FPU) ++ if (!FPU_IS_EMU) ++ asm volatile ("frestore %0@\n\t" : : "a" (&zero)); ++#endif ++#endif + } + + /* +@@ -258,6 +276,7 @@ int copy_thread(unsigned long clone_flag + * Must save the current SFC/DFC value, NOT the value when + * the parent was last descheduled - RGH 10-08-96 + */ ++#if !defined(CONFIG_COLDFIRE) + p->thread.fs = get_fs().seg; + + if (!FPU_IS_EMU) { +@@ -269,9 +288,34 @@ int copy_thread(unsigned long clone_flag + "fmoveml %/fpiar/%/fpcr/%/fpsr,%1" + : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0]) + : "memory"); ++#else ++ p->thread.fs = get_fs(); ++ ++#if defined(CONFIG_FPU) ++ if (!FPU_IS_EMU) { ++ /* Copy the current fpu state */ ++ asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) ++ : "memory"); ++ ++ if (p->thread.fpstate[0]) { ++ asm volatile ("fmovemd %/fp0-%/fp7,%0" ++ : : "m" (p->thread.fp[0]) ++ : "memory"); ++ asm volatile ("fmovel %/fpiar,%0" ++ : : "m" (p->thread.fpcntl[0]) ++ : "memory"); ++ asm volatile ("fmovel %/fpcr,%0" ++ : : "m" (p->thread.fpcntl[1]) ++ : "memory"); ++ asm volatile ("fmovel %/fpsr,%0" ++ : : "m" (p->thread.fpcntl[2]) ++ : "memory"); ++ } + /* Restore the state in case the fpu was busy */ + asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0])); + } ++#endif ++#endif + + return 0; + } +@@ -280,7 +324,9 @@ int copy_thread(unsigned long clone_flag + + int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu) + { ++#if !defined(CONFIG_COLDFIRE) || defined(CONFIG_FPU) + char fpustate[216]; ++#endif + + if (FPU_IS_EMU) { + int i; +@@ -297,6 +343,7 @@ int dump_fpu (struct pt_regs *regs, stru + } + + /* First dump the fpu context to avoid protocol violation. */ ++#if !defined(CONFIG_COLDFIRE) + asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory"); + if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2]) + return 0; +@@ -307,6 +354,25 @@ int dump_fpu (struct pt_regs *regs, stru + asm volatile ("fmovemx %/fp0-%/fp7,%0" + :: "m" (fpu->fpregs[0]) + : "memory"); ++#elif defined(CONFIG_FPU) ++ asm volatile ("fsave %0" : : "m" (fpustate[0]) : "memory"); ++ if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2]) ++ return 0; ++ ++ asm volatile ("fmovel %/fpiar,%0" ++ : : "m" (fpu->fpcntl[0]) ++ : "memory"); ++ asm volatile ("fmovel %/fpcr,%0" ++ : : "m" (fpu->fpcntl[1]) ++ : "memory"); ++ asm volatile ("fmovel %/fpsr,%0" ++ : : "m" (fpu->fpcntl[2]) ++ : "memory"); ++ asm volatile ("fmovemd %/fp0-%/fp7,%0" ++ : : "m" (fpu->fpregs[0]) ++ : "memory"); ++#endif ++ + return 1; + } + EXPORT_SYMBOL(dump_fpu); +--- a/arch/m68k/kernel/setup.c ++++ b/arch/m68k/kernel/setup.c +@@ -2,7 +2,14 @@ + * linux/arch/m68k/kernel/setup.c + * + * Copyright (C) 1995 Hamish Macdonald +- */ ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++*/ + + /* + * This file handles the architecture-dependent parts of system setup +@@ -74,14 +81,26 @@ struct mem_info m68k_memory[NUM_MEMINFO] + EXPORT_SYMBOL(m68k_memory); + + struct mem_info m68k_ramdisk; ++EXPORT_SYMBOL(m68k_ramdisk); + ++#if !defined(CONFIG_COLDFIRE) + static char m68k_command_line[CL_SIZE]; ++#else ++char m68k_command_line[CL_SIZE]; ++unsigned long uboot_info_stk; ++EXPORT_SYMBOL(uboot_info_stk); ++#endif + + void (*mach_sched_init) (irq_handler_t handler) __initdata = NULL; + /* machine dependent irq functions */ + void (*mach_init_IRQ) (void) __initdata = NULL; + void (*mach_get_model) (char *model); + void (*mach_get_hardware_list) (struct seq_file *m); ++ ++#ifdef CONFIG_COLDFIRE ++void (*mach_tick)(void); ++#endif ++ + /* machine dependent timer functions */ + unsigned long (*mach_gettimeoffset) (void); + int (*mach_hwclk) (int, struct rtc_time*); +@@ -137,13 +156,17 @@ extern void config_hp300(void); + extern void config_q40(void); + extern void config_sun3x(void); + ++#ifdef CONFIG_COLDFIRE ++void coldfire_sort_memrec(void); ++#endif ++ + #define MASK_256K 0xfffc0000 + + extern void paging_init(void); + + static void __init m68k_parse_bootinfo(const struct bi_record *record) + { +- while (record->tag != BI_LAST) { ++ while ((record->tag != BI_LAST) && !(CONFIG_COLDFIRE)) { + int unknown = 0; + const unsigned long *data = record->data; + +@@ -203,6 +226,10 @@ static void __init m68k_parse_bootinfo(c + record->size); + } + ++#ifdef CONFIG_COLDFIRE ++ coldfire_sort_memrec(); ++#endif ++ + m68k_realnum_memory = m68k_num_memory; + #ifdef CONFIG_SINGLE_MEMORY_CHUNK + if (m68k_num_memory > 1) { +@@ -215,7 +242,9 @@ static void __init m68k_parse_bootinfo(c + + void __init setup_arch(char **cmdline_p) + { ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + int i; ++#endif + + /* The bootinfo is located right after the kernel bss */ + m68k_parse_bootinfo((const struct bi_record *)_end); +@@ -230,9 +259,10 @@ void __init setup_arch(char **cmdline_p) + * We should really do our own FPU check at startup. + * [what do we do with buggy 68LC040s? if we have problems + * with them, we should add a test to check_bugs() below] */ +-#ifndef CONFIG_M68KFPU_EMU_ONLY ++#if !defined(CONFIG_M68KFPU_EMU_ONLY) && defined(CONFIG_FPU) + /* clear the fpu if we have one */ +- if (m68k_fputype & (FPU_68881|FPU_68882|FPU_68040|FPU_68060)) { ++ if (m68k_fputype & (FPU_68881|FPU_68882|FPU_68040|FPU_68060| ++ FPU_CFV4E)) { + volatile int zero = 0; + asm volatile ("frestore %0" : : "m" (zero)); + } +@@ -320,16 +350,17 @@ void __init setup_arch(char **cmdline_p) + config_sun3x(); + break; + #endif ++#ifdef CONFIG_COLDFIRE ++ case MACH_CFMMU: ++ config_coldfire(); ++ break; ++#endif + default: + panic("No configuration setup"); + } + + paging_init(); + +-#ifndef CONFIG_SUN3 +- for (i = 1; i < m68k_num_memory; i++) +- free_bootmem_node(NODE_DATA(i), m68k_memory[i].addr, +- m68k_memory[i].size); + #ifdef CONFIG_BLK_DEV_INITRD + if (m68k_ramdisk.size) { + reserve_bootmem_node(__virt_to_node(phys_to_virt(m68k_ramdisk.addr)), +@@ -341,6 +372,10 @@ void __init setup_arch(char **cmdline_p) + } + #endif + ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) ++ for (i = 1; i < m68k_num_memory; i++) ++ free_bootmem_node(NODE_DATA(i), m68k_memory[i].addr, ++ m68k_memory[i].size); + #ifdef CONFIG_ATARI + if (MACH_IS_ATARI) + atari_stram_reserve_pages((void *)availmem); +@@ -353,12 +388,22 @@ void __init setup_arch(char **cmdline_p) + + #endif /* !CONFIG_SUN3 */ + ++#ifdef CONFIG_COLDFIRE ++ mmu_context_init(); ++#endif ++ + /* set ISA defs early as possible */ + #if defined(CONFIG_ISA) && defined(MULTI_ISA) + if (MACH_IS_Q40) { + isa_type = ISA_TYPE_Q40; + isa_sex = 0; + } ++#ifdef CONFIG_GG2 ++ if (MACH_IS_AMIGA && AMIGAHW_PRESENT(GG2_ISA)) { ++ isa_type = ISA_TYPE_GG2; ++ isa_sex = 0; ++ } ++#endif + #ifdef CONFIG_AMIGA_PCMCIA + if (MACH_IS_AMIGA && AMIGAHW_PRESENT(PCMCIA)) { + isa_type = ISA_TYPE_AG; +@@ -377,6 +422,7 @@ static int show_cpuinfo(struct seq_file + #define LOOP_CYCLES_68030 (8) + #define LOOP_CYCLES_68040 (3) + #define LOOP_CYCLES_68060 (1) ++#define LOOP_CYCLES_COLDFIRE (2) + + if (CPU_IS_020) { + cpu = "68020"; +@@ -390,6 +436,9 @@ static int show_cpuinfo(struct seq_file + } else if (CPU_IS_060) { + cpu = "68060"; + clockfactor = LOOP_CYCLES_68060; ++ } else if (CPU_IS_CFV4E) { ++ cpu = "ColdFire V4e"; ++ clockfactor = LOOP_CYCLES_COLDFIRE; + } else { + cpu = "680x0"; + clockfactor = 0; +@@ -408,6 +457,8 @@ static int show_cpuinfo(struct seq_file + fpu = "68060"; + else if (m68k_fputype & FPU_SUNFPA) + fpu = "Sun FPA"; ++ else if (m68k_fputype & FPU_CFV4E) ++ fpu = "ColdFire V4e"; + else + fpu = "none"; + #endif +@@ -424,6 +475,8 @@ static int show_cpuinfo(struct seq_file + mmu = "Sun-3"; + else if (m68k_mmutype & MMU_APOLLO) + mmu = "Apollo"; ++ else if (m68k_mmutype & MMU_CFV4E) ++ mmu = "ColdFire"; + else + mmu = "unknown"; + +@@ -506,7 +559,8 @@ module_init(proc_hardware_init); + + void check_bugs(void) + { +-#ifndef CONFIG_M68KFPU_EMU ++#if !defined(CONFIG_M68KFPU_EMU) && !defined(CONFIG_M5445X) && \ ++ !defined(CONFIG_M5441X) + if (m68k_fputype == 0) { + printk(KERN_EMERG "*** YOU DO NOT HAVE A FLOATING POINT UNIT, " + "WHICH IS REQUIRED BY LINUX/M68K ***\n"); +--- a/arch/m68k/kernel/sys_m68k.c ++++ b/arch/m68k/kernel/sys_m68k.c +@@ -1,5 +1,12 @@ + /* + * linux/arch/m68k/kernel/sys_m68k.c ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + * + * This file contains various random system calls that + * have a non-standard calling sequence on the Linux/m68k +@@ -29,6 +36,9 @@ + #include <asm/unistd.h> + #include <linux/elf.h> + #include <asm/tlb.h> ++#ifdef CONFIG_COLDFIRE ++#include <asm/cacheflush.h> ++#endif + + asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, + unsigned long error_code); +@@ -45,6 +55,59 @@ asmlinkage long sys_mmap2(unsigned long + return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff); + } + ++/* ++ * Perform the select(nd, in, out, ex, tv) and mmap() system ++ * calls. Linux/m68k cloned Linux/i386, which didn't use to be able to ++ * handle more than 4 system call parameters, so these system calls ++ * used a memory block for parameter passing.. ++ */ ++ ++struct mmap_arg_struct { ++ unsigned long addr; ++ unsigned long len; ++ unsigned long prot; ++ unsigned long flags; ++ unsigned long fd; ++ unsigned long offset; ++}; ++ ++asmlinkage int old_mmap(struct mmap_arg_struct __user *arg) ++{ ++ struct mmap_arg_struct a; ++ int error = -EFAULT; ++ ++ if (copy_from_user(&a, arg, sizeof(a))) ++ goto out; ++ ++ error = -EINVAL; ++ if (a.offset & ~PAGE_MASK) ++ goto out; ++ ++ a.flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); ++ ++ error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, ++ a.fd, a.offset >> PAGE_SHIFT); ++out: ++ return error; ++} ++ ++struct sel_arg_struct { ++ unsigned long n; ++ fd_set __user *inp, *outp, *exp; ++ struct timeval __user *tvp; ++}; ++ ++asmlinkage int old_select(struct sel_arg_struct __user *arg) ++{ ++ struct sel_arg_struct a; ++ ++ if (copy_from_user(&a, arg, sizeof(a))) ++ return -EFAULT; ++ /* sys_select() does the appropriate kernel locking */ ++ return sys_select(a.n, a.inp, a.outp, a.exp, a.tvp); ++} ++ ++#ifndef CONFIG_COLDFIRE + /* Convert virtual (user) address VADDR to physical address PADDR */ + #define virt_to_phys_040(vaddr) \ + ({ \ +@@ -368,6 +431,7 @@ cache_flush_060 (unsigned long addr, int + } + return 0; + } ++#endif /* CONFIG_COLDFIRE */ + + /* sys_cacheflush -- flush (part of) the processor cache. */ + asmlinkage int +@@ -399,6 +463,7 @@ sys_cacheflush (unsigned long addr, int + goto out; + } + ++#ifndef CONFIG_COLDFIRE + if (CPU_IS_020_OR_030) { + if (scope == FLUSH_SCOPE_LINE && len < 256) { + unsigned long cacr; +@@ -443,6 +508,16 @@ sys_cacheflush (unsigned long addr, int + ret = cache_flush_060 (addr, scope, cache, len); + } + } ++#else /* CONFIG_COLDFIRE */ ++ if ((cache & FLUSH_CACHE_INSN) && (cache & FLUSH_CACHE_DATA)) ++ flush_bcache(); ++ else if (cache & FLUSH_CACHE_INSN) ++ flush_icache(); ++ else ++ flush_dcache(); ++ ++ ret = 0; ++#endif /* CONFIG_COLDFIRE */ + out: + return ret; + } +@@ -474,9 +549,14 @@ asmlinkage unsigned long sys_get_thread_ + return current_thread_info()->tp_value; + } + ++extern void *_vdso_tp; ++ + asmlinkage int sys_set_thread_area(unsigned long tp) + { + current_thread_info()->tp_value = tp; ++#ifdef CONFIG_VDSO ++ *(unsigned long *)_vdso_tp = tp; ++#endif + return 0; + } + +--- a/arch/m68k/kernel/time.c ++++ b/arch/m68k/kernel/time.c +@@ -2,6 +2,14 @@ + * linux/arch/m68k/kernel/time.c + * + * Copyright (C) 1991, 1992, 1995 Linus Torvalds ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * Alison Wang b18965@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + * + * This file contains the m68k-specific time handling details. + * Most of the stuff is located in the machine specific files. +@@ -9,9 +17,12 @@ + * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + */ +- ++#include <linux/clk.h> ++#include <linux/clocksource.h> ++#include <linux/clockchips.h> + #include <linux/errno.h> + #include <linux/module.h> ++#include <linux/sysdev.h> + #include <linux/sched.h> + #include <linux/kernel.h> + #include <linux/param.h> +@@ -27,6 +38,7 @@ + #include <linux/time.h> + #include <linux/timex.h> + #include <linux/profile.h> ++#include <asm/mcfsim.h> + + static inline int set_rtc_mmss(unsigned long nowtime) + { +@@ -35,12 +47,18 @@ static inline int set_rtc_mmss(unsigned + return -1; + } + ++#ifndef CONFIG_GENERIC_CLOCKEVENTS + /* + * timer_interrupt() needs to keep up the real-time clock, + * as well as call the "do_timer()" routine every clocktick + */ + static irqreturn_t timer_interrupt(int irq, void *dummy) + { ++#ifdef CONFIG_COLDFIRE ++ /* kick hardware timer if necessary */ ++ if (mach_tick) ++ mach_tick(); ++#endif + do_timer(1); + update_process_times(user_mode(get_irq_regs())); + profile_tick(CPU_PROFILING); +@@ -91,11 +109,133 @@ void __init time_init(void) + { + mach_sched_init(timer_interrupt); + } ++#endif + ++#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET + u32 arch_gettimeoffset(void) + { + return mach_gettimeoffset() * 1000; + } ++#endif ++ ++#ifdef CONFIG_GENERIC_CLOCKEVENTS ++ ++extern unsigned long long sys_dtim2_read(void); ++extern void sys_dtim2_init(void); ++static int cfv4_set_next_event(unsigned long evt, ++ struct clock_event_device *dev); ++static void cfv4_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *dev); ++ ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++#define FREQ (MCF_BUSCLK / 16) ++#else ++#define FREQ (MCF_BUSCLK) ++#endif ++ ++/* ++ * Clock Evnt setup ++ */ ++static struct clock_event_device clockevent_cfv4 = { ++ .name = "CFV4 timer2even", ++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, ++ .rating = 200, ++ .shift = 20, ++ .set_mode = cfv4_set_mode, ++ .set_next_event = cfv4_set_next_event, ++}; ++ ++static int cfv4_set_next_event(unsigned long evt, ++ struct clock_event_device *dev) ++{ ++ return 0; ++} ++ ++static void cfv4_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *dev) ++{ ++ if (mode != CLOCK_EVT_MODE_ONESHOT) ++ cfv4_set_next_event((FREQ / HZ), dev); ++} ++ ++static int __init cfv4_clockevent_init(void) ++{ ++ clockevent_cfv4.mult = ++ div_sc(FREQ, NSEC_PER_SEC, ++ clockevent_cfv4.shift); ++ clockevent_cfv4.max_delta_ns = ++ clockevent_delta2ns((FREQ / HZ), ++ &clockevent_cfv4); ++ clockevent_cfv4.min_delta_ns = ++ clockevent_delta2ns(1, &clockevent_cfv4); ++ ++ clockevent_cfv4.cpumask = &cpumask_of_cpu(0); ++ ++ printk(KERN_INFO "timer: register clockevent\n"); ++ clockevents_register_device(&clockevent_cfv4); ++ ++ return 0; ++} ++ ++/* ++ * clocksource setup ++ */ ++ ++struct clocksource clocksource_cfv4 = { ++ .name = "ColdfireV4", ++ .rating = 250, ++ .mask = CLOCKSOURCE_MASK(32), ++ .read = sys_dtim2_read, ++ .shift = 20, ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++/* ++ * Initialize time subsystem. Called from linux/init/main.c ++ */ ++void __init time_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "Initializing time\n"); ++ ++ cfv4_clockevent_init(); ++ /* initialize the system timer */ ++ sys_dtim2_init(); ++ ++ /* JKM */ ++ clocksource_cfv4.mult = clocksource_hz2mult(FREQ, ++ clocksource_cfv4.shift); ++ ++ /* register our clocksource */ ++ ret = clocksource_register(&clocksource_cfv4); ++ if (ret) ++ printk(KERN_ERR "timer: unable to " ++ "register clocksource - %d\n", ret); ++} ++ ++/* ++ * sysfs pieces ++ */ ++ ++static struct sysdev_class timer_class = { ++ .name = "timer", ++}; ++ ++static struct sys_device timer_device = { ++ .id = 0, ++ .cls = &timer_class, ++}; ++ ++static int __init timer_init_sysfs(void) ++{ ++ int err = sysdev_class_register(&timer_class); ++ if (!err) ++ err = sysdev_register(&timer_device); ++ return err; ++} ++device_initcall(timer_init_sysfs); ++#endif /* CONFIG_GENERIC_CLOCKEVENTS */ + + static int __init rtc_init(void) + { +--- /dev/null ++++ b/arch/m68k/kernel/vmlinux-cf.lds +@@ -0,0 +1,142 @@ ++/* ld script to make m68k Coldfire Linux kernel ++ * ++ * Derived from arch/m68k/kernel/vmlinux-std.lds ++ * ++ * Updated 11/26/2007 for new CodeSourcery toolset ++ * by Kurt Mahan <kmahan@freescale.com> ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#define LOAD_OFFSET 0x00000000 ++ ++#include <asm-generic/vmlinux.lds.h> ++#include <asm/page_offset.h> ++ ++#define START_OFFSET 0x00020000 ++#define IMAGE_START PAGE_OFFSET_RAW + START_OFFSET ++ ++OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", "elf32-m68k") ++OUTPUT_ARCH(m68k) ++ENTRY(_stext) ++jiffies = jiffies_64 + 4; ++ ++SECTIONS ++{ ++ . = IMAGE_START; ++ .text.head : AT(ADDR(.text.head) - LOAD_OFFSET) { ++ _text = .; /* Text and read-only data */ ++ *(.text.head) ++ } :text = 0x4e75 ++ ++ .text : AT(ADDR(.text) - LOAD_OFFSET) { ++ TEXT_TEXT ++ SCHED_TEXT ++ LOCK_TEXT ++ *(.fixup) ++ *(.gnu.warning) ++ } :text = 0x4e75 ++ _etext = .; /* End of text section */ ++ ++ . = ALIGN(16); ++ __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { ++ __start___ex_table = .; ++ *(__ex_table) ++ __stop___ex_table = .; ++ } ++ ++ RODATA ++ ++ . = ALIGN(8192); ++ .data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */ ++ DATA_DATA ++ CONSTRUCTORS ++ } :data ++ ++ ++ . = ALIGN(16); ++ .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET ) { ++ *(.data.cacheline_aligned) ++ } :data ++ ++ _edata = .; /* End of data section */ ++ ++ NOTES /* support ld --build-id */ ++ ++ . = ALIGN(8192); /* Initrd */ ++ .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) { ++ __init_begin = .; ++ _sinittext = .; ++ *(.init.text) ++ _einittext = .; ++ } ++ ++ .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) { ++ *(.init.data) ++ } ++ ++ . = ALIGN(16); ++ .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) { ++ __setup_start = .; ++ *(.init.setup) ++ __setup_end = .; ++ } ++ ++ .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) { ++ __initcall_start = .; ++ INITCALLS ++ __initcall_end = .; ++ } ++ ++ .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) { ++ __con_initcall_start = .; ++ *(.con_initcall.init) ++ __con_initcall_end = .; ++ } ++ ++ SECURITY_INIT ++ ++#ifdef CONFIG_BLK_DEV_INITRD ++ . = ALIGN(8192); ++ .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { ++ __initramfs_start = .; ++ *(.init.ramfs) ++ __initramfs_end = .; ++ } ++#endif ++ ++ . = ALIGN(8192); ++ __init_end = .; ++ ++ .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) { ++ *(.data.init_task) /* The initial task and kernel stack */ ++ } ++ ++ _sbss = .; ++ .bss : AT(ADDR(.bss) - LOAD_OFFSET) { /* BSS */ ++ *(.bss) ++ } ++ _ebss = .; ++ ++ _end = . ; ++ ++ __ctors_start = . ; ++ ++ __ctors_end = . ; ++ ++ /* Sections to be discarded */ ++ /DISCARD/ : { ++ *(.exit.text) ++ *(.exit.data) ++ *(.exitcall.exit) ++ } ++ ++ /* Stabs debugging sections. */ ++ STABS_DEBUG ++} +--- a/arch/m68k/kernel/vmlinux.lds.S ++++ b/arch/m68k/kernel/vmlinux.lds.S +@@ -1,10 +1,20 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ + PHDRS + { +- text PT_LOAD FILEHDR PHDRS FLAGS (7); ++ headers PT_PHDR PHDRS ; ++ text PT_LOAD FILEHDR PHDRS FLAGS (5); + data PT_LOAD FLAGS (7); + } + #ifdef CONFIG_SUN3 + #include "vmlinux-sun3.lds" ++#elif CONFIG_COLDFIRE ++#include "vmlinux-cf.lds" + #else + #include "vmlinux-std.lds" + #endif +--- a/arch/m68k/lib/checksum.c ++++ b/arch/m68k/lib/checksum.c +@@ -30,6 +30,10 @@ + * 1998/8/31 Andreas Schwab: + * Zero out rest of buffer on exception in + * csum_partial_copy_from_user. ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com + */ + + #include <linux/module.h> +@@ -39,8 +43,132 @@ + * computes a partial checksum, e.g. for TCP/UDP fragments + */ + ++#ifdef CONFIG_COLDFIRE ++ ++static inline unsigned short from32to16(unsigned long x) ++{ ++ /* add up 16-bit and 16-bit for 16+c bit */ ++ x = (x & 0xffff) + (x >> 16); ++ /* add up carry.. */ ++ x = (x & 0xffff) + (x >> 16); ++ return x; ++} ++ ++static unsigned long do_csum(const unsigned char *buff, int len) ++{ ++ int odd, count; ++ unsigned long result = 0; ++ ++ if (len <= 0) ++ goto out; ++ odd = 1 & (unsigned long) buff; ++ if (odd) { ++ result = *buff; ++ len--; ++ buff++; ++ } ++ count = len >> 1; /* nr of 16-bit words.. */ ++ if (count) { ++ if (2 & (unsigned long) buff) { ++ result += *(unsigned short *) buff; ++ count--; ++ len -= 2; ++ buff += 2; ++ } ++ count >>= 1; /* nr of 32-bit words.. */ ++ if (count) { ++ unsigned long carry = 0; ++ do { ++ unsigned long w = *(unsigned long *) buff; ++ count--; ++ buff += 4; ++ result += carry; ++ result += w; ++ carry = (w > result); ++ } while (count); ++ result += carry; ++ result = (result & 0xffff) + (result >> 16); ++ } ++ if (len & 2) { ++ result += *(unsigned short *) buff; ++ buff += 2; ++ } ++ } ++ if (len & 1) ++ result += (*buff << 8); ++ result = from32to16(result); ++ if (odd) ++ result = ((result >> 8) & 0xff) | ((result & 0xff) << 8); ++out: ++ return result; ++} ++ ++/* ++ * This is a version of ip_compute_csum() optimized for IP headers, ++ * which always checksum on 4 octet boundaries. ++ */ ++__sum16 ip_fast_csum(const void *iph, unsigned int ihl) ++{ ++ return ~do_csum(iph, ihl*4); ++} ++EXPORT_SYMBOL(ip_fast_csum); ++ ++/* ++ * computes the checksum of a memory block at buff, length len, ++ * and adds in "sum" (32-bit) ++ * ++ * returns a 32-bit number suitable for feeding into itself ++ * or csum_tcpudp_magic ++ * ++ * this function must be called with even lengths, except ++ * for the last fragment, which may be odd ++ * ++ * it's best to have buff aligned on a 32-bit boundary ++ */ + __wsum csum_partial(const void *buff, int len, __wsum sum) + { ++ unsigned int result = do_csum(buff, len); ++ ++ /* add in old sum, and carry.. */ ++ result += sum; ++ if (sum > result) ++ result += 1; ++ return result; ++} ++EXPORT_SYMBOL(csum_partial); ++ ++/* ++ * copy from fs while checksumming, otherwise like csum_partial ++ */ ++ ++__wsum ++csum_partial_copy_from_user(const void __user *src, void *dst, int len, ++ __wsum sum, int *csum_err) ++{ ++ if (csum_err) ++ *csum_err = 0; ++ memcpy(dst, src, len); ++ return csum_partial(dst, len, sum); ++} ++EXPORT_SYMBOL(csum_partial_copy_from_user); ++ ++/* ++ * copy from ds while checksumming, otherwise like csum_partial ++ */ ++ ++__wsum ++csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum) ++{ ++ memcpy(dst, src, len); ++ return csum_partial(dst, len, sum); ++} ++EXPORT_SYMBOL(csum_partial_copy_nocheck); ++ ++#else /* !CONFIG_COLDFIRE */ ++ ++unsigned int ++csum_partial(const unsigned char *buff, int len, unsigned int sum) ++{ + unsigned long tmp1, tmp2; + /* + * Experiments with ethernet and slip connections show that buff +@@ -423,3 +551,4 @@ csum_partial_copy_nocheck(const void *sr + return(sum); + } + EXPORT_SYMBOL(csum_partial_copy_nocheck); ++#endif /* CONFIG_COLDFIRE */ +--- a/arch/m68k/lib/muldi3.c ++++ b/arch/m68k/lib/muldi3.c +@@ -1,6 +1,9 @@ + /* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and + gcc-2.7.2.3/longlong.h which is: */ + /* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. ++ Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ Jason Jin Jason.Jin@freescale.com ++ Shrek Wu B16972@freescale.com + + This file is part of GNU CC. + +@@ -21,12 +24,22 @@ Boston, MA 02111-1307, USA. */ + + #define BITS_PER_UNIT 8 + ++#ifdef CONFIG_COLDFIRE ++#define umul_ppmm(w1, w0, u, v) \ ++ do { \ ++ unsigned long long x; \ ++ x = (unsigned long long)u * v; \ ++ w0 = (unsigned long)(x & 0x00000000ffffffff); \ ++ w1 = (unsigned long)(x & 0xffffffff00000000) >> 32; \ ++ } while (0) ++#else /* CONFIG_COLDFIRE */ + #define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mulu%.l %3,%1:%0" \ + : "=d" ((USItype)(w0)), \ + "=d" ((USItype)(w1)) \ + : "%0" ((USItype)(u)), \ + "dmi" ((USItype)(v))) ++#endif /* CONFIG_COLDFIRE */ + + #define __umulsidi3(u, v) \ + ({DIunion __w; \ +--- a/arch/m68k/lib/string.c ++++ b/arch/m68k/lib/string.c +@@ -1,4 +1,8 @@ + /* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. +@@ -21,6 +25,7 @@ char *strcat(char *dest, const char *src + } + EXPORT_SYMBOL(strcat); + ++#ifndef CONFIG_COLDFIRE + void *memset(void *s, int c, size_t count) + { + void *xs = s; +@@ -149,6 +154,69 @@ void *memcpy(void *to, const void *from, + } + EXPORT_SYMBOL(memcpy); + ++#else /* CONFIG_COLDFIRE */ ++ ++void *memset(void *s, int c, size_t count) ++{ ++ unsigned long x; ++ void *originalTo = s; ++ ++ for (x = 0; x < count; x++) ++ *(unsigned char *)s++ = (unsigned char)c; ++ ++ return originalTo; ++} ++EXPORT_SYMBOL(memset); ++ ++void *memcpy(void *to, const void *from, size_t n) ++{ ++ void *xto = to; ++ size_t temp; ++ ++ if (!n) ++ return xto; ++ if ((long) to & 1) { ++ char *cto = to; ++ const char *cfrom = from; ++ *cto++ = *cfrom++; ++ to = cto; ++ from = cfrom; ++ n--; ++ } ++ if (n > 2 && (long) to & 2) { ++ short *sto = to; ++ const short *sfrom = from; ++ *sto++ = *sfrom++; ++ to = sto; ++ from = sfrom; ++ n -= 2; ++ } ++ temp = n >> 2; ++ if (temp) { ++ long *lto = to; ++ const long *lfrom = from; ++ for (; temp; temp--) ++ *lto++ = *lfrom++; ++ to = lto; ++ from = lfrom; ++ } ++ if (n & 2) { ++ short *sto = to; ++ const short *sfrom = from; ++ *sto++ = *sfrom++; ++ to = sto; ++ from = sfrom; ++ } ++ if (n & 1) { ++ char *cto = to; ++ const char *cfrom = from; ++ *cto = *cfrom; ++ } ++ return xto; ++} ++EXPORT_SYMBOL(memcpy); ++#endif /* CONFIG_COLDFIRE */ ++ + void *memmove(void *dest, const void *src, size_t n) + { + void *xdest = dest; +--- a/arch/m68k/lib/uaccess.c ++++ b/arch/m68k/lib/uaccess.c +@@ -1,10 +1,15 @@ + /* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + + #include <linux/module.h> ++#ifndef CONFIG_COLDFIRE + #include <asm/uaccess.h> + + unsigned long __generic_copy_from_user(void *to, const void __user *from, +@@ -220,3 +225,245 @@ unsigned long __clear_user(void __user * + return res; + } + EXPORT_SYMBOL(__clear_user); ++ ++#else /* CONFIG_COLDFIRE */ ++ ++#include <asm/cf_uaccess.h> ++ ++unsigned long __generic_copy_from_user(void *to, const void *from, ++ unsigned long n) ++{ ++ unsigned long tmp; ++ __asm__ __volatile__ ++ (" tstl %2\n" ++ " jeq 2f\n" ++ "1: movel (%1)+,%3\n" ++ " movel %3,(%0)+\n" ++ " subql #1,%2\n" ++ " jne 1b\n" ++ "2: movel %4,%2\n" ++ " bclr #1,%2\n" ++ " jeq 4f\n" ++ "3: movew (%1)+,%3\n" ++ " movew %3,(%0)+\n" ++ "4: bclr #0,%2\n" ++ " jeq 6f\n" ++ "5: moveb (%1)+,%3\n" ++ " moveb %3,(%0)+\n" ++ "6:\n" ++ ".section .fixup,\"ax\"\n" ++ " .even\n" ++ "7: movel %2,%%d0\n" ++ "71:clrl (%0)+\n" ++ " subql #1,%%d0\n" ++ " jne 71b\n" ++ " lsll #2,%2\n" ++ " addl %4,%2\n" ++ " btst #1,%4\n" ++ " jne 81f\n" ++ " btst #0,%4\n" ++ " jne 91f\n" ++ " jra 6b\n" ++ "8: addql #2,%2\n" ++ "81:clrw (%0)+\n" ++ " btst #0,%4\n" ++ " jne 91f\n" ++ " jra 6b\n" ++ "9: addql #1,%2\n" ++ "91:clrb (%0)+\n" ++ " jra 6b\n" ++ ".previous\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 1b,7b\n" ++ " .long 3b,8b\n" ++ " .long 5b,9b\n" ++ ".previous" ++ : "=a"(to), "=a"(from), "=d"(n), "=&d"(tmp) ++ : "d"(n & 3), "0"(to), "1"(from), "2"(n/4) ++ : "d0", "memory"); ++ return n; ++} ++EXPORT_SYMBOL(__generic_copy_from_user); ++ ++ ++unsigned long __generic_copy_to_user(void *to, const void *from, ++ unsigned long n) ++{ ++ unsigned long tmp; ++ __asm__ __volatile__ ++ (" tstl %2\n" ++ " jeq 3f\n" ++ "1: movel (%1)+,%3\n" ++ "22:movel %3,(%0)+\n" ++ "2: subql #1,%2\n" ++ " jne 1b\n" ++ "3: movel %4,%2\n" ++ " bclr #1,%2\n" ++ " jeq 4f\n" ++ " movew (%1)+,%3\n" ++ "24:movew %3,(%0)+\n" ++ "4: bclr #0,%2\n" ++ " jeq 5f\n" ++ " moveb (%1)+,%3\n" ++ "25:moveb %3,(%0)+\n" ++ "5:\n" ++ ".section .fixup,\"ax\"\n" ++ " .even\n" ++ "60:addql #1,%2\n" ++ "6: lsll #2,%2\n" ++ " addl %4,%2\n" ++ " jra 5b\n" ++ "7: addql #2,%2\n" ++ " jra 5b\n" ++ "8: addql #1,%2\n" ++ " jra 5b\n" ++ ".previous\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 1b,60b\n" ++ " .long 22b,6b\n" ++ " .long 2b,6b\n" ++ " .long 24b,7b\n" ++ " .long 3b,60b\n" ++ " .long 4b,7b\n" ++ " .long 25b,8b\n" ++ " .long 5b,8b\n" ++ ".previous" ++ : "=a"(to), "=a"(from), "=d"(n), "=&d"(tmp) ++ : "r"(n & 3), "0"(to), "1"(from), "2"(n / 4) ++ : "memory"); ++ return n; ++} ++EXPORT_SYMBOL(__generic_copy_to_user); ++ ++/* ++ * Copy a null terminated string from userspace. ++ */ ++ ++long strncpy_from_user(char *dst, const char *src, long count) ++{ ++ long res = -EFAULT; ++ if (!(access_ok(VERIFY_READ, src, 1))) /* --tym-- */ ++ return res; ++ if (count == 0) ++ return count; ++ __asm__ __volatile__ ++ ("1: moveb (%2)+,%%d0\n" ++ "12:moveb %%d0,(%1)+\n" ++ " jeq 2f\n" ++ " subql #1,%3\n" ++ " jne 1b\n" ++ "2: subl %3,%0\n" ++ "3:\n" ++ ".section .fixup,\"ax\"\n" ++ " .even\n" ++ "4: movel %4,%0\n" ++ " jra 3b\n" ++ ".previous\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 1b,4b\n" ++ " .long 12b,4b\n" ++ ".previous" ++ : "=d"(res), "=a"(dst), "=a"(src), "=d"(count) ++ : "i"(-EFAULT), "0"(count), "1"(dst), "2"(src), "3"(count) ++ : "d0", "memory"); ++ return res; ++} ++EXPORT_SYMBOL(strncpy_from_user); ++ ++/* ++ * Return the size of a string (including the ending 0) ++ * ++ * Return 0 on exception, a value greater than N if too long ++ */ ++long strnlen_user(const char *src, long n) ++{ ++ long res = -EFAULT; ++ if (!(access_ok(VERIFY_READ, src, 1))) /* --tym-- */ ++ return res; ++ ++ res = -(long)src; ++ __asm__ __volatile__ ++ ("1:\n" ++ " tstl %2\n" ++ " jeq 3f\n" ++ "2: moveb (%1)+,%%d0\n" ++ "22:\n" ++ " subql #1,%2\n" ++ " tstb %%d0\n" ++ " jne 1b\n" ++ " jra 4f\n" ++ "3:\n" ++ " addql #1,%0\n" ++ "4:\n" ++ " addl %1,%0\n" ++ "5:\n" ++ ".section .fixup,\"ax\"\n" ++ " .even\n" ++ "6: moveq %3,%0\n" ++ " jra 5b\n" ++ ".previous\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 2b,6b\n" ++ " .long 22b,6b\n" ++ ".previous" ++ : "=d"(res), "=a"(src), "=d"(n) ++ : "i"(0), "0"(res), "1"(src), "2"(n) ++ : "d0"); ++ return res; ++} ++EXPORT_SYMBOL(strnlen_user); ++ ++ ++/* ++ * Zero Userspace ++ */ ++ ++unsigned long __clear_user(void *to, unsigned long n) ++{ ++ __asm__ __volatile__ ++ (" tstl %1\n" ++ " jeq 3f\n" ++ "1: movel %3,(%0)+\n" ++ "2: subql #1,%1\n" ++ " jne 1b\n" ++ "3: movel %2,%1\n" ++ " bclr #1,%1\n" ++ " jeq 4f\n" ++ "24:movew %3,(%0)+\n" ++ "4: bclr #0,%1\n" ++ " jeq 5f\n" ++ "25:moveb %3,(%0)+\n" ++ "5:\n" ++ ".section .fixup,\"ax\"\n" ++ " .even\n" ++ "61:addql #1,%1\n" ++ "6: lsll #2,%1\n" ++ " addl %2,%1\n" ++ " jra 5b\n" ++ "7: addql #2,%1\n" ++ " jra 5b\n" ++ "8: addql #1,%1\n" ++ " jra 5b\n" ++ ".previous\n" ++ ".section __ex_table,\"a\"\n" ++ " .align 4\n" ++ " .long 1b,61b\n" ++ " .long 2b,6b\n" ++ " .long 3b,61b\n" ++ " .long 24b,7b\n" ++ " .long 4b,7b\n" ++ " .long 25b,8b\n" ++ " .long 5b,8b\n" ++ ".previous" ++ : "=a"(to), "=d"(n) ++ : "r"(n & 3), "d"(0), "0"(to), "1"(n/4)); ++ return n; ++} ++EXPORT_SYMBOL(__clear_user); ++ ++#endif /* CONFIG_COLDFIRE */ ++ +--- a/arch/m68k/mm/Makefile ++++ b/arch/m68k/mm/Makefile +@@ -6,3 +6,5 @@ obj-y := cache.o init.o fault.o hwtest. + + obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o + obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o ++obj-$(CONFIG_MMU_CFV4E) += cf-mmu.o kmap.o memory.o ++obj-$(CONFIG_SRAM) += cf-sram.o +--- a/arch/m68k/mm/cache.c ++++ b/arch/m68k/mm/cache.c +@@ -4,13 +4,24 @@ + * Instruction cache handling + * + * Copyright (C) 1995 Hamish Macdonald ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + #include <linux/module.h> + #include <asm/pgalloc.h> + #include <asm/traps.h> + ++#ifdef CONFIG_COLDFIRE ++#include <asm/cfcache.h> ++#endif /* CONFIG_COLDFIRE */ + ++#ifndef CONFIG_COLDFIRE + static unsigned long virt_to_phys_slow(unsigned long vaddr) + { + if (CPU_IS_060) { +@@ -69,11 +80,16 @@ static unsigned long virt_to_phys_slow(u + } + return 0; + } ++#endif /* CONFIG_COLDFIRE */ ++ + + /* Push n pages at kernel virtual address and clear the icache */ + /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ + void flush_icache_range(unsigned long address, unsigned long endaddr) + { ++#ifdef CONFIG_COLDFIRE ++ flush_icache(); ++#else /* !CONFIG_COLDFIRE */ + + if (CPU_IS_040_OR_060) { + address &= PAGE_MASK; +@@ -94,9 +110,11 @@ void flush_icache_range(unsigned long ad + : "=&d" (tmp) + : "di" (FLUSH_I)); + } ++#endif /* CONFIG_COLDFIRE */ + } + EXPORT_SYMBOL(flush_icache_range); + ++#ifndef CONFIG_COLDFIRE + void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, + unsigned long addr, int len) + { +@@ -115,4 +133,5 @@ void flush_icache_user_range(struct vm_a + : "di" (FLUSH_I)); + } + } ++#endif /* CONFIG_COLDFIRE */ + +--- /dev/null ++++ b/arch/m68k/mm/cf-mmu.c +@@ -0,0 +1,311 @@ ++/* ++ * linux/arch/m68k/mm/cf-mmu.c ++ * ++ * Based upon linux/arch/m68k/mm/sun3mmu.c ++ * Based upon linux/arch/ppc/mm/mmu_context.c ++ * ++ * Implementations of mm routines specific to the Coldfire MMU. ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#include <linux/signal.h> ++#include <linux/sched.h> ++#include <linux/mm.h> ++#include <linux/swap.h> ++#include <linux/kernel.h> ++#include <linux/string.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#ifdef CONFIG_BLK_DEV_RAM ++#include <linux/blkdev.h> ++#endif ++#include <linux/bootmem.h> ++ ++#include <asm/setup.h> ++#include <asm/uaccess.h> ++#include <asm/page.h> ++#include <asm/pgtable.h> ++#include <asm/system.h> ++#include <asm/machdep.h> ++#include <asm/io.h> ++#include <asm/mmu_context.h> ++#include <asm/cf_pgalloc.h> ++ ++#include <asm/coldfire.h> ++#include <asm/tlbflush.h> ++ ++#define KMAPAREA(x) ((x >= VMALLOC_START) && (x < KMAP_END)) ++ ++#undef DEBUG ++ ++#ifdef CONFIG_VDSO ++unsigned long next_mmu_context; ++#else ++mm_context_t next_mmu_context; ++#endif ++ ++unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1]; ++ ++atomic_t nr_free_contexts; ++struct mm_struct *context_mm[LAST_CONTEXT+1]; ++const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n"; ++ ++extern unsigned long num_pages; ++EXPORT_SYMBOL(num_pages); ++/* ++ * Free memory used for system initialization. ++ */ ++void free_initmem(void) ++{ ++#if 0 ++ unsigned long addr; ++ unsigned long start = (unsigned long)&__init_begin; ++ unsigned long end = (unsigned long)&__init_end; ++ ++ printk(KERN_INFO "free_initmem: __init_begin = 0x%lx" ++ " __init_end = 0x%lx\n", start, end); ++ ++ addr = (unsigned long)&__init_begin; ++ for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) { ++ /* not currently used */ ++ virt_to_page(addr)->flags &= ~(1 << PG_reserved); ++ init_page_count(virt_to_page(addr)); ++ free_page(addr); ++ totalram_pages++; ++ } ++#endif ++} ++ ++/* ++ * Initialize the paging system. ++ */ ++void __init paging_init(void) ++{ ++ pgd_t *pg_dir; ++ pte_t *pg_table; ++ int i; ++ unsigned long address; ++ unsigned long next_pgtable; ++ unsigned long zones_size[MAX_NR_ZONES]; ++ unsigned long size; ++ enum zone_type zone; ++ ++ /* allocate zero page */ ++ empty_zero_page = (void *)alloc_bootmem_pages(PAGE_SIZE); ++ memset((void *)empty_zero_page, 0, PAGE_SIZE); ++ ++ /* zero kernel page directory */ ++ pg_dir = swapper_pg_dir; ++ memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); ++ /* ++ * setup page tables for PHYSRAM ++ */ ++ ++ /* starting loc in page directory */ ++ pg_dir += PAGE_OFFSET >> PGDIR_SHIFT; ++ ++ /* allocate page tables */ ++ size = num_pages * sizeof(pte_t); ++ size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1); ++ next_pgtable = (unsigned long)alloc_bootmem_pages(size); ++ address = PAGE_OFFSET; ++ while (address < (unsigned long)high_memory) { ++ /* setup page table in page directory */ ++ pg_table = (pte_t *)next_pgtable; ++ next_pgtable += PTRS_PER_PTE * sizeof(pte_t); ++ pgd_val(*pg_dir) = (unsigned long)pg_table; ++ pg_dir++; ++ ++ /* create PTEs in page table */ ++ for (i = 0; i < PTRS_PER_PTE; ++i, ++pg_table) { ++ pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT); ++ if (address >= (unsigned long)high_memory) ++ pte_val(pte) = 0; ++ ++ set_pte(pg_table, pte); ++ address += PAGE_SIZE; ++ } ++ } ++ ++ /* ++ * setup page tables for DMA area ++ */ ++ ++ /* starting loc in page directory */ ++ pg_dir = swapper_pg_dir; ++ pg_dir += CONFIG_DMA_BASE >> PGDIR_SHIFT; ++ ++ /* allocate page tables */ ++ size = (CONFIG_DMA_SIZE >> PAGE_SHIFT) * sizeof(pte_t); ++ size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1); ++ next_pgtable = (unsigned long)alloc_bootmem_pages(size); ++ address = CONFIG_DMA_BASE; ++ while (address < (CONFIG_DMA_BASE + CONFIG_DMA_SIZE)) { ++ /* setup page table in page directory */ ++ pg_table = (pte_t *)next_pgtable; ++ next_pgtable += PTRS_PER_PTE * sizeof(pte_t); ++ pgd_val(*pg_dir) = (unsigned long)pg_table; ++ pg_dir++; ++ ++ /* create PTEs in page table */ ++ for (i = 0; i < PTRS_PER_PTE; ++i, ++pg_table) { ++ pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT); ++ if (address >= (CONFIG_DMA_BASE + CONFIG_DMA_SIZE)) ++ pte_val(pte) = 0; ++ ++ set_pte(pg_table, pte); ++ address += PAGE_SIZE; ++ } ++ } ++ ++ /* ++ * setup zones ++ */ ++ ++ current->mm = NULL; ++ ++ /* clear zones */ ++ for (zone = 0; zone < MAX_NR_ZONES; zone++) ++ zones_size[zone] = 0x0; ++ ++ zones_size[ZONE_DMA] = CONFIG_DMA_SIZE >> PAGE_SHIFT; ++ zones_size[ZONE_NORMAL] = (((unsigned long)high_memory - ++ PAGE_OFFSET) >> PAGE_SHIFT) - ++ zones_size[ZONE_DMA]; ++ ++ free_area_init(zones_size); ++} ++/* ++ * Handle a missed TLB ++ */ ++int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word) ++{ ++ struct mm_struct *mm; ++ pgd_t *pgd; ++ pmd_t *pmd; ++ pte_t *pte; ++ unsigned long mmuar; ++ int asid; ++ unsigned long flags; ++ ++ local_save_flags(flags); ++ local_irq_disable(); ++ ++ mmuar = (dtlb) ? regs->mmuar ++ : regs->pc + (extension_word * sizeof(long)); ++ ++ mm = (!user_mode(regs) && KMAPAREA(mmuar)) ? &init_mm : current->mm; ++ ++ if (!mm) { ++ local_irq_restore(flags); ++ return -1; ++ } ++ ++ pgd = pgd_offset(mm, mmuar); ++ if (pgd_none(*pgd)) { ++ local_irq_restore(flags); ++ return -1; ++ } ++ ++ pmd = pmd_offset(pgd, mmuar); ++ if (pmd_none(*pmd)) { ++ local_irq_restore(flags); ++ return -1; ++ } ++ ++ pte = (KMAPAREA(mmuar)) ? pte_offset_kernel(pmd, mmuar) ++ : pte_offset_map(pmd, mmuar); ++ if (pte_none(*pte) || !pte_present(*pte)) { ++ local_irq_restore(flags); ++ return -1; ++ } ++ ++ if (write) { ++ if (!pte_write(*pte)) { ++ local_irq_restore(flags); ++ return -1; ++ } ++ set_pte(pte, pte_mkdirty(*pte)); ++ } ++ ++ set_pte(pte, pte_mkyoung(*pte)); ++ asid = cpu_context(mm) & 0xff; ++ if (!pte_dirty(*pte) && !KMAPAREA(mmuar)) ++ set_pte(pte, pte_wrprotect(*pte)); ++ ++ *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT) ++ | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK) ++ >> CF_PAGE_MMUTR_SHIFT) | MMUTR_V; ++ ++ *MMUDR = (pte_val(*pte) & PAGE_MASK) ++ | ((pte->pte) & CF_PAGE_MMUDR_MASK) ++ | MMUDR_SZ8K | MMUDR_X; ++ ++ if (dtlb) ++ *MMUOR = MMUOR_ACC | MMUOR_UAA; ++ else ++ *MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA; ++ ++ asm("nop"); ++ ++#ifdef DEBUG ++ printk(KERN_INFO "cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK), ++ (pte_val(*pte) & PAGE_MASK)); ++#endif ++ local_irq_restore(flags); ++ return 0; ++} ++ ++ ++/* ++ * Context Management ++ * ++ * Based on arch/ppc/mmu_context.c ++ */ ++ ++/* ++ * Initialize the context management system. ++ */ ++void __init mmu_context_init(void) ++{ ++ /* ++ * Some processors have too few contexts to reserve one for ++ * init_mm, and require using context 0 for a normal task. ++ * Other processors reserve the use of context zero for the kernel. ++ * This code assumes FIRST_CONTEXT < 32. ++ */ ++ context_map[0] = (1 << FIRST_CONTEXT) - 1; ++ next_mmu_context = FIRST_CONTEXT; ++ atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1); ++} ++ ++/* ++ * Steal a context from a task that has one at the moment. ++ * This is only used on 8xx and 4xx and we presently assume that ++ * they don't do SMP. If they do then thicfpgalloc.hs will have to check ++ * whether the MM we steal is in use. ++ * We also assume that this is only used on systems that don't ++ * use an MMU hash table - this is true for 8xx and 4xx. ++ * This isn't an LRU system, it just frees up each context in ++ * turn (sort-of pseudo-random replacement :). This would be the ++ * place to implement an LRU scheme if anyone was motivated to do it. ++ * -- paulus ++ */ ++void steal_context(void) ++{ ++ struct mm_struct *mm; ++ /* free up context `next_mmu_context' */ ++ /* if we shouldn't free context 0, don't... */ ++ if (next_mmu_context < FIRST_CONTEXT) ++ next_mmu_context = FIRST_CONTEXT; ++ mm = context_mm[next_mmu_context]; ++ flush_tlb_mm(mm); ++ destroy_context(mm); ++} +--- /dev/null ++++ b/arch/m68k/mm/cf-sram.c +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Lanttor.Guo@freescale.com ++ * ++ * Providing on-chip SRAM allocation and free APIs to kernel ++ * The implemention uses gen_pool_alloc/gen_pool_free interface ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/genalloc.h> ++ ++/* sram memory min allocation size per once */ ++static long blk_size = CONFIG_SRAM_ALLOC_GRANULARITY; ++static struct gen_pool *sram_pool; ++ ++/* ++ * Set up memory pools to manage on-chip sram. ++ * @ start the start address of SRAM ++ * @ size the size of SRAM ++ * return return 0 express success ++ */ ++int declare_sram_pool(void *start, size_t size) ++{ ++ int status = 0; ++ ++ pr_debug("%s %p %d\n", __func__, start, size); ++ ++ sram_pool = gen_pool_create(ilog2(blk_size), -1); ++ if (!sram_pool) { ++ printk(KERN_ERR "gen_pool_creat faile at %s()\n", __func__); ++ status = -ENOMEM; ++ } ++ ++ status = gen_pool_add(sram_pool, (unsigned long)start, size, -1); ++ if (status < 0) ++ printk(KERN_ERR "gen_pool_add failed at %s()\n", __func__); ++ ++ return status; ++ ++} ++ ++/* ++ * Allocate memory from sram pool ++ * @ len the size of allocated memory ++ * return return the start addr of allocated memory ++ */ ++void *sram_alloc(size_t len) ++{ ++ unsigned long vaddr; ++ ++ if (!len) { ++ printk(KERN_ERR "the len parameter of sram_alloc() is zero\n"); ++ return NULL; ++ } ++ ++ vaddr = gen_pool_alloc(sram_pool, len); ++ if (!vaddr) ++ return NULL; ++ ++ return (void *)vaddr; ++} ++EXPORT_SYMBOL(sram_alloc); ++ ++/* ++ * Free memory to sram pool ++ * @ addr the addr of allocated memory ++ * @ len the size of allocated memory ++ */ ++void sram_free(void *addr, size_t len) ++{ ++ gen_pool_free(sram_pool, (unsigned long)addr, len); ++} ++EXPORT_SYMBOL(sram_free); +--- a/arch/m68k/mm/hwtest.c ++++ b/arch/m68k/mm/hwtest.c +@@ -12,6 +12,14 @@ + * them here complete with the comments from the original atari + * config.c... + * -- PMM <pmaydell@chiark.greenend.org.uk>, 05/1998 ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + /* This function tests for the presence of an address, specially a +@@ -25,6 +33,7 @@ + + #include <linux/module.h> + ++#ifndef CONFIG_COLDFIRE + int hwreg_present( volatile void *regp ) + { + int ret = 0; +@@ -82,4 +91,5 @@ int hwreg_write( volatile void *regp, un + return( ret ); + } + EXPORT_SYMBOL(hwreg_write); ++#endif + +--- a/arch/m68k/mm/init.c ++++ b/arch/m68k/mm/init.c +@@ -2,6 +2,13 @@ + * linux/arch/m68k/mm/init.c + * + * Copyright (C) 1995 Hamish Macdonald ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + * + * Contains common initialization routines, specific init code moved + * to motorola.c and sun3mmu.c +@@ -32,6 +39,7 @@ + #include <asm/sections.h> + #include <asm/tlb.h> + ++ + DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + + pg_data_t pg_data_map[MAX_NUMNODES]; +@@ -113,7 +121,7 @@ void __init mem_init(void) + } + } + +-#ifndef CONFIG_SUN3 ++#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) + /* insert pointer tables allocated so far into the tablelist */ + init_pointer_table((unsigned long)kernel_pg_dir); + for (i = 0; i < PTRS_PER_PGD; i++) { +@@ -132,6 +140,11 @@ void __init mem_init(void) + codepages << (PAGE_SHIFT-10), + datapages << (PAGE_SHIFT-10), + initpages << (PAGE_SHIFT-10)); ++ ++#ifdef CONFIG_VDSO ++ /* init the vdso page */ ++ vdso_init(); ++#endif + } + + #ifdef CONFIG_BLK_DEV_INITRD +--- a/arch/m68k/mm/kmap.c ++++ b/arch/m68k/mm/kmap.c +@@ -2,6 +2,13 @@ + * linux/arch/m68k/mm/kmap.c + * + * Copyright (C) 1997 Roman Hodek ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + * + * 10/01/99 cleaned up the code and changing to the same interface + * used by other architectures /Roman Zippel +@@ -24,7 +31,11 @@ + + #undef DEBUG + ++#ifndef CONFIG_COLDFIRE + #define PTRTREESIZE (256*1024) ++#else ++#define PTRTREESIZE PAGE_SIZE ++#endif + + /* + * For 040/060 we can use the virtual memory area like other architectures, +@@ -50,7 +61,11 @@ static inline void free_io_area(void *ad + + #else + ++#ifdef CONFIG_COLDFIRE ++#define IO_SIZE PAGE_SIZE ++#else + #define IO_SIZE (256*1024) ++#endif + + static struct vm_struct *iolist; + +@@ -126,8 +141,58 @@ void __iomem *__ioremap(unsigned long ph + } + #endif + ++#ifdef CONFIG_M5445X ++ if (physaddr >= 0xf0000000) { ++ /* ++ * On the M5445x processors an ACR is setup to map ++ * the 0xF0000000 range into kernel memory as ++ * non-cacheable. ++ */ ++ return (void __iomem *)physaddr; ++ } ++ if ((physaddr >= KMAP_START) && (physaddr <= KMAP_END)) { ++ /* if physaddr belongs to virtual address range for ioremap, ++ * then return physaddr because it has been ioremapped ++ */ ++ return (void __iomem *)physaddr; ++ } ++#endif ++#ifdef CONFIG_M547X_8X ++ if (physaddr >= 0xf0000000) { ++ /* ++ * On the M547x/M548x processors an ACR is setup to map ++ * the 0xF0000000 range into kernel memory as ++ * non-cacheable. ++ */ ++ return (void __iomem *)physaddr; ++ } ++ ++ if ((physaddr >= 0xd0000000) && (physaddr + size < 0xd800ffff)) { ++ printk(KERN_ERR "ioremap:PCI 0x%lx,0x%lx(%d)" ++ " - PCI area hit\n", physaddr, size, cacheflag); ++ return (void *)physaddr; ++ } ++#endif ++#ifdef CONFIG_M5441X ++ if (physaddr >= 0xe0000000) { ++ /* ++ * On the M5441x processors an ACR is setup to map ++ * the 0xe0000000 range into kernel memory as ++ * non-cacheable. ++ */ ++ return (void __iomem *)physaddr; ++ } ++ if ((physaddr >= KMAP_START) && (physaddr <= KMAP_END)) { ++ /* if physaddr belongs to virtual address range for ioremap, ++ * then return physaddr because it has been ioremapped ++ */ ++ return (void __iomem *)physaddr; ++ } ++#endif ++ + #ifdef DEBUG +- printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag); ++ printk(KERN_ERR "ioremap: paddr=0x%lx,size=0x%lx(%d) - ", ++ physaddr, size, cacheflag); + #endif + /* + * Mappings have to be aligned +@@ -146,7 +211,8 @@ void __iomem *__ioremap(unsigned long ph + virtaddr = (unsigned long)area->addr; + retaddr = virtaddr + offset; + #ifdef DEBUG +- printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr); ++ printk(KERN_ERR " paddr=0x%lx,vaddr=0x%lx,retaddr=0x%lx", ++ physaddr, virtaddr, retaddr); + #endif + + /* +@@ -171,7 +237,12 @@ void __iomem *__ioremap(unsigned long ph + break; + } + } else { ++#ifndef CONFIG_COLDFIRE + physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); ++#else ++ physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | \ ++ _PAGE_READWRITE); ++#endif + switch (cacheflag) { + case IOMAP_NOCACHE_SER: + case IOMAP_NOCACHE_NONSER: +@@ -251,6 +322,13 @@ void __iounmap(void *addr, unsigned long + pmd_t *pmd_dir; + pte_t *pte_dir; + ++#ifdef CONFIG_M547X_8X ++ if ((addr >= (void *)0xd0000000) ++ && (addr + size < (void *)0xd800ffff)) { ++ printk(KERN_ERR "%s: PCI address\n", __func__); ++ return; ++ } ++#endif + while ((long)size > 0) { + pgd_dir = pgd_offset_k(virtaddr); + if (pgd_bad(*pgd_dir)) { +--- a/arch/m68k/mm/memory.c ++++ b/arch/m68k/mm/memory.c +@@ -2,6 +2,13 @@ + * linux/arch/m68k/mm/memory.c + * + * Copyright (C) 1995 Hamish Macdonald ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. + */ + + #include <linux/module.h> +@@ -127,6 +134,7 @@ int free_pointer_table (pmd_t *ptable) + return 0; + } + ++#ifndef CONFIG_COLDFIRE + /* invalidate page in both caches */ + static inline void clear040(unsigned long paddr) + { +@@ -173,6 +181,7 @@ static inline void pushcl040(unsigned lo + clear040(paddr); + local_irq_restore(flags); + } ++#endif /* CONFIG_COLDFIRE */ + + /* + * 040: Hit every page containing an address in the range paddr..paddr+len-1. +@@ -203,6 +212,9 @@ static inline void pushcl040(unsigned lo + + void cache_clear (unsigned long paddr, int len) + { ++#ifdef CONFIG_COLDFIRE ++ flush_bcache(); ++#else + if (CPU_IS_040_OR_060) { + int tmp; + +@@ -237,6 +249,7 @@ void cache_clear (unsigned long paddr, i + if(mach_l2_flush) + mach_l2_flush(0); + #endif ++#endif /* CONFIG_COLDFIRE */ + } + EXPORT_SYMBOL(cache_clear); + +@@ -250,6 +263,9 @@ EXPORT_SYMBOL(cache_clear); + + void cache_push (unsigned long paddr, int len) + { ++#ifdef CONFIG_COLDFIRE ++ flush_bcache(); ++#else + if (CPU_IS_040_OR_060) { + int tmp = PAGE_SIZE; + +@@ -290,6 +306,7 @@ void cache_push (unsigned long paddr, in + if(mach_l2_flush) + mach_l2_flush(1); + #endif ++#endif /* CONFIG_COLDFIRE */ + } + EXPORT_SYMBOL(cache_push); + +--- a/fs/namespace.c ++++ b/fs/namespace.c +@@ -3,6 +3,10 @@ + * + * (C) Copyright Al Viro 2000, 2001 + * Released under GPL v2. ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Change to align on page size for coldfire ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com + * + * Based on code from fs/super.c, copyright Linus Torvalds and others. + * Heavily rewritten. +@@ -2161,7 +2165,11 @@ int copy_mount_options(const void __user + /* copy_from_user cannot cross TASK_SIZE ! */ + size = TASK_SIZE - (unsigned long)data; + if (size > PAGE_SIZE) ++#ifndef CONFIG_COLDFIRE + size = PAGE_SIZE; ++#else ++ size = PAGE_SIZE - ((unsigned long)data & ~PAGE_MASK); ++#endif + + i = size - exact_copy_from_user((void *)page, data, size); + if (!i) { +--- a/include/linux/fsl_devices.h ++++ b/include/linux/fsl_devices.h +@@ -6,7 +6,7 @@ + * + * Maintainer: Kumar Gala <galak@kernel.crashing.org> + * +- * Copyright 2004 Freescale Semiconductor, Inc ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the +@@ -18,7 +18,7 @@ + #define _FSL_DEVICE_H_ + + #include <linux/types.h> +- ++#include <linux/interrupt.h> + /* + * Some conventions on how we handle peripherals on Freescale chips + * +@@ -119,4 +119,14 @@ int fsl_deep_sleep(void); + static inline int fsl_deep_sleep(void) { return 0; } + #endif + ++struct fsl_ata_platform_data { ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ int udma_mask; /* UDMA modes h/w can handle */ ++ int fifo_alarm; /* value for fifo_alarm reg */ ++ int max_sg; /* longest sglist h/w can handle */ ++#endif ++ int (*init)(struct platform_device *pdev); ++ void (*exit)(void); ++ int (*get_clk_rate)(void); ++}; + #endif /* _FSL_DEVICE_H_ */ diff --git a/target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch b/target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch new file mode 100644 index 000000000..82fc1eda7 --- /dev/null +++ b/target/linux/coldfire/patches/002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch @@ -0,0 +1,10546 @@ +From f46a96f02d74535e928710eaebffe6c8b201b76a Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:37 +0800 +Subject: [PATCH 02/52] MCF54451 and MCF54455 support in Linux 2.6.38 + +Add MCF54451 and MCF54455 support in Linux 2.6.38. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5445x/Makefile | 20 + + arch/m68k/coldfire/m5445x/config.c | 599 ++++++++++ + arch/m68k/coldfire/m5445x/devices.c | 527 +++++++++ + arch/m68k/configs/m54451evb_defconfig | 1412 +++++++++++++++++++++++ + arch/m68k/configs/m54455evb_defconfig | 1597 +++++++++++++++++++++++++++ + arch/m68k/include/asm/cf_5445x_cacheflush.h | 534 +++++++++ + arch/m68k/include/asm/mcf5445x_ccm.h | 206 ++++ + arch/m68k/include/asm/mcf5445x_dspi.h | 665 +++++++++++ + arch/m68k/include/asm/mcf5445x_dtim.h | 96 ++ + arch/m68k/include/asm/mcf5445x_edma.h | 1472 ++++++++++++++++++++++++ + arch/m68k/include/asm/mcf5445x_eport.h | 117 ++ + arch/m68k/include/asm/mcf5445x_fbcs.h | 200 ++++ + arch/m68k/include/asm/mcf5445x_gpio.h | 1411 +++++++++++++++++++++++ + arch/m68k/include/asm/mcf5445x_intc.h | 724 ++++++++++++ + arch/m68k/include/asm/mcf5445x_pci.h | 238 ++++ + arch/m68k/include/asm/mcf5445x_pciarb.h | 40 + + arch/m68k/include/asm/mcf5445x_rtc.h | 114 ++ + arch/m68k/include/asm/mcf5445x_scm.h | 48 + + arch/m68k/include/asm/mcf5445x_sdramc.h | 142 +++ + arch/m68k/include/asm/mcf5445x_ssi.h | 187 ++++ + arch/m68k/include/asm/mcf5445x_xbs.h | 81 ++ + 21 files changed, 10430 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m5445x/Makefile + create mode 100644 arch/m68k/coldfire/m5445x/config.c + create mode 100644 arch/m68k/coldfire/m5445x/devices.c + create mode 100644 arch/m68k/configs/m54451evb_defconfig + create mode 100644 arch/m68k/configs/m54455evb_defconfig + create mode 100644 arch/m68k/include/asm/cf_5445x_cacheflush.h + create mode 100644 arch/m68k/include/asm/mcf5445x_ccm.h + create mode 100644 arch/m68k/include/asm/mcf5445x_dspi.h + create mode 100644 arch/m68k/include/asm/mcf5445x_dtim.h + create mode 100644 arch/m68k/include/asm/mcf5445x_edma.h + create mode 100644 arch/m68k/include/asm/mcf5445x_eport.h + create mode 100644 arch/m68k/include/asm/mcf5445x_fbcs.h + create mode 100644 arch/m68k/include/asm/mcf5445x_gpio.h + create mode 100644 arch/m68k/include/asm/mcf5445x_intc.h + create mode 100644 arch/m68k/include/asm/mcf5445x_pci.h + create mode 100644 arch/m68k/include/asm/mcf5445x_pciarb.h + create mode 100644 arch/m68k/include/asm/mcf5445x_rtc.h + create mode 100644 arch/m68k/include/asm/mcf5445x_scm.h + create mode 100644 arch/m68k/include/asm/mcf5445x_sdramc.h + create mode 100644 arch/m68k/include/asm/mcf5445x_ssi.h + create mode 100644 arch/m68k/include/asm/mcf5445x_xbs.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for Linux arch/m68k/coldfire/m5445x source directory ++# ++ ++obj-$(CONFIG_M5445X) += devices.o config.o ++ ++ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) ++ obj-y += usb.o ++endif ++ifneq ($(strip $(CONFIG_USB_GADGET_FSL_USB2) $(CONFIG_USB_EHCI_HCD)),) ++ obj-y += usb_dr.o ++endif ++ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) ++ obj-y += xcvr.o ++endif ++ ++obj-$(CONFIG_PCI) += pci.o mcf5445x-pci.o ++ifneq ($(CONFIG_FEC),) ++obj-y += fec.o ++endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/config.c +@@ -0,0 +1,599 @@ ++/* ++ * linux/arch/m68k/coldfire/config_m5445x.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: ++ * Kurt Mahan kmahan@freescale.com ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/string.h> ++#include <linux/kernel.h> ++#include <linux/console.h> ++#include <linux/bootmem.h> ++#include <linux/mm.h> ++#include <linux/sched.h> ++#include <linux/clockchips.h> ++#include <linux/delay.h> ++#include <asm/bootinfo.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/cfcache.h> ++#include <asm/cacheflush.h> ++#include <asm/io.h> ++#include <asm/cfmmu.h> ++#include <asm/setup.h> ++#include <asm/irq.h> ++#include <asm/traps.h> ++#include <asm/movs.h> ++#include <asm/movs.h> ++#include <asm/page.h> ++#include <asm/pgalloc.h> ++#include <asm/cf-sram.h> ++ ++#include <asm/mcfsim.h> ++ ++#define UBOOT_EXTRA_CLOCKS ++#include <asm/bootinfo.h> ++ ++#include <asm/mcf5445x_intc.h> ++#include <asm/mcf5445x_sdramc.h> ++#include <asm/mcf5445x_fbcs.h> ++#include <asm/mcf5445x_dtim.h> ++#include <asm/mcf5445x_xbs.h> ++ ++extern int get_irq_list(struct seq_file *p, void *v); ++extern char _text, _end; ++extern char _etext, _edata, __init_begin, __init_end; ++extern struct console mcfrs_console; ++extern char m68k_command_line[CL_SIZE]; ++extern unsigned long availmem; ++extern unsigned long shadow_cacr; ++EXPORT_SYMBOL(shadow_cacr); ++extern struct mem_info m68k_ramdisk; ++ ++static int irq_enable[NR_IRQS]; ++unsigned long num_pages; ++ ++/* cf dma physical addresses */ ++unsigned long cf_dma_base; ++EXPORT_SYMBOL(cf_dma_base); ++unsigned long cf_dma_end; ++EXPORT_SYMBOL(cf_dma_end); ++unsigned long cf_dma_size; ++EXPORT_SYMBOL(cf_dma_size); ++ ++/* ethernet mac addresses from uboot */ ++unsigned char uboot_enet0[6]; ++unsigned char uboot_enet1[6]; ++ ++void coldfire_sort_memrec(void) ++{ ++ int i, j; ++ ++ /* Sort the m68k_memory records by address */ ++ for (i = 0; i < m68k_num_memory; ++i) { ++ for (j = i + 1; j < m68k_num_memory; ++j) { ++ if (m68k_memory[i].addr > m68k_memory[j].addr) { ++ struct mem_info tmp; ++ tmp = m68k_memory[i]; ++ m68k_memory[i] = m68k_memory[j]; ++ m68k_memory[j] = tmp; ++ } ++ } ++ } ++ /* Trim off discontiguous bits */ ++ for (i = 1; i < m68k_num_memory; ++i) { ++ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) != ++ m68k_memory[i].addr) { ++ printk(KERN_DEBUG "m68k_parse_bootinfo: " ++ "addr gap between 0x%lx & 0x%lx\n", ++ m68k_memory[i-1].addr+m68k_memory[i-1].size, ++ m68k_memory[i].addr); ++ m68k_num_memory = i; ++ break; ++ } ++ } ++} ++ ++/* ++ * UBoot Handler ++ */ ++int __init uboot_commandline(char *bootargs) ++{ ++ int len = 0, cmd_line_len; ++ static struct uboot_record uboot_info; ++ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; ++ ++ extern unsigned long uboot_info_stk; ++ ++ /* validate address */ ++ if ((uboot_info_stk < PAGE_OFFSET_RAW) || ++ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE))) ++ return 0; ++ ++ /* Add offset to get post-remapped kernel memory location */ ++ uboot_info.bdi = (struct bd_info *) ++ ((*(u32 *)(uboot_info_stk)) + offset); ++ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset; ++ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset; ++ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset; ++ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset; ++ ++#if defined(CONFIG_BLK_DEV_INITRD) ++ m68k_ramdisk.addr = uboot_info.initrd_start; ++ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ? ++ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0; ++#endif ++ ++ /* copy over mac addresses */ ++ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6); ++ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6); ++ ++ /* copy command line */ ++ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start; ++ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1)) ++ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\ ++ cmd_line_len); ++ ++ return len; ++} ++ ++#if defined(CONFIG_M54451) ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \ ++ ip=172.27.155.51:172.27.155.1" ++#elif defined(CONFIG_M54455) ++#define MTD_DEFAULT_COMMAND_LINE \ ++ "root=/dev/mtdblock1 rw rootfstype=jffs2 \ ++ ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \ ++ ip=172.27.155.55:172.27.155.1" ++#endif ++ ++ ++/* ++ * Early Coldfire Initialization. ++ */ ++asmlinkage void __init cf_early_init(void) ++{ ++ SET_VBR((void *)MCF_RAMBAR1); ++ ++ /* Mask all interrupts */ ++ MCF_INTC0_IMRL = 0xFFFFFFFF; ++ MCF_INTC0_IMRH = 0xFFFFFFFF; ++ MCF_INTC1_IMRL = 0xFFFFFFFF; ++ MCF_INTC1_IMRH = 0xFFFFFFFF; ++ ++#if defined(CONFIG_NOR_FLASH_BASE) ++ MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE; ++#else ++ MCF_FBCS_CSAR(1) = 0x00000000; ++#endif ++ ++#if CONFIG_SDRAM_SIZE > (256*1024*1024) ++ /* Init optional SDRAM chip select */ ++ MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B; ++#endif ++ ++ MCF_XBS_CRS2 = 0x100; ++ /* Setup SDRAM crossbar(XBS) priorities */ ++ MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | /*CPU*/ ++ MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | /*eDMA*/ ++ MCF_XBS_PRS_M2(MCF_XBS_PRI_1) | /*FEC0*/ ++ MCF_XBS_PRS_M3(MCF_XBS_PRI_5) | /*FEC1*/ ++ MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | /*PCI*/ ++ MCF_XBS_PRS_M6(MCF_XBS_PRI_4) | /*USB*/ ++ MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); /*SBF*/ ++ ++ m68k_machtype = MACH_CFMMU; ++ m68k_fputype = FPU_CFV4E; ++ m68k_mmutype = MMU_CFV4E; ++ m68k_cputype = CPU_CFV4E; ++ ++ /* initialize PHYSRAM */ ++ m68k_num_memory = 0; ++ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; /* phys */ ++ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE; ++ ++ if (!uboot_commandline(m68k_command_line)) { ++#if defined(CONFIG_BOOTPARAM) ++ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1); ++#else ++ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); ++#endif ++ } ++ ++ /* Invalidate caches via CACR */ ++ flush_bcache(); ++ cacr_set(CACHE_DISABLE_MODE); ++ ++ /* Turn on caches via CACR, enable EUSP */ ++ cacr_set(CACHE_INITIAL_MODE); ++} ++ ++/* Assembler routines */ ++asmlinkage void buserr(void); ++asmlinkage void trap(void); ++asmlinkage void system_call(void); ++asmlinkage void inthandler(void); ++ ++void __init coldfire_trap_init(void) ++{ ++ int i = 0; ++ e_vector *vectors; ++ ++ vectors = (e_vector *)MCF_RAMBAR1; ++ /* ++ * There is a common trap handler and common interrupt ++ * handler that handle almost every vector. We treat ++ * the system call and bus error special, they get their ++ * own first level handlers. ++ */ ++ for (i = 3; (i <= 23); i++) ++ vectors[i] = trap; ++ for (i = 33; (i <= 63); i++) ++ vectors[i] = trap; ++ for (i = 24; (i <= 31); i++) ++ vectors[i] = inthandler; ++ for (i = 64; (i < 255); i++) ++ vectors[i] = inthandler; ++ ++ vectors[255] = 0; ++ vectors[2] = buserr; ++ vectors[32] = system_call; ++} ++ ++void settimericr(unsigned int timer, unsigned int level) ++{ ++ volatile unsigned char *icrp; ++ unsigned int icr = 0; ++ unsigned char irq = 0; ++ ++ if (timer <= 3) { ++ switch (timer) { ++ case 0: ++ irq = 32; ++ icr = MCFSIM_ICR_TIMER0; ++ break; ++ case 1: ++ irq = 33; ++ icr = MCFSIM_ICR_TIMER1; ++ break; ++ case 2: ++ irq = 34; ++ icr = MCFSIM_ICR_TIMER2; ++ break; ++ case 3: ++ irq = 35; ++ icr = MCFSIM_ICR_TIMER3; ++ break; ++ } ++ ++ icrp = (volatile unsigned char *) (icr); ++ *icrp = level; ++ coldfire_enable_irq0(irq); ++ } ++} ++ ++void coldfire_sched_clk_init(void); ++ ++void coldfire_tick(void) ++{ ++ /* Reset the ColdFire timer */ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER); ++} ++ ++void __init coldfire_sched_init(irq_handler_t handler) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32; ++ ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR); ++ __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 | ++ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \ ++ MCF_DTIM0_DTMR); ++ ++ request_irq(mcf_timervector, handler, IRQF_DISABLED, \ ++ "timer", (void *)MCF_DTIM0_DTMR); ++ ++ settimericr(0, mcf_timerlevel); ++ ++ /* initialize the fast clock */ ++ coldfire_sched_clk_init(); ++} ++ ++int timerirqpending(int timer) ++{ ++ unsigned int imr = 0; ++ unsigned ret = 0; ++ ++ switch (timer) { ++ case 1: ++ imr = 0x1; ++ break; ++ case 2: ++ imr = 0x2; ++ break; ++ default: ++ break; ++ } ++ ++ ret = getiprh() & imr; ++ return ret; ++} ++ ++unsigned long coldfire_gettimeoffset(void) ++{ ++ volatile unsigned long trr, tcn, offset; ++ ++ tcn = __raw_readw(MCF_DTIM0_DTCN); ++ trr = __raw_readl(MCF_DTIM0_DTRR); ++ offset = (tcn * (1000000 / HZ)) / trr; ++ ++ /* Check if we just wrapped the counters and maybe missed a tick */ ++ if ((offset < (1000000 / HZ / 2)) && timerirqpending(1)) ++ offset += 1000000 / HZ; ++ return offset; ++} ++ ++/* sched_clock support */ ++ ++static unsigned long long sched_clk_val; ++ ++static irqreturn_t coldfire_sched_clk_irq(int irq, void *dev) ++{ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM3_DTER); ++ sched_clk_val += 0x100000000LL; ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Setup DTIM3 as the 5445x sched_clock() implementation. The ++ * input frequency to the clock is the internal bus clock (MCF_BUSCLK) ++ * which is the system clock (MCF_CLK) / 2. ++ * ++ * On a system running at 266Mhz: ++ * MCF_CLK = 266Mhz (266000000) ++ * MCF_BUSCLK = 133Mhz (133000000) ++ * DTIM3 Tick = 133Mhz (133000000) ++ * Tick Resolution = 7.5ns (round to 8ns/Tick) ++ * ++ * On a system running at 240Mhz: ++ * MCF_CLK = 240Mhz (240000000) ++ * MCF_BUSCLK = 120Mhz (120000000) ++ * DTIM3 Tick = 120Mhz (120000000) ++ * Tick Resolution = 8.4ns (round to 8ns/Tick) ++ */ ++void __init coldfire_sched_clk_init(void) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32+3; /* DTIM3 */ ++ ++ printk(KERN_INFO "Initializing DTIM3 for sched_clock\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM3_DTMR); ++ __raw_writel(0xffffffff, MCF_DTIM3_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV1 | \ ++ MCF_DTIM_DTMR_RST_EN, MCF_DTIM3_DTMR); ++ ++ sched_clk_val = 0; ++ request_irq(mcf_timervector, coldfire_sched_clk_irq, IRQF_DISABLED, \ ++ "timer", (void *)MCF_DTIM3_DTMR); ++ ++ settimericr(3, mcf_timerlevel); ++} ++ ++#ifndef CONFIG_GENERIC_CLOCKEVENTS ++/* get highres timer */ ++unsigned long long sched_clock(void) ++{ ++ unsigned long long ret = 0; ++ ret = sched_clk_val | (unsigned long long)(MCF_REG32(MCF_DTIM3_DTCN)); ++ ret = ret << 3; ++ return ret; ++} ++ ++#else /*CONFIG_GENERIC_CLOCKEVENTS*/ ++ ++static unsigned long long sched_dtim_clk_val; ++ ++unsigned long long sched_clock(void) ++{ ++ unsigned long flags; ++ unsigned long long tcn, cycles; ++ ++ local_irq_save(flags); ++ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN))); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ return cycles + tcn; ++} ++ ++unsigned long long sys_dtim2_read(void) ++{ ++ unsigned long flags; ++ unsigned long long tcn, cycles; ++ ++ local_irq_save(flags); ++ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN))); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + tcn; ++} ++ ++static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev) ++{ ++ struct clock_event_device *evt = (struct clock_event_device *)dev; ++ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM2_DTER); ++ sched_dtim_clk_val += (MCF_BUSCLK / 16) / HZ; ++ evt->event_handler(evt); ++ return IRQ_HANDLED; ++} ++ ++void sys_dtim2_init(struct clock_event_device *evt) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32+2; /* DTIM2 */ ++ ++ printk(KERN_INFO "Initializing DTIM2 for sched_clock\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM2_DTMR); ++ __raw_writel(((MCF_BUSCLK / 16) / HZ)-1, MCF_DTIM2_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 | ++ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \ ++ MCF_DTIM2_DTMR); ++ ++ request_irq(mcf_timervector, coldfire_dtim_clk_irq, IRQF_DISABLED, \ ++ "timer2", (void *)evt); ++ ++ settimericr(3, mcf_timerlevel); ++ return; ++} ++ ++#endif ++ ++void coldfire_reboot(void) ++{ ++ /* disable interrupts and do a software reset */ ++ asm("movew #0x2700, %%sr\n\t" ++ "moveb #0x40, %%d0\n\t" ++ "moveb %%d0, 0xfc0a0000\n\t" ++ : : : "%d0"); ++ ++ mdelay(10); ++ ++ asm("moveb #0xc0, %%d0\n\t" ++ "moveb %%d0, 0xfc0a0000\n\t" ++ : : : "%d0"); ++} ++ ++static void coldfire_get_model(char *model) ++{ ++ sprintf(model, "Version 4 ColdFire"); ++} ++ ++/* ++ * Setup the nodes and the boot memory. ++ * ++ * memory_start and memory_end are VIRTUAL addresses ++ */ ++static void __init ++coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end) ++{ ++ unsigned long base_pfn; ++ ++ /* compute total pages in system */ ++ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT; ++ ++ /* align start/end to page boundries */ ++ memory_start = PAGE_ALIGN(memory_start); ++ memory_end = memory_end & PAGE_MASK; ++ ++ /* page numbers */ ++ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT; ++ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT; ++ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT; ++ ++ high_memory = (void *)memory_end; ++ availmem = memory_start; ++ ++ /* setup bootmem data */ ++ m68k_setup_node(0); ++ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn, ++ base_pfn, max_low_pfn); ++ availmem = PAGE_ALIGN(availmem); ++ ++ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n", ++ availmem, __pa(availmem)); ++ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n", ++ memory_start, memory_end); ++ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n", ++ base_pfn, min_low_pfn, max_low_pfn); ++ ++ /* turn over physram */ ++ free_bootmem(__pa(availmem), memory_end - availmem); ++ ++ /* configure physical dma area */ ++ cf_dma_base = __pa(PAGE_ALIGN(memory_start)); ++ cf_dma_size = CONFIG_DMA_SIZE; ++ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1; ++ ++ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n", ++ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE); ++ ++ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n", ++ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS)); ++} ++ ++/* ++ * Architecture setup for Coldfire ++ */ ++void __init config_coldfire(void) ++{ ++ unsigned long endmem, startmem; ++ ++ /* ++ * Calculate endmem from m68k_memory[0] assuming that a single ++ * chunk of ram is being configured. ++ */ ++ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK); ++ endmem = PAGE_OFFSET + m68k_memory[0].size; ++ ++ /* set virt to node shift to be the high nibble byte */ ++ m68k_virt_to_node_shift = 28; ++ ++ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \ ++ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20); ++ ++ memset(irq_enable, 0, sizeof(irq_enable)); ++ ++ /* ++ * Setup coldfire mach-specific handlers ++ */ ++ mach_max_dma_address = 0xffffffff; ++ mach_sched_init = coldfire_sched_init; ++ mach_tick = coldfire_tick; ++ mach_gettimeoffset = coldfire_gettimeoffset; ++ mach_reset = coldfire_reboot; ++ mach_get_model = coldfire_get_model; ++ ++ coldfire_bootmem_alloc(startmem, endmem-1); ++ ++#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE) ++ conswitchp = &dummy_con; ++#endif ++ ++#if defined(CONFIG_SERIAL_COLDFIRE) ++ /* ++ * This causes trouble when it is re-registered later. ++ * Currently this is fixed by conditionally commenting ++ * out the register_console in mcf_serial.c ++ */ ++/*JKM -- moved earlier*/ ++ register_console(&mcfrs_console); ++#endif ++} ++ ++#ifdef CONFIG_SRAM ++static int __init setup_sram_pool(void) ++{ ++ declare_sram_pool((void *)CONFIG_SRAM_BASE, CONFIG_SRAM_SIZE); ++ return 0; ++} ++postcore_initcall(setup_sram_pool); ++#endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/devices.c +@@ -0,0 +1,527 @@ ++/* ++ * arch/m68k/coldfire/mcf5445x-devices.c ++ * ++ * Coldfire M5445x Platform Device Configuration ++ * ++ * Based on the Freescale MXC devices.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/spi/spi.h> ++ ++#include <linux/interrupt.h> ++#include <linux/init.h> ++#ifdef CONFIG_MMC_SPI ++#include <linux/mmc/host.h> ++#include <linux/spi/mmc_spi.h> ++#endif ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfuart.h> ++#include <asm/mcfqspi.h> ++#include <asm/mcfdspi.h> ++#include <asm/cf_io.h> ++ ++/* ATA Interrupt */ ++#define IRQ_ATA (64 + 64 + 54) ++ ++/* ATA Base */ ++void __iomem *io_ata_map; ++unsigned long io_ata_mapsize = 16 * 1024 * 1024; ++#define BASE_IO_ATA ((unsigned int)(io_ata_map)) ++#define BASE_IO_ATA_PHY 0x90000000 ++#define IO_ATA_MAP_OFFSET (BASE_IO_ATA-BASE_IO_ATA_PHY) ++ ++/* conversion function between virtual address and physical address */ ++unsigned int io_ata_virt2phys(void *x) ++{ ++ return (unsigned int)x - IO_ATA_MAP_OFFSET; ++} ++ ++void *io_ata_phys2virt(unsigned int x) ++{ ++ return (void *)(x + IO_ATA_MAP_OFFSET); ++} ++ ++#define ATA_IER MCF_REG08(BASE_IO_ATA+0x2c) /* int enable reg */ ++#define ATA_ICR MCF_REG08(BASE_IO_ATA+0x30) /* int clear reg */ ++ ++/* DSPI */ ++#define M5445X_DSPI_MCR 0xfc05c000 /* base */ ++ ++#define M5445X_DSPI_IRQ_SOURCE (31) ++#define M5445X_DSPI_IRQ_VECTOR (64 + M5445X_DSPI_IRQ_SOURCE) ++ ++#define M5445X_AUDIO_IRQ_SOURCE (49) /* SSI interrupt */ ++#define M5445X_AUDIO_IRQ_VECTOR (128+M5445X_AUDIO_IRQ_SOURCE) ++#define M5445X_AUDIO_IRQ_LEVEL (4) ++ ++/* number of supported SPI selects */ ++#define SPI_NUM_CHIPSELECTS 8 ++ ++#define M5445X_SPI_PAR_VAL (MCF_GPIO_PAR_DSPI_SCK | \ ++ MCF_GPIO_PAR_DSPI_SOUT | \ ++ MCF_GPIO_PAR_DSPI_SIN | \ ++ MCF_GPIO_PAR_DSPI_PCS5_PCS5 | \ ++ MCF_GPIO_PAR_DSPI_PCS1_PCS1 | \ ++ MCF_GPIO_PAR_DSPI_PCS0_PCS0) ++ ++#ifdef CONFIG_SPI ++/* ++ * DSPI ++ */ ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++static struct coldfire_dspi_chip spidev_chip_info = { ++ .bits_per_word = 8, ++}; ++#endif ++ ++#if defined(CONFIG_SND_COLDFIRE) || defined(CONFIG_SND_COLDFIRE_MODULE) ++static struct coldfire_dspi_chip codec_spi_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 16, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 2, ++ .br = 8, ++ .pcssck = 1, ++ .pasc = 1, ++ .pdt = 1, ++ .cssck = 0, ++ .asc = 1, ++ .dt = 1, ++}; ++#endif ++ ++#if defined(CONFIG_MMC_SPI) ++int mmc_spi_init(struct device *mmc_spi_device, ++ irqreturn_t mmc_spi_irq_handler(int irq, void *private), ++ void *irq_privatedata) ++{ ++#if 0 ++ MCF_GPIO_PAR_IRQ = MCF_GPIO_PAR_IRQ | MCF_GPIO_PAR_IRQ_IRQ4_GPIO; ++ /* Set trailing edge for PCI interrupts */ ++ MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA4(3); ++ MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA4_LEVEL; ++ /* Turn on irq line in eport */ ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE4; ++#endif ++ MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA7(3); ++ MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++#if defined(CONFIG_M54451_SD_HW_DETECT) ++ MCF_INTC0_ICR7 = 2; ++ if (request_irq(64 + 7, mmc_spi_irq_handler, ++ IRQF_DISABLED, "mmc_spi_irq", irq_privatedata)) { ++ printk(KERN_INFO "Cannot allocate " ++ "eport_irq_lines[%d] IRQ\n", 7); ++ return -EBUSY; ++ } ++ printk(KERN_INFO " extern irq7 as sd card detect\n"); ++#endif ++ return 0; ++} ++ ++static struct coldfire_dspi_chip dspi_sd_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 8, ++ .void_write_data = 0xff, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 2, ++ .pasc = 2, ++ .pdt = 2, ++ .cssck = 5, ++ .asc = 5, ++ .dt = 5, ++}; ++ ++static struct mmc_spi_platform_data mcf54451_mmc_pdata = { ++ .ocr_mask = MMC_VDD_33_34, ++ .init = mmc_spi_init, ++}; ++#endif ++ ++#if defined(CONFIG_VOIP_FXS) || defined(CONFIG_VOIP_FXS_MODULE) ++static struct coldfire_dspi_chip fxs_chip_info = { ++ .mode = SPI_MODE_3, ++ .bits_per_word = 8, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 0, ++ .pasc = 0, ++ .pdt = 0, ++ .cssck = 0, ++ .asc = 0, ++ .dt = 0, ++}; ++#endif ++ ++#if defined(CONFIG_VOIP_FXO) || defined(CONFIG_VOIP_FXO_MODULE) ++static struct coldfire_dspi_chip fxo_chip_info = { ++ .mode = SPI_MODE_3, ++ .bits_per_word = 8, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 0, ++ .pasc = 0, ++ .pdt = 0, ++ .cssck = 0, ++ .asc = 0, ++ .dt = 0, ++}; ++#endif ++ ++static struct spi_board_info spi_board_info[] = { ++#if defined(CONFIG_SND_COLDFIRE) || defined(CONFIG_SND_COLDFIRE_MODULE) ++ { ++ .modalias = "mcf_codec_spi", ++ .max_speed_hz = 300000, ++ .bus_num = 1, ++ .chip_select = 5, ++ .irq = M5445X_AUDIO_IRQ_VECTOR, ++ .platform_data = NULL, ++ .controller_data = &codec_spi_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_VOIP_FXS) || defined(CONFIG_VOIP_FXS_MODULE) ++ { ++ .modalias = "spi_fxs", ++ .max_speed_hz = 10000000, /* max spi clock in HZ */ ++ .bus_num = 1, ++ .chip_select = 2, ++ .controller_data = &fxs_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_VOIP_FXO) || defined(CONFIG_VOIP_FXO_MODULE) ++ { ++ .modalias = "spi_fxo", ++ .max_speed_hz = 10000000, /* max spi clock in HZ */ ++ .bus_num = 1, ++ .chip_select = 3, ++ .controller_data = &fxo_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */ ++ .bus_num = 1, ++ .chip_select = 0, /* CS0 */ ++ .controller_data = &spidev_chip_info, ++ }, ++#endif ++ ++#if defined(CONFIG_MMC_SPI) ++ { ++ .modalias = "mmc_spi", ++ .max_speed_hz = 25000000, ++ .bus_num = 1, ++ .chip_select = 0, ++ .platform_data = &mcf54451_mmc_pdata, ++ .controller_data = &dspi_sd_chip_info, ++ }, ++#endif ++}; ++ ++ ++static struct coldfire_spi_master coldfire_master_info = { ++ .bus_num = 1, ++ .num_chipselect = SPI_NUM_CHIPSELECTS, ++ .irq_list = 0, /* not used */ ++ .irq_source = M5445X_DSPI_IRQ_SOURCE, ++ .irq_vector = M5445X_DSPI_IRQ_VECTOR, ++ .irq_mask = (1 << M5445X_DSPI_IRQ_SOURCE), ++ .irq_lp = 0x2, /* irq level */ ++ .par_val = M5445X_SPI_PAR_VAL, ++ .cs_control = NULL, ++}; ++ ++static struct resource coldfire_spi_resources[] = { ++ [0] = { ++ .name = "spi-par", ++ .start = (u32)&MCF_GPIO_PAR_DSPI, /* PAR_DSPI */ ++ .end = (u32)&MCF_GPIO_PAR_DSPI, /* PAR_DSPI */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [1] = { ++ .name = "spi-module", ++ .start = M5445X_DSPI_MCR, /* DSPI MCR Base */ ++ .end = M5445X_DSPI_MCR + 0xc0, /* DSPI mem map end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [2] = { ++ .name = "spi-int-level", ++ .start = (u32)&MCF_INTC0_ICR31, /* ICR start */ ++ .end = (u32)&MCF_INTC0_ICR31, /* ICR end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [3] = { ++ .name = "spi-int-mask", ++ .start = (u32)&MCF_INTC0_IMRL, /* IMRL */ ++ .end = (u32)&MCF_INTC0_IMRL, /* IMRL */ ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct platform_device coldfire_spi = { ++ .name = "spi_coldfire", ++ .id = -1, ++ .resource = coldfire_spi_resources, ++ .num_resources = ARRAY_SIZE(coldfire_spi_resources), ++ .dev = { ++ .platform_data = &coldfire_master_info, ++ } ++}; ++ ++/** ++ * m5445x_spi_init - Initialize SPI ++ */ ++static int __init m5445x_spi_init(void) ++{ ++ int retval; ++ ++ /* register device */ ++ retval = platform_device_register(&coldfire_spi); ++ if (retval < 0) ++ goto out; ++ ++ /* register board info */ ++ if (ARRAY_SIZE(spi_board_info)) ++ retval = spi_register_board_info(spi_board_info, ++ ARRAY_SIZE(spi_board_info)); ++ ++out: ++ return retval; ++} ++#endif ++ ++/* ++ * On-chip PATA ++ */ ++#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) ++static int ata_init(struct platform_device *pdev) ++{ ++ /* clear ints */ ++ ATA_IER = 0x00; ++ ATA_ICR = 0xff; ++ ++ /* setup shared pins */ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & MCF_GPIO_PAR_FEC_FEC1_MASK) | ++ MCF_GPIO_PAR_FEC_FEC1_ATA; ++ ++ MCF_GPIO_PAR_FECI2C = (MCF_GPIO_PAR_FECI2C & ++ (MCF_GPIO_PAR_FECI2C_MDC1_MASK & ++ MCF_GPIO_PAR_FECI2C_MDIO1_MASK)) | ++ MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR | ++ MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW; ++ ++ MCF_GPIO_PAR_ATA = MCF_GPIO_PAR_ATA_BUFEN | ++ MCF_GPIO_PAR_ATA_CS1 | ++ MCF_GPIO_PAR_ATA_CS0 | ++ MCF_GPIO_PAR_ATA_DA2 | ++ MCF_GPIO_PAR_ATA_DA1 | ++ MCF_GPIO_PAR_ATA_DA0 | ++ MCF_GPIO_PAR_ATA_RESET_RESET | ++ MCF_GPIO_PAR_ATA_DMARQ_DMARQ | ++ MCF_GPIO_PAR_ATA_IORDY_IORDY; ++ ++ MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI & ++ (MCF_GPIO_PAR_PCI_GNT3_MASK & ++ MCF_GPIO_PAR_PCI_REQ3_MASK)) | ++ MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK | ++ MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ; ++ ++ return 0; ++} ++ ++static void ata_exit(void) ++{ ++ printk(KERN_INFO "** ata_exit\n"); ++} ++ ++static int ata_get_clk_rate(void) ++{ ++ return MCF_BUSCLK; ++} ++ ++ ++static struct fsl_ata_platform_data ata_data = { ++ .init = ata_init, ++ .exit = ata_exit, ++ .get_clk_rate = ata_get_clk_rate, ++}; ++ ++static struct resource pata_fsl_resources[] = { ++ [0] = { /* I/O */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { /* IRQ */ ++ .start = IRQ_ATA, ++ .end = IRQ_ATA, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device pata_fsl_device = { ++ .name = "pata_fsl", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(pata_fsl_resources), ++ .resource = pata_fsl_resources, ++ .dev = { ++ .platform_data = &ata_data, ++ .coherent_dma_mask = ~0, /* $$$ REVISIT */ ++ }, ++}; ++ ++static inline void mcf5445x_init_pata(void) ++{ ++ io_ata_map = ioremap(BASE_IO_ATA_PHY, io_ata_mapsize); ++ if (!io_ata_map) { ++ printk(KERN_ERR "IO ATA map failed by ioremap!\n"); ++ return; ++ } ++ printk(KERN_INFO "BASE_IO_ATA value is 0x%x\n", BASE_IO_ATA); ++ ++ pata_fsl_resources[0].start = BASE_IO_ATA; ++ pata_fsl_resources[0].end = BASE_IO_ATA + 0x000000d8; ++ ++ (void)platform_device_register(&pata_fsl_device); ++} ++#endif ++ ++/* ++ * I2C ++ */ ++#if defined(CONFIG_I2C) ++static struct resource coldfire_i2c_resources[] = { ++ { /* I/O */ ++ .start = 0xFC058000, ++ .end = 0xFC058010, ++ .flags = IORESOURCE_MEM, ++ }, ++ { /* IRQ */ ++ .start = (64 + 30), ++ .end = (64 + 30), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_i2c_device = { ++ .name = "mcf-i2c", ++ .id = 0, /*bus number*/ ++ .num_resources = ARRAY_SIZE(coldfire_i2c_resources), ++ .resource = coldfire_i2c_resources, ++}; ++ ++static void mcf5445x_init_i2c(void) ++{ ++ platform_device_register(&coldfire_i2c_device); ++} ++#endif ++ ++static int __init mcf5445x_init_devices(void) ++{ ++ printk(KERN_INFO "mcf5445x_init_devices: %s.\n", __func__); ++#ifdef CONFIG_SPI ++ m5445x_spi_init(); ++#endif ++ ++#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) ++ mcf5445x_init_pata(); ++#endif ++ ++#if defined(CONFIG_I2C) ++ mcf5445x_init_i2c(); ++#endif ++ return 0; ++} ++arch_initcall(mcf5445x_init_devices); ++ ++/***************************************************************************/ ++static struct mcf_platform_uart m5445x_uart_platform[] = { ++ { ++ .mapbase = MCFUART_BASE1, ++ .irq = MCFINT_VECBASE + MCFINT_UART0, ++ }, ++#ifdef CONFIG_M54455 ++ { ++ .mapbase = MCFUART_BASE2, ++ .irq = MCFINT_VECBASE + MCFINT_UART1, ++ }, ++#endif ++ { }, ++}; ++ ++static struct platform_device m5445x_uart = { ++ .name = "mcfuart", ++ .id = 0, ++ .dev.platform_data = m5445x_uart_platform, ++}; ++ ++#if defined(CONFIG_RTC_MCF) || defined(CONFIG_RTC_MCF_MODULE) ++static struct platform_device rtc_device = { ++ .name = "mcf-rtc", ++ .id = -1, ++}; ++#endif ++ ++static struct platform_device *m5445x_devices[] __initdata = { ++ &m5445x_uart, ++#if defined(CONFIG_RTC_MCF) || defined(CONFIG_RTC_MCF_MODULE) ++ &rtc_device, ++#endif ++}; ++ ++ ++static void m5445x_uart_init_line(int line, int irq) ++{ ++ if (line == 0) ++ MCF_GPIO_PAR_UART = (0 | 0x000F); ++ else if (line == 1) ++ MCF_GPIO_PAR_UART |= (0 | 0x0FF0); ++} ++ ++void m5445x_uarts_init(void) ++{ ++ const int nrlines = ARRAY_SIZE(m5445x_uart_platform); ++ int line; ++ ++ for (line = 0; (line < nrlines); line++) ++ m5445x_uart_init_line(line, m5445x_uart_platform[line].irq); ++} ++/****************************************************************************/ ++/***************************************************************************/ ++ ++static int __init init_BSP(void) ++{ ++ m5445x_uarts_init(); ++ platform_add_devices(m5445x_devices, ARRAY_SIZE(m5445x_devices)); ++ return 0; ++} ++ ++arch_initcall(init_BSP); ++ ++ +--- /dev/null ++++ b/arch/m68k/configs/m54451evb_defconfig +@@ -0,0 +1,1412 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:14:20 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++CONFIG_M5445X=y ++CONFIG_M54451=y ++# CONFIG_M54455 is not set ++CONFIG_M54451EVB=y ++# CONFIG_M54455EVB is not set ++CONFIG_HAVE_FSL_USB_DR=y ++# CONFIG_M547X_8X is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=240000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x40000000 ++CONFIG_SDRAM_SIZE=0x08000000 ++CONFIG_NOR_FLASH_BASE=0x00000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x1000000 ++CONFIG_SRAM=y ++CONFIG_SRAM_BASE=0x8ff00000 ++CONFIG_SRAM_SIZE=0x8000 ++CONFIG_SRAM_ALLOC_GRANULARITY=0x200 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++CONFIG_MTD_CFI_ADV_OPTIONS=y ++CONFIG_MTD_CFI_NOSWAP=y ++# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set ++# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set ++CONFIG_MTD_CFI_GEOMETRY=y ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_OTP is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++CONFIG_MTD_CFI_STAA=y ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0x0 ++CONFIG_MTD_PHYSMAP_LEN=0x01000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_LIBFC is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++CONFIG_MicrelKSZ8041_PHY=y ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_ENC28J60 is not set ++# CONFIG_DNET is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_FEC=y ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++# CONFIG_USB_NET_GL620A is not set ++# CONFIG_USB_NET_NET1080 is not set ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++# CONFIG_USB_NET_RNDIS_HOST is not set ++# CONFIG_USB_NET_CDC_SUBSET is not set ++# CONFIG_USB_NET_ZAURUS is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_LIBPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++CONFIG_DEVSRAM=m ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_SPI_DSPI=y ++CONFIG_SPI_COLDFIRE_DSPI_EDMA=y ++# CONFIG_VOIP_FXS is not set ++# CONFIG_VOIP_FXO is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++# CONFIG_SND_MIXER_OSS is not set ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# ALSA for Coldfire ++# ++CONFIG_SND_COLDFIRE=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++CONFIG_USB_EHCI_FSL=y ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++CONFIG_USB_M5445X_ULPI=y ++# CONFIG_USB_M5445X_FSLS is not set ++# CONFIG_USB_M5441X_ULPI is not set ++# CONFIG_USB_M5441X_FSLS is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++CONFIG_USB_GADGET_FSL_USB2=y ++CONFIG_USB_FSL_USB2=m ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++ ++# ++# OTG and related infrastructure ++# ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_SPI=y ++CONFIG_M54451_SD_HW_DETECT=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_MCF=y ++# CONFIG_RTC_M5441X is not set ++CONFIG_DMADEVICES=y ++ ++# ++# DMA Devices ++# ++CONFIG_COLDFIRE_EDMA=y ++CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++CONFIG_CRYPTO_PCBC=m ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++ ++# ++# Talitos Driver ++# ++CONFIG_CRYPTO_HW=y ++CONFIG_CRYPTO_DEV_MCFCAU=y ++CONFIG_CRYPTO_DEV_MCFCAU_DES=y ++CONFIG_CRYPTO_DEV_MCFCAU_AES=y ++CONFIG_CRYPTO_DEV_MCFCAU_MD5=y ++CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++CONFIG_CRC7=y ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/configs/m54455evb_defconfig +@@ -0,0 +1,1597 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:16:14 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++CONFIG_M5445X=y ++# CONFIG_M54451 is not set ++CONFIG_M54455=y ++# CONFIG_M54451EVB is not set ++CONFIG_M54455EVB=y ++CONFIG_HAVE_FSL_USB_DR=y ++# CONFIG_M547X_8X is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=266666666 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x40000000 ++CONFIG_SDRAM_SIZE=0x10000000 ++CONFIG_NOR_FLASH_BASE=0x00000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x1000000 ++CONFIG_SRAM=y ++CONFIG_SRAM_BASE=0x8ff00000 ++CONFIG_SRAM_SIZE=0x8000 ++CONFIG_SRAM_ALLOC_GRANULARITY=0x200 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0x0 ++CONFIG_MTD_PHYSMAP_LEN=0x01000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=1 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC7XXX_OLD is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_DPT_I2O is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_LIBFC is not set ++# CONFIG_FCOE is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_FUTURE_DOMAIN is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_IPR is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_FC is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_LPFC is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_DC390T is not set ++# CONFIG_SCSI_NSP32 is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_SRP is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++# CONFIG_SATA_AHCI is not set ++# CONFIG_SATA_SIL24 is not set ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++# CONFIG_SATA_SIL is not set ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MARVELL is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NINJA32 is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_NS87415 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++# CONFIG_PATA_SIL680 is not set ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++# CONFIG_PATA_PLATFORM is not set ++# CONFIG_PATA_SCH is not set ++CONFIG_PATA_FSL=y ++CONFIG_FSL_PATA_USE_DMA=y ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++CONFIG_NATIONAL8384x_PHY=y ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_ENC28J60 is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++CONFIG_E100=y ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++# CONFIG_NE2K_PCI is not set ++# CONFIG_8139CP is not set ++CONFIG_8139TOO=y ++# CONFIG_8139TOO_PIO is not set ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++CONFIG_FEC=y ++# CONFIG_FEC2 is not set ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++CONFIG_E1000=y ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++# CONFIG_R8169 is not set ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++CONFIG_USB_RTL8150=y ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_LIBPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++CONFIG_DEVSRAM=m ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_GEN_RTC is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_SPI_DSPI=y ++CONFIG_SPI_COLDFIRE_DSPI_EDMA=y ++# CONFIG_VOIP_FXS is not set ++# CONFIG_VOIP_FXO is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++# CONFIG_SND_MIXER_OSS is not set ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ALS300 is not set ++# CONFIG_SND_ALI5451 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_AZT3328 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_EMU10K1 is not set ++# CONFIG_SND_EMU10K1X is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_ES1938 is not set ++# CONFIG_SND_ES1968 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDA_INTEL is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_HIFIER is not set ++# CONFIG_SND_ICE1712 is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_MAESTRO3 is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SONICVIBES is not set ++# CONFIG_SND_TRIDENT is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++ ++# ++# ALSA for Coldfire ++# ++CONFIG_SND_COLDFIRE=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++CONFIG_USB_EHCI_FSL=y ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++CONFIG_USB_M5445X_ULPI=y ++# CONFIG_USB_M5445X_FSLS is not set ++# CONFIG_USB_M5441X_ULPI is not set ++# CONFIG_USB_M5441X_FSLS is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++CONFIG_USB_GADGET_FSL_USB2=y ++CONFIG_USB_FSL_USB2=m ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++# CONFIG_RTC_CLASS is not set ++CONFIG_DMADEVICES=y ++ ++# ++# DMA Devices ++# ++CONFIG_COLDFIRE_EDMA=y ++CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++CONFIG_CRYPTO_PCBC=m ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++ ++# ++# Talitos Driver ++# ++CONFIG_CRYPTO_HW=y ++CONFIG_CRYPTO_DEV_MCFCAU=y ++CONFIG_CRYPTO_DEV_MCFCAU_DES=y ++CONFIG_CRYPTO_DEV_MCFCAU_AES=y ++CONFIG_CRYPTO_DEV_MCFCAU_MD5=y ++CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y ++# CONFIG_CRYPTO_DEV_HIFN_795X is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/include/asm/cf_5445x_cacheflush.h +@@ -0,0 +1,534 @@ ++/* ++ * include/asm-m68k/cf_5445x_cacheflush.h - Coldfire 5445x Cache ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * Based on include/asm-m68k/cacheflush.h ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef M68K_CF_5445x_CACHEFLUSH_H ++#define M68K_CF_5445x_CACHEFLUSH_H ++ ++#include <asm/cfcache.h> ++ ++/* ++ * Coldfire Cache Model ++ * ++ * The Coldfire processors use a Harvard architecture cache configured ++ * as four-way set associative. The cache does not implement bus snooping ++ * so cache coherency with other masters must be maintained in software. ++ * ++ * The cache is managed via the CPUSHL instruction in conjunction with ++ * bits set in the CACR (cache control register). Currently the code ++ * uses the CPUSHL enhancement which adds the ability to ++ * invalidate/clear/push a cacheline by physical address. This feature ++ * is designated in the Hardware Configuration Register [D1-CPES]. ++ * ++ * CACR Bits: ++ * DPI[28] cpushl invalidate disable for d-cache ++ * IDPI[12] cpushl invalidate disable for i-cache ++ * SPA[14] cpushl search by physical address ++ * IVO[20] cpushl invalidate only ++ * ++ * Random Terminology: ++ * * invalidate = reset the cache line's valid bit ++ * * push = generate a line-sized store of the data if its contents are ++ * marked as modifed (the modified flag is cleared after ++ * the store) ++ * * clear = push + invalidate ++ */ ++ ++/** ++ * flush_icache - Flush all of the instruction cache ++ */ ++static inline void flush_icache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%ic,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * flush_dcache - Flush all of the data cache ++ */ ++static inline void flush_dcache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * flush_bcache - Flush all of both caches ++ */ ++static inline void flush_bcache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * cf_cache_clear - invalidate cache ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Invalidate cache lines starting at paddr for len bytes. ++ * Those lines are not pushed. ++ */ ++static inline void cf_cache_clear(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne%.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA+CF_CACR_IVO) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_push - Push dirty cache out with no invalidate ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Push the any dirty lines starting at paddr for len bytes. ++ * Those lines are not invalidated. ++ */ ++static inline void cf_cache_push(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_flush - Push dirty cache out and invalidate ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Push the any dirty lines starting at paddr for len bytes and ++ * invalidate those lines. ++ */ ++static inline void cf_cache_flush(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the any dirty data/instr lines starting at paddr for len bytes and ++ * invalidate those lines. ++ */ ++static inline void cf_cache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ int len; ++ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0; ++ len = vend - vstart; ++ if (len == 0) ++ return; ++ vstart = __pa(vstart); ++ vend = vstart + len; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (vstart), "a" (vend), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_flush_range - Push dirty data cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push/Clear the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[IVO] is 0 ++ * CACR[DDPI] is 0 ++ * ++ * Sets CACR[SPA] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_inv_range - Invalidate data cache in range ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Invalidate the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[DDPI] is 0 ++ * ++ * Sets CACR[SPA] and CACR[IVO] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_inv_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA | CF_CACR_IVO) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_push_range - Push data cache in range ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[IVO] is 0 ++ * ++ * Sets CACR[SPA] and CACR[DDPI] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_push_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA | CF_CACR_DPI) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_icache_flush_range - Push dirty inst cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the any dirty instr lines starting at paddr for len bytes and ++ * invalidate those lines. This should just be an invalidate since you ++ * shouldn't be able to have dirty instruction cache. ++ */ ++static inline void cf_icache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%ic,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * flush_cache_mm - Flush an mm_struct ++ * @mm: mm_struct to flush ++ */ ++static inline void flush_cache_mm(struct mm_struct *mm) ++{ ++ if (mm == current->mm) ++ flush_bcache(); ++} ++ ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) ++ ++/** ++ * flush_cache_range - Flush a cache range ++ * @vma: vma struct ++ * @start: Starting address ++ * @end: Ending address ++ * ++ * flush_cache_range must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_range(struct vm_area_struct *vma, ++ unsigned long start, unsigned long end) ++{ ++ if (vma->vm_mm == current->mm) ++ cf_cache_flush_range(start, end); ++} ++ ++/** ++ * flush_cache_page - Flush a page of the cache ++ * @vma: vma struct ++ * @vmaddr: ++ * @pfn: page numer ++ * ++ * flush_cache_page must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_page(struct vm_area_struct *vma, ++ unsigned long vmaddr, unsigned long pfn) ++{ ++ if (vma->vm_mm == current->mm) ++ cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE); ++} ++ ++/** ++ * __flush_page_to_ram - Push a page out of the cache ++ * @vaddr: Virtual address at start of page ++ * ++ * Push the page at kernel virtual address *vaddr* and clear ++ * the icache. ++ */ ++static inline void __flush_page_to_ram(void *vaddr) ++{ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%d0\n" ++ "and%.l #0xfffffff0,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE), ++ "r" (shadow_cacr), "i" (CF_CACR_SPA) ++ : "a0", "d0"); ++} ++ ++/* ++ * Various defines for the kernel. ++ */ ++ ++extern void cache_clear(unsigned long paddr, int len); ++extern void cache_push(unsigned long paddr, int len); ++extern void flush_icache_range(unsigned long address, unsigned long endaddr); ++ ++#define flush_cache_all() flush_bcache() ++#define flush_cache_vmap(start, end) flush_bcache() ++#define flush_cache_vunmap(start, end) flush_bcache() ++ ++#define flush_dcache_range(vstart, vend) \ ++ cf_dcache_flush_range(vstart, vend) ++#define flush_dcache_page(page) \ ++ __flush_page_to_ram(page_address(page)) ++#define flush_dcache_mmap_lock(mapping) do { } while (0) ++#define flush_dcache_mmap_unlock(mapping) do { } while (0) ++ ++#define flush_icache_page(vma, page) \ ++ __flush_page_to_ram(page_address(page)) ++ ++/** ++ * copy_to_user_page - Copy memory to user page ++ */ ++static inline void copy_to_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++ cf_cache_flush(page_to_phys(page), PAGE_SIZE); ++} ++ ++/** ++ * copy_from_user_page - Copy memory from user page ++ */ ++static inline void copy_from_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ cf_cache_flush(page_to_phys(page), PAGE_SIZE); ++ memcpy(dst, src, len); ++} ++ ++#endif /* M68K_CF_5445x_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_ccm.h +@@ -0,0 +1,206 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_CCM_H__ ++#define __MCF5445X_CCM_H__ ++ ++/********************************************************************* ++* ++* Chip Configuration Module (CCM) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */ ++#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) ++/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */ ++#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) ++/* Chip Identification Register (Read-only) */ ++#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) ++/* Miscellaneous Control Register */ ++#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) ++#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */ ++/* USB On-the-Go Controller Status Register */ ++#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014) ++/* Serial Boot Facility Status Register (Read Only) */ ++#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018) ++/* Serial Boot Facility Control Register */ ++#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020) ++ ++/* Bit definitions and macros for CCR_360 */ ++/* 2-Bit PLL clock mode */ ++#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003)) ++/* PCI pad slew rate mode */ ++#define MCF_CCM_CCR_360_PCISLEW (0x0004) ++#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ ++#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5) ++/* 3-Bit PLL Clock Mode */ ++#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007)) ++#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ ++#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0) ++#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003) ++#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007) ++#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) ++#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) ++#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) ++#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) ++#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) ++#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) ++#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) ++#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) ++#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000) ++#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001) ++#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002) ++#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003) ++#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000) ++#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001) ++#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002) ++#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003) ++#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004) ++#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005) ++#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006) ++#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007) ++ ++/* Bit definitions and macros for CCR_256 */ ++/* 3-Bit PLL clock mode */ ++#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007)) ++/* Oscillator clock mode */ ++#define MCF_CCM_CCR_256_OSCMODE (0x0008) ++#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5) ++#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0) ++#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000) ++#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020) ++#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040) ++#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080) ++#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0) ++#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0) ++#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007) ++#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000) ++#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001) ++#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002) ++#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003) ++#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004) ++#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005) ++#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006) ++#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007) ++ ++/* Bit definitions and macros for RCON_360 */ ++#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ ++#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ ++#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ ++#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5) ++ ++/* Bit definitions and macros for RCON_256 */ ++#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */ ++#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ ++#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ ++/* Flexbus/PCI port size configuration */ ++#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5) ++ ++/* Bit definitions and macros for CIR */ ++/* Part revision number */ ++#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) ++/* Part identification number */ ++#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) ++#define MCF_CCM_CIR_PIN_MASK (0xFFC0) ++#define MCF_CCM_CIR_PRN_MASK (0x003F) ++#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6) ++#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6) ++#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6) ++#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6) ++#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6) ++#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6) ++ ++/* Bit definitions and macros for MISCCR */ ++/* USB clock source */ ++#define MCF_CCM_MISCCR_USBSRC (0x0001) ++/* USB VBUS over-current sense polarity */ ++#define MCF_CCM_MISCCR_USBOC (0x0002) ++/* USB transceiver pull-up enable */ ++#define MCF_CCM_MISCCR_USBPUE (0x0004) ++/* SSI clock source */ ++#define MCF_CCM_MISCCR_SSI_SRC (0x0010) ++/* Timer DMA mux selection */ ++#define MCF_CCM_MISCCR_TIM_DMA (0x0020) ++/* SSI RXD/TXD pull select */ ++#define MCF_CCM_MISCCR_SSI_PUS (0x0040) ++/* SSI RXD/TXD pull enable */ ++#define MCF_CCM_MISCCR_SSI_PUE (0x0080) ++/* Bus monitor timing field */ ++#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) ++/* Bus monitor external enable bit */ ++#define MCF_CCM_MISCCR_BME (0x0800) ++/* Limp mode enable */ ++#define MCF_CCM_MISCCR_LIMP (0x1000) ++#define MCF_CCM_MISCCR_BMT_65536 (0 << 8) ++#define MCF_CCM_MISCCR_BMT_32768 (1 << 8) ++#define MCF_CCM_MISCCR_BMT_16384 (2 << 8) ++#define MCF_CCM_MISCCR_BMT_8192 (3 << 8) ++#define MCF_CCM_MISCCR_BMT_4096 (4 << 8) ++#define MCF_CCM_MISCCR_BMT_2048 (5 << 8) ++#define MCF_CCM_MISCCR_BMT_1024 (6 << 8) ++#define MCF_CCM_MISCCR_BMT_512 (7 << 8) ++#define MCF_CCM_MISCCR_SSIPUE_UP (1 << 7) ++#define MCF_CCM_MISCCR_SSIPUE_DOWN (0 << 7) ++#define MCF_CCM_MISCCR_SSIPUS_UP (1 << 6) ++#define MCF_CCM_MISCCR_SSIPUS_DOWN (0 << 6) ++#define MCF_CCM_MISCCR_TIMDMA_TIM (1 << 5) ++#define MCF_CCM_MISCCR_TIMDMA_SSI (0 << 5) ++#define MCF_CCM_MISCCR_SSISRC_CLKIN (0 << 4) ++#define MCF_CCM_MISCCR_SSISRC_PLL (1 << 4) ++#define MCF_CCM_MISCCR_USBOC_ACTHI (0 << 1) ++#define MCF_CCM_MISCCR_USBOC_ACTLO (1 << 1) ++#define MCF_CCM_MISCCR_USBSRC_CLKIN (0) ++#define MCF_CCM_MISCCR_USBSRC_PLL (1) ++ ++/* Bit definitions and macros for CDR */ ++/* SSI oversampling clock divider */ ++#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF)) ++/* Low power clock divider */ ++#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8) ++ ++/* Bit definitions and macros for UOCSR */ ++/* On-chip transceiver pull-down enable */ ++#define MCF_CCM_UOCSR_XPDE (0x0001) ++/* USB OTG misc interrupt enable */ ++#define MCF_CCM_UOCSR_UOMIE (0x0002) ++/* USB OTG controller wake-up event */ ++#define MCF_CCM_UOCSR_WKUP (0x0004) ++/* VBUS power fault */ ++#define MCF_CCM_UOCSR_PWRFLT (0x0008) ++/* Session end */ ++#define MCF_CCM_UOCSR_SEND (0x0010) ++/* VBUS valid indicator */ ++#define MCF_CCM_UOCSR_VVLD (0x0020) ++/* B-peripheral valid indicator */ ++#define MCF_CCM_UOCSR_BVLD (0x0040) ++/* A-peripheral valid indicator */ ++#define MCF_CCM_UOCSR_AVLD (0x0080) ++/* D+ pull-up for FS enabled (read-only) */ ++#define MCF_CCM_UOCSR_DPPU (0x0100) ++/* VBUS discharge resistor enabled (read-only) */ ++#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) ++/* VBUS charge resistor enabled (read-only) */ ++#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) ++/* D- 15Kohm pull-down (read-only) */ ++#define MCF_CCM_UOCSR_DMPD (0x1000) ++/* D+ 15Kohm pull-down (read-only) */ ++#define MCF_CCM_UOCSR_DPPD (0x2000) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_CCM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_dspi.h +@@ -0,0 +1,665 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_DSPI_H__ ++#define __MCF5445X_DSPI_H__ ++ ++/********************************************************************* ++* ++* DMA Serial Peripheral Interface (DSPI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* DSPI Module Configuration Register */ ++#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) ++/* DSPI Transfer Count Register */ ++#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028 ++/* DSPI Status Register */ ++#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) ++/* DSPI DMA/Interrupt Request Select and Enable Register */ ++#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) ++/* DSPI Transmit FIFO Register */ ++#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) ++/* DSPI Receive FIFO Register */ ++#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) ++ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) ++ ++/* Bit definitions and macros for DMCR */ ++/* Halt -- stops and starts DSPI transfers */ ++#define MCF_DSPI_DMCR_HALT (0x00000001) ++/* Sample point selection */ ++#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) ++/* Clear receive FIFO */ ++#define MCF_DSPI_DMCR_CLRRXF (0x00000400) ++/* Clear transmit FIFO */ ++#define MCF_DSPI_DMCR_CLRTXF (0x00000800) ++/* Disable receive FIFO */ ++#define MCF_DSPI_DMCR_DISRXF (0x00001000) ++/* Disable transmit FIFO */ ++#define MCF_DSPI_DMCR_DISTXF (0x00002000) ++/* Module Disable */ ++#define MCF_DSPI_DMCR_MDIS (0x00004000) ++/* Peripheral chip-select 0 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) ++/* Peripheral chip-select 1 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) ++/* Peripheral chip-select 2 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) ++/* Peripheral chip-select 3 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) ++/* Peripheral chip-select 4 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) ++/* Peripheral chip-select 5 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) ++/* Peripheral chip-select 6 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) ++/* Peripheral chip-select 7 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) ++/* Receive FIFO overflow overwrite enable */ ++#define MCF_DSPI_DMCR_ROOE (0x01000000) ++/* Peripheral chip select strobe enable */ ++#define MCF_DSPI_DMCR_PCSSE (0x02000000) ++/* Modified timing format enable */ ++#define MCF_DSPI_DMCR_MTFE (0x04000000) ++/* Freeze */ ++#define MCF_DSPI_DMCR_FRZ (0x08000000) ++/* DSPI configuration */ ++#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) ++/* Continuous SCK enable */ ++#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) ++/* Master/Slave mode select */ ++#define MCF_DSPI_DMCR_MSTR (0x80000000) ++#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000) ++#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000) ++#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000) ++#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000) ++#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000) ++#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000) ++#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000) ++#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000) ++ ++/* Bit definitions and macros for DTCR */ ++/* SPI transfer count */ ++#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for DCTAR group */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR_DBR (0x80000000) ++#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000) ++#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000) ++#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000) ++#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000) ++#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000) ++#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000) ++#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for DCTAR0 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR0_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR0_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR0_DBR (0x80000000) ++#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000) ++#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000) ++#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000) ++#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000) ++#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000) ++#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000) ++#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for DCTAR1 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR1_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR1_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR1_DBR (0x80000000) ++ ++ ++/* Bit definitions and macros for DCTAR2 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR2_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR2_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR2_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR3 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR3_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR3_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR3_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR4 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR4_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR4_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR4_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR5 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR5_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR5_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR5_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR6 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR6_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR6_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR6_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR7 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR7_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR7_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR7_DBR (0x80000000) ++ ++/* Bit definitions and macros for DSR */ ++/* Receive next pointer */ ++#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) ++/* Receive FIFO counter */ ++#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) ++/* Transmit next pointer */ ++#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) ++/* Transmit FIFO counter */ ++#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) ++/* Receive FIFO drain flag */ ++#define MCF_DSPI_DSR_RFDF (0x00020000) ++/* Receive FIFO overflow flag */ ++#define MCF_DSPI_DSR_RFOF (0x00080000) ++/* Transmit FIFO fill flag */ ++#define MCF_DSPI_DSR_TFFF (0x02000000) ++/* Transmit FIFO underflow flag */ ++#define MCF_DSPI_DSR_TFUF (0x08000000) ++/* End of queue flag */ ++#define MCF_DSPI_DSR_EOQF (0x10000000) ++/* Tx and Rx status (enabled | disabled) */ ++#define MCF_DSPI_DSR_TXRXS (0x40000000) ++/* Transfer complete flag */ ++#define MCF_DSPI_DSR_TCF (0x80000000) ++ ++/* Bit definitions and macros for DRSER */ ++/* Receive FIFO drain DMA or interrupt select */ ++#define MCF_DSPI_DRSER_RFDFS (0x00010000) ++/* Receive FIFO drain request enable */ ++#define MCF_DSPI_DRSER_RFDFE (0x00020000) ++/* Receive FIFO overflow request enable */ ++#define MCF_DSPI_DRSER_RFOFE (0x00080000) ++/* Transmit FIFO fill DMA or interrupt select */ ++#define MCF_DSPI_DRSER_TFFFS (0x01000000) ++/* Transmit FIFO fill request enable */ ++#define MCF_DSPI_DRSER_TFFFE (0x02000000) ++/* Transmit FIFO underflow request enable */ ++#define MCF_DSPI_DRSER_TFUFE (0x08000000) ++/* DSPI finished request enable */ ++#define MCF_DSPI_DRSER_EOQFE (0x10000000) ++/* Transmission complete request enable */ ++#define MCF_DSPI_DRSER_TCFE (0x80000000) ++ ++/* Bit definitions and macros for DTFR */ ++/* Transmit data */ ++#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFR_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFR_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFR_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFR_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFR_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFR_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFR_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFR_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFR_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFR_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFR_CONT (0x80000000) ++ ++/* Bit definitions and macros for DRFR */ ++/* Receive data */ ++#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DTFDR group */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS0 (0x00010000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS1 (0x00020000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS2 (0x00040000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS3 (0x00080000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS4 (0x00100000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS5 (0x00200000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS6 (0x00400000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR0 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR0_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR0_CONT (0x80000000) ++/* Bit definitions and macros for DTFDR1 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR1_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR1_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR2 */ ++#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR2_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR2_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR3 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR3_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR3_CONT (0x80000000) ++ ++/* Bit definitions and macros for DRFDR group */ ++#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR0 */ ++#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR1 */ ++#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR2 */ ++#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR3 */ ++#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_DSPI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_dtim.h +@@ -0,0 +1,96 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_DTIM_H__ ++#define __MCF5445X_DTIM_H__ ++ ++/********************************************************************* ++* ++* DMA Timers (DTIM) ++* ++*********************************************************************/ ++/* Register read/write macros */ ++#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */ ++#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */ ++#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */ ++#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */ ++#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */ ++#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */ ++#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */ ++#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */ ++#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */ ++#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */ ++#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */ ++#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */ ++#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */ ++#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */ ++#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */ ++#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */ ++#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */ ++#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */ ++#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */ ++#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */ ++ ++/* Parameterized register read/write macros for multiple modules */ ++/* DMA Timer Mode Register */ ++#define MCF_DTIM_DTMR(x) (0xFC070000+((x)*0x4000)) ++/* DMA Timer Extended Mode Register */ ++#define MCF_DTIM_DTXMR(x) (0xFC070002+((x)*0x4000)) ++/* DMA Timer Event Register */ ++#define MCF_DTIM_DTER(x) (0xFC070003+((x)*0x4000)) ++/* DMA Timer Reference Register */ ++#define MCF_DTIM_DTRR(x) (0xFC070004+((x)*0x4000)) ++/* DMA Timer Capture Register */ ++#define MCF_DTIM_DTCR(x) (0xFC070008+((x)*0x4000)) ++/* DMA Timer Counter Register */ ++#define MCF_DTIM_DTCN(x) (0xFC07000C+((x)*0x4000)) ++ ++/* Bit definitions and macros for DTMR */ ++#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */ ++#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ ++#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */ ++/* Output reference request/interrupt enable */ ++#define MCF_DTIM_DTMR_ORRI (0x0010) ++#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */ ++#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ ++#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ ++#define MCF_DTIM_DTMR_RST_EN (0x0001) ++#define MCF_DTIM_DTMR_RST_RST (0x0000) ++#define MCF_DTIM_DTMR_CE_ANY (0x00C0) ++#define MCF_DTIM_DTMR_CE_FALL (0x0080) ++#define MCF_DTIM_DTMR_CE_RISE (0x0040) ++#define MCF_DTIM_DTMR_CE_NONE (0x0000) ++#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) ++#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) ++#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) ++#define MCF_DTIM_DTMR_CLK_STOP (0x0000) ++ ++/* Bit definitions and macros for DTXMR */ ++#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ ++#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */ ++ ++/* Bit definitions and macros for DTER */ ++#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */ ++#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */ ++ ++/* Interrupts used for system timers */ ++#define MCFSIM_ICR_TIMER0 (0xFC048040+32) ++#define MCFSIM_ICR_TIMER1 (0xFC048040+33) ++#define MCFSIM_ICR_TIMER2 (0xFC048040+34) ++#define MCFSIM_ICR_TIMER3 (0xFC048040+35) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_DTIM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_edma.h +@@ -0,0 +1,1472 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef __MCF5445X_EDMA_H__ ++#define __MCF5445X_EDMA_H__ ++ ++/* ++ * Enhanced DMA (EDMA) ++ */ ++ ++/* Channels */ ++#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */ ++#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */ ++#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */ ++#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */ ++#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */ ++#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */ ++#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */ ++#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */ ++#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */ ++#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */ ++#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */ ++#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */ ++#define MCF_EDMA_CHAN_DSPI_RX 12 /* DSPI Receive */ ++#define MCF_EDMA_CHAN_DSPI_TX 13 /* DSPI Transmit */ ++#define MCF_EDMA_CHAN_ATA_RX 14 /* ATA Receive */ ++#define MCF_EDMA_CHAN_ATA_TX 15 /* ATA Transmit */ ++ ++/* Register read/write macros */ ++#define MCF_EDMA_CR MCF_REG32(0xFC044000) ++#define MCF_EDMA_ES MCF_REG32(0xFC044004) ++#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E) ++#define MCF_EDMA_EEI MCF_REG16(0xFC044016) ++#define MCF_EDMA_SERQ MCF_REG08(0xFC044018) ++#define MCF_EDMA_CERQ MCF_REG08(0xFC044019) ++#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A) ++#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B) ++#define MCF_EDMA_CINT MCF_REG08(0xFC04401C) ++#define MCF_EDMA_CERR MCF_REG08(0xFC04401D) ++#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E) ++#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F) ++#define MCF_EDMA_INTR MCF_REG16(0xFC044026) ++#define MCF_EDMA_ERR MCF_REG16(0xFC04402E) ++#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100) ++#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101) ++#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102) ++#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103) ++#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104) ++#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105) ++#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106) ++#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107) ++#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108) ++#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109) ++#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A) ++#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B) ++#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C) ++#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D) ++#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E) ++#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F) ++#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000) ++#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004) ++#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006) ++#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008) ++#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C) ++#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010) ++#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014) ++#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014) ++#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016) ++#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018) ++#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C) ++#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C) ++#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E) ++#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020) ++#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024) ++#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026) ++#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028) ++#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C) ++#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030) ++#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034) ++#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034) ++#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036) ++#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038) ++#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C) ++#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C) ++#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E) ++#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040) ++#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044) ++#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046) ++#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048) ++#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C) ++#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050) ++#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054) ++#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054) ++#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056) ++#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058) ++#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C) ++#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C) ++#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E) ++#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060) ++#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064) ++#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066) ++#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068) ++#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C) ++#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070) ++#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074) ++#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074) ++#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076) ++#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078) ++#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C) ++#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C) ++#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E) ++#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080) ++#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084) ++#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086) ++#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088) ++#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C) ++#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090) ++#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094) ++#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094) ++#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096) ++#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098) ++#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C) ++#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C) ++#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E) ++#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0) ++#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4) ++#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6) ++#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8) ++#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC) ++#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0) ++#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4) ++#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4) ++#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6) ++#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8) ++#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC) ++#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC) ++#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE) ++#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0) ++#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4) ++#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6) ++#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8) ++#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC) ++#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0) ++#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4) ++#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4) ++#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6) ++#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8) ++#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC) ++#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC) ++#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE) ++#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0) ++#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4) ++#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6) ++#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8) ++#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC) ++#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0) ++#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4) ++#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4) ++#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6) ++#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8) ++#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC) ++#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC) ++#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE) ++#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100) ++#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104) ++#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106) ++#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108) ++#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C) ++#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110) ++#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114) ++#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114) ++#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116) ++#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118) ++#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C) ++#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C) ++#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E) ++#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120) ++#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124) ++#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126) ++#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128) ++#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C) ++#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130) ++#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134) ++#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134) ++#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136) ++#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138) ++#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C) ++#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C) ++#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E) ++#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140) ++#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144) ++#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146) ++#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148) ++#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C) ++#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150) ++#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154) ++#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154) ++#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156) ++#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158) ++#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C) ++#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C) ++#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E) ++#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160) ++#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164) ++#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166) ++#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168) ++#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C) ++#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170) ++#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174) ++#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174) ++#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176) ++#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178) ++#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C) ++#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C) ++#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E) ++#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180) ++#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184) ++#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186) ++#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188) ++#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C) ++#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190) ++#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194) ++#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194) ++#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196) ++#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198) ++#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C) ++#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C) ++#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E) ++#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0) ++#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4) ++#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6) ++#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8) ++#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC) ++#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0) ++#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4) ++#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4) ++#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6) ++#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8) ++#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC) ++#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC) ++#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE) ++#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0) ++#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4) ++#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6) ++#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8) ++#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC) ++#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0) ++#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4) ++#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4) ++#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6) ++#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8) ++#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC) ++#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC) ++#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE) ++#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0) ++#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4) ++#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6) ++#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8) ++#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC) ++#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0) ++#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4) ++#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4) ++#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6) ++#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8) ++#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC) ++#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC) ++#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001)) ++#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020)) ++#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020)) ++#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020)) ++#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020)) ++#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020)) ++#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020)) ++#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020)) ++#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020)) ++#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020)) ++#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020)) ++#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020)) ++#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020)) ++#define MCF_EDMA_TCD_CSR(x) MCF_REG16((0xFC04501e)+((x)*0x020)) ++ ++/* Bit definitions and macros for CR */ ++#define MCF_EDMA_CR_EDBG (0x00000002) ++#define MCF_EDMA_CR_ERCA (0x00000004) ++ ++/* Bit definitions and macros for ES */ ++#define MCF_EDMA_ES_DBE (0x00000001) ++#define MCF_EDMA_ES_SBE (0x00000002) ++#define MCF_EDMA_ES_SGE (0x00000004) ++#define MCF_EDMA_ES_NCE (0x00000008) ++#define MCF_EDMA_ES_DOE (0x00000010) ++#define MCF_EDMA_ES_DAE (0x00000020) ++#define MCF_EDMA_ES_SOE (0x00000040) ++#define MCF_EDMA_ES_SAE (0x00000080) ++#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8) ++#define MCF_EDMA_ES_CPE (0x00004000) ++#define MCF_EDMA_ES_VLD (0x80000000) ++ ++/* Bit definitions and macros for ERQ */ ++#define MCF_EDMA_ERQ_ERQ0 (0x0001) ++#define MCF_EDMA_ERQ_ERQ1 (0x0002) ++#define MCF_EDMA_ERQ_ERQ2 (0x0004) ++#define MCF_EDMA_ERQ_ERQ3 (0x0008) ++#define MCF_EDMA_ERQ_ERQ4 (0x0010) ++#define MCF_EDMA_ERQ_ERQ5 (0x0020) ++#define MCF_EDMA_ERQ_ERQ6 (0x0040) ++#define MCF_EDMA_ERQ_ERQ7 (0x0080) ++#define MCF_EDMA_ERQ_ERQ8 (0x0100) ++#define MCF_EDMA_ERQ_ERQ9 (0x0200) ++#define MCF_EDMA_ERQ_ERQ10 (0x0400) ++#define MCF_EDMA_ERQ_ERQ11 (0x0800) ++#define MCF_EDMA_ERQ_ERQ12 (0x1000) ++#define MCF_EDMA_ERQ_ERQ13 (0x2000) ++#define MCF_EDMA_ERQ_ERQ14 (0x4000) ++#define MCF_EDMA_ERQ_ERQ15 (0x8000) ++ ++/* Bit definitions and macros for EEI */ ++#define MCF_EDMA_EEI_EEI0 (0x0001) ++#define MCF_EDMA_EEI_EEI1 (0x0002) ++#define MCF_EDMA_EEI_EEI2 (0x0004) ++#define MCF_EDMA_EEI_EEI3 (0x0008) ++#define MCF_EDMA_EEI_EEI4 (0x0010) ++#define MCF_EDMA_EEI_EEI5 (0x0020) ++#define MCF_EDMA_EEI_EEI6 (0x0040) ++#define MCF_EDMA_EEI_EEI7 (0x0080) ++#define MCF_EDMA_EEI_EEI8 (0x0100) ++#define MCF_EDMA_EEI_EEI9 (0x0200) ++#define MCF_EDMA_EEI_EEI10 (0x0400) ++#define MCF_EDMA_EEI_EEI11 (0x0800) ++#define MCF_EDMA_EEI_EEI12 (0x1000) ++#define MCF_EDMA_EEI_EEI13 (0x2000) ++#define MCF_EDMA_EEI_EEI14 (0x4000) ++#define MCF_EDMA_EEI_EEI15 (0x8000) ++ ++/* Bit definitions and macros for SERQ */ ++#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)) ++#define MCF_EDMA_SERQ_SAER (0x40) ++ ++/* Bit definitions and macros for CERQ */ ++#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)) ++#define MCF_EDMA_CERQ_CAER (0x40) ++ ++/* Bit definitions and macros for SEEI */ ++#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)) ++#define MCF_EDMA_SEEI_SAEE (0x40) ++ ++/* Bit definitions and macros for CEEI */ ++#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)) ++#define MCF_EDMA_CEEI_CAEE (0x40) ++ ++/* Bit definitions and macros for CINT */ ++#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)) ++#define MCF_EDMA_CINT_CAIR (0x40) ++ ++/* Bit definitions and macros for CERR */ ++#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)) ++#define MCF_EDMA_CERR_CAER (0x40) ++ ++/* Bit definitions and macros for SSRT */ ++#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)) ++#define MCF_EDMA_SSRT_SAST (0x40) ++ ++/* Bit definitions and macros for CDNE */ ++#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)) ++#define MCF_EDMA_CDNE_CADN (0x40) ++ ++/* Bit definitions and macros for INTR */ ++#define MCF_EDMA_INTR_INT0 (0x0001) ++#define MCF_EDMA_INTR_INT1 (0x0002) ++#define MCF_EDMA_INTR_INT2 (0x0004) ++#define MCF_EDMA_INTR_INT3 (0x0008) ++#define MCF_EDMA_INTR_INT4 (0x0010) ++#define MCF_EDMA_INTR_INT5 (0x0020) ++#define MCF_EDMA_INTR_INT6 (0x0040) ++#define MCF_EDMA_INTR_INT7 (0x0080) ++#define MCF_EDMA_INTR_INT8 (0x0100) ++#define MCF_EDMA_INTR_INT9 (0x0200) ++#define MCF_EDMA_INTR_INT10 (0x0400) ++#define MCF_EDMA_INTR_INT11 (0x0800) ++#define MCF_EDMA_INTR_INT12 (0x1000) ++#define MCF_EDMA_INTR_INT13 (0x2000) ++#define MCF_EDMA_INTR_INT14 (0x4000) ++#define MCF_EDMA_INTR_INT15 (0x8000) ++ ++/* Bit definitions and macros for ERR */ ++#define MCF_EDMA_ERR_ERR0 (0x0001) ++#define MCF_EDMA_ERR_ERR1 (0x0002) ++#define MCF_EDMA_ERR_ERR2 (0x0004) ++#define MCF_EDMA_ERR_ERR3 (0x0008) ++#define MCF_EDMA_ERR_ERR4 (0x0010) ++#define MCF_EDMA_ERR_ERR5 (0x0020) ++#define MCF_EDMA_ERR_ERR6 (0x0040) ++#define MCF_EDMA_ERR_ERR7 (0x0080) ++#define MCF_EDMA_ERR_ERR8 (0x0100) ++#define MCF_EDMA_ERR_ERR9 (0x0200) ++#define MCF_EDMA_ERR_ERR10 (0x0400) ++#define MCF_EDMA_ERR_ERR11 (0x0800) ++#define MCF_EDMA_ERR_ERR12 (0x1000) ++#define MCF_EDMA_ERR_ERR13 (0x2000) ++#define MCF_EDMA_ERR_ERR14 (0x4000) ++#define MCF_EDMA_ERR_ERR15 (0x8000) ++ ++/* Bit definitions and macros for DCHPRI group */ ++#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI0 */ ++#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI0_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI1 */ ++#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI1_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI2 */ ++#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI2_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI3 */ ++#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI3_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI4 */ ++#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI4_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI5 */ ++#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI5_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI6 */ ++#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI6_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI7 */ ++#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI7_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI8 */ ++#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI8_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI9 */ ++#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI9_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI10 */ ++#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI10_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI11 */ ++#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI11_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI12 */ ++#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI12_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI13 */ ++#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI13_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI14 */ ++#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI14_ECP (0x80) ++ ++/* Bit definitions and macros for DCHPRI15 */ ++#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI15_ECP (0x80) ++ ++/* Bit definitions and macros for TCD_SADDR group */ ++#define MCF_EDMA_TCD_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD0_SADDR */ ++#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD_ATTR group */ ++#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11) ++#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) ++#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) ++#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) ++#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) ++#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) ++#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) ++ ++/* Bit definitions and macros for TCD0_ATTR */ ++#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200) ++#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002) ++#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004) ++ ++/* Bit definitions and macros for TCD_SOFF group */ ++#define MCF_EDMA_TCD_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD0_SOFF */ ++#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD_NBYTES group */ ++#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD0_NBYTES */ ++#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD_SLAST group */ ++#define MCF_EDMA_TCD_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD0_SLAST */ ++#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD_DADDR group */ ++#define MCF_EDMA_TCD_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD0_DADDR */ ++#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD_CITER_ELINK group */ ++#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_CITER_ELINK */ ++#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_CITER group */ ++#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_CITER */ ++#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_DOFF group */ ++#define MCF_EDMA_TCD_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD0_DOFF */ ++#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD_DLAST_SGA group */ ++#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD0_DLAST_SGA */ ++#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD_BITER_ELINK group */ ++#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_BITER_ELINK */ ++#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_BITER group */ ++#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD0_BITER */ ++#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_CSR group */ ++#define MCF_EDMA_TCD_CSR_START (0x0001) ++#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14) ++#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000) ++#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000) ++#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000) ++ ++/* Bit definitions and macros for TCD0_CSR */ ++#define MCF_EDMA_TCD0_CSR_START (0x0001) ++#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD0_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD0_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14) ++#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000) ++#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000) ++#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000) ++ ++/* Bit definitions and macros for TCD1_SADDR */ ++#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD1_ATTR */ ++#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD1_SOFF */ ++#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD1_NBYTES */ ++#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD1_SLAST */ ++#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD1_DADDR */ ++#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD1_CITER_ELINK */ ++#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_CITER */ ++#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_DOFF */ ++#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD1_DLAST_SGA */ ++#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD1_BITER */ ++#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_BITER_ELINK */ ++#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD1_CSR */ ++#define MCF_EDMA_TCD1_CSR_START (0x0001) ++#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD1_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD1_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD2_SADDR */ ++#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD2_ATTR */ ++#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD2_SOFF */ ++#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD2_NBYTES */ ++#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD2_SLAST */ ++#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD2_DADDR */ ++#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD2_CITER */ ++#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_CITER_ELINK */ ++#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_DOFF */ ++#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD2_DLAST_SGA */ ++#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD2_BITER_ELINK */ ++#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_BITER */ ++#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD2_CSR */ ++#define MCF_EDMA_TCD2_CSR_START (0x0001) ++#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD2_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD2_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD3_SADDR */ ++#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD3_ATTR */ ++#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD3_SOFF */ ++#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD3_NBYTES */ ++#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD3_SLAST */ ++#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD3_DADDR */ ++#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD3_CITER */ ++#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_CITER_ELINK */ ++#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_DOFF */ ++#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD3_DLAST_SGA */ ++#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD3_BITER_ELINK */ ++#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_BITER */ ++#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD3_CSR */ ++#define MCF_EDMA_TCD3_CSR_START (0x0001) ++#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD3_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD3_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD4_SADDR */ ++#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD4_ATTR */ ++#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD4_SOFF */ ++#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD4_NBYTES */ ++#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD4_SLAST */ ++#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD4_DADDR */ ++#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD4_CITER */ ++#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_CITER_ELINK */ ++#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_DOFF */ ++#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD4_DLAST_SGA */ ++#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD4_BITER */ ++#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_BITER_ELINK */ ++#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD4_CSR */ ++#define MCF_EDMA_TCD4_CSR_START (0x0001) ++#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD4_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD4_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD5_SADDR */ ++#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD5_ATTR */ ++#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD5_SOFF */ ++#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD5_NBYTES */ ++#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD5_SLAST */ ++#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD5_DADDR */ ++#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD5_CITER */ ++#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_CITER_ELINK */ ++#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_DOFF */ ++#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD5_DLAST_SGA */ ++#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD5_BITER_ELINK */ ++#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_BITER */ ++#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD5_CSR */ ++#define MCF_EDMA_TCD5_CSR_START (0x0001) ++#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD5_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD5_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD6_SADDR */ ++#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD6_ATTR */ ++#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD6_SOFF */ ++#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD6_NBYTES */ ++#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD6_SLAST */ ++#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD6_DADDR */ ++#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD6_CITER */ ++#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_CITER_ELINK */ ++#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_DOFF */ ++#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD6_DLAST_SGA */ ++#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD6_BITER_ELINK */ ++#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_BITER */ ++#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD6_CSR */ ++#define MCF_EDMA_TCD6_CSR_START (0x0001) ++#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD6_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD6_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD7_SADDR */ ++#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD7_ATTR */ ++#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD7_SOFF */ ++#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD7_NBYTES */ ++#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD7_SLAST */ ++#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD7_DADDR */ ++#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD7_CITER */ ++#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_CITER_ELINK */ ++#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_DOFF */ ++#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD7_DLAST_SGA */ ++#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD7_BITER_ELINK */ ++#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_BITER */ ++#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD7_CSR */ ++#define MCF_EDMA_TCD7_CSR_START (0x0001) ++#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD7_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD7_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD8_SADDR */ ++#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD8_ATTR */ ++#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD8_SOFF */ ++#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD8_NBYTES */ ++#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD8_SLAST */ ++#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD8_DADDR */ ++#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD8_CITER */ ++#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_CITER_ELINK */ ++#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_DOFF */ ++#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD8_DLAST_SGA */ ++#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD8_BITER_ELINK */ ++#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_BITER */ ++#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD8_CSR */ ++#define MCF_EDMA_TCD8_CSR_START (0x0001) ++#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD8_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD8_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD9_SADDR */ ++#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD9_ATTR */ ++#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD9_SOFF */ ++#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD9_NBYTES */ ++#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD9_SLAST */ ++#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD9_DADDR */ ++#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD9_CITER_ELINK */ ++#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_CITER */ ++#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_DOFF */ ++#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD9_DLAST_SGA */ ++#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD9_BITER_ELINK */ ++#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_BITER */ ++#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD9_CSR */ ++#define MCF_EDMA_TCD9_CSR_START (0x0001) ++#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD9_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD9_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD10_SADDR */ ++#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD10_ATTR */ ++#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD10_SOFF */ ++#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD10_NBYTES */ ++#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD10_SLAST */ ++#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD10_DADDR */ ++#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD10_CITER_ELINK */ ++#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_CITER */ ++#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_DOFF */ ++#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD10_DLAST_SGA */ ++#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD10_BITER */ ++#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_BITER_ELINK */ ++#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD10_CSR */ ++#define MCF_EDMA_TCD10_CSR_START (0x0001) ++#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD10_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD10_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD11_SADDR */ ++#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD11_ATTR */ ++#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD11_SOFF */ ++#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD11_NBYTES */ ++#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD11_SLAST */ ++#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD11_DADDR */ ++#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD11_CITER */ ++#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_CITER_ELINK */ ++#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_DOFF */ ++#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD11_DLAST_SGA */ ++#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD11_BITER */ ++#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_BITER_ELINK */ ++#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD11_CSR */ ++#define MCF_EDMA_TCD11_CSR_START (0x0001) ++#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD11_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD11_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD12_SADDR */ ++#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD12_ATTR */ ++#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD12_SOFF */ ++#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD12_NBYTES */ ++#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD12_SLAST */ ++#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD12_DADDR */ ++#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD12_CITER */ ++#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_CITER_ELINK */ ++#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_DOFF */ ++#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD12_DLAST_SGA */ ++#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD12_BITER */ ++#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_BITER_ELINK */ ++#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD12_CSR */ ++#define MCF_EDMA_TCD12_CSR_START (0x0001) ++#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD12_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD12_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD13_SADDR */ ++#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD13_ATTR */ ++#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD13_SOFF */ ++#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD13_NBYTES */ ++#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD13_SLAST */ ++#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD13_DADDR */ ++#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD13_CITER_ELINK */ ++#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_CITER */ ++#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_DOFF */ ++#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD13_DLAST_SGA */ ++#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD13_BITER_ELINK */ ++#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_BITER */ ++#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD13_CSR */ ++#define MCF_EDMA_TCD13_CSR_START (0x0001) ++#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD13_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD13_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD14_SADDR */ ++#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD14_ATTR */ ++#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD14_SOFF */ ++#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD14_NBYTES */ ++#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD14_SLAST */ ++#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD14_DADDR */ ++#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD14_CITER */ ++#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_CITER_ELINK */ ++#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_DOFF */ ++#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD14_DLAST_SGA */ ++#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD14_BITER_ELINK */ ++#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_BITER */ ++#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD14_CSR */ ++#define MCF_EDMA_TCD14_CSR_START (0x0001) ++#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD14_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD14_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++/* Bit definitions and macros for TCD15_SADDR */ ++#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD15_ATTR */ ++#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11) ++ ++/* Bit definitions and macros for TCD15_SOFF */ ++#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD15_NBYTES */ ++#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x) ++ ++/* Bit definitions and macros for TCD15_SLAST */ ++#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD15_DADDR */ ++#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD15_CITER_ELINK */ ++#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_CITER */ ++#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_DOFF */ ++#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD15_DLAST_SGA */ ++#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD15_BITER */ ++#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_BITER_ELINK */ ++#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD15_CSR */ ++#define MCF_EDMA_TCD15_CSR_START (0x0001) ++#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD15_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD15_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14) ++ ++#endif /* __MCF5445X_EDMA_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_eport.h +@@ -0,0 +1,117 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_EPORT_H__ ++#define __MCF5445X_EPORT_H__ ++ ++/********************************************************************* ++* ++* Edge Port Module (EPORT) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) ++#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) ++#define MCF_EPORT_EPIER MCF_REG08(0xFC094003) ++#define MCF_EPORT_EPDR MCF_REG08(0xFC094004) ++#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) ++#define MCF_EPORT_EPFR MCF_REG08(0xFC094006) ++ ++/* Bit definitions and macros for EPPAR */ ++#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) ++#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) ++#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) ++#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) ++#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) ++#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) ++#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) ++#define MCF_EPORT_EPPAR_LEVEL (0) ++#define MCF_EPORT_EPPAR_RISING (1) ++#define MCF_EPORT_EPPAR_FALLING (2) ++#define MCF_EPORT_EPPAR_BOTH (3) ++#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) ++#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) ++#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) ++#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) ++#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) ++#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) ++#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) ++#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) ++#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) ++#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) ++#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) ++#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) ++#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) ++#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) ++#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) ++#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) ++#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) ++#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) ++#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) ++#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) ++#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) ++ ++/* Bit definitions and macros for EPDDR */ ++#define MCF_EPORT_EPDDR_EPDD1 (0x02) ++#define MCF_EPORT_EPDDR_EPDD2 (0x04) ++#define MCF_EPORT_EPDDR_EPDD3 (0x08) ++#define MCF_EPORT_EPDDR_EPDD4 (0x10) ++#define MCF_EPORT_EPDDR_EPDD5 (0x20) ++#define MCF_EPORT_EPDDR_EPDD6 (0x40) ++#define MCF_EPORT_EPDDR_EPDD7 (0x80) ++ ++/* Bit definitions and macros for EPIER */ ++#define MCF_EPORT_EPIER_EPIE1 (0x02) ++#define MCF_EPORT_EPIER_EPIE2 (0x04) ++#define MCF_EPORT_EPIER_EPIE3 (0x08) ++#define MCF_EPORT_EPIER_EPIE4 (0x10) ++#define MCF_EPORT_EPIER_EPIE5 (0x20) ++#define MCF_EPORT_EPIER_EPIE6 (0x40) ++#define MCF_EPORT_EPIER_EPIE7 (0x80) ++ ++/* Bit definitions and macros for EPDR */ ++#define MCF_EPORT_EPDR_EPD1 (0x02) ++#define MCF_EPORT_EPDR_EPD2 (0x04) ++#define MCF_EPORT_EPDR_EPD3 (0x08) ++#define MCF_EPORT_EPDR_EPD4 (0x10) ++#define MCF_EPORT_EPDR_EPD5 (0x20) ++#define MCF_EPORT_EPDR_EPD6 (0x40) ++#define MCF_EPORT_EPDR_EPD7 (0x80) ++ ++/* Bit definitions and macros for EPPDR */ ++#define MCF_EPORT_EPPDR_EPPD1 (0x02) ++#define MCF_EPORT_EPPDR_EPPD2 (0x04) ++#define MCF_EPORT_EPPDR_EPPD3 (0x08) ++#define MCF_EPORT_EPPDR_EPPD4 (0x10) ++#define MCF_EPORT_EPPDR_EPPD5 (0x20) ++#define MCF_EPORT_EPPDR_EPPD6 (0x40) ++#define MCF_EPORT_EPPDR_EPPD7 (0x80) ++ ++/* Bit definitions and macros for EPFR */ ++#define MCF_EPORT_EPFR_EPF1 (0x02) ++#define MCF_EPORT_EPFR_EPF2 (0x04) ++#define MCF_EPORT_EPFR_EPF3 (0x08) ++#define MCF_EPORT_EPFR_EPF4 (0x10) ++#define MCF_EPORT_EPFR_EPF5 (0x20) ++#define MCF_EPORT_EPFR_EPF6 (0x40) ++#define MCF_EPORT_EPFR_EPF7 (0x80) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_EPORT_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_fbcs.h +@@ -0,0 +1,200 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_FBCS_H__ ++#define __MCF5445X_FBCS_H__ ++ ++/********************************************************************* ++* ++* FlexBus Chip Selects (FBCS) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* Chip-select Addr Register */ ++#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) ++/* Chip-select Mask Register */ ++#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) ++/* Chip-select Cntl Register */ ++#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) ++ ++/* Bit definitions and macros for CSAR group */ ++#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) ++ ++/* Bit definitions and macros for CSAR0 */ ++#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000) ++ ++/* Bit definitions and macros for CSMR group */ ++#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ ++#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) ++#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) ++#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) ++#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) ++#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) ++#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) ++#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) ++#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) ++#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) ++#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) ++#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) ++#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) ++#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) ++#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) ++#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) ++#define MCF_FBCS_CSMR_BAM_512K (0x00070000) ++#define MCF_FBCS_CSMR_BAM_256K (0x00030000) ++#define MCF_FBCS_CSMR_BAM_128K (0x00010000) ++#define MCF_FBCS_CSMR_BAM_64K (0x00000000) ++ ++/* Bit definitions and macros for CSMR0 */ ++#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ ++#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000) ++#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000) ++#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000) ++#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000) ++#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000) ++#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000) ++#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000) ++#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000) ++#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000) ++#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000) ++#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000) ++#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000) ++#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000) ++#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000) ++#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000) ++#define MCF_FBCS_CSMR0_BAM_512K (0x00070000) ++#define MCF_FBCS_CSMR0_BAM_256K (0x00030000) ++#define MCF_FBCS_CSMR0_BAM_128K (0x00010000) ++#define MCF_FBCS_CSMR0_BAM_64K (0x00000000) ++ ++/* Bit definitions and macros for CSCR group */ ++#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) ++#define MCF_FBCS_CSCR_PS_8 (0x00000040) ++#define MCF_FBCS_CSCR_PS_16 (0x00000080) ++#define MCF_FBCS_CSCR_PS_32 (0x00000000) ++ ++/* Bit definitions and macros for CSCR0 */ ++#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) ++#define MCF_FBCS_CSCR0_PS_8 (0x00000040) ++#define MCF_FBCS_CSCR0_PS_16 (0x00000080) ++#define MCF_FBCS_CSCR0_PS_32 (0x00000000) ++ ++/* Bit definitions and macros for CSMR1 */ ++#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR1 */ ++#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) ++ ++/* Bit definitions and macros for CSMR2 */ ++#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR2 */ ++#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) ++ ++/* Bit definitions and macros for CSMR3 */ ++#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR3 */ ++#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */ ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_FBCS_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_gpio.h +@@ -0,0 +1,1411 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_GPIO_H__ ++#define __MCF5445X_GPIO_H__ ++ ++/********************************************************************* ++* ++* General Purpose I/O Module (GPIO) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_GPIO_PODR_FEC0H \ ++ MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */ ++#define MCF_GPIO_PODR_FEC0L \ ++ MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */ ++#define MCF_GPIO_PODR_SSI \ ++ MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */ ++#define MCF_GPIO_PODR_FBCTL \ ++ MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */ ++/* Flexbus Byte Enable Port Output Data Register */ ++#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) ++/* Flexbus Chip-Select Port Output Data Register */ ++#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) ++#define MCF_GPIO_PODR_DMA \ ++ MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */ ++#define MCF_GPIO_PODR_FECI2C \ ++ MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */ ++#define MCF_GPIO_PODR_UART \ ++ MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */ ++#define MCF_GPIO_PODR_DSPI \ ++ MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */ ++#define MCF_GPIO_PODR_TIMER \ ++ MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */ ++#define MCF_GPIO_PODR_PCI \ ++ MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */ ++#define MCF_GPIO_PODR_USB \ ++ MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */ ++#define MCF_GPIO_PODR_ATAH \ ++ MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */ ++#define MCF_GPIO_PODR_ATAL \ ++ MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */ ++#define MCF_GPIO_PODR_FEC1H \ ++ MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */ ++#define MCF_GPIO_PODR_FEC1L \ ++ MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */ ++#define MCF_GPIO_PODR_FBADH \ ++ MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */ ++/* Flexbus AD Med-High Port Output Data Register */ ++#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015) ++/* Flexbus AD Med-Low Port Output Data Register */ ++#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016) ++#define MCF_GPIO_PODR_FBADL \ ++ MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */ ++#define MCF_GPIO_PDDR_FEC0H \ ++ MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FEC0L \ ++ MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_SSI \ ++ MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */ ++/* Flexbus Control Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B) ++/* Flexbus Byte Enable Port Data Direction Register */ ++#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C) ++/* Flexbus Chip-Select Port Data Direction Register */ ++#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D) ++#define MCF_GPIO_PDDR_DMA \ ++ MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FECI2C \ ++ MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */ ++#define MCF_GPIO_PDDR_UART \ ++ MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */ ++#define MCF_GPIO_PDDR_DSPI \ ++ MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */ ++#define MCF_GPIO_PDDR_TIMER \ ++ MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */ ++#define MCF_GPIO_PDDR_PCI \ ++ MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */ ++#define MCF_GPIO_PDDR_USB \ ++ MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */ ++#define MCF_GPIO_PDDR_ATAH \ ++ MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_ATAL \ ++ MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FEC1H \ ++ MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FEC1L \ ++ MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */ ++/* Flexbus AD High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C) ++/* Flexbus AD Med-High Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D) ++/* Flexbus AD Med-Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E) ++/* Flexbus AD Low Port Data Direction Register */ ++#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F) ++#define MCF_GPIO_PPDSDR_FEC0H \ ++ MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FEC0L \ ++ MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */ ++#define MCF_GPIO_PPDSDR_SSI \ ++ MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */ ++/* Flexbus Control Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033) ++/* Flexbus Byte Enable Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034) ++/* Flexbus Chip-Select Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035) ++#define MCF_GPIO_PPDSDR_DMA \ ++ MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FECI2C \ ++ MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_UART \ ++ MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_DSPI \ ++ MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_TIMER \ ++ MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_PCI \ ++ MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_USB \ ++ MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_ATAH \ ++ MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_ATAL \ ++ MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FEC1H \ ++ MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FEC1L \ ++ MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */ ++/* Flexbus AD High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044) ++/* Flexbus AD Med-High Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045) ++/* Flexbus AD Med-Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046) ++/* Flexbus AD Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047) ++#define MCF_GPIO_PCLRR_FEC0H \ ++ MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FEC0L \ ++ MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */ ++#define MCF_GPIO_PCLRR_SSI \ ++ MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */ ++/* Flexbus Control Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B) ++/* Flexbus Byte Enable Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C) ++/* Flexbus Chip-Select Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D) ++#define MCF_GPIO_PCLRR_DMA \ ++ MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FECI2C \ ++ MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_UART \ ++ MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_DSPI \ ++ MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_TIMER \ ++ MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_PCI \ ++ MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_USB \ ++ MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_ATAH \ ++ MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_ATAL \ ++ MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FEC1H \ ++ MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FEC1L \ ++ MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */ ++/* Flexbus AD High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C) ++/* Flexbus AD Med-High Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D) ++/* Flexbus AD Med-Low Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E) ++/* Flexbus AD Low Port Clear Output Data Register */ ++#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F) ++#define MCF_GPIO_PAR_FEC \ ++ MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */ ++#define MCF_GPIO_PAR_DMA \ ++ MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */ ++#define MCF_GPIO_PAR_FBCTL \ ++ MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */ ++#define MCF_GPIO_PAR_DSPI \ ++ MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */ ++/* Flexbus Byte-Enable Pin Assignment Register */ ++#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064) ++/* Flexbus Chip-Select Pin Assignment Register */ ++#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065) ++#define MCF_GPIO_PAR_TIMER \ ++ MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */ ++#define MCF_GPIO_PAR_USB \ ++ MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */ ++#define MCF_GPIO_PAR_UART \ ++ MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */ ++#define MCF_GPIO_PAR_FECI2C \ ++ MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */ ++#define MCF_GPIO_PAR_SSI \ ++ MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */ ++#define MCF_GPIO_PAR_ATA \ ++ MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */ ++#define MCF_GPIO_PAR_IRQ \ ++ MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */ ++#define MCF_GPIO_PAR_PCI \ ++ MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */ ++#define MCF_GPIO_MSCR_SDRAM \ ++ MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */ ++#define MCF_GPIO_MSCR_PCI \ ++ MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */ ++#define MCF_GPIO_DSCR_I2C \ ++ MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_FLEXBUS \ ++ MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_FEC \ ++ MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_UART \ ++ MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_DSPI \ ++ MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_TIMER \ ++ MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_SSI \ ++ MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_DMA \ ++ MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_DEBUG \ ++ MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_RESET \ ++ MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_IRQ \ ++ MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_USB \ ++ MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */ ++#define MCF_GPIO_DSCR_ATA \ ++ MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */ ++ ++/* Bit definitions and macros for PODR_FEC0H */ ++#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PODR_FEC0L */ ++#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PODR_SSI */ ++#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PODR_FBCTL */ ++#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PODR_BE */ ++#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PODR_CS */ ++#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PODR_DMA */ ++#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PODR_FECI2C */ ++#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PODR_UART */ ++#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PODR_DSPI */ ++#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PODR_TIMER */ ++#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PODR_PCI */ ++#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PODR_USB */ ++#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PODR_ATAH */ ++#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PODR_ATAL */ ++#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PODR_FEC1H */ ++#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */ ++#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02) ++/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */ ++#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04) ++#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ ++#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20) ++/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ ++#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40) ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80) ++ ++/* Bit definitions and macros for PODR_FEC1L */ ++#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PODR_FBADH */ ++#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PODR_FBADMH */ ++#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PODR_FBADML */ ++#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PODR_FBADL */ ++#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PDDR_FEC0H */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PDDR_FEC0L */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PDDR_SSI */ ++#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PDDR_FBCTL */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PDDR_BE */ ++#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PDDR_CS */ ++#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PDDR_DMA */ ++#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PDDR_FECI2C */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PDDR_UART */ ++#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PDDR_DSPI */ ++#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PDDR_TIMER */ ++#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PDDR_PCI */ ++#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PDDR_USB */ ++#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PDDR_ATAH */ ++#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PDDR_ATAL */ ++#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PDDR_FEC1H */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 ++ / ATA_DATA13 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV ++ / ATA_DATA15 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20) ++/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40) ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80) ++ ++/* Bit definitions and macros for PDDR_FEC1L */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PDDR_FBADH */ ++#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PDDR_FBADMH */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PDDR_FBADML */ ++#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PDDR_FBADL */ ++#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PPDSDR_FEC0H */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV ++ / FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PPDSDR_FEC0L */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PPDSDR_SSI */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PPDSDR_FBCTL */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PPDSDR_BE */ ++#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PPDSDR_CS */ ++#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PPDSDR_DMA */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PPDSDR_FECI2C */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PPDSDR_UART */ ++#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PPDSDR_DSPI */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PPDSDR_TIMER */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PPDSDR_PCI */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PPDSDR_USB */ ++#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PPDSDR_ATAH */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PPDSDR_ATAL */ ++#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PPDSDR_FEC1H */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 ++ / ATA_DATA13 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV ++ / ATA_DATA15 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 ++ / ATA_DATA9 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN ++ / ATA_DATA8 */ ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80) ++ ++/* Bit definitions and macros for PPDSDR_FEC1L */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADH */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADMH */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADML */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PPDSDR_FBADL */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PCLRR_FEC0H */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK ++ / FEC0_RMII_REF_CLK */ ++ ++/* Bit definitions and macros for PCLRR_FEC0L */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ ++#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ ++ ++/* Bit definitions and macros for PCLRR_SSI */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */ ++#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */ ++ ++/* Bit definitions and macros for PCLRR_FBCTL */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */ ++ ++/* Bit definitions and macros for PCLRR_BE */ ++#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ ++#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ ++#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ ++#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ ++ ++/* Bit definitions and macros for PCLRR_CS */ ++#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */ ++#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */ ++#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */ ++ ++/* Bit definitions and macros for PCLRR_DMA */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */ ++#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */ ++ ++/* Bit definitions and macros for PCLRR_FECI2C */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */ ++ ++/* Bit definitions and macros for PCLRR_UART */ ++#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */ ++#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */ ++#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */ ++#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */ ++#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */ ++ ++/* Bit definitions and macros for PCLRR_DSPI */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */ ++ ++/* Bit definitions and macros for PCLRR_TIMER */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */ ++#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */ ++ ++/* Bit definitions and macros for PCLRR_PCI */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */ ++#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ ++ ++/* Bit definitions and macros for PCLRR_USB */ ++#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ ++#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP ++ / ULPI_NXT */ ++ ++/* Bit definitions and macros for PCLRR_ATAH */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */ ++#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */ ++ ++/* Bit definitions and macros for PCLRR_ATAL */ ++#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */ ++#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */ ++#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */ ++ ++/* Bit definitions and macros for PCLRR_FEC1H */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 ++ /ATA_DATA13 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV ++ / ATA_DATA15 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 ++ / ATA_DATA9 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN ++ / ATA_DATA8 */ ++/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80) ++ ++/* Bit definitions and macros for PCLRR_FEC1L */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER ++ / ATA_DATA12 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 ++ / ATA_DATA14 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 ++ / ATA_DATA10 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ ++ ++/* Bit definitions and macros for PCLRR_FBADH */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */ ++#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */ ++ ++/* Bit definitions and macros for PCLRR_FBADMH */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */ ++#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */ ++ ++/* Bit definitions and macros for PCLRR_FBADML */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */ ++#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */ ++ ++/* Bit definitions and macros for PCLRR_FBADL */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */ ++#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */ ++ ++/* Bit definitions and macros for PAR_FEC */ ++#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) ++#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) ++#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F) ++#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70) ++#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) ++#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) ++#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10) ++#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00) ++#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8) ++#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07) ++#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) ++#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) ++#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01) ++#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_DMA */ ++#define MCF_GPIO_PAR_DMA_DREQ0 (0x01) ++#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F) ++#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0) ++#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) ++#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00) ++#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF) ++#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) ++#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) ++#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00) ++#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3) ++#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C) ++#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) ++#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00) ++#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) ++#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_FBCTL */ ++#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) ++#define MCF_GPIO_PAR_FBCTL_RW (0x20) ++#define MCF_GPIO_PAR_FBCTL_TA (0x40) ++#define MCF_GPIO_PAR_FBCTL_OE (0x80) ++#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80) ++#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40) ++#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20) ++#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7) ++#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18) ++#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10) ++#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08) ++#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80) ++ ++/* Bit definitions and macros for PAR_DSPI */ ++#define MCF_GPIO_PAR_DSPI_SCK (0x01) ++#define MCF_GPIO_PAR_DSPI_SOUT (0x02) ++#define MCF_GPIO_PAR_DSPI_SIN (0x04) ++#define MCF_GPIO_PAR_DSPI_PCS0 (0x08) ++#define MCF_GPIO_PAR_DSPI_PCS1 (0x10) ++#define MCF_GPIO_PAR_DSPI_PCS2 (0x20) ++#define MCF_GPIO_PAR_DSPI_PCS5 (0x40) ++#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40) ++#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20) ++#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10) ++#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08) ++#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04) ++#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02) ++#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01) ++#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_BE */ ++#define MCF_GPIO_PAR_BE_BE0 (0x01) ++#define MCF_GPIO_PAR_BE_BE1 (0x04) ++#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F) ++#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0) ++#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80) ++#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF) ++#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30) ++#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20) ++#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04) ++#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01) ++#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_CS */ ++#define MCF_GPIO_PAR_CS_CS1 (0x02) ++#define MCF_GPIO_PAR_CS_CS2 (0x04) ++#define MCF_GPIO_PAR_CS_CS3 (0x08) ++#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08) ++#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04) ++#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02) ++#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_TIMER */ ++#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) ++#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F) ++#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0) ++#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80) ++#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40) ++#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF) ++#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30) ++#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20) ++#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10) ++#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3) ++#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C) ++#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08) ++#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04) ++#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC) ++#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03) ++#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02) ++#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01) ++#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_USB */ ++#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) ++#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3) ++#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) ++#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) ++#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) ++#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00) ++#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC) ++#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) ++#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) ++#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_UART */ ++#define MCF_GPIO_PAR_UART_U0TXD (0x01) ++#define MCF_GPIO_PAR_UART_U0RXD (0x02) ++#define MCF_GPIO_PAR_UART_U0RTS (0x04) ++#define MCF_GPIO_PAR_UART_U0CTS (0x08) ++#define MCF_GPIO_PAR_UART_U1TXD (0x10) ++#define MCF_GPIO_PAR_UART_U1RXD (0x20) ++#define MCF_GPIO_PAR_UART_U1RTS (0x40) ++#define MCF_GPIO_PAR_UART_U1CTS (0x80) ++#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80) ++#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40) ++#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20) ++#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10) ++#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08) ++#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04) ++#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02) ++#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01) ++#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_FECI2C */ ++#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) ++#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003)) ++#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010) ++#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040) ++#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) ++#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) ++#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) ++#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) ++#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) ++#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) ++#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) ++#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) ++#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C) ++#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) ++#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000) ++#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) ++#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003) ++#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) ++#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000) ++ ++/* Bit definitions and macros for PAR_SSI */ ++#define MCF_GPIO_PAR_SSI_MCLK (0x0001) ++#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF) ++#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300) ++#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200) ++#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F) ++#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0) ++#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080) ++#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF) ++#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030) ++#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020) ++#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3) ++#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C) ++#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008) ++#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000) ++#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001) ++#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000) ++ ++/* Bit definitions and macros for PAR_ATA */ ++#define MCF_GPIO_PAR_ATA_IORDY (0x0001) ++#define MCF_GPIO_PAR_ATA_DMARQ (0x0002) ++#define MCF_GPIO_PAR_ATA_RESET (0x0004) ++#define MCF_GPIO_PAR_ATA_DA0 (0x0020) ++#define MCF_GPIO_PAR_ATA_DA1 (0x0040) ++#define MCF_GPIO_PAR_ATA_DA2 (0x0080) ++#define MCF_GPIO_PAR_ATA_CS0 (0x0100) ++#define MCF_GPIO_PAR_ATA_CS1 (0x0200) ++#define MCF_GPIO_PAR_ATA_BUFEN (0x0400) ++#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) ++#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200) ++#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100) ++#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080) ++#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040) ++#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020) ++#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004) ++#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) ++#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000) ++#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001) ++#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000) ++ ++/* Bit definitions and macros for PAR_IRQ */ ++#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02) ++#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10) ++#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) ++#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00) ++#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) ++#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00) ++ ++/* Bit definitions and macros for PAR_PCI */ ++#define MCF_GPIO_PAR_PCI_REQ0 (0x0001) ++#define MCF_GPIO_PAR_PCI_REQ1 (0x0004) ++#define MCF_GPIO_PAR_PCI_REQ2 (0x0010) ++#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_PCI_GNT0 (0x0100) ++#define MCF_GPIO_PAR_PCI_GNT1 (0x0400) ++#define MCF_GPIO_PAR_PCI_GNT2 (0x1000) ++#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) ++#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF) ++#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000) ++#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) ++#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000) ++#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400) ++#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100) ++#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F) ++#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) ++#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) ++#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010) ++#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040) ++#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000) ++#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001) ++#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000) ++ ++/* Bit definitions and macros for MSCR_SDRAM */ ++#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) ++#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) ++#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) ++#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) ++#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) ++ ++/* Bit definitions and macros for MSCR_PCI */ ++#define MCF_GPIO_MSCR_PCI_PCI (0x01) ++#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) ++#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) ++ ++/* Bit definitions and macros for DSCR_I2C */ ++#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_FLEXBUS */ ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) ++#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_FEC */ ++#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) ++#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_UART */ ++#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) ++#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_DSPI */ ++#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_TIMER */ ++#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_SSI */ ++#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_DMA */ ++#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_DEBUG */ ++#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_RESET */ ++#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_IRQ */ ++#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_USB */ ++#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00) ++ ++/* Bit definitions and macros for DSCR_ATA */ ++#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) ++#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_GPIO_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_intc.h +@@ -0,0 +1,724 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_INTC_H__ ++#define __MCF5445X_INTC_H__ ++ ++/********************************************************************* ++* ++* Interrupt Controller (INTC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) ++#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) ++#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) ++#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) ++#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) ++#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) ++#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) ++#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) ++#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) ++#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) ++#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) ++#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) ++#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) ++#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) ++#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) ++#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) ++#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) ++#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) ++#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) ++#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) ++#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) ++#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) ++#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) ++#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) ++#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) ++#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) ++#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) ++#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) ++#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) ++#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) ++#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) ++#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) ++#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) ++#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) ++#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) ++#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) ++#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) ++#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) ++#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) ++#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) ++#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) ++#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) ++#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) ++#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) ++#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) ++#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) ++#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) ++#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) ++#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) ++#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) ++#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) ++#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) ++#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) ++#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) ++#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) ++#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) ++#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) ++#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) ++#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) ++#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) ++#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) ++#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) ++#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) ++#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) ++#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) ++#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) ++#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) ++#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) ++#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) ++#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) ++#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) ++#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) ++#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) ++#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) ++#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) ++#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) ++#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) ++#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) ++#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) ++#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) ++#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) ++#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) ++#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) ++#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) ++#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) ++#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) ++#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) ++#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) ++#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) ++#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) ++#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) ++#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) ++#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) ++#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) ++#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) ++#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) ++#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) ++#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) ++#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) ++#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) ++#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) ++#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) ++#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) ++#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) ++#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) ++#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) ++#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) ++#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) ++#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) ++#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) ++#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) ++#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) ++#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) ++#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) ++#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) ++#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) ++#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) ++#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) ++#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) ++#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) ++#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) ++#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) ++#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) ++#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) ++#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) ++#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) ++#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) ++#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) ++#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) ++#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) ++#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) ++#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) ++#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) ++#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) ++#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) ++#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) ++#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) ++#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) ++#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) ++#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) ++#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) ++#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) ++#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) ++#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) ++#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) ++#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) ++#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) ++#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) ++#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) ++#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) ++#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) ++#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) ++#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) ++#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) ++#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) ++#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) ++#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) ++#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) ++#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) ++#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) ++#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) ++#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) ++#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8 ++#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001)) ++#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004)) ++#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001)) ++#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004)) ++ ++/* Parameterized register read/write macros for multiple modules */ ++#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) ++#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) ++#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) ++#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) ++#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) ++#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) ++#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) ++#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) ++#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) ++#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) ++#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) ++#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) ++#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) ++#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) ++#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) ++#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) ++#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) ++#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) ++#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) ++#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) ++#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) ++#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) ++#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) ++#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) ++#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) ++#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) ++#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) ++#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) ++#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) ++#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) ++#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) ++#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) ++#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) ++#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) ++#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) ++#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) ++#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) ++#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) ++#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) ++#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) ++#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) ++#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) ++#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) ++#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) ++#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) ++#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) ++#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) ++#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) ++#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) ++#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) ++#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) ++#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) ++#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) ++#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) ++#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) ++#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) ++#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) ++#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) ++#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) ++#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) ++#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) ++#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) ++#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) ++#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) ++#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) ++#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) ++#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) ++#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) ++#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) ++#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) ++#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) ++#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) ++#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) ++#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) ++#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) ++#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) ++#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) ++#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) ++#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) ++#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) ++#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) ++#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) ++ ++/* Bit definitions and macros for IPRH */ ++#define MCF_INTC_IPRH_INT32 (0x00000001) ++#define MCF_INTC_IPRH_INT33 (0x00000002) ++#define MCF_INTC_IPRH_INT34 (0x00000004) ++#define MCF_INTC_IPRH_INT35 (0x00000008) ++#define MCF_INTC_IPRH_INT36 (0x00000010) ++#define MCF_INTC_IPRH_INT37 (0x00000020) ++#define MCF_INTC_IPRH_INT38 (0x00000040) ++#define MCF_INTC_IPRH_INT39 (0x00000080) ++#define MCF_INTC_IPRH_INT40 (0x00000100) ++#define MCF_INTC_IPRH_INT41 (0x00000200) ++#define MCF_INTC_IPRH_INT42 (0x00000400) ++#define MCF_INTC_IPRH_INT43 (0x00000800) ++#define MCF_INTC_IPRH_INT44 (0x00001000) ++#define MCF_INTC_IPRH_INT45 (0x00002000) ++#define MCF_INTC_IPRH_INT46 (0x00004000) ++#define MCF_INTC_IPRH_INT47 (0x00008000) ++#define MCF_INTC_IPRH_INT48 (0x00010000) ++#define MCF_INTC_IPRH_INT49 (0x00020000) ++#define MCF_INTC_IPRH_INT50 (0x00040000) ++#define MCF_INTC_IPRH_INT51 (0x00080000) ++#define MCF_INTC_IPRH_INT52 (0x00100000) ++#define MCF_INTC_IPRH_INT53 (0x00200000) ++#define MCF_INTC_IPRH_INT54 (0x00400000) ++#define MCF_INTC_IPRH_INT55 (0x00800000) ++#define MCF_INTC_IPRH_INT56 (0x01000000) ++#define MCF_INTC_IPRH_INT57 (0x02000000) ++#define MCF_INTC_IPRH_INT58 (0x04000000) ++#define MCF_INTC_IPRH_INT59 (0x08000000) ++#define MCF_INTC_IPRH_INT60 (0x10000000) ++#define MCF_INTC_IPRH_INT61 (0x20000000) ++#define MCF_INTC_IPRH_INT62 (0x40000000) ++#define MCF_INTC_IPRH_INT63 (0x80000000) ++ ++/* Bit definitions and macros for IPRL */ ++#define MCF_INTC_IPRL_INT0 (0x00000001) ++#define MCF_INTC_IPRL_INT1 (0x00000002) ++#define MCF_INTC_IPRL_INT2 (0x00000004) ++#define MCF_INTC_IPRL_INT3 (0x00000008) ++#define MCF_INTC_IPRL_INT4 (0x00000010) ++#define MCF_INTC_IPRL_INT5 (0x00000020) ++#define MCF_INTC_IPRL_INT6 (0x00000040) ++#define MCF_INTC_IPRL_INT7 (0x00000080) ++#define MCF_INTC_IPRL_INT8 (0x00000100) ++#define MCF_INTC_IPRL_INT9 (0x00000200) ++#define MCF_INTC_IPRL_INT10 (0x00000400) ++#define MCF_INTC_IPRL_INT11 (0x00000800) ++#define MCF_INTC_IPRL_INT12 (0x00001000) ++#define MCF_INTC_IPRL_INT13 (0x00002000) ++#define MCF_INTC_IPRL_INT14 (0x00004000) ++#define MCF_INTC_IPRL_INT15 (0x00008000) ++#define MCF_INTC_IPRL_INT16 (0x00010000) ++#define MCF_INTC_IPRL_INT17 (0x00020000) ++#define MCF_INTC_IPRL_INT18 (0x00040000) ++#define MCF_INTC_IPRL_INT19 (0x00080000) ++#define MCF_INTC_IPRL_INT20 (0x00100000) ++#define MCF_INTC_IPRL_INT21 (0x00200000) ++#define MCF_INTC_IPRL_INT22 (0x00400000) ++#define MCF_INTC_IPRL_INT23 (0x00800000) ++#define MCF_INTC_IPRL_INT24 (0x01000000) ++#define MCF_INTC_IPRL_INT25 (0x02000000) ++#define MCF_INTC_IPRL_INT26 (0x04000000) ++#define MCF_INTC_IPRL_INT27 (0x08000000) ++#define MCF_INTC_IPRL_INT28 (0x10000000) ++#define MCF_INTC_IPRL_INT29 (0x20000000) ++#define MCF_INTC_IPRL_INT30 (0x40000000) ++#define MCF_INTC_IPRL_INT31 (0x80000000) ++ ++/* Bit definitions and macros for IMRH */ ++#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) ++#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) ++#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) ++#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) ++#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) ++#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) ++#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) ++#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) ++#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) ++#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) ++#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) ++#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) ++#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) ++#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) ++#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) ++#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) ++#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) ++#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) ++#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) ++#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) ++#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) ++#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) ++#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) ++#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) ++#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) ++#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) ++#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) ++#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) ++#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) ++#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) ++#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) ++#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) ++ ++/* Bit definitions and macros for IMRL */ ++#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) ++#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) ++#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) ++#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) ++#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) ++#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) ++#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) ++#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) ++#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) ++#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) ++#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) ++#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) ++#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) ++#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) ++#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) ++#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) ++#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) ++#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) ++#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) ++#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) ++#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) ++#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) ++#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) ++#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) ++#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) ++#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) ++#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) ++#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) ++#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) ++#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) ++#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) ++#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) ++ ++/* Bit definitions and macros for INTFRCH */ ++#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) ++#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) ++#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) ++#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) ++#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) ++#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) ++#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) ++#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) ++#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) ++#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) ++#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) ++#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) ++#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) ++#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) ++#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) ++#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) ++#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) ++#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) ++#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) ++#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) ++#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) ++#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) ++#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) ++#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) ++#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) ++#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) ++#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) ++#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) ++#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) ++#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) ++#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) ++#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) ++ ++/* Bit definitions and macros for INTFRCL */ ++#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) ++#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) ++#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) ++#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) ++#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) ++#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) ++#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) ++#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) ++#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) ++#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) ++#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) ++#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) ++#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) ++#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) ++#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) ++#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) ++#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) ++#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) ++#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) ++#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) ++#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) ++#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) ++#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) ++#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) ++#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) ++#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) ++#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) ++#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) ++#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) ++#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) ++#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) ++#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) ++ ++/* Bit definitions and macros for ICONFIG */ ++#define MCF_INTC_ICONFIG_EMASK (0x0020) ++#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) ++#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) ++#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) ++#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) ++#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) ++#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) ++#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) ++ ++/* Bit definitions and macros for SIMR */ ++#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)) ++ ++/* Bit definitions and macros for CIMR */ ++#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)) ++ ++/* Bit definitions and macros for CLMASK */ ++#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)) ++ ++/* Bit definitions and macros for SLMASK */ ++#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)) ++ ++/* Bit definitions and macros for ICR group */ ++#define MCF_INTC_ICR_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR1 */ ++#define MCF_INTC_ICR1_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR2 */ ++#define MCF_INTC_ICR2_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR3 */ ++#define MCF_INTC_ICR3_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR4 */ ++#define MCF_INTC_ICR4_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR5 */ ++#define MCF_INTC_ICR5_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR6 */ ++#define MCF_INTC_ICR6_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR7 */ ++#define MCF_INTC_ICR7_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR8 */ ++#define MCF_INTC_ICR8_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR9 */ ++#define MCF_INTC_ICR9_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR10 */ ++#define MCF_INTC_ICR10_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR11 */ ++#define MCF_INTC_ICR11_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR12 */ ++#define MCF_INTC_ICR12_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR13 */ ++#define MCF_INTC_ICR13_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR14 */ ++#define MCF_INTC_ICR14_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR15 */ ++#define MCF_INTC_ICR15_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR16 */ ++#define MCF_INTC_ICR16_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR17 */ ++#define MCF_INTC_ICR17_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR18 */ ++#define MCF_INTC_ICR18_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR19 */ ++#define MCF_INTC_ICR19_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR20 */ ++#define MCF_INTC_ICR20_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR21 */ ++#define MCF_INTC_ICR21_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR22 */ ++#define MCF_INTC_ICR22_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR23 */ ++#define MCF_INTC_ICR23_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR24 */ ++#define MCF_INTC_ICR24_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR25 */ ++#define MCF_INTC_ICR25_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR26 */ ++#define MCF_INTC_ICR26_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR27 */ ++#define MCF_INTC_ICR27_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR28 */ ++#define MCF_INTC_ICR28_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR29 */ ++#define MCF_INTC_ICR29_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR30 */ ++#define MCF_INTC_ICR30_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR31 */ ++#define MCF_INTC_ICR31_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR32 */ ++#define MCF_INTC_ICR32_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR33 */ ++#define MCF_INTC_ICR33_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR34 */ ++#define MCF_INTC_ICR34_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR35 */ ++#define MCF_INTC_ICR35_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR36 */ ++#define MCF_INTC_ICR36_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR37 */ ++#define MCF_INTC_ICR37_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR38 */ ++#define MCF_INTC_ICR38_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR39 */ ++#define MCF_INTC_ICR39_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR40 */ ++#define MCF_INTC_ICR40_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR41 */ ++#define MCF_INTC_ICR41_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR42 */ ++#define MCF_INTC_ICR42_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR43 */ ++#define MCF_INTC_ICR43_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR44 */ ++#define MCF_INTC_ICR44_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR45 */ ++#define MCF_INTC_ICR45_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR46 */ ++#define MCF_INTC_ICR46_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR47 */ ++#define MCF_INTC_ICR47_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR48 */ ++#define MCF_INTC_ICR48_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR49 */ ++#define MCF_INTC_ICR49_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR50 */ ++#define MCF_INTC_ICR50_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR51 */ ++#define MCF_INTC_ICR51_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR52 */ ++#define MCF_INTC_ICR52_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR53 */ ++#define MCF_INTC_ICR53_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR54 */ ++#define MCF_INTC_ICR54_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR55 */ ++#define MCF_INTC_ICR55_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR56 */ ++#define MCF_INTC_ICR56_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR57 */ ++#define MCF_INTC_ICR57_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR58 */ ++#define MCF_INTC_ICR58_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR59 */ ++#define MCF_INTC_ICR59_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR60 */ ++#define MCF_INTC_ICR60_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR61 */ ++#define MCF_INTC_ICR61_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR62 */ ++#define MCF_INTC_ICR62_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR63 */ ++#define MCF_INTC_ICR63_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for SWIACK */ ++#define MCF_INTC_SWIACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for LIACK group */ ++#define MCF_INTC_LIACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L1IACK */ ++#define MCF_INTC_L1IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L2IACK */ ++#define MCF_INTC_L2IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L3IACK */ ++#define MCF_INTC_L3IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L4IACK */ ++#define MCF_INTC_L4IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L5IACK */ ++#define MCF_INTC_L5IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L6IACK */ ++#define MCF_INTC_L6IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L7IACK */ ++#define MCF_INTC_L7IACK_VECTOR(x) (x) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_INTC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_pci.h +@@ -0,0 +1,238 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_PCI_H__ ++#define __MCF5445X_PCI_H__ ++ ++/********************************************************************* ++* ++* PCI Bus Controller (PCI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000) ++#define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004) ++#define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008) ++#define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C) ++#define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010) ++#define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014) ++#define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018) ++#define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C) ++#define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020) ++#define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024) ++#define MCF_PCI_PCISID MCF_REG32(0xFC0A802C) ++#define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C) ++#define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060) ++#define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064) ++#define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068) ++#define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C) ++#define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070) ++#define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074) ++#define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078) ++#define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080) ++#define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084) ++#define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088) ++#define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C) ++#define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090) ++#define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094) ++#define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098) ++#define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C) ++#define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0) ++#define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4) ++#define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004)) ++ ++/* Bit definitions and macros for PCIIDR */ ++#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)) ++#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for PCISCR */ ++#define MCF_PCI_PCISCR_M (0x00000002) ++#define MCF_PCI_PCISCR_B (0x00000004) ++#define MCF_PCI_PCISCR_SP (0x00000008) ++#define MCF_PCI_PCISCR_MW (0x00000010) ++#define MCF_PCI_PCISCR_PER (0x00000040) ++#define MCF_PCI_PCISCR_S (0x00000100) ++#define MCF_PCI_PCISCR_F (0x00000200) ++#define MCF_PCI_PCISCR_C (0x00100000) ++#define MCF_PCI_PCISCR_66M (0x00200000) ++#define MCF_PCI_PCISCR_R (0x00400000) ++#define MCF_PCI_PCISCR_FC (0x00800000) ++#define MCF_PCI_PCISCR_DP (0x01000000) ++#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) ++#define MCF_PCI_PCISCR_TS (0x08000000) ++#define MCF_PCI_PCISCR_TR (0x10000000) ++#define MCF_PCI_PCISCR_MA (0x20000000) ++#define MCF_PCI_PCISCR_SE (0x40000000) ++#define MCF_PCI_PCISCR_PE (0x80000000) ++ ++/* Bit definitions and macros for PCICCRIR */ ++#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) ++ ++/* Bit definitions and macros for PCICR1 */ ++#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)) ++#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) ++#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) ++#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCIBAR0 */ ++#define MCF_PCI_PCIBAR0_IO (0x00000001) ++#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) ++#define MCF_PCI_PCIBAR0_PREF (0x00000008) ++#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for PCIBAR1 */ ++#define MCF_PCI_PCIBAR1_IO (0x00000001) ++#define MCF_PCI_PCIBAR1_PREF (0x00000008) ++#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20) ++ ++/* Bit definitions and macros for PCIBAR2 */ ++#define MCF_PCI_PCIBAR2_IO (0x00000001) ++#define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1) ++#define MCF_PCI_PCIBAR2_PREF (0x00000008) ++#define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22) ++ ++/* Bit definitions and macros for PCIBAR3 */ ++#define MCF_PCI_PCIBAR3_IO (0x00000001) ++#define MCF_PCI_PCIBAR3_PREF (0x00000008) ++#define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCIBAR4 */ ++#define MCF_PCI_PCIBAR4_IO (0x00000001) ++#define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1) ++#define MCF_PCI_PCIBAR4_PREF (0x00000008) ++#define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27) ++ ++/* Bit definitions and macros for PCIBAR5 */ ++#define MCF_PCI_PCIBAR5_IO (0x00000001) ++#define MCF_PCI_PCIBAR5_PREF (0x00000008) ++#define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for PCISID */ ++#define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF)) ++#define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for PCICR2 */ ++#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) ++#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) ++#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCIGSCR */ ++#define MCF_PCI_PCIGSCR_PR (0x00000001) ++#define MCF_PCI_PCIGSCR_SEE (0x00001000) ++#define MCF_PCI_PCIGSCR_PEE (0x00002000) ++#define MCF_PCI_PCIGSCR_SE (0x10000000) ++#define MCF_PCI_PCIGSCR_PE (0x20000000) ++ ++/* Bit definitions and macros for PCITBATR0A */ ++#define MCF_PCI_PCITBATR0A_EN (0x00000001) ++#define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for PCITBATR1A */ ++#define MCF_PCI_PCITBATR1A_EN (0x00000001) ++#define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20) ++ ++/* Bit definitions and macros for PCITCR */ ++#define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCITCR_WCD (0x00000100) ++#define MCF_PCI_PCITCR_P (0x00010000) ++#define MCF_PCI_PCITCR_PID (0x00020000) ++#define MCF_PCI_PCITCR_LD (0x01000000) ++ ++/* Bit definitions and macros for PCIIWBTAR group */ ++#define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000))) ++#define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000) ++#define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000) ++ ++/* Bit definitions and macros for PCIIW0BTAR */ ++#define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000))) ++#define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000) ++#define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000) ++ ++/* Bit definitions and macros for PCIIWCR */ ++#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) ++#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) ++#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) ++#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) ++#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) ++#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) ++#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100) ++#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) ++#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) ++#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) ++#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) ++ ++/* Bit definitions and macros for PCIICR */ ++#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)) ++#define MCF_PCI_PCIICR_TAE (0x01000000) ++#define MCF_PCI_PCIICR_IAE (0x02000000) ++#define MCF_PCI_PCIICR_REE (0x04000000) ++ ++/* Bit definitions and macros for PCIISR */ ++#define MCF_PCI_PCIISR_TA (0x01000000) ++#define MCF_PCI_PCIISR_IA (0x02000000) ++#define MCF_PCI_PCIISR_RE (0x04000000) ++ ++/* Bit definitions and macros for PCITCR2 */ ++#define MCF_PCI_PCITCR2_CR (0x00000001) ++#define MCF_PCI_PCITCR2_B0E (0x00000100) ++#define MCF_PCI_PCITCR2_B1E (0x00000200) ++#define MCF_PCI_PCITCR2_B2E (0x00000400) ++#define MCF_PCI_PCITCR2_B3E (0x00000800) ++#define MCF_PCI_PCITCR2_B4E (0x00001000) ++#define MCF_PCI_PCITCR2_B5E (0x00002000) ++ ++/* Bit definitions and macros for PCITBATR0 */ ++#define MCF_PCI_PCITBATR0_EN (0x00000001) ++#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for PCITBATR1 */ ++#define MCF_PCI_PCITBATR1_EN (0x00000001) ++#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20) ++ ++/* Bit definitions and macros for PCITBATR2 */ ++#define MCF_PCI_PCITBATR2_EN (0x00000001) ++#define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22) ++ ++/* Bit definitions and macros for PCITBATR3 */ ++#define MCF_PCI_PCITBATR3_EN (0x00000001) ++#define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for PCITBATR4 */ ++#define MCF_PCI_PCITBATR4_EN (0x00000001) ++#define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27) ++ ++/* Bit definitions and macros for PCITBATR5 */ ++#define MCF_PCI_PCITBATR5_EN (0x00000001) ++#define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for PCICAR */ ++#define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC) ++#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) ++#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) ++#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) ++#define MCF_PCI_PCICAR_E (0x80000000) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_PCI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_pciarb.h +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_PCIARB_H__ ++#define __MCF5445X_PCIARB_H__ ++ ++/********************************************************************* ++* ++* PCI Arbiter Module (PCIARB) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_PCIARB_PACR MCF_REG32(0xFC0AC000) ++#define MCF_PCIARB_PASR MCF_REG32(0xFC0AC004) ++ ++/* Bit definitions and macros for PACR */ ++#define MCF_PCIARB_PACR_INTMPRI (0x00000001) ++#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) ++#define MCF_PCIARB_PACR_RA (0x00008000) ++#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) ++#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) ++#define MCF_PCIARB_PACR_PKMD (0x40000000) ++#define MCF_PCIARB_PACR_DS (0x80000000) ++ ++/* Bit definitions and macros for PASR */ ++#define MCF_PCIARB_PASR_ITLMBK (0x00010000) ++#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_PCIARB_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_rtc.h +@@ -0,0 +1,114 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: ChengJu Cai, B22600@freescale.com ++ * ++ * Description: ++ * This file is the register definition of m5445x RTC module ++ * ++ * Changelog: ++ * ++ * ++ * This file is part of the Linux kernel ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++ ++#ifndef __MCF5445X_RTC_H__ ++#define __MCF5445X_RTC_H__ ++ ++/********************************************************************* ++* ++* Real-time Clock (RTC) ++* ++*********************************************************************/ ++#ifndef MCFINT_VECBASE ++#define MCFINT_VECBASE 64 ++#endif ++ ++#define MCFSIM_ICR_RTC (0xFC048040 + 63) ++ ++/* Register read/write macros */ ++#define MCF_RTC_HOURMIN 0xFC03C000 ++#define MCF_RTC_SECONDS 0xFC03C004 ++#define MCF_RTC_ALRM_HM 0xFC03C008 ++#define MCF_RTC_ALRM_SEC 0xFC03C00C ++#define MCF_RTC_CR 0xFC03C010 ++#define MCF_RTC_ISR 0xFC03C014 ++#define MCF_RTC_IER 0xFC03C018 ++#define MCF_RTC_STPWCH 0xFC03C01C ++#define MCF_RTC_DAYS 0xFC03C020 ++#define MCF_RTC_ALRM_DAY 0xFC03C024 ++#define MCF_RTC_GOCU 0xFC03C034 ++#define MCF_RTC_GOCL 0xFC03C038 ++ ++/* Bit definitions and macros for MCF_RTC_HOURMIN */ ++#define MCF_RTC_HOURMIN_MINUTES(x) (((x) & 0x0000003F) << 0) ++#define MCF_RTC_HOURMIN_HOURS(x) (((x) & 0x0000001F) << 8) ++ ++/* Bit definitions and macros for MCF_RTC_SECONDS */ ++#define MCF_RTC_SECONDS_SECONDS(x) (((x) & 0x0000003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_ALRM_HM */ ++#define MCF_RTC_ALRM_HM_MINUTES(x) (((x) & 0x0000003F) << 0) ++#define MCF_RTC_ALRM_HM_HOURS(x) (((x) & 0x0000001F) << 8) ++ ++/* Bit definitions and macros for MCF_RTC_ALRM_SEC */ ++#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x) & 0x0000003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_CR */ ++#define MCF_RTC_CR_SWR 0x00000001 ++#define MCF_RTC_CR_EN 0x00000080 ++ ++/* Bit definitions and macros for MCF_RTC_ISR */ ++#define MCF_RTC_ISR_SW 0x00000001 ++#define MCF_RTC_ISR_MIN 0x00000002 ++#define MCF_RTC_ISR_ALM 0x00000004 ++#define MCF_RTC_ISR_DAY 0x00000008 ++#define MCF_RTC_ISR_1HZ 0x00000010 ++#define MCF_RTC_ISR_HR 0x00000020 ++#define MCF_RTC_ISR_2HZ 0x00000080 ++#define MCF_RTC_ISR_SAM0 0x00000100 ++#define MCF_RTC_ISR_SAM1 0x00000200 ++#define MCF_RTC_ISR_SAM2 0x00000400 ++#define MCF_RTC_ISR_SAM3 0x00000800 ++#define MCF_RTC_ISR_SAM4 0x00001000 ++#define MCF_RTC_ISR_SAM5 0x00002000 ++#define MCF_RTC_ISR_SAM6 0x00004000 ++#define MCF_RTC_ISR_SAM7 0x00008000 ++ ++/* Bit definitions and macros for MCF_RTC_IER */ ++#define MCF_RTC_IER_SW 0x00000001 ++#define MCF_RTC_IER_MIN 0x00000002 ++#define MCF_RTC_IER_ALM 0x00000004 ++#define MCF_RTC_IER_DAY 0x00000008 ++#define MCF_RTC_IER_1HZ 0x00000010 ++#define MCF_RTC_IER_HR 0x00000020 ++#define MCF_RTC_IER_2HZ 0x00000080 ++#define MCF_RTC_IER_SAM0 0x00000100 ++#define MCF_RTC_IER_SAM1 0x00000200 ++#define MCF_RTC_IER_SAM2 0x00000400 ++#define MCF_RTC_IER_SAM3 0x00000800 ++#define MCF_RTC_IER_SAM4 0x00001000 ++#define MCF_RTC_IER_SAM5 0x00002000 ++#define MCF_RTC_IER_SAM6 0x00004000 ++#define MCF_RTC_IER_SAM7 0x00008000 ++ ++/* Bit definitions and macros for MCF_RTC_STPWCH */ ++#define MCF_RTC_STPWCH_CNT(x) (((x) & 0x0000003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_DAYS */ ++#define MCF_RTC_DAYS_DAYS(x) (((x) & 0x0000FFFF) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_ALRM_DAY */ ++#define MCF_RTC_ALRM_DAY_DAYS(x) (((x) & 0x0000FFFF) << 0) ++ ++/* Interrupt source */ ++#define MCFINT_RTC 63 ++/*********************************************************************/ ++ ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_scm.h +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: ChengJu Cai<B22600@freescale.com> ++ * ++ * Description: ++ * This file is the register definition of m5445x's SCM module ++ * ++ * Changelog: ++ * Thur Sep 03 2009 ChengJu Cai <B22600@freescale.com> ++ * - create ++ * ++ * This file is part of the Linux kernel ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef __MCF5445X_SCM_H__ ++#define __MCF5445X_SCM_H__ ++ ++/********************************************************************* ++* ++* System Control Module (SCM) ++* ++*********************************************************************/ ++ ++/* Core Watchdog(CW) Register read/write macros */ ++#define MCF_SCM_CWCR MCF_REG16(0xFC040016) /* CW Control Register */ ++#define MCF_SCM_CWSR MCF_REG08(0xFC04001B) /* CW Service Register */ ++ ++/* CW Bit definitions and macros for SWCR */ ++#define MCF_SCM_CWCR_RO (0x8000) /* CWCR is read-only */ ++#define MCF_SCM_CWCR_CWRWR (0x0100) /* CW run when halted */ ++#define MCF_SCM_CWCR_CWE (0x0080) /* CW timer enable */ ++#define MCF_SCM_CWCR_CWRI(x) (((x) & 0x03) << 5) /* CW reset/interrupt */ ++#define MCF_SCM_CWCR_CWT(x) (((x) & 0x1F) << 0) /* CW time-out period */ ++ ++#ifdef CONFIG_M54455 ++#define MCF_GPT_MAX_TIMEOUT 16 ++#elif defined(CONFIG_M54451) ++#define MCF_GPT_MAX_TIMEOUT 17 ++#endif ++/********************************************************************/ ++ ++#endif /* __MCF5445X_SCM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_sdramc.h +@@ -0,0 +1,142 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Matt Waddel Matt.Waddel@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_SDRAMC_H__ ++#define __MCF5445X_SDRAMC_H__ ++ ++/********************************************************************* ++* ++* SDRAM Controller (SDRAMC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_SDRAMC_SDMR \ ++ (*(vuint32 *)(0xFC0B8000)) /* SDRAM Mode/Extended Mode Register */ ++#define MCF_SDRAMC_SDCR \ ++ (*(vuint32 *)(0xFC0B8004)) /* SDRAM Control Register */ ++#define MCF_SDRAMC_SDCFG1 \ ++ (*(vuint32 *)(0xFC0B8008)) /* SDRAM Configuration Register 1 */ ++#define MCF_SDRAMC_SDCFG2 \ ++ (*(vuint32 *)(0xFC0B800C)) /* SDRAM Configuration Register 2 */ ++#define MCF_SDRAMC_SDCS0 \ ++ (*(vuint32 *)(0xFC0B8110)) /* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS1 \ ++ (*(vuint32 *)(0xFC0B8114)) /* SDRAM Chip Select Register */ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004))) ++ ++/* Bit definitions and macros for SDMR */ ++#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ ++#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */ ++#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ ++#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ ++#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000) ++#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) ++ ++/* Bit definitions and macros for SDCR */ ++#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ ++#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ ++#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ ++#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ ++#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ ++#define MCF_SDRAMC_SDCR_REF_CNT(x) \ ++ (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ ++#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ ++#define MCF_SDRAMC_SDCR_ADDR_MUX(x) \ ++ (((x)&0x00000003)<<24) /* Internal Address Mux Select */ ++#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ ++#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ ++#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ ++#define MCF_SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ ++/* SDRAM Mode Register Programming Enable */ ++#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) ++#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00) ++ ++/* Bit definitions and macros for SDCFG1 */ ++#define MCF_SDRAMC_SDCFG1_WT_LAT(x) \ ++ (((x)&0x00000007)<<4) /* Write Latency */ ++#define MCF_SDRAMC_SDCFG1_REF2ACT(x) \ ++ (((x)&0x0000000F)<<8) /* Refresh to active delay */ ++#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) \ ++ (((x)&0x00000007)<<12) /* Precharge to active delay */ ++#define MCF_SDRAMC_SDCFG1_ACT2RW(x) \ ++ (((x)&0x00000007)<<16) /* Active to read/write delay */ ++#define MCF_SDRAMC_SDCFG1_RD_LAT(x) \ ++ (((x)&0x0000000F)<<20) /* Read CAS Latency */ ++#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) \ ++ (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) \ ++ (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ ++ ++/* Bit definitions and macros for SDCFG2 */ ++#define MCF_SDRAMC_SDCFG2_BL(x) \ ++ (((x)&0x0000000F)<<16) /* Burst Length */ ++#define MCF_SDRAMC_SDCFG2_BRD2W(x) \ ++ (((x)&0x0000000F)<<20) /* Burst read to write delay */ ++#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) \ ++ (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG2_BRD2RP(x) \ ++ (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ ++ ++/* Bit definitions and macros for SDCS group */ ++#define MCF_SDRAMC_SDCS_CSSZ(x) \ ++ (((x)&0x0000001F)) /* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS_CSBA(x) \ ++ (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) ++#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) ++#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) ++#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) ++#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) ++#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) ++#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) ++#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) ++#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) ++#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) ++#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) ++#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) ++#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) ++#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) ++#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) ++ ++/* Bit definitions and macros for SDCS0 */ ++#define MCF_SDRAMC_SDCS0_CSSZ(x) \ ++ (((x)&0x0000001F)) /* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS0_CSBA(x) \ ++ (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000) ++#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000) ++#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013) ++#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014) ++#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015) ++#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016) ++#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017) ++#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018) ++#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019) ++#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A) ++#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B) ++#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C) ++#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D) ++#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E) ++#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F) ++ ++/* Bit definitions and macros for SDCS1 */ ++#define MCF_SDRAMC_SDCS1_CSSZ(x) \ ++ (((x)&0x0000001F)) /* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS1_CSBA(x) \ ++ (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_SDRAMC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_ssi.h +@@ -0,0 +1,187 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_SSI_H__ ++#define __MCF5445X_SSI_H__ ++ ++/********************************************************************* ++* ++* Synchronous Serial Interface (SSI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_SSI_TX0 MCF_REG32(0xFC0BC000) ++#define MCF_SSI_TX1 MCF_REG32(0xFC0BC004) ++#define MCF_SSI_RX0 MCF_REG32(0xFC0BC008) ++#define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C) ++#define MCF_SSI_CR MCF_REG32(0xFC0BC010) ++#define MCF_SSI_ISR MCF_REG32(0xFC0BC014) ++#define MCF_SSI_IER MCF_REG32(0xFC0BC018) ++#define MCF_SSI_TCR MCF_REG32(0xFC0BC01C) ++#define MCF_SSI_RCR MCF_REG32(0xFC0BC020) ++#define MCF_SSI_CCR MCF_REG32(0xFC0BC024) ++#define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C) ++#define MCF_SSI_ACR MCF_REG32(0xFC0BC038) ++#define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C) ++#define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040) ++#define MCF_SSI_ATAG MCF_REG32(0xFC0BC044) ++#define MCF_SSI_TMASK MCF_REG32(0xFC0BC048) ++#define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004)) ++#define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004)) ++ ++/* Bit definitions and macros for TX group */ ++#define MCF_SSI_TX_SSI_TX(x) (x) ++ ++/* Bit definitions and macros for TX0 */ ++#define MCF_SSI_TX0_SSI_TX(x) (x) ++ ++/* Bit definitions and macros for TX1 */ ++#define MCF_SSI_TX1_SSI_TX(x) (x) ++ ++/* Bit definitions and macros for RX group */ ++#define MCF_SSI_RX_SSI_RX(x) (x) ++ ++/* Bit definitions and macros for RX0 */ ++#define MCF_SSI_RX0_SSI_RX(x) (x) ++ ++/* Bit definitions and macros for RX1 */ ++#define MCF_SSI_RX1_SSI_RX(x) (x) ++ ++/* Bit definitions and macros for CR */ ++#define MCF_SSI_CR_SSI_EN (0x00000001) ++#define MCF_SSI_CR_TE (0x00000002) ++#define MCF_SSI_CR_RE (0x00000004) ++#define MCF_SSI_CR_NET (0x00000008) ++#define MCF_SSI_CR_SYN (0x00000010) ++#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5) ++#define MCF_SSI_CR_MCE (0x00000080) ++#define MCF_SSI_CR_TCH (0x00000100) ++#define MCF_SSI_CR_CIS (0x00000200) ++#define MCF_SSI_CR_I2S_NORMAL (0x00000000) ++#define MCF_SSI_CR_I2S_MASTER (0x00000020) ++#define MCF_SSI_CR_I2S_SLAVE (0x00000040) ++ ++/* Bit definitions and macros for ISR */ ++#define MCF_SSI_ISR_TFE0 (0x00000001) ++#define MCF_SSI_ISR_TFE1 (0x00000002) ++#define MCF_SSI_ISR_RFF0 (0x00000004) ++#define MCF_SSI_ISR_RFF1 (0x00000008) ++#define MCF_SSI_ISR_RLS (0x00000010) ++#define MCF_SSI_ISR_TLS (0x00000020) ++#define MCF_SSI_ISR_RFS (0x00000040) ++#define MCF_SSI_ISR_TFS (0x00000080) ++#define MCF_SSI_ISR_TUE0 (0x00000100) ++#define MCF_SSI_ISR_TUE1 (0x00000200) ++#define MCF_SSI_ISR_ROE0 (0x00000400) ++#define MCF_SSI_ISR_ROE1 (0x00000800) ++#define MCF_SSI_ISR_TDE0 (0x00001000) ++#define MCF_SSI_ISR_TDE1 (0x00002000) ++#define MCF_SSI_ISR_RDR0 (0x00004000) ++#define MCF_SSI_ISR_RDR1 (0x00008000) ++#define MCF_SSI_ISR_RXT (0x00010000) ++#define MCF_SSI_ISR_CMDDU (0x00020000) ++#define MCF_SSI_ISR_CMDAU (0x00040000) ++ ++/* Bit definitions and macros for IER */ ++#define MCF_SSI_IER_TFE0 (0x00000001) ++#define MCF_SSI_IER_TFE1 (0x00000002) ++#define MCF_SSI_IER_RFF0 (0x00000004) ++#define MCF_SSI_IER_RFF1 (0x00000008) ++#define MCF_SSI_IER_RLS (0x00000010) ++#define MCF_SSI_IER_TLS (0x00000020) ++#define MCF_SSI_IER_RFS (0x00000040) ++#define MCF_SSI_IER_TFS (0x00000080) ++#define MCF_SSI_IER_TUE0 (0x00000100) ++#define MCF_SSI_IER_TUE1 (0x00000200) ++#define MCF_SSI_IER_ROE0 (0x00000400) ++#define MCF_SSI_IER_ROE1 (0x00000800) ++#define MCF_SSI_IER_TDE0 (0x00001000) ++#define MCF_SSI_IER_TDE1 (0x00002000) ++#define MCF_SSI_IER_RDR0 (0x00004000) ++#define MCF_SSI_IER_RDR1 (0x00008000) ++#define MCF_SSI_IER_RXT (0x00010000) ++#define MCF_SSI_IER_CMDU (0x00020000) ++#define MCF_SSI_IER_CMDAU (0x00040000) ++#define MCF_SSI_IER_TIE (0x00080000) ++#define MCF_SSI_IER_TDMAE (0x00100000) ++#define MCF_SSI_IER_RIE (0x00200000) ++#define MCF_SSI_IER_RDMAE (0x00400000) ++ ++/* Bit definitions and macros for TCR */ ++#define MCF_SSI_TCR_TEFS (0x00000001) ++#define MCF_SSI_TCR_TFSL (0x00000002) ++#define MCF_SSI_TCR_TFSI (0x00000004) ++#define MCF_SSI_TCR_TSCKP (0x00000008) ++#define MCF_SSI_TCR_TSHFD (0x00000010) ++#define MCF_SSI_TCR_TXDIR (0x00000020) ++#define MCF_SSI_TCR_TFDIR (0x00000040) ++#define MCF_SSI_TCR_TFEN0 (0x00000080) ++#define MCF_SSI_TCR_TFEN1 (0x00000100) ++#define MCF_SSI_TCR_TXBIT0 (0x00000200) ++ ++/* Bit definitions and macros for RCR */ ++#define MCF_SSI_RCR_REFS (0x00000001) ++#define MCF_SSI_RCR_RFSL (0x00000002) ++#define MCF_SSI_RCR_RFSI (0x00000004) ++#define MCF_SSI_RCR_RSCKP (0x00000008) ++#define MCF_SSI_RCR_RSHFD (0x00000010) ++#define MCF_SSI_RCR_RFEN0 (0x00000080) ++#define MCF_SSI_RCR_RFEN1 (0x00000100) ++#define MCF_SSI_RCR_RXBIT0 (0x00000200) ++#define MCF_SSI_RCR_RXEXT (0x00000400) ++ ++/* Bit definitions and macros for CCR */ ++#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)) ++#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8) ++#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13) ++#define MCF_SSI_CCR_PSR (0x00020000) ++#define MCF_SSI_CCR_DIV2 (0x00040000) ++ ++/* Bit definitions and macros for FCSR */ ++#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)) ++#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) ++#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) ++#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) ++#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) ++#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) ++#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) ++#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for ACR */ ++#define MCF_SSI_ACR_AC97EN (0x00000001) ++#define MCF_SSI_ACR_FV (0x00000002) ++#define MCF_SSI_ACR_TIF (0x00000004) ++#define MCF_SSI_ACR_RD (0x00000008) ++#define MCF_SSI_ACR_WR (0x00000010) ++#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) ++ ++/* Bit definitions and macros for ACADD */ ++#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)) ++ ++/* Bit definitions and macros for ACDAT */ ++#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)) ++ ++/* Bit definitions and macros for ATAG */ ++#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for TMASK */ ++#define MCF_SSI_TMASK_SSI_TMASK(x) (x) ++ ++/* Bit definitions and macros for RMASK */ ++#define MCF_SSI_RMASK_SSI_RMASK(x) (x) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5445X_SSI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5445x_xbs.h +@@ -0,0 +1,81 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5445X_XBS_H__ ++#define __MCF5445X_XBS_H__ ++ ++/* ++ * Crossbar Switch (XBS) ++ */ ++ ++/* Register read/write macros */ ++#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */ ++#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */ ++#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */ ++#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */ ++#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */ ++#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */ ++#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */ ++#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */ ++#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */ ++#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */ ++#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */ ++#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */ ++#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */ ++#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */ ++ ++/* Priorities */ ++#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */ ++#define MCF_XBS_PRI_2 1 /* Level 2 */ ++#define MCF_XBS_PRI_3 2 /* Level 3 */ ++#define MCF_XBS_PRI_4 3 /* Level 4 */ ++#define MCF_XBS_PRI_5 4 /* Level 5 */ ++#define MCF_XBS_PRI_6 5 /* Level 6 */ ++#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */ ++#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */ ++ ++/* Priority Register (PRSn) Defs */ ++#define MCF_XBS_PRS_MACRO(m, p) ((p)<<((m)<<2)) ++#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */ ++#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */ ++#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */ ++#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */ ++#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */ ++#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */ ++#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */ ++#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */ ++ ++/* Control Register (CRSn) Defs */ ++#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */ ++#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */ ++#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */ ++#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */ ++ ++/* MCF_XBS_CRS_ARB Defs */ ++#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */ ++#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */ ++ ++/* MCF_XBS_CRS_PCTL Defs */ ++#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */ ++#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */ ++#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */ ++ ++/* MCF_XBS_CRS_PARK Defs */ ++#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */ ++#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */ ++#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */ ++#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */ ++#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */ ++#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */ ++#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */ ++#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */ ++ ++#endif /* __MCF5445X_XBS_H__ */ diff --git a/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch b/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch new file mode 100644 index 000000000..08bc86fc4 --- /dev/null +++ b/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch @@ -0,0 +1,7673 @@ +From b19b66d24fe96f4f79753762048328fe985351a6 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:38 +0800 +Subject: [PATCH 03/52] MCF547x and MCF548x support in Linux 2.6.38 + +MCF547x and MCF548x support in Linux 2.6.38. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m547x/Makefile | 7 + + arch/m68k/coldfire/m547x/config.c | 412 ++++++++ + arch/m68k/coldfire/m547x/devices.c | 176 +++ + arch/m68k/coldfire/m547x/mcf548x-devices.c | 126 +++ + arch/m68k/configs/m5474lite_defconfig | 1269 ++++++++++++++++++++++ + arch/m68k/configs/m5475evb_defconfig | 1324 +++++++++++++++++++++++ + arch/m68k/configs/m5485evb_defconfig | 1582 ++++++++++++++++++++++++++++ + arch/m68k/include/asm/cf_548x_cacheflush.h | 262 +++++ + arch/m68k/include/asm/m5485dma.h | 98 ++ + arch/m68k/include/asm/m5485dspi.h | 146 +++ + arch/m68k/include/asm/m5485gpio.h | 695 ++++++++++++ + arch/m68k/include/asm/m5485gpt.h | 90 ++ + arch/m68k/include/asm/m5485pci.h | 380 +++++++ + arch/m68k/include/asm/m5485psc.h | 475 +++++++++ + arch/m68k/include/asm/m5485sec.h | 177 ++++ + arch/m68k/include/asm/m5485sim.h | 346 ++++++ + arch/m68k/include/asm/m5485sram.h | 12 + + 17 files changed, 7577 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m547x/Makefile + create mode 100644 arch/m68k/coldfire/m547x/config.c + create mode 100644 arch/m68k/coldfire/m547x/devices.c + create mode 100644 arch/m68k/coldfire/m547x/mcf548x-devices.c + create mode 100644 arch/m68k/configs/m5474lite_defconfig + create mode 100644 arch/m68k/configs/m5475evb_defconfig + create mode 100644 arch/m68k/configs/m5485evb_defconfig + create mode 100644 arch/m68k/include/asm/cf_548x_cacheflush.h + create mode 100644 arch/m68k/include/asm/m5485dma.h + create mode 100644 arch/m68k/include/asm/m5485dspi.h + create mode 100644 arch/m68k/include/asm/m5485gpio.h + create mode 100644 arch/m68k/include/asm/m5485gpt.h + create mode 100644 arch/m68k/include/asm/m5485pci.h + create mode 100644 arch/m68k/include/asm/m5485psc.h + create mode 100644 arch/m68k/include/asm/m5485sec.h + create mode 100644 arch/m68k/include/asm/m5485sim.h + create mode 100644 arch/m68k/include/asm/m5485sram.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/Makefile +@@ -0,0 +1,7 @@ ++# ++# Makefile for Linux arch/m68k/coldfire/m547x source directory ++# ++ ++obj-$(CONFIG_M547X_8X) += config.o mcf548x-devices.o devices.o ++obj-$(CONFIG_PCI) += pci.o pci_dummy.o ++obj-$(CONFIG_MCD_DMA) += dma.o +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/config.c +@@ -0,0 +1,412 @@ ++/* ++ * linux/arch/m68k/coldfire/config.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan kmahan@freescale.com ++ * Matt Waddel Matt.Waddel@freescale.com ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/string.h> ++#include <linux/kernel.h> ++#include <linux/console.h> ++#include <linux/bootmem.h> ++#include <linux/mm.h> ++#include <linux/clockchips.h> ++#include <asm/bootinfo.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/cfcache.h> ++#include <asm/cacheflush.h> ++#include <linux/io.h> ++#include <asm/cfmmu.h> ++#include <asm/setup.h> ++#include <asm/irq.h> ++#include <asm/traps.h> ++#include <asm/movs.h> ++#include <asm/movs.h> ++#include <asm/page.h> ++#include <asm/pgalloc.h> ++ ++#include <asm/mcfsim.h> ++ ++#define UBOOT_PCI ++#include <asm/bootinfo.h> ++#include <asm/m5485gpt.h> ++ ++extern int get_irq_list(struct seq_file *p, void *v); ++extern char _text, _end; ++extern char _etext, _edata, __init_begin, __init_end; ++extern struct console mcfrs_console; ++extern char m68k_command_line[CL_SIZE]; ++extern unsigned long availmem; ++extern struct mem_info m68k_ramdisk; ++ ++static int irq_enable[NR_IRQS]; ++unsigned long num_pages; ++ ++/* cf dma physical addresses */ ++unsigned long cf_dma_base; ++EXPORT_SYMBOL(cf_dma_base); ++unsigned long cf_dma_end; ++EXPORT_SYMBOL(cf_dma_end); ++unsigned long cf_dma_size; ++EXPORT_SYMBOL(cf_dma_size); ++ ++/* ethernet mac addresses from uboot */ ++unsigned char uboot_enet0[6]; ++unsigned char uboot_enet1[6]; ++ ++void coldfire_sort_memrec(void) ++{ ++ int i, j; ++ ++ /* Sort the m68k_memory records by address */ ++ for (i = 0; i < m68k_num_memory; ++i) { ++ for (j = i + 1; j < m68k_num_memory; ++j) { ++ if (m68k_memory[i].addr > m68k_memory[j].addr) { ++ struct mem_info tmp; ++ tmp = m68k_memory[i]; ++ m68k_memory[i] = m68k_memory[j]; ++ m68k_memory[j] = tmp; ++ } ++ } ++ } ++ /* Trim off discontiguous bits */ ++ for (i = 1; i < m68k_num_memory; ++i) { ++ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) != ++ m68k_memory[i].addr) { ++ printk(KERN_DEBUG "m68k_parse_bootinfo: " ++ "addr gap between 0x%lx & 0x%lx\n", ++ m68k_memory[i-1].addr+m68k_memory[i-1].size, ++ m68k_memory[i].addr); ++ m68k_num_memory = i; ++ break; ++ } ++ } ++} ++ ++/* ++ * UBoot Handler ++ */ ++int __init uboot_commandline(char *bootargs) ++{ ++ int len = 0, cmd_line_len; ++ static struct uboot_record uboot_info; ++ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; ++ ++ extern unsigned long uboot_info_stk; ++ ++ /* validate address */ ++ if ((uboot_info_stk < PAGE_OFFSET_RAW) || ++ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE))) ++ return 0; ++ ++ /* Add offset to get post-remapped kernel memory location */ ++ uboot_info.bdi = (struct bd_info *)((*(u32 *)(uboot_info_stk)) ++ + offset); ++ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset; ++ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset; ++ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset; ++ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset; ++ ++#if defined(CONFIG_BLK_DEV_INITRD) ++ m68k_ramdisk.addr = uboot_info.initrd_start; ++ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ? ++ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0; ++#endif ++ ++ /* copy over mac addresses */ ++ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6); ++ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6); ++ ++ /* copy command line */ ++ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start; ++ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1)) ++ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\ ++ cmd_line_len); ++ ++ return len; ++} ++ ++/* ++ * This routine does things not done in the bootloader. ++ */ ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ \ ++ ip=172.27.155.75:172.27.155.1" ++ ++asmlinkage void __init cf_early_init(void) ++{ ++ SET_VBR((void *)MCF_RAMBAR0); ++ ++ /* Mask all interrupts */ ++ MCF_IMRL = 0xFFFFFFFF; ++ MCF_IMRH = 0xFFFFFFFF; ++ ++ m68k_machtype = MACH_CFMMU; ++ m68k_fputype = FPU_CFV4E; ++ m68k_mmutype = MMU_CFV4E; ++ m68k_cputype = CPU_CFV4E; ++ ++ m68k_num_memory = 0; ++ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; ++ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE; ++ ++ if (!uboot_commandline(m68k_command_line)) { ++#if defined(CONFIG_BOOTPARAM) ++ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1); ++#else ++ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); ++#endif ++ } ++ ++ /* Invalidate caches via CACR */ ++ flush_bcache(); ++ cacr_set(CACHE_DISABLE_MODE); ++ ++ /* Turn on caches via CACR, enable EUSP */ ++ cacr_set(CACHE_INITIAL_MODE); ++} ++ ++/* Assembler routines */ ++asmlinkage void buserr(void); ++asmlinkage void trap(void); ++asmlinkage void system_call(void); ++asmlinkage void inthandler(void); ++ ++void __init coldfire_trap_init(void) ++{ ++ int i = 0; ++ e_vector *vectors; ++ ++ vectors = (e_vector *)MCF_RAMBAR0; ++ /* ++ * There is a common trap handler and common interrupt ++ * handler that handle almost every vector. We treat ++ * the system call and bus error special, they get their ++ * own first level handlers. ++ */ ++ for (i = 3; (i <= 23); i++) ++ vectors[i] = trap; ++ for (i = 33; (i <= 63); i++) ++ vectors[i] = trap; ++ for (i = 24; (i <= 31); i++) ++ vectors[i] = inthandler; ++ for (i = 64; (i < 255); i++) ++ vectors[i] = inthandler; ++ ++ vectors[255] = 0; ++ vectors[2] = buserr; ++ vectors[32] = system_call; ++} ++ ++void coldfire_tick(void) ++{ ++ /* Reset the ColdFire timer */ ++ MCF_SSR(0) = MCF_SSR_ST; ++} ++ ++void __init coldfire_sched_init(irq_handler_t handler) ++{ ++ int irq = ISC_SLTn(0); ++ ++ MCF_SCR(0) = 0; ++ MCF_ICR(irq) = ILP_SLT0; ++ request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL); ++ MCF_SLTCNT(0) = MCF_BUSCLK / HZ; ++ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN; ++} ++ ++unsigned long coldfire_gettimeoffset(void) ++{ ++ volatile unsigned long trr, tcn, offset; ++ trr = MCF_SLTCNT(0); ++ tcn = MCF_SCNT(0); ++ ++ offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3); ++ if (MCF_SSR(0) & MCF_SSR_ST) ++ offset += 1000000 / HZ; ++ ++ return offset; ++} ++ ++static unsigned long long sched_dtim_clk_val; ++ ++unsigned long long sched_clock(void) ++{ ++ unsigned long flags; ++ unsigned long long cycles; ++ volatile unsigned long trr, tcn, offset; ++ ++ local_irq_save(flags); ++ trr = MCF_SLTCNT(0); ++ tcn = MCF_SCNT(0); ++ offset = (trr - tcn); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + offset; ++} ++ ++unsigned long long sys_dtim2_read(void) ++{ ++ unsigned long flags; ++ unsigned long long cycles; ++ volatile unsigned long trr, tcn, offset; ++ ++ local_irq_save(flags); ++ trr = MCF_SLTCNT(0); ++ tcn = MCF_SCNT(0); ++ offset = (trr - tcn); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + offset; ++} ++ ++static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev) ++{ ++ struct clock_event_device *evt = ++ (struct clock_event_device *)dev; ++ ++ MCF_SSR(0) = MCF_SSR_ST; ++ sched_dtim_clk_val += (MCF_BUSCLK) / HZ; ++ evt->event_handler(evt); ++ return IRQ_HANDLED; ++} ++ ++void sys_dtim2_init(struct clock_event_device *evt) ++{ ++ int irq = ISC_SLTn(0); ++ ++ sched_dtim_clk_val = 0; ++ MCF_SCR(0) = 0; ++ MCF_ICR(irq) = ILP_SLT0; ++ request_irq(64 + irq, coldfire_dtim_clk_irq, IRQF_DISABLED, ++ "ColdFire Timer 0", (void *)evt); ++ MCF_SLTCNT(0) = MCF_BUSCLK / HZ; ++ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN; ++} ++ ++void coldfire_reboot(void) ++{ ++ /* disable interrupts and enable the watchdog */ ++ printk(KERN_INFO "Rebooting\n"); ++ ++ /*Disable the XLB priority settings, then set the core to same priority ++ * level as other XLB masters, also disable the PCI here, otherwise the ++ * watchdog may fail to reset. ++ */ ++ MCF_XARB_PRIEN = 0; ++ MCF_SPCR &= ~0x02; ++ asm("tpf"); ++ asm("movew #0x2700, %sr\n"); ++ MCF_GPT_GMS0 = MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4); ++ MCF_GPT_GCIR0 = (0x0A << 16) | 0x03; ++} ++ ++static void coldfire_get_model(char *model) ++{ ++ sprintf(model, "Version 4 ColdFire"); ++} ++ ++static void __init ++coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end) ++{ ++ unsigned long base_pfn; ++ ++ /* compute total pages in system */ ++ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT; ++ ++ /* align start/end to page boundries */ ++ memory_start = PAGE_ALIGN(memory_start); ++ memory_end = memory_end & PAGE_MASK; ++ ++ /* page numbers */ ++ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT; ++ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT; ++ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT; ++ ++ high_memory = (void *)memory_end; ++ availmem = memory_start; ++ ++ /* setup bootmem data */ ++ m68k_setup_node(0); ++ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn, ++ base_pfn, max_low_pfn); ++ availmem = PAGE_ALIGN(availmem); ++ ++ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n", ++ availmem, __pa(availmem)); ++ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n", ++ memory_start, memory_end); ++ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n", ++ base_pfn, min_low_pfn, max_low_pfn); ++ ++ /* turn over physram */ ++ free_bootmem(__pa(availmem), memory_end - (availmem)); ++ ++ /* configure physical dma area */ ++ cf_dma_base = __pa(PAGE_ALIGN(memory_start)); ++ cf_dma_size = CONFIG_DMA_SIZE; ++ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1; ++ ++ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n", ++ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE); ++ ++ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n", ++ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS)); ++} ++ ++void __init config_coldfire(void) ++{ ++ unsigned long endmem, startmem; ++ int i; ++ ++ /* ++ * Calculate endmem from m68k_memory, assume all are contiguous ++ */ ++ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK); ++ endmem = PAGE_OFFSET; ++ for (i = 0; i < m68k_num_memory; ++i) ++ endmem += m68k_memory[i].size; ++ ++ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \ ++ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20); ++ ++ memset(irq_enable, 0, sizeof(irq_enable)); ++ ++ /* ++ * Setup coldfire mach-specific handlers ++ */ ++ mach_max_dma_address = 0xffffffff; ++ mach_sched_init = coldfire_sched_init; ++ mach_tick = coldfire_tick; ++ mach_gettimeoffset = coldfire_gettimeoffset; ++ mach_reset = coldfire_reboot; ++ mach_get_model = coldfire_get_model; ++ ++ coldfire_bootmem_alloc(startmem, endmem-1); ++ ++#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE) ++ conswitchp = &dummy_con; ++#endif ++ ++#if defined(CONFIG_SERIAL_COLDFIRE) ++ /* ++ * This causes trouble when it is re-registered later. ++ * Currently this is fixed by conditionally commenting ++ * out the register_console in mcf_serial.c ++ */ ++ register_console(&mcfrs_console); ++#endif ++} +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/devices.c +@@ -0,0 +1,176 @@ ++/* ++ * arch/m68k/coldfire/m547x/devices.c ++ * ++ * Coldfire M547x/M548x Platform Device Configuration ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/spi/spi.h> ++#include <linux/i2c.h> ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfqspi.h> ++ ++ ++#ifdef CONFIG_SPI ++/* ++ * ++ * DSPI ++ * ++ */ ++ ++/* number of supported SPI selects */ ++#define SPI_NUM_CHIPSELECTS 8 ++ ++void coldfire_spi_cs_control(u8 cs, u8 command) ++{ ++ /* nothing special required */ ++} ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++static struct coldfire_spi_chip spidev_chip_info = { ++ .bits_per_word = 8, ++}; ++#endif ++ ++static struct spi_board_info spi_board_info[] = { ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */ ++ .bus_num = 1, ++ .chip_select = 0, /* CS0 */ ++ .controller_data = &spidev_chip_info, ++ } ++#endif ++}; ++ ++static int spi_irq_list[] = { ++ /* IRQ, ICR Offset, ICR Val,Mask */ ++ 64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0, ++ 64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0, ++ 64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0, ++ 64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0, ++ 64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0, ++ 64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0, ++ 64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0, ++ 0, 0, 0, 0, ++}; ++ ++static struct coldfire_spi_master coldfire_master_info = { ++ .bus_num = 1, ++ .num_chipselect = SPI_NUM_CHIPSELECTS, ++ .irq_list = spi_irq_list, ++ .irq_source = 0, /* not used */ ++ .irq_vector = 0, /* not used */ ++ .irq_mask = 0, /* not used */ ++ .irq_lp = 0, /* not used */ ++ .par_val = 0, /* not used */ ++ .cs_control = coldfire_spi_cs_control, ++}; ++ ++static struct resource coldfire_spi_resources[] = { ++ [0] = { ++ .name = "spi-par", ++ .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */ ++ .end = MCF_MBAR + 0x00000a50, /* PAR_DSPI */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [1] = { ++ .name = "spi-module", ++ .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */ ++ .end = MCF_MBAR + 0x00008ab8, /* DSPI mem map end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [2] = { ++ .name = "spi-int-level", ++ .start = MCF_MBAR + 0x740, /* ICR start */ ++ .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [3] = { ++ .name = "spi-int-mask", ++ .start = MCF_MBAR + 0x70c, /* IMRL */ ++ .end = MCF_MBAR + 0x70c, /* IMRL */ ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct platform_device coldfire_spi = { ++ .name = "spi_coldfire", ++ .id = -1, ++ .resource = coldfire_spi_resources, ++ .num_resources = ARRAY_SIZE(coldfire_spi_resources), ++ .dev = { ++ .platform_data = &coldfire_master_info, ++ } ++}; ++ ++/** ++ * m547x_8x_spi_init - Initialize SPI ++ */ ++static int __init m547x_8x_spi_init(void) ++{ ++ int retval; ++ ++ /* initialize the DSPI PAR */ ++ MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 | ++ MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS | ++ MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS | ++ MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS | ++ MCF_GPIO_PAR_DSPI_PAR_SCK_SCK | ++ MCF_GPIO_PAR_DSPI_PAR_SIN_SIN | ++ MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT); ++ ++ /* register device */ ++ retval = platform_device_register(&coldfire_spi); ++ if (retval < 0) ++ goto out; ++ ++ /* register board info */ ++ if (ARRAY_SIZE(spi_board_info)) ++ retval = spi_register_board_info(spi_board_info, ++ ARRAY_SIZE(spi_board_info)); ++ ++out: ++ return retval; ++} ++#endif ++ ++#ifdef CONFIG_I2C_BOARDINFO ++static struct i2c_board_info mcf_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("rv5c387a", 0x32), ++ }, ++}; ++#endif ++ ++/** ++ * m547x_8x_init_devices - Initialize M547X_8X devices ++ * ++ * Returns 0 on success. ++ */ ++static int __init m547x_8x_init_devices(void) ++{ ++#ifdef CONFIG_SPI ++ m547x_8x_spi_init(); ++#endif ++#ifdef CONFIG_I2C_BOARDINFO ++ i2c_register_board_info(0, mcf_i2c_devices, ++ ARRAY_SIZE(mcf_i2c_devices)); ++#endif ++ ++ return 0; ++} ++arch_initcall(m547x_8x_init_devices); +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/mcf548x-devices.c +@@ -0,0 +1,126 @@ ++/* ++ * arch/m68k/coldfire/m547x/mcf548x-devices.c ++ * ++ * Coldfire M548x Platform Device Configuration ++ * ++ * Based on the Freescale MXC devices.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/mtd/physmap.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfuart.h> ++ ++static struct resource coldfire_i2c_resources[] = { ++ { /* I/O */ ++ .start = MCF_MBAR + 0x008F00, ++ .end = MCF_MBAR + 0x008F20, ++ .flags = IORESOURCE_MEM, ++ }, ++ { /* IRQ */ ++ .start = 40, ++ .end = 40, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_i2c_device = { ++ .name = "mcf-i2c", ++ .id = 0, /*bus number*/ ++ .num_resources = ARRAY_SIZE(coldfire_i2c_resources), ++ .resource = coldfire_i2c_resources, ++}; ++ ++static struct resource coldfire_sec_resources[] = { ++ [0] = { /* I/O */ ++ .start = MCF_MBAR + 0x00020000, ++ .end = MCF_MBAR + 0x00033000, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { /* IRQ */ ++ .start = ISC_SEC, ++ .end = ISC_SEC, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_sec_device = { ++ .name = "fsl-sec1", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(coldfire_sec_resources), ++ .resource = coldfire_sec_resources, ++}; ++ ++static int __init mcf5485_init_devices(void) ++{ ++ printk(KERN_INFO "MCF5485x INIT_DEVICES\n"); ++ ++ platform_device_register(&coldfire_i2c_device); ++ platform_device_register(&coldfire_sec_device); ++ return 0; ++} ++arch_initcall(mcf5485_init_devices); ++ ++static struct mcf_platform_uart m548x_uart_platform[] = { ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE1, ++ .irq = MCFINT_VECBASE + MCFINT_UART0, ++ }, ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE2, ++ .irq = MCFINT_VECBASE + MCFINT_UART1, ++ }, ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE3, ++ .irq = MCFINT_VECBASE + MCFINT_UART2, ++ }, ++ { ++ .mapbase = MCF_MBAR + MCFUART_BASE4, ++ .irq = MCFINT_VECBASE + MCFINT_UART3, ++ }, ++ { }, ++}; ++ ++static struct platform_device m548x_uart = { ++ .name = "mcfuart", ++ .id = 0, ++ .dev.platform_data = m548x_uart_platform, ++}; ++ ++static struct platform_device *m548x_devices[] __initdata = { ++ &m548x_uart, ++}; ++ ++void m548x_uarts_init(void) ++{ ++ const int nrlines = ARRAY_SIZE(m548x_uart_platform); ++ int line; ++ ++ /* Set GPIO port register to enable PSC(port) signals */ ++ for (line = 0; (line < nrlines); line++) { ++ MCF_PAR_PSCn(line) = (0 ++ | MCF_PAR_PSC_TXD ++ | MCF_PAR_PSC_RXD); ++ ++ MCF_ICR(m548x_uart_platform[line].irq - 64) = ILP_PSCn(line); ++ } ++} ++/***************************************************************************/ ++ ++static int __init init_BSP(void) ++{ ++ m548x_uarts_init(); ++ platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices)); ++ return 0; ++} ++ ++arch_initcall(init_BSP); +--- /dev/null ++++ b/arch/m68k/configs/m5474lite_defconfig +@@ -0,0 +1,1269 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:17:48 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++CONFIG_MCD_DMA=y ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++# CONFIG_HAVE_FSL_USB_DR is not set ++CONFIG_M547X_8X=y ++CONFIG_M547X=y ++# CONFIG_M548X is not set ++CONFIG_M5474LITE=y ++# CONFIG_M5475AFE is not set ++# CONFIG_M5475BFE is not set ++# CONFIG_M5475CFE is not set ++# CONFIG_M5475DFE is not set ++# CONFIG_M5475EFE is not set ++# CONFIG_M5475FFE is not set ++# CONFIG_M5484LITE is not set ++# CONFIG_M5485AFE is not set ++# CONFIG_M5485BFE is not set ++# CONFIG_M5485CFE is not set ++# CONFIG_M5485DFE is not set ++# CONFIG_M5485EFE is not set ++# CONFIG_M5485FFE is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=266000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x00000000 ++CONFIG_SDRAM_SIZE=0x04000000 ++CONFIG_NOR_FLASH_BASE=0xFF800000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x800000 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_DEV is not set ++CONFIG_CAN_FLEXCAN=y ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++CONFIG_MTD_CFI_STAA=y ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0xff800000 ++CONFIG_MTD_PHYSMAP_LEN=0x400000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++# CONFIG_BLK_DEV_IDECD is not set ++# CONFIG_BLK_DEV_IDETAPE is not set ++# CONFIG_IDE_TASK_IOCTL is not set ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_BLK_DEV_PLATFORM is not set ++ ++# ++# PCI IDE chipsets support ++# ++# CONFIG_BLK_DEV_GENERIC is not set ++# CONFIG_BLK_DEV_OPTI621 is not set ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++# CONFIG_BLK_DEV_AMD74XX is not set ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++# CONFIG_BLK_DEV_VIA82CXXX is not set ++# CONFIG_BLK_DEV_TC86C001 is not set ++# CONFIG_BLK_DEV_IDEDMA is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++# CONFIG_SATA_AHCI is not set ++CONFIG_SATA_SIL24=y ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_SATA_SIL=y ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MARVELL is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NINJA32 is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_NS87415 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++# CONFIG_PATA_SIL680 is not set ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++# CONFIG_PATA_SCH is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++CONFIG_BROADCOM5222_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++CONFIG_E100=y ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++CONFIG_NE2K_PCI=y ++# CONFIG_8139CP is not set ++CONFIG_8139TOO=y ++CONFIG_8139TOO_PIO=y ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++CONFIG_FEC_548x=y ++CONFIG_FEC_548x_ENABLE_FEC2=y ++CONFIG_FEC_548x_SHARED_PHY=y ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++CONFIG_E1000=y ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++# CONFIG_R8169 is not set ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_GEN_RTC is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_CHARDEV is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++# CONFIG_HID_SUPPORT is not set ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++# CONFIG_INOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/configs/m5475evb_defconfig +@@ -0,0 +1,1324 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 15:41:10 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++CONFIG_MCD_DMA=y ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++# CONFIG_HAVE_FSL_USB_DR is not set ++CONFIG_M547X_8X=y ++CONFIG_M547X=y ++# CONFIG_M548X is not set ++# CONFIG_M5474LITE is not set ++# CONFIG_M5475AFE is not set ++# CONFIG_M5475BFE is not set ++CONFIG_M5475CFE=y ++# CONFIG_M5475DFE is not set ++# CONFIG_M5475EFE is not set ++# CONFIG_M5475FFE is not set ++# CONFIG_M5484LITE is not set ++# CONFIG_M5485AFE is not set ++# CONFIG_M5485BFE is not set ++# CONFIG_M5485CFE is not set ++# CONFIG_M5485DFE is not set ++# CONFIG_M5485EFE is not set ++# CONFIG_M5485FFE is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=266000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x00000000 ++CONFIG_SDRAM_SIZE=0x04000000 ++CONFIG_NOR_FLASH_BASE=0xE0000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x800000 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_DEV is not set ++# CONFIG_CAN_FLEXCAN is not set ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++# CONFIG_MTD_CHAR is not set ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++CONFIG_MTD_JEDECPROBE=y ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0xe0000000 ++CONFIG_MTD_PHYSMAP_LEN=0x1000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++CONFIG_BROADCOM5222_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_NET_PCI is not set ++# CONFIG_B44 is not set ++CONFIG_FEC_548x=y ++CONFIG_FEC_548x_ENABLE_FEC2=y ++CONFIG_FEC_548x_SHARED_PHY=y ++# CONFIG_ATL2 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++# CONFIG_HID_SUPPORT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++CONFIG_USB_MON=y ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++CONFIG_RTC_DRV_RS5C372=y ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_MCF is not set ++# CONFIG_RTC_M5441X is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++# CONFIG_INOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/configs/m5485evb_defconfig +@@ -0,0 +1,1582 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Tue Aug 24 16:19:05 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++# CONFIG_NET_NS is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++CONFIG_MCD_DMA=y ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++CONFIG_PCI=y ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++# CONFIG_HAVE_FSL_USB_DR is not set ++CONFIG_M547X_8X=y ++# CONFIG_M547X is not set ++CONFIG_M548X=y ++# CONFIG_M5474LITE is not set ++# CONFIG_M5475AFE is not set ++# CONFIG_M5475BFE is not set ++# CONFIG_M5475CFE is not set ++# CONFIG_M5475DFE is not set ++# CONFIG_M5475EFE is not set ++# CONFIG_M5475FFE is not set ++# CONFIG_M5484LITE is not set ++# CONFIG_M5485AFE is not set ++# CONFIG_M5485BFE is not set ++CONFIG_M5485CFE=y ++# CONFIG_M5485DFE is not set ++# CONFIG_M5485EFE is not set ++# CONFIG_M5485FFE is not set ++# CONFIG_M5441X is not set ++CONFIG_MCFCLK=200000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x00000000 ++CONFIG_SDRAM_SIZE=0x04000000 ++CONFIG_NOR_FLASH_BASE=0xE0000000 ++CONFIG_DMA_BASE=0xef000000 ++CONFIG_DMA_SIZE=0x800000 ++CONFIG_VDSO=y ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++CONFIG_CAN_DEV=y ++CONFIG_CAN_CALC_BITTIMING=y ++CONFIG_CAN_FLEXCAN=y ++CONFIG_CAN_MCF=y ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=y ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++CONFIG_MTD_RAM=y ++CONFIG_MTD_ROM=y ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0xE0000000 ++CONFIG_MTD_PHYSMAP_LEN=0x1000000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++# CONFIG_BLK_DEV_IDECD is not set ++# CONFIG_BLK_DEV_IDETAPE is not set ++# CONFIG_IDE_TASK_IOCTL is not set ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_BLK_DEV_PLATFORM is not set ++ ++# ++# PCI IDE chipsets support ++# ++# CONFIG_BLK_DEV_GENERIC is not set ++# CONFIG_BLK_DEV_OPTI621 is not set ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++# CONFIG_BLK_DEV_AMD74XX is not set ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++# CONFIG_BLK_DEV_VIA82CXXX is not set ++# CONFIG_BLK_DEV_TC86C001 is not set ++# CONFIG_BLK_DEV_IDEDMA is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++# CONFIG_SATA_AHCI is not set ++CONFIG_SATA_SIL24=y ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_SATA_SIL=y ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MARVELL is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NINJA32 is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_NS87415 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++# CONFIG_PATA_SIL680 is not set ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++# CONFIG_PATA_SCH is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++CONFIG_BROADCOM5222_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_NATIONAL8364x_PHY is not set ++# CONFIG_NATIONAL8384x_PHY is not set ++# CONFIG_MicrelKSZ8041_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_HP100 is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++CONFIG_E100=y ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++CONFIG_NE2K_PCI=y ++CONFIG_8139CP=y ++CONFIG_8139TOO=y ++CONFIG_8139TOO_PIO=y ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++CONFIG_FEC_548x=y ++CONFIG_FEC_548x_ENABLE_FEC2=y ++CONFIG_FEC_548x_SHARED_PHY=y ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++CONFIG_E1000=y ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++CONFIG_R8169=y ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_MCF=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_ALIM7101_WDT is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++CONFIG_FB_DEFERRED_IO=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_SMI=y ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_VIA is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++CONFIG_FONTS=y ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_FONT_6x11=y ++# CONFIG_FONT_7x14 is not set ++CONFIG_FONT_PEARL_8x8=y ++CONFIG_FONT_ACORN_8x8=y ++CONFIG_FONT_MINI_4x6=y ++CONFIG_FONT_SUN8x16=y ++CONFIG_FONT_SUN12x22=y ++CONFIG_FONT_10x18=y ++CONFIG_LOGO=y ++CONFIG_LOGO_LINUX_MONO=y ++CONFIG_LOGO_LINUX_VGA16=y ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_NTRIG=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_GREENASIA_FF is not set ++CONFIG_HID_TOPSEED=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++CONFIG_USB_MON=y ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++CONFIG_RTC_DRV_RS5C372=y ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_MCF is not set ++# CONFIG_RTC_M5441X is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++# CONFIG_INOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++# CONFIG_CRYPTO_HW is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/include/asm/cf_548x_cacheflush.h +@@ -0,0 +1,262 @@ ++/* ++ * arch/m68k/include/asm/cf_548x_cacheflush.h - Coldfire 547x/548x Cache ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan kmahan@freescale.com ++ * Shrek Wu b16972@freescale.com ++ * ++ * Based on include/asm-m68k/cacheflush.h ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef M68K_CF_548x_CACHEFLUSH_H ++#define M68K_CF_548x_CACHEFLUSH_H ++ ++#include <asm/cfcache.h> ++/* ++ * Cache handling functions ++ */ ++ ++#define flush_icache() \ ++({ \ ++ unsigned long set; \ ++ unsigned long start_set; \ ++ unsigned long end_set; \ ++ \ ++ start_set = 0; \ ++ end_set = (unsigned long)LAST_DCACHE_ADDR; \ ++ \ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) {\ ++ asm volatile("cpushl %%ic,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%ic,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%ic,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \ ++ } \ ++}) ++ ++#define flush_dcache() \ ++({ \ ++ unsigned long set; \ ++ unsigned long start_set; \ ++ unsigned long end_set; \ ++ \ ++ start_set = 0; \ ++ end_set = (unsigned long)LAST_DCACHE_ADDR; \ ++ \ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ ++ asm volatile("cpushl %%dc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%dc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%dc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \ ++ } \ ++}) ++ ++#define flush_bcache() \ ++({ \ ++ unsigned long set; \ ++ unsigned long start_set; \ ++ unsigned long end_set; \ ++ \ ++ start_set = 0; \ ++ end_set = (unsigned long)LAST_DCACHE_ADDR; \ ++ \ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ ++ asm volatile("cpushl %%bc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%bc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%bc,(%0)\n" \ ++ "\taddq%.l #1,%0\n" \ ++ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \ ++ } \ ++}) ++ ++/* ++ * invalidate the cache for the specified memory range. ++ * It starts at the physical address specified for ++ * the given number of bytes. ++ */ ++extern void cache_clear(unsigned long paddr, int len); ++/* ++ * push any dirty cache in the specified memory range. ++ * It starts at the physical address specified for ++ * the given number of bytes. ++ */ ++extern void cache_push(unsigned long paddr, int len); ++ ++/* ++ * push and invalidate pages in the specified user virtual ++ * memory range. ++ */ ++extern void cache_push_v(unsigned long vaddr, int len); ++ ++/* This is needed whenever the virtual mapping of the current ++ process changes. */ ++ ++/** ++ * flush_cache_mm - Flush an mm_struct ++ * @mm: mm_struct to flush ++ */ ++static inline void flush_cache_mm(struct mm_struct *mm) ++{ ++ if (mm == current->mm) ++ flush_bcache(); ++} ++ ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) ++ ++#define flush_cache_all() flush_bcache() ++ ++/** ++ * flush_cache_range - Flush a cache range ++ * @vma: vma struct ++ * @start: Starting address ++ * @end: Ending address ++ * ++ * flush_cache_range must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_range(struct vm_area_struct *vma, ++ unsigned long start, unsigned long end) ++{ ++ if (vma->vm_mm == current->mm) ++ flush_bcache(); ++/*cf_cache_flush_range(start, end);*/ ++} ++ ++/** ++ * flush_cache_page - Flush a page of the cache ++ * @vma: vma struct ++ * @vmaddr: ++ * @pfn: page numer ++ * ++ * flush_cache_page must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_page(struct vm_area_struct *vma, ++ unsigned long vmaddr, unsigned long pfn) ++{ ++ if (vma->vm_mm == current->mm) ++ flush_bcache(); ++/*cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);*/ ++} ++ ++/* Push the page at kernel virtual address and clear the icache */ ++/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ ++#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page)) ++extern inline void __flush_page_to_ram(void *address) ++{ ++ unsigned long set; ++ unsigned long start_set; ++ unsigned long end_set; ++ unsigned long addr = (unsigned long) address; ++ ++ addr &= ~(PAGE_SIZE - 1); ++ /* round down to page start address */ ++ ++ start_set = addr & _ICACHE_SET_MASK; ++ end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK; ++ ++ if (start_set > end_set) { ++ /* from the begining to the lowest address */ ++ for (set = 0; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); ++ } ++ /* next loop will finish the cache ie pass the hole */ ++ end_set = LAST_ICACHE_ADDR; ++ } ++ ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); ++ } ++} ++ ++/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */ ++#define flush_dcache_page(page) \ ++ __flush_page_to_ram((void *) page_address(page)) ++#define flush_icache_page(vma, pg) \ ++ __flush_page_to_ram((void *) page_address(pg)) ++#define flush_icache_user_range(adr, len) \ ++ do { } while (0) ++/* NL */ ++#define flush_icache_user_page(vma, page, addr, len) \ ++ do { } while (0) ++ ++/* Push n pages at kernel virtual address and clear the icache */ ++/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ ++extern inline void flush_icache_range(unsigned long address, ++ unsigned long endaddr) ++{ ++ unsigned long set; ++ unsigned long start_set; ++ unsigned long end_set; ++ ++ start_set = address & _ICACHE_SET_MASK; ++ end_set = endaddr & _ICACHE_SET_MASK; ++ ++ if (start_set > end_set) { ++ /* from the begining to the lowest address */ ++ for (set = 0; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); ++ } ++ /* next loop will finish the cache ie pass the hole */ ++ end_set = LAST_ICACHE_ADDR; ++ } ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); ++ } ++} ++ ++static inline void copy_to_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++ flush_icache_user_page(vma, page, vaddr, len); ++} ++static inline void copy_from_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++} ++ ++#define flush_cache_vmap(start, end) flush_cache_all() ++#define flush_cache_vunmap(start, end) flush_cache_all() ++#define flush_dcache_mmap_lock(mapping) do { } while (0) ++#define flush_dcache_mmap_unlock(mapping) do { } while (0) ++ ++#endif /* M68K_CF_548x_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485dma.h +@@ -0,0 +1,98 @@ ++/* ++ * m5485dma.h -- ColdFire 547x/548x DMA controller support. ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef __MCF548X_DMA_H__ ++#define __MCF548X_DMA_H__ ++ ++ ++/* Register read/write macros */ ++#define MCF_DMA_DIPR MCF_REG32(0x008014) ++#define MCF_DMA_DIMR MCF_REG32(0x008018) ++#define MCF_DMA_IMCR MCF_REG32(0x00805C) ++ ++/* Bit definitions and macros for MCF_DMA_DIPR */ ++#define MCF_DMA_DIPR_TASK0 (0x00000001) ++#define MCF_DMA_DIPR_TASK1 (0x00000002) ++#define MCF_DMA_DIPR_TASK2 (0x00000004) ++#define MCF_DMA_DIPR_TASK3 (0x00000008) ++#define MCF_DMA_DIPR_TASK4 (0x00000010) ++#define MCF_DMA_DIPR_TASK5 (0x00000020) ++#define MCF_DMA_DIPR_TASK6 (0x00000040) ++#define MCF_DMA_DIPR_TASK7 (0x00000080) ++#define MCF_DMA_DIPR_TASK8 (0x00000100) ++#define MCF_DMA_DIPR_TASK9 (0x00000200) ++#define MCF_DMA_DIPR_TASK10 (0x00000400) ++#define MCF_DMA_DIPR_TASK11 (0x00000800) ++#define MCF_DMA_DIPR_TASK12 (0x00001000) ++#define MCF_DMA_DIPR_TASK13 (0x00002000) ++#define MCF_DMA_DIPR_TASK14 (0x00004000) ++#define MCF_DMA_DIPR_TASK15 (0x00008000) ++ ++/* Bit definitions and macros for MCF_DMA_DIMR */ ++#define MCF_DMA_DIMR_TASK0 (0x00000001) ++#define MCF_DMA_DIMR_TASK1 (0x00000002) ++#define MCF_DMA_DIMR_TASK2 (0x00000004) ++#define MCF_DMA_DIMR_TASK3 (0x00000008) ++#define MCF_DMA_DIMR_TASK4 (0x00000010) ++#define MCF_DMA_DIMR_TASK5 (0x00000020) ++#define MCF_DMA_DIMR_TASK6 (0x00000040) ++#define MCF_DMA_DIMR_TASK7 (0x00000080) ++#define MCF_DMA_DIMR_TASK8 (0x00000100) ++#define MCF_DMA_DIMR_TASK9 (0x00000200) ++#define MCF_DMA_DIMR_TASK10 (0x00000400) ++#define MCF_DMA_DIMR_TASK11 (0x00000800) ++#define MCF_DMA_DIMR_TASK12 (0x00001000) ++#define MCF_DMA_DIMR_TASK13 (0x00002000) ++#define MCF_DMA_DIMR_TASK14 (0x00004000) ++#define MCF_DMA_DIMR_TASK15 (0x00008000) ++ ++/* Bit definitions and macros for MCF_DMA_IMCR */ ++#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) ++#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) ++#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) ++#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) ++#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) ++#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) ++#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) ++#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) ++#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) ++#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) ++#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) ++#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) ++#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) ++#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) ++#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) ++#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) ++#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) ++#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) ++#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) ++#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) ++#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) ++#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) ++#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) ++#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) ++#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) ++#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) ++#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) ++#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) ++#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) ++#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) ++#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) ++#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) ++#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) ++#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) ++#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) ++#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) ++#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) ++#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) ++#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) ++#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) ++#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) ++#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) ++#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) ++#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) ++#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) ++#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) ++ ++#endif /* __MCF548X_DMA_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485dspi.h +@@ -0,0 +1,146 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * File: mcf548x_dspi.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes: ++ * ++ */ ++ ++#ifndef _M5485DSPI_H_ ++#define _M5485DSPI_H_ ++ ++/* ++ * ++ * DMA Serial Peripheral Interface (DSPI) ++ * ++ */ ++ ++/* Register read/write macros */ ++#define MCF_DSPI_DMCR MCF_REG32(0x008A00) ++#define MCF_DSPI_DTCR MCF_REG32(0x008A08) ++#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C) ++#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10) ++#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14) ++#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18) ++#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C) ++#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20) ++#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24) ++#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28) ++#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4)) ++#define MCF_DSPI_DSR MCF_REG32(0x008A2C) ++#define MCF_DSPI_DRSER MCF_REG32(0x008A30) ++#define MCF_DSPI_DTFR MCF_REG32(0x008A34) ++#define MCF_DSPI_DRFR MCF_REG32(0x008A38) ++#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C) ++#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40) ++#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44) ++#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48) ++#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4)) ++#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C) ++#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80) ++#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84) ++#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88) ++#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4)) ++ ++/* Bit definitions and macros for MCF_DSPI_DMCR */ ++#define MCF_DSPI_DMCR_HALT (0x00000001) ++#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) ++#define MCF_DSPI_DMCR_CRXF (0x00000400) ++#define MCF_DSPI_DMCR_CTXF (0x00000800) ++#define MCF_DSPI_DMCR_DRXF (0x00001000) ++#define MCF_DSPI_DMCR_DTXF (0x00002000) ++#define MCF_DSPI_DMCR_CSIS0 (0x00010000) ++#define MCF_DSPI_DMCR_CSIS2 (0x00040000) ++#define MCF_DSPI_DMCR_CSIS3 (0x00080000) ++#define MCF_DSPI_DMCR_CSIS5 (0x00200000) ++#define MCF_DSPI_DMCR_ROOE (0x01000000) ++#define MCF_DSPI_DMCR_PCSSE (0x02000000) ++#define MCF_DSPI_DMCR_MTFE (0x04000000) ++#define MCF_DSPI_DMCR_FRZ (0x08000000) ++#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) ++#define MCF_DSPI_DMCR_CSCK (0x40000000) ++#define MCF_DSPI_DMCR_MSTR (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DTCR */ ++#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_DSPI_DCTARn */ ++#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0) ++#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) ++#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) ++#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) ++#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) ++#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) ++#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) ++#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) ++#define MCF_DSPI_DCTAR_LSBFE (0x01000000) ++#define MCF_DSPI_DCTAR_CPHA (0x02000000) ++#define MCF_DSPI_DCTAR_CPOL (0x04000000) ++/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */ ++#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) ++#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) ++#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000) ++#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for MCF_DSPI_DSR */ ++#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) ++#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) ++#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) ++#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) ++#define MCF_DSPI_DSR_RFDF (0x00020000) ++#define MCF_DSPI_DSR_RFOF (0x00080000) ++#define MCF_DSPI_DSR_TFFF (0x02000000) ++#define MCF_DSPI_DSR_TFUF (0x08000000) ++#define MCF_DSPI_DSR_EOQF (0x10000000) ++#define MCF_DSPI_DSR_TXRXS (0x40000000) ++#define MCF_DSPI_DSR_TCF (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DRSER */ ++#define MCF_DSPI_DRSER_RFDFS (0x00010000) ++#define MCF_DSPI_DRSER_RFDFE (0x00020000) ++#define MCF_DSPI_DRSER_RFOFE (0x00080000) ++#define MCF_DSPI_DRSER_TFFFS (0x01000000) ++#define MCF_DSPI_DRSER_TFFFE (0x02000000) ++#define MCF_DSPI_DRSER_TFUFE (0x08000000) ++#define MCF_DSPI_DRSER_EOQFE (0x10000000) ++#define MCF_DSPI_DRSER_TCFE (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DTFR */ ++#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) ++#define MCF_DSPI_DTFR_CS0 (0x00010000) ++#define MCF_DSPI_DTFR_CS2 (0x00040000) ++#define MCF_DSPI_DTFR_CS3 (0x00080000) ++#define MCF_DSPI_DTFR_CS5 (0x00200000) ++#define MCF_DSPI_DTFR_CTCNT (0x04000000) ++#define MCF_DSPI_DTFR_EOQ (0x08000000) ++#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) ++#define MCF_DSPI_DTFR_CONT (0x80000000) ++ ++/* Bit definitions and macros for MCF_DSPI_DRFR */ ++#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_DSPI_DTFDRn */ ++#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) ++#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_DSPI_DRFDRn */ ++#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) ++ ++/********************************************************************/ ++ ++#endif /* _M5485DSPI_H_ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485gpio.h +@@ -0,0 +1,695 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * File: mcf548x_gpio.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes: ++ * ++ */ ++ ++#ifndef _M5485GPIO_H_ ++#define _M5485GPIO_H_ ++ ++/********************************************************************* ++* ++* General Purpose I/O (GPIO) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00) ++#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01) ++#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02) ++#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04) ++#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05) ++#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06) ++#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07) ++#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08) ++#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09) ++#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A) ++#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C) ++#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D) ++#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E) ++#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10) ++#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11) ++#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12) ++#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14) ++#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15) ++#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16) ++#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17) ++#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18) ++#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19) ++#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A) ++#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C) ++#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D) ++#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E) ++#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20) ++#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21) ++#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22) ++#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24) ++#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25) ++#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26) ++#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27) ++#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28) ++#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29) ++#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A) ++#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C) ++#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D) ++#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E) ++#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30) ++#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31) ++#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32) ++#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34) ++#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35) ++#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36) ++#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37) ++#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38) ++#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39) ++#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A) ++#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C) ++#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D) ++#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E) ++#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40) ++#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42) ++#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43) ++#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44) ++#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48) ++#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A) ++#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C) ++#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D) ++#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E) ++#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F) ++#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50) ++#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40) ++#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ ++#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10) ++#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ ++#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01) ++#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02) ++#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04) ++#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40) ++#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40) ++#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40) ++#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40) ++#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01) ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02) ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04) ++#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08) ++#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08) ++#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40) ++#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40) ++#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ ++#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20) ++#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40) ++#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10) ++#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ ++#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01) ++#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02) ++#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04) ++#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40) ++#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40) ++#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40) ++#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40) ++#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01) ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02) ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04) ++#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08) ++#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08) ++#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40) ++#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40) ++#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20) ++#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40) ++#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10) ++#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01) ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02) ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04) ++#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40) ++#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01) ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02) ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04) ++#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08) ++#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08) ++#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40) ++#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40) ++#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08) ++#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20) ++#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40) ++#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10) ++#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01) ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02) ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04) ++#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40) ++#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02) ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04) ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20) ++#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40) ++#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04) ++#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08) ++#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40) ++#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08) ++#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40) ++#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ ++#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01) ++#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02) ++#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04) ++#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ ++#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01) ++#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02) ++#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04) ++#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08) ++#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ ++#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01) ++#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02) ++#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04) ++#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08) ++#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40) ++#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40) ++#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80) ++ ++/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20) ++#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ ++#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) ++#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010) ++#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) ++#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) ++#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) ++#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) ++#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ ++#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) ++#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) ++#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) ++#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) ++#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ ++#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) ++#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) ++#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) ++#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) ++#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) ++#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) ++#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) ++#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ ++#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) ++#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) ++#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ ++#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) ++#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) ++#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ ++#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) ++#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ ++#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) ++#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) ++#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) ++#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) ++#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) ++#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) ++#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) ++#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) ++#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) ++#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) ++#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) ++ ++/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ ++#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) ++#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) ++#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) ++ ++/********************************************************************/ ++ ++#endif /* _M5485GPIO_H_ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485gpt.h +@@ -0,0 +1,90 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * File: mcf548x_gpt.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes: ++ * ++ */ ++ ++#ifndef __MCF548X_GPT_H__ ++#define __MCF548X_GPT_H__ ++ ++/********************************************************************* ++* ++* General Purpose Timers (GPT) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_GPT_GMS0 MCF_REG32(0x000800) ++#define MCF_GPT_GCIR0 MCF_REG32(0x000804) ++#define MCF_GPT_GPWM0 MCF_REG32(0x000808) ++#define MCF_GPT_GSR0 MCF_REG32(0x00080C) ++#define MCF_GPT_GMS1 MCF_REG32(0x000810) ++#define MCF_GPT_GCIR1 MCF_REG32(0x000814) ++#define MCF_GPT_GPWM1 MCF_REG32(0x000818) ++#define MCF_GPT_GSR1 MCF_REG32(0x00081C) ++#define MCF_GPT_GMS2 MCF_REG32(0x000820) ++#define MCF_GPT_GCIR2 MCF_REG32(0x000824) ++#define MCF_GPT_GPWM2 MCF_REG32(0x000828) ++#define MCF_GPT_GSR2 MCF_REG32(0x00082C) ++#define MCF_GPT_GMS3 MCF_REG32(0x000830) ++#define MCF_GPT_GCIR3 MCF_REG32(0x000834) ++#define MCF_GPT_GPWM3 MCF_REG32(0x000838) ++#define MCF_GPT_GSR3 MCF_REG32(0x00083C) ++#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010)) ++#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010)) ++#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010)) ++#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010)) ++ ++/* Bit definitions and macros for MCF_GPT_GMS */ ++#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) ++#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) ++#define MCF_GPT_GMS_IEN (0x00000100) ++#define MCF_GPT_GMS_OD (0x00000200) ++#define MCF_GPT_GMS_SC (0x00000400) ++#define MCF_GPT_GMS_CE (0x00001000) ++#define MCF_GPT_GMS_WDEN (0x00008000) ++#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) ++#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) ++#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) ++#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) ++#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) ++#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) ++#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) ++#define MCF_GPT_GMS_ICT_ANY (0x00000000) ++#define MCF_GPT_GMS_ICT_RISE (0x00010000) ++#define MCF_GPT_GMS_ICT_FALL (0x00020000) ++#define MCF_GPT_GMS_ICT_PULSE (0x00030000) ++#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) ++#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) ++#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) ++#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) ++#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) ++#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) ++#define MCF_GPT_GMS_TMS_PWM (0x00000003) ++#define MCF_GPT_GMS_TMS_GPIO (0x00000004) ++ ++/* Bit definitions and macros for MCF_GPT_GCIR */ ++#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) ++#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_GPT_GPWM */ ++#define MCF_GPT_GPWM_LOAD (0x00000001) ++#define MCF_GPT_GPWM_PWMOP (0x00000100) ++#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_GPT_GSR */ ++#define MCF_GPT_GSR_CAPT (0x00000001) ++#define MCF_GPT_GSR_COMP (0x00000002) ++#define MCF_GPT_GSR_PWMP (0x00000004) ++#define MCF_GPT_GSR_TEXP (0x00000008) ++#define MCF_GPT_GSR_PIN (0x00000100) ++#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) ++#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) ++ ++#define MCF_GPT_MAX_TIMEOUT 30 ++/********************************************************************/ ++ ++#endif /* __MCF548X_GPT_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485pci.h +@@ -0,0 +1,380 @@ ++/* ++ * m5485pci.h -- ColdFire 547x/548x PCI controller support. ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef __MCF548X_PCI_H__ ++#define __MCF548X_PCI_H__ ++ ++ ++/* PCI Type 0 Configuration Registers */ ++#define MCF_PCIIDR MCF_REG32(0x000B00) ++/* PCI Device ID/Vendor ID */ ++#define MCF_PCISCR MCF_REG32(0x000B04) ++/* PCI Status/Command */ ++#define MCF_PCICCRIR MCF_REG32(0x000B08) ++/* PCI Class Code / Revision ID */ ++#define MCF_PCICR1 MCF_REG32(0x000B0C) ++/* PCI Configuration 1 Register */ ++#define MCF_PCIBAR0 MCF_REG32(0x000B10) ++/* PCI Base Address Register 0 */ ++#define MCF_PCIBAR1 MCF_REG32(0x000B14) ++/* PCI Base Address Register 1 */ ++#define MCF_PCICCPR MCF_REG32(0x000B28) ++/* PCI Cardbus CIS Pointer */ ++#define MCF_PCISID MCF_REG32(0x000B2C) ++/* Subsystem ID/Subsystem Vendor ID*/ ++#define MCF_PCIERBAR MCF_REG32(0x000B30) ++/* PCI Expansion ROM */ ++#define MCF_PCICPR MCF_REG32(0x000B30) ++/* PCI Capabilities Pointer */ ++#define MCF_PCICR2 MCF_REG32(0x000B3C) ++/* PCI Configuration Register 2 */ ++ ++/* General Control/Status Registers */ ++#define MCF_PCIGSCR MCF_REG32(0x000B60) ++/* Global Status/Control Register */ ++#define MCF_PCITBATR0 MCF_REG32(0x000B64) ++/* Target Base Address Translation 0*/ ++#define MCF_PCITBATR1 MCF_REG32(0x000B68) ++/* Target Base Address Translation 1*/ ++#define MCF_PCITCR MCF_REG32(0x000B6C) ++/* Target Control Register */ ++#define MCF_PCIIW0BTAR MCF_REG32(0x000B70) ++/* Initiator Window 0 Base Address */ ++#define MCF_PCIIW1BTAR MCF_REG32(0x000B74) ++/* Initiator Window 1 Base Address */ ++#define MCF_PCIIW2BTAR MCF_REG32(0x000B78) ++/* Initiator Window 2 Base Address */ ++#define MCF_PCIIWCR MCF_REG32(0x000B80) ++/* Initiator Window Configuration */ ++#define MCF_PCIICR MCF_REG32(0x000B84) ++/* Initiator Control Register */ ++#define MCF_PCIISR MCF_REG32(0x000B88) ++/* Initiator Status Register */ ++#define MCF_PCICAR MCF_REG32(0x000BF8) ++/* Configuration Address Register */ ++ ++/* CommBus FIFO Transmit Interface Registers */ ++#define MCF_PCITPSR MCF_REG32(0x008400) ++/* Tx Packet Size Register */ ++#define MCF_PCITSAR MCF_REG32(0x008404) ++/* Tx Start Address Register */ ++#define MCF_PCITTCR MCF_REG32(0x008408) ++/* Tx Transaction Control Register */ ++#define MCF_PCITER MCF_REG32(0x00840C) ++/* Tx Enables Register */ ++#define MCF_PCITNAR MCF_REG32(0x008410) ++/* Tx Next Address Register */ ++#define MCF_PCITLWR MCF_REG32(0x008414) ++/* Tx Last Word Register */ ++#define MCF_PCITDCR MCF_REG32(0x008418) ++/* Tx Done Counts Register */ ++#define MCF_PCITSR MCF_REG32(0x00841C) ++/* Tx Status Register */ ++#define MCF_PCITFDR MCF_REG32(0x008440) ++/* Tx FIFO Data Register */ ++#define MCF_PCITFSR MCF_REG32(0x008444) ++/* Tx FIFO Status Register */ ++#define MCF_PCITFCR MCF_REG32(0x008448) ++/* Tx FIFO Control Register */ ++#define MCF_PCITFAR MCF_REG32(0x00844C) ++/* Tx FIFO Alarm Register */ ++#define MCF_PCITFRPR MCF_REG32(0x008450) ++/* Tx FIFO Read Pointer Register */ ++#define MCF_PCITFWPR MCF_REG32(0x008454) ++/* Tx FIFO Write Pointer Register */ ++ ++/* CommBus FIFO Receive Interface Registers */ ++#define MCF_PCIRPSR MCF_REG32(0x008480) ++/* Tx Packet Size Register */ ++#define MCF_PCIRSAR MCF_REG32(0x008484) ++/* Tx Start Address Register */ ++#define MCF_PCIRTCR MCF_REG32(0x008488) ++/* Tx Transaction Control Register */ ++#define MCF_PCIRER MCF_REG32(0x00848C) ++/* Tx Enables Register */ ++#define MCF_PCIRNAR MCF_REG32(0x008490) ++/* Tx Next Address Register */ ++#define MCF_PCIRDCR MCF_REG32(0x008498) ++/* Tx Done Counts Register */ ++#define MCF_PCIRSR MCF_REG32(0x00849C) ++/* Tx Status Register */ ++#define MCF_PCIRFDR MCF_REG32(0x0084C0) ++/* Tx FIFO Data Register */ ++#define MCF_PCIRFSR MCF_REG32(0x0084C4) ++/* Tx FIFO Status Register */ ++#define MCF_PCIRFCR MCF_REG32(0x0084C8) ++/* Tx FIFO Control Register */ ++#define MCF_PCIRFAR MCF_REG32(0x0084CC) ++/* Tx FIFO Alarm Register */ ++#define MCF_PCIRFRPR MCF_REG32(0x0084D0) ++/* Tx FIFO Read Pointer Register */ ++#define MCF_PCIRFWPR MCF_REG32(0x0084D4) ++/* Tx FIFO Write Pointer Register */ ++ ++/* PCI Arbiter Registers */ ++#define MCF_PCIARB_PACR MCF_REG32(0x000C00) ++#define MCF_PCIARB_PASR MCF_REG32(0x000C04) ++ ++ ++/* Bit definitions and macros for MCF_PCIIDR */ ++#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCISCR */ ++#define MCF_PCISCR_M (0x00000002) ++#define MCF_PCISCR_B (0x00000004) ++#define MCF_PCISCR_SP (0x00000008) ++#define MCF_PCISCR_MW (0x00000010) ++#define MCF_PCISCR_PER (0x00000040) ++#define MCF_PCISCR_S (0x00000100) ++#define MCF_PCISCR_F (0x00000200) ++#define MCF_PCISCR_C (0x00100000) ++#define MCF_PCISCR_66M (0x00200000) ++#define MCF_PCISCR_R (0x00400000) ++#define MCF_PCISCR_FC (0x00800000) ++#define MCF_PCISCR_DP (0x01000000) ++#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25) ++#define MCF_PCISCR_TS (0x08000000) ++#define MCF_PCISCR_TR (0x10000000) ++#define MCF_PCISCR_MA (0x20000000) ++#define MCF_PCISCR_SE (0x40000000) ++#define MCF_PCISCR_PE (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCICCRIR */ ++#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) ++#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) ++ ++/* Bit definitions and macros for MCF_PCICR1 */ ++#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) ++#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) ++#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) ++#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIBAR# */ ++#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18) ++#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30) ++ ++/* Bit definitions and macros for MCF_PCICR2 */ ++#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) ++#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) ++#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) ++#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIGSCR */ ++#define MCF_PCIGSCR_PR (0x00000001) ++#define MCF_PCIGSCR_SEE (0x00001000) ++#define MCF_PCIGSCR_PEE (0x00002000) ++#define MCF_PCIGSCR_SE (0x10000000) ++#define MCF_PCIGSCR_PE (0x20000000) ++ ++/* Bit definitions and macros for MCF_PCITBATR0 */ ++#define MCF_PCITBATR0_EN (0x00000001) ++#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) ++ ++/* Bit definitions and macros for MCF_PCITBATR1 */ ++#define MCF_PCITBATR1_EN (0x00000001) ++#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) ++ ++/* Bit definitions and macros for MCF_PCITCR */ ++#define MCF_PCITCR_P (0x00010000) ++#define MCF_PCITCR_LD (0x01000000) ++ ++/* Bit definitions and macros for MCF_PCIIW0BTAR */ ++#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) ++#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIIW1BTAR */ ++#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) ++#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIIW2BTAR */ ++#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) ++#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PCIIWCR */ ++#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) ++#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) ++#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) ++#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) ++#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) ++#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) ++#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000) ++#define MCF_PCIIWCR_WINCTRL0_E (0x01000000) ++#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) ++#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) ++#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) ++#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000) ++#define MCF_PCIIWCR_WINCTRL1_E (0x00010000) ++#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) ++#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) ++#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) ++#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900) ++#define MCF_PCIIWCR_WINCTRL2_E (0x00000100) ++ ++ ++/* Bit definitions and macros for MCF_PCIICR */ ++#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) ++#define MCF_PCIICR_TAE (0x01000000) ++#define MCF_PCIICR_IAE (0x02000000) ++#define MCF_PCIICR_REE (0x04000000) ++ ++/* Bit definitions and macros for MCF_PCIISR */ ++#define MCF_PCIISR_TA (0x01000000) ++#define MCF_PCIISR_IA (0x02000000) ++#define MCF_PCIISR_RE (0x04000000) ++ ++/* Bit definitions and macros for MCF_PCICAR */ ++#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) ++#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) ++#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) ++#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) ++#define MCF_PCICAR_E (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCITPSR */ ++#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCITTCR */ ++#define MCF_PCITTCR_DI (0x00000001) ++#define MCF_PCITTCR_W (0x00000010) ++#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) ++#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) ++#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) ++ ++/* Bit definitions and macros for MCF_PCITER */ ++#define MCF_PCITER_NE (0x00010000) ++#define MCF_PCITER_IAE (0x00020000) ++#define MCF_PCITER_TAE (0x00040000) ++#define MCF_PCITER_RE (0x00080000) ++#define MCF_PCITER_SE (0x00100000) ++#define MCF_PCITER_FEE (0x00200000) ++#define MCF_PCITER_ME (0x01000000) ++#define MCF_PCITER_BE (0x08000000) ++#define MCF_PCITER_CM (0x10000000) ++#define MCF_PCITER_RF (0x40000000) ++#define MCF_PCITER_RC (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCITDCR */ ++#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCITSR */ ++#define MCF_PCITSR_IA (0x00010000) ++#define MCF_PCITSR_TA (0x00020000) ++#define MCF_PCITSR_RE (0x00040000) ++#define MCF_PCITSR_SE (0x00080000) ++#define MCF_PCITSR_FE (0x00100000) ++#define MCF_PCITSR_BE1 (0x00200000) ++#define MCF_PCITSR_BE2 (0x00400000) ++#define MCF_PCITSR_BE3 (0x00800000) ++#define MCF_PCITSR_NT (0x01000000) ++ ++/* Bit definitions and macros for MCF_PCITFSR */ ++#define MCF_PCITFSR_EMT (0x00010000) ++#define MCF_PCITFSR_ALARM (0x00020000) ++#define MCF_PCITFSR_FU (0x00040000) ++#define MCF_PCITFSR_FR (0x00080000) ++#define MCF_PCITFSR_OF (0x00100000) ++#define MCF_PCITFSR_UF (0x00200000) ++#define MCF_PCITFSR_RXW (0x00400000) ++ ++/* Bit definitions and macros for MCF_PCITFCR */ ++#define MCF_PCITFCR_OF_MSK (0x00080000) ++#define MCF_PCITFCR_UF_MSK (0x00100000) ++#define MCF_PCITFCR_RXW_MSK (0x00200000) ++#define MCF_PCITFCR_FAE_MSK (0x00400000) ++#define MCF_PCITFCR_IP_MSK (0x00800000) ++#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24) ++ ++/* Bit definitions and macros for MCF_PCITFAR */ ++#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) ++ ++/* Bit definitions and macros for MCF_PCITFRPR */ ++#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) ++ ++/* Bit definitions and macros for MCF_PCITFWPR */ ++#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) ++ ++/* Bit definitions and macros for MCF_PCIRPSR */ ++#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCIRTCR */ ++#define MCF_PCIRTCR_DI (0x00000001) ++#define MCF_PCIRTCR_W (0x00000010) ++#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) ++#define MCF_PCIRTCR_FB (0x00001000) ++#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) ++#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) ++ ++/* Bit definitions and macros for MCF_PCIRER */ ++#define MCF_PCIRER_NE (0x00010000) ++#define MCF_PCIRER_IAE (0x00020000) ++#define MCF_PCIRER_TAE (0x00040000) ++#define MCF_PCIRER_RE (0x00080000) ++#define MCF_PCIRER_SE (0x00100000) ++#define MCF_PCIRER_FEE (0x00200000) ++#define MCF_PCIRER_ME (0x01000000) ++#define MCF_PCIRER_BE (0x08000000) ++#define MCF_PCIRER_CM (0x10000000) ++#define MCF_PCIRER_FE (0x20000000) ++#define MCF_PCIRER_RF (0x40000000) ++#define MCF_PCIRER_RC (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCIRDCR */ ++#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PCIRSR */ ++#define MCF_PCIRSR_IA (0x00010000) ++#define MCF_PCIRSR_TA (0x00020000) ++#define MCF_PCIRSR_RE (0x00040000) ++#define MCF_PCIRSR_SE (0x00080000) ++#define MCF_PCIRSR_FE (0x00100000) ++#define MCF_PCIRSR_BE1 (0x00200000) ++#define MCF_PCIRSR_BE2 (0x00400000) ++#define MCF_PCIRSR_BE3 (0x00800000) ++#define MCF_PCIRSR_NT (0x01000000) ++ ++/* Bit definitions and macros for MCF_PCIRFSR */ ++#define MCF_PCIRFSR_EMT (0x00010000) ++#define MCF_PCIRFSR_ALARM (0x00020000) ++#define MCF_PCIRFSR_FU (0x00040000) ++#define MCF_PCIRFSR_FR (0x00080000) ++#define MCF_PCIRFSR_OF (0x00100000) ++#define MCF_PCIRFSR_UF (0x00200000) ++#define MCF_PCIRFSR_RXW (0x00400000) ++ ++/* Bit definitions and macros for MCF_PCIRFCR */ ++#define MCF_PCIRFCR_OF_MSK (0x00080000) ++#define MCF_PCIRFCR_UF_MSK (0x00100000) ++#define MCF_PCIRFCR_RXW_MSK (0x00200000) ++#define MCF_PCIRFCR_FAE_MSK (0x00400000) ++#define MCF_PCIRFCR_IP_MSK (0x00800000) ++#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24) ++ ++/* Bit definitions and macros for MCF_PCIRFAR */ ++#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) ++ ++/* Bit definitions and macros for MCF_PCIRFRPR */ ++#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) ++ ++/* Bit definitions and macros for MCF_PCIRFWPR */ ++#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) ++ ++ ++/* Bit definitions and macros for MCF_PCIARB_PACR */ ++#define MCF_PCIARB_PACR_INTMPRI (0x00000001) ++#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) ++#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) ++#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) ++#define MCF_PCIARB_PACR_PKMD (0x40000000) ++#define MCF_PCIARB_PACR_DS (0x80000000) ++ ++/* Bit definitions and macros for MCF_PCIARB_PASR */ ++#define MCF_PCIARB_PASR_ITLMBK (0x00010000) ++#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) ++ ++#endif /* __MCF548X_PCI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485psc.h +@@ -0,0 +1,475 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * File: mcf548x_psc.h ++ * Purpose: Register and bit definitions for the MCF548X ++ * ++ * Notes ++ * ++ */ ++ ++#ifndef __MCF548X_PSC_H__ ++#define __MCF548X_PSC_H__ ++ ++/********************************************************************* ++* ++* Programmable Serial Controller (PSC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_PSC_MR0 MCF_REG08(0x008600) ++#define MCF_PSC_SR0 MCF_REG16(0x008604) ++#define MCF_PSC_CSR0 MCF_REG08(0x008604) ++#define MCF_PSC_CR0 MCF_REG08(0x008608) ++#define MCF_PSC_RB0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB_8BIT0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB_16BIT0 MCF_REG32(0x00860C) ++#define MCF_PSC_TB_AC970 MCF_REG32(0x00860C) ++#define MCF_PSC_IPCR0 MCF_REG08(0x008610) ++#define MCF_PSC_ACR0 MCF_REG08(0x008610) ++#define MCF_PSC_ISR0 MCF_REG16(0x008614) ++#define MCF_PSC_IMR0 MCF_REG16(0x008614) ++#define MCF_PSC_CTUR0 MCF_REG08(0x008618) ++#define MCF_PSC_CTLR0 MCF_REG08(0x00861C) ++#define MCF_PSC_IP0 MCF_REG08(0x008634) ++#define MCF_PSC_OPSET0 MCF_REG08(0x008638) ++#define MCF_PSC_OPRESET0 MCF_REG08(0x00863C) ++#define MCF_PSC_SICR0 MCF_REG08(0x008640) ++#define MCF_PSC_IRCR10 MCF_REG08(0x008644) ++#define MCF_PSC_IRCR20 MCF_REG08(0x008648) ++#define MCF_PSC_IRSDR0 MCF_REG08(0x00864C) ++#define MCF_PSC_IRMDR0 MCF_REG08(0x008650) ++#define MCF_PSC_IRFDR0 MCF_REG08(0x008654) ++#define MCF_PSC_RFCNT0 MCF_REG16(0x008658) ++#define MCF_PSC_TFCNT0 MCF_REG16(0x00865C) ++#define MCF_PSC_RFSR0 MCF_REG16(0x008664) ++#define MCF_PSC_TFSR0 MCF_REG16(0x008684) ++#define MCF_PSC_RFCR0 MCF_REG32(0x008668) ++#define MCF_PSC_TFCR0 MCF_REG32(0x008688) ++#define MCF_PSC_RFAR0 MCF_REG16(0x00866E) ++#define MCF_PSC_TFAR0 MCF_REG16(0x00868E) ++#define MCF_PSC_RFRP0 MCF_REG16(0x008672) ++#define MCF_PSC_TFRP0 MCF_REG16(0x008692) ++#define MCF_PSC_RFWP0 MCF_REG16(0x008676) ++#define MCF_PSC_TFWP0 MCF_REG16(0x008696) ++#define MCF_PSC_RLRFP0 MCF_REG16(0x00867A) ++#define MCF_PSC_TLRFP0 MCF_REG16(0x00869A) ++#define MCF_PSC_RLWFP0 MCF_REG16(0x00867E) ++#define MCF_PSC_TLWFP0 MCF_REG16(0x00869E) ++#define MCF_PSC_MR1 MCF_REG08(0x008700) ++#define MCF_PSC_SR1 MCF_REG16(0x008704) ++#define MCF_PSC_CSR1 MCF_REG08(0x008704) ++#define MCF_PSC_CR1 MCF_REG08(0x008708) ++#define MCF_PSC_RB1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB_8BIT1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB_16BIT1 MCF_REG32(0x00870C) ++#define MCF_PSC_TB_AC971 MCF_REG32(0x00870C) ++#define MCF_PSC_IPCR1 MCF_REG08(0x008710) ++#define MCF_PSC_ACR1 MCF_REG08(0x008710) ++#define MCF_PSC_ISR1 MCF_REG16(0x008714) ++#define MCF_PSC_IMR1 MCF_REG16(0x008714) ++#define MCF_PSC_CTUR1 MCF_REG08(0x008718) ++#define MCF_PSC_CTLR1 MCF_REG08(0x00871C) ++#define MCF_PSC_IP1 MCF_REG08(0x008734) ++#define MCF_PSC_OPSET1 MCF_REG08(0x008738) ++#define MCF_PSC_OPRESET1 MCF_REG08(0x00873C) ++#define MCF_PSC_SICR1 MCF_REG08(0x008740) ++#define MCF_PSC_IRCR11 MCF_REG08(0x008744) ++#define MCF_PSC_IRCR21 MCF_REG08(0x008748) ++#define MCF_PSC_IRSDR1 MCF_REG08(0x00874C) ++#define MCF_PSC_IRMDR1 MCF_REG08(0x008750) ++#define MCF_PSC_IRFDR1 MCF_REG08(0x008754) ++#define MCF_PSC_RFCNT1 MCF_REG16(0x008758) ++#define MCF_PSC_TFCNT1 MCF_REG16(0x00875C) ++#define MCF_PSC_RFSR1 MCF_REG16(0x008764) ++#define MCF_PSC_TFSR1 MCF_REG16(0x008784) ++#define MCF_PSC_RFCR1 MCF_REG32(0x008768) ++#define MCF_PSC_TFCR1 MCF_REG32(0x008788) ++#define MCF_PSC_RFAR1 MCF_REG16(0x00876E) ++#define MCF_PSC_TFAR1 MCF_REG16(0x00878E) ++#define MCF_PSC_RFRP1 MCF_REG16(0x008772) ++#define MCF_PSC_TFRP1 MCF_REG16(0x008792) ++#define MCF_PSC_RFWP1 MCF_REG16(0x008776) ++#define MCF_PSC_TFWP1 MCF_REG16(0x008796) ++#define MCF_PSC_RLRFP1 MCF_REG16(0x00877A) ++#define MCF_PSC_TLRFP1 MCF_REG16(0x00879A) ++#define MCF_PSC_RLWFP1 MCF_REG16(0x00877E) ++#define MCF_PSC_TLWFP1 MCF_REG16(0x00879E) ++#define MCF_PSC_MR2 MCF_REG08(0x008800) ++#define MCF_PSC_SR2 MCF_REG16(0x008804) ++#define MCF_PSC_CSR2 MCF_REG08(0x008804) ++#define MCF_PSC_CR2 MCF_REG08(0x008808) ++#define MCF_PSC_RB2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB_8BIT2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB_16BIT2 MCF_REG32(0x00880C) ++#define MCF_PSC_TB_AC972 MCF_REG32(0x00880C) ++#define MCF_PSC_IPCR2 MCF_REG08(0x008810) ++#define MCF_PSC_ACR2 MCF_REG08(0x008810) ++#define MCF_PSC_ISR2 MCF_REG16(0x008814) ++#define MCF_PSC_IMR2 MCF_REG16(0x008814) ++#define MCF_PSC_CTUR2 MCF_REG08(0x008818) ++#define MCF_PSC_CTLR2 MCF_REG08(0x00881C) ++#define MCF_PSC_IP2 MCF_REG08(0x008834) ++#define MCF_PSC_OPSET2 MCF_REG08(0x008838) ++#define MCF_PSC_OPRESET2 MCF_REG08(0x00883C) ++#define MCF_PSC_SICR2 MCF_REG08(0x008840) ++#define MCF_PSC_IRCR12 MCF_REG08(0x008844) ++#define MCF_PSC_IRCR22 MCF_REG08(0x008848) ++#define MCF_PSC_IRSDR2 MCF_REG08(0x00884C) ++#define MCF_PSC_IRMDR2 MCF_REG08(0x008850) ++#define MCF_PSC_IRFDR2 MCF_REG08(0x008854) ++#define MCF_PSC_RFCNT2 MCF_REG16(0x008858) ++#define MCF_PSC_TFCNT2 MCF_REG16(0x00885C) ++#define MCF_PSC_RFSR2 MCF_REG16(0x008864) ++#define MCF_PSC_TFSR2 MCF_REG16(0x008884) ++#define MCF_PSC_RFCR2 MCF_REG32(0x008868) ++#define MCF_PSC_TFCR2 MCF_REG32(0x008888) ++#define MCF_PSC_RFAR2 MCF_REG16(0x00886E) ++#define MCF_PSC_TFAR2 MCF_REG16(0x00888E) ++#define MCF_PSC_RFRP2 MCF_REG16(0x008872) ++#define MCF_PSC_TFRP2 MCF_REG16(0x008892) ++#define MCF_PSC_RFWP2 MCF_REG16(0x008876) ++#define MCF_PSC_TFWP2 MCF_REG16(0x008896) ++#define MCF_PSC_RLRFP2 MCF_REG16(0x00887A) ++#define MCF_PSC_TLRFP2 MCF_REG16(0x00889A) ++#define MCF_PSC_RLWFP2 MCF_REG16(0x00887E) ++#define MCF_PSC_TLWFP2 MCF_REG16(0x00889E) ++#define MCF_PSC_MR3 MCF_REG08(0x008900) ++#define MCF_PSC_SR3 MCF_REG16(0x008904) ++#define MCF_PSC_CSR3 MCF_REG08(0x008904) ++#define MCF_PSC_CR3 MCF_REG08(0x008908) ++#define MCF_PSC_RB3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB_8BIT3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB_16BIT3 MCF_REG32(0x00890C) ++#define MCF_PSC_TB_AC973 MCF_REG32(0x00890C) ++#define MCF_PSC_IPCR3 MCF_REG08(0x008910) ++#define MCF_PSC_ACR3 MCF_REG08(0x008910) ++#define MCF_PSC_ISR3 MCF_REG16(0x008914) ++#define MCF_PSC_IMR3 MCF_REG16(0x008914) ++#define MCF_PSC_CTUR3 MCF_REG08(0x008918) ++#define MCF_PSC_CTLR3 MCF_REG08(0x00891C) ++#define MCF_PSC_IP3 MCF_REG08(0x008934) ++#define MCF_PSC_OPSET3 MCF_REG08(0x008938) ++#define MCF_PSC_OPRESET3 MCF_REG08(0x00893C) ++#define MCF_PSC_SICR3 MCF_REG08(0x008940) ++#define MCF_PSC_IRCR13 MCF_REG08(0x008944) ++#define MCF_PSC_IRCR23 MCF_REG08(0x008948) ++#define MCF_PSC_IRSDR3 MCF_REG08(0x00894C) ++#define MCF_PSC_IRMDR3 MCF_REG08(0x008950) ++#define MCF_PSC_IRFDR3 MCF_REG08(0x008954) ++#define MCF_PSC_RFCNT3 MCF_REG16(0x008958) ++#define MCF_PSC_TFCNT3 MCF_REG16(0x00895C) ++#define MCF_PSC_RFSR3 MCF_REG16(0x008964) ++#define MCF_PSC_TFSR3 MCF_REG16(0x008984) ++#define MCF_PSC_RFCR3 MCF_REG32(0x008968) ++#define MCF_PSC_TFCR3 MCF_REG32(0x008988) ++#define MCF_PSC_RFAR3 MCF_REG16(0x00896E) ++#define MCF_PSC_TFAR3 MCF_REG16(0x00898E) ++#define MCF_PSC_RFRP3 MCF_REG16(0x008972) ++#define MCF_PSC_TFRP3 MCF_REG16(0x008992) ++#define MCF_PSC_RFWP3 MCF_REG16(0x008976) ++#define MCF_PSC_TFWP3 MCF_REG16(0x008996) ++#define MCF_PSC_RLRFP3 MCF_REG16(0x00897A) ++#define MCF_PSC_TLRFP3 MCF_REG16(0x00899A) ++#define MCF_PSC_RLWFP3 MCF_REG16(0x00897E) ++#define MCF_PSC_TLWFP3 MCF_REG16(0x00899E) ++#define MCF_PSC_MR(x) MCF_REG08(0x008600+((x)*0x100)) ++#define MCF_PSC_SR(x) MCF_REG16(0x008604+((x)*0x100)) ++#define MCF_PSC_CSR(x) MCF_REG08(0x008604+((x)*0x100)) ++#define MCF_PSC_CR(x) MCF_REG08(0x008608+((x)*0x100)) ++#define MCF_PSC_RB(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB_8BIT(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB_16BIT(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_TB_AC97(x) MCF_REG32(0x00860C+((x)*0x100)) ++#define MCF_PSC_IPCR(x) MCF_REG08(0x008610+((x)*0x100)) ++#define MCF_PSC_ACR(x) MCF_REG08(0x008610+((x)*0x100)) ++#define MCF_PSC_ISR(x) MCF_REG16(0x008614+((x)*0x100)) ++#define MCF_PSC_IMR(x) MCF_REG16(0x008614+((x)*0x100)) ++#define MCF_PSC_CTUR(x) MCF_REG08(0x008618+((x)*0x100)) ++#define MCF_PSC_CTLR(x) MCF_REG08(0x00861C+((x)*0x100)) ++#define MCF_PSC_IP(x) MCF_REG08(0x008634+((x)*0x100)) ++#define MCF_PSC_OPSET(x) MCF_REG08(0x008638+((x)*0x100)) ++#define MCF_PSC_OPRESET(x) MCF_REG08(0x00863C+((x)*0x100)) ++#define MCF_PSC_SICR(x) MCF_REG08(0x008640+((x)*0x100)) ++#define MCF_PSC_IRCR1(x) MCF_REG08(0x008644+((x)*0x100)) ++#define MCF_PSC_IRCR2(x) MCF_REG08(0x008648+((x)*0x100)) ++#define MCF_PSC_IRSDR(x) MCF_REG08(0x00864C+((x)*0x100)) ++#define MCF_PSC_IRMDR(x) MCF_REG08(0x008650+((x)*0x100)) ++#define MCF_PSC_IRFDR(x) MCF_REG08(0x008654+((x)*0x100)) ++#define MCF_PSC_RFCNT(x) MCF_REG16(0x008658+((x)*0x100)) ++#define MCF_PSC_TFCNT(x) MCF_REG16(0x00865C+((x)*0x100)) ++#define MCF_PSC_RFSR(x) MCF_REG16(0x008664+((x)*0x100)) ++#define MCF_PSC_TFSR(x) MCF_REG16(0x008684+((x)*0x100)) ++#define MCF_PSC_RFCR(x) MCF_REG32(0x008668+((x)*0x100)) ++#define MCF_PSC_TFCR(x) MCF_REG32(0x008688+((x)*0x100)) ++#define MCF_PSC_RFAR(x) MCF_REG16((0x00866E)+((x)*0x100)) ++#define MCF_PSC_TFAR(x) MCF_REG16((0x00868E)+((x)*0x100)) ++#define MCF_PSC_RFRP(x) MCF_REG16(0x008672+((x)*0x100)) ++#define MCF_PSC_TFRP(x) MCF_REG16(0x008692+((x)*0x100)) ++#define MCF_PSC_RFWP(x) MCF_REG16(0x008676+((x)*0x100)) ++#define MCF_PSC_TFWP(x) MCF_REG16(0x008696+((x)*0x100)) ++#define MCF_PSC_RLRFP(x) MCF_REG16(0x00867A+((x)*0x100)) ++#define MCF_PSC_TLRFP(x) MCF_REG16(0x00869A+((x)*0x100)) ++#define MCF_PSC_RLWFP(x) MCF_REG16(0x00867E+((x)*0x100)) ++#define MCF_PSC_TLWFP(x) MCF_REG16(0x00869E+((x)*0x100)) ++ ++/* Bit definitions and macros for MCF_PSC_MR */ ++#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) ++#define MCF_PSC_MR_PT (0x04) ++#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) ++#define MCF_PSC_MR_ERR (0x20) ++#define MCF_PSC_MR_RXIRQ (0x40) ++#define MCF_PSC_MR_RXRTS (0x80) ++#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) ++#define MCF_PSC_MR_TXCTS (0x10) ++#define MCF_PSC_MR_TXRTS (0x20) ++#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) ++#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) ++#define MCF_PSC_MR_PM_MULTI_DATA (0x18) ++#define MCF_PSC_MR_PM_NONE (0x10) ++#define MCF_PSC_MR_PM_FORCE_HI (0x0C) ++#define MCF_PSC_MR_PM_FORCE_LO (0x08) ++#define MCF_PSC_MR_PM_ODD (0x04) ++#define MCF_PSC_MR_PM_EVEN (0x00) ++#define MCF_PSC_MR_BC_5 (0x00) ++#define MCF_PSC_MR_BC_6 (0x01) ++#define MCF_PSC_MR_BC_7 (0x02) ++#define MCF_PSC_MR_BC_8 (0x03) ++#define MCF_PSC_MR_CM_NORMAL (0x00) ++#define MCF_PSC_MR_CM_ECHO (0x40) ++#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) ++#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) ++#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) ++#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) ++#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) ++ ++/* Bit definitions and macros for MCF_PSC_SR */ ++#define MCF_PSC_SR_ERR (0x0040) ++#define MCF_PSC_SR_CDE_DEOF (0x0080) ++#define MCF_PSC_SR_RXRDY (0x0100) ++#define MCF_PSC_SR_FU (0x0200) ++#define MCF_PSC_SR_TXRDY (0x0400) ++#define MCF_PSC_SR_TXEMP_URERR (0x0800) ++#define MCF_PSC_SR_OE (0x1000) ++#define MCF_PSC_SR_PE_CRCERR (0x2000) ++#define MCF_PSC_SR_FE_PHYERR (0x4000) ++#define MCF_PSC_SR_RB_NEOF (0x8000) ++ ++/* Bit definitions and macros for MCF_PSC_CSR */ ++#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) ++#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) ++#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) ++#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) ++#define MCF_PSC_CSR_RCSEL_CTM (0xF0) ++#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) ++#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) ++#define MCF_PSC_CSR_TCSEL_CTM (0x0F) ++ ++/* Bit definitions and macros for MCF_PSC_CR */ ++#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) ++#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) ++#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) ++#define MCF_PSC_CR_NONE (0x00) ++#define MCF_PSC_CR_STOP_BREAK (0x70) ++#define MCF_PSC_CR_START_BREAK (0x60) ++#define MCF_PSC_CR_BKCHGINT (0x50) ++#define MCF_PSC_CR_RESET_ERROR (0x40) ++#define MCF_PSC_CR_RESET_TX (0x30) ++#define MCF_PSC_CR_RESET_RX (0x20) ++#define MCF_PSC_CR_RESET_MR (0x10) ++#define MCF_PSC_CR_TX_DISABLED (0x08) ++#define MCF_PSC_CR_TX_ENABLED (0x04) ++#define MCF_PSC_CR_RX_DISABLED (0x02) ++#define MCF_PSC_CR_RX_ENABLED (0x01) ++ ++/* Bit definitions and macros for MCF_PSC_TB_8BIT */ ++#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) ++#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) ++#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) ++#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) ++ ++/* Bit definitions and macros for MCF_PSC_TB_16BIT */ ++#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_PSC_TB_AC97 */ ++#define MCF_PSC_TB_AC97_SOF (0x00000800) ++#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) ++ ++/* Bit definitions and macros for MCF_PSC_IPCR */ ++#define MCF_PSC_IPCR_RESERVED (0x0C) ++#define MCF_PSC_IPCR_CTS (0x0D) ++#define MCF_PSC_IPCR_D_CTS (0x1C) ++#define MCF_PSC_IPCR_SYNC (0x8C) ++ ++/* Bit definitions and macros for MCF_PSC_ACR */ ++#define MCF_PSC_ACR_IEC0 (0x01) ++#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) ++#define MCF_PSC_ACR_BRG (0x80) ++ ++/* Bit definitions and macros for MCF_PSC_ISR */ ++#define MCF_PSC_ISR_ERR (0x0040) ++#define MCF_PSC_ISR_DEOF (0x0080) ++#define MCF_PSC_ISR_TXRDY (0x0100) ++#define MCF_PSC_ISR_RXRDY_FU (0x0200) ++#define MCF_PSC_ISR_DB (0x0400) ++#define MCF_PSC_ISR_IPC (0x8000) ++ ++/* Bit definitions and macros for MCF_PSC_IMR */ ++#define MCF_PSC_IMR_ERR (0x0040) ++#define MCF_PSC_IMR_DEOF (0x0080) ++#define MCF_PSC_IMR_TXRDY (0x0100) ++#define MCF_PSC_IMR_RXRDY_FU (0x0200) ++#define MCF_PSC_IMR_DB (0x0400) ++#define MCF_PSC_IMR_IPC (0x8000) ++ ++/* Bit definitions and macros for MCF_PSC_IP */ ++#define MCF_PSC_IP_CTS (0x01) ++#define MCF_PSC_IP_TGL (0x40) ++#define MCF_PSC_IP_LWPR_B (0x80) ++ ++/* Bit definitions and macros for MCF_PSC_OPSET */ ++#define MCF_PSC_OPSET_RTS (0x01) ++ ++/* Bit definitions and macros for MCF_PSC_OPRESET */ ++#define MCF_PSC_OPRESET_RTS (0x01) ++ ++/* Bit definitions and macros for MCF_PSC_SICR */ ++#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) ++#define MCF_PSC_SICR_SHDIR (0x10) ++#define MCF_PSC_SICR_DTS (0x20) ++#define MCF_PSC_SICR_AWR (0x40) ++#define MCF_PSC_SICR_ACRB (0x80) ++#define MCF_PSC_SICR_SIM_UART (0x00) ++#define MCF_PSC_SICR_SIM_MODEM8 (0x01) ++#define MCF_PSC_SICR_SIM_MODEM16 (0x02) ++#define MCF_PSC_SICR_SIM_AC97 (0x03) ++#define MCF_PSC_SICR_SIM_SIR (0x04) ++#define MCF_PSC_SICR_SIM_MIR (0x05) ++#define MCF_PSC_SICR_SIM_FIR (0x06) ++ ++/* Bit definitions and macros for MCF_PSC_IRCR1 */ ++#define MCF_PSC_IRCR1_SPUL (0x01) ++#define MCF_PSC_IRCR1_SIPEN (0x02) ++#define MCF_PSC_IRCR1_FD (0x04) ++ ++/* Bit definitions and macros for MCF_PSC_IRCR2 */ ++#define MCF_PSC_IRCR2_NXTEOF (0x01) ++#define MCF_PSC_IRCR2_ABORT (0x02) ++#define MCF_PSC_IRCR2_SIPREQ (0x04) ++ ++/* Bit definitions and macros for MCF_PSC_IRMDR */ ++#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) ++#define MCF_PSC_IRMDR_FREQ (0x80) ++ ++/* Bit definitions and macros for MCF_PSC_IRFDR */ ++#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFCNT */ ++#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFCNT */ ++#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFSR */ ++#define MCF_PSC_RFSR_EMT (0x0001) ++#define MCF_PSC_RFSR_ALARM (0x0002) ++#define MCF_PSC_RFSR_FU (0x0004) ++#define MCF_PSC_RFSR_FRMRY (0x0008) ++#define MCF_PSC_RFSR_OF (0x0010) ++#define MCF_PSC_RFSR_UF (0x0020) ++#define MCF_PSC_RFSR_RXW (0x0040) ++#define MCF_PSC_RFSR_FAE (0x0080) ++#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) ++#define MCF_PSC_RFSR_TAG (0x1000) ++#define MCF_PSC_RFSR_TXW (0x4000) ++#define MCF_PSC_RFSR_IP (0x8000) ++#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) ++#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) ++#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) ++#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) ++ ++/* Bit definitions and macros for MCF_PSC_TFSR */ ++#define MCF_PSC_TFSR_EMT (0x0001) ++#define MCF_PSC_TFSR_ALARM (0x0002) ++#define MCF_PSC_TFSR_FU (0x0004) ++#define MCF_PSC_TFSR_FRMRY (0x0008) ++#define MCF_PSC_TFSR_OF (0x0010) ++#define MCF_PSC_TFSR_UF (0x0020) ++#define MCF_PSC_TFSR_RXW (0x0040) ++#define MCF_PSC_TFSR_FAE (0x0080) ++#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) ++#define MCF_PSC_TFSR_TAG (0x1000) ++#define MCF_PSC_TFSR_TXW (0x4000) ++#define MCF_PSC_TFSR_IP (0x8000) ++#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) ++#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) ++#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) ++#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) ++ ++/* Bit definitions and macros for MCF_PSC_RFCR */ ++#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PSC_RFCR_TXW_MSK (0x00040000) ++#define MCF_PSC_RFCR_OF_MSK (0x00080000) ++#define MCF_PSC_RFCR_UF_MSK (0x00100000) ++#define MCF_PSC_RFCR_RXW_MSK (0x00200000) ++#define MCF_PSC_RFCR_FAE_MSK (0x00400000) ++#define MCF_PSC_RFCR_IP_MSK (0x00800000) ++#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) ++#define MCF_PSC_RFCR_FRMEN (0x08000000) ++#define MCF_PSC_RFCR_TIMER (0x10000000) ++#define MCF_PSC_RFCR_WRITETAG (0x20000000) ++#define MCF_PSC_RFCR_SHADOW (0x80000000) ++ ++/* Bit definitions and macros for MCF_PSC_TFCR */ ++#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) ++#define MCF_PSC_TFCR_TXW_MSK (0x00040000) ++#define MCF_PSC_TFCR_OF_MSK (0x00080000) ++#define MCF_PSC_TFCR_UF_MSK (0x00100000) ++#define MCF_PSC_TFCR_RXW_MSK (0x00200000) ++#define MCF_PSC_TFCR_FAE_MSK (0x00400000) ++#define MCF_PSC_TFCR_IP_MSK (0x00800000) ++#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) ++#define MCF_PSC_TFCR_FRMEN (0x08000000) ++#define MCF_PSC_TFCR_TIMER (0x10000000) ++#define MCF_PSC_TFCR_WRITETAG (0x20000000) ++#define MCF_PSC_TFCR_SHADOW (0x80000000) ++ ++/* Bit definitions and macros for MCF_PSC_RFAR */ ++#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFAR */ ++#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFRP */ ++#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFRP */ ++#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RFWP */ ++#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TFWP */ ++#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RLRFP */ ++#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TLRFP */ ++#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_RLWFP */ ++#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/* Bit definitions and macros for MCF_PSC_TLWFP */ ++#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) ++ ++/********************************************************************/ ++ ++#endif /* __MCF548X_PSC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485sec.h +@@ -0,0 +1,177 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++ ++#ifndef M5485SEC_H ++#define M5484SEC_H ++ ++#define SEC_EUACR_U MCF_REG32(0x21000) ++#define SEC_EUACR_L MCF_REG32(0x21004) ++#define SEC_EUASR_U MCF_REG32(0x21028) ++#define SEC_EUASR_L MCF_REG32(0x2102C) ++#define SEC_SMCR MCF_REG32(0x21030) ++#define SEC_SISR_U MCF_REG32(0x21010) ++#define SEC_SISR_L MCF_REG32(0x21014) ++#define SEC_SICR_U MCF_REG32(0x21018) ++#define SEC_SICR_L MCF_REG32(0x2101C) ++#define SEC_SIMR_U MCF_REG32(0x21008) ++#define SEC_SIMR_L MCF_REG32(0x2100C) ++#define SEC_SID MCF_REG32(0x21020) ++ ++#define SEC_SMCR_RESET 0x01000000 ++#define SEC_SIMR_MASK_U 0x00000000 ++#define SEC_SIMR_MASK_L 0x03333340 ++ ++#define SEC_CC0_FR MCF_REG32(0x2204C) ++#define SEC_CC0_CR MCF_REG32(0x2200C) ++#define SEC_CC0_CDPR MCF_REG32(0x22044) ++#define SEC_CC0_PSR_U MCF_REG32(0x22010) ++#define SEC_CC0_PSR_L MCF_REG32(0x22014) ++#define SEC_CC1_FR MCF_REG32(0x2304C) ++#define SEC_CC1_CR MCF_REG32(0x2300C) ++#define SEC_CC1_CDPR MCF_REG32(0x23044) ++#define SEC_CC1_PSR_U MCF_REG32(0x23010) ++#define SEC_CC1_PSR_L MCF_REG32(0x23014) ++ ++#define SEC_CC_CR_RESET 0x00000001 ++#define SEC_CC_CR_CONFIGURATION 0x0000001E ++#define SEC_CC_PSR_U_ERR_CH0 0x20000000 ++#define SEC_CC_PSR_U_ERR_CH1 0x80000000 ++#define SEC_CC_PSR_U_DN_CH0 0x10000000 ++#define SEC_CC_PSR_U_DN_CH1 0x40000000 ++ ++#define SEC_DEU_DRCR MCF_REG32(0x2A018) ++#define SEC_DEU_DSR MCF_REG32(0x2A028) ++#define SEC_DEU_DISR MCF_REG32(0x2A030) ++#define SEC_DEU_DIMR MCF_REG32(0x2A038) ++ ++#define SEC_DEU_DRCR_RESET 0x01000000 ++#define SEC_DEU_DSR_RD 0x01000000 ++#define SEC_DEU_DIMR_MASK 0xF63F0000 ++ ++#define SEC_AFEU_AFRCR MCF_REG32(0x28018) ++#define SEC_AFEU_AFSR MCF_REG32(0x28028) ++#define SEC_AFEU_AFISR MCF_REG32(0x28030) ++#define SEC_AFEU_AFIMR MCF_REG32(0x28038) ++ ++#define SEC_AFEU_AFRCR_RESET 0x01000000 ++#define SEC_AFEU_AFSR_RD 0x01000000 ++#define SEC_AFEU_AFIMR_MASK 0xF61F0000 ++ ++ ++#define SEC_MDEU_MDRCR MCF_REG32(0x2C018) ++#define SEC_MDEU_MDSR MCF_REG32(0x2C028) ++#define SEC_MDEU_MDISR MCF_REG32(0x2C030) ++#define SEC_MDEU_MDIMR MCF_REG32(0x2C038) ++ ++#define SEC_MDEU_MDRCR_RESET 0x01000000 ++#define SEC_MDEU_MDSR_RD 0x01000000 ++#define SEC_MDEU_MDIMR_MASK 0xC41F0000 ++ ++ ++#define SEC_RNG_RNGRCR MCF_REG32(0x2E018) ++#define SEC_RNG_RNGSR MCF_REG32(0x2E028) ++#define SEC_RNG_RNGISR MCF_REG32(0x2E030) ++#define SEC_RNG_RNGIMR MCF_REG32(0x2E038) ++ ++#define SEC_RNG_RNGRCR_RESET 0x01000000 ++#define SEC_RNG_RNGSR_RD 0x01000000 ++#define SEC_RNG_RNGIMR_MASK 0xC2100000 ++ ++#define SEC_AESU_AESRCR MCF_REG32(0x32018) ++#define SEC_AESU_AESSR MCF_REG32(0x32028) ++#define SEC_AESU_AESISR MCF_REG32(0x32030) ++#define SEC_AESU_AESIMR MCF_REG32(0x32038) ++ ++#define SEC_AESU_AESRCR_RESET 0x01000000 ++#define SEC_AESU_AESSR_RD 0x01000000 ++#define SEC_AESU_AESIMR_MASK 0xF61F0000 ++ ++ ++#define SEC_DESC_NUM 20 ++#define SEC_CHANNEL_NUMBER 2 ++#define SEC_MAX_BUF_SIZE (32 * 1024) ++#define SEC_INIT_TIMEOUT (1 * HZ) ++#define SEC_INTERRUPT 37 ++ ++/* Header descriptor values*/ ++#define SEC_ALG_ENCR_DES_ECB_SINGLE 0x20100010 ++#define SEC_ALG_DECR_DES_ECB_SINGLE 0x20000010 ++#define SEC_ALG_ENCR_DES_ECB_TRIPLE 0x20300010 ++#define SEC_ALG_DECR_DES_ECB_TRIPLE 0x20200010 ++#define SEC_ALG_ENCR_DES_CBC_SINGLE 0x20500010 ++#define SEC_ALG_DECR_DES_CBC_SINGLE 0x20400010 ++#define SEC_ALG_ENCR_DES_CBC_TRIPLE 0x20700010 ++#define SEC_ALG_DECR_DES_CBC_TRIPLE 0x20600010 ++ ++#define SEC_ALG_MDEU_SHA256 0x30500010 ++#define SEC_ALG_MDEU_MD5 0x30600010 ++#define SEC_ALG_MDEU_SHA 0x30400010 ++#define SEC_ALG_MDEU_SHA256_HMAC 0x31D00010 ++#define SEC_ALG_MDEU_MD5_HMAC 0x31E00010 ++#define SEC_ALG_MDEU_SHA_HMAC 0x31C00010 ++ ++#define SEC_ALG_RNG 0x40000010 ++ ++ ++#define SEC_ALG_AFEU_KEY 0x10200050 ++#define SEC_ALG_AFEU_CONTEXT 0x10700050 ++ ++#define SEC_ALG_ENCR_AESU_CBC 0x60300010 ++#define SEC_ALG_DECR_AESU_CBC 0x60200010 ++#define SEC_ALG_ENCR_AESU_ECB 0x60100010 ++#define SEC_ALG_DECR_AESU_ECB 0x60000010 ++#define SEC_ALG_AESU_CTR 0x60600010 ++ ++ ++ ++#define SEC_DESCHEAD_ERROR 0xFE000000 ++#define SEC_DESCHEAD_COMPLETED 0xFF000000 ++ ++#define SEC_DEVICE_NAME "cfsec" ++ ++/*!!! This number must be changed*/ ++#define SEC_MAJOR 130 ++ ++#define SEC_DEV_BUF 1024 ++#define SEC_DEV_KEY_LEN 64 ++#define SEC_DEV_VECTOR_LEN 259 ++ ++#define SEC_AES_BLCK_LEN 16 ++#define SEC_DES_BLCK_LEN 8 ++ ++ ++/* Descriptor structure of SEC*/ ++struct sec_descriptor { ++ volatile unsigned long secdesc_header; ++ unsigned long secdesc_len1; ++ void *secdesc_ptr1; ++ unsigned long secdesc_iv_in_len; ++ void *secdesc_iv_in_ptr; ++ unsigned long secdesc_key_len; ++ void *secdesc_key_ptr; ++ unsigned long secdesc_data_in_len; ++ void *secdesc_data_in_ptr; ++ unsigned long secdesc_data_out_len; ++ void *secdesc_data_out_ptr; ++ unsigned long secdesc_iv_out_len; ++ void *secdesc_iv_out_ptr; ++ unsigned long secdesc_len7; ++ void *secdesc_ptr7; ++ void *secdesc_ptrnext; ++}; ++ ++struct sec_device_data { ++ unsigned char secdev_inbuf[SEC_DEV_BUF]; ++ unsigned char secdev_outbuf[SEC_DEV_BUF]; ++ unsigned char secdev_key[SEC_DEV_KEY_LEN]; ++ unsigned char secdev_iv[SEC_DEV_VECTOR_LEN]; ++ unsigned char secdev_ov[SEC_DEV_VECTOR_LEN]; ++ struct sec_descriptor *secdev_desc; ++}; ++ ++struct sec_descriptor *sec_desc_alloc(void); ++inline void sec_desc_free(struct sec_descriptor *desc); ++int sec_execute(int channel, struct sec_descriptor *desc, int timeout); ++int sec_nonblock_execute(struct sec_descriptor *desc); ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/m5485sim.h +@@ -0,0 +1,346 @@ ++/* ++ * m5485sim.h -- ColdFire 547x/548x System Integration Unit support. ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef m5485sim_h ++#define m5485sim_h ++/* ++ * System Integration Unit Registers ++ */ ++#define MCF_SDRAMDS MCF_REG32(0x000004) ++/* SDRAM Drive Strength */ ++#define MCF_SBCR MCF_REG32(0x000010) ++/* System Breakpoint Control */ ++#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4)) ++/* SDRAM Chip Select X */ ++#define MCF_SECSACR MCF_REG32(0x000038) ++/* Sequential Access Control */ ++#define MCF_RSR MCF_REG32(0x000044) ++/* Reset Status */ ++#define MCF_JTAGID MCF_REG32(0x000050) ++/* JTAG Device Identification */ ++#define MCF_XARB_PRIEN MCF_REG32(0x000264) ++/* Arbiter master pri enable */ ++#define MCF_XARB_PRI MCF_REG32(0x000268) ++/* Arbiter master pri levels */ ++#define MCF_SPCR MCF_REG32(0x000300) ++ ++/* ++ * FlexBus Chip Selects Registers ++ */ ++#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC)) ++#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC)) ++#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC)) ++ ++/* ++ * Interrupt Controller Registers ++ */ ++#define MCF_IPRH MCF_REG32(0x000700) ++#define MCF_IPRL MCF_REG32(0x000704) ++#define MCF_IMRH MCF_REG32(0x000708) ++#define MCF_IMRL MCF_REG32(0x00070C) ++#define MCF_INTFRCH MCF_REG32(0x000710) ++#define MCF_INTFRCL MCF_REG32(0x000714) ++#define MCF_IRLR MCF_REG08(0x000718) ++#define MCF_IACKLPR MCF_REG08(0x000719) ++#define MCF_SWIACK MCF_REG08(0x0007E0) ++#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004)) ++#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001)) ++ ++/* ++ * Slice Timers Registers ++ */ ++#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010)) ++#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010)) ++#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010)) ++#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010)) ++ ++/* ++ * Interrupt sources ++ */ ++#define ISC_EPORT_Fn(x) (x) ++/* EPORT Interrupts */ ++#define ISC_USB_EPn(x) (15+(x)) ++/* USB Endopint */ ++#define ISC_USB_ISR (22) ++/* USB General source */ ++#define ISC_USB_AISR (22) ++/* USB core source */ ++#define ISC_DSPI_OVRFW (25) ++/* DSPI overflow */ ++#define ISC_DSPI_RFOF (26) ++#define ISC_DSPI_RFDF (27) ++#define ISC_DSPI_TFUF (28) ++#define ISC_DSPI_TCF (29) ++#define ISC_DSPI_TFFF (30) ++#define ISC_DSPI_EOQF (31) ++#define ISC_PSCn(x) (35-(x)) ++#define ISC_COMM_TIM (36) ++#define ISC_SEC (37) ++#define ISC_FEC1 (38) ++#define ISC_FEC0 (39) ++#define ISC_I2C (40) ++#define ISC_PCI_ARB (41) ++#define ISC_PCI_CB (42) ++#define ISC_PCI_XLB (43) ++#define ISC_DMA (48) ++#define ISC_CANn_ERR(x) (49+(6*(x))) ++#define ISC_CANn_BUSOFF(x) (50+(6*(x))) ++#define ISC_CANn_MBOR(x) (51+(6*(x))) ++#define ISC_CAN0_WAKEIN (52) ++#define ISC_SLTn(x) (54-(x)) ++#define ISC_GPTn(x) (62-(x)) ++ ++/* ++ * Interrupt level and priorities ++ */ ++#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3)) ++#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2)) ++#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1)) ++#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0)) ++#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7)) ++#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6)) ++#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5)) ++#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4)) ++#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3)) ++#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2)) ++#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1)) ++ ++#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x))) ++#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7)) ++#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6)) ++#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5)) ++#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4)) ++#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3)) ++#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2)) ++#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1)) ++#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0)) ++ ++#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7)) ++#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6)) ++#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5)) ++#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4)) ++#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3)) ++#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2)) ++#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1)) ++#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0)) ++ ++#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7)) ++#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3))) ++#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3)) ++#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2)) ++#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1)) ++#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0)) ++ ++ ++ ++ ++ ++/********************************************************************/ ++ ++/* ++ * System Integration Unit Bitfields ++ */ ++ ++/* SBCR */ ++#define MCF_SBCR_PIN2DSPI (0x08000000) ++#define MCF_SBCR_DMA2CPU (0x10000000) ++#define MCF_SBCR_CPU2DMA (0x20000000) ++#define MCF_SBCR_PIN2DMA (0x40000000) ++#define MCF_SBCR_PIN2CPU (0x80000000) ++ ++/* SECSACR */ ++#define MCF_SECSACR_SEQEN (0x00000001) ++ ++/* RSR */ ++#define MCF_RSR_RST (0x00000001) ++#define MCF_RSR_RSTWD (0x00000002) ++#define MCF_RSR_RSTJTG (0x00000008) ++ ++/* JTAGID */ ++#define MCF_JTAGID_REV (0xF0000000) ++#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF) ++#define MCF_JTAGID_MCF5485 (0x0800C01D) ++#define MCF_JTAGID_MCF5484 (0x0800D01D) ++#define MCF_JTAGID_MCF5483 (0x0800E01D) ++#define MCF_JTAGID_MCF5482 (0x0800F01D) ++#define MCF_JTAGID_MCF5481 (0x0801001D) ++#define MCF_JTAGID_MCF5480 (0x0801101D) ++#define MCF_JTAGID_MCF5475 (0x0801201D) ++#define MCF_JTAGID_MCF5474 (0x0801301D) ++#define MCF_JTAGID_MCF5473 (0x0801401D) ++#define MCF_JTAGID_MCF5472 (0x0801501D) ++#define MCF_JTAGID_MCF5471 (0x0801601D) ++#define MCF_JTAGID_MCF5470 (0x0801701D) ++ ++ ++/* ++ * Interrupt Controller Bitfields ++ */ ++#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1) ++#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0) ++#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4) ++#define MCF_ICR_IP(x) (((x)&0x07)<<0) ++#define MCF_ICR_IL(x) (((x)&0x07)<<3) ++ ++/* ++ * Slice Timers Bitfields ++ */ ++#define MCF_SCR_TEN (0x01000000) ++#define MCF_SCR_IEN (0x02000000) ++#define MCF_SCR_RUN (0x04000000) ++#define MCF_SSR_ST (0x01000000) ++#define MCF_SSR_BE (0x02000000) ++ ++ ++/* ++ * Some needed coldfire registers ++ */ ++#define MCF_PAR_PCIBG MCF_REG16(0x000A48) ++#define MCF_PAR_PCIBR MCF_REG16(0x000A4A) ++#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3)) ++#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44) ++#define MCF_PAR_DSPI MCF_REG16(0x000A50) ++#define MCF_PAR_TIMER MCF_REG08(0X000A52) ++#define MCF_EPPAR MCF_REG16(0x000F00) ++#define MCF_EPDDR MCF_REG08(0x000F04) ++#define MCF_EPIER MCF_REG08(0x000F05) ++#define MCF_EPFR MCF_REG08(0x000F0C) ++ ++/* ++ * Some GPIO bitfields ++ */ ++#define MCF_PAR_SDA (0x0008) ++#define MCF_PAR_SCL (0x0004) ++#define MCF_PAR_PSC_TXD (0x04) ++#define MCF_PAR_PSC_RXD (0x08) ++#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) ++#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) ++#define MCF_PAR_PSC_CTS_GPIO (0x00) ++#define MCF_PAR_PSC_CTS_BCLK (0x80) ++#define MCF_PAR_PSC_CTS_CTS (0xC0) ++#define MCF_PAR_PSC_RTS_GPIO (0x00) ++#define MCF_PAR_PSC_RTS_FSYNC (0x20) ++#define MCF_PAR_PSC_RTS_RTS (0x30) ++#define MCF_PAR_PSC_CANRX (0x40) ++ ++/* ++ * FlexCAN Module Configuration Register ++ */ ++#define CANMCR_MDIS (0x80000000) ++#define CANMCR_FRZ (0x40000000) ++#define CANMCR_HALT (0x10000000) ++#define CANMCR_SOFTRST (0x02000000) ++#define CANMCR_NOTRDY (0x08000000) ++#define CANMCR_FRZACK (0x01000000) ++#define CANMCR_SUPV (0x00800000) ++#define CANMCR_MAXMB (0x0F) ++/* ++ * FlexCAN Control Register ++ */ ++#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) ++#define CANCTRL_RJW(x) (((x)&0x03)<<22) ++#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) ++#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) ++#define CANCTRL_BOFFMSK (0x00008000) ++#define CANCTRL_ERRMSK (0x00004000) ++#define CANCTRL_CLKSRC (0x00002000) ++#define CANCTRL_LPB (0x00001000) ++#define CANCTRL_SAMP(x) (((x)&0x01)<<7) ++#define CANCTRL_BOFFREC (0x00000040) ++#define CANCTRL_TSYNC (0x00000020) ++#define CANCTRL_LBUF (0x00000010) ++#define CANCTRL_LOM (0x00000008) ++#define CANCTRL_PROPSEG(x) ((x)&0x07) ++ ++/* ++ * FlexCAN Error Counter Register ++ */ ++#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) ++#define ERRCNT_TXECTR(x) ((x)&0xFF) ++ ++/* ++ * FlexCAN Error and Status Register ++ */ ++#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) ++#define ERRSTAT_ACKERR (0x00002000) ++#define ERRSTAT_CRCERR (0x00001000) ++#define ERRSTAT_FRMERR (0x00000800) ++#define ERRSTAT_STFERR (0x00000400) ++#define ERRSTAT_TXWRN (0x00000200) ++#define ERRSTAT_RXWRN (0x00000100) ++#define ERRSTAT_IDLE (0x00000080) ++#define ERRSTAT_TXRX (0x00000040) ++#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) ++#define ERRSTAT_BOFFINT (0x00000004) ++#define ERRSTAT_ERRINT (0x00000002) ++ ++/* ++ * Interrupt Mask Register ++ */ ++#define IMASK_BUF15M (0x8000) ++#define IMASK_BUF14M (0x4000) ++#define IMASK_BUF13M (0x2000) ++#define IMASK_BUF12M (0x1000) ++#define IMASK_BUF11M (0x0800) ++#define IMASK_BUF10M (0x0400) ++#define IMASK_BUF9M (0x0200) ++#define IMASK_BUF8M (0x0100) ++#define IMASK_BUF7M (0x0080) ++#define IMASK_BUF6M (0x0040) ++#define IMASK_BUF5M (0x0020) ++#define IMASK_BUF4M (0x0010) ++#define IMASK_BUF3M (0x0008) ++#define IMASK_BUF2M (0x0004) ++#define IMASK_BUF1M (0x0002) ++#define IMASK_BUF0M (0x0001) ++#define IMASK_BUFnM(x) (0x1<<(x)) ++#define IMASK_BUFF_ENABLE_ALL (0xFFFF) ++#define IMASK_BUFF_DISABLE_ALL (0x0000) ++ ++/* ++ * Interrupt Flag Register ++ */ ++#define IFLAG_BUF15M (0x8000) ++#define IFLAG_BUF14M (0x4000) ++#define IFLAG_BUF13M (0x2000) ++#define IFLAG_BUF12M (0x1000) ++#define IFLAG_BUF11M (0x0800) ++#define IFLAG_BUF10M (0x0400) ++#define IFLAG_BUF9M (0x0200) ++#define IFLAG_BUF8M (0x0100) ++#define IFLAG_BUF7M (0x0080) ++#define IFLAG_BUF6M (0x0040) ++#define IFLAG_BUF5M (0x0020) ++#define IFLAG_BUF4M (0x0010) ++#define IFLAG_BUF3M (0x0008) ++#define IFLAG_BUF2M (0x0004) ++#define IFLAG_BUF1M (0x0002) ++#define IFLAG_BUF0M (0x0001) ++#define IFLAG_BUFF_SET_ALL (0xFFFF) ++#define IFLAG_BUFF_CLEAR_ALL (0x0000) ++#define IFLAG_BUFnM(x) (0x1<<(x)) ++ ++/* ++ * Message Buffers ++ */ ++#define MB_CNT_CODE(x) (((x)&0x0F)<<24) ++#define MB_CNT_SRR (0x00400000) ++#define MB_CNT_IDE (0x00200000) ++#define MB_CNT_RTR (0x00100000) ++#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) ++#define MB_ID_STD (0x07FF) ++#define MB_ID_EXT (0x1FFFFFFF) ++#define MB_CODE_MASK (0xF0FFFFFF) ++#define CAN_MB 16 ++#define PDEV_MAX 2 ++ ++/* ++ * Some used coldfire values ++ */ ++#define MCF_EPIER_EPIE(x) (0x01 << (x)) ++#define MCF_EPPAR_EPPAx_FALLING (2) ++#define MCF_EPPAR_EPPA(n, x) (((x)&0x0003) << (2*n)) ++ ++ ++#endif /* m5485sim_h */ +--- /dev/null ++++ b/arch/m68k/include/asm/m5485sram.h +@@ -0,0 +1,12 @@ ++#ifndef SYS_SRAM_H ++#define SYS_SRAM_H ++ ++ ++#define SYS_SRAM_DMA_START (MCF_MBAR + 0x10000) ++#define SYS_SRAM_DMA_SIZE 8192 ++#define SYS_SRAM_FEC_START (SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE) ++#define SYS_SRAM_FEC_SIZE 2048 ++#define SYS_SRAM_SEC_START (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE) ++#define SYS_SRAM_SEC_SIZE 1280 ++ ++#endif /* SYS_SRAM_H */ diff --git a/target/linux/coldfire/patches/004-MCF54418-support-in-Linux-2.6.38.patch b/target/linux/coldfire/patches/004-MCF54418-support-in-Linux-2.6.38.patch new file mode 100644 index 000000000..87e03ef54 --- /dev/null +++ b/target/linux/coldfire/patches/004-MCF54418-support-in-Linux-2.6.38.patch @@ -0,0 +1,6643 @@ +From b23f9dc392de5be8a2bc17342d6aee49208a80d8 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:39 +0800 +Subject: [PATCH 04/52] MCF54418 support in Linux 2.6.38 + +Add MCF54418 support in Linux 2.6.38. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5441x/Makefile | 38 + + arch/m68k/coldfire/m5441x/config.c | 604 +++++++++++++ + arch/m68k/coldfire/m5441x/devices.c | 787 +++++++++++++++++ + arch/m68k/configs/m54418twr_defconfig | 1244 +++++++++++++++++++++++++++ + arch/m68k/include/asm/cf_5441x_cacheflush.h | 527 ++++++++++++ + arch/m68k/include/asm/mcf5441x_ccm.h | 157 ++++ + arch/m68k/include/asm/mcf5441x_clock.h | 22 + + arch/m68k/include/asm/mcf5441x_dspi.h | 671 +++++++++++++++ + arch/m68k/include/asm/mcf5441x_dtim.h | 95 ++ + arch/m68k/include/asm/mcf5441x_edma.h | 303 +++++++ + arch/m68k/include/asm/mcf5441x_eport.h | 94 ++ + arch/m68k/include/asm/mcf5441x_fbcs.h | 204 +++++ + arch/m68k/include/asm/mcf5441x_flexcan.h | 139 +++ + arch/m68k/include/asm/mcf5441x_gpio.h | 509 +++++++++++ + arch/m68k/include/asm/mcf5441x_intc.h | 727 ++++++++++++++++ + arch/m68k/include/asm/mcf5441x_pm.h | 33 + + arch/m68k/include/asm/mcf5441x_rtc.h | 127 +++ + arch/m68k/include/asm/mcf5441x_scm.h | 33 + + arch/m68k/include/asm/mcf5441x_sdramc.h | 141 +++ + arch/m68k/include/asm/mcf5441x_xbs.h | 77 ++ + 20 files changed, 6532 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m5441x/Makefile + create mode 100644 arch/m68k/coldfire/m5441x/config.c + create mode 100644 arch/m68k/coldfire/m5441x/devices.c + create mode 100644 arch/m68k/configs/m54418twr_defconfig + create mode 100644 arch/m68k/include/asm/cf_5441x_cacheflush.h + create mode 100644 arch/m68k/include/asm/mcf5441x_ccm.h + create mode 100644 arch/m68k/include/asm/mcf5441x_clock.h + create mode 100644 arch/m68k/include/asm/mcf5441x_dspi.h + create mode 100644 arch/m68k/include/asm/mcf5441x_dtim.h + create mode 100644 arch/m68k/include/asm/mcf5441x_edma.h + create mode 100644 arch/m68k/include/asm/mcf5441x_eport.h + create mode 100644 arch/m68k/include/asm/mcf5441x_fbcs.h + create mode 100644 arch/m68k/include/asm/mcf5441x_flexcan.h + create mode 100644 arch/m68k/include/asm/mcf5441x_gpio.h + create mode 100644 arch/m68k/include/asm/mcf5441x_intc.h + create mode 100644 arch/m68k/include/asm/mcf5441x_pm.h + create mode 100644 arch/m68k/include/asm/mcf5441x_rtc.h + create mode 100644 arch/m68k/include/asm/mcf5441x_scm.h + create mode 100644 arch/m68k/include/asm/mcf5441x_sdramc.h + create mode 100644 arch/m68k/include/asm/mcf5441x_xbs.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/Makefile +@@ -0,0 +1,38 @@ ++# ++# Makefile for Linux arch/m68k/coldfire/m5441x source directory ++# ++ ++obj-$(CONFIG_M5441X) += devices.o config.o ++ ++ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) ++ obj-y += usb.o ++endif ++ifneq ($(strip $(CONFIG_USB_GADGET_FSL_USB2) $(CONFIG_USB_EHCI_HCD)),) ++ifeq ($(strip $(CONFIG_USB_M5441X_FSLS)),) ++ obj-y += usb_dr.o ++endif ++endif ++ ++#ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) ++ifneq ($(strip $(CONFIG_USB_OTG) $(CONFIG_USB_M5441X_MAX3353_FSLS)),) ++ obj-y += xcvr.o ++endif ++ifneq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)), ) ++ obj-y += max3353_xc.o ++ifneq ($(strip $(CONFIG_USB_OTG)),) ++ obj-m += max3353_otg.o ++endif ++endif ++ ++# USB Host controller support ++ifneq ($(strip $(CONFIG_USB_M5441X_H1)),) ++ obj-y += usb_host.o xcvr_host.o ++endif ++ ++ifneq ($(CONFIG_FEC),) ++obj-y += fec.o ++endif ++ ++ifneq ($(CONFIG_MODELO_SWITCH),) ++obj-y += l2switch.o ++endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/config.c +@@ -0,0 +1,604 @@ ++/* ++ * linux/arch/m68k/coldfire/m5441x/config.c ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/string.h> ++#include <linux/kernel.h> ++#include <linux/console.h> ++#include <linux/bootmem.h> ++#include <linux/mm.h> ++#include <linux/sched.h> ++#include <linux/clockchips.h> ++#include <linux/delay.h> ++#include <asm/bootinfo.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/cfcache.h> ++#include <asm/cacheflush.h> ++#include <asm/io.h> ++#include <asm/cfmmu.h> ++#include <asm/setup.h> ++#include <asm/irq.h> ++#include <asm/traps.h> ++#include <asm/movs.h> ++#include <asm/movs.h> ++#include <asm/page.h> ++#include <asm/pgalloc.h> ++#include <asm/cf-sram.h> ++ ++#include <asm/mcfsim.h> ++ ++#define UBOOT_EXTRA_CLOCKS ++#include <asm/bootinfo.h> ++ ++#include <asm/mcf5441x_intc.h> ++#include <asm/mcf5441x_sdramc.h> ++#include <asm/mcf5441x_fbcs.h> ++#include <asm/mcf5441x_dtim.h> ++#include <asm/mcf5441x_xbs.h> ++ ++extern int get_irq_list(struct seq_file *p, void *v); ++extern char _text, _end; ++extern char _etext, _edata, __init_begin, __init_end; ++extern struct console mcfrs_console; ++extern char m68k_command_line[CL_SIZE]; ++extern unsigned long availmem; ++extern unsigned long shadow_cacr; ++EXPORT_SYMBOL(shadow_cacr); ++extern struct mem_info m68k_ramdisk; ++ ++static int irq_enable[NR_IRQS]; ++unsigned long num_pages; ++ ++/* cf dma physical addresses */ ++unsigned long cf_dma_base; ++EXPORT_SYMBOL(cf_dma_base); ++unsigned long cf_dma_end; ++EXPORT_SYMBOL(cf_dma_end); ++unsigned long cf_dma_size; ++EXPORT_SYMBOL(cf_dma_size); ++ ++/* ethernet mac addresses from uboot */ ++unsigned char uboot_enet0[6]; ++unsigned char uboot_enet1[6]; ++ ++void coldfire_sort_memrec(void) ++{ ++ int i, j; ++ ++ /* Sort the m68k_memory records by address */ ++ for (i = 0; i < m68k_num_memory; ++i) { ++ for (j = i + 1; j < m68k_num_memory; ++j) { ++ if (m68k_memory[i].addr > m68k_memory[j].addr) { ++ struct mem_info tmp; ++ tmp = m68k_memory[i]; ++ m68k_memory[i] = m68k_memory[j]; ++ m68k_memory[j] = tmp; ++ } ++ } ++ } ++ /* Trim off discontiguous bits */ ++ for (i = 1; i < m68k_num_memory; ++i) { ++ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) != ++ m68k_memory[i].addr) { ++ printk(KERN_DEBUG "m68k_parse_bootinfo: " ++ "addr gap between 0x%lx & 0x%lx\n", ++ m68k_memory[i-1].addr+m68k_memory[i-1].size, ++ m68k_memory[i].addr); ++ m68k_num_memory = i; ++ break; ++ } ++ } ++} ++ ++/* ++ * UBoot Handler ++ */ ++int __init uboot_commandline(char *bootargs) ++{ ++ int len = 0, cmd_line_len; ++ static struct uboot_record uboot_info; ++ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; ++ ++ extern unsigned long uboot_info_stk; ++ ++ /* validate address */ ++ if ((uboot_info_stk < PAGE_OFFSET_RAW) || ++ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE))) ++ return 0; ++ ++ /* Add offset to get post-remapped kernel memory location */ ++ uboot_info.bdi = (struct bd_info *) ++ ((*(u32 *)(uboot_info_stk)) + offset); ++ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset; ++ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset; ++ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset; ++ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset; ++ ++#if defined(CONFIG_BLK_DEV_INITRD) ++ m68k_ramdisk.addr = uboot_info.initrd_start; ++ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ? ++ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0; ++#endif ++ ++ /* copy over mac addresses */ ++ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6); ++ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6); ++ ++ /* copy command line */ ++ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start; ++ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1)) ++ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\ ++ cmd_line_len); ++ ++ return len; ++} ++ ++#define DEFAULT_COMMAND_LINE \ ++ "debug root=/dev/nfs rw \ ++ nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \ ++ ip=172.27.155.51:172.27.155.1" ++ ++/* ++ * Early Coldfire Initialization. ++ */ ++asmlinkage void __init cf_early_init(void) ++{ ++ SET_VBR((void *)MCF_RAMBAR1); ++ ++ /* Mask all interrupts */ ++ MCF_INTC0_IMRL = 0xFFFFFFFF; ++ MCF_INTC0_IMRH = 0xFFFFFFFF; ++ MCF_INTC1_IMRL = 0xFFFFFFFF; ++ MCF_INTC1_IMRH = 0xFFFFFFFF; ++ ++#if defined(CONFIG_USB) ++ /* reset USB3300 */ ++ asm ("moveb #0x40, %%d0\n\t" ++ "moveb %%d0, 0xec090000\n\t" ++ : : : "%d0"); ++ mdelay(1); ++ asm ("moveb #0x0, %%d0\n\t" ++ "moveb %%d0, 0xec090000\n\t" ++ : : : "%d0"); ++#endif ++ ++#if defined(CONFIG_NOR_FLASH_BASE) ++ MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE; ++#else ++ MCF_FBCS_CSAR(1) = 0x00000000; ++#endif ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ MCF_FBCS_CSAR(0) = FLEXBUS_LCD_CMD_ADDRESS; ++ MCF_FBCS_CSMR(0) = MCF_FBCS_CSMR_BAM_128K | MCF_FBCS_CSMR_V; ++ MCF_FBCS_CSCR(0) = MCF_FBCS_CSCR_BLS | MCF_FBCS_CSCR_AA | ++ MCF_FBCS_CSCR_PS_16; ++#endif ++ ++#if CONFIG_SDRAM_SIZE > (256*1024*1024) ++ /* Init optional SDRAM chip select */ ++ MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B; ++#endif ++ ++ MCF_XBS_CRS2 = 0x100; ++ /* Setup SDRAM crossbar(XBS) priorities */ ++ MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | /*CPU*/ ++ MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | /*eDMA*/ ++ MCF_XBS_PRS_M2(MCF_XBS_PRI_1) | /*FEC0*/ ++ MCF_XBS_PRS_M3(MCF_XBS_PRI_5) | /*FEC1*/ ++ MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | /*PCI*/ ++ MCF_XBS_PRS_M6(MCF_XBS_PRI_4) | /*USB*/ ++ MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); /*SBF*/ ++ ++ m68k_machtype = MACH_CFMMU; ++ m68k_fputype = FPU_CFV4E; ++ m68k_mmutype = MMU_CFV4E; ++ m68k_cputype = CPU_CFV4E; ++ ++ /* initialize PHYSRAM */ ++ m68k_num_memory = 0; ++ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; /* phys */ ++ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE; ++ ++ if (!uboot_commandline(m68k_command_line)) { ++#if defined(CONFIG_BOOTPARAM) ++ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1); ++#else ++ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); ++#endif ++ } ++ ++ /* Invalidate caches via CACR */ ++ flush_bcache(); ++ cacr_set(CACHE_DISABLE_MODE); ++ ++ /* Turn on caches via CACR, enable EUSP */ ++ cacr_set(CACHE_INITIAL_MODE); ++} ++ ++/* Assembler routines */ ++asmlinkage void buserr(void); ++asmlinkage void trap(void); ++asmlinkage void system_call(void); ++asmlinkage void inthandler(void); ++ ++void __init coldfire_trap_init(void) ++{ ++ int i = 0; ++ e_vector *vectors; ++ ++ vectors = (e_vector *)MCF_RAMBAR1; ++ /* ++ * There is a common trap handler and common interrupt ++ * handler that handle almost every vector. We treat ++ * the system call and bus error special, they get their ++ * own first level handlers. ++ */ ++ for (i = 3; (i <= 23); i++) ++ vectors[i] = trap; ++ for (i = 33; (i <= 63); i++) ++ vectors[i] = trap; ++ for (i = 24; (i <= 31); i++) ++ vectors[i] = inthandler; ++ for (i = 64; (i < 255); i++) ++ vectors[i] = inthandler; ++ ++ vectors[255] = 0; ++ vectors[2] = buserr; ++ vectors[32] = system_call; ++} ++ ++void settimericr(unsigned int timer, unsigned int level) ++{ ++ volatile unsigned char *icrp; ++ unsigned int icr = 0; ++ unsigned char irq = 0; ++ ++ if (timer <= 3) { ++ switch (timer) { ++ case 0: ++ irq = 32; ++ icr = MCFSIM_ICR_TIMER0; ++ break; ++ case 1: ++ irq = 33; ++ icr = MCFSIM_ICR_TIMER1; ++ break; ++ case 2: ++ irq = 34; ++ icr = MCFSIM_ICR_TIMER2; ++ break; ++ case 3: ++ irq = 35; ++ icr = MCFSIM_ICR_TIMER3; ++ break; ++ } ++ ++ icrp = (volatile unsigned char *) (icr); ++ *icrp = level; ++ coldfire_enable_irq0(irq); ++ } ++} ++ ++void coldfire_sched_clk_init(void); ++ ++void coldfire_tick(void) ++{ ++ /* Reset the ColdFire timer */ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER); ++} ++ ++void __init coldfire_sched_init(irq_handler_t handler) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32; ++ ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR); ++ __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 | ++ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \ ++ MCF_DTIM0_DTMR); ++ ++ request_irq(mcf_timervector, handler, IRQF_DISABLED, \ ++ "timer", (void *)MCF_DTIM0_DTMR); ++ ++ settimericr(0, mcf_timerlevel); ++ ++ /* initialize the fast clock */ ++ coldfire_sched_clk_init(); ++} ++ ++int timerirqpending(int timer) ++{ ++ unsigned int imr = 0; ++ unsigned ret = 0; ++ ++ switch (timer) { ++ case 1: ++ imr = 0x1; ++ break; ++ case 2: ++ imr = 0x2; ++ break; ++ default: ++ break; ++ } ++ ++ ret = getiprh() & imr; ++ return ret; ++} ++ ++unsigned long coldfire_gettimeoffset(void) ++{ ++ volatile unsigned long trr, tcn, offset; ++ ++ tcn = __raw_readw(MCF_DTIM0_DTCN); ++ trr = __raw_readl(MCF_DTIM0_DTRR); ++ offset = (tcn * (1000000 / HZ)) / trr; ++ ++ /* Check if we just wrapped the counters and maybe missed a tick */ ++ if ((offset < (1000000 / HZ / 2)) && timerirqpending(1)) ++ offset += 1000000 / HZ; ++ return offset; ++} ++ ++/* sched_clock support */ ++ ++static unsigned long long sched_clk_val; ++ ++static irqreturn_t coldfire_sched_clk_irq(int irq, void *dev) ++{ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM3_DTER); ++ sched_clk_val += 0x100000000LL; ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Setup DTIM3 as the 5441x sched_clock() implementation. The ++ * input frequency to the clock is the internal bus clock (MCF_BUSCLK) ++ * which is the system clock (MCF_CLK) / 2. ++ * ++ * On a system running at 266Mhz: ++ * MCF_CLK = 266Mhz (266000000) ++ * MCF_BUSCLK = 133Mhz (133000000) ++ * DTIM3 Tick = 133Mhz (133000000) ++ * Tick Resolution = 7.5ns (round to 8ns/Tick) ++ * ++ * On a system running at 240Mhz: ++ * MCF_CLK = 240Mhz (240000000) ++ * MCF_BUSCLK = 120Mhz (120000000) ++ * DTIM3 Tick = 120Mhz (120000000) ++ * Tick Resolution = 8.4ns (round to 8ns/Tick) ++ */ ++void __init coldfire_sched_clk_init(void) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32+3; /* DTIM3 */ ++ ++ printk(KERN_INFO "Initializing DTIM3 for sched_clock\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM3_DTMR); ++ __raw_writel(0xffffffff, MCF_DTIM3_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV1 | \ ++ MCF_DTIM_DTMR_RST_EN, MCF_DTIM3_DTMR); ++ ++ sched_clk_val = 0; ++ request_irq(mcf_timervector, coldfire_sched_clk_irq, IRQF_DISABLED, \ ++ "timer", (void *)MCF_DTIM3_DTMR); ++ ++ settimericr(3, mcf_timerlevel); ++} ++ ++#ifndef CONFIG_GENERIC_CLOCKEVENTS ++/* get highres timer */ ++unsigned long long sched_clock(void) ++{ ++ unsigned long long ret = 0; ++ ret = sched_clk_val | (unsigned long long)(MCF_REG32(MCF_DTIM3_DTCN)); ++ ret = ret << 3; ++ return ret; ++} ++ ++#else /*CONFIG_GENERIC_CLOCKEVENTS*/ ++ ++static unsigned long long sched_dtim_clk_val; ++ ++unsigned long long sched_clock(void) ++{ ++ unsigned long flags; ++ unsigned long long tcn, cycles; ++ ++ local_irq_save(flags); ++ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN))); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ return cycles + tcn; ++} ++ ++unsigned long long sys_dtim2_read(void) ++{ ++ unsigned long flags; ++ unsigned long long tcn, cycles; ++ ++ local_irq_save(flags); ++ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN))); ++ cycles = sched_dtim_clk_val; ++ local_irq_restore(flags); ++ ++ return cycles + tcn; ++} ++ ++static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev) ++{ ++ struct clock_event_device *evt = (struct clock_event_device *)dev; ++ ++ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM2_DTER); ++ sched_dtim_clk_val += (MCF_BUSCLK / 16) / HZ; ++ evt->event_handler(evt); ++ return IRQ_HANDLED; ++} ++ ++void sys_dtim2_init(struct clock_event_device *evt) ++{ ++ unsigned int mcf_timerlevel = 5; ++ unsigned int mcf_timervector = 64+32+2; /* DTIM2 */ ++ ++ printk(KERN_INFO "Initializing DTIM2 for sched_clock\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM2_DTMR); ++ __raw_writel(((MCF_BUSCLK / 16) / HZ)-1, MCF_DTIM2_DTRR); ++ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 | ++ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \ ++ MCF_DTIM2_DTMR); ++ ++ request_irq(mcf_timervector, coldfire_dtim_clk_irq, IRQF_DISABLED, \ ++ "timer2", (void *)evt); ++ ++ settimericr(3, mcf_timerlevel); ++ return; ++} ++ ++#endif ++ ++void coldfire_reboot(void) ++{ ++ /* disable interrupts and do a software reset */ ++ asm("movew #0x2700, %%sr\n\t" ++ "moveb #0x40, %%d0\n\t" ++ "moveb %%d0, 0xec090000\n\t" ++ : : : "%d0"); ++ ++ mdelay(10); ++ ++ asm("moveb #0xc0, %%d0\n\t" ++ "moveb %%d0, 0xec090000\n\t" ++ : : : "%d0"); ++} ++ ++static void coldfire_get_model(char *model) ++{ ++ sprintf(model, "Version 4 ColdFire"); ++} ++ ++/* ++ * Setup the nodes and the boot memory. ++ * ++ * memory_start and memory_end are VIRTUAL addresses ++ */ ++static void __init ++coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end) ++{ ++ unsigned long base_pfn; ++ ++ /* compute total pages in system */ ++ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT; ++ ++ /* align start/end to page boundries */ ++ memory_start = PAGE_ALIGN(memory_start); ++ memory_end = memory_end & PAGE_MASK; ++ ++ /* page numbers */ ++ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT; ++ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT; ++ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT; ++ ++ high_memory = (void *)memory_end; ++ availmem = memory_start; ++ ++ /* setup bootmem data */ ++ m68k_setup_node(0); ++ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn, ++ base_pfn, max_low_pfn); ++ availmem = PAGE_ALIGN(availmem); ++ ++ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n", ++ availmem, __pa(availmem)); ++ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n", ++ memory_start, memory_end); ++ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n", ++ base_pfn, min_low_pfn, max_low_pfn); ++ ++ /* turn over physram */ ++ free_bootmem(__pa(availmem), memory_end - availmem); ++ ++ /* configure physical dma area */ ++ cf_dma_base = __pa(PAGE_ALIGN(memory_start)); ++ cf_dma_size = CONFIG_DMA_SIZE; ++ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1; ++ ++ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n", ++ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE); ++ ++ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n", ++ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS)); ++} ++ ++/* ++ * Architecture setup for Coldfire ++ */ ++void __init config_coldfire(void) ++{ ++ unsigned long endmem, startmem; ++ ++ /* ++ * Calculate endmem from m68k_memory[0] assuming that a single ++ * chunk of ram is being configured. ++ */ ++ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK); ++ endmem = PAGE_OFFSET + m68k_memory[0].size; ++ ++ /* set virt to node shift to be the high nibble byte */ ++ m68k_virt_to_node_shift = 28; ++ ++ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \ ++ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20); ++ ++ memset(irq_enable, 0, sizeof(irq_enable)); ++ ++/* JKM -- moved early*/ ++/*register_console(&mcfrs_console);*/ ++ ++ /* ++ * Setup coldfire mach-specific handlers ++ */ ++ mach_max_dma_address = 0xffffffff; ++ mach_sched_init = coldfire_sched_init; ++ mach_tick = coldfire_tick; ++ mach_gettimeoffset = coldfire_gettimeoffset; ++ mach_reset = coldfire_reboot; ++ mach_get_model = coldfire_get_model; ++ ++ coldfire_bootmem_alloc(startmem, endmem-1); ++ ++#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE) ++ conswitchp = &dummy_con; ++#endif ++ ++#if defined(CONFIG_SERIAL_COLDFIRE) ++ /* ++ * This causes trouble when it is re-registered later. ++ * Currently this is fixed by conditionally commenting ++ * out the register_console in mcf_serial.c ++ */ ++/*JKM -- moved earlier*/ ++ register_console(&mcfrs_console); ++#endif ++} ++ ++#ifdef CONFIG_SRAM ++static int __init setup_sram_pool(void) ++{ ++ declare_sram_pool((void *)CONFIG_SRAM_BASE, CONFIG_SRAM_SIZE); ++ return 0; ++} ++postcore_initcall(setup_sram_pool); ++#endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/devices.c +@@ -0,0 +1,787 @@ ++/* ++ * Coldfire M5441x Platform Device Configuration ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Lanttor.Guo@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> ++#include <linux/i2c.h> ++ ++#include <linux/interrupt.h> ++#include <linux/init.h> ++#include <linux/mtd/partitions.h> ++#ifdef CONFIG_MMC_SPI ++#include <linux/mmc/host.h> ++#include <linux/spi/mmc_spi.h> ++#endif ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfuart.h> ++#include <asm/mcfqspi.h> ++#include <asm/mcfdspi.h> ++#include <asm/cf_io.h> ++ ++/* ++ * I2C: only support i2c0 module on m5441x platform ++ */ ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++static struct resource coldfire_i2c_resources[] = { ++ { /* I/O */ ++ .start = 0xFC058000, ++ .end = 0xFC058010, ++ .flags = IORESOURCE_MEM, ++ }, ++ { /* IRQ */ ++ .start = (64 + 30), ++ .end = (64 + 30), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device coldfire_i2c_device = { ++ .name = "mcf-i2c", ++ .id = 0, /*bus number*/ ++ .num_resources = ARRAY_SIZE(coldfire_i2c_resources), ++ .resource = coldfire_i2c_resources, ++}; ++ ++static void mcf5441x_init_i2c(void) ++{ ++ MCF_PM_PPMCR0 = 22; ++ platform_device_register(&coldfire_i2c_device); ++} ++ ++#ifdef CONFIG_I2C_BOARDINFO ++static struct i2c_board_info mcf_i2c_devices[] = { ++#ifdef CONFIG_USB_M5441X_MAX3353_FSLS ++ { ++ I2C_BOARD_INFO("max3353", 0x2c), ++ }, ++#endif ++}; ++#endif ++ ++#endif ++ ++#if defined(CONFIG_MMC_ESDHC) ++static struct resource sd_mmc_esdhc_resources[] = { ++ [0] = { ++ .name = "esdhc-module", ++ .start = 0xFC0CC000, ++ .end = 0xFC0CC000 + 0x100, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .name = "esdhc-int-level", ++ .start = (64 + 64 + 64 + 31), ++ .end = (64 + 64 + 64 + 31), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .name = "esdhc-pin", ++ .start = &MCF_GPIO_PAR_ESDHCH, ++ .end = &MCF_GPIO_PAR_ESDHCL, ++ .flags = IORESOURCE_MEM, ++ }, ++ [3] = { ++ .name = "esdhc-slew", ++ .start = &MCF_GPIO_SRCR_SDHC, ++ .end = &MCF_GPIO_SRCR_SDHC, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device sd_mmc_esdhc_device = { ++ .name = "esdhc", ++ .id = -1, ++ .resource = sd_mmc_esdhc_resources, ++ .num_resources = ARRAY_SIZE(sd_mmc_esdhc_resources), ++}; ++#endif ++ ++#if defined(CONFIG_MTD_NAND_FSL_NFC) ++static struct resource nfc_resources[] = { ++ [0] = { ++ .name = "nfc-config", ++ .start = 0xFC0FC000, ++ .end = 0xFC0FFF3B, ++ .flags = IORESOURCE_MEM, ++ ++ }, ++ [1] = { ++ .name = "nfc-int-level", ++ .start = (64 + 64 + 64 + 25), ++ .end = (64 + 64 + 64 + 25), ++ .flags = IORESOURCE_IRQ, ++ }, ++ ++}; ++static struct platform_device nfc_device = { ++ .name = "fsl_nfc", ++ .id = -1, ++ .resource = nfc_resources, ++ .num_resources = ARRAY_SIZE(nfc_resources), ++}; ++#endif ++ ++/* ++ * DSPI ++ */ ++#ifdef CONFIG_SPI ++ ++#if defined(CONFIG_DSPI0) /* DSPI0 initialization */ ++#define M5441X_DSPI0_MCR 0xFC05C000 /* base */ ++ ++#define M5441X_DSPI0_IRQ_SOURCE (31) ++#define M5441X_DSPI0_IRQ_VECTOR (64 + M5441X_DSPI0_IRQ_SOURCE) ++ ++/* number of supported SPI selects */ ++#define SPI_NUM_CHIPSELECTS 8 ++ ++#define M5441X_SPI0_PAR_VAL (MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK | \ ++ MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | \ ++ MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN | \ ++ MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0) ++ ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition at26df081a_partitions[] = { ++ { ++ .name = "at26df081a", ++ .size = (1024*64*16), ++ .offset = 0x00000000, ++ .mask_flags = 0, ++ } ++}; ++#endif ++ ++#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) ++static struct flash_platform_data at26df081a_platform_data = { ++ .name = "Atmel at26df081a SPI Flash chip", ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = at26df081a_partitions, ++ .nr_parts = ++ sizeof(at26df081a_partitions) / sizeof(*at26df081a_partitions), ++#endif ++ .type = "at26df081a" ++}; ++ ++static struct coldfire_dspi_chip at26df081a_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 16, /* How many bits per word to transfer ++ per one time (8 or 16) */ ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 0, ++ .br = 0, ++ .pcssck = 1, ++ .pasc = 1, ++ .pdt = 1, ++ .cssck = 4, ++ .asc = 4, ++ .dt = 14, ++}; ++#endif ++ ++#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE) ++static struct fsl_ssd1289_fb_display fsl_ssd1289_data = { ++ .width = 320, ++ .height = 240, ++ .xres = 320, ++ .yres = 240, ++ .bpp = 16, ++}; ++#endif ++ ++#if defined(CONFIG_SSD1289_SPI_MODE) ++static struct coldfire_dspi_chip ssd1289_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 9, ++ .void_write_data = 0, ++ .dbr = 0, ++ .pbr = 0, ++ .br = 1, ++ .pcssck = 0, ++ .pasc = 0, ++ .pdt = 0, ++ .cssck = 0, ++ .asc = 0, ++ .dt = 0, ++}; ++#endif ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++static struct coldfire_dspi_chip spidev_chip_info = { ++ .bits_per_word = 8, ++}; ++#endif ++ ++ ++static struct coldfire_spi_master spi0_master_info = { ++ .bus_num = 1, ++ .num_chipselect = SPI_NUM_CHIPSELECTS, ++ .irq_list = 0, /* not used */ ++ .irq_source = M5441X_DSPI0_IRQ_SOURCE, ++ .irq_vector = M5441X_DSPI0_IRQ_VECTOR, ++ .irq_mask = (1 << M5441X_DSPI0_IRQ_SOURCE), ++ .irq_lp = 0x2, /* irq level */ ++ .par_val = M5441X_SPI0_PAR_VAL, ++ .cs_control = NULL, ++}; ++ ++static struct resource coldfire_spi0_resources[] = { ++ [0] = { ++ .name = "spi-par", ++ .start = (u32)&MCF_GPIO_PAR_DSPI0WH, /* PAR_DSPI0 */ ++ .end = (u32)&MCF_GPIO_PAR_DSPI0WH, /* PAR_DSPI0 */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [1] = { ++ .name = "spi-module", ++ .start = M5441X_DSPI0_MCR, /* DSPI MCR Base */ ++ .end = M5441X_DSPI0_MCR + 0xc0, /* DSPI mem map end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [2] = { ++ .name = "spi-int-level", ++ .start = (u32)&MCF_INTC0_ICR31, /* ICR start */ ++ .end = (u32)&MCF_INTC0_ICR31, /* ICR end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [3] = { ++ .name = "spi-int-mask", ++ .start = (u32)&MCF_INTC0_IMRL, /* IMRL */ ++ .end = (u32)&MCF_INTC0_IMRL, /* IMRL */ ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct platform_device coldfire_spi0 = { ++ .name = "spi_coldfire", ++ .id = -1, ++ .resource = coldfire_spi0_resources, ++ .num_resources = ARRAY_SIZE(coldfire_spi0_resources), ++ .dev = { ++ .platform_data = &spi0_master_info, ++ } ++}; ++ ++#elif defined(CONFIG_DSPI1) /* DSPI1 initialization */ ++#define M5441X_DSPI1_MCR 0xFC03C000 /* base */ ++ ++#define M5441X_DSPI1_IRQ_SOURCE (54) ++#define M5441X_DSPI1_IRQ_VECTOR (64 + 64 + M5441X_DSPI1_IRQ_SOURCE) ++ ++/* number of supported SPI selects */ ++#define SPI_NUM_CHIPSELECTS 8 ++ ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++static struct coldfire_dspi_chip spidev_chip_info = { ++ .bits_per_word = 8, ++}; ++#endif ++ ++static struct coldfire_spi_master spi1_master_info = { ++ .bus_num = 1, ++ .num_chipselect = SPI_NUM_CHIPSELECTS, ++ .irq_list = 0, /* not used */ ++ .irq_source = M5441X_DSPI1_IRQ_SOURCE, ++ .irq_vector = M5441X_DSPI1_IRQ_VECTOR, ++ .irq_mask = (1 << (M5441X_DSPI1_IRQ_SOURCE - 32)), ++ .irq_lp = 0x2, /* irq level */ ++ .cs_control = NULL, ++}; ++ ++static struct resource coldfire_spi1_resources[] = { ++ [0] = { ++ .name = "spi-par", ++ .start = (u32)&MCF_GPIO_PAR_ESDHCH, /* PAR_ESDHCH */ ++ .end = (u32)&MCF_GPIO_PAR_ESDHCL, /* PAR_ESDHCL */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [1] = { ++ .name = "spi-module", ++ .start = M5441X_DSPI1_MCR, /* DSPI MCR Base */ ++ .end = M5441X_DSPI1_MCR + 0xc0, /* DSPI mem map end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [2] = { ++ .name = "spi-int-level", ++ .start = (u32)&MCF_INTC1_ICR54, /* ICR start */ ++ .end = (u32)&MCF_INTC1_ICR54, /* ICR end */ ++ .flags = IORESOURCE_MEM ++ }, ++ ++ [3] = { ++ .name = "spi-int-mask", ++ .start = (u32)&MCF_INTC1_IMRH, /* IMRL */ ++ .end = (u32)&MCF_INTC1_IMRH, /* IMRL */ ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct platform_device coldfire_spi1 = { ++ .name = "spi_coldfire", ++ .id = -1, ++ .resource = coldfire_spi1_resources, ++ .num_resources = ARRAY_SIZE(coldfire_spi1_resources), ++ .dev = { ++ .platform_data = &spi1_master_info, ++ } ++}; ++ ++#ifdef CONFIG_MMC_SPI ++static struct coldfire_dspi_chip dspi_sd_chip_info = { ++ .mode = SPI_MODE_0, ++ .bits_per_word = 8, ++ .void_write_data = 0xff, ++ .dbr = 0, ++ .pbr = 1, ++ .br = 1, ++ .pcssck = 2, ++ .pasc = 2, ++ .pdt = 2, ++ .cssck = 5, ++ .asc = 5, ++ .dt = 5, ++}; ++ ++int mmc_spi_init(struct device *mmc_spi_device, ++ irqreturn_t mmc_spi_irq_handler(int irq, void *private), ++ void *irq_privatedata) ++{ ++ int ret; ++#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1) ++ int card_detect_extern_irq = 64 + 1; ++ /*this is irq1 hardware work round*/ ++ MCF_GPIO_PAR_IRQ0H |= 0x3; ++ ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1; ++ ++ MCF_INTC0_ICR1 = 7; /* IRQ1 */ ++#if debug_mmc_spi ++ printk(KERN_INFO "MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x " ++ "MCF_EPORT_EPFR %x MCF_EPORT_EPIER %x " ++ "MCF_INTC0_IMRL %x MCF_INTC0_INTFRCL %x " ++ "MCF_INTC0_IPRL %x\n", ++ MCF_INTC0_ICR1, MCF_EPORT_EPPAR, MCF_EPORT_EPFR, ++ MCF_EPORT_EPIER, MCF_INTC0_IMRL, MCF_INTC0_INTFRCL, ++ MCF_INTC0_IPRL); ++#endif ++#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7) ++ int card_detect_extern_irq = 64 + 7; ++ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7; ++ ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ ++ MCF_INTC0_ICR7 = 2; /* IRQ7 */ ++#ifdef debug_mmc_spi ++ printk("MCF_INTC0_ICR7 %x MCF_EPORT_EPPAR %x\n", ++ MCF_INTC0_ICR7, MCF_EPORT_EPPAR); ++#endif ++#else ++ int card_detect_extern_irq = 64 + 7; ++ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7; ++ ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ ++ MCF_INTC0_ICR7 = 2; /* IRQ7 */ ++#ifdef debug_mmc_spi ++ printk(KERN_INFO "MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x\n", ++ MCF_INTC0_ICR7, MCF_EPORT_EPPAR); ++#endif ++#endif ++ ++ ret = request_irq(card_detect_extern_irq, ++ mmc_spi_irq_handler, IRQF_DISABLED, ++ "mmc_spi_irq", irq_privatedata); ++ if (ret) { ++ printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static struct mmc_spi_platform_data mcf5441x_mmc_pdata = { ++ .ocr_mask = MMC_VDD_33_34, ++ .init = mmc_spi_init, ++}; ++#endif ++ ++#endif ++ ++/* DSPI device */ ++static struct spi_board_info spi_board_info[] = { ++ ++#if defined(CONFIG_DSPI1) && defined(CONFIG_MMC_SPI) ++ { ++ .modalias = "mmc_spi", ++ .max_speed_hz = 50000000, ++ .bus_num = 1, ++ .chip_select = 0, ++ .platform_data = &mcf5441x_mmc_pdata, ++ .controller_data = &dspi_sd_chip_info, ++ }, ++#endif ++#if defined(CONFIG_DSPI0) && (defined(CONFIG_MTD_M25P80) || \ ++ defined(CONFIG_MTD_M25P80_MODULE)) ++ { ++ .modalias = "m25p80", /* Name of spi driver for this device */ ++ .max_speed_hz = 70000000, /* max spi clock in HZ */ ++ .bus_num = 1, ++ .chip_select = CONFIG_DSP0_SBF_CS, ++ .platform_data = &at26df081a_platform_data, ++ .controller_data = &at26df081a_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_DSPI0) && defined(CONFIG_SSD1289_SPI_MODE) ++ { ++ .modalias = "spi-ssd1289", ++ .max_speed_hz = 50000000, ++ .bus_num = 1, ++ .chip_select = 0, ++ .platform_data = &fsl_ssd1289_data, ++ .controller_data = &ssd1289_chip_info ++ }, ++#endif ++ ++#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */ ++ .bus_num = 1, ++ .chip_select = 0, /* CS0 */ ++ .controller_data = &spidev_chip_info, ++ }, ++#endif ++}; ++ ++/* ++ * m5441x_spi_init - Initialize SPI ++ */ ++static int __init m5441x_spi_init(void) ++{ ++ int retval; ++ ++ /* register device */ ++#if defined(CONFIG_DSPI0) ++ MCF_GPIO_PAR_DSPI0WH = ++ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SCK_MASK) | ++ MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK; ++ MCF_GPIO_PAR_DSPI0WH = ++ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SOUT_MASK) | ++ MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT; ++ MCF_GPIO_PAR_DSPI0WH = ++ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SIN_MASK) | ++ MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN; ++ MCF_GPIO_PAR_DSPI0WH = ++ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_PCS0_MASK) | ++ MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0; ++ MCF_GPIO_PAR_DSPI0WL = 0x80; ++ retval = platform_device_register(&coldfire_spi0); ++ if (retval < 0) ++ goto out; ++#elif defined(CONFIG_DSPI1) ++ MCF_PM_PPMCR0 = 0xf; ++ MCF_GPIO_PAR_ESDHCH = 0x55; /* DAT[3:0] */ ++ MCF_GPIO_PAR_ESDHCL = 0x05; /* CMD, CLK */ ++ MCF_GPIO_SRCR_IRQ0 = 3; ++ MCF_GPIO_SRCR_SDHC = 3; ++ retval = platform_device_register(&coldfire_spi1); ++ if (retval < 0) ++ goto out; ++#endif ++ ++ /* register board info */ ++ if (ARRAY_SIZE(spi_board_info)) ++ retval = spi_register_board_info(spi_board_info, ++ ARRAY_SIZE(spi_board_info)); ++ ++out: ++ return retval; ++} ++#endif ++ ++#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE) ++/* ++ * UART initialization ++ */ ++static struct mcf_platform_uart m5441x_uart_platform[] = { ++#ifdef CONFIG_SERIAL_MCF_UART0 ++ { ++ .mapbase = MCFUART_BASE0, ++ .irq = MCFINT0_VECBASE + MCFINT_UART0, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART1 ++ { ++ .mapbase = MCFUART_BASE1, ++ .irq = MCFINT0_VECBASE + MCFINT_UART1, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART2 ++ { ++ .mapbase = MCFUART_BASE2, ++ .irq = MCFINT0_VECBASE + MCFINT_UART2, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART3 ++ { ++ .mapbase = MCFUART_BASE3, ++ .irq = MCFINT0_VECBASE + MCFINT_UART3, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART4 ++ { ++ .mapbase = MCFUART_BASE4, ++ .irq = MCFINT1_VECBASE + MCFINT_UART4, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART5 ++ { ++ .mapbase = MCFUART_BASE5, ++ .irq = MCFINT1_VECBASE + MCFINT_UART5, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART6 ++ { ++ .mapbase = MCFUART_BASE6, ++ .irq = MCFINT1_VECBASE + MCFINT_UART6, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART7 ++ { ++ .mapbase = MCFUART_BASE7, ++ .irq = MCFINT1_VECBASE + MCFINT_UART7, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART8 ++ { ++ .mapbase = MCFUART_BASE8, ++ .irq = MCFINT1_VECBASE + MCFINT_UART8, ++ }, ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART9 ++ { ++ .mapbase = MCFUART_BASE9, ++ .irq = MCFINT1_VECBASE + MCFINT_UART9, ++ }, ++#endif ++ {} ++}; ++ ++static struct platform_device m5441x_uart = { ++ .name = "mcfuart", ++ .id = 0, ++ .dev.platform_data = m5441x_uart_platform, ++}; ++ ++static void m5441x_uarts_init(void) ++{ ++#ifdef CONFIG_SERIAL_MCF_UART0 ++ /* enable uart0 clock */ ++ MCF_PM_PPMCR0 = 24; ++ /* gpio pin assignment for uart0 */ ++ MCF_GPIO_PAR_UART0 = ++ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0RXD_MASK) | ++ MCF_GPIO_PAR_UART0_U0RXD_U0RXD; ++ MCF_GPIO_PAR_UART0 = ++ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0TXD_MASK) | ++ MCF_GPIO_PAR_UART0_U0TXD_U0TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART1 ++ /* enable uart1 clock */ ++ MCF_PM_PPMCR0 = 25; ++ /* gpio pin assignment for uart1 */ ++ MCF_GPIO_PAR_UART1 = ++ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1RXD_MASK) | ++ MCF_GPIO_PAR_UART1_U1RXD_U1RXD; ++ MCF_GPIO_PAR_UART1 = ++ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1TXD_MASK) | ++ MCF_GPIO_PAR_UART1_U1TXD_U1TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART2 ++ /* enable uart2 clock */ ++ MCF_PM_PPMCR0 = 26; ++ /* gpio pin assignment for uart2 */ ++ MCF_GPIO_PAR_UART2 = ++ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2RXD_MASK) | ++ MCF_GPIO_PAR_UART2_U2RXD_U2RXD; ++ MCF_GPIO_PAR_UART2 = ++ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2TXD_MASK) | ++ MCF_GPIO_PAR_UART2_U2TXD_U2TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART3 ++ /* enable uart3 clock */ ++ MCF_PM_PPMCR0 = 27; ++ /* gpio pin assignment for uart3 */ ++ MCF_GPIO_PAR_DSPI0WH = ++ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SIN_MASK) | ++ MCF_GPIO_PAR_DSPI0_SIN_U3RXD; ++ MCF_GPIO_PAR_DSPI0WH = ++ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SOUT_MASK) | ++ MCF_GPIO_PAR_DSPI0_SOUT_U3TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART4 ++ /* enable uart4 clock */ ++ MCF_PM_PPMCR1 = 24; ++ /* gpio pin assignment for uart4 */ ++ MCF_GPIO_PAR_UART0 = ++ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0RTS_MASK) | ++ MCF_GPIO_PAR_UART0_U0RTS_U4RXD; ++ MCF_GPIO_PAR_UART0 = ++ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0CTS_MASK) | ++ MCF_GPIO_PAR_UART0_U0CTS_U4TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART5 ++ /* enable uart5 clock */ ++ MCF_PM_PPMCR1 = 25; ++ /* gpio pin assignment for uart5 */ ++ MCF_GPIO_PAR_UART1 = ++ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1RTS_MASK) | ++ MCF_GPIO_PAR_UART1_U1RTS_U5RXD; ++ MCF_GPIO_PAR_UART1 = ++ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1CTS_MASK) | ++ MCF_GPIO_PAR_UART1_U1CTS_U5TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART6 ++ /* enable uart6 clock */ ++ MCF_PM_PPMCR1 = 26; ++ /* gpio pin assignment for uart6 */ ++ MCF_GPIO_PAR_UART2 = ++ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2RTS_MASK) | ++ MCF_GPIO_PAR_UART2_U2RTS_U6RXD; ++ MCF_GPIO_PAR_UART2 = ++ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2CTS_MASK) | ++ MCF_GPIO_PAR_UART2_U2CTS_U6TXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART7 ++ /* enable uart7 clock */ ++ MCF_PM_PPMCR1 = 27; ++ /* gpio pin assignment for uart7 */ ++ MCF_GPIO_PAR_SSI0H &= (MCF_GPIO_PAR_SSI0H_FS_MASK); ++ MCF_GPIO_PAR_SSI0H |= (MCF_GPIO_PAR_SSI0H_FS_U7TXD); ++ MCF_GPIO_PAR_SSI0L &= (MCF_GPIO_PAR_SSI0L_BCLK_MASK); ++ MCF_GPIO_PAR_SSI0L |= (MCF_GPIO_PAR_SSI0L_BCLK_U7RXD); ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART8 ++ /* enable uart8 clock */ ++ MCF_PM_PPMCR1 = 28; ++ /* gpio pin assignment for uart8 */ ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK) | ++ MCF_GPIO_PAR_CANI2C_I2C0SCL_U8TXD; ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK) | ++ MCF_GPIO_PAR_CANI2C_I2C0SDA_U8RXD; ++#endif ++#ifdef CONFIG_SERIAL_MCF_UART9 ++ /* enable uart4 clock */ ++ MCF_PM_PPMCR1 = 29; ++ /* gpio pin assignment for uart9 */ ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1TX_MASK) | ++ MCF_GPIO_PAR_CANI2C_CAN1TX_U9TXD; ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1RX_MASK) | ++ MCF_GPIO_PAR_CANI2C_CAN1RX_U9RXD; ++#endif ++} ++#endif ++ ++#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE) ++/* ++ * RTC initialization ++ */ ++static struct platform_device rtc_device = { ++ .name = "rtc-m5441x", ++ .id = -1, ++}; ++ ++static void m5441x_rtc_init(void) ++{ ++ /* Power management: enable RTC clock */ ++ MCF_PM_PPMCR0 = 42; ++} ++#endif ++ ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static struct platform_device fsl_ssd1289_device = { ++ .name = "fsl-ssd1289", ++ .id = -1, ++ .dev = { ++ .platform_data = &fsl_ssd1289_data, ++ }, ++}; ++#endif ++ ++static struct platform_device *m5441x_devices[] __initdata = { ++#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE) ++ &m5441x_uart, ++#endif ++#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE) ++ &rtc_device, ++#endif ++#if defined(CONFIG_MMC_ESDHC) ++ &sd_mmc_esdhc_device, ++#endif ++#if defined(CONFIG_MTD_NAND_FSL_NFC) ++ &nfc_device, ++#endif ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ &fsl_ssd1289_device, ++#endif ++}; ++ ++static int __init mcf5441x_init_devices(void) ++{ ++ printk(KERN_INFO "mcf5441x_init_devices: %s.\n", __func__); ++ ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++#ifdef CONFIG_I2C_BOARDINFO ++ i2c_register_board_info(0, mcf_i2c_devices, ++ ARRAY_SIZE(mcf_i2c_devices)); ++#endif ++ mcf5441x_init_i2c(); ++#endif ++#if defined(CONFIG_SPI) || defined(CONFIG_SPI_MODULE) ++ m5441x_spi_init(); ++#endif ++#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE) ++ m5441x_uarts_init(); ++#endif ++#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE) ++ m5441x_rtc_init(); ++#endif ++ platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices)); ++ return 0; ++} ++ ++arch_initcall(mcf5441x_init_devices); ++ ++ +--- /dev/null ++++ b/arch/m68k/configs/m54418twr_defconfig +@@ -0,0 +1,1244 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.29 ++# Fri Apr 23 14:36:43 2010 ++# ++CONFIG_M68K=y ++CONFIG_MMU=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++# CONFIG_TIME_LOW_RES is not set ++CONFIG_GENERIC_IOMAP=y ++# CONFIG_NO_IOPORT is not set ++# CONFIG_NO_DMA is not set ++CONFIG_HZ=100 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_RT_GROUP_SCHED is not set ++CONFIG_USER_SCHED=y ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++# CONFIG_NAMESPACES is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_FREEZER is not set ++ ++# ++# Platform dependent setup ++# ++CONFIG_COLDFIRE=y ++CONFIG_CFV4E=y ++# CONFIG_FPU is not set ++# CONFIG_AMIGA is not set ++# CONFIG_ATARI is not set ++# CONFIG_MAC is not set ++# CONFIG_APOLLO is not set ++# CONFIG_VME is not set ++# CONFIG_HP300 is not set ++# CONFIG_SUN3X is not set ++# CONFIG_Q40 is not set ++# CONFIG_SUN3 is not set ++ ++# ++# Processor type ++# ++# CONFIG_M68020 is not set ++# CONFIG_M68030 is not set ++# CONFIG_M68040 is not set ++# CONFIG_M68060 is not set ++# CONFIG_M5445X is not set ++CONFIG_HAVE_FSL_USB_DR=y ++# CONFIG_M547X_8X is not set ++CONFIG_M5441X=y ++CONFIG_M54418=y ++CONFIG_M54418EVB=y ++CONFIG_MCFCLK=250000000 ++# CONFIG_MCF_USER_HALT is not set ++CONFIG_MMU_CFV4E=y ++CONFIG_SDRAM_BASE=0x40000000 ++CONFIG_SDRAM_SIZE=0x08000000 ++CONFIG_NOR_FLASH_BASE=0x00000000 ++CONFIG_DMA_BASE=0xdf000000 ++CONFIG_DMA_SIZE=0x1000000 ++# CONFIG_VDSO is not set ++# CONFIG_M68KFPU_EMU is not set ++CONFIG_ADVANCED=y ++# CONFIG_RMW_INSNS is not set ++CONFIG_SINGLE_MEMORY_CHUNK=y ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_NEED_MULTIPLE_NODES=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++ ++# ++# General setup ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_PROC_HARDWARE=y ++CONFIG_ZONE_DMA=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_PACKET=y ++# CONFIG_PACKET_MMAP is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++# CONFIG_IP_MULTIPLE_TABLES is not set ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++CONFIG_INET_AH=y ++CONFIG_INET_ESP=y ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++# CONFIG_WIRELESS_EXT is not set ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_KLIPS is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_STANDALONE is not set ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++CONFIG_MTD_M25P80=y ++CONFIG_M25PXX_USE_FAST_READ=y ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++CONFIG_MTD_BLOCK2MTD=y ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++CONFIG_MTD_NAND_FSL_NFC=y ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=64000 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_HD is not set ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_LIBFC is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++CONFIG_NATIONAL8364x_PHY=y ++CONFIG_NATIONAL8384x_PHY=y ++CONFIG_MicrelKSZ8041_PHY=y ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_ENC28J60 is not set ++# CONFIG_DNET is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_FEC=y ++CONFIG_FEC2=y ++CONFIG_FEC_SHARED_PHY=y ++# CONFIG_MODELO_SWITCH is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_LIBPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++# CONFIG_SERIAL_COLDFIRE_EDMA is not set ++CONFIG_SERIAL_MCF=y ++CONFIG_SERIAL_MCF_BAUDRATE=115200 ++CONFIG_SERIAL_MCF_CONSOLE=y ++CONFIG_SERIAL_MCF_UART0=y ++# CONFIG_SERIAL_MCF_UART1 is not set ++# CONFIG_SERIAL_MCF_UART2 is not set ++# CONFIG_SERIAL_MCF_UART3 is not set ++# CONFIG_SERIAL_MCF_UART4 is not set ++# CONFIG_SERIAL_MCF_UART5 is not set ++# CONFIG_SERIAL_MCF_UART6 is not set ++# CONFIG_SERIAL_MCF_UART7 is not set ++# CONFIG_SERIAL_MCF_UART8 is not set ++# CONFIG_SERIAL_MCF_UART9 is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_I2C is not set ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_SPI_DSPI=y ++# CONFIG_SPI_COLDFIRE_DSPI_EDMA is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_COLDFIRE_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++# CONFIG_HID_SUPPORT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++CONFIG_USB_EHCI_FSL=y ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_M5445X_ULPI is not set ++# CONFIG_USB_M5445X_FSLS is not set ++CONFIG_USB_M5441X_ULPI=y ++# CONFIG_USB_M5441X_FSLS is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++CONFIG_USB_GADGET_FSL_USB2=y ++CONFIG_USB_FSL_USB2=m ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++CONFIG_USB_GADGETFS=m ++CONFIG_USB_FILE_STORAGE=m ++CONFIG_USB_FILE_STORAGE_TEST=y ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++ ++# ++# OTG and related infrastructure ++# ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_ESDHC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_MCF is not set ++CONFIG_RTC_M5441X=y ++CONFIG_DMADEVICES=y ++ ++# ++# DMA Devices ++# ++CONFIG_COLDFIRE_EDMA=y ++CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# Character devices ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=y ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++CONFIG_MINIX_FS=y ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++# CONFIG_BOOTPARAM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=y ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++CONFIG_CRYPTO_PCBC=m ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++ ++# ++# OCF Configuration ++# ++# CONFIG_OCF_OCF is not set ++ ++# ++# Talitos Driver ++# ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_MCFCAU is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++CONFIG_CRC7=y ++CONFIG_LIBCRC32C=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +--- /dev/null ++++ b/arch/m68k/include/asm/cf_5441x_cacheflush.h +@@ -0,0 +1,527 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Based on include/asm-m68k/cacheflush.h ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef M68K_CF_5441x_CACHEFLUSH_H ++#define M68K_CF_5441x_CACHEFLUSH_H ++ ++#include <asm/cfcache.h> ++ ++/* ++ * Coldfire Cache Model ++ * ++ * The Coldfire processors use a Harvard architecture cache configured ++ * as four-way set associative. The cache does not implement bus snooping ++ * so cache coherency with other masters must be maintained in software. ++ * ++ * The cache is managed via the CPUSHL instruction in conjunction with ++ * bits set in the CACR (cache control register). Currently the code ++ * uses the CPUSHL enhancement which adds the ability to ++ * invalidate/clear/push a cacheline by physical address. This feature ++ * is designated in the Hardware Configuration Register [D1-CPES]. ++ * ++ * CACR Bits: ++ * DPI[28] cpushl invalidate disable for d-cache ++ * IDPI[12] cpushl invalidate disable for i-cache ++ * SPA[14] cpushl search by physical address ++ * IVO[20] cpushl invalidate only ++ * ++ * Random Terminology: ++ * * invalidate = reset the cache line's valid bit ++ * * push = generate a line-sized store of the data if its contents are ++ * marked as modifed (the modified flag is cleared after ++ * the store) ++ * * clear = push + invalidate ++ */ ++ ++/** ++ * flush_icache - Flush all of the instruction cache ++ */ ++static inline void flush_icache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%ic,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * flush_dcache - Flush all of the data cache ++ */ ++static inline void flush_dcache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * flush_bcache - Flush all of both caches ++ */ ++static inline void flush_bcache(void) ++{ ++ asm volatile("nop\n" ++ "moveq%.l #0,%%d0\n" ++ "moveq%.l #0,%%d1\n" ++ "move%.l %%d0,%%a0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "add%.l #0x0010,%%a0\n" ++ "addq%.l #1,%%d1\n" ++ "cmpi%.l %0,%%d1\n" ++ "bne 1b\n" ++ "moveq%.l #0,%%d1\n" ++ "addq%.l #1,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "cmpi%.l #4,%%d0\n" ++ "bne 1b\n" ++ : : "i" (CACHE_SETS) ++ : "a0", "d0", "d1"); ++} ++ ++/** ++ * cf_cache_clear - invalidate cache ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Invalidate cache lines starting at paddr for len bytes. ++ * Those lines are not pushed. ++ */ ++static inline void cf_cache_clear(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne%.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA+CF_CACR_IVO) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_push - Push dirty cache out with no invalidate ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Push the any dirty lines starting at paddr for len bytes. ++ * Those lines are not invalidated. ++ */ ++static inline void cf_cache_push(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_flush - Push dirty cache out and invalidate ++ * @paddr: starting physical address ++ * @len: number of bytes ++ * ++ * Push the any dirty lines starting at paddr for len bytes and ++ * invalidate those lines. ++ */ ++static inline void cf_cache_flush(unsigned long paddr, int len) ++{ ++ /* number of lines */ ++ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; ++ if (len == 0) ++ return; ++ ++ /* align on set boundary */ ++ paddr &= 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (paddr), "r" (len), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "d0"); ++} ++ ++/** ++ * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the any dirty data/instr lines starting at paddr for len bytes and ++ * invalidate those lines. ++ */ ++static inline void cf_cache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ int len; ++ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0; ++ len = vend - vstart; ++ if (len == 0) ++ return; ++ vstart = __pa(vstart); ++ vend = vstart + len; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (vstart), "a" (vend), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_flush_range - Push dirty data cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push/Clear the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[IVO] is 0 ++ * CACR[DDPI] is 0 ++ * ++ * Sets CACR[SPA] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_inv_range - Invalidate data cache in range ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Invalidate the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[DDPI] is 0 ++ * ++ * Sets CACR[SPA] and CACR[IVO] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_inv_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA | CF_CACR_IVO) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_dcache_push_range - Push data cache in range ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the virtual range *vstart* -> *vend* using the enhanced ++ * cpushl instruction to search by physical address. ++ * ++ * Assumes CACR[IVO] is 0 ++ * ++ * Sets CACR[SPA] and CACR[DDPI] to 1 for the duration of this routine ++ */ ++static inline void cf_dcache_push_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%dc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA | CF_CACR_DPI) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * cf_icache_flush_range - Push dirty inst cache in range out and invalidate ++ * @vstart - starting virtual address ++ * @vend: ending virtual address ++ * ++ * Push the any dirty instr lines starting at paddr for len bytes and ++ * invalidate those lines. This should just be an invalidate since you ++ * shouldn't be able to have dirty instruction cache. ++ */ ++static inline void cf_icache_flush_range(unsigned long vstart, ++ unsigned long vend) ++{ ++ /* align on set boundary */ ++ vstart &= 0xfffffff0; ++ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; ++ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%a0\n" ++ "move%.l %1,%%a1\n" ++ "1:\n" ++ "cpushl %%ic,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "cmpa%.l %%a0,%%a1\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : /* no return */ ++ : "a" (__pa(vstart)), "a" (__pa(vend)), ++ "r" (shadow_cacr), ++ "i" (CF_CACR_SPA) ++ : "a0", "a1", "d0"); ++} ++ ++/** ++ * flush_cache_mm - Flush an mm_struct ++ * @mm: mm_struct to flush ++ */ ++static inline void flush_cache_mm(struct mm_struct *mm) ++{ ++ if (mm == current->mm) ++ flush_bcache(); ++} ++ ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) ++ ++/** ++ * flush_cache_range - Flush a cache range ++ * @vma: vma struct ++ * @start: Starting address ++ * @end: Ending address ++ * ++ * flush_cache_range must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_range(struct vm_area_struct *vma, ++ unsigned long start, unsigned long end) ++{ ++ if (vma->vm_mm == current->mm) ++ cf_cache_flush_range(start, end); ++} ++ ++/** ++ * flush_cache_page - Flush a page of the cache ++ * @vma: vma struct ++ * @vmaddr: ++ * @pfn: page numer ++ * ++ * flush_cache_page must be a macro to avoid a dependency on ++ * linux/mm.h which includes this file. ++ */ ++static inline void flush_cache_page(struct vm_area_struct *vma, ++ unsigned long vmaddr, unsigned long pfn) ++{ ++ if (vma->vm_mm == current->mm) ++ cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE); ++} ++ ++/** ++ * __flush_page_to_ram - Push a page out of the cache ++ * @vaddr: Virtual address at start of page ++ * ++ * Push the page at kernel virtual address *vaddr* and clear ++ * the icache. ++ */ ++static inline void __flush_page_to_ram(void *vaddr) ++{ ++ asm volatile("nop\n" ++ "move%.l %2,%%d0\n" ++ "or%.l %3,%%d0\n" ++ "movec %%d0,%%cacr\n" ++ "move%.l %0,%%d0\n" ++ "and%.l #0xfffffff0,%%d0\n" ++ "move%.l %%d0,%%a0\n" ++ "move%.l %1,%%d0\n" ++ "1:\n" ++ "cpushl %%bc,(%%a0)\n" ++ "lea 0x10(%%a0),%%a0\n" ++ "subq%.l #1,%%d0\n" ++ "bne.b 1b\n" ++ "movec %2,%%cacr\n" ++ : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE), ++ "r" (shadow_cacr), "i" (CF_CACR_SPA) ++ : "a0", "d0"); ++} ++ ++/* ++ * Various defines for the kernel. ++ */ ++ ++extern void cache_clear(unsigned long paddr, int len); ++extern void cache_push(unsigned long paddr, int len); ++extern void flush_icache_range(unsigned long address, unsigned long endaddr); ++ ++#define flush_cache_all() flush_bcache() ++#define flush_cache_vmap(start, end) flush_bcache() ++#define flush_cache_vunmap(start, end) flush_bcache() ++ ++#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend) ++#define flush_dcache_page(page) __flush_page_to_ram(page_address(page)) ++#define flush_dcache_mmap_lock(mapping) do { } while (0) ++#define flush_dcache_mmap_unlock(mapping) do { } while (0) ++ ++#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page)) ++ ++/** ++ * copy_to_user_page - Copy memory to user page ++ */ ++static inline void copy_to_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ memcpy(dst, src, len); ++ cf_cache_flush(page_to_phys(page), PAGE_SIZE); ++} ++ ++/** ++ * copy_from_user_page - Copy memory from user page ++ */ ++static inline void copy_from_user_page(struct vm_area_struct *vma, ++ struct page *page, unsigned long vaddr, ++ void *dst, void *src, int len) ++{ ++ cf_cache_flush(page_to_phys(page), PAGE_SIZE); ++ memcpy(dst, src, len); ++} ++ ++#endif /* M68K_CF_5441x_CACHEFLUSH_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_ccm.h +@@ -0,0 +1,157 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_CCM_H__ ++#define __MCF5441X_CCM_H__ ++ ++/********************************************************************* ++* ++* Chip Configuration Module (CCM) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */ ++#define MCF_CCM_CCR MCF_REG16(0xEC090004) ++/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */ ++#define MCF_CCM_RCON MCF_REG16(0xEC090008) ++/* Chip Identification Register (Read-only) */ ++#define MCF_CCM_CIR MCF_REG16(0xEC09000A) ++/* Miscellaneous Control Register */ ++#define MCF_CCM_MISCCR MCF_REG16(0xEC09000E) ++#define MCF_CCM_CDRH MCF_REG16(0xEC090010) /* Clock Divider Register */ ++#define MCF_CCM_CDRL MCF_REG16(0xEC090012) /* Clock Divider Register */ ++/* USB On-the-Go Controller Status Register */ ++#define MCF_CCM_UOCSR MCF_REG16(0xEC090014) ++/* USB On-the-Go Controller Status Register */ ++#define MCF_CCM_UHCSR MCF_REG16(0xEC090016) ++/* Miscellaneous Control Register */ ++#define MCF_CCM_MISCCR3 MCF_REG16(0xEC090018) ++/* Miscellaneous Control Register */ ++#define MCF_CCM_MISCCR2 MCF_REG16(0xEC09001A) ++#define MCF_CCM_ADCTSR MCF_REG16(0xEC09001C) ++#define MCF_CCM_DACTSR MCF_REG16(0xEC09001E) ++/* Serial Boot Facility Status Register (Read Only) */ ++#define MCF_CCM_SBFSR MCF_REG16(0xEC090020) ++/* Serial Boot Facility Control Register */ ++#define MCF_CCM_SBFCR MCF_REG16(0xEC090022) ++#define MCF_CCM_FNACR MCF_REG16(0xEC090024) ++ ++/* Bit definitions and macros for CIR */ ++/* Part revision number */ ++#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) ++/* Part identification number */ ++#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) ++#define MCF_CCM_CIR_PIN_MASK (0xFFC0) ++#define MCF_CCM_CIR_PRN_MASK (0x003F) ++#define MCF_CCM_CIR_PIN_MCF54410 (0x9F<<6) ++#define MCF_CCM_CIR_PIN_MCF54415 (0xA0<<6) ++#define MCF_CCM_CIR_PIN_MCF54416 (0xA1<<6) ++#define MCF_CCM_CIR_PIN_MCF54417 (0xA2<<6) ++#define MCF_CCM_CIR_PIN_MCF54418 (0xA3<<6) ++ ++/* Bit definitions and macros for MISCCR */ ++/* Part revision number */ ++#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) ++/* Part identification number */ ++#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) ++#define MCF_CCM_CIR_PIN_MASK (0xFFC0) ++#define MCF_CCM_CIR_PRN_MASK (0x003F) ++#define MCF_CCM_CIR_PIN_MCF54410 (0x9F<<6) ++#define MCF_CCM_CIR_PIN_MCF54415 (0xA0<<6) ++#define MCF_CCM_CIR_PIN_MCF54416 (0xA1<<6) ++#define MCF_CCM_CIR_PIN_MCF54417 (0xA2<<6) ++#define MCF_CCM_CIR_PIN_MCF54418 (0xA3<<6) ++#define MCF_CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14) ++#define MCF_CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF) ++#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000) ++#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000) ++#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000) ++#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000) ++#define MCF_CCM_MISCCR_LIMP (0x1000) ++#define MCF_CCM_MISCCR_BME (0x0800) ++#define MCF_CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) ++#define MCF_CCM_MISCCR_BMT_MASK (0xF8FF) ++#define MCF_CCM_MISCCR_BMT_65536 (0) ++#define MCF_CCM_MISCCR_BMT_32768 (1) ++#define MCF_CCM_MISCCR_BMT_16384 (2) ++#define MCF_CCM_MISCCR_BMT_8192 (3) ++#define MCF_CCM_MISCCR_BMT_4096 (4) ++#define MCF_CCM_MISCCR_BMT_2048 (5) ++#define MCF_CCM_MISCCR_BMT_1024 (6) ++#define MCF_CCM_MISCCR_BMT_512 (7) ++#define MCF_CCM_MISCCR_SDHCSRC (0x0040) ++#define MCF_CCM_MISCCR_SSI1SRC (0x0020) ++#define MCF_CCM_MISCCR_SSI0SRC (0x0010) ++#define MCF_CCM_MISCCR_USBHOC (0x0008) ++#define MCF_CCM_MISCCR_USBOOC (0x0004) ++#define MCF_CCM_MISCCR_USBPUE (0x0002) ++#define MCF_CCM_MISCCR_USBSRC (0x0001) ++#define MCF_CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8) ++#define MCF_CCM_CDRH_SSI0DIV_MASK (0x00FF) ++#define MCF_CCM_CDRH_SSI1DIV(x) (((x)&0x00FF)) ++#define MCF_CCM_CDRH_SSI1DIV_MASK (0xFF00) ++#define MCF_CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8) ++#define MCF_CCM_CDRL_LPDIV_MASK (0xFF0F) ++#define MCF_CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x) ++ ++#define MCF_CCM_UOCSR_DPPD (0x2000) ++#define MCF_CCM_UOCSR_DMPD (0x1000) ++#define MCF_CCM_UOCSR_DRV_VBUS (0x0800) ++#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) ++#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) ++#define MCF_CCM_UOCSR_DPPU (0x0100) ++#define MCF_CCM_UOCSR_AVLD (0x0080) ++#define MCF_CCM_UOCSR_BVLD (0x0040) ++#define MCF_CCM_UOCSR_VVLD (0x0020) ++#define MCF_CCM_UOCSR_SEND (0x0010) ++#define MCF_CCM_UOCSR_PWRFLT (0x0008) ++#define MCF_CCM_UOCSR_WKUP (0x0004) ++#define MCF_CCM_UOCSR_UOMIE (0x0002) ++#define MCF_CCM_UOCSR_XPDE (0x0001) ++ ++#define MCF_CCM_UHCSR_DRV_VBUS (0x0010) ++#define MCF_CCM_UHCSR_PWRFLT (0x0008) ++#define MCF_CCM_UHCSR_WKUP (0x0004) ++#define MCF_CCM_UHCSR_UOMIE (0x0002) ++#define MCF_CCM_UHCSR_XPDE (0x0001) ++ ++#define MCF_CCM_MISCCR3_TMR_ENET (0x1000) ++#define MCF_CCM_MISCCR3_ENETCLK(x) ((((x)&7))<<8) ++#define MCF_CCM_MISCCR3_ENETCLK_MASK (0xF8FF) ++#define MCF_CCM_MISCCR3_ENETCLK_MII (0x0700) ++#define MCF_CCM_MISCCR3_ENETCLK_OSC (0x0600) ++#define MCF_CCM_MISCCR3_ENETCLK_USB (0x0500) ++#define MCF_CCM_MISCCR3_ENETCLK_TMR3 (0x0400) ++#define MCF_CCM_MISCCR3_ENETCLK_TMR2 (0x0300) ++#define MCF_CCM_MISCCR3_ENETCLK_TMR1 (0x0200) ++#define MCF_CCM_MISCCR3_ENETCLK_TMR0 (0x0100) ++#define MCF_CCM_MISCCR3_ENETCLK_INTBUS (0x0000) ++ ++#define MCF_CCM_MISCCR2_EXTCLKBYP (0x0800) ++#define MCF_CCM_MISCCR2_DDR2CLK (0x0400) ++#define MCF_CCM_MISCCR2_RGPIO_HALF (0x0200) ++#define MCF_CCM_MISCCR2_SWTSCR (0x0100) ++#define MCF_CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8) ++#define MCF_CCM_MISCCR2_PLLMODE_MASK (0xF8FF) ++#define MCF_CCM_MISCCR2_DCCBYP (0x0080) ++#define MCF_CCM_MISCCR2_DAC1SEL (0x0040) ++#define MCF_CCM_MISCCR2_DAC0SEL (0x0020) ++#define MCF_CCM_MISCCR2_ADCEN (0x0010) ++#define MCF_CCM_MISCCR2_ADC7SEL (0x0008) ++#define MCF_CCM_MISCCR2_ADC3SEL (0x0004) ++#define MCF_CCM_MISCCR2_FBHALF (0x0002) ++#define MCF_CCM_MISCCR2_ULPI (0x0001) ++ ++#define MCF_CCM_FNACR_PCR(x) (((x)&0x0F)<<24) ++#define MCF_CCM_FNACR_PCR_MASK (0xF0FFFFFF) ++#define MCF_CCM_FNACR_MCC(x) ((x)&0xFFFF) ++#define MCF_CCM_FNACR_MCC_MASK (0xFFFF0000) ++ ++#endif /* __MCF5445X_CCM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_clock.h +@@ -0,0 +1,22 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_CLOCK_H__ ++#define __MCF5441X_CLOCK_H__ ++ ++#define MCF_PLL_CR MCF_REG32(0xFC000000) ++#define MCF_PLL_DR MCF_REG32(0xFC000004) ++#define MCF_PLL_SR MCF_REG32(0xFC000008) ++ ++#define MCF_PLL_DR_OUTDIV4 0x001F0000 ++#define MCF_PLL_DR_OUTDIV1 0x1F ++ ++ ++#endif /*__MCF5441X_CLOCK_H__*/ ++ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_dspi.h +@@ -0,0 +1,671 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Lanttor.Guo@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_DSPI_H__ ++#define __MCF5441X_DSPI_H__ ++ ++/********************************************************************* ++* ++* DMA Serial Peripheral Interface (DSPI) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* DSPI Module Configuration Register */ ++#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) ++#define MCF_DSPI1_DMCR MCF_REG32(0xFC03C000) ++/* DSPI Transfer Count Register */ ++#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) ++#define MCF_DSPI1_DTCR MCF_REG32(0xFC03C008) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) ++#define MCF_DSPI1_DCTAR0 MCF_REG32(0xFC03C00C) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028 ++/* DSPI Status Register */ ++#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) ++#define MCF_DSPI1_DSR MCF_REG32(0xFC03C02C) ++/* DSPI DMA/Interrupt Request Select and Enable Register */ ++#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) ++#define MCF_DSPI1_DRSER MCF_REG32(0xFC03C030) ++/* DSPI Transmit FIFO Register */ ++#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) ++#define MCF_DSPI1_DTFR MCF_REG32(0xFC03C034) ++/* DSPI Receive FIFO Register */ ++#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) ++#define MCF_DSPI1_DRFR MCF_REG32(0xFC03C038) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* DSPI Clock and Transfer Attributes Register */ ++#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) ++/* DSPI Transmit FIFO Debugging Registers */ ++#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) ++/* DSPI Receive FIFO Debugging Registers */ ++#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) ++ ++/* Bit definitions and macros for DMCR */ ++/* Halt -- stops and starts DSPI transfers */ ++#define MCF_DSPI_DMCR_HALT (0x00000001) ++/* Sample point selection */ ++#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) ++/* Clear receive FIFO */ ++#define MCF_DSPI_DMCR_CLRRXF (0x00000400) ++/* Clear transmit FIFO */ ++#define MCF_DSPI_DMCR_CLRTXF (0x00000800) ++/* Disable receive FIFO */ ++#define MCF_DSPI_DMCR_DISRXF (0x00001000) ++/* Disable transmit FIFO */ ++#define MCF_DSPI_DMCR_DISTXF (0x00002000) ++/* Module Disable */ ++#define MCF_DSPI_DMCR_MDIS (0x00004000) ++/* Peripheral chip-select 0 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) ++/* Peripheral chip-select 1 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) ++/* Peripheral chip-select 2 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) ++/* Peripheral chip-select 3 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) ++/* Peripheral chip-select 4 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) ++/* Peripheral chip-select 5 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) ++/* Peripheral chip-select 6 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) ++/* Peripheral chip-select 7 inactive state */ ++#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) ++/* Receive FIFO overflow overwrite enable */ ++#define MCF_DSPI_DMCR_ROOE (0x01000000) ++/* Peripheral chip select strobe enable */ ++#define MCF_DSPI_DMCR_PCSSE (0x02000000) ++/* Modified timing format enable */ ++#define MCF_DSPI_DMCR_MTFE (0x04000000) ++/* Freeze */ ++#define MCF_DSPI_DMCR_FRZ (0x08000000) ++/* DSPI configuration */ ++#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) ++/* Continuous SCK enable */ ++#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) ++/* Master/Slave mode select */ ++#define MCF_DSPI_DMCR_MSTR (0x80000000) ++#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000) ++#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000) ++#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000) ++#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000) ++#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000) ++#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000) ++#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000) ++#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000) ++#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000) ++ ++/* Bit definitions and macros for DTCR */ ++/* SPI transfer count */ ++#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for DCTAR group */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR_DBR (0x80000000) ++#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000) ++#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000) ++#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000) ++#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000) ++#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000) ++#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000) ++#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000) ++#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for DCTAR0 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR0_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR0_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR0_DBR (0x80000000) ++#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000) ++#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000) ++#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000) ++#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000) ++#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000) ++#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000) ++#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000) ++#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000) ++#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000) ++#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000) ++#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000) ++#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000) ++#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000) ++#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000) ++#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000) ++#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000) ++#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000) ++ ++/* Bit definitions and macros for DCTAR1 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR1_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR1_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR1_DBR (0x80000000) ++ ++ ++/* Bit definitions and macros for DCTAR2 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR2_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR2_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR2_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR3 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR3_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR3_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR3_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR4 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR4_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR4_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR4_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR5 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR5_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR5_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR5_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR6 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR6_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR6_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR6_DBR (0x80000000) ++ ++/* Bit definitions and macros for DCTAR7 */ ++/* Baud rate scaler */ ++#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) ++/* Delay after transfer scaler */ ++#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) ++/* After SCK delay scaler */ ++#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) ++/* PCS to SCK delay scaler */ ++#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) ++/* Baud rate prescaler */ ++#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) ++/* Delay after transfer prescaler */ ++#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) ++/* After SCK delay prescaler */ ++#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) ++/* PCS to SCK delay prescaler */ ++#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) ++/* LSB first enable */ ++#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) ++/* Clock phase */ ++#define MCF_DSPI_DCTAR7_CPHA (0x02000000) ++/* Clock polarity */ ++#define MCF_DSPI_DCTAR7_CPOL (0x04000000) ++/* Frame size */ ++#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) ++/* Double baud rate */ ++#define MCF_DSPI_DCTAR7_DBR (0x80000000) ++ ++/* Bit definitions and macros for DSR */ ++/* Receive next pointer */ ++#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) ++/* Receive FIFO counter */ ++#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) ++/* Transmit next pointer */ ++#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) ++/* Transmit FIFO counter */ ++#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) ++/* Receive FIFO drain flag */ ++#define MCF_DSPI_DSR_RFDF (0x00020000) ++/* Receive FIFO overflow flag */ ++#define MCF_DSPI_DSR_RFOF (0x00080000) ++/* Transmit FIFO fill flag */ ++#define MCF_DSPI_DSR_TFFF (0x02000000) ++/* Transmit FIFO underflow flag */ ++#define MCF_DSPI_DSR_TFUF (0x08000000) ++/* End of queue flag */ ++#define MCF_DSPI_DSR_EOQF (0x10000000) ++/* Tx and Rx status (enabled | disabled) */ ++#define MCF_DSPI_DSR_TXRXS (0x40000000) ++/* Transfer complete flag */ ++#define MCF_DSPI_DSR_TCF (0x80000000) ++ ++/* Bit definitions and macros for DRSER */ ++/* Receive FIFO drain DMA or interrupt select */ ++#define MCF_DSPI_DRSER_RFDFS (0x00010000) ++/* Receive FIFO drain request enable */ ++#define MCF_DSPI_DRSER_RFDFE (0x00020000) ++/* Receive FIFO overflow request enable */ ++#define MCF_DSPI_DRSER_RFOFE (0x00080000) ++/* Transmit FIFO fill DMA or interrupt select */ ++#define MCF_DSPI_DRSER_TFFFS (0x01000000) ++/* Transmit FIFO fill request enable */ ++#define MCF_DSPI_DRSER_TFFFE (0x02000000) ++/* Transmit FIFO underflow request enable */ ++#define MCF_DSPI_DRSER_TFUFE (0x08000000) ++/* DSPI finished request enable */ ++#define MCF_DSPI_DRSER_EOQFE (0x10000000) ++/* Transmission complete request enable */ ++#define MCF_DSPI_DRSER_TCFE (0x80000000) ++ ++/* Bit definitions and macros for DTFR */ ++/* Transmit data */ ++#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFR_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFR_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFR_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFR_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFR_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFR_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFR_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFR_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFR_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFR_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFR_CONT (0x80000000) ++ ++/* Bit definitions and macros for DRFR */ ++/* Receive data */ ++#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DTFDR group */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS0 (0x00010000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS1 (0x00020000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS2 (0x00040000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS3 (0x00080000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS4 (0x00100000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS5 (0x00200000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS6 (0x00400000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR0 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR0_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR0_CONT (0x80000000) ++/* Bit definitions and macros for DTFDR1 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR1_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR1_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR2 */ ++#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR2_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR2_CONT (0x80000000) ++ ++/* Bit definitions and macros for DTFDR3 */ ++/* Transmit data */ ++#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) ++/* Peripheral chip select 0 */ ++#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) ++/* Peripheral chip select 1 */ ++#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) ++/* Peripheral chip select 2 */ ++#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) ++/* Peripheral chip select 3 */ ++#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) ++/* Peripheral chip select 4 */ ++#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) ++/* Peripheral chip select 5 */ ++#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) ++/* Peripheral chip select 6 */ ++#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) ++/* Peripheral chip select 7 */ ++#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) ++/* Clear SPI transfer counter */ ++#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) ++/* End of queue */ ++#define MCF_DSPI_DTFDR3_EOQ (0x08000000) ++/* Clock and transfer attributes select */ ++#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) ++/* Continuous peripheral chip-select enable */ ++#define MCF_DSPI_DTFDR3_CONT (0x80000000) ++ ++/* Bit definitions and macros for DRFDR group */ ++#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR0 */ ++#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR1 */ ++#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR2 */ ++#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/* Bit definitions and macros for DRFDR3 */ ++#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_DSPI_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_dtim.h +@@ -0,0 +1,95 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_DTIM_H__ ++#define __MCF5441X_DTIM_H__ ++ ++/********************************************************************* ++* ++* DMA Timers (DTIM) ++* ++*********************************************************************/ ++/* Register read/write macros */ ++#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */ ++#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */ ++#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */ ++#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */ ++#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */ ++#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */ ++#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */ ++#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */ ++#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */ ++#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */ ++#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */ ++#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */ ++#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */ ++#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */ ++#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */ ++#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */ ++#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */ ++#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */ ++#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */ ++#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */ ++#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */ ++ ++/* Parameterized register read/write macros for multiple modules */ ++/* DMA Timer Mode Register */ ++#define MCF_DTIM_DTMR(x) (0xFC070000+((x)*0x4000)) ++/* DMA Timer Extended Mode Register */ ++#define MCF_DTIM_DTXMR(x) (0xFC070002+((x)*0x4000)) ++/* DMA Timer Event Register */ ++#define MCF_DTIM_DTER(x) (0xFC070003+((x)*0x4000)) ++/* DMA Timer Reference Register */ ++#define MCF_DTIM_DTRR(x) (0xFC070004+((x)*0x4000)) ++/* DMA Timer Capture Register */ ++#define MCF_DTIM_DTCR(x) (0xFC070008+((x)*0x4000)) ++/* DMA Timer Counter Register */ ++#define MCF_DTIM_DTCN(x) (0xFC07000C+((x)*0x4000)) ++ ++/* Bit definitions and macros for DTMR */ ++#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */ ++#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ ++#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */ ++/* Output reference request/interrupt enable */ ++#define MCF_DTIM_DTMR_ORRI (0x0010) ++#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */ ++#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ ++#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ ++#define MCF_DTIM_DTMR_RST_EN (0x0001) ++#define MCF_DTIM_DTMR_RST_RST (0x0000) ++#define MCF_DTIM_DTMR_CE_ANY (0x00C0) ++#define MCF_DTIM_DTMR_CE_FALL (0x0080) ++#define MCF_DTIM_DTMR_CE_RISE (0x0040) ++#define MCF_DTIM_DTMR_CE_NONE (0x0000) ++#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) ++#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) ++#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) ++#define MCF_DTIM_DTMR_CLK_STOP (0x0000) ++ ++/* Bit definitions and macros for DTXMR */ ++#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ ++#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */ ++#define MCF_DTIM_DTXMR_1588EN (0x20) /* Enable 1588 mode*/ ++ ++/* Bit definitions and macros for DTER */ ++#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */ ++#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */ ++ ++/* Interrupts used for system timers */ ++#define MCFSIM_ICR_TIMER0 (0xFC048040+32) ++#define MCFSIM_ICR_TIMER1 (0xFC048040+33) ++#define MCFSIM_ICR_TIMER2 (0xFC048040+34) ++#define MCFSIM_ICR_TIMER3 (0xFC048040+35) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_DTIM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_edma.h +@@ -0,0 +1,303 @@ ++/* mcf5441x_edma.h ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Lanttor.Guo@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef __MCF5441X_EDMA_H__ ++#define __MCF5441X_EDMA_H__ ++ ++/* ++ * Enhanced DMA (EDMA) ++ */ ++ ++/* Channels */ ++#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */ ++#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */ ++#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */ ++#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */ ++#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */ ++#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */ ++#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */ ++#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */ ++#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */ ++#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */ ++#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */ ++#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */ ++#define MCF_EDMA_CHAN_DSPI0_RX 12 /* DSPI0 Receive */ ++#define MCF_EDMA_CHAN_DSPI0_TX 13 /* DSPI0 Transmit */ ++#define MCF_EDMA_CHAN_DSPI1_RX 14 /* DSPI1 Receive */ ++#define MCF_EDMA_CHAN_DSPI1_TX 15 /* DSPI1 Transmit */ ++#define MCF_EDMA_CHAN_UART3_RX 16 /* UART3 Receive */ ++#define MCF_EDMA_CHAN_UART3_TX 17 /* UART3 Transmit */ ++#define MCF_EDMA_CHAN_UART4_RX 18 /* UART4 Receive */ ++#define MCF_EDMA_CHAN_UART4_TX 19 /* UART4 Transmit */ ++#define MCF_EDMA_CHAN_UART5_RX 20 /* UART5 Receive */ ++#define MCF_EDMA_CHAN_UART5_TX 21 /* UART5 Transmit */ ++#define MCF_EDMA_CHAN_UART6_RX 22 /* UART6 Receive */ ++#define MCF_EDMA_CHAN_UART6_TX 23 /* UART6 Transmit */ ++#define MCF_EDMA_CHAN_I2C0 24 /* I2C0 */ ++#define MCF_EDMA_CHAN_I2C1 25 /* I2C1 */ ++#define MCF_EDMA_CHAN_I2C2 26 /* I2C2 */ ++#define MCF_EDMA_CHAN_I2C3 27 /* I2C3 */ ++#define MCF_EDMA_CHAN_DSPI2_RX 28 /* DSPI2 Receive */ ++#define MCF_EDMA_CHAN_DSPI2_TX 29 /* DSPI2 Transmit */ ++#define MCF_EDMA_CHAN_N0 30 /* Available for software */ ++#define MCF_EDMA_CHAN_N1 31 /* Available for software */ ++#define MCF_EDMA_CHAN_UART7_RX 32 /* UART7 Receive */ ++#define MCF_EDMA_CHAN_UART7_TX 33 /* UART7 Transmit */ ++#define MCF_EDMA_CHAN_UART8_RX 34 /* UART8 Receive */ ++#define MCF_EDMA_CHAN_UART8_TX 35 /* UART8 Transmit */ ++#define MCF_EDMA_CHAN_UART9_RX 36 /* UART9 Receive */ ++#define MCF_EDMA_CHAN_UART9_TX 37 /* UART9 Transmit */ ++#define MCF_EDMA_CHAN_OW 38 /* 1-Wire */ ++#define MCF_EDMA_CHAN_RESERVED 39 /* Reserved */ ++#define MCF_EDMA_CHAN_I2C4 40 /* I2C4 */ ++#define MCF_EDMA_CHAN_I2C5 41 /* I2C5 */ ++#define MCF_EDMA_CHAN_N2 42 /* Available for software */ ++#define MCF_EDMA_CHAN_N3 43 /* Available for software */ ++#define MCF_EDMA_CHAN_DSPI3_RX 44 /* DSPI3 Receive */ ++#define MCF_EDMA_CHAN_DSPI3_TX 45 /* DSPI3 Transmit */ ++#define MCF_EDMA_CHAN_SSI0_RX0 48 /* SSI0 Receive 0 */ ++#define MCF_EDMA_CHAN_SSI0_RX1 49 /* SSI0 Receive 1 */ ++#define MCF_EDMA_CHAN_SSI0_TX0 50 /* SSI0 Transmit 0 */ ++#define MCF_EDMA_CHAN_SSI0_TX1 51 /* SSI0 Transmit 1 */ ++#define MCF_EDMA_CHAN_SSI1_RX0 52 /* SSI1 Receive 0 */ ++#define MCF_EDMA_CHAN_SSI1_RX1 53 /* SSI1 Receive 1 */ ++#define MCF_EDMA_CHAN_SSI1_TX0 54 /* SSI1 Transmit 0 */ ++#define MCF_EDMA_CHAN_SSI1_TX1 55 /* SSI1 Transmit 1 */ ++#define MCF_EDMA_CHAN_PWM_CAP 56 /* PWM Capture */ ++#define MCF_EDMA_CHAN_PWM_VAL 57 /* PWM Value */ ++#define MCF_EDMA_CHAN_RESERVED2 58 /* Reserved */ ++#define MCF_EDMA_CHAN_ESDHC 59 /* eSDHC */ ++#define MCF_EDMA_CHAN_ADC0 60 /* ADC 0 */ ++#define MCF_EDMA_CHAN_ADC1 61 /* ADC 1 */ ++#define MCF_EDMA_CHAN_DAC0 62 /* DAC 0 */ ++#define MCF_EDMA_CHAN_DAC1 63 /* DAC 1 */ ++ ++/* Register read/write macros */ ++#define MCF_EDMA_CR MCF_REG32(0xFC044000) ++#define MCF_EDMA_ES MCF_REG32(0xFC044004) ++#define MCF_EDMA_ERQH MCF_REG32(0xFC044008) ++#define MCF_EDMA_ERQL MCF_REG32(0xFC04400C) ++#define MCF_EDMA_EEIH MCF_REG32(0xFC044010) ++#define MCF_EDMA_EEIL MCF_REG32(0xFC044014) ++#define MCF_EDMA_SERQ MCF_REG08(0xFC044018) ++#define MCF_EDMA_CERQ MCF_REG08(0xFC044019) ++#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A) ++#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B) ++#define MCF_EDMA_CINT MCF_REG08(0xFC04401C) ++#define MCF_EDMA_CERR MCF_REG08(0xFC04401D) ++#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E) ++#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F) ++#define MCF_EDMA_INTH MCF_REG32(0xFC044020) ++#define MCF_EDMA_INTL MCF_REG32(0xFC044024) ++#define MCF_EDMA_ERRH MCF_REG32(0xFC044028) ++#define MCF_EDMA_ERRL MCF_REG32(0xFC04402C) ++#define MCF_EDMA_RSH MCF_REG32(0xFC044030) ++#define MCF_EDMA_RSL MCF_REG32(0xFC044034) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001)) ++#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020)) ++#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020)) ++#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020)) ++#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020)) ++#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020)) ++#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020)) ++#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020)) ++#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020)) ++#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020)) ++#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020)) ++#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020)) ++#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020)) ++#define MCF_EDMA_TCD_CSR(x) MCF_REG16((0xFC04501e)+((x)*0x020)) ++ ++/* Bit definitions and macros for CR */ ++#define MCF_EDMA_CR_EDBG (0x00000002) ++#define MCF_EDMA_CR_ERCA (0x00000004) ++#define MCF_EDMA_CR_ERGA (0x00000008) ++#define MCF_EDMA_CR_HOE (0x00000010) ++#define MCF_EDMA_CR_HALT (0x00000020) ++#define MCF_EDMA_CR_CLM (0x00000040) ++#define MCF_EDMA_CR_EMLM (0x00000080) ++#define MCF_EDMA_CR_GRP0PRI(x) (((x)&0x03)<<8) ++#define MCF_EDMA_CR_GRP1PRI(x) (((x)&0x03)<<10) ++#define MCF_EDMA_CR_GRP2PRI(x) (((x)&0x03)<<12) ++#define MCF_EDMA_CR_GRP3PRI(x) (((x)&0x03)<<14) ++#define MCF_EDMA_CR_ECX (0x00010000) ++#define MCF_EDMA_CR_CX (0x00020000) ++ ++/* Bit definitions and macros for ES */ ++#define MCF_EDMA_ES_DBE (0x00000001) ++#define MCF_EDMA_ES_SBE (0x00000002) ++#define MCF_EDMA_ES_SGE (0x00000004) ++#define MCF_EDMA_ES_NCE (0x00000008) ++#define MCF_EDMA_ES_DOE (0x00000010) ++#define MCF_EDMA_ES_DAE (0x00000020) ++#define MCF_EDMA_ES_SOE (0x00000040) ++#define MCF_EDMA_ES_SAE (0x00000080) ++#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000003F)<<8) ++#define MCF_EDMA_ES_CPE (0x00004000) ++#define MCF_EDMA_ES_GPE (0x00008000) ++#define MCF_EDMA_ES_ECX (0x00010000) ++#define MCF_EDMA_ES_VLD (0x80000000) ++ ++/* Bit definitions and macros for ERQ: 0~63 bits */ ++#define MCF_EDMA_ERQ_ERQH(x) (0x01<<x) /*32~63*/ ++#define MCF_EDMA_ERQ_ERQL(x) (0x01<<x) /*0~31*/ ++ ++/* Bit definitions and macros for EEI: 0~63 bits */ ++#define MCF_EDMA_EEI_EEIH(x) (0x01<<x) /*32~63*/ ++#define MCF_EDMA_EEI_EEIL(x) (0x01<<x) /*0~31*/ ++ ++/* Bit definitions and macros for SERQ */ ++#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x3F)) ++#define MCF_EDMA_SERQ_SAER (0x40) ++#define MCF_EDMA_SERQ_NOP (0x80) ++ ++/* Bit definitions and macros for CERQ */ ++#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x3F)) ++#define MCF_EDMA_CERQ_CAER (0x40) ++#define MCF_EDMA_CERQ_NOP (0x80) ++ ++/* Bit definitions and macros for SEEI */ ++#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x3F)) ++#define MCF_EDMA_SEEI_SAEE (0x40) ++#define MCF_EDMA_SEEI_NOP (0x80) ++ ++/* Bit definitions and macros for CEEI */ ++#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x3F)) ++#define MCF_EDMA_CEEI_CAEE (0x40) ++#define MCF_EDMA_CEEI_NOP (0x80) ++ ++/* Bit definitions and macros for CINT */ ++#define MCF_EDMA_CINT_CINT(x) (((x)&0x3F)) ++#define MCF_EDMA_CINT_CAIR (0x40) ++#define MCF_EDMA_CINT_NOP (0x80) ++ ++/* Bit definitions and macros for CERR */ ++#define MCF_EDMA_CERR_CERR(x) (((x)&0x3F)) ++#define MCF_EDMA_CERR_CAER (0x40) ++#define MCF_EDMA_CERR_NOP (0x80) ++ ++/* Bit definitions and macros for SSRT */ ++#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x3F)) ++#define MCF_EDMA_SSRT_SAST (0x40) ++#define MCF_EDMA_SSRT_NOP (0x80) ++ ++/* Bit definitions and macros for CDNE */ ++#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x3F)) ++#define MCF_EDMA_CDNE_CADN (0x40) ++#define MCF_EDMA_CDNE_NOP (0x80) ++ ++/* Bit definitions and macros for INTR: 0~63 bits */ ++#define MCF_EDMA_INTR_INTH(x) (0x01<<x) /*32~63*/ ++#define MCF_EDMA_INTR_INTL(x) (0x01<<x) /*0~31*/ ++ ++/* Bit definitions and macros for ERR: 0~63 bits */ ++#define MCF_EDMA_ERR_ERRH(x) (0x01<<x) /*32~63*/ ++#define MCF_EDMA_ERR_ERRL(x) (0x01<<x) /*0~31*/ ++ ++/* Bit defineitions and macros for HRSH/HRSL */ ++#define MCF_EDMA_HRS_HRSH(x) (0x01<<x) /*32~63*/ ++#define MCF_EDMA_HRS_HRSL(x) (0x01<<x) /*0~31*/ ++ ++/* Bit definitions and macros for DCHPRI group */ ++#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)) ++#define MCF_EDMA_DCHPRI_GRPPRI(x) (((x)&0x03) << 4) ++#define MCF_EDMA_DCHPRI_DPA (0x40) ++#define MCF_EDMA_DCHPRI_ECP (0x80) ++ ++/* Bit definitions and macros for TCD_SADDR group */ ++#define MCF_EDMA_TCD_SADDR_SADDR(x) (x) ++ ++/* Bit definitions and macros for TCD_ATTR group */ ++#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)) ++#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3) ++#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8) ++#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11) ++#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) ++#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) ++#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) ++#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) ++#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) ++#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) ++#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) ++ ++/* Bit definitions and macros for TCD_SOFF group */ ++#define MCF_EDMA_TCD_SOFF_SOFF(x) (x) ++ ++/* Bit definitions and macros for TCD_NBYTES group */ ++#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x) ++#define MCF_EDMA_TCD_NBYTES_SMLOE (0x80000000) ++#define MCF_EDMA_TCD_NBYTES_DMLOE (0x40000000) ++#define MCF_EDMA_TCD_NBYTES_MLOFF(x) (((x)&0xFFFFF)<<20) ++#define MCF_EDMA_TCD_NBYTES_9BITS ((x)&0x1FF) ++ ++/* Bit definitions and macros for TCD_SLAST group */ ++#define MCF_EDMA_TCD_SLAST_SLAST(x) (x) ++ ++/* Bit definitions and macros for TCD_DADDR group */ ++#define MCF_EDMA_TCD_DADDR_DADDR(x) (x) ++ ++/* Bit definitions and macros for TCD_CITER_ELINK group */ ++#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_CITER group */ ++#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD_CITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_DOFF group */ ++#define MCF_EDMA_TCD_DOFF_DOFF(x) (x) ++ ++/* Bit definitions and macros for TCD_DLAST_SGA group */ ++#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) ++ ++/* Bit definitions and macros for TCD_BITER_ELINK group */ ++#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)) ++#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) ++#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_BITER group */ ++#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)) ++#define MCF_EDMA_TCD_BITER_E_LINK (0x8000) ++ ++/* Bit definitions and macros for TCD_CSR group */ ++#define MCF_EDMA_TCD_CSR_START (0x0001) ++#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14) ++#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000) ++#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000) ++#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000) ++ ++/* Bit definitions and macros for TCD0_CSR */ ++#define MCF_EDMA_TCD0_CSR_START (0x0001) ++#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002) ++#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004) ++#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008) ++#define MCF_EDMA_TCD0_CSR_E_SG (0x0010) ++#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020) ++#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040) ++#define MCF_EDMA_TCD0_CSR_DONE (0x0080) ++#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8) ++#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14) ++#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000) ++#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000) ++#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000) ++ ++#endif /* __MCF5441X_EDMA_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_eport.h +@@ -0,0 +1,94 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_EPORT_H__ ++#define __MCF5441X_EPORT_H__ ++ ++/********************************************************************* ++* ++* Edge Port Module (EPORT) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_EPORT_EPPAR MCF_REG16(0xFC090000) ++#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) ++#define MCF_EPORT_EPIER MCF_REG08(0xFC090003) ++#define MCF_EPORT_EPDR MCF_REG08(0xFC090004) ++#define MCF_EPORT_EPPDR MCF_REG08(0xFC090005) ++#define MCF_EPORT_EPFR MCF_REG08(0xFC090006) ++ ++/* Bit definitions and macros for EPPAR */ ++#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) ++#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) ++#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) ++#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) ++#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) ++#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) ++#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) ++#define MCF_EPORT_EPPAR_LEVEL (0) ++#define MCF_EPORT_EPPAR_RISING (1) ++#define MCF_EPORT_EPPAR_FALLING (2) ++#define MCF_EPORT_EPPAR_BOTH (3) ++#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) ++#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) ++#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) ++#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) ++#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) ++#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) ++#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) ++#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) ++#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) ++#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) ++#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) ++#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) ++#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) ++#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) ++#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) ++#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) ++#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) ++#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) ++#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) ++#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) ++#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) ++#define MCF_EPORT_EPPAR_EPPA0_LEVEL (0x0000) ++#define MCF_EPORT_EPPAR_EPPA0_RISING (0x0001) ++#define MCF_EPORT_EPPAR_EPPA0_FALLING (0x0002) ++#define MCF_EPORT_EPPAR_EPPA0_BOTH (0x0003) ++ ++/* Bit definitions and macros for EPIER */ ++#define MCF_EPORT_EPIER_EPIE0 (0x01) ++#define MCF_EPORT_EPIER_EPIE1 (0x02) ++#define MCF_EPORT_EPIER_EPIE2 (0x04) ++#define MCF_EPORT_EPIER_EPIE3 (0x08) ++#define MCF_EPORT_EPIER_EPIE4 (0x10) ++#define MCF_EPORT_EPIER_EPIE5 (0x20) ++#define MCF_EPORT_EPIER_EPIE6 (0x40) ++#define MCF_EPORT_EPIER_EPIE7 (0x80) ++ ++/* Bit definitions and macros for EPFR */ ++#define MCF_EPORT_EPFR_EPF0 (0x01) ++#define MCF_EPORT_EPFR_EPF1 (0x02) ++#define MCF_EPORT_EPFR_EPF2 (0x04) ++#define MCF_EPORT_EPFR_EPF3 (0x08) ++#define MCF_EPORT_EPFR_EPF4 (0x10) ++#define MCF_EPORT_EPFR_EPF5 (0x20) ++#define MCF_EPORT_EPFR_EPF6 (0x40) ++#define MCF_EPORT_EPFR_EPF7 (0x80) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_EPORT_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_fbcs.h +@@ -0,0 +1,204 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_FBCS_H__ ++#define __MCF5441X_FBCS_H__ ++ ++/********************************************************************* ++* ++* FlexBus Chip Selects (FBCS) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */ ++#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */ ++#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */ ++#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */ ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* Chip-select Addr Register */ ++#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) ++/* Chip-select Mask Register */ ++#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) ++/* Chip-select Cntl Register */ ++#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) ++ ++/* Bit definitions and macros for CSAR group */ ++#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) ++ ++/* Bit definitions and macros for CSAR0 */ ++#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000) ++ ++/* Bit definitions and macros for CSMR group */ ++#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ ++#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) ++#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) ++#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) ++#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) ++#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) ++#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) ++#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) ++#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) ++#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) ++#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) ++#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) ++#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) ++#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) ++#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) ++#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) ++#define MCF_FBCS_CSMR_BAM_512K (0x00070000) ++#define MCF_FBCS_CSMR_BAM_256K (0x00030000) ++#define MCF_FBCS_CSMR_BAM_128K (0x00010000) ++#define MCF_FBCS_CSMR_BAM_64K (0x00000000) ++ ++/* Bit definitions and macros for CSMR0 */ ++#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ ++#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000) ++#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000) ++#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000) ++#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000) ++#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000) ++#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000) ++#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000) ++#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000) ++#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000) ++#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000) ++#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000) ++#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000) ++#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000) ++#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000) ++#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000) ++#define MCF_FBCS_CSMR0_BAM_512K (0x00070000) ++#define MCF_FBCS_CSMR0_BAM_256K (0x00030000) ++#define MCF_FBCS_CSMR0_BAM_128K (0x00010000) ++#define MCF_FBCS_CSMR0_BAM_64K (0x00000000) ++ ++/* Bit definitions and macros for CSCR group */ ++#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR_BLS (0x00000200) /* Byte-lane shift */ ++#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++/* Secondary wait state enable */ ++#define MCF_FBCS_CSCR_SWSEN (0x00800000) ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) ++#define MCF_FBCS_CSCR_PS_8 (0x00000040) ++#define MCF_FBCS_CSCR_PS_16 (0x00000080) ++#define MCF_FBCS_CSCR_PS_32 (0x00000000) ++ ++/* Bit definitions and macros for CSCR0 */ ++#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++/* Secondary wait state enable */ ++#define MCF_FBCS_CSCR0_SWSEN (0x00800000) ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) ++#define MCF_FBCS_CSCR0_PS_8 (0x00000040) ++#define MCF_FBCS_CSCR0_PS_16 (0x00000080) ++#define MCF_FBCS_CSCR0_PS_32 (0x00000000) ++ ++/* Bit definitions and macros for CSMR1 */ ++#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR1 */ ++#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++/* Secondary wait state enable */ ++#define MCF_FBCS_CSCR1_SWSEN (0x00800000) ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) ++ ++/* Bit definitions and macros for CSMR2 */ ++#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR2 */ ++#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++/* Secondary wait state enable */ ++#define MCF_FBCS_CSCR2_SWSEN (0x00800000) ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) ++ ++/* Bit definitions and macros for CSMR3 */ ++#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */ ++#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */ ++#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ ++ ++/* Bit definitions and macros for CSCR3 */ ++#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */ ++#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */ ++#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */ ++#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */ ++#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */ ++#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ ++/* Write address hold or deselect */ ++#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) ++/* Read address hold or deselect */ ++#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) ++#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ ++/* Secondary wait state enable */ ++#define MCF_FBCS_CSCR3_SWSEN (0x00800000) ++/* Secondary wait states */ ++#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_FBCS_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_flexcan.h +@@ -0,0 +1,139 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: Lanttor Guo <b18203@freescale.com> ++ * ++ * This is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef MCF5441X_FLEXCAN_H ++#define MCF5441X_FLEXCAN_H ++/* ++ * FlexCAN Module Configuration Register ++ */ ++#define CANMCR_MDIS (0x80000000) ++#define CANMCR_FRZ (0x40000000) ++#define CANMCR_FEN (0x20000000) ++#define CANMCR_HALT (0x10000000) ++#define CANMCR_SOFTRST (0x02000000) ++#define CANMCR_NOTRDY (0x08000000) ++#define CANMCR_FRZACK (0x01000000) ++#define CANMCR_SUPV (0x00800000) ++#define CANMCR_WARN_EN (0x00200000) ++#define CANMCR_LPMACK (0x00100000) ++#define CANMCR_DOZE (0x00040000) ++#define CANMCR_SRXDIS (0x00020000) ++#define CANMCR_BCC (0x00010000) ++#define CANMCR_LPRIO_EN (0x00002000) ++#define CANMCR_AEN (0x00001000) ++#define CANMCR_IDAM_VAL(x) ((x & 0x3) << 8) ++#define CANMCR_MAXMB (0x0F) ++/* ++ * FlexCAN Control Register ++ */ ++#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) ++#define CANCTRL_RJW(x) (((x)&0x03)<<22) ++#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) ++#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) ++#define CANCTRL_BOFFMSK (0x00008000) ++#define CANCTRL_ERRMSK (0x00004000) ++#define CANCTRL_CLKSRC (0x00002000) ++#define CANCTRL_LPB (0x00001000) ++#define CANCTRL_TWRN_MSK (0x00000800) ++#define CANCTRL_RWRN_MSK (0x00000400) ++#define CANCTRL_SAMP(x) (((x)&0x01)<<7) ++#define CANCTRL_BOFFREC (0x00000040) ++#define CANCTRL_TSYNC (0x00000020) ++#define CANCTRL_LBUF (0x00000010) ++#define CANCTRL_LOM (0x00000008) ++#define CANCTRL_PROPSEG(x) ((x)&0x07) ++ ++/* ++ * FlexCAN Error Counter Register ++ */ ++#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) ++#define ERRCNT_TXECTR(x) ((x)&0xFF) ++ ++/* ++ * FlexCAN Error and Status Register ++ */ ++#define ERRSTAT_TWRN_INT (0x00020000) ++#define ERRSTAT_RWRN_INT (0x00010000) ++#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) ++#define ERRSTAT_ACKERR (0x00002000) ++#define ERRSTAT_CRCERR (0x00001000) ++#define ERRSTAT_FRMERR (0x00000800) ++#define ERRSTAT_STFERR (0x00000400) ++#define ERRSTAT_TXWRN (0x00000200) ++#define ERRSTAT_RXWRN (0x00000100) ++#define ERRSTAT_IDLE (0x00000080) ++#define ERRSTAT_TXRX (0x00000040) ++#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) ++#define ERRSTAT_BOFFINT (0x00000004) ++#define ERRSTAT_ERRINT (0x00000002) ++ ++/* ++ * Interrupt Mask Register ++ */ ++#define IMASK_BUF15M (0x8000) ++#define IMASK_BUF14M (0x4000) ++#define IMASK_BUF13M (0x2000) ++#define IMASK_BUF12M (0x1000) ++#define IMASK_BUF11M (0x0800) ++#define IMASK_BUF10M (0x0400) ++#define IMASK_BUF9M (0x0200) ++#define IMASK_BUF8M (0x0100) ++#define IMASK_BUF7M (0x0080) ++#define IMASK_BUF6M (0x0040) ++#define IMASK_BUF5M (0x0020) ++#define IMASK_BUF4M (0x0010) ++#define IMASK_BUF3M (0x0008) ++#define IMASK_BUF2M (0x0004) ++#define IMASK_BUF1M (0x0002) ++#define IMASK_BUF0M (0x0001) ++#define IMASK_BUFnM(x) (0x1<<(x)) ++#define IMASK_BUFF_ENABLE_ALL (0xFFFF) ++#define IMASK_BUFF_DISABLE_ALL (0x0000) ++ ++/* ++ * Interrupt Flag Register ++ */ ++#define IFLAG_BUF15M (0x8000) ++#define IFLAG_BUF14M (0x4000) ++#define IFLAG_BUF13M (0x2000) ++#define IFLAG_BUF12M (0x1000) ++#define IFLAG_BUF11M (0x0800) ++#define IFLAG_BUF10M (0x0400) ++#define IFLAG_BUF9M (0x0200) ++#define IFLAG_BUF8M (0x0100) ++#define IFLAG_BUF7M (0x0080) ++#define IFLAG_BUF6M (0x0040) ++#define IFLAG_BUF5M (0x0020) ++#define IFLAG_BUF4M (0x0010) ++#define IFLAG_BUF3M (0x0008) ++#define IFLAG_BUF2M (0x0004) ++#define IFLAG_BUF1M (0x0002) ++#define IFLAG_BUF0M (0x0001) ++#define IFLAG_BUFF_SET_ALL (0xFFFF) ++#define IFLAG_BUFF_CLEAR_ALL (0x0000) ++#define IFLAG_BUFnM(x) (0x1<<(x)) ++ ++/* ++ * Message Buffers ++ */ ++#define MB_CNT_CODE(x) (((x)&0x0F)<<24) ++#define MB_CNT_SRR (0x00400000) ++#define MB_CNT_IDE (0x00200000) ++#define MB_CNT_RTR (0x00100000) ++#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) ++#define MB_PRIO(x) (((x)&0x7)<<29) ++#define MB_ID_STD (0x07FF) ++#define MB_ID_EXT (0x1FFFFFFF) ++#define MB_CODE_MASK (0xF0FFFFFF) ++#define CAN_MB 16 ++#define PDEV_MAX 2 ++ ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_gpio.h +@@ -0,0 +1,509 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_GPIO_H__ ++#define __MCF5441X_GPIO_H__ ++ ++/********************************************************************* ++* ++* General Purpose I/O Module (GPIO) ++* ++*********************************************************************/ ++ ++#define MCF_GPIO_PODR_A MCF_REG08(0xEC094000) ++#define MCF_GPIO_PODR_B MCF_REG08(0xEC094001) ++#define MCF_GPIO_PODR_C MCF_REG08(0xEC094002) ++#define MCF_GPIO_PODR_D MCF_REG08(0xEC094003) ++#define MCF_GPIO_PODR_E MCF_REG08(0xEC094004) ++#define MCF_GPIO_PODR_F MCF_REG08(0xEC094005) ++#define MCF_GPIO_PODR_G MCF_REG08(0xEC094006) ++#define MCF_GPIO_PODR_H MCF_REG08(0xEC094007) ++#define MCF_GPIO_PODR_I MCF_REG08(0xEC094008) ++#define MCF_GPIO_PODR_J MCF_REG08(0xEC094009) ++#define MCF_GPIO_PODR_K MCF_REG08(0xEC09400A) ++ ++#define MCF_GPIO_PDDR_A MCF_REG08(0xEC09400C) ++#define MCF_GPIO_PDDR_B MCF_REG08(0xEC09400D) ++#define MCF_GPIO_PDDR_C MCF_REG08(0xEC09400E) ++#define MCF_GPIO_PDDR_D MCF_REG08(0xEC09400F) ++#define MCF_GPIO_PDDR_E MCF_REG08(0xEC094010) ++#define MCF_GPIO_PDDR_F MCF_REG08(0xEC094011) ++#define MCF_GPIO_PDDR_G MCF_REG08(0xEC094012) ++#define MCF_GPIO_PDDR_H MCF_REG08(0xEC094013) ++#define MCF_GPIO_PDDR_I MCF_REG08(0xEC094014) ++#define MCF_GPIO_PDDR_J MCF_REG08(0xEC094015) ++#define MCF_GPIO_PDDR_K MCF_REG08(0xEC094016) ++ ++#define MCF_GPIO_PPDSDR_A MCF_REG08(0xEC094018) ++#define MCF_GPIO_PPDSDR_B MCF_REG08(0xEC094019) ++#define MCF_GPIO_PPDSDR_C MCF_REG08(0xEC09401A) ++#define MCF_GPIO_PPDSDR_D MCF_REG08(0xEC09401B) ++#define MCF_GPIO_PPDSDR_E MCF_REG08(0xEC09401C) ++#define MCF_GPIO_PPDSDR_F MCF_REG08(0xEC09401D) ++#define MCF_GPIO_PPDSDR_G MCF_REG08(0xEC09401E) ++#define MCF_GPIO_PPDSDR_H MCF_REG08(0xEC09401F) ++#define MCF_GPIO_PPDSDR_I MCF_REG08(0xEC094020) ++#define MCF_GPIO_PPDSDR_J MCF_REG08(0xEC094021) ++#define MCF_GPIO_PPDSDR_K MCF_REG08(0xEC094022) ++ ++#define MCF_GPIO_PCLRR_A MCF_REG08(0xEC094024) ++#define MCF_GPIO_PCLRR_B MCF_REG08(0xEC094025) ++#define MCF_GPIO_PCLRR_C MCF_REG08(0xEC094026) ++#define MCF_GPIO_PCLRR_D MCF_REG08(0xEC094027) ++#define MCF_GPIO_PCLRR_E MCF_REG08(0xEC094028) ++#define MCF_GPIO_PCLRR_F MCF_REG08(0xEC094029) ++#define MCF_GPIO_PCLRR_G MCF_REG08(0xEC09402A) ++#define MCF_GPIO_PCLRR_H MCF_REG08(0xEC09402B) ++#define MCF_GPIO_PCLRR_I MCF_REG08(0xEC09402C) ++#define MCF_GPIO_PCLRR_J MCF_REG08(0xEC09402D) ++#define MCF_GPIO_PCLRR_K MCF_REG08(0xEC09402E) ++ ++#define MCF_GPIO_PCR_A MCF_REG16(0xEC094030) ++#define MCF_GPIO_PCR_B MCF_REG16(0xEC094032) ++#define MCF_GPIO_PCR_C MCF_REG16(0xEC094034) ++#define MCF_GPIO_PCR_D MCF_REG16(0xEC094036) ++#define MCF_GPIO_PCR_E MCF_REG16(0xEC094038) ++#define MCF_GPIO_PCR_F MCF_REG16(0xEC09403A) ++#define MCF_GPIO_PCR_G MCF_REG16(0xEC09403C) ++ ++#define MCF_GPIO_PCR_H MCF_REG16(0xEC09403E) ++#define MCF_GPIO_PCR_I MCF_REG16(0xEC094040) ++#define MCF_GPIO_PCR_J MCF_REG16(0xEC094042) ++#define MCF_GPIO_PCR_K MCF_REG16(0xEC094044) ++ ++#define MCF_GPIO_PODR_G4_VAL (0x01 << 4) ++#define MCF_GPIO_PODR_G4_MASK (0xff & ~MCF_GPIO_PODR_G4_VAL) ++#define MCF_GPIO_PDDR_G4_OUTPUT (0x01 << 4) ++#define MCF_GPIO_PDDR_G4_MASK (0xff & ~MCF_GPIO_PDDR_G4_OUTPUT) ++ ++#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xEC094048) ++#define MCF_GPIO_PAR_BE MCF_REG08(0xEC094049) ++#define MCF_GPIO_PAR_CS MCF_REG08(0xEC09404A) ++#define MCF_GPIO_PAR_CANI2C MCF_REG08(0xEC09404B) ++#define MCF_GPIO_PAR_IRQ0H MCF_REG08(0xEC09404C) ++#define MCF_GPIO_PAR_IRQ0L MCF_REG08(0xEC09404D) ++#define MCF_GPIO_PAR_DSPI0WH MCF_REG08(0xEC09404E) ++#define MCF_GPIO_PAR_DSPI0WL MCF_REG08(0xEC09404F) ++#define MCF_GPIO_PAR_TIMER MCF_REG08(0xEC094050) ++#define MCF_GPIO_PAR_UART2 MCF_REG08(0xEC094051) ++#define MCF_GPIO_PAR_UART1 MCF_REG08(0xEC094052) ++#define MCF_GPIO_PAR_UART0 MCF_REG08(0xEC094053) ++#define MCF_GPIO_PAR_ESDHCH MCF_REG08(0xEC094054) ++#define MCF_GPIO_PAR_ESDHCL MCF_REG08(0xEC094055) ++#define MCF_GPIO_PAR_SIMP0H MCF_REG08(0xEC094056) ++#define MCF_GPIO_PAR_SIMP0L MCF_REG08(0xEC094057) ++#define MCF_GPIO_PAR_SSI0H MCF_REG08(0xEC094058) ++#define MCF_GPIO_PAR_SSI0L MCF_REG08(0xEC094059) ++#define MCF_GPIO_PAR_DBGH1 MCF_REG08(0xEC09405A) ++#define MCF_GPIO_PAR_DBGH0 MCF_REG08(0xEC09405B) ++#define MCF_GPIO_PAR_DBGL MCF_REG08(0xEC09405C) ++#define MCF_GPIO_PAR_FEC MCF_REG08(0xEC09405E) ++#define MCF_GPIO_MSCR_SDRAMC MCF_REG08(0xEC094064) ++#define MCF_GPIO_SRCR_FB1 MCF_REG08(0xEC094064) ++#define MCF_GPIO_SRCR_FB2 MCF_REG08(0xEC094065) ++#define MCF_GPIO_SRCR_FB3 MCF_REG08(0xEC094066) ++#define MCF_GPIO_SRCR_FB4 MCF_REG08(0xEC094067) ++#define MCF_GPIO_SRCR_DSPI0W MCF_REG08(0xEC094068) ++#define MCF_GPIO_SRCR_CANI2C MCF_REG08(0xEC094069) ++#define MCF_GPIO_SRCR_IRQ0 MCF_REG08(0xEC09406A) ++#define MCF_GPIO_SRCR_TIMER MCF_REG08(0xEC09406B) ++#define MCF_GPIO_SRCR_UART MCF_REG08(0xEC09406C) ++#define MCF_GPIO_SRCR_FEC MCF_REG08(0xEC09406D) ++#define MCF_GPIO_SRCR_SDHC MCF_REG08(0xEC09406E) ++#define MCF_GPIO_SRCR_SIM0 MCF_REG08(0xEC09406F) ++#define MCF_GPIO_SRCR_SSI0 MCF_REG08(0xEC094070) ++ ++#define MCF_GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6) ++#define MCF_GPIO_PAR_FBCTL_ALE_MASK (0x3F) ++#define MCF_GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0) ++#define MCF_GPIO_PAR_FBCTL_ALE_FB_TS (0x80) ++#define MCF_GPIO_PAR_FBCTL_ALE_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4) ++#define MCF_GPIO_PAR_FBCTL_OE_MASK (0xCF) ++#define MCF_GPIO_PAR_FBCTL_OE_FB_OE (0x30) ++#define MCF_GPIO_PAR_FBCTL_OE_FB_TBST (0x20) ++#define MCF_GPIO_PAR_FBCTL_OE_NFC_RE (0x20) ++#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00) ++#define MCF_GPIO_PAR_FBCTL_FBCLK (0x08) ++#define MCF_GPIO_PAR_FBCTL_RW (0x04) ++#define MCF_GPIO_PAR_FBCTL_TA(x) ((x)&3) ++#define MCF_GPIO_PAR_FBCTL_TA_MASK (0xFC) ++#define MCF_GPIO_PAR_FBCTL_TA_TA (0x03) ++#define MCF_GPIO_PAR_FBCTL_TA_NFC_RB (0x01) ++#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F) ++#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0) ++#define MCF_GPIO_PAR_BE_BE3_CS3 (0x80) ++#define MCF_GPIO_PAR_BE_BE3_FB_A1 (0x40) ++#define MCF_GPIO_PAR_BE_BE3_NFC_ALE (0x40) ++#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF) ++#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30) ++#define MCF_GPIO_PAR_BE_BE2_CS2 (0x20) ++#define MCF_GPIO_PAR_BE_BE2_FB_A0 (0x10) ++#define MCF_GPIO_PAR_BE_BE2_NFC_CLE (0x10) ++#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_BE_BE1_MASK (0xF3) ++#define MCF_GPIO_PAR_BE_BE1_BE1 (0x0C) ++#define MCF_GPIO_PAR_BE_BE1_FB_TSZ1 (0x08) ++#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00) ++#define MCF_GPIO_PAR_BE_BS0(x) ((x)&0x03) ++#define MCF_GPIO_PAR_BE_BE0_MASK (0xFC) ++#define MCF_GPIO_PAR_BE_BE0_BE0 (0x03) ++#define MCF_GPIO_PAR_BE_BE0_FB_TSZ0 (0x02) ++#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_CS_CS5_MASK (0x3F) ++#define MCF_GPIO_PAR_CS_CS5_CS5 (0xC0) ++#define MCF_GPIO_PAR_CS_CS5_DACK1 (0x80) ++#define MCF_GPIO_PAR_CS_CS5_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_CS_CS4_MASK (0xCF) ++#define MCF_GPIO_PAR_CS_CS4_CS4 (0x30) ++#define MCF_GPIO_PAR_CS_CS4_DREQ1 (0x20) ++#define MCF_GPIO_PAR_CS_CS4_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_CS_CS1_MASK (0xF3) ++#define MCF_GPIO_PAR_CS_CS1_CS1 (0x0C) ++#define MCF_GPIO_PAR_CS_CS1_NFC_CE (0x04) ++#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00) ++#define MCF_GPIO_PAR_CS_CS0_CS0 (0x01) ++ ++#define MCF_GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F) ++#define MCF_GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0) ++#define MCF_GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80) ++#define MCF_GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40) ++#define MCF_GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00) ++#define MCF_GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF) ++#define MCF_GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30) ++#define MCF_GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20) ++#define MCF_GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10) ++#define MCF_GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00) ++#define MCF_GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3) ++#define MCF_GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C) ++#define MCF_GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08) ++#define MCF_GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04) ++#define MCF_GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00) ++#define MCF_GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03) ++#define MCF_GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC) ++#define MCF_GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03) ++#define MCF_GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02) ++#define MCF_GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01) ++#define MCF_GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_IRQH_IRQ7 (0x10) ++#define MCF_GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_IRQH_IRQ4_MASK (0xF3) ++#define MCF_GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C) ++#define MCF_GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08) ++#define MCF_GPIO_PAR_IRQH_IRQ4_GPIO (0x00) ++#define MCF_GPIO_PAR_IRQH_IRQ1 (0x01) ++ ++#define MCF_GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_IRQL_IRQ6_MASK (0x3F) ++#define MCF_GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0) ++#define MCF_GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40) ++#define MCF_GPIO_PAR_IRQL_IRQ6_GPIO (0x00) ++#define MCF_GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_IRQL_IRQ3_MASK (0xCF) ++#define MCF_GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30) ++#define MCF_GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20) ++#define MCF_GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10) ++#define MCF_GPIO_PAR_IRQL_IRQ3_GPIO (0x00) ++#define MCF_GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_IRQL_IRQ2_MASK (0xF3) ++#define MCF_GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C) ++#define MCF_GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08) ++#define MCF_GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04) ++#define MCF_GPIO_PAR_IRQL_IRQ2_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_DSPI0_SIN_MASK (0x3F) ++#define MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0) ++#define MCF_GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0) ++#define MCF_GPIO_PAR_DSPI0_SIN_U3RXD (0x80) ++#define MCF_GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40) ++#define MCF_GPIO_PAR_DSPI0_SIN_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_DSPI0_SOUT_MASK (0xCF) ++#define MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30) ++#define MCF_GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30) ++#define MCF_GPIO_PAR_DSPI0_SOUT_U3TXD (0x20) ++#define MCF_GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10) ++#define MCF_GPIO_PAR_DSPI0_SOUT_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_DSPI0_SCK_MASK (0xF3) ++#define MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C) ++#define MCF_GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C) ++#define MCF_GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08) ++#define MCF_GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04) ++#define MCF_GPIO_PAR_DSPI0_SCK_GPIO (0x00) ++#define MCF_GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03) ++#define MCF_GPIO_PAR_DSPI0_PCS0_MASK (0xFC) ++#define MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03) ++#define MCF_GPIO_PAR_DSPI0_PCS0_SS (0x03) ++#define MCF_GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02) ++#define MCF_GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01) ++#define MCF_GPIO_PAR_DSPI0_PCS0_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80) ++#define MCF_GPIO_PAR_DSPIOW_SBF_CS (0x80) ++#define MCF_GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF) ++#define MCF_GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30) ++#define MCF_GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20) ++#define MCF_GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F) ++#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0) ++#define MCF_GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0) ++#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80) ++#define MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40) ++#define MCF_GPIO_PAR_TIMER_T3IN_ULPI_DIR (0x40) ++#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF) ++#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30) ++#define MCF_GPIO_PAR_TIMER_T2IN_EXTA2 (0x30) ++#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20) ++#define MCF_GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10) ++#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3) ++#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C) ++#define MCF_GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C) ++#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08) ++#define MCF_GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04) ++#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00) ++#define MCF_GPIO_PAR_TIMER_T0IN(x) ((x)&0x03) ++#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC) ++#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03) ++#define MCF_GPIO_PAR_TIMER_T0IN_EXTA0 (0x03) ++#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02) ++#define MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01) ++#define MCF_GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01) ++#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_UART2_U2CTS_MASK (0x3F) ++#define MCF_GPIO_PAR_UART2_U2CTS_U2CTS (0xC0) ++#define MCF_GPIO_PAR_UART2_U2CTS_U6TXD (0x80) ++#define MCF_GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40) ++#define MCF_GPIO_PAR_UART2_U2CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_UART2_U2RTS_MASK (0xCF) ++#define MCF_GPIO_PAR_UART2_U2RTS_U2RTS (0x30) ++#define MCF_GPIO_PAR_UART2_U2RTS_U6RXD (0x20) ++#define MCF_GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10) ++#define MCF_GPIO_PAR_UART2_U2RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_UART2_U2RXD_MASK (0xF3) ++#define MCF_GPIO_PAR_UART2_U2RXD_U2RXD (0x0C) ++#define MCF_GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08) ++#define MCF_GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04) ++#define MCF_GPIO_PAR_UART2_U2RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART2_U2TXD(x) ((x)&0x03) ++#define MCF_GPIO_PAR_UART2_U2TXD_MASK (0xFC) ++#define MCF_GPIO_PAR_UART2_U2TXD_U2TXD (0x03) ++#define MCF_GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02) ++#define MCF_GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01) ++#define MCF_GPIO_PAR_UART2_U2TXD_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_UART1_U1CTS_MASK (0x3F) ++#define MCF_GPIO_PAR_UART1_U1CTS_U1CTS (0xC0) ++#define MCF_GPIO_PAR_UART1_U1CTS_U5TXD (0x80) ++#define MCF_GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40) ++#define MCF_GPIO_PAR_UART1_U1CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_UART1_U1RTS_MASK (0xCF) ++#define MCF_GPIO_PAR_UART1_U1RTS_U1RTS (0x30) ++#define MCF_GPIO_PAR_UART1_U1RTS_U5RXD (0x20) ++#define MCF_GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10) ++#define MCF_GPIO_PAR_UART1_U1RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_UART1_U1RXD_MASK (0xF3) ++#define MCF_GPIO_PAR_UART1_U1RXD_U1RXD (0x0C) ++#define MCF_GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08) ++#define MCF_GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04) ++#define MCF_GPIO_PAR_UART1_U1RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART1_U1TXD(x) ((x)&0x03) ++#define MCF_GPIO_PAR_UART1_U1TXD_MASK (0xFC) ++#define MCF_GPIO_PAR_UART1_U1TXD_U1TXD (0x03) ++#define MCF_GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02) ++#define MCF_GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01) ++#define MCF_GPIO_PAR_UART1_U1TXD_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_UART0_U0CTS_MASK (0x3F) ++#define MCF_GPIO_PAR_UART0_U0CTS_U0CTS (0xC0) ++#define MCF_GPIO_PAR_UART0_U0CTS_U4TXD (0x80) ++#define MCF_GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40) ++#define MCF_GPIO_PAR_UART0_U0CTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_UART0_U0RTS_MASK (0xCF) ++#define MCF_GPIO_PAR_UART0_U0RTS_U0RTS (0x30) ++#define MCF_GPIO_PAR_UART0_U0RTS_U4RXD (0x20) ++#define MCF_GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10) ++#define MCF_GPIO_PAR_UART0_U0RTS_GPIO (0x00) ++#define MCF_GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_UART0_U0RXD_MASK (0xF3) ++#define MCF_GPIO_PAR_UART0_U0RXD_U0RXD (0x0C) ++#define MCF_GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08) ++#define MCF_GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04) ++#define MCF_GPIO_PAR_UART0_U0RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_UART0_U0TXD(x) ((x)&0x03) ++#define MCF_GPIO_PAR_UART0_U0TXD_MASK (0xFC) ++#define MCF_GPIO_PAR_UART0_U0TXD_U0TXD (0x03) ++#define MCF_GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02) ++#define MCF_GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01) ++#define MCF_GPIO_PAR_UART0_U0TXD_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_SDHCH_DAT3_MASK (0x3F) ++#define MCF_GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0) ++#define MCF_GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80) ++#define MCF_GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40) ++#define MCF_GPIO_PAR_SDHCH_DAT3_GPIO (0x00) ++#define MCF_GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_SDHCH_DAT2_MASK (0xCF) ++#define MCF_GPIO_PAR_SDHCH_DAT2_DAT2 (0x30) ++#define MCF_GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20) ++#define MCF_GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10) ++#define MCF_GPIO_PAR_SDHCH_DAT2_GPIO (0x00) ++#define MCF_GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_SDHCH_DAT1_MASK (0xF3) ++#define MCF_GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C) ++#define MCF_GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08) ++#define MCF_GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04) ++#define MCF_GPIO_PAR_SDHCH_DAT1_GPIO (0x00) ++#define MCF_GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03) ++#define MCF_GPIO_PAR_SDHCH_DAT0_MASK (0xFC) ++#define MCF_GPIO_PAR_SDHCH_DAT0_DAT0 (0x03) ++#define MCF_GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02) ++#define MCF_GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01) ++#define MCF_GPIO_PAR_SDHCH_DAT0_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_SDHCL_CMD_MASK (0xF3) ++#define MCF_GPIO_PAR_SDHCL_CMD_CMD (0x0C) ++#define MCF_GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08) ++#define MCF_GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04) ++#define MCF_GPIO_PAR_SDHCL_CMD_GPIO (0x00) ++#define MCF_GPIO_PAR_SDHCL_CLK(x) ((x)&0x03) ++#define MCF_GPIO_PAR_SDHCL_CLK_MASK (0xFC) ++#define MCF_GPIO_PAR_SDHCL_CLK_CLK (0x03) ++#define MCF_GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02) ++#define MCF_GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01) ++#define MCF_GPIO_PAR_SDHCL_CLK_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_SIMP0H_DAT_MASK (0x3F) ++#define MCF_GPIO_PAR_SIMP0H_DAT_DAT (0xC0) ++#define MCF_GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80) ++#define MCF_GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40) ++#define MCF_GPIO_PAR_SIMP0H_DAT_GPIO (0x00) ++#define MCF_GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_SIMP0H_VEN_MASK (0xCF) ++#define MCF_GPIO_PAR_SIMP0H_VEN_VEN (0x30) ++#define MCF_GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20) ++#define MCF_GPIO_PAR_SIMP0H_VEN_GPIO (0x00) ++#define MCF_GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_SIMP0H_RST_MASK (0xF3) ++#define MCF_GPIO_PAR_SIMP0H_RST_RST (0x0C) ++#define MCF_GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08) ++#define MCF_GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04) ++#define MCF_GPIO_PAR_SIMP0H_RST_GPIO (0x00) ++#define MCF_GPIO_PAR_SIMP0H_PD(x) ((x)&0x03) ++#define MCF_GPIO_PAR_SIMP0H_PD_MASK (0xFC) ++#define MCF_GPIO_PAR_SIMP0H_PD_PD (0x03) ++#define MCF_GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02) ++#define MCF_GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01) ++#define MCF_GPIO_PAR_SIMP0H_PD_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03) ++#define MCF_GPIO_PAR_SIMP0L_CLK_MASK (0xFC) ++#define MCF_GPIO_PAR_SIMP0L_CLK_CLK (0x03) ++#define MCF_GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02) ++#define MCF_GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01) ++#define MCF_GPIO_PAR_SIMP0L_CLK_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6) ++#define MCF_GPIO_PAR_SSI0H_RXD_MASK (0x3F) ++#define MCF_GPIO_PAR_SSI0H_RXD_RXD (0xC0) ++#define MCF_GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80) ++#define MCF_GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40) ++#define MCF_GPIO_PAR_SSI0H_RXD_GPIO (0x00) ++#define MCF_GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4) ++#define MCF_GPIO_PAR_SSI0H_TXD_MASK (0xCF) ++#define MCF_GPIO_PAR_SSI0H_TXD_TXD (0x30) ++#define MCF_GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20) ++#define MCF_GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10) ++#define MCF_GPIO_PAR_SSI0H_TXD_GPIO (0x00) ++#define MCF_GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2) ++#define MCF_GPIO_PAR_SSI0H_FS_MASK (0xF3) ++#define MCF_GPIO_PAR_SSI0H_FS_FS (0x0C) ++#define MCF_GPIO_PAR_SSI0H_FS_U7TXD (0x08) ++#define MCF_GPIO_PAR_SSI0H_FS_SIM1_RST (0x04) ++#define MCF_GPIO_PAR_SSI0H_FS_GPIO (0x00) ++#define MCF_GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03) ++#define MCF_GPIO_PAR_SSI0H_MCLK_MASK (0xFC) ++#define MCF_GPIO_PAR_SSI0H_MCLK_MCLK (0x03) ++#define MCF_GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02) ++#define MCF_GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01) ++#define MCF_GPIO_PAR_SSI0H_MCLK_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03) ++#define MCF_GPIO_PAR_SSI0L_BCLK_MASK (0xFC) ++#define MCF_GPIO_PAR_SSI0L_BCLK_BCLK (0x03) ++#define MCF_GPIO_PAR_SSI0L_BCLK_U7RXD (0x02) ++#define MCF_GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01) ++#define MCF_GPIO_PAR_SSI0L_BCLK_GPIO (0x00) ++ ++#define MCF_GPIO_PAR_DEBUGH1_DAT3 (0x40) ++#define MCF_GPIO_PAR_DEBUGH1_DAT2 (0x10) ++#define MCF_GPIO_PAR_DEBUGH1_DAT1 (0x04) ++#define MCF_GPIO_PAR_DEBUGH1_DAT0 (0x01) ++ ++#define MCF_GPIO_PAR_DEBUGH0_PST3 (0x40) ++#define MCF_GPIO_PAR_DEBUGH0_PST2 (0x10) ++#define MCF_GPIO_PAR_DEBUGH0_PST1 (0x04) ++#define MCF_GPIO_PAR_DEBUGH0_PST0 (0x01) ++ ++#define MCF_GPIO_PAR_DEBUGL_ALLPST (0x01) ++ ++#define MCF_GPIO_PAR_FEC_FEC(x) ((x)&0x0F) ++#define MCF_GPIO_PAR_FEC_FEC_MASK (0xF0) ++#define MCF_GPIO_PAR_FEC_FEC_GPIO (0x0D) ++#define MCF_GPIO_PAR_FEC_FEC_RMII1 (0x0C) ++#define MCF_GPIO_PAR_FEC_FEC_RMII1FUL (0x0B) ++#define MCF_GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A) ++#define MCF_GPIO_PAR_FEC_FEC_RMII0 (0x09) ++#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08) ++#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL (0x07) ++#define MCF_GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06) ++#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */ ++/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */ ++#define MCF_GPIO_PAR_FEC_FEC_RMII0_1 (0x04) ++#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03) ++#define MCF_GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */ ++#define MCF_GPIO_PAR_FEC_FEC_MIIFUL (0x00) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_GPIO_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_intc.h +@@ -0,0 +1,727 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_INTC_H__ ++#define __MCF5441X_INTC_H__ ++ ++/********************************************************************* ++* ++* Interrupt Controller (INTC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) ++#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) ++#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) ++#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) ++#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) ++#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) ++#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) ++#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) ++#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) ++#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) ++#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) ++#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) ++#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) ++#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) ++#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) ++#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) ++#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) ++#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) ++#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) ++#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) ++#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) ++#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) ++#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) ++#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) ++#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) ++#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) ++#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) ++#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) ++#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) ++#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) ++#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) ++#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) ++#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) ++#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) ++#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) ++#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) ++#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) ++#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) ++#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) ++#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) ++#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) ++#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) ++#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) ++#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) ++#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) ++#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) ++#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) ++#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) ++#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) ++#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) ++#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) ++#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) ++#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) ++#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) ++#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) ++#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) ++#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) ++#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) ++#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) ++#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) ++#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) ++#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) ++#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) ++#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) ++#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) ++#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) ++#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) ++#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) ++#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) ++#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) ++#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) ++#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) ++#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) ++#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) ++#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) ++#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) ++#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) ++#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) ++#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) ++#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) ++#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) ++#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) ++#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) ++#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) ++#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) ++#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) ++#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) ++#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) ++#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) ++#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) ++#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) ++#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) ++#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) ++#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) ++#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) ++#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) ++#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) ++#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) ++#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) ++#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) ++#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) ++#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) ++#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) ++#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) ++#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) ++#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) ++#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) ++#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) ++#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) ++#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) ++#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) ++#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) ++#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) ++#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) ++#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) ++#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) ++#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) ++#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) ++#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) ++#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) ++#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) ++#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) ++#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) ++#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) ++#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) ++#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) ++#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) ++#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) ++#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) ++#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) ++#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) ++#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) ++#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) ++#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) ++#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) ++#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) ++#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) ++#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) ++#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) ++#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) ++#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) ++#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) ++#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) ++#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) ++#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) ++#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) ++#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) ++#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) ++#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) ++#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) ++#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) ++#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) ++#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) ++#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) ++#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) ++#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) ++#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) ++#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) ++#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) ++#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) ++#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) ++#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) ++#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8 ++#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) ++ ++#define MCF_INTC2_SIMR MCF_REG08(0xFC05001C) ++#define MCF_INTC2_CIMR MCF_REG08(0xFC05001D) ++#define MCF_INTC2_ICR31 MCF_REG08(0xFC05005F) ++ ++/* Parameterized register read/write macros for multiple registers */ ++#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001)) ++#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004)) ++#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001)) ++#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004)) ++#define MCF_INTC2_ICR(x) MCF_REG08(0xFC050041+((x-1)*0x001)) ++ ++/* Parameterized register read/write macros for multiple modules */ ++#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) ++#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) ++#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) ++#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) ++#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) ++#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) ++#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) ++#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) ++#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) ++#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) ++#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) ++#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) ++#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) ++#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) ++#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) ++#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) ++#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) ++#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) ++#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) ++#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) ++#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) ++#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) ++#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) ++#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) ++#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) ++#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) ++#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) ++#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) ++#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) ++#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) ++#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) ++#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) ++#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) ++#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) ++#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) ++#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) ++#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) ++#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) ++#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) ++#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) ++#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) ++#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) ++#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) ++#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) ++#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) ++#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) ++#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) ++#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) ++#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) ++#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) ++#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) ++#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) ++#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) ++#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) ++#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) ++#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) ++#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) ++#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) ++#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) ++#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) ++#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) ++#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) ++#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) ++#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) ++#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) ++#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) ++#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) ++#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) ++#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) ++#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) ++#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) ++#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) ++#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) ++#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) ++#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) ++#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) ++#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) ++#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) ++#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) ++#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) ++#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) ++#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) ++ ++/* Bit definitions and macros for IPRH */ ++#define MCF_INTC_IPRH_INT32 (0x00000001) ++#define MCF_INTC_IPRH_INT33 (0x00000002) ++#define MCF_INTC_IPRH_INT34 (0x00000004) ++#define MCF_INTC_IPRH_INT35 (0x00000008) ++#define MCF_INTC_IPRH_INT36 (0x00000010) ++#define MCF_INTC_IPRH_INT37 (0x00000020) ++#define MCF_INTC_IPRH_INT38 (0x00000040) ++#define MCF_INTC_IPRH_INT39 (0x00000080) ++#define MCF_INTC_IPRH_INT40 (0x00000100) ++#define MCF_INTC_IPRH_INT41 (0x00000200) ++#define MCF_INTC_IPRH_INT42 (0x00000400) ++#define MCF_INTC_IPRH_INT43 (0x00000800) ++#define MCF_INTC_IPRH_INT44 (0x00001000) ++#define MCF_INTC_IPRH_INT45 (0x00002000) ++#define MCF_INTC_IPRH_INT46 (0x00004000) ++#define MCF_INTC_IPRH_INT47 (0x00008000) ++#define MCF_INTC_IPRH_INT48 (0x00010000) ++#define MCF_INTC_IPRH_INT49 (0x00020000) ++#define MCF_INTC_IPRH_INT50 (0x00040000) ++#define MCF_INTC_IPRH_INT51 (0x00080000) ++#define MCF_INTC_IPRH_INT52 (0x00100000) ++#define MCF_INTC_IPRH_INT53 (0x00200000) ++#define MCF_INTC_IPRH_INT54 (0x00400000) ++#define MCF_INTC_IPRH_INT55 (0x00800000) ++#define MCF_INTC_IPRH_INT56 (0x01000000) ++#define MCF_INTC_IPRH_INT57 (0x02000000) ++#define MCF_INTC_IPRH_INT58 (0x04000000) ++#define MCF_INTC_IPRH_INT59 (0x08000000) ++#define MCF_INTC_IPRH_INT60 (0x10000000) ++#define MCF_INTC_IPRH_INT61 (0x20000000) ++#define MCF_INTC_IPRH_INT62 (0x40000000) ++#define MCF_INTC_IPRH_INT63 (0x80000000) ++ ++/* Bit definitions and macros for IPRL */ ++#define MCF_INTC_IPRL_INT0 (0x00000001) ++#define MCF_INTC_IPRL_INT1 (0x00000002) ++#define MCF_INTC_IPRL_INT2 (0x00000004) ++#define MCF_INTC_IPRL_INT3 (0x00000008) ++#define MCF_INTC_IPRL_INT4 (0x00000010) ++#define MCF_INTC_IPRL_INT5 (0x00000020) ++#define MCF_INTC_IPRL_INT6 (0x00000040) ++#define MCF_INTC_IPRL_INT7 (0x00000080) ++#define MCF_INTC_IPRL_INT8 (0x00000100) ++#define MCF_INTC_IPRL_INT9 (0x00000200) ++#define MCF_INTC_IPRL_INT10 (0x00000400) ++#define MCF_INTC_IPRL_INT11 (0x00000800) ++#define MCF_INTC_IPRL_INT12 (0x00001000) ++#define MCF_INTC_IPRL_INT13 (0x00002000) ++#define MCF_INTC_IPRL_INT14 (0x00004000) ++#define MCF_INTC_IPRL_INT15 (0x00008000) ++#define MCF_INTC_IPRL_INT16 (0x00010000) ++#define MCF_INTC_IPRL_INT17 (0x00020000) ++#define MCF_INTC_IPRL_INT18 (0x00040000) ++#define MCF_INTC_IPRL_INT19 (0x00080000) ++#define MCF_INTC_IPRL_INT20 (0x00100000) ++#define MCF_INTC_IPRL_INT21 (0x00200000) ++#define MCF_INTC_IPRL_INT22 (0x00400000) ++#define MCF_INTC_IPRL_INT23 (0x00800000) ++#define MCF_INTC_IPRL_INT24 (0x01000000) ++#define MCF_INTC_IPRL_INT25 (0x02000000) ++#define MCF_INTC_IPRL_INT26 (0x04000000) ++#define MCF_INTC_IPRL_INT27 (0x08000000) ++#define MCF_INTC_IPRL_INT28 (0x10000000) ++#define MCF_INTC_IPRL_INT29 (0x20000000) ++#define MCF_INTC_IPRL_INT30 (0x40000000) ++#define MCF_INTC_IPRL_INT31 (0x80000000) ++ ++/* Bit definitions and macros for IMRH */ ++#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) ++#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) ++#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) ++#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) ++#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) ++#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) ++#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) ++#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) ++#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) ++#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) ++#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) ++#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) ++#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) ++#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) ++#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) ++#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) ++#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) ++#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) ++#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) ++#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) ++#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) ++#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) ++#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) ++#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) ++#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) ++#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) ++#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) ++#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) ++#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) ++#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) ++#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) ++#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) ++ ++/* Bit definitions and macros for IMRL */ ++#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) ++#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) ++#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) ++#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) ++#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) ++#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) ++#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) ++#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) ++#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) ++#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) ++#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) ++#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) ++#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) ++#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) ++#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) ++#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) ++#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) ++#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) ++#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) ++#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) ++#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) ++#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) ++#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) ++#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) ++#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) ++#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) ++#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) ++#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) ++#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) ++#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) ++#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) ++#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) ++ ++/* Bit definitions and macros for INTFRCH */ ++#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) ++#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) ++#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) ++#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) ++#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) ++#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) ++#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) ++#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) ++#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) ++#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) ++#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) ++#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) ++#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) ++#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) ++#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) ++#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) ++#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) ++#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) ++#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) ++#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) ++#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) ++#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) ++#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) ++#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) ++#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) ++#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) ++#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) ++#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) ++#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) ++#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) ++#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) ++#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) ++ ++/* Bit definitions and macros for INTFRCL */ ++#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) ++#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) ++#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) ++#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) ++#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) ++#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) ++#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) ++#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) ++#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) ++#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) ++#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) ++#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) ++#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) ++#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) ++#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) ++#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) ++#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) ++#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) ++#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) ++#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) ++#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) ++#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) ++#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) ++#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) ++#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) ++#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) ++#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) ++#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) ++#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) ++#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) ++#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) ++#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) ++ ++/* Bit definitions and macros for ICONFIG */ ++#define MCF_INTC_ICONFIG_EMASK (0x0020) ++#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) ++#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) ++#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) ++#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) ++#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) ++#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) ++#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) ++ ++/* Bit definitions and macros for SIMR */ ++#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)) ++ ++/* Bit definitions and macros for CIMR */ ++#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)) ++ ++/* Bit definitions and macros for CLMASK */ ++#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)) ++ ++/* Bit definitions and macros for SLMASK */ ++#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)) ++ ++/* Bit definitions and macros for ICR group */ ++#define MCF_INTC_ICR_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR1 */ ++#define MCF_INTC_ICR1_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR2 */ ++#define MCF_INTC_ICR2_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR3 */ ++#define MCF_INTC_ICR3_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR4 */ ++#define MCF_INTC_ICR4_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR5 */ ++#define MCF_INTC_ICR5_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR6 */ ++#define MCF_INTC_ICR6_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR7 */ ++#define MCF_INTC_ICR7_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR8 */ ++#define MCF_INTC_ICR8_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR9 */ ++#define MCF_INTC_ICR9_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR10 */ ++#define MCF_INTC_ICR10_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR11 */ ++#define MCF_INTC_ICR11_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR12 */ ++#define MCF_INTC_ICR12_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR13 */ ++#define MCF_INTC_ICR13_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR14 */ ++#define MCF_INTC_ICR14_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR15 */ ++#define MCF_INTC_ICR15_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR16 */ ++#define MCF_INTC_ICR16_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR17 */ ++#define MCF_INTC_ICR17_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR18 */ ++#define MCF_INTC_ICR18_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR19 */ ++#define MCF_INTC_ICR19_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR20 */ ++#define MCF_INTC_ICR20_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR21 */ ++#define MCF_INTC_ICR21_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR22 */ ++#define MCF_INTC_ICR22_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR23 */ ++#define MCF_INTC_ICR23_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR24 */ ++#define MCF_INTC_ICR24_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR25 */ ++#define MCF_INTC_ICR25_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR26 */ ++#define MCF_INTC_ICR26_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR27 */ ++#define MCF_INTC_ICR27_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR28 */ ++#define MCF_INTC_ICR28_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR29 */ ++#define MCF_INTC_ICR29_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR30 */ ++#define MCF_INTC_ICR30_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR31 */ ++#define MCF_INTC_ICR31_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR32 */ ++#define MCF_INTC_ICR32_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR33 */ ++#define MCF_INTC_ICR33_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR34 */ ++#define MCF_INTC_ICR34_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR35 */ ++#define MCF_INTC_ICR35_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR36 */ ++#define MCF_INTC_ICR36_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR37 */ ++#define MCF_INTC_ICR37_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR38 */ ++#define MCF_INTC_ICR38_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR39 */ ++#define MCF_INTC_ICR39_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR40 */ ++#define MCF_INTC_ICR40_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR41 */ ++#define MCF_INTC_ICR41_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR42 */ ++#define MCF_INTC_ICR42_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR43 */ ++#define MCF_INTC_ICR43_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR44 */ ++#define MCF_INTC_ICR44_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR45 */ ++#define MCF_INTC_ICR45_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR46 */ ++#define MCF_INTC_ICR46_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR47 */ ++#define MCF_INTC_ICR47_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR48 */ ++#define MCF_INTC_ICR48_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR49 */ ++#define MCF_INTC_ICR49_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR50 */ ++#define MCF_INTC_ICR50_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR51 */ ++#define MCF_INTC_ICR51_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR52 */ ++#define MCF_INTC_ICR52_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR53 */ ++#define MCF_INTC_ICR53_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR54 */ ++#define MCF_INTC_ICR54_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR55 */ ++#define MCF_INTC_ICR55_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR56 */ ++#define MCF_INTC_ICR56_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR57 */ ++#define MCF_INTC_ICR57_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR58 */ ++#define MCF_INTC_ICR58_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR59 */ ++#define MCF_INTC_ICR59_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR60 */ ++#define MCF_INTC_ICR60_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR61 */ ++#define MCF_INTC_ICR61_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR62 */ ++#define MCF_INTC_ICR62_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for ICR63 */ ++#define MCF_INTC_ICR63_IL(x) (((x)&0x07)) ++ ++/* Bit definitions and macros for SWIACK */ ++#define MCF_INTC_SWIACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for LIACK group */ ++#define MCF_INTC_LIACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L1IACK */ ++#define MCF_INTC_L1IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L2IACK */ ++#define MCF_INTC_L2IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L3IACK */ ++#define MCF_INTC_L3IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L4IACK */ ++#define MCF_INTC_L4IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L5IACK */ ++#define MCF_INTC_L5IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L6IACK */ ++#define MCF_INTC_L6IACK_VECTOR(x) (x) ++ ++/* Bit definitions and macros for L7IACK */ ++#define MCF_INTC_L7IACK_VECTOR(x) (x) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_INTC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_pm.h +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_PM_H__ ++#define __MCF5441X_PM_H__ ++ ++/********************************************************************* ++* ++* Power Management Module Register Definition ++* ++*********************************************************************/ ++ ++#define MCF_PM_WCR MCF_REG08(0xFC040013) ++#define MCF_PM_PPMSR0 MCF_REG08(0xFC04002C) ++#define MCF_PM_PPMCR0 MCF_REG08(0xFC04002D) ++#define MCF_PM_PPMSR1 MCF_REG08(0xFC04002E) ++#define MCF_PM_PPMCR1 MCF_REG08(0xFC04002F) ++#define MCF_PM_PPMHR0 MCF_REG32(0xFC040030) ++#define MCF_PM_PPMLR0 MCF_REG32(0xFC040034) ++#define MCF_PM_PPMHR1 MCF_REG32(0xFC040038) ++#define MCF_PM_PPMLR1 MCF_REG32(0xFC04003C) ++#define MCF_PM_LPCR MCF_REG08(0xEC090007) ++#define MCF_PM_MISCCR MCF_REG16(0xEC09000E) ++#define MCF_PM_CDHR MCF_REG16(0xEC090010) ++#define MCF_PM_CDLR MCF_REG16(0xEC090012) ++ ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_rtc.h +@@ -0,0 +1,127 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Lanttor.Guo@freescale.com ++ * ++ * Description: ++ * This file is the register definition of m5441x RTC module ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++ ++#ifndef __MCF5441X_RTC_H__ ++#define __MCF5441X_RTC_H__ ++ ++/********************************************************************* ++* ++* Real-time Clock (RTC) ++* ++*********************************************************************/ ++#ifndef MCFINT_VECBASE ++#define MCFINT_VECBASE 64 ++#endif ++ ++#define MCFSIM_ICR_RTC (0xFC050040 + 26) ++ ++/* Register read/write macros */ ++#define MCF_RTC_YEARMON 0xFC0A8000 ++#define MCF_RTC_DAYS 0xFC0A8002 ++#define MCF_RTC_HOURMIN 0xFC0A8004 ++#define MCF_RTC_SECONDS 0xFC0A8006 ++#define MCF_RTC_ALRM_YRMON 0xFC0A8008 ++#define MCF_RTC_ALRM_DAYS 0xFC0A800A ++#define MCF_RTC_ALRM_HM 0xFC0A800C ++#define MCF_RTC_ALRM_SEC 0xFC0A800E ++#define MCF_RTC_CR 0xFC0A8010 ++#define MCF_RTC_SR 0xFC0A8012 ++#define MCF_RTC_ISR 0xFC0A8014 ++#define MCF_RTC_IER 0xFC0A8016 ++#define MCF_RTC_COUNT_DN 0xFC0A8018 ++#define MCF_RTC_CFG_DATA 0xFC0A8020 ++#define MCF_RTC_DST_HOUR 0xFC0A8022 ++#define MCF_RTC_DST_MON 0xFC0A8024 ++#define MCF_RTC_DST_DAY 0xFC0A8026 ++#define MCF_RTC_COMPEN 0xFC0A8028 ++#define MCF_RTC_UP_CNTRH 0xFC0A8032 ++#define MCF_RTC_UP_CNTRL 0xFC0A8034 ++ ++#define MCF_RTC_STANDBY_RAM_START 0xFC0A8040 ++#define MCF_RTC_STANDBY_RAM_END 0xFC0A8040 ++ ++/* Bit definitions and macros for MCF_RTC_YEARMON */ ++ ++#define MCF_RTC_YEARMON_YEAR_RD(x) (((x) & 0xFF00) >> 8) ++#define MCF_RTC_YEARMON_MON_RD(x) ((x) & 0x00FF) ++#define MCF_RTC_YEARMON_YEAR_SET(x) (((x) & 0x00FF) << 8) ++#define MCF_RTC_YEARMON_MON_SET(x) ((x) & 0x000F) ++ ++/* Bit definitions and macros for MCF_RTC_DAYS */ ++#define MCF_RTC_DAYS_DAYWEEK_RD(x) (((x) & 0xFF00) >> 8) ++#define MCF_RTC_DAYS_DAY_RD(x) ((x) & 0x00FF) ++#define MCF_RTC_DAYS_DAYWEEK_SET(x) (((x) & 0x0007) << 8) ++#define MCF_RTC_DAYS_DAY_SET(x) ((x) & 0x001F) ++ ++/* Bit definitions and macros for MCF_RTC_HOURMIN */ ++#define MCF_RTC_HOURMIN_HOURS_RD(x) (((x) & 0xFF00) >> 8) ++#define MCF_RTC_HOURMIN_MINUTES_RD(x) ((x) & 0x00FF) ++#define MCF_RTC_HOURMIN_HOURS_SET(x) (((x) & 0x001F) << 8) ++#define MCF_RTC_HOURMIN_MINUTES_SET(x) ((x) & 0x003F) ++ ++/* Bit definitions and macros for MCF_RTC_SECONDS */ ++#define MCF_RTC_SECONDS_SECONDS_RD(x) ((x) & 0x00FF) ++#define MCF_RTC_SECONDS_SECONDS_SET(x) (((x) & 0x003F) << 0) ++ ++/* Bit definitions and macros for MCF_RTC_CR */ ++#define MCF_RTC_CR_WP 0x0002 ++ ++/* Bit definitions and macros for MCF_RTC_ISR */ ++#define MCF_RTC_ISR_STW 0x0002 ++#define MCF_RTC_ISR_ALM 0x0004 ++#define MCF_RTC_ISR_DAY 0x0008 ++#define MCF_RTC_ISR_HR 0x0010 ++#define MCF_RTC_ISR_MIN 0x0020 ++#define MCF_RTC_ISR_1HZ 0x0040 ++#define MCF_RTC_ISR_2HZ 0x0080 ++#define MCF_RTC_ISR_SAM0 0x0100 ++#define MCF_RTC_ISR_SAM1 0x0200 ++#define MCF_RTC_ISR_SAM2 0x0400 ++#define MCF_RTC_ISR_SAM3 0x0800 ++#define MCF_RTC_ISR_SAM4 0x1000 ++#define MCF_RTC_ISR_SAM5 0x2000 ++#define MCF_RTC_ISR_SAM6 0x4000 ++#define MCF_RTC_ISR_SAM7 0x8000 ++ ++/* Bit definitions and macros for MCF_RTC_IER */ ++#define MCF_RTC_IER_STW 0x0002 ++#define MCF_RTC_IER_ALM 0x0004 ++#define MCF_RTC_IER_DAY 0x0008 ++#define MCF_RTC_IER_HR 0x0010 ++#define MCF_RTC_IER_MIN 0x0020 ++#define MCF_RTC_IER_1HZ 0x0040 ++#define MCF_RTC_IER_2HZ 0x0080 ++#define MCF_RTC_IER_SAM0 0x0100 ++#define MCF_RTC_IER_SAM1 0x0200 ++#define MCF_RTC_IER_SAM2 0x0400 ++#define MCF_RTC_IER_SAM3 0x0800 ++#define MCF_RTC_IER_SAM4 0x1000 ++#define MCF_RTC_IER_SAM5 0x2000 ++#define MCF_RTC_IER_SAM6 0x4000 ++#define MCF_RTC_IER_SAM7 0x8000 ++ ++/* Bit definitions and macros for MCF_RTC_CFG_DATA */ ++#define MCF_RTC_CFG_DATA_OSCBYP 0x0010 ++#define MCF_RTC_CFG_DATA_OSCEN 0x0008 ++ ++/* Bit definitions and macros for MCF_RTC_SR */ ++#define MCF_RTC_SR_INVALID 0x0001 ++#define MCF_RTC_SR_WPE 0x0010 ++ ++/* Interrupt source */ ++#define MCFINT_RTC (64+64+26) ++/*********************************************************************/ ++ ++#endif +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_scm.h +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef __MCF5441X_SCM_H__ ++#define __MCF5441X_SCM_H__ ++ ++/********************************************************************* ++* ++* System Control Module (SCM) ++* ++*********************************************************************/ ++ ++/* Core Watchdog(CW) Register read/write macros */ ++#define MCF_SCM_CWCR MCF_REG16(0xFC040016) /* CW Control Register */ ++#define MCF_SCM_CWSR MCF_REG08(0xFC04001B) /* CW Service Register */ ++ ++/* CW Bit definitions and macros for SWCR */ ++#define MCF_SCM_CWCR_RO (0x8000) /* CWCR is read-only */ ++#define MCF_SCM_CWCR_CWRWR (0x0100) /* CW run when halted */ ++#define MCF_SCM_CWCR_CWE (0x0080) /* CW timer enable */ ++#define MCF_SCM_CWCR_CWRI(x) (((x) & 0x03) << 5) /* CW reset/interrupt */ ++#define MCF_SCM_CWCR_CWT(x) (((x) & 0x1F) << 0) /* CW time-out period */ ++ ++#define MCF_GPT_MAX_TIMEOUT 17 ++/********************************************************************/ ++ ++#endif /* __MCF5441X_SCM_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_sdramc.h +@@ -0,0 +1,141 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_SDRAMC_H__ ++#define __MCF5441X_SDRAMC_H__ ++ ++/********************************************************************* ++* ++* SDRAM Controller (SDRAMC) ++* ++*********************************************************************/ ++ ++/* Register read/write macros */ ++/* SDRAM Mode/Extended Mode Register */ ++#define MCF_SDRAMC_SDMR (*(vuint32 *)(0xFC0B8000)) ++/* SDRAM Control Register */ ++#define MCF_SDRAMC_SDCR (*(vuint32 *)(0xFC0B8004)) ++/* SDRAM Configuration Register 1 */ ++#define MCF_SDRAMC_SDCFG1 (*(vuint32 *)(0xFC0B8008)) ++/* SDRAM Configuration Register 2 */ ++#define MCF_SDRAMC_SDCFG2 (*(vuint32 *)(0xFC0B800C)) ++/* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS0 (*(vuint32 *)(0xFC0B8110)) ++/* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS1 (*(vuint32 *)(0xFC0B8114)) ++ ++/* Parameterized register read/write macros for multiple registers */ ++/* SDRAM Chip Select Register */ ++#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004))) ++ ++/* Bit definitions and macros for SDMR */ ++#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ ++#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */ ++#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ ++#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ ++#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000) ++#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) ++ ++/* Bit definitions and macros for SDCR */ ++#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ ++#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ ++#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ ++#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ ++#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ ++/* Periodic Refresh Counter */ ++#define MCF_SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) ++#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ ++/* Internal Address Mux Select */ ++#define MCF_SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) ++#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ ++#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ ++#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ ++/* Clock Enable */ ++#define MCF_SDRAMC_SDCR_CKE (0x40000000) ++/* SDRAM Mode Register Programming Enable */ ++#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) ++#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00) ++ ++/* Bit definitions and macros for SDCFG1 */ ++/* Write Latency */ ++#define MCF_SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) ++/* Refresh to active delay */ ++#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) ++/* Precharge to active delay */ ++#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) ++/* Active to read/write delay */ ++#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) ++/* Read CAS Latency */ ++#define MCF_SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) ++/* Single write to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) ++/* Single read to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for SDCFG2 */ ++/* Burst Length */ ++#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) ++/* Burst read to write delay */ ++#define MCF_SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) ++/* Burst write to read/write/precharge delay */ ++#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) ++/* Burst read to read/precharge delay */ ++#define MCF_SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) ++ ++/* Bit definitions and macros for SDCS group */ ++/* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) ++/* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) ++#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) ++#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) ++#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) ++#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) ++#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) ++#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) ++#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) ++#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) ++#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) ++#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) ++#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) ++#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) ++#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) ++#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) ++#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) ++ ++/* Bit definitions and macros for SDCS0 */ ++/* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS0_CSSZ(x) (((x)&0x0000001F)) ++/* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS0_CSBA(x) (((x)&0x00000FFF)<<20) ++#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000) ++#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000) ++#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013) ++#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014) ++#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015) ++#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016) ++#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017) ++#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018) ++#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019) ++#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A) ++#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B) ++#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C) ++#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D) ++#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E) ++#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F) ++ ++/* Bit definitions and macros for SDCS1 */ ++/* Chip-Select Size */ ++#define MCF_SDRAMC_SDCS1_CSSZ(x) (((x)&0x0000001F)) ++/* Chip-Select Base Address */ ++#define MCF_SDRAMC_SDCS1_CSBA(x) (((x)&0x00000FFF)<<20) ++ ++/********************************************************************/ ++ ++#endif /* __MCF5441X_SDRAMC_H__ */ +--- /dev/null ++++ b/arch/m68k/include/asm/mcf5441x_xbs.h +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MCF5441X_XBS_H__ ++#define __MCF5441X_XBS_H__ ++ ++/* ++ * Crossbar Switch (XBS) ++ */ ++ ++/* Register read/write macros */ ++#define MCF_XBS_PRS0 MCF_REG32(0xFC004000) /* DRAM */ ++#define MCF_XBS_CRS0 MCF_REG32(0xFC004010) ++#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */ ++#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */ ++#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */ ++#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */ ++#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */ ++#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */ ++#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */ ++#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */ ++#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */ ++#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */ ++ ++/* Priorities */ ++#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */ ++#define MCF_XBS_PRI_2 1 /* Level 2 */ ++#define MCF_XBS_PRI_3 2 /* Level 3 */ ++#define MCF_XBS_PRI_4 3 /* Level 4 */ ++#define MCF_XBS_PRI_5 4 /* Level 5 */ ++#define MCF_XBS_PRI_6 5 /* Level 6 */ ++#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */ ++#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */ ++ ++/* Priority Register (PRSn) Defs */ ++#define MCF_XBS_PRS_MACRO(m, p) ((p)<<((m)<<2)) ++#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */ ++#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */ ++#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */ ++#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */ ++#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */ ++#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */ ++#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */ ++#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */ ++ ++/* Control Register (CRSn) Defs */ ++#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */ ++#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */ ++#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */ ++#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */ ++ ++/* MCF_XBS_CRS_ARB Defs */ ++#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */ ++#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */ ++ ++/* MCF_XBS_CRS_PCTL Defs */ ++#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */ ++#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */ ++#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */ ++ ++/* MCF_XBS_CRS_PARK Defs */ ++#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */ ++#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */ ++#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */ ++#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */ ++#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */ ++#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */ ++#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */ ++#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */ ++ ++#endif /* __MCF5441X_XBS_H__ */ diff --git a/target/linux/coldfire/patches/005-Add-serial-driver-and-irda-driver-support-for-MCF544.patch b/target/linux/coldfire/patches/005-Add-serial-driver-and-irda-driver-support-for-MCF544.patch new file mode 100644 index 000000000..1ccbb123b --- /dev/null +++ b/target/linux/coldfire/patches/005-Add-serial-driver-and-irda-driver-support-for-MCF544.patch @@ -0,0 +1,200 @@ +From 5c37079957c5e5555aa8284a879f8cc44fa8eb25 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:39 +0800 +Subject: [PATCH 05/52] Add serial driver and irda driver support for MCF5445x and MCF547x/MCF548x + +Add common serial driver for MCF5445x and MCF547x/MCF548x. +Also add irda support for MCF547x/MCF548x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/tty/serial/Kconfig | 20 ++++++++++ + drivers/tty/serial/mcf.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 107 insertions(+), 0 deletions(-) + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -1027,6 +1027,26 @@ config SERIAL_68328_RTS_CTS + bool "Support RTS/CTS on 68328 serial port" + depends on SERIAL_68328 + ++config SERIAL_COLDFIRE_IRDA ++ bool "ColdFire IRDA support" ++ depends on SERIAL_MCF ++ help ++ This driver supports IrDA on the ColdFire platform, ++ such as MCF547x and MCF548x. ++ ++ Say Y here if you want to use IrDA 1.1 SIR mode. ++ ++config SERIAL_COLDFIRE_EDMA ++ bool "ColdFire serial EDMA support" ++ depends on SERIAL_MCF ++ default n ++ help ++ Enables Enhanced Direct Memory Access(eDMA) in the Coldfire ++ serial driver. ++ ++ Say Y here if you want to use DMA processing of transmit ++ and receive data for the serial driver. ++ + config SERIAL_MCF + bool "Coldfire serial support" + depends on COLDFIRE +--- a/drivers/tty/serial/mcf.c ++++ b/drivers/tty/serial/mcf.c +@@ -4,6 +4,10 @@ + * mcf.c -- Freescale ColdFire UART driver + * + * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com> ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Jason Jin Jason.Jin@freescale.com ++ * Shrek Wu B16972@freescale.com ++ * Chengju Cai b22600@freescale.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -23,9 +27,11 @@ + #include <linux/serial.h> + #include <linux/serial_core.h> + #include <linux/io.h> ++#include <linux/delay.h> + #include <asm/coldfire.h> + #include <asm/mcfsim.h> + #include <asm/mcfuart.h> ++#include <asm/m5485psc.h> + #include <asm/nettel.h> + + /****************************************************************************/ +@@ -46,6 +52,10 @@ + #define mcf_setppdtr(p, v) do { } while (0) + #endif + ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++#define SERIAL_IRDA_LINE (2) ++#endif ++ + /****************************************************************************/ + + /* +@@ -101,6 +111,15 @@ static void mcf_start_tx(struct uart_por + { + struct mcf_uart *pp = container_of(port, struct mcf_uart, port); + ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ if (port->line == SERIAL_IRDA_LINE) { ++ /* Disable IRDA receiver*/ ++ writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); ++ writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); ++ ++ writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); ++ } ++#endif + pp->imr |= MCFUART_UIR_TXREADY; + writeb(pp->imr, port->membase + MCFUART_UIMR); + } +@@ -154,6 +173,30 @@ static int mcf_startup(struct uart_port + + spin_lock_irqsave(&port->lock, flags); + ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ if (port->line == SERIAL_IRDA_LINE) { ++ /* Put PSC in IrDA mode */ ++ MCF_PSC_SICR(port->line) = MCF_PSC_SICR_SIM_SIR; ++ ++ /* Set pulse width to 1.6 uS */ ++ MCF_PSC_IRSDR(port->line) = (uint8_t) ++ (16 * (CONFIG_MCFCLK / 10000000)); ++ MCF_PSC_IRCR1(port->line) = MCF_PSC_IRCR1_SPUL; ++ MCF_PSC_IRCR2(port->line) = 0; ++ ++ /* Enable RTS to send */ ++ MCF_PSC_OPSET(port->line) = MCF_PSC_OPSET_RTS; ++ ++ /* Setup FIFO Alarms */ ++ MCF_PSC_RFAR(port->line) = MCF_PSC_RFAR_ALARM(248); ++ MCF_PSC_TFAR(port->line) = MCF_PSC_TFAR_ALARM(248); ++ ++ MCF_PSC_RFCR(port->line) = MCF_PSC_RFCR_FRMEN ++ | MCF_PSC_RFCR_GR(4); ++ MCF_PSC_TFCR(port->line) = MCF_PSC_TFCR_FRMEN ++ | MCF_PSC_RFCR_GR(4); ++ } ++#endif + /* Reset UART, get it into known state... */ + writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); + writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); +@@ -177,7 +220,17 @@ static void mcf_shutdown(struct uart_por + { + struct mcf_uart *pp = container_of(port, struct mcf_uart, port); + unsigned long flags; ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ unsigned long delay_counter = 0; ++#endif + ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ while (!((readb(port->membase + MCFUART_USR)) & MCFUART_USR_TXEMPTY)) { ++ if (delay_counter++ > 25000) ++ break; ++ udelay(10); ++ } ++#endif + spin_lock_irqsave(&port->lock, flags); + + /* Disable all interrupts now */ +@@ -202,7 +255,14 @@ static void mcf_set_termios(struct uart_ + unsigned int baudfr; + #endif + unsigned char mr1, mr2; ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ int i = 0; /* hush GCC */ ++#endif + ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ while (i++ < 35000) ++ udelay(1); ++#endif + baud = uart_get_baud_rate(port, termios, old, 0, 230400); + #if defined(CONFIG_M5272) + baudclk = (MCF_BUSCLK / baud) / 32; +@@ -331,6 +391,23 @@ static void mcf_tx_chars(struct mcf_uart + while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) { + if (xmit->head == xmit->tail) + break; ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ if (port->line == SERIAL_IRDA_LINE) { ++ while (!((readb(port->membase + MCFUART_USR))\ ++ & MCFUART_USR_TXEMPTY)) ++ ; ++ /* delay for settle */ ++#if defined(CONFIG_M548X) ++ udelay(1); ++#elif defined(CONFIG_M547X) ++ udelay(2); ++#else ++ int i = 0; ++ while (i++ < 25000) ++ udelay(1); ++#endif ++ } ++#endif + writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); + port->icount.tx++; +@@ -340,6 +417,16 @@ static void mcf_tx_chars(struct mcf_uart + uart_write_wakeup(port); + + if (xmit->head == xmit->tail) { ++#ifdef CONFIG_SERIAL_COLDFIRE_IRDA ++ if (port->line == SERIAL_IRDA_LINE) { ++ /* Enable receiver for IRDA */ ++ writeb(MCFUART_UCR_CMDRESETRX,\ ++ port->membase + MCFUART_UCR); ++ /* reset RX */ ++ writeb(MCFUART_UCR_TXENABLE | MCFUART_UCR_RXENABLE,\ ++ port->membase + MCFUART_UCR); ++ } ++#endif + pp->imr &= ~MCFUART_UIR_TXREADY; + writeb(pp->imr, port->membase + MCFUART_UIMR); + } diff --git a/target/linux/coldfire/patches/006-Add-FEC-driver-support-for-MCF5445x-MCF5441x-MCF547x.patch b/target/linux/coldfire/patches/006-Add-FEC-driver-support-for-MCF5445x-MCF5441x-MCF547x.patch new file mode 100644 index 000000000..aa13146ab --- /dev/null +++ b/target/linux/coldfire/patches/006-Add-FEC-driver-support-for-MCF5445x-MCF5441x-MCF547x.patch @@ -0,0 +1,2759 @@ +From 9be336132025e7670790cdc9c24a81c23e893484 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:40 +0800 +Subject: [PATCH 06/52] Add FEC driver support for MCF5445x/MCF5441x/MCF547x/MCF548x + +Add FEC driver support for MCF5445x/MCF5441x/MCF547x/MCF548x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5441x/fec.c | 172 +++++ + arch/m68k/coldfire/m5445x/fec.c | 143 ++++ + drivers/net/Kconfig | 33 +- + drivers/net/Makefile | 1 + + drivers/net/fec.c | 27 +- + drivers/net/fec.h | 7 +- + drivers/net/fec_m547x.c | 1551 +++++++++++++++++++++++++++++++++++++++ + drivers/net/fec_m547x.h | 241 ++++++ + drivers/net/phy/Kconfig | 15 + + drivers/net/phy/Makefile | 3 + + drivers/net/phy/broadcom522x.c | 170 +++++ + drivers/net/phy/national836x.c | 104 +++ + drivers/net/phy/national8384x.c | 110 +++ + 13 files changed, 2566 insertions(+), 11 deletions(-) + create mode 100644 arch/m68k/coldfire/m5441x/fec.c + create mode 100644 arch/m68k/coldfire/m5445x/fec.c + create mode 100644 drivers/net/fec_m547x.c + create mode 100644 drivers/net/fec_m547x.h + create mode 100644 drivers/net/phy/broadcom522x.c + create mode 100644 drivers/net/phy/national836x.c + create mode 100644 drivers/net/phy/national8384x.c + +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/fec.c +@@ -0,0 +1,172 @@ ++/* ++ * fec.c on m5441x platform ++ * ++ * Sub-architcture dependant initialization code for the Freescale ++ * 5441X FEC module. ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ShrekWu B16972@freescale.com ++ * Alison Wang b18965@freescale.com ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/param.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/device.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/spinlock.h> ++#include <linux/workqueue.h> ++#include <linux/platform_device.h> ++#include <linux/fec.h> ++#include <linux/io.h> ++ ++#include <asm/pgtable.h> ++#include <asm/traps.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/mcf5441x_dtim.h> ++ ++static struct resource fec0_resources[] = { ++ [0] = { ++ .start = MCF_MBAR + 0xfc0d4000, ++ .end = MCF_MBAR + 0xfc0d42ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = (64 + 36), ++ .end = (64 + 36), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = (64 + 40), ++ .end = (64 + 40), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = (64 + 42), ++ .end = (64 + 42), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++#if defined(CONFIG_FEC2) ++static struct resource fec1_resources[] = { ++ [0] = { ++ .start = MCF_MBAR + 0xfc0d8000, ++ .end = MCF_MBAR + 0xfc0d82ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = (64 + 13 + 36), ++ .end = (64 + 13 + 36), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = (64 + 13 + 40), ++ .end = (64 + 13 + 40), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = (64 + 13 + 42), ++ .end = (64 + 13 + 42), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++#endif ++ ++static struct fec_platform_data m54418_fec_pdata = { ++ .phy = PHY_INTERFACE_MODE_RMII, ++}; ++ ++static struct platform_device fec0_coldfire_device = { ++ .name = "m54418-fec", ++ .id = 0, ++ .resource = fec0_resources, ++ .num_resources = ARRAY_SIZE(fec0_resources), ++ .dev = { ++ .platform_data = &m54418_fec_pdata, ++ } ++}; ++ ++#if defined(CONFIG_FEC2) ++static struct platform_device fec1_coldfire_device = { ++ .name = "m54418-fec", ++ .id = 1, ++ .resource = fec1_resources, ++ .num_resources = ARRAY_SIZE(fec1_resources), ++ .dev = { ++ .platform_data = &m54418_fec_pdata, ++ } ++}; ++#endif ++ ++static struct platform_device *fec_device[] = { ++ &fec0_coldfire_device, ++#if defined(CONFIG_FEC2) ++ &fec1_coldfire_device, ++#endif ++}; ++ ++static int __init mcf5441x_fec_dev_init(void) ++{ ++ int retval = 0; ++ ++ MCF_GPIO_PAR_FEC = ++ (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC_MASK) | ++ MCF_GPIO_PAR_FEC_FEC_RMII0FUL_ULPI; ++ ++ MCF_GPIO_SRCR_FEC = 0x0C; ++ ++#if defined(CONFIG_FEC2) ++ MCF_GPIO_PAR_FEC = ++ (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC_MASK) | ++ MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL; ++ ++ MCF_GPIO_SRCR_FEC |= 0x03; ++ ++ MCF_GPIO_PAR_SIMP0H = ++ (MCF_GPIO_PAR_SIMP0H & ++ MCF_GPIO_PAR_SIMP0H_DAT_MASK) | ++ MCF_GPIO_PAR_SIMP0H_DAT_GPIO; ++ ++ MCF_GPIO_PDDR_G = ++ (MCF_GPIO_PDDR_G & ++ MCF_GPIO_PDDR_G4_MASK) | ++ MCF_GPIO_PDDR_G4_OUTPUT; ++ ++ MCF_GPIO_PODR_G = ++ (MCF_GPIO_PODR_G & ++ MCF_GPIO_PODR_G4_MASK); ++#endif ++ ++ retval = platform_add_devices(fec_device, ARRAY_SIZE(fec_device)); ++ if (retval < 0) { ++ printk(KERN_ERR "MCF5441x FEC: platform_device_register failed" ++ "with code=%d\n", retval); ++ } ++ ++ return retval; ++} ++ ++arch_initcall(mcf5441x_fec_dev_init); +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/fec.c +@@ -0,0 +1,143 @@ ++/* ++ * fec-mcf5445x.c ++ * ++ * Sub-architcture dependant initialization code for the Freescale ++ * 5445X FEC module. ++ * ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Shrek Wu B16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/param.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/device.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/spinlock.h> ++#include <linux/workqueue.h> ++#include <asm/pgtable.h> ++ ++#include <asm/traps.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++ ++static struct resource fec0_resources[] = { ++ [0] = { ++ .start = MCF_MBAR + 0xfc030000, ++ .end = MCF_MBAR + 0xfc0302ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = (64 + 36), ++ .end = (64 + 36), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = (64 + 40), ++ .end = (64 + 40), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = (64 + 42), ++ .end = (64 + 42), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++#if defined(CONFIG_FEC2) ++static struct resource fec1_resources[] = { ++ [0] = { ++ .start = MCF_MBAR + 0xfc034000, ++ .end = MCF_MBAR + 0xfc0342ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = (64 + 13 + 36), ++ .end = (64 + 13 + 36), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = (64 + 13 + 40), ++ .end = (64 + 13 + 40), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = (64 + 13 + 42), ++ .end = (64 + 13 + 42), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++#endif ++ ++static struct platform_device fec0_coldfire_device = { ++ .name = "fec", ++ .id = 0, ++ .resource = fec0_resources, ++ .num_resources = ARRAY_SIZE(fec0_resources), ++}; ++ ++#if defined(CONFIG_FEC2) ++static struct platform_device fec1_coldfire_device = { ++ .name = "fec", ++ .id = 1, ++ .resource = fec1_resources, ++ .num_resources = ARRAY_SIZE(fec1_resources), ++}; ++#endif ++ ++static struct platform_device *fec_device[] = { ++ &fec0_coldfire_device, ++#if defined(CONFIG_FEC2) ++ &fec1_coldfire_device, ++#endif ++}; ++ ++static int __init mcf5445x_fec_dev_init(void) ++{ ++ int retval = 0; ++ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC0_MASK) | ++ MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO; ++ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC1_MASK) | ++ MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO; ++ ++ MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 | ++ MCF_GPIO_PAR_FECI2C_MDC0_MDC0); ++ ++ MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 | ++ MCF_GPIO_PAR_FECI2C_MDC1_MDC1); ++ ++ retval = platform_add_devices(fec_device, ARRAY_SIZE(fec_device)); ++ if (retval < 0) { ++ printk(KERN_ERR "MCF5445x FEC: platform_device_register failed" ++ "with code=%d\n", ++ retval); ++ } ++ ++ return retval; ++} ++ ++arch_initcall(mcf5445x_fec_dev_init); +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -1943,13 +1943,44 @@ config 68360_ENET + + config FEC + bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)" +- depends on M523x || M527x || M5272 || M528x || M520x || M532x || \ ++ depends on M523x || M527x || M5272 || M528x || M520x || M532x || M5445X || M5441X || \ + MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28 + select PHYLIB + help + Say Y here if you want to use the built-in 10/100 Fast ethernet + controller on some Motorola ColdFire and Freescale i.MX processors. + ++ ++config FEC2 ++ bool "Second FEC ethernet controller (on some ColdFire CPUs)" ++ depends on FEC && (M54455 || M5441X) ++ help ++ Say Y here if you want to use the second built-in 10/100 Fast ++ ethernet controller on some Motorola ColdFire processors. ++ ++config FEC_548x ++ tristate "MCF547x/MCF548x Fast Ethernet Controller support" ++ depends on M547X_8X ++ help ++ The MCF547x and MCF548x have a built-in Fast Ethernet Controller. ++ Saying Y here will include support for this device in the kernel. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called fecm. ++ ++config FEC_548x_ENABLE_FEC2 ++ bool "Enable the second FEC" ++ depends on FEC_548x ++ help ++ This enables the second FEC on the 547x/548x. If you want to use ++ it, say Y. ++ ++config FEC_548x_SHARED_PHY ++ bool "Shared PHY interface(on some ColdFire designs)" ++ depends on FEC_548x_ENABLE_FEC2 ++ help ++ Say Y here if both PHYs are controlled via a single channel. ++ + config FEC_MPC52xx + tristate "MPC52xx FEC driver" + depends on PPC_MPC52xx && PPC_BESTCOMM +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -123,6 +123,7 @@ obj-$(CONFIG_PCMCIA_PCNET) += 8390.o + obj-$(CONFIG_HP100) += hp100.o + obj-$(CONFIG_SMC9194) += smc9194.o + obj-$(CONFIG_FEC) += fec.o ++obj-$(CONFIG_FEC_548x) += fec_m547x.o + obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o + ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y) + obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o +--- a/drivers/net/fec.c ++++ b/drivers/net/fec.c +@@ -18,7 +18,7 @@ + * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) + * Copyright (c) 2004-2006 Macq Electronique SA. + * +- * Copyright (C) 2010 Freescale Semiconductor, Inc. ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + #include <linux/module.h> +@@ -74,6 +74,9 @@ static struct platform_device_id fec_dev + }, { + .name = "imx28-fec", + .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, ++ }, { ++ .name = "m54418-fec", ++ .driver_data = FEC_QUIRK_ENET_MAC, + }, + { } + }; +@@ -148,8 +151,9 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet + * account when setting it. + */ + #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ +- defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ +- defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) ++ defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ ++ defined(CONFIG_M5445X) || defined(CONFIG_M5441X) || \ ++ defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) + #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) + #else + #define OPT_FRAME_SIZE 0 +@@ -400,7 +404,8 @@ fec_enet_tx(struct net_device *dev) + if (bdp == fep->cur_tx && fep->tx_full == 0) + break; + +- dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); ++/* dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, \ ++ FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);*/ + bdp->cbd_bufaddr = 0; + + skb = fep->tx_skbuff[fep->skb_dirty]; +@@ -527,8 +532,8 @@ fec_enet_rx(struct net_device *dev) + dev->stats.rx_bytes += pkt_len; + data = (__u8*)__va(bdp->cbd_bufaddr); + +- dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, +- DMA_FROM_DEVICE); ++/* dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, ++ DMA_FROM_DEVICE);*/ + + if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) + swap_buffer(data, pkt_len); +@@ -552,8 +557,8 @@ fec_enet_rx(struct net_device *dev) + netif_rx(skb); + } + +- bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, +- DMA_FROM_DEVICE); ++/* bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, ++ DMA_FROM_DEVICE);*/ + rx_processing_done: + /* Clear the status flags for this buffer */ + status &= ~BD_ENET_RX_STATS; +@@ -632,6 +637,8 @@ static void __inline__ fec_get_mac(struc + static void fec_enet_adjust_link(struct net_device *dev) + { + struct fec_enet_private *fep = netdev_priv(dev); ++ const struct platform_device_id *id_entry = ++ platform_get_device_id(fep->pdev); + struct phy_device *phy_dev = fep->phy_dev; + unsigned long flags; + +@@ -660,6 +667,10 @@ static void fec_enet_adjust_link(struct + fec_restart(dev, phy_dev->duplex); + else + fec_stop(dev); ++ ++ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) ++ writel(2, fep->hwp + FEC_ECNTRL); ++ + status_change = 1; + } + +--- a/drivers/net/fec.h ++++ b/drivers/net/fec.h +@@ -4,6 +4,7 @@ + * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC + * processors. + * ++ * Copyright (C) 2011 Freescale Semiconductor,Inc. All Rights Reserved. + * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000-2001, Lineo (www.lineo.com) + */ +@@ -14,8 +15,10 @@ + /****************************************************************************/ + + #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ +- defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ +- defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) ++ defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ ++ defined(CONFIG_M537x) || defined(CONFIG_M5301x) || \ ++ defined(CONFIG_M5445X) || defined(CONFIG_M5441X) || \ ++ defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) + /* + * Just figures, Motorola would have to change the offsets for + * registers in the same peripheral device on different models +--- /dev/null ++++ b/drivers/net/fec_m547x.c +@@ -0,0 +1,1551 @@ ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Kurt Mahan, kmahan@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/string.h> ++#include <linux/ptrace.h> ++#include <linux/errno.h> ++#include <linux/ioport.h> ++#include <linux/slab.h> ++#include <linux/interrupt.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/phy.h> ++#include <linux/delay.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/spinlock.h> ++#include <linux/workqueue.h> ++#include <linux/bitops.h> ++ ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++ ++#include <asm/dma.h> ++#include <asm/MCD_dma.h> ++#include <asm/m5485sram.h> ++#include <asm/virtconvert.h> ++#include <asm/irq.h> ++ ++#include "fec_m547x.h" ++ ++#ifdef CONFIG_FEC_548x_ENABLE_FEC2 ++#define FEC_MAX_PORTS 2 ++#define FEC_2 ++#else ++#define FEC_MAX_PORTS 1 ++#undef FEC_2 ++#endif ++ ++#define VERSION "0.20" ++MODULE_DESCRIPTION("DMA Fast Ethernet Controller driver ver " VERSION); ++ ++/* fec private */ ++struct fec_priv { ++ struct net_device *netdev; /* owning net device */ ++ void *fecpriv_txbuf[FEC_TX_BUF_NUMBER]; /* tx buffer ptrs */ ++ MCD_bufDescFec *fecpriv_txdesc; /* tx descriptor ptrs */ ++ volatile unsigned int fecpriv_current_tx; /* current tx desc index */ ++ volatile unsigned int fecpriv_next_tx; /* next tx desc index */ ++ unsigned int fecpriv_current_rx; /* current rx desc index */ ++ MCD_bufDescFec *fecpriv_rxdesc; /* rx descriptor ptrs */ ++ struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; /* rx SKB ptrs */ ++ unsigned int fecpriv_initiator_rx; /* rx dma initiator */ ++ unsigned int fecpriv_initiator_tx; /* tx dma initiator */ ++ int fecpriv_fec_rx_channel; /* rx dma channel */ ++ int fecpriv_fec_tx_channel; /* tx dma channel */ ++ int fecpriv_rx_requestor; /* rx dma requestor */ ++ int fecpriv_tx_requestor; /* tx dma requestor */ ++ void *fecpriv_interrupt_fec_rx_handler; /* dma rx handler */ ++ void *fecpriv_interrupt_fec_tx_handler; /* dma tx handler */ ++ unsigned char *fecpriv_mac_addr; /* private fec mac addr */ ++ struct net_device_stats fecpriv_stat; /* stats ptr */ ++ spinlock_t fecpriv_lock; ++ int fecpriv_rxflag; ++ struct tasklet_struct fecpriv_tasklet_reinit; ++ int index; /* fec hw number */ ++ struct phy_device *phydev; ++ struct mii_bus *mdio_bus; ++ int duplex; ++ int link; ++ int speed; ++}; ++ ++struct net_device *fec_dev[FEC_MAX_PORTS]; ++ ++/* FEC functions */ ++static int __init fec_init(void); ++/* ++static struct net_device_stats *fec_get_stat(struct net_device *dev); ++static int fec_open(struct net_device *dev); ++static int fec_close(struct net_device *nd); ++static int fec_tx(struct sk_buff *skb, struct net_device *dev); ++static void fec_set_multicast_list(struct net_device *nd); ++static int fec_set_mac_address(struct net_device *dev, void *p); ++static void fec_tx_timeout(struct net_device *dev); ++*/ ++static void fec_interrupt_fec_tx_handler(struct net_device *dev); ++static void fec_interrupt_fec_rx_handler(struct net_device *dev); ++static irqreturn_t fec_interrupt_handler(int irq, void *dev_id); ++static void fec_interrupt_fec_tx_handler_fec0(void); ++static void fec_interrupt_fec_rx_handler_fec0(void); ++static void fec_interrupt_fec_reinit(unsigned long data); ++ ++/* default fec0 address */ ++unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 }; ++ ++#ifdef FEC_2 ++/* default fec1 address */ ++unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 }; ++#endif ++ ++extern unsigned char uboot_enet0[]; ++extern unsigned char uboot_enet1[]; ++ ++#ifndef MODULE ++int fec_str_to_mac(char *str_mac, unsigned char* addr); ++int __init fec_mac_setup0(char *s); ++#endif ++ ++ ++#ifdef FEC_2 ++void fec_interrupt_fec_tx_handler_fec1(void); ++void fec_interrupt_fec_rx_handler_fec1(void); ++#endif ++ ++#ifndef MODULE ++int __init fec_mac_setup1(char *s); ++#endif ++ ++module_init(fec_init); ++/* module_exit(fec_cleanup); */ ++ ++__setup("mac0=", fec_mac_setup0); ++ ++#ifdef FEC_2 ++__setup("mac1=", fec_mac_setup1); ++#endif ++ ++#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) ++#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ ++ (VAL & 0xffff)) ++/* ----------------------------------------------------------- */ ++static int coldfire_fec_mdio_read(struct mii_bus *bus, ++ int phy_id, int reg) ++{ ++ int ret; ++#ifdef CONFIG_FEC_548x_SHARED_PHY ++ unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0; ++#else ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++#endif ++ int tries = 100; ++ ++ /* Clear the MII interrupt bit */ ++ FEC_EIR(base_addr) = FEC_EIR_MII; ++ ++ /* Write to the MII management frame register */ ++ FEC_MMFR(base_addr) = mk_mii_read(reg) | (phy_id << 23); ++ ++ /* Wait for the reading */ ++ while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) { ++ udelay(10); ++ ++ if (!tries) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -ETIMEDOUT; ++ } ++ tries--; ++ } ++ ++ /* Clear the MII interrupt bit */ ++ FEC_EIR(base_addr) = FEC_EIR_MII; ++ ret = FEC_MMFR(base_addr) & 0x0000FFFF; ++ return ret; ++} ++ ++static int coldfire_fec_mdio_write(struct mii_bus *bus, ++ int phy_id, int reg, u16 data) ++{ ++ int ret; ++#ifdef CONFIG_FEC_548x_SHARED_PHY ++ unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0; ++#else ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++#endif ++ int tries = 100; ++ ++ printk(KERN_ERR "%s base_addr %lx, phy_id %x, reg %x, data %x\n", ++ __func__, base_addr, phy_id, reg, data); ++ /* Clear the MII interrupt bit */ ++ FEC_EIR(base_addr) = FEC_EIR_MII; ++ ++ /* Write to the MII management frame register */ ++ FEC_MMFR(base_addr) = mk_mii_write(reg, data) | (phy_id << 23); ++ ++ /* Wait for the writing */ ++ while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) { ++ udelay(10); ++ if (!tries) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -ETIMEDOUT; ++ } ++ tries--; ++ } ++ /* Clear the MII interrupt bit */ ++ FEC_EIR(base_addr) = FEC_EIR_MII; ++ ret = FEC_MMFR(base_addr) & 0x0000FFFF; ++ ++ return ret; ++} ++ ++static void fec_adjust_link(struct net_device *dev) ++{ ++ struct fec_priv *priv = netdev_priv(dev); ++ struct phy_device *phydev = priv->phydev; ++ int new_state = 0; ++ ++ if (phydev->link != PHY_DOWN) { ++ if (phydev->duplex != priv->duplex) { ++ new_state = 1; ++ priv->duplex = phydev->duplex; ++ } ++ ++ if (phydev->speed != priv->speed) { ++ new_state = 1; ++ priv->speed = phydev->speed; ++ } ++ ++ if (priv->link == PHY_DOWN) { ++ new_state = 1; ++ priv->link = phydev->link; ++ } ++ } else if (priv->link) { ++ new_state = 1; ++ priv->link = PHY_DOWN; ++ priv->speed = 0; ++ priv->duplex = -1; ++ } ++ ++ if (new_state) ++ phy_print_status(phydev); ++} ++ ++static int coldfire_fec_init_phy(struct net_device *dev) ++{ ++ struct fec_priv *priv = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ int i; ++ int startnode; ++ ++#ifdef CONFIG_FEC_548x_SHARED_PHY ++ if (priv->index == 0) ++ startnode = 0; ++ else if (priv->index == 1) { ++ struct fec_priv *priv0 = netdev_priv(fec_dev[0]); ++ startnode = priv0->phydev->addr + 1; ++ } else ++ startnode = 0; ++#else ++ startnode = 0; ++#endif ++#ifdef FEC_DEBUG ++ printk(KERN_ERR "%s priv->index %x, startnode %x\n", ++ __func__, priv->index, startnode); ++#endif ++ /* search for connect PHY device */ ++ for (i = startnode; i < PHY_MAX_ADDR; i++) { ++ struct phy_device *const tmp_phydev = ++ priv->mdio_bus->phy_map[i]; ++ ++ if (!tmp_phydev) { ++#ifdef FEC_DEBUG ++ printk(KERN_INFO "%s no PHY here at" ++ "mii_bus->phy_map[%d]\n", ++ __func__, i); ++#endif ++ continue; /* no PHY here... */ ++ } ++ phydev = tmp_phydev; ++#ifdef FEC_DEBUG ++ printk(KERN_INFO "%s find PHY here at" ++ "mii_bus->phy_map[%d]\n", ++ __func__, i); ++#endif ++ break; /* found it */ ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ if (!phydev) { ++ printk(KERN_INFO "%s: Don't found any phy device at all\n", ++ dev->name); ++ return -ENODEV; ++ } ++ ++ priv->link = 0; ++ priv->speed = 0; ++ priv->duplex = 0; ++#ifdef FEC_DEBUG ++ printk(KERN_INFO "%s phydev_busid %s\n", __func__, phydev->dev.bus_id); ++#endif ++ phydev = phy_connect(dev, dev_name(&phydev->dev), ++ &fec_adjust_link, 0, PHY_INTERFACE_MODE_MII); ++ if (IS_ERR(phydev)) { ++ printk(KERN_ERR " %s phy_connect failed\n", __func__); ++ return PTR_ERR(phydev); ++ } ++ ++ printk(KERN_INFO "attached phy %i to driver %s\n", ++ phydev->addr, phydev->drv->name); ++ priv->phydev = phydev; ++ return 0; ++} ++ ++static int fec_mdio_register(struct net_device *dev, ++ int slot) ++{ ++ int err = 0; ++ struct fec_priv *fp = netdev_priv(dev); ++ ++ fp->mdio_bus = mdiobus_alloc(); ++ if (!fp->mdio_bus) { ++ printk(KERN_ERR "ethernet mdiobus_alloc fail\n"); ++ return -ENOMEM; ++ } ++ ++ if (slot == 0) { ++ fp->mdio_bus->name = "Coldfire FEC MII 0 Bus"; ++ strcpy(fp->mdio_bus->id, "0"); ++ } else if (slot == 1) { ++ fp->mdio_bus->name = "Coldfire FEC MII 1 Bus"; ++ strcpy(fp->mdio_bus->id, "1"); ++ } else { ++ printk(KERN_ERR "Now coldfire can not" ++ "support more than 2 mii bus\n"); ++ } ++ ++ fp->mdio_bus->read = &coldfire_fec_mdio_read; ++ fp->mdio_bus->write = &coldfire_fec_mdio_write; ++ fp->mdio_bus->priv = dev; ++ err = mdiobus_register(fp->mdio_bus); ++ if (err) { ++ mdiobus_free(fp->mdio_bus); ++ printk(KERN_ERR "%s: ethernet mdiobus_register fail %d\n", ++ dev->name, err); ++ return -EIO; ++ } ++ ++ printk(KERN_INFO "mdiobus_register %s ok\n", ++ fp->mdio_bus->name); ++ return err; ++} ++ ++/************************************************************************ ++* NAME: mcf547x_fec_open ++* ++* DESCRIPTION: This function performs the initialization of ++* of FEC and corresponding KS8721 transiver ++* ++* RETURNS: If no error occurs, this function returns zero. ++*************************************************************************/ ++static int mcf547x_fec_open(struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ int fduplex; ++ int i; ++ int channel; ++ int error_code = -EBUSY; ++ ++ fp->link = 0; ++ fp->duplex = 0; ++ fp->speed = 0; ++ coldfire_fec_init_phy(dev); ++ phy_start(fp->phydev); ++ ++ /* Receive the DMA channels */ ++ channel = dma_set_channel_fec(fp->fecpriv_rx_requestor); ++ ++ if (channel == -1) { ++ printk(KERN_ERR "Dma channel cannot be reserved\n"); ++ goto ERRORS; ++ } ++ ++ fp->fecpriv_fec_rx_channel = channel; ++ ++ dma_connect(channel, (int) fp->fecpriv_interrupt_fec_rx_handler); ++ ++ channel = dma_set_channel_fec(fp->fecpriv_tx_requestor); ++ ++ if (channel == -1) { ++ printk(KERN_ERR "Dma channel cannot be reserved\n"); ++ goto ERRORS; ++ } ++ ++ fp->fecpriv_fec_tx_channel = channel; ++ ++ dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler); ++ ++ /* init tasklet for controller reinitialization */ ++ tasklet_init(&fp->fecpriv_tasklet_reinit, ++ fec_interrupt_fec_reinit, (unsigned long) dev); ++ ++ /* Reset FIFOs */ ++ FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL; ++ FEC_FECFRST(base_addr) &= ~FEC_SW_RST; ++ ++ /* Reset and disable FEC */ ++ FEC_ECR(base_addr) = FEC_ECR_RESET; ++ ++ udelay(10); ++ ++ /* Clear all events */ ++ FEC_EIR(base_addr) = FEC_EIR_CLEAR; ++ ++ /* Reset FIFO status */ ++ FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK; ++ FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK; ++ ++ /* Set the default address */ ++ FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | ++ (fp->fecpriv_mac_addr[1] << 16) | ++ (fp->fecpriv_mac_addr[2] << 8) | ++ fp->fecpriv_mac_addr[3]; ++ FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | ++ (fp->fecpriv_mac_addr[5] << 16) | 0x8808; ++ ++ /* Reset the group address descriptor */ ++ FEC_GALR(base_addr) = 0x00000000; ++ FEC_GAUR(base_addr) = 0x00000000; ++ ++ /* Reset the individual address descriptor */ ++ FEC_IALR(base_addr) = 0x00000000; ++ FEC_IAUR(base_addr) = 0x00000000; ++ ++ /* Set the receive control register */ ++ FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII; ++ ++ /* Set the receive FIFO control register */ ++ /*FEC_FECRFCR(base_addr) = ++ * FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;*/ ++ FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR ++ | (FEC_FECRFCR_MSK ++ /* disable all but ...*/ ++ & ~FEC_FECRFCR_FAE ++ /* enable frame accept error*/ ++ & ~FEC_FECRFCR_RXW ++ /* enable receive wait condition*/ ++ /*& ~FEC_FECRFCR_UF*/ ++ /* enable FIFO underflow*/ ++ ); ++ ++ /* Set the receive FIFO alarm register */ ++ FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM; ++ ++ /* Set the transmit FIFO control register */ ++ /*FEC_FECTFCR(base_addr) = ++ FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;*/ ++ FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR ++ | (FEC_FECTFCR_MSK ++ /* disable all but ... */ ++ & ~FEC_FECTFCR_FAE ++ /* enable frame accept error */ ++ /* & ~FEC_FECTFCR_TXW */ ++ /*enable transmit wait condition*/ ++ /*& ~FEC_FECTFCR_UF*/ ++ /*enable FIFO underflow*/ ++ & ~FEC_FECTFCR_OF); ++ /* enable FIFO overflow */ ++ ++ /* Set the transmit FIFO alarm register */ ++ FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM; ++ ++ /* Set the Tx FIFO watermark */ ++ FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK; ++ ++ /* Enable the transmitter to append the CRC */ ++ FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC; ++ ++ /* Enable the ethernet interrupts */ ++ /*FEC_EIMR(base_addr) = FEC_EIMR_MASK;*/ ++ FEC_EIMR(base_addr) = FEC_EIMR_DISABLE ++ | FEC_EIR_LC ++ | FEC_EIR_RL ++ | FEC_EIR_HBERR ++ | FEC_EIR_XFUN ++ | FEC_EIR_XFERR ++ | FEC_EIR_RFERR; ++ ++#if 0 ++ error_code = init_transceiver(base_addr, &fduplex); ++ if (error_code != 0) { ++ printk(KERN_ERR "Initialization of the " ++ "transceiver is failed\n"); ++ goto ERRORS; ++ } ++#else ++ fduplex = 1; ++#endif ++ if (fduplex) ++ /* Enable the full duplex mode */ ++ FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC; ++ else ++ /* Disable reception of frames while transmitting */ ++ FEC_RCR(base_addr) |= FEC_RCR_DRT; ++ ++ /* Enable MIB */ ++ FEC_MIBC(base_addr) = FEC_MIBC_ENABLE; ++ ++ /* Enable FEC */ ++ FEC_ECR(base_addr) |= FEC_ECR_ETHEREN; ++ FEC_MSCR(dev->base_addr) = FEC_MII_SPEED; ++ /* Initialize tx descriptors and start DMA for the transmission */ ++ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) ++ fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT; ++ ++ fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP; ++ ++ fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; ++ ++ MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0, ++ (unsigned char *) &(FEC_FECTFDR(base_addr)), 0, ++ FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx, ++ FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT, ++ MCD_NO_CSUM | MCD_NO_BYTE_SWAP); ++ ++ /* Initialize rx descriptors and start DMA for the reception */ ++ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) { ++ fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA); ++ if (!fp->askb_rx[i]) { ++ fp->fecpriv_rxdesc[i].dataPointer = 0; ++ fp->fecpriv_rxdesc[i].statCtrl = 0; ++ fp->fecpriv_rxdesc[i].length = 0; ++ } else { ++ skb_reserve(fp->askb_rx[i], 16); ++ fp->askb_rx[i]->dev = dev; ++ fp->fecpriv_rxdesc[i].dataPointer = ++ (unsigned int)virt_to_phys(fp->askb_rx[i]->tail); ++ fp->fecpriv_rxdesc[i].statCtrl = ++ MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT; ++ fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE; ++ } ++ } ++ ++ fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP; ++ fp->fecpriv_current_rx = 0; ++ ++ MCD_startDma(fp->fecpriv_fec_rx_channel, (char *) fp->fecpriv_rxdesc, 0, ++ (unsigned char *) &(FEC_FECRFDR(base_addr)), 0, ++ FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx, ++ FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT, ++ MCD_NO_CSUM | MCD_NO_BYTE_SWAP); ++ ++ netif_start_queue(dev); ++ return 0; ++ ++ERRORS: ++ ++ /* Remove the channels and return with the error code */ ++ if (fp->fecpriv_fec_rx_channel != -1) { ++ dma_disconnect(fp->fecpriv_fec_rx_channel); ++ dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel); ++ fp->fecpriv_fec_rx_channel = -1; ++ } ++ ++ if (fp->fecpriv_fec_tx_channel != -1) { ++ dma_disconnect(fp->fecpriv_fec_tx_channel); ++ dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel); ++ fp->fecpriv_fec_tx_channel = -1; ++ } ++ ++ return error_code; ++} ++ ++/************************************************************************ ++* NAME: mcf547x_fec_close ++* ++* DESCRIPTION: This function performs the graceful stop of the ++* transmission and disables FEC ++* ++* RETURNS: This function always returns zero. ++*************************************************************************/ ++static int mcf547x_fec_close(struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ unsigned long time; ++ int i; ++ ++ netif_stop_queue(dev); ++ phy_disconnect(fp->phydev); ++ phy_stop(fp->phydev); ++ /* Perform the graceful stop */ ++ FEC_TCR(base_addr) |= FEC_TCR_GTS; ++ ++ time = jiffies; ++ ++ /* Wait for the graceful stop */ ++ while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time < ++ (FEC_GR_TIMEOUT * HZ)) ++ schedule(); ++ ++ /* Disable FEC */ ++ FEC_ECR(base_addr) = FEC_ECR_DISABLE; ++ ++ /* Reset the DMA channels */ ++ spin_lock_irq(&fp->fecpriv_lock); ++ MCD_killDma(fp->fecpriv_fec_tx_channel); ++ spin_unlock_irq(&fp->fecpriv_lock); ++ dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel); ++ dma_disconnect(fp->fecpriv_fec_tx_channel); ++ fp->fecpriv_fec_tx_channel = -1; ++ ++ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) { ++ kfree(fp->fecpriv_txbuf[i]); ++ fp->fecpriv_txbuf[i] = NULL; ++ } ++ ++ spin_lock_irq(&fp->fecpriv_lock); ++ MCD_killDma(fp->fecpriv_fec_rx_channel); ++ spin_unlock_irq(&fp->fecpriv_lock); ++ ++ dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel); ++ dma_disconnect(fp->fecpriv_fec_rx_channel); ++ fp->fecpriv_fec_rx_channel = -1; ++ ++ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) { ++ if (fp->askb_rx[i]) { ++ kfree_skb(fp->askb_rx[i]); ++ fp->askb_rx[i] = NULL; ++ } ++ } ++ ++ return 0; ++} ++ ++/************************************************************************ ++* +NAME: mcf547x_fec_get_stat ++* ++* RETURNS: This function returns the statistical information. ++*************************************************************************/ ++static struct net_device_stats *mcf547x_fec_get_stats(struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = dev->base_addr; ++ ++ /* Receive the statistical information */ ++ fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr); ++ fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr); ++ fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr); ++ fp->fecpriv_stat.tx_bytes = FECSTAT_RMON_T_OCTETS(base_addr); ++ ++ fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr); ++ fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr); ++ ++ fp->fecpriv_stat.rx_length_errors = ++ FECSTAT_RMON_R_UNDERSIZE(base_addr) + ++ FECSTAT_RMON_R_OVERSIZE(base_addr) + ++ FECSTAT_RMON_R_FRAG(base_addr) + ++ FECSTAT_RMON_R_JAB(base_addr); ++ fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr); ++ fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr); ++ fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr); ++ ++ fp->fecpriv_stat.tx_carrier_errors = FECSTAT_IEEE_T_CSERR(base_addr); ++ fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr); ++ fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr); ++ ++ /* I hope that one frame doesn't have more than one error */ ++ fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors + ++ fp->fecpriv_stat.rx_crc_errors + ++ fp->fecpriv_stat.rx_frame_errors + ++ fp->fecpriv_stat.rx_over_errors + ++ fp->fecpriv_stat.rx_dropped; ++ fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors + ++ fp->fecpriv_stat.tx_fifo_errors + ++ fp->fecpriv_stat.tx_window_errors + ++ fp->fecpriv_stat.tx_aborted_errors + ++ fp->fecpriv_stat.tx_heartbeat_errors + ++ fp->fecpriv_stat.tx_dropped; ++ ++ return &fp->fecpriv_stat; ++} ++ ++/************************************************************************ ++* NAME: mcf547x_fec_set_multicast_list ++* ++* DESCRIPTION: This function sets the frame filtering parameters ++*************************************************************************/ ++static void mcf547x_fec_set_multicast_list(struct net_device *dev) ++{ ++ unsigned int crc, data; ++ int j, k; ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ struct netdev_hw_addr *ha; ++ ++ if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI) { ++ /* Allow all incoming frames */ ++ FEC_GALR(base_addr) = 0xFFFFFFFF; ++ FEC_GAUR(base_addr) = 0xFFFFFFFF; ++ return; ++ } ++ ++ /* Reset the group address register */ ++ FEC_GALR(base_addr) = 0x00000000; ++ FEC_GAUR(base_addr) = 0x00000000; ++ ++ /* Process all addresses */ ++ netdev_for_each_mc_addr(ha, dev) { ++ /* Processing must be only for the group addresses */ ++ if (!(ha->addr[0] & 1)) ++ continue; ++ ++ /* Calculate crc value for the current address */ ++ crc = 0xFFFFFFFF; ++ for (j = 0; j < dev->addr_len; j++) { ++ data = ha->addr[j]; ++ for (k = 0; k < 8; k++, data >>= 1) { ++ if ((crc ^ data) & 1) ++ crc = (crc >> 1) ^ FEC_CRCPOL; ++ else ++ crc >>= 1; ++ } ++ } ++ ++ /* Add this value */ ++ crc >>= 26; ++ crc &= 0x3F; ++ if (crc > 31) ++ FEC_GAUR(base_addr) |= 0x1 << (crc - 32); ++ else ++ FEC_GALR(base_addr) |= 0x1 << crc; ++ } ++} ++ ++/************************************************************************ ++* NAME: mcf547x_fec_set_mac_address ++* ++* DESCRIPTION: This function sets the MAC address ++*************************************************************************/ ++static int mcf547x_fec_set_mac_address(struct net_device *dev, void *p) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ struct sockaddr *addr = p; ++ ++ if (netif_running(dev)) ++ return -EBUSY; ++ ++ /* Copy a new address to the device structure */ ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ ++ /* Copy a new address to the private structure */ ++ memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6); ++ ++ /* Set the address to the registers */ ++ FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | ++ (fp->fecpriv_mac_addr[1] << 16) | ++ (fp->fecpriv_mac_addr[2] << 8) | ++ fp->fecpriv_mac_addr[3]; ++ FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | ++ (fp->fecpriv_mac_addr[5] << 16) | ++ 0x8808; ++ ++ return 0; ++} ++ ++/************************************************************************ ++* NAME: mcf547x_fec_start_xmit ++* ++* DESCRIPTION: This function starts transmission of the frame using DMA ++* ++* RETURNS: This function always returns zero. ++*************************************************************************/ ++static int mcf547x_fec_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ void *data, *data_aligned; ++ int offset; ++ ++ data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC); ++ ++ if (!data) { ++ fp->fecpriv_stat.tx_dropped++; ++ dev_kfree_skb(skb); ++ return 0; ++ } ++ ++ offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) - ++ (unsigned long)virt_to_phys(data); ++ data_aligned = (void *)((unsigned long)data + offset); ++ memcpy(data_aligned, skb->data, skb->len); ++ ++ /* flush data cache before initializing ++ * the descriptor and starting DMA */ ++ ++ spin_lock_irq(&fp->fecpriv_lock); ++ ++ /* Initialize the descriptor */ ++ fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data; ++ fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer ++ = (unsigned int) virt_to_phys(data_aligned); ++ fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len; ++ fp->fecpriv_txdesc[fp->fecpriv_next_tx].statCtrl ++ |= (MCD_FEC_END_FRAME | MCD_FEC_BUF_READY); ++ fp->fecpriv_next_tx = (fp->fecpriv_next_tx + 1) & FEC_TX_INDEX_MASK; ++ ++ if (fp->fecpriv_txbuf[fp->fecpriv_current_tx] ++ && fp->fecpriv_current_tx == fp->fecpriv_next_tx) ++ netif_stop_queue(dev); ++ ++ spin_unlock_irq(&fp->fecpriv_lock); ++ ++ /* Tell the DMA to continue the transmission */ ++ MCD_continDma(fp->fecpriv_fec_tx_channel); ++ ++ dev_kfree_skb(skb); ++ ++ dev->trans_start = jiffies; ++ ++ return 0; ++} ++ ++/************************************************************************ ++* NAME: mcf547x_fec_tx_timeout ++* ++* DESCRIPTION: If the interrupt processing of received frames was lost ++* and DMA stopped the reception, this function clears ++* the transmission descriptors and starts DMA ++* ++*************************************************************************/ ++static void mcf547x_fec_tx_timeout(struct net_device *dev) ++{ ++ int i; ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ ++ spin_lock_irq(&fp->fecpriv_lock); ++ MCD_killDma(fp->fecpriv_fec_tx_channel); ++ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) { ++ kfree(fp->fecpriv_txbuf[i]); ++ fp->fecpriv_txbuf[i] = NULL; ++ fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT; ++ } ++ fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP; ++ ++ fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; ++ ++ /* Reset FIFOs */ ++ FEC_FECFRST(base_addr) |= FEC_SW_RST; ++ FEC_FECFRST(base_addr) &= ~FEC_SW_RST; ++ ++ /* Reset and disable FEC */ ++ /* FEC_ECR(base_addr) = FEC_ECR_RESET; */ ++ ++ /* Enable FEC */ ++ FEC_ECR(base_addr) |= FEC_ECR_ETHEREN; ++ ++ MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0, ++ (unsigned char *) &(FEC_FECTFDR(base_addr)), 0, ++ FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx, ++ FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT, ++ MCD_NO_CSUM | MCD_NO_BYTE_SWAP); ++ ++ spin_unlock_irq(&fp->fecpriv_lock); ++ ++ netif_wake_queue(dev); ++ ++} ++ ++static const struct net_device_ops mcf547x_fec_netdev_ops = { ++ .ndo_open = mcf547x_fec_open, ++ .ndo_stop = mcf547x_fec_close, ++ .ndo_start_xmit = mcf547x_fec_start_xmit, ++ .ndo_set_multicast_list = mcf547x_fec_set_multicast_list, ++ .ndo_set_mac_address = mcf547x_fec_set_mac_address, ++ .ndo_tx_timeout = mcf547x_fec_tx_timeout, ++ .ndo_get_stats = mcf547x_fec_get_stats, ++}; ++ ++/* ++ * Initialize a FEC device ++ */ ++int fec_enet_init(struct net_device *dev, int slot) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ int i; ++ ++ fp->index = slot; ++ fp->netdev = dev; ++ fec_dev[slot] = dev; ++ ++ if (slot == 0) { ++ /* disable fec0 */ ++ FEC_ECR(FEC_BASE_ADDR_FEC0) = FEC_ECR_DISABLE; ++ ++ /* setup the interrupt handler */ ++ dev->irq = 64 + ISC_FEC0; ++ ++ if (request_irq(dev->irq, fec_interrupt_handler, ++ IRQF_DISABLED, "ColdFire FEC 0", dev)) { ++ dev->irq = 0; ++ printk(KERN_ERR "Cannot allocate FEC0 IRQ\n"); ++ } else { ++ /* interrupt priority and level */ ++ MCF_ICR(ISC_FEC0) = ILP_FEC0; ++ } ++ ++ /* fec base address */ ++ dev->base_addr = FEC_BASE_ADDR_FEC0; ++ ++ /* requestor numbers */ ++ fp->fecpriv_rx_requestor = DMA_FEC0_RX; ++ fp->fecpriv_tx_requestor = DMA_FEC0_TX; ++ ++ /* fec0 handlers */ ++ fp->fecpriv_interrupt_fec_rx_handler = ++ fec_interrupt_fec_rx_handler_fec0; ++ fp->fecpriv_interrupt_fec_tx_handler = ++ fec_interrupt_fec_tx_handler_fec0; ++ ++ /* tx descriptors */ ++ fp->fecpriv_txdesc = (void *)FEC_TX_DESC_FEC0; ++ ++ /* rx descriptors */ ++ fp->fecpriv_rxdesc = (void *)FEC_RX_DESC_FEC0; ++ ++ /* mac addr ++ if (uboot_enet0[0] || uboot_enet0[1] || uboot_enet0[2] || ++ uboot_enet0[3] || uboot_enet0[4] || uboot_enet0[5]) { ++ use uboot enet 0 addr ++ memcpy(fec_mac_addr_fec0, uboot_enet0, 6); ++ }*/ ++ fec_mac_addr_fec0[0] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 24) & 0xFF; ++ fec_mac_addr_fec0[1] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 16) & 0xFF; ++ fec_mac_addr_fec0[2] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 8) & 0xFF; ++ fec_mac_addr_fec0[3] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC0)) & 0xFF; ++ fec_mac_addr_fec0[4] = ++ (FEC_PAUR(FEC_BASE_ADDR_FEC0) >> 24) & 0xFF; ++ fec_mac_addr_fec0[5] = ++ (FEC_PAUR(FEC_BASE_ADDR_FEC0) >> 16) & 0xFF; ++ ++ fp->fecpriv_mac_addr = fec_mac_addr_fec0; ++ } else { ++ /* disable fec1 */ ++ FEC_ECR(FEC_BASE_ADDR_FEC1) = FEC_ECR_DISABLE; ++#ifdef FEC_2 ++ /* setup the interrupt handler */ ++ dev->irq = 64 + ISC_FEC1; ++ ++ if (request_irq(dev->irq, fec_interrupt_handler, ++ IRQF_DISABLED, "ColdFire FEC 1", dev)) { ++ dev->irq = 0; ++ printk(KERN_ERR "Cannot allocate FEC1 IRQ\n"); ++ } else { ++ /* interrupt priority and level */ ++ MCF_ICR(ISC_FEC1) = ILP_FEC1; ++ } ++ ++ /* fec base address */ ++ dev->base_addr = FEC_BASE_ADDR_FEC1; ++ ++ /* requestor numbers */ ++ fp->fecpriv_rx_requestor = DMA_FEC1_RX; ++ fp->fecpriv_tx_requestor = DMA_FEC1_TX; ++ ++ /* fec1 handlers */ ++ fp->fecpriv_interrupt_fec_rx_handler = ++ fec_interrupt_fec_rx_handler_fec1; ++ fp->fecpriv_interrupt_fec_tx_handler = ++ fec_interrupt_fec_tx_handler_fec1; ++ ++ /* tx descriptors */ ++ fp->fecpriv_txdesc = (void *)FEC_TX_DESC_FEC1; ++ ++ /* rx descriptors */ ++ fp->fecpriv_rxdesc = (void *)FEC_RX_DESC_FEC1; ++ ++ /* mac addr ++ if (uboot_enet1[0] || uboot_enet1[1] || uboot_enet1[2] || ++ uboot_enet1[3] || uboot_enet1[4] || uboot_enet1[5]) { ++ use uboot enet 1 addr ++ memcpy(fec_mac_addr_fec1, uboot_enet1, 6); ++ }*/ ++ fec_mac_addr_fec1[0] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 24) & 0xFF; ++ fec_mac_addr_fec1[1] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 16) & 0xFF; ++ fec_mac_addr_fec1[2] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 8) & 0xFF; ++ fec_mac_addr_fec1[3] = ++ (FEC_PALR(FEC_BASE_ADDR_FEC1)) & 0xFF; ++ fec_mac_addr_fec1[4] = ++ (FEC_PAUR(FEC_BASE_ADDR_FEC1) >> 24) & 0xFF; ++ fec_mac_addr_fec1[5] = ++ (FEC_PAUR(FEC_BASE_ADDR_FEC1) >> 16) & 0xFF; ++ ++ fp->fecpriv_mac_addr = fec_mac_addr_fec1; ++#endif ++ } ++ ++ /* clear MIB */ ++ memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN); ++ ++ /* clear the statistics structure */ ++ memset((void *) &(fp->fecpriv_stat), 0, ++ sizeof(struct net_device_stats)); ++ ++ /* grab the FEC initiators */ ++ dma_set_initiator(fp->fecpriv_tx_requestor); ++ fp->fecpriv_initiator_tx = dma_get_initiator(fp->fecpriv_tx_requestor); ++ dma_set_initiator(fp->fecpriv_rx_requestor); ++ fp->fecpriv_initiator_rx = dma_get_initiator(fp->fecpriv_rx_requestor); ++ ++ /* reset the DMA channels */ ++ fp->fecpriv_fec_rx_channel = -1; ++ fp->fecpriv_fec_tx_channel = -1; ++ ++ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) ++ fp->askb_rx[i] = NULL; ++ ++ /* initialize the pointers to the socket buffers */ ++ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) ++ fp->fecpriv_txbuf[i] = NULL; ++ ++ ether_setup(dev); ++ ++ dev->netdev_ops = &mcf547x_fec_netdev_ops; ++ dev->watchdog_timeo = FEC_TX_TIMEOUT * HZ; ++ ++ memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN); ++ ++ spin_lock_init(&fp->fecpriv_lock); ++ ++ /* Initialize FEC/I2C/IRQ Pin Assignment Register*/ ++ FEC_GPIO_PAR_FECI2CIRQ &= 0xF; ++ FEC_GPIO_PAR_FECI2CIRQ |= FEC_FECI2CIRQ; ++ ++ return 0; ++} ++ ++/* ++ * Module Initialization ++ */ ++int __init fec_init(void) ++{ ++ struct net_device *dev; ++ int i; ++ int err; ++ struct fec_priv *fep; ++ ++ printk(KERN_INFO "FEC ENET (DMA) Version %s\n", VERSION); ++ ++ for (i = 0; i < FEC_MAX_PORTS; i++) { ++ dev = alloc_etherdev(sizeof(struct fec_priv)); ++ if (!dev) ++ return -ENOMEM; ++ err = fec_enet_init(dev, i); ++ if (err) { ++ free_netdev(dev); ++ continue; ++ } ++ ++ fep = netdev_priv(dev); ++ FEC_MSCR(dev->base_addr) = FEC_MII_SPEED; ++#ifdef CONFIG_FEC_548x_SHARED_PHY ++ if (i == 0) ++ err = fec_mdio_register(dev, i); ++ else { ++ struct fec_priv *priv0 = netdev_priv(fec_dev[0]); ++ fep->mdio_bus = priv0->mdio_bus; ++ printk(KERN_INFO "FEC%d SHARED the %s ok\n", ++ i, fep->mdio_bus->name); ++ } ++#else ++ err = fec_mdio_register(dev, i); ++#endif ++ if (err) { ++ printk(KERN_ERR "%s: ethernet fec_mdio_register\n", ++ dev->name); ++ free_netdev(dev); ++ return -ENOMEM; ++ } ++ ++ if (register_netdev(dev) != 0) { ++ free_netdev(dev); ++ return -EIO; ++ } ++ ++ printk(KERN_INFO "%s: ethernet %s\n", ++ dev->name, dev->dev_addr); ++ } ++ return 0; ++} ++ ++/* ++ * Stop a device ++ */ ++void fec_stop(struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ ++ dma_remove_initiator(fp->fecpriv_initiator_tx); ++ dma_remove_initiator(fp->fecpriv_initiator_rx); ++ ++ if (dev->irq) ++ free_irq(dev->irq, dev); ++} ++ ++/************************************************************************ ++* NAME: fec_interrupt_tx_handler ++* ++* DESCRIPTION: This function is called when the data ++* transmission from the buffer to the FEC is completed. ++* ++*************************************************************************/ ++void fec_interrupt_fec_tx_handler(struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ ++ /* Release the socket buffer */ ++ kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]); ++ fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL; ++ ++ fp->fecpriv_current_tx = ++ (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK; ++ ++ if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE) { ++ for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; ++ fp->fecpriv_current_tx = ++ (fp->fecpriv_current_tx + 1) ++ & FEC_TX_INDEX_MASK) { ++ if (fp->fecpriv_txbuf[fp->fecpriv_current_tx]) { ++ kfree(fp->fecpriv_txbuf[ ++ fp->fecpriv_current_tx]); ++ fp->fecpriv_txbuf[fp->fecpriv_current_tx] ++ = NULL; ++ } ++ } ++ } ++ ++ if (netif_queue_stopped(dev)) ++ netif_wake_queue(dev); ++} ++ ++/************************************************************************ ++* NAME: fec_interrupt_rx_handler ++* ++* DESCRIPTION: This function is called when the data ++* reception from the FEC to the reception buffer is completed. ++* ++*************************************************************************/ ++void fec_interrupt_fec_rx_handler(struct net_device *dev) ++{ ++ struct fec_priv *fp = netdev_priv(dev); ++ struct sk_buff *skb; ++ int i; ++ ++ fp->fecpriv_rxflag = 1; ++ /* Some buffers can be missed */ ++ if (!(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl ++ & MCD_FEC_END_FRAME)) { ++ /* Find a valid index */ ++ for (i = 0; ((i < FEC_RX_BUF_NUMBER) && ++ !(fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].statCtrl ++ & MCD_FEC_END_FRAME)); i++, ++ (fp->fecpriv_current_rx = ++ (fp->fecpriv_current_rx + 1) ++ & FEC_RX_INDEX_MASK)) ++ ; ++ ++ if (i == FEC_RX_BUF_NUMBER) { ++ /* There are no data to process */ ++ /* Tell the DMA to continue the reception */ ++ MCD_continDma(fp->fecpriv_fec_rx_channel); ++ ++ fp->fecpriv_rxflag = 0; ++ ++ return; ++ } ++ } ++ ++ for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl ++ & MCD_FEC_END_FRAME; ++ fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) ++ & FEC_RX_INDEX_MASK) { ++ if ((fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length ++ <= FEC_MAXBUF_SIZE) && ++ (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length ++ > 4)) { ++ /* --tym-- */ ++ skb = fp->askb_rx[fp->fecpriv_current_rx]; ++ if (!skb) ++ fp->fecpriv_stat.rx_dropped++; ++ else { ++ /* ++ * flush data cache before initializing ++ * the descriptor and starting DMA ++ */ ++ skb_put(skb, ++ (fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].length - 4)); ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_rx(skb); ++ } ++ fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ++ ~MCD_FEC_END_FRAME; ++ /* allocate new skbuff */ ++ fp->askb_rx[fp->fecpriv_current_rx] = ++ alloc_skb(FEC_MAXBUF_SIZE + 16, ++ /*GFP_ATOMIC |*/ GFP_DMA); ++ if (!fp->askb_rx[fp->fecpriv_current_rx]) { ++ fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].dataPointer ++ = 0; ++ fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].length = 0; ++ fp->fecpriv_stat.rx_dropped++; ++ } else { ++ skb_reserve( ++ fp->askb_rx[fp->fecpriv_current_rx], 16); ++ fp->askb_rx[fp->fecpriv_current_rx]->dev = dev; ++ ++ /* ++ * flush data cache before initializing ++ * the descriptor and starting DMA ++ */ ++ ++ fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].dataPointer = ++ (unsigned int) virt_to_phys( ++ fp->askb_rx[ ++ fp->fecpriv_current_rx]->tail); ++ fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].length = ++ FEC_MAXBUF_SIZE; ++ fp->fecpriv_rxdesc[ ++ fp->fecpriv_current_rx].statCtrl |= ++ MCD_FEC_BUF_READY; ++ ++ /* ++ * flush data cache before initializing ++ * the descriptor and starting DMA ++ */ ++ } ++ } ++ ++ } ++ ++ /* Tell the DMA to continue the reception */ ++ MCD_continDma(fp->fecpriv_fec_rx_channel); ++ ++ fp->fecpriv_rxflag = 0; ++} ++ ++/************************************************************************ ++* NAME: fec_interrupt_handler ++* ++* DESCRIPTION: This function is called when some special errors occur ++* ++*************************************************************************/ ++irqreturn_t fec_interrupt_handler(int irq, void *dev_id) ++{ ++ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ unsigned long events; ++ ++ /* Read and clear the events */ ++ events = FEC_EIR(base_addr) & FEC_EIMR(base_addr); ++ ++ if (events & FEC_EIR_HBERR) { ++ fp->fecpriv_stat.tx_heartbeat_errors++; ++ FEC_EIR(base_addr) = FEC_EIR_HBERR; ++ } ++ ++ /* receive/transmit FIFO error */ ++ if (((events & FEC_EIR_RFERR) != 0) ++ || ((events & FEC_EIR_XFERR) != 0)) { ++ /* kill DMA receive channel */ ++ MCD_killDma(fp->fecpriv_fec_rx_channel); ++ ++ /* kill running transmission by DMA */ ++ MCD_killDma(fp->fecpriv_fec_tx_channel); ++ ++ /* Reset FIFOs */ ++ FEC_FECFRST(base_addr) |= FEC_SW_RST; ++ FEC_FECFRST(base_addr) &= ~FEC_SW_RST; ++ ++ /* reset receive FIFO status register */ ++ FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE | ++ FEC_FECRFSR_RXW | ++ FEC_FECRFSR_UF; ++ ++ /* reset transmit FIFO status register */ ++ FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE | ++ FEC_FECTFSR_TXW | ++ FEC_FECTFSR_UF | ++ FEC_FECTFSR_OF; ++ ++ /* reset RFERR and XFERR event */ ++ FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR; ++ ++ /* stop queue */ ++ netif_stop_queue(dev); ++ ++ /* execute reinitialization as tasklet */ ++ tasklet_schedule(&fp->fecpriv_tasklet_reinit); ++ ++ fp->fecpriv_stat.rx_dropped++; ++ } ++ ++ /* transmit FIFO underrun */ ++ if ((events & FEC_EIR_XFUN) != 0) { ++ /* reset XFUN event */ ++ FEC_EIR(base_addr) = FEC_EIR_XFUN; ++ fp->fecpriv_stat.tx_aborted_errors++; ++ } ++ ++ /* late collision */ ++ if ((events & FEC_EIR_LC) != 0) { ++ /* reset LC event */ ++ FEC_EIR(base_addr) = FEC_EIR_LC; ++ fp->fecpriv_stat.tx_aborted_errors++; ++ } ++ ++ /* collision retry limit */ ++ if ((events & FEC_EIR_RL) != 0) { ++ /* reset RL event */ ++ FEC_EIR(base_addr) = FEC_EIR_RL; ++ fp->fecpriv_stat.tx_aborted_errors++; ++ } ++ return 0; ++} ++ ++/************************************************************************ ++* NAME: fec_interrupt_reinit ++* ++* DESCRIPTION: This function is called from interrupt handler ++* when controller must be reinitialized. ++* ++*************************************************************************/ ++void fec_interrupt_fec_reinit(unsigned long data) ++{ ++ int i; ++ struct net_device *dev = (struct net_device *)data; ++ struct fec_priv *fp = netdev_priv(dev); ++ unsigned long base_addr = (unsigned long) dev->base_addr; ++ ++ /* Initialize reception descriptors and start DMA for the reception */ ++ for (i = 0; i < FEC_RX_BUF_NUMBER; i++) { ++ if (!fp->askb_rx[i]) { ++ fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, ++ GFP_ATOMIC | GFP_DMA); ++ if (!fp->askb_rx[i]) { ++ fp->fecpriv_rxdesc[i].dataPointer = 0; ++ fp->fecpriv_rxdesc[i].statCtrl = 0; ++ fp->fecpriv_rxdesc[i].length = 0; ++ continue; ++ } ++ fp->askb_rx[i]->dev = dev; ++ skb_reserve(fp->askb_rx[i], 16); ++ } ++ fp->fecpriv_rxdesc[i].dataPointer = ++ (unsigned int) virt_to_phys(fp->askb_rx[i]->tail); ++ fp->fecpriv_rxdesc[i].statCtrl = ++ MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT; ++ fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE; ++ } ++ ++ fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP; ++ fp->fecpriv_current_rx = 0; ++ ++ /* restart frame transmission */ ++ for (i = 0; i < FEC_TX_BUF_NUMBER; i++) { ++ kfree(fp->fecpriv_txbuf[i]); ++ fp->fecpriv_txbuf[i] = NULL; ++ fp->fecpriv_stat.tx_dropped++; ++ fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT; ++ } ++ fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP; ++ fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; ++ ++ /* flush entire data cache before restarting the DMA */ ++ ++ /* restart DMA from beginning */ ++ MCD_startDma(fp->fecpriv_fec_rx_channel, ++ (char *) fp->fecpriv_rxdesc, 0, ++ (unsigned char *) &(FEC_FECRFDR(base_addr)), 0, ++ FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx, ++ FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT, ++ MCD_NO_CSUM | MCD_NO_BYTE_SWAP); ++ ++ MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0, ++ (unsigned char *) &(FEC_FECTFDR(base_addr)), 0, ++ FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx, ++ FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT, ++ MCD_NO_CSUM | MCD_NO_BYTE_SWAP); ++ ++ /* Enable FEC */ ++ FEC_ECR(base_addr) |= FEC_ECR_ETHEREN; ++ ++ netif_wake_queue(dev); ++} ++ ++/************************************************************************ ++* NAME: fec_interrupt_tx_handler_fec0 ++* ++* DESCRIPTION: This is the DMA interrupt handler using for FEC0 ++* transmission. ++* ++*************************************************************************/ ++void fec_interrupt_fec_tx_handler_fec0(void) ++{ ++ fec_interrupt_fec_tx_handler(fec_dev[0]); ++} ++ ++#ifdef FEC_2 ++/************************************************************************ ++* NAME: fec_interrupt_tx_handler_fec1 ++* ++* DESCRIPTION: This is the DMA interrupt handler using for the FEC1 ++* transmission. ++* ++*************************************************************************/ ++void fec_interrupt_fec_tx_handler_fec1(void) ++{ ++ fec_interrupt_fec_tx_handler(fec_dev[1]); ++} ++#endif ++ ++/************************************************************************ ++* NAME: fec_interrupt_rx_handler_fec0 ++* ++* DESCRIPTION: This is the DMA interrupt handler using for the FEC0 ++* reception. ++* ++*************************************************************************/ ++void fec_interrupt_fec_rx_handler_fec0(void) ++{ ++ fec_interrupt_fec_rx_handler(fec_dev[0]); ++} ++ ++#ifdef FEC_2 ++/************************************************************************ ++* NAME: fec_interrupt_rx_handler_fec1 ++* ++* DESCRIPTION: This is the DMA interrupt handler using for the FEC1 ++* reception. ++* ++*************************************************************************/ ++void fec_interrupt_fec_rx_handler_fec1(void) ++{ ++ fec_interrupt_fec_rx_handler(fec_dev[1]); ++} ++ ++#endif ++ ++#ifndef MODULE ++/************************************************************************ ++* NAME: fec_mac_setup0 ++* ++* DESCRIPTION: This function sets the MAC address of FEC0 from command line ++* ++*************************************************************************/ ++int __init fec_mac_setup0(char *s) ++{ ++ if (!s || !*s) ++ return 1; ++ ++ if (fec_str_to_mac(s, fec_mac_addr_fec0)) ++ printk(KERN_ERR "The MAC address of FEC0 " ++ "cannot be set from command line"); ++ return 1; ++} ++ ++#ifdef FEC_2 ++ ++/************************************************************************ ++* NAME: fec_mac_setup1 ++* ++* DESCRIPTION: This function sets the MAC address of FEC1 from command line ++* ++*************************************************************************/ ++int __init fec_mac_setup1(char *s) ++{ ++ if (!s || !*s) ++ return 1; ++ ++ if (fec_str_to_mac(s, fec_mac_addr_fec1)) ++ printk(KERN_ERR "The MAC address of FEC1 " ++ "cannot be set from command line\n"); ++ return 1; ++} ++#endif ++ ++/************************************************************************ ++* NAME: fec_str_to_mac ++* ++* DESCRIPTION: This function interprets the character string into MAC addr ++* ++*************************************************************************/ ++int fec_str_to_mac(char *str_mac, unsigned char* addr) ++{ ++ unsigned long val; ++ char c; ++ unsigned long octet[6], *octetptr = octet; ++ int i; ++ ++again: ++ val = 0; ++ while ((c = *str_mac) != '\0') { ++ if ((c >= '0') && (c <= '9')) { ++ val = (val * 16) + (c - '0'); ++ str_mac++; ++ continue; ++ } else if (((c >= 'a') && (c <= 'f')) ++ || ((c >= 'A') && (c <= 'F'))) { ++ val = (val << 4) + ++ (c + 10 - ++ (((c >= 'a') && (c <= 'f')) ? 'a' : 'A')); ++ str_mac++; ++ continue; ++ } ++ break; ++ } ++ if (*str_mac == ':') { ++ *octetptr++ = val, str_mac++; ++ if (octetptr >= octet + 6) ++ return 1; ++ goto again; ++ } ++ ++ /* Check for trailing characters */ ++ if (*str_mac && !(*str_mac == ' ')) ++ return 1; ++ ++ *octetptr++ = val; ++ ++ if ((octetptr - octet) == 6) { ++ for (i = 0; i <= 6; i++) ++ addr[i] = octet[i]; ++ } else ++ return 1; ++ ++ return 0; ++} ++#endif +--- /dev/null ++++ b/drivers/net/fec_m547x.h +@@ -0,0 +1,241 @@ ++#ifndef FEC_M547X_H ++#define FEC_M547X_H ++/* ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#define FEC_BASE_ADDR_FEC0 ((unsigned int)MCF_MBAR + 0x9000) ++#define FEC_BASE_ADDR_FEC1 ((unsigned int)MCF_MBAR + 0x9800) ++ ++#define FEC_FECI2CIRQ (0xFFC0) ++#define FEC_GPIO_PAR_FECI2CIRQ \ ++ (*(volatile unsigned short *)((unsigned int)MCF_MBAR + 0xA44)) ++ ++#define FEC_ECR_DISABLE (0x00000000) ++ ++#define FEC_ECR(x) \ ++ (*(volatile unsigned int *)(x + 0x024)) ++#define FEC_EIR(x) \ ++ (*(volatile unsigned int *)(x + 0x004)) ++#define FEC_PALR(x) \ ++ (*(volatile unsigned int *)(x + 0x0E4)) ++#define FEC_PAUR(x) \ ++ (*(volatile unsigned int *)(x + 0x0E8)) ++#define FEC_IALR(x) \ ++ (*(volatile unsigned int *)(x + 0x11C)) ++#define FEC_IAUR(x) \ ++ (*(volatile unsigned int *)(x + 0x118)) ++#define FEC_GALR(x) \ ++ (*(volatile unsigned int *)(x + 0x124)) ++#define FEC_GAUR(x) \ ++ (*(volatile unsigned int *)(x + 0x120)) ++#define FEC_RCR(x) \ ++ (*(volatile unsigned int *)(x + 0x084)) ++#define FEC_FECRFCR(x) \ ++ (*(volatile unsigned int *)(x + 0x18C)) ++#define FEC_FECRFAR(x) \ ++ (*(volatile unsigned int *)(x + 0x198)) ++#define FEC_FECTFCR(x) \ ++ (*(volatile unsigned int *)(x + 0x1AC)) ++#define FEC_FECTFAR(x) \ ++ (*(volatile unsigned int *)(x + 0x1B8)) ++#define FEC_FECTFWR(x) \ ++ (*(volatile unsigned int *)(x + 0x144)) ++#define FEC_CTCWR(x) \ ++ (*(volatile unsigned int *)(x + 0x1C8)) ++#define FEC_EIMR(x) \ ++ (*(volatile unsigned int *)(x + 0x008)) ++#define FEC_TCR(x) \ ++ (*(volatile unsigned int *)(x + 0x0C4)) ++#define FEC_MIBC(x) \ ++ (*(volatile unsigned int *)(x + 0x064)) ++#define FEC_MSCR(x) \ ++ (*(volatile unsigned int *)(x + 0x044)) ++#define FEC_FECTFDR(x) \ ++ (*(volatile unsigned int *)(x + 0x1A4)) ++#define FEC_FECRFDR(x) \ ++ (*(volatile unsigned int *)(x + 0x184)) ++#define FEC_FECTFSR(x) \ ++ (*(volatile unsigned int *)(x + 0x1A8)) ++#define FEC_FECRFSR(x) \ ++ (*(volatile unsigned int *)(x + 0x188)) ++#define FECSTAT_RMON_R_PACKETS(x) \ ++ (*(volatile unsigned int *)(x + 0x284)) ++#define FECSTAT_RMON_T_PACKETS(x) \ ++ (*(volatile unsigned int *)(x + 0x204)) ++#define FECSTAT_RMON_R_OCTETS(x) \ ++ (*(volatile unsigned int *)(x + 0x2C4)) ++#define FECSTAT_RMON_T_OCTETS(x) \ ++ (*(volatile unsigned int *)(x + 0x244)) ++#define FECSTAT_RMON_R_UNDERSIZE(x) \ ++ (*(volatile unsigned int *)(x + 0x294)) ++#define FECSTAT_RMON_R_OVERSIZE(x) \ ++ (*(volatile unsigned int *)(x + 0x298)) ++#define FECSTAT_RMON_R_FRAG(x) \ ++ (*(volatile unsigned int *)(x + 0x29C)) ++#define FECSTAT_RMON_R_JAB(x) \ ++ (*(volatile unsigned int *)(x + 0x2A0)) ++#define FECSTAT_RMON_R_MC_PKT(x) \ ++ (*(volatile unsigned int *)(x + 0x28C)) ++#define FECSTAT_RMON_T_COL(x) \ ++ (*(volatile unsigned int *)(x + 0x224)) ++#define FECSTAT_IEEE_R_ALIGN(x) \ ++ (*(volatile unsigned int *)(x + 0x2D4)) ++#define FECSTAT_IEEE_R_CRC(x) \ ++ (*(volatile unsigned int *)(x + 0x2D0)) ++#define FECSTAT_IEEE_R_MACERR(x) \ ++ (*(volatile unsigned int *)(x + 0x2D8)) ++#define FECSTAT_IEEE_T_CSERR(x) \ ++ (*(volatile unsigned int *)(x + 0x268)) ++#define FECSTAT_IEEE_T_MACERR(x) \ ++ (*(volatile unsigned int *)(x + 0x264)) ++#define FECSTAT_IEEE_T_LCOL(x) \ ++ (*(volatile unsigned int *)(x + 0x25C)) ++#define FECSTAT_IEEE_R_OCTETS_OK(x) \ ++ (*(volatile unsigned int *)(x + 0x2E0)) ++#define FECSTAT_IEEE_T_OCTETS_OK(x) \ ++ (*(volatile unsigned int *)(x + 0x274)) ++#define FECSTAT_IEEE_R_DROP(x) \ ++ (*(volatile unsigned int *)(x + 0x2C8)) ++#define FECSTAT_IEEE_T_DROP(x) \ ++ (*(volatile unsigned int *)(x + 0x248)) ++#define FECSTAT_IEEE_R_FRAME_OK(x) \ ++ (*(volatile unsigned int *)(x + 0x2CC)) ++#define FECSTAT_IEEE_T_FRAME_OK(x) \ ++ (*(volatile unsigned int *)(x + 0x24C)) ++#define FEC_MMFR(x) \ ++ (*(volatile unsigned int *)(x + 0x040)) ++#define FEC_FECFRST(x) \ ++ (*(volatile unsigned int *)(x + 0x1C4)) ++ ++#define FEC_MAX_FRM_SIZE (1518) ++#define FEC_MAXBUF_SIZE (1520) ++ ++/* Register values */ ++#define FEC_ECR_RESET (0x00000001) ++#define FEC_EIR_CLEAR (0xFFFFFFFF) ++#define FEC_EIR_RL (0x00100000) ++#define FEC_EIR_HBERR (0x80000000) ++#define FEC_EIR_BABR (0x40000000) ++/* babbling receive error */ ++#define FEC_EIR_BABT (0x20000000) ++/* babbling transmit error */ ++#define FEC_EIR_TXF (0x08000000) ++/* transmit frame interrupt */ ++#define FEC_EIR_MII (0x00800000) ++/* MII interrupt */ ++#define FEC_EIR_LC (0x00200000) ++/* late collision */ ++#define FEC_EIR_XFUN (0x00080000) ++/* transmit FIFO underrun */ ++#define FEC_EIR_XFERR (0x00040000) ++/* transmit FIFO error */ ++#define FEC_EIR_RFERR (0x00020000) ++/* receive FIFO error */ ++#define FEC_RCR_MAX_FRM_SIZE (FEC_MAX_FRM_SIZE << 16) ++#define FEC_RCR_MII (0x00000004) ++#define FEC_FECRFCR_FAE (0x00400000) ++/* frame accept error */ ++#define FEC_FECRFCR_RXW (0x00200000) ++/* receive wait condition */ ++#define FEC_FECRFCR_UF (0x00100000) ++/* receive FIFO underflow */ ++#define FEC_FECRFCR_FRM (0x08000000) ++#define FEC_FECRFCR_GR (0x7 << 24) ++ ++#define FEC_EIMR_DISABLE (0x00000000) ++ ++#define FEC_FECRFAR_ALARM (0x300) ++#define FEC_FECTFCR_FRM (0x08000000) ++#define FEC_FECTFCR_GR (0x7 << 24) ++#define FEC_FECTFCR_FAE (0x00400000) ++/* frame accept error */ ++#define FEC_FECTFCR_TXW (0x00040000) ++/* transmit wait condition */ ++#define FEC_FECTFCR_UF (0x00100000) ++/* transmit FIFO underflow */ ++#define FEC_FECTFCR_OF (0x00080000) ++/* transmit FIFO overflow */ ++ ++#define FEC_FECTFAR_ALARM (0x100) ++#define FEC_FECTFWR_XWMRK (0x00000000) ++ ++#define FEC_FECTFSR_MSK (0xC0B00000) ++#define FEC_FECTFSR_TXW (0x40000000) ++/* transmit wait condition */ ++#define FEC_FECTFSR_FAE (0x00800000) ++/* frame accept error */ ++#define FEC_FECTFSR_UF (0x00200000) ++/* transmit FIFO underflow */ ++#define FEC_FECTFSR_OF (0x00100000) ++/* transmit FIFO overflow */ ++ ++#define FEC_FECRFSR_MSK (0x80F00000) ++#define FEC_FECRFSR_FAE (0x00800000) ++/* frame accept error */ ++#define FEC_FECRFSR_RXW (0x00400000) ++/* receive wait condition */ ++#define FEC_FECRFSR_UF (0x00200000) ++/* receive FIFO underflow */ ++ ++#define FEC_CTCWR_TFCW_CRC (0x03000000) ++#define FEC_TCR_FDEN (0x00000004) ++#define FEC_TCR_HBC (0x00000002) ++#define FEC_RCR_DRT (0x00000002) ++#define FEC_EIMR_MASK (FEC_EIR_RL | FEC_EIR_HBERR) ++#define FEC_ECR_ETHEREN (0x00000002) ++#define FEC_FECTFCR_MSK (0x00FC0000) ++#define FEC_FECRFCR_MSK (0x00F80000) ++#define FEC_EIR_GRA (0x10000000) ++#define FEC_TCR_GTS (0x00000001) ++#define FEC_MIBC_ENABLE (0x00000000) ++#define FEC_MIB_LEN (228) ++#define FEC_PHY_ADDR (0x01) ++ ++#define FEC_RX_DMA_PRI (6) ++#define FEC_TX_DMA_PRI (6) ++ ++#define FEC_TX_BUF_NUMBER (8) ++#define FEC_RX_BUF_NUMBER (64) ++ ++#define FEC_TX_INDEX_MASK (0x7) ++#define FEC_RX_INDEX_MASK (0x3f) ++ ++#define FEC_RX_DESC_FEC0 SYS_SRAM_FEC_START ++#define FEC_TX_DESC_FEC0 \ ++ (FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)) ++ ++#define FEC_RX_DESC_FEC1 \ ++ (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2) ++#define FEC_TX_DESC_FEC1 \ ++ (FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)) ++ ++#define FEC_EIR_MII (0x00800000) ++#define FEC_MMFR_READ (0x60020000) ++#define FEC_MMFR_WRITE (0x50020000) ++ ++#define FEC_FLAGS_RX (0x00000001) ++ ++#define FEC_CRCPOL (0xEDB88320) ++ ++#define FEC_MII_TIMEOUT (2) ++#define FEC_GR_TIMEOUT (1) ++#define FEC_TX_TIMEOUT (1) ++#define FEC_RX_TIMEOUT (1) ++ ++#define FEC_SW_RST 0x2000000 ++#define FEC_RST_CTL 0x1000000 ++ ++int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, ++ unsigned int *data); ++int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, ++ unsigned int data); ++ ++#define FEC_MII_SPEED \ ++ ((MCF_CLK / 2) / ((2500000 / 2) * 2)) ++#endif +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -62,6 +62,11 @@ config BROADCOM_PHY + Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481 + and BCM5482 PHYs. + ++config BROADCOM5222_PHY ++ tristate "Drivers for Broadcom5222 PHY" ++ ---help--- ++ Currently supports the BCM5222 PHYs. ++ + config BCM63XX_PHY + tristate "Drivers for Broadcom 63xx SOCs internal PHY" + ---help--- +@@ -82,6 +87,16 @@ config NATIONAL_PHY + ---help--- + Currently supports the DP83865 PHY. + ++config NATIONAL8364x_PHY ++ tristate "Drivers for National Semiconductor dp83640 PHYs" ++ ---help--- ++ Currently supports the DP83640 PHY. ++ ++config NATIONAL8384x_PHY ++ tristate "Drivers for National Semiconductor dp83848 dp83849 PHYs" ++ ---help--- ++ Currently supports the DP83848 PHY. ++ + config STE10XP + depends on PHYLIB + tristate "Driver for STMicroelectronics STe10Xp PHYs" +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o + obj-$(CONFIG_SMSC_PHY) += smsc.o + obj-$(CONFIG_VITESSE_PHY) += vitesse.o + obj-$(CONFIG_BROADCOM_PHY) += broadcom.o ++obj-$(CONFIG_BROADCOM5222_PHY) += broadcom522x.o + obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o +@@ -28,6 +29,8 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o + obj-$(CONFIG_NATIONAL_PHY) += national.o ++obj-$(CONFIG_NATIONAL8364x_PHY) +=national836x.o ++obj-$(CONFIG_NATIONAL8384x_PHY) +=national8384x.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_MICREL_PHY) += micrel.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o +--- /dev/null ++++ b/drivers/net/phy/broadcom522x.c +@@ -0,0 +1,170 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Chenghu Wu <b16972@freescale.com> ++ * ++ * Driver for broadcom PHYs 522x ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/mii.h> ++#include <linux/ethtool.h> ++#include <linux/phy.h> ++#include <linux/netdevice.h> ++ ++/* DP83865 phy identifier values */ ++#define BCM5222_PHY_ID 0x00406320 ++ ++/* PHY Register */ ++#define BCM5222_TIMEOUT 0x100 ++ ++/* MII Registers */ ++#define BCM5222_CTRL 0x00 ++#define BCM5222_STATUS 0x01 ++#define BCM5222_ID_HIGH 0x02 ++#define BCM5222_ID_LOW 0x03 ++#define BCM5222_AN_ADV 0x04 ++#define BCM5222_AN_LP 0x05 ++#define BCM5222_AN_EXP 0x06 ++#define BCM5222_AN_NEXTPG 0x07 ++#define BCM5222_AN_LP_NPTX 0x08 ++#define BCM5222_AUX_CS 0x18 ++#define BCM5222_AUX_STATUS 0x19 ++ ++/* CONTROL Bits */ ++#define BCM5222_CTRL_RESET 0x8000 ++#define BCM5222_CTRL_LOOPBACK 0x4000 ++#define BCM5222_CTRL_FORCE 0x2000 ++#define BCM5222_CTRL_AUTOEN 0x1000 ++#define BCM5222_CTRL_PWRDN 0x0800 ++#define BCM5222_CTRL_ISOLATE 0x0400 ++#define BCM5222_CTRL_RESTART 0x0200 ++#define BCM5222_CTRL_DUPLEX 0x0100 ++#define BCM5222_CTRL_COLLEN 0x0080 ++ ++/* STATUS Bits */ ++#define BCM5222_STATUS_100T4 0x8000 ++#define BCM5222_STATUS_100TXFDX 0x4000 ++#define BCM5222_STATUS_100TX 0x2000 ++#define BCM5222_STATUS_10FDX 0x1000 ++#define BCM5222_STATUS_10 0x0800 ++#define BCM5222_STATUS_MF_PREAMBLE 0x0040 ++#define BCM5222_STATUS_AN_COMPLETE 0x0020 ++#define BCM5222_STATUS_REMOTE_FAULT 0x0010 ++#define BCM5222_STATUS_AN_CAPABLE 0x0008 ++#define BCM5222_STATUS_LINK 0x0004 ++#define BCM5222_STATUS_JABBER 0x0002 ++#define BCM5222_STATUS_EXT_CAP 0x0001 ++ ++/* ID Values */ ++#define BCM5222_ID_HIGH_VAL 0x0040 ++#define BCM5222_ID_LOW_VAL 0x6320 ++ ++/* Advertise Bits */ ++#define BCM5222_AN_ADV_NEXTPG 0x8000 ++#define BCM5222_AN_ADV_REMOTE_FAULT 0x2000 ++#define BCM5222_AN_ADV_PAUSE 0x0400 ++#define BCM5222_AN_ADV_100T4 0x0200 ++#define BCM5222_AN_ADV_100TXFDX 0x0100 ++#define BCM5222_AN_ADV_100TX 0x0080 ++#define BCM5222_AN_ADV_10FDX 0x0040 ++#define BCM5222_AN_ADV_10 0x0020 ++#define BCM5222_AN_ADV_8023 0x0001 ++#define BCM5222_AN_ADV_ALL \ ++ (BCM5222_AN_ADV_100TXFDX | \ ++ BCM5222_AN_ADV_100TXFDX | \ ++ BCM5222_AN_ADV_100TX | \ ++ BCM5222_AN_ADV_10FDX | \ ++ BCM5222_AN_ADV_10 | \ ++ BCM5222_AN_ADV_8023) ++ ++/* AUX CTRL/STATUS Bits */ ++#define BCM5222_AUX_CS_JABBER_DIS 0x8000 ++#define BCM5222_AUX_CS_FORCE_LINK 0x4000 ++#define BCM5222_AUX_CS_10M_TX_PWR 0x0100 ++#define BCM5222_AUX_CS_HSQ_LSQ_MASK 0x00c0 ++#define BCM5222_AUX_CS_EDGE_RATE_MASK 0x0030 ++#define BCM5222_AUX_CS_AN_IND 0x0008 ++#define BCM5222_AUX_CS_SPEED_FORCE 0x0004 ++#define BCM5222_AUX_CS_SPEED 0x0002 ++#define BCM5222_AUX_CS_DUPLEX 0x0001 ++ ++/* AUX STATUS Bits */ ++#define BCM5222_AUX_STATUS_AN_COMP 0x8000 ++#define BCM5222_AUX_STATUS_AN_COMPACK 0x4000 ++#define BCM5222_AUX_STATUS_AN_ACKDET 0x2000 ++#define BCM5222_AUX_STATUS_AN_ABDET 0x1000 ++#define BCM5222_AUX_STATUS_AN_PAUSE 0x0800 ++#define BCM5222_AUX_STATUS_AN_HCDMASK 0x0700 ++#define BCM5222_AUX_STATUS_AN_PDFAULT 0x0080 ++#define BCM5222_AUX_STATUS_LP_RMTFAULT 0x0040 ++#define BCM5222_AUX_STATUS_LP_PGRX 0x0020 ++#define BCM5222_AUX_STATUS_LP_NEGABLE 0x0010 ++#define BCM5222_AUX_STATUS_SPEED 0x0008 ++#define BCM5222_AUX_STATUS_LINK 0x0004 ++#define BCM5222_AUX_STATUS_AN_EN 0x0002 ++#define BCM5222_AUX_STATUS_JABBER 0x0001 ++ ++static int bcm5222_config_intr(struct phy_device *phydev) ++{ ++ int err = 0; ++ printk(KERN_INFO "%s PHY_INTERRUPT %x\n", ++ __func__, phydev->interrupts); ++ ++ return err; ++} ++ ++static int bcm5222_ack_interrupt(struct phy_device *phydev) ++{ ++ return 0; ++} ++ ++static int bcm5222_config_init(struct phy_device *phydev) ++{ ++ return bcm5222_ack_interrupt(phydev); ++} ++ ++static struct phy_driver bcm5222_driver = { ++ .phy_id = BCM5222_PHY_ID, ++ .phy_id_mask = 0xfffffff0, ++ .name = "Broadcom BCM5222", ++ .features = PHY_BASIC_FEATURES, ++ .flags = PHY_HAS_INTERRUPT, ++ .config_init = bcm5222_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = bcm5222_ack_interrupt, ++ .config_intr = bcm5222_config_intr, ++ .driver = {.owner = THIS_MODULE,} ++}; ++ ++static int __init bcm5222_init(void) ++{ ++ int ret; ++ ++ ret = phy_driver_register(&bcm5222_driver); ++ if (ret) ++ goto err1; ++ ++ return 0; ++err1: ++ printk(KERN_INFO "register bcm5222 PHY driver fail\n"); ++ return ret; ++} ++ ++static void __exit bcm5222_exit(void) ++{ ++ phy_driver_unregister(&bcm5222_driver); ++} ++ ++MODULE_DESCRIPTION("Broadcom PHY driver"); ++MODULE_LICENSE("GPL v2"); ++ ++module_init(bcm5222_init); ++module_exit(bcm5222_exit); +--- /dev/null ++++ b/drivers/net/phy/national836x.c +@@ -0,0 +1,104 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Chenghu Wu <b16972@freescale.com> ++ * ++ * Driver for National Semiconductor PHYs 83640 ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/mii.h> ++#include <linux/ethtool.h> ++#include <linux/phy.h> ++#include <linux/netdevice.h> ++ ++/* DP83640 phy identifier values */ ++#define DP83640_PHY_ID 0x20005ce0 ++ ++/* PHY Status Register */ ++#define MII_DP83640_PHYSTST 16 ++/* Interrupt Control Register */ ++#define MII_DP83640_ICR 17 ++/* Interrupt Status and Interrupt EVEN Enable Register */ ++#define MII_DP83640_ISR 18 ++ ++#define MII_DP83640_ICR_IRQEVEN_EN 0x0001 ++#define MII_DP83640_ICR_IRQOUTPUT_EN 0x0002 ++#define MII_DP83640_ISR_ENERGY_EVEN 0x0040 ++#define MII_DP83640_ISR_LINKSTATUS_EVEN 0x0020 ++ ++static int ns_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { ++ err = phy_write(phydev, MII_DP83640_ICR, ++ MII_DP83640_ICR_IRQEVEN_EN | ++ MII_DP83640_ICR_IRQOUTPUT_EN); ++ err = phy_write(phydev, MII_DP83640_ICR, ++ MII_DP83640_ISR_ENERGY_EVEN | ++ MII_DP83640_ISR_LINKSTATUS_EVEN); ++ } else { ++ err = phy_write(phydev, MII_DP83640_ICR, 0); ++ } ++ return err; ++} ++ ++static int ns83640_ack_interrupt(struct phy_device *phydev) ++{ ++ int ret = phy_read(phydev, MII_DP83640_ISR); ++ if (ret < 0) { ++ printk(KERN_INFO "%s MII_DP83640_ISR %x\n", ++ __func__, ret); ++ return ret; ++ } ++ return 0; ++} ++ ++static int ns83640_config_init(struct phy_device *phydev) ++{ ++ int ret = phy_read(phydev, MII_DP83640_PHYSTST); ++ if (ret < 0) { ++ printk(KERN_INFO "%s MII_DP83640_ISR %x\n", ++ __func__, ret); ++ } ++ ++ return ns83640_ack_interrupt(phydev); ++} ++ ++static struct phy_driver dp83640_driver = { ++ .phy_id = DP83640_PHY_ID, ++ .phy_id_mask = 0xfffffff0, ++ .name = "NatSemi DP83640", ++ .features = PHY_BASIC_FEATURES, ++ .flags = PHY_HAS_INTERRUPT, ++ .config_init = ns83640_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = ns83640_ack_interrupt, ++ .config_intr = ns_config_intr, ++ .driver = {.owner = THIS_MODULE,} ++}; ++ ++static int __init ns83640_init(void) ++{ ++ return phy_driver_register(&dp83640_driver); ++} ++ ++static void __exit ns83640_exit(void) ++{ ++ phy_driver_unregister(&dp83640_driver); ++} ++ ++MODULE_DESCRIPTION("NatSemi PHY driver"); ++MODULE_AUTHOR("Chenghu Wu <b16972@freescale.com>"); ++MODULE_LICENSE("GPL v2"); ++ ++module_init(ns83640_init); ++module_exit(ns83640_exit); +--- /dev/null ++++ b/drivers/net/phy/national8384x.c +@@ -0,0 +1,110 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Chenghu Wu <b16972@freescale.com> ++ * ++ * Driver for National Semiconductor PHYs 8384x ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/mii.h> ++#include <linux/ethtool.h> ++#include <linux/phy.h> ++#include <linux/netdevice.h> ++ ++/* DP8384x phy identifier values */ ++#define DP83848_PHY_ID 0x20005c90 ++#define DP83849_PHY_ID 0x20005ca0 ++/* PHY Status Register */ ++#define MII_DP8384X_PHYSTST 16 ++ ++static int ns8384x_config_intr(struct phy_device *phydev) ++{ ++ int err = 0; ++ ++ return err; ++} ++ ++static int ns8384x_ack_interrupt(struct phy_device *phydev) ++{ ++ return 0; ++} ++ ++static int ns8384x_config_init(struct phy_device *phydev) ++{ ++ int ret = phy_read(phydev, MII_DP8384X_PHYSTST); ++ if (ret < 0) { ++ printk(KERN_INFO "%s MII_DP83640_ISR %x\n", ++ __func__, ret); ++ } ++ ++ return ns8384x_ack_interrupt(phydev); ++} ++ ++static struct phy_driver dp83848_driver = { ++ .phy_id = DP83848_PHY_ID, ++ .phy_id_mask = 0xfffffff0, ++ .name = "NatSemi DP83848", ++ .features = PHY_BASIC_FEATURES, ++ .flags = PHY_HAS_INTERRUPT, ++ .config_init = ns8384x_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = ns8384x_ack_interrupt, ++ .config_intr = ns8384x_config_intr, ++ .driver = {.owner = THIS_MODULE,} ++}; ++ ++static struct phy_driver dp83849_driver = { ++ .phy_id = DP83849_PHY_ID, ++ .phy_id_mask = 0xfffffff0, ++ .name = "NatSemi DP83849", ++ .features = PHY_BASIC_FEATURES, ++ .flags = PHY_HAS_INTERRUPT, ++ .config_init = ns8384x_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = ns8384x_ack_interrupt, ++ .config_intr = ns8384x_config_intr, ++ .driver = {.owner = THIS_MODULE,} ++}; ++ ++static int __init ns8384x_init(void) ++{ ++ int ret; ++ ++ ret = phy_driver_register(&dp83848_driver); ++ if (ret) ++ goto err1; ++ ++ ret = phy_driver_register(&dp83849_driver); ++ if (ret) ++ goto err2; ++ ++ return 0; ++err2: ++ printk(KERN_INFO "register dp83849 PHY driver fail\n"); ++ phy_driver_unregister(&dp83848_driver); ++err1: ++ printk(KERN_INFO "register dp83848 PHY driver fail\n"); ++ return ret; ++} ++ ++static void __exit ns8384x_exit(void) ++{ ++ phy_driver_unregister(&dp83848_driver); ++ phy_driver_unregister(&dp83849_driver); ++} ++ ++MODULE_DESCRIPTION("NatSemi PHY driver"); ++MODULE_AUTHOR("Chenghu Wu <b16972@freescale.com>"); ++MODULE_LICENSE("GPL v2"); ++ ++module_init(ns8384x_init); ++module_exit(ns8384x_exit); diff --git a/target/linux/coldfire/patches/007-Add-eDMA-support-for-MCF5445x.patch b/target/linux/coldfire/patches/007-Add-eDMA-support-for-MCF5445x.patch new file mode 100644 index 000000000..3e9d45cfb --- /dev/null +++ b/target/linux/coldfire/patches/007-Add-eDMA-support-for-MCF5445x.patch @@ -0,0 +1,1639 @@ +From cd07e01d0c6c207a6138e9d5229dfa8c88ab3879 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:40 +0800 +Subject: [PATCH 07/52] Add eDMA support for MCF5445x + +Add MCF5445x on-chip eDMA controller driver. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/mcf_edma.h | 246 +++++++++ + drivers/Makefile | 2 + + drivers/dma/Kconfig | 15 + + drivers/dma/Makefile | 4 + + drivers/dma/mcf_edma.c | 1029 ++++++++++++++++++++++++++++++++++++++ + drivers/dma/mcf_edma_test.c | 276 ++++++++++ + 6 files changed, 1572 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/include/asm/mcf_edma.h + create mode 100644 drivers/dma/mcf_edma.c + create mode 100644 drivers/dma/mcf_edma_test.c + +--- /dev/null ++++ b/arch/m68k/include/asm/mcf_edma.h +@@ -0,0 +1,246 @@ ++/* ++ * mcf_edma.h - Coldfire eDMA driver header file. ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Add support for m5441x platform (Lanttor.Guo@freescale.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef _MCF_EDMA_H ++#define _MCF_EDMA_H ++ ++#include <asm/mcfsim.h> ++#include <linux/interrupt.h> ++#if defined(CONFIG_M5445X) ++#include <asm/mcf5445x_edma.h> ++#elif defined(CONFIG_M5441X) ++#include <asm/mcf5441x_edma.h> ++#endif ++#include <linux/scatterlist.h> ++ ++#define MCF_EDMA_INT0_CHANNEL_BASE (8) ++#define MCF_EDMA_INT0_CONTROLLER_BASE (64) ++#define MCF_EDMA_INT0_BASE (MCF_EDMA_INT0_CHANNEL_BASE + \ ++ MCF_EDMA_INT0_CONTROLLER_BASE) ++#define MCF_EDMA_INT0_NUM (16) ++#define MCF_EDMA_INT0_END (MCF_EDMA_INT0_NUM) ++ ++#if defined(CONFIG_M5441X) ++#define MCF_EDMA_INT1_CHANNEL_BASE (8) ++#define MCF_EDMA_INT1_CONTROLLER_BASE (128) ++#define MCF_EDMA_INT1_BASE (MCF_EDMA_INT1_CHANNEL_BASE + \ ++ MCF_EDMA_INT1_CONTROLLER_BASE) ++#define MCF_EDMA_INT1_NUM (40) ++#define MCF_EDMA_INT1_END (MCF_EDMA_INT0_END + MCF_EDMA_INT1_NUM) ++ ++#define MCF_EDMA_INT2_CHANNEL_BASE (0) ++#define MCF_EDMA_INT2_CONTROLLER_BASE (192) ++#define MCF_EDMA_INT2_BASE (MCF_EDMA_INT2_CHANNEL_BASE + \ ++ MCF_EDMA_INT2_CONTROLLER_BASE) ++#define MCF_EDMA_INT2_NUM (8) ++#define MCF_EDMA_INT2_END (MCF_EDMA_INT1_END + MCF_EDMA_INT2_NUM) ++ ++#endif ++ ++#if defined(CONFIG_M5445X) ++#define MCF_EDMA_CHANNELS (16) /* 0-15 */ ++#elif defined(CONFIG_M5441X) ++#define MCF_EDMA_CHANNELS (64) /* 0-63 */ ++#endif ++ ++#define MCF_EDMA_CHANNEL_ANY (0xFF) ++#define MCF_EDMA_INT_ERR (16) /* edma error interrupt */ ++ ++#define MCF_EDMA_TCD_PER_CHAN 256 ++ ++#ifdef CONFIG_M54455 ++/* eDMA engine TCD memory description */ ++ ++struct TCD { ++ u32 saddr; ++ u16 attr; ++ u16 soff; ++ u32 nbytes; ++ u32 slast; ++ u32 daddr; ++ u16 citer; ++ u16 doff; ++ u32 dlast_sga; ++ u16 biter; ++ u16 csr; ++} __packed; ++ ++struct fsl_edma_requestbuf { ++ dma_addr_t saddr; ++ dma_addr_t daddr; ++ u32 soff; ++ u32 doff; ++ u32 attr; ++ u32 minor_loop; ++ u32 len; ++}; ++ ++/* ++ * config the eDMA to use the TCD sg feature ++ * ++ * @channel: which channel. in fact this function is designed to satisfy ++ * the ATA driver TCD SG need, i.e. by now it is a special ++ * func, because it need prev alloc channel TCD physical memory ++ * first, we add the ATA's in the eDMA init only ++ * @buf: buffer array to fill the TCDs ++ * @nents: the size of the buf ++ */ ++void mcf_edma_sg_config(int channel, struct fsl_edma_requestbuf *buf, ++ int nents); ++ ++/* ++ * The zero-copy version of mcf_edma_sg_config() ++ */ ++void mcf_edma_sglist_config(int channel, struct scatterlist *sgl, int n_elem, ++ int dma_dir, u32 addr, u32 attr, ++ u32 soff, u32 doff, u32 nbytes); ++#endif ++ ++/* Setup transfer control descriptor (TCD) ++ * channel - descriptor number ++ * source - source address ++ * dest - destination address ++ * attr - attributes ++ * soff - source offset ++ * nbytes - number of bytes to be transfered in minor loop ++ * slast - last source address adjustment ++ * citer - major loop count ++ * biter - begining minor loop count ++ * doff - destination offset ++ * dlast_sga - last destination address adjustment ++ * major_int - generate interrupt after each major loop ++ * disable_req - disable DMA request after major loop ++ */ ++void mcf_edma_set_tcd_params(int channel, u32 source, u32 dest, ++ u32 attr, u32 soff, u32 nbytes, u32 slast, ++ u32 citer, u32 biter, u32 doff, u32 dlast_sga, ++ int major_int, int disable_req); ++ ++/* Setup transfer control descriptor (TCD) and enable halfway irq ++ * channel - descriptor number ++ * source - source address ++ * dest - destination address ++ * attr - attributes ++ * soff - source offset ++ * nbytes - number of bytes to be transfered in minor loop ++ * slast - last source address adjustment ++ * biter - major loop count ++ * doff - destination offset ++ * dlast_sga - last destination address adjustment ++ * disable_req - disable DMA request after major loop ++ */ ++void mcf_edma_set_tcd_params_halfirq(int channel, u32 source, u32 dest, ++ u32 attr, u32 soff, u32 nbytes, u32 slast, ++ u32 biter, u32 doff, u32 dlast_sga, ++ int disable_req); ++ ++/* check if dma is done ++ * channel - descriptor number ++ * return 1 if done ++ */ ++int mcf_edma_check_done(int channel); ++ ++/* Starts eDMA transfer on specified channel ++ * channel - eDMA TCD number ++ */ ++static inline void ++mcf_edma_start_transfer(int channel) ++{ ++ MCF_EDMA_SERQ = channel; ++ MCF_EDMA_SSRT = channel; ++} ++ ++/* Restart eDMA transfer from halfirq ++ * channel - eDMA TCD number ++ */ ++static inline void ++mcf_edma_confirm_halfirq(int channel) ++{ ++ /*MCF_EDMA_TCD_CSR(channel) = 7;*/ ++ MCF_EDMA_SSRT = channel; ++} ++ ++/* Starts eDMA transfer on specified channel based on peripheral request ++ * channel - eDMA TCD number ++ */ ++static inline void mcf_edma_enable_transfer(int channel) ++{ ++ MCF_EDMA_SERQ = channel; ++} ++ ++ ++/* Stops eDMA transfer ++ * channel - eDMA TCD number ++ */ ++static inline void ++mcf_edma_stop_transfer(int channel) ++{ ++ MCF_EDMA_CINT = channel; ++ MCF_EDMA_CERQ = channel; ++} ++ ++/* Confirm that interrupt has been handled ++ * channel - eDMA TCD number ++ */ ++static inline void ++mcf_edma_confirm_interrupt_handled(int channel) ++{ ++ MCF_EDMA_CINT = channel; ++} ++ ++/** ++ * mcf_edma_request_channel - Request an eDMA channel ++ * @channel: channel number. In case it is equal to EDMA_CHANNEL_ANY ++ * it will be allocated a first free eDMA channel. ++ * @handler: dma handler ++ * @error_handler: dma error handler ++ * @irq_level: irq level for the dma handler ++ * @arg: argument to pass back ++ * @lock: optional spinlock to hold over interrupt ++ * @device_id: device id ++ * ++ * Returns allocatedd channel number if success or ++ * a negative value if failure. ++ */ ++int mcf_edma_request_channel(int channel, ++ irqreturn_t(*handler) (int, void *), ++ void (*error_handler) (int, void *), ++ u8 irq_level, ++ void *arg, ++ spinlock_t *lock, const char *device_id); ++ ++/** ++ * Update the channel callback/arg ++ * @channel: channel number ++ * @handler: dma handler ++ * @error_handler: dma error handler ++ * @arg: argument to pass back ++ * ++ * Returns 0 if success or a negative value if failure ++ */ ++int mcf_edma_set_callback(int channel, ++ irqreturn_t(*handler) (int, void *), ++ void (*error_handler) (int, void *), void *arg); ++ ++/** ++ * Free the edma channel ++ * @channel: channel number ++ * @arg: argument created with ++ * ++ * Returns 0 if success or a negative value if failure ++ */ ++int mcf_edma_free_channel(int channel, void *arg); ++ ++void mcf_edma_dump_channel(int channel); ++ ++#endif /* _MCF_EDMA_H */ +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_FB_I810) += video + obj-$(CONFIG_FB_INTEL) += video/intelfb/ + + obj-$(CONFIG_PARPORT) += parport/ ++obj-$(CONFIG_COLDFIRE_EDMA) += dma/ + obj-y += base/ block/ misc/ mfd/ nfc/ + obj-$(CONFIG_NUBUS) += nubus/ + obj-y += macintosh/ +@@ -114,6 +115,7 @@ obj-$(CONFIG_BCMA) += bcma/ + obj-$(CONFIG_VHOST_NET) += vhost/ + obj-$(CONFIG_VLYNQ) += vlynq/ + obj-$(CONFIG_STAGING) += staging/ ++obj-$(CONFIG_MCD_DMA) += dma/ + obj-y += platform/ + obj-y += ieee802154/ + #common clk code +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -114,6 +114,21 @@ config MPC512X_DMA + ---help--- + Enable support for the Freescale MPC512x built-in DMA engine. + ++config COLDFIRE_EDMA ++ tristate "Coldfire eDMA support" ++ default y ++ depends on COLDFIRE && (M5445X || M5441X) ++ help ++ Enable support for Coldfire eDMA controller. For example ++ used by Coldfire SSI Audio device driver. ++ ++config COLDFIRE_EDMA_TEST ++ tristate "Coldfire eDMA simple test module" ++ default m ++ depends on COLDFIRE_EDMA ++ help ++ This is simple eDMA test module. ++ + config MV_XOR + bool "Marvell XOR engine support" + depends on PLAT_ORION +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -13,10 +13,14 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioat/ + obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o + obj-$(CONFIG_FSL_DMA) += fsldma.o + obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o ++obj-$(CONFIG_COLDFIRE_EDMA) += mcf_edma.o ++obj-$(CONFIG_COLDFIRE_EDMA_TEST) += mcf_edma_test.o + obj-$(CONFIG_MV_XOR) += mv_xor.o + obj-$(CONFIG_DW_DMAC) += dw_dmac.o + obj-$(CONFIG_AT_HDMAC) += at_hdmac.o + obj-$(CONFIG_MX3_IPU) += ipu/ ++obj-$(CONFIG_MCD_DMA) += mcddma.o ++mcddma-objs := MCD_dmaApi.o MCD_tasks.o MCD_tasksInit.o + obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o + obj-$(CONFIG_SH_DMAE) += shdma.o + obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o +--- /dev/null ++++ b/drivers/dma/mcf_edma.c +@@ -0,0 +1,1029 @@ ++/* ++ * mcf_edma.c - eDMA driver for Coldfire. ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Yaroslav Vinogradov ++ * Lanttor.Guo@freescale.com add m5441x platform support. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.002 29 February 2008 Andrey Butok, Freescale Semiconductor ++ * Added support of atomatic channel allocation from the ++ * channel pool. ++ * v0.001 12 February 2008 Andrey Butok ++ * Initial Release - developed on uClinux with 2.6.23 kernel. ++ * Based on coldfire_edma.c code ++ * of Yaroslav Vinogradov (Freescale Semiconductor, Inc.) ++ * ++ * NOTE: This driver was tested on MCF52277 platform. ++ * It should also work on other Coldfire platdorms with eDMA module. ++ * ++ * TBD: Try to make it more general. ++ * Try to integrate with current <asm/dma.h> <kernel/dma.c> API ++ * or use Intel DMA API ++ */ ++ ++#include <linux/dma-mapping.h> ++#include <asm/mcf_edma.h> ++#include <linux/init.h> ++#include <linux/module.h> ++#include <asm/coldfire.h> ++#include <linux/fs.h> ++#include <linux/cdev.h> ++#include <linux/seq_file.h> ++#include <linux/proc_fs.h> ++ ++/* Please add here processors that were tested with this driver */ ++#if !defined(CONFIG_M5227x) && !defined(CONFIG_M5445X) && \ ++ !defined(CONFIG_M5441X) ++#error "The driver is not tested/designed for your processor!" ++#endif ++ ++#define MCF_EDMA_DRIVER_VERSION "Revision: 0.003" ++#define MCF_EDMA_DRIVER_AUTHOR "Freescale Semiconductor Inc, Andrey Butok" ++#define MCF_EDMA_DRIVER_DESC "Coldfire EDMA driver." ++#define MCF_EDMA_DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC ++#define MCF_EDMA_DRIVER_LICENSE "GPL" ++#define MCF_EDMA_DRIVER_NAME "mcf_edma" ++ ++#define MCF_EDMA_DEV_MINOR (1) ++ ++#undef MCF_EDMA_DEBUG ++ ++#ifdef MCF_EDMA_DEBUG ++#define DBG(fmt, args...) printk(KERN_INFO "[%s] " fmt, \ ++ __func__, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#define ERR(format, arg...) printk(KERN_ERR "%s:%s: " format "\n", \ ++ __FILE__, __func__ , ## arg) ++#define INFO(stuff...) printk(KERN_INFO MCF_EDMA_DRIVER_NAME \ ++ ": " stuff) ++ ++/* DMA channel pool used for atomtic channel allocation. ++ * You can edit this list. First candidates are "Not used/Reserved" channels */ ++u8 mcf_edma_channel_pool[] = { 1, /* Not used */ ++ 0, /* External DMA request */ ++ 5, /* UART1 Receive */ ++ 6, /* UART1 Transmit */ ++ 7, /* UART2 Receive */ ++ 8, /* UART2 Transmit */ ++#if defined(CONFIG_M5441X) ++ 16, ++ 55, ++ 56, ++ 63, ++#endif ++}; ++ ++/* ++ * Callback handler data for each TCD ++ */ ++struct mcf_edma_isr_record { ++ irqreturn_t(*irq_handler) (int, void *); /* interrupt handler */ ++ void (*error_handler) (int, void *); /* error interrupt handler */ ++ void *arg; /* argument to pass back */ ++ int allocated; /* busy flag */ ++ spinlock_t *lock; /* spin lock (optional) */ ++ const char *device_id; /* dev id string, used in procfs */ ++}; ++ ++/* ++ * Device structure ++ */ ++struct mcf_edma_dev { ++ struct cdev cdev; /* character device */ ++ struct mcf_edma_isr_record dma_interrupt_handlers[MCF_EDMA_CHANNELS]; ++}; ++ ++/* allocated major device number */ ++static int mcf_edma_major; ++ ++/* device driver structure */ ++static struct mcf_edma_dev *mcf_edma_devp; ++ ++#ifdef CONFIG_M54455 ++/* PATA controller structure */ ++static struct { ++ struct TCD *pata_tcd_va; ++ dma_addr_t pata_tcd_pa; ++} fsl_pata_dma_tcd; ++#endif ++ ++/* device driver file operations */ ++const struct file_operations mcf_edma_fops = { ++ .owner = THIS_MODULE, ++}; ++ ++/** ++ * mcf_edma_isr - eDMA channel interrupt handler ++ * @irq: interrupt number ++ * @dev_id: argument ++ */ ++static irqreturn_t ++mcf_edma_isr(int irq, void *dev_id) ++{ ++ int channel = -1; ++ int result = IRQ_HANDLED; ++ ++#if defined(CONFIG_M5445X) ++ channel = irq - MCF_EDMA_INT0_BASE; ++#elif defined(CONFIG_M5441X) ++ if (irq >= MCF_EDMA_INT0_BASE && ++ irq < MCF_EDMA_INT0_BASE + MCF_EDMA_INT0_NUM) ++ channel = irq - MCF_EDMA_INT0_BASE; ++ else if (irq >= MCF_EDMA_INT1_BASE && ++ irq < MCF_EDMA_INT1_BASE + MCF_EDMA_INT1_NUM) ++ channel = irq - MCF_EDMA_INT1_BASE + MCF_EDMA_INT0_END; ++ else if (irq == MCF_EDMA_INT2_BASE && ++ irq < MCF_EDMA_INT2_BASE + MCF_EDMA_INT2_NUM) { ++ int i; ++ for (i = 0; i < MCF_EDMA_INT2_NUM; i++) { ++ if ((MCF_EDMA_INTH >> 24) & (0x1 << i)) { ++ channel = irq - MCF_EDMA_INT2_BASE + ++ MCF_EDMA_INT1_END + i; ++ break; ++ } ++ } ++ } else { ++ ERR("Bad irq number at isr!\n"); ++ return result; ++ } ++#endif ++ ++ DBG("\n"); ++ ++ if ((mcf_edma_devp != NULL) && ++ (mcf_edma_devp->dma_interrupt_handlers[channel].irq_handler)) { ++ /* call user irq handler */ ++ if (mcf_edma_devp->dma_interrupt_handlers[channel].lock) ++ spin_lock(mcf_edma_devp-> ++ dma_interrupt_handlers[channel].lock); ++ ++ result = ++ mcf_edma_devp->dma_interrupt_handlers[channel]. ++ irq_handler(channel, ++ mcf_edma_devp->dma_interrupt_handlers[channel]. ++ arg); ++ ++ if (mcf_edma_devp->dma_interrupt_handlers[channel].lock) ++ spin_unlock(mcf_edma_devp-> ++ dma_interrupt_handlers[channel].lock); ++ } else { ++ /* no irq handler so just ack it */ ++ mcf_edma_confirm_interrupt_handled(channel); ++ ERR(" No handler for DMA channel (%d)\n", channel); ++ } ++ ++ return result; ++} ++ ++/** ++ * mcf_edma_error_isr - eDMA error interrupt handler ++ * @irq: interrupt number ++ * @dev_id: argument ++ */ ++static irqreturn_t ++mcf_edma_error_isr(int irq, void *dev_id) ++{ ++ int i; ++ ++#if defined(CONFIG_M5445X) ++ u16 err; ++ ++ err = MCF_EDMA_ERR; ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ if (err & (1 << i)) { ++ if (mcf_edma_devp != NULL && ++ mcf_edma_devp->dma_interrupt_handlers[i]. ++ error_handler) ++ mcf_edma_devp->dma_interrupt_handlers[i]. ++ error_handler(i, ++ mcf_edma_devp-> ++ dma_interrupt_handlers[i]. ++ arg); ++ else ++ ERR(" DMA error on channel (%d)\n", i); ++ } ++ } ++#elif defined(CONFIG_M5441X) ++ u32 errl, errh; ++ ++ errl = MCF_EDMA_ERRL; ++ errh = MCF_EDMA_ERRH; ++ ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ if ((errl & (1 << i)) || (errh & (1 << (i - 32)))) { ++ if (mcf_edma_devp != NULL && ++ mcf_edma_devp->dma_interrupt_handlers[i]. ++ error_handler) ++ mcf_edma_devp->dma_interrupt_handlers[i]. ++ error_handler(i, mcf_edma_devp-> ++ dma_interrupt_handlers[i].arg); ++ else ++ ERR(" DMA error on channel (%d)\n", i); ++ } ++ } ++#endif ++ MCF_EDMA_CERR = MCF_EDMA_CERR_CAER; ++ return IRQ_HANDLED; ++} ++ ++/** ++ * mcf_edma_check_done - Check if channel is finished or not ++ * @channel: channel number ++ * return: 0 if not done yet ++ */ ++int ++mcf_edma_check_done(int channel) ++{ ++ if (channel < 0 || channel > MCF_EDMA_CHANNELS) ++ return 1; ++ ++ return MCF_EDMA_TCD_CSR(channel) & MCF_EDMA_TCD_CSR_DONE; ++} ++EXPORT_SYMBOL(mcf_edma_check_done); ++ ++/** ++ * mcf_edma_set_tcd_params - Set transfer control descriptor (TCD) ++ * @channel: channel number ++ * @source: source address ++ * @dest: destination address ++ * @attr: attributes ++ * @soff: source offset ++ * @nbytes: number of bytes to be transfered in minor loop ++ * @slast: last source address adjustment ++ * @citer: major loop count ++ * @biter: beginning major loop count ++ * @doff: destination offset ++ * @dlast_sga: last destination address adjustment ++ * @major_int: generate interrupt after each major loop ++ * @disable_req: disable DMA request after major loop ++ */ ++void ++mcf_edma_set_tcd_params(int channel, u32 source, u32 dest, ++ u32 attr, u32 soff, u32 nbytes, u32 slast, ++ u32 citer, u32 biter, u32 doff, u32 dlast_sga, ++ int major_int, int disable_req) ++{ ++ DBG("(%d)\n", channel); ++ ++ if (channel < 0 || channel > MCF_EDMA_CHANNELS) ++ return; ++ ++ MCF_EDMA_TCD_SADDR(channel) = source; ++ MCF_EDMA_TCD_DADDR(channel) = dest; ++ MCF_EDMA_TCD_ATTR(channel) = attr; ++ MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(soff); ++ MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(nbytes); ++ MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(slast); ++ MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(citer); ++ MCF_EDMA_TCD_BITER(channel) = MCF_EDMA_TCD_BITER_BITER(biter); ++ MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(doff); ++ MCF_EDMA_TCD_DLAST_SGA(channel) = ++ MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga); ++ MCF_EDMA_TCD_CSR(channel) = 0x0000; ++ ++ /* interrupt at the end of major loop */ ++ if (major_int) ++ MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_INT_MAJOR; ++ else ++ MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_INT_MAJOR; ++ ++ /* disable request at the end of major loop of transfer or not */ ++ if (disable_req) ++ MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_D_REQ; ++ else ++ MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_D_REQ; ++ ++ /* enable error interrupt */ ++ MCF_EDMA_SEEI = MCF_EDMA_SEEI_SEEI(channel); ++} ++EXPORT_SYMBOL(mcf_edma_set_tcd_params); ++#ifdef CONFIG_M54455 ++/** ++ * mcf_edma_sg_config - config an eDMA channel to use the S/G tcd feature ++ * @channel: channel number ++ * @buf: the array of tcd sg ++ * @nents: number of tcd sg array, the max is 256 set but can modify ++ * ++ * limitation: ++ * currently this function is only for PATA RX/TX on MCF54455, ++ * so eDMA init does not allocate TCD memory for other memory ++ * ++ * TODO: ++ * any one who need this feature shoule add his own TCD memory init ++ */ ++void mcf_edma_sg_config(int channel, struct fsl_edma_requestbuf *buf, ++ int nents) ++{ ++ struct TCD *vtcd = (struct TCD *)fsl_pata_dma_tcd.pata_tcd_va; ++ u32 ptcd = fsl_pata_dma_tcd.pata_tcd_pa; ++ struct fsl_edma_requestbuf *pb = buf; ++ int i; ++ ++ if (channel < MCF_EDMA_CHAN_ATA_RX || channel > MCF_EDMA_CHAN_ATA_TX) { ++ printk(KERN_ERR "mcf edma sg config err, not support\n"); ++ return; ++ } ++ if (nents > MCF_EDMA_TCD_PER_CHAN) { ++ printk(KERN_ERR "Too many SGs, please confirm.%d > %d\n", ++ nents, MCF_EDMA_TCD_PER_CHAN); ++ return; ++ } ++ ++ /* build our tcd sg array */ ++ for (i = 0; i < nents; i++) { ++ memset(vtcd, 0 , sizeof(struct TCD)); ++ vtcd->saddr = pb->saddr; ++ vtcd->daddr = pb->daddr; ++ vtcd->attr = pb->attr; ++ vtcd->soff = pb->soff; ++ vtcd->doff = pb->doff; ++ vtcd->nbytes = pb->minor_loop; ++ vtcd->citer = vtcd->biter = pb->len/pb->minor_loop; ++ ++ if (i != nents - 1) { ++ vtcd->csr |= MCF_EDMA_TCD_CSR_E_SG;/* we are tcd sg */ ++ vtcd->dlast_sga = ++ (u32)(ptcd + (i + 1)*sizeof(struct TCD)); ++ } else { ++ /*this is the last sg, so enable the major int*/ ++ vtcd->csr |= MCF_EDMA_TCD_CSR_INT_MAJOR ++ |MCF_EDMA_TCD_CSR_D_REQ; ++ } ++ pb++; ++ vtcd++; ++ } ++ ++ /* Now setup the firset TCD for this sg to the edma enginee */ ++ vtcd = fsl_pata_dma_tcd.pata_tcd_va; ++ ++ MCF_EDMA_TCD_CSR(channel) = 0x0000; ++ MCF_EDMA_TCD_SADDR(channel) = vtcd->saddr; ++ MCF_EDMA_TCD_DADDR(channel) = vtcd->daddr; ++ MCF_EDMA_TCD_ATTR(channel) = vtcd->attr; ++ MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(vtcd->soff); ++ MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(vtcd->nbytes); ++ MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(vtcd->slast); ++ MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(vtcd->citer); ++ MCF_EDMA_TCD_BITER(channel) = MCF_EDMA_TCD_BITER_BITER(vtcd->biter); ++ MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(vtcd->doff); ++ MCF_EDMA_TCD_DLAST_SGA(channel) = ++ MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(vtcd->dlast_sga); ++ MCF_EDMA_TCD_CSR(channel) |= vtcd->csr; ++} ++EXPORT_SYMBOL(mcf_edma_sg_config); ++ ++/** ++ * The zero-copy version of mcf_edma_sg_config ++ * dma_dir : indicate teh addr direction ++ */ ++void mcf_edma_sglist_config(int channel, struct scatterlist *sgl, int n_elem, ++ int dma_dir, u32 addr, u32 attr, ++ u32 soff, u32 doff, u32 nbytes) ++{ ++ struct TCD *vtcd = (struct TCD *)fsl_pata_dma_tcd.pata_tcd_va; ++ u32 ptcd = fsl_pata_dma_tcd.pata_tcd_pa; ++ struct scatterlist *sg; ++ u32 si; ++ ++ if (channel < MCF_EDMA_CHAN_ATA_RX || channel > MCF_EDMA_CHAN_ATA_TX) { ++ printk(KERN_ERR "mcf edma sg config err, not support\n"); ++ return; ++ } ++ if (n_elem > MCF_EDMA_TCD_PER_CHAN) { ++ printk(KERN_ERR "Too many SGs, please confirm.%d > %d\n", ++ n_elem, MCF_EDMA_TCD_PER_CHAN); ++ return; ++ } ++ ++ /* build our tcd sg array */ ++ if (dma_dir == DMA_TO_DEVICE) { /* write */ ++ for_each_sg(sgl, sg, n_elem, si) { ++ memset(vtcd, 0 , sizeof(struct TCD)); ++ vtcd->saddr = sg_dma_address(sg); ++ vtcd->daddr = addr; ++ vtcd->attr = attr; ++ vtcd->soff = soff; ++ vtcd->doff = doff; ++ vtcd->nbytes = nbytes; ++ vtcd->citer = vtcd->biter = sg_dma_len(sg)/nbytes; ++ ++ if (si != n_elem - 1) { ++ /* we are tcd sg */ ++ vtcd->csr |= MCF_EDMA_TCD_CSR_E_SG; ++ vtcd->dlast_sga = (u32)(ptcd + (si + 1) * \ ++ sizeof(struct TCD)); ++ } else { ++ /*this is the last sg, so enable the major int*/ ++ vtcd->csr |= MCF_EDMA_TCD_CSR_INT_MAJOR ++ |MCF_EDMA_TCD_CSR_D_REQ; ++ } ++ vtcd++; ++ } ++ } else { ++ for_each_sg(sgl, sg, n_elem, si) { ++ memset(vtcd, 0 , sizeof(struct TCD)); ++ vtcd->daddr = sg_dma_address(sg); ++ vtcd->saddr = addr; ++ vtcd->attr = attr; ++ vtcd->soff = soff; ++ vtcd->doff = doff; ++ vtcd->nbytes = nbytes; ++ vtcd->citer = vtcd->biter = sg_dma_len(sg)/nbytes; ++ ++ if (si != n_elem - 1) { ++ /* we are tcd sg */ ++ vtcd->csr |= MCF_EDMA_TCD_CSR_E_SG; ++ vtcd->dlast_sga = (u32)(ptcd + (si + 1) * \ ++ sizeof(struct TCD)); ++ } else { ++ /*this is the last sg, so enable the major int*/ ++ vtcd->csr |= MCF_EDMA_TCD_CSR_INT_MAJOR ++ |MCF_EDMA_TCD_CSR_D_REQ; ++ } ++ vtcd++; ++ } ++ } ++ ++ /* Now setup the firset TCD for this sg to the edma enginee */ ++ vtcd = fsl_pata_dma_tcd.pata_tcd_va; ++ ++ MCF_EDMA_TCD_CSR(channel) = 0x0000; ++ MCF_EDMA_TCD_SADDR(channel) = vtcd->saddr; ++ MCF_EDMA_TCD_DADDR(channel) = vtcd->daddr; ++ MCF_EDMA_TCD_ATTR(channel) = vtcd->attr; ++ MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(vtcd->soff); ++ MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(vtcd->nbytes); ++ MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(vtcd->slast); ++ MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(vtcd->citer); ++ MCF_EDMA_TCD_BITER(channel) = MCF_EDMA_TCD_BITER_BITER(vtcd->biter); ++ MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(vtcd->doff); ++ MCF_EDMA_TCD_DLAST_SGA(channel) = ++ MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(vtcd->dlast_sga); ++ ++ MCF_EDMA_TCD_CSR(channel) |= vtcd->csr; ++} ++EXPORT_SYMBOL(mcf_edma_sglist_config); ++#endif ++/** ++ * mcf_edma_set_tcd_params_halfirq - Set TCD AND enable half irq ++ * @channel: channel number ++ * @source: source address ++ * @dest: destination address ++ * @attr: attributes ++ * @soff: source offset ++ * @nbytes: number of bytes to be transfered in minor loop ++ * @slast: last source address adjustment ++ * @biter: beginning major loop count ++ * @doff: destination offset ++ * @dlast_sga: last destination address adjustment ++ * @disable_req: disable DMA request after major loop ++ */ ++void ++mcf_edma_set_tcd_params_halfirq(int channel, u32 source, u32 dest, ++ u32 attr, u32 soff, u32 nbytes, u32 slast, ++ u32 biter, u32 doff, u32 dlast_sga, ++ int disable_req) ++{ ++ DBG("(%d)\n", channel); ++ ++ if (channel < 0 || channel > MCF_EDMA_CHANNELS) ++ return; ++ ++ mcf_edma_set_tcd_params(channel, source, dest, ++ attr, soff, nbytes, slast, ++ biter, biter, doff, dlast_sga, ++ 1/*0*/, disable_req); ++ ++ if (biter < 2) ++ printk(KERN_ERR "MCF_EDMA: Request for halfway irq denied\n"); ++ ++ /* interrupt midway through major loop */ ++ MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_INT_HALF; ++} ++EXPORT_SYMBOL(mcf_edma_set_tcd_params_halfirq); ++ ++/** ++ * mcf_edma_request_channel - Request an eDMA channel ++ * @channel: channel number. In case it is equal to EDMA_CHANNEL_ANY ++ * it will be allocated a first free eDMA channel. ++ * @handler: dma handler ++ * @error_handler: dma error handler ++ * @irq_level: irq level for the dma handler ++ * @arg: argument to pass back ++ * @lock: optional spinlock to hold over interrupt ++ * @device_id: device id ++ * ++ * Returns allocatedd channel number if success or ++ * a negative value if failure. ++ */ ++int ++mcf_edma_request_channel(int channel, ++ irqreturn_t(*handler) (int, void *), ++ void (*error_handler) (int, void *), ++ u8 irq_level, ++ void *arg, spinlock_t *lock, const char *device_id) ++{ ++ DBG("\n channel=%d\n", channel); ++ ++ if (mcf_edma_devp != NULL ++ && ((channel >= 0 && channel <= MCF_EDMA_CHANNELS) ++ || (channel == MCF_EDMA_CHANNEL_ANY))) { ++ if (channel == MCF_EDMA_CHANNEL_ANY) { ++ int i; ++ for (i = 0; i < sizeof(mcf_edma_channel_pool); i++) { ++ if (mcf_edma_devp->dma_interrupt_handlers ++ [mcf_edma_channel_pool[i]].allocated == ++ 0) { ++ channel = mcf_edma_channel_pool[i]; ++ break; ++ } ++ }; ++ if (channel == MCF_EDMA_CHANNEL_ANY) ++ return -EBUSY; ++ } else { ++ if (mcf_edma_devp->dma_interrupt_handlers[channel]. ++ allocated) ++ return -EBUSY; ++ } ++ ++ mcf_edma_devp->dma_interrupt_handlers[channel].allocated = 1; ++ mcf_edma_devp->dma_interrupt_handlers[channel].irq_handler = ++ handler; ++ mcf_edma_devp->dma_interrupt_handlers[channel].error_handler = ++ error_handler; ++ mcf_edma_devp->dma_interrupt_handlers[channel].arg = arg; ++ mcf_edma_devp->dma_interrupt_handlers[channel].lock = lock; ++ mcf_edma_devp->dma_interrupt_handlers[channel].device_id = ++ device_id; ++ ++ /* Initalize interrupt controller to allow eDMA interrupts */ ++#if defined(CONFIG_M5445X) ++ MCF_INTC0_ICR(MCF_EDMA_INT0_CHANNEL_BASE + channel) = irq_level; ++ MCF_INTC0_CIMR = MCF_EDMA_INT0_CHANNEL_BASE + channel; ++#elif defined(CONFIG_M5441X) ++ if (channel >= 0 && channel < MCF_EDMA_INT0_END) { ++ MCF_INTC0_ICR(MCF_EDMA_INT0_CHANNEL_BASE + channel) = ++ irq_level; ++ MCF_INTC0_CIMR = MCF_EDMA_INT0_CHANNEL_BASE + channel; ++ } else if (channel >= MCF_EDMA_INT0_END && ++ channel < MCF_EDMA_INT1_END) { ++ MCF_INTC1_ICR(MCF_EDMA_INT1_CHANNEL_BASE + ++ (channel - MCF_EDMA_INT0_END)) = irq_level; ++ MCF_INTC1_CIMR = MCF_EDMA_INT1_CHANNEL_BASE + ++ (channel - MCF_EDMA_INT0_END); ++ } else if (channel >= MCF_EDMA_INT1_END && ++ channel < MCF_EDMA_INT2_END) { ++ MCF_INTC2_ICR(MCF_EDMA_INT2_CHANNEL_BASE) = irq_level; ++ MCF_INTC2_CIMR = MCF_EDMA_INT2_CHANNEL_BASE; ++ } else ++ ERR("Bad channel number!\n"); ++#endif ++ return channel; ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(mcf_edma_request_channel); ++ ++/** ++ * mcf_edma_set_callback - Update the channel callback/arg ++ * @channel: channel number ++ * @handler: dma handler ++ * @error_handler: dma error handler ++ * @arg: argument to pass back ++ * ++ * Returns 0 if success or a negative value if failure ++ */ ++int ++mcf_edma_set_callback(int channel, ++ irqreturn_t(*handler) (int, void *), ++ void (*error_handler) (int, void *), void *arg) ++{ ++ DBG("\n"); ++ ++ if (mcf_edma_devp != NULL && channel >= 0 ++ && channel <= MCF_EDMA_CHANNELS ++ && mcf_edma_devp->dma_interrupt_handlers[channel].allocated) { ++ mcf_edma_devp->dma_interrupt_handlers[channel].irq_handler = ++ handler; ++ mcf_edma_devp->dma_interrupt_handlers[channel].error_handler = ++ error_handler; ++ mcf_edma_devp->dma_interrupt_handlers[channel].arg = arg; ++ return 0; ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(mcf_edma_set_callback); ++ ++/** ++ * mcf_edma_free_channel - Free the edma channel ++ * @channel: channel number ++ * @arg: argument created with ++ * ++ * Returns 0 if success or a negative value if failure ++ */ ++int ++mcf_edma_free_channel(int channel, void *arg) ++{ ++ DBG("\n"); ++ ++ if (mcf_edma_devp != NULL && channel >= 0 ++ && channel <= MCF_EDMA_CHANNELS) { ++ if (mcf_edma_devp->dma_interrupt_handlers[channel].allocated) { ++#if 1 ++ if (mcf_edma_devp->dma_interrupt_handlers[channel]. ++ arg != arg) ++ return -EBUSY; ++#endif ++ ++ mcf_edma_devp->dma_interrupt_handlers[channel]. ++ allocated = 0; ++ mcf_edma_devp->dma_interrupt_handlers[channel].arg = ++ NULL; ++ mcf_edma_devp->dma_interrupt_handlers[channel]. ++ irq_handler = NULL; ++ mcf_edma_devp->dma_interrupt_handlers[channel]. ++ error_handler = NULL; ++ mcf_edma_devp->dma_interrupt_handlers[channel].lock = ++ NULL; ++ } ++ ++ /* make sure error interrupt is disabled */ ++ MCF_EDMA_CEEI = MCF_EDMA_CEEI_CEEI(channel); ++ ++ return 0; ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(mcf_edma_free_channel); ++ ++/** ++ * mcf_edma_cleanup - cleanup driver allocated resources ++ */ ++static void ++mcf_edma_cleanup(void) ++{ ++ dev_t devno; ++ int i; ++ ++ DBG("\n"); ++ ++ /* disable all error ints */ ++ MCF_EDMA_CEEI = MCF_EDMA_CEEI_CAEE; ++ ++ /* free interrupts/memory */ ++ if (mcf_edma_devp) { ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ #if defined(CONFIG_M5445X) ++ free_irq(MCF_EDMA_INT0_BASE + i, mcf_edma_devp); ++ #elif defined(CONFIG_M5441X) ++ if (i >= 0 && i < MCF_EDMA_INT0_END) ++ free_irq(MCF_EDMA_INT0_BASE + i, mcf_edma_devp); ++ else if (i >= MCF_EDMA_INT0_END && ++ i <= MCF_EDMA_INT1_END) ++ free_irq(MCF_EDMA_INT1_BASE + ++ (i - MCF_EDMA_INT0_END), mcf_edma_devp); ++ else if (i >= MCF_EDMA_INT1_END && ++ i < MCF_EDMA_INT2_END) { ++ free_irq(MCF_EDMA_INT2_BASE, mcf_edma_devp); ++ break; ++ } else { ++ ERR("Bad irq number!\n"); ++ return; ++ } ++ #endif ++ } ++ ++ free_irq(MCF_EDMA_INT0_BASE + MCF_EDMA_INT_ERR, mcf_edma_devp); ++ cdev_del(&mcf_edma_devp->cdev); ++ kfree(mcf_edma_devp); ++ } ++ ++ /* unregister character device */ ++ devno = MKDEV(mcf_edma_major, 0); ++ unregister_chrdev_region(devno, 1); ++} ++ ++/** ++ * mcf_edma_dump_channel - dump a channel information ++ */ ++void ++mcf_edma_dump_channel(int channel) ++{ ++ printk(KERN_DEBUG "EDMA Channel %d\n", channel); ++ printk(KERN_DEBUG " TCD Base = 0x%x\n", ++ (int)&MCF_EDMA_TCD_SADDR(channel)); ++ printk(KERN_DEBUG " SRCADDR = 0x%lx\n", ++ MCF_EDMA_TCD_SADDR(channel)); ++ printk(KERN_DEBUG " SRCOFF = 0x%x\n", ++ MCF_EDMA_TCD_SOFF(channel)); ++ printk(KERN_DEBUG " XFR ATTRIB = 0x%x\n", ++ MCF_EDMA_TCD_ATTR(channel)); ++ printk(KERN_DEBUG " SRCLAST = 0x%lx\n", ++ MCF_EDMA_TCD_SLAST(channel)); ++ printk(KERN_DEBUG " DSTADDR = 0x%lx\n", ++ MCF_EDMA_TCD_DADDR(channel)); ++ printk(KERN_DEBUG " MINOR BCNT = 0x%lx\n", ++ MCF_EDMA_TCD_NBYTES(channel)); ++ printk(KERN_DEBUG " CUR_LOOP_CNT = 0x%x\n", ++ MCF_EDMA_TCD_CITER(channel)&0x1ff); ++ printk(KERN_DEBUG " BEG_LOOP_CNT = 0x%x\n", ++ MCF_EDMA_TCD_BITER(channel)&0x1ff); ++ printk(KERN_DEBUG " STATUS = 0x%x\n", ++ MCF_EDMA_TCD_CSR(channel)); ++ ++} ++EXPORT_SYMBOL(mcf_edma_dump_channel); ++ ++#ifdef CONFIG_PROC_FS ++/* ++ * proc file system support ++ */ ++ ++#define FREE_CHANNEL "free" ++#define DEVICE_UNKNOWN "device unknown" ++ ++/** ++ * mcf_edma_proc_show - print out proc info ++ * @m: seq_file ++ * @v: ++ */ ++static int ++mcf_edma_proc_show(struct seq_file *m, void *v) ++{ ++ int i; ++ ++ if (mcf_edma_devp == NULL) ++ return 0; ++ ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ if (mcf_edma_devp->dma_interrupt_handlers[i].allocated) { ++ if (mcf_edma_devp->dma_interrupt_handlers[i].device_id) ++ seq_printf(m, "%2d: %s\n", i, ++ mcf_edma_devp-> ++ dma_interrupt_handlers[i]. ++ device_id); ++ else ++ seq_printf(m, "%2d: %s\n", i, DEVICE_UNKNOWN); ++ } else ++ seq_printf(m, "%2d: %s\n", i, FREE_CHANNEL); ++ } ++ return 0; ++} ++ ++/** ++ * mcf_edma_proc_open - open the proc file ++ * @inode: inode ptr ++ * @file: file ptr ++ */ ++static int ++mcf_edma_proc_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, mcf_edma_proc_show, NULL); ++} ++ ++static const struct file_operations mcf_edma_proc_operations = { ++ .open = mcf_edma_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/** ++ * mcf_edma_proc_init - initialize proc filesystem ++ */ ++static int __init ++mcf_edma_proc_init(void) ++{ ++ struct proc_dir_entry *e; ++ ++ e = create_proc_entry("edma", 0, NULL); ++ if (e) ++ e->proc_fops = &mcf_edma_proc_operations; ++ ++ return 0; ++} ++ ++#endif ++ ++/** ++ * mcf_edma_init - eDMA module init ++ */ ++static int __init ++mcf_edma_init(void) ++{ ++ dev_t dev; ++ int result; ++ int i; ++#ifdef CONFIG_M54455 ++ u32 offset; ++#endif ++ ++#if defined(CONFIG_M5441X) ++ /* edma group priority, default grp0 > grp1 > grp2 > grp3 */ ++ u32 grp0_pri = MCF_EDMA_CR_GRP0PRI(0x00); ++ u32 grp1_pri = MCF_EDMA_CR_GRP1PRI(0x01); ++ u32 grp2_pri = MCF_EDMA_CR_GRP2PRI(0x02); ++ u32 grp3_pri = MCF_EDMA_CR_GRP3PRI(0x03); ++#endif ++ ++ DBG("Entry\n"); ++ ++ /* allocate free major number */ ++ result = ++ alloc_chrdev_region(&dev, MCF_EDMA_DEV_MINOR, 1, ++ MCF_EDMA_DRIVER_NAME); ++ if (result < 0) { ++ ERR("Error %d can't get major number.\n", result); ++ return result; ++ } ++ mcf_edma_major = MAJOR(dev); ++ ++ /* allocate device driver structure */ ++ mcf_edma_devp = kmalloc(sizeof(struct mcf_edma_dev), GFP_KERNEL); ++ if (!mcf_edma_devp) { ++ result = -ENOMEM; ++ goto fail; ++ } ++ ++ /* init handlers (no handlers for beginning) */ ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ mcf_edma_devp->dma_interrupt_handlers[i].irq_handler = NULL; ++ mcf_edma_devp->dma_interrupt_handlers[i].error_handler = NULL; ++ mcf_edma_devp->dma_interrupt_handlers[i].arg = NULL; ++ mcf_edma_devp->dma_interrupt_handlers[i].allocated = 0; ++ mcf_edma_devp->dma_interrupt_handlers[i].lock = NULL; ++ mcf_edma_devp->dma_interrupt_handlers[i].device_id = NULL; ++ MCF_EDMA_TCD_CSR(i) = 0x0000; ++ } ++ ++ /* register char device */ ++ cdev_init(&mcf_edma_devp->cdev, &mcf_edma_fops); ++ mcf_edma_devp->cdev.owner = THIS_MODULE; ++ mcf_edma_devp->cdev.ops = &mcf_edma_fops; ++ result = cdev_add(&mcf_edma_devp->cdev, dev, 1); ++ if (result) { ++ ERR("Error %d adding coldfire-dma device.\n", result); ++ result = -ENODEV; ++ goto fail; ++ } ++ ++ /* request/enable irq for each eDMA channel */ ++#if defined(CONFIG_M5445X) ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ result = request_irq(MCF_EDMA_INT0_BASE + i, ++ mcf_edma_isr, IRQF_DISABLED, ++ MCF_EDMA_DRIVER_NAME, mcf_edma_devp); ++ if (result) { ++ ERR("Cannot request irq %d\n", ++ (MCF_EDMA_INT0_BASE + i)); ++ result = -EBUSY; ++ goto fail; ++ } ++ } ++#elif defined(CONFIG_M5441X) ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ if (i >= 0 && i < MCF_EDMA_INT0_END) { ++ result = request_irq(MCF_EDMA_INT0_BASE + i, ++ mcf_edma_isr, IRQF_DISABLED, ++ MCF_EDMA_DRIVER_NAME, ++ mcf_edma_devp); ++ ++ if (result) { ++ ERR("Cannot request irq %d\n", ++ (MCF_EDMA_INT0_BASE + i)); ++ result = -EBUSY; ++ goto fail; ++ } ++ } else if (i >= MCF_EDMA_INT0_END && i < MCF_EDMA_INT1_END) { ++ result = request_irq(MCF_EDMA_INT1_BASE + ++ (i - MCF_EDMA_INT0_END), ++ mcf_edma_isr, IRQF_DISABLED, ++ MCF_EDMA_DRIVER_NAME, ++ mcf_edma_devp); ++ ++ if (result) { ++ ERR("Cannot request irq %d\n", ++ (MCF_EDMA_INT1_BASE + ++ (i - MCF_EDMA_INT0_END))); ++ result = -EBUSY; ++ goto fail; ++ } ++ } else if (i >= MCF_EDMA_INT1_END && MCF_EDMA_INT2_END) { ++ result = request_irq(MCF_EDMA_INT2_BASE, ++ mcf_edma_isr, IRQF_DISABLED, ++ MCF_EDMA_DRIVER_NAME, ++ mcf_edma_devp); ++ if (result) { ++ ERR("Cannot request irq %d\n", ++ MCF_EDMA_INT2_BASE); ++ result = -EBUSY; ++ goto fail; ++ } ++ break; ++ } else { ++ ERR(" Cannot request irq because of wrong number!\n"); ++ result = -EBUSY; ++ goto fail; ++ } ++ } ++#endif ++ ++ /* request error interrupt */ ++ result = request_irq(MCF_EDMA_INT0_BASE + MCF_EDMA_INT_ERR, ++ mcf_edma_error_isr, IRQF_DISABLED, ++ MCF_EDMA_DRIVER_NAME, mcf_edma_devp); ++ if (result) { ++ ERR("Cannot request irq %d\n", ++ (MCF_EDMA_INT0_BASE + MCF_EDMA_INT_ERR)); ++ result = -EBUSY; ++ goto fail; ++ } ++ ++#if defined(CONFIG_M5445X) ++ MCF_EDMA_CR = 0; ++#elif defined(CONFIG_M5441X) ++ MCF_EDMA_CR = (0 | grp0_pri | grp1_pri | grp2_pri | grp3_pri); ++ DBG("MCF_EDMA_CR = %lx\n", MCF_EDMA_CR); ++#endif ++ ++#ifdef CONFIG_M54455 ++ fsl_pata_dma_tcd.pata_tcd_va = (struct TCD *) dma_alloc_coherent(NULL, ++ MCF_EDMA_TCD_PER_CHAN + 1, ++ &fsl_pata_dma_tcd.pata_tcd_pa, ++ GFP_KERNEL); ++ ++ if (!fsl_pata_dma_tcd.pata_tcd_va) { ++ printk(KERN_INFO "MCF eDMA alllocate tcd memeory failed\n"); ++ goto fail; ++ } ++ ++ ++ offset = (fsl_pata_dma_tcd.pata_tcd_pa & (sizeof(struct TCD)-1)) ; ++ if (offset) { ++ /* ++ * up align the addr to 32B to match the eDMA enginee require, ++ * ie. sizeof tcd boundary ++ * */ ++ printk(KERN_INFO "pata tcd original:pa-%x[%x]\n", ++ fsl_pata_dma_tcd.pata_tcd_pa, ++ (u32)fsl_pata_dma_tcd.pata_tcd_va); ++ ++ fsl_pata_dma_tcd.pata_tcd_pa += sizeof(struct TCD) - offset; ++ fsl_pata_dma_tcd.pata_tcd_va += sizeof(struct TCD) - offset; ++ ++ printk(KERN_INFO "pata tcd realigned:pa-%x[%x]\n", ++ fsl_pata_dma_tcd.pata_tcd_pa, ++ (u32)fsl_pata_dma_tcd.pata_tcd_va); ++ } ++#endif ++#ifdef CONFIG_PROC_FS ++ mcf_edma_proc_init(); ++#endif ++ ++ INFO("Initialized successfully\n"); ++ return 0; ++fail: ++ mcf_edma_cleanup(); ++ return result; ++} ++ ++/** ++ * mcf_edma_exit - eDMA module exit ++ */ ++static void __exit ++mcf_edma_exit(void) ++{ ++ mcf_edma_cleanup(); ++} ++ ++#ifdef CONFIG_COLDFIRE_EDMA_MODULE ++module_init(mcf_edma_init); ++module_exit(mcf_edma_exit); ++#else ++/* get us in early */ ++postcore_initcall(mcf_edma_init); ++#endif ++ ++MODULE_DESCRIPTION(MCF_EDMA_DRIVER_INFO); ++MODULE_AUTHOR(MCF_EDMA_DRIVER_AUTHOR); ++MODULE_LICENSE(MCF_EDMA_DRIVER_LICENSE); +--- /dev/null ++++ b/drivers/dma/mcf_edma_test.c +@@ -0,0 +1,276 @@ ++/* ++ * mcf_edma_test.c - simple test/example module for Coldfire eDMA. ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.001 29 February 2008 Andrey Butok ++ * Initial Release ++ * ++ * NOTE: This module tests eDMA driver performing ++ * a simple memory to memory transfer with a 32 bit ++ * source and destination transfer size that generates ++ * an interrupt when the transfer is complete. ++ */ ++ ++#include <linux/dma-mapping.h> ++#include <linux/init.h> ++#include <linux/fs.h> ++#include <linux/cdev.h> ++#include <linux/seq_file.h> ++#include <linux/proc_fs.h> ++#include <asm/mcfsim.h> ++#include <asm/coldfire.h> ++#include <asm/mcf_edma.h> ++#include <asm/cacheflush.h> ++ ++#define MCF_EDMA_TEST_DRIVER_VERSION "Revision: 0.001" ++#define MCF_EDMA_TEST_DRIVER_AUTHOR \ ++ "Freescale Semiconductor Inc, Andrey Butok" ++#define MCF_EDMA_TEST_DRIVER_DESC \ ++ "Simple testing module for Coldfire eDMA " ++#define MCF_EDMA_TEST_DRIVER_INFO \ ++ MCF_EDMA_TEST_DRIVER_VERSION " " MCF_EDMA_TEST_DRIVER_DESC ++#define MCF_EDMA_TEST_DRIVER_LICENSE "GPL" ++#define MCF_EDMA_TEST_DRIVER_NAME "mcf_edma_test" ++ ++#ifndef TRUE ++#define TRUE 1 ++#define FALSE 0 ++#endif ++ ++#define TEST_HALFIRQ ++ ++/* Global variable used to signal main process when interrupt is recognized */ ++static volatile int mcf_edma_test_interrupt; ++volatile int *mcf_edma_test_interrupt_p = ++ (volatile int *) &mcf_edma_test_interrupt; ++ ++/********************************************************************/ ++static irqreturn_t ++mcf_edma_test_handler(int channel, void *dev_id) ++{ ++ int done = mcf_edma_check_done(channel); ++ ++ /* Clear interrupt flag */ ++ mcf_edma_confirm_interrupt_handled(channel); ++ ++ if (done) { ++ printk(KERN_INFO "DMA Finished\n"); ++ ++ /* Set interrupt status flag to TRUE */ ++ mcf_edma_test_interrupt = TRUE; ++ } else { ++ printk(KERN_INFO "DMA Halfway Done\n"); ++ ++ /* restart DMA. */ ++ mcf_edma_confirm_halfirq(channel); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void ++mcf_edma_test_error_handler(int channel, void *dev_id) ++{ ++ printk(KERN_INFO "DMA ERROR: Channel = %d\n", channel); ++ printk(KERN_INFO " EDMA_ES = 0x%lx\n", (MCF_EDMA_ES)); ++ mcf_edma_dump_channel(channel); ++} ++ ++/********************************************************************/ ++ ++int ++mcf_edma_test_block_compare(u8 *block1, u8 *block2, u32 size) ++{ ++ u32 i; ++ ++ for (i = 0; i < (size); i++) { ++ if ((*(u8 *) (block1 + i)) != (*(u8 *) (block2 + i))) { ++ printk(KERN_INFO "Data Mismatch index=0x%x len=0x%x " ++ "block1=0x%p block2=0x%p\n", ++ i, size, block1, block2); ++ return FALSE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++/********************************************************************/ ++ ++void ++mcf_edma_test_run(void) ++{ ++ u16 byte_count; ++ u32 i, j; ++ u8 *start_address; ++ u8 *dest_address; ++ u32 test_data; ++ int channel; ++ u32 allocated_channels_low = 0; ++ u32 allocated_channels_high = 0; ++ ++ printk(KERN_INFO "\n===============================================\n"); ++ printk(KERN_INFO "\nStarting eDMA transfer test!\n"); ++ ++ /* Initialize test variables */ ++ byte_count = 0x2000; ++ test_data = 0xA5A5A5A5; ++ ++ /* DMA buffer must be from GFP_DMA zone, so it will not be cached */ ++ start_address = kmalloc(byte_count, GFP_DMA); ++ if (start_address == NULL) { ++ printk(KERN_INFO MCF_EDMA_TEST_DRIVER_NAME ++ ": failed to allocate DMA[%d] buffer\n", byte_count); ++ goto err_out; ++ } ++ dest_address = kmalloc(byte_count, /*GFP_KERNEL*/GFP_DMA); ++ if (dest_address == NULL) { ++ printk(KERN_INFO MCF_EDMA_TEST_DRIVER_NAME ++ ": failed to allocate DMA[%d] buffer\n", byte_count); ++ goto err_free_mem; ++ } ++ ++ /* Test all automatically allocated DMA channels. The test data is ++ * complemented at the end of the loop, so that the testData value ++ * isn't the same twice in a row */ ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ /* request eDMA channel */ ++ channel = mcf_edma_request_channel(MCF_EDMA_CHANNEL_ANY, ++ mcf_edma_test_handler, ++ mcf_edma_test_error_handler, ++ 0x6, ++ NULL, ++ NULL, ++ MCF_EDMA_TEST_DRIVER_NAME); ++ if (channel < 0) ++ goto test_end; ++ ++ ++ if (channel >= 0 && channel < 32) ++ allocated_channels_low |= (1 << channel); ++ else if (channel >= 32 && channel < 64) ++ allocated_channels_high |= (1 << (channel - 32)); ++ ++ /* Initialize data for DMA to move */ ++ for (j = 0; j < byte_count; j = j + 4) { ++ *((u32 *) (start_address + j)) = test_data; ++ *((u32 *) (dest_address + j)) = ~test_data; ++ } ++ ++ /* Clear interrupt status indicator */ ++ mcf_edma_test_interrupt = FALSE; ++ ++ /* Configure DMA Channel TCD */ ++#ifndef TEST_HALFIRQ ++ /* regular irq on completion */ ++ mcf_edma_set_tcd_params(channel, ++ (u32)virt_to_phys(start_address), ++ (u32)virt_to_phys(dest_address), ++ (0 | MCF_EDMA_TCD_ATTR_SSIZE_32BIT | ++ MCF_EDMA_TCD_ATTR_DSIZE_32BIT), 0x04, ++ byte_count, 0x0, 1, 1, 0x04, 0x0, 0x1, ++ 0x0); ++#else ++ /* half completion irq */ ++ mcf_edma_set_tcd_params_halfirq(channel, ++ (u32)virt_to_phys(start_address), ++ (u32)virt_to_phys(dest_address), ++ (MCF_EDMA_TCD_ATTR_SSIZE_32BIT | ++ MCF_EDMA_TCD_ATTR_DSIZE_32BIT), ++ 0x04, /* soff */ ++ byte_count/2, /* bytes/loop */ ++ 0x0, /* slast */ ++ 2, /* loop count */ ++ 0x04, /* doff */ ++ 0x0, /* dlast_sga */ ++ 0x0); /* req dis */ ++#endif ++ ++ printk(KERN_INFO "DMA Channel %d Bytes = 0x%x\n", ++ channel, byte_count); ++ /* Start DMA. */ ++ mcf_edma_start_transfer(channel); ++ ++ printk(KERN_INFO "DMA channel %d started.\n", channel); ++ ++ /* Wait for DMA to complete */ ++ while (!*mcf_edma_test_interrupt_p) ++ ; ++ ++ /* Test data */ ++ if (mcf_edma_test_block_compare ++ (start_address, dest_address, byte_count)) ++ printk(KERN_INFO "Data are moved correctly.\n"); ++ else ++ printk(KERN_INFO "ERROR!!! Data error!\n"); ++ ++ printk(KERN_INFO "DMA channel %d test complete.\n", channel); ++ printk(KERN_INFO "-------------------------------\n"); ++ ++ /* Complement test data so next channel test does not ++ * use same values */ ++ test_data = ~test_data; ++ } ++ ++test_end: ++ printk(KERN_INFO "All tests are complete\n\n"); ++ printk(KERN_INFO ++ "It has been automatically allocated %d eDMA channels:\n", i); ++ for (i = 0; i < MCF_EDMA_CHANNELS; i++) { ++ if ((allocated_channels_low & (1 << i)) || ++ (allocated_channels_high & (1 << (i - 32)))) { ++ printk(KERN_INFO "%d,\n", i); ++ mcf_edma_free_channel(i, NULL); ++ } ++ } ++ printk(KERN_INFO "===============================================\n\n"); ++ ++ kfree(dest_address); ++err_free_mem: ++ kfree(start_address); ++err_out: ++ return; ++} ++ ++/********************************************************************/ ++ ++static int __init ++mcf_edma_test_init(void) ++{ ++ mcf_edma_test_run(); ++ ++ /* We intentionaly return -EAGAIN to prevent keeping ++ * the module. It does all its work from init() ++ * and doesn't offer any runtime functionality */ ++ return -EAGAIN; ++} ++ ++static void __exit ++mcf_edma_test_exit(void) ++{ ++} ++ ++module_init(mcf_edma_test_init); ++module_exit(mcf_edma_test_exit); ++ ++MODULE_DESCRIPTION(MCF_EDMA_TEST_DRIVER_INFO); ++MODULE_AUTHOR(MCF_EDMA_TEST_DRIVER_AUTHOR); ++MODULE_LICENSE(MCF_EDMA_TEST_DRIVER_LICENSE); diff --git a/target/linux/coldfire/patches/008-Add-DSPI-driver-support-for-MCF5445x-MCF5441x.patch b/target/linux/coldfire/patches/008-Add-DSPI-driver-support-for-MCF5445x-MCF5441x.patch new file mode 100644 index 000000000..d64837def --- /dev/null +++ b/target/linux/coldfire/patches/008-Add-DSPI-driver-support-for-MCF5445x-MCF5441x.patch @@ -0,0 +1,1580 @@ +From ec1abf6de20d80b8a2c43f747b5a05aba0ecd3b2 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:40 +0800 +Subject: [PATCH 08/52] Add DSPI driver support for MCF5445x/MCF5441x + +Add DSPI driver support for MCF5445x and MCF5441x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/mcfqspi.h | 5 + + drivers/spi/Kconfig | 35 + + drivers/spi/Makefile | 1 + + drivers/spi/dspi_mcf.c | 1486 +++++++++++++++++++++++++++++++++++++++ + 4 files changed, 1527 insertions(+), 0 deletions(-) + create mode 100644 drivers/spi/dspi_mcf.c + +--- a/arch/m68k/include/asm/mcfqspi.h ++++ b/arch/m68k/include/asm/mcfqspi.h +@@ -2,6 +2,7 @@ + * Definitions for Freescale Coldfire QSPI module + * + * Copyright 2010 Steven King <sfking@fdwdc.com> ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 +@@ -21,6 +22,10 @@ + #ifndef mcfqspi_h + #define mcfqspi_h + ++#define QSPI_CS_INIT 0x01 ++#define QSPI_CS_ASSERT 0x02 ++#define QSPI_CS_DROP 0x04 ++ + #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) + #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) + #elif defined(CONFIG_M5249) +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -154,6 +154,41 @@ config SPI_GPIO + GPIO operations, you should be able to leverage that for better + speed with a custom version of this driver; see the source code. + ++config SPI_DSPI ++ tristate "Coldfire DSPI" ++ depends on SPI_MASTER && COLDFIRE ++ help ++ SPI driver for Coldfire DSPI driver only. ++ ++choice ++ prompt "Selsect DSPI controller" ++ depends on SPI_DSPI && M5441X ++ default DSPI0 ++ ++config DSPI0 ++ bool "DSPI0 controller" ++ help ++ DSPI0 controller on m5441x platform ++ ++config DSP0_SBF_CS ++ hex ++ prompt "Chip select for serial flash on DSPI0" ++ depends on DSPI0 && M5441X ++ default 1 ++ ++config DSPI1 ++ bool "DSPI1 controller" ++ help ++ DSPI1 controller on m5441x platform ++endchoice ++ ++config SPI_COLDFIRE_DSPI_EDMA ++ boolean "Coldfire DSPI master driver uses eDMA" ++ depends on SPI_MASTER && COLDFIRE && SPI_DSPI && COLDFIRE_EDMA ++ default n ++ help ++ Say "yes" if you want DSPI master driver to use eDMA for transfers. ++ + config SPI_IMX_VER_IMX1 + def_bool y if SOC_IMX1 + +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -23,6 +23,7 @@ dw_spi_midpci-objs := dw_spi_pci.o dw_ + obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o + obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o + obj-$(CONFIG_SPI_GPIO) += spi_gpio.o ++obj-$(CONFIG_SPI_DSPI) += dspi_mcf.o + obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o + obj-$(CONFIG_SPI_IMX) += spi_imx.o + obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o +--- /dev/null ++++ b/drivers/spi/dspi_mcf.c +@@ -0,0 +1,1486 @@ ++/* ++ * dspi_mcf.c - DSPI controller for ColdFire processors ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Matt Waddel Matt.Waddel@freescale.com ++ * Kurt Mahan kmahan@freescale.com ++ * Wang Huan <b18965@freescale.com> ++ * Jingchang Lu <b22599@freescale.com> ++ * Lanttor.Guo@freescale.com ++ * ++ * Based on spi_coldfire.c ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.003 M5301x support. ++ * v0.002 M547x/M548x support. ++ * v0.001 Initial version. Coldfire DSPI master driver. ++ ****************************************************************************/ ++ ++/* ++ * Includes ++ */ ++ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/device.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <linux/spi/spi.h> ++#include <linux/workqueue.h> ++#include <linux/delay.h> ++#include <asm/mcfsim.h> ++#include <asm/mcfqspi.h> ++#include <asm/coldfire.h> ++#include <linux/io.h> ++#include <asm/mcfdspi.h> ++#include <linux/dma-mapping.h> ++ ++#include <linux/time.h> ++#undef DSPI_COLDFIRE_DEBUG ++ ++#ifdef DSPI_COLDFIRE_DEBUG ++#define DBG(fmt, args...) \ ++ printk(KERN_INFO "[%s] " fmt , __func__, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#if defined(CONFIG_M5445X) ++#include <asm/mcf5445x_dspi.h> ++#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA) ++ #include <asm/mcf5445x_edma.h> ++#endif ++#elif defined(CONFIG_M5441X) ++#include <asm/mcf5441x_dspi.h> ++#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA) ++#include <asm/mcf5441x_edma.h> ++#endif ++#endif ++ ++#if defined(CONFIG_M547X_8X) ++#include <asm/virtconvert.h> ++#include <asm/m5485dspi.h> ++#endif ++ ++#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA) ++#include <asm/mcf_edma.h> ++#define SPI_DSPI_EDMA ++#define EDMA_BUFSIZE_KMALLOC (DSPI_FIFO_SIZE*4) ++#if defined(CONFIG_M5445X) ++#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI_RX ++#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI_TX ++#elif defined(CONFIG_M5441X) ++#if defined(CONFIG_DSPI0) ++#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI0_RX ++#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI0_TX ++#elif defined(CONFIG_DSPI1) ++#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI1_RX ++#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI1_TX ++#endif ++#endif ++ ++#undef NEW_DMA_METHOD ++ ++#endif ++ ++#define DSPI_BITS MCF_DSPI_DCTAR_FMSZ(0xF) ++#define DSPI_BITS_16 MCF_DSPI_DCTAR_FMSZ(0xF) ++#define DSPI_BITS_8 MCF_DSPI_DCTAR_FMSZ(0x7) ++ ++#ifdef NEW_DMA_METHOD ++#define DSPI_FIFO_SIZE (16) ++#else ++#define DSPI_FIFO_SIZE 16 ++#endif ++ ++#define DRIVER_NAME "Coldfire DSPI" ++ ++/****************************************************************************/ ++ ++/* ++ * Local constants and macros ++ */ ++ ++#define START_STATE ((void *)0) ++#define RUNNING_STATE ((void *)1) ++#define DONE_STATE ((void *)2) ++#define ERROR_STATE ((void *)-1) ++ ++#define QUEUE_RUNNING 0 ++#define QUEUE_STOPPED 1 ++#define TRAN_STATE_RX_VOID 0x01 ++#define TRAN_STATE_TX_VOID 0x02 ++#define TRAN_STATE_WORD_ODD_NUM 0x04 ++/****************************************************************************/ ++ ++/* ++ * Local Data Structures ++ */ ++ ++struct DSPI_MCR { ++ unsigned master:1; ++ unsigned cont_scke:1; ++ unsigned dconf:2; ++ unsigned frz:1; ++ unsigned mtfe:1; ++ unsigned pcsse:1; ++ unsigned rooe:1; ++ unsigned pcsis:8; ++ unsigned reserved15:1; ++ unsigned mdis:1; ++ unsigned dis_tx:1; ++ unsigned dis_rxf:1; ++ unsigned clr_tx:1; ++ unsigned clr_rxf:1; ++ unsigned smpl_pt:2; ++ unsigned reserved71:7; ++ unsigned halt:1; ++}; ++ ++struct DSPI_CTAR { ++ unsigned dbr:1; ++ unsigned fmsz:4; ++ unsigned cpol:1; ++ unsigned cpha:1; ++ unsigned lsbfe:1; ++ unsigned pcssck:2; ++ unsigned pasc:2; ++ unsigned pdt:2; ++ unsigned pbr:2; ++ unsigned cssck:4; ++ unsigned asc:4; ++ unsigned dt:4; ++ unsigned br:4; ++}; ++ ++struct chip_data { ++ /* dspi data */ ++ union { ++ u32 mcr_val; ++ struct DSPI_MCR mcr; ++ }; ++ union { ++ u32 ctar_val; ++ struct DSPI_CTAR ctar; ++ }; ++ u16 void_write_data; ++}; ++ ++ ++struct driver_data { ++ /* Driver model hookup */ ++ struct platform_device *pdev; ++ ++ /* SPI framework hookup */ ++ struct spi_master *master; ++ ++ /* Driver message queue */ ++ struct workqueue_struct *workqueue; ++ struct work_struct pump_messages; ++ spinlock_t lock; /* lock */ ++ struct list_head queue; ++ int busy; ++ int run; ++ ++ /* Message Transfer pump */ ++ struct tasklet_struct pump_transfers; ++ ++ /* Current message transfer state info */ ++ struct spi_message *cur_msg; ++ struct spi_transfer *cur_transfer; ++ struct chip_data *cur_chip; ++ size_t len; ++ void *tx; ++ void *tx_end; ++ void *rx; ++ void *rx_end; ++ char flags; ++ u8 cs; ++ u16 void_write_data; ++ unsigned cs_change:1; ++ ++ u32 trans_cnt; ++ u32 wce_cnt; ++ u32 abrt_cnt; ++ volatile u32 *mcr; /* DSPI MCR register */ ++ volatile u32 *ctar; /* DSPI CTAR register */ ++ volatile u32 *dspi_dtfr; /* DSPI DTFR register */ ++ volatile u32 *dspi_drfr; /* DSPI DRFR register */ ++ volatile u32 *dspi_rser; /* DSPI RSER register */ ++ volatile u32 *dspi_sr; /* DSPI status register */ ++ ++#if defined(SPI_DSPI_EDMA) ++ volatile void *edma_tx_buf; ++ volatile void *edma_rx_buf; ++ dma_addr_t edma_tx_buf_pa; ++ dma_addr_t edma_rx_buf_pa; ++#endif ++ ++#if defined(CONFIG_M5301x) ++ u8 *parh; ++ u8 *parl; ++#else ++ u8 *par; /* Pin assignment register */ ++#endif ++ u8 *int_icr; /* Interrupt level and priority register */ ++ u32 *int_mr; /* Interrupt mask register */ ++ void (*cs_control)(u8 cs, u8 command); ++}; ++ ++#define DSPI_CS(cs) ((1<<(cs))<<16) ++ ++/****************************************************************************/ ++ ++/* ++ * SPI local functions ++ */ ++ ++static void *next_transfer(struct driver_data *drv_data) ++{ ++ struct spi_message *msg = drv_data->cur_msg; ++ struct spi_transfer *trans = drv_data->cur_transfer; ++ ++ DBG("\n"); ++ /* Move to next transfer */ ++ if (trans->transfer_list.next != &msg->transfers) { ++ drv_data->cur_transfer = list_entry(trans->transfer_list.next, ++ struct spi_transfer, ++ transfer_list); ++ ++ if (drv_data->cur_transfer->transfer_list.next ++ == &msg->transfers) /* last transfer */ ++ drv_data->cur_transfer->cs_change = 1; ++ ++ return RUNNING_STATE; ++ } else ++ return DONE_STATE; ++} ++ ++ ++static inline int is_word_transfer(struct driver_data *drv_data) ++{ ++ return ((*(volatile u32 *)(drv_data->ctar+drv_data->cs) & DSPI_BITS_16) ++ == DSPI_BITS_8) ? 0 : 1; ++} ++ ++static inline void set_8bit_transfer_mode(struct driver_data *drv_data) ++{ ++ DBG("\n"); ++ *(volatile u32 *)(drv_data->ctar+drv_data->cs) = ++ ((*(volatile u32 *)(drv_data->ctar + drv_data->cs)) & ~DSPI_BITS) ++ | DSPI_BITS_8; ++} ++ ++static inline void set_16bit_transfer_mode(struct driver_data *drv_data) ++{ ++ DBG("\n"); ++ (*(volatile u32 *)(drv_data->ctar+drv_data->cs)) = ++ ((*(volatile u32 *)(drv_data->ctar + drv_data->cs)) & ~DSPI_BITS) ++ | DSPI_BITS_16; ++} ++ ++static unsigned char hz_to_spi_baud(int pbr, int dbr, int speed_hz) ++{ ++ int pbr_tbl[4] = {2, 3, 5, 7}; /* Valid baud rate pre-scaler values */ ++ int brs[16] = { 2, 4, 6, 8, ++ 16, 32, 64, 128, ++ 256, 512, 1024, 2048, ++ 4096, 8192, 16384, 32768 }; ++ int temp, index = 0; ++ ++ if ((pbr < 0) || (pbr > 3) || ++ (dbr < 0) || (dbr > 1)) ++ return 15; /* table indexes out of range, go slow */ ++ ++ temp = ((((MCF_CLK / 2) / pbr_tbl[pbr]) * (1 + dbr)) / speed_hz); ++ ++ while (temp > brs[index]) ++ if (index++ >= 15) ++ break; ++ ++ DBG("baud rate scaler = 0x%x - %d\n", index, brs[index]); ++ return index; ++} ++ ++static int write(struct driver_data *drv_data) ++{ ++ int tx_count = 0; ++ int tx_word = is_word_transfer(drv_data); ++ u16 d16; ++ u8 d8; ++ u32 dspi_pushr = 0; ++ int first = 1; ++#if defined(SPI_DSPI_EDMA) ++ volatile u32 *edma_wr = (volatile u32 *)(drv_data->edma_tx_buf); ++#endif ++ ++ /* If we are in word mode, but only have a single byte to transfer ++ * then switch to byte mode temporarily. Will switch back at the ++ * end of the transfer. */ ++ if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) { ++ drv_data->flags |= TRAN_STATE_WORD_ODD_NUM; ++ set_8bit_transfer_mode(drv_data); ++ tx_word = 0; ++ } ++ while ((drv_data->tx < drv_data->tx_end) ++ && (tx_count < DSPI_FIFO_SIZE)) { ++ if (tx_word) { ++ if ((drv_data->tx_end - drv_data->tx) == 1) ++ break; ++ ++ if (!(drv_data->flags & TRAN_STATE_TX_VOID)) ++ d16 = *(u16 *)drv_data->tx; ++ else ++ d16 = drv_data->void_write_data; ++ ++ dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16) | ++ DSPI_CS(drv_data->cs) | ++ MCF_DSPI_DTFR_CTAS(drv_data->cs) | ++ MCF_DSPI_DTFR_CONT; ++ ++ drv_data->tx += 2; ++ } else { ++ if (!(drv_data->flags & TRAN_STATE_TX_VOID)) ++ d8 = *(u8 *)drv_data->tx; ++ else ++ d8 = (u8)drv_data->void_write_data; ++ ++ dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8) | ++ DSPI_CS(drv_data->cs) | ++ MCF_DSPI_DTFR_CTAS(drv_data->cs) | ++ MCF_DSPI_DTFR_CONT; ++ ++ drv_data->tx++; ++ } ++#ifdef NEW_DMA_METHOD ++ if ((drv_data->cs_change) ++ && (drv_data->tx == drv_data->tx_end)) ++ dspi_pushr &= ~MCF_DSPI_DTFR_CONT; ++#else ++ if (drv_data->tx == drv_data->tx_end ++ || tx_count == DSPI_FIFO_SIZE-1) { ++ /* last transfer in the queue */ ++ dspi_pushr |= MCF_DSPI_DTFR_EOQ; ++ if ((drv_data->cs_change) ++ && (drv_data->tx == drv_data->tx_end)) ++ dspi_pushr &= ~MCF_DSPI_DTFR_CONT; ++#ifdef CONFIG_M547X_8X ++ /* EOQ gets missed if we don't delay */ ++ udelay(100); ++#endif ++ } else if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) ++ dspi_pushr |= MCF_DSPI_DTFR_EOQ; ++#endif ++#if 1 ++ /* ++ * we don't need this count in NEW_DMA_METHOD, ++ * so let is be.(2009-09-11) ++ */ ++ if (first) { ++ first = 0; ++ dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */ ++ } ++#endif ++#if defined(SPI_DSPI_EDMA) ++ *(volatile u32 *)edma_wr = dspi_pushr; ++ edma_wr++; ++#else ++ *drv_data->dspi_dtfr = dspi_pushr; ++#endif ++ tx_count++; ++ } ++ ++#if defined(SPI_DSPI_EDMA) ++#ifdef NEW_DMA_METHOD ++ ++ if (tx_count > 0) { ++ mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD, ++ /*virt_to_phys((void *)drv_data->edma_tx_buf),*/ ++ (u32)drv_data->edma_tx_buf_pa, ++ (u32)drv_data->dspi_dtfr, ++ MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT, ++ 4, /* soff */ ++ 4, /* nbytes */ ++ 0, /* slast */ ++ tx_count, /* citer */ ++ tx_count, /* biter */ ++ 0, /* doff */ ++ 0, /* dlastsga */ ++ 0, /* major_int */ ++ 1); /* disable_req */ ++ ++ mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD, ++ (u32)drv_data->dspi_drfr, ++ /*virt_to_phys((void *)drv_data->edma_rx_buf),*/ ++ (u32)drv_data->edma_rx_buf_pa, ++ MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT, ++ 0, /* soff */ ++ 4, /* nbytes */ ++ 0, /* slast */ ++ tx_count, /* citer */ ++ tx_count, /* biter */ ++ 4, /* doff */ ++ 0, /* dlastsga */ ++ 1, /* major_int */ ++ 1); /* disable_req */ ++ ++ mcf_edma_enable_transfer(DSPI_DMA_RX_TCD); ++ mcf_edma_enable_transfer(DSPI_DMA_TX_TCD); ++ } ++#else ++ if (tx_count > 0) { ++ ++ mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD, ++ virt_to_phys((void *)drv_data->edma_tx_buf), ++ (u32)drv_data->dspi_dtfr, ++ MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT, ++ 4, /* soff */ ++ 4 * tx_count, /* nbytes */ ++ 0, /* slast */ ++ 1, /* citer */ ++ 1, /* biter */ ++ 0, /* doff */ ++ 0, /* dlastsga */ ++ 0, /* major_int */ ++ 1); /* disable_req */ ++ ++ mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD, ++ (u32)drv_data->dspi_drfr, ++ virt_to_phys((void *)drv_data->edma_rx_buf), ++ MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT, ++ 0, /* soff */ ++ 4 * tx_count, /* nbytes */ ++ 0, /* slast */ ++ 1, /* citer */ ++ 1, /* biter */ ++ 4, /* doff */ ++ 0, /* dlastsga */ ++ 0, /* major_int */ ++ 1); /* disable_req */ ++ ++ mcf_edma_start_transfer(DSPI_DMA_TX_TCD); ++ } ++#endif ++#endif ++ DBG(" send %d[%d]\n", tx_count, tx_count*(tx_word + 1)); ++ return tx_count * (tx_word + 1); ++} ++ ++static int read(struct driver_data *drv_data) ++{ ++ int rx_count = 0; ++ int rx_word = is_word_transfer(drv_data); ++ u16 d; ++#if defined(SPI_DSPI_EDMA) ++ u32 *rx_edma = (u32 *) drv_data->edma_rx_buf; ++ ++ /* receive SPI data */ ++ udelay(10); ++ mcf_edma_start_transfer(DSPI_DMA_RX_TCD); ++ udelay(10); ++#endif ++ while ((drv_data->rx < drv_data->rx_end) ++ && (rx_count < DSPI_FIFO_SIZE)) { ++ ++ if (rx_word) { ++ if ((drv_data->rx_end - drv_data->rx) == 1) ++ break; ++#if defined(SPI_DSPI_EDMA) ++ d = MCF_DSPI_DRFR_RXDATA(*rx_edma); ++ rx_edma++; ++#else ++ d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr); ++#endif ++ if (!(drv_data->flags & TRAN_STATE_RX_VOID)) ++ *(u16 *)drv_data->rx = d; ++ drv_data->rx += 2; ++ ++ } else { ++#if defined(SPI_DSPI_EDMA) ++ d = MCF_DSPI_DRFR_RXDATA(*rx_edma); ++ rx_edma++; ++#else ++ d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr); ++#endif ++ if (!(drv_data->flags & TRAN_STATE_RX_VOID)) ++ *(u8 *)drv_data->rx = d; ++ drv_data->rx++; ++ } ++ rx_count++; ++ DBG("rxd=0x%x\n", d); ++ } ++ return rx_count; ++} ++ ++ ++static inline void dspi_setup_chip(struct driver_data *drv_data) ++{ ++ struct chip_data *chip = drv_data->cur_chip; ++ ++ DBG("\n"); ++ (*(volatile u32 *)drv_data->mcr) = chip->mcr_val; ++ (*(volatile u32 *)(drv_data->ctar+drv_data->cs)) = chip->ctar_val; ++#ifdef NEW_DMA_METHOD ++ /* enable DSPI DMA request function */ ++ (*(volatile u32 *)drv_data->dspi_rser) = MCF_DSPI_DRSER_TFFFE ++ | MCF_DSPI_DRSER_TFFFS | MCF_DSPI_DRSER_RFDFE ++ | MCF_DSPI_DRSER_RFDFS; ++#else ++ *drv_data->dspi_rser = MCF_DSPI_DRSER_EOQFE; ++#endif ++} ++ ++#if defined(SPI_DSPI_EDMA) ++static irqreturn_t edma_tx_handler(int channel, void *dev) ++{ ++ DBG("\n"); ++ if (channel == DSPI_DMA_TX_TCD) ++ mcf_edma_stop_transfer(DSPI_DMA_TX_TCD); ++ return IRQ_HANDLED; ++} ++ ++static struct driver_data *dspi_drv_data; ++ ++static irqreturn_t edma_rx_handler(int channel, void *dev) ++{ ++ struct driver_data *drv_data = dspi_drv_data; ++#if 1 ++ int rx_count = 0; ++ int rx_word = is_word_transfer(drv_data); ++ u16 d; ++ volatile u32 *rx_edma = (volatile u32 *) drv_data->edma_rx_buf; ++ struct spi_message *msg = drv_data->cur_msg; ++#endif ++ DBG("\n"); ++ if (channel == DSPI_DMA_RX_TCD) { ++ mcf_edma_stop_transfer(DSPI_DMA_TX_TCD); ++ mcf_edma_stop_transfer(DSPI_DMA_RX_TCD); ++ } ++ ++#if 1 ++ if (!(drv_data->flags & TRAN_STATE_RX_VOID)) { ++ while ((drv_data->rx < drv_data->rx_end) ++ && (rx_count < DSPI_FIFO_SIZE)) { ++ if (rx_word) { ++ if ((drv_data->rx_end - drv_data->rx) == 1) ++ break; ++ d = MCF_DSPI_DRFR_RXDATA(*rx_edma); ++ rx_edma++; ++ *(u16 *)drv_data->rx = d; ++ drv_data->rx += 2; ++ ++ } else { ++ d = MCF_DSPI_DRFR_RXDATA(*rx_edma); ++ rx_edma++; ++ *(u8 *)drv_data->rx = d; ++ drv_data->rx++; ++ } ++ rx_count++; ++ } ++ } else { /* rx void by upper */ ++ if ((drv_data->rx_end - drv_data->rx) > DSPI_FIFO_SIZE) ++ drv_data->rx += DSPI_FIFO_SIZE; ++ else ++ drv_data->rx = drv_data->rx_end - ++ (drv_data->tx_end - drv_data->tx); ++ } ++ if (drv_data->rx == drv_data->rx_end) { ++ /* ++ * * Finished now - fall through and schedule next ++ * * transfer tasklet ++ * */ ++ if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM) ++ set_16bit_transfer_mode(drv_data); ++ ++ msg->state = next_transfer(drv_data); ++ } else { ++ /* not finished yet - keep going */ ++ msg->actual_length += write(drv_data); ++ ++ return IRQ_HANDLED; ++ } ++ ++#endif ++ tasklet_schedule(&drv_data->pump_transfers); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++static irqreturn_t dspi_interrupt(int irq, void *dev_id) ++{ ++ struct driver_data *drv_data = (struct driver_data *)dev_id; ++ struct spi_message *msg = drv_data->cur_msg; ++ ++ /* Clear all flags immediately */ ++ *drv_data->dspi_sr = MCF_DSPI_DSR_EOQF; ++ ++ if (!drv_data->cur_msg || !drv_data->cur_msg->state) { ++#if !defined(SPI_DSPI_EDMA) ++ u32 irq_status = *drv_data->dspi_sr; ++ /* if eDMA is used it happens some time (at least once)*/ ++ printk(KERN_ERR "Bad message or transfer state handler. \ ++ IRQ status = %x\n", irq_status); ++#endif ++ return IRQ_NONE; ++ } ++ ++ DBG("\n"); ++ /* ++ * Read the data into the buffer and reload and start ++ * queue with new data if not finished. If finished ++ * then setup the next transfer ++ */ ++#if defined(SPI_DSPI_EDMA) ++ mcf_edma_start_transfer(DSPI_DMA_RX_TCD); ++#endif ++ read(drv_data); ++ ++ if (drv_data->rx == drv_data->rx_end) { ++ /* ++ * Finished now - fall through and schedule next ++ * transfer tasklet ++ */ ++ if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM) ++ set_16bit_transfer_mode(drv_data); ++ ++ msg->state = next_transfer(drv_data); ++ } else { ++ /* not finished yet - keep going */ ++ msg->actual_length += write(drv_data); ++ return IRQ_HANDLED; ++ } ++ ++ tasklet_schedule(&drv_data->pump_transfers); ++ ++ return IRQ_HANDLED; ++} ++ ++/* caller already set message->status; dma and pio irqs are blocked */ ++static void giveback(struct driver_data *drv_data) ++{ ++ struct spi_transfer *last_transfer; ++ unsigned long flags; ++ struct spi_message *msg; ++ DBG("\n"); ++ ++ spin_lock_irqsave(&drv_data->lock, flags); ++ msg = drv_data->cur_msg; ++ drv_data->cur_msg = NULL; ++ drv_data->cur_transfer = NULL; ++ drv_data->cur_chip = NULL; ++ queue_work(drv_data->workqueue, &drv_data->pump_messages); ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ ++ last_transfer = list_entry(msg->transfers.prev, ++ struct spi_transfer, transfer_list); ++ ++ if (!last_transfer->cs_change) ++ drv_data->cs_control(drv_data->cs, QSPI_CS_DROP); ++ ++ msg->state = NULL; ++ if (msg->complete) ++ msg->complete(msg->context); ++} ++ ++ ++static void pump_transfers(unsigned long data) ++{ ++ struct driver_data *drv_data = (struct driver_data *)data; ++ struct spi_message *message = NULL; ++ struct spi_transfer *transfer = NULL; ++ struct spi_transfer *previous = NULL; ++ struct chip_data *chip = NULL; ++ unsigned long flags; ++#if 0 ++ int rx_count = 0; ++ int rx_word = is_word_transfer(drv_data); ++ u16 d; ++ volatile u32 *rx_edma = (volatile u32 *) drv_data->edma_rx_buf; ++ struct spi_message *msg = drv_data->cur_msg; ++#endif ++ DBG("\n"); ++ ++#if 0 ++ if (!first_in_transfer) { ++ if (!(drv_data->flags & TRAN_STATE_RX_VOID)) { ++ while ((drv_data->rx < drv_data->rx_end) ++ && (rx_count < DSPI_FIFO_SIZE)) { ++ if (rx_word) { ++ if ((drv_data->rx_end - drv_data->rx) ++ == 1) ++ break; ++ d = MCF_DSPI_DRFR_RXDATA(*rx_edma); ++ rx_edma++; ++ *(u16 *)drv_data->rx = d; ++ drv_data->rx += 2; ++ ++ } else { ++ d = MCF_DSPI_DRFR_RXDATA(*rx_edma); ++ rx_edma++; ++ *(u8 *)drv_data->rx = d; ++ drv_data->rx++; ++ } ++ rx_count++; ++ } ++ } else { /* rx void by upper */ ++ if ((drv_data->rx_end - drv_data->rx) > DSPI_FIFO_SIZE) ++ drv_data->rx += DSPI_FIFO_SIZE; ++ else ++ drv_data->rx = drv_data->rx_end - ++ (drv_data->tx_end - drv_data->tx); ++ } ++ if (drv_data->rx == drv_data->rx_end) { ++ /* ++ * * Finished now - fall through and schedule next ++ * * transfer tasklet ++ * */ ++ if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM) ++ set_16bit_transfer_mode(drv_data); ++ ++ msg->state = next_transfer(drv_data); ++ } else { ++ /* not finished yet - keep going */ ++ local_irq_save(flags); ++ msg->actual_length += write(drv_data); ++ local_irq_restore(flags); ++ return; ++ } ++ } else { ++ first_in_transfer = 0; ++ } ++#endif ++ ++ ++ /* Get current state information */ ++ message = drv_data->cur_msg; ++ transfer = drv_data->cur_transfer; ++ chip = drv_data->cur_chip; ++ ++ /* Handle for abort */ ++ if (message->state == ERROR_STATE) { ++ message->status = -EIO; ++ giveback(drv_data); ++ return; ++ } ++ ++ /* Handle end of message */ ++ if (message->state == DONE_STATE) { ++ message->status = 0; ++ giveback(drv_data); ++ return; ++ } ++#if 1 ++ drv_data->cs = message->spi->chip_select; ++ drv_data->cs_change = transfer->cs_change; ++ drv_data->void_write_data = chip->void_write_data; ++#endif ++ ++ if (message->state == START_STATE) { ++#if 0 ++ drv_data->cs = message->spi->chip_select; ++ drv_data->cs_change = transfer->cs_change; ++ drv_data->void_write_data = chip->void_write_data; ++#endif ++ ++ dspi_setup_chip(drv_data); ++ ++ if (drv_data->cs_control) ++ drv_data->cs_control(message->spi->chip_select, ++ QSPI_CS_ASSERT); ++ } ++ ++ /* Delay if requested at end of transfer*/ ++ if (message->state == RUNNING_STATE) { ++ previous = list_entry(transfer->transfer_list.prev, ++ struct spi_transfer, ++ transfer_list); ++ ++ if (drv_data->cs_control && transfer->cs_change) ++ drv_data->cs_control(message->spi->chip_select, ++ QSPI_CS_DROP); ++ ++ if (previous->delay_usecs) ++ udelay(previous->delay_usecs); ++ ++ if (drv_data->cs_control && transfer->cs_change) ++ drv_data->cs_control(message->spi->chip_select, ++ QSPI_CS_ASSERT); ++ } ++ ++ drv_data->flags = 0; ++ drv_data->tx = (void *)transfer->tx_buf; ++ drv_data->tx_end = drv_data->tx + transfer->len; ++ drv_data->rx = transfer->rx_buf; ++ drv_data->rx_end = drv_data->rx + transfer->len; ++ ++ if (!drv_data->rx) ++ drv_data->flags |= TRAN_STATE_RX_VOID; ++ ++ if (!drv_data->tx) ++ drv_data->flags |= TRAN_STATE_TX_VOID; ++ ++#if 0 ++ drv_data->cs = message->spi->chip_select; ++ drv_data->cs_change = transfer->cs_change; ++ drv_data->void_write_data = chip->void_write_data; ++#endif ++ if (transfer->speed_hz) { ++ *(drv_data->ctar + drv_data->cs) = \ ++ ((chip->ctar_val & ~0xF) | \ ++ hz_to_spi_baud(chip->ctar.pbr, \ ++ chip->ctar.dbr, \ ++ transfer->speed_hz)); ++ } ++ ++ message->state = RUNNING_STATE; ++ ++ /* Go baby, go */ ++ local_irq_save(flags); ++ message->actual_length += write(drv_data); ++ local_irq_restore(flags); ++} ++ ++ ++static void pump_messages(struct work_struct *work) ++{ ++ struct driver_data *drv_data; ++ unsigned long flags; ++ DBG("\n"); ++ ++ drv_data = container_of(work, struct driver_data, pump_messages); ++ ++ /* Lock queue and check for queue work */ ++ spin_lock_irqsave(&drv_data->lock, flags); ++ if (list_empty(&drv_data->queue) ++ || drv_data->run == QUEUE_STOPPED) { ++ drv_data->busy = 0; ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ return; ++ } ++ ++ /* Make sure we are not already running a message */ ++ if (drv_data->cur_msg) { ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ return; ++ } ++ ++ /* Extract head of queue */ ++ drv_data->cur_msg = list_entry(drv_data->queue.next, ++ struct spi_message, queue); ++ list_del_init(&drv_data->cur_msg->queue); ++ ++ /* Initial message state*/ ++ drv_data->cur_msg->state = START_STATE; ++ drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, ++ struct spi_transfer, ++ transfer_list); ++ ++ if (drv_data->cur_transfer->transfer_list.next ++ == &drv_data->cur_msg->transfers) ++ drv_data->cur_transfer->cs_change = 1; /* last */ ++ ++#ifdef NEW_DMA_METHOD ++ mcf_edma_stop_transfer(DSPI_DMA_TX_TCD); ++ mcf_edma_stop_transfer(DSPI_DMA_RX_TCD); ++ first_in_transfer = 1; ++#endif ++ /* Setup the SPI Registers using the per chip configuration */ ++ drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); ++ ++ /* Mark as busy and launch transfers */ ++ tasklet_schedule(&drv_data->pump_transfers); ++ ++ drv_data->busy = 1; ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++} ++ ++/****************************************************************************/ ++ ++/* ++ * SPI master implementation ++ */ ++ ++static int transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct driver_data *drv_data = spi_master_get_devdata(spi->master); ++ unsigned long flags; ++ ++ DBG("\n"); ++ spin_lock_irqsave(&drv_data->lock, flags); ++ ++ if (drv_data->run == QUEUE_STOPPED) { ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ return -ESHUTDOWN; ++ } ++ ++ msg->actual_length = 0; ++ msg->status = -EINPROGRESS; ++ msg->state = START_STATE; ++ ++ list_add_tail(&msg->queue, &drv_data->queue); ++ ++ if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) ++ queue_work(drv_data->workqueue, &drv_data->pump_messages); ++ ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ ++ return 0; ++} ++ ++ ++static int setup(struct spi_device *spi) ++{ ++ struct chip_data *chip; ++ struct coldfire_dspi_chip *chip_info ++ = (struct coldfire_dspi_chip *)spi->controller_data; ++ DBG("\n"); ++ ++ /* Only alloc on first setup */ ++ chip = spi_get_ctldata(spi); ++ if (chip == NULL) { ++ chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL); ++ if (!chip) ++ return -ENOMEM; ++ spi->mode = chip_info->mode; ++ spi->bits_per_word = chip_info->bits_per_word; ++ } ++ ++ chip->mcr.master = 1; ++ chip->mcr.cont_scke = 0; ++ chip->mcr.dconf = 0; ++ chip->mcr.frz = 0; ++ chip->mcr.mtfe = 0; ++ chip->mcr.pcsse = 0; ++ chip->mcr.rooe = 0; ++ chip->mcr.pcsis = 0xFF; ++ chip->mcr.reserved15 = 0; ++ chip->mcr.mdis = 0; ++ chip->mcr.dis_tx = 0; ++ chip->mcr.dis_rxf = 0; ++ chip->mcr.clr_tx = 1; ++ chip->mcr.clr_rxf = 1; ++ chip->mcr.smpl_pt = 0; ++ chip->mcr.reserved71 = 0; ++ chip->mcr.halt = 0; ++ ++ if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { ++ chip->ctar.fmsz = spi->bits_per_word-1; ++ } else { ++ printk(KERN_ERR "Invalid wordsize\n"); ++ kfree(chip); ++ return -ENODEV; ++ } ++ ++ chip->void_write_data = chip_info->void_write_data; ++ ++ if (spi->max_speed_hz != 0) ++ chip_info->br = hz_to_spi_baud(chip_info->pbr, chip_info->dbr, \ ++ spi->max_speed_hz); ++ ++ chip->ctar.cpha = (spi->mode & SPI_CPHA) ? 1 : 0; ++ chip->ctar.cpol = (spi->mode & SPI_CPOL) ? 1 : 0; ++ chip->ctar.lsbfe = (spi->mode & SPI_LSB_FIRST) ? 1 : 0; ++ chip->ctar.dbr = chip_info->dbr; ++ chip->ctar.pbr = chip_info->pbr; ++ chip->ctar.br = chip_info->br; ++ chip->ctar.pcssck = chip_info->pcssck; ++ chip->ctar.pasc = chip_info->pasc; ++ chip->ctar.pdt = chip_info->pdt; ++ chip->ctar.cssck = chip_info->cssck; ++ chip->ctar.asc = chip_info->asc; ++ chip->ctar.dt = chip_info->dt; ++ ++ spi_set_ctldata(spi, chip); ++ ++ return 0; ++} ++ ++static int init_queue(struct driver_data *drv_data) ++{ ++ INIT_LIST_HEAD(&drv_data->queue); ++ spin_lock_init(&drv_data->lock); ++ ++ drv_data->run = QUEUE_STOPPED; ++ drv_data->busy = 0; ++ ++ tasklet_init(&drv_data->pump_transfers, ++ pump_transfers, (unsigned long)drv_data); ++ ++ INIT_WORK(&drv_data->pump_messages, pump_messages); ++ ++ drv_data->workqueue = create_singlethread_workqueue( ++ dev_name(drv_data->master->dev.parent)); ++ if (drv_data->workqueue == NULL) ++ return -EBUSY; ++ ++ return 0; ++} ++ ++static int start_queue(struct driver_data *drv_data) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&drv_data->lock, flags); ++ ++ if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ return -EBUSY; ++ } ++ ++ drv_data->run = QUEUE_RUNNING; ++ drv_data->cur_msg = NULL; ++ drv_data->cur_transfer = NULL; ++ drv_data->cur_chip = NULL; ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ ++ queue_work(drv_data->workqueue, &drv_data->pump_messages); ++ ++ return 0; ++} ++ ++static int stop_queue(struct driver_data *drv_data) ++{ ++ unsigned long flags; ++ unsigned limit = 500; ++ int status = 0; ++ ++ spin_lock_irqsave(&drv_data->lock, flags); ++ ++ /* This is a bit lame, but is optimized for the common execution path. ++ * A wait_queue on the drv_data->busy could be used, but then the common ++ * execution path (pump_messages) would be required to call wake_up or ++ * friends on every SPI message. Do this instead */ ++ drv_data->run = QUEUE_STOPPED; ++ while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ msleep(20); ++ spin_lock_irqsave(&drv_data->lock, flags); ++ } ++ ++ if (!list_empty(&drv_data->queue) || drv_data->busy) ++ status = -EBUSY; ++ ++ spin_unlock_irqrestore(&drv_data->lock, flags); ++ ++ return status; ++} ++ ++static int destroy_queue(struct driver_data *drv_data) ++{ ++ int status; ++ ++ status = stop_queue(drv_data); ++ if (status != 0) ++ return status; ++ ++ destroy_workqueue(drv_data->workqueue); ++ ++ return 0; ++} ++ ++ ++static void cleanup(struct spi_device *spi) ++{ ++ struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); ++ ++ dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", ++ spi->master->bus_num, spi->chip_select); ++ ++ kfree(chip); ++} ++ ++ ++/****************************************************************************/ ++ ++/* ++ * Generic Device driver routines and interface implementation ++ */ ++ ++static int coldfire_spi_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct coldfire_spi_master *platform_info; ++ struct spi_master *master; ++ struct driver_data *drv_data = 0; ++ struct resource *memory_resource; ++ int irq; ++ int status = 0; ++ int i; ++ ++ platform_info = (struct coldfire_spi_master *)dev->platform_data; ++ ++ master = spi_alloc_master(dev, sizeof(struct driver_data)); ++ if (!master) ++ return -ENOMEM; ++ ++ drv_data = spi_master_get_devdata(master); ++ drv_data->master = master; ++ ++ INIT_LIST_HEAD(&drv_data->queue); ++ spin_lock_init(&drv_data->lock); ++ ++ master->bus_num = platform_info->bus_num; ++ master->num_chipselect = platform_info->num_chipselect; ++ master->cleanup = cleanup; ++ master->setup = setup; ++ master->transfer = transfer; ++ ++ drv_data->cs_control = platform_info->cs_control; ++ if (drv_data->cs_control) ++ for (i = 0; i < master->num_chipselect; i++) ++ drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP); ++ ++ /* Setup register addresses */ ++ memory_resource = platform_get_resource_byname(pdev, ++ IORESOURCE_MEM, "spi-module"); ++ if (!memory_resource) { ++ dev_dbg(dev, "can not find platform module memory\n"); ++ goto out_error_master_alloc; ++ } ++ ++#if defined(SPI_DSPI_EDMA) ++ drv_data->edma_tx_buf = (volatile void *)dma_alloc_coherent(NULL, ++ EDMA_BUFSIZE_KMALLOC, ++ &drv_data->edma_tx_buf_pa, ++ GFP_DMA); ++ if (!drv_data->edma_tx_buf) { ++ dev_dbg(dev, "cannot allocate eDMA TX memory\n"); ++ goto out_error_master_alloc; ++ } ++ drv_data->edma_rx_buf = (volatile void *)dma_alloc_coherent(NULL, ++ EDMA_BUFSIZE_KMALLOC, ++ &drv_data->edma_rx_buf_pa, ++ GFP_DMA); ++ if (!drv_data->edma_rx_buf) { ++ dma_free_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \ ++ (void *)drv_data->edma_tx_buf, ++ drv_data->edma_tx_buf_pa); ++ dev_dbg(dev, "cannot allocate eDMA RX memory\n"); ++ goto out_error_master_alloc; ++ } ++ printk(KERN_INFO "Coldfire DSPI DMA addr: Tx-0x%p[0x%x]," ++ " Rx-0x%p[0x%x]\n", ++ drv_data->edma_tx_buf, drv_data->edma_tx_buf_pa, ++ drv_data->edma_rx_buf, drv_data->edma_rx_buf_pa); ++#endif ++#if defined(CONFIG_DSPI0) ++ drv_data->mcr = (volatile u32 *)&MCF_DSPI_DMCR; ++ drv_data->ctar = (volatile u32 *)&MCF_DSPI_DCTAR0; ++ drv_data->dspi_sr = (volatile u32 *)&MCF_DSPI_DSR; ++ drv_data->dspi_rser = (volatile u32 *)&MCF_DSPI_DRSER; ++ drv_data->dspi_dtfr = (volatile u32 *)&MCF_DSPI_DTFR; ++ drv_data->dspi_drfr = (volatile u32 *)&MCF_DSPI_DRFR; ++#elif defined(CONFIG_DSPI1) ++ drv_data->mcr = (volatile u32 *)&MCF_DSPI1_DMCR; ++ drv_data->ctar = (volatile u32 *)&MCF_DSPI1_DCTAR0; ++ drv_data->dspi_sr = (volatile u32 *)&MCF_DSPI1_DSR; ++ drv_data->dspi_rser = (volatile u32 *)&MCF_DSPI1_DRSER; ++ drv_data->dspi_dtfr = (volatile u32 *)&MCF_DSPI1_DTFR; ++ drv_data->dspi_drfr = (volatile u32 *)&MCF_DSPI1_DRFR; ++#else ++ drv_data->mcr = (volatile u32 *)&MCF_DSPI_DMCR; ++ drv_data->ctar = (volatile u32 *)&MCF_DSPI_DCTAR0; ++ drv_data->dspi_sr = (volatile u32 *)&MCF_DSPI_DSR; ++ drv_data->dspi_rser = (volatile u32 *)&MCF_DSPI_DRSER; ++ drv_data->dspi_dtfr = (volatile u32 *)&MCF_DSPI_DTFR; ++ drv_data->dspi_drfr = (volatile u32 *)&MCF_DSPI_DRFR; ++#endif ++ memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "spi-par"); ++ if (!memory_resource) { ++ dev_dbg(dev, "No spi-par memory\n"); ++ goto out_error_master_alloc; ++ } ++#ifdef CONFIG_M5301x ++ drv_data->parh = (void *)memory_resource->start; ++ drv_data->parl = (void *)memory_resource->end; ++#elif defined(CONFIG_M5441X) ++ /* This configuration has been set at arch scource*/ ++#else ++ drv_data->par = (void *)memory_resource->start; ++#endif ++ ++ memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "spi-int-level"); ++ if (!memory_resource) { ++ dev_dbg(dev, "No spi-int-level memory\n"); ++ goto out_error_master_alloc; ++ } ++ drv_data->int_icr = (void *)memory_resource->start; ++ ++ memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "spi-int-mask"); ++ if (!memory_resource) { ++ dev_dbg(dev, "No spi-int-mask memory\n"); ++ goto out_error_master_alloc; ++ } ++ drv_data->int_mr = (void *)memory_resource->start; ++#ifndef NEW_DMA_METHOD ++ /* ++ * PIO mode ++ */ ++ if (platform_info->irq_list) { ++ /* multiple IRQs */ ++ int *irqlist = platform_info->irq_list; ++ while ((irq = *irqlist++)) { ++ int off = *irqlist++; ++ int lvl = *irqlist++; ++ int msk = *irqlist++; ++ status = request_irq(irq, dspi_interrupt, IRQF_DISABLED, ++ pdev->name, drv_data); ++ if (status < 0) { ++ dev_err(&pdev->dev, ++ "Unable to attach ColdFire DSPI interrupt\n"); ++ goto out_error_master_alloc; ++ } ++ ++ if (lvl) ++ *(drv_data->int_icr + off) = lvl; ++ ++ if (msk) ++ *drv_data->int_mr &= ~msk; ++ } ++ } else { ++ irq = platform_info->irq_vector; ++ ++ status = request_irq(platform_info->irq_vector, dspi_interrupt, ++ IRQF_DISABLED, pdev->name, drv_data); ++ if (status < 0) { ++ dev_err(&pdev->dev, ++ "Unable to attach ColdFire DSPI interrupt\n"); ++ goto out_error_master_alloc; ++ } ++ ++ *drv_data->int_icr = platform_info->irq_lp; ++ *drv_data->int_mr &= ~platform_info->irq_mask; ++ } ++#endif ++ /* Now that we have all the addresses etc. Let's set it up */ ++#ifdef CONFIG_M5301x ++ *drv_data->parh = (u8) (platform_info->par_val16 >> 8); ++ *drv_data->parl = (u8) (platform_info->par_val16 & 0xff); ++#elif defined(CONFIG_M5441X) ++ /* This configuration has been set at arch source */ ++#else ++ *drv_data->par = platform_info->par_val; ++#endif ++ ++ /* Initial and start queue */ ++ status = init_queue(drv_data); ++ if (status != 0) { ++ dev_err(&pdev->dev, "Problem initializing DSPI queue\n"); ++ goto out_error_irq_alloc; ++ } ++ status = start_queue(drv_data); ++ if (status != 0) { ++ dev_err(&pdev->dev, "Problem starting DSPI queue\n"); ++ goto out_error_irq_alloc; ++ } ++ ++#if defined(SPI_DSPI_EDMA) ++ DBG("MCF edma request channel for SPI\n"); ++ ++ if (mcf_edma_request_channel(DSPI_DMA_TX_TCD, ++ edma_tx_handler, ++ NULL, ++ 0x00, ++ pdev, ++ NULL, /* spinlock */ ++ DRIVER_NAME) < 0){ ++ dev_err(&pdev->dev, "eDMA transmit channel request\n"); ++ status = -EINVAL; ++ goto out_error_queue_alloc; ++ } ++/* ++ * we only need RX eDMA interrupt to sync a spi transfer, ++ * the Tx eDMA interrupt can be ignored, this is determined ++ * by SPI communicate machnisim, i.e, is half duplex mode, that is ++ * whether read or write, we need write data out to get we wanted. ++ */ ++ if (mcf_edma_request_channel(DSPI_DMA_RX_TCD, ++ edma_rx_handler, ++ NULL, ++ 0x06, ++ pdev, ++ NULL, /* spinlock */ ++ DRIVER_NAME) < 0){ ++ dev_err(&pdev->dev, "eDAM receive channel request\n"); ++ status = -EINVAL; ++ mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev); ++ goto out_error_queue_alloc; ++ } ++ ++ dspi_drv_data = drv_data; ++#endif ++ ++ /* Register with the SPI framework */ ++ platform_set_drvdata(pdev, drv_data); ++ status = spi_register_master(master); ++ if (status != 0) { ++ dev_err(&pdev->dev, "Problem registering DSPI master\n"); ++ status = -EINVAL; ++ goto out_error_queue_alloc; ++ } ++ ++#ifdef NEW_DMA_METHOD ++ printk(KERN_INFO "Coldfire DSPI: Using Highspeed eDMA transfer method!\n"); ++#endif ++ printk(KERN_INFO "DSPI: Coldfire master initialized\n"); ++ return status; ++ ++out_error_queue_alloc: ++ destroy_queue(drv_data); ++ ++out_error_irq_alloc: ++ free_irq(platform_info->irq_vector, drv_data); ++ ++out_error_master_alloc: ++ spi_master_put(master); ++ return status; ++ ++} ++ ++static int coldfire_spi_remove(struct platform_device *pdev) ++{ ++ struct driver_data *drv_data = platform_get_drvdata(pdev); ++ int irq; ++ int status = 0; ++ ++ if (!drv_data) ++ return 0; ++ ++#if defined(SPI_DSPI_EDMA) ++ mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev); ++ mcf_edma_free_channel(DSPI_DMA_RX_TCD, pdev); ++#endif ++ ++ /* Remove the queue */ ++ status = destroy_queue(drv_data); ++ if (status != 0) ++ return status; ++ ++ /* Release IRQ */ ++ irq = platform_get_irq(pdev, 0); ++ if (irq >= 0) ++ free_irq(irq, drv_data); ++ ++ /* Disconnect from the SPI framework */ ++ spi_unregister_master(drv_data->master); ++ ++ /* Prevent double remove */ ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++static void coldfire_spi_shutdown(struct platform_device *pdev) ++{ ++ int status = coldfire_spi_remove(pdev); ++ ++ if (status != 0) ++ dev_err(&pdev->dev, "shutdown failed with %d\n", status); ++} ++ ++ ++#ifdef CONFIG_PM ++static int suspend_devices(struct device *dev, void *pm_message) ++{ ++ pm_message_t *state = pm_message; ++ ++ if (dev->power.power_state.event != state->event) { ++ dev_warn(dev, "pm state does not match request\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static int coldfire_spi_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ struct driver_data *drv_data = platform_get_drvdata(pdev); ++ int status = 0; ++ ++ /* Check all childern for current power state */ ++ if (device_for_each_child(&pdev->dev, ++ &state, suspend_devices) != 0) { ++ dev_warn(&pdev->dev, "suspend aborted\n"); ++ return -1; ++ } ++ ++ status = stop_queue(drv_data); ++ if (status != 0) ++ return status; ++ ++ return 0; ++} ++ ++static int coldfire_spi_resume(struct platform_device *pdev) ++{ ++ struct driver_data *drv_data = platform_get_drvdata(pdev); ++ int status = 0; ++ ++ /* Start the queue running */ ++ status = start_queue(drv_data); ++ if (status != 0) { ++ dev_err(&pdev->dev, "problem starting queue (%d)\n", status); ++ return status; ++ } ++ ++ return 0; ++} ++#else ++#define coldfire_spi_suspend NULL ++#define coldfire_spi_resume NULL ++#endif /* CONFIG_PM */ ++ ++static struct platform_driver driver = { ++ .driver = { ++ .name = "spi_coldfire", ++ .bus = &platform_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ .probe = coldfire_spi_probe, ++ .remove = __devexit_p(coldfire_spi_remove), ++ .shutdown = coldfire_spi_shutdown, ++ .suspend = coldfire_spi_suspend, ++ .resume = coldfire_spi_resume, ++}; ++ ++static int __init coldfire_spi_init(void) ++{ ++ platform_driver_register(&driver); ++ ++ return 0; ++} ++module_init(coldfire_spi_init); ++ ++static void __exit coldfire_spi_exit(void) ++{ ++ platform_driver_unregister(&driver); ++} ++module_exit(coldfire_spi_exit); ++ ++MODULE_AUTHOR("Matt Waddel"); ++MODULE_DESCRIPTION("ColdFire DSPI Contoller"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/coldfire/patches/009-Add-ALSA-driver-for-MCF5445x.patch b/target/linux/coldfire/patches/009-Add-ALSA-driver-for-MCF5445x.patch new file mode 100644 index 000000000..52c1f56a8 --- /dev/null +++ b/target/linux/coldfire/patches/009-Add-ALSA-driver-for-MCF5445x.patch @@ -0,0 +1,1869 @@ +From d37d2d880efdc0ce515df4155ddafef3835d1b7f Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:41 +0800 +Subject: [PATCH 09/52] Add ALSA driver for MCF5445x + +Add ALSA driver for MCF54451 and MCF54455. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + sound/Kconfig | 6 +- + sound/Makefile | 1 + + sound/coldfire/Kconfig | 14 + + sound/coldfire/Makefile | 6 + + sound/coldfire/coldfire-codec-spi.c | 93 ++ + sound/coldfire/snd-coldfire.c | 1664 +++++++++++++++++++++++++++++++++++ + sound/coldfire/snd-coldfire.h | 15 + + 7 files changed, 1795 insertions(+), 4 deletions(-) + create mode 100644 sound/coldfire/Kconfig + create mode 100644 sound/coldfire/Makefile + create mode 100644 sound/coldfire/coldfire-codec-spi.c + create mode 100644 sound/coldfire/snd-coldfire.c + create mode 100644 sound/coldfire/snd-coldfire.h + +--- a/sound/Kconfig ++++ b/sound/Kconfig +@@ -59,8 +59,6 @@ config SOUND_OSS_CORE_PRECLAIM + + source "sound/oss/dmasound/Kconfig" + +-if !M68K +- + menuconfig SND + tristate "Advanced Linux Sound Architecture" + help +@@ -85,6 +83,8 @@ source "sound/aoa/Kconfig" + + source "sound/arm/Kconfig" + ++source "sound/coldfire/Kconfig" ++ + source "sound/atmel/Kconfig" + + source "sound/spi/Kconfig" +@@ -121,8 +121,6 @@ source "sound/oss/Kconfig" + + endif # SOUND_PRIME + +-endif # !M68K +- + endif # SOUND + + # AC97_BUS is used from both sound and ucb1400 +--- a/sound/Makefile ++++ b/sound/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_DMASOUND) += oss/ + obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \ + sparc/ spi/ parisc/ pcmcia/ mips/ soc/ atmel/ + obj-$(CONFIG_SND_AOA) += aoa/ ++obj-$(CONFIG_SND_COLDFIRE) += coldfire/ + + # This one must be compilable even if sound is configured out + obj-$(CONFIG_AC97_BUS) += ac97_bus.o +--- /dev/null ++++ b/sound/coldfire/Kconfig +@@ -0,0 +1,14 @@ ++ ++menu "ALSA for Coldfire" ++ ++config SND_COLDFIRE ++ bool "Coldfire sound devices" ++ depends on SND ++ select SND_PCM ++ select SSIAUDIO_USE_EDMA ++ default y ++ help ++ Support for sound devices specific to Coldfire architectures. ++ ++endmenu ++ +--- /dev/null ++++ b/sound/coldfire/Makefile +@@ -0,0 +1,6 @@ ++# ++# Makefile for Coldfire ALSA ++# ++ ++obj-y += snd-coldfire.o coldfire-codec-spi.o ++ +--- /dev/null ++++ b/sound/coldfire/coldfire-codec-spi.c +@@ -0,0 +1,93 @@ ++/* ++ * linux/sound/coldfire/coldfire-codec-spi.c ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Kurt Mahan <kmahan@freescale.com> ++ * ++ * Simple SPI interface for the CODEC. ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/device.h> ++#include <linux/init.h> ++#include <linux/spi/spi.h> ++#include <linux/kernel.h> ++#include <asm/mcfsim.h> ++#include <asm/coldfire.h> ++#include <linux/delay.h> ++ ++#define MCF_CODEC_SPI_DRIVER_NAME "mcf_codec_spi" ++ ++static struct spi_device *mcf_codec_spi; ++ ++/* ++ * Write CODEC register via SPI ++ */ ++int mcf_codec_spi_write(u8 addr, u16 data) ++{ ++ u16 spi_word; ++ ++ if (mcf_codec_spi == NULL) ++ return -ENODEV; ++ ++ spi_word = ((addr & 0x7F)<<9)|(data & 0x1FF); ++ return spi_write(mcf_codec_spi, (const u8 *)&spi_word, ++ sizeof(spi_word)); ++} ++EXPORT_SYMBOL(mcf_codec_spi_write); ++ ++static int __devinit mcf_codec_spi_probe(struct spi_device *spi) ++{ ++ spi->dev.power.power_state = PMSG_ON; ++ mcf_codec_spi = spi; ++ ++ return 0; ++} ++ ++static int __devexit mcf_codec_spi_remove(struct spi_device *spi) ++{ ++ return 0; ++} ++ ++static int mcf_codec_spi_suspend(struct spi_device *spi, pm_message_t message) ++{ ++ return 0; ++} ++ ++static int mcf_codec_spi_resume(struct spi_device *spi) ++{ ++ return 0; ++} ++ ++static struct spi_driver mcf_codec_spi_driver = { ++ .driver = { ++ .name = MCF_CODEC_SPI_DRIVER_NAME, ++ .bus = &spi_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ .probe = mcf_codec_spi_probe, ++ .remove = __devexit_p(mcf_codec_spi_remove), ++ .suspend = mcf_codec_spi_suspend, ++ .resume = mcf_codec_spi_resume, ++}; ++ ++static int __init mcf_codec_spi_init(void) ++{ ++ return spi_register_driver(&mcf_codec_spi_driver); ++} ++module_init(mcf_codec_spi_init); ++ ++static void __exit mcf_codec_spi_exit(void) ++{ ++ spi_unregister_driver(&mcf_codec_spi_driver); ++} ++module_exit(mcf_codec_spi_exit); ++ ++ ++MODULE_DESCRIPTION("Coldfire Codec SPI driver"); ++MODULE_AUTHOR("Kurt Mahan, Freescale Semiconductor, Inc."); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/coldfire/snd-coldfire.c +@@ -0,0 +1,1664 @@ ++/* ++ * linux/sound/coldfire/snd-coldfire.c ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: York Sun <r58495@freescale.com> ++ * Alison Wang <b18965@freescale.com> ++ * ++ * Coldfire ALSA driver based on SSI and TLV320A ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ *************************************************************************** ++ * ++ * NOTE: This driver was tested on MCF5445x, MCF5301x, MCF5227x, MCF532x and ++ * MCF537x platforms. ++ * */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/platform_device.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/slab.h> ++#include <linux/dma-mapping.h> ++#include <linux/ioctl.h> ++#include <linux/soundcard.h> ++#include <linux/spi/spi.h> ++ ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/control.h> ++#include <linux/fs.h> ++#include <linux/delay.h> ++ ++#include <asm/mcfsim.h> ++#include <asm/coldfire.h> ++#include <asm/mcf_edma.h> ++#include "snd-coldfire.h" ++ ++#if defined(CONFIG_M5445X) ++#include <asm/mcf5445x_ssi.h> ++#endif ++ ++#define CF_ALSA_DEBUG 0 ++#if CF_ALSA_DEBUG ++#define DBG(fmt, args...) printk(KERN_INFO "[%s] " fmt , \ ++ __func__, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#define SOUND_CARD_NAME "Coldfire ALSA" ++#define MAX_BUFFER_SIZE (32*1024) ++ ++/* eDMA channel for SSI channel 0,1 TX,RX */ ++#define DMA_TX_TCD0 MCF_EDMA_CHAN_TIMER2 ++#define DMA_TX_TCD1 MCF_EDMA_CHAN_TIMER3 ++#define DMA_RX_TCD0 MCF_EDMA_CHAN_TIMER0 ++#define DMA_RX_TCD1 MCF_EDMA_CHAN_TIMER1 ++ ++#define CODEC_LEFT_IN_REG (0x00) ++#define CODEC_RIGHT_IN_REG (0x01) ++#define CODEC_LEFT_HP_VOL_REG (0x02) ++#define CODEC_RIGHT_HP_VOL_REG (0x03) ++#define CODEC_ANALOG_APATH_REG (0x04) ++#define CODEC_DIGITAL_APATH_REG (0x05) ++#define CODEC_POWER_DOWN_REG (0x06) ++#define CODEC_DIGITAL_IF_FMT_REG (0x07) ++#define CODEC_SAMPLE_RATE_REG (0x08) ++#define CODEC_DIGITAL_IF_ACT_REG (0x09) ++#define CODEC_RESET_REG (0x0f) ++ ++#define TLV320AIC23_CODEC_SAMPLE_RATE_REG (0x08) ++#define TLV320AIC23_CODEC_SAMPLERATE_REG_8KHZ (0x0C) ++#define TLV320AIC23_CODEC_SAMPLERATE_REG_11KHZ (0x0C) ++#define TLV320AIC23_CODEC_SAMPLERATE_REG_16KHZ (0x58) ++#define TLV320AIC23_CODEC_SAMPLERATE_REG_22KHZ (0x62) ++#define TLV320AIC23_CODEC_SAMPLERATE_REG_44KHZ (0x22) ++#define TLV320AIC23_CODEC_SAMPLERATE_REG_48KHZ (0x00) ++ ++#define MCF_SSI_AUDIO_IRQ_LEVEL (5) ++#define TLV320A_VOL_MAX 0x07F ++#define TLV320A_VOL_MIN 0x030 ++#define TLV320A_VOL_INIT 0x065 ++#define TLV320A_LINEIN_MAX 0x1F ++#define TLV320A_LINEIN_INIT 0x17 ++#define TLV320A_ANALOGPATH_INIT 0x11 ++ ++/* Codec settings */ ++#define MCF_SSI_AUDIO_MCLK_1 (12288000U) /*Hz*/ ++#define MCF_SSI_AUDIO_MCLK_2 (16934400U) /*Hz*/ ++#define MCF_SSI_AUDIO_MCLK_3 (14112000U) /*Hz*/ ++#define MCF_SSI_AUDIO_MCLK_4 (18432000U) /*Hz*/ ++ ++#define MCF_SSI_AUDIO_SSDIV_VALUE_1 \ ++ ((((u32)MCF_CLK*2)/MCF_SSI_AUDIO_MCLK_1)+ \ ++ (((((u32)MCF_CLK*2*10)/MCF_SSI_AUDIO_MCLK_1)%10) > 5)) ++ ++#define MCF_SSI_AUDIO_SSDIV_VALUE_2 \ ++ ((((u32)MCF_CLK*2)/MCF_SSI_AUDIO_MCLK_2)+ \ ++ (((((u32)MCF_CLK*2*10)/MCF_SSI_AUDIO_MCLK_2)%10) > 5)) ++ ++#define MCF_SSI_AUDIO_SSDIV_VALUE_3 \ ++ ((((u32)MCF_CLK*2)/MCF_SSI_AUDIO_MCLK_3)+ \ ++ (((((u32)MCF_CLK*2*10)/MCF_SSI_AUDIO_MCLK_3)%10) > 5)) ++ ++#define MCF_SSI_AUDIO_SSDIV_VALUE_4 \ ++ ((((u32)MCF_CLK*2)/MCF_SSI_AUDIO_MCLK_4)+ \ ++ (((((u32)MCF_CLK*2*10)/MCF_SSI_AUDIO_MCLK_4)%10) > 5)) ++ ++#define SNDRV_COLDFIRE_PCM_PLAYBACK_FORMATS SNDRV_PCM_FMTBIT_S16_BE ++#define SNDRV_COLDFIRE_PCM_CAPTURE_FORMATS SNDRV_PCM_FMTBIT_S16_BE ++ ++#define RXFWM 2 ++#define TXFWM 2 ++#define HW_PERIODS_BYTES_MIN 4096 ++#define HW_PERIODS_BYTES_STEP 4096 ++ ++#define INPUT_MICROPHONE 0 ++#define INPUT_LINEIN 1 ++#define NUM_TCDS 4 ++ ++static char *id; ++static struct platform_device *device; ++static int g_tx_dmaing; ++static int g_rx_dmaing; ++static unsigned char g_mastervol, g_lineinvol, g_analogpath; ++ ++/** Use 4 TCDs for scatter/gather address ++ * to setup dma chain, one TCD per period ++ * so that we don't need change them on the fly ++ */ ++ ++/** ++ * Link Descriptor ++ * ++ * must be aligned on a 32-byte boundary. ++ */ ++struct dma_tcd { ++ __be32 saddr; /* source address */ ++ __be16 attr; /* transfer attribute */ ++ __be16 soffset; /* source offset */ ++ __be32 nbytes; /* minor byte count */ ++ __be32 slast; /* last source address adjust */ ++ __be32 daddr; /* dest address */ ++ __be16 citer; /* current minor looplink, major count */ ++ __be16 doffset; /* dest offset */ ++ __be32 dlast_sga; /* last dest addr adjust, scatter/gather addr*/ ++ __be16 biter; /* begging minor looklink, major count */ ++ __be16 csr; /* control and status */ ++} __packed; ++ ++/** dma_private: p-substream DMA data ++ * ++ * The tcd[] array is first because it needs to be aligned on a 32-byte ++ * boundary, so putting it first will ensure alignment without padding the ++ * structure. ++ * ++ * @tcd[]: array of TCDs ++ */ ++struct dma_private { ++ struct dma_tcd tcd0[NUM_TCDS]; ++ struct dma_tcd tcd1[NUM_TCDS]; ++ dma_addr_t tcd_buf_phys; /* physical address of dma_private */ ++ dma_addr_t dma_buf_phys; ++ dma_addr_t dma_buf_next; ++ dma_addr_t dma_buf_end; ++ size_t period_size; ++ unsigned int num_periods; ++}; ++ ++struct tlv320a_audio_device { ++ struct spi_device *spi; ++ u32 speed; ++ u32 stereo; ++ u32 bits; ++ u32 format; ++ u8 isopen; ++ u8 dmaing; ++ u8 ssi_enabled; ++ u8 channel; ++ spinlock_t lock; ++ u8 *audio_buf; ++}; ++ ++/* chip specific define */ ++struct chip_spec { ++ struct snd_card *card; ++ struct snd_pcm *pcm; ++ struct tlv320a_audio_device *audio_device; ++ u32 offset; ++ void *mixer_data; ++}; ++ ++/* hardware definition */ ++static struct snd_pcm_hardware snd_coldfire_playback_hw = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | ++#if defined(CONFIG_MMU) ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID| ++#endif ++ SNDRV_PCM_INFO_BLOCK_TRANSFER), ++ .formats = SNDRV_COLDFIRE_PCM_PLAYBACK_FORMATS, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .channels_min = 1, ++ .channels_max = 2, ++ .buffer_bytes_max = MAX_BUFFER_SIZE, ++ .period_bytes_min = HW_PERIODS_BYTES_MIN, ++ .period_bytes_max = MAX_BUFFER_SIZE/NUM_TCDS, ++ .periods_min = NUM_TCDS, ++ .periods_max = NUM_TCDS, ++ .fifo_size = 0, ++}; ++ ++/* hardware definition */ ++static struct snd_pcm_hardware snd_coldfire_capture_hw = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | ++#if defined(CONFIG_MMU) ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID| ++#endif ++ SNDRV_PCM_INFO_BLOCK_TRANSFER), ++ .formats = SNDRV_COLDFIRE_PCM_CAPTURE_FORMATS, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .channels_min = 1, ++ .channels_max = 2, ++ .buffer_bytes_max = MAX_BUFFER_SIZE, ++ .period_bytes_min = HW_PERIODS_BYTES_MIN, ++ .period_bytes_max = MAX_BUFFER_SIZE/NUM_TCDS, ++ .periods_min = NUM_TCDS, ++ .periods_max = NUM_TCDS, ++ .fifo_size = 0, ++}; ++ ++static unsigned int rates[] = {8000, 11025, 16000, 22000, ++ 22050, 44000, 44100, 48000}; ++ ++/* hw constraints */ ++static struct snd_pcm_hw_constraint_list constraints_rates = { ++ .count = ARRAY_SIZE(rates), ++ .list = rates, ++ .mask = 0, ++}; ++ ++static inline void ssi_audio_dma_playback_start(void) ++{ ++ g_tx_dmaing = 1; ++ mcf_edma_start_transfer(DMA_TX_TCD0); ++ mcf_edma_start_transfer(DMA_TX_TCD1); ++} ++ ++static inline void ssi_audio_dma_capture_start(void) ++{ ++ g_rx_dmaing = 1; ++ mcf_edma_start_transfer(DMA_RX_TCD0); ++ mcf_edma_start_transfer(DMA_RX_TCD1); ++} ++ ++static inline void ssi_audio_dma_playback_stop(void) ++{ ++ g_tx_dmaing = 0; ++ mcf_edma_stop_transfer(DMA_TX_TCD0); ++ mcf_edma_stop_transfer(DMA_TX_TCD1); ++} ++ ++inline void ssi_audio_dma_capture_stop(void) ++{ ++ g_rx_dmaing = 0; ++ mcf_edma_stop_transfer(DMA_RX_TCD0); ++ mcf_edma_stop_transfer(DMA_RX_TCD1); ++} ++ ++/** ++ * fill_tcd_params - Fill transfer control descriptor (TCD) ++ * @base: base address of TCD ++ * @source: source address ++ * @dest: destination address ++ * @attr: attributes ++ * @soff: source offset ++ * @nbytes: number of bytes to be transfered in minor loop ++ * @slast: last source address adjustment ++ * @citer: major loop count ++ * @biter: beginning minor loop count ++ * @doff: destination offset ++ * @dlast_sga: last destination address adjustment ++ * @major_int: generate interrupt after each major loop ++ * @disable_req: disable DMA request after major loop ++ * @enable_sg: enable scatter/gather address ++ */ ++void fill_tcd_params(u32 base, u32 source, u32 dest, ++ u32 attr, u32 soff, u32 nbytes, u32 slast, ++ u32 citer, u32 biter, u32 doff, u32 dlast_sga, ++ int major_int, int disable_req, int enable_sg) ++{ ++ struct dma_tcd *tcd = (struct dma_tcd *) base; ++ ++ tcd->saddr = source; ++ tcd->attr = attr; ++ tcd->soffset = soff; ++ tcd->nbytes = nbytes; ++ tcd->slast = slast; ++ tcd->daddr = dest; ++ tcd->citer = citer & 0x7fff; ++ tcd->doffset = doff; ++ tcd->dlast_sga = dlast_sga; ++ tcd->biter = biter & 0x7fff; ++ tcd->csr = ((major_int) ? 0x2 : 0) | ++ ((disable_req) ? 0x8 : 0) | ++ ((enable_sg) ? 0x10 : 0); ++} ++ ++static int ++ssi_audio_dma_playback_config(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct dma_private *dma_private = runtime->private_data; ++ u32 size = frames_to_bytes(runtime, runtime->period_size); ++ u32 offset, soffset, daddr0, daddr1, attr, sga0, sga1; ++ u32 i, nbyte, major_loops; ++ ++ if ((runtime->channels < 1) || (runtime->channels > 2)) { ++ printk(KERN_ERR "Error on channels = %d\n", runtime->channels); ++ return -EINVAL; ++ } ++ ++ dma_private->dma_buf_phys = runtime->dma_addr; ++ dma_private->dma_buf_next = dma_private->dma_buf_phys; ++ dma_private->dma_buf_end = dma_private->dma_buf_phys + ++ runtime->periods * size; ++ ++ if (runtime->format == SNDRV_PCM_FORMAT_S16_BE) { ++ nbyte = 2 * TXFWM; ++ soffset = 2 * runtime->channels; ++ daddr0 = (u32)&MCF_SSI_TX0 + 2; ++ daddr1 = (u32)&MCF_SSI_TX1 + 2; ++ attr = MCF_EDMA_TCD_ATTR_SSIZE_16BIT | ++ MCF_EDMA_TCD_ATTR_DSIZE_16BIT; ++ } else { ++ printk(KERN_ERR "Not supported PCM format %x\n", ++ runtime->format); ++ return -EINVAL; ++ } ++ ++ major_loops = size/nbyte/runtime->channels; ++ sga0 = (u32)dma_private->tcd_buf_phys; ++ sga1 = (u32)dma_private->tcd_buf_phys + ++ 4 * sizeof(struct dma_tcd); ++ ++#if defined(CONFIG_M5301x) || defined(CONFIG_M5445X) ++ MCF_EDMA_TCD10_CSR = 0; ++ MCF_EDMA_TCD11_CSR = 0; ++#else ++ MCF_EDMA_TCD11_CSR = 0; ++ MCF_EDMA_TCD12_CSR = 0; ++#endif ++ offset = (runtime->channels - 1) * 2; ++ mcf_edma_set_tcd_params(DMA_TX_TCD0, ++ (u32)dma_private->dma_buf_next, ++ daddr0, ++ attr, ++ soffset, ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ 0, /* dest offset */ ++ sga0, ++ 1, /* major_int */ ++ 0); /* enable dma request after */ ++ ++ mcf_edma_set_tcd_params(DMA_TX_TCD1, ++ (u32)dma_private->dma_buf_next + offset, ++ daddr1, ++ attr, ++ soffset, ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ 0, /* dest offset */ ++ sga1, ++ 0, /* major_int */ ++ 0); /* enable dma request after */ ++ ++ while (!(MCF_EDMA_TCD_CSR(DMA_TX_TCD0) & MCF_EDMA_TCD_CSR_E_SG)) ++ MCF_EDMA_TCD_CSR(DMA_TX_TCD0) |= MCF_EDMA_TCD_CSR_E_SG; ++ while (!(MCF_EDMA_TCD_CSR(DMA_TX_TCD1) & MCF_EDMA_TCD_CSR_E_SG)) ++ MCF_EDMA_TCD_CSR(DMA_TX_TCD1) |= MCF_EDMA_TCD_CSR_E_SG; ++ ++ for (i = 0; i < NUM_TCDS; i++) { ++ dma_private->dma_buf_next += size; ++ if (dma_private->dma_buf_next >= dma_private->dma_buf_end) ++ dma_private->dma_buf_next = dma_private->dma_buf_phys; ++ sga0 = (u32)dma_private->tcd_buf_phys + ++ ((i+1)%NUM_TCDS) * sizeof(struct dma_tcd); ++ sga1 = (u32)dma_private->tcd_buf_phys + ++ ((i+1)%NUM_TCDS + 4) * sizeof(struct dma_tcd); ++ DBG("sga0 = 0x%x, sga1 = 0x%x.\n", sga0, sga1); ++ fill_tcd_params((u32)&dma_private->tcd0[i], ++ (u32)dma_private->dma_buf_next, ++ daddr0, ++ attr, ++ soffset, ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ 0, /* dest offset */ ++ sga0, ++ 1, /* major_int */ ++ 0, /* enable dma request after */ ++ 1); /* enable scatter/gather */ ++ ++ fill_tcd_params((u32)&dma_private->tcd1[i], ++ (u32)dma_private->dma_buf_next + offset, ++ daddr1, ++ attr, ++ soffset, ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ 0, /* dest offset */ ++ sga1, ++ 0, /* major_int */ ++ 0, /* enable dma request after */ ++ 1); /* enable scatter/gather */ ++ } ++ ++ return 0; ++} ++ ++static int ++ssi_audio_dma_capture_config(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct dma_private *dma_private = runtime->private_data; ++ u32 size = frames_to_bytes(runtime, runtime->period_size); ++ u32 offset, saddr0, saddr1, doffset, attr, sga0, sga1; ++ int i, nbyte, major_loops; ++ ++ if ((runtime->channels < 1) || (runtime->channels > 2)) { ++ printk(KERN_ERR "Error on channels = %d\n", runtime->channels); ++ return -EINVAL; ++ } ++ ++ dma_private->dma_buf_phys = runtime->dma_addr; ++ dma_private->dma_buf_next = dma_private->dma_buf_phys; ++ dma_private->dma_buf_end = dma_private->dma_buf_phys + ++ runtime->periods * size; ++ ++ switch (runtime->format) { ++ case SNDRV_PCM_FORMAT_S16_BE: ++ saddr0 = (u32)&MCF_SSI_RX0 + 2; ++ saddr1 = (u32)&MCF_SSI_RX1 + 2; ++ nbyte = 2 * RXFWM; ++ doffset = 2 * runtime->channels; ++ attr = MCF_EDMA_TCD_ATTR_SSIZE_16BIT | ++ MCF_EDMA_TCD_ATTR_DSIZE_16BIT; ++ break; ++ default: ++ printk(KERN_ERR "Not supported PCM format %x\n", ++ runtime->format); ++ return -EINVAL; ++ } ++ ++ major_loops = size/nbyte/runtime->channels; ++ sga0 = (u32)dma_private->tcd_buf_phys; ++ sga1 = (u32)dma_private->tcd_buf_phys + ++ 4 * sizeof(struct dma_tcd); ++ ++#if defined(CONFIG_M5301x) || defined(CONFIG_M5445X) ++ MCF_EDMA_TCD8_CSR = 0; ++ MCF_EDMA_TCD9_CSR = 0; ++#else ++ MCF_EDMA_TCD9_CSR = 0; ++ MCF_EDMA_TCD10_CSR = 0; ++#endif ++ offset = (runtime->channels - 1) * 2; ++ mcf_edma_set_tcd_params(DMA_RX_TCD0, ++ saddr0, ++ (u32)dma_private->dma_buf_next, ++ attr, ++ 0, /* source offset */ ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ doffset, ++ sga0, ++ 1, /* major_int */ ++ 0); /* enable dma request after */ ++ ++ mcf_edma_set_tcd_params(DMA_RX_TCD1, ++ saddr1, ++ (u32)dma_private->dma_buf_next + offset, ++ attr, ++ 0, /* source offset */ ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ doffset, ++ sga1, ++ 0, /* major_int */ ++ 0); /* enable dma request after */ ++ ++ while (!(MCF_EDMA_TCD_CSR(DMA_RX_TCD0) & MCF_EDMA_TCD_CSR_E_SG)) ++ MCF_EDMA_TCD_CSR(DMA_RX_TCD0) |= MCF_EDMA_TCD_CSR_E_SG; ++ while (!(MCF_EDMA_TCD_CSR(DMA_RX_TCD1) & MCF_EDMA_TCD_CSR_E_SG)) ++ MCF_EDMA_TCD_CSR(DMA_RX_TCD1) |= MCF_EDMA_TCD_CSR_E_SG; ++ ++ for (i = 0; i < NUM_TCDS; i++) { ++ dma_private->dma_buf_next += size; ++ if (dma_private->dma_buf_next >= dma_private->dma_buf_end) ++ dma_private->dma_buf_next = dma_private->dma_buf_phys; ++ sga0 = (u32)dma_private->tcd_buf_phys + ++ ((i+1)%NUM_TCDS) * sizeof(struct dma_tcd); ++ sga1 = (u32)dma_private->tcd_buf_phys + ++ ((i+1)%NUM_TCDS + 4) * sizeof(struct dma_tcd); ++ fill_tcd_params((u32)&dma_private->tcd0[i], ++ saddr0, ++ (u32)dma_private->dma_buf_next, ++ attr, ++ 0, /* source offset */ ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ doffset, ++ sga0, ++ 1, /* major_int */ ++ 0, /* enable dma request after */ ++ 1); /* enable scatter/gather */ ++ fill_tcd_params((u32)&dma_private->tcd1[i], ++ saddr1, ++ (u32)dma_private->dma_buf_next + offset, ++ attr, ++ 0, /* source offset */ ++ nbyte, ++ 0, /* slast */ ++ major_loops, /* citer */ ++ major_loops, /* biter */ ++ doffset, ++ sga1, ++ 0, /* major_int */ ++ 0, /* enable dma request after */ ++ 1); /* enable scatter/gather */ ++ } ++ return 0; ++} ++ ++static inline void ssi_audio_enable_ssi_playback(void) ++{ ++ MCF_SSI_CR |= MCF_SSI_CR_SSI_EN | MCF_SSI_CR_TE; ++} ++ ++static inline void ssi_audio_enable_ssi_capture(void) ++{ ++ MCF_SSI_CR |= MCF_SSI_CR_SSI_EN | MCF_SSI_CR_RE; ++} ++ ++static inline void ssi_audio_disable_ssi(void) ++{ ++ MCF_SSI_CR &= ~(MCF_SSI_CR_TE | MCF_SSI_CR_RE | MCF_SSI_CR_SSI_EN); ++} ++ ++static inline void ssi_audio_disable_ssi_playback(void) ++{ ++ MCF_SSI_CR &= ~MCF_SSI_CR_TE; ++} ++ ++static inline void ssi_audio_disable_ssi_capture(void) ++{ ++ MCF_SSI_CR &= ~MCF_SSI_CR_RE; ++} ++ ++static irqreturn_t ssi_audio_dma_playback_handler(int channel, void *dev_id) ++{ ++ struct snd_pcm_substream *substream; ++ struct snd_pcm_runtime *runtime; ++ ++ substream = (struct snd_pcm_substream *)dev_id; ++ runtime = substream->runtime; ++ ++ /* inform ALSA middle layer about transfer status */ ++ snd_pcm_period_elapsed(substream); ++ mcf_edma_confirm_interrupt_handled(DMA_TX_TCD0); ++ mcf_edma_confirm_interrupt_handled(DMA_TX_TCD1); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t ssi_audio_dma_capture_handler(int channel, void *dev_id) ++{ ++ struct snd_pcm_substream *substream; ++ struct snd_pcm_runtime *runtime; ++ ++ substream = (struct snd_pcm_substream *)dev_id; ++ runtime = substream->runtime; ++ ++ /* inform ALSA middle layer about transfer status */ ++ snd_pcm_period_elapsed(substream); ++ mcf_edma_confirm_interrupt_handled(DMA_RX_TCD0); ++ mcf_edma_confirm_interrupt_handled(DMA_RX_TCD1); ++ ++ return IRQ_HANDLED; ++} ++ ++int ssi_audio_dma_request_playback_channel(struct snd_pcm_substream *substream) ++{ ++ int err; ++ struct chip_spec *chip = snd_pcm_substream_chip(substream); ++ ++ /* request eDMA channel */ ++ err = mcf_edma_request_channel(DMA_TX_TCD0, ++ ssi_audio_dma_playback_handler, ++ NULL, ++ MCF_SSI_AUDIO_IRQ_LEVEL, ++ substream, ++ &(chip->audio_device->lock), ++ id); ++ if (err < 0) ++ return err; ++ err = mcf_edma_request_channel(DMA_TX_TCD1, ++ ssi_audio_dma_playback_handler, ++ NULL, ++ MCF_SSI_AUDIO_IRQ_LEVEL, ++ substream, ++ &(chip->audio_device->lock), ++ id); ++ return err; ++} ++ ++int ssi_audio_dma_request_capture_channel(struct snd_pcm_substream *substream) ++{ ++ int err; ++ struct chip_spec *chip = snd_pcm_substream_chip(substream); ++ ++ /* request 2 eDMA channels for two fifo */ ++ err = mcf_edma_request_channel(DMA_RX_TCD0, ++ ssi_audio_dma_capture_handler, ++ NULL, ++ MCF_SSI_AUDIO_IRQ_LEVEL, ++ substream, ++ &(chip->audio_device->lock), ++ id); ++ if (err < 0) ++ return err; ++ err = mcf_edma_request_channel(DMA_RX_TCD1, ++ ssi_audio_dma_capture_handler, ++ NULL, ++ MCF_SSI_AUDIO_IRQ_LEVEL, ++ substream, ++ &(chip->audio_device->lock), ++ id); ++ return err; ++} ++ ++static inline void ssi_audio_init_dma(void) ++{ ++ /* SSI DMA Signals mapped to DMA request */ ++ MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA; ++} ++ ++static void ssi_audio_adjust_codec_speed(struct snd_pcm_substream *substream) ++{ ++ ssi_audio_disable_ssi(); ++ ++ if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_BE) { ++ MCF_SSI_CCR = MCF_SSI_CCR_WL(7) | /* 16 bit word length */ ++ MCF_SSI_CCR_DC(1); /* Frame rate divider */ ++ } ++ ++ switch (substream->runtime->rate) { ++ case 8000: ++#if defined(CONFIG_M532x) || defined(CONFIG_M537x) ++ MCF_CCM_CDR = (MCF_CCM_CDR | MCF_CCM_CDR_SSIDIV(0x20)) ++ | MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_1); ++#else ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0xFF)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_1); ++#endif ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(11); ++ mcf_codec_spi_write(TLV320AIC23_CODEC_SAMPLE_RATE_REG, ++ TLV320AIC23_CODEC_SAMPLERATE_REG_8KHZ); ++ break; ++ case 11000: ++ case 11025: ++#if defined(CONFIG_M532x) || defined(CONFIG_M537x) ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0x3F)) | ++ MCF_CCM_CDR_SSIDIV(0x2B); ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(11); ++#else ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0xFF)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_3); ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(9); ++#endif ++ mcf_codec_spi_write(TLV320AIC23_CODEC_SAMPLE_RATE_REG, ++ TLV320AIC23_CODEC_SAMPLERATE_REG_11KHZ); ++ break; ++ case 16000: ++#if defined(CONFIG_M532x) || defined(CONFIG_M537x) ++ MCF_CCM_CDR = (MCF_CCM_CDR | MCF_CCM_CDR_SSIDIV(0x20)) ++ | MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_1); ++#else ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0xFF)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_1); ++#endif ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(5); ++ mcf_codec_spi_write(TLV320AIC23_CODEC_SAMPLE_RATE_REG, ++ TLV320AIC23_CODEC_SAMPLERATE_REG_16KHZ); ++ break; ++ case 22000: ++ case 22050: ++#if defined(CONFIG_M532x) || defined(CONFIG_M537x) ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0x3F)) | ++ MCF_CCM_CDR_SSIDIV(0x2B); ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(5); ++#else ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0xFF)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_3); ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(4); ++#endif ++ mcf_codec_spi_write(TLV320AIC23_CODEC_SAMPLE_RATE_REG, ++ TLV320AIC23_CODEC_SAMPLERATE_REG_22KHZ); ++ break; ++ case 48000: ++#if defined(CONFIG_M532x) || defined(CONFIG_M537x) ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0x3F)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_4); ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(3); ++#else ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0xFF)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_1); ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(1); ++#endif ++ mcf_codec_spi_write(TLV320AIC23_CODEC_SAMPLE_RATE_REG, ++ TLV320AIC23_CODEC_SAMPLERATE_REG_48KHZ); ++ break; ++ case 44000: ++ case 44100: ++ default: ++#if defined(CONFIG_M532x) || defined(CONFIG_M537x) ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0x3F)) | ++ MCF_CCM_CDR_SSIDIV(0x2B); ++#else ++ MCF_CCM_CDR = (MCF_CCM_CDR & ~MCF_CCM_CDR_SSIDIV(0xFF)) | ++ MCF_CCM_CDR_SSIDIV(MCF_SSI_AUDIO_SSDIV_VALUE_2); ++#endif ++ MCF_SSI_CCR |= MCF_SSI_CCR_PM(2); ++ mcf_codec_spi_write(TLV320AIC23_CODEC_SAMPLE_RATE_REG, ++ TLV320AIC23_CODEC_SAMPLERATE_REG_44KHZ); ++ break; ++ } ++ DBG("MCF_CCM_CDR = 0x%x, MCF_SSI_CCR = 0x%x.\n", ++ MCF_CCM_CDR, MCF_SSI_CCR); ++} ++ ++static void ssi_audio_codec_reset(void) ++{ ++ mcf_codec_spi_write(CODEC_RESET_REG, 0); /* reset the audio chip */ ++ udelay(2500); /* wait for reset */ ++} ++ ++static void ++ssi_audio_init_codec_for_playback(struct snd_pcm_substream *substream) ++{ ++ mcf_codec_spi_write(CODEC_LEFT_IN_REG, g_lineinvol); ++ mcf_codec_spi_write(CODEC_RIGHT_IN_REG, g_lineinvol); ++ mcf_codec_spi_write(CODEC_POWER_DOWN_REG, 0x060); ++ mcf_codec_spi_write(CODEC_DIGITAL_IF_FMT_REG, 0x02); ++ mcf_codec_spi_write(CODEC_DIGITAL_APATH_REG, 0x006); ++ mcf_codec_spi_write(CODEC_DIGITAL_IF_ACT_REG, 0x001); ++ mcf_codec_spi_write(CODEC_ANALOG_APATH_REG, g_analogpath); ++ mcf_codec_spi_write(CODEC_LEFT_HP_VOL_REG, g_mastervol); ++ mcf_codec_spi_write(CODEC_RIGHT_HP_VOL_REG, g_mastervol); ++} ++ ++static void ++ssi_audio_init_codec_for_capture(struct snd_pcm_substream *substream) ++{ ++ mcf_codec_spi_write(CODEC_LEFT_IN_REG, g_lineinvol); ++ mcf_codec_spi_write(CODEC_RIGHT_IN_REG, g_lineinvol); ++ mcf_codec_spi_write(CODEC_POWER_DOWN_REG, 0x060); ++ mcf_codec_spi_write(CODEC_DIGITAL_IF_FMT_REG, 0x02); ++ mcf_codec_spi_write(CODEC_DIGITAL_APATH_REG, 0x006); ++ mcf_codec_spi_write(CODEC_DIGITAL_IF_ACT_REG, 0x001); ++ mcf_codec_spi_write(CODEC_ANALOG_APATH_REG, g_analogpath); ++ mcf_codec_spi_write(CODEC_LEFT_HP_VOL_REG, g_mastervol); ++ mcf_codec_spi_write(CODEC_RIGHT_HP_VOL_REG, g_mastervol); ++} ++ ++static void ssi_audio_chip_init(void) ++{ ++ int chip_initialized = 0; ++ if (chip_initialized == 1) ++ return; ++ ++ ssi_audio_init_dma(); ++ /* Enable the SSI pins */ ++#if defined(CONFIG_M5227x) ++ MCF_GPIO_PAR_UART = (MCF_GPIO_PAR_UART ++ &~MCF_GPIO_PAR_UART_PAR_U1TXD(0xF) ++ &~MCF_GPIO_PAR_UART_PAR_U1RXD(0xF) ++ &~MCF_GPIO_PAR_UART_PAR_U1RTS(0xF) ++ &~MCF_GPIO_PAR_UART_PAR_U1CTS(0xF)) ++ | MCF_GPIO_PAR_UART_PAR_U1CTS_SSI_BCLK ++ | MCF_GPIO_PAR_UART_PAR_U1RTS_SSI_FS ++ | MCF_GPIO_PAR_UART_PAR_U1RXD_SSI_RXD ++ | MCF_GPIO_PAR_UART_PAR_U1TXD_SSI_TXD; ++ ++ MCF_GPIO_PAR_TIMER = (MCF_GPIO_PAR_TIMER ++ &~MCF_GPIO_PAR_TIMER_PAR_T3IN(0xF)) ++ | MCF_GPIO_PAR_TIMER_PAR_T3IN_SSI_MCLK; ++#endif ++#if defined(CONFIG_M532x) ++ MCF_GPIO_PAR_SSI = (0 ++ | MCF_GPIO_PAR_SSI_PAR_MCLK ++ | MCF_GPIO_PAR_SSI_PAR_TXD(3) ++ | MCF_GPIO_PAR_SSI_PAR_RXD(3) ++ | MCF_GPIO_PAR_SSI_PAR_FS(3) ++ | MCF_GPIO_PAR_SSI_PAR_BCLK(3)); ++#endif ++#if defined(CONFIG_M537x) ++ MCF_GPIO_PAR_UART = (MCF_GPIO_PAR_UART ++ &~MCF_GPIO_PAR_UART_PAR_UTXD1(0xF) ++ &~MCF_GPIO_PAR_UART_PAR_URXD1(0xF) ++ &~MCF_GPIO_PAR_UART_PAR_URTS1(0xF) ++ &~MCF_GPIO_PAR_UART_PAR_UCTS1(0xF)) ++ | MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK ++ | MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS ++ | MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD ++ | MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD; ++ ++ MCF_GPIO_PAR_IRQ = MCF_GPIO_PAR_IRQ_PAR_IRQ4(1); ++#endif ++#if defined(CONFIG_M5301x) ++ MCF_GPIO_PAR_SSIH = (MCF_GPIO_PAR_SSIH_PAR_RXD_SSI_RXD | ++ MCF_GPIO_PAR_SSIH_PAR_TXD_SSI_TXD | ++ MCF_GPIO_PAR_SSIH_PAR_FS_SSI_FS | ++ MCF_GPIO_PAR_SSIH_PAR_MCLK_SSI_MCLK); ++ MCF_GPIO_PAR_SSIL = MCF_GPIO_PAR_SSIL_PAR_BCLK_SSI_BCLK; ++#endif ++#if defined(CONFIG_M5445X) ++ MCF_GPIO_PAR_SSI = (MCF_GPIO_PAR_SSI_MCLK | ++ MCF_GPIO_PAR_SSI_STXD_STXD | ++ MCF_GPIO_PAR_SSI_SRXD_SRXD | ++ MCF_GPIO_PAR_SSI_FS_FS | ++ MCF_GPIO_PAR_SSI_BCLK_BCLK); ++#endif ++ chip_initialized = 1; ++} ++ ++static void ssi_audio_init_ssi_playback(void) ++{ ++ /* Issue a SSI reset */ ++ MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; ++ ++ /* SSI module uses internal CPU clock */ ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSI_SRC; ++#if defined(CONFIG_M5445X) || defined(CONFIG_M532x) || defined(CONFIG_M537x) \ ++ || defined(CONFIG_M5227x) ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSI_PUE | MCF_CCM_MISCCR_SSI_PUS; ++#endif ++#if defined(CONFIG_M5301x) ++ MCF_GPIO_PCRH |= MCF_GPIO_PCRH_SSI_PUS | MCF_GPIO_PCRH_SSI_PUE; ++#endif ++ MCF_SSI_CR = MCF_SSI_CR_CIS | ++ MCF_SSI_CR_TCH | /* Enable two channel mode */ ++ MCF_SSI_CR_MCE | /* clock out on SSI_MCLK pin */ ++ MCF_SSI_CR_I2S_MASTER | /* I2S master mode */ ++ MCF_SSI_CR_SYN | /* Enable synchronous mode */ ++ MCF_SSI_CR_NET; /* Auto set by I2S Master */ ++ ++ MCF_SSI_TCR = 0 | ++ /* internally generated bit clock */ ++ MCF_SSI_TCR_TXDIR | ++ /* internally generated frame sync */ ++ MCF_SSI_TCR_TFDIR | ++ /* Clock data on falling edge of bit clock */ ++ MCF_SSI_TCR_TSCKP | ++ /* Frame sync active low */ ++ MCF_SSI_TCR_TFSI | ++ /* TX frame sync 1 bit before data */ ++ MCF_SSI_TCR_TEFS | ++ /* TX FIFO 0 enabled */ ++ MCF_SSI_TCR_TFEN0 | ++ /* TX FIFO 1 enabled */ ++ MCF_SSI_TCR_TFEN1 | ++ MCF_SSI_TCR_TXBIT0; ++ ++ MCF_SSI_FCSR = MCF_SSI_FCSR_TFWM0(TXFWM) | MCF_SSI_FCSR_TFWM1(TXFWM); ++ ++ MCF_SSI_IER = MCF_SSI_IER_TDMAE | /* DMA request enabled */ ++ MCF_SSI_IER_TFE0 | ++ MCF_SSI_IER_TFE1; /* set by reset actually*/ ++} ++ ++static void ssi_audio_init_ssi_capture(void) ++{ ++ /* Issue a SSI reset */ ++ MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; ++ ++ /* SSI module uses internal CPU clock */ ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSI_SRC; ++#if defined(CONFIG_M5445X) || defined(CONFIG_M532x) || defined(CONFIG_M537x) \ ++ || defined(CONFIG_M5227x) ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSI_PUE | MCF_CCM_MISCCR_SSI_PUS; ++#endif ++#if defined(CONFIG_M5301x) ++ MCF_GPIO_PCRH |= MCF_GPIO_PCRH_SSI_PUS | MCF_GPIO_PCRH_SSI_PUE; ++#endif ++ MCF_SSI_CR = MCF_SSI_CR_CIS | ++ MCF_SSI_CR_TCH | /* Enable two channel mode */ ++ MCF_SSI_CR_MCE | /* clock out on SSI_MCLK pin */ ++ MCF_SSI_CR_I2S_MASTER | /* I2S master mode */ ++ MCF_SSI_CR_SYN | /* Enable synchronous mode */ ++ MCF_SSI_CR_NET; /* Auto set by I2S Master */ ++ ++ MCF_SSI_TCR = 0 | ++ /* internally generated bit clock */ ++ MCF_SSI_TCR_TXDIR | ++ /* internally generated frame sync */ ++ MCF_SSI_TCR_TFDIR | ++ /* Clock data on falling edge of bit clock */ ++ MCF_SSI_TCR_TSCKP | ++ /* Frame sync active low */ ++ MCF_SSI_TCR_TFSI | ++ /* TX frame sync 1 bit before data */ ++ MCF_SSI_TCR_TEFS | ++ /* TX FIFO 0 enabled */ ++ MCF_SSI_TCR_TFEN0 | ++ /* TX FIFO 1 enabled */ ++ MCF_SSI_TCR_TFEN1 | ++ MCF_SSI_TCR_TXBIT0; ++ ++ MCF_SSI_RCR = 0 | ++ /* Clock data on rising edge of bit clock */ ++ MCF_SSI_RCR_RSCKP | ++ /* Frame sync active low */ ++ MCF_SSI_RCR_RFSI | ++ /* RX frame sync 1 bit before data */ ++ MCF_SSI_RCR_REFS | ++ /* RX FIFO 0 enabled */ ++ MCF_SSI_RCR_RFEN0 | ++ /* RX FIFO 1 enabled */ ++ MCF_SSI_RCR_RFEN1 | ++ MCF_SSI_RCR_RXBIT0; /* Auto set by I2S Master */ ++ ++ MCF_SSI_FCSR = MCF_SSI_FCSR_RFWM0(RXFWM) | MCF_SSI_FCSR_RFWM1(RXFWM); ++ ++ /* interrupts */ ++ MCF_SSI_IER = MCF_SSI_IER_RDMAE | /* DMA request enabled */ ++ MCF_SSI_IER_RFF0 | /* rx FIFO 0 full */ ++ MCF_SSI_IER_RFF1; /* rx FIFO 1 full */ ++} ++ ++static int snd_coldfire_playback_open(struct snd_pcm_substream *substream) ++{ ++ int err; ++ struct chip_spec *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct dma_private *dma_private; ++ dma_addr_t tcd_buf_phys; ++ ++ runtime->hw = snd_coldfire_playback_hw; ++ err = snd_pcm_hw_constraint_integer(runtime, ++ SNDRV_PCM_HW_PARAM_PERIODS); ++ if (err < 0) { ++ printk(KERN_ERR "invalid buffer size\n"); ++ return err; ++ } ++ /* to make sure period_bytes is the multiple of size of minor loops */ ++ err = snd_pcm_hw_constraint_step(runtime, 0, ++ SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ HW_PERIODS_BYTES_STEP); ++ if (err < 0) { ++ printk(KERN_ERR "Error setting period_bytes step, " ++ "err=%d\n", err); ++ return err; ++ } ++ err = snd_pcm_hw_constraint_list(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ &constraints_rates); ++ if (err < 0) { ++ printk(KERN_ERR "Error setting rate constraints, " ++ "err=%d\n", err); ++ return err; ++ } ++ ssi_audio_chip_init(); ++ ssi_audio_init_ssi_playback(); ++ ssi_audio_init_codec_for_playback(substream); ++ err = ssi_audio_dma_request_playback_channel(substream); ++ if (err < 0) { ++ printk(KERN_ERR "Error requesting dma channel, err=%d\n", err); ++ return err; ++ } ++ ++ dma_private = dma_alloc_coherent(substream->pcm->dev, ++ sizeof(struct dma_private), &tcd_buf_phys, GFP_KERNEL); ++ ++ if (!dma_private) { ++ dev_err(substream->pcm->card->dev, ++ "can't allocate DMA private data\n"); ++ return -ENOMEM; ++ } ++ ++ dma_private->tcd_buf_phys = tcd_buf_phys; ++ runtime->private_data = dma_private; ++ ++ chip->offset = 0; ++ g_tx_dmaing = 0; ++ return 0; ++} ++ ++static int snd_coldfire_capture_open(struct snd_pcm_substream *substream) ++{ ++ int err; ++ struct chip_spec *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct dma_private *dma_private; ++ dma_addr_t tcd_buf_phys; ++ ++ runtime->hw = snd_coldfire_capture_hw; ++ ++ err = snd_pcm_hw_constraint_integer(runtime, ++ SNDRV_PCM_HW_PARAM_PERIODS); ++ if (err < 0) { ++ printk(KERN_ERR "invalid buffer size\n"); ++ return err; ++ } ++ /* to make sure period_bytes is the multiple of size of minor loops */ ++ err = snd_pcm_hw_constraint_step(runtime, 0, ++ SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ HW_PERIODS_BYTES_STEP); ++ if (err < 0) { ++ printk(KERN_ERR "Error setting period_bytes step, " ++ "err=%d\n", err); ++ return err; ++ } ++ err = snd_pcm_hw_constraint_list(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ &constraints_rates); ++ if (err < 0) { ++ printk(KERN_ERR "Error setting pcm_hw_constraint_list, " ++ "err=%d\n", err); ++ return err; ++ } ++ ++ ssi_audio_chip_init(); ++ ssi_audio_init_ssi_capture(); ++ ssi_audio_init_codec_for_capture(substream); ++ err = ssi_audio_dma_request_capture_channel(substream); ++ if (err < 0) { ++ printk(KERN_ERR "Error requesting dma channel, err=%d\n", err); ++ return err; ++ } ++ ++ dma_private = dma_alloc_coherent(substream->pcm->dev, ++ sizeof(struct dma_private), &tcd_buf_phys, GFP_KERNEL); ++ ++ if (!dma_private) { ++ dev_err(substream->pcm->card->dev, ++ "can't allocate DMA private data\n"); ++ return -ENOMEM; ++ } ++ dma_private->tcd_buf_phys = tcd_buf_phys; ++ dma_private->dma_buf_phys = substream->dma_buffer.addr; ++ ++ runtime->private_data = dma_private; ++ ++ chip->offset = 0; ++ g_rx_dmaing = 0; ++ return 0; ++} ++ ++static int snd_coldfire_playback_close(struct snd_pcm_substream *substream) ++{ ++ struct dma_private *dma_private = substream->runtime->private_data; ++ ++ ssi_audio_dma_playback_stop(); ++ mcf_edma_free_channel(DMA_TX_TCD0, substream); ++ mcf_edma_free_channel(DMA_TX_TCD1, substream); ++ if (dma_private) { ++ dma_free_coherent(substream->pcm->dev, ++ sizeof(struct dma_private), ++ dma_private, dma_private->tcd_buf_phys); ++ substream->runtime->private_data = NULL; ++ } ++ ssi_audio_disable_ssi(); ++ return 0; ++} ++ ++static int snd_coldfire_capture_close(struct snd_pcm_substream *substream) ++{ ++ struct dma_private *dma_private = substream->runtime->private_data; ++ ++ ssi_audio_dma_capture_stop(); ++ mcf_edma_free_channel(DMA_RX_TCD0, substream); ++ mcf_edma_free_channel(DMA_RX_TCD1, substream); ++ /* Deallocate the fsl_dma_private structure */ ++ if (dma_private) { ++ dma_free_coherent(substream->pcm->dev, ++ sizeof(struct dma_private), ++ dma_private, dma_private->tcd_buf_phys); ++ substream->runtime->private_data = NULL; ++ } ++ ssi_audio_disable_ssi(); ++ return 0; ++} ++ ++static int snd_coldfire_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *hw_params) ++{ ++ int err; ++ ++ /* set runtime buffer */ ++ err = snd_pcm_lib_malloc_pages( ++ substream, params_buffer_bytes(hw_params)); ++ if (err < 0) ++ printk(KERN_ERR "Error allocating pages, err=%d\n", err); ++ return err; ++} ++ ++static int snd_coldfire_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ /* free the memory if was newly allocated */ ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++static int ++snd_coldfire_pcm_playback_prepare(struct snd_pcm_substream *substream) ++{ ++ int err; ++ ++ if (g_tx_dmaing == 1) ++ return 0; ++ ++ ssi_audio_adjust_codec_speed(substream); ++ err = ssi_audio_dma_playback_config(substream); ++ if (err < 0) { ++ printk(KERN_ERR "Error configuring playback, " ++ "err=%d\n", err); ++ return err; ++ } ++ ++ ssi_audio_dma_playback_start(); ++ return 0; ++} ++ ++static int snd_coldfire_pcm_capture_prepare(struct snd_pcm_substream *substream) ++{ ++ int err; ++ ++ if (g_rx_dmaing == 1) ++ return 0; ++ ++ ssi_audio_adjust_codec_speed(substream); ++ err = ssi_audio_dma_capture_config(substream); ++ if (err < 0) { ++ printk(KERN_ERR "Error configuring capture, " ++ "err=%d\n", err); ++ return err; ++ } ++ ssi_audio_dma_capture_start(); ++ ++ return 0; ++} ++ ++static int ++snd_coldfire_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ ssi_audio_enable_ssi_playback(); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ ssi_audio_disable_ssi_playback(); ++ break; ++ default: ++ printk(KERN_ERR "Unsupported trigger command, cmd=%d\n", cmd); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ++snd_coldfire_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ ssi_audio_enable_ssi_capture(); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ ssi_audio_disable_ssi_capture(); ++ break; ++ default: ++ printk(KERN_ERR "Unsupported trigger command, cmd=%d\n", cmd); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static snd_pcm_uframes_t ++snd_coldfire_pcm_playback_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct dma_private *dma_private = runtime->private_data; ++ snd_pcm_uframes_t pointer; ++ u32 offset; ++ ++ offset = (u32)(MCF_EDMA_TCD_SADDR(DMA_TX_TCD0) - ++ dma_private->dma_buf_phys); ++ if (runtime->format == SNDRV_PCM_FORMAT_S16_BE) ++ pointer = offset / (runtime->channels == 1 ? 2 : 4); ++ else ++ pointer = 0; ++ ++ return pointer; ++} ++ ++static snd_pcm_uframes_t ++snd_coldfire_pcm_capture_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct dma_private *dma_private = runtime->private_data; ++ snd_pcm_uframes_t pointer; ++ u32 offset; ++ ++ offset = (u32)(MCF_EDMA_TCD_DADDR(DMA_RX_TCD0) - ++ dma_private->dma_buf_phys); ++ if (runtime->format == SNDRV_PCM_FORMAT_S16_BE) ++ pointer = offset / (runtime->channels == 1 ? 2 : 4); ++ else ++ pointer = 0; ++ ++ return pointer; ++} ++ ++static struct snd_pcm_ops snd_coldfire_playback_ops = { ++ .open = snd_coldfire_playback_open, ++ .close = snd_coldfire_playback_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = snd_coldfire_pcm_hw_params, ++ .hw_free = snd_coldfire_pcm_hw_free, ++ .prepare = snd_coldfire_pcm_playback_prepare, ++ .trigger = snd_coldfire_pcm_playback_trigger, ++ .pointer = snd_coldfire_pcm_playback_pointer, ++}; ++ ++static struct snd_pcm_ops snd_coldfire_capture_ops = { ++ .open = snd_coldfire_capture_open, ++ .close = snd_coldfire_capture_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = snd_coldfire_pcm_hw_params, ++ .hw_free = snd_coldfire_pcm_hw_free, ++ .prepare = snd_coldfire_pcm_capture_prepare, ++ .trigger = snd_coldfire_pcm_capture_trigger, ++ .pointer = snd_coldfire_pcm_capture_pointer, ++}; ++ ++static int snd_coldfire_new_pcm(struct chip_spec *chip) ++{ ++ struct snd_pcm *pcm; ++ int err; ++ ++ err = snd_pcm_new(chip->card, "coldfire", 0, 1, 1, ++ &pcm); ++ if (err < 0) { ++ printk(KERN_ERR "Error creating new pcm, err=%d\n", err); ++ return err; ++ } ++ pcm->private_data = chip; ++ strncpy(pcm->name, SOUND_CARD_NAME, sizeof(pcm->name)); ++ chip->pcm = pcm; ++ pcm->info_flags = 0; ++ ++ /* set operators */ ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, ++ &snd_coldfire_playback_ops); ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, ++ &snd_coldfire_capture_ops); ++ /* pre-allocation of buffers */ ++ err = snd_pcm_lib_preallocate_pages_for_all( ++ pcm, ++ SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data(GFP_KERNEL), ++ MAX_BUFFER_SIZE, ++ MAX_BUFFER_SIZE); ++ ++ if (!pcm->streams[0].substream->dma_buffer.addr) ++ pcm->streams[0].substream->dma_buffer.addr = ++ virt_to_phys(pcm->streams[0].substream->dma_buffer.area); ++ if (!pcm->streams[1].substream->dma_buffer.addr) ++ pcm->streams[1].substream->dma_buffer.addr = ++ virt_to_phys(pcm->streams[1].substream->dma_buffer.area); ++ ++ if (err) { ++ printk(KERN_ERR ++ "Can't pre-allocate DMA buffer (size=%u)\n", ++ MAX_BUFFER_SIZE); ++ return -ENOMEM; ++ } ++ ++ chip->audio_device = ++ kmalloc(sizeof(struct tlv320a_audio_device), GFP_DMA); ++ ++ if (!chip->audio_device) { ++ snd_pcm_lib_preallocate_free_for_all(pcm); ++ printk(KERN_ERR ++ "Can't allocate buffer for audio device\n"); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int tlv320a_set_out_volume(unsigned char value) ++{ ++ unsigned char data; ++ ++ if (value > TLV320A_VOL_MAX) ++ data = TLV320A_VOL_MAX; ++ else ++ data = value; ++ ++ if (mcf_codec_spi_write(CODEC_LEFT_HP_VOL_REG, data) < 0) ++ return -EINVAL; ++ ++ if (mcf_codec_spi_write(CODEC_RIGHT_HP_VOL_REG, data) < 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int tlv320a_info_out_volume(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = TLV320A_VOL_MIN; ++ uinfo->value.integer.max = TLV320A_VOL_MAX; ++ return 0; ++} ++ ++static int tlv320a_get_out_volume(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ ucontrol->value.integer.value[0] = g_mastervol; ++ return 0; ++} ++ ++static int tlv320a_put_out_volume(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ unsigned char vol; ++ int change; ++ ++ vol = ucontrol->value.integer.value[0]; ++ ++ if (vol > TLV320A_VOL_MAX) ++ return -EINVAL; ++ ++ change = (g_mastervol != vol); ++ if (change) { ++ g_mastervol = vol; ++ tlv320a_set_out_volume(vol); ++ } ++ return change; ++} ++ ++static int tlv320a_set_linein_volume(unsigned char value) ++{ ++ unsigned char data; ++ ++ if (value > TLV320A_LINEIN_MAX) ++ data = TLV320A_LINEIN_MAX; ++ else ++ data = value; ++ ++ if (mcf_codec_spi_write(CODEC_LEFT_IN_REG, data) < 0) ++ return -EINVAL; ++ ++ if (mcf_codec_spi_write(CODEC_RIGHT_IN_REG, data) < 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int tlv320a_info_linein_volume(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = TLV320A_LINEIN_MAX; ++ return 0; ++} ++ ++static int tlv320a_get_linein_volume(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ ucontrol->value.integer.value[0] = g_lineinvol; ++ return 0; ++} ++ ++static int tlv320a_put_linein_volume(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ unsigned char vol; ++ int change; ++ ++ vol = ucontrol->value.integer.value[0]; ++ ++ if (vol > TLV320A_LINEIN_MAX) ++ return -EINVAL; ++ ++ change = (g_lineinvol != vol); ++ if (change) { ++ g_lineinvol = vol; ++ tlv320a_set_linein_volume(vol); ++ } ++ return change; ++} ++ ++#define tlv320a_info_mic_boost snd_ctl_boolean_mono_info ++static int tlv320a_get_mic_boost(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ ucontrol->value.integer.value[0] = ((g_analogpath & 0x1) == 1); ++ return 0; ++} ++ ++static int tlv320a_put_mic_boost(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int oldboost, newboost; ++ u8 data; ++ if (ucontrol->value.integer.value[0] == 1) ++ newboost = 1; ++ else ++ newboost = 0; ++ oldboost = g_analogpath & 0x1; ++ ++ if (oldboost == newboost) ++ return 0; ++ data = (g_analogpath & 0xfe) | (newboost & 0x1); ++ if (mcf_codec_spi_write(CODEC_ANALOG_APATH_REG, data) < 0) ++ return -EINVAL; ++ g_analogpath = data; ++ return 1; ++} ++ ++static int tlv320a_info_capture_source(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ static char *texts[] = { "Line-In", "Microphone" }; ++ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; ++ uinfo->count = 1; ++ uinfo->value.enumerated.items = 2; ++ if (uinfo->value.enumerated.item > 1) ++ uinfo->value.enumerated.item = 1; ++ strcpy(uinfo->value.enumerated.name, ++ texts[uinfo->value.enumerated.item]); ++ return 0; ++} ++ ++static int tlv320a_get_capture_source(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ ++ ucontrol->value.enumerated.item[0] = ((g_analogpath & 0x4) == 0x4); ++ return 0; ++} ++ ++static int tlv320a_put_capture_source(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int oldinput, newinput; ++ u8 data; ++ ++ if (ucontrol->value.enumerated.item[0] > 1) ++ return -EINVAL; ++ ++ oldinput = (g_analogpath & 0x4) ? INPUT_MICROPHONE : INPUT_LINEIN; ++ ++ if (ucontrol->value.enumerated.item[0]) ++ newinput = INPUT_MICROPHONE; ++ else ++ newinput = INPUT_LINEIN; ++ if (oldinput == newinput) ++ return 0; ++ data = (g_analogpath & 0xfb) | ++ (newinput == INPUT_MICROPHONE ? 0x4 : 0); ++ if (mcf_codec_spi_write(CODEC_ANALOG_APATH_REG, data) < 0) ++ return -EINVAL; ++ g_analogpath = data; ++ return 1; ++} ++ ++static struct snd_kcontrol_new tlv320_mixer_out __devinitdata = { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "play volume", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .info = tlv320a_info_out_volume, ++ .get = tlv320a_get_out_volume, ++ .put = tlv320a_put_out_volume, ++}; ++ ++static struct snd_kcontrol_new tlv320_mixer_linein __devinitdata = { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "record volume", ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .info = tlv320a_info_linein_volume, ++ .get = tlv320a_get_linein_volume, ++ .put = tlv320a_put_linein_volume, ++}; ++ ++static struct snd_kcontrol_new tlv320_mixer_capture_source __devinitdata = { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "record source", ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .info = tlv320a_info_capture_source, ++ .get = tlv320a_get_capture_source, ++ .put = tlv320a_put_capture_source, ++}; ++ ++static struct snd_kcontrol_new tlv320_mixer_mic_boost __devinitdata = { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "mic Boost", ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .info = tlv320a_info_mic_boost, ++ .get = tlv320a_get_mic_boost, ++ .put = tlv320a_put_mic_boost, ++}; ++ ++static int __devinit coldfire_alsa_audio_probe(struct platform_device *dev) ++{ ++ struct snd_card *card; ++ struct chip_spec *chip; ++ int err; ++ ++ err = snd_card_create(-1, id, THIS_MODULE, ++ sizeof(struct chip_spec), &card); ++ if (err < 0) ++ return -ENOMEM; ++ ++ chip = card->private_data; ++ ++ chip->card = card; ++ card->dev = &dev->dev; ++ ++ err = snd_coldfire_new_pcm(chip); ++ if (err < 0) ++ return -ENOMEM; ++ ++ strcpy(card->driver, "coldfire"); ++ strcpy(card->shortname, "Coldfire-TLV320A"); ++ sprintf(card->longname, "Freescale Coldfire with TLV320A"); ++ ++ err = snd_card_register(card); ++ if (err == 0) { ++ pr_debug(KERN_INFO "Coldfire audio support initialized\n"); ++ platform_set_drvdata(dev, card); ++ } ++ ++ strcpy(chip->card->mixername, "TLV320A Volume"); ++ err = snd_ctl_add(chip->card, snd_ctl_new1(&tlv320_mixer_out, chip)); ++ if (err) ++ goto error; ++ err = snd_ctl_add(chip->card, snd_ctl_new1(&tlv320_mixer_linein, chip)); ++ if (err) ++ goto error; ++ err = snd_ctl_add(chip->card, ++ snd_ctl_new1(&tlv320_mixer_capture_source, ++ chip)); ++ if (err) ++ goto error; ++ err = snd_ctl_add(chip->card, ++ snd_ctl_new1(&tlv320_mixer_mic_boost, ++ chip)); ++ if (err) ++ goto error; ++ g_mastervol = TLV320A_VOL_INIT; ++ g_lineinvol = TLV320A_LINEIN_INIT; ++ g_analogpath = TLV320A_ANALOGPATH_INIT; ++ ssi_audio_codec_reset(); ++ return 0; ++error: ++ kfree(card->private_data); ++ snd_card_free(card); ++ platform_set_drvdata(dev, NULL); ++ return err; ++} ++ ++static int coldfire_alsa_audio_remove(struct platform_device *dev) ++{ ++ struct snd_card *card; ++ ++ card = platform_get_drvdata(dev); ++ kfree(card->private_data); ++ snd_card_free(card); ++ platform_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++static struct platform_driver coldfire_alsa_audio_driver = { ++ .probe = coldfire_alsa_audio_probe, ++ .remove = coldfire_alsa_audio_remove, ++ .driver = { ++ .name = SOUND_CARD_NAME, ++ }, ++}; ++ ++static int __init coldfire_alsa_audio_init(void) ++{ ++ int err; ++ err = platform_driver_register(&coldfire_alsa_audio_driver); ++ if (err < 0) ++ return err; ++ ++ device = platform_device_register_simple(SOUND_CARD_NAME, -1, NULL, 0); ++ if (!IS_ERR(device)) { ++ if (platform_get_drvdata(device)) ++ return 0; ++ platform_device_unregister(device); ++ platform_driver_unregister(&coldfire_alsa_audio_driver); ++ err = -ENODEV; ++ } else ++ err = PTR_ERR(device); ++ ++ platform_driver_unregister(&coldfire_alsa_audio_driver); ++ return err; ++} ++ ++static void __exit coldfire_alsa_audio_exit(void) ++{ ++ platform_device_unregister(device); ++ platform_driver_unregister(&coldfire_alsa_audio_driver); ++} ++ ++module_init(coldfire_alsa_audio_init); ++module_exit(coldfire_alsa_audio_exit); ++ ++MODULE_DESCRIPTION("Coldfire driver for ALSA"); ++MODULE_LICENSE("GPL"); ++MODULE_SUPPORTED_DEVICE("{{TLV320A}}"); ++ ++module_param(id, charp, 0444); ++MODULE_PARM_DESC(id, "ID string for Coldfire + TLV320A soundcard."); +--- /dev/null ++++ b/sound/coldfire/snd-coldfire.h +@@ -0,0 +1,15 @@ ++/* ++ * linux/sound/coldfire/snd-coldfire.h ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * ALSA driver for Coldfire SSI ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++extern int mcf_codec_spi_write(u8 addr, u16 data); ++ diff --git a/target/linux/coldfire/patches/010-Add-SRAM-char-device-driver-support-for-MCF5445x.patch b/target/linux/coldfire/patches/010-Add-SRAM-char-device-driver-support-for-MCF5445x.patch new file mode 100644 index 000000000..ed0516fcd --- /dev/null +++ b/target/linux/coldfire/patches/010-Add-SRAM-char-device-driver-support-for-MCF5445x.patch @@ -0,0 +1,198 @@ +From f54ba59d355f59e4c01b5b9c7dbc2d27b47302d2 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:41 +0800 +Subject: [PATCH 10/52] Add SRAM char device driver support for MCF5445x + +Created "/dev/sram" device file and implemented the sram mmap() operation to +provide interface for userspace access. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/char/Kconfig | 11 ++++ + drivers/char/Makefile | 2 + + drivers/char/sram.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 164 insertions(+), 0 deletions(-) + create mode 100644 drivers/char/sram.c + +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -97,6 +97,17 @@ config DEVKMEM + kind of kernel debugging operations. + When in doubt, say "N". + ++config DEVSRAM ++ tristate "/dev/sram virtual device support" ++ depends on M5445X ++ default m ++ help ++ Say Y here if you want to suppot the SRAM char device. When in ++ doubt, say "N". ++ ++ It implements mmap system call to provide interface for ++ user space access. ++ + config BFIN_JTAG_COMM + tristate "Blackfin JTAG Communication" + depends on BLACKFIN +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -87,3 +87,5 @@ obj-$(CONFIG_RAMOOPS) += ramoops.o + + obj-$(CONFIG_JS_RTC) += js-rtc.o + js-rtc-y = rtc.o ++ ++obj-$(CONFIG_DEVSRAM) += sram.o +--- /dev/null ++++ b/drivers/char/sram.c +@@ -0,0 +1,151 @@ ++/* ++ * linux/drivers/char/sram.c ++ * ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Lanttor.Guo@freescale.com ++ * ++ * SRAM char device driver, implements mmap() system call to provide ++ * interface for user space access. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/fs.h> ++#include <linux/errno.h> ++#include <linux/types.h> ++#include <linux/mm.h> ++#include <linux/kdev_t.h> ++#include <asm/page.h> ++#include <linux/cdev.h> ++#include <linux/device.h> ++ ++MODULE_LICENSE("GPL"); ++ ++static struct class *sram_class; ++static int sram_major; ++static int sram_minor; ++static struct cdev sram_cdev; ++ ++/* ++ * Set up the cdev structure for sram. ++ */ ++static void sram_setup_cdev(struct cdev *dev, int minor, ++ const struct file_operations *fops) ++{ ++ int err, devno = MKDEV(sram_major, minor); ++ ++ cdev_init(dev, fops); ++ dev->owner = THIS_MODULE; ++ dev->ops = fops; ++ err = cdev_add(dev, devno, 1); ++ /* Fail gracefully if need be */ ++ if (err) ++ printk(KERN_NOTICE "Error %d adding sram%d", err, minor); ++} ++ ++static int sram_open(struct inode *inode, struct file *filp) ++{ ++ filp->f_mapping->backing_dev_info = &directly_mappable_cdev_bdi; ++ return 0; ++} ++ ++static int sram_release(struct inode *inode, struct file *filp) ++{ ++ return 0; ++} ++ ++void sram_vma_open(struct vm_area_struct *vma) ++{ ++ printk(KERN_DEBUG "Sram VMA open, virt %lx, phys %lx\n", ++ vma->vm_start, ++ CONFIG_SRAM_BASE + (vma->vm_pgoff << PAGE_SHIFT)); ++} ++ ++void sram_vma_close(struct vm_area_struct *vma) ++{ ++ printk(KERN_DEBUG "Sram VMA close.\n"); ++} ++ ++ ++static struct vm_operations_struct sram_remap_vm_ops = { ++ .open = sram_vma_open, ++ .close = sram_vma_close, ++}; ++ ++static int sram_remap_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ size_t size = vma->vm_end - vma->vm_start; ++ ++ if (PAGE_ALIGN(size) > CONFIG_SRAM_SIZE) { ++ printk(KERN_ERR "required length exceed the size " ++ "of physical sram (%x)\n", CONFIG_SRAM_SIZE); ++ return -EAGAIN; ++ } ++ ++ if ((CONFIG_SRAM_BASE + (vma->vm_pgoff << PAGE_SHIFT) + size) ++ > (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE)) { ++ printk(KERN_ERR "required sram range exceed the size " ++ "of phisical sram\n"); ++ return -EAGAIN; ++ } ++ ++ if (remap_pfn_range(vma, vma->vm_start, ++ (CONFIG_SRAM_BASE >> PAGE_SHIFT) + vma->vm_pgoff, ++ size, ++ vma->vm_page_prot)) { ++ printk(KERN_ERR "remap_pfn_range faile at %s()\n", __func__); ++ return -EAGAIN; ++ } ++ ++ vma->vm_ops = &sram_remap_vm_ops; ++ return 0; ++} ++ ++static const struct file_operations sram_ops = { ++ .owner = THIS_MODULE, ++ .open = sram_open, ++ .release = sram_release, ++ .mmap = sram_remap_mmap, ++}; ++ ++static int __init sram_chrdev_init(void) ++{ ++ int minor_devs = 1; ++ int result; ++ dev_t dev = 0; ++ sram_minor = 0; ++ ++ result = alloc_chrdev_region(&dev, sram_minor, minor_devs, "sram"); ++ sram_major = MAJOR(dev); ++ if (result < 0) { ++ printk(KERN_WARNING "sram: can't get major %d\n", sram_major); ++ return result; ++ } ++ ++ sram_setup_cdev(&sram_cdev, 0, &sram_ops); ++ ++ sram_class = class_create(THIS_MODULE, "sram"); ++ device_create(sram_class, NULL, MKDEV(sram_major, sram_minor), ++ NULL, "sram"); ++ ++ return 0; ++} ++ ++static void sram_chrdev_cleanup(void) ++{ ++ cdev_del(&sram_cdev); ++ device_destroy(sram_class, MKDEV(sram_major, sram_minor)); ++ class_destroy(sram_class); ++ unregister_chrdev_region(MKDEV(sram_major, 0), 1); ++} ++ ++module_init(sram_chrdev_init); ++module_exit(sram_chrdev_cleanup); diff --git a/target/linux/coldfire/patches/011-Add-CAU-driver-for-MCF5445x-and-MCF5441x.patch b/target/linux/coldfire/patches/011-Add-CAU-driver-for-MCF5445x-and-MCF5441x.patch new file mode 100644 index 000000000..6608246c3 --- /dev/null +++ b/target/linux/coldfire/patches/011-Add-CAU-driver-for-MCF5445x-and-MCF5441x.patch @@ -0,0 +1,2514 @@ +From 0419eb27af72bd37c3ef926169fe4db90e8690d3 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:41 +0800 +Subject: [PATCH 11/52] Add CAU driver for MCF5445x and MCF5441x + +Add CAU driver support for MCF5445x and MCF5441x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + crypto/testmgr.c | 13 +- + drivers/crypto/Kconfig | 65 +++ + drivers/crypto/Makefile | 5 + + drivers/crypto/mcfcau-aes.c | 367 ++++++++++++++++ + drivers/crypto/mcfcau-des.c | 525 +++++++++++++++++++++++ + drivers/crypto/mcfcau-md5.c | 972 ++++++++++++++++++++++++++++++++++++++++++ + drivers/crypto/mcfcau-sha1.c | 331 ++++++++++++++ + drivers/crypto/mcfcau.c | 33 ++ + drivers/crypto/mcfcau.h | 101 +++++ + 9 files changed, 2410 insertions(+), 2 deletions(-) + create mode 100644 drivers/crypto/mcfcau-aes.c + create mode 100644 drivers/crypto/mcfcau-des.c + create mode 100644 drivers/crypto/mcfcau-md5.c + create mode 100644 drivers/crypto/mcfcau-sha1.c + create mode 100644 drivers/crypto/mcfcau.c + create mode 100644 drivers/crypto/mcfcau.h + +--- a/crypto/testmgr.c ++++ b/crypto/testmgr.c +@@ -705,6 +705,7 @@ static int test_cipher(struct crypto_cip + else + e = "decryption"; + ++ printk(KERN_INFO "%s testing %s %s\n", __func__, algo, e); + j = 0; + for (i = 0; i < tcount; i++) { + if (template[i].np) +@@ -750,7 +751,9 @@ static int test_cipher(struct crypto_cip + hexdump(q, template[i].rlen); + ret = -EINVAL; + goto out; +- } ++ } else ++ printk(KERN_INFO "alg: cipher: Test %d pass " ++ "on %s for %s\n", j, e, algo); + } + + ret = 0; +@@ -785,6 +788,7 @@ static int test_skcipher(struct crypto_a + else + e = "decryption"; + ++ printk(KERN_INFO "%s testing %s %s\n", __func__, algo, e); + init_completion(&result.completion); + + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); +@@ -863,10 +867,13 @@ static int test_skcipher(struct crypto_a + hexdump(q, template[i].rlen); + ret = -EINVAL; + goto out; +- } ++ } else ++ printk(KERN_INFO "alg: skcipher: Test %d " ++ "pass on %s for %s\n", j, e, algo); + } + } + ++ printk(KERN_INFO "\ntesting %s %s across pages (chunking)\n", algo, e); + j = 0; + for (i = 0; i < tcount; i++) { + +@@ -2514,6 +2521,8 @@ int alg_test(const char *driver, const c + int j; + int rc; + ++ printk(KERN_INFO "\ntesting %s\n", alg); ++ + if ((type & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_CIPHER) { + char nalg[CRYPTO_MAX_ALG_NAME]; + +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -61,6 +61,71 @@ config CRYPTO_DEV_GEODE + To compile this driver as a module, choose M here: the module + will be called geode-aes. + ++config CRYPTO_DEV_MCFCAU ++ bool "Support for Freescale Coldfire Cryptographic Acceleration Unit (CAU)" ++ depends on M5445X || M5441X ++ select CRYPTO_ALGAPI ++ help ++ The cryptographic acceleration unit (CAU) is a ColdFire coprocessor ++ implementing a set of specialized operations in hardware. For example, ++ you can find it on MCF5445X, or M5441X. ++ ++ Say Y here if you want to use CAU. ++ ++config CRYPTO_DEV_MCFCAU_DES ++ tristate "DES and Triple DES cipher algorithms (coldfire)" ++ depends on CRYPTO_DEV_MCFCAU ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ help ++ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). ++ ++ Say 'Y' here to use the CAU coprocessor for ++ the CryptoAPI DES and 3DES alogrithms. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called mcfcau-des. ++ ++config CRYPTO_DEV_MCFCAU_AES ++ tristate "AES cipher algorithm (coldfire)" ++ depends on CRYPTO_DEV_MCFCAU ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ help ++ AES cipher algorithm (FIPS 197). ++ ++ Say 'Y' here to use the CAU coprocessor for ++ the CryptoAPI AES alogrithm. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called mcfcau-aes. ++ ++config CRYPTO_DEV_MCFCAU_MD5 ++ tristate "MD5 digest algorithm (coldfire)" ++ depends on CRYPTO_DEV_MCFCAU ++ select CRYPTO_ALGAPI ++ help ++ MD5 message digest algorithm (RFC1321). ++ ++ Say 'Y' here to use the CAU coprocessor for ++ the CryptoAPI MD5 alogrithm. ++ ++ To compile this driver as a module, choose M here: ++ the module will be called mcfcau-md5. ++ ++config CRYPTO_DEV_MCFCAU_SHA1 ++ tristate "SHA1 digest algorithm (coldfire)" ++ depends on CRYPTO_DEV_MCFCAU ++ select CRYPTO_ALGAPI ++ help ++ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). ++ ++ Say 'Y' here to use the CAU coprocessor for ++ the CryptoAPI SHA1 alogrithm. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called mcfcau-sha1. ++ + config ZCRYPT + tristate "Support for PCI-attached cryptographic adapters" + depends on S390 +--- a/drivers/crypto/Makefile ++++ b/drivers/crypto/Makefile +@@ -7,6 +7,11 @@ obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hi + obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o + obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o + obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o ++obj-$(CONFIG_CRYPTO_DEV_MCFCAU) += mcfcau.o ++obj-$(CONFIG_CRYPTO_DEV_MCFCAU_DES) += mcfcau-des.o ++obj-$(CONFIG_CRYPTO_DEV_MCFCAU_AES) += mcfcau-aes.o ++obj-$(CONFIG_CRYPTO_DEV_MCFCAU_MD5) += mcfcau-md5.o ++obj-$(CONFIG_CRYPTO_DEV_MCFCAU_SHA1) += mcfcau-sha1.o + obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ + obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o + obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o +--- /dev/null ++++ b/drivers/crypto/mcfcau-aes.c +@@ -0,0 +1,367 @@ ++/*************************************************************************** ++ * mcfcau-aes.c - Implementation of AES Cipher Algorithm ++ * for Freescale ColdFire Cryptographic Acceleration Unit (CAU). ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Shrek Wu B16972@freescale.com ++ * ++ * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.01 17 September 2007 Andrey Butok ++ * Initial Release - developed on 2.6.20 Linux kernel. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/crypto.h> ++ ++/* ++#undef DEBUG ++#define DEBUG 1 ++*/ ++ ++#include "mcfcau.h" ++ ++#define MCFCAU_AES_MIN_KEY_SIZE (16) ++#define MCFCAU_AES_MAX_KEY_SIZE (32) ++#define MCFCAU_AES_BLOCK_SIZE (16) ++ ++#define MCFCAU_AES_DRIVER_DESC "AES ColdFire CAU driver" ++#define MCFCAU_AES_DRIVER_VERSION "v0.01" ++ ++struct mcfcau_aes_ctx { ++ int Nr_1; ++ u32 buf[120]; ++ u32 buf_tmp[16]; ++}; ++ ++static u32 mcfcau_rco_tab[10] ++ = { 0x01000000, 0x02000000, 0x04000000, 0x08000000, ++ 0x10000000, 0x20000000, 0x40000000, 0x80000000, ++ 0x1b000000, 0x36000000}; ++ ++int mcfcau_aes_setkey(struct crypto_tfm *tfm, const u8 *in_key, ++ unsigned int key_len) ++{ ++ struct mcfcau_aes_ctx *ctx = crypto_tfm_ctx(tfm); ++ const u32 *key = (const u32 *)in_key; ++ u32 *flags = &tfm->crt_flags; ++ u32 i; ++ u32 *key_sch = (&ctx->buf[0]); ++ u32 *temp_p, *rcon_p; ++ u32 Nx; ++ u32 Nk; ++ unsigned long iflags; ++ ++ DBG("mcfcau_aes_setkey\n"); ++ ++ if (key_len % 8) { ++ *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; ++ return -EINVAL; ++ } ++ ++ Nk = key_len>>2; ++ ++ for (i = 0; i < Nk; i++) ++ key_sch[i] = key[i]; ++ ++ ctx->Nr_1 = Nk+5; ++ ++ /* Key Expansion */ ++ temp_p = &key_sch[Nk-1]; ++ rcon_p = &mcfcau_rco_tab[0]; ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ ++ asm volatile ("move.l %0, %%a1" ++ : : "m"(temp_p) : "a1"); ++ asm volatile ("move.l %0, %%a3" ++ : : "m"(rcon_p) : "a3"); ++ asm volatile ("move.l %0, %%a4" ++ : : "m"(key_sch) : "a4"); ++ ++ Nx = (Nk+7)<<2; /* (Nr+1)*Nb */ ++ ++ for (i = Nk; i < Nx; i++) { ++ /* temp = key_sch[Nk-1] */ ++ asm volatile ("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CAA) : "a1"); ++ ++ if (i % Nk == 0) { ++ asm volatile ("moveq #8, %%d0" : : : "d0"); ++ /* CAA=RotWord(temp) */ ++ asm volatile ("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA) : "d0"); ++ /* SubWord(CAA) */ ++ asm volatile ("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESS+MCFCAU_CAA)); ++ /* ACC xor rcon[i/Nk] */ ++ asm volatile ("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CAA) : "a3"); ++ ++ } else if ((Nk > 6) && (i % Nk == 4)) { ++ /* SubWord(ACC) */ ++ asm volatile ("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESS+MCFCAU_CAA)); ++ } ++ ++ /* key_sch[i]^=key_sch[i-Nk]; store ACC to key_sch[i] */ ++ asm volatile ("cp0ld.l (%%a4)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CAA) : "a4"); ++ asm volatile ("cp0st.l %%d0,(%%a1),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CAA)); ++ } ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++ ++ return 0; ++} ++ ++ ++/* encrypt a block of text */ ++static void mcfcau_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) ++{ ++ struct mcfcau_aes_ctx *ctx = crypto_tfm_ctx(tfm); ++ const int Nr_1 = ctx->Nr_1; ++ ++ u32 *key_sch = &(ctx->buf[0]); ++ u32 i; ++ unsigned long iflags; ++ ++ DBG("mcfcau_aes_encrypt\n"); ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ asm("move.l %0, %%a1" : : "m"(in) : "a1"); ++ asm("move.l %0, %%a0" : : "m"(key_sch) : "a0"); ++ /* state=in */ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3) : "a1"); ++ /* AddRoundKey() */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA1) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA3) : "a0"); ++ ++ for (i = Nr_1; i > 0; i--) { ++ /* SubBytes(state) */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESS+MCFCAU_CA0)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESS+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESS+MCFCAU_CA2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESS+MCFCAU_CA3)); ++ /* ShiftRows(state) */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESR)); ++ /* MixColumns(state); AddRoundKey() */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESC+MCFCAU_CA0) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESC+MCFCAU_CA1) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESC+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESC+MCFCAU_CA3) : "a0"); ++ } ++ /* SubBytes(state)*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESS+MCFCAU_CA0)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESS+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESS+MCFCAU_CA2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESS+MCFCAU_CA3)); ++ /* ShiftRows(state) */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESR)); ++ /* AddRoundKey() */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA1) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA3) : "a0"); ++ /* out = state */ ++ asm("move.l %0, %%a1" : : "m"(out) : "a1"); ++ asm("cp0st.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA0) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA1) : "d1"); ++ ++ asm("move.l %%d0,(%%a1)+" : : : "a1"); ++ asm("move.l %%d1,(%%a1)+" : : : "a1"); ++ ++ asm("cp0st.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "d1"); ++ ++ asm("move.l %%d0,(%%a1)+" : : : "a1"); ++ asm("move.l %%d1,(%%a1)+" : : : "a1"); ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++ ++/* decrypt a block of text */ ++static void mcfcau_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) ++{ ++ struct mcfcau_aes_ctx *ctx = crypto_tfm_ctx(tfm); ++ u32 *key_sch = &(ctx->buf[0]); ++ u32 i; ++ unsigned long iflags; ++ const int Nr_1 = ctx->Nr_1; ++ key_sch = &key_sch[(Nr_1+2)*4]; ++ ++ DBG("mcfcau_aes_decrypt\n"); ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ ++ asm("move.l %0, %%a1" : : "m"(in) : "a1"); ++ asm("move.l %0, %%a0" : : "m"(key_sch) : "a0"); ++ /* state=in */ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3) : "a1"); ++ /* AddRoundKey() */ ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA3) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA1) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0) : "a0"); ++ ++ for (i = Nr_1; i > 0; i--) { ++ /* InvShiftRows(state) */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIR)); ++ /* InvSubBytes(state) */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIS+MCFCAU_CA3)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIS+MCFCAU_CA2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIS+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIS+MCFCAU_CA0)); ++ /* InvMixColumns(state); AddRoundKey() */ ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIC+MCFCAU_CA3) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIC+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIC+MCFCAU_CA1) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_AESIC+MCFCAU_CA0) : "a0"); ++ } ++ /* InvShiftRows(state) */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESIR)); ++ /* InvSubBytes(state)*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESIS+MCFCAU_CA3)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESIS+MCFCAU_CA2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESIS+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_AESIS+MCFCAU_CA0)); ++ /* AddRoundKey() */ ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA3) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA1) : "a0"); ++ asm("cp0ld.l -(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0) : "a0"); ++ /* out = state */ ++ asm("move.l %0, %%a1" : : "m"(out) : "a1"); ++ asm("cp0st.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_STR+MCFCAU_CA0) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" : : "n"(MCFCAU_STR+MCFCAU_CA1) : "d1"); ++ ++ asm("move.l %%d0,(%%a1)+" : : : "a1"); ++ asm("move.l %%d1,(%%a1)+" : : : "a1"); ++ ++ asm("cp0st.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_STR+MCFCAU_CA2) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" : : "n"(MCFCAU_STR+MCFCAU_CA3) : "d1"); ++ ++ asm("move.l %%d0,(%%a1)+" : : : "a1"); ++ asm("move.l %%d1,(%%a1)+" : : : "a1"); ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++ ++} ++ ++ ++static struct crypto_alg mcfcau_aes_alg = { ++ .cra_name = "aes", ++ .cra_driver_name = "aes-mcfcau", ++ .cra_priority = MCFCAU_CRA_PRIORITY, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER, ++ .cra_blocksize = MCFCAU_AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct mcfcau_aes_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(mcfcau_aes_alg.cra_list), ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = MCFCAU_AES_MIN_KEY_SIZE, ++ .cia_max_keysize = MCFCAU_AES_MAX_KEY_SIZE, ++ .cia_setkey = mcfcau_aes_setkey, ++ .cia_encrypt = mcfcau_aes_encrypt, ++ .cia_decrypt = mcfcau_aes_decrypt ++ } ++ } ++}; ++ ++static int __init mcfcau_aes_init(void) ++{ ++ int ret = crypto_register_alg(&mcfcau_aes_alg); ++ ++ printk(KERN_INFO MCFCAU_AES_DRIVER_DESC " " ++ MCFCAU_AES_DRIVER_VERSION " %s.\n", ++ ret ? "failed" : "registered"); ++ return ret; ++} ++ ++static void __exit mcfcau_aes_fini(void) ++{ ++ crypto_unregister_alg(&mcfcau_aes_alg); ++ printk(KERN_INFO MCFCAU_AES_DRIVER_DESC " " ++ MCFCAU_AES_DRIVER_VERSION " unregistered.\n"); ++} ++ ++module_init(mcfcau_aes_init); ++module_exit(mcfcau_aes_fini); ++ ++MODULE_DESCRIPTION(MCFCAU_AES_DRIVER_DESC); ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("Andrey Butok"); +--- /dev/null ++++ b/drivers/crypto/mcfcau-des.c +@@ -0,0 +1,525 @@ ++/*************************************************************************** ++ * mcfcau-des.c - Implementation of DES & Triple DES EDE Cipher Algorithms ++ * for Freescale ColdFire Cryptographic Acceleration Unit (CAU). ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Shrek Wu B16972@freescale.com ++ * ++ * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.01 14 August 2007 Andrey Butok ++ * Initial Release - developed on 2.6.20 Linux kernel. ++ */ ++ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/errno.h> ++#include <linux/crypto.h> ++#include <linux/types.h> ++ ++/* ++#undef DEBUG ++#define DEBUG 1 ++*/ ++ ++#include "mcfcau.h" ++ ++#define MCFCAU_DES_KEY_SIZE (8) ++#define MCFCAU_DES_EXPKEY_WORDS (32) ++#define MCFCAU_DES_BLOCK_SIZE (8) ++ ++#define MCFCAU_DES3_EDE_KEY_SIZE (3 * MCFCAU_DES_KEY_SIZE) ++#define MCFCAU_DES3_EDE_EXPKEY_WORDS (3 * MCFCAU_DES_EXPKEY_WORDS) ++#define MCFCAU_DES3_EDE_BLOCK_SIZE (MCFCAU_DES_BLOCK_SIZE) ++ ++#define MCFCAU_DES_DRIVER_DESC "DES & 3DES ColdFire CAU driver" ++#define MCFCAU_DES_DRIVER_VERSION "v0.01" ++ ++struct mcfcau_des_ctx { ++ u32 expkey[MCFCAU_DES_EXPKEY_WORDS]; ++}; ++ ++struct mcfcau_des3_ede_ctx { ++ u32 expkey[MCFCAU_DES3_EDE_EXPKEY_WORDS]; ++}; ++ ++/* DES round operations */ ++static inline void mcfcau_des_encipher(void) ++{ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESK)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_IP+MCFCAU_KSL1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSL1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_FP+MCFCAU_KSL1)); ++} ++ ++static inline void mcfcau_des_decipher(void) ++{ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESK+MCFCAU_DC)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_IP+MCFCAU_KSR1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR2)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_KSR1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_DESR+MCFCAU_FP+MCFCAU_KSL1)); ++} ++ ++ ++static int mcfcau_des_setkey(struct crypto_tfm *tfm, const u8 *key_p, ++ unsigned int keylen) ++{ ++ struct mcfcau_des_ctx *dctx = crypto_tfm_ctx(tfm); ++ u32 *flags = &tfm->crt_flags; ++ u32 * key = (u32 *) key_p; ++ ++ DBG("mcfcau_des_setkey\n"); ++ ++ /* ++ * RFC2451: Weak key checks SHOULD be performed. ++ * ++ * FIPS 74: ++ * Keys having duals are keys which produce all zeros, all ones, or ++ * alternating zero-one patterns in the C and D registers ++ * after Permuted ++ * Choice 1 has operated on the key. ++ * ++ */ ++ if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) { /* FIPS 74 */ ++ if (key[0] < 0xE001E00l) { ++ if (key[0] < 0x1FE01FE0) { ++ if (key[0] < 0x01E001E0) { ++ if (((key[0] == 0x01010101) && ++ (key[1] == 0x01010101)) || ++ ((key[0] == 0x011F011F) && ++ (key[1] == 0x010E010E))) ++ goto WEAK_KEY; ++ } else { ++ if (((key[0] == 0x01E001E0) && ++ (key[1] == 0x01F101F1)) || ++ ((key[0] == 0x01FE01FE) && ++ (key[1] == 0x01FE01FE))) ++ goto WEAK_KEY; ++ } ++ } else { ++ if (key[0] < 0x1F1F1F1F) { ++ if (((key[0] == 0x1FE01FE0) && ++ (key[1] == 0x0EF10EF1)) || ++ ((key[0] == 0x1F011F0l) && ++ (key[1] == 0x0E010E01))) ++ goto WEAK_KEY; ++ } else{ ++ if (((key[0] == 0x1F1F1F1F) && ++ (key[1] == 0x0E0E0E0E)) || ++ ((key[0] == 0x1FFE1FFE) && ++ (key[1] == 0x0EFE0EFE))) ++ goto WEAK_KEY; ++ } ++ } ++ } else { ++ if (key[0] < 0xFE01FE01) { ++ if (key[0] < 0xE0E0E0E0) { ++ if (((key[0] == 0xE001E00l) && ++ (key[1] == 0xF101F101)) || ++ ((key[0] == 0xE01FE01F) && ++ (key[1] == 0xF10EF10E))) ++ goto WEAK_KEY; ++ } else { ++ if (((key[0] == 0xE0E0E0E0) && ++ (key[1] == 0xF1F1F1F1)) || ++ ((key[0] == 0xE0FEE0FE) && ++ (key[1] == 0xF1FEF1FE))) ++ goto WEAK_KEY; ++ } ++ } else { ++ if (key[0] < 0xFEE0FEE0) { ++ if (((key[0] == 0xFE01FE01) && ++ (key[1] == 0xFE01FE01)) || ++ ((key[0] == 0xFE1FFE1F) && ++ (key[1] == 0xFE0EFE0E))) ++ goto WEAK_KEY; ++ } else { ++ if (((key[0] == 0xFEE0FEE0) && ++ (key[1] == 0xFEF1FEF1)) || ++ ((key[0] == 0xFEFEFEFE) ++ && (key[1] == 0xFEFEFEFE))) ++ goto WEAK_KEY; ++ } ++ } ++ } ++ } ++ memcpy(dctx->expkey, key_p, keylen); ++ return 0; ++WEAK_KEY: ++ *flags |= CRYPTO_TFM_RES_WEAK_KEY; ++ return -EINVAL; ++} ++ ++ ++void mcfcau_des_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src) ++{ ++ struct mcfcau_des_ctx *ctx = crypto_tfm_ctx(tfm); ++ u32 *des_key_tmp = ctx->expkey; ++ unsigned long iflags; ++ ++ DBG("mcfcau_des_encrypt\n"); ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ ++ asm("move.l %0, %%a0" : : "m"(src) : "a0"); ++ asm("move.l %0, %%a1" : : "m"(des_key_tmp) : "a1"); ++ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3)); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1)); ++ ++ mcfcau_des_encipher(); ++ ++ asm("cp0st.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "d1"); ++ asm("move.l %0, %%a1" : : "m"(dst) : "a1"); ++ asm("move.l %d0,(%a1)+"); ++ asm("move.l %d1,(%a1)"); ++ ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++ ++void mcfcau_des_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src) ++{ ++ struct mcfcau_des_ctx *ctx = crypto_tfm_ctx(tfm); ++ u32 *des_key_tmp = ctx->expkey; ++ unsigned long iflags; ++ ++ DBG("mcfcau_des_decrypt\n"); ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ ++ asm("move.l %0, %%a0" : : "m"(src) : "a0"); ++ asm("move.l %0, %%a1" : : "m"(des_key_tmp) : "a1"); ++ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3)); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1)); ++ ++ mcfcau_des_decipher(); ++ ++ asm("move.l %0, %%a1" : : "m"(dst) : "a1"); ++ asm("cp0st.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "d1"); ++ asm("move.l %d0,(%a1)+"); ++ asm("move.l %d1,(%a1)"); ++ ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++ ++/* ++ * RFC2451: ++ * ++ * For DES-EDE3, there is no known need to reject weak or ++ * complementation keys. Any weakness is obviated by the use of ++ * multiple keys. ++ * ++ * However, if the first two or last two independent 64-bit keys are ++ * equal (k1 == k2 or k2 == k3), then the DES3 operation is simply the ++ * same as DES. Implementers MUST reject keys that exhibit this ++ * property. ++ * ++ */ ++ ++static int mcfcau_des3_ede_setkey( ++ struct crypto_tfm *tfm, const u8 *key_p, unsigned int keylen) ++{ ++ const u32 *key = (const u32 *)key_p; ++ struct mcfcau_des3_ede_ctx *dctx = crypto_tfm_ctx(tfm); ++ u32 *flags = &tfm->crt_flags; ++ ++ DBG("mcfcau_des3_ede_setkey\n"); ++ ++ if (unlikely(!((key[0] ^ key[2]) | (key[1] ^ key[3])) || ++ !((key[2] ^ key[4]) | (key[3] ^ key[5])))) { ++ *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED; ++ return -EINVAL; ++ } ++ ++ memcpy(dctx->expkey, key_p, keylen); ++ ++ return 0; ++} ++ ++static void mcfcau_des3_ede_encrypt( ++ struct crypto_tfm *tfm, u8 *dst, const u8 *src) ++{ ++ struct mcfcau_des3_ede_ctx *dctx = crypto_tfm_ctx(tfm); ++ const u32 *des_key_tmp = dctx->expkey; ++ unsigned long iflags; ++ ++ DBG("mcfcau_des3_ede_encrypt\n"); ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ ++ /*EK1*/ ++ asm("move.l %0, %%a0" ++ : : "m"(src) : "a0"); ++ asm("move.l %0, %%a1" ++ : : "m"(des_key_tmp) : "a1"); ++ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3)); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1) : "a1"); ++ ++ mcfcau_des_encipher(); ++ ++ /*DK2*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1) : "a1"); ++ ++ mcfcau_des_decipher(); ++ ++ /*EK3*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1)); ++ ++ mcfcau_des_encipher(); ++ ++ asm("move.l %0, %%a1" ++ : : "m"(dst) : "a1"); ++ asm("cp0st.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "d1"); ++ asm("move.l %d0,(%a1)+"); ++ asm("move.l %d1,(%a1)"); ++ ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++static void mcfcau_des3_ede_decrypt( ++ struct crypto_tfm *tfm, u8 *dst, const u8 *src) ++{ ++ struct mcfcau_des3_ede_ctx *dctx = crypto_tfm_ctx(tfm); ++ const u32 *des_key_tmp = dctx->expkey + 6 - 2; ++ unsigned long iflags; ++ ++ DBG("mcfcau_des3_ede_decrypt\n"); ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ ++ /*DK3*/ ++ asm("move.l %0, %%a0" ++ : : "m"(src) : "a0"); ++ asm("move.l %0, %%a1" ++ : : "m"(des_key_tmp) : "a1"); ++ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a0"); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3)); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1)); ++ ++ mcfcau_des_decipher(); ++ ++ /*EK2*/ ++ asm("suba.l #12,%a1"); /*dec key pointer*/ ++ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1)); ++ ++ mcfcau_des_encipher(); ++ ++ /*DK1*/ ++ asm("suba.l #12,%a1"); /*dec key pointer*/ ++ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a1"); ++ asm("cp0ld.l (%%a1),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1)); ++ ++ mcfcau_des_decipher(); ++ ++ asm("move.l %0, %%a1" ++ : : "m"(dst) : "a1"); ++ asm("cp0st.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "d0"); ++ asm("cp0st.l %%d0,%%d1,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "d1"); ++ asm("move.l %d0,(%a1)+"); ++ asm("move.l %d1,(%a1)"); ++ ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++ ++static struct crypto_alg mcfcau_des_alg = { ++ .cra_name = "des", ++ .cra_driver_name = "des-mcfcau", ++ .cra_priority = MCFCAU_CRA_PRIORITY, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER, ++ .cra_blocksize = MCFCAU_DES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct mcfcau_des_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_alignmask = 3, ++ .cra_list = LIST_HEAD_INIT(mcfcau_des_alg.cra_list), ++ .cra_u = { .cipher = { ++ .cia_min_keysize = MCFCAU_DES_KEY_SIZE, ++ .cia_max_keysize = MCFCAU_DES_KEY_SIZE, ++ .cia_setkey = mcfcau_des_setkey, ++ .cia_encrypt = mcfcau_des_encrypt, ++ .cia_decrypt = mcfcau_des_decrypt } } ++}; ++ ++static struct crypto_alg mcfcau_des3_ede_alg = { ++ .cra_name = "des3_ede", ++ .cra_driver_name = "des3_ede-mcfcau", ++ .cra_priority = MCFCAU_CRA_PRIORITY, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER, ++ .cra_blocksize = MCFCAU_DES3_EDE_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct mcfcau_des3_ede_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_alignmask = 3, ++ .cra_list = ++ LIST_HEAD_INIT(mcfcau_des3_ede_alg.cra_list), ++ .cra_u = { .cipher = { ++ .cia_min_keysize = MCFCAU_DES3_EDE_KEY_SIZE, ++ .cia_max_keysize = MCFCAU_DES3_EDE_KEY_SIZE, ++ .cia_setkey = mcfcau_des3_ede_setkey, ++ .cia_encrypt = mcfcau_des3_ede_encrypt, ++ .cia_decrypt = mcfcau_des3_ede_decrypt } } ++}; ++ ++MODULE_ALIAS("mcfcau_des3_ede"); ++ ++static int __init mcfcau_des_init(void) ++{ ++ int ret; ++ ++ ret = crypto_register_alg(&mcfcau_des_alg); ++ if (ret < 0) ++ goto out; ++ ++ ret = crypto_register_alg(&mcfcau_des3_ede_alg); ++ if (ret < 0) ++ crypto_unregister_alg(&mcfcau_des_alg); ++out: ++ printk(KERN_INFO MCFCAU_DES_DRIVER_DESC " " ++ MCFCAU_DES_DRIVER_VERSION " %s.\n", ++ ret ? "failed" : "registered"); ++ return ret; ++} ++ ++static void __exit mcfcau_des_exit(void) ++{ ++ crypto_unregister_alg(&mcfcau_des3_ede_alg); ++ crypto_unregister_alg(&mcfcau_des_alg); ++ ++ printk(KERN_INFO MCFCAU_DES_DRIVER_DESC " " ++ MCFCAU_DES_DRIVER_VERSION " unregistered.\n"); ++} ++ ++module_init(mcfcau_des_init); ++module_exit(mcfcau_des_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms for ColdFire CAU"); ++MODULE_AUTHOR("Andrey Butok"); +--- /dev/null ++++ b/drivers/crypto/mcfcau-md5.c +@@ -0,0 +1,972 @@ ++/*************************************************************************** ++ * mcfcau-md5.c - Implementation of MD5 Message Digest Algorithm (RFC1321) ++ * for Freescale ColdFire Cryptographic Acceleration Unit (CAU). ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Shrek Wu B16972@freescale.com ++ * Alison Wang b18965@freescale.com ++ * ++ * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.01 30 September 2007 Andrey Butok ++ * Initial Release - developed on 2.6.20 Linux kernel. ++ */ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/string.h> ++#include <linux/crypto.h> ++#include <linux/types.h> ++#include <crypto/algapi.h> ++#include <crypto/hash.h> ++#include <crypto/internal/hash.h> ++#include <asm/byteorder.h> ++ ++#include "mcfcau.h" ++ ++#define MCFCAU_MD5_DIGEST_SIZE (16) ++#define MCFCAU_MD5_HMAC_BLOCK_SIZE (64) ++#define MCFCAU_MD5_BLOCK_WORDS (16) ++#define MCFCAU_MD5_HASH_WORDS (4) ++ ++#define MCFCAU_MD5_DRIVER_DESC "MD5 ColdFire CAU driver" ++#define MCFCAU_MD5_DRIVER_VERSION "v0.01" ++ ++ ++struct mcfcau_md5_ctx { ++ u32 hash[MCFCAU_MD5_HASH_WORDS]; ++ u32 block[MCFCAU_MD5_BLOCK_WORDS]; ++ u64 byte_count; ++}; ++ ++u32 mcfcau_md5_t[64] = {0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, ++ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, ++ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, ++ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, ++ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, ++ 0xd62f105d, 0x02441453, 0xd8a1e681, 0xe7d3fbc8, ++ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, ++ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, ++ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, ++ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, ++ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x04881d05, ++ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, ++ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, ++ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, ++ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, ++ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391}; ++ ++ ++ ++static void mcfcau_md5_transform(u32 *hash, u32 const *in) ++{ ++ int i; ++ u32 *md5_t_p = &mcfcau_md5_t[0]; ++ unsigned long iflags; ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ asm("move.l %0, %%a1" : : "m"(hash) : "a1"); ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CAA) : "a1");/*a*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1) : "a1");/*b*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a1");/*c*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3) : "a1");/*d*/ ++ asm("move.l %0, %%a0" : : "m"(in) : "a0"); /* X[] */ ++ asm("move.l %0, %%a3" : : "m"(md5_t_p) : "a3"); /* T[] */ ++ ++ /* Round 1 */ ++ asm("moveq.l #7, %%d4" : : : "d4"); /* for rotating by 7 */ ++ asm("moveq.l #12, %%d5" : : : "d5"); /* for rotating by 12 */ ++ asm("moveq.l #17, %%d6" : : : "d6"); /* for rotating by 17 */ ++ asm("moveq.l #22, %%d7" : : : "d7"); /* for rotating by 22 */ ++ ++ for (i = 0; i < 4; i++) { ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFF)); ++ /* a+F(b,c,d) */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ /* add byterev x[i] */ ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ /* add t[i] */ ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ /* rotate by 7 */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ /* add b */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ /* register to register shift */ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFF)); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFF)); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFF)); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ }; ++ ++ ++ /* Round 2 */ ++ asm("moveq.l #5, %%d4" : : : "d4"); /* for rotating by 5 */ ++ asm("moveq.l #9, %%d5" : : : "d5"); /* for rotating by 9 */ ++ asm("moveq.l #14, %%d6" : : : "d6"); /* for rotating by 14 */ ++ asm("moveq.l #20, %%d7" : : : "d7"); /* for rotating by 20 */ ++ ++ asm("lea -60(%%a0),%%a0" : : : "a0"); ++ ++ for (i = 0; i < 2; i++) { ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -44(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ }; ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" ++ : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -44(%%a0),%%a0" ++ : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" ++ : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -44(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 20(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFG)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ /* Round 3 */ ++ asm("moveq.l #4, %%d4" : : : "d4"); /* for rotating by 5 */ ++ asm("moveq.l #11, %%d5" : : : "d5"); /* for rotating by 9 */ ++ asm("moveq.l #16, %%d6" : : : "d6"); /* for rotating by 14 */ ++ asm("moveq.l #23, %%d7" : : : "d7"); /* for rotating by 20 */ ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -52(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -52(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 12(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -52(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -8(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ /* Round 4 */ ++ asm("moveq.l #6, %%d4" : : : "d4"); /* for rotating by 6 */ ++ asm("moveq.l #10, %%d5" : : : "d5"); /* for rotating by 10 */ ++ asm("moveq.l #15, %%d6" : : : "d6"); /* for rotating by 15 */ ++ asm("moveq.l #21, %%d7" : : : "d7"); /* for rotating by 21 */ ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -36(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -36(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -36(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -36(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -36(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" ++ : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d4,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea -36(%%a0),%%a0" ++ : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d5,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" ++ : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d6,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFI)); ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_RADR+MCFCAU_CAA) : "a0"); ++ asm("lea 28(%%a0),%%a0" : : : "a0"); ++ asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a3"); ++ asm("cp0ld.l %%d7,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA1)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MDS)); ++ ++ ++ asm("move.l %0, %%a1" : : "m"(hash) : "a1"); ++ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a1");/*a*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA1) : "a1");/*b*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA2) : "a1");/*c*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA3) : "a1");/*d*/ ++ ++ asm("cp0st.l %%d0,-(%%a1),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "a1");/*d*/ ++ asm("cp0st.l %%d0,-(%%a1),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "a1");/*c*/ ++ asm("cp0st.l %%d0,-(%%a1),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA1) : "a1");/*b*/ ++ asm("cp0st.l %%d0,-(%%a1),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CAA) : "a1");/*a*/ ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++static inline void le32_to_cpu_array(u32 *buf, unsigned int words) ++{ ++ while (words--) { ++ __le32_to_cpus(buf); ++ buf++; ++ } ++} ++ ++static inline void cpu_to_le32_array(u32 *buf, unsigned int words) ++{ ++ while (words--) { ++ __cpu_to_le32s(buf); ++ buf++; ++ } ++} ++ ++static int mcfcau_md5_initialization(struct shash_desc *desc) ++{ ++ struct mcfcau_md5_ctx *mctx = shash_desc_ctx(desc); ++ ++ DBG("mcfcau_md5_initialization\n"); ++ mctx->hash[0] = 0x67452301; ++ mctx->hash[1] = 0xefcdab89; ++ mctx->hash[2] = 0x98badcfe; ++ mctx->hash[3] = 0x10325476; ++ mctx->byte_count = 0; ++ ++ return 0; ++} ++ ++static int mcfcau_md5_update(struct shash_desc *desc, ++ const u8 *data, unsigned int len) ++{ ++ struct mcfcau_md5_ctx *mctx = shash_desc_ctx(desc); ++ const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f); ++ ++ DBG("mcfcau_md5_update\n"); ++ mctx->byte_count += len; ++ ++ if (avail > len) { ++ memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), ++ data, len); ++ } else { ++ memcpy((char *)mctx->block + ++ (sizeof(mctx->block) - avail), data, avail); ++ ++ mcfcau_md5_transform(mctx->hash, mctx->block); ++ data += avail; ++ len -= avail; ++ ++ while (len >= sizeof(mctx->block)) { ++ memcpy(mctx->block, data, sizeof(mctx->block)); ++ mcfcau_md5_transform(mctx->hash, mctx->block); ++ data += sizeof(mctx->block); ++ len -= sizeof(mctx->block); ++ } ++ ++ memcpy(mctx->block, data, len); ++ } ++ ++ return 0; ++} ++ ++static int mcfcau_md5_final(struct shash_desc *desc, u8 *out) ++{ ++ struct mcfcau_md5_ctx *mctx = shash_desc_ctx(desc); ++ const unsigned int offset = mctx->byte_count & 0x3f; ++ char *p = (char *)mctx->block + offset; ++ int padding = 56 - (offset + 1); ++ ++ DBG("mcfcau_md5_final\n"); ++ ++ *p++ = 0x80; ++ if (padding < 0) { ++ memset(p, 0x00, padding + sizeof(u64)); ++ mcfcau_md5_transform(mctx->hash, mctx->block); ++ p = (char *)mctx->block; ++ padding = 56; ++ } ++ ++ memset(p, 0, padding); ++ mctx->block[14] = mctx->byte_count << 3; ++ mctx->block[15] = mctx->byte_count >> 29; ++ le32_to_cpu_array(&mctx->block[14], 2); ++ ++ mcfcau_md5_transform(mctx->hash, mctx->block); ++ ++ cpu_to_le32_array(mctx->hash, sizeof(mctx->hash) / sizeof(u32)); ++ memcpy(out, mctx->hash, sizeof(mctx->hash)); ++ memset(mctx, 0, sizeof(*mctx)); ++ ++ return 0; ++} ++ ++static struct shash_alg mcfcau_md5_alg = { ++ .init = mcfcau_md5_initialization, ++ .update = mcfcau_md5_update, ++ .final = mcfcau_md5_final, ++ .digestsize = MCFCAU_MD5_DIGEST_SIZE, ++ .descsize = sizeof(struct mcfcau_md5_ctx), ++ .statesize = sizeof(struct mcfcau_md5_ctx), ++ .base = { ++ .cra_name = "md5", ++ .cra_driver_name = "md5-mcfcau", ++ .cra_blocksize = MCFCAU_MD5_HMAC_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_SHASH, ++ .cra_priority = MCFCAU_CRA_PRIORITY, ++ .cra_module = THIS_MODULE ++ } ++}; ++ ++static int __init mcfcau_md5_init(void) ++{ ++ int ret = 0; ++ ++ ret = crypto_register_shash(&mcfcau_md5_alg); ++ printk(KERN_INFO MCFCAU_MD5_DRIVER_DESC " " ++ MCFCAU_MD5_DRIVER_VERSION " %s.\n", ++ ret ? "failed" : "registered"); ++ return ret; ++} ++ ++static void __exit mcfcau_md5_exit(void) ++{ ++ crypto_unregister_shash(&mcfcau_md5_alg); ++ printk(KERN_INFO MCFCAU_MD5_DRIVER_DESC " " ++ MCFCAU_MD5_DRIVER_VERSION " unregistered.\n"); ++} ++ ++module_init(mcfcau_md5_init); ++module_exit(mcfcau_md5_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION(MCFCAU_MD5_DRIVER_DESC); ++MODULE_AUTHOR("Andrey Butok"); +--- /dev/null ++++ b/drivers/crypto/mcfcau-sha1.c +@@ -0,0 +1,331 @@ ++/*************************************************************************** ++ * mcfcau-sha1.c - Implementation of SHA1 Secure Hash Algorithm ++ * for Freescale ColdFire Cryptographic Acceleration Unit (CAU). ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Shrek Wu B16972@freescale.com ++ * Alison Wang b18965@freescale.com ++ * ++ * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.01 15 October 2007 Andrey Butok ++ * Initial Release - developed on 2.6.20 Linux kernel. ++ */ ++ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/mm.h> ++#include <linux/crypto.h> ++#include <linux/types.h> ++#include <crypto/algapi.h> ++#include <crypto/hash.h> ++#include <crypto/internal/hash.h> ++ ++#include "mcfcau.h" ++ ++#define MCFCAU_SHA1_DIGEST_WORDS (5) ++#define MCFCAU_SHA1_WORKSPACE_WORDS (80) ++ ++#define MCFCAU_SHA1_DIGEST_SIZE (20) ++#define MCFCAU_SHA1_HMAC_BLOCK_SIZE (64) ++ ++#define MCFCAU_SHA1_DRIVER_DESC "SHA1 ColdFire CAU driver" ++#define MCFCAU_SHA1_DRIVER_VERSION "v0.01" ++ ++static const u32 K[4] = {0x5A827999L, /* Rounds 0-19: sqrt(2) * 2^30 */ ++ 0x6ED9EBA1L, /* Rounds 20-39: sqrt(3) * 2^30 */ ++ 0x8F1BBCDCL, /* Rounds 40-59: sqrt(5) * 2^30 */ ++ 0xCA62C1D6L}; /* Rounds 60-79: sqrt(10) * 2^30 */ ++ ++struct mcfcau_sha1_ctx { ++ u64 count; ++ u32 state[5]; ++ u8 buffer[64]; ++}; ++ ++static void mcfcau_sha1_transform(__u32 *digest, const char *in, __u32 *W) ++{ ++ int i; ++ u32 *tmp_p; ++ unsigned long iflags; ++ ++ /* (a) Devide M(i) into 16 words W */ ++ for (i = 0; i < 16; i++) ++ W[i] = ((const u32 *)in)[i]; ++ ++ /* (b) W[i+16] = S^1(W[i+13] ^ W[i+8] ^ W[i+2] ^ W[i]) */ ++ tmp_p = &W[16]; ++ ++ spin_lock_irqsave(&mcfcau_lock, iflags); ++ asm("move.l %0, %%a0" : : "m"(tmp_p) : "a0"); ++ asm("moveq.l #1, %%d3" : : : "d3"); ++ ++ for (i = 0; i < 64; i++) { ++ asm("cp0ld.l -64(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0)); ++ asm("cp0ld.l -56(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0)); ++ asm("cp0ld.l -32(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0)); ++ asm("cp0ld.l -12(%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_XOR+MCFCAU_CA0)); ++ asm("cp0ld.l %%d3,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CA0) : "d3"); ++ asm("cp0st.l %%d0,(%%a0)+,#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA0)); ++ } ++ ++ /* (c) */ ++ asm("move.l %0, %%a0" : : "m"(digest) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA0) : "a0"); /* a */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA1) : "a0"); /* b */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA2) : "a0"); /* c */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA3) : "a0"); /* d */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_LDR+MCFCAU_CA4) : "a0"); /* e */ ++ ++ /* (d) */ ++ asm("moveq.l #5, %%d0" : : : "d0"); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_MVRA+MCFCAU_CA0)); ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ROTL+MCFCAU_CAA)); /*S^5(A)*/ ++ ++ tmp_p = (u32 *)K; ++ asm("move.l %0, %%a0" : : "m"(tmp_p) : "a0"); ++ asm("move.l %0, %%a1" : : "m"(W) : "a1"); ++ ++ for (i = 0; i < 20; i++) { ++ /* t = f1(b, c, d) + K1 + rol32(a, 5) + e + W[i]; */ ++ /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFC)); /*f(b,c,d)*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/ ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a1"); /*+W*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_SHS)); ++ } ++ ++ asm("add.l #4,%%a0" : : : "a0"); /* update K */ ++ ++ for (; i < 40; i++) { ++ /* t = f2(b, c, d) + K2 + rol32(a, 5) + e + W[i]; */ ++ /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); /*f(b,c,d)*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/ ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a1"); /*+W*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_SHS)); ++ } ++ ++ asm("add.l #4,%%a0" : : : "a0"); /* update K */ ++ ++ for (; i < 60; i++) { ++ /* t = f3(b, c, d) + K3 + rol32(a, 5) + e + W[i]; */ ++ /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFM)); /*f(b,c,d)*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/ ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a1"); /*+W*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_SHS)); ++ } ++ ++ asm("add.l #4,%%a0" : : : "a0"); /* update K */ ++ ++ for (; i < 80; i++) { ++ /* t = f2(b, c, d) + K4 + rol32(a, 5) + e + W[i]; */ ++ /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_HASH+MCFCAU_HFH)); /*f(b,c,d)*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/ ++ asm("cp0ld.l (%%a0),%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/ ++ asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CAA) : "a1"); /*+W*/ ++ asm("cp0ld.l %%d0,%%d0,#1,%0" ++ : : "n"(MCFCAU_SHS)); ++ } ++ ++ /* (e) */ ++ asm("move.l %0, %%a0" : : "m"(digest) : "a0"); ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA0) : "a0"); /* +a */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA1) : "a0"); /* +b */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA2) : "a0"); /* +c */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA3) : "a0"); /* +d */ ++ asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ++ : : "n"(MCFCAU_ADR+MCFCAU_CA4) : "a0"); /* +e */ ++ ++ asm("cp0st.l %%d0,-(%%a0),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA4) : "a0"); ++ asm("cp0st.l %%d0,-(%%a0),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA3) : "a0"); ++ asm("cp0st.l %%d0,-(%%a0),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA2) : "a0"); ++ asm("cp0st.l %%d0,-(%%a0),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA1) : "a0"); ++ asm("cp0st.l %%d0,-(%%a0),#1,%0" ++ : : "n"(MCFCAU_STR+MCFCAU_CA0) : "a0"); ++ spin_unlock_irqrestore(&mcfcau_lock, iflags); ++} ++ ++static int mcfcau_sha1_init(struct shash_desc *desc) ++{ ++ struct mcfcau_sha1_ctx *sctx = shash_desc_ctx(desc); ++ static const struct mcfcau_sha1_ctx initstate = { ++ 0, ++ { 0x67452301, 0xEFCDAB89, 0x98BADCFE, 0x10325476, 0xC3D2E1F0 }, ++ { 0, } ++ }; ++ ++ DBG("mcfcau_sha1_init\n"); ++ *sctx = initstate; ++ ++ return 0; ++} ++ ++static int mcfcau_sha1_update(struct shash_desc *desc, const u8 *data, ++ unsigned int len) ++{ ++ struct mcfcau_sha1_ctx *sctx = shash_desc_ctx(desc); ++ unsigned int partial, done; ++ const u8 *src; ++ ++ DBG("mcfcau_sha1_update\n"); ++ partial = sctx->count & 0x3f; ++ sctx->count += len; ++ done = 0; ++ src = data; ++ ++ if ((partial + len) > 63) { ++ u32 temp[MCFCAU_SHA1_WORKSPACE_WORDS]; ++ ++ if (partial) { ++ done = -partial; ++ memcpy(sctx->buffer + partial, data, done + 64); ++ src = sctx->buffer; ++ } ++ ++ do { ++ mcfcau_sha1_transform(sctx->state, src, temp); ++ done += 64; ++ src = data + done; ++ } while (done + 63 < len); ++ ++ memset(temp, 0, sizeof(temp)); ++ partial = 0; ++ } ++ memcpy(sctx->buffer + partial, src, len - done); ++ return 0; ++} ++ ++ ++/* Add padding and return the message digest. */ ++static int mcfcau_sha1_final(struct shash_desc *desc, u8 *out) ++{ ++ struct mcfcau_sha1_ctx *sctx = shash_desc_ctx(desc); ++ u32 *dst = (u32 *)out; ++ u32 i, index, padlen; ++ u64 bits; ++ static const u8 padding[64] = { 0x80, }; ++ ++ DBG("mcfcau_sha1_final\n"); ++ bits = sctx->count << 3; ++ ++ /* Pad out to 56 mod 64 */ ++ index = sctx->count & 0x3f; ++ padlen = (index < 56) ? (56 - index) : ((64+56) - index); ++ mcfcau_sha1_update(desc, padding, padlen); ++ ++ /* Append length */ ++ mcfcau_sha1_update(desc, (const u8 *)&bits, sizeof(bits)); ++ ++ /* Store state in digest */ ++ for (i = 0; i < 5; i++) ++ dst[i] = sctx->state[i]; ++ ++ /* Wipe context */ ++ memset(sctx, 0, sizeof *sctx); ++ ++ return 0; ++} ++ ++static struct shash_alg mcfcau_sha1_alg = { ++ .init = mcfcau_sha1_init, ++ .update = mcfcau_sha1_update, ++ .final = mcfcau_sha1_final, ++ .digestsize = MCFCAU_SHA1_DIGEST_SIZE, ++ .descsize = sizeof(struct mcfcau_sha1_ctx), ++ .statesize = sizeof(struct mcfcau_sha1_ctx), ++ .base = { ++ .cra_name = "sha1", ++ .cra_driver_name = "sha1-mcfcau", ++ .cra_priority = MCFCAU_CRA_PRIORITY, ++ .cra_flags = CRYPTO_ALG_TYPE_SHASH, ++ .cra_blocksize = MCFCAU_SHA1_HMAC_BLOCK_SIZE, ++ .cra_module = THIS_MODULE, ++ .cra_alignmask = 3, ++ } ++}; ++ ++static int __init init(void) ++{ ++ int ret = crypto_register_shash(&mcfcau_sha1_alg); ++ printk(KERN_INFO MCFCAU_SHA1_DRIVER_DESC " " ++ MCFCAU_SHA1_DRIVER_VERSION " %s.\n", ++ ret ? "failed" : "registered"); ++ return ret; ++} ++ ++static void __exit fini(void) ++{ ++ crypto_unregister_shash(&mcfcau_sha1_alg); ++ printk(KERN_INFO MCFCAU_SHA1_DRIVER_DESC " " ++ MCFCAU_SHA1_DRIVER_VERSION " unregistered.\n"); ++} ++ ++module_init(init); ++module_exit(fini); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION(MCFCAU_SHA1_DRIVER_DESC); ++MODULE_AUTHOR("Andrey Butok"); +--- /dev/null ++++ b/drivers/crypto/mcfcau.c +@@ -0,0 +1,33 @@ ++/*************************************************************************** ++ * mcfcau.c - Implementation of DES & Triple DES EDE Cipher Algorithms ++ * for Freescale ColdFire Cryptographic Acceleration Unit (CAU). ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Shrek Wu B16972@freescale.com ++ * ++ * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.01 28 September 2006 Andrey Butok ++ * Initial Release - developed on 2.6.20 Linux kernel. ++ */ ++#include <linux/module.h> ++ ++DEFINE_SPINLOCK(mcfcau_lock); ++EXPORT_SYMBOL(mcfcau_lock); +--- /dev/null ++++ b/drivers/crypto/mcfcau.h +@@ -0,0 +1,101 @@ ++/*************************************************************************** ++ * mcfcau.h - Common header file for Freescale ColdFire ++ * Cryptographic Acceleration Unit (CAU) drivers. ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Andrey Butok ++ * Shrek Wu B16972@freescale.com ++ * ++ * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ *************************************************************************** ++ * Changes: ++ * v0.01 14 August 2007 Andrey Butok ++ */ ++ ++#ifndef MCFCAU_H ++#define MCFCAU_H ++ ++#include <linux/spinlock.h> ++ ++/* CAU Registers (CAx) */ ++#define MCFCAU_CASR (0x0) ++#define MCFCAU_CAA (0x1) ++#define MCFCAU_CA0 (0x2) ++#define MCFCAU_CA1 (0x3) ++#define MCFCAU_CA2 (0x4) ++#define MCFCAU_CA3 (0x5) ++#define MCFCAU_CA4 (0x6) ++#define MCFCAU_CA5 (0x7) ++ ++ /* CAU Commands */ ++#define MCFCAU_CNOP (0x000) ++#define MCFCAU_LDR (0x010) ++#define MCFCAU_STR (0x020) ++#define MCFCAU_ADR (0x030) ++#define MCFCAU_RADR (0x040) ++#define MCFCAU_ADRA (0x050) ++#define MCFCAU_XOR (0x060) ++#define MCFCAU_ROTL (0x070) ++#define MCFCAU_MVRA (0x080) ++#define MCFCAU_MVAR (0x090) ++#define MCFCAU_AESS (0x0A0) ++#define MCFCAU_AESIS (0x0B0) ++#define MCFCAU_AESC (0x0C0) ++#define MCFCAU_AESIC (0x0D0) ++#define MCFCAU_AESR (0x0E0) ++#define MCFCAU_AESIR (0x0F0) ++#define MCFCAU_DESR (0x100) ++#define MCFCAU_DESK (0x110) ++#define MCFCAU_HASH (0x120) ++#define MCFCAU_SHS (0x130) ++#define MCFCAU_MDS (0x140) ++#define MCFCAU_ILL (0x1F0) ++ ++/* DESR Fields */ ++#define MCFCAU_IP (0x08) /* initial permutation */ ++#define MCFCAU_FP (0x04) /* final permutation */ ++#define MCFCAU_KSL1 (0x00) /* key schedule left 1 bit */ ++#define MCFCAU_KSL2 (0x01) /* key schedule left 2 bits */ ++#define MCFCAU_KSR1 (0x02) /* key schedule right 1 bit */ ++#define MCFCAU_KSR2 (0x03) /* key schedule right 2 bits */ ++ ++/* DESK Field */ ++#define MCFCAU_DC (0x01) /* decrypt key schedule */ ++#define MCFCAU_CP (0x02) /* check parity */ ++ ++/* HASH Functions Codes */ ++#define MCFCAU_HFF (0x0) /* MD5 F() CA1&CA2 | ~CA1&CA3 */ ++#define MCFCAU_HFG (0x1) /* MD5 G() CA1&CA3 | CA2&~CA3 */ ++#define MCFCAU_HFH (0x2) /* MD5 H(), SHA Parity() CA1^CA2^CA3 */ ++#define MCFCAU_HFI (0x3) /* MD5 I() CA2^(CA1|~CA3) */ ++#define MCFCAU_HFC (0x4) /* SHA Ch() CA1&CA2 ^ ~CA1&CA3 */ ++#define MCFCAU_HFM (0x5) ++/* SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3 */ ++ ++#define MCFCAU_CRA_PRIORITY (300) ++ ++extern spinlock_t mcfcau_lock; ++ ++#ifdef DEBUG ++#define DBG(fmt, args...) printk(KERN_INFO "[%s] " fmt ,\ ++ __func__, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#endif diff --git a/target/linux/coldfire/patches/012-Add-vDSO-support-for-Coldfire-platform.patch b/target/linux/coldfire/patches/012-Add-vDSO-support-for-Coldfire-platform.patch new file mode 100644 index 000000000..8a7ead563 --- /dev/null +++ b/target/linux/coldfire/patches/012-Add-vDSO-support-for-Coldfire-platform.patch @@ -0,0 +1,497 @@ +From 1ba9968246337836bf0acdbf7733a628da5c5e42 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:42 +0800 +Subject: [PATCH 12/52] Add vDSO support for Coldfire platform + +This patch adds vDSO support for Coldfire platform. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/common/entry.S | 36 ++++++++++ + arch/m68k/coldfire/vdso/Makefile | 46 +++++++++++++ + arch/m68k/coldfire/vdso/vdso-bin.S | 14 ++++ + arch/m68k/coldfire/vdso/vdso-lib.S | 57 ++++++++++++++++ + arch/m68k/coldfire/vdso/vdso-note.S | 27 ++++++++ + arch/m68k/coldfire/vdso/vdso.c | 124 +++++++++++++++++++++++++++++++++++ + arch/m68k/coldfire/vdso/vdso.lds.S | 89 +++++++++++++++++++++++++ + arch/m68k/include/asm/auxvec.h | 9 +++ + arch/m68k/mm/init.c | 3 + + 9 files changed, 405 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/vdso/Makefile + create mode 100644 arch/m68k/coldfire/vdso/vdso-bin.S + create mode 100644 arch/m68k/coldfire/vdso/vdso-lib.S + create mode 100644 arch/m68k/coldfire/vdso/vdso-note.S + create mode 100644 arch/m68k/coldfire/vdso/vdso.c + create mode 100644 arch/m68k/coldfire/vdso/vdso.lds.S + +--- a/arch/m68k/coldfire/common/entry.S ++++ b/arch/m68k/coldfire/common/entry.S +@@ -69,6 +69,9 @@ ENTRY(buserr) + movew #0x2700,%sr /* lock interrupts */ + #endif + SAVE_ALL_INT ++#ifdef CONFIG_VDSO ++ jsr check_vdso_atomic_cmpxchg_32 ++#endif + #ifdef CONFIG_COLDFIRE_FOO + movew PT_0FF_SR(%sp),%d3 /* get original %sr */ + oril #0x2000,%d3 /* set supervisor mode in it */ +@@ -82,6 +85,9 @@ ENTRY(buserr) + + ENTRY(trap) + SAVE_ALL_INT ++#ifdef CONFIG_VDSO ++ jsr check_vdso_atomic_cmpxchg_32 ++#endif + GET_CURRENT(%d0) + movel %sp,%sp@- /* stack frame pointer argument */ + jsr trap_c +@@ -213,6 +219,9 @@ do_delayed_trace: + */ + ENTRY(inthandler) + SAVE_ALL_INT ++#ifdef CONFIG_VDSO ++ jsr check_vdso_atomic_cmpxchg_32 ++#endif + GET_CURRENT(%d0) + movel %curptr@(TASK_INFO+TINFO_PREEMPT),%d0 + addil #0x10000,%d0 +@@ -398,8 +407,35 @@ resume: + movew %a1@(TASK_THREAD+THREAD_SR),%d0 + movew %d0,%sr + ++#ifdef CONFIG_VDSO ++ /* save thread pointer */ ++ lea _vdso_tp,%a0 ++ movel (%a0),%a0 ++ movel %a1@(TASK_INFO+TINFO_TP_VALUE),(%a0) ++#endif + rts + ++#ifdef CONFIG_VDSO ++/* if interrupted PC is between 0x5fffe40c to 0x5ffffe412 */ ++/* then set PC back to 0x5fffe40c (start addr of __kernel_atomic_cmpxchg_32) */ ++/* note: these absolute addresses depend on vdso-lib.S and vdso.lds.S */ ++ENTRY(check_vdso_atomic_cmpxchg_32) ++ movel %sp@(PT_OFF_PC),%d0 ++ cmpil #0x5fffe414,%d0 /* __kernel_atomic_cmpxchg_32: line 4 */ ++ ble label1 ++ cmpil #0x5fffe412,%d0 /* __kernel_atomic_cmpxchg_32: line 3 */ ++ beql label0 ++ cmpil #0x5fffe40e,%d0 /* __kernel_atomic_cmpxchg_32: line 2 */ ++ beql label0 ++ jra label1 ++label0: ++ /* __kernel_atomic_cmpxchg_32: line 1 */ ++ movel #0x5fffe40c,%d0 ++ movel %d0,%sp@(PT_OFF_PC) ++label1: ++ rts ++#endif ++ + .data + ALIGN + sys_call_table: +--- /dev/null ++++ b/arch/m68k/coldfire/vdso/Makefile +@@ -0,0 +1,46 @@ ++# ++# Makefile for arch/m68k/coldfire/vdso with special rules ++# for building the DSO lib ++# ++# Based on arch/sh/kernel/vsyscall/Makefile ++# ++# Kurt Mahan <kmahan@freescale.com> ++# ++ ++obj-y := vdso.o vdso-bin.o ++ ++$(obj)/vdso-bin.o: $(obj)/vdso.lds $(obj)/vdso-lib.so ++ ++# ++# The DSO Lib ++# ++ ++# special linker script for building DSO images ++quiet_cmd_vdso = VDSO $@ ++ cmd_vdso = $(LD) -nostdlib --eh-frame-hdr $(SYSCFLAGS_$(@F)) \ ++ -T $(obj)/vdso.lds $^ -o $@ ++ ++vdso-flags = -shared -s -soname=linux-gate.so.1 ++ ++SYSCFLAGS_vdso-lib.so = $(vdso-flags) ++ ++$(obj)/vdso-lib.so: $(obj)/vdso-lib.o $(obj)/vdso-note.o ++ $(call if_changed,vdso) ++ ++$(obj)/vdso.lds: $(srctree)/arch/m68k/coldfire/vdso/vdso.lds.S ++ cp $< $@ ++ ++# ++# Create a special relocatable object that should mirror the ++# symbol table and layout of the linked DSO lib. With ld -R ++# these symbols can be refered to in the kernel code rather ++# than as hand-coded addresses ++# ++# extra-y += vdso-syms.o ++# $(obj)/built-in.o: $(obj)/vdso-syms.o ++# $(obj)/built-in.o: ld_flags += -R (obj)/vdso-syms.o ++ ++# SYSCFLAGS_vdso-syms.o = -r ++# $(obj)/vdso-syms.o: $(src)/vdso.lds \ ++# $(obj)/vdso-lib.o $(obj)/vdso-note.o FORCE ++# $(call if_changed,vdso) +--- /dev/null ++++ b/arch/m68k/coldfire/vdso/vdso-bin.S +@@ -0,0 +1,14 @@ ++/* ++ * Setup vdso lib (.so) as binary image. ++ */ ++ ++#include <linux/init.h> ++ ++__INITDATA ++ ++ .globl vdso_bin_start, vdso_bin_end ++vdso_bin_start: ++ .incbin "arch/m68k/coldfire/vdso/vdso-lib.so" ++vdso_bin_end: ++ ++__FINIT +--- /dev/null ++++ b/arch/m68k/coldfire/vdso/vdso-lib.S +@@ -0,0 +1,57 @@ ++/* ++ * VDSO userspace code ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/linkage.h> ++#include <asm/unistd.h> ++ ++ .text ++/* ++ * Read the thread pointer into A0 (and D0, for compatibility). ++ */ ++ENTRY(__kernel_read_tp) ++ .cfi_startproc ++ lea kuser_vdso_tp,%a0 ++ movel (%a0), %d0 ++ movel %d0,%a0 ++ rts ++ .cfi_endproc ++ .size __kernel_read_tp,.-__kernel_read_tp ++ ++/* ++ * Atomic compare exchange. Can not clobber any registers ++ * other than conditional codes. ++ */ ++ENTRY(__kernel_atomic_cmpxchg_32) ++ .cfi_startproc ++ cmpl (%a0),%d0 ++ bne label0 ++ movel %d1, (%a0) ++ jmp label1 ++label0: ++ movel (%a0),%d0 ++label1: ++ rts ++ .cfi_endproc ++ .size __kernel_atomic_cmpxchg_32,.-__kernel_atomic_cmpxchg_32 ++ ++/* ++ * Atomic memory barrier. Can not clobber any registers ++ * other than condition codes. ++ */ ++ENTRY(__kernel_atomic_barrier) ++ .cfi_startproc ++ /* no code needed for uniprocs */ ++ rts ++ .cfi_endproc ++ .size __kernel_atomic_barrier,.-__kernel_atomic_barrier ++ ++ .previous +--- /dev/null ++++ b/arch/m68k/coldfire/vdso/vdso-note.S +@@ -0,0 +1,27 @@ ++/* ++ * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text. ++ * Here we can supply some information useful to userland. ++ * ++ * Based on arch/sh/kernel/vsyscall/vsyscall-note.S ++ */ ++ ++#include <linux/uts.h> ++#include <linux/version.h> ++ ++#define ASM_ELF_NOTE_BEGIN(name, flags, vendor, type) \ ++ .section name, flags; \ ++ .balign 4; \ ++ .long 1f - 0f; /* name length */ \ ++ .long 3f - 2f; /* data length */ \ ++ .long type; /* note type */ \ ++0: .asciz vendor; /* vendor name */ \ ++1: .balign 4; \ ++2: ++ ++#define ASM_ELF_NOTE_END \ ++3: .balign 4; /* pad out section */ \ ++ .previous ++ ++ ASM_ELF_NOTE_BEGIN(".note.kernel-version", "a", UTS_SYSNAME, 0) ++ .long LINUX_VERSION_CODE ++ ASM_ELF_NOTE_END +--- /dev/null ++++ b/arch/m68k/coldfire/vdso/vdso.c +@@ -0,0 +1,124 @@ ++/* ++ * arch/m68k/coldfire/vdso/vdso.c ++ * ++ * Based on arch/sh/kernel/vsyscall/vsyscall.c ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/mm.h> ++#include <linux/slab.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/gfp.h> ++#include <linux/module.h> ++#include <linux/elf.h> ++#include <linux/sched.h> ++#include <linux/err.h> ++ ++/* Mapping vDSO at the default address (what would've been returned ++ * if VDSO_MBASE was 0) makes it impossible to extend data segment ++ * (through brk()) for static binaries. The vDSO fits into one page, ++ * so map it just before TASK_UNMAPPED_BASE. ++ */ ++#define VDSO_MBASE (TASK_UNMAPPED_BASE - PAGE_SIZE) ++#define VDSO_VAR_OFFSET 4096 ++ ++unsigned int vdso_enabled = 1; ++EXPORT_SYMBOL_GPL(vdso_enabled); ++ ++static struct page *vdso_pages[1]; ++ ++/* _vdso_var_start: vdso_page_start + offset_4K */ ++/* it's used to save key values from kernel */ ++void *_vdso_var_start; ++void *_vdso_tp; ++ ++extern const char vdso_bin_start, vdso_bin_end; ++ ++int __init vdso_init(void) ++{ ++ void *vdso_page = (void *)get_zeroed_page(GFP_ATOMIC); ++ vdso_pages[0] = virt_to_page(vdso_page); ++ ++ _vdso_var_start = (void *)(vdso_page + VDSO_VAR_OFFSET); ++ _vdso_tp = _vdso_var_start; ++ ++ printk(KERN_INFO "** VDSO_INIT\n"); ++ ++ /* copy dso bin in */ ++ memcpy(vdso_page, ++ &vdso_bin_start, &vdso_bin_end - &vdso_bin_start); ++ ++ return 0; ++} ++ ++/* setup VMA at program startup for the vdso page */ ++int arch_setup_additional_pages(struct linux_binprm *bprm, ++ int executable_stack) ++{ ++ struct mm_struct *mm = current->mm; ++ unsigned long addr; ++ int ret; ++ ++ current->mm->context.vdso = 0; ++ ++ down_write(&mm->mmap_sem); ++ addr = get_unmapped_area(NULL, VDSO_MBASE, PAGE_SIZE, 0, 0); ++ if (IS_ERR_VALUE(addr)) { ++ ret = addr; ++ goto up_fail; ++ } ++ ++ ret = install_special_mapping(mm, addr, PAGE_SIZE, ++ VM_READ | VM_EXEC | ++ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | ++ VM_ALWAYSDUMP, ++ vdso_pages); ++ ++ if (unlikely(ret)) ++ goto up_fail; ++ ++ current->mm->context.vdso = (void *)addr; ++ ++up_fail: ++#ifdef DEBUG ++ printk(KERN_DEBUG "arch_setup_additional_pages: addr: %lx; ret: %d\n", ++ addr, ret); ++#endif ++ ++ up_write(&mm->mmap_sem); ++ return ret; ++} ++ ++/* ++ * check vma name ++ */ ++const char *arch_vma_name(struct vm_area_struct *vma) ++{ ++ if (vma->vm_mm && vma->vm_start == (long)vma->vm_mm->context.vdso) ++ return "[vdso]"; ++ ++ return NULL; ++} ++ ++struct vm_area_struct *get_gate_vma(struct task_struct *task) ++{ ++ return NULL; ++} ++ ++int in_gate_area(struct task_struct *task, unsigned long address) ++{ ++ return 0; ++} ++ ++int in_gate_area_no_task(unsigned long address) ++{ ++ return 0; ++} +--- /dev/null ++++ b/arch/m68k/coldfire/vdso/vdso.lds.S +@@ -0,0 +1,89 @@ ++/* ++ * Linker script for vdso DSO. The vdso page is an ELF shared ++ * object prelinked to its virtual address, and with only one read-only ++ * segment (that fits in one page). This script controls its layout. ++ * ++ * Based on arch/sh/kernel/vsyscall/vsyscall.lds.S ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", "elf32-m68k") ++OUTPUT_ARCH(m68k) ++ ++/* The ELF entry point can be used to set the AT_SYSINFO value. */ ++ENTRY(__kernel_read_tp); ++ENTRY(__kernel_atomic_cmpxchg_32); ++ENTRY(__kernel_atomic_barrier); ++ ++SECTIONS ++{ ++ . = 0x5fffe000 + SIZEOF_HEADERS; ++ ++ .hash : { *(.hash) } :text ++ .gnu.hash : { *(.gnu.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .gnu.version : { *(.gnu.version) } ++ .gnu.version_d : { *(.gnu.version_d) } ++ .gnu.version_r : { *(.gnu.version_r) } ++ ++ /* ++ * This linker script is used both with -r and with -shared. ++ * For the layouts to match, we need to skip more than enough ++ * space for the dynamic symbol table et al. If this amount ++ * is insufficient, ld -shared will barf. Just increase it here. ++ */ ++ . = 0x5fffe000 + 0x400; ++ ++ .text : { *(.text) } :text ++ .note : { *(.note.*) } :text :note ++ .eh_frame_hdr : { *(.eh_frame_hdr ) } :text :eh_frame_hdr ++ .eh_frame : { ++ KEEP (*(.eh_frame)) ++ LONG (0) ++ } :text ++ .dynamic : { *(.dynamic) } :text :dynamic ++ .useless : { ++ *(.got.plt) *(.got) ++ *(.data .data.* .gnu.linkonce.d.*) ++ *(.dynbss) ++ *(.bss .bss.* .gnu.linkonce.b.*) ++ } :text ++ ++ . = 0x5fffe000 + 0x1000; ++ kuser_vdso_tp = .; ++} ++ ++/* ++ * We must supply the ELF program headers explicitly to get just one ++ * PT_LOAD segment, and set the flags explicitly to make segments read-only. ++ */ ++PHDRS ++{ ++ text PT_LOAD FILEHDR PHDRS FLAGS(5); /* PF_R|PF_X */ ++ dynamic PT_DYNAMIC FLAGS(4); /* PF_R */ ++ note PT_NOTE FLAGS(4); /* PF_R */ ++ eh_frame_hdr PT_GNU_EH_FRAME; ++} ++ ++/* ++ * This controls what symbols we export from the DSO. ++ */ ++VERSION ++{ ++ LINUX_2.6 { ++ global: ++ __kernel_read_tp; ++ __kernel_atomic_cmpxchg_32; ++ __kernel_atomic_barrier; ++ ++ local: *; ++ }; ++} +--- a/arch/m68k/include/asm/auxvec.h ++++ b/arch/m68k/include/asm/auxvec.h +@@ -1,4 +1,13 @@ + #ifndef __ASMm68k_AUXVEC_H + #define __ASMm68k_AUXVEC_H ++/* ++ * Architecture-neutral AT_ values in 0-17, leave some room ++ * for more of them. ++ */ ++ ++#ifdef CONFIG_VDSO ++/* Entry point to the vdso page */ ++#define AT_SYSINFO_EHDR 33 ++#endif + + #endif +--- a/arch/m68k/mm/init.c ++++ b/arch/m68k/mm/init.c +@@ -39,6 +39,9 @@ + #include <asm/sections.h> + #include <asm/tlb.h> + ++#ifdef CONFIG_VDSO ++int vdso_init(void); ++#endif + + DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + diff --git a/target/linux/coldfire/patches/013-Add-MCD-DMA-driver-for-MCF547x-MCF548x.patch b/target/linux/coldfire/patches/013-Add-MCD-DMA-driver-for-MCF547x-MCF548x.patch new file mode 100644 index 000000000..3cc8555f0 --- /dev/null +++ b/target/linux/coldfire/patches/013-Add-MCD-DMA-driver-for-MCF547x-MCF548x.patch @@ -0,0 +1,5318 @@ +From de2bd6eff9a9f20c6c997b5384c8e81720d9d659 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:43 +0800 +Subject: [PATCH 13/52] Add MCD DMA driver for MCF547x/MCF548x + +Add MCD DMA driver for MCF547x/MCF548x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m547x/dma.c | 518 ++++++++ + arch/m68k/include/asm/MCD_dma.h | 434 +++++++ + drivers/dma/MCD_dma.h | 431 +++++++ + drivers/dma/MCD_dmaApi.c | 1043 +++++++++++++++++ + drivers/dma/MCD_progCheck.h | 29 + + drivers/dma/MCD_tasks.c | 2457 +++++++++++++++++++++++++++++++++++++++ + drivers/dma/MCD_tasksInit.c | 271 +++++ + drivers/dma/MCD_tasksInit.h | 84 ++ + 8 files changed, 5267 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m547x/dma.c + create mode 100644 arch/m68k/include/asm/MCD_dma.h + create mode 100644 drivers/dma/MCD_dma.h + create mode 100644 drivers/dma/MCD_dmaApi.c + create mode 100644 drivers/dma/MCD_progCheck.h + create mode 100644 drivers/dma/MCD_tasks.c + create mode 100644 drivers/dma/MCD_tasksInit.c + create mode 100644 drivers/dma/MCD_tasksInit.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/dma.c +@@ -0,0 +1,518 @@ ++/* ++ * arch/m68k/coldfire/m547x/dma.c ++ * ++ * Coldfire M547x/M548x DMA ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This code is based on patches from the Freescale M547x_8x BSP ++ * release mcf547x_8x-20070107-ltib.iso ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/mm.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <asm/io.h> ++#include <asm/irq.h> ++#include <asm/dma.h> ++#include <asm/coldfire.h> ++#include <asm/m5485sram.h> ++#include <asm/mcfsim.h> ++#include <asm/MCD_dma.h> ++ ++/* ++ * This global keeps track of which initiators have been ++ * used of the available assignments. Initiators 0-15 are ++ * hardwired. Initiators 16-31 are multiplexed and controlled ++ * via the Initiatior Mux Control Registe (IMCR). The ++ * assigned requestor is stored with the associated initiator ++ * number. ++ */ ++static int used_reqs[32] = { ++ DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0, ++ DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1, ++ DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX, ++ DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, 0 ++}; ++ ++/* ++ * This global keeps track of which channels have been assigned ++ * to tasks. This methology assumes that no single initiator ++ * will be tied to more than one task/channel ++ */ ++static char used_channel[16] = { ++ -1, -1, -1, -1, -1, -1, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1 ++}; ++ ++unsigned int connected_channel[16] = { ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0 ++}; ++ ++/** ++ * dma_set_initiator - enable initiator ++ * @initiator: initiator identifier ++ * ++ * Returns 0 of successful, non-zero otherwise ++ * ++ * Attempt to enable the provided Initiator in the Initiator ++ * Mux Control Register. ++ */ ++int dma_set_initiator(int initiator) ++{ ++ switch (initiator) { ++ case DMA_ALWAYS: ++ case DMA_DSPI_RX: ++ case DMA_DSPI_TX: ++ case DMA_DREQ0: ++ case DMA_PSC0_RX: ++ case DMA_PSC0_TX: ++ case DMA_USBEP0: ++ case DMA_USBEP1: ++ case DMA_USBEP2: ++ case DMA_USBEP3: ++ case DMA_PCI_TX: ++ case DMA_PCI_RX: ++ case DMA_PSC1_RX: ++ case DMA_PSC1_TX: ++ case DMA_I2C_RX: ++ case DMA_I2C_TX: ++ /* ++ * These initiators are always active ++ */ ++ break; ++ ++ case DMA_FEC0_RX: ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3)) ++ | MCF_DMA_IMCR_SRC16_FEC0RX; ++ used_reqs[16] = DMA_FEC0_RX; ++ break; ++ ++ case DMA_FEC0_TX: ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3)) ++ | MCF_DMA_IMCR_SRC17_FEC0TX; ++ used_reqs[17] = DMA_FEC0_TX; ++ break; ++ ++ case DMA_FEC1_RX: ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3)) ++ | MCF_DMA_IMCR_SRC20_FEC1RX; ++ used_reqs[20] = DMA_FEC1_RX; ++ break; ++ ++ case DMA_FEC1_TX: ++ if (used_reqs[21] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) ++ | MCF_DMA_IMCR_SRC21_FEC1TX; ++ used_reqs[21] = DMA_FEC1_TX; ++ } else if (used_reqs[25] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) ++ | MCF_DMA_IMCR_SRC25_FEC1TX; ++ used_reqs[25] = DMA_FEC1_TX; ++ } else if (used_reqs[31] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) ++ | MCF_DMA_IMCR_SRC31_FEC1TX; ++ used_reqs[31] = DMA_FEC1_TX; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_DREQ1: ++ if (used_reqs[29] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) ++ | MCF_DMA_IMCR_SRC29_DREQ1; ++ used_reqs[29] = DMA_DREQ1; ++ } else if (used_reqs[21] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) ++ | MCF_DMA_IMCR_SRC21_DREQ1; ++ used_reqs[21] = DMA_DREQ1; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM0: ++ if (used_reqs[24] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3)) ++ | MCF_DMA_IMCR_SRC24_CTM0; ++ used_reqs[24] = DMA_CTM0; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM1: ++ if (used_reqs[25] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) ++ | MCF_DMA_IMCR_SRC25_CTM1; ++ used_reqs[25] = DMA_CTM1; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM2: ++ if (used_reqs[26] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) ++ | MCF_DMA_IMCR_SRC26_CTM2; ++ used_reqs[26] = DMA_CTM2; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM3: ++ if (used_reqs[27] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) ++ | MCF_DMA_IMCR_SRC27_CTM3; ++ used_reqs[27] = DMA_CTM3; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM4: ++ if (used_reqs[28] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) ++ | MCF_DMA_IMCR_SRC28_CTM4; ++ used_reqs[28] = DMA_CTM4; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM5: ++ if (used_reqs[29] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) ++ | MCF_DMA_IMCR_SRC29_CTM5; ++ used_reqs[29] = DMA_CTM5; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM6: ++ if (used_reqs[30] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) ++ | MCF_DMA_IMCR_SRC30_CTM6; ++ used_reqs[30] = DMA_CTM6; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_CTM7: ++ if (used_reqs[31] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) ++ | MCF_DMA_IMCR_SRC31_CTM7; ++ used_reqs[31] = DMA_CTM7; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_USBEP4: ++ if (used_reqs[26] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) ++ | MCF_DMA_IMCR_SRC26_USBEP4; ++ used_reqs[26] = DMA_USBEP4; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_USBEP5: ++ if (used_reqs[27] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) ++ | MCF_DMA_IMCR_SRC27_USBEP5; ++ used_reqs[27] = DMA_USBEP5; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_USBEP6: ++ if (used_reqs[28] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) ++ | MCF_DMA_IMCR_SRC28_USBEP6; ++ used_reqs[28] = DMA_USBEP6; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_PSC2_RX: ++ if (used_reqs[28] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) ++ | MCF_DMA_IMCR_SRC28_PSC2RX; ++ used_reqs[28] = DMA_PSC2_RX; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_PSC2_TX: ++ if (used_reqs[29] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) ++ | MCF_DMA_IMCR_SRC29_PSC2TX; ++ used_reqs[29] = DMA_PSC2_TX; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_PSC3_RX: ++ if (used_reqs[30] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) ++ | MCF_DMA_IMCR_SRC30_PSC3RX; ++ used_reqs[30] = DMA_PSC3_RX; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ case DMA_PSC3_TX: ++ if (used_reqs[31] == 0) { ++ MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) ++ | MCF_DMA_IMCR_SRC31_PSC3TX; ++ used_reqs[31] = DMA_PSC3_TX; ++ } else /* No empty slots */ ++ return 1; ++ break; ++ ++ default: ++ return 1; ++ } ++ return 0; ++} ++ ++/** ++ * dma_get_initiator - get the initiator for the given requestor ++ * @requestor: initiator identifier ++ * ++ * Returns initiator number (0-31) if assigned or just 0 ++ */ ++unsigned int dma_get_initiator(int requestor) ++{ ++ u32 i; ++ ++ for (i = 0; i < sizeof(used_reqs); ++i) { ++ if (used_reqs[i] == requestor) ++ return i; ++ } ++ return 0; ++} ++ ++/** ++ * dma_remove_initiator - remove the given initiator from active list ++ * @requestor: requestor to remove ++ */ ++void dma_remove_initiator(int requestor) ++{ ++ u32 i; ++ ++ for (i = 0; i < sizeof(used_reqs); ++i) { ++ if (used_reqs[i] == requestor) { ++ used_reqs[i] = -1; ++ break; ++ } ++ } ++} ++ ++/** ++ * dma_set_channel_fec: find available channel for fec and mark ++ * @requestor: initiator/requestor identifier ++ * ++ * Returns first avaialble channel (0-5) or -1 if all occupied ++ */ ++int dma_set_channel_fec(int requestor) ++{ ++ u32 i, t; ++ ++#ifdef CONFIG_FEC_548x_ENABLE_FEC2 ++ t = 4; ++#else ++ t = 2; ++#endif ++ ++ for (i = 0; i < t ; ++i) { ++ if (used_channel[i] == -1) { ++ used_channel[i] = requestor; ++ return i; ++ } ++ } ++ /* All channels taken */ ++ return -1; ++} ++ ++/** ++ * dma_set_channel - find an available channel and mark as used ++ * @requestor: initiator/requestor identifier ++ * ++ * Returns first available channel (6-15) or -1 if all occupied ++ */ ++int dma_set_channel(int requestor) ++{ ++ u32 i; ++#ifdef CONFIG_NET_FEC2 ++ i = 4; ++#else ++ i = 2; ++#endif ++ ++ for (; i < 16; ++i) ++ if (used_channel[i] == -1) { ++ used_channel[i] = requestor; ++ return i; ++ } ++ ++ /* All channels taken */ ++ return -1; ++} ++ ++/** ++ * dma_get_channel - get the channel being initiated by the requestor ++ * @requestor: initiator/requestor identifier ++ * ++ * Returns Initiator for requestor or -1 if not found ++ */ ++int dma_get_channel(int requestor) ++{ ++ u32 i; ++ ++ for (i = 0; i < sizeof(used_channel); ++i) { ++ if (used_channel[i] == requestor) ++ return i; ++ } ++ return -1; ++} ++ ++/** ++ * dma_connect - connect a channel with reference on data ++ * @channel: channel number ++ * @address: reference address of data ++ * ++ * Returns 0 if success or -1 if invalid channel ++ */ ++int dma_connect(int channel, int address) ++{ ++ if ((channel < 16) && (channel >= 0)) { ++ connected_channel[channel] = address; ++ return 0; ++ } ++ return -1; ++} ++ ++/** ++ * dma_disconnect - disconnect a channel ++ * @channel: channel number ++ * ++ * Returns 0 if success or -1 if invalid channel ++ */ ++int dma_disconnect(int channel) ++{ ++ if ((channel < 16) && (channel >= 0)) { ++ connected_channel[channel] = 0; ++ return 0; ++ } ++ return -1; ++} ++ ++/** ++ * dma_remove_channel - remove channel from the active list ++ * @requestor: initiator/requestor identifier ++ */ ++void dma_remove_channel(int requestor) ++{ ++ u32 i; ++ ++ for (i = 0; i < sizeof(used_channel); ++i) { ++ if (used_channel[i] == requestor) { ++ used_channel[i] = -1; ++ break; ++ } ++ } ++} ++ ++/** ++ * dma_interrupt_handler - dma interrupt handler ++ * @irq: interrupt number ++ * @dev_id: data ++ * ++ * Returns IRQ_HANDLED ++ */ ++irqreturn_t dma_interrupt_handler(int irq, void *dev_id) ++{ ++ u32 i, interrupts; ++ ++ /* ++ * Determine which interrupt(s) triggered by AND'ing the ++ * pending interrupts with those that aren't masked. ++ */ ++ interrupts = MCF_DMA_DIPR; ++ MCF_DMA_DIPR = interrupts; ++ ++ for (i = 0; i < 16; ++i, interrupts >>= 1) { ++ if (interrupts & 0x1) ++ if (connected_channel[i] != 0) ++ ((void (*)(void)) (connected_channel[i])) (); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * dma_remove_channel_by_number - clear dma channel ++ * @channel: channel number to clear ++ */ ++void dma_remove_channel_by_number(int channel) ++{ ++ if ((channel < sizeof(used_channel)) && (channel >= 0)) ++ used_channel[channel] = -1; ++} ++ ++/** ++ * dma_init - initialize the dma subsystem ++ * ++ * Returns 0 if success non-zero if failure ++ * ++ * Handles the DMA initialization during device setup. ++ */ ++int __devinit dma_init() ++{ ++ int result; ++ char *dma_version_str; ++ ++ MCD_getVersion(&dma_version_str); ++ printk(KERN_INFO "m547x_8x DMA: Initialize %s\n", dma_version_str); ++ ++ /* attempt to setup dma interrupt handler */ ++ if (request_irq(64 + ISC_DMA, dma_interrupt_handler, IRQF_DISABLED, ++ "MCD-DMA", NULL)) { ++ printk(KERN_ERR "MCD-DMA: Cannot allocate the DMA IRQ(48)\n"); ++ return 1; ++ } ++ ++ MCF_DMA_DIMR = 0; ++ MCF_DMA_DIPR = 0xFFFFFFFF; ++ ++ MCF_ICR(ISC_DMA) = ILP_DMA; ++ ++ result = MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000), ++ (void *) SYS_SRAM_DMA_START, MCD_RELOC_TASKS); ++ if (result != MCD_OK) { ++ printk(KERN_ERR "MCD-DMA: Cannot perform DMA initialization\n"); ++ free_irq(64 + ISC_DMA, NULL); ++ return 1; ++ } ++ ++ return 0; ++} ++device_initcall(dma_init); +--- /dev/null ++++ b/arch/m68k/include/asm/MCD_dma.h +@@ -0,0 +1,434 @@ ++/********************************************************************* ++ * ++ * Copyright (C) 2004 Motorola, Inc. ++ * MOTOROLA, INC. All Rights Reserved. ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Shrek Wu b16972@freescale.com ++ * ++ * You are hereby granted a copyright license to use ++ * the SOFTWARE so long as this entire notice is ++ * retained without alteration in any modified and/or redistributed ++ * versions, and that such modified versions are clearly identified ++ * as such. No licenses are granted by implication, estoppel or ++ * otherwise under any patents or trademarks of Motorola, Inc. This ++ * software is provided on an "AS IS" basis and without warranty. ++ * ++ * To the maximum extent permitted by applicable law, MOTOROLA ++ * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING ++ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR ++ * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE ++ * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY ++ * ACCOMPANYING WRITTEN MATERIALS. ++ * ++ * To the maximum extent permitted by applicable law, IN NO EVENT ++ * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING ++ * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS ++ * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY ++ * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. ++ * ++ * Motorola assumes no responsibility for the maintenance and support ++ * of this software ++ ********************************************************************/ ++ ++/* ++ * File: MCD_dma.h ++ * Purpose: Main header file for multi-channel DMA API. ++ * ++ * Notes: ++ * ++ * Modifications: ++ */ ++#ifndef _MCD_API_H ++#define _MCD_API_H ++ ++#include <asm/types.h> ++ ++/* ++ * Turn Execution Unit tasks ON (#define) or OFF (#undef) ++ */ ++#undef MCD_INCLUDE_EU ++ ++/* ++ * Number of DMA channels ++ */ ++#define NCHANNELS 16 ++ ++/* ++ * Total number of variants ++ */ ++#ifdef MCD_INCLUDE_EU ++#define NUMOFVARIANTS 6 ++#else ++#define NUMOFVARIANTS 4 ++#endif ++ ++/* ++ * Define sizes of the various tables ++ */ ++#define TASK_TABLE_SIZE (NCHANNELS*32) ++#define VAR_TAB_SIZE (128) ++#define CONTEXT_SAVE_SIZE (128) ++#define FUNCDESC_TAB_SIZE (256) ++ ++#ifdef MCD_INCLUDE_EU ++#define FUNCDESC_TAB_NUM 16 ++#else ++#define FUNCDESC_TAB_NUM 1 ++#endif ++ ++ ++#ifndef DEFINESONLY ++ ++/* ++ * Portability typedefs ++ */ ++ /* ++#ifndef s32 ++typedef int s32; ++#endif ++#ifndef u32 ++typedef unsigned int u32; ++#endif ++#ifndef s16 ++typedef short s16; ++#endif ++#ifndef u16 ++typedef unsigned short u16; ++#endif ++#ifndef s8 ++typedef char s8; ++#endif ++#ifndef u8 ++typedef unsigned char u8; ++#endif ++*/ ++/* ++ * These structures represent the internal registers of the ++ * multi-channel DMA ++ */ ++struct dmaRegs_s { ++ u32 taskbar; /* task table base address register */ ++ u32 currPtr; ++ u32 endPtr; ++ u32 varTablePtr; ++ u16 dma_rsvd0; ++ u16 ptdControl; /* ptd control */ ++ u32 intPending; /* interrupt pending register */ ++ u32 intMask; /* interrupt mask register */ ++ u16 taskControl[16]; /* task control registers */ ++ u8 priority[32]; /* priority registers */ ++ u32 initiatorMux; /* initiator mux control */ ++ u32 taskSize0; /* task size control register 0. */ ++ u32 taskSize1; /* task size control register 1. */ ++ u32 dma_rsvd1; /* reserved */ ++ u32 dma_rsvd2; /* reserved */ ++ u32 debugComp1; /* debug comparator 1 */ ++ u32 debugComp2; /* debug comparator 2 */ ++ u32 debugControl; /* debug control */ ++ u32 debugStatus; /* debug status */ ++ u32 ptdDebug; /* priority task decode debug */ ++ u32 dma_rsvd3[31]; /* reserved */ ++}; ++typedef volatile struct dmaRegs_s dmaRegs; ++ ++#endif ++ ++/* ++ * PTD contrl reg bits ++ */ ++#define PTD_CTL_TSK_PRI 0x8000 ++#define PTD_CTL_COMM_PREFETCH 0x0001 ++ ++/* ++ * Task Control reg bits and field masks ++ */ ++#define TASK_CTL_EN 0x8000 ++#define TASK_CTL_VALID 0x4000 ++#define TASK_CTL_ALWAYS 0x2000 ++#define TASK_CTL_INIT_MASK 0x1f00 ++#define TASK_CTL_ASTRT 0x0080 ++#define TASK_CTL_HIPRITSKEN 0x0040 ++#define TASK_CTL_HLDINITNUM 0x0020 ++#define TASK_CTL_ASTSKNUM_MASK 0x000f ++ ++/* ++ * Priority reg bits and field masks ++ */ ++#define PRIORITY_HLD 0x80 ++#define PRIORITY_PRI_MASK 0x07 ++ ++/* ++ * Debug Control reg bits and field masks ++ */ ++#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 ++#define DBG_CTL_AUTO_ARM 0x00008000 ++#define DBG_CTL_BREAK 0x00004000 ++#define DBG_CTL_COMP1_TYP_MASK 0x00003800 ++#define DBG_CTL_COMP2_TYP_MASK 0x00000070 ++#define DBG_CTL_EXT_BREAK 0x00000004 ++#define DBG_CTL_INT_BREAK 0x00000002 ++ ++/* ++ * PTD Debug reg selector addresses ++ * This reg must be written with a value to show the contents of ++ * one of the desired internal register. ++ */ ++#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ ++#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and ++ have initiators asserted */ ++ ++ ++/* ++ * General return values ++ */ ++#define MCD_OK 0 ++#define MCD_ERROR -1 ++#define MCD_TABLE_UNALIGNED -2 ++#define MCD_CHANNEL_INVALID -3 ++ ++/* ++ * MCD_initDma input flags ++ */ ++#define MCD_RELOC_TASKS 0x00000001 ++#define MCD_NO_RELOC_TASKS 0x00000000 ++#define MCD_COMM_PREFETCH_EN 0x00000002 ++/* Commbus Prefetching - MCF547x/548x ONLY */ ++ ++/* ++ * MCD_dmaStatus Status Values for each channel ++ */ ++#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ ++#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ ++#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ ++#define MCD_PAUSED 4 /* DMA active but it is currently paused */ ++#define MCD_HALTED 5 ++/* the most recent DMA has been killed with MCD_killTask() */ ++#define MCD_DONE 6 /* the most recent DMA has completed. */ ++ ++ ++/* ++ * MCD_startDma parameter defines ++ */ ++ ++/* ++ * Constants for the funcDesc parameter ++ */ ++/* Byte swapping: */ ++#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ ++#define MCD_BYTE_REVERSE 0x00076540 ++/* to reverse the bytes of each u32 of the DMAed data. */ ++#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of ++ each 32-bit data value being DMAed.*/ ++#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each ++ 16-bit half of each 32-bit data value DMAed */ ++#define MCD_NO_BIT_REV 0x00000000 ++/* do not reverse the bits of each byte DMAed. */ ++#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ ++/* CRCing: */ ++#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ ++#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ ++#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ ++#define MCD_CSUMINET 0xc0400000 ++/* to perform internet checksums on DMAed data.*/ ++#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ ++ ++#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) ++#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) ++ ++/* ++ * Constants for the flags parameter ++ */ ++#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ ++#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ ++#define MCD_TT_FLAGS_SP 0x00000004 ++/* Speculative prefetch(XLB) MCF547x/548x ONLY */ ++#define MCD_TT_FLAGS_MASK 0x000000ff ++#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) ++ ++#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ ++#define MCD_CHAIN_DMA /* TBD */ ++#define MCD_EU_DMA /* TBD */ ++#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ ++#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ ++ ++ ++/* these flags are valid for MCD_startDma and the chained buffer descriptors */ ++#define MCD_BUF_READY 0x80000000 ++/* indicates that this buffer is now under the DMA's control */ ++#define MCD_WRAP 0x20000000 ++/* to tell the FEC Dmas to wrap to the first BD */ ++#define MCD_INTERRUPT 0x10000000 ++/* to generate an interrupt after completion of the DMA. */ ++#define MCD_END_FRAME 0x08000000 ++/* tell the DMA to end the frame when transferring ++ last byte of data in buffer */ ++#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum ++ prior to performing the DMA. */ ++ ++/* Defines for the FEC buffer descriptor control/status word*/ ++#define MCD_FEC_BUF_READY 0x8000 ++#define MCD_FEC_WRAP 0x2000 ++#define MCD_FEC_INTERRUPT 0x1000 ++#define MCD_FEC_END_FRAME 0x0800 ++ ++ ++/* ++ * Defines for general intuitiveness ++ */ ++ ++#define MCD_TRUE 1 ++#define MCD_FALSE 0 ++ ++/* ++ * Three different cases for destination and source. ++ */ ++#define MINUS1 -1 ++#define ZERO 0 ++#define PLUS1 1 ++ ++#ifndef DEFINESONLY ++ ++/* Task Table Entry struct*/ ++typedef struct { ++ u32 TDTstart; /* task descriptor table start */ ++ u32 TDTend; /* task descriptor table end */ ++ u32 varTab; /* variable table start */ ++ u32 FDTandFlags; /* function descriptor table start and flags */ ++ volatile u32 descAddrAndStatus; ++ volatile u32 modifiedVarTab; ++ u32 contextSaveSpace; /* context save space start */ ++ u32 literalBases; ++} TaskTableEntry; ++ ++ ++/* Chained buffer descriptor */ ++typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; ++struct MCD_bufDesc_struct { ++ u32 flags; /* flags describing the DMA */ ++ u32 csumResult; ++ /* checksum from checksumming performed since last checksum reset */ ++ s8 *srcAddr; /* the address to move data from */ ++ s8 *destAddr; /* the address to move data to */ ++ s8 *lastDestAddr; /* the last address written to */ ++ u32 dmaSize; ++ /* the number of bytes to transfer independent of the transfer size */ ++ MCD_bufDesc *next; /* next buffer descriptor in chain */ ++ u32 info; ++ /* private information about this descriptor; DMA does not affect it */ ++}; ++ ++/* Progress Query struct */ ++typedef volatile struct MCD_XferProg_struct { ++ s8 *lastSrcAddr; ++ /* the most-recent or last, post-increment source address */ ++ s8 *lastDestAddr; ++ /* the most-recent or last, post-increment destination address */ ++ u32 dmaSize; ++ /* the amount of data transferred for the current buffer */ ++ MCD_bufDesc *currBufDesc; ++ /* pointer to the current buffer descriptor being DMAed */ ++} MCD_XferProg; ++ ++ ++/* FEC buffer descriptor */ ++typedef volatile struct MCD_bufDescFec_struct { ++ u16 statCtrl; ++ u16 length; ++ u32 dataPointer; ++} MCD_bufDescFec; ++ ++ ++/*************************************************************************/ ++/* ++ * API function Prototypes - see MCD_dmaApi.c for further notes ++ */ ++ ++/* ++ * MCD_startDma starts a particular kind of DMA . ++ */ ++int MCD_startDma( ++ int channel, /* the channel on which to run the DMA */ ++ /* the address to move data from, or buffer-descriptor address */ ++ s8 *srcAddr, ++ /* the amount to increment the source address per transfer */ ++ s16 srcIncr, ++ s8 *destAddr, /* the address to move data to */ ++ /* the amount to increment the destination address per transfer */ ++ s16 destIncr, ++ /* the number of bytes to transfer independent of the transfer size */ ++ u32 dmaSize, ++ /* the number bytes in of each data movement (1, 2, or 4) */ ++ u32 xferSize, ++ u32 initiator, /* what device initiates the DMA */ ++ int priority, /* priority of the DMA */ ++ u32 flags, /* flags describing the DMA */ ++ /* a description of byte swapping, bit swapping, and CRC actions */ ++ u32 funcDesc ++); ++ ++/* ++ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA ++ * registers, relocating and creating the appropriate task structures, and ++ * setting up some global settings ++ */ ++int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); ++ ++/* ++ * MCD_dmaStatus() returns the status of the DMA on the requested channel. ++ */ ++int MCD_dmaStatus(int channel); ++ ++/* ++ * MCD_XferProgrQuery() returns progress of DMA on requested channel ++ */ ++int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep); ++ ++/* ++ * MCD_killDma() halts the DMA on the requested channel, without any ++ * intention of resuming the DMA. ++ */ ++int MCD_killDma(int channel); ++ ++/* ++ * MCD_continDma() continues a DMA which as stopped due to encountering an ++ * unready buffer descriptor. ++ */ ++int MCD_continDma(int channel); ++ ++/* ++ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is ++ * running on that channel). ++ */ ++int MCD_pauseDma(int channel); ++ ++/* ++ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is ++ * running on that channel). ++ */ ++int MCD_resumeDma(int channel); ++ ++/* ++ * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA ++ */ ++int MCD_csumQuery(int channel, u32 *csum); ++ ++/* ++ * MCD_getCodeSize provides the packed size required by the microcoded task ++ * and structures. ++ */ ++int MCD_getCodeSize(void); ++ ++/* ++ * MCD_getVersion provides a pointer to a version string and returns a ++ * version number. ++ */ ++int MCD_getVersion(char **longVersion); ++ ++/* macro for setting a location in the variable table */ ++#define MCD_SET_VAR(taskTab, idx, value) ((u32 *)(taskTab)->varTab)[idx] = value ++ /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, ++ so I'm avoiding surrounding it with "do {} while(0)" */ ++ ++#endif /* DEFINESONLY */ ++ ++#endif /* _MCD_API_H */ +--- /dev/null ++++ b/drivers/dma/MCD_dma.h +@@ -0,0 +1,431 @@ ++/* ++ * drivers/dma/MCD_dma.h ++ * ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef _MCD_API_H ++#define _MCD_API_H ++ ++/* ++ * Turn Execution Unit tasks ON (#define) or OFF (#undef) ++ */ ++#undef MCD_INCLUDE_EU ++ ++/* ++ * Number of DMA channels ++ */ ++#define NCHANNELS 16 ++ ++/* ++ * Total number of variants ++ */ ++#ifdef MCD_INCLUDE_EU ++#define NUMOFVARIANTS 6 ++#else ++#define NUMOFVARIANTS 4 ++#endif ++ ++/* ++ * Define sizes of the various tables ++ */ ++#define TASK_TABLE_SIZE (NCHANNELS*32) ++#define VAR_TAB_SIZE (128) ++#define CONTEXT_SAVE_SIZE (128) ++#define FUNCDESC_TAB_SIZE (256) ++ ++#ifdef MCD_INCLUDE_EU ++#define FUNCDESC_TAB_NUM 16 ++#else ++#define FUNCDESC_TAB_NUM 1 ++#endif ++ ++ ++#ifndef DEFINESONLY ++ ++/* ++ * Portability typedefs ++ */ ++typedef int s32; ++typedef unsigned int u32; ++typedef short s16; ++typedef unsigned short u16; ++typedef char s8; ++typedef unsigned char u8; ++ ++/* ++ * These structures represent the internal registers of the ++ * multi-channel DMA ++ */ ++struct dmaRegs_s { ++ u32 taskbar; /* task table base address register */ ++ u32 currPtr; ++ u32 endPtr; ++ u32 varTablePtr; ++ u16 dma_rsvd0; ++ u16 ptdControl; /* ptd control */ ++ u32 intPending; /* interrupt pending register */ ++ u32 intMask; /* interrupt mask register */ ++ u16 taskControl[16]; /* task control registers */ ++ u8 priority[32]; /* priority registers */ ++ u32 initiatorMux; /* initiator mux control */ ++ u32 taskSize0; /* task size control register 0. */ ++ u32 taskSize1; /* task size control register 1. */ ++ u32 dma_rsvd1; /* reserved */ ++ u32 dma_rsvd2; /* reserved */ ++ u32 debugComp1; /* debug comparator 1 */ ++ u32 debugComp2; /* debug comparator 2 */ ++ u32 debugControl; /* debug control */ ++ u32 debugStatus; /* debug status */ ++ u32 ptdDebug; /* priority task decode debug */ ++ u32 dma_rsvd3[31]; /* reserved */ ++}; ++typedef volatile struct dmaRegs_s dmaRegs; ++ ++#endif ++ ++/* ++ * PTD contrl reg bits ++ */ ++#define PTD_CTL_TSK_PRI 0x8000 ++#define PTD_CTL_COMM_PREFETCH 0x0001 ++ ++/* ++ * Task Control reg bits and field masks ++ */ ++#define TASK_CTL_EN 0x8000 ++#define TASK_CTL_VALID 0x4000 ++#define TASK_CTL_ALWAYS 0x2000 ++#define TASK_CTL_INIT_MASK 0x1f00 ++#define TASK_CTL_ASTRT 0x0080 ++#define TASK_CTL_HIPRITSKEN 0x0040 ++#define TASK_CTL_HLDINITNUM 0x0020 ++#define TASK_CTL_ASTSKNUM_MASK 0x000f ++ ++/* ++ * Priority reg bits and field masks ++ */ ++#define PRIORITY_HLD 0x80 ++#define PRIORITY_PRI_MASK 0x07 ++ ++/* ++ * Debug Control reg bits and field masks ++ */ ++#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 ++#define DBG_CTL_AUTO_ARM 0x00008000 ++#define DBG_CTL_BREAK 0x00004000 ++#define DBG_CTL_COMP1_TYP_MASK 0x00003800 ++#define DBG_CTL_COMP2_TYP_MASK 0x00000070 ++#define DBG_CTL_EXT_BREAK 0x00000004 ++#define DBG_CTL_INT_BREAK 0x00000002 ++ ++/* ++ * PTD Debug reg selector addresses ++ * This reg must be written with a value to show the contents of ++ * one of the desired internal register. ++ */ ++#define PTD_DBG_REQ 0x00 ++/* shows the state of 31 initiators */ ++#define PTD_DBG_TSK_VLD_INIT 0x01 ++/* shows which 16 tasks are valid and ++ * have initiators asserted */ ++ ++ ++/* ++ * General return values ++ */ ++#define MCD_OK 0 ++#define MCD_ERROR -1 ++#define MCD_TABLE_UNALIGNED -2 ++#define MCD_CHANNEL_INVALID -3 ++ ++/* ++ * MCD_initDma input flags ++ */ ++#define MCD_RELOC_TASKS 0x00000001 ++#define MCD_NO_RELOC_TASKS 0x00000000 ++#define MCD_COMM_PREFETCH_EN 0x00000002 ++/* Commbus Prefetching - MCF547x/548x ONLY */ ++ ++/* ++ * MCD_dmaStatus Status Values for each channel ++ */ ++#define MCD_NO_DMA 1 ++/* No DMA has been requested since reset */ ++#define MCD_IDLE 2 ++/* DMA active, but the initiator is currently inactive */ ++#define MCD_RUNNING 3 ++/* DMA active, and the initiator is currently active */ ++#define MCD_PAUSED 4 ++/* DMA active but it is currently paused */ ++#define MCD_HALTED 5 ++/* the most recent DMA has been killed with MCD_killTask() */ ++#define MCD_DONE 6 ++/* the most recent DMA has completed. */ ++ ++ ++/* ++ * MCD_startDma parameter defines ++ */ ++ ++/* ++ * Constants for the funcDesc parameter ++ */ ++/* Byte swapping: */ ++#define MCD_NO_BYTE_SWAP 0x00045670 ++/* to disable byte swapping. */ ++#define MCD_BYTE_REVERSE 0x00076540 ++/* to reverse the bytes of each u32 of the DMAed data. */ ++#define MCD_U16_REVERSE 0x00067450 ++/* to reverse the 16-bit halves of ++ * each 32-bit data value being DMAed.*/ ++#define MCD_U16_BYTE_REVERSE 0x00054760 ++/* to reverse the byte halves of each ++ * 16-bit half of each 32-bit data value DMAed */ ++#define MCD_NO_BIT_REV 0x00000000 ++/* do not reverse the bits of each byte DMAed. */ ++#define MCD_BIT_REV 0x00088880 ++/* reverse the bits of each byte DMAed */ ++/* CRCing: */ ++#define MCD_CRC16 0xc0100000 ++/* to perform CRC-16 on DMAed data. */ ++#define MCD_CRCCCITT 0xc0200000 ++/* to perform CRC-CCITT on DMAed data. */ ++#define MCD_CRC32 0xc0300000 ++/* to perform CRC-32 on DMAed data. */ ++#define MCD_CSUMINET 0xc0400000 ++/* to perform internet checksums on DMAed data.*/ ++#define MCD_NO_CSUM 0xa0000000 ++/* to perform no checksumming. */ ++ ++#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) ++#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) ++ ++/* ++ * Constants for the flags parameter ++ */ ++#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ ++#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ ++#define MCD_TT_FLAGS_SP 0x00000004 ++/* Speculative prefetch(XLB) MCF547x/548x ONLY */ ++#define MCD_TT_FLAGS_PI 0x00000040 /* Precise Increment */ ++#define MCD_TT_FLAGS_MASK 0x000000ff ++#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) ++ ++#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ ++#define MCD_CHAIN_DMA /* TBD */ ++#define MCD_EU_DMA /* TBD */ ++#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ ++#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ ++ ++ ++/* these flags are valid for MCD_startDma ++ * and the chained buffer descriptors */ ++#define MCD_BUF_READY 0x80000000 ++/* indicates that this buffer is now ++ * under the DMA's control */ ++#define MCD_WRAP 0x20000000 ++/* to tell the FEC Dmas to wrap to the first BD */ ++#define MCD_INTERRUPT 0x10000000 ++/* to generate an interrupt after completion of the DMA. */ ++#define MCD_END_FRAME 0x08000000 ++/* tell the DMA to end the frame when transferring ++ * last byte of data in buffer */ ++#define MCD_CRC_RESTART 0x40000000 ++/* to empty out the accumulated checksum ++ prior to performing the DMA. */ ++ ++/* Defines for the FEC buffer descriptor control/status word*/ ++#define MCD_FEC_BUF_READY 0x8000 ++#define MCD_FEC_WRAP 0x2000 ++#define MCD_FEC_INTERRUPT 0x1000 ++#define MCD_FEC_END_FRAME 0x0800 ++ ++ ++/* ++ * Defines for general intuitiveness ++ */ ++ ++#define MCD_TRUE 1 ++#define MCD_FALSE 0 ++ ++/* ++ * Three different cases for destination and source. ++ */ ++#define MINUS1 -1 ++#define ZERO 0 ++#define PLUS1 1 ++ ++#ifndef DEFINESONLY ++ ++/* Task Table Entry struct*/ ++typedef struct { ++ u32 TDTstart; /* task descriptor table start */ ++ u32 TDTend; /* task descriptor table end */ ++ u32 varTab; /* variable table start */ ++ u32 FDTandFlags; /* function descriptor table start and flags */ ++ volatile u32 descAddrAndStatus; ++ volatile u32 modifiedVarTab; ++ u32 contextSaveSpace; /* context save space start */ ++ u32 literalBases; ++} TaskTableEntry; ++ ++ ++/* Chained buffer descriptor */ ++typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; ++struct MCD_bufDesc_struct { ++ u32 flags; ++/* flags describing the DMA */ ++ u32 csumResult; ++/* checksum from checksumming performed since last checksum reset */ ++ s8 *srcAddr; ++/* the address to move data from */ ++ s8 *destAddr; ++/* the address to move data to */ ++ s8 *lastDestAddr; ++/* the last address written to */ ++ u32 dmaSize; ++/* the number of bytes to transfer independent of the transfer size */ ++ MCD_bufDesc *next; ++/* next buffer descriptor in chain */ ++ u32 info; ++/* private information about this descriptor; DMA does not affect it */ ++}; ++ ++/* Progress Query struct */ ++typedef volatile struct MCD_XferProg_struct { ++ s8 *lastSrcAddr; ++/* the most-recent or last, post-increment source address */ ++ s8 *lastDestAddr; ++/* the most-recent or last, post-increment destination address */ ++ u32 dmaSize; ++/* the amount of data transferred for the current buffer */ ++ MCD_bufDesc *currBufDesc; ++/* pointer to the current buffer descriptor being DMAed */ ++} MCD_XferProg; ++ ++ ++/* FEC buffer descriptor */ ++typedef volatile struct MCD_bufDescFec_struct { ++ u16 statCtrl; ++ u16 length; ++ u32 dataPointer; ++} MCD_bufDescFec; ++ ++ ++/*************************************************************************/ ++/* ++ * API function Prototypes - see MCD_dmaApi.c for further notes ++ */ ++ ++/* ++ * MCD_startDma starts a particular kind of DMA . ++ */ ++int MCD_startDma( ++ int channel, ++/* the channel on which to run the DMA */ ++ s8 *srcAddr, ++/* the address to move data from, or buffer-descriptor address */ ++ s16 srcIncr, ++/* the amount to increment the source address per transfer */ ++ s8 *destAddr, ++/* the address to move data to */ ++ s16 destIncr, ++/* the amount to increment the destination address per transfer */ ++ u32 dmaSize, ++/* the number of bytes to transfer independent of the transfer size */ ++ u32 xferSize, ++/* the number bytes in of each data movement (1, 2, or 4) */ ++ u32 initiator, ++/* what device initiates the DMA */ ++ int priority, ++/* priority of the DMA */ ++ u32 flags, ++/* flags describing the DMA */ ++ u32 funcDesc ++/* a description of byte swapping, bit swapping, and CRC actions */ ++); ++ ++/* ++ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA ++ * registers, relocating and creating the appropriate task structures, and ++ * setting up some global settings ++ */ ++int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); ++ ++/* ++ * MCD_dmaStatus() returns the status of the DMA on the requested channel. ++ */ ++int MCD_dmaStatus(int channel); ++ ++/* ++ * MCD_XferProgrQuery() returns progress of DMA on requested channel ++ */ ++int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep); ++ ++/* ++ * MCD_killDma() halts the DMA on the requested channel, without any ++ * intention of resuming the DMA. ++ */ ++int MCD_killDma(int channel); ++ ++/* ++ * MCD_continDma() continues a DMA which as stopped due to encountering an ++ * unready buffer descriptor. ++ */ ++int MCD_continDma(int channel); ++ ++/* ++ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is ++ * running on that channel). ++ */ ++int MCD_pauseDma(int channel); ++ ++/* ++ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is ++ * running on that channel). ++ */ ++int MCD_resumeDma(int channel); ++ ++/* ++ * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA ++ */ ++int MCD_csumQuery(int channel, u32 *csum); ++ ++/* ++ * MCD_getCodeSize provides the packed size required by the microcoded task ++ * and structures. ++ */ ++int MCD_getCodeSize(void); ++ ++/* ++ * MCD_getVersion provides a pointer to a version string and returns a ++ * version number. ++ */ ++int MCD_getVersion(char **longVersion); ++ ++/* macro for setting a location in the variable table */ ++#define MCD_SET_VAR(taskTab, idx, value) \ ++ ((u32 *)(taskTab)->varTab)[idx] = value ++ /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, ++ so I'm avoiding surrounding it with "do {} while(0)" */ ++ ++#endif /* DEFINESONLY */ ++ ++#endif /* _MCD_API_H */ +--- /dev/null ++++ b/drivers/dma/MCD_dmaApi.c +@@ -0,0 +1,1043 @@ ++/* ++ * drivers/dma/MCD_dmaApi.c ++ * ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include "MCD_dma.h" ++#include "MCD_tasksInit.h" ++#include "MCD_progCheck.h" ++ ++/********************************************************************/ ++/* ++ * This is an API-internal pointer to the DMA's registers ++ */ ++dmaRegs *MCD_dmaBar; ++ ++/* ++ * These are the real and model task tables as generated by the ++ * build process ++ */ ++extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS]; ++extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS]; ++ ++/* ++ * However, this (usually) gets relocated to on-chip SRAM, at which ++ * point we access them as these tables ++ */ ++volatile TaskTableEntry *MCD_taskTable; ++TaskTableEntry *MCD_modelTaskTable; ++ ++ ++/* ++ * MCD_chStatus[] is an array of status indicators for remembering ++ * whether a DMA has ever been attempted on each channel, pausing ++ * status, etc. ++ */ ++static int MCD_chStatus[NCHANNELS] = { ++ MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, ++ MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, ++ MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, ++ MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA ++}; ++ ++/* ++ * Prototypes for local functions ++ */ ++static void MCD_memcpy(int *dest, int *src, u32 size); ++static void MCD_resmActions(int channel); ++ ++/* ++ * Buffer descriptors used for storage of progress info for single Dmas ++ * Also used as storage for the DMA for CRCs for single DMAs ++ * Otherwise, the DMA does not parse these buffer descriptors ++ */ ++#ifdef MCD_INCLUDE_EU ++extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; ++#else ++MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; ++#endif ++MCD_bufDesc *MCD_relocBuffDesc; ++ ++ ++/* ++ * Defines for the debug control register's functions ++ */ ++#define DBG_CTL_COMP1_TASK (0x00002000) ++/* have comparator 1 look for a task # */ ++#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \ ++ DBG_CTL_BREAK | \ ++ DBG_CTL_INT_BREAK | \ ++ DBG_CTL_COMP1_TASK) ++#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \ ++ DBG_CTL_INT_BREAK | \ ++ DBG_CTL_COMP1_TASK) ++#define DBG_KILL_ALL_STAT (0xFFFFFFFF) ++ ++/* ++ * Offset to context save area where progress info is stored ++ */ ++#define CSAVE_OFFSET 10 ++ ++/* ++ * Defines for Byte Swapping ++ */ ++#define MCD_BYTE_SWAP_KILLER 0xFFF8888F ++#define MCD_NO_BYTE_SWAP_ATALL 0x00040000 ++ ++/* ++ * Execution Unit Identifiers ++ */ ++#define MAC 0 /* legacy - not used */ ++#define LUAC 1 /* legacy - not used */ ++#define CRC 2 /* legacy - not used */ ++#define LURC 3 /* Logic Unit with CRC */ ++ ++/* ++ * Task Identifiers ++ */ ++#define TASK_CHAINNOEU 0 ++#define TASK_SINGLENOEU 1 ++#ifdef MCD_INCLUDE_EU ++#define TASK_CHAINEU 2 ++#define TASK_SINGLEEU 3 ++#define TASK_FECRX 4 ++#define TASK_FECTX 5 ++#else ++#define TASK_CHAINEU 0 ++#define TASK_SINGLEEU 1 ++#define TASK_FECRX 2 ++#define TASK_FECTX 3 ++#endif ++ ++/* ++ * Structure to remember which variant is on which channel ++ */ ++struct MCD_remVariants_struct { ++ int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ ++ int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ ++ s16 remDestIncr[NCHANNELS]; /* DestIncr */ ++ s16 remSrcIncr[NCHANNELS]; /* srcIncr */ ++ u32 remXferSize[NCHANNELS]; /* xferSize */ ++}; ++ ++/* ++ * Structure to remember the startDma parameters for each channel ++ */ ++struct MCD_remVariants_struct MCD_remVariants; ++ ++/********************************************************************/ ++/* ++ * Function: MCD_initDma ++ * Purpose: Initializes the DMA API by setting up a pointer to the DMA ++ * registers, relocating and creating the appropriate task ++ * structures, and setting up some global settings ++ * Arguments: ++ * dmaBarAddr - pointer to the multichannel DMA registers ++ * taskTableDest - location to move DMA task code and structs to ++ * flags - operational parameters ++ * Return Value: ++ * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned ++ * MCD_OK otherwise ++ */ ++extern u32 MCD_funcDescTab0[]; ++ ++int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) ++{ ++ int i; ++ TaskTableEntry *entryPtr; ++ ++ /* Setup the local pointer to register set */ ++ MCD_dmaBar = dmaBarAddr; ++ ++ /* Do we need to move/create a task table */ ++ if ((flags & MCD_RELOC_TASKS) != 0) { ++ int fixedSize; ++ u32 *fixedPtr; ++ int varTabsOffset, funcDescTabsOffset; ++ int contextSavesOffset; ++ int taskDescTabsOffset; ++ int taskTableSize, varTabsSize; ++ int funcDescTabsSize, contextSavesSize; ++ int taskDescTabSize; ++ int i; ++ ++ /* Check if physical address is ++ * aligned on 512 byte boundary */ ++ if (((u32)taskTableDest & 0x000001ff) != 0) ++ return MCD_TABLE_UNALIGNED; ++ ++ MCD_taskTable = taskTableDest; ++ /* set up local pointer to task Table */ ++ ++ /* ++ * Create a task table: ++ * compute aligned base offsets for variable tables and ++ * function descriptor tables, then ++ * loop through the task table and setup the pointers ++ *copy over model task table with the the actual ++ *task descriptor tables ++ */ ++ taskTableSize = NCHANNELS * sizeof(TaskTableEntry); ++ /* Align variable tables to size */ ++ varTabsOffset = taskTableSize + (u32)taskTableDest; ++ if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) ++ varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) ++ & (~VAR_TAB_SIZE); ++ /* Align function descriptor tables */ ++ varTabsSize = NCHANNELS * VAR_TAB_SIZE; ++ funcDescTabsOffset = varTabsOffset + varTabsSize; ++ ++ if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0) ++ funcDescTabsOffset = (funcDescTabsOffset ++ + FUNCDESC_TAB_SIZE) & ++ (~FUNCDESC_TAB_SIZE); ++ ++ funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE; ++ contextSavesOffset = funcDescTabsOffset ++ + funcDescTabsSize; ++ contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE); ++ fixedSize = taskTableSize + varTabsSize + ++ funcDescTabsSize + contextSavesSize; ++ ++ /* Zero the thing out */ ++ fixedPtr = (u32 *)taskTableDest; ++ for (i = 0; i < (fixedSize/4); i++) ++ fixedPtr[i] = 0; ++ ++ entryPtr = (TaskTableEntry *)MCD_taskTable; ++ /* Set up fixed pointers */ ++ for (i = 0; i < NCHANNELS; i++) { ++ entryPtr[i].varTab = (u32)varTabsOffset; ++ /* update ptr to local value */ ++ entryPtr[i].FDTandFlags = ++ (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF; ++ entryPtr[i].contextSaveSpace = ++ (u32)contextSavesOffset; ++ varTabsOffset += VAR_TAB_SIZE; ++#ifdef MCD_INCLUDE_EU ++ /* if not there is only one, ++ * just point to the same one */ ++ funcDescTabsOffset += FUNCDESC_TAB_SIZE; ++#endif ++ contextSavesOffset += CONTEXT_SAVE_SIZE; ++ } ++ /* Copy over the function descriptor table */ ++ for (i = 0; i < FUNCDESC_TAB_NUM; i++) { ++ MCD_memcpy((void *)(entryPtr[i].FDTandFlags ++ & ~MCD_TT_FLAGS_MASK), ++ (void *)MCD_funcDescTab0, ++ FUNCDESC_TAB_SIZE); ++ } ++ ++ /* Copy model task table to where the ++ * context save stuff leaves off */ ++ MCD_modelTaskTable = ++ (TaskTableEntry *)contextSavesOffset; ++ ++ MCD_memcpy((void *)MCD_modelTaskTable, ++ (void *)MCD_modelTaskTableSrc, ++ NUMOFVARIANTS * sizeof(TaskTableEntry)); ++ ++ /* Point to local version of model task table */ ++ entryPtr = MCD_modelTaskTable; ++ taskDescTabsOffset = (u32)MCD_modelTaskTable + ++ (NUMOFVARIANTS * sizeof(TaskTableEntry)); ++ ++ /* Copy actual task code and update TDT ptrs ++ * in local model task table */ ++ for (i = 0; i < NUMOFVARIANTS; i++) { ++ taskDescTabSize = entryPtr[i].TDTend ++ - entryPtr[i].TDTstart + 4; ++ MCD_memcpy((void *)taskDescTabsOffset, ++ (void *)entryPtr[i].TDTstart, ++ taskDescTabSize); ++ entryPtr[i].TDTstart = ++ (u32)taskDescTabsOffset; ++ taskDescTabsOffset += taskDescTabSize; ++ entryPtr[i].TDTend = ++ (u32)taskDescTabsOffset - 4; ++ } ++#ifdef MCD_INCLUDE_EU ++ /* ++ * Tack single DMA BDs onto end of ++ * code so API controls where ++ * they are since DMA might write to them ++ */ ++ MCD_relocBuffDesc = (MCD_bufDesc *) ++ (entryPtr[NUMOFVARIANTS - 1].TDTend + 4); ++#else ++ /* ++ * DMA does not touch them so they ++ * can be wherever and we don't need to ++ * waste SRAM on them ++ */ ++ MCD_relocBuffDesc = MCD_singleBufDescs; ++#endif ++ } else { ++ /* ++ * Point the would-be relocated task tables and ++ * the buffer descriptors ++ * to the ones the linker generated ++ */ ++ if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0) ++ return MCD_TABLE_UNALIGNED; ++ ++ entryPtr = MCD_realTaskTableSrc; ++ for (i = 0; i < NCHANNELS; i++) { ++ if (((entryPtr[i].varTab ++ & (VAR_TAB_SIZE - 1)) != 0) || ++ ((entryPtr[i].FDTandFlags & ++ (FUNCDESC_TAB_SIZE - 1)) != 0)) ++ return MCD_TABLE_UNALIGNED; ++ } ++ ++ MCD_taskTable = MCD_realTaskTableSrc; ++ MCD_modelTaskTable = MCD_modelTaskTableSrc; ++ MCD_relocBuffDesc = MCD_singleBufDescs; ++ } ++ ++ /* Make all channels inactive, ++ * and remember them as such: */ ++ MCD_dmaBar->taskbar = (u32) MCD_taskTable; ++ for (i = 0; i < NCHANNELS; i++) { ++ MCD_dmaBar->taskControl[i] = 0x0; ++ MCD_chStatus[i] = MCD_NO_DMA; ++ } ++ ++ /* Set up pausing mechanism to inactive state: */ ++ MCD_dmaBar->debugComp1 = 0; ++ MCD_dmaBar->debugComp2 = 0; ++ MCD_dmaBar->debugControl = DBG_CTL_DISABLE; ++ MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT; ++ ++ /* Enable or disable commbus prefetch */ ++ if ((flags & MCD_COMM_PREFETCH_EN) != 0) ++ MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH; ++ else ++ MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH; ++ ++ return MCD_OK; ++} ++/*********************** End of MCD_initDma() ***********************/ ++ ++/********************************************************************/ ++/* Function: MCD_dmaStatus ++ * Purpose: Returns the status of the DMA on the requested channel ++ * Arguments: channel - channel number ++ * Returns: Predefined status indicators ++ */ ++int MCD_dmaStatus(int channel) ++{ ++ u16 tcrValue; ++ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ tcrValue = MCD_dmaBar->taskControl[channel]; ++ if ((tcrValue & TASK_CTL_EN) == 0) { ++ /* Nothing running if last reported ++ * with task enabled */ ++ if (MCD_chStatus[channel] == MCD_RUNNING ++ || MCD_chStatus[channel] == MCD_IDLE) ++ MCD_chStatus[channel] = MCD_DONE; ++ } else /* something is running */{ ++ /* There are three possibilities: ++ * paused, running or idle. */ ++ if (MCD_chStatus[channel] == MCD_RUNNING ++ || MCD_chStatus[channel] == MCD_IDLE) { ++ MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; ++ /* Determine which initiator ++ * is asserted. */ ++ if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) ++ MCD_chStatus[channel] = MCD_RUNNING; ++ else ++ MCD_chStatus[channel] = MCD_IDLE; ++ /* Do not change the status if it is already paused */ ++ } ++ } ++ return MCD_chStatus[channel]; ++} ++/******************** End of MCD_dmaStatus() ************************/ ++ ++/********************************************************************/ ++/* Function: MCD_startDma ++ * Ppurpose: Starts a particular kind of DMA ++ * Arguments: see below ++ * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK ++ */ ++ ++int MCD_startDma( ++ int channel, ++/* the channel on which to run the DMA */ ++ s8 *srcAddr, ++/* the address to move data from, ++ * or physical buffer-descriptor address */ ++ s16 srcIncr, ++/* the amount to increment the source ++ * address per transfer */ ++ s8 *destAddr, ++/* the address to move data to */ ++ s16 destIncr, ++/* the amount to increment the ++ * destination address per transfer */ ++ u32 dmaSize, ++/* the number of bytes to transfer ++ * independent of the transfer size */ ++ u32 xferSize, ++/* the number bytes in of each data ++ * movement (1, 2, or 4) */ ++ u32 initiator, ++/* what device initiates the DMA */ ++ int priority, ++/* priority of the DMA */ ++ u32 flags, ++/* flags describing the DMA */ ++ u32 funcDesc ++/* a description of byte swapping, ++ * bit swapping, and CRC actions */ ++#ifdef MCD_NEED_ADDR_TRANS ++ s8 *srcAddrVirt ++/* virtual buffer descriptor address TBD*/ ++#endif ++) ++{ ++ int srcRsdIncr, destRsdIncr; ++ int *cSave; ++ short xferSizeIncr; ++ int tcrCount = 0; ++#ifdef MCD_INCLUDE_EU ++ u32 *realFuncArray; ++#endif ++ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++#ifndef MCD_INCLUDE_EU ++ funcDesc = MCD_FUNC_NOEU1; ++#endif ++ ++#ifdef MCD_DEBUG ++ printf("startDma:Setting up params\n"); ++#endif ++ ++ /* Enable task-wise priority */ ++ MCD_dmaBar->ptdControl |= (u16) 0x8000; ++ ++ /* Calculate additional parameters ++ * to the regular DMA calls. */ ++ srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); ++ destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0); ++ xferSizeIncr = (xferSize & 0xffff) | 0x20000000; ++ ++ /* Remember which variant is running for each channel */ ++ MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr; ++ MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr; ++ MCD_remVariants.remDestIncr[channel] = destIncr; ++ MCD_remVariants.remSrcIncr[channel] = srcIncr; ++ MCD_remVariants.remXferSize[channel] = xferSize; ++ ++ cSave = (int *)(MCD_taskTable[channel].contextSaveSpace) ++ + CSAVE_OFFSET ++ + CURRBD; ++ ++#ifdef MCD_INCLUDE_EU ++ realFuncArray = (u32 *)(MCD_taskTable[channel].FDTandFlags ++ & 0xffffff00); ++ ++ /* ++ * Modify the LURC's normal and byte-residue-loop functions ++ * according to parameter. ++ */ ++ switch (xferSize) { ++ case 4: ++ realFuncArray[(LURC*16)] = funcDesc; ++ break; ++ case 2: ++ realFuncArray[(LURC*16)] = funcDesc & 0xfffff00f; ++ break; ++ case 1: ++ default: ++ realFuncArray[(LURC*16)] = funcDesc & 0xffff000f; ++ break; ++ } ++ ++ realFuncArray[(LURC*16 + 1)] = 0 ++ | (funcDesc & MCD_BYTE_SWAP_KILLER) ++ | MCD_NO_BYTE_SWAP_ATALL; ++#endif ++ ++ /* Write the initiator field in the TCR and ++ * set the initiator-hold bit*/ ++ MCD_dmaBar->taskControl[channel] = 0 ++ | (initiator << 8) ++ | TASK_CTL_HIPRITSKEN ++ | TASK_CTL_HLDINITNUM; ++ ++ /* ++ * Current versions of the MPC8220 MCD have a hardware quirk that could ++ * cause the write to the TCR to collide with an MDE access to the ++ * initiator-register file, so we have to verify that the write occurred ++ * correctly by reading back the value. On MCF547x/8x devices and any ++ * future revisions of the MPC8220, this loop will not be entered. ++ */ ++ while (((MCD_dmaBar->taskControl[channel] & 0x1fff) != ++ ((initiator << 8) | TASK_CTL_HIPRITSKEN ++ | TASK_CTL_HLDINITNUM)) && (tcrCount < 1000)) { ++ tcrCount++; ++ MCD_dmaBar->taskControl[channel] = 0 ++ | (initiator << 8) ++ | TASK_CTL_HIPRITSKEN ++ | TASK_CTL_HLDINITNUM; ++ } ++ ++ MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK; ++ ++ if (channel < 8 && channel >= 0) { ++ MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4); ++ MCD_dmaBar->taskSize0 ++ |= (xferSize & 3) << (((7 - channel)*4) + 2); ++ MCD_dmaBar->taskSize0 ++ |= (xferSize & 3) << ((7 - channel)*4); ++ } else { ++ MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4); ++ MCD_dmaBar->taskSize1 ++ |= (xferSize & 3) << (((15 - channel)*4) + 2); ++ MCD_dmaBar->taskSize1 ++ |= (xferSize & 3) << ((15 - channel)*4); ++ } ++ ++ /* Setup task table flags/options */ ++ MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK; ++ MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags); ++ ++ if (flags & MCD_FECTX_DMA) { ++ /* TDTStart and TDTEnd */ ++ MCD_taskTable[channel].TDTstart = ++ MCD_modelTaskTable[TASK_FECTX].TDTstart; ++ MCD_taskTable[channel].TDTend = ++ MCD_modelTaskTable[TASK_FECTX].TDTend; ++ MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, ++ MCD_taskTable, channel); ++ } else if (flags & MCD_FECRX_DMA) { ++ /* TDTStart and TDTEnd */ ++ MCD_taskTable[channel].TDTstart = ++ MCD_modelTaskTable[TASK_FECRX].TDTstart; ++ MCD_taskTable[channel].TDTend = ++ MCD_modelTaskTable[TASK_FECRX].TDTend; ++ MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, ++ MCD_taskTable, channel); ++ } else if (flags & MCD_SINGLE_DMA) { ++ /* ++ * This buffer descriptor is used for storing off ++ * initial parameters for later progress query ++ * calculation and for the DMA to write the resulting ++ * checksum. The DMA does not use this to determine how ++ * to operate, that info is passed with the init routine ++ */ ++ MCD_relocBuffDesc[channel].srcAddr = srcAddr; ++ MCD_relocBuffDesc[channel].destAddr = destAddr; ++ MCD_relocBuffDesc[channel].lastDestAddr = destAddr; ++ MCD_relocBuffDesc[channel].dmaSize = dmaSize; ++ MCD_relocBuffDesc[channel].flags = 0; ++ /* not used */ ++ MCD_relocBuffDesc[channel].csumResult = 0; ++ /* not used */ ++ MCD_relocBuffDesc[channel].next = 0; ++ /* not used */ ++ ++ /* Initialize the progress-querying stuff ++ * to show no progress:*/ ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ SRCPTR + CSAVE_OFFSET] = (int)srcAddr; ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DESTPTR + CSAVE_OFFSET] = (int)destAddr; ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DCOUNT + CSAVE_OFFSET] = 0; ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ CURRBD + CSAVE_OFFSET] = ++ (u32) &(MCD_relocBuffDesc[channel]); ++ ++ if ((funcDesc == MCD_FUNC_NOEU1) ++ || (funcDesc == MCD_FUNC_NOEU2)) { ++ /* TDTStart and TDTEnd */ ++ MCD_taskTable[channel].TDTstart = ++ MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart; ++ MCD_taskTable[channel].TDTend = ++ MCD_modelTaskTable[TASK_SINGLENOEU].TDTend; ++ MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, ++ destIncr, dmaSize, xferSizeIncr, flags, ++ (int *)&(MCD_relocBuffDesc[channel]), ++ cSave, MCD_taskTable, channel); ++ } else { ++ /* TDTStart and TDTEnd */ ++ MCD_taskTable[channel].TDTstart = ++ MCD_modelTaskTable[TASK_SINGLEEU].TDTstart; ++ MCD_taskTable[channel].TDTend = ++ MCD_modelTaskTable[TASK_SINGLEEU].TDTend; ++ MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, ++ destIncr, dmaSize, xferSizeIncr, flags, ++ (int *)&(MCD_relocBuffDesc[channel]), ++ cSave, MCD_taskTable, channel); ++ } ++ } else /* Chained DMA */ { ++ /* Initialize the progress-querying ++ * stuff to show no progress:*/ ++#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */ ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ SRCPTR + CSAVE_OFFSET] ++ = (int)((MCD_bufDesc *) srcAddr)->srcAddr; ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DESTPTR + CSAVE_OFFSET] ++ = (int)((MCD_bufDesc *) srcAddr)->destAddr; ++#else ++ /* if using address translation, need the ++ * virtual addr of the first buffdesc */ ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ SRCPTR + CSAVE_OFFSET] ++ = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr; ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DESTPTR + CSAVE_OFFSET] ++ = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr; ++#endif ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DCOUNT + CSAVE_OFFSET] = 0; ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ CURRBD + CSAVE_OFFSET] = (u32) srcAddr; ++ ++ if (funcDesc == MCD_FUNC_NOEU1 ++ || funcDesc == MCD_FUNC_NOEU2) { ++ /* TDTStart and TDTEnd */ ++ MCD_taskTable[channel].TDTstart = ++ MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart; ++ MCD_taskTable[channel].TDTend = ++ MCD_modelTaskTable[TASK_CHAINNOEU].TDTend; ++ MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, ++ destIncr, xferSize, xferSizeIncr, cSave, ++ MCD_taskTable, channel); ++ } else { ++ /* TDTStart and TDTEnd */ ++ MCD_taskTable[channel].TDTstart = ++ MCD_modelTaskTable[TASK_CHAINEU].TDTstart; ++ MCD_taskTable[channel].TDTend = ++ MCD_modelTaskTable[TASK_CHAINEU].TDTend; ++ MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, ++ xferSize, xferSizeIncr, cSave, ++ MCD_taskTable, channel); ++ } ++ } ++ ++ MCD_chStatus[channel] = MCD_IDLE; ++ return MCD_OK; ++} ++ ++/************************ End of MCD_startDma() *********************/ ++ ++/********************************************************************/ ++/* Function: MCD_XferProgrQuery ++ * Purpose: Returns progress of DMA on requested channel ++ * Arguments: channel - channel to retrieve progress for ++ * progRep - pointer to user supplied MCD_XferProg struct ++ * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK ++ * ++ * Notes: ++ * MCD_XferProgrQuery() upon completing or after aborting a DMA, or ++ * while the DMA is in progress, this function returns the first ++ * DMA-destination address not (or not yet) used in the DMA. When ++ * encountering a non-ready buffer descriptor, the information for ++ * the last completed descriptor is returned. ++ * ++ * MCD_XferProgQuery() has to avoid the possibility of getting ++ * partially-updated information in the event that we should happen ++ * to query DMA progress just as the DMA is updating it. It does that ++ * by taking advantage of the fact context is not saved frequently for ++ * the most part. We therefore read it at least twice until we get the ++ * same information twice in a row. ++ * ++ * Because a small, but not insignificant, amount of time is required ++ * to write out the progress-query information, especially upon ++ * completion of the DMA, it would be wise to guarantee some time lag ++ * between successive readings of the progress-query information. ++ */ ++ ++/* ++ * How many iterations of the loop below to execute to stabilize values ++ */ ++#define STABTIME 0 ++ ++int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep) ++{ ++ MCD_XferProg prevRep; ++ int again; ++ /* true if we are to try again to get consistent results */ ++ int i; /* used as a time-waste counter */ ++ int destDiffBytes; ++ /* Total number of bytes that we think actually got xfered. */ ++ int numIterations; /* number of iterations */ ++ int bytesNotXfered; /* bytes that did not get xfered. */ ++ s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; ++ int subModVal, addModVal; ++ /* Mode values to added and subtracted from the final destAddr */ ++ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ /* Read a trial value for the progress-reporting values*/ ++ prevRep.lastSrcAddr = ++ (s8 *)((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ SRCPTR + CSAVE_OFFSET]; ++ prevRep.lastDestAddr = ++ (s8 *)((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DESTPTR + CSAVE_OFFSET]; ++ prevRep.dmaSize = ++ ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ ++ DCOUNT + CSAVE_OFFSET]; ++ prevRep.currBufDesc = ++ (MCD_bufDesc *)((volatile int *)MCD_taskTable[ ++ channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; ++ ++ /* Repeatedly reread those values until ++ * they match previous values: */ ++ do { ++ /* Take a little bit of time to ensure stability: */ ++ for (i = 0; i < STABTIME; i++) ++ i += i >> 2; ++ /* make sure this loop does something so that it ++ doesn't get optimized out */ ++ /* Check them again: */ ++ progRep->lastSrcAddr = ++ (s8 *)((volatile int *)MCD_taskTable[ ++ channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; ++ progRep->lastDestAddr = ++ (s8 *)((volatile int *)MCD_taskTable[ ++ channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; ++ progRep->dmaSize = ((volatile int *)MCD_taskTable[ ++ channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; ++ progRep->currBufDesc = ++ (MCD_bufDesc *)((volatile int *)MCD_taskTable[ ++ channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; ++ ++ /* See if they match: */ ++ if (prevRep.lastSrcAddr != progRep->lastSrcAddr ++ || prevRep.lastDestAddr != progRep->lastDestAddr ++ || prevRep.dmaSize != progRep->dmaSize ++ || prevRep.currBufDesc != progRep->currBufDesc) { ++ /* If they don't match, remember previous ++ values and try again:*/ ++ prevRep.lastSrcAddr = progRep->lastSrcAddr; ++ prevRep.lastDestAddr = progRep->lastDestAddr; ++ prevRep.dmaSize = progRep->dmaSize; ++ prevRep.currBufDesc = progRep->currBufDesc; ++ again = MCD_TRUE; ++ } else ++ again = MCD_FALSE; ++ } while (again == MCD_TRUE); ++ ++ ++ /* Update dmaSize and lastDestAddr */ ++ switch (MCD_remVariants.remDestRsdIncr[channel]) { ++ case MINUS1: ++ subModVal = ((int)progRep->lastDestAddr) ++ & ((MCD_remVariants.remXferSize[channel]) - 1); ++ addModVal = ((int)progRep->currBufDesc->destAddr) ++ & ((MCD_remVariants.remXferSize[channel]) - 1); ++ LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) ++ - addModVal; ++ LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal; ++ destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr; ++ bytesNotXfered = ++ (destDiffBytes/MCD_remVariants.remDestIncr[channel]) * ++ (MCD_remVariants.remDestIncr[channel] ++ + MCD_remVariants.remXferSize[channel]); ++ progRep->dmaSize = destDiffBytes - bytesNotXfered ++ + addModVal - subModVal; ++ break; ++ case ZERO: ++ progRep->lastDestAddr = progRep->currBufDesc->destAddr; ++ break; ++ case PLUS1: ++ /* This value has to be subtracted ++ from the final calculated dmaSize. */ ++ subModVal = ((int)progRep->currBufDesc->destAddr) ++ & ((MCD_remVariants.remXferSize[channel]) - 1); ++ /* These bytes are already in lastDestAddr. */ ++ addModVal = ((int)progRep->lastDestAddr) ++ & ((MCD_remVariants.remXferSize[channel]) - 1); ++ LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) ++ - subModVal; ++ LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal; ++ destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr); ++ numIterations = (LWAlignedCurrDestAddr - ++ LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel]; ++ bytesNotXfered = numIterations * ++ (MCD_remVariants.remDestIncr[channel] ++ - MCD_remVariants.remXferSize[channel]); ++ progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal; ++ break; ++ default: ++ break; ++ } ++ ++ /* This covers M1,P1,Z for source */ ++ switch (MCD_remVariants.remSrcRsdIncr[channel]) { ++ case MINUS1: ++ progRep->lastSrcAddr = ++ progRep->currBufDesc->srcAddr + ++ (MCD_remVariants.remSrcIncr[channel] * ++ (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); ++ break; ++ case ZERO: ++ progRep->lastSrcAddr = progRep->currBufDesc->srcAddr; ++ break; ++ case PLUS1: ++ progRep->lastSrcAddr = ++ progRep->currBufDesc->srcAddr + ++ (MCD_remVariants.remSrcIncr[channel] * ++ (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); ++ break; ++ default: ++ break; ++ } ++ ++ return MCD_OK; ++} ++/******************* End of MCD_XferProgrQuery() ********************/ ++ ++/********************************************************************/ ++/* MCD_resmActions() does the majority of the actions of a DMA resume. ++ * It is called from MCD_killDma() and MCD_resumeDma(). It has to be ++ * a separate function because the kill function has to negate the task ++ * enable before resuming it, but the resume function has to do nothing ++ * if there is no DMA on that channel (i.e., if the enable bit is 0). ++ */ ++static void MCD_resmActions(int channel) ++{ ++ MCD_dmaBar->debugControl = DBG_CTL_DISABLE; ++ MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; ++ ++ /* Determine which initiators are asserted */ ++ MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; ++ ++ if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) ++ MCD_chStatus[channel] = MCD_RUNNING; ++ else ++ MCD_chStatus[channel] = MCD_IDLE; ++} ++/********************* End of MCD_resmActions() *********************/ ++ ++/********************************************************************/ ++/* Function: MCD_killDma ++ * Purpose: Halt the DMA on the requested channel, without any ++ * intention of resuming the DMA. ++ * Arguments: channel - requested channel ++ * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK ++ * ++ * Notes: ++ * A DMA may be killed from any state, including paused state, and it ++ * always goes to the MCD_HALTED state even if it is killed while in ++ * the MCD_NO_DMA or MCD_IDLE states. ++ */ ++int MCD_killDma(int channel) ++{ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ MCD_dmaBar->taskControl[channel] = 0x0; ++ ++ /* Clean up after a paused task */ ++ if (MCD_chStatus[channel] == MCD_PAUSED) { ++ MCD_dmaBar->debugControl = DBG_CTL_DISABLE; ++ MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; ++ } ++ ++ MCD_chStatus[channel] = MCD_HALTED; ++ ++ return MCD_OK; ++} ++/************************ End of MCD_killDma() **********************/ ++ ++/********************************************************************/ ++/* Function: MCD_continDma ++ * Purpose: Continue a DMA which as stopped due to encountering an ++ * unready buffer descriptor. ++ * Arguments: channel - channel to continue the DMA on ++ * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK ++ * ++ * Notes: ++ * This routine does not check to see if there is a task which can ++ * be continued. Also this routine should not be used with single DMAs. ++ */ ++int MCD_continDma(int channel) ++{ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN; ++ MCD_chStatus[channel] = MCD_RUNNING; ++ ++ return MCD_OK; ++} ++/********************** End of MCD_continDma() **********************/ ++ ++/********************************************************************* ++ * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit ++ * to freeze a task and resume it. We freeze a task by breakpointing ++ * on the stated task. That is, not any specific place in the task, ++ * but any time that task executes. In particular, when that task ++ * executes, we want to freeze that task and only that task. ++ * ++ * The bits of the debug control register influence interrupts vs. ++ * breakpoints as follows: ++ * - Bits 14 and 0 enable or disable debug functions. If enabled, you ++ * will get the interrupt but you may or may not get a breakpoint. ++ * - Bits 2 and 1 decide whether you also get a breakpoint in addition ++ * to an interrupt. ++ * ++ * The debug unit can do these actions in response to either internally ++ * detected breakpoint conditions from the comparators, or in response ++ * to the external breakpoint pin, or both. ++ * - Bits 14 and 1 perform the above-described functions for ++ * internally-generated conditions, i.e., the debug comparators. ++ * - Bits 0 and 2 perform the above-described functions for external ++ * conditions, i.e., the breakpoint external pin. ++ * ++ * Note that, although you "always" get the interrupt when you turn ++ * the debug functions, the interrupt can nevertheless, if desired, be ++ * masked by the corresponding bit in the PTD's IMR. Note also that ++ * this means that bits 14 and 0 must enable debug functions before ++ * bits 1 and 2, respectively, have any effect. ++ * ++ * NOTE: It's extremely important to not pause more than one DMA channel ++ * at a time. ++ ********************************************************************/ ++ ++/********************************************************************/ ++/* Function: MCD_pauseDma ++ * Purpose: Pauses the DMA on a given channel (if any DMA is running ++ * on that channel). ++ * Arguments: channel ++ * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK ++ */ ++int MCD_pauseDma(int channel) ++{ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) { ++ MCD_dmaBar->debugComp1 = channel; ++ MCD_dmaBar->debugControl = ++ DBG_CTL_ENABLE | (1 << (channel + 16)); ++ MCD_chStatus[channel] = MCD_PAUSED; ++ } ++ ++ return MCD_OK; ++} ++/************************* End of MCD_pauseDma() ********************/ ++ ++/********************************************************************/ ++/* Function: MCD_resumeDma ++ * Purpose: Resumes the DMA on a given channel (if any DMA is ++ * running on that channel). ++ * Arguments: channel - channel on which to resume DMA ++ * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK ++ */ ++int MCD_resumeDma(int channel) ++{ ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) ++ MCD_resmActions(channel); ++ ++ return MCD_OK; ++} ++/************************ End of MCD_resumeDma() ********************/ ++ ++/********************************************************************/ ++/* Function: MCD_csumQuery ++ * Purpose: Provide the checksum after performing a non-chained DMA ++ * Arguments: channel - channel to report on ++ * csum - pointer to where to write the checksum/CRC ++ * Returns: MCD_ERROR if the channel is invalid, else MCD_OK ++ * ++ * Notes: ++ * ++ */ ++int MCD_csumQuery(int channel, u32 *csum) ++{ ++#ifdef MCD_INCLUDE_EU ++ if ((channel < 0) || (channel >= NCHANNELS)) ++ return MCD_CHANNEL_INVALID; ++ ++ *csum = MCD_relocBuffDesc[channel].csumResult; ++ return MCD_OK; ++#else ++ return MCD_ERROR; ++#endif ++} ++/*********************** End of MCD_resumeDma() *********************/ ++ ++/********************************************************************/ ++/* Function: MCD_getCodeSize ++ * Purpose: Provide the size requirements of the microcoded tasks ++ * Returns: Size in bytes ++ */ ++int MCD_getCodeSize(void) ++{ ++#ifdef MCD_INCLUDE_EU ++ return 0x2b64; ++#else ++ return 0x1744; ++#endif ++} ++/********************** End of MCD_getCodeSize() ********************/ ++ ++/********************************************************************/ ++/* Function: MCD_getVersion ++ * Purpose: Provide the version string and number ++ * Arguments: longVersion - user supplied pointer to a pointer to a char ++ * which points to the version string ++ * Returns: Version number and version string (by reference) ++ */ ++char MCD_versionString[] = "Multi-channel DMA API v1.0"; ++#define MCD_REV_MAJOR 0x01 ++#define MCD_REV_MINOR 0x00 ++ ++int MCD_getVersion(char **longVersion) ++{ ++ int ret = 0; ++ *longVersion = MCD_versionString; ++ ret = (MCD_REV_MAJOR << 8) | MCD_REV_MINOR; ++ return ret; ++} ++/********************** End of MCD_getVersion() *********************/ ++ ++/********************************************************************/ ++/* Private version of memcpy() ++ * Note that everything this is used for is longword-aligned. ++ */ ++static void MCD_memcpy(int *dest, int *src, u32 size) ++{ ++ u32 i; ++ ++ for (i = 0; i < size; i += sizeof(int), dest++, src++) ++ *dest = *src; ++} ++/********************************************************************/ +--- /dev/null ++++ b/drivers/dma/MCD_progCheck.h +@@ -0,0 +1,29 @@ ++/* ++ * drivers/dma/MCD_progCheck.h ++ * ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* This file is autogenerated. Do not change */ ++ ++#define CURRBD 4 ++#define DCOUNT 6 ++#define DESTPTR 5 ++#define SRCPTR 7 +--- /dev/null ++++ b/drivers/dma/MCD_tasks.c +@@ -0,0 +1,2457 @@ ++/* ++ * drivers/dma/MCD_tasks.c ++ * ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include "MCD_dma.h" ++ ++u32 MCD_varTab0[]; ++u32 MCD_varTab1[]; ++u32 MCD_varTab2[]; ++u32 MCD_varTab3[]; ++u32 MCD_varTab4[]; ++u32 MCD_varTab5[]; ++u32 MCD_varTab6[]; ++u32 MCD_varTab7[]; ++u32 MCD_varTab8[]; ++u32 MCD_varTab9[]; ++u32 MCD_varTab10[]; ++u32 MCD_varTab11[]; ++u32 MCD_varTab12[]; ++u32 MCD_varTab13[]; ++u32 MCD_varTab14[]; ++u32 MCD_varTab15[]; ++ ++u32 MCD_funcDescTab0[]; ++#ifdef MCD_INCLUDE_EU ++u32 MCD_funcDescTab1[]; ++u32 MCD_funcDescTab2[]; ++u32 MCD_funcDescTab3[]; ++u32 MCD_funcDescTab4[]; ++u32 MCD_funcDescTab5[]; ++u32 MCD_funcDescTab6[]; ++u32 MCD_funcDescTab7[]; ++u32 MCD_funcDescTab8[]; ++u32 MCD_funcDescTab9[]; ++u32 MCD_funcDescTab10[]; ++u32 MCD_funcDescTab11[]; ++u32 MCD_funcDescTab12[]; ++u32 MCD_funcDescTab13[]; ++u32 MCD_funcDescTab14[]; ++u32 MCD_funcDescTab15[]; ++#endif ++ ++u32 MCD_contextSave0[]; ++u32 MCD_contextSave1[]; ++u32 MCD_contextSave2[]; ++u32 MCD_contextSave3[]; ++u32 MCD_contextSave4[]; ++u32 MCD_contextSave5[]; ++u32 MCD_contextSave6[]; ++u32 MCD_contextSave7[]; ++u32 MCD_contextSave8[]; ++u32 MCD_contextSave9[]; ++u32 MCD_contextSave10[]; ++u32 MCD_contextSave11[]; ++u32 MCD_contextSave12[]; ++u32 MCD_contextSave13[]; ++u32 MCD_contextSave14[]; ++u32 MCD_contextSave15[]; ++ ++u32 MCD_realTaskTableSrc[] = { ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab0, /* Task 0 Variable Table */ ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave0, /* Task 0 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab1, /* Task 1 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave1, /* Task 1 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab2, /* Task 2 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave2, /* Task 2 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab3, /* Task 3 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave3, /* Task 3 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab4, /* Task 4 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave4, /* Task 4 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab5, /* Task 5 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave5, /* Task 5 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab6, /* Task 6 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave6, /* Task 6 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab7, /* Task 7 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave7, /* Task 7 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab8, /* Task 8 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave8, /* Task 8 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab9, /* Task 9 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave9, /* Task 9 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab10, /* Task 10 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave10, /* Task 10 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab11, /* Task 11 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave11, /* Task 11 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab12, /* Task 12 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave12, /* Task 12 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab13, /* Task 13 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave13, /* Task 13 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab14, /* Task 14 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave14, /* Task 14 context save space */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_varTab15, /* Task 15 Variable Table */ ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */ ++#else ++ (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ ++#endif ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_contextSave15, /* Task 15 context save space */ ++ 0x00000000, ++}; ++ ++ ++u32 MCD_varTab0[] = { ++/* Task 0 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++ ++u32 MCD_varTab1[] = { ++/* Task 1 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab2[] = { ++/* Task 2 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab3[] = { ++/* Task 3 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab4[] = { ++/* Task 4 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab5[] = { ++/* Task 5 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab6[] = { ++/* Task 6 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab7[] = { ++/* Task 7 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab8[] = { ++/* Task 8 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab9[] = { ++/* Task 9 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab10[] = { ++/* Task 10 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab11[] = { ++/* Task 11 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab12[] = { ++/* Task 12 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab13[] = { ++/* Task 13 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab14[] = { ++/* Task 14 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_varTab15[] = { ++/* Task 15 Variable Table */ ++ 0x00000000, /* var[0] */ ++ 0x00000000, /* var[1] */ ++ 0x00000000, /* var[2] */ ++ 0x00000000, /* var[3] */ ++ 0x00000000, /* var[4] */ ++ 0x00000000, /* var[5] */ ++ 0x00000000, /* var[6] */ ++ 0x00000000, /* var[7] */ ++ 0x00000000, /* var[8] */ ++ 0x00000000, /* var[9] */ ++ 0x00000000, /* var[10] */ ++ 0x00000000, /* var[11] */ ++ 0x00000000, /* var[12] */ ++ 0x00000000, /* var[13] */ ++ 0x00000000, /* var[14] */ ++ 0x00000000, /* var[15] */ ++ 0x00000000, /* var[16] */ ++ 0x00000000, /* var[17] */ ++ 0x00000000, /* var[18] */ ++ 0x00000000, /* var[19] */ ++ 0x00000000, /* var[20] */ ++ 0x00000000, /* var[21] */ ++ 0x00000000, /* var[22] */ ++ 0x00000000, /* var[23] */ ++ 0xe0000000, /* inc[0] */ ++ 0x20000000, /* inc[1] */ ++ 0x2000ffff, /* inc[2] */ ++ 0x00000000, /* inc[3] */ ++ 0x00000000, /* inc[4] */ ++ 0x00000000, /* inc[5] */ ++ 0x00000000, /* inc[6] */ ++ 0x00000000, /* inc[7] */ ++}; ++ ++u32 MCD_funcDescTab0[] = { ++/* Task 0 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++#ifdef MCD_INCLUDE_EU ++u32 MCD_funcDescTab1[] = { ++/* Task 1 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab2[] = { ++/* Task 2 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab3[] = { ++/* Task 3 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab4[] = { ++/* Task 4 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab5[] = { ++/* Task 5 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab6[] = { ++/* Task 6 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab7[] = { ++/* Task 7 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab8[] = { ++/* Task 8 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab9[] = { ++/* Task 9 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab10[] = { ++/* Task 10 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab11[] = { ++/* Task 11 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab12[] = { ++/* Task 12 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab13[] = { ++/* Task 13 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab14[] = { ++/* Task 14 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++ ++u32 MCD_funcDescTab15[] = { /* Task 15 Function Descriptor Table */ ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0xa0045670, /* mainFunc(), EU# 3 */ ++ 0xa0000000, /* rsduFunc(), EU# 3 */ ++ 0xa0000000, /* crcAccumVal(), EU# 3 */ ++ 0x20000000, /* setCrcAccum(), EU# 3 */ ++ 0x21800000, /* and(), EU# 3 */ ++ 0x21e00000, /* or(), EU# 3 */ ++ 0x20400000, /* add(), EU# 3 */ ++ 0x20500000, /* sub(), EU# 3 */ ++ 0x205a0000, /* andNot(), EU# 3 */ ++ 0x20a00000, /* shiftR(), EU# 3 */ ++ 0x202fa000, /* andReadyBit(), EU# 3 */ ++ 0x202f9000, /* andNotReadyBit(), EU# 3 */ ++ 0x202ea000, /* andWrapBit(), EU# 3 */ ++ 0x202da000, /* andLastBit(), EU# 3 */ ++ 0x202e2000, /* andInterruptBit(), EU# 3 */ ++ 0x202f2000, /* andCrcRestartBit(), EU# 3 */ ++}; ++#endif /*MCD_INCLUDE_EU*/ ++ ++u32 MCD_contextSave0[128]; /* Task 0 context save space */ ++u32 MCD_contextSave1[128]; /* Task 1 context save space */ ++u32 MCD_contextSave2[128]; /* Task 2 context save space */ ++u32 MCD_contextSave3[128]; /* Task 3 context save space */ ++u32 MCD_contextSave4[128]; /* Task 4 context save space */ ++u32 MCD_contextSave5[128]; /* Task 5 context save space */ ++u32 MCD_contextSave6[128]; /* Task 6 context save space */ ++u32 MCD_contextSave7[128]; /* Task 7 context save space */ ++u32 MCD_contextSave8[128]; /* Task 8 context save space */ ++u32 MCD_contextSave9[128]; /* Task 9 context save space */ ++u32 MCD_contextSave10[128]; /* Task 10 context save space */ ++u32 MCD_contextSave11[128]; /* Task 11 context save space */ ++u32 MCD_contextSave12[128]; /* Task 12 context save space */ ++u32 MCD_contextSave13[128]; /* Task 13 context save space */ ++u32 MCD_contextSave14[128]; /* Task 14 context save space */ ++u32 MCD_contextSave15[128]; /* Task 15 context save space */ ++ ++u32 MCD_ChainNoEu_TDT[]; ++u32 MCD_SingleNoEu_TDT[]; ++#ifdef MCD_INCLUDE_EU ++u32 MCD_ChainEu_TDT[]; ++u32 MCD_SingleEu_TDT[]; ++#endif ++u32 MCD_ENetRcv_TDT[]; ++u32 MCD_ENetXmit_TDT[]; ++ ++u32 MCD_modelTaskTableSrc[] = { ++ (u32)MCD_ChainNoEu_TDT, ++ (u32)&((u8 *)MCD_ChainNoEu_TDT)[0x0000016c], ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_SingleNoEu_TDT, ++ (u32)&((u8 *)MCD_SingleNoEu_TDT)[0x000000d4], ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++#ifdef MCD_INCLUDE_EU ++ (u32)MCD_ChainEu_TDT, ++ (u32)&((u8 *)MCD_ChainEu_TDT)[0x000001b4], ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_SingleEu_TDT, ++ (u32)&((u8 *)MCD_SingleEu_TDT)[0x00000124], ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++#endif ++ (u32)MCD_ENetRcv_TDT, ++ (u32)&((u8 *)MCD_ENetRcv_TDT)[0x000000a4], ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ (u32)MCD_ENetXmit_TDT, ++ (u32)&((u8 *)MCD_ENetXmit_TDT)[0x000000d0], ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++}; ++u32 MCD_ChainNoEu_TDT[] = { ++ 0x80004000, ++ 0x8118801b, ++ 0xb8c60018, ++ 0x10002b10, ++ 0x7000000d, ++ 0x018cf89f, ++ 0x6000000a, ++ 0x080cf89f, ++ 0x000001f8, ++ 0x98180364, ++ 0x8118801b, ++ 0xf8c6001a, ++ 0xb8c6601b, ++ 0x10002710, ++ 0x00000f18, ++ 0xb8c6001d, ++ 0x10001310, ++ 0x60000007, ++ 0x014cf88b, ++ 0x98c6001c, ++ 0x00000710, ++ 0x98c70018, ++ 0x10001f10, ++ 0x0000c818, ++ 0x000001f8, /* 0060(:0): NOP */ ++ 0xc1476018, ++ 0xc003231d, ++ 0x811a601b, ++ 0xc1862102, ++ 0x849be009, ++ 0x03fed7b8, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x1000cb20, ++ 0x70000006, ++ 0x088cf88f, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf88f, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf88f, ++ 0x1000cb38, ++ 0x0000c728, ++ 0x000001f8, /* 00B0(:0): NOP */ ++ 0xc1476018, ++ 0xc003241d, ++ 0x811a601b, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x0000d3a0, ++ 0xc1862102, ++ 0x849be009, ++ 0x0bfed7b8, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x1000cb20, ++ 0x70000006, ++ 0x088cf88f, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf88f, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf88f, ++ 0x1000cb38, ++ 0x0000c728, ++ 0x000001f8, /* 010C(:0): NOP */ ++ 0x8118801b, ++ 0xd8c60018, ++ 0x98c6601c, ++ 0x6000000b, ++ 0x0c8cfc9f, ++ 0x000001f8, /* 0124(:0): NOP */ ++ 0xa146001e, ++ 0x10000b08, ++ 0x10002050, ++ 0xb8c60018, ++ 0x10002b10, ++ 0x7000000a, ++ 0x080cf89f, ++ 0x6000000d, ++ 0x018cf89f, ++ 0x000001f8, /* 014C(:0): NOP */ ++ 0x8618801b, ++ 0x7000000e, ++ 0x084cf21f, ++ 0xd8990336, ++ 0x8019801b, ++ 0x040001f8, ++ 0x000001f8, /* 0168(:0): NOP */ ++ 0x000001f8, /* 016C(:0): NOP */ ++}; ++u32 MCD_SingleNoEu_TDT[] = { ++ 0x8198001b, ++ 0x7000000d, ++ 0x080cf81f, ++ 0x8198801b, ++ 0x6000000e, ++ 0x084cf85f, ++ 0x000001f8, /* 0018(:0): NOP */ ++ 0x8298001b, ++ 0x7000000d, ++ 0x010cf81f, ++ 0x6000000e, ++ 0x018cf81f, ++ 0xc202601b, ++ 0xc002221c, ++ 0x809a601b, ++ 0xc10420c2, ++ 0x839be009, ++ 0x03fed7b8, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x70000006, ++ 0x088cf889, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf889, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf889, ++ 0x0000cb38, ++ 0x000001f8, /* 0074(:0): NOP */ ++ 0xc202601b, ++ 0xc002229c, ++ 0x809a601b, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x0000d3a0, ++ 0xc10420c2, ++ 0x839be009, ++ 0x0bfed7b8, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x70000006, ++ 0x088cf889, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf889, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf889, ++ 0x0000cb38, ++ 0x000001f8, /* 00C8(:0): NOP */ ++ 0xc318022d, ++ 0x8018801b, ++ 0x040001f8, ++}; ++#ifdef MCD_INCLUDE_EU ++u32 MCD_ChainEu_TDT[] = { ++ 0x80004000, ++ 0x8198801b, ++ 0xb8c68018, ++ 0x10002f10, ++ 0x7000000d, ++ 0x01ccf89f, ++ 0x6000000a, ++ 0x080cf89f, ++ 0x000001f8, ++ 0x981803a4, ++ 0x8198801b, ++ 0xf8c6801a, ++ 0xb8c6e01b, ++ 0x10002b10, ++ 0x00001318, ++ 0xb8c6801d, ++ 0x10001710, ++ 0x60000007, ++ 0x018cf88c, ++ 0x98c6801c, ++ 0x00000b10, ++ 0x98c78018, ++ 0x10002310, ++ 0x0000c820, ++ 0x000001f8, /* 0060(:0): NOP */ ++ 0x8698801b, ++ 0x7000000f, ++ 0x084cf2df, ++ 0xd899042d, ++ 0x8019801b, ++ 0x60000003, ++ 0x2cd7c7df, /* 007C(:979): DRD2B2: EU3(var13) */ ++ 0xd8990364, ++ 0x8019801b, ++ 0x60000003, ++ 0x2c17c7df, /* 008C(:981): DRD2B2: EU3(var1) */ ++ 0x000001f8, /* 0090(:0): NOP */ ++ 0xc1c7e018, ++ 0xc003a35e, ++ 0x819a601b, ++ 0xc206a142, ++ 0x851be009, ++ 0x63fe0000, ++ 0x0d4cfddf, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x70000002, ++ 0x004cf81f, ++ 0x1000cb20, ++ 0x70000006, ++ 0x088cf891, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf891, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf891, ++ 0x1000cb38, ++ 0x0000c728, ++ 0x000001f8, /* 00EC(:0): NOP */ ++ 0xc1c7e018, ++ 0xc003a49e, ++ 0x819a601b, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x0000d3a0, ++ 0xc206a142, ++ 0x851be009, ++ 0x6bfe0000, ++ 0x0d4cfddf, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x70000002, ++ 0x004cf81f, ++ 0x1000cb20, ++ 0x70000006, ++ 0x088cf891, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf891, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf891, ++ 0x1000cb38, ++ 0x0000c728, ++ 0x000001f8, /* 0154(:0): NOP */ ++ 0x8198801b, ++ 0xd8c68018, ++ 0x98c6e01c, ++ 0x6000000b, ++ 0x0c8cfc9f, ++ 0x0000cc08, ++ 0xa1c6801e, ++ 0x10000f08, ++ 0x10002458, ++ 0xb8c68018, ++ 0x10002f10, ++ 0x7000000a, ++ 0x080cf89f, ++ 0x6000000d, ++ 0x01ccf89f, ++ 0x000001f8, /* 0194(:0): NOP */ ++ 0x8698801b, ++ 0x7000000e, ++ 0x084cf25f, ++ 0xd899037f, ++ 0x8019801b, ++ 0x040001f8, ++ 0x000001f8, /* 01B0(:0): NOP */ ++ 0x000001f8, /* 01B4(:0): NOP */ ++}; ++u32 MCD_SingleEu_TDT[] = { ++ 0x8218001b, ++ 0x7000000d, ++ 0x080cf81f, ++ 0x8218801b, ++ 0x6000000e, ++ 0x084cf85f, ++ 0x000001f8, /* 0018(:0): NOP */ ++ 0x8318001b, ++ 0x7000000d, ++ 0x014cf81f, ++ 0x6000000e, ++ 0x01ccf81f, ++ 0x8498001b, ++ 0x7000000f, ++ 0x080cf19f, ++ 0xd81882a4, ++ 0x8019001b, ++ 0x60000003, ++ 0x2c97c7df, ++ 0xd818826d, ++ 0x8019001b, ++ 0x60000003, ++ 0x2c17c7df, ++ 0x000001f8, /* 005C(:0): NOP */ ++ 0xc282e01b, ++ 0xc002a25e, ++ 0x811a601b, ++ 0xc184a102, ++ 0x841be009, ++ 0x63fe0000, ++ 0x0d4cfddf, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x70000002, ++ 0x004cf99f, ++ 0x70000006, ++ 0x088cf88b, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf88b, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf88b, ++ 0x0000cb38, ++ 0x000001f8, /* 00B0(:0): NOP */ ++ 0xc282e01b, ++ 0xc002a31e, ++ 0x811a601b, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x0000d3a0, ++ 0xc184a102, ++ 0x841be009, ++ 0x6bfe0000, ++ 0x0d4cfddf, ++ 0xda9b001b, ++ 0x9b9be01b, ++ 0x70000002, ++ 0x004cf99f, ++ 0x70000006, ++ 0x088cf88b, ++ 0x1000cb28, ++ 0x70000006, ++ 0x088cf88b, ++ 0x1000cb30, ++ 0x70000006, ++ 0x088cf88b, ++ 0x0000cb38, ++ 0x000001f8, /* 0110(:0): NOP */ ++ 0x8144801c, ++ 0x0000c008, ++ 0xc398027f, ++ 0x8018801b, ++ 0x040001f8, ++}; ++#endif ++u32 MCD_ENetRcv_TDT[] = { ++ 0x80004000, ++ 0x81988000, ++ 0x10000788, ++ 0x6000000a, ++ 0x080cf05f, ++ 0x98180209, ++ 0x81c40004, ++ 0x7000000e, ++ 0x010cf05f, ++ 0x7000000c, ++ 0x01ccf05f, ++ 0x70000004, ++ 0x014cf049, ++ 0x70000004, ++ 0x004cf04a, ++ 0x00000b88, ++ 0xc4030150, ++ 0x8119e012, ++ 0x03e0cf90, ++ 0x81188000, ++ 0x000ac788, ++ 0xc4030000, ++ 0x8199e000, ++ 0x63e00004, ++ 0x084cfc8b, ++ 0xd8990000, ++ 0x9999e000, ++ 0x60000005, ++ 0x0cccf841, ++ 0x81c60000, ++ 0xc399021b, ++ 0x80198000, ++ 0x00008400, ++ 0x00000f08, ++ 0x81988000, ++ 0x10000788, ++ 0x6000000a, ++ 0x080cf05f, ++ 0xc2188209, ++ 0x80190000, ++ 0x040001f8, ++ 0x000001f8, ++}; ++u32 MCD_ENetXmit_TDT[] = { ++ 0x80004000, ++ 0x81988000, ++ 0x10000788, ++ 0x6000000a, ++ 0x080cf05f, ++ 0x98180309, ++ 0x80004003, ++ 0x81c60004, ++ 0x7000000e, ++ 0x014cf05f, ++ 0x7000000c, ++ 0x028cf05f, ++ 0x7000000d, ++ 0x018cf05f, ++ 0x70000004, ++ 0x01ccf04d, ++ 0x10000b90, ++ 0x60000004, ++ 0x020cf0a1, ++ 0xc3188312, ++ 0x83c70000, ++ 0x00001f10, ++ 0xc583a3c3, ++ 0x81042325, ++ 0x03e0c798, ++ 0xd8990000, ++ 0x9999e000, ++ 0x000acf98, ++ 0xd8992306, ++ 0x9999e03f, ++ 0x03eac798, ++ 0xd8990000, ++ 0x9999e000, ++ 0x000acf98, ++ 0xd8990000, ++ 0x99832302, ++ 0x0beac798, ++ 0x81988000, ++ 0x6000000b, ++ 0x0c4cfc5f, ++ 0x81c80000, ++ 0xc5190312, ++ 0x80198000, ++ 0x00008400, ++ 0x00000f08, ++ 0x81988000, ++ 0x10000788, ++ 0x6000000a, ++ 0x080cf05f, ++ 0xc2988309, ++ 0x80190000, ++ 0x040001f8, ++ 0x000001f8, ++}; ++ ++#ifdef MCD_INCLUDE_EU ++MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; ++#endif +--- /dev/null ++++ b/drivers/dma/MCD_tasksInit.c +@@ -0,0 +1,271 @@ ++/* ++ * drivers/dma/MCD_tasksInit.c ++ * ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * Autogenerated - Do not edit! ++ */ ++ ++#include "MCD_dma.h" ++ ++extern dmaRegs *MCD_dmaBar; ++ ++ ++/* ++ * Task 0 ++ */ ++ ++void MCD_startDmaChainNoEu(int *currBD, short srcIncr, ++ short destIncr, int xferSize, short xferSizeIncr, ++ int *cSave, volatile TaskTableEntry *taskTable, ++ int channel) ++{ ++ MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ ++ MCD_SET_VAR(taskTable+channel, 25, ++ (u32)(0xe000 << 16) | (0xffff & srcIncr)); ++ ++ /* inc[1] */ ++ MCD_SET_VAR(taskTable+channel, 24, ++ (u32)(0xe000 << 16) | (0xffff & destIncr)); ++ /* inc[0] */ ++ MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */ ++ MCD_SET_VAR(taskTable+channel, 26, ++ (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); ++ /* inc[2] */ ++ MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ ++ MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ ++ MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */ ++ MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ ++ MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ ++ MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ ++ MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ ++ MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ ++ MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ ++ MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ ++ MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ ++ MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */ ++ MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */ ++ MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ ++ MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */ ++ MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ ++ MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ ++ MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */ ++ MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */ ++ ++ /* Set the task's Enable bit in its Task Control Register */ ++ MCD_dmaBar->taskControl[channel] |= (u16)0x8000; ++} ++ ++ ++/* ++ * Task 1 ++ */ ++ ++void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, ++ char *destAddr, short destIncr, int dmaSize, ++ short xferSizeIncr, int flags, int *currBD, int *cSave, ++ volatile TaskTableEntry *taskTable, int channel) ++{ ++ MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */ ++ MCD_SET_VAR(taskTable+channel, 25, ++ (u32)(0xe000 << 16) | (0xffff & srcIncr)); ++ /* inc[1] */ ++ MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */ ++ MCD_SET_VAR(taskTable+channel, 24, ++ (u32)(0xe000 << 16) | (0xffff & destIncr)); ++ /* inc[0] */ ++ MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */ ++ MCD_SET_VAR(taskTable+channel, 26, ++ (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); ++ /* inc[2] */ ++ MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */ ++ MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */ ++ MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ ++ MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ ++ MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ ++ MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ ++ MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */ ++ MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */ ++ MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ ++ MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */ ++ MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */ ++ ++ /* Set the task's Enable bit in its Task Control Register */ ++ MCD_dmaBar->taskControl[channel] |= (u16)0x8000; ++} ++ ++ ++/* ++ * Task 2 ++ */ ++ ++void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, ++ int xferSize, short xferSizeIncr, int *cSave, ++ volatile TaskTableEntry *taskTable, int channel) ++{ ++ ++ MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ ++ MCD_SET_VAR(taskTable+channel, 25, ++ (u32)(0xe000 << 16) | (0xffff & srcIncr)); ++ /* inc[1] */ ++ MCD_SET_VAR(taskTable+channel, 24, ++ (u32)(0xe000 << 16) | (0xffff & destIncr)); ++ /* inc[0] */ ++ MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); ++ /* var[12] */ ++ MCD_SET_VAR(taskTable+channel, 26, ++ (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); ++ /* inc[2] */ ++ MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ ++ MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ ++ MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ ++ MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ ++ MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ ++ MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ ++ MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ ++ MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ ++ MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ ++ MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ ++ MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */ ++ MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */ ++ MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */ ++ MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */ ++ MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */ ++ MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */ ++ MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */ ++ MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ ++ MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ ++ MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */ ++ MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ ++ MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ ++ ++ /* Set the task's Enable bit in its Task Control Register */ ++ MCD_dmaBar->taskControl[channel] |= (u16)0x8000; ++} ++ ++ ++/* ++ * Task 3 ++ */ ++ ++void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, ++ char *destAddr, short destIncr, int dmaSize, ++ short xferSizeIncr, int flags, int *currBD, int *cSave, ++ volatile TaskTableEntry *taskTable, int channel) ++{ ++ MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */ ++ MCD_SET_VAR(taskTable+channel, 25, ++ (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ ++ MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */ ++ MCD_SET_VAR(taskTable+channel, 24, ++ (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ ++ MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */ ++ MCD_SET_VAR(taskTable+channel, 26, ++ (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ ++ MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */ ++ MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ ++ MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ ++ MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ ++ MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ ++ MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ ++ MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ ++ MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */ ++ MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */ ++ MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */ ++ MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ ++ MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */ ++ MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ ++ MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ ++ MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ ++ ++ /* Set the task's Enable bit in its Task Control Register */ ++ MCD_dmaBar->taskControl[channel] |= (u16)0x8000; ++} ++ ++ ++/* ++ * Task 4 ++ */ ++ ++void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, ++ volatile TaskTableEntry *taskTable, int channel) ++{ ++ MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ ++ MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ ++ MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */ ++ MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ ++ MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ ++ MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ ++ MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ ++ MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ ++ MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ ++ MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */ ++ MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */ ++ MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */ ++ MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */ ++ MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ ++ MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ ++ MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */ ++ MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */ ++ ++ /* Set the task's Enable bit in its Task Control Register */ ++ MCD_dmaBar->taskControl[channel] |= (u16)0x8000; ++} ++ ++ ++/* ++ * Task 5 ++ */ ++ ++void MCD_startDmaENetXmit(char *bDBase, char *currBD, ++ char *xmitFifoPtr, volatile TaskTableEntry *taskTable, ++ int channel) ++{ ++ MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ ++ MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ ++ MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */ ++ MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ ++ MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ ++ MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ ++ MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ ++ MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ ++ MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ ++ MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ ++ MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ ++ MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ ++ MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ ++ MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */ ++ MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */ ++ MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ ++ MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */ ++ MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ ++ MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ ++ MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */ ++ MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */ ++ MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */ ++ MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ ++ MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */ ++ MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */ ++ ++ /* Set the task's Enable bit in its Task Control Register */ ++ MCD_dmaBar->taskControl[channel] |= (u16)0x8000; ++} +--- /dev/null ++++ b/drivers/dma/MCD_tasksInit.h +@@ -0,0 +1,84 @@ ++/* ++ * drivers/dma/MCD_tasksInit.h ++ * ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ * Shrek Wu b16972@freescale.com ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef MCD_TSK_INIT_H ++#define MCD_TSK_INIT_H 1 ++ ++/* ++ * Autogenerated - Do not edit! ++ */ ++ ++/* ++ * Task 0 ++ */ ++void MCD_startDmaChainNoEu(int *currBD, short srcIncr, ++ short destIncr, int xferSize, ++ short xferSizeIncr, int *cSave, ++ volatile TaskTableEntry *taskTable, ++ int channel); ++ ++ ++/* ++ * Task 1 ++ */ ++void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, ++ char *destAddr, short destIncr, int dmaSize, ++ short xferSizeIncr, int flags, int *currBD, ++ int *cSave, volatile TaskTableEntry *taskTable, ++ int channel); ++ ++ ++/* ++ * Task 2 ++ */ ++void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, ++ int xferSize, short xferSizeIncr, int *cSave, ++ volatile TaskTableEntry *taskTable, ++ int channel); ++ ++ ++/* ++ * Task 3 ++ */ ++void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, ++ char *destAddr, short destIncr, int dmaSize, ++ short xferSizeIncr, int flags, int *currBD, ++ int *cSave, volatile TaskTableEntry *taskTable, ++ int channel); ++ ++ ++/* ++ * Task 4 ++ */ ++void MCD_startDmaENetRcv(char *bDBase, char *currBD, ++ char *rcvFifoPtr, ++ volatile TaskTableEntry *taskTable, int channel); ++ ++ ++/* ++ * Task 5 ++ */ ++void MCD_startDmaENetXmit(char *bDBase, char *currBD, ++ char *xmitFifoPtr, ++ volatile TaskTableEntry *taskTable, int channel); ++ ++#endif /* MCD_TSK_INIT_H */ diff --git a/target/linux/coldfire/patches/014-Add-CFV4E-FPU-support-for-MCF547x-MCF548x.patch b/target/linux/coldfire/patches/014-Add-CFV4E-FPU-support-for-MCF547x-MCF548x.patch new file mode 100644 index 000000000..17c38a8ae --- /dev/null +++ b/target/linux/coldfire/patches/014-Add-CFV4E-FPU-support-for-MCF547x-MCF548x.patch @@ -0,0 +1,23 @@ +From f5d90ef1f575d712c9f061dd5e4d48aa34d73bd0 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:43 +0800 +Subject: [PATCH 14/52] Add CFV4E FPU support for MCF547x/MCF548x + +Add CFV4E FPU support for MCF547x/MCF548x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/fpu.h | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/m68k/include/asm/fpu.h ++++ b/arch/m68k/include/asm/fpu.h +@@ -14,6 +14,8 @@ + #define FPSTATESIZE (28) + #elif defined(CONFIG_M68060) + #define FPSTATESIZE (12) ++#elif defined(CONFIG_CFV4E) ++#define FPSTATESIZE (16) + #else + #define FPSTATESIZE (0) + #endif diff --git a/target/linux/coldfire/patches/015-Add-driver-to-support-ten-UART-devices-on-MCF5441x.patch b/target/linux/coldfire/patches/015-Add-driver-to-support-ten-UART-devices-on-MCF5441x.patch new file mode 100644 index 000000000..6fa3e5987 --- /dev/null +++ b/target/linux/coldfire/patches/015-Add-driver-to-support-ten-UART-devices-on-MCF5441x.patch @@ -0,0 +1,104 @@ +From a42f35579c21ffdda461031a5d2d210e27eb506a Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:43 +0800 +Subject: [PATCH 15/52] Add driver to support ten UART devices on MCF5441x + +Test CPU board: UART0(J1), UART4(J3) +Test SER2 board: UART1(J11), UART2(J31) + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/tty/serial/Kconfig | 70 ++++++++++++++++++++++++++++++++++++++++++++ + drivers/tty/serial/mcf.c | 2 +- + 2 files changed, 71 insertions(+), 1 deletions(-) + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -1070,6 +1070,76 @@ config SERIAL_MCF_CONSOLE + help + Enable a ColdFire internal serial port to be the system console. + ++config SERIAL_MCF_UART0 ++ bool "Coldfire UART0 device support" ++ depends on SERIAL_MCF && M5441X ++ default y ++ help ++ Enable ColdFire UART0 device configuration ++ ++config SERIAL_MCF_UART1 ++ bool "Coldfire UART1 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART1 device configuration ++ ++config SERIAL_MCF_UART2 ++ bool "Coldfire UART2 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART2 device configuration ++ ++config SERIAL_MCF_UART3 ++ bool "Coldfire UART3 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART3 device configuration ++ ++config SERIAL_MCF_UART4 ++ bool "Coldfire UART4 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART4 device configuration ++ ++config SERIAL_MCF_UART5 ++ bool "Coldfire UART5 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART5 device configuration ++ ++config SERIAL_MCF_UART6 ++ bool "Coldfire UART6 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART6 device configuration ++ ++config SERIAL_MCF_UART7 ++ bool "Coldfire UART7 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART7 device configuration ++ ++config SERIAL_MCF_UART8 ++ bool "Coldfire UART8 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART8 device configuration ++ ++config SERIAL_MCF_UART9 ++ bool "Coldfire UART9 device support" ++ depends on SERIAL_MCF && M5441X ++ default n ++ help ++ Enable ColdFire UART9 device configuration ++ + config SERIAL_68360_SMC + bool "68360 SMC uart support" + depends on M68360 +--- a/drivers/tty/serial/mcf.c ++++ b/drivers/tty/serial/mcf.c +@@ -527,7 +527,7 @@ static const struct uart_ops mcf_uart_op + .verify_port = mcf_verify_port, + }; + +-static struct mcf_uart mcf_ports[4]; ++static struct mcf_uart mcf_ports[MAX_PORT_NUM]; + + #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports) + diff --git a/target/linux/coldfire/patches/016-Add-nand-driver-support-for-M54418TWR-board.patch b/target/linux/coldfire/patches/016-Add-nand-driver-support-for-M54418TWR-board.patch new file mode 100644 index 000000000..e495ab81c --- /dev/null +++ b/target/linux/coldfire/patches/016-Add-nand-driver-support-for-M54418TWR-board.patch @@ -0,0 +1,1381 @@ +From 6a5c2427d53c24a30f28b8061b2cda4edad37f58 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:43 +0800 +Subject: [PATCH 16/52] Add nand driver support for M54418TWR board + +Disable hw ECC for erase block aligned pages. + +On the erase block, there's always have clean marker for jffs2, +The NFC ECC provide a fake correction on the erase block when +there're clean marker and adjust the bits on the fly when reading back. + +Disable the hw ECC on erase block aligned pages is a workaround +for jffs2 on the NAND. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/fsl_nfc.h | 330 +++++++++++++ + drivers/mtd/nand/Kconfig | 7 + + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/fsl_nfc.c | 995 +++++++++++++++++++++++++++++++++++++++ + 4 files changed, 1333 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/include/asm/fsl_nfc.h + create mode 100644 drivers/mtd/nand/fsl_nfc.c + +--- /dev/null ++++ b/arch/m68k/include/asm/fsl_nfc.h +@@ -0,0 +1,330 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: Shaohui Xie <b21989@freescale.com> ++ * ++ * Description: ++ * MPC5125/M54418TWR Nand driver. ++ * ++ * This is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef MPC5125_NFC_H ++#define MPC5125_NFC_H ++ ++ ++/* NFC PAD Define */ ++#define PAD_NFC_IO PAD_FUNC0 ++#define PAD_NFC_ALE PAD_FUNC0 ++#define PAD_NFC_CLE PAD_FUNC0 ++#define PAD_NFC_WE PAD_FUNC0 ++#define PAD_NFC_RE PAD_FUNC0 ++#define PAD_NFC_CE0 PAD_FUNC0 ++#define PAD_NFC_CE1 PAD_FUNC1 ++#define PAD_NFC_CE2 PAD_FUNC2 ++#define PAD_NFC_CE3 PAD_FUNC2 ++#define PAD_NFC_RB0 PAD_FUNC0 ++#define PAD_NFC_RB1 PAD_FUNC2 ++#define PAD_NFC_RB2 PAD_FUNC2 ++#define PAD_NFC_RB3 PAD_FUNC2 ++ ++/* NFC Control PAD Define */ ++#define BALL_NFC_CE0 IOCTL_NFC_CE0_B ++#define BALL_NFC_CE1 IOCTL_SDHC1_CLK ++#define BALL_NFC_CE2 IOCTL_PSC1_4 ++#define BALL_NFC_CE3 IOCTL_J1850_TX ++#define BALL_NFC_RB0 IOCTL_NFC_RB ++#define BALL_NFC_RB1 IOCTL_FEC1_TXD_0 ++#define BALL_NFC_RB2 IOCTL_PSC1_3 ++#define BALL_NFC_RB3 IOCTL_J1850_RX ++#define BALL_NFC_ALE IOCTL_EMB_AD19 ++#define BALL_NFC_CLE IOCTL_EMB_AD18 ++#define BALL_NFC_WE IOCTL_EMB_AD16 ++#define BALL_NFC_RE IOCTL_EMB_AD17 ++ ++/* NFC IO Pad Define */ ++#define BALL_NFC_IO0 IOCTL_EMB_AD00 ++#define BALL_NFC_IO1 IOCTL_EMB_AD01 ++#define BALL_NFC_IO2 IOCTL_EMB_AD02 ++#define BALL_NFC_IO3 IOCTL_EMB_AD03 ++#define BALL_NFC_IO4 IOCTL_EMB_AD04 ++#define BALL_NFC_IO5 IOCTL_EMB_AD05 ++#define BALL_NFC_IO6 IOCTL_EMB_AD06 ++#define BALL_NFC_IO7 IOCTL_EMB_AD07 ++ ++/* Addresses for NFC MAIN RAM BUFFER areas */ ++#define NFC_MAIN_AREA(n) ((n) * 0x1000) ++ ++/* Addresses for NFC SPARE BUFFER areas */ ++#define NFC_SPARE_BUFFERS 8 ++#define NFC_SPARE_LEN 0x10 ++#define NFC_SPARE_AREA(n) (0x800 + ((n) * NFC_SPARE_LEN)) ++ ++#define PAGE_2K 0x0800 ++#define PAGE_64 0x0040 ++ ++/* MPC5125 NFC registers */ ++/* Typical Flash Commands */ ++#define READ_PAGE_CMD_CODE 0x7EE0 ++#define PROGRAM_PAGE_CMD_CODE 0x7FC0 ++#define ERASE_CMD_CODE 0x4EC0 ++#define READ_ID_CMD_CODE 0x4804 ++#define RESET_CMD_CODE 0x4040 ++#define DMA_PROGRAM_PAGE_CMD_CODE 0xFFC8 ++#define RANDOM_IN_CMD_CODE 0x7140 ++#define RANDOM_OUT_CMD_CODE 0x70E0 ++#define STATUS_READ_CMD_CODE 0x4068 ++ ++#define PAGE_READ_CMD_BYTE1 0x00 ++#define PAGE_READ_CMD_BYTE2 0x30 ++#define PROGRAM_PAGE_CMD_BYTE1 0x80 ++#define PROGRAM_PAGE_CMD_BYTE2 0x10 ++#define READ_STATUS_CMD_BYTE 0x70 ++#define ERASE_CMD_BYTE1 0x60 ++#define ERASE_CMD_BYTE2 0xD0 ++#define READ_ID_CMD_BYTE 0x90 ++#define RESET_CMD_BYTE 0xFF ++#define RANDOM_OUT_CMD_BYTE1 0x05 ++#define RANDOM_OUT_CMD_BYTE2 0xE0 ++ ++/* NFC ECC mode define */ ++#define ECC_BYPASS 0x0 ++#define ECC_8_BYTE 0x1 ++#define ECC_12_BYTE 0x2 ++#define ECC_15_BYTE 0x3 ++#define ECC_23_BYTE 0x4 ++#define ECC_30_BYTE 0x5 ++#define ECC_45_BYTE 0x6 ++#define ECC_60_BYTE 0x7 ++#define ECC_ERROR 1 ++#define ECC_RIGHT 0 ++ ++/***************** Module-Relative Register Offsets *************************/ ++#define NFC_SRAM_BUFFER 0x0000 ++#define NFC_FLASH_CMD1 0x3F00 ++#define NFC_FLASH_CMD2 0x3F04 ++#define NFC_COL_ADDR 0x3F08 ++#define NFC_ROW_ADDR 0x3F0c ++#define NFC_FLASH_COMMAND_REPEAT 0x3F10 ++#define NFC_ROW_ADDR_INC 0x3F14 ++#define NFC_FLASH_STATUS1 0x3F18 ++#define NFC_FLASH_STATUS2 0x3F1c ++#define NFC_DMA1_ADDR 0x3F20 ++#define NFC_DMA2_ADDR 0x3F34 ++#define NFC_DMA_CONFIG 0x3F24 ++#define NFC_CACHE_SWAP 0x3F28 ++#define NFC_SECTOR_SIZE 0x3F2c ++#define NFC_FLASH_CONFIG 0x3F30 ++#define NFC_IRQ_STATUS 0x3F38 ++ ++/***************** Module-Relative Register Reset Value *********************/ ++#define NFC_SRAM_BUFFER_RSTVAL 0x00000000 ++#define NFC_FLASH_CMD1_RSTVAL 0x30FF0000 ++#define NFC_FLASH_CMD2_RSTVAL 0x007EE000 ++#define NFC_COL_ADDR_RSTVAL 0x00000000 ++#define NFC_ROW_ADDR_RSTVAL 0x11000000 ++#define NFC_FLASH_COMMAND_REPEAT_RSTVAL 0x00000000 ++#define NFC_ROW_ADDR_INC_RSTVAL 0x00000001 ++#define NFC_FLASH_STATUS1_RSTVAL 0x00000000 ++#define NFC_FLASH_STATUS2_RSTVAL 0x00000000 ++#define NFC_DMA1_ADDR_RSTVAL 0x00000000 ++#define NFC_DMA2_ADDR_RSTVAL 0x00000000 ++#define NFC_DMA_CONFIG_RSTVAL 0x00000000 ++#define NFC_CACHE_SWAP_RSTVAL 0x0FFE0FFE ++#define NFC_SECTOR_SIZE_RSTVAL 0x00000420 ++#define NFC_FLASH_CONFIG_RSTVAL 0x000EA631 ++#define NFC_IRQ_STATUS_RSTVAL 0x04000000 ++ ++/***************** Module-Relative Register Mask *************************/ ++ ++/* NFC_FLASH_CMD1 Field */ ++#define CMD1_MASK 0xFFFF0000 ++#define CMD1_SHIFT 0 ++#define CMD_BYTE2_MASK 0xFF000000 ++#define CMD_BYTE2_SHIFT 24 ++#define CMD_BYTE3_MASK 0x00FF0000 ++#define CMD_BYTE3_SHIFT 16 ++ ++/* NFC_FLASH_CM2 Field */ ++#define CMD2_MASK 0xFFFFFF07 ++#define CMD2_SHIFT 0 ++#define CMD_BYTE1_MASK 0xFF000000 ++#define CMD_BYTE1_SHIFT 24 ++#define CMD_CODE_MASK 0x00FFFF00 ++#define CMD_CODE_SHIFT 8 ++#define BUFNO_MASK 0x00000006 ++#define BUFNO_SHIFT 1 ++#define BUSY_MASK 0x00000001 ++#define BUSY_SHIFT 0 ++#define START_MASK 0x00000001 ++#define START_SHIFT 0 ++ ++/* NFC_COL_ADDR Field */ ++#define COL_ADDR_MASK 0x0000FFFF ++#define COL_ADDR_SHIFT 0 ++#define COL_ADDR_COL_ADDR2_MASK 0x0000FF00 ++#define COL_ADDR_COL_ADDR2_SHIFT 8 ++#define COL_ADDR_COL_ADDR1_MASK 0x000000FF ++#define COL_ADDR_COL_ADDR1_SHIFT 0 ++ ++/* NFC_ROW_ADDR Field */ ++#define ROW_ADDR_MASK 0x00FFFFFF ++#define ROW_ADDR_SHIFT 0 ++#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 ++#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 ++#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 ++#define ROW_ADDR_CHIP_SEL_SHIFT 24 ++#define ROW_ADDR_ROW_ADDR3_MASK 0x00FF0000 ++#define ROW_ADDR_ROW_ADDR3_SHIFT 16 ++#define ROW_ADDR_ROW_ADDR2_MASK 0x0000FF00 ++#define ROW_ADDR_ROW_ADDR2_SHIFT 8 ++#define ROW_ADDR_ROW_ADDR1_MASK 0x000000FF ++#define ROW_ADDR_ROW_ADDR1_SHIFT 0 ++ ++/* NFC_FLASH_COMMAND_REPEAT Field */ ++#define COMMAND_REPEAT_MASK 0x0000FFFF ++#define COMMAND_REPEAT_SHIFT 0 ++#define COMMAND_REPEAT_REPEAT_COUNT_MASK 0x0000FFFF ++#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT 0 ++ ++/* NFC_ROW_ADDR_INC Field */ ++#define ROW_ADDR_INC_MASK 0x00FFFFFF ++#define ROW_ADDR_INC_SHIFT 0 ++#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK 0x00FF0000 ++#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT 16 ++#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK 0x0000FF00 ++#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT 8 ++#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK 0x000000FF ++#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT 0 ++ ++/* NFC_FLASH_STATUS1 Field */ ++#define STATUS1_MASK 0xFFFFFFFF ++#define STATUS1_SHIFT 0 ++#define STATUS1_ID_BYTE1_MASK 0xFF000000 ++#define STATUS1_ID_BYTE1_SHIFT 24 ++#define STATUS1_ID_BYTE2_MASK 0x00FF0000 ++#define STATUS1_ID_BYTE2_SHIFT 16 ++#define STATUS1_ID_BYTE3_MASK 0x0000FF00 ++#define STATUS1_ID_BYTE3_SHIFT 8 ++#define STATUS1_ID_BYTE4_MASK 0x000000FF ++#define STATUS1_ID_BYTE4_SHIFT 0 ++ ++/* NFC_FLASH_STATUS2 Field */ ++#define STATUS2_MASK 0xFF0000FF ++#define STATUS2_SHIFT 0 ++#define STATUS2_ID_BYTE5_MASK 0xFF000000 ++#define STATUS2_ID_BYTE5_SHIFT 24 ++#define STATUS_BYTE1_MASK 0x000000FF ++#define STATUS2_STATUS_BYTE1_SHIFT 0 ++ ++/* NFC_DMA1_ADDR Field */ ++#define DMA1_ADDR_MASK 0xFFFFFFFF ++#define DMA1_ADDR_SHIFT 0 ++#define DMA1_ADDR_DMA1_ADDR_MASK 0xFFFFFFFF ++#define DMA1_ADDR_DMA1_ADDR_SHIFT 0 ++ ++/* DMA2_ADDR Field */ ++#define DMA2_ADDR_MASK 0xFFFFFFFF ++#define DMA2_ADDR_SHIFT 0 ++#define DMA2_ADDR_DMA2_ADDR_MASK 0xFFFFFFFF ++#define DMA2_ADDR_DMA2_ADDR_SHIFT 0 ++ ++/* DMA_CONFIG Field */ ++#define DMA_CONFIG_MASK 0xFFFFFFFF ++#define DMA_CONFIG_SHIFT 0 ++#define DMA_CONFIG_DMA1_CNT_MASK 0xFFF00000 ++#define DMA_CONFIG_DMA1_CNT_SHIFT 20 ++#define DMA_CONFIG_DMA2_CNT_MASK 0x000FE000 ++#define DMA_CONFIG_DMA2_CNT_SHIFT 13 ++#define DMA_CONFIG_DMA2_OFFSET_MASK 0x00001FC0 ++#define DMA_CONFIG_DMA2_OFFSET_SHIFT 2 ++#define DMA_CONFIG_DMA1_ACT_MASK 0x00000002 ++#define DMA_CONFIG_DMA1_ACT_SHIFT 1 ++#define DMA_CONFIG_DMA2_ACT_MASK 0x00000001 ++#define DMA_CONFIG_DMA2_ACT_SHIFT 0 ++ ++/* NFC_CACHE_SWAP Field */ ++#define CACHE_SWAP_MASK 0x0FFE0FFE ++#define CACHE_SWAP_SHIFT 1 ++#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK 0x0FFE0000 ++#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT 17 ++#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK 0x00000FFE ++#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT 1 ++ ++/* NFC_SECTOR_SIZE Field */ ++#define SECTOR_SIZE_MASK 0x00001FFF ++#define SECTOR_SIZE_SHIFT 0 ++#define SECTOR_SIZE_SECTOR_SIZE_MASK 0x00001FFF ++#define SECTOR_SIZE_SECTOR_SIZE_SHIFT 0 ++ ++/* NFC_FLASH_CONFIG Field */ ++#define CONFIG_MASK 0xFFFFFFFF ++#define CONFIG_SHIFT 0 ++#define CONFIG_STOP_ON_WERR_MASK 0x80000000 ++#define CONFIG_STOP_ON_WERR_SHIFT 31 ++#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 ++#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 ++#define CONFIG_ECC_SRAM_REQ_MASK 0x00200000 ++#define CONFIG_ECC_SRAM_REQ_SHIFT 21 ++#define CONFIG_DMA_REQ_MASK 0x00100000 ++#define CONFIG_DMA_REQ_SHIFT 20 ++#define CONFIG_ECC_MODE_MASK 0x000E0000 ++#define CONFIG_ECC_MODE_SHIFT 17 ++#define CONFIG_FAST_FLASH_MASK 0x00010000 ++#define CONFIG_FAST_FLASH_SHIFT 16 ++#define CONFIG_ID_COUNT_MASK 0x0000E000 ++#define CONFIG_ID_COUNT_SHIFT 13 ++#define CONFIG_CMD_TIMEOUT_MASK 0x00001F00 ++#define CONFIG_CMD_TIMEOUT_SHIFT 8 ++#define CONFIG_16BIT_MASK 0x00000080 ++#define CONFIG_16BIT_SHIFT 7 ++#define CONFIG_BOOT_MODE_MASK 0x00000040 ++#define CONFIG_BOOT_MODE_SHIFT 6 ++#define CONFIG_ADDR_AUTO_INCR_MASK 0x00000020 ++#define CONFIG_ADDR_AUTO_INCR_SHIFT 5 ++#define CONFIG_BUFNO_AUTO_INCR_MASK 0x00000010 ++#define CONFIG_BUFNO_AUTO_INCR_SHIFT 4 ++#define CONFIG_PAGE_CNT_MASK 0x0000000F ++#define CONFIG_PAGE_CNT_SHIFT 0 ++ ++/* NFC_IRQ_STATUS Field */ ++#define MASK 0xEFFC003F ++#define SHIFT 0 ++#define WERR_IRQ_MASK 0x80000000 ++#define WERR_IRQ_SHIFT 31 ++#define CMD_DONE_IRQ_MASK 0x40000000 ++#define CMD_DONE_IRQ_SHIFT 30 ++#define IDLE_IRQ_MASK 0x20000000 ++#define IDLE_IRQ_SHIFT 29 ++#define WERR_STATUS_MASK 0x08000000 ++#define WERR_STATUS_SHIFT 27 ++#define FLASH_CMD_BUSY_MASK 0x04000000 ++#define FLASH_CMD_BUSY_SHIFT 26 ++#define RESIDUE_BUSY_MASK 0x02000000 ++#define RESIDUE_BUSY_SHIFT 25 ++#define ECC_BUSY_MASK 0x01000000 ++#define ECC_BUSY_SHIFT 24 ++#define DMA_BUSY_MASK 0x00800000 ++#define DMA_BUSY_SHIFT 23 ++#define WERR_EN_MASK 0x00400000 ++#define WERR_EN_SHIFT 22 ++#define CMD_DONE_EN_MASK 0x00200000 ++#define CMD_DONE_EN_SHIFT 21 ++#define IDLE_EN_MASK 0x00100000 ++#define IDLE_EN_SHIFT 20 ++#define WERR_CLEAR_MASK 0x00080000 ++#define WERR_CLEAR_SHIFT 19 ++#define CMD_DONE_CLEAR_MASK 0x00040000 ++#define CMD_DONE_CLEAR_SHIFT 18 ++#define IDLE_CLEAR_MASK 0x00020000 ++#define IDLE_CLEAR_SHIFT 17 ++#define RESIDUE_BUFF_NO_MASK 0x00000030 ++#define RESIDUE_BUFF_NO_SHIFT 4 ++#define ECC_BUFF_NO_MASK 0x000000C0 ++#define ECC_BUFF_NO_SHIFT 2 ++#define DMA_BUFF_NO_MASK 0x00000003 ++ ++#endif /* MPC5125_NFC_H */ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -474,6 +474,13 @@ config MTD_NAND_MPC5121_NFC + This enables the driver for the NAND flash controller on the + MPC5121 SoC. + ++config MTD_NAND_FSL_NFC ++ tristate "Support for NAND on Freescale ColdFire NFC" ++ depends on MTD_NAND && M5441X ++ help ++ Enables support for NAND Flash chips wired onto Freescale PowerPC ++ processor localbus with User-Programmable Machine support. ++ + config MTD_NAND_MXC + tristate "MXC NAND support" + depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51 +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -38,6 +38,7 @@ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o + obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o ++obj-$(CONFIG_MTD_NAND_FSL_NFC) += fsl_nfc.o + obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o + obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o + obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o +--- /dev/null ++++ b/drivers/mtd/nand/fsl_nfc.c +@@ -0,0 +1,995 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: Shaohui Xie <b21989@freescale.com> ++ * Jason Jin <Jason.jin@freescale.com> ++ * ++ * Description: ++ * MPC5125 Nand driver. ++ * Jason ported to M54418TWR. ++ * ++ * Based on original driver mpc5121_nfc.c. ++ * ++ * This is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/clk.h> ++#include <linux/delay.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/io.h> ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/nand.h> ++#include <linux/mtd/partitions.h> ++#include <linux/platform_device.h> ++#include <linux/slab.h> ++#include <asm/fsl_nfc.h> ++#include <asm/mcfsim.h> ++ ++#define DRV_NAME "fsl_nfc" ++#define DRV_VERSION "0.5" ++ ++/* Timeouts */ ++#define NFC_RESET_TIMEOUT 1000 /* 1 ms */ ++#define NFC_TIMEOUT (HZ) ++ ++ ++#define ECC_SRAM_ADDR (0x840 >> 3) ++#define ECC_STATUS_MASK 0x80 ++#define ECC_ERR_COUNT 0x3F ++ ++#define MIN(x, y) ((x < y) ? x : y) ++ ++#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC ++static int hardware_ecc; ++#else ++static int hardware_ecc = 1; ++#endif ++ ++ ++struct fsl_nfc_prv { ++ struct mtd_info mtd; ++ struct nand_chip chip; ++ int irq; ++ void __iomem *regs; ++ struct clk *clk; ++ wait_queue_head_t irq_waitq; ++ uint column; ++ int spareonly; ++ int page; ++}; ++ ++static int get_status; ++static int get_id; ++ ++static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; ++static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; ++ ++static struct nand_bbt_descr bbt_main_descr = { ++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | ++ NAND_BBT_2BIT | NAND_BBT_VERSION, ++ .offs = 11, ++ .len = 4, ++ .veroffs = 15, ++ .maxblocks = 4, ++ .pattern = bbt_pattern, ++}; ++ ++static struct nand_bbt_descr bbt_mirror_descr = { ++ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | ++ NAND_BBT_2BIT | NAND_BBT_VERSION, ++ .offs = 11, ++ .len = 4, ++ .veroffs = 15, ++ .maxblocks = 4, ++ .pattern = mirror_pattern, ++}; ++ ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *fsl_nfc_pprobes[] = { "cmdlinepart", NULL }; ++#endif ++#if 0 ++static struct nand_ecclayout nand_hw_eccoob_512 = { ++ .eccbytes = 8, ++ .eccpos = { ++ 8, 9, 10, 11, 12, 13, 14, 15, ++ }, ++ .oobfree = { ++ {0, 5} /* byte 5 is factory bad block marker */ ++ }, ++}; ++#endif ++ ++static struct nand_ecclayout fsl_nfc_ecc45 = { ++ .eccbytes = 45, ++ .eccpos = {19, 20, 21, 22, 23, ++ 24, 25, 26, 27, 28, 29, 30, 31, ++ 32, 33, 34, 35, 36, 37, 38, 39, ++ 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55, ++ 56, 57, 58, 59, 60, 61, 62, 63}, ++ .oobfree = { ++ {.offset = 8, ++ .length = 11} } ++}; ++ ++ ++#if 0 ++static struct nand_ecclayout nand_hw_eccoob_2k = { ++ .eccbytes = 32, ++ .eccpos = { ++ /* 8 bytes of ecc for each 512 bytes of data */ ++ 8, 9, 10, 11, 12, 13, 14, 15, ++ 24, 25, 26, 27, 28, 29, 30, 31, ++ 40, 41, 42, 43, 44, 45, 46, 47, ++ 56, 57, 58, 59, 60, 61, 62, 63, ++ }, ++ .oobfree = { ++ {2, 5}, /* bytes 0 and 1 are factory bad block markers */ ++ {16, 7}, ++ {32, 7}, ++ {48, 7}, ++ }, ++}; ++ ++ ++/* ecc struct for nand 5125 */ ++static struct nand_ecclayout nand5125_hw_eccoob_2k = { ++ .eccbytes = 60, ++ .eccpos = { ++ /* 60 bytes of ecc for one page bytes of data */ ++ 4, 5, ++ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ++ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, ++ 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, ++ 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, ++ 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, ++ 56, 57, 58, 59, 60, 61, 62, 63, ++ }, ++ .oobfree = { ++ {2, 2}, /* bytes 0 and 1 are factory bad block markers */ ++ }, ++}; ++#endif ++ ++static inline u32 nfc_read(struct mtd_info *mtd, uint reg) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ return in_be32(prv->regs + reg); ++} ++ ++/* Write NFC register */ ++static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ out_be32(prv->regs + reg, val); ++} ++ ++/* Set bits in NFC register */ ++static inline void nfc_set(struct mtd_info *mtd, uint reg, u32 bits) ++{ ++ nfc_write(mtd, reg, nfc_read(mtd, reg) | bits); ++} ++ ++/* Clear bits in NFC register */ ++static inline void nfc_clear(struct mtd_info *mtd, uint reg, u32 bits) ++{ ++ nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits); ++} ++ ++static inline void ++nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ out_be32(prv->regs + reg, ++ (in_be32(prv->regs + reg) & (~mask)) ++ | val << shift); ++} ++ ++static inline int ++nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ return in_be32(prv->regs + reg) & field_mask; ++} ++ ++static inline u8 nfc_check_status(struct mtd_info *mtd) ++{ ++ u8 fls_status = 0; ++ fls_status = nfc_get_field(mtd, NFC_FLASH_STATUS2, STATUS_BYTE1_MASK); ++ return fls_status; ++} ++ ++/* clear cmd_done and cmd_idle falg for the coming command */ ++static void fsl_nfc_clear(struct mtd_info *mtd) ++{ ++ nfc_write(mtd, NFC_IRQ_STATUS, 1 << CMD_DONE_CLEAR_SHIFT); ++ nfc_write(mtd, NFC_IRQ_STATUS, 1 << IDLE_CLEAR_SHIFT); ++} ++ ++/* Wait for operation complete */ ++static void fsl_nfc_done(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ int rv; ++ ++ nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_MASK); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK, ++ START_SHIFT, 1); ++ ++ if (!nfc_get_field(mtd, NFC_IRQ_STATUS, IDLE_IRQ_MASK)) { ++ rv = wait_event_timeout(prv->irq_waitq, ++ nfc_get_field(mtd, NFC_IRQ_STATUS, ++ IDLE_IRQ_MASK), NFC_TIMEOUT); ++ if (!rv) ++ printk(KERN_DEBUG DRV_NAME ++ ": Timeout while waiting for BUSY.\n"); ++ } ++ fsl_nfc_clear(mtd); ++} ++ ++static inline u8 fsl_nfc_get_id(struct mtd_info *mtd, int col) ++{ ++ u32 flash_id1 = 0; ++ u8 *pid; ++ ++ flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1); ++ pid = (u8 *)&flash_id1; ++ ++ return *(pid + col); ++} ++ ++static inline u8 fsl_nfc_get_status(struct mtd_info *mtd) ++{ ++ u32 flash_status = 0; ++ u8 *pstatus; ++ ++ flash_status = nfc_read(mtd, NFC_FLASH_STATUS2); ++ pstatus = (u8 *)&flash_status; ++ ++ return *(pstatus + 3); ++} ++ ++/* Invoke command cycle */ ++static inline void ++fsl_nfc_send_cmd(struct mtd_info *mtd, u32 cmd_byte1, ++ u32 cmd_byte2, u32 cmd_code) ++{ ++ fsl_nfc_clear(mtd); ++ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK, ++ CMD_BYTE1_SHIFT, cmd_byte1); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD1, CMD_BYTE2_MASK, ++ CMD_BYTE2_SHIFT, cmd_byte2); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK, ++ BUFNO_SHIFT, 0); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK, ++ CMD_CODE_SHIFT, cmd_code); ++ ++ if (cmd_code == RANDOM_OUT_CMD_CODE) ++ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK, ++ BUFNO_SHIFT, 1); ++} ++ ++/* Receive ID and status from NAND flash */ ++static inline void ++fsl_nfc_send_one_byte(struct mtd_info *mtd, u32 cmd_byte1, u32 cmd_code) ++{ ++ fsl_nfc_clear(mtd); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK, ++ CMD_BYTE1_SHIFT, cmd_byte1); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK, ++ BUFNO_SHIFT, 0); ++ ++ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK, ++ CMD_CODE_SHIFT, cmd_code); ++} ++ ++/* NFC interrupt handler */ ++static irqreturn_t ++fsl_nfc_irq(int irq, void *data) ++{ ++ struct mtd_info *mtd = data; ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ nfc_clear(mtd, NFC_IRQ_STATUS, IDLE_EN_MASK); ++ wake_up(&prv->irq_waitq); ++ ++ return IRQ_HANDLED; ++} ++ ++/* Do address cycle(s) */ ++static void ++fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) ++{ ++ ++ if (column != -1) { ++ nfc_set_field(mtd, NFC_COL_ADDR, ++ COL_ADDR_MASK, ++ COL_ADDR_SHIFT, column); ++ } ++ ++ if (page != -1) { ++ nfc_set_field(mtd, NFC_ROW_ADDR, ++ ROW_ADDR_MASK, ++ ROW_ADDR_SHIFT, page); ++ } ++ ++ /* DMA Disable */ ++ nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK); ++ ++ /* PAGE_CNT = 1 */ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, ++ CONFIG_PAGE_CNT_SHIFT, 0x1); ++} ++ ++/* Control chips select signal on m54418twr board */ ++static void ++m54418twr_select_chip(struct mtd_info *mtd, int chip) ++{ ++ if (chip < 0) { ++ MCF_GPIO_PAR_FBCTL &= (MCF_GPIO_PAR_FBCTL_ALE_MASK & ++ MCF_GPIO_PAR_FBCTL_TA_MASK); ++ MCF_GPIO_PAR_FBCTL |= MCF_GPIO_PAR_FBCTL_ALE_FB_TS | ++ MCF_GPIO_PAR_FBCTL_TA_TA; ++ ++ MCF_GPIO_PAR_BE = ++ MCF_GPIO_PAR_BE_BE3_BE3 | MCF_GPIO_PAR_BE_BE2_BE2 | ++ MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0; ++ ++ MCF_GPIO_PAR_CS &= ~MCF_GPIO_PAR_CS_CS1_NFC_CE; ++ MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS0_CS0; ++ return; ++ } ++ ++ MCF_GPIO_PAR_FBCTL &= (MCF_GPIO_PAR_FBCTL_ALE_MASK & ++ MCF_GPIO_PAR_FBCTL_TA_MASK); ++ MCF_GPIO_PAR_FBCTL |= MCF_GPIO_PAR_FBCTL_ALE_FB_ALE | ++ MCF_GPIO_PAR_FBCTL_TA_NFC_RB; ++ MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_BE3_FB_A1 | ++ MCF_GPIO_PAR_BE_BE2_FB_A0 | ++ MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0; ++ ++ MCF_GPIO_PAR_CS &= (MCF_GPIO_PAR_BE_BE3_MASK & ++ MCF_GPIO_PAR_BE_BE2_MASK); ++ MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS1_NFC_CE; ++ return; ++} ++ ++/* Read NAND Ready/Busy signal */ ++static int ++fsl_nfc_dev_ready(struct mtd_info *mtd) ++{ ++ /* ++ * NFC handles ready/busy signal internally. Therefore, this function ++ * always returns status as ready. ++ */ ++ return 1; ++} ++ ++/* Write command to NAND flash */ ++static void ++fsl_nfc_command(struct mtd_info *mtd, unsigned command, ++ int column, int page) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ prv->column = (column >= 0) ? column : 0; ++ prv->spareonly = 0; ++ get_id = 0; ++ get_status = 0; ++ ++ if (page != -1) ++ prv->page = page; ++ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); ++ ++ if (!(page%0x40)) { ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_BYPASS); ++ } ++ ++ switch (command) { ++ case NAND_CMD_PAGEPROG: ++ if (!(prv->page%0x40)) ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_BYPASS); ++ ++ fsl_nfc_send_cmd(mtd, ++ PROGRAM_PAGE_CMD_BYTE1, ++ PROGRAM_PAGE_CMD_BYTE2, ++ PROGRAM_PAGE_CMD_CODE); ++ break; ++ /* ++ * NFC does not support sub-page reads and writes, ++ * so emulate them using full page transfers. ++ */ ++ case NAND_CMD_READ0: ++ column = 0; ++ goto read0; ++ break; ++ ++ case NAND_CMD_READ1: ++ prv->column += 256; ++ command = NAND_CMD_READ0; ++ column = 0; ++ goto read0; ++ break; ++ ++ case NAND_CMD_READOOB: ++ prv->spareonly = 1; ++ command = NAND_CMD_READ0; ++ column = 0; ++read0: ++ fsl_nfc_send_cmd(mtd, ++ PAGE_READ_CMD_BYTE1, ++ PAGE_READ_CMD_BYTE2, ++ READ_PAGE_CMD_CODE); ++ break; ++ ++ case NAND_CMD_SEQIN: ++ fsl_nfc_command(mtd, NAND_CMD_READ0, column, page); ++ column = 0; ++ break; ++ ++ case NAND_CMD_ERASE1: ++ fsl_nfc_send_cmd(mtd, ++ ERASE_CMD_BYTE1, ++ ERASE_CMD_BYTE2, ++ ERASE_CMD_CODE); ++ break; ++ case NAND_CMD_ERASE2: ++ return; ++ case NAND_CMD_READID: ++ get_id = 1; ++ fsl_nfc_send_one_byte(mtd, command, READ_ID_CMD_CODE); ++ break; ++ case NAND_CMD_STATUS: ++ get_status = 1; ++ fsl_nfc_send_one_byte(mtd, command, STATUS_READ_CMD_CODE); ++ break; ++ case NAND_CMD_RNDOUT: ++ fsl_nfc_send_cmd(mtd, ++ RANDOM_OUT_CMD_BYTE1, ++ RANDOM_OUT_CMD_BYTE2, ++ RANDOM_OUT_CMD_CODE); ++ break; ++ case NAND_CMD_RESET: ++ fsl_nfc_send_one_byte(mtd, command, RESET_CMD_CODE); ++ break; ++ default: ++ return; ++ } ++ ++ fsl_nfc_addr_cycle(mtd, column, page); ++ ++ fsl_nfc_done(mtd); ++} ++ ++/* Copy data from/to NFC spare buffers. */ ++static void ++fsl_nfc_copy_spare(struct mtd_info *mtd, uint offset, ++ u8 *buffer, uint size, int wr) ++{ ++ struct nand_chip *nand = mtd->priv; ++ struct fsl_nfc_prv *prv = nand->priv; ++ uint o, s, sbsize, blksize; ++ ++ /* ++ * NAND spare area is available through NFC spare buffers. ++ * The NFC divides spare area into (page_size / 512) chunks. ++ * Each chunk is placed into separate spare memory area, using ++ * first (spare_size / num_of_chunks) bytes of the buffer. ++ * ++ * For NAND device in which the spare area is not divided fully ++ * by the number of chunks, number of used bytes in each spare ++ * buffer is rounded down to the nearest even number of bytes, ++ * and all remaining bytes are added to the last used spare area. ++ * ++ * For more information read section 26.6.10 of MPC5121e ++ * Microcontroller Reference Manual, Rev. 3. ++ */ ++ ++ /* Calculate number of valid bytes in each spare buffer */ ++/* sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;*/ ++ sbsize = (mtd->oobsize / (mtd->writesize / 2048)) & ~1; ++ ++ ++ while (size) { ++ /* Calculate spare buffer number */ ++ s = offset / sbsize; ++ if (s > NFC_SPARE_BUFFERS - 1) ++ s = NFC_SPARE_BUFFERS - 1; ++ ++ /* ++ * Calculate offset to requested data block in selected spare ++ * buffer and its size. ++ */ ++ o = offset - (s * sbsize); ++ blksize = min(sbsize - o, size); ++ ++ if (wr) ++ memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o, ++ buffer, blksize); ++ else { ++ memcpy_fromio(buffer, ++ prv->regs + NFC_SPARE_AREA(s) + o, blksize); ++ } ++ ++ buffer += blksize; ++ offset += blksize; ++ size -= blksize; ++ }; ++} ++ ++/* Copy data from/to NFC main and spare buffers */ ++static void ++fsl_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len, int wr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ uint c = prv->column; ++ uint l; ++ ++ /* Handle spare area access */ ++ if (prv->spareonly || c >= mtd->writesize) { ++ /* Calculate offset from beginning of spare area */ ++ if (c >= mtd->writesize) ++ c -= mtd->writesize; ++ ++ prv->column += len; ++ fsl_nfc_copy_spare(mtd, c, buf, len, wr); ++ return; ++ } ++ ++ /* ++ * Handle main area access - limit copy length to prevent ++ * crossing main/spare boundary. ++ */ ++ l = min((uint)len, mtd->writesize - c); ++ prv->column += l; ++ ++ if (wr) ++ memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l); ++ else { ++ if (get_status) { ++ get_status = 0; ++ *buf = fsl_nfc_get_status(mtd); ++ } else if (l == 1 && c <= 3 && get_id) { ++ *buf = fsl_nfc_get_id(mtd, c); ++ } else ++ memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l); ++ } ++ ++ /* Handle crossing main/spare boundary */ ++ if (l != len) { ++ buf += l; ++ len -= l; ++ fsl_nfc_buf_copy(mtd, buf, len, wr); ++ } ++} ++ ++/* Read data from NFC buffers */ ++static void ++fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ fsl_nfc_buf_copy(mtd, buf, len, 0); ++} ++ ++/* Write data to NFC buffers */ ++static void ++fsl_nfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ fsl_nfc_buf_copy(mtd, (u_char *)buf, len, 1); ++} ++ ++/* Compare buffer with NAND flash */ ++static int ++fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ u_char tmp[256]; ++ uint bsize; ++ ++ while (len) { ++ bsize = min(len, 256); ++ fsl_nfc_read_buf(mtd, tmp, bsize); ++ ++ if (memcmp(buf, tmp, bsize)) ++ return 1; ++ ++ buf += bsize; ++ len -= bsize; ++ } ++ ++ return 0; ++} ++ ++/* Read byte from NFC buffers */ ++static u8 ++fsl_nfc_read_byte(struct mtd_info *mtd) ++{ ++ u8 tmp; ++ fsl_nfc_read_buf(mtd, &tmp, sizeof(tmp)); ++ return tmp; ++} ++ ++/* Read word from NFC buffers */ ++static u16 ++fsl_nfc_read_word(struct mtd_info *mtd) ++{ ++ u16 tmp; ++ fsl_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); ++ return tmp; ++} ++ ++#if 0 ++static void fsl_nfc_check_ecc_status(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ u8 ecc_status, ecc_count; ++ ++ ecc_status = *(u8 *)(prv->regs + ECC_SRAM_ADDR * 8 + 7); ++ ecc_count = ecc_status & ECC_ERR_COUNT; ++ if (ecc_status & ECC_STATUS_MASK) { ++ /*mtd->ecc_stats.failed++;*/ ++ printk("ECC failed to correct all errors!\n"); ++ } else if (ecc_count) { ++ /*mtd->ecc_stats.corrected += ecc_count;*/ ++ printk(KERN_INFO"ECC corrected %d errors\n", ecc_count); ++ } ++ ++} ++#endif ++ ++static void ++copy_from_to_spare(struct mtd_info *mtd, void *pbuf, int len, int wr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ int i, copy_count, copy_size; ++ ++/* copy_count = mtd->writesize / 512;*/ ++ copy_count = mtd->writesize / 2048; ++ /* ++ * Each spare area has 16 bytes for 512, 2K and normal 4K nand. ++ * For 4K nand with large 218 byte spare size, the size is 26 bytes for ++ * the first 7 buffers and 36 for the last. ++ */ ++/* copy_size = mtd->oobsize == 218 ? 26 : 16;*/ ++ copy_size = 64; ++ ++ /* ++ * Each spare area has 16 bytes for 512, 2K and normal 4K nand. ++ * For 4K nand with large 218 byte spare size, the size is 26 ++ * bytes for the first 7 buffers and 36 for the last. ++ */ ++ for (i = 0; i < copy_count - 1 && len > 0; i++) { ++ if (wr) ++ memcpy_toio(prv->regs + NFC_SPARE_AREA(i), ++ pbuf, MIN(len, copy_size)); ++ else ++ memcpy_fromio(pbuf, prv->regs + NFC_SPARE_AREA(i), ++ MIN(len, copy_size)); ++ pbuf += copy_size; ++ len -= copy_size; ++ } ++ if (len > 0) { ++ if (wr) ++ memcpy_toio(prv->regs + NFC_SPARE_AREA(i), ++ pbuf, len); ++ else ++ memcpy_fromio(pbuf, ++ prv->regs + NFC_SPARE_AREA(i), len); ++ } ++} ++ ++ ++static int fsl_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page, int sndcmd) ++{ ++ fsl_nfc_command(mtd, NAND_CMD_READ0, 0, page); ++ ++ copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 0); ++ return 0; ++} ++ ++static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ fsl_nfc_command(mtd, NAND_CMD_READ0, 0, page); ++ /* copy the oob data */ ++ copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 1); ++ fsl_nfc_command(mtd, NAND_CMD_PAGEPROG, 0, page); ++ return 0; ++} ++ ++static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int page) ++{ ++ struct fsl_nfc_prv *prv = chip->priv; ++ /*fsl_nfc_check_ecc_status(mtd);*/ ++ ++ memcpy_fromio((void *)buf, prv->regs + NFC_MAIN_AREA(0), ++ mtd->writesize); ++ copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 0); ++ return 0; ++} ++ ++static void fsl_nfc_write_page(struct mtd_info *mtd, ++ struct nand_chip *chip, const uint8_t *buf) ++{ ++ struct fsl_nfc_prv *prv = chip->priv; ++ memcpy_toio(prv->regs + NFC_MAIN_AREA(0), buf, mtd->writesize); ++ copy_from_to_spare(mtd, chip->oob_poi, mtd->oobsize, 1); ++} ++ ++static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode) ++{ ++ return; ++} ++ ++/* Free driver resources */ ++static void ++fsl_nfc_free(struct platform_device *dev, struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ kfree(prv); ++} ++ ++static int __devinit ++fsl_nfc_probe(struct platform_device *pdev) ++{ ++ struct fsl_nfc_prv *prv; ++ struct resource *res; ++ struct mtd_info *mtd; ++#ifdef CONFIG_MTD_PARTITIONS ++ struct mtd_partition *parts; ++#endif ++ struct nand_chip *chip; ++ unsigned long regs_paddr, regs_size; ++ int retval = 0; ++ ++ prv = kzalloc(sizeof(*prv), GFP_KERNEL); ++ if (!prv) { ++ printk(KERN_ERR DRV_NAME ": Memory exhausted!\n"); ++ return -ENOMEM; ++ } ++ mtd = &prv->mtd; ++ chip = &prv->chip; ++ ++ mtd->priv = chip; ++ chip->priv = prv; ++ ++ prv->irq = platform_get_irq(pdev, 0); ++ if (prv->irq <= 0) { ++ printk(KERN_ERR DRV_NAME ": Error mapping IRQ!\n"); ++ return -EINVAL; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ printk(KERN_ERR "%s platform_get_resource MEM failed %x\n", ++ __func__, (unsigned int)res); ++ retval = -ENOMEM; ++ goto error; ++ } ++ regs_paddr = res->start; ++ regs_size = res->end - res->start + 1; ++ ++#if 0 ++ if (!request_mem_region(regs_paddr, regs_size, DRV_NAME)) { ++ printk(KERN_ERR DRV_NAME ": Error requesting memory region!\n"); ++ return -EBUSY; ++ } ++ ++ prv->regs = ioremap(regs_paddr, regs_size); ++#endif ++ prv->regs = (void __iomem *)regs_paddr; ++ if (!prv->regs) { ++ printk(KERN_ERR DRV_NAME ": Error mapping memory region!\n"); ++ return -ENOMEM; ++ } ++ ++ mtd->name = "NAND"; ++ mtd->writesize = 2048; ++ mtd->oobsize = 64; ++ ++ chip->dev_ready = fsl_nfc_dev_ready; ++ chip->cmdfunc = fsl_nfc_command; ++ chip->read_byte = fsl_nfc_read_byte; ++ chip->read_word = fsl_nfc_read_word; ++ chip->read_buf = fsl_nfc_read_buf; ++ chip->write_buf = fsl_nfc_write_buf; ++ chip->verify_buf = fsl_nfc_verify_buf; ++ chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT | ++ NAND_BUSWIDTH_16 | NAND_CACHEPRG; ++ ++ chip->select_chip = m54418twr_select_chip; ++ ++ if (hardware_ecc) { ++ chip->ecc.read_page = fsl_nfc_read_page; ++ chip->ecc.write_page = fsl_nfc_write_page; ++ chip->ecc.read_oob = fsl_nfc_read_oob; ++ chip->ecc.write_oob = fsl_nfc_write_oob; ++ chip->ecc.layout = &fsl_nfc_ecc45; ++ ++ /* propagate ecc.layout to mtd_info */ ++ mtd->ecclayout = chip->ecc.layout; ++ chip->ecc.calculate = NULL; ++ chip->ecc.hwctl = fsl_nfc_enable_hwecc; ++ chip->ecc.correct = NULL; ++ chip->ecc.mode = NAND_ECC_HW; ++ /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */ ++ chip->ecc.steps = 1; ++ chip->ecc.bytes = 45; ++ chip->ecc.size = 0x800; ++ ++ /* set ECC mode = ECC_45_BYTE */ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); ++ /* set ECC_STATUS write position */ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_SRAM_ADDR_MASK, ++ CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR); ++ /* enable ECC_STATUS results write */ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_SRAM_REQ_MASK, ++ CONFIG_ECC_SRAM_REQ_SHIFT, 1); ++ } else { ++ chip->ecc.mode = NAND_ECC_SOFT; ++ /* set ECC BY_PASS */ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_BYPASS); ++ } ++ chip->bbt_td = &bbt_main_descr; ++ chip->bbt_md = &bbt_mirror_descr; ++ bbt_main_descr.pattern = bbt_pattern; ++ bbt_mirror_descr.pattern = mirror_pattern; ++ ++ init_waitqueue_head(&prv->irq_waitq); ++ retval = request_irq(prv->irq, fsl_nfc_irq, IRQF_DISABLED, ++ DRV_NAME, mtd); ++ if (retval) { ++ printk(KERN_ERR DRV_NAME ": Error requesting IRQ!\n"); ++ goto error; ++ } ++ ++ /* SET SECTOR SIZE */ ++ nfc_write(mtd, NFC_SECTOR_SIZE, PAGE_2K | PAGE_64); ++ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ADDR_AUTO_INCR_MASK, ++ CONFIG_ADDR_AUTO_INCR_SHIFT, 0); ++ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_BUFNO_AUTO_INCR_MASK, ++ CONFIG_BUFNO_AUTO_INCR_SHIFT, 0); ++ /* SET FAST_FLASH = 1 */ ++#if 0 ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_FAST_FLASH_MASK, ++ CONFIG_FAST_FLASH_SHIFT, 1); ++#endif ++ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_16BIT_MASK, ++ CONFIG_16BIT_SHIFT, 1); ++ ++ ++ /* Detect NAND chips */ ++ if (nand_scan(mtd, 1)) { ++ printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n"); ++ free_irq(prv->irq, mtd); ++ retval = -ENXIO; ++ goto error; ++ } ++ ++ platform_set_drvdata(pdev, mtd); ++ ++ /* Register device in MTD */ ++#ifdef CONFIG_MTD_PARTITIONS ++ retval = parse_mtd_partitions(mtd, fsl_nfc_pprobes, &parts, 0); ++ if (retval < 0) { ++ printk(KERN_ERR DRV_NAME ": Error parsing MTD partitions!\n"); ++ free_irq(prv->irq, mtd); ++ retval = -EINVAL; ++ goto error; ++ } ++ ++ printk(KERN_DEBUG "parse partition: partnr = %d\n", retval); ++ ++ if (retval > 0) ++ retval = add_mtd_partitions(mtd, parts, retval); ++ else ++#endif ++ retval = add_mtd_device(mtd); ++ ++ if (retval) { ++ printk(KERN_ERR DRV_NAME ": Error adding MTD device!\n"); ++ free_irq(prv->irq, mtd); ++ goto error; ++ } ++ ++ return 0; ++error: ++ fsl_nfc_free(pdev, mtd); ++ return retval; ++} ++ ++static int __exit ++fsl_nfc_remove(struct platform_device *pdev) ++{ ++ struct mtd_info *mtd = platform_get_drvdata(pdev); ++ struct nand_chip *chip = mtd->priv; ++ struct fsl_nfc_prv *prv = chip->priv; ++ ++ nand_release(mtd); ++ free_irq(prv->irq, mtd); ++ fsl_nfc_free(pdev, mtd); ++ ++ return 0; ++} ++ ++static struct platform_driver fsl_nfc_driver = { ++ .probe = fsl_nfc_probe, ++ .remove = __exit_p(fsl_nfc_remove), ++ .suspend = NULL, ++ .resume = NULL, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init fsl_nfc_init(void) ++{ ++ pr_info("FSL NFC MTD nand Driver %s\n", DRV_VERSION); ++ if (platform_driver_register(&fsl_nfc_driver) != 0) { ++ printk(KERN_ERR DRV_NAME ": Driver register failed!\n"); ++ return -ENODEV; ++ } ++ return 0; ++} ++ ++static void __exit fsl_nfc_cleanup(void) ++{ ++ platform_driver_unregister(&fsl_nfc_driver); ++} ++ ++module_init(fsl_nfc_init); ++module_exit(fsl_nfc_cleanup); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("FSL NFC NAND MTD driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); diff --git a/target/linux/coldfire/patches/017-Add-cpu-dma-sync-function-for-coldfire-platform.patch b/target/linux/coldfire/patches/017-Add-cpu-dma-sync-function-for-coldfire-platform.patch new file mode 100644 index 000000000..6151c97b9 --- /dev/null +++ b/target/linux/coldfire/patches/017-Add-cpu-dma-sync-function-for-coldfire-platform.patch @@ -0,0 +1,68 @@ +From 04491155db32bc1a9c0b367a7cac0f4a9ea9c4d2 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:43 +0800 +Subject: [PATCH 17/52] Add cpu dma sync function for coldfire platform + +This patch add dma_sync_sg_for_cpu() and dma_sync_single_for_cpu() +for coldfire platform. The previous empty function do not flush the +cache for the ram used for DMA. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/dma-mapping.h | 10 ++++++++-- + 1 files changed, 8 insertions(+), 2 deletions(-) + +--- a/arch/m68k/include/asm/dma-mapping.h ++++ b/arch/m68k/include/asm/dma-mapping.h +@@ -21,6 +21,9 @@ extern void *dma_alloc_coherent(struct d + extern void dma_free_coherent(struct device *, size_t, + void *, dma_addr_t); + ++extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t, ++ enum dma_data_direction); ++ + static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t flag) + { +@@ -42,6 +45,7 @@ extern dma_addr_t dma_map_single(struct + static inline void dma_unmap_single(struct device *dev, dma_addr_t addr, + size_t size, enum dma_data_direction dir) + { ++ dma_sync_single_for_device(dev, addr, size, dir); + } + + extern dma_addr_t dma_map_page(struct device *, struct page *, +@@ -50,6 +54,7 @@ extern dma_addr_t dma_map_page(struct de + static inline void dma_unmap_page(struct device *dev, dma_addr_t address, + size_t size, enum dma_data_direction dir) + { ++ dma_sync_single_for_device(dev, address, size, dir); + } + + extern int dma_map_sg(struct device *, struct scatterlist *, int, +@@ -57,10 +62,9 @@ extern int dma_map_sg(struct device *, s + static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction dir) + { ++ dma_map_sg(dev, sg, nhwentries, dir); + } + +-extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t, +- enum dma_data_direction); + extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int, + enum dma_data_direction); + +@@ -75,11 +79,13 @@ static inline void dma_sync_single_range + static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, + size_t size, enum dma_data_direction dir) + { ++ dma_sync_single_for_device(dev, handle, size, dir); + } + + static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) + { ++ dma_sync_sg_for_device(dev, sg, nents, dir); + } + + static inline void dma_sync_single_range_for_cpu(struct device *dev, diff --git a/target/linux/coldfire/patches/018-Add-SSD1289-TFT-LCD-framebuffer-driver-on-TWR-MCF544.patch b/target/linux/coldfire/patches/018-Add-SSD1289-TFT-LCD-framebuffer-driver-on-TWR-MCF544.patch new file mode 100644 index 000000000..ec203461e --- /dev/null +++ b/target/linux/coldfire/patches/018-Add-SSD1289-TFT-LCD-framebuffer-driver-on-TWR-MCF544.patch @@ -0,0 +1,973 @@ +From c1de95e3a608c48b5576e32181480930d9106ac4 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:44 +0800 +Subject: [PATCH 18/52] Add SSD1289 TFT LCD framebuffer driver on TWR-MCF5441X + +Add SSD1289 TFT LCD framebuffer driver on TWR-MCF5441X. Flexbus and spi +interfaces are both supported. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5441x/config.c | 1 + + arch/m68k/coldfire/m5441x/devices.c | 1 + + arch/m68k/include/asm/fsl-ssd1289-fb.h | 93 ++++ + drivers/video/Kconfig | 24 + + drivers/video/Makefile | 1 + + drivers/video/fsl-ssd1289-fb.c | 791 ++++++++++++++++++++++++++++++++ + 6 files changed, 911 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/include/asm/fsl-ssd1289-fb.h + create mode 100644 drivers/video/fsl-ssd1289-fb.c + +--- a/arch/m68k/coldfire/m5441x/config.c ++++ b/arch/m68k/coldfire/m5441x/config.c +@@ -45,6 +45,7 @@ + #include <asm/mcf5441x_fbcs.h> + #include <asm/mcf5441x_dtim.h> + #include <asm/mcf5441x_xbs.h> ++#include <asm/fsl-ssd1289-fb.h> + + extern int get_irq_list(struct seq_file *p, void *v); + extern char _text, _end; +--- a/arch/m68k/coldfire/m5441x/devices.c ++++ b/arch/m68k/coldfire/m5441x/devices.c +@@ -33,6 +33,7 @@ + #include <asm/mcfqspi.h> + #include <asm/mcfdspi.h> + #include <asm/cf_io.h> ++#include <asm/fsl-ssd1289-fb.h> + + /* + * I2C: only support i2c0 module on m5441x platform +--- /dev/null ++++ b/arch/m68k/include/asm/fsl-ssd1289-fb.h +@@ -0,0 +1,93 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Freescale MCF54418 SSD1289 TFT LCD framebuffer driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __FSL_SSD1289_FB_H__ ++#define __FSL_SSD1289_FB_H__ ++ ++#define SSD1289_REG_OSCILLATION 0x00 ++#define SSD1289_REG_DRIVER_OUT_CTRL 0x01 ++#define SSD1289_REG_LCD_DRIVE_AC 0x02 ++#define SSD1289_REG_POWER_CTRL_1 0x03 ++#define SSD1289_REG_COMPARE_1 0x05 ++#define SSD1289_REG_COMPARE_2 0x06 ++#define SSD1289_REG_DISPLAY_CTRL 0x07 ++#define SSD1289_REG_FRAME_CYCLE 0x0b ++#define SSD1289_REG_POWER_CTRL_2 0x0c ++#define SSD1289_REG_POWER_CTRL_3 0x0d ++#define SSD1289_REG_POWER_CTRL_4 0x0e ++#define SSD1289_REG_GATE_SCAN_START 0x0f ++#define SSD1289_REG_SLEEP_MODE 0x10 ++#define SSD1289_REG_ENTRY_MODE 0x11 ++#define SSD1289_REG_OPT_SPEED_3 0x12 ++#define SSD1289_REG_H_PORCH 0x16 ++#define SSD1289_REG_V_PORCH 0x17 ++#define SSD1289_REG_POWER_CTRL_5 0x1e ++#define SSD1289_REG_GDDRAM_DATA 0x22 ++#define SSD1289_REG_WR_DATA_MASK_1 0x23 ++#define SSD1289_REG_WR_DATA_MASK_2 0x24 ++#define SSD1289_REG_FRAME_FREQUENCY 0x25 ++#define SSD1289_REG_OPT_SPEED_1 0x28 ++#define SSD1289_REG_OPT_SPEED_2 0x2f ++#define SSD1289_REG_GAMMA_CTRL_1 0x30 ++#define SSD1289_REG_GAMMA_CTRL_2 0x31 ++#define SSD1289_REG_GAMMA_CTRL_3 0x32 ++#define SSD1289_REG_GAMMA_CTRL_4 0x33 ++#define SSD1289_REG_GAMMA_CTRL_5 0x34 ++#define SSD1289_REG_GAMMA_CTRL_6 0x35 ++#define SSD1289_REG_GAMMA_CTRL_7 0x36 ++#define SSD1289_REG_GAMMA_CTRL_8 0x37 ++#define SSD1289_REG_GAMMA_CTRL_9 0x3a ++#define SSD1289_REG_GAMMA_CTRL_10 0x3b ++#define SSD1289_REG_V_SCROLL_CTRL_1 0x41 ++#define SSD1289_REG_V_SCROLL_CTRL_2 0x42 ++#define SSD1289_REG_H_RAM_ADR_POS 0x44 ++#define SSD1289_REG_V_RAM_ADR_START 0x45 ++#define SSD1289_REG_V_RAM_ADR_END 0x46 ++#define SSD1289_REG_FIRST_WIN_START 0x48 ++#define SSD1289_REG_FIRST_WIN_END 0x49 ++#define SSD1289_REG_SECND_WIN_START 0x4a ++#define SSD1289_REG_SECND_WIN_END 0x4b ++#define SSD1289_REG_GDDRAM_X_ADDR 0x4e ++#define SSD1289_REG_GDDRAM_Y_ADDR 0x4f ++ ++struct ssd1289 { ++ void __iomem *cmd; ++ void __iomem *data; ++} __packed; ++ ++struct fsl_ssd1289_fb_info { ++ struct device *dev; ++ struct ssd1289 ssd1289_reg; ++ int openflag; ++ struct spi_device *spidev; ++ ++ struct task_struct *task; ++ unsigned long pseudo_palette[16]; ++}; ++ ++/* LCD description */ ++struct fsl_ssd1289_fb_display { ++ /* Screen size */ ++ unsigned short width; ++ unsigned short height; ++ ++ /* Screen info */ ++ unsigned short xres; ++ unsigned short yres; ++ unsigned short bpp; ++}; ++ ++#define FLEXBUS_LCD_CMD_ADDRESS 0xc0000000 ++#define FLEXBUS_LCD_DATA_ADDRESS 0xc0010000 ++ ++#define SPI_LCD_BLOCK_SIZE 4096 ++#define SPI_LCD_BLOCK_HALF_SIZE 2048 ++#endif +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -1980,6 +1980,30 @@ config FB_FSL_DIU + ---help--- + Framebuffer driver for the Freescale SoC DIU + ++config FB_FSL_SSD1289 ++ tristate "SSD1289 TFT LCD (Freescale MCF54418)" ++ depends on FB && M5441X ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ select FB_SYS_FOPS ++ ---help--- ++ This is the framebuffer device driver for a Solomon Systech 240RGBx320 ++ TFT LCD SSD1289. ++ ++choice ++ prompt "SSD1289 LCD Controller Interface mode" ++ depends on FB_FSL_SSD1289 ++ ++config SSD1289_FLEXBUS_MODE ++ bool "SSD1289 LCD Controller Flexbus Interface mode" ++ ++config SSD1289_SPI_MODE ++ bool "SSD1289 LCD Controller SPI Interface mode" ++ depends on SPI_DSPI && DSPI0 ++ ++endchoice ++ + config FB_W100 + tristate "W100 frame buffer support" + depends on FB && ARCH_PXA +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_IMX) += imx + obj-$(CONFIG_FB_S3C) += s3c-fb.o + obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o + obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o ++obj-$(CONFIG_FB_FSL_SSD1289) += fsl-ssd1289-fb.o + obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o + obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ + obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ +--- /dev/null ++++ b/drivers/video/fsl-ssd1289-fb.c +@@ -0,0 +1,791 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Freescale MCF54418 SSD1289 TFT LCD framebuffer driver ++ * ++ * Author: Alison Wang <b18965@freescale.com> ++ * Jason Jin <Jason.jin@freescale.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/errno.h> ++#include <linux/string.h> ++#include <linux/mm.h> ++#include <linux/slab.h> ++#include <linux/delay.h> ++#include <linux/fb.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <linux/dma-mapping.h> ++#include <linux/clk.h> ++#include <linux/uaccess.h> ++#include <linux/timer.h> ++#include <linux/kthread.h> ++#include <linux/spi/spi.h> ++ ++#include <asm/mcf5441x_fbcs.h> ++#include <asm/mcf5441x_dspi.h> ++#include <asm/fsl-ssd1289-fb.h> ++#include <asm/mcf5441x_gpio.h> ++#include <asm/mcf5441x_ccm.h> ++#include <asm/mcf_edma.h> ++ ++#ifdef CONFIG_PM ++#include <linux/pm.h> ++#endif ++ ++#if defined(CONFIG_SSD1289_SPI_MODE) ++unsigned char spi_block_buffer[SPI_LCD_BLOCK_SIZE]; ++ ++static int ssd1289_spi_writeblock(struct fb_info *info, ++ unsigned char *daddr, int flag) ++{ ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ struct spi_device *devtmp; ++ int i; ++ ++ for (i = 0; i < SPI_LCD_BLOCK_SIZE; i++) { ++ if (i % 2 == 0) ++ spi_block_buffer[i] = 0x01; ++ else if (flag == 1) ++ spi_block_buffer[i] = *(daddr + (i >> 1)); ++ else if (flag == 0) ++ spi_block_buffer[i] = 0; ++ } ++ ++ devtmp = fbinfo->spidev; ++ spi_write(devtmp, (const unsigned char *)spi_block_buffer, ++ SPI_LCD_BLOCK_SIZE); ++ return 0; ++} ++ ++static int ssd1289_spi_write(struct fb_info *info, ++ unsigned short value, unsigned int flag) ++{ ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ struct spi_device *devtmp; ++ unsigned short tmpl; ++ unsigned short tmph; ++ ++ devtmp = fbinfo->spidev; ++ if (flag == 1) { ++ /* D/C = 1 */ ++ tmph = ((value >> 8) & 0xff) + 0x0100; ++ tmpl = (value & 0xff) + 0x0100; ++ spi_write(devtmp, (const u8 *)&tmph, sizeof(tmph)); ++ spi_write(devtmp, (const u8 *)&tmpl, sizeof(tmpl)); ++ } else { ++ /* D/C = 0 */ ++ tmpl = (value & 0xff); ++ spi_write(devtmp, (const u8 *)&tmpl, sizeof(tmpl)); ++ } ++ return 0; ++} ++#elif defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static int ssd1289_flexbus_write(struct fb_info *info, unsigned short value, ++ unsigned int flag) ++{ ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ void __iomem *cmd_addr, *data_addr; ++ ++ cmd_addr = fbinfo->ssd1289_reg.cmd; ++ data_addr = fbinfo->ssd1289_reg.data; ++ ++ if (flag == 0) ++ out_be16(cmd_addr, value); ++ else ++ out_be16(data_addr, value); ++ ++ return 0; ++} ++#endif ++ ++static int ssd1289_write(struct fb_info *info, unsigned short value, ++ unsigned int flag) ++{ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ ssd1289_flexbus_write(info, value, flag); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ ssd1289_spi_write(info, value, flag); ++#endif ++ return 0; ++} ++ ++static void fsl_ssd1289_enable_lcd(struct fb_info *info) ++{ ++ int i; ++ ++#if defined(CONFIG_SSD1289_SPI_MODE) ++ int count; ++#elif defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ /* GPIO configuration */ ++ MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_BE3_FB_A1 | MCF_GPIO_PAR_BE_BE2_FB_A0 ++ | MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0; ++ MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS0_CS0; ++#endif ++ ++ ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0); ++ ssd1289_write(info, 0x0200, 1); ++ ++ ssd1289_write(info, SSD1289_REG_OSCILLATION, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ mdelay(100); ++ ++ /* turn on the oscillator */ ++ ssd1289_write(info, SSD1289_REG_OSCILLATION, 0); ++ ssd1289_write(info, 0x0001, 1); ++ ++ mdelay(100); ++ /* power control 1 */ ++ ssd1289_write(info, SSD1289_REG_POWER_CTRL_1, 0); ++ ssd1289_write(info, 0xaeac, 1); ++ ++ /* power control 2 */ ++ ssd1289_write(info, SSD1289_REG_POWER_CTRL_2, 0); ++ ssd1289_write(info, 0x0007, 1); ++ ++ /* power control 3 */ ++ ssd1289_write(info, SSD1289_REG_POWER_CTRL_3, 0); ++ ssd1289_write(info, 0x000f, 1); ++ ++ /* power control 4 */ ++ ssd1289_write(info, SSD1289_REG_POWER_CTRL_4, 0); ++ ssd1289_write(info, 0x2900, 1); ++ ++ /* power control 5 */ ++ ssd1289_write(info, SSD1289_REG_POWER_CTRL_5, 0); ++ ssd1289_write(info, 0x00b3, 1); ++ ++ mdelay(15); ++ /* driver output control */ ++ ssd1289_write(info, SSD1289_REG_DRIVER_OUT_CTRL, 0); ++ ssd1289_write(info, 0x2b3f, 1); ++ ++ /* lcd-driving-waveform control */ ++ ssd1289_write(info, SSD1289_REG_LCD_DRIVE_AC, 0); ++ ssd1289_write(info, 0x0600, 1); ++ ++ /* sleep mode */ ++ ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ /* entry mode */ ++ ssd1289_write(info, SSD1289_REG_ENTRY_MODE, 0); ++ ssd1289_write(info, 0x60a8, 1); ++ ++ mdelay(15); ++ /* compare register */ ++ ssd1289_write(info, SSD1289_REG_COMPARE_1, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_COMPARE_2, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ /* horizontal porch */ ++ ssd1289_write(info, SSD1289_REG_H_PORCH, 0); ++ ssd1289_write(info, 0xef1c, 1); ++ ++ /* vertical porch */ ++ ssd1289_write(info, SSD1289_REG_V_PORCH, 0); ++ ssd1289_write(info, 0x0003, 1); ++ ++ /* display control */ ++ ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0); ++ ssd1289_write(info, 0x0233, 1); ++ ++ /* frame cycle control */ ++ ssd1289_write(info, SSD1289_REG_FRAME_CYCLE, 0); ++ ssd1289_write(info, 0x5312, 1); ++ ++ /* gate scan position */ ++ ssd1289_write(info, SSD1289_REG_GATE_SCAN_START, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ mdelay(20); ++ /* vertical scroll control */ ++ ssd1289_write(info, SSD1289_REG_V_SCROLL_CTRL_1, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_V_SCROLL_CTRL_2, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ /* 1st screen driving position */ ++ ssd1289_write(info, SSD1289_REG_FIRST_WIN_START, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_FIRST_WIN_END, 0); ++ ssd1289_write(info, 0x013F, 1); ++ ++ /* 2nd screen driving position */ ++ ssd1289_write(info, SSD1289_REG_SECND_WIN_START, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_SECND_WIN_END, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ mdelay(20); ++ /* gamma control */ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_1, 0); ++ ssd1289_write(info, 0x0707, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_2, 0); ++ ssd1289_write(info, 0x0704, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_3, 0); ++ ssd1289_write(info, 0x0204, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_4, 0); ++ ssd1289_write(info, 0x0201, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_5, 0); ++ ssd1289_write(info, 0x0203, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_6, 0); ++ ssd1289_write(info, 0x0204, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_7, 0); ++ ssd1289_write(info, 0x0204, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_8, 0); ++ ssd1289_write(info, 0x0502, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_9, 0); ++ ssd1289_write(info, 0x0302, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_10, 0); ++ ssd1289_write(info, 0x0500, 1); ++ ++ /* ram write data mask */ ++ ssd1289_write(info, SSD1289_REG_WR_DATA_MASK_1, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_WR_DATA_MASK_2, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ /* frame frequency control */ ++ ssd1289_write(info, SSD1289_REG_FRAME_FREQUENCY, 0); ++ ssd1289_write(info, 0xe000, 1); ++ ++ /* optimize data access speed */ ++ ssd1289_write(info, SSD1289_REG_OPT_SPEED_1, 0); ++ ssd1289_write(info, 0x0006, 1); ++ ++ ssd1289_write(info, SSD1289_REG_OPT_SPEED_2, 0); ++ ssd1289_write(info, 0x12ae, 1); ++ ++ ssd1289_write(info, SSD1289_REG_OPT_SPEED_3, 0); ++ ssd1289_write(info, 0x6ceb, 1); ++ ++ /* horizontal ram address position */ ++ ssd1289_write(info, SSD1289_REG_H_RAM_ADR_POS, 0); ++ ssd1289_write(info, 0xef00, 1); ++ ++ /* vertical ram address position */ ++ ssd1289_write(info, SSD1289_REG_V_RAM_ADR_START, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_V_RAM_ADR_END, 0); ++ ssd1289_write(info, 0x013f, 1); ++ ++ mdelay(20); ++ ++ /* set start address counter */ ++ ssd1289_write(info, SSD1289_REG_GDDRAM_X_ADDR, 0); ++ ssd1289_write(info, 0x00ef, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GDDRAM_Y_ADDR, 0); ++ ssd1289_write(info, 0x0000, 1); ++ ++ ssd1289_write(info, SSD1289_REG_GDDRAM_DATA, 0); ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ for (i = 0; i < info->screen_size; i += 2) ++ ssd1289_write(info, 0, 1); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ count = info->screen_size / SPI_LCD_BLOCK_HALF_SIZE; ++ for (i = 0; i < count; i++) ++ ssd1289_spi_writeblock(info, NULL, 0); ++#endif ++} ++ ++static void fsl_ssd1289_disable_lcd(struct fb_info *info) ++{ ++ ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0); ++ ssd1289_write(info, 0x0200, 1); ++ ++ ssd1289_write(info, SSD1289_REG_OSCILLATION, 0); ++ ssd1289_write(info, 0x0000, 1); ++} ++ ++static int ssd1289fbd(void *arg) ++{ ++ struct fb_info *info = arg; ++ int i; ++ unsigned short *buf_p; ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++#if defined(CONFIG_SSD1289_SPI_MODE) ++ unsigned char *bufspi_p; ++ int count; ++#endif ++ ++ while (!kthread_should_stop()) { ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ if (fbinfo->openflag == 1) { ++ buf_p = (unsigned short *)(info->screen_base); ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ for (i = 0; i < info->screen_size; i += 2) { ++ ssd1289_write(info, *buf_p, 1); ++ buf_p++; ++ } ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ bufspi_p = (unsigned char *)buf_p; ++ count = info->screen_size / SPI_LCD_BLOCK_HALF_SIZE; ++ for (i = 0; i < count; i++) ++ ssd1289_spi_writeblock(info, (bufspi_p + ++ SPI_LCD_BLOCK_HALF_SIZE * i), 1); ++#endif ++ } ++ schedule_timeout(HZ/25); ++ } ++ ++ return 0; ++} ++ ++static int fsl_ssd1289_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ if (var->xres_virtual < var->xres) ++ var->xres_virtual = var->xres; ++ if (var->yres_virtual < var->yres) ++ var->yres_virtual = var->yres; ++ ++ if (var->xoffset < 0) ++ var->xoffset = 0; ++ ++ if (var->yoffset < 0) ++ var->yoffset = 0; ++ ++ if (var->xoffset + info->var.xres > info->var.xres_virtual) ++ var->xoffset = info->var.xres_virtual - info->var.xres; ++ ++ if (var->yoffset + info->var.yres > info->var.yres_virtual) ++ var->yoffset = info->var.yres_virtual - info->var.yres; ++ ++ switch (var->bits_per_pixel) { ++ case 8: ++ /* 8 bpp, 332 format */ ++ var->red.length = 3; ++ var->red.offset = 5; ++ var->red.msb_right = 0; ++ ++ var->green.length = 3; ++ var->green.offset = 2; ++ var->green.msb_right = 0; ++ ++ var->blue.length = 2; ++ var->blue.offset = 0; ++ var->blue.msb_right = 0; ++ ++ var->transp.length = 0; ++ var->transp.offset = 0; ++ var->transp.msb_right = 0; ++ break; ++ case 16: ++ /* 16 bpp, 565 format */ ++ var->red.length = 5; ++ var->red.offset = 11; ++ var->red.msb_right = 0; ++ ++ var->green.length = 6; ++ var->green.offset = 5; ++ var->green.msb_right = 0; ++ ++ var->blue.length = 5; ++ var->blue.offset = 0; ++ var->blue.msb_right = 0; ++ ++ var->transp.length = 0; ++ var->transp.offset = 0; ++ var->transp.msb_right = 0; ++ break; ++ default: ++ printk(KERN_ERR "Depth not supported: %u BPP\n", ++ var->bits_per_pixel); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int fsl_ssd1289_set_par(struct fb_info *info) ++{ ++ struct fb_var_screeninfo *var = &info->var; ++ ++ switch (var->bits_per_pixel) { ++ case 16: ++ info->fix.visual = FB_VISUAL_TRUECOLOR; ++ break; ++ case 8: ++ info->fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ break; ++ default: ++ info->fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ break; ++ } ++ ++ return 0; ++} ++ ++static inline __u32 CNVT_TOHW(__u32 val, __u32 width) ++{ ++ return ((val<<width) + 0x7FFF - val)>>16; ++} ++ ++static int fsl_ssd1289_setcolreg(unsigned regno, ++ unsigned red, unsigned green, unsigned blue, ++ unsigned transp, struct fb_info *info) ++{ ++ int ret = 1; ++ ++ /* ++ * If greyscale is true, then we convert the RGB value ++ * to greyscale no matter what visual we are using. ++ */ ++ if (info->var.grayscale) ++ red = green = blue = (19595 * red + 38470 * green + ++ 7471 * blue) >> 16; ++ switch (info->fix.visual) { ++ case FB_VISUAL_TRUECOLOR: ++ if (regno < 16) { ++ u32 *pal = info->pseudo_palette; ++ u32 value; ++ ++ red = CNVT_TOHW(red, info->var.red.length); ++ green = CNVT_TOHW(green, info->var.green.length); ++ blue = CNVT_TOHW(blue, info->var.blue.length); ++ transp = CNVT_TOHW(transp, info->var.transp.length); ++ ++ value = (red << info->var.red.offset) | ++ (green << info->var.green.offset) | ++ (blue << info->var.blue.offset) | ++ (transp << info->var.transp.offset); ++ ++ pal[regno] = value; ++ ret = 0; ++ } ++ break; ++ case FB_VISUAL_STATIC_PSEUDOCOLOR: ++ case FB_VISUAL_PSEUDOCOLOR: ++ break; ++ } ++ return ret; ++} ++ ++static int fsl_ssd1289_blank(int blank_mode, struct fb_info *info) ++{ ++ if (blank_mode == FB_BLANK_POWERDOWN) ++ fsl_ssd1289_disable_lcd(info); ++ else ++ fsl_ssd1289_enable_lcd(info); ++ ++ return 0; ++} ++ ++static int fsl_ssd1289_open(struct fb_info *info, int user) ++{ ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ struct task_struct *task; ++ int ret; ++ ++ if (fbinfo->openflag == 0) { ++ memset(info->screen_base, 0, info->screen_size); ++ fsl_ssd1289_enable_lcd(info); ++ ++ task = kthread_run(ssd1289fbd, info, "SSD1289 LCD"); ++ if (IS_ERR(task)) { ++ ret = PTR_ERR(task); ++ return ret; ++ } ++ fbinfo->task = task; ++ } ++ ++ fbinfo->openflag = 1; ++ return 0; ++} ++ ++static int fsl_ssd1289_release(struct fb_info *info, int user) ++{ ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ ++ fbinfo->openflag = 0; ++ if (fbinfo->task) { ++ struct task_struct *task = fbinfo->task; ++ fbinfo->task = NULL; ++ kthread_stop(task); ++ } ++ ++ memset(info->screen_base, 0, info->screen_size); ++ fsl_ssd1289_disable_lcd(info); ++ return 0; ++} ++ ++static struct fb_ops fsl_ssd1289_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = fsl_ssd1289_check_var, ++ .fb_set_par = fsl_ssd1289_set_par, ++ .fb_setcolreg = fsl_ssd1289_setcolreg, ++ .fb_blank = fsl_ssd1289_blank, ++ .fb_open = fsl_ssd1289_open, ++ .fb_release = fsl_ssd1289_release, ++ .fb_copyarea = cfb_copyarea, ++ .fb_fillrect = cfb_fillrect, ++ .fb_imageblit = cfb_imageblit, ++}; ++ ++static int fsl_ssd1289_map_video_memory(struct fb_info *info) ++{ ++ unsigned int map_size = info->fix.smem_len; ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ ++ fbinfo->ssd1289_reg.cmd = ++ ioremap_nocache(FLEXBUS_LCD_CMD_ADDRESS, 2); ++ fbinfo->ssd1289_reg.data = ++ ioremap_nocache(FLEXBUS_LCD_DATA_ADDRESS, 2); ++#endif ++ ++ info->screen_base = kmalloc(map_size, GFP_KERNEL); ++ info->fix.smem_start = virt_to_phys(info->screen_base); ++ info->screen_size = info->fix.smem_len; ++ ++ if (info->screen_base) ++ memset(info->screen_base, 0, map_size); ++ ++ return info->screen_base ? 0 : -ENOMEM; ++} ++ ++static inline void fsl_ssd1289_unmap_video_memory(struct fb_info *info) ++{ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ struct fsl_ssd1289_fb_info *fbinfo = info->par; ++ ++ iounmap(fbinfo->ssd1289_reg.cmd); ++ iounmap(fbinfo->ssd1289_reg.data); ++#endif ++ kfree(info->screen_base); ++} ++ ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static int fsl_ssd1289_probe(struct platform_device *pdev) ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++static int fsl_ssd1289_probe(struct spi_device *spi) ++#endif ++{ ++ struct fsl_ssd1289_fb_info *fbinfo; ++ struct fb_info *info; ++ struct fsl_ssd1289_fb_display *display; ++ int ret; ++ unsigned long smem_len; ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ info = framebuffer_alloc(sizeof(struct fsl_ssd1289_fb_info), ++ &pdev->dev); ++ if (!info) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, info); ++ ++ fbinfo = info->par; ++ fbinfo->dev = &pdev->dev; ++ display = pdev->dev.platform_data; ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ info = framebuffer_alloc(sizeof(struct fsl_ssd1289_fb_info), ++ &spi->dev); ++ if (!info) ++ return -ENOMEM; ++ ++ dev_set_drvdata(&spi->dev, info); ++ ++ fbinfo = info->par; ++ fbinfo->dev = &spi->dev; ++ fbinfo->spidev = spi; ++ display = spi->dev.platform_data; ++#endif ++ ++ fbinfo->openflag = 0; ++ info->fix.type = FB_TYPE_PACKED_PIXELS; ++ info->fix.type_aux = 0; ++ info->fix.xpanstep = 0; ++ info->fix.ypanstep = 0; ++ info->fix.ywrapstep = 0; ++ info->fix.accel = FB_ACCEL_NONE; ++ ++ info->var.nonstd = 0; ++ info->var.activate = FB_ACTIVATE_NOW; ++ info->var.accel_flags = 0; ++ info->var.vmode = FB_VMODE_NONINTERLACED; ++ ++ info->fbops = &fsl_ssd1289_ops; ++ info->flags = FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT ++ | FBINFO_HWACCEL_COPYAREA; ++ info->pseudo_palette = &fbinfo->pseudo_palette; ++ ++ /* find maximum required memory size for display */ ++ smem_len = display->xres; ++ smem_len *= display->yres; ++ smem_len *= display->bpp; ++ smem_len >>= 3; ++ if (info->fix.smem_len < smem_len) ++ info->fix.smem_len = smem_len; ++ ++ /* Intialize video memory */ ++ ret = fsl_ssd1289_map_video_memory(info); ++ if (ret) { ++ printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret); ++ ret = -ENOMEM; ++ goto dealloc_fb; ++ } ++ ++ info->var.xres = display->xres; ++ info->var.yres = display->yres; ++ info->var.bits_per_pixel = display->bpp; ++ info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8; ++ ++ fsl_ssd1289_check_var(&info->var, info); ++ ++ ret = register_framebuffer(info); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register framebuffer device: %d\n", ++ ret); ++ goto free_video_memory; ++ } ++ ++ printk(KERN_INFO "fb: SSD1289 TFT LCD Framebuffer Driver\n"); ++ return 0; ++ ++free_video_memory: ++ fsl_ssd1289_unmap_video_memory(info); ++dealloc_fb: ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ platform_set_drvdata(pdev, NULL); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ dev_set_drvdata(&spi->dev, NULL); ++#endif ++ framebuffer_release(info); ++ return ret; ++} ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static int fsl_ssd1289_remove(struct platform_device *pdev) ++{ ++ struct fb_info *info = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++static int fsl_ssd1289_remove(struct spi_device *spi) ++{ ++ struct fb_info *info = dev_get_drvdata(&spi->dev); ++ ++ dev_set_drvdata(&spi->dev, NULL); ++#endif ++ unregister_framebuffer(info); ++ fsl_ssd1289_unmap_video_memory(info); ++ framebuffer_release(info); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static int fsl_ssd1289_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct fb_info *info = platform_get_drvdata(dev); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++static int fsl_ssd1289_suspend(struct spi_device *spi, pm_message_t state) ++{ ++ struct fb_info *info = dev_get_drvdata(&spi->dev); ++#endif ++ /* enter into sleep mode */ ++ ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0); ++ ssd1289_write(info, 0x0001, 1); ++ return 0; ++} ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static int fsl_ssd1289_resume(struct platform_device *dev) ++{ ++ struct fb_info *info = platform_get_drvdata(dev); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++static int fsl_ssd1289_resume(struct spi_device *spi) ++{ ++ struct fb_info *info = dev_get_drvdata(&spi->dev); ++#endif ++ /* leave sleep mode */ ++ ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0); ++ ssd1289_write(info, 0x0000, 1); ++ return 0; ++} ++#else ++#define fsl_ssd1289_suspend NULL ++#define fsl_ssd1289_resume NULL ++#endif ++ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++static struct platform_driver fsl_ssd1289_driver = { ++ .probe = fsl_ssd1289_probe, ++ .remove = fsl_ssd1289_remove, ++ .suspend = fsl_ssd1289_suspend, ++ .resume = fsl_ssd1289_resume, ++ .driver = { ++ .name = "fsl-ssd1289", ++ .owner = THIS_MODULE, ++ }, ++}; ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++static struct spi_driver spi_ssd1289_driver = { ++ .driver = { ++ .name = "spi-ssd1289", ++ .bus = &spi_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ .probe = fsl_ssd1289_probe, ++ .remove = fsl_ssd1289_remove, ++ .suspend = fsl_ssd1289_suspend, ++ .resume = fsl_ssd1289_resume, ++}; ++#endif ++ ++static int __devinit fsl_ssd1289_init(void) ++{ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ return platform_driver_register(&fsl_ssd1289_driver); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ return spi_register_driver(&spi_ssd1289_driver); ++#endif ++} ++ ++static void __exit fsl_ssd1289_exit(void) ++{ ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ return platform_driver_unregister(&fsl_ssd1289_driver); ++#elif defined(CONFIG_SSD1289_SPI_MODE) ++ return spi_unregister_driver(&spi_ssd1289_driver); ++#endif ++} ++ ++module_init(fsl_ssd1289_init); ++module_exit(fsl_ssd1289_exit); ++ ++MODULE_AUTHOR("Alison Wang <b18965@freescale.com>"); ++MODULE_DESCRIPTION("Freescale MCF54418 SSD1289 TFT LCD Framebuffer Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/coldfire/patches/019-Fix-the-format-field-for-the-Coldfire-exception-fram.patch b/target/linux/coldfire/patches/019-Fix-the-format-field-for-the-Coldfire-exception-fram.patch new file mode 100644 index 000000000..42c6f1b55 --- /dev/null +++ b/target/linux/coldfire/patches/019-Fix-the-format-field-for-the-Coldfire-exception-fram.patch @@ -0,0 +1,27 @@ +From 53cfdf92d9b68f5dac006853dd6727d7bf666b17 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:44 +0800 +Subject: [PATCH 19/52] Fix the format field for the Coldfire exception frame + +Different with M68K, the correct format field encoding +for ColdFire should be 4, 5, 6 or 7. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/mm/fault.c | 4 ++++ + 1 files changed, 4 insertions(+), 0 deletions(-) + +--- a/arch/m68k/mm/fault.c ++++ b/arch/m68k/mm/fault.c +@@ -45,7 +45,11 @@ int send_fault_sig(struct pt_regs *regs) + regs->stkadj = frame_extra_sizes[regs->format]; + tregs = (struct pt_regs *)((ulong)regs + regs->stkadj); + tregs->vector = regs->vector; ++#ifdef CONFIG_COLDFIRE ++ tregs->format = regs->stkadj + 4; ++#else + tregs->format = 0; ++#endif + tregs->pc = fixup->fixup; + tregs->sr = regs->sr; + return -1; diff --git a/target/linux/coldfire/patches/020-Add-dual-FEC-1588-timer-support.patch b/target/linux/coldfire/patches/020-Add-dual-FEC-1588-timer-support.patch new file mode 100644 index 000000000..43a258f17 --- /dev/null +++ b/target/linux/coldfire/patches/020-Add-dual-FEC-1588-timer-support.patch @@ -0,0 +1,1257 @@ +From 67d56859d24864af530506c76523f0fc3c5cb502 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:44 +0800 +Subject: [PATCH 20/52] Add dual FEC 1588 timer support + +Add Modelo dual FEC 1588 function with IXXXAT statck. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/net/Kconfig | 6 + + drivers/net/Makefile | 3 + + drivers/net/fec.c | 153 ++++++++++++- + drivers/net/fec.h | 25 ++ + drivers/net/fec_1588.c | 626 ++++++++++++++++++++++++++++++++++++++++++++++++ + drivers/net/fec_1588.h | 195 +++++++++++++++ + 6 files changed, 1006 insertions(+), 2 deletions(-) + create mode 100644 drivers/net/fec_1588.c + create mode 100644 drivers/net/fec_1588.h + +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -1958,6 +1958,12 @@ config FEC2 + Say Y here if you want to use the second built-in 10/100 Fast + ethernet controller on some Motorola ColdFire processors. + ++config FEC_1588 ++ bool "Enable 1588 interface(on some ColdFire designs)" ++ depends on M5441X && FEC ++ help ++ Say Y here if 1588 function is enabled. ++ + config FEC_548x + tristate "MCF547x/MCF548x Fast Ethernet Controller support" + depends on M547X_8X +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -123,6 +123,9 @@ obj-$(CONFIG_PCMCIA_PCNET) += 8390.o + obj-$(CONFIG_HP100) += hp100.o + obj-$(CONFIG_SMC9194) += smc9194.o + obj-$(CONFIG_FEC) += fec.o ++ifeq ($(CONFIG_FEC_1588), y) ++obj-$(CONFIG_FEC) += fec_1588.o ++endif + obj-$(CONFIG_FEC_548x) += fec_m547x.o + obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o + ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y) +--- a/drivers/net/fec.c ++++ b/drivers/net/fec.c +@@ -53,6 +53,7 @@ + #endif + + #include "fec.h" ++#include "fec_1588.h" + + #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) + #define FEC_ALIGNMENT 0xf +@@ -135,8 +136,15 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet + #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ + #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ + #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ ++#define FEC_ENET_TS_AVAIL ((uint)0x00010000) ++#define FEC_ENET_TS_TIMER ((uint)0x00008000) + ++#if defined(CONFIG_FEC_1588) ++#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | \ ++ FEC_ENET_TS_AVAIL | FEC_ENET_TS_TIMER) ++#else + #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) ++#endif + + /* The FEC stores dest/src/type, data, and checksum for receive packets. + */ +@@ -209,6 +217,10 @@ struct fec_enet_private { + int link; + int full_duplex; + struct completion mdio_done; ++#ifdef CONFIG_FEC_1588 ++ struct fec_ptp_private *ptp_priv; ++ uint ptimer_present; ++#endif + }; + + static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); +@@ -252,6 +264,9 @@ fec_enet_start_xmit(struct sk_buff *skb, + struct bufdesc *bdp; + void *bufaddr; + unsigned short status; ++#ifdef CONFIG_FEC_1588 ++ unsigned long estatus; ++#endif + unsigned long flags; + + if (!fep->link) { +@@ -293,6 +308,17 @@ fec_enet_start_xmit(struct sk_buff *skb, + bufaddr = fep->tx_bounce[index]; + } + ++#ifdef CONFIG_FEC_1588 ++ if (fep->ptimer_present) { ++ if (fec_ptp_do_txstamp(skb)) ++ estatus = BD_ENET_TX_TS; ++ else ++ estatus = 0; ++ ++ bdp->cbd_esc = (estatus | BD_ENET_TX_INT); ++ bdp->cbd_bdu = 0; ++ } ++#endif + /* + * Some design made an incorrect assumption on endian mode of + * the system that it's running on. As the result, driver has to +@@ -357,6 +383,9 @@ fec_enet_interrupt(int irq, void * dev_i + { + struct net_device *dev = dev_id; + struct fec_enet_private *fep = netdev_priv(dev); ++#ifdef CONFIG_FEC_1588 ++ struct fec_ptp_private *fpp = fep->ptp_priv; ++#endif + uint int_events; + irqreturn_t ret = IRQ_NONE; + +@@ -364,6 +393,10 @@ fec_enet_interrupt(int irq, void * dev_i + int_events = readl(fep->hwp + FEC_IEVENT); + writel(int_events, fep->hwp + FEC_IEVENT); + ++#ifdef CONFIG_FEC_1588 ++ if (__raw_readb(MCF_DTIM1_DTER) & MCF_DTIM_DTER_REF) ++ __raw_writeb(MCF_DTIM_DTER_REF, MCF_DTIM1_DTER); ++#endif + if (int_events & FEC_ENET_RXF) { + ret = IRQ_HANDLED; + fec_enet_rx(dev); +@@ -378,6 +411,19 @@ fec_enet_interrupt(int irq, void * dev_i + fec_enet_tx(dev); + } + ++#ifdef CONFIG_FEC_1588 ++ if (int_events & FEC_ENET_TS_AVAIL) { ++ ret = IRQ_HANDLED; ++ fec_ptp_store_txstamp(fep->ptp_priv); ++ } ++ ++ if (int_events & FEC_ENET_TS_TIMER) { ++ ret = IRQ_HANDLED; ++ if (fep->ptimer_present) ++ fpp->prtc++; ++ } ++#endif ++ + if (int_events & FEC_ENET_MII) { + ret = IRQ_HANDLED; + complete(&fep->mdio_done); +@@ -394,6 +440,9 @@ fec_enet_tx(struct net_device *dev) + struct fec_enet_private *fep; + struct bufdesc *bdp; + unsigned short status; ++#ifdef CONFIG_FEC_1588 ++ unsigned long estatus; ++#endif + struct sk_buff *skb; + + fep = netdev_priv(dev); +@@ -437,6 +486,13 @@ fec_enet_tx(struct net_device *dev) + if (status & BD_ENET_TX_DEF) + dev->stats.collisions++; + ++#if defined(CONFIG_FEC_1588) ++ if (fep->ptimer_present) { ++ estatus = bdp->cbd_esc; ++ if (estatus & BD_ENET_TX_TS) ++ fec_ptp_store_txstamp(fep->ptp_priv); ++ } ++#endif + /* Free the sk buffer associated with this last transmit */ + dev_kfree_skb_any(skb); + fep->tx_skbuff[fep->skb_dirty] = NULL; +@@ -470,6 +526,9 @@ static void + fec_enet_rx(struct net_device *dev) + { + struct fec_enet_private *fep = netdev_priv(dev); ++#ifdef CONFIG_FEC_1588 ++ struct fec_ptp_private *fpp = fep->ptp_priv; ++#endif + const struct platform_device_id *id_entry = + platform_get_device_id(fep->pdev); + struct bufdesc *bdp; +@@ -554,6 +613,12 @@ fec_enet_rx(struct net_device *dev) + skb_put(skb, pkt_len - 4); /* Make room */ + skb_copy_to_linear_data(skb, data, pkt_len - 4); + skb->protocol = eth_type_trans(skb, dev); ++ ++#ifdef CONFIG_FEC_1588 ++ /* 1588 messeage TS handle */ ++ if (fep->ptimer_present) ++ fec_ptp_store_rxstamp(fpp, skb, bdp); ++#endif + netif_rx(skb); + } + +@@ -567,6 +632,11 @@ rx_processing_done: + status |= BD_ENET_RX_EMPTY; + bdp->cbd_sc = status; + ++#ifdef CONFIG_FEC_1588 ++ bdp->cbd_esc = BD_ENET_RX_INT; ++ bdp->cbd_prot = 0; ++ bdp->cbd_bdu = 0; ++#endif + /* Update BD pointer to next entry */ + if (status & BD_ENET_RX_WRAP) + bdp = fep->rx_bd_base; +@@ -669,8 +739,11 @@ static void fec_enet_adjust_link(struct + fec_stop(dev); + + if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) +- writel(2, fep->hwp + FEC_ECNTRL); +- ++#ifdef CONFIG_FEC_1588 ++ writel(0x00000012, fep->hwp + FEC_ECNTRL); ++#else ++ writel(0x00000002, fep->hwp + FEC_ECNTRL); ++#endif + status_change = 1; + } + +@@ -983,6 +1056,10 @@ static int fec_enet_alloc_buffers(struct + bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, + FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); + bdp->cbd_sc = BD_ENET_RX_EMPTY; ++ ++#ifdef CONFIG_FEC_1588 ++ bdp->cbd_esc = BD_ENET_RX_INT; ++#endif + bdp++; + } + +@@ -996,6 +1073,9 @@ static int fec_enet_alloc_buffers(struct + + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; ++#ifdef CONFIG_FEC_1588 ++ bdp->cbd_esc = BD_ENET_TX_INT; ++#endif + bdp++; + } + +@@ -1256,8 +1336,12 @@ fec_restart(struct net_device *dev, int + writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); + } + ++#ifdef CONFIG_FEC_1588 ++ writel(0x7fff8000, fep->hwp + FEC_IEVENT); ++#else + /* Clear any outstanding interrupt. */ + writel(0xffc00000, fep->hwp + FEC_IEVENT); ++#endif + + /* Reset all multicast. */ + writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); +@@ -1342,8 +1426,25 @@ fec_restart(struct net_device *dev, int + #endif + } + ++#ifdef CONFIG_FEC_1588 ++ if (fep->ptimer_present) { ++ int ret; ++ /* Set Timer count */ ++ ret = fec_ptp_start(fep->ptp_priv); ++ if (ret) { ++ fep->ptimer_present = 0; ++ writel(2, fep->hwp + FEC_ECNTRL); ++ } else { ++ val = readl(fep->hwp + FEC_ECNTRL); ++ val |= 0x00000012; ++ writel(val, fep->hwp + FEC_ECNTRL); ++ } ++ } else ++ writel(2, fep->hwp + FEC_ECNTRL); ++#else + /* And last, enable the transmit and receive processing */ + writel(2, fep->hwp + FEC_ECNTRL); ++#endif + writel(0, fep->hwp + FEC_R_DES_ACTIVE); + + /* Enable interrupts we wish to service */ +@@ -1367,6 +1468,10 @@ fec_stop(struct net_device *dev) + writel(1, fep->hwp + FEC_ECNTRL); + udelay(10); + writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); ++#ifdef CONFIG_FEC_1588 ++ if (fep->ptimer_present) ++ fec_ptp_stop(fep->ptp_priv); ++#endif + writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + } + +@@ -1428,6 +1533,24 @@ fec_probe(struct platform_device *pdev) + } + } + ++#ifdef CONFIG_FEC_1588 ++ i = (pdev->id) ? (64 + 64 + 64 + 7) : (64 + 64 + 64); ++ if (request_irq(i + 48, fec_enet_interrupt, IRQF_DISABLED, ++ "1588 TS AVAIL", ndev) != 0) ++ printk(KERN_ERR "FEC: Could not alloc FEC %x 1588 TS AVAIL " ++ "IRQ(%d)!\n", pdev->id, i + 48); ++ ++ if (pdev->id == 0) { ++ printk("setup TS timer interrupt through DMA timer1\n"); ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM1_DTMR); ++ ++ if (request_irq(64 + 33, fec_enet_interrupt, IRQF_DISABLED, ++ "1588 TS TIMER", ndev) != 0) ++ printk(KERN_ERR "FEC: Could not alloc FEC %x 1588 TS" ++ " TIMER IRQ(%d)!\n", pdev->id, 64 + 33); ++ } ++#endif ++ + fep->clk = clk_get(&pdev->dev, "fec_clk"); + if (IS_ERR(fep->clk)) { + ret = PTR_ERR(fep->clk); +@@ -1443,6 +1566,20 @@ fec_probe(struct platform_device *pdev) + if (ret) + goto failed_mii_init; + ++#ifdef CONFIG_FEC_1588 ++ fep->ptp_priv = kzalloc(sizeof(struct fec_ptp_private), ++ GFP_KERNEL); ++ if (fep->ptp_priv) { ++ fep->ptp_priv->hwp = fep->hwp; ++ ret = fec_ptp_init(fep->ptp_priv, pdev->id); ++ if (ret) ++ printk(KERN_ERR "IEEE1588: ptp-timer init failed\n"); ++ else ++ fep->ptimer_present = 1; ++ } else ++ printk(KERN_ERR "IEEE1588: failed to malloc memory\n"); ++#endif ++ + /* Carrier starts down, phylib will bring it up */ + netif_carrier_off(ndev); + +@@ -1454,6 +1591,12 @@ fec_probe(struct platform_device *pdev) + + failed_register: + fec_enet_mii_remove(fep); ++#ifdef CONFIG_FEC_1588 ++ if (fep->ptimer_present) ++ fec_ptp_cleanup(fep->ptp_priv); ++ ++ kfree(fep->ptp_priv); ++#endif + failed_mii_init: + failed_init: + clk_disable(fep->clk); +@@ -1485,6 +1628,12 @@ fec_drv_remove(struct platform_device *p + clk_disable(fep->clk); + clk_put(fep->clk); + iounmap((void __iomem *)ndev->base_addr); ++#ifdef CONFIG_FEC_1588 ++ if (fep->ptimer_present) ++ fec_ptp_cleanup(fep->ptp_priv); ++ ++ kfree(fep->ptp_priv); ++#endif + unregister_netdev(ndev); + free_netdev(ndev); + return 0; +--- a/drivers/net/fec.h ++++ b/drivers/net/fec.h +@@ -50,6 +50,16 @@ + #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ + #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ + ++#if defined(CONFIG_FEC_1588) ++#define FEC_ATIME_CTRL 0x400 ++#define FEC_ATIME 0x404 ++#define FEC_ATIME_EVT_OFFSET 0x408 ++#define FEC_ATIME_EVT_PERIOD 0x40c ++#define FEC_ATIME_CORR 0x410 ++#define FEC_ATIME_INC 0x414 ++#define FEC_TS_TIMESTAMP 0x418 ++#endif ++ + #else + + #define FEC_ECNTRL 0x000 /* Ethernet control reg */ +@@ -78,6 +88,9 @@ + + #endif /* CONFIG_M5272 */ + ++#if defined(CONFIG_FEC_1588) ++#define FEC_ENHANCED_MODE 1 ++#endif + + /* + * Define the buffer descriptor structure. +@@ -93,6 +106,14 @@ struct bufdesc { + unsigned short cbd_sc; /* Control and status info */ + unsigned short cbd_datlen; /* Data length */ + unsigned long cbd_bufaddr; /* Buffer address */ ++ ++#ifdef FEC_ENHANCED_MODE ++ unsigned long cbd_esc; ++ unsigned long cbd_prot; ++ unsigned long cbd_bdu; ++ unsigned long ts; ++ unsigned short res0[4]; ++#endif + }; + #endif + +@@ -128,6 +149,7 @@ struct bufdesc { + #define BD_ENET_RX_OV ((ushort)0x0002) + #define BD_ENET_RX_CL ((ushort)0x0001) + #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ ++#define BD_ENET_RX_INT 0x00800000 + + /* Buffer descriptor control/status used by Ethernet transmit. + */ +@@ -146,6 +168,9 @@ struct bufdesc { + #define BD_ENET_TX_CSL ((ushort)0x0001) + #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + ++#define BD_ENET_TX_TS 0x20000000 ++#define BD_ENET_TX_INT 0x40000000 ++#define BD_ENET_TX_BDU 0x80000000 + + /****************************************************************************/ + #endif /* FEC_H */ +--- /dev/null ++++ b/drivers/net/fec_1588.c +@@ -0,0 +1,626 @@ ++/* ++ * drivers/net/fec_1588.c ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Copyright (C) 2009 IXXAT Automation, GmbH ++ * ++ * FEC Ethernet Driver -- IEEE 1588 interface functionality ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ */ ++ ++#include <linux/io.h> ++#include <linux/device.h> ++#include <linux/fs.h> ++#include <linux/vmalloc.h> ++#include <linux/spinlock.h> ++#include <linux/ip.h> ++#include <linux/udp.h> ++#include <asm/mcf5441x_ccm.h> ++#include <asm/mcf5441x_dtim.h> ++#include <asm/mcfsim.h> ++#include "fec_1588.h" ++ ++static DECLARE_WAIT_QUEUE_HEAD(ptp_rx_ts_wait); ++#define PTP_GET_RX_TIMEOUT (HZ/10) ++#define COLDFIRE_DTIM1_INT (64+32+1) ++ ++static struct fec_ptp_private *ptp_private[2]; ++ ++static void init_DTIM1_for_1588(struct fec_ptp_private *priv) ++{ ++ printk(KERN_INFO "Initializing DTIM1 for 1588 TS timer\n"); ++ ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM1_DTMR); ++ ++ /*Enable 1588*/ ++ ++ __raw_writeb(MCF_DTIM_DTXMR_1588EN, MCF_DTIM1_DTXMR); ++ ++ /*Compare to the 1588 timerbase*/ ++ __raw_writel(FEC_T_PERIOD_ONE_SEC - FEC_T_INC_40MHZ, MCF_DTIM1_DTRR); ++ ++ __raw_writeb(MCF_DTIM_DTER_REF, MCF_DTIM1_DTER); ++ ++ MCF_GPIO_PAR_TIMER = (MCF_GPIO_PAR_TIMER & MCF_GPIO_PAR_TIMER_T1IN_MASK) ++ | MCF_GPIO_PAR_TIMER_T1IN_T1OUT; ++} ++ ++static void start_DTIM1(void) ++{ ++ __raw_writew(MCF_DTIM_DTMR_RST_EN | MCF_DTIM_DTMR_ORRI | ++ MCF_DTIM_DTMR_OM, MCF_DTIM1_DTMR); ++} ++ ++static void stop_DTIM1(void) ++{ ++ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM1_DTMR); ++} ++ ++/* Alloc the ring resource */ ++static int fec_ptp_init_circ(struct circ_buf *ptp_buf) ++{ ++ ptp_buf->buf = vmalloc(DEFAULT_PTP_RX_BUF_SZ * ++ sizeof(struct fec_ptp_data_t)); ++ ++ if (!ptp_buf->buf) ++ return 1; ++ ptp_buf->head = 0; ++ ptp_buf->tail = 0; ++ ++ return 0; ++} ++ ++static inline int fec_ptp_calc_index(int size, int curr_index, int offset) ++{ ++ return (curr_index + offset) % size; ++} ++ ++static int fec_ptp_is_empty(struct circ_buf *buf) ++{ ++ return (buf->head == buf->tail); ++} ++ ++static int fec_ptp_nelems(struct circ_buf *buf) ++{ ++ const int front = buf->head; ++ const int end = buf->tail; ++ const int size = DEFAULT_PTP_RX_BUF_SZ; ++ int n_items; ++ ++ if (end > front) ++ n_items = end - front; ++ else if (end < front) ++ n_items = size - (front - end); ++ else ++ n_items = 0; ++ ++ return n_items; ++} ++ ++static int fec_ptp_is_full(struct circ_buf *buf) ++{ ++ if (fec_ptp_nelems(buf) == ++ (DEFAULT_PTP_RX_BUF_SZ - 1)) ++ return 1; ++ else ++ return 0; ++} ++ ++static int fec_ptp_insert(struct circ_buf *ptp_buf, ++ struct fec_ptp_data_t *data, ++ struct fec_ptp_private *priv) ++{ ++ struct fec_ptp_data_t *tmp; ++ ++ if (fec_ptp_is_full(ptp_buf)) ++ return 1; ++ ++ spin_lock(&priv->ptp_lock); ++ tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + ptp_buf->tail; ++ ++ tmp->key = data->key; ++ tmp->ts_time.sec = data->ts_time.sec; ++ tmp->ts_time.nsec = data->ts_time.nsec; ++ ++ ptp_buf->tail = fec_ptp_calc_index(DEFAULT_PTP_RX_BUF_SZ, ++ ptp_buf->tail, 1); ++ spin_unlock(&priv->ptp_lock); ++ ++ return 0; ++} ++ ++static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf, ++ int key, ++ struct fec_ptp_data_t *data, ++ struct fec_ptp_private *priv) ++{ ++ int i; ++ int size = DEFAULT_PTP_RX_BUF_SZ; ++ int end = ptp_buf->tail; ++ unsigned long flags; ++ struct fec_ptp_data_t *tmp; ++ ++ if (fec_ptp_is_empty(ptp_buf)) ++ return 1; ++ ++ i = ptp_buf->head; ++ while (i != end) { ++ tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + i; ++ if (tmp->key == key) ++ break; ++ i = fec_ptp_calc_index(size, i, 1); ++ } ++ ++ spin_lock_irqsave(&priv->ptp_lock, flags); ++ if (i == end) { ++ ptp_buf->head = end; ++ spin_unlock_irqrestore(&priv->ptp_lock, flags); ++ return 1; ++ } ++ ++ data->ts_time.sec = tmp->ts_time.sec; ++ data->ts_time.nsec = tmp->ts_time.nsec; ++ ++ ptp_buf->head = fec_ptp_calc_index(size, i, 1); ++ spin_unlock_irqrestore(&priv->ptp_lock, flags); ++ ++ return 0; ++} ++ ++/* 1588 Module intialization */ ++int fec_ptp_start(struct fec_ptp_private *priv) ++{ ++ struct fec_ptp_private *fpp = priv; ++ ++ MCF_CCM_MISCCR3 = 0x0000; ++ ++ init_DTIM1_for_1588(priv); ++ ++ /* Select 1588 Timer source and enable module for starting Tmr Clock */ ++ fec_writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL); ++ fec_writel(FEC_T_INC_40MHZ << FEC_T_INC_OFFSET, ++ fpp->hwp + FEC_ATIME_INC); ++ fec_writel(FEC_T_PERIOD_ONE_SEC, fpp->hwp + FEC_ATIME_EVT_PERIOD); ++ /* start counter */ ++ fec_writel(FEC_T_CTRL_PERIOD_RST | FEC_T_CTRL_ENABLE | ++ FEC_T_CTRL_PINPER, fpp->hwp + FEC_ATIME_CTRL); ++ ++ start_DTIM1(); ++ ++ return 0; ++} ++ ++/* Cleanup routine for 1588 module. ++ * When PTP is disabled this routing is called */ ++void fec_ptp_stop(struct fec_ptp_private *priv) ++{ ++ struct fec_ptp_private *fpp = priv; ++ ++ fec_writel(0, fpp->hwp + FEC_ATIME_CTRL); ++ fec_writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL); ++ stop_DTIM1(); ++} ++ ++static void fec_get_curr_cnt(struct fec_ptp_private *priv, ++ struct ptp_rtc_time *curr_time) ++{ ++ u32 tempval; ++ ++ fec_writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL); ++ fec_writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL); ++ curr_time->rtc_time.nsec = fec_readl(priv->hwp + FEC_ATIME); ++ curr_time->rtc_time.sec = priv->prtc; ++ ++ fec_writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL); ++ tempval = fec_readl(priv->hwp + FEC_ATIME); ++ if (tempval < curr_time->rtc_time.nsec) { ++ curr_time->rtc_time.nsec = tempval; ++ curr_time->rtc_time.sec = priv->prtc; ++ } ++} ++ ++/* Set the 1588 timer counter registers */ ++static void fec_set_1588cnt(struct fec_ptp_private *priv, ++ struct ptp_rtc_time *fec_time) ++{ ++ u32 tempval; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->cnt_lock, flags); ++ ++ priv->prtc = fec_time->rtc_time.sec; ++ ++ tempval = fec_time->rtc_time.nsec; ++ fec_writel(tempval, priv->hwp + FEC_ATIME); ++ spin_unlock_irqrestore(&priv->cnt_lock, flags); ++} ++ ++/* Set the BD to ptp */ ++int fec_ptp_do_txstamp(struct sk_buff *skb) ++{ ++ struct iphdr *iph; ++ struct udphdr *udph; ++ ++ if (skb->len > 44) { ++ /* Check if port is 319 for PTP Event, and check for UDP */ ++ iph = ip_hdr(skb); ++ if (iph == NULL || iph->protocol != FEC_PACKET_TYPE_UDP) ++ return 0; ++ ++ udph = udp_hdr(skb); ++ if (udph != NULL && ntohs(udph->source) == 319) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++void fec_ptp_store_txstamp(struct fec_ptp_private *priv) ++{ ++ struct fec_ptp_private *fpp = priv; ++ unsigned int reg; ++ ++ reg = fec_readl(fpp->hwp + FEC_TS_TIMESTAMP); ++ fpp->txstamp.nsec = reg; ++ fpp->txstamp.sec = fpp->prtc; ++} ++ ++void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, ++ struct sk_buff *skb, ++ struct bufdesc *bdp) ++{ ++ int msg_type, seq_id, control; ++ struct fec_ptp_data_t tmp_rx_time; ++ struct fec_ptp_private *fpp = priv; ++ struct iphdr *iph; ++ struct udphdr *udph; ++ ++ /* Check for UDP, and Check if port is 319 for PTP Event */ ++ iph = (struct iphdr *)(skb->data + FEC_PTP_IP_OFFS); ++ if (iph->protocol != FEC_PACKET_TYPE_UDP) ++ return; ++ ++ udph = (struct udphdr *)(skb->data + FEC_PTP_UDP_OFFS); ++ if (ntohs(udph->source) != 319) ++ return; ++ ++ seq_id = *((u16 *)(skb->data + FEC_PTP_SEQ_ID_OFFS)); ++ control = *((u8 *)(skb->data + FEC_PTP_CTRL_OFFS)); ++ ++ tmp_rx_time.key = ntohs(seq_id); ++ tmp_rx_time.ts_time.sec = fpp->prtc; ++ tmp_rx_time.ts_time.nsec = bdp->ts; ++ ++ switch (control) { ++ ++ case PTP_MSG_SYNC: ++ fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time, priv); ++ break; ++ ++ case PTP_MSG_DEL_REQ: ++ fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time, priv); ++ break; ++ ++ /* clear transportSpecific field*/ ++ case PTP_MSG_ALL_OTHER: ++ msg_type = (*((u8 *)(skb->data + ++ FEC_PTP_MSG_TYPE_OFFS))) & 0x0F; ++ switch (msg_type) { ++ case PTP_MSG_P_DEL_REQ: ++ fec_ptp_insert(&(priv->rx_time_pdel_req), ++ &tmp_rx_time, priv); ++ break; ++ case PTP_MSG_P_DEL_RESP: ++ fec_ptp_insert(&(priv->rx_time_pdel_resp), ++ &tmp_rx_time, priv); ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ wake_up_interruptible(&ptp_rx_ts_wait); ++} ++ ++static void fec_get_tx_timestamp(struct fec_ptp_private *priv, ++ struct ptp_time *tx_time) ++{ ++ tx_time->sec = priv->txstamp.sec; ++ tx_time->nsec = priv->txstamp.nsec; ++} ++ ++static uint8_t fec_get_rx_time(struct fec_ptp_private *priv, ++ struct ptp_ts_data *pts, ++ struct ptp_time *rx_time) ++{ ++ struct fec_ptp_data_t tmp; ++ int key, flag; ++ u8 mode; ++ ++ key = pts->seq_id; ++ mode = pts->message_type; ++ switch (mode) { ++ case PTP_MSG_SYNC: ++ flag = fec_ptp_find_and_remove(&(priv->rx_time_sync), ++ key, &tmp, priv); ++ break; ++ case PTP_MSG_DEL_REQ: ++ flag = fec_ptp_find_and_remove(&(priv->rx_time_del_req), ++ key, &tmp, priv); ++ break; ++ ++ case PTP_MSG_P_DEL_REQ: ++ flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_req), ++ key, &tmp, priv); ++ break; ++ case PTP_MSG_P_DEL_RESP: ++ flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_resp), ++ key, &tmp, priv); ++ break; ++ ++ default: ++ flag = 1; ++ printk(KERN_ERR "ERROR\n"); ++ break; ++ } ++ ++ if (!flag) { ++ rx_time->sec = tmp.ts_time.sec; ++ rx_time->nsec = tmp.ts_time.nsec; ++ return 0; ++ } else { ++ wait_event_interruptible_timeout(ptp_rx_ts_wait, 0, ++ PTP_GET_RX_TIMEOUT); ++ ++ switch (mode) { ++ case PTP_MSG_SYNC: ++ flag = fec_ptp_find_and_remove(&(priv->rx_time_sync), ++ key, &tmp, priv); ++ break; ++ case PTP_MSG_DEL_REQ: ++ flag = fec_ptp_find_and_remove( ++ &(priv->rx_time_del_req), key, &tmp, priv); ++ break; ++ case PTP_MSG_P_DEL_REQ: ++ flag = fec_ptp_find_and_remove( ++ &(priv->rx_time_pdel_req), key, &tmp, priv); ++ break; ++ case PTP_MSG_P_DEL_RESP: ++ flag = fec_ptp_find_and_remove( ++ &(priv->rx_time_pdel_resp), key, &tmp, priv); ++ break; ++ } ++ ++ if (flag == 0) { ++ rx_time->sec = tmp.ts_time.sec; ++ rx_time->nsec = tmp.ts_time.nsec; ++ return 0; ++ } ++ ++ return -1; ++ } ++} ++ ++static void fec_handle_ptpdrift( ++ struct ptp_set_comp *comp, ++ struct ptp_time_correct *ptc) ++{ ++ u32 ndrift; ++ u32 i; ++ u32 tmp, tmp_ns, tmp_prid; ++ u32 min_ns, min_prid, miss_ns; ++ ++ ndrift = comp->drift; ++ if (ndrift == 0) { ++ ptc->corr_inc = 0; ++ ptc->corr_period = 0; ++ return; ++ } ++ ++ if (ndrift >= FEC_ATIME_40MHZ) { ++ ptc->corr_inc = (u32)(ndrift / FEC_ATIME_40MHZ); ++ ptc->corr_period = 1; ++ return; ++ } ++ ++ min_ns = 1; ++ tmp = FEC_ATIME_40MHZ % ndrift; ++ tmp_prid = (u32)(FEC_ATIME_40MHZ / ndrift); ++ min_prid = tmp_prid; ++ miss_ns = tmp / tmp_prid; ++ for (i = 2; i <= FEC_T_INC_40MHZ; i++) { ++ tmp = (FEC_ATIME_40MHZ * i) % ndrift; ++ tmp_prid = (FEC_ATIME_40MHZ * i) / ndrift; ++ tmp_ns = tmp / tmp_prid; ++ if (tmp_ns <= 10) { ++ min_ns = i; ++ min_prid = tmp_prid; ++ break; ++ } ++ ++ if (tmp_ns < miss_ns) { ++ min_ns = i; ++ min_prid = tmp_prid; ++ miss_ns = tmp_ns; ++ } ++ } ++ ++ ptc->corr_inc = min_ns; ++ ptc->corr_period = min_prid; ++} ++ ++static void fec_set_drift(struct fec_ptp_private *priv, ++ struct ptp_set_comp *comp) ++{ ++ struct ptp_time_correct tc; ++ struct fec_ptp_private *fpp = priv; ++ u32 tmp, corr_ns; ++ ++ fec_handle_ptpdrift(comp, &tc); ++ if (tc.corr_inc == 0) ++ return; ++ ++ if (comp->o_ops == TRUE) ++ corr_ns = FEC_T_INC_40MHZ + tc.corr_inc; ++ else ++ corr_ns = FEC_T_INC_40MHZ - tc.corr_inc; ++ ++ tmp = fec_readl(fpp->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; ++ tmp |= corr_ns << FEC_T_INC_CORR_OFFSET; ++ fec_writel(tmp, fpp->hwp + FEC_ATIME_INC); ++ ++ fec_writel(tc.corr_period, fpp->hwp + FEC_ATIME_CORR); ++} ++ ++static int ptp_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int ptp_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static long ptp_unlocked_ioctl( ++ struct file *file, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ struct ptp_rtc_time *cnt; ++ struct ptp_rtc_time curr_time; ++ struct ptp_time rx_time, tx_time; ++ struct ptp_ts_data *p_ts; ++ struct ptp_set_comp *p_comp; ++ struct fec_ptp_private *priv; ++ struct inode *inode = file->f_mapping->host; ++ unsigned int minor = MINOR(inode->i_rdev); ++ long retval = 0; ++ ++ priv = (struct fec_ptp_private *) ptp_private[minor]; ++ switch (cmd) { ++ case PTP_GET_RX_TIMESTAMP: ++ p_ts = (struct ptp_ts_data *)arg; ++ retval = fec_get_rx_time(priv, p_ts, &rx_time); ++ if (retval == 0) ++ copy_to_user((void __user *)(&(p_ts->ts)), &rx_time, ++ sizeof(rx_time)); ++ break; ++ case PTP_GET_TX_TIMESTAMP: ++ p_ts = (struct ptp_ts_data *)arg; ++ fec_get_tx_timestamp(priv, &tx_time); ++ copy_to_user((void __user *)(&(p_ts->ts)), &tx_time, ++ sizeof(tx_time)); ++ break; ++ case PTP_GET_CURRENT_TIME: ++ fec_get_curr_cnt(priv, &curr_time); ++ copy_to_user((void __user *)arg, &curr_time, sizeof(curr_time)); ++ break; ++ case PTP_SET_RTC_TIME: ++ cnt = (struct ptp_rtc_time *)arg; ++ fec_set_1588cnt(priv, cnt); ++ break; ++ case PTP_FLUSH_TIMESTAMP: ++ /* reset sync buffer */ ++ priv->rx_time_sync.head = 0; ++ priv->rx_time_sync.tail = 0; ++ /* reset delay_req buffer */ ++ priv->rx_time_del_req.head = 0; ++ priv->rx_time_del_req.tail = 0; ++ /* reset pdelay_req buffer */ ++ priv->rx_time_pdel_req.head = 0; ++ priv->rx_time_pdel_req.tail = 0; ++ /* reset pdelay_resp buffer */ ++ priv->rx_time_pdel_resp.head = 0; ++ priv->rx_time_pdel_resp.tail = 0; ++ break; ++ case PTP_SET_COMPENSATION: ++ p_comp = (struct ptp_set_comp *)arg; ++ fec_set_drift(priv, p_comp); ++ break; ++ case PTP_GET_ORIG_COMP: ++ ((struct ptp_get_comp *)arg)->dw_origcomp = FEC_PTP_ORIG_COMP; ++ break; ++ default: ++ return -EINVAL; ++ } ++ return retval; ++} ++ ++static const struct file_operations ptp_fops = { ++ .owner = THIS_MODULE, ++ .llseek = NULL, ++ .read = NULL, ++ .write = NULL, ++ .unlocked_ioctl = ptp_unlocked_ioctl, ++ .open = ptp_open, ++ .release = ptp_release, ++}; ++ ++static int init_ptp(void) ++{ ++ if (register_chrdev(PTP_MAJOR, "ptp", &ptp_fops)) ++ printk(KERN_ERR "Unable to register PTP deivce as char\n"); ++ ++ return 0; ++} ++ ++static void ptp_free(void) ++{ ++ /*unregister the PTP device*/ ++ unregister_chrdev(PTP_MAJOR, "ptp"); ++} ++ ++ ++ ++/* ++ * Resource required for accessing 1588 Timer Registers. ++ */ ++int fec_ptp_init(struct fec_ptp_private *priv, int id) ++{ ++ fec_ptp_init_circ(&(priv->rx_time_sync)); ++ fec_ptp_init_circ(&(priv->rx_time_del_req)); ++ fec_ptp_init_circ(&(priv->rx_time_pdel_req)); ++ fec_ptp_init_circ(&(priv->rx_time_pdel_resp)); ++ ++ spin_lock_init(&priv->ptp_lock); ++ spin_lock_init(&priv->cnt_lock); ++ ptp_private[id] = priv; ++ if (id == 0) ++ init_ptp(); ++ return 0; ++} ++EXPORT_SYMBOL(fec_ptp_init); ++ ++void fec_ptp_cleanup(struct fec_ptp_private *priv) ++{ ++ ++ if (priv->rx_time_sync.buf) ++ vfree(priv->rx_time_sync.buf); ++ if (priv->rx_time_del_req.buf) ++ vfree(priv->rx_time_del_req.buf); ++ if (priv->rx_time_pdel_req.buf) ++ vfree(priv->rx_time_pdel_req.buf); ++ if (priv->rx_time_pdel_resp.buf) ++ vfree(priv->rx_time_pdel_resp.buf); ++ ++ ptp_free(); ++} ++EXPORT_SYMBOL(fec_ptp_cleanup); +--- /dev/null ++++ b/drivers/net/fec_1588.h +@@ -0,0 +1,195 @@ ++/* ++ * drivers/net/fec_1588.h ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ */ ++ ++#ifndef FEC_1588_H ++#define FEC_1588_H ++ ++#include <linux/circ_buf.h> ++#include "fec.h" ++ ++#define fec_readl(addr) \ ++ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) ++ ++#define fec_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) ++ ++#define FALSE 0 ++#define TRUE 1 ++ ++/* FEC 1588 register bits */ ++#define FEC_T_CTRL_CAPTURE 0x00000800 ++#define FEC_T_CTRL_RESTART 0x00000200 ++#define FEC_T_CTRL_PERIOD_RST 0x00000010 ++#define FEC_T_CTRL_PINPER 0x00000080 ++#define FEC_T_CTRL_ENABLE 0x00000001 ++ ++#define FEC_T_INC_MASK 0x0000007f ++#define FEC_T_INC_OFFSET 0 ++#define FEC_T_INC_CORR_MASK 0x00007f00 ++#define FEC_T_INC_CORR_OFFSET 8 ++ ++#define FEC_T_INC_40MHZ 8 ++#define FEC_ATIME_40MHZ 125000000 ++ ++#define FEC_T_PERIOD_ONE_SEC 0x3B9ACA00 ++ ++/* IEEE 1588 definition */ ++#define FEC_ECNTRL_TS_EN 0x10 ++#define PTP_MAJOR 232 /*the temporary major number ++ *used by PTP driver, the major ++ *number 232~239 is unassigned*/ ++ ++#define DEFAULT_PTP_RX_BUF_SZ 2048 ++#define PTP_MSG_SYNC 0x0 ++#define PTP_MSG_DEL_REQ 0x1 ++#define PTP_MSG_P_DEL_REQ 0x2 ++#define PTP_MSG_P_DEL_RESP 0x3 ++#define PTP_MSG_DEL_RESP 0x4 ++#define PTP_MSG_ALL_OTHER 0x5 ++ ++#define PTP_GET_TX_TIMESTAMP 0x1 ++#define PTP_GET_RX_TIMESTAMP 0x9 ++#define PTP_SET_RTC_TIME 0x3 ++#define PTP_SET_COMPENSATION 0x4 ++#define PTP_GET_CURRENT_TIME 0x5 ++#define PTP_FLUSH_TIMESTAMP 0x6 ++#define PTP_ADJ_ADDEND 0x7 ++#define PTP_GET_ORIG_COMP 0x8 ++#define PTP_GET_ADDEND 0xB ++#define PTP_GET_RX_TIMESTAMP_PDELAY_REQ 0xC ++#define PTP_GET_RX_TIMESTAMP_PDELAY_RESP 0xD ++ ++#define FEC_PTP_DOMAIN_DLFT 0xe0000181 ++#define FEC_PTP_IP_OFFS 0x0 ++#define FEC_PTP_UDP_OFFS 0x14 ++#define FEC_PTP_MSG_TYPE_OFFS 0x1C ++#define FEC_PTP_SEQ_ID_OFFS 0x3A ++#define FEC_PTP_COR_NS 0x24 ++#define FEC_PTP_CTRL_OFFS 0x3C ++#define FEC_PACKET_TYPE_UDP 0x11 ++ ++#define FEC_PTP_ORIG_COMP 0x15555 ++ ++/* PTP standard time representation structure */ ++struct ptp_time { ++ u64 sec; /* seconds */ ++ u32 nsec; /* nanoseconds */ ++}; ++ ++/* Structure for PTP Time Stamp */ ++struct fec_ptp_data_t { ++ int key; ++ struct ptp_time ts_time; ++}; ++ ++/* interface for PTP driver command GET_TX_TIME */ ++struct ptp_ts_data { ++ /* PTP version */ ++ u8 version; ++ /* PTP source port ID */ ++ u8 spid[10]; ++ /* PTP sequence ID */ ++ u16 seq_id; ++ /* PTP message type */ ++ u8 message_type; ++ /* PTP timestamp */ ++ struct ptp_time ts; ++}; ++ ++/* interface for PTP driver command SET_RTC_TIME/GET_CURRENT_TIME */ ++struct ptp_rtc_time { ++ struct ptp_time rtc_time; ++}; ++ ++/* interface for PTP driver command SET_COMPENSATION */ ++struct ptp_set_comp { ++ u32 drift; ++ u32 o_ops; ++}; ++ ++/* interface for PTP driver command GET_ORIG_COMP */ ++struct ptp_get_comp { ++ /* the initial compensation value */ ++ u32 dw_origcomp; ++ /* the minimum compensation value */ ++ u32 dw_mincomp; ++ /*the max compensation value*/ ++ u32 dw_maxcomp; ++ /*the min drift applying min compensation value in ppm*/ ++ u32 dw_mindrift; ++ /*the max drift applying max compensation value in ppm*/ ++ u32 dw_maxdrift; ++}; ++ ++struct ptp_time_correct { ++ u32 corr_period; ++ u32 corr_inc; ++}; ++ ++/* PTP message version */ ++#define PTP_1588_MSG_VER_1 1 ++#define PTP_1588_MSG_VER_2 2 ++ ++struct fec_ptp_private { ++ void __iomem *hwp; ++ ++ struct circ_buf rx_time_sync; ++ struct circ_buf rx_time_del_req; ++ struct circ_buf rx_time_pdel_req; ++ struct circ_buf rx_time_pdel_resp; ++ spinlock_t ptp_lock; ++ spinlock_t cnt_lock; ++ ++ u64 prtc; ++ struct ptp_time txstamp; ++}; ++ ++#ifdef CONFIG_FEC_1588 ++extern int fec_ptp_init(struct fec_ptp_private *priv, int id); ++extern void fec_ptp_cleanup(struct fec_ptp_private *priv); ++extern int fec_ptp_start(struct fec_ptp_private *priv); ++extern void fec_ptp_stop(struct fec_ptp_private *priv); ++extern int fec_ptp_do_txstamp(struct sk_buff *skb); ++extern void fec_ptp_store_txstamp(struct fec_ptp_private *priv); ++extern void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, ++ struct sk_buff *skb, ++ struct bufdesc *bdp); ++#else ++static inline int fec_ptp_init(struct fec_ptp_private *priv, int id) ++{ ++ return 1; ++} ++static inline void fec_ptp_cleanup(struct fec_ptp_private *priv) { } ++static inline int fec_ptp_start(struct fec_ptp_private *priv) ++{ ++ return 1; ++} ++static inline void fec_ptp_stop(struct fec_ptp_private *priv) {} ++static inline int fec_ptp_do_txstamp(struct sk_buff *skb) ++{ ++ return 0; ++} ++static inline void fec_ptp_store_txstamp(struct fec_ptp_private *priv) {} ++static inline void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, ++ struct sk_buff *skb, ++ struct bufdesc *bdp) {} ++#endif /* 1588 */ ++ ++#endif diff --git a/target/linux/coldfire/patches/021-Add-ethernet-switch-driver-for-MCF54418.patch b/target/linux/coldfire/patches/021-Add-ethernet-switch-driver-for-MCF54418.patch new file mode 100644 index 000000000..e5bbc6973 --- /dev/null +++ b/target/linux/coldfire/patches/021-Add-ethernet-switch-driver-for-MCF54418.patch @@ -0,0 +1,6152 @@ +From 51e66f289f280a33bb17047717d2e6539a2917e1 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:44 +0800 +Subject: [PATCH 21/52] Add ethernet switch driver for MCF54418 + +Add ethernet switch driver support for MCF54418. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5441x/l2switch.c | 284 +++ + arch/m68k/include/asm/mcfswitch.h | 324 +++ + drivers/net/Kconfig | 8 + + drivers/net/Makefile | 1 + + drivers/net/modelo_switch.c | 4293 ++++++++++++++++++++++++++++++++++ + drivers/net/modelo_switch.h | 1141 +++++++++ + include/linux/fsl_devices.h | 17 + + net/core/dev.c | 8 + + 8 files changed, 6076 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m5441x/l2switch.c + create mode 100644 arch/m68k/include/asm/mcfswitch.h + create mode 100644 drivers/net/modelo_switch.c + create mode 100644 drivers/net/modelo_switch.h + +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/l2switch.c +@@ -0,0 +1,284 @@ ++/* ++ * l2switch.c ++ * ++ * Sub-architcture dependant initialization code for the Freescale ++ * 5441X L2 Switch module. ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ShrekWu B16972@freescale.com ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/param.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/device.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++ ++#include <asm/traps.h> ++#include <asm/machdep.h> ++#include <asm/coldfire.h> ++#include <asm/mcfswitch.h> ++#include <asm/mcfsim.h> ++ ++static unsigned char switch_mac_default[] = { ++ 0x00, 0x04, 0x9F, 0x00, 0xB3, 0x49, ++}; ++ ++static unsigned char switch_mac_addr[6]; ++ ++static void switch_request_intrs(struct net_device *dev, ++ irqreturn_t switch_net_irq_handler(int irq, void *private), ++ void *irq_privatedata) ++{ ++ struct switch_enet_private *fep; ++ int b; ++ static const struct idesc { ++ char *name; ++ unsigned short irq; ++ } *idp, id[] = { ++ /*{ "esw_isr(EBERR)", 38 },*/ ++ { "esw_isr(RxBuffer)", 39 }, ++ { "esw_isr(RxFrame)", 40 }, ++ { "esw_isr(TxBuffer)", 41 }, ++ { "esw_isr(TxFrame)", 42 }, ++ { "esw_isr(QM)", 43 }, ++ { "esw_isr(P0OutputDiscard)", 44 }, ++ { "esw_isr(P1OutputDiscard)", 45 }, ++ { "esw_isr(P2OutputDiscard)", 46 }, ++ { "esw_isr(LearningRecord)", 47 }, ++ { NULL }, ++ }; ++ ++ fep = netdev_priv(dev); ++ /*intrruption L2 ethernet SWITCH */ ++ b = 64 + 64 + 64; ++ ++ /* Setup interrupt handlers. */ ++ for (idp = id; idp->name; idp++) { ++ if (request_irq(b+idp->irq, ++ switch_net_irq_handler, IRQF_DISABLED, ++ idp->name, irq_privatedata) != 0) ++ printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n", ++ idp->name, b+idp->irq); ++ } ++ ++ /* Configure RMII */ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC_MASK) | ++ MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL; ++ ++ MCF_GPIO_PAR_FEC = ++ (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC_MASK) | ++ MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL; ++ ++ MCF_GPIO_SRCR_FEC = 0x0F; ++ ++ MCF_GPIO_PAR_SIMP0H = ++ (MCF_GPIO_PAR_SIMP0H & ++ MCF_GPIO_PAR_SIMP0H_DAT_MASK) | ++ MCF_GPIO_PAR_SIMP0H_DAT_GPIO; ++ ++ MCF_GPIO_PDDR_G = ++ (MCF_GPIO_PDDR_G & ++ MCF_GPIO_PDDR_G4_MASK) | ++ MCF_GPIO_PDDR_G4_OUTPUT; ++ ++ MCF_GPIO_PODR_G = ++ (MCF_GPIO_PODR_G & ++ MCF_GPIO_PODR_G4_MASK); ++} ++ ++static void switch_set_mii(struct net_device *dev) ++{ ++ struct switch_enet_private *fep = netdev_priv(dev); ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ MCF_FEC_RCR0 = (MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | ++ MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD); ++ MCF_FEC_RCR1 = (MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | ++ MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD); ++ /* TCR */ ++ MCF_FEC_TCR0 = MCF_FEC_TCR_FDEN; ++ MCF_FEC_TCR1 = MCF_FEC_TCR_FDEN; ++ /* ECR */ ++#ifdef MODELO_ENHANCE_BUFFER ++ MCF_FEC_ECR0 = MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588; ++ MCF_FEC_ECR1 = MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588; ++#else /*legac buffer*/ ++ MCF_FEC_ECR0 = MCF_FEC_ECR_ETHER_EN; ++ MCF_FEC_ECR1 = MCF_FEC_ECR_ETHER_EN; ++#endif ++ /* ++ * Set MII speed to 2.5 MHz ++ */ ++ MCF_FEC_MSCR0 = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; ++ MCF_FEC_MSCR1 = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; ++ ++} ++ ++static void switch_get_mac(struct net_device *dev) ++{ ++ struct switch_enet_private *fep = netdev_priv(dev); ++ volatile switch_t *fecp; ++ unsigned char *iap; ++ ++ fecp = fep->hwp; ++ ++ if (FEC_FLASHMAC) { ++ /* ++ * Get MAC address from FLASH. ++ * If it is all 1's or 0's, use the default. ++ */ ++ iap = FEC_FLASHMAC; ++ if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && ++ (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) ++ iap = switch_mac_default; ++ if ((iap[0] == 0xff) && (iap[1] == 0xff) && ++ (iap[2] == 0xff) && (iap[3] == 0xff) && ++ (iap[4] == 0xff) && (iap[5] == 0xff)) ++ iap = switch_mac_default; ++ ++ } else { ++ iap = &switch_mac_addr[0]; ++ ++ if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && ++ (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) ++ iap = switch_mac_default; ++ if ((iap[0] == 0xff) && (iap[1] == 0xff) && ++ (iap[2] == 0xff) && (iap[3] == 0xff) && ++ (iap[4] == 0xff) && (iap[5] == 0xff)) ++ iap = switch_mac_default; ++ } ++ ++ memcpy(dev->dev_addr, iap, ETH_ALEN); ++ /* Adjust MAC if using default MAC address */ ++ if (iap == switch_mac_default) ++ dev->dev_addr[ETH_ALEN-1] = switch_mac_default[ETH_ALEN-1] + ++ fep->index; ++} ++ ++static void switch_enable_phy_intr(void) ++{ ++} ++ ++static void switch_disable_phy_intr(void) ++{ ++} ++ ++static void switch_phy_ack_intr(void) ++{ ++} ++ ++static void switch_localhw_setup(void) ++{ ++} ++ ++static void switch_uncache(unsigned long addr) ++{ ++} ++ ++static void switch_platform_flush_cache(void) ++{ ++} ++ ++/* ++ * Define the fixed address of the FEC hardware. ++ */ ++static unsigned int switch_platform_hw[] = { ++ (0xfc0dc000), ++ (0xfc0e000), ++}; ++ ++static struct coldfire_switch_platform_data mcf5441x_switch_data = { ++ .hash_table = 0, ++ .switch_hw = switch_platform_hw, ++ .request_intrs = switch_request_intrs, ++ .set_mii = switch_set_mii, ++ .get_mac = switch_get_mac, ++ .enable_phy_intr = switch_enable_phy_intr, ++ .disable_phy_intr = switch_disable_phy_intr, ++ .phy_ack_intr = switch_phy_ack_intr, ++ .localhw_setup = switch_localhw_setup, ++ .uncache = switch_uncache, ++ .platform_flush_cache = switch_platform_flush_cache, ++}; ++ ++static struct resource l2switch_coldfire_resources[] = { ++ [0] = { ++ .start = 0xFC0DC000, ++ .end = 0xFC0DC508, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = (64 + 64 + 64 + 38), ++ .end = (64 + 64 + 64 + 48), ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = 0xFC0E0000, ++ .end = 0xFC0E3FFC, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device l2switch_coldfire_device = { ++ .name = "coldfire-switch", ++ .id = 0, ++ .resource = l2switch_coldfire_resources, ++ .num_resources = ARRAY_SIZE(l2switch_coldfire_resources), ++ .dev = { ++ .platform_data = &mcf5441x_switch_data, ++ .coherent_dma_mask = ~0, /* $$$ REVISIT */ ++ } ++}; ++ ++ ++static int __init mcf5441x_switch_dev_init(void) ++{ ++ int retval = 0; ++ ++ retval = platform_device_register(&l2switch_coldfire_device); ++ ++ if (retval < 0) { ++ printk(KERN_ERR "MCF5441x L2Switch: platform_device_register" ++ " failed with code=%d\n", retval); ++ } ++ ++ return retval; ++} ++ ++static int __init param_switch_addr_setup(char *str) ++{ ++ char *end; ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ switch_mac_addr[i] = str ? simple_strtoul(str, &end, 16) : 0; ++ if (str) ++ str = (*end) ? end + 1 : end; ++ } ++ return 0; ++} ++__setup("switchaddr=", param_switch_addr_setup); ++ ++arch_initcall(mcf5441x_switch_dev_init); +--- /dev/null ++++ b/arch/m68k/include/asm/mcfswitch.h +@@ -0,0 +1,324 @@ ++/****************************************************************************/ ++ ++/* ++ * mcfswitch -- L2 SWITCH Controller for Motorola ColdFire SoC ++ * processors. ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/****************************************************************************/ ++#ifndef SWITCH_H ++#define SWITCH_H ++/****************************************************************************/ ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/spinlock.h> ++#include <linux/workqueue.h> ++#include <linux/platform_device.h> ++#include <asm/pgtable.h> ++ ++#define FEC_FLASHMAC 0 ++#define SWITCH_EPORT_NUMBER 2 ++ ++#ifdef CONFIG_SWITCH_DMA_USE_SRAM ++#define TX_RING_SIZE 8 /* Must be power of two */ ++#define TX_RING_MOD_MASK 7 /* for this to work */ ++#else ++#define TX_RING_SIZE 16 /* Must be power of two */ ++#define TX_RING_MOD_MASK 15 /* for this to work */ ++#endif ++ ++typedef struct l2switch_port_statistics_status { ++ /*outgoing frames discarded due to transmit queue congestion*/ ++ unsigned long MCF_ESW_POQC; ++ /*incoming frames discarded due to VLAN domain mismatch*/ ++ unsigned long MCF_ESW_PMVID; ++ /*incoming frames discarded due to untagged discard*/ ++ unsigned long MCF_ESW_PMVTAG; ++ /*incoming frames discarded due port is in blocking state*/ ++ unsigned long MCF_ESW_PBL; ++} esw_port_statistics_status; ++ ++typedef struct l2switch { ++ unsigned long ESW_REVISION; ++ unsigned long ESW_SCRATCH; ++ unsigned long ESW_PER; ++ unsigned long reserved0[1]; ++ unsigned long ESW_VLANV; ++ unsigned long ESW_DBCR; ++ unsigned long ESW_DMCR; ++ unsigned long ESW_BKLR; ++ unsigned long ESW_BMPC; ++ unsigned long ESW_MODE; ++ unsigned long ESW_VIMSEL; ++ unsigned long ESW_VOMSEL; ++ unsigned long ESW_VIMEN; ++ unsigned long ESW_VID;/*0x34*/ ++ /*from 0x38 0x3C*/ ++ unsigned long esw_reserved0[2]; ++ unsigned long ESW_MCR;/*0x40*/ ++ unsigned long ESW_EGMAP; ++ unsigned long ESW_INGMAP; ++ unsigned long ESW_INGSAL; ++ unsigned long ESW_INGSAH; ++ unsigned long ESW_INGDAL; ++ unsigned long ESW_INGDAH; ++ unsigned long ESW_ENGSAL; ++ unsigned long ESW_ENGSAH; ++ unsigned long ESW_ENGDAL; ++ unsigned long ESW_ENGDAH; ++ unsigned long ESW_MCVAL;/*0x6C*/ ++ /*from 0x70--0x7C*/ ++ unsigned long esw_reserved1[4]; ++ unsigned long ESW_MMSR;/*0x80*/ ++ unsigned long ESW_LMT; ++ unsigned long ESW_LFC; ++ unsigned long ESW_PCSR; ++ unsigned long ESW_IOSR; ++ unsigned long ESW_QWT;/*0x94*/ ++ unsigned long esw_reserved2[1];/*0x98*/ ++ unsigned long ESW_P0BCT;/*0x9C*/ ++ /*from 0xA0-0xB8*/ ++ unsigned long esw_reserved3[7]; ++ unsigned long ESW_P0FFEN;/*0xBC*/ ++ unsigned long ESW_PSNP[8]; ++ unsigned long ESW_IPSNP[8]; ++ unsigned long ESW_PVRES[3]; ++ /*from 0x10C-0x13C*/ ++ unsigned long esw_reserved4[13]; ++ unsigned long ESW_IPRES;/*0x140*/ ++ /*from 0x144-0x17C*/ ++ unsigned long esw_reserved5[15]; ++ ++ /*port0-port2 Priority Configuration 0xFC0D_C180-C188*/ ++ unsigned long ESW_PRES[3]; ++ /*from 0x18C-0x1FC*/ ++ unsigned long esw_reserved6[29]; ++ ++ /*port0-port2 VLAN ID 0xFC0D_C200-C208*/ ++ unsigned long ESW_PID[3]; ++ /*from 0x20C-0x27C*/ ++ unsigned long esw_reserved7[29]; ++ ++ /*port0-port2 VLAN domain resolution entry 0xFC0D_C280-C2FC*/ ++ unsigned long ESW_VRES[32]; ++ ++ unsigned long ESW_DISCN;/*0x300*/ ++ unsigned long ESW_DISCB; ++ unsigned long ESW_NDISCN; ++ unsigned long ESW_NDISCB;/*0xFC0DC30C*/ ++ /*per port statistics 0xFC0DC310_C33C*/ ++ esw_port_statistics_status port_statistics_status[3]; ++ /*from 0x340-0x400*/ ++ unsigned long esw_reserved8[48]; ++ ++ /*0xFC0DC400---0xFC0DC418*/ ++ /*unsigned long MCF_ESW_ISR;*/ ++ unsigned long switch_ievent; /* Interrupt event reg */ ++ /*unsigned long MCF_ESW_IMR;*/ ++ unsigned long switch_imask; /* Interrupt mask reg */ ++ /*unsigned long MCF_ESW_RDSR;*/ ++ unsigned long fec_r_des_start; /* Receive descriptor ring */ ++ /*unsigned long MCF_ESW_TDSR;*/ ++ unsigned long fec_x_des_start; /* Transmit descriptor ring */ ++ /*unsigned long MCF_ESW_MRBR;*/ ++ unsigned long fec_r_buff_size; /* Maximum receive buff size */ ++ /*unsigned long MCF_ESW_RDAR;*/ ++ unsigned long fec_r_des_active; /* Receive descriptor reg */ ++ /*unsigned long MCF_ESW_TDAR;*/ ++ unsigned long fec_x_des_active; /* Transmit descriptor reg */ ++ /*from 0x420-0x4FC*/ ++ unsigned long esw_reserved9[57]; ++ ++ /*0xFC0DC500---0xFC0DC508*/ ++ unsigned long ESW_LREC0; ++ unsigned long ESW_LREC1; ++ unsigned long ESW_LSR; ++} switch_t; ++ ++typedef struct _64bTableEntry { ++ unsigned int lo; /* lower 32 bits */ ++ unsigned int hi; /* upper 32 bits */ ++} AddrTable64bEntry; ++ ++typedef struct l2switchaddrtable { ++ AddrTable64bEntry eswTable64bEntry[2048]; ++} eswAddrTable_t; ++ ++#define MCF_FEC_MSCR0 (*(volatile unsigned long *)(0xFC0D4044)) ++#define MCF_FEC_MSCR1 (*(volatile unsigned long *)(0xFC0D8044)) ++#define MCF_FEC_RCR0 (*(volatile unsigned long *)(0xFC0D4084)) ++#define MCF_FEC_RCR1 (*(volatile unsigned long *)(0xFC0D8084)) ++#define MCF_FEC_TCR0 (*(volatile unsigned long *)(0xFC0D40C4)) ++#define MCF_FEC_TCR1 (*(volatile unsigned long *)(0xFC0D80C4)) ++#define MCF_FEC_ECR0 (*(volatile unsigned long *)(0xFC0D4024)) ++#define MCF_FEC_ECR1 (*(volatile unsigned long *)(0xFC0D8024)) ++ ++#define MCF_FEC_RCR_PROM (0x00000008) ++#define MCF_FEC_RCR_RMII_MODE (0x00000100) ++#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x00003FFF)<<16) ++#define MCF_FEC_RCR_CRC_FWD (0x00004000) ++ ++#define MCF_FEC_TCR_FDEN (0x00000004) ++ ++#define MCF_FEC_ECR_ETHER_EN (0x00000002) ++#define MCF_FEC_ECR_ENA_1588 (0x00000010) ++ ++ ++typedef struct bufdesc { ++ unsigned short cbd_sc; /* Control and status info */ ++ unsigned short cbd_datlen; /* Data length */ ++ unsigned long cbd_bufaddr; /* Buffer address */ ++#ifdef MODELO_BUFFER ++ unsigned long ebd_status; ++ unsigned short length_proto_type; ++ unsigned short payload_checksum; ++ unsigned long bdu; ++ unsigned long timestamp; ++ unsigned long reserverd_word1; ++ unsigned long reserverd_word2; ++#endif ++} cbd_t; ++ ++/* Forward declarations of some structures to support different PHYs ++ */ ++typedef struct { ++ uint mii_data; ++ void (*funct)(uint mii_reg, struct net_device *dev); ++} phy_cmd_t; ++ ++typedef struct { ++ uint id; ++ char *name; ++ ++ const phy_cmd_t *config; ++ const phy_cmd_t *startup; ++ const phy_cmd_t *ack_int; ++ const phy_cmd_t *shutdown; ++} phy_info_t; ++ ++/* The switch buffer descriptors track the ring buffers. The rx_bd_base and ++ * tx_bd_base always point to the base of the buffer descriptors. The ++ * cur_rx and cur_tx point to the currently available buffer. ++ * The dirty_tx tracks the current buffer that is being sent by the ++ * controller. The cur_tx and dirty_tx are equal under both completely ++ * empty and completely full conditions. The empty/ready indicator in ++ * the buffer descriptor determines the actual condition. ++ */ ++struct switch_enet_private { ++ /* Hardware registers of the switch device */ ++ volatile switch_t *hwp; ++ volatile eswAddrTable_t *hwentry; ++ ++ struct net_device *netdev; ++ struct platform_device *pdev; ++ /* The saved address of a sent-in-place packet/buffer, for skfree(). */ ++ unsigned char *tx_bounce[TX_RING_SIZE]; ++ struct sk_buff *tx_skbuff[TX_RING_SIZE]; ++ ushort skb_cur; ++ ushort skb_dirty; ++ ++ /* CPM dual port RAM relative addresses. ++ */ ++ cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ ++ cbd_t *tx_bd_base; ++ cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ ++ cbd_t *dirty_tx; /* The ring entries to be free()ed. */ ++ uint tx_full; ++ /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ ++ spinlock_t hw_lock; ++ ++ /* hold while accessing the mii_list_t() elements */ ++ spinlock_t mii_lock; ++ struct mii_bus *mdio_bus; ++ struct phy_device *phydev[SWITCH_EPORT_NUMBER]; ++ ++ uint phy_id; ++ uint phy_id_done; ++ uint phy_status; ++ uint phy_speed; ++ phy_info_t const *phy; ++ struct work_struct phy_task; ++ volatile switch_t *phy_hwp; ++ ++ uint sequence_done; ++ uint mii_phy_task_queued; ++ ++ uint phy_addr; ++ ++ int index; ++ int opened; ++ int full_duplex; ++ int msg_enable; ++ int phy1_link; ++ int phy1_old_link; ++ int phy1_duplex; ++ int phy1_speed; ++ ++ int phy2_link; ++ int phy2_old_link; ++ int phy2_duplex; ++ int phy2_speed; ++ /* --------------Statistics--------------------------- */ ++ /* when a new element deleted a element with in ++ * a block due to lack of space */ ++ int atBlockOverflows; ++ /* Peak number of valid entries in the address table */ ++ int atMaxEntries; ++ /* current number of valid entries in the address table */ ++ int atCurrEntries; ++ /* maximum entries within a block found ++ * (updated within ageing)*/ ++ int atMaxEntriesPerBlock; ++ ++ /* -------------------ageing function------------------ */ ++ /* maximum age allowed for an entry */ ++ int ageMax; ++ /* last LUT entry to block that was ++ * inspected by the Ageing task*/ ++ int ageLutIdx; ++ /* last element within block inspected by the Ageing task */ ++ int ageBlockElemIdx; ++ /* complete table has been processed by ageing process */ ++ int ageCompleted; ++ /* delay setting */ ++ int ageDelay; ++ /* current delay Counter */ ++ int ageDelayCnt; ++ ++ /* ----------------timer related---------------------------- */ ++ /* current time (for timestamping) */ ++ int currTime; ++ /* flag set by timer when currTime changed ++ * and cleared by serving function*/ ++ int timeChanged; ++ ++ /* Timer for Aging */ ++ struct timer_list timer_aging; ++ int learning_irqhandle_enable; ++}; ++ ++struct switch_platform_private { ++ struct platform_device *pdev; ++ ++ unsigned long quirks; ++ int num_slots; /* Slots on controller */ ++ struct switch_enet_private *fep_host[0]; /* Pointers to hosts */ ++}; ++#endif +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -1950,6 +1950,14 @@ config FEC + Say Y here if you want to use the built-in 10/100 Fast ethernet + controller on some Motorola ColdFire and Freescale i.MX processors. + ++config MODELO_SWITCH ++ bool "ethernet switch controller (of ColdFire CPUs)" ++ depends on !FEC && M5441X ++ help ++ Say Y here if you want to use the built-in ethernet switch ++ controller on some ColdFire processors. ++ The Integrated Ethernet switch engine is compatible with ++ 10/100 MAC-NET core. + + config FEC2 + bool "Second FEC ethernet controller (on some ColdFire CPUs)" +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -127,6 +127,7 @@ ifeq ($(CONFIG_FEC_1588), y) + obj-$(CONFIG_FEC) += fec_1588.o + endif + obj-$(CONFIG_FEC_548x) += fec_m547x.o ++obj-$(CONFIG_MODELO_SWITCH) += modelo_switch.o + obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o + ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y) + obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o +--- /dev/null ++++ b/drivers/net/modelo_switch.c +@@ -0,0 +1,4293 @@ ++/* ++ * L2 switch Controller (Etheren switch) driver for MCF5441x. ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Shrek Wu (B16972@freescale.com) ++ * Alison Wang (b18965@freescale.com) ++ * Jason Jin (Jason.jin@freescale.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/string.h> ++#include <linux/ptrace.h> ++#include <linux/errno.h> ++#include <linux/ioport.h> ++#include <linux/slab.h> ++#include <linux/interrupt.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/spinlock.h> ++#include <linux/workqueue.h> ++#include <linux/bitops.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/phy.h> ++#include <linux/kthread.h> ++#include <linux/syscalls.h> ++#include <linux/uaccess.h> ++#include <linux/io.h> ++#include <linux/signal.h> ++ ++#include <asm/irq.h> ++#include <asm/pgtable.h> ++#include <asm/cacheflush.h> ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include "modelo_switch.h" ++ ++#define SWITCH_MAX_PORTS 1 ++#define CONFIG_FEC_SHARED_PHY ++ ++/* Interrupt events/masks. ++*/ ++#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ ++#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ ++#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ ++#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ ++#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ ++#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ ++#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ ++#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ ++#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ ++#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ ++ ++static int switch_enet_open(struct net_device *dev); ++static int switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); ++static irqreturn_t switch_enet_interrupt(int irq, void *dev_id); ++static void switch_enet_tx(struct net_device *dev); ++static void switch_enet_rx(struct net_device *dev); ++static int switch_enet_close(struct net_device *dev); ++static void set_multicast_list(struct net_device *dev); ++static void switch_restart(struct net_device *dev, int duplex); ++static void switch_stop(struct net_device *dev); ++static void switch_set_mac_address(struct net_device *dev); ++ ++#define NMII 20 ++ ++/* Make MII read/write commands for the FEC. ++*/ ++#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) ++#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ ++ (VAL & 0xffff)) ++ ++/* Transmitter timeout. ++*/ ++#define TX_TIMEOUT (2*HZ) ++ ++/*last read entry from learning interface*/ ++eswPortInfo g_info; ++/* switch ports status */ ++struct port_status ports_link_status; ++ ++/* the user space pid, used to send the link change to user space */ ++long user_pid = 1; ++ ++/* ----------------------------------------------------------------*/ ++/* ++ * Calculate Galois Field Arithmetic CRC for Polynom x^8+x^2+x+1. ++ * It omits the final shift in of 8 zeroes a "normal" CRC would do ++ * (getting the remainder). ++ * ++ * Examples (hexadecimal values):<br> ++ * 10-11-12-13-14-15 => CRC=0xc2 ++ * 10-11-cc-dd-ee-00 => CRC=0xe6 ++ * ++ * param: pmacaddress ++ * A 6-byte array with the MAC address. ++ * The first byte is the first byte transmitted ++ * return The 8-bit CRC in bits 7:0 ++ */ ++int crc8_calc(unsigned char *pmacaddress) ++{ ++ /* byte index */ ++ int byt; ++ /* bit index */ ++ int bit; ++ int inval; ++ int crc; ++ /* preset */ ++ crc = 0x12; ++ for (byt = 0; byt < 6; byt++) { ++ inval = (((int)pmacaddress[byt]) & 0xff); ++ /* ++ * shift bit 0 to bit 8 so all our bits ++ * travel through bit 8 ++ * (simplifies below calc) ++ */ ++ inval <<= 8; ++ ++ for (bit = 0; bit < 8; bit++) { ++ /* next input bit comes into d7 after shift */ ++ crc |= inval & 0x100; ++ if (crc & 0x01) ++ /* before shift */ ++ crc ^= 0x1c0; ++ ++ crc >>= 1; ++ inval >>= 1; ++ } ++ ++ } ++ /* upper bits are clean as we shifted in zeroes! */ ++ return crc; ++} ++ ++void read_atable(struct switch_enet_private *fep, ++ int index, unsigned long *read_lo, unsigned long *read_hi) ++{ ++ unsigned long atable_base = 0xFC0E0000; ++ ++ *read_lo = *((volatile unsigned long *)(atable_base + (index<<3))); ++ *read_hi = *((volatile unsigned long *)(atable_base + (index<<3) + 4)); ++} ++ ++void write_atable(struct switch_enet_private *fep, ++ int index, unsigned long write_lo, unsigned long write_hi) ++{ ++ unsigned long atable_base = 0xFC0E0000; ++ ++ *((volatile unsigned long *)(atable_base + (index<<3))) = write_lo; ++ *((volatile unsigned long *)(atable_base + (index<<3) + 4)) = write_hi; ++} ++ ++/* Check if the Port Info FIFO has data available ++ * for reading. 1 valid, 0 invalid*/ ++int esw_portinfofifo_status(struct switch_enet_private *fep) ++{ ++ volatile switch_t *fecp; ++ fecp = fep->hwp; ++ return fecp->ESW_LSR; ++} ++ ++/* Initialize the Port Info FIFO. */ ++void esw_portinfofifo_initialize(struct switch_enet_private *fep) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp; ++ fecp = fep->hwp; ++ ++ /*disable all learn*/ ++ fecp->switch_imask &= (~MCF_ESW_IMR_LRN); ++ /* remove all entries from FIFO */ ++ while (esw_portinfofifo_status(fep)) { ++ /* read one data word */ ++ tmp = fecp->ESW_LREC0; ++ tmp = fecp->ESW_LREC1; ++ } ++ ++} ++ ++/* Read one element from the HW receive FIFO (Queue) ++ * if available and return it. ++ * return ms_HwPortInfo or null if no data is available ++ */ ++eswPortInfo *esw_portinfofifo_read(struct switch_enet_private *fep) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp; ++ ++ fecp = fep->hwp; ++ /* check learning record valid */ ++ if (fecp->ESW_LSR == 0) ++ return NULL; ++ ++ /*read word from FIFO*/ ++ g_info.maclo = fecp->ESW_LREC0; ++ ++ /*but verify that we actually did so ++ * (0=no data available)*/ ++ if (g_info.maclo == 0) ++ return NULL; ++ ++ /* read 2nd word from FIFO */ ++ tmp = fecp->ESW_LREC1; ++ g_info.machi = tmp & 0xffff; ++ g_info.hash = (tmp >> 16) & 0xff; ++ g_info.port = (tmp >> 24) & 0xf; ++ ++ return &g_info; ++} ++ ++/* ++ * Clear complete MAC Look Up Table ++ */ ++void esw_clear_atable(struct switch_enet_private *fep) ++{ ++ int index; ++ for (index = 0; index < 2048; index++) ++ write_atable(fep, index, 0, 0); ++} ++ ++void esw_dump_atable(struct switch_enet_private *fep) ++{ ++ int index; ++ unsigned long read_lo, read_hi; ++ for (index = 0; index < 2048; index++) ++ read_atable(fep, index, &read_lo, &read_hi); ++} ++ ++/* ++ * pdates MAC address lookup table with a static entry ++ * Searches if the MAC address is already there in the block and replaces ++ * the older entry with new one. If MAC address is not there then puts a ++ * new entry in the first empty slot available in the block ++ * ++ * mac_addr Pointer to the array containing MAC address to ++ * be put as static entry ++ * port Port bitmask numbers to be added in static entry, ++ * valid values are 1-7 ++ * priority Priority for the static entry in table ++ * ++ * return 0 for a successful update else -1 when no slot available ++ */ ++int esw_update_atable_static(unsigned char *mac_addr, ++ unsigned int port, unsigned int priority, ++ struct switch_enet_private *fep) ++{ ++ unsigned long block_index, entry, index_end; ++ unsigned long read_lo, read_hi; ++ unsigned long write_lo, write_hi; ++ ++ write_lo = (unsigned long)((mac_addr[3] << 24) | ++ (mac_addr[2] << 16) | ++ (mac_addr[1] << 8) | ++ mac_addr[0]); ++ write_hi = (unsigned long)(0 | ++ (port << AT_SENTRY_PORTMASK_shift) | ++ (priority << AT_SENTRY_PRIO_shift) | ++ (AT_ENTRY_TYPE_STATIC << AT_ENTRY_TYPE_shift) | ++ (AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift) | ++ (mac_addr[5] << 8) | (mac_addr[4])); ++ ++ block_index = GET_BLOCK_PTR(crc8_calc(mac_addr)); ++ index_end = block_index + ATABLE_ENTRY_PER_SLOT; ++ /* Now search all the entries in the selected block */ ++ for (entry = block_index; entry < index_end; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ /* ++ * MAC address matched, so update the ++ * existing entry ++ * even if its a dynamic one ++ */ ++ if ((read_lo == write_lo) && ((read_hi & 0x0000ffff) == ++ (write_hi & 0x0000ffff))) { ++ write_atable(fep, entry, write_lo, write_hi); ++ return 0; ++ } else if (!(read_hi & (1 << 16))) { ++ /* ++ * Fill this empty slot (valid bit zero), ++ * assuming no holes in the block ++ */ ++ write_atable(fep, entry, write_lo, write_hi); ++ fep->atCurrEntries++; ++ return 0; ++ } ++ } ++ ++ /* No space available for this static entry */ ++ return -1; ++} ++ ++/* lookup entry in given Address Table slot and ++ * insert (learn) it if it is not found. ++ * return 0 if entry was found and updated. ++ * 1 if entry was not found and has been inserted (learned). ++ */ ++int esw_update_atable_dynamic(unsigned char *mac_addr, unsigned int port, ++ unsigned int currTime, struct switch_enet_private *fep) ++{ ++ unsigned long block_index, entry, index_end; ++ unsigned long read_lo, read_hi; ++ unsigned long write_lo, write_hi; ++ unsigned long tmp; ++ int time, timeold, indexold; ++ ++ /* prepare update port and timestamp */ ++ write_hi = (mac_addr[5] << 8) | (mac_addr[4]); ++ write_lo = (unsigned long)((mac_addr[3] << 24) | ++ (mac_addr[2] << 16) | ++ (mac_addr[1] << 8) | ++ mac_addr[0]); ++ tmp = AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift; ++ tmp |= AT_ENTRY_TYPE_DYNAMIC << AT_ENTRY_TYPE_shift; ++ tmp |= currTime << AT_DENTRY_TIME_shift; ++ tmp |= port << AT_DENTRY_PORT_shift; ++ tmp |= write_hi; ++ ++ /* ++ * linear search through all slot ++ * entries and update if found ++ */ ++ block_index = GET_BLOCK_PTR(crc8_calc(mac_addr)); ++ index_end = block_index + ATABLE_ENTRY_PER_SLOT; ++ /* Now search all the entries in the selected block */ ++ for (entry = block_index; entry < index_end; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ ++ if ((read_lo == write_lo) && ++ ((read_hi & 0x0000ffff) == ++ (write_hi & 0x0000ffff))) { ++ /* found correct address, ++ * update timestamp. */ ++ write_atable(fep, entry, write_lo, tmp); ++ return 0; ++ } else if (!(read_hi & (1 << 16))) { ++ /* slot is empty, then use it ++ * for new entry ++ * Note: There are no holes, ++ * therefore cannot be any ++ * more that need to be compared. ++ */ ++ write_atable(fep, entry, write_lo, tmp); ++ /* statistics (we do it between writing ++ * .hi an .lo due to ++ * hardware limitation... ++ */ ++ fep->atCurrEntries++; ++ /* newly inserted */ ++ return 1; ++ } ++ } ++ ++ /* ++ * no more entry available in blockk ... ++ * overwrite oldest ++ */ ++ timeold = 0; ++ indexold = 0; ++ for (entry = block_index; entry < index_end; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ time = AT_EXTRACT_TIMESTAMP(read_hi); ++ time = TIMEDELTA(currTime, time); ++ if (time > timeold) { ++ /* is it older ?*/ ++ timeold = time; ++ indexold = entry; ++ } ++ } ++ ++ write_atable(fep, indexold, write_lo, tmp); ++ /* Statistics (do it inbetween ++ * writing to .lo and .hi*/ ++ fep->atBlockOverflows++; ++ /* newly inserted */ ++ return 1; ++} ++ ++int esw_update_atable_dynamic1(unsigned long write_lo, unsigned long write_hi, ++ int block_index, unsigned int port, unsigned int currTime, ++ struct switch_enet_private *fep) ++{ ++ unsigned long entry, index_end; ++ unsigned long read_lo, read_hi; ++ unsigned long tmp; ++ int time, timeold, indexold; ++ ++ /* prepare update port and timestamp */ ++ tmp = AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift; ++ tmp |= AT_ENTRY_TYPE_DYNAMIC << AT_ENTRY_TYPE_shift; ++ tmp |= currTime << AT_DENTRY_TIME_shift; ++ tmp |= port << AT_DENTRY_PORT_shift; ++ tmp |= write_hi; ++ ++ /* ++ * linear search through all slot ++ * entries and update if found ++ */ ++ index_end = block_index + ATABLE_ENTRY_PER_SLOT; ++ /* Now search all the entries in the selected block */ ++ for (entry = block_index; entry < index_end; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ if ((read_lo == write_lo) && ++ ((read_hi & 0x0000ffff) == ++ (write_hi & 0x0000ffff))) { ++ /* found correct address, ++ * update timestamp. */ ++ write_atable(fep, entry, write_lo, tmp); ++ return 0; ++ } else if (!(read_hi & (1 << 16))) { ++ /* slot is empty, then use it ++ * for new entry ++ * Note: There are no holes, ++ * therefore cannot be any ++ * more that need to be compared. ++ */ ++ write_atable(fep, entry, write_lo, tmp); ++ /* statistics (we do it between writing ++ * .hi an .lo due to ++ * hardware limitation... ++ */ ++ fep->atCurrEntries++; ++ /* newly inserted */ ++ return 1; ++ } ++ } ++ ++ /* ++ * no more entry available in block ... ++ * overwrite oldest ++ */ ++ timeold = 0; ++ indexold = 0; ++ for (entry = block_index; entry < index_end; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ time = AT_EXTRACT_TIMESTAMP(read_hi); ++ time = TIMEDELTA(currTime, time); ++ if (time > timeold) { ++ /* is it older ?*/ ++ timeold = time; ++ indexold = entry; ++ } ++ } ++ ++ write_atable(fep, indexold, write_lo, tmp); ++ /* Statistics (do it inbetween ++ * writing to .lo and .hi*/ ++ fep->atBlockOverflows++; ++ /* newly inserted */ ++ return 1; ++} ++ ++/* ++ * Delete one dynamic entry within the given block ++ * of 64-bit entries. ++ * return number of valid entries in the block after deletion. ++ */ ++int esw_del_atable_dynamic(struct switch_enet_private *fep, ++ int blockidx, int entryidx) ++{ ++ unsigned long index_start, index_end; ++ int i; ++ unsigned long read_lo, read_hi; ++ ++ /* the entry to delete */ ++ index_start = blockidx + entryidx; ++ /* one after last */ ++ index_end = blockidx + ATABLE_ENTRY_PER_SLOT; ++ /* Statistics */ ++ fep->atCurrEntries--; ++ ++ if (entryidx == (ATABLE_ENTRY_PER_SLOT - 1)) { ++ /* if it is the very last entry, ++ * just delete it without further efford*/ ++ write_atable(fep, index_start, 0, 0); ++ /*number of entries left*/ ++ i = ATABLE_ENTRY_PER_SLOT - 1; ++ return i; ++ } else { ++ /*not the last in the block, then ++ * shift all that follow the one ++ * that is deleted to avoid "holes". ++ */ ++ for (i = index_start; i < (index_end - 1); i++) { ++ read_atable(fep, i + 1, &read_lo, &read_hi); ++ /* move it down */ ++ write_atable(fep, i, read_lo, read_hi); ++ if (!(read_hi & (1 << 16))) { ++ /* stop if we just copied the last */ ++ return i - blockidx; ++ } ++ } ++ ++ /*moved all entries up to the last. ++ * then set invalid flag in the last*/ ++ write_atable(fep, index_end - 1, 0, 0); ++ /* number of valid entries left */ ++ return i - blockidx; ++ } ++} ++ ++void esw_atable_dynamicms_del_entries_for_port( ++ struct switch_enet_private *fep, int port_index) ++{ ++ unsigned long read_lo, read_hi; ++ unsigned int port_idx; ++ int i; ++ ++ for (i = 0; i < ESW_ATABLE_MEM_NUM_ENTRIES; i++) { ++ read_atable(fep, i, &read_lo, &read_hi); ++ if (read_hi & (1 << 16)) { ++ port_idx = AT_EXTRACT_PORT(read_hi); ++ ++ if (port_idx == port_index) ++ write_atable(fep, i, 0, 0); ++ } ++ } ++} ++ ++void esw_atable_dynamicms_del_entries_for_other_port( ++ struct switch_enet_private *fep, ++ int port_index) ++{ ++ unsigned long read_lo, read_hi; ++ unsigned int port_idx; ++ int i; ++ ++ for (i = 0; i < ESW_ATABLE_MEM_NUM_ENTRIES; i++) { ++ read_atable(fep, i, &read_lo, &read_hi); ++ if (read_hi & (1 << 16)) { ++ port_idx = AT_EXTRACT_PORT(read_hi); ++ ++ if (port_idx != port_index) ++ write_atable(fep, i, 0, 0); ++ } ++ } ++} ++ ++/* ++ * Scan one complete block (Slot) for outdated entries and delete them. ++ * blockidx index of block of entries that should be analyzed. ++ * return number of deleted entries, 0 if nothing was modified. ++ */ ++int esw_atable_dynamicms_check_block_age( ++ struct switch_enet_private *fep, int blockidx) { ++ ++ int i, tm, tdelta; ++ int deleted = 0, entries = 0; ++ unsigned long read_lo, read_hi; ++ /* Scan all entries from last down to ++ * have faster deletion speed if necessary*/ ++ for (i = (blockidx + ATABLE_ENTRY_PER_SLOT - 1); ++ i >= blockidx; i--) { ++ read_atable(fep, i, &read_lo, &read_hi); ++ ++ if (read_hi & (1 << 16)) { ++ /* the entry is valide*/ ++ tm = AT_EXTRACT_TIMESTAMP(read_hi); ++ tdelta = TIMEDELTA(fep->currTime, tm); ++ if (tdelta > fep->ageMax) { ++ esw_del_atable_dynamic(fep, ++ blockidx, i-blockidx); ++ deleted++; ++ } else { ++ /* statistics */ ++ entries++; ++ } ++ } ++ } ++ ++ /*update statistics*/ ++ if (fep->atMaxEntriesPerBlock < entries) ++ fep->atMaxEntriesPerBlock = entries; ++ ++ return deleted; ++} ++ ++/* scan the complete address table and find the most current entry. ++ * The time of the most current entry then is used as current time ++ * for the context structure. ++ * In addition the atCurrEntries value is updated as well. ++ * return time that has been set in the context. ++ */ ++int esw_atable_dynamicms_find_set_latesttime( ++ struct switch_enet_private *fep) { ++ ++ int tm_min, tm_max, tm; ++ int delta, current, i; ++ unsigned long read_lo, read_hi; ++ ++ tm_min = (1 << AT_DENTRY_TIMESTAMP_WIDTH) - 1; ++ tm_max = 0; ++ current = 0; ++ ++ for (i = 0; i < ESW_ATABLE_MEM_NUM_ENTRIES; i++) { ++ read_atable(fep, i, &read_lo, &read_hi); ++ if (read_hi & (1 << 16)) { ++ /*the entry is valid*/ ++ tm = AT_EXTRACT_TIMESTAMP(read_hi); ++ if (tm > tm_max) ++ tm_max = tm; ++ if (tm < tm_min) ++ tm_min = tm; ++ current++; ++ } ++ } ++ ++ delta = TIMEDELTA(tm_max, tm_min); ++ if (delta < fep->ageMax) { ++ /*Difference must be in range*/ ++ fep->currTime = tm_max; ++ } else { ++ fep->currTime = tm_min; ++ } ++ ++ fep->atCurrEntries = current; ++ return fep->currTime; ++} ++ ++int esw_atable_dynamicms_get_port( ++ struct switch_enet_private *fep, ++ unsigned long write_lo, ++ unsigned long write_hi, ++ int block_index) ++{ ++ int i, index_end; ++ unsigned long read_lo, read_hi, port; ++ ++ index_end = block_index + ATABLE_ENTRY_PER_SLOT; ++ /* Now search all the entries in the selected block */ ++ for (i = block_index; i < index_end; i++) { ++ read_atable(fep, i, &read_lo, &read_hi); ++ ++ if ((read_lo == write_lo) && ++ ((read_hi & 0x0000ffff) == ++ (write_hi & 0x0000ffff))) { ++ /* found correct address,*/ ++ if (read_hi & (1 << 16)) { ++ /*extract the port index from the valid entry*/ ++ port = AT_EXTRACT_PORT(read_hi); ++ return port; ++ } ++ } ++ } ++ ++ return -1; ++} ++ ++/* Get the port index from the source MAC address ++ * of the received frame ++ * @return port index ++ */ ++int esw_atable_dynamicms_get_portindex_from_mac( ++ struct switch_enet_private *fep, ++ unsigned char *mac_addr, ++ unsigned long write_lo, ++ unsigned long write_hi) ++{ ++ int blockIdx; ++ int rc; ++ /*compute the block index*/ ++ blockIdx = GET_BLOCK_PTR(crc8_calc(mac_addr)); ++ /* Get the ingress port index of the received BPDU */ ++ rc = esw_atable_dynamicms_get_port(fep, ++ write_lo, write_hi, blockIdx); ++ ++ return rc; ++} ++ ++/* dynamicms MAC address table learn and migration*/ ++int esw_atable_dynamicms_learn_migration( ++ struct switch_enet_private *fep, ++ int currTime) ++{ ++ eswPortInfo *pESWPortInfo; ++ int index; ++ int inserted = 0; ++ ++ pESWPortInfo = esw_portinfofifo_read(fep); ++ /* Anything to learn */ ++ if (pESWPortInfo != 0) { ++ /*get block index from lookup table*/ ++ index = GET_BLOCK_PTR(pESWPortInfo->hash); ++ inserted = esw_update_atable_dynamic1( ++ pESWPortInfo->maclo, ++ pESWPortInfo->machi, index, ++ pESWPortInfo->port, currTime, fep); ++ } ++ ++ return 0; ++} ++/* -----------------------------------------------------------------*/ ++/* ++ * esw_forced_forward ++ * The frame is forwared to the forced destination ports. ++ * It only replace the MAC lookup function, ++ * all other filtering(eg.VLAN verification) act as normal ++ */ ++int esw_forced_forward(struct switch_enet_private *fep, ++ int port1, int port2, int enable) ++{ ++ unsigned long tmp = 0; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ /* Enable Forced forwarding for port num */ ++ if ((port1 == 1) && (port2 == 1)) ++ tmp |= MCF_ESW_P0FFEN_FD(3); ++ else if (port1 == 1) ++ /*Enable Forced forwarding for port 1 only*/ ++ tmp |= MCF_ESW_P0FFEN_FD(1); ++ else if (port2 == 1) ++ /*Enable Forced forwarding for port 2 only*/ ++ tmp |= MCF_ESW_P0FFEN_FD(2); ++ else { ++ printk(KERN_ERR "%s:do not support " ++ "the forced forward mode" ++ "port1 %x port2 %x\n", ++ __func__, port1, port2); ++ return -1; ++ } ++ ++ if (enable == 1) ++ tmp |= MCF_ESW_P0FFEN_FEN; ++ else if (enable == 0) ++ tmp &= ~MCF_ESW_P0FFEN_FEN; ++ else { ++ printk(KERN_ERR "%s: the enable %x is error\n", ++ __func__, enable); ++ return -2; ++ } ++ ++ fecp->ESW_P0FFEN = tmp; ++ return 0; ++} ++ ++void esw_get_forced_forward( ++ struct switch_enet_private *fep, ++ unsigned long *ulForceForward) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulForceForward = fecp->ESW_P0FFEN; ++} ++ ++void esw_get_port_enable( ++ struct switch_enet_private *fep, ++ unsigned long *ulPortEnable) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulPortEnable = fecp->ESW_PER; ++} ++/* ++ * enable or disable port n tx or rx ++ * tx_en 0 disable port n tx ++ * tx_en 1 enable port n tx ++ * rx_en 0 disbale port n rx ++ * rx_en 1 enable port n rx ++ */ ++int esw_port_enable_config(struct switch_enet_private *fep, ++ int port, int tx_en, int rx_en) ++{ ++ unsigned long tmp = 0; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ tmp = fecp->ESW_PER; ++ if (tx_en == 1) { ++ if (port == 0) ++ tmp |= MCF_ESW_PER_TE0; ++ else if (port == 1) ++ tmp |= MCF_ESW_PER_TE1; ++ else if (port == 2) ++ tmp |= MCF_ESW_PER_TE2; ++ else { ++ printk(KERN_ERR "%s:do not support the" ++ " port %x tx enable\n", ++ __func__, port); ++ return -1; ++ } ++ } else if (tx_en == 0) { ++ if (port == 0) ++ tmp &= (~MCF_ESW_PER_TE0); ++ else if (port == 1) ++ tmp &= (~MCF_ESW_PER_TE1); ++ else if (port == 2) ++ tmp &= (~MCF_ESW_PER_TE2); ++ else { ++ printk(KERN_ERR "%s:do not support " ++ "the port %x tx disable\n", ++ __func__, port); ++ return -2; ++ } ++ } else { ++ printk(KERN_ERR "%s:do not support the port %x" ++ " tx op value %x\n", ++ __func__, port, tx_en); ++ return -3; ++ } ++ ++ if (rx_en == 1) { ++ if (port == 0) ++ tmp |= MCF_ESW_PER_RE0; ++ else if (port == 1) ++ tmp |= MCF_ESW_PER_RE1; ++ else if (port == 2) ++ tmp |= MCF_ESW_PER_RE2; ++ else { ++ printk(KERN_ERR "%s:do not support the " ++ "port %x rx enable\n", ++ __func__, port); ++ return -4; ++ } ++ } else if (rx_en == 0) { ++ if (port == 0) ++ tmp &= (~MCF_ESW_PER_RE0); ++ else if (port == 1) ++ tmp &= (~MCF_ESW_PER_RE1); ++ else if (port == 2) ++ tmp &= (~MCF_ESW_PER_RE2); ++ else { ++ printk(KERN_ERR "%s:do not support the " ++ "port %x rx disable\n", ++ __func__, port); ++ return -5; ++ } ++ } else { ++ printk(KERN_ERR "%s:do not support the port %x" ++ " rx op value %x\n", ++ __func__, port, tx_en); ++ return -6; ++ } ++ ++ fecp->ESW_PER = tmp; ++ return 0; ++} ++ ++ ++void esw_get_port_broadcast(struct switch_enet_private *fep, ++ unsigned long *ulPortBroadcast) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulPortBroadcast = fecp->ESW_DBCR; ++} ++ ++int esw_port_broadcast_config(struct switch_enet_private *fep, ++ int port, int enable) ++{ ++ unsigned long tmp = 0; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port > 2) || (port < 0)) { ++ printk(KERN_ERR "%s:do not support the port %x" ++ " default broadcast\n", ++ __func__, port); ++ return -1; ++ } ++ ++ tmp = fecp->ESW_DBCR; ++ if (enable == 1) { ++ if (port == 0) ++ tmp |= MCF_ESW_DBCR_P0; ++ else if (port == 1) ++ tmp |= MCF_ESW_DBCR_P1; ++ else if (port == 2) ++ tmp |= MCF_ESW_DBCR_P2; ++ } else if (enable == 0) { ++ if (port == 0) ++ tmp &= ~MCF_ESW_DBCR_P0; ++ else if (port == 1) ++ tmp &= ~MCF_ESW_DBCR_P1; ++ else if (port == 2) ++ tmp &= ~MCF_ESW_DBCR_P2; ++ } ++ ++ fecp->ESW_DBCR = tmp; ++ return 0; ++} ++ ++ ++void esw_get_port_multicast(struct switch_enet_private *fep, ++ unsigned long *ulPortMulticast) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulPortMulticast = fecp->ESW_DMCR; ++} ++ ++int esw_port_multicast_config(struct switch_enet_private *fep, ++ int port, int enable) ++{ ++ unsigned long tmp = 0; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port > 2) || (port < 0)) { ++ printk(KERN_ERR "%s:do not support the port %x" ++ " default broadcast\n", ++ __func__, port); ++ return -1; ++ } ++ ++ tmp = fecp->ESW_DMCR; ++ if (enable == 1) { ++ if (port == 0) ++ tmp |= MCF_ESW_DMCR_P0; ++ else if (port == 1) ++ tmp |= MCF_ESW_DMCR_P1; ++ else if (port == 2) ++ tmp |= MCF_ESW_DMCR_P2; ++ } else if (enable == 0) { ++ if (port == 0) ++ tmp &= ~MCF_ESW_DMCR_P0; ++ else if (port == 1) ++ tmp &= ~MCF_ESW_DMCR_P1; ++ else if (port == 2) ++ tmp &= ~MCF_ESW_DMCR_P2; ++ } ++ ++ fecp->ESW_DMCR = tmp; ++ return 0; ++} ++ ++ ++void esw_get_port_blocking(struct switch_enet_private *fep, ++ unsigned long *ulPortBlocking) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulPortBlocking = (fecp->ESW_BKLR & 0x0000000f); ++} ++ ++int esw_port_blocking_config(struct switch_enet_private *fep, ++ int port, int enable) ++{ ++ unsigned long tmp = 0; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port > 2) || (port < 0)) { ++ printk(KERN_ERR "%s:do not support the port %x" ++ " default broadcast\n", ++ __func__, port); ++ return -1; ++ } ++ ++ tmp = fecp->ESW_BKLR; ++ if (enable == 1) { ++ if (port == 0) ++ tmp |= MCF_ESW_BKLR_BE0; ++ else if (port == 1) ++ tmp |= MCF_ESW_BKLR_BE1; ++ else if (port == 2) ++ tmp |= MCF_ESW_BKLR_BE2; ++ } else if (enable == 0) { ++ if (port == 0) ++ tmp &= ~MCF_ESW_BKLR_BE0; ++ else if (port == 1) ++ tmp &= ~MCF_ESW_BKLR_BE1; ++ else if (port == 2) ++ tmp &= ~MCF_ESW_BKLR_BE2; ++ } ++ ++ fecp->ESW_BKLR = tmp; ++ return 0; ++} ++ ++ ++void esw_get_port_learning(struct switch_enet_private *fep, ++ unsigned long *ulPortLearning) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulPortLearning = (fecp->ESW_BKLR & 0x000f0000) >> 16; ++} ++ ++int esw_port_learning_config(struct switch_enet_private *fep, ++ int port, int disable) ++{ ++ unsigned long tmp = 0; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port > 2) || (port < 0)) { ++ printk(KERN_ERR "%s:do not support the port %x" ++ " default broadcast\n", ++ __func__, port); ++ return -1; ++ } ++ ++ tmp = fecp->ESW_BKLR; ++ if (disable == 0) { ++ fep->learning_irqhandle_enable = 0; ++ if (port == 0) ++ tmp |= MCF_ESW_BKLR_LD0; ++ else if (port == 1) ++ tmp |= MCF_ESW_BKLR_LD1; ++ else if (port == 2) ++ tmp |= MCF_ESW_BKLR_LD2; ++ } else if (disable == 1) { ++ if (port == 0) ++ tmp &= ~MCF_ESW_BKLR_LD0; ++ else if (port == 1) ++ tmp &= ~MCF_ESW_BKLR_LD1; ++ else if (port == 2) ++ tmp &= ~MCF_ESW_BKLR_LD2; ++ } ++ ++ fecp->ESW_BKLR = tmp; ++ return 0; ++} ++/*********************************************************************/ ++void esw_mac_lookup_table_range(struct switch_enet_private *fep) ++{ ++ int index; ++ unsigned long read_lo, read_hi; ++ /* Pointer to switch address look up memory*/ ++ for (index = 0; index < 2048; index++) ++ write_atable(fep, index, index, (~index)); ++ ++ /* Pointer to switch address look up memory*/ ++ for (index = 0; index < 2048; index++) { ++ read_atable(fep, index, &read_lo, &read_hi); ++ if (read_lo != index) { ++ printk(KERN_ERR "%s:Mismatch at low %d\n", ++ __func__, index); ++ return; ++ } ++ ++ if (read_hi != (~index)) { ++ printk(KERN_ERR "%s:Mismatch at high %d\n", ++ __func__, index); ++ return; ++ } ++ } ++} ++ ++/* ++ * Checks IP Snoop options of handling the snooped frame. ++ * mode 0 : The snooped frame is forward only to management port ++ * mode 1 : The snooped frame is copy to management port and ++ * normal forwarding is checked. ++ * mode 2 : The snooped frame is discarded. ++ * mode 3 : Disable the ip snoop function ++ * ip_header_protocol : the IP header protocol field ++ */ ++int esw_ip_snoop_config(struct switch_enet_private *fep, ++ int mode, unsigned long ip_header_protocol) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp = 0, protocol_type = 0; ++ int num = 0; ++ ++ fecp = fep->hwp; ++ /* Config IP Snooping */ ++ if (mode == 0) { ++ /* Enable IP Snooping */ ++ tmp = MCF_ESW_IPSNP_EN; ++ tmp |= MCF_ESW_IPSNP_MODE(0);/*For Forward*/ ++ } else if (mode == 1) { ++ /* Enable IP Snooping */ ++ tmp = MCF_ESW_IPSNP_EN; ++ /*For Forward and copy_to_mangmnt_port*/ ++ tmp |= MCF_ESW_IPSNP_MODE(1); ++ } else if (mode == 2) { ++ /* Enable IP Snooping */ ++ tmp = MCF_ESW_IPSNP_EN; ++ tmp |= MCF_ESW_IPSNP_MODE(2);/*discard*/ ++ } else if (mode == 3) { ++ /* disable IP Snooping */ ++ tmp = MCF_ESW_IPSNP_EN; ++ tmp &= ~MCF_ESW_IPSNP_EN; ++ } else { ++ printk(KERN_ERR "%s: the mode %x " ++ "we do not support\n", __func__, mode); ++ return -1; ++ } ++ ++ protocol_type = ip_header_protocol; ++ for (num = 0; num < 8; num++) { ++ if (protocol_type == ++ AT_EXTRACT_IP_PROTOCOL(fecp->ESW_IPSNP[num])) { ++ fecp->ESW_IPSNP[num] = ++ tmp | MCF_ESW_IPSNP_PROTOCOL(protocol_type); ++ break; ++ } else if (!(fecp->ESW_IPSNP[num])) { ++ fecp->ESW_IPSNP[num] = ++ tmp | MCF_ESW_IPSNP_PROTOCOL(protocol_type); ++ break; ++ } ++ } ++ if (num == 8) { ++ printk(KERN_INFO "IP snooping table is full\n"); ++ return 0; ++ } ++ ++ return 0; ++} ++ ++void esw_get_ip_snoop_config(struct switch_enet_private *fep, ++ unsigned long *ulpESW_IPSNP) ++{ ++ int i; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ for (i = 0; i < 8; i++) ++ *(ulpESW_IPSNP + i) = fecp->ESW_IPSNP[i]; ++} ++/* ++ * Checks TCP/UDP Port Snoop options of handling the snooped frame. ++ * mode 0 : The snooped frame is forward only to management port ++ * mode 1 : The snooped frame is copy to management port and ++ * normal forwarding is checked. ++ * mode 2 : The snooped frame is discarded. ++ * mode 3 : Disable the TCP/UDP port snoop function ++ * compare_port : port number in the TCP/UDP header ++ * compare_num 1: TCP/UDP source port number is compared ++ * compare_num 2: TCP/UDP destination port number is compared ++ * compare_num 3: TCP/UDP source and destination port number is compared ++ */ ++int esw_tcpudp_port_snoop_config(struct switch_enet_private *fep, ++ int mode, int compare_port, int compare_num) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp; ++ int num; ++ ++ fecp = fep->hwp; ++ ++ /* Enable TCP/UDP port Snooping */ ++ tmp = MCF_ESW_PSNP_EN; ++ if (mode == 0) ++ tmp |= MCF_ESW_PSNP_MODE(0);/*For Forward*/ ++ else if (mode == 1)/*For Forward and copy_to_mangmnt_port*/ ++ tmp |= MCF_ESW_PSNP_MODE(1); ++ else if (mode == 2) ++ tmp |= MCF_ESW_PSNP_MODE(2);/*discard*/ ++ else if (mode == 3) /*disable the port function*/ ++ tmp &= (~MCF_ESW_PSNP_EN); ++ else { ++ printk(KERN_ERR "%s: the mode %x we do not support\n", ++ __func__, mode); ++ return -1; ++ } ++ ++ if (compare_num == 1) ++ tmp |= MCF_ESW_PSNP_CS; ++ else if (compare_num == 2) ++ tmp |= MCF_ESW_PSNP_CD; ++ else if (compare_num == 3) ++ tmp |= MCF_ESW_PSNP_CD | MCF_ESW_PSNP_CS; ++ else { ++ printk(KERN_ERR "%s: the compare port address %x" ++ " we do not support\n", ++ __func__, compare_num); ++ return -1; ++ } ++ ++ for (num = 0; num < 8; num++) { ++ if (compare_port == ++ AT_EXTRACT_TCP_UDP_PORT(fecp->ESW_PSNP[num])) { ++ fecp->ESW_PSNP[num] = ++ tmp | MCF_ESW_PSNP_PORT_COMPARE(compare_port); ++ break; ++ } else if (!(fecp->ESW_PSNP[num])) { ++ fecp->ESW_PSNP[num] = ++ tmp | MCF_ESW_PSNP_PORT_COMPARE(compare_port); ++ break; ++ } ++ } ++ if (num == 8) { ++ printk(KERN_INFO "TCP/UDP port snooping table is full\n"); ++ return 0; ++ } ++ ++ return 0; ++} ++ ++void esw_get_tcpudp_port_snoop_config( ++ struct switch_enet_private *fep, ++ unsigned long *ulpESW_PSNP) ++{ ++ int i; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ for (i = 0; i < 8; i++) ++ *(ulpESW_PSNP + i) = fecp->ESW_PSNP[i]; ++} ++/*-----------------mirror----------------------------------------*/ ++void esw_get_port_mirroring(struct switch_enet_private *fep) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ printk(KERN_INFO "Mirror Port: %1ld Egress Port Match:%s " ++ "Ingress Port Match:%s\n", fecp->ESW_MCR & 0xf, ++ (fecp->ESW_MCR >> 6) & 1 ? "Y" : "N", ++ (fecp->ESW_MCR >> 5) & 1 ? "Y" : "N"); ++ ++ if ((fecp->ESW_MCR >> 6) & 1) ++ printk(KERN_INFO "Egress Port to be mirrored: Port %ld\n", ++ fecp->ESW_EGMAP >> 1); ++ if ((fecp->ESW_MCR >> 5) & 1) ++ printk(KERN_INFO "Ingress Port to be mirrored: Port %ld\n", ++ fecp->ESW_INGMAP >> 1); ++ ++ printk(KERN_INFO "Egress Des Address Match:%s " ++ "Egress Src Address Match:%s\n", ++ (fecp->ESW_MCR >> 10) & 1 ? "Y" : "N", ++ (fecp->ESW_MCR >> 9) & 1 ? "Y" : "N"); ++ printk(KERN_INFO "Ingress Des Address Match:%s " ++ "Ingress Src Address Match:%s\n", ++ (fecp->ESW_MCR >> 8) & 1 ? "Y" : "N", ++ (fecp->ESW_MCR >> 7) & 1 ? "Y" : "N"); ++ ++ if ((fecp->ESW_MCR >> 10) & 1) ++ printk(KERN_INFO "Egress Des Address to be mirrored: " ++ "%02lx-%02lx-%02lx-%02lx-%02lx-%02lx\n", ++ fecp->ESW_ENGDAL & 0xff, (fecp->ESW_ENGDAL >> 8) & 0xff, ++ (fecp->ESW_ENGDAL >> 16) & 0xff, ++ (fecp->ESW_ENGDAL >> 24) & 0xff, ++ fecp->ESW_ENGDAH & 0xff, ++ (fecp->ESW_ENGDAH >> 8) & 0xff); ++ if ((fecp->ESW_MCR >> 9) & 1) ++ printk("Egress Src Address to be mirrored: " ++ "%02lx-%02lx-%02lx-%02lx-%02lx-%02lx\n", ++ fecp->ESW_ENGSAL & 0xff, (fecp->ESW_ENGSAL >> 8) & 0xff, ++ (fecp->ESW_ENGSAL >> 16) & 0xff, ++ (fecp->ESW_ENGSAL >> 24) & 0xff, ++ fecp->ESW_ENGSAH & 0xff, ++ (fecp->ESW_ENGSAH >> 8) & 0xff); ++ if ((fecp->ESW_MCR >> 8) & 1) ++ printk("Ingress Des Address to be mirrored: " ++ "%02lx-%02lx-%02lx-%02lx-%02lx-%02lx\n", ++ fecp->ESW_INGDAL & 0xff, (fecp->ESW_INGDAL >> 8) & 0xff, ++ (fecp->ESW_INGDAL >> 16) & 0xff, ++ (fecp->ESW_INGDAL >> 24) & 0xff, ++ fecp->ESW_INGDAH & 0xff, ++ (fecp->ESW_INGDAH >> 8) & 0xff); ++ if ((fecp->ESW_MCR >> 7) & 1) ++ printk("Ingress Src Address to be mirrored: " ++ "%02lx-%02lx-%02lx-%02lx-%02lx-%02lx\n", ++ fecp->ESW_INGSAL & 0xff, (fecp->ESW_INGSAL >> 8) & 0xff, ++ (fecp->ESW_INGSAL >> 16) & 0xff, ++ (fecp->ESW_INGSAL >> 24) & 0xff, ++ fecp->ESW_INGSAH & 0xff, ++ (fecp->ESW_INGSAH >> 8) & 0xff); ++} ++ ++int esw_port_mirroring_config_port_match(struct switch_enet_private *fep, ++ int mirror_port, int port_match_en, int port) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp = 0; ++ ++ fecp = fep->hwp; ++ ++ tmp = fecp->ESW_MCR; ++ if (mirror_port != (tmp & 0xf)) ++ tmp = 0; ++ ++ switch (port_match_en) { ++ case MIRROR_EGRESS_PORT_MATCH: ++ tmp |= MCF_ESW_MCR_EGMAP; ++ if (port == 0) ++ fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG0; ++ else if (port == 1) ++ fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG1; ++ else if (port == 2) ++ fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG2; ++ break; ++ case MIRROR_INGRESS_PORT_MATCH: ++ tmp |= MCF_ESW_MCR_INGMAP; ++ if (port == 0) ++ fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING0; ++ else if (port == 1) ++ fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING1; ++ else if (port == 2) ++ fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING2; ++ break; ++ default: ++ tmp = 0; ++ break; ++ } ++ ++ tmp = tmp & 0x07e0; ++ if (port_match_en) ++ tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port); ++ ++ fecp->ESW_MCR = tmp; ++ return 0; ++} ++ ++int esw_port_mirroring_config(struct switch_enet_private *fep, ++ int mirror_port, int port, int mirror_enable, ++ unsigned char *src_mac, unsigned char *des_mac, ++ int egress_en, int ingress_en, ++ int egress_mac_src_en, int egress_mac_des_en, ++ int ingress_mac_src_en, int ingress_mac_des_en) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp; ++ ++ fecp = fep->hwp; ++ ++ /*mirroring config*/ ++ tmp = 0; ++ if (egress_en == 1) { ++ tmp |= MCF_ESW_MCR_EGMAP; ++ if (port == 0) ++ fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG0; ++ else if (port == 1) ++ fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG1; ++ else if (port == 2) ++ fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG2; ++ else { ++ printk(KERN_ERR "%s: the port %x we do not support\n", ++ __func__, port); ++ return -1; ++ } ++ } else if (egress_en == 0) { ++ tmp &= (~MCF_ESW_MCR_EGMAP); ++ } else { ++ printk(KERN_ERR "%s: egress_en %x we do not support\n", ++ __func__, egress_en); ++ return -1; ++ } ++ ++ if (ingress_en == 1) { ++ tmp |= MCF_ESW_MCR_INGMAP; ++ if (port == 0) ++ fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING0; ++ else if (port == 1) ++ fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING1; ++ else if (port == 2) ++ fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING2; ++ else { ++ printk(KERN_ERR "%s: the port %x we do not support\n", ++ __func__, port); ++ return -1; ++ } ++ } else if (ingress_en == 0) { ++ tmp &= ~MCF_ESW_MCR_INGMAP; ++ } else{ ++ printk(KERN_ERR "%s: ingress_en %x we do not support\n", ++ __func__, ingress_en); ++ return -1; ++ } ++ ++ if (egress_mac_src_en == 1) { ++ tmp |= MCF_ESW_MCR_EGSA; ++ fecp->ESW_ENGSAH = (src_mac[5] << 8) | (src_mac[4]); ++ fecp->ESW_ENGSAL = (unsigned long)((src_mac[3] << 24) | ++ (src_mac[2] << 16) | ++ (src_mac[1] << 8) | ++ src_mac[0]); ++ } else if (egress_mac_src_en == 0) { ++ tmp &= ~MCF_ESW_MCR_EGSA; ++ } else { ++ printk(KERN_ERR "%s: egress_mac_src_en %x we do not support\n", ++ __func__, egress_mac_src_en); ++ return -1; ++ } ++ ++ if (egress_mac_des_en == 1) { ++ tmp |= MCF_ESW_MCR_EGDA; ++ fecp->ESW_ENGDAH = (des_mac[5] << 8) | (des_mac[4]); ++ fecp->ESW_ENGDAL = (unsigned long)((des_mac[3] << 24) | ++ (des_mac[2] << 16) | ++ (des_mac[1] << 8) | ++ des_mac[0]); ++ } else if (egress_mac_des_en == 0) { ++ tmp &= ~MCF_ESW_MCR_EGDA; ++ } else { ++ printk(KERN_ERR "%s: egress_mac_des_en %x we do not support\n", ++ __func__, egress_mac_des_en); ++ return -1; ++ } ++ ++ if (ingress_mac_src_en == 1) { ++ tmp |= MCF_ESW_MCR_INGSA; ++ fecp->ESW_INGSAH = (src_mac[5] << 8) | (src_mac[4]); ++ fecp->ESW_INGSAL = (unsigned long)((src_mac[3] << 24) | ++ (src_mac[2] << 16) | ++ (src_mac[1] << 8) | ++ src_mac[0]); ++ } else if (ingress_mac_src_en == 0) { ++ tmp &= ~MCF_ESW_MCR_INGSA; ++ } else { ++ printk(KERN_ERR "%s: ingress_mac_src_en %x we do not support\n", ++ __func__, ingress_mac_src_en); ++ return -1; ++ } ++ ++ if (ingress_mac_des_en == 1) { ++ tmp |= MCF_ESW_MCR_INGDA; ++ fecp->ESW_INGDAH = (des_mac[5] << 8) | (des_mac[4]); ++ fecp->ESW_INGDAL = (unsigned long)((des_mac[3] << 24) | ++ (des_mac[2] << 16) | ++ (des_mac[1] << 8) | ++ des_mac[0]); ++ } else if (ingress_mac_des_en == 0) { ++ tmp &= ~MCF_ESW_MCR_INGDA; ++ } else { ++ printk(KERN_ERR "%s: ingress_mac_des_en %x we do not support\n", ++ __func__, ingress_mac_des_en); ++ return -1; ++ } ++ ++ if (mirror_enable == 1) ++ tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port); ++ else if (mirror_enable == 0) ++ tmp &= ~MCF_ESW_MCR_MEN; ++ else ++ printk(KERN_ERR "%s: the mirror enable %x is error\n", ++ __func__, mirror_enable); ++ ++ ++ fecp->ESW_MCR = tmp; ++ return 0; ++} ++ ++int esw_port_mirroring_config_addr_match(struct switch_enet_private *fep, ++ int mirror_port, int addr_match_enable, unsigned char *mac_addr) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp = 0; ++ ++ fecp = fep->hwp; ++ ++ tmp = fecp->ESW_MCR; ++ if (mirror_port != (tmp & 0xf)) ++ tmp = 0; ++ ++ switch (addr_match_enable) { ++ case MIRROR_EGRESS_SOURCE_MATCH: ++ tmp |= MCF_ESW_MCR_EGSA; ++ fecp->ESW_ENGSAH = (mac_addr[5] << 8) | (mac_addr[4]); ++ fecp->ESW_ENGSAL = (unsigned long)((mac_addr[3] << 24) | ++ (mac_addr[2] << 16) | (mac_addr[1] << 8) | mac_addr[0]); ++ break; ++ case MIRROR_INGRESS_SOURCE_MATCH: ++ tmp |= MCF_ESW_MCR_INGSA; ++ fecp->ESW_INGSAH = (mac_addr[5] << 8) | (mac_addr[4]); ++ fecp->ESW_INGSAL = (unsigned long)((mac_addr[3] << 24) | ++ (mac_addr[2] << 16) | (mac_addr[1] << 8) | mac_addr[0]); ++ break; ++ case MIRROR_EGRESS_DESTINATION_MATCH: ++ tmp |= MCF_ESW_MCR_EGDA; ++ fecp->ESW_ENGDAH = (mac_addr[5] << 8) | (mac_addr[4]); ++ fecp->ESW_ENGDAL = (unsigned long)((mac_addr[3] << 24) | ++ (mac_addr[2] << 16) | (mac_addr[1] << 8) | mac_addr[0]); ++ break; ++ case MIRROR_INGRESS_DESTINATION_MATCH: ++ tmp |= MCF_ESW_MCR_INGDA; ++ fecp->ESW_INGDAH = (mac_addr[5] << 8) | (mac_addr[4]); ++ fecp->ESW_INGDAL = (unsigned long)((mac_addr[3] << 24) | ++ (mac_addr[2] << 16) | (mac_addr[1] << 8) | mac_addr[0]); ++ break; ++ default: ++ tmp = 0; ++ break; ++ } ++ ++ tmp = tmp & 0x07e0; ++ if (addr_match_enable) ++ tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port); ++ ++ fecp->ESW_MCR = tmp; ++ return 0; ++} ++ ++void esw_get_vlan_verification(struct switch_enet_private *fep, ++ unsigned long *ulValue) ++{ ++ volatile switch_t *fecp; ++ fecp = fep->hwp; ++ *ulValue = fecp->ESW_VLANV; ++} ++ ++int esw_set_vlan_verification(struct switch_enet_private *fep, int port, ++ int vlan_domain_verify_en, int vlan_discard_unknown_en) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ if ((port < 0) || (port > 2)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ ++ if (vlan_domain_verify_en == 1) { ++ if (port == 0) ++ fecp->ESW_VLANV |= MCF_ESW_VLANV_VV0; ++ else if (port == 1) ++ fecp->ESW_VLANV |= MCF_ESW_VLANV_VV1; ++ else if (port == 2) ++ fecp->ESW_VLANV |= MCF_ESW_VLANV_VV2; ++ } else if (vlan_domain_verify_en == 0) { ++ if (port == 0) ++ fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV0; ++ else if (port == 1) ++ fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV1; ++ else if (port == 2) ++ fecp->ESW_VLANV &= ~MCF_ESW_VLANV_VV2; ++ } else { ++ printk(KERN_INFO "%s: donot support " ++ "vlan_domain_verify %x\n", ++ __func__, vlan_domain_verify_en); ++ return -2; ++ } ++ ++ if (vlan_discard_unknown_en == 1) { ++ if (port == 0) ++ fecp->ESW_VLANV |= MCF_ESW_VLANV_DU0; ++ else if (port == 1) ++ fecp->ESW_VLANV |= MCF_ESW_VLANV_DU1; ++ else if (port == 2) ++ fecp->ESW_VLANV |= MCF_ESW_VLANV_DU2; ++ } else if (vlan_discard_unknown_en == 0) { ++ if (port == 0) ++ fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU0; ++ else if (port == 1) ++ fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU1; ++ else if (port == 2) ++ fecp->ESW_VLANV &= ~MCF_ESW_VLANV_DU2; ++ } else { ++ printk(KERN_INFO "%s: donot support " ++ "vlan_discard_unknown %x\n", ++ __func__, vlan_discard_unknown_en); ++ return -3; ++ } ++ ++ return 0; ++} ++ ++void esw_get_vlan_resolution_table(struct switch_enet_private *fep, ++ struct eswVlanTableItem *tableaddr) ++{ ++ volatile switch_t *fecp; ++ int vnum = 0; ++ int i; ++ ++ fecp = fep->hwp; ++ for (i = 0; i < 32; i++) { ++ if (fecp->ESW_VRES[i]) { ++ tableaddr->table[i].port_vlanid = ++ fecp->ESW_VRES[i] >> 3; ++ tableaddr->table[i].vlan_domain_port = ++ fecp->ESW_VRES[i] & 7; ++ vnum++; ++ } ++ } ++ tableaddr->valid_num = vnum; ++} ++ ++int esw_set_vlan_id(struct switch_enet_private *fep, unsigned long configData) ++{ ++ volatile switch_t *fecp; ++ int i; ++ ++ fecp = fep->hwp; ++ ++ for (i = 0; i < 32; i++) { ++ if (fecp->ESW_VRES[i] == 0) { ++ fecp->ESW_VRES[i] = MCF_ESW_VRES_VLANID(configData); ++ return 0; ++ } else if (((fecp->ESW_VRES[i] >> 3) & 0xfff) == configData) { ++ printk(KERN_INFO "The VLAN already exists\n"); ++ return 0; ++ } ++ } ++ ++ printk(KERN_INFO "The VLAN can't create, because VLAN table is full\n"); ++ return 0; ++} ++ ++int esw_set_vlan_id_cleared(struct switch_enet_private *fep, ++ unsigned long configData) ++{ ++ volatile switch_t *fecp; ++ int i; ++ ++ fecp = fep->hwp; ++ ++ for (i = 0; i < 32; i++) { ++ if (((fecp->ESW_VRES[i] >> 3) & 0xfff) == configData) { ++ fecp->ESW_VRES[i] = 0; ++ break; ++ } ++ } ++ return 0; ++} ++ ++int esw_set_port_in_vlan_id(struct switch_enet_private *fep, ++ eswIoctlVlanResoultionTable configData) ++{ ++ volatile switch_t *fecp; ++ int i; ++ int lastnum = 0; ++ ++ fecp = fep->hwp; ++ ++ for (i = 0; i < 32; i++) { ++ if (fecp->ESW_VRES[i] == 0) { ++ lastnum = i; ++ break; ++ } else if (((fecp->ESW_VRES[i] >> 3) & 0xfff) == ++ configData.port_vlanid) { ++ /* update the port members of this vlan */ ++ fecp->ESW_VRES[i] |= 1 << configData.vlan_domain_port; ++ return 0; ++ } ++ } ++ /* creat a new vlan in vlan table */ ++ fecp->ESW_VRES[lastnum] = MCF_ESW_VRES_VLANID(configData.port_vlanid) | ++ (1 << configData.vlan_domain_port); ++ return 0; ++} ++ ++int esw_set_vlan_resolution_table(struct switch_enet_private *fep, ++ unsigned short port_vlanid, int vlan_domain_num, ++ int vlan_domain_port) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ if ((vlan_domain_num < 0) ++ || (vlan_domain_num > 31)) { ++ printk(KERN_ERR "%s: do not support the " ++ "vlan_domain_num %d\n", ++ __func__, vlan_domain_num); ++ return -1; ++ } ++ ++ if ((vlan_domain_port < 0) ++ || (vlan_domain_port > 7)) { ++ printk(KERN_ERR "%s: do not support the " ++ "vlan_domain_port %d\n", ++ __func__, vlan_domain_port); ++ return -2; ++ } ++ ++ fecp->ESW_VRES[vlan_domain_num] = ++ MCF_ESW_VRES_VLANID(port_vlanid) ++ | vlan_domain_port; ++ ++ return 0; ++} ++ ++void esw_get_vlan_input_config(struct switch_enet_private *fep, ++ eswIoctlVlanInputStatus *pVlanInputConfig) ++{ ++ volatile switch_t *fecp; ++ int i; ++ ++ fecp = fep->hwp; ++ for (i = 0; i < 3; i++) ++ pVlanInputConfig->ESW_PID[i] = fecp->ESW_PID[i]; ++ ++ pVlanInputConfig->ESW_VLANV = fecp->ESW_VLANV; ++ pVlanInputConfig->ESW_VIMSEL = fecp->ESW_VIMSEL; ++ pVlanInputConfig->ESW_VIMEN = fecp->ESW_VIMEN; ++ ++ for (i = 0; i < 32; i++) ++ pVlanInputConfig->ESW_VRES[i] = fecp->ESW_VRES[i]; ++} ++ ++ ++int esw_vlan_input_process(struct switch_enet_private *fep, ++ int port, int mode, unsigned short port_vlanid) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((mode < 0) || (mode > 5)) { ++ printk(KERN_ERR "%s: do not support the" ++ " VLAN input processing mode %d\n", ++ __func__, mode); ++ return -1; ++ } ++ ++ if ((port < 0) || (port > 3)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, mode); ++ return -2; ++ } ++ ++ fecp->ESW_PID[port] = MCF_ESW_PID_VLANID(port_vlanid); ++ if (port == 0) { ++ if (mode == 4) ++ fecp->ESW_VIMEN &= ~MCF_ESW_VIMEN_EN0; ++ else ++ fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN0; ++ ++ fecp->ESW_VIMSEL &= ~MCF_ESW_VIMSEL_IM0(3); ++ fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM0(mode); ++ } else if (port == 1) { ++ if (mode == 4) ++ fecp->ESW_VIMEN &= ~MCF_ESW_VIMEN_EN1; ++ else ++ fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN1; ++ ++ fecp->ESW_VIMSEL &= ~MCF_ESW_VIMSEL_IM1(3); ++ fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM1(mode); ++ } else if (port == 2) { ++ if (mode == 4) ++ fecp->ESW_VIMEN &= ~MCF_ESW_VIMEN_EN2; ++ else ++ fecp->ESW_VIMEN |= MCF_ESW_VIMEN_EN2; ++ ++ fecp->ESW_VIMSEL &= ~MCF_ESW_VIMSEL_IM2(3); ++ fecp->ESW_VIMSEL |= MCF_ESW_VIMSEL_IM2(mode); ++ } else { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -2; ++ } ++ ++ return 0; ++} ++ ++void esw_get_vlan_output_config(struct switch_enet_private *fep, ++ unsigned long *ulVlanOutputConfig) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulVlanOutputConfig = fecp->ESW_VOMSEL; ++} ++ ++int esw_vlan_output_process(struct switch_enet_private *fep, ++ int port, int mode) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port < 0) || (port > 2)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, mode); ++ return -1; ++ } ++ ++ if (port == 0) { ++ fecp->ESW_VOMSEL &= ~MCF_ESW_VOMSEL_OM0(3); ++ fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM0(mode); ++ } else if (port == 1) { ++ fecp->ESW_VOMSEL &= ~MCF_ESW_VOMSEL_OM1(3); ++ fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM1(mode); ++ } else if (port == 2) { ++ fecp->ESW_VOMSEL &= ~MCF_ESW_VOMSEL_OM2(3); ++ fecp->ESW_VOMSEL |= MCF_ESW_VOMSEL_OM2(mode); ++ } else { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++/*------------frame calssify and priority resolution------------*/ ++/*vlan priority lookup*/ ++int esw_framecalssify_vlan_priority_lookup(struct switch_enet_private *fep, ++ int port, int func_enable, int vlan_pri_table_num, ++ int vlan_pri_table_value) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port < 0) || (port > 3)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ ++ if (func_enable == 0) { ++ fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_VLAN; ++ printk(KERN_ERR "%s: disable port %d VLAN priority " ++ "lookup function\n", __func__, port); ++ return 0; ++ } ++ ++ if ((vlan_pri_table_num < 0) || (vlan_pri_table_num > 7)) { ++ printk(KERN_ERR "%s: do not support the priority %d\n", ++ __func__, vlan_pri_table_num); ++ return -1; ++ } ++ ++ fecp->ESW_PVRES[port] |= ((vlan_pri_table_value & 0x3) ++ << (vlan_pri_table_num*3)); ++ /* enable port VLAN priority lookup function*/ ++ fecp->ESW_PRES[port] |= MCF_ESW_PRES_VLAN; ++ return 0; ++} ++ ++int esw_framecalssify_ip_priority_lookup(struct switch_enet_private *fep, ++ int port, int func_enable, int ipv4_en, int ip_priority_num, ++ int ip_priority_value) ++{ ++ volatile switch_t *fecp; ++ unsigned long tmp = 0, tmp_prio = 0; ++ ++ fecp = fep->hwp; ++ ++ if ((port < 0) || (port > 3)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ ++ if (func_enable == 0) { ++ fecp->ESW_PRES[port] &= ~MCF_ESW_PRES_IP; ++ printk(KERN_ERR "%s: disable port %d ip priority " ++ "lookup function\n", __func__, port); ++ return 0; ++ } ++ ++ /* IPV4 priority 64 entry table lookup*/ ++ /* IPv4 head 6 bit TOS field*/ ++ if (ipv4_en == 1) { ++ if ((ip_priority_num < 0) || (ip_priority_num > 63)) { ++ printk(KERN_ERR "%s: do not support the table entry %d\n", ++ __func__, ip_priority_num); ++ return -2; ++ } ++ } else { /* IPV6 priority 256 entry table lookup*/ ++ /* IPv6 head 8 bit COS field*/ ++ if ((ip_priority_num < 0) || (ip_priority_num > 255)) { ++ printk(KERN_ERR "%s: do not support the table entry %d\n", ++ __func__, ip_priority_num); ++ return -3; ++ } ++ } ++ ++ /* IP priority table lookup : address*/ ++ tmp = MCF_ESW_IPRES_ADDRESS(ip_priority_num); ++ /* IP priority table lookup : ipv4sel*/ ++ if (ipv4_en == 1) ++ tmp = tmp | MCF_ESW_IPRES_IPV4SEL; ++ /* IP priority table lookup : priority*/ ++ if (port == 0) ++ tmp |= MCF_ESW_IPRES_PRI0(ip_priority_value); ++ else if (port == 1) ++ tmp |= MCF_ESW_IPRES_PRI1(ip_priority_value); ++ else if (port == 2) ++ tmp |= MCF_ESW_IPRES_PRI2(ip_priority_value); ++ ++ /* configure*/ ++ fecp->ESW_IPRES = MCF_ESW_IPRES_READ | ++ MCF_ESW_IPRES_ADDRESS(ip_priority_num); ++ tmp_prio = fecp->ESW_IPRES; ++ ++ fecp->ESW_IPRES = tmp | tmp_prio; ++ ++ fecp->ESW_IPRES = MCF_ESW_IPRES_READ | ++ MCF_ESW_IPRES_ADDRESS(ip_priority_num); ++ tmp_prio = fecp->ESW_IPRES; ++ ++ /* enable port IP priority lookup function*/ ++ fecp->ESW_PRES[port] |= MCF_ESW_PRES_IP; ++ return 0; ++} ++ ++int esw_framecalssify_mac_priority_lookup( ++ struct switch_enet_private *fep, int port) ++{ ++ volatile switch_t *fecp; ++ ++ if ((port < 0) || (port > 3)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ ++ fecp = fep->hwp; ++ fecp->ESW_PRES[port] |= MCF_ESW_PRES_MAC; ++ ++ return 0; ++} ++ ++int esw_frame_calssify_priority_init(struct switch_enet_private *fep, ++ int port, unsigned char priority_value) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if ((port < 0) || (port > 3)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ /*disable all priority lookup function*/ ++ fecp->ESW_PRES[port] = 0; ++ fecp->ESW_PRES[port] = MCF_ESW_PRES_DFLT_PRI(priority_value & 0x7); ++ ++ return 0; ++} ++ ++/*---------------------------------------------------------------------------*/ ++int esw_get_statistics_status(struct switch_enet_private *fep, ++ esw_statistics_status *pStatistics) ++{ ++ volatile switch_t *fecp; ++ fecp = fep->hwp; ++ ++ pStatistics->ESW_DISCN = fecp->ESW_DISCN; ++ pStatistics->ESW_DISCB = fecp->ESW_DISCB; ++ pStatistics->ESW_NDISCN = fecp->ESW_NDISCN; ++ pStatistics->ESW_NDISCB = fecp->ESW_NDISCB; ++ return 0; ++} ++ ++int esw_get_port_statistics_status(struct switch_enet_private *fep, ++ int port, esw_port_statistics_status *pPortStatistics) ++{ ++ volatile switch_t *fecp; ++ ++ if ((port < 0) || (port > 3)) { ++ printk(KERN_ERR "%s: do not support the port %d\n", ++ __func__, port); ++ return -1; ++ } ++ ++ fecp = fep->hwp; ++ ++ pPortStatistics->MCF_ESW_POQC = ++ fecp->port_statistics_status[port].MCF_ESW_POQC; ++ pPortStatistics->MCF_ESW_PMVID = ++ fecp->port_statistics_status[port].MCF_ESW_PMVID; ++ pPortStatistics->MCF_ESW_PMVTAG = ++ fecp->port_statistics_status[port].MCF_ESW_PMVTAG; ++ pPortStatistics->MCF_ESW_PBL = ++ fecp->port_statistics_status[port].MCF_ESW_PBL; ++ return 0; ++} ++/*----------------------------------------------------------------------*/ ++int esw_get_output_queue_status(struct switch_enet_private *fep, ++ esw_output_queue_status *pOutputQueue) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ pOutputQueue->ESW_MMSR = fecp->ESW_MMSR; ++ pOutputQueue->ESW_LMT = fecp->ESW_LMT; ++ pOutputQueue->ESW_LFC = fecp->ESW_LFC; ++ pOutputQueue->ESW_IOSR = fecp->ESW_IOSR; ++ pOutputQueue->ESW_PCSR = fecp->ESW_PCSR; ++ pOutputQueue->ESW_QWT = fecp->ESW_QWT; ++ pOutputQueue->ESW_P0BCT = fecp->ESW_P0BCT; ++ return 0; ++} ++ ++/* set output queue memory status and configure*/ ++int esw_set_output_queue_memory(struct switch_enet_private *fep, ++ int fun_num, esw_output_queue_status *pOutputQueue) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if (fun_num == 1) { ++ /* memory manager status*/ ++ fecp->ESW_MMSR = pOutputQueue->ESW_MMSR; ++ } else if (fun_num == 2) { ++ /*low memory threshold*/ ++ fecp->ESW_LMT = pOutputQueue->ESW_LMT; ++ } else if (fun_num == 3) { ++ /*lowest number of free cells*/ ++ fecp->ESW_LFC = pOutputQueue->ESW_LFC; ++ } else if (fun_num == 4) { ++ /*queue weights*/ ++ fecp->ESW_QWT = pOutputQueue->ESW_QWT; ++ } else if (fun_num == 5) { ++ /*port 0 backpressure congenstion thresled*/ ++ fecp->ESW_P0BCT = pOutputQueue->ESW_P0BCT; ++ } else { ++ printk(KERN_ERR "%s: do not support the cmd %x\n", ++ __func__, fun_num); ++ return -1; ++ } ++ return 0; ++} ++/*--------------------------------------------------------------------*/ ++int esw_get_irq_status(struct switch_enet_private *fep, ++ eswIoctlIrqStatus *pIrqStatus) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ pIrqStatus->isr = fecp->switch_ievent; ++ pIrqStatus->imr = fecp->switch_imask; ++ pIrqStatus->rx_buf_pointer = fecp->fec_r_des_start; ++ pIrqStatus->tx_buf_pointer = fecp->fec_x_des_start; ++ pIrqStatus->rx_max_size = fecp->fec_r_buff_size; ++ pIrqStatus->rx_buf_active = fecp->fec_r_des_active; ++ pIrqStatus->tx_buf_active = fecp->fec_x_des_active; ++ return 0; ++} ++ ++int esw_set_irq_mask(struct switch_enet_private *fep, ++ unsigned long mask, int enable) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ ++ if (enable == 1) ++ fecp->switch_imask |= mask; ++ else if (enable == 1) ++ fecp->switch_imask &= (~mask); ++ else { ++ printk(KERN_INFO "%s: enable %lx is error value\n", ++ __func__, mask); ++ return -1; ++ } ++ return 0; ++} ++ ++void esw_clear_irq_event(struct switch_enet_private *fep, ++ unsigned long mask) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ fecp->switch_ievent |= mask; ++} ++ ++void esw_get_switch_mode(struct switch_enet_private *fep, ++ unsigned long *ulModeConfig) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulModeConfig = fecp->ESW_MODE; ++} ++ ++void esw_switch_mode_configure(struct switch_enet_private *fep, ++ unsigned long configure) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ fecp->ESW_MODE |= configure; ++} ++ ++void esw_get_bridge_port(struct switch_enet_private *fep, ++ unsigned long *ulBMPConfig) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ *ulBMPConfig = fecp->ESW_BMPC; ++} ++ ++void esw_bridge_port_configure(struct switch_enet_private *fep, ++ unsigned long configure) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ fecp->ESW_BMPC = configure; ++} ++ ++int esw_get_port_all_status(struct switch_enet_private *fep, ++ unsigned char portnum, struct port_all_status *port_alstatus) ++{ ++ volatile switch_t *fecp; ++ unsigned long PortBlocking; ++ unsigned long PortLearning; ++ unsigned long VlanVerify; ++ unsigned long DiscardUnknown; ++ unsigned long MultiReso; ++ unsigned long BroadReso; ++ unsigned long FTransmit; ++ unsigned long FReceive; ++ ++ fecp = fep->hwp; ++ PortBlocking = fecp->ESW_BKLR & 0x0000000f; ++ PortLearning = (fecp->ESW_BKLR & 0x000f0000) >> 16; ++ VlanVerify = fecp->ESW_VLANV & 0x0000000f; ++ DiscardUnknown = (fecp->ESW_VLANV & 0x000f0000) >> 16; ++ MultiReso = fecp->ESW_DMCR & 0x0000000f; ++ BroadReso = fecp->ESW_DBCR & 0x0000000f; ++ FTransmit = fecp->ESW_PER & 0x0000000f; ++ FReceive = (fecp->ESW_PER & 0x000f0000) >> 16; ++ ++ switch (portnum) { ++ case 0: ++ port_alstatus->link_status = 1; ++ port_alstatus->block_status = PortBlocking & 1; ++ port_alstatus->learn_status = PortLearning & 1; ++ port_alstatus->vlan_verify = VlanVerify & 1; ++ port_alstatus->discard_unknown = DiscardUnknown & 1; ++ port_alstatus->multi_reso = MultiReso & 1; ++ port_alstatus->broad_reso = BroadReso & 1; ++ port_alstatus->ftransmit = FTransmit & 1; ++ port_alstatus->freceive = FReceive & 1; ++ break; ++ case 1: ++ port_alstatus->link_status = ++ ports_link_status.port1_link_status; ++ port_alstatus->block_status = (PortBlocking >> 1) & 1; ++ port_alstatus->learn_status = (PortLearning >> 1) & 1; ++ port_alstatus->vlan_verify = (VlanVerify >> 1) & 1; ++ port_alstatus->discard_unknown = (DiscardUnknown >> 1) & 1; ++ port_alstatus->multi_reso = (MultiReso >> 1) & 1; ++ port_alstatus->broad_reso = (BroadReso >> 1) & 1; ++ port_alstatus->ftransmit = (FTransmit >> 1) & 1; ++ port_alstatus->freceive = (FReceive >> 1) & 1; ++ break; ++ case 2: ++ port_alstatus->link_status = ++ ports_link_status.port2_link_status; ++ port_alstatus->block_status = (PortBlocking >> 2) & 1; ++ port_alstatus->learn_status = (PortLearning >> 2) & 1; ++ port_alstatus->vlan_verify = (VlanVerify >> 2) & 1; ++ port_alstatus->discard_unknown = (DiscardUnknown >> 2) & 1; ++ port_alstatus->multi_reso = (MultiReso >> 2) & 1; ++ port_alstatus->broad_reso = (BroadReso >> 2) & 1; ++ port_alstatus->ftransmit = (FTransmit >> 2) & 1; ++ port_alstatus->freceive = (FReceive >> 2) & 1; ++ break; ++ default: ++ printk(KERN_ERR "%s:do not support the port %d", ++ __func__, portnum); ++ break; ++ } ++ return 0; ++} ++ ++int esw_atable_get_entry_port_number(struct switch_enet_private *fep, ++ unsigned char *mac_addr, unsigned char *port) ++{ ++ int block_index, block_index_end, entry; ++ unsigned long read_lo, read_hi; ++ unsigned long mac_addr_lo, mac_addr_hi; ++ ++ mac_addr_lo = (unsigned long)((mac_addr[3]<<24) | (mac_addr[2]<<16) | ++ (mac_addr[1]<<8) | mac_addr[0]); ++ mac_addr_hi = (unsigned long)((mac_addr[5]<<8) | (mac_addr[4])); ++ ++ block_index = GET_BLOCK_PTR(crc8_calc(mac_addr)); ++ block_index_end = block_index + ATABLE_ENTRY_PER_SLOT; ++ ++ /* now search all the entries in the selected block */ ++ for (entry = block_index; entry < block_index_end; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ if ((read_lo == mac_addr_lo) && ++ ((read_hi & 0x0000ffff) == ++ (mac_addr_hi & 0x0000ffff))) { ++ /* found the correct address */ ++ if ((read_hi & (1 << 16)) && (!(read_hi & (1 << 17)))) ++ *port = AT_EXTRACT_PORT(read_hi); ++ break; ++ } else ++ *port = -1; ++ } ++ ++ return 0; ++} ++ ++int esw_get_mac_address_lookup_table(struct switch_enet_private *fep, ++ unsigned long *tableaddr, unsigned long *dnum, unsigned long *snum) ++{ ++ unsigned long read_lo, read_hi; ++ unsigned long entry; ++ unsigned long dennum = 0; ++ unsigned long sennum = 0; ++ ++ for (entry = 0; entry < ESW_ATABLE_MEM_NUM_ENTRIES; entry++) { ++ read_atable(fep, entry, &read_lo, &read_hi); ++ if ((read_hi & (1 << 17)) && (read_hi & (1 << 16))) { ++ /* static entry */ ++ *(tableaddr + (2047 - sennum) * 11) = entry; ++ *(tableaddr + (2047 - sennum) * 11 + 2) = ++ read_lo & 0x000000ff; ++ *(tableaddr + (2047 - sennum) * 11 + 3) = ++ (read_lo & 0x0000ff00) >> 8; ++ *(tableaddr + (2047 - sennum) * 11 + 4) = ++ (read_lo & 0x00ff0000) >> 16; ++ *(tableaddr + (2047 - sennum) * 11 + 5) = ++ (read_lo & 0xff000000) >> 24; ++ *(tableaddr + (2047 - sennum) * 11 + 6) = ++ read_hi & 0x000000ff; ++ *(tableaddr + (2047 - sennum) * 11 + 7) = ++ (read_hi & 0x0000ff00) >> 8; ++ *(tableaddr + (2047 - sennum) * 11 + 8) = ++ AT_EXTRACT_PORTMASK(read_hi); ++ *(tableaddr + (2047 - sennum) * 11 + 9) = ++ AT_EXTRACT_PRIO(read_hi); ++ sennum++; ++ } else if ((read_hi & (1 << 16)) && (!(read_hi & (1 << 17)))) { ++ /* dynamic entry */ ++ *(tableaddr + dennum * 11) = entry; ++ *(tableaddr + dennum * 11 + 2) = read_lo & 0xff; ++ *(tableaddr + dennum * 11 + 3) = ++ (read_lo & 0x0000ff00) >> 8; ++ *(tableaddr + dennum * 11 + 4) = ++ (read_lo & 0x00ff0000) >> 16; ++ *(tableaddr + dennum * 11 + 5) = ++ (read_lo & 0xff000000) >> 24; ++ *(tableaddr + dennum * 11 + 6) = read_hi & 0xff; ++ *(tableaddr + dennum * 11 + 7) = ++ (read_hi & 0x0000ff00) >> 8; ++ *(tableaddr + dennum * 11 + 8) = ++ AT_EXTRACT_PORT(read_hi); ++ *(tableaddr + dennum * 11 + 9) = ++ AT_EXTRACT_TIMESTAMP(read_hi); ++ dennum++; ++ } ++ } ++ ++ *dnum = dennum; ++ *snum = sennum; ++ return 0; ++} ++ ++/*----------------------------------------------------------------------------*/ ++/* The timer should create an interrupt every 4 seconds*/ ++static void l2switch_aging_timer(unsigned long data) ++{ ++ struct switch_enet_private *fep; ++ ++ fep = (struct switch_enet_private *)data; ++ ++ if (fep) { ++ TIMEINCREMENT(fep->currTime); ++ fep->timeChanged++; ++ } ++ ++ mod_timer(&fep->timer_aging, jiffies + LEARNING_AGING_TIMER); ++} ++ ++/* ----------------------------------------------------------------------- */ ++void esw_check_rxb_txb_interrupt(struct switch_enet_private *fep) ++{ ++ volatile switch_t *fecp; ++ fecp = fep->hwp; ++ ++ /*Enable Forced forwarding for port 1*/ ++ fecp->ESW_P0FFEN = MCF_ESW_P0FFEN_FEN | ++ MCF_ESW_P0FFEN_FD(1); ++ /*Disable learning for all ports*/ ++ MCF_ESW_IMR = MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF | ++ MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF; ++} ++ ++/*----------------------------------------------------------------*/ ++static int switch_enet_learning(void *arg) ++{ ++ struct switch_enet_private *fep = arg; ++ volatile switch_t *fecp; ++ ++ fecp = fep->hwp; ++ while (!kthread_should_stop()) { ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ /* check learning record valid */ ++ if (fecp->ESW_LSR) ++ esw_atable_dynamicms_learn_migration(fep, ++ fep->currTime); ++ else ++ schedule_timeout(HZ/100); ++ } ++ ++ return 0; ++} ++ ++static int switch_enet_ioctl(struct net_device *dev, ++ struct ifreq *ifr, int cmd) ++{ ++ struct switch_enet_private *fep = netdev_priv(dev); ++ volatile switch_t *fecp; ++ int ret = 0; ++ ++ fecp = (volatile switch_t *)dev->base_addr; ++ ++ switch (cmd) { ++ /*------------------------------------------------------------*/ ++ case ESW_SET_PORTENABLE_CONF: ++ { ++ eswIoctlPortEnableConfig configData; ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, ++ sizeof(eswIoctlPortEnableConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_enable_config(fep, ++ configData.port, ++ configData.tx_enable, ++ configData.rx_enable); ++ } ++ break; ++ case ESW_SET_BROADCAST_CONF: ++ { ++ eswIoctlPortConfig configData; ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPortConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_broadcast_config(fep, ++ configData.port, configData.enable); ++ } ++ break; ++ ++ case ESW_SET_MULTICAST_CONF: ++ { ++ eswIoctlPortConfig configData; ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPortConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_multicast_config(fep, ++ configData.port, configData.enable); ++ } ++ break; ++ ++ case ESW_SET_BLOCKING_CONF: ++ { ++ eswIoctlPortConfig configData; ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPortConfig)); ++ ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_blocking_config(fep, ++ configData.port, configData.enable); ++ } ++ break; ++ ++ case ESW_SET_LEARNING_CONF: ++ { ++ eswIoctlPortConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPortConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_learning_config(fep, ++ configData.port, configData.enable); ++ } ++ break; ++ ++ case ESW_SET_PORT_ENTRY_EMPTY: ++ { ++ unsigned long portnum; ++ ++ ret = copy_from_user(&portnum, ++ ifr->ifr_data, sizeof(portnum)); ++ if (ret) ++ return -EFAULT; ++ esw_atable_dynamicms_del_entries_for_port(fep, portnum); ++ } ++ break; ++ ++ case ESW_SET_OTHER_PORT_ENTRY_EMPTY: ++ { ++ unsigned long portnum; ++ ++ ret = copy_from_user(&portnum, ++ ifr->ifr_data, sizeof(portnum)); ++ if (ret) ++ return -EFAULT; ++ ++ esw_atable_dynamicms_del_entries_for_other_port(fep, portnum); ++ } ++ break; ++ ++ case ESW_SET_IP_SNOOP_CONF: ++ { ++ eswIoctlIpsnoopConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlIpsnoopConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_ip_snoop_config(fep, configData.mode, ++ configData.ip_header_protocol); ++ } ++ break; ++ ++ case ESW_SET_PORT_SNOOP_CONF: ++ { ++ eswIoctlPortsnoopConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPortsnoopConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_tcpudp_port_snoop_config(fep, configData.mode, ++ configData.compare_port, ++ configData.compare_num); ++ } ++ break; ++ ++ case ESW_SET_PORT_MIRROR_CONF_PORT_MATCH: ++ { ++ struct eswIoctlMirrorCfgPortMatch configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(configData)); ++ if (ret) ++ return -EFAULT; ++ ret = esw_port_mirroring_config_port_match(fep, ++ configData.mirror_port, configData.port_match_en, ++ configData.port); ++ } ++ break; ++ ++ case ESW_SET_PORT_MIRROR_CONF: ++ { ++ eswIoctlPortMirrorConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPortMirrorConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_mirroring_config(fep, ++ configData.mirror_port, configData.port, ++ configData.mirror_enable, ++ configData.src_mac, configData.des_mac, ++ configData.egress_en, configData.ingress_en, ++ configData.egress_mac_src_en, ++ configData.egress_mac_des_en, ++ configData.ingress_mac_src_en, ++ configData.ingress_mac_des_en); ++ } ++ break; ++ ++ case ESW_SET_PORT_MIRROR_CONF_ADDR_MATCH: ++ { ++ struct eswIoctlMirrorCfgAddrMatch configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(configData)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_port_mirroring_config_addr_match(fep, ++ configData.mirror_port, configData.addr_match_en, ++ configData.mac_addr); ++ } ++ break; ++ ++ case ESW_SET_PIRORITY_VLAN: ++ { ++ eswIoctlPriorityVlanConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPriorityVlanConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_framecalssify_vlan_priority_lookup(fep, ++ configData.port, configData.func_enable, ++ configData.vlan_pri_table_num, ++ configData.vlan_pri_table_value); ++ } ++ break; ++ ++ case ESW_SET_PIRORITY_IP: ++ { ++ eswIoctlPriorityIPConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPriorityIPConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_framecalssify_ip_priority_lookup(fep, ++ configData.port, configData.func_enable, ++ configData.ipv4_en, configData.ip_priority_num, ++ configData.ip_priority_value); ++ } ++ break; ++ ++ case ESW_SET_PIRORITY_MAC: ++ { ++ eswIoctlPriorityMacConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPriorityMacConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_framecalssify_mac_priority_lookup(fep, ++ configData.port); ++ } ++ break; ++ ++ case ESW_SET_PIRORITY_DEFAULT: ++ { ++ eswIoctlPriorityDefaultConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlPriorityDefaultConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_frame_calssify_priority_init(fep, ++ configData.port, configData.priority_value); ++ } ++ break; ++ ++ case ESW_SET_P0_FORCED_FORWARD: ++ { ++ eswIoctlP0ForcedForwardConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlP0ForcedForwardConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_forced_forward(fep, configData.port1, ++ configData.port2, configData.enable); ++ } ++ break; ++ ++ case ESW_SET_BRIDGE_CONFIG: ++ { ++ unsigned long configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ ++ esw_bridge_port_configure(fep, configData); ++ } ++ break; ++ ++ case ESW_SET_SWITCH_MODE: ++ { ++ unsigned long configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ ++ esw_switch_mode_configure(fep, configData); ++ } ++ break; ++ ++ case ESW_SET_OUTPUT_QUEUE_MEMORY: ++ { ++ eswIoctlOutputQueue configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlOutputQueue)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_set_output_queue_memory(fep, ++ configData.fun_num, &configData.sOutputQueue); ++ } ++ break; ++ ++ case ESW_SET_VLAN_OUTPUT_PROCESS: ++ { ++ eswIoctlVlanOutputConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlVlanOutputConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_vlan_output_process(fep, ++ configData.port, configData.mode); ++ } ++ break; ++ ++ case ESW_SET_VLAN_INPUT_PROCESS: ++ { ++ eswIoctlVlanInputConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, ++ sizeof(eswIoctlVlanInputConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_vlan_input_process(fep, configData.port, ++ configData.mode, configData.port_vlanid); ++ } ++ break; ++ ++ case ESW_SET_VLAN_DOMAIN_VERIFICATION: ++ { ++ eswIoctlVlanVerificationConfig configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, ++ sizeof(eswIoctlVlanVerificationConfig)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_set_vlan_verification( ++ fep, configData.port, ++ configData.vlan_domain_verify_en, ++ configData.vlan_discard_unknown_en); ++ } ++ break; ++ ++ case ESW_SET_VLAN_RESOLUTION_TABLE: ++ { ++ eswIoctlVlanResoultionTable configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, ++ sizeof(eswIoctlVlanResoultionTable)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_set_vlan_resolution_table( ++ fep, configData.port_vlanid, ++ configData.vlan_domain_num, ++ configData.vlan_domain_port); ++ ++ } ++ break; ++ ++ case ESW_SET_VLAN_ID: ++ { ++ unsigned long configData; ++ ret = copy_from_user(&configData, ifr->ifr_data, ++ sizeof(configData)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_set_vlan_id(fep, configData); ++ } ++ break; ++ ++ case ESW_SET_VLAN_ID_CLEARED: ++ { ++ unsigned long configData; ++ ret = copy_from_user(&configData, ifr->ifr_data, ++ sizeof(configData)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_set_vlan_id_cleared(fep, configData); ++ } ++ break; ++ ++ case ESW_SET_PORT_IN_VLAN_ID: ++ { ++ eswIoctlVlanResoultionTable configData; ++ ++ ret = copy_from_user(&configData, ifr->ifr_data, ++ sizeof(configData)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_set_port_in_vlan_id(fep, configData); ++ } ++ break; ++ ++ /*--------------------------------------------------------------------*/ ++ case ESW_UPDATE_STATIC_MACTABLE: ++ { ++ eswIoctlUpdateStaticMACtable configData; ++ ++ ret = copy_from_user(&configData, ++ ifr->ifr_data, sizeof(eswIoctlUpdateStaticMACtable)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_update_atable_static(configData.mac_addr, ++ configData.port, configData.priority, fep); ++ } ++ break; ++ ++ case ESW_CLEAR_ALL_MACTABLE: ++ { ++ esw_clear_atable(fep); ++ } ++ break; ++ ++ /*-------------------get----------------------------------------------*/ ++ case ESW_GET_STATISTICS_STATUS: ++ { ++ esw_statistics_status Statistics; ++ esw_port_statistics_status PortSta; ++ int i; ++ ++ ret = esw_get_statistics_status(fep, &Statistics); ++ if (ret != 0) { ++ printk(KERN_ERR "%s: cmd %x fail\n", __func__, cmd); ++ return -1; ++ } ++ printk(KERN_INFO "DISCN : %10ld DISCB : %10ld\n", ++ Statistics.ESW_DISCN, Statistics.ESW_DISCB); ++ printk(KERN_INFO "NDISCN: %10ld NDISCB: %10ld\n", ++ Statistics.ESW_NDISCN, Statistics.ESW_NDISCB); ++ ++ for (i = 0; i < 3; i++) { ++ ret = esw_get_port_statistics_status(fep, i, ++ &PortSta); ++ if (ret != 0) { ++ printk(KERN_ERR "%s: cmd %x fail\n", ++ __func__, cmd); ++ return -1; ++ } ++ printk(KERN_INFO "port %d: POQC : %ld\n", ++ i, PortSta.MCF_ESW_POQC); ++ printk(KERN_INFO " PMVID : %ld\n", ++ PortSta.MCF_ESW_PMVID); ++ printk(KERN_INFO " PMVTAG: %ld\n", ++ PortSta.MCF_ESW_PMVTAG); ++ printk(KERN_INFO " PBL : %ld\n", ++ PortSta.MCF_ESW_PBL); ++ } ++ } ++ break; ++ ++ case ESW_GET_LEARNING_CONF: ++ { ++ unsigned long PortLearning; ++ ++ esw_get_port_learning(fep, &PortLearning); ++ ret = copy_to_user(ifr->ifr_data, &PortLearning, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_BLOCKING_CONF: ++ { ++ unsigned long PortBlocking; ++ ++ esw_get_port_blocking(fep, &PortBlocking); ++ ret = copy_to_user(ifr->ifr_data, &PortBlocking, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_MULTICAST_CONF: ++ { ++ unsigned long PortMulticast; ++ ++ esw_get_port_multicast(fep, &PortMulticast); ++ ret = copy_to_user(ifr->ifr_data, &PortMulticast, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_BROADCAST_CONF: ++ { ++ unsigned long PortBroadcast; ++ ++ esw_get_port_broadcast(fep, &PortBroadcast); ++ ret = copy_to_user(ifr->ifr_data, &PortBroadcast, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_PORTENABLE_CONF: ++ { ++ unsigned long PortEnable; ++ ++ esw_get_port_enable(fep, &PortEnable); ++ ret = copy_to_user(ifr->ifr_data, &PortEnable, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_IP_SNOOP_CONF: ++ { ++ unsigned long ESW_IPSNP[8]; ++ int i; ++ ++ esw_get_ip_snoop_config(fep, (unsigned long *)ESW_IPSNP); ++ printk(KERN_INFO "IP Protocol Mode Type\n"); ++ for (i = 0; i < 8; i++) { ++ if (ESW_IPSNP[i] != 0) ++ printk(KERN_INFO "%3ld " ++ "%1ld %s\n", ++ (ESW_IPSNP[i] >> 8) & 0xff, ++ (ESW_IPSNP[i] >> 1) & 3, ++ ESW_IPSNP[i] & 1 ? "Active" : ++ "Inactive"); ++ } ++ } ++ break; ++ ++ case ESW_GET_PORT_SNOOP_CONF: ++ { ++ unsigned long ESW_PSNP[8]; ++ int i; ++ ++ esw_get_tcpudp_port_snoop_config(fep, ++ (unsigned long *)ESW_PSNP); ++ printk(KERN_INFO "TCP/UDP Port SrcCompare DesCompare " ++ "Mode Type\n"); ++ for (i = 0; i < 8; i++) { ++ if (ESW_PSNP[i] != 0) ++ printk(KERN_INFO "%5ld %s " ++ "%s %1ld %s\n", ++ (ESW_PSNP[i] >> 16) & 0xffff, ++ (ESW_PSNP[i] >> 4) & 1 ? "Y" : "N", ++ (ESW_PSNP[i] >> 3) & 1 ? "Y" : "N", ++ (ESW_PSNP[i] >> 1) & 3, ++ ESW_PSNP[i] & 1 ? "Active" : ++ "Inactive"); ++ } ++ } ++ break; ++ ++ case ESW_GET_PORT_MIRROR_CONF: ++ esw_get_port_mirroring(fep); ++ break; ++ ++ case ESW_GET_P0_FORCED_FORWARD: ++ { ++ unsigned long ForceForward; ++ ++ esw_get_forced_forward(fep, &ForceForward); ++ ret = copy_to_user(ifr->ifr_data, &ForceForward, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_SWITCH_MODE: ++ { ++ unsigned long Config; ++ ++ esw_get_switch_mode(fep, &Config); ++ ret = copy_to_user(ifr->ifr_data, &Config, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_BRIDGE_CONFIG: ++ { ++ unsigned long Config; ++ ++ esw_get_bridge_port(fep, &Config); ++ ret = copy_to_user(ifr->ifr_data, &Config, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ case ESW_GET_OUTPUT_QUEUE_STATUS: ++ { ++ esw_output_queue_status Config; ++ esw_get_output_queue_status(fep, ++ &Config); ++ ret = copy_to_user(ifr->ifr_data, &Config, ++ sizeof(esw_output_queue_status)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_VLAN_OUTPUT_PROCESS: ++ { ++ unsigned long Config; ++ int tmp; ++ int i; ++ ++ esw_get_vlan_output_config(fep, &Config); ++ ++ for (i = 0; i < 3; i++) { ++ tmp = (Config >> (i << 1)) & 3; ++ ++ if (tmp != 0) ++ printk(KERN_INFO "port %d: vlan output " ++ "manipulation enable (mode %d)\n", ++ i, tmp); ++ else ++ printk(KERN_INFO "port %d: vlan output " ++ "manipulation disable\n", i); ++ } ++ } ++ break; ++ ++ case ESW_GET_VLAN_INPUT_PROCESS: ++ { ++ eswIoctlVlanInputStatus Config; ++ int i; ++ ++ esw_get_vlan_input_config(fep, &Config); ++ ++ for (i = 0; i < 3; i++) { ++ if (((Config.ESW_VIMEN >> i) & 1) == 0) ++ printk(KERN_INFO "port %d: vlan input " ++ "manipulation disable\n", i); ++ else ++ printk("port %d: vlan input manipulation enable" ++ " (mode %ld, vlan id %ld)\n", i, ++ (((Config.ESW_VIMSEL >> (i << 1)) & 3) ++ + 1), Config.ESW_PID[i]); ++ } ++ } ++ break; ++ ++ case ESW_GET_VLAN_RESOLUTION_TABLE: ++ { ++ struct eswVlanTableItem vtableitem; ++ unsigned char tmp0, tmp1, tmp2; ++ int i; ++ ++ esw_get_vlan_resolution_table(fep, &vtableitem); ++ ++ printk(KERN_INFO "VLAN Name VLAN Id Ports\n"); ++ for (i = 0; i < vtableitem.valid_num; i++) { ++ tmp0 = vtableitem.table[i].vlan_domain_port & 1; ++ tmp1 = (vtableitem.table[i].vlan_domain_port >> 1) & 1; ++ tmp2 = (vtableitem.table[i].vlan_domain_port >> 2) & 1; ++ printk(KERN_INFO "%2d %4d %s%s%s\n", ++ i, vtableitem.table[i].port_vlanid, ++ tmp0 ? "0 " : "", tmp1 ? "1 " : "", ++ tmp2 ? "2" : ""); ++ } ++ } ++ break; ++ ++ case ESW_GET_VLAN_DOMAIN_VERIFICATION: ++ { ++ unsigned long Config; ++ ++ esw_get_vlan_verification(fep, &Config); ++ ret = copy_to_user(ifr->ifr_data, &Config, ++ sizeof(unsigned long)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_ENTRY_PORT_NUMBER: ++ { ++ unsigned char mac_addr[6]; ++ unsigned char portnum; ++ ++ ret = copy_from_user(mac_addr, ++ ifr->ifr_data, sizeof(mac_addr)); ++ if (ret) ++ return -EFAULT; ++ ++ ret = esw_atable_get_entry_port_number(fep, mac_addr, ++ &portnum); ++ ++ ret = copy_to_user(ifr->ifr_data, &portnum, ++ sizeof(unsigned char)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_LOOKUP_TABLE: ++ { ++ unsigned long *ConfigData; ++ unsigned long dennum, sennum; ++ int i; ++ int tmp; ++ ++ ConfigData = kmalloc(sizeof(struct eswAddrTableEntryExample) * ++ ESW_ATABLE_MEM_NUM_ENTRIES, GFP_KERNEL); ++ ret = esw_get_mac_address_lookup_table(fep, ConfigData, ++ &dennum, &sennum); ++ printk(KERN_INFO "Dynamic entries number: %ld\n", dennum); ++ printk(KERN_INFO "Static entries number: %ld\n", sennum); ++ printk(KERN_INFO "Type MAC address Port Timestamp\n"); ++ for (i = 0; i < dennum; i++) { ++ printk(KERN_INFO "dynamic " ++ "%02lx-%02lx-%02lx-%02lx-%02lx-%02lx " ++ "%01lx %4ld\n", *(ConfigData + i * 11 + 2), ++ *(ConfigData + i * 11 + 3), ++ *(ConfigData + i * 11 + 4), ++ *(ConfigData + i * 11 + 5), ++ *(ConfigData + i * 11 + 6), ++ *(ConfigData + i * 11 + 7), ++ *(ConfigData + i * 11 + 8), ++ *(ConfigData + i * 11 + 9)); ++ } ++ ++ if (sennum != 0) ++ printk(KERN_INFO "Type MAC address" ++ " Port Priority\n"); ++ ++ for (i = 0; i < sennum; i++) { ++ printk(KERN_INFO "static %02lx-%02lx-%02lx-%02lx" ++ "-%02lx-%02lx ", ++ *(ConfigData + (2047 - i) * 11 + 2), ++ *(ConfigData + (2047 - i) * 11 + 3), ++ *(ConfigData + (2047 - i) * 11 + 4), ++ *(ConfigData + (2047 - i) * 11 + 5), ++ *(ConfigData + (2047 - i) * 11 + 6), ++ *(ConfigData + (2047 - i) * 11 + 7)); ++ ++ tmp = *(ConfigData + (2047 - i) * 11 + 8); ++ if ((tmp == 0) || (tmp == 2) || (tmp == 4)) ++ printk("%01x ", tmp >> 1); ++ else if (tmp == 3) ++ printk("0,1 "); ++ else if (tmp == 5) ++ printk("0,2 "); ++ else if (tmp == 6) ++ printk("1,2 "); ++ ++ printk("%4ld\n", *(ConfigData + (2047 - i) * 11 + 9)); ++ } ++ kfree(ConfigData); ++ } ++ break; ++ ++ case ESW_GET_PORT_STATUS: ++ { ++ unsigned long PortBlocking; ++ ++ esw_get_port_blocking(fep, &PortBlocking); ++ ++ ports_link_status.port0_block_status = PortBlocking & 1; ++ ports_link_status.port1_block_status = (PortBlocking >> 1) & 1; ++ ports_link_status.port2_block_status = PortBlocking >> 2; ++ ++ ret = copy_to_user(ifr->ifr_data, &ports_link_status, ++ sizeof(ports_link_status)); ++ if (ret) ++ return -EFAULT; ++ } ++ break; ++ ++ case ESW_GET_PORT_ALL_STATUS: ++ { ++ unsigned char portnum; ++ struct port_all_status port_astatus; ++ ++ ret = copy_from_user(&portnum, ++ ifr->ifr_data, sizeof(portnum)); ++ if (ret) ++ return -EFAULT; ++ ++ esw_get_port_all_status(fep, portnum, &port_astatus); ++ printk(KERN_INFO "Port %d status:\n", portnum); ++ printk(KERN_INFO "Link:%-4s Blocking:%1s " ++ "Learning:%1s\n", ++ port_astatus.link_status ? "Up" : "Down", ++ port_astatus.block_status ? "Y" : "N", ++ port_astatus.learn_status ? "N" : "Y"); ++ printk(KERN_INFO "VLAN Verify:%1s Discard Unknown:%1s " ++ "Multicast Res:%1s\n", ++ port_astatus.vlan_verify ? "Y" : "N", ++ port_astatus.discard_unknown ? "Y" : "N", ++ port_astatus.multi_reso ? "Y" : "N"); ++ printk(KERN_INFO "Broadcast Res:%1s Transmit:%-7s " ++ "Receive:%7s\n", ++ port_astatus.broad_reso ? "Y" : "N", ++ port_astatus.ftransmit ? "Enable" : "Disable", ++ port_astatus.freceive ? "Enable" : "Disable"); ++ ++ } ++ break; ++ ++ case ESW_GET_USER_PID: ++ { ++ long get_pid = 0; ++ ret = copy_from_user(&get_pid, ++ ifr->ifr_data, sizeof(get_pid)); ++ ++ if (ret) ++ return -EFAULT; ++ user_pid = get_pid; ++ } ++ break; ++ /*------------------------------------------------------------------*/ ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return ret; ++} ++ ++static netdev_tx_t switch_enet_start_xmit(struct sk_buff *skb, ++ struct net_device *dev) ++{ ++ struct switch_enet_private *fep; ++ volatile switch_t *fecp; ++ cbd_t *bdp; ++ unsigned short status; ++ unsigned long flags; ++ ++ fep = netdev_priv(dev); ++ fecp = (switch_t *)fep->hwp; ++ ++ spin_lock_irqsave(&fep->hw_lock, flags); ++ /* Fill in a Tx ring entry */ ++ bdp = fep->cur_tx; ++ ++ status = bdp->cbd_sc; ++ ++ /* Clear all of the status flags. ++ */ ++ status &= ~BD_ENET_TX_STATS; ++ ++ /* Set buffer length and buffer pointer. ++ */ ++ bdp->cbd_bufaddr = __pa(skb->data); ++ bdp->cbd_datlen = skb->len; ++ ++ /* ++ * On some FEC implementations data must be aligned on ++ * 4-byte boundaries. Use bounce buffers to copy data ++ * and get it aligned. Ugh. ++ */ ++ if (bdp->cbd_bufaddr & 0x3) { ++ unsigned int index1; ++ index1 = bdp - fep->tx_bd_base; ++ ++ memcpy(fep->tx_bounce[index1], ++ (void *)skb->data, bdp->cbd_datlen); ++ bdp->cbd_bufaddr = __pa(fep->tx_bounce[index1]); ++ } ++ ++ /* Save skb pointer. */ ++ fep->tx_skbuff[fep->skb_cur] = skb; ++ ++ dev->stats.tx_bytes += skb->len; ++ fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; ++ ++ /* Push the data cache so the CPM does not get stale memory ++ * data. ++ */ ++ flush_dcache_range((unsigned long)skb->data, ++ (unsigned long)skb->data + skb->len); ++ ++ /* Send it on its way. Tell FEC it's ready, interrupt when done, ++ * it's the last BD of the frame, and to put the CRC on the end. ++ */ ++ ++ status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR ++ | BD_ENET_TX_LAST | BD_ENET_TX_TC); ++ bdp->cbd_sc = status; ++ dev->trans_start = jiffies; ++ ++ /* Trigger transmission start */ ++ fecp->fec_x_des_active = MCF_ESW_TDAR_X_DES_ACTIVE; ++ ++ /* If this was the last BD in the ring, ++ * start at the beginning again.*/ ++ if (status & BD_ENET_TX_WRAP) ++ bdp = fep->tx_bd_base; ++ else ++ bdp++; ++ ++ if (bdp == fep->dirty_tx) { ++ fep->tx_full = 1; ++ netif_stop_queue(dev); ++ printk(KERN_ERR "%s: net stop\n", __func__); ++ } ++ ++ fep->cur_tx = (cbd_t *)bdp; ++ ++ spin_unlock_irqrestore(&fep->hw_lock, flags); ++ ++ return NETDEV_TX_OK; ++} ++ ++static void switch_timeout(struct net_device *dev) ++{ ++ struct switch_enet_private *fep = netdev_priv(dev); ++ ++ printk(KERN_ERR "%s: transmit timed out.\n", dev->name); ++ dev->stats.tx_errors++; ++ switch_restart(dev, fep->full_duplex); ++ netif_wake_queue(dev); ++} ++ ++/* The interrupt handler. ++ * This is called from the MPC core interrupt. ++ */ ++static irqreturn_t switch_enet_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = dev_id; ++ volatile switch_t *fecp; ++ uint int_events; ++ irqreturn_t ret = IRQ_NONE; ++ ++ fecp = (switch_t *)dev->base_addr; ++ ++ /* Get the interrupt events that caused us to be here. ++ */ ++ do { ++ int_events = fecp->switch_ievent; ++ fecp->switch_ievent = int_events; ++ /* Handle receive event in its own function. */ ++ ++ /* Transmit OK, or non-fatal error. Update the buffer ++ descriptors. Switch handles all errors, we just discover ++ them as part of the transmit process. ++ */ ++ if (int_events & MCF_ESW_ISR_OD0) ++ ret = IRQ_HANDLED; ++ ++ if (int_events & MCF_ESW_ISR_OD1) ++ ret = IRQ_HANDLED; ++ ++ if (int_events & MCF_ESW_ISR_OD2) ++ ret = IRQ_HANDLED; ++ ++ if (int_events & MCF_ESW_ISR_RXB) ++ ret = IRQ_HANDLED; ++ ++ if (int_events & MCF_ESW_ISR_RXF) { ++ ret = IRQ_HANDLED; ++ switch_enet_rx(dev); ++ } ++ ++ if (int_events & MCF_ESW_ISR_TXB) ++ ret = IRQ_HANDLED; ++ ++ if (int_events & MCF_ESW_ISR_TXF) { ++ ret = IRQ_HANDLED; ++ switch_enet_tx(dev); ++ } ++ ++ } while (int_events); ++ ++ return ret; ++} ++ ++static void switch_enet_tx(struct net_device *dev) ++{ ++ struct switch_enet_private *fep; ++ cbd_t *bdp; ++ unsigned short status; ++ struct sk_buff *skb; ++ ++ fep = netdev_priv(dev); ++ spin_lock_irq(&fep->hw_lock); ++ bdp = fep->dirty_tx; ++ ++ while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { ++ if (bdp == fep->cur_tx && fep->tx_full == 0) ++ break; ++ ++ skb = fep->tx_skbuff[fep->skb_dirty]; ++ /* Check for errors. */ ++ if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | ++ BD_ENET_TX_RL | BD_ENET_TX_UN | ++ BD_ENET_TX_CSL)) { ++ dev->stats.tx_errors++; ++ if (status & BD_ENET_TX_HB) /* No heartbeat */ ++ dev->stats.tx_heartbeat_errors++; ++ if (status & BD_ENET_TX_LC) /* Late collision */ ++ dev->stats.tx_window_errors++; ++ if (status & BD_ENET_TX_RL) /* Retrans limit */ ++ dev->stats.tx_aborted_errors++; ++ if (status & BD_ENET_TX_UN) /* Underrun */ ++ dev->stats.tx_fifo_errors++; ++ if (status & BD_ENET_TX_CSL) /* Carrier lost */ ++ dev->stats.tx_carrier_errors++; ++ } else { ++ dev->stats.tx_packets++; ++ } ++ ++ /* Deferred means some collisions occurred during transmit, ++ * but we eventually sent the packet OK. ++ */ ++ if (status & BD_ENET_TX_DEF) ++ dev->stats.collisions++; ++ ++ /* Free the sk buffer associated with this last transmit. ++ */ ++ dev_kfree_skb_any(skb); ++ fep->tx_skbuff[fep->skb_dirty] = NULL; ++ fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; ++ ++ /* Update pointer to next buffer descriptor to be transmitted. ++ */ ++ if (status & BD_ENET_TX_WRAP) ++ bdp = fep->tx_bd_base; ++ else ++ bdp++; ++ ++ /* Since we have freed up a buffer, the ring is no longer ++ * full. ++ */ ++ if (fep->tx_full) { ++ fep->tx_full = 0; ++ printk(KERN_ERR "%s: tx full is zero\n", __func__); ++ if (netif_queue_stopped(dev)) ++ netif_wake_queue(dev); ++ } ++ } ++ fep->dirty_tx = (cbd_t *)bdp; ++ spin_unlock_irq(&fep->hw_lock); ++} ++ ++ ++/* During a receive, the cur_rx points to the current incoming buffer. ++ * When we update through the ring, if the next incoming buffer has ++ * not been given to the system, we just set the empty indicator, ++ * effectively tossing the packet. ++ */ ++static void switch_enet_rx(struct net_device *dev) ++{ ++ struct switch_enet_private *fep; ++ volatile switch_t *fecp; ++ cbd_t *bdp; ++ unsigned short status; ++ struct sk_buff *skb; ++ ushort pkt_len; ++ __u8 *data; ++ ++ fep = netdev_priv(dev); ++ /*fecp = (volatile switch_t *)dev->base_addr;*/ ++ fecp = (volatile switch_t *)fep->hwp; ++ ++ spin_lock_irq(&fep->hw_lock); ++ /* First, grab all of the stats for the incoming packet. ++ * These get messed up if we get called due to a busy condition. ++ */ ++ bdp = fep->cur_rx; ++ ++ while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { ++ ++ /* Since we have allocated space to hold a complete frame, ++ * the last indicator should be set. ++ * */ ++ if ((status & BD_ENET_RX_LAST) == 0) ++ printk(KERN_ERR "SWITCH ENET: rcv is not +last\n"); ++ ++ if (!fep->opened) ++ goto rx_processing_done; ++ ++ /* Check for errors. */ ++ if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | ++ BD_ENET_RX_CR | BD_ENET_RX_OV)) { ++ dev->stats.rx_errors++; ++ if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { ++ /* Frame too long or too short. */ ++ dev->stats.rx_length_errors++; ++ } ++ if (status & BD_ENET_RX_NO) /* Frame alignment */ ++ dev->stats.rx_frame_errors++; ++ if (status & BD_ENET_RX_CR) /* CRC Error */ ++ dev->stats.rx_crc_errors++; ++ if (status & BD_ENET_RX_OV) /* FIFO overrun */ ++ dev->stats.rx_fifo_errors++; ++ } ++ /* Report late collisions as a frame error. ++ * On this error, the BD is closed, but we don't know what we ++ * have in the buffer. So, just drop this frame on the floor. ++ * */ ++ if (status & BD_ENET_RX_CL) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_frame_errors++; ++ goto rx_processing_done; ++ } ++ /* Process the incoming frame */ ++ dev->stats.rx_packets++; ++ pkt_len = bdp->cbd_datlen; ++ dev->stats.rx_bytes += pkt_len; ++ data = (__u8 *)__va(bdp->cbd_bufaddr); ++ ++ /* This does 16 byte alignment, exactly what we need. ++ * The packet length includes FCS, but we don't want to ++ * include that when passing upstream as it messes up ++ * bridging applications. ++ * */ ++ skb = dev_alloc_skb(pkt_len); ++ ++ if (skb == NULL) ++ dev->stats.rx_dropped++; ++ else { ++ skb_put(skb, pkt_len); /* Make room */ ++ skb_copy_to_linear_data(skb, data, pkt_len); ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_rx(skb); ++ } ++rx_processing_done: ++ ++ /* Clear the status flags for this buffer */ ++ status &= ~BD_ENET_RX_STATS; ++ ++ /* Mark the buffer empty */ ++ status |= BD_ENET_RX_EMPTY; ++ bdp->cbd_sc = status; ++ ++ /* Update BD pointer to next entry */ ++ if (status & BD_ENET_RX_WRAP) ++ bdp = fep->rx_bd_base; ++ else ++ bdp++; ++ ++ /* Doing this here will keep the FEC running while we process ++ * incoming frames. On a heavily loaded network, we should be ++ * able to keep up at the expense of system resources. ++ * */ ++ fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE; ++ } ++ fep->cur_rx = (cbd_t *)bdp; ++ ++ spin_unlock_irq(&fep->hw_lock); ++} ++ ++static int fec_mdio_transfer(struct mii_bus *bus, int phy_id, ++ int reg, int regval) ++{ ++ struct net_device *dev = bus->priv; ++ unsigned long flags; ++ struct switch_enet_private *fep; ++ int tries = 100; ++ int retval = 0; ++ ++ fep = netdev_priv(dev); ++ spin_lock_irqsave(&fep->mii_lock, flags); ++ ++ regval |= phy_id << 23; ++ MCF_FEC_MMFR0 = regval; ++ ++ /* wait for it to finish, this takes about 23 us on lite5200b */ ++ while (!(MCF_FEC_EIR0 & FEC_ENET_MII) && --tries) ++ udelay(5); ++ ++ if (!tries) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -ETIMEDOUT; ++ } ++ ++ MCF_FEC_EIR0 = FEC_ENET_MII; ++ retval = MCF_FEC_MMFR0; ++ spin_unlock_irqrestore(&fep->mii_lock, flags); ++ ++ return retval; ++} ++ ++ ++static int coldfire_fec_mdio_read(struct mii_bus *bus, ++ int phy_id, int reg) ++{ ++ int ret; ++ ret = fec_mdio_transfer(bus, phy_id, reg, ++ mk_mii_read(reg)); ++ return ret; ++} ++ ++static int coldfire_fec_mdio_write(struct mii_bus *bus, ++ int phy_id, int reg, u16 data) ++{ ++ return fec_mdio_transfer(bus, phy_id, reg, ++ mk_mii_write(reg, data)); ++} ++ ++static void switch_adjust_link1(struct net_device *dev) ++{ ++ struct switch_enet_private *priv = netdev_priv(dev); ++ struct phy_device *phydev1 = priv->phydev[0]; ++ int new_state = 0; ++ ++ if (phydev1->link != PHY_DOWN) { ++ if (phydev1->duplex != priv->phy1_duplex) { ++ new_state = 1; ++ priv->phy1_duplex = phydev1->duplex; ++ } ++ ++ if (phydev1->speed != priv->phy1_speed) { ++ new_state = 1; ++ priv->phy1_speed = phydev1->speed; ++ } ++ ++ if (priv->phy1_old_link == PHY_DOWN) { ++ new_state = 1; ++ priv->phy1_old_link = phydev1->link; ++ } ++ } else if (priv->phy1_old_link) { ++ new_state = 1; ++ priv->phy1_old_link = PHY_DOWN; ++ priv->phy1_speed = 0; ++ priv->phy1_duplex = -1; ++ } ++ ++ if (new_state) { ++ ports_link_status.port1_link_status = phydev1->link; ++ if (phydev1->link == PHY_DOWN) ++ esw_atable_dynamicms_del_entries_for_port(priv, 1); ++ ++ /*Send the new status to user space*/ ++ if (user_pid != 1) ++ sys_tkill(user_pid, SIGUSR1); ++ } ++} ++ ++static void switch_adjust_link2(struct net_device *dev) ++{ ++ struct switch_enet_private *priv = netdev_priv(dev); ++ struct phy_device *phydev2 = priv->phydev[1]; ++ int new_state = 0; ++ ++ if (phydev2->link != PHY_DOWN) { ++ if (phydev2->duplex != priv->phy2_duplex) { ++ new_state = 1; ++ priv->phy2_duplex = phydev2->duplex; ++ } ++ ++ if (phydev2->speed != priv->phy2_speed) { ++ new_state = 1; ++ priv->phy2_speed = phydev2->speed; ++ } ++ ++ if (priv->phy2_old_link == PHY_DOWN) { ++ new_state = 1; ++ priv->phy2_old_link = phydev2->link; ++ } ++ } else if (priv->phy2_old_link) { ++ new_state = 1; ++ priv->phy2_old_link = PHY_DOWN; ++ priv->phy2_speed = 0; ++ priv->phy2_duplex = -1; ++ } ++ ++ if (new_state) { ++ ports_link_status.port2_link_status = phydev2->link; ++ if (phydev2->link == PHY_DOWN) ++ esw_atable_dynamicms_del_entries_for_port(priv, 2); ++ ++ /*Send the new status to user space*/ ++ if (user_pid != 1) ++ sys_tkill(user_pid, SIGUSR1); ++ } ++} ++ ++static int coldfire_switch_init_phy(struct net_device *dev) ++{ ++ struct switch_enet_private *priv = netdev_priv(dev); ++ struct phy_device *phydev[SWITCH_EPORT_NUMBER] = {NULL, NULL}; ++ int i, startnode = 0; ++ ++ /* search for connect PHY device */ ++ for (i = 0; i < PHY_MAX_ADDR; i++) { ++ struct phy_device *const tmp_phydev = ++ priv->mdio_bus->phy_map[i]; ++ ++ if (!tmp_phydev) ++ continue; ++ ++#ifdef CONFIG_FEC_SHARED_PHY ++ if (priv->index == 0) ++ phydev[i] = tmp_phydev; ++ else if (priv->index == 1) { ++ if (startnode == 1) { ++ phydev[i] = tmp_phydev; ++ startnode = 0; ++ } else { ++ startnode++; ++ continue; ++ } ++ } else ++ printk(KERN_INFO "%s now we do not" ++ "support (%d) more than" ++ "2 phys shared " ++ "one mdio bus\n", ++ __func__, startnode); ++#else ++ phydev[i] = tmp_phydev; ++#endif ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ if ((!phydev[0]) && (!phydev[1])) { ++ printk(KERN_INFO "%s: Don't found any phy device at all\n", ++ dev->name); ++ return -ENODEV; ++ } ++ ++ priv->phy1_link = PHY_DOWN; ++ priv->phy1_old_link = PHY_DOWN; ++ priv->phy1_speed = 0; ++ priv->phy1_duplex = -1; ++ ++ priv->phy2_link = PHY_DOWN; ++ priv->phy2_old_link = PHY_DOWN; ++ priv->phy2_speed = 0; ++ priv->phy2_duplex = -1; ++ ++ phydev[0] = phy_connect(dev, dev_name(&phydev[0]->dev), ++ &switch_adjust_link1, 0, PHY_INTERFACE_MODE_MII); ++ if (IS_ERR(phydev[0])) { ++ printk(KERN_ERR " %s phy_connect failed\n", __func__); ++ return PTR_ERR(phydev[0]); ++ } ++ ++ phydev[1] = phy_connect(dev, dev_name(&phydev[1]->dev), ++ &switch_adjust_link2, 0, PHY_INTERFACE_MODE_MII); ++ if (IS_ERR(phydev[1])) { ++ printk(KERN_ERR " %s phy_connect failed\n", __func__); ++ return PTR_ERR(phydev[1]); ++ } ++ ++ for (i = 0; i < SWITCH_EPORT_NUMBER; i++) { ++ printk(KERN_INFO "attached phy %i to driver %s\n", ++ phydev[i]->addr, phydev[i]->drv->name); ++ priv->phydev[i] = phydev[i]; ++ } ++ ++ return 0; ++} ++/* -----------------------------------------------------------------------*/ ++static int switch_enet_open(struct net_device *dev) ++{ ++ struct switch_enet_private *fep = netdev_priv(dev); ++ volatile switch_t *fecp; ++ int i; ++ ++ fecp = (volatile switch_t *)fep->hwp; ++ /* I should reset the ring buffers here, but I don't yet know ++ * a simple way to do that. ++ */ ++ switch_set_mac_address(dev); ++ ++ fep->phy1_link = 0; ++ fep->phy2_link = 0; ++ ++ coldfire_switch_init_phy(dev); ++ for (i = 0; i < SWITCH_EPORT_NUMBER; i++) { ++ phy_write(fep->phydev[i], MII_BMCR, BMCR_RESET); ++ phy_start(fep->phydev[i]); ++ } ++ ++ fep->phy1_old_link = 0; ++ fep->phy2_old_link = 0; ++ fep->phy1_link = 1; ++ fep->phy2_link = 1; ++ ++ /* no phy, go full duplex, it's most likely a hub chip */ ++ switch_restart(dev, 1); ++ ++ /* if the fec is the fist open, we need to do nothing*/ ++ /* if the fec is not the fist open, we need to restart the FEC*/ ++ if (fep->sequence_done == 0) ++ switch_restart(dev, 1); ++ else ++ fep->sequence_done = 0; ++ ++ fep->currTime = 0; ++ fep->learning_irqhandle_enable = 0; ++ ++ MCF_ESW_PER = 0x70007; ++ fecp->ESW_DBCR = MCF_ESW_DBCR_P0 | MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2; ++ fecp->ESW_DMCR = MCF_ESW_DMCR_P0 | MCF_ESW_DMCR_P1 | MCF_ESW_DMCR_P2; ++ ++ netif_start_queue(dev); ++ fep->opened = 1; ++ ++ return 0; ++} ++ ++static int switch_enet_close(struct net_device *dev) ++{ ++ struct switch_enet_private *fep = netdev_priv(dev); ++ int i; ++ ++ /* Don't know what to do yet.*/ ++ fep->opened = 0; ++ netif_stop_queue(dev); ++ switch_stop(dev); ++ ++ for (i = 0; i < SWITCH_EPORT_NUMBER; i++) { ++ phy_disconnect(fep->phydev[i]); ++ phy_stop(fep->phydev[i]); ++ phy_write(fep->phydev[i], MII_BMCR, BMCR_PDOWN); ++ } ++ ++ return 0; ++} ++ ++/* Set or clear the multicast filter for this adaptor. ++ * Skeleton taken from sunlance driver. ++ * The CPM Ethernet implementation allows Multicast as well as individual ++ * MAC address filtering. Some of the drivers check to make sure it is ++ * a group multicast address, and discard those that are not. I guess I ++ * will do the same for now, but just remove the test if you want ++ * individual filtering as well (do the upper net layers want or support ++ * this kind of feature?). ++ */ ++ ++#define HASH_BITS 6 /* #bits in hash */ ++#define CRC32_POLY 0xEDB88320 ++ ++static void set_multicast_list(struct net_device *dev) ++{ ++ struct switch_enet_private *fep; ++ volatile switch_t *ep; ++ unsigned int i, bit, data, crc; ++ struct netdev_hw_addr *ha; ++ ++ fep = netdev_priv(dev); ++ ep = fep->hwp; ++ ++ if (dev->flags & IFF_PROMISC) { ++ printk(KERN_INFO "%s IFF_PROMISC\n", __func__); ++ } else { ++ if (dev->flags & IFF_ALLMULTI) ++ /* Catch all multicast addresses, so set the ++ * filter to all 1's. ++ */ ++ printk(KERN_INFO "%s IFF_ALLMULTI\n", __func__); ++ else { ++ netdev_for_each_mc_addr(ha, dev) { ++ if (!(ha->addr[0] & 1)) ++ continue; ++ ++ /* calculate crc32 value of mac address ++ */ ++ crc = 0xffffffff; ++ ++ for (i = 0; i < dev->addr_len; i++) { ++ data = ha->addr[i]; ++ for (bit = 0; bit < 8; bit++, ++ data >>= 1) { ++ crc = (crc >> 1) ^ ++ (((crc ^ data) & 1) ? ++ CRC32_POLY : 0); ++ } ++ } ++ ++ } ++ } ++ } ++} ++ ++/* Set a MAC change in hardware.*/ ++static void switch_set_mac_address(struct net_device *dev) ++{ ++ volatile switch_t *fecp; ++ ++ fecp = ((struct switch_enet_private *)netdev_priv(dev))->hwp; ++} ++ ++static void switch_hw_init(void) ++{ ++ /* GPIO config - RMII mode for both MACs */ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC_MASK) | ++ MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL; ++ ++ /* Initialize MAC 0/1 */ ++ /* RCR */ ++ MCF_FEC_RCR0 = (MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | ++ MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD); ++ MCF_FEC_RCR1 = (MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | ++ MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD); ++ /* TCR */ ++ MCF_FEC_TCR0 = MCF_FEC_TCR_FDEN; ++ MCF_FEC_TCR1 = MCF_FEC_TCR_FDEN; ++ /* ECR */ ++#ifdef MODELO_BUFFER ++ MCF_FEC_ECR0 = MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588; ++ MCF_FEC_ECR1 = MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588; ++#else ++ MCF_FEC_ECR0 = MCF_FEC_ECR_ETHER_EN; ++ MCF_FEC_ECR1 = MCF_FEC_ECR_ETHER_EN; ++#endif ++ MCF_FEC_MSCR0 = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; ++ MCF_FEC_MSCR1 = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; ++ ++ MCF_FEC_EIMR0 = FEC_ENET_TXF | FEC_ENET_RXF; ++ MCF_FEC_EIMR1 = FEC_ENET_TXF | FEC_ENET_RXF; ++ /*MCF_PPMHR0*/ ++ MCF_PPMCR0 = 0; ++} ++ ++static const struct net_device_ops switch_netdev_ops = { ++ .ndo_open = switch_enet_open, ++ .ndo_stop = switch_enet_close, ++ .ndo_start_xmit = switch_enet_start_xmit, ++ .ndo_set_multicast_list = set_multicast_list, ++ .ndo_do_ioctl = switch_enet_ioctl, ++ .ndo_tx_timeout = switch_timeout, ++}; ++ ++/* Initialize the FEC Ethernet. ++ */ ++ /* ++ * XXX: We need to clean up on failure exits here. ++ */ ++static int switch_enet_init(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct switch_enet_private *fep = netdev_priv(dev); ++ unsigned long mem_addr; ++ cbd_t *bdp; ++ cbd_t *cbd_base; ++ volatile switch_t *fecp; ++ int i, j; ++ struct coldfire_switch_platform_data *plat = ++ pdev->dev.platform_data; ++ ++ /* Allocate memory for buffer descriptors. ++ */ ++ mem_addr = __get_free_page(GFP_DMA); ++ if (mem_addr == 0) { ++ printk(KERN_ERR "Switch: allocate descriptor memory failed?\n"); ++ return -ENOMEM; ++ } ++ ++ spin_lock_init(&fep->hw_lock); ++ spin_lock_init(&fep->mii_lock); ++ ++ /* Create an Ethernet device instance. ++ */ ++ fecp = (volatile switch_t *)plat->switch_hw[0]; ++ fep->hwp = fecp; ++ fep->netdev = dev; ++ ++ /* ++ * SWITCH CONFIGURATION ++ */ ++ fecp->ESW_MODE = MCF_ESW_MODE_SW_RST; ++ udelay(10); ++ /* enable switch*/ ++ fecp->ESW_MODE = MCF_ESW_MODE_STATRST; ++ fecp->ESW_MODE = MCF_ESW_MODE_SW_EN; ++ ++ /* Enable transmit/receive on all ports */ ++ fecp->ESW_PER = 0xffffffff; ++ ++ /* Management port configuration, ++ * make port 0 as management port */ ++ fecp->ESW_BMPC = 0; ++ ++ /* clear all switch irq*/ ++ fecp->switch_ievent = 0xffffffff; ++ fecp->switch_imask = 0; ++ ++ udelay(10); ++ ++ /* Set the Ethernet address. If using multiple Enets on the 8xx, ++ * this needs some work to get unique addresses. ++ * ++ * This is our default MAC address unless the user changes ++ * it via eth_mac_addr (our dev->set_mac_addr handler). ++ */ ++ if (plat && plat->get_mac) ++ plat->get_mac(dev); ++ ++ cbd_base = (cbd_t *)mem_addr; ++ /* XXX: missing check for allocation failure */ ++ if (plat && plat->uncache) ++ plat->uncache(mem_addr); ++ ++ /* Set receive and transmit descriptor base. ++ */ ++ fep->rx_bd_base = cbd_base; ++ fep->tx_bd_base = cbd_base + RX_RING_SIZE; ++ ++ dev->base_addr = (unsigned long)fecp; ++ ++ /* The FEC Ethernet specific entries in the device structure. */ ++ dev->watchdog_timeo = TX_TIMEOUT; ++ dev->netdev_ops = &switch_netdev_ops; ++ ++ fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; ++ fep->cur_rx = fep->rx_bd_base; ++ ++ fep->skb_cur = fep->skb_dirty = 0; ++ ++ /* Initialize the receive buffer descriptors. */ ++ bdp = fep->rx_bd_base; ++ ++ for (i = 0; i < SWITCH_ENET_RX_PAGES; i++) { ++ ++ /* Allocate a page. ++ */ ++ mem_addr = __get_free_page(GFP_DMA); ++ /* XXX: missing check for allocation failure */ ++ if (plat && plat->uncache) ++ plat->uncache(mem_addr); ++ ++ /* Initialize the BD for every fragment in the page. ++ */ ++ for (j = 0; j < SWITCH_ENET_RX_FRPPG; j++) { ++ bdp->cbd_sc = BD_ENET_RX_EMPTY; ++ bdp->cbd_bufaddr = __pa(mem_addr); ++#ifdef MODELO_BUFFER ++ bdp->bdu = 0x00000000; ++ bdp->ebd_status = RX_BD_INT; ++#endif ++ mem_addr += SWITCH_ENET_RX_FRSIZE; ++ bdp++; ++ } ++ } ++ ++ /* Set the last buffer to wrap. ++ */ ++ bdp--; ++ bdp->cbd_sc |= BD_SC_WRAP; ++ ++ /* ...and the same for transmmit. ++ */ ++ bdp = fep->tx_bd_base; ++ for (i = 0, j = SWITCH_ENET_TX_FRPPG; i < TX_RING_SIZE; i++) { ++ if (j >= SWITCH_ENET_TX_FRPPG) { ++ mem_addr = __get_free_page(GFP_DMA); ++ j = 1; ++ } else { ++ mem_addr += SWITCH_ENET_TX_FRSIZE; ++ j++; ++ } ++ fep->tx_bounce[i] = (unsigned char *) mem_addr; ++ ++ /* Initialize the BD for every fragment in the page. ++ */ ++ bdp->cbd_sc = 0; ++ bdp->cbd_bufaddr = 0; ++ bdp++; ++ } ++ ++ /* Set the last buffer to wrap. ++ */ ++ bdp--; ++ bdp->cbd_sc |= BD_SC_WRAP; ++ ++ /* Set receive and transmit descriptor base. ++ */ ++ fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); ++ fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); ++ ++ /* Install our interrupt handlers. This varies depending on ++ * the architecture. ++ */ ++ if (plat && plat->request_intrs) ++ plat->request_intrs(dev, switch_enet_interrupt, dev); ++ ++ fecp->fec_r_buff_size = RX_BUFFER_SIZE; ++ fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE; ++ ++ /* setup MII interface */ ++ if (plat && plat->set_mii) ++ plat->set_mii(dev); ++ ++ /* Clear and enable interrupts */ ++ fecp->switch_ievent = 0xffffffff; ++ fecp->switch_imask = MCF_ESW_IMR_RXB | MCF_ESW_IMR_TXB | ++ MCF_ESW_IMR_RXF | MCF_ESW_IMR_TXF; ++ esw_clear_atable(fep); ++ /* Queue up command to detect the PHY and initialize the ++ * remainder of the interface. ++ */ ++#ifndef CONFIG_FEC_SHARED_PHY ++ fep->phy_addr = 0; ++#else ++ fep->phy_addr = fep->index; ++#endif ++ ++ fep->sequence_done = 1; ++ return 0; ++} ++ ++/* This function is called to start or restart the FEC during a link ++ * change. This only happens when switching between half and full ++ * duplex. ++ */ ++static void switch_restart(struct net_device *dev, int duplex) ++{ ++ struct switch_enet_private *fep; ++ cbd_t *bdp; ++ volatile switch_t *fecp; ++ int i; ++ struct coldfire_switch_platform_data *plat; ++ ++ fep = netdev_priv(dev); ++ fecp = fep->hwp; ++ plat = fep->pdev->dev.platform_data; ++ /* Whack a reset. We should wait for this.*/ ++ MCF_FEC_ECR0 = 1; ++ MCF_FEC_ECR1 = 1; ++ udelay(10); ++ ++ fecp->ESW_MODE = MCF_ESW_MODE_SW_RST; ++ udelay(10); ++ fecp->ESW_MODE = MCF_ESW_MODE_STATRST; ++ fecp->ESW_MODE = MCF_ESW_MODE_SW_EN; ++ ++ /* Enable transmit/receive on all ports */ ++ fecp->ESW_PER = 0xffffffff; ++ ++ /* Management port configuration, ++ * make port 0 as management port */ ++ fecp->ESW_BMPC = 0; ++ ++ /* Clear any outstanding interrupt. ++ */ ++ fecp->switch_ievent = 0xffffffff; ++ ++ /* Set station address.*/ ++ switch_set_mac_address(dev); ++ ++ switch_hw_init(); ++ ++ /* Reset all multicast.*/ ++ ++ /* Set maximum receive buffer size. ++ */ ++ fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; ++ ++ if (plat && plat->localhw_setup) ++ plat->localhw_setup(); ++ /* Set receive and transmit descriptor base. ++ */ ++ fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); ++ fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); ++ ++ fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; ++ fep->cur_rx = fep->rx_bd_base; ++ ++ /* Reset SKB transmit buffers. ++ */ ++ fep->skb_cur = fep->skb_dirty = 0; ++ for (i = 0; i <= TX_RING_MOD_MASK; i++) { ++ if (fep->tx_skbuff[i] != NULL) { ++ dev_kfree_skb_any(fep->tx_skbuff[i]); ++ fep->tx_skbuff[i] = NULL; ++ } ++ } ++ ++ /* Initialize the receive buffer descriptors. ++ */ ++ bdp = fep->rx_bd_base; ++ for (i = 0; i < RX_RING_SIZE; i++) { ++ ++ /* Initialize the BD for every fragment in the page. ++ */ ++ bdp->cbd_sc = BD_ENET_RX_EMPTY; ++#ifdef MODELO_BUFFER ++ bdp->bdu = 0x00000000; ++ bdp->ebd_status = RX_BD_INT; ++#endif ++ bdp++; ++ } ++ ++ /* Set the last buffer to wrap. ++ */ ++ bdp--; ++ bdp->cbd_sc |= BD_SC_WRAP; ++ ++ /* ...and the same for transmmit. ++ */ ++ bdp = fep->tx_bd_base; ++ for (i = 0; i < TX_RING_SIZE; i++) { ++ ++ /* Initialize the BD for every fragment in the page.*/ ++ bdp->cbd_sc = 0; ++ bdp->cbd_bufaddr = 0; ++ bdp++; ++ } ++ ++ /* Set the last buffer to wrap.*/ ++ bdp--; ++ bdp->cbd_sc |= BD_SC_WRAP; ++ ++ fep->full_duplex = duplex; ++ ++ /* And last, enable the transmit and receive processing.*/ ++ fecp->fec_r_buff_size = RX_BUFFER_SIZE; ++ fecp->fec_r_des_active = MCF_ESW_RDAR_R_DES_ACTIVE; ++ ++ /* Enable interrupts we wish to service. ++ */ ++ fecp->switch_ievent = 0xffffffff; ++ fecp->switch_imask = MCF_ESW_IMR_RXF | MCF_ESW_IMR_TXF | ++ MCF_ESW_IMR_RXB | MCF_ESW_IMR_TXB; ++} ++ ++static void switch_stop(struct net_device *dev) ++{ ++ volatile switch_t *fecp; ++ struct switch_enet_private *fep; ++ struct coldfire_switch_platform_data *plat; ++ ++ fep = netdev_priv(dev); ++ fecp = fep->hwp; ++ plat = fep->pdev->dev.platform_data; ++ /* ++ ** We cannot expect a graceful transmit stop without link !!! ++ */ ++ if (fep->phy1_link) ++ udelay(10); ++ if (fep->phy2_link) ++ udelay(10); ++ ++ /* Whack a reset. We should wait for this. ++ */ ++ udelay(10); ++} ++ ++static int fec_mdio_register(struct net_device *dev) ++{ ++ int err = 0; ++ struct switch_enet_private *fep = netdev_priv(dev); ++ ++ fep->mdio_bus = mdiobus_alloc(); ++ if (!fep->mdio_bus) { ++ printk(KERN_ERR "ethernet switch mdiobus_alloc fail\n"); ++ return -ENOMEM; ++ } ++ ++ fep->mdio_bus->name = "Coldfire switch MII 0 Bus"; ++ strcpy(fep->mdio_bus->id, "0"); ++ ++ fep->mdio_bus->read = &coldfire_fec_mdio_read; ++ fep->mdio_bus->write = &coldfire_fec_mdio_write; ++ fep->mdio_bus->priv = dev; ++ err = mdiobus_register(fep->mdio_bus); ++ if (err) { ++ mdiobus_free(fep->mdio_bus); ++ printk(KERN_ERR "%s: ethernet mdiobus_register fail\n", ++ dev->name); ++ return -EIO; ++ } ++ ++ printk(KERN_INFO "mdiobus_register %s ok\n", ++ fep->mdio_bus->name); ++ return err; ++} ++ ++static int __devinit eth_switch_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ int err; ++ struct switch_enet_private *fep; ++ struct task_struct *task; ++ ++ printk(KERN_INFO "Ethernet Switch Version 1.0\n"); ++ ++ dev = alloc_etherdev(sizeof(struct switch_enet_private)); ++ if (!dev) { ++ printk(KERN_ERR "%s: ethernet switch alloc_etherdev fail\n", ++ dev->name); ++ return -ENOMEM; ++ } ++ ++ SET_NETDEV_DEV(dev, &pdev->dev); ++ ++ fep = netdev_priv(dev); ++ memset(fep, 0, sizeof(*fep)); ++ ++ fep->pdev = pdev; ++ platform_set_drvdata(pdev, dev); ++ printk(KERN_ERR "%s: ethernet switch port 0 init\n", ++ __func__); ++ err = switch_enet_init(pdev); ++ if (err) { ++ free_netdev(dev); ++ platform_set_drvdata(pdev, NULL); ++ } ++ ++ err = fec_mdio_register(dev); ++ if (err) { ++ printk(KERN_ERR "%s: ethernet switch fec_mdio_register\n", ++ dev->name); ++ free_netdev(dev); ++ platform_set_drvdata(pdev, NULL); ++ return -ENOMEM; ++ } ++ ++ /* setup timer for Learning Aging function */ ++ init_timer(&fep->timer_aging); ++ fep->timer_aging.function = l2switch_aging_timer; ++ fep->timer_aging.data = (unsigned long) fep; ++ fep->timer_aging.expires = jiffies + LEARNING_AGING_TIMER; ++ add_timer(&fep->timer_aging); ++ ++ /* register network device*/ ++ if (register_netdev(dev) != 0) { ++ /* XXX: missing cleanup here */ ++ free_netdev(dev); ++ platform_set_drvdata(pdev, NULL); ++ printk(KERN_ERR "%s: ethernet switch register_netdev fail\n", ++ dev->name); ++ return -EIO; ++ } ++ ++ task = kthread_run(switch_enet_learning, fep, ++ "modelo l2switch"); ++ if (IS_ERR(task)) { ++ err = PTR_ERR(task); ++ return err; ++ } ++ ++ printk(KERN_INFO "%s: ethernet switch %pM\n", ++ dev->name, dev->dev_addr); ++ return 0; ++} ++ ++static int __devexit eth_switch_remove(struct platform_device *pdev) ++{ ++ int i; ++ struct net_device *dev; ++ struct switch_enet_private *fep; ++ struct switch_platform_private *chip; ++ ++ chip = platform_get_drvdata(pdev); ++ if (chip) { ++ for (i = 0; i < chip->num_slots; i++) { ++ fep = chip->fep_host[i]; ++ dev = fep->netdev; ++ fep->sequence_done = 1; ++ unregister_netdev(dev); ++ free_netdev(dev); ++ ++ del_timer_sync(&fep->timer_aging); ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ kfree(chip); ++ ++ } else ++ printk(KERN_ERR "%s: can not get the " ++ "switch_platform_private %x\n", __func__, ++ (unsigned int)chip); ++ ++ return 0; ++} ++ ++static struct platform_driver eth_switch_driver = { ++ .probe = eth_switch_probe, ++ .remove = __devexit_p(eth_switch_remove), ++ .driver = { ++ .name = "coldfire-switch", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init coldfire_switch_init(void) ++{ ++ return platform_driver_register(ð_switch_driver); ++} ++ ++static void __exit coldfire_switch_exit(void) ++{ ++ platform_driver_unregister(ð_switch_driver); ++} ++ ++module_init(coldfire_switch_init); ++module_exit(coldfire_switch_exit); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/net/modelo_switch.h +@@ -0,0 +1,1141 @@ ++/****************************************************************************/ ++ ++/* ++ * mcfswitch -- L2 Switch Controller for Modelo ColdFire SoC ++ * processors. ++ * ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ */ ++ ++/****************************************************************************/ ++#ifndef SWITCH_H ++#define SWITCH_H ++/****************************************************************************/ ++/* The Switch stores dest/src/type, data, and checksum for receive packets. ++ */ ++#define PKT_MAXBUF_SIZE 1518 ++#define PKT_MINBUF_SIZE 64 ++#define PKT_MAXBLR_SIZE 1520 ++ ++/* ++ * The 5441x RX control register also contains maximum frame ++ * size bits. ++ */ ++#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) ++ ++/* ++ * Some hardware gets it MAC address out of local flash memory. ++ * if this is non-zero then assume it is the address to get MAC from. ++ */ ++#define FEC_FLASHMAC 0 ++ ++/* The number of Tx and Rx buffers. These are allocated from the page ++ * pool. The code may assume these are power of two, so it it best ++ * to keep them that size. ++ * We don't need to allocate pages for the transmitter. We just use ++ * the skbuffer directly. ++ */ ++#ifdef CONFIG_SWITCH_DMA_USE_SRAM ++#define SWITCH_ENET_RX_PAGES 6 ++#else ++#define SWITCH_ENET_RX_PAGES 8 ++#endif ++ ++#define SWITCH_ENET_RX_FRSIZE 2048 ++#define SWITCH_ENET_RX_FRPPG (PAGE_SIZE / SWITCH_ENET_RX_FRSIZE) ++#define RX_RING_SIZE (SWITCH_ENET_RX_FRPPG * SWITCH_ENET_RX_PAGES) ++#define SWITCH_ENET_TX_FRSIZE 2048 ++#define SWITCH_ENET_TX_FRPPG (PAGE_SIZE / SWITCH_ENET_TX_FRSIZE) ++ ++#ifdef CONFIG_SWITCH_DMA_USE_SRAM ++#define TX_RING_SIZE 8 /* Must be power of two */ ++#define TX_RING_MOD_MASK 7 /* for this to work */ ++#else ++#define TX_RING_SIZE 16 /* Must be power of two */ ++#define TX_RING_MOD_MASK 15 /* for this to work */ ++#endif ++ ++#define SWITCH_EPORT_NUMBER 2 ++ ++#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) ++#error "L2SWITCH: descriptor ring size constants too large" ++#endif ++/*-----------------------------------------------------------------------*/ ++typedef struct l2switch_output_queue_status { ++ unsigned long ESW_MMSR; ++ unsigned long ESW_LMT; ++ unsigned long ESW_LFC; ++ unsigned long ESW_PCSR; ++ unsigned long ESW_IOSR; ++ unsigned long ESW_QWT; ++ unsigned long esw_reserved; ++ unsigned long ESW_P0BCT; ++} esw_output_queue_status; ++ ++typedef struct l2switch_statistics_status { ++ /* ++ * Total number of incoming frames processed ++ * but discarded in switch ++ */ ++ unsigned long ESW_DISCN; ++ /*Sum of bytes of frames counted in ESW_DISCN*/ ++ unsigned long ESW_DISCB; ++ /* ++ * Total number of incoming frames processed ++ * but not discarded in switch ++ */ ++ unsigned long ESW_NDISCN; ++ /*Sum of bytes of frames counted in ESW_NDISCN*/ ++ unsigned long ESW_NDISCB; ++} esw_statistics_status; ++ ++typedef struct l2switch_port_statistics_status { ++ /*outgoing frames discarded due to transmit queue congestion*/ ++ unsigned long MCF_ESW_POQC; ++ /*incoming frames discarded due to VLAN domain mismatch*/ ++ unsigned long MCF_ESW_PMVID; ++ /*incoming frames discarded due to untagged discard*/ ++ unsigned long MCF_ESW_PMVTAG; ++ /*incoming frames discarded due port is in blocking state*/ ++ unsigned long MCF_ESW_PBL; ++} esw_port_statistics_status; ++ ++typedef struct l2switch { ++ unsigned long ESW_REVISION; ++ unsigned long ESW_SCRATCH; ++ unsigned long ESW_PER; ++ unsigned long reserved0[1]; ++ unsigned long ESW_VLANV; ++ unsigned long ESW_DBCR; ++ unsigned long ESW_DMCR; ++ unsigned long ESW_BKLR; ++ unsigned long ESW_BMPC; ++ unsigned long ESW_MODE; ++ unsigned long ESW_VIMSEL; ++ unsigned long ESW_VOMSEL; ++ unsigned long ESW_VIMEN; ++ unsigned long ESW_VID;/*0x34*/ ++ /*from 0x38 0x3C*/ ++ unsigned long esw_reserved0[2]; ++ unsigned long ESW_MCR;/*0x40*/ ++ unsigned long ESW_EGMAP; ++ unsigned long ESW_INGMAP; ++ unsigned long ESW_INGSAL; ++ unsigned long ESW_INGSAH; ++ unsigned long ESW_INGDAL; ++ unsigned long ESW_INGDAH; ++ unsigned long ESW_ENGSAL; ++ unsigned long ESW_ENGSAH; ++ unsigned long ESW_ENGDAL; ++ unsigned long ESW_ENGDAH; ++ unsigned long ESW_MCVAL;/*0x6C*/ ++ /*from 0x70--0x7C*/ ++ unsigned long esw_reserved1[4]; ++ unsigned long ESW_MMSR;/*0x80*/ ++ unsigned long ESW_LMT; ++ unsigned long ESW_LFC; ++ unsigned long ESW_PCSR; ++ unsigned long ESW_IOSR; ++ unsigned long ESW_QWT;/*0x94*/ ++ unsigned long esw_reserved2[1];/*0x98*/ ++ unsigned long ESW_P0BCT;/*0x9C*/ ++ /*from 0xA0-0xB8*/ ++ unsigned long esw_reserved3[7]; ++ unsigned long ESW_P0FFEN;/*0xBC*/ ++ unsigned long ESW_PSNP[8]; ++ unsigned long ESW_IPSNP[8]; ++ /*port0-port2 VLAN Priority resolution map 0xFC0D_C100-C108*/ ++ unsigned long ESW_PVRES[3]; ++ /*from 0x10C-0x13C*/ ++ unsigned long esw_reserved4[13]; ++ unsigned long ESW_IPRES;/*0x140*/ ++ /*from 0x144-0x17C*/ ++ unsigned long esw_reserved5[15]; ++ ++ /*port0-port2 Priority Configuration 0xFC0D_C180-C188*/ ++ unsigned long ESW_PRES[3]; ++ /*from 0x18C-0x1FC*/ ++ unsigned long esw_reserved6[29]; ++ ++ /*port0-port2 VLAN ID 0xFC0D_C200-C208*/ ++ unsigned long ESW_PID[3]; ++ /*from 0x20C-0x27C*/ ++ unsigned long esw_reserved7[29]; ++ ++ /*port0-port2 VLAN domain resolution entry 0xFC0D_C280-C2FC*/ ++ unsigned long ESW_VRES[32]; ++ ++ unsigned long ESW_DISCN;/*0x300*/ ++ unsigned long ESW_DISCB; ++ unsigned long ESW_NDISCN; ++ unsigned long ESW_NDISCB;/*0xFC0DC30C*/ ++ /*per port statistics 0xFC0DC310_C33C*/ ++ esw_port_statistics_status port_statistics_status[3]; ++ /*from 0x340-0x400*/ ++ unsigned long esw_reserved8[48]; ++ ++ /*0xFC0DC400---0xFC0DC418*/ ++ /*unsigned long MCF_ESW_ISR;*/ ++ unsigned long switch_ievent; /* Interrupt event reg */ ++ /*unsigned long MCF_ESW_IMR;*/ ++ unsigned long switch_imask; /* Interrupt mask reg */ ++ /*unsigned long MCF_ESW_RDSR;*/ ++ unsigned long fec_r_des_start; /* Receive descriptor ring */ ++ /*unsigned long MCF_ESW_TDSR;*/ ++ unsigned long fec_x_des_start; /* Transmit descriptor ring */ ++ /*unsigned long MCF_ESW_MRBR;*/ ++ unsigned long fec_r_buff_size; /* Maximum receive buff size */ ++ /*unsigned long MCF_ESW_RDAR;*/ ++ unsigned long fec_r_des_active; /* Receive descriptor reg */ ++ /*unsigned long MCF_ESW_TDAR;*/ ++ unsigned long fec_x_des_active; /* Transmit descriptor reg */ ++ /*from 0x420-0x4FC*/ ++ unsigned long esw_reserved9[57]; ++ ++ /*0xFC0DC500---0xFC0DC508*/ ++ unsigned long ESW_LREC0; ++ unsigned long ESW_LREC1; ++ unsigned long ESW_LSR; ++} switch_t; ++ ++typedef struct _64bTableEntry { ++ unsigned int lo; /* lower 32 bits */ ++ unsigned int hi; /* upper 32 bits */ ++} AddrTable64bEntry; ++ ++typedef struct l2switchaddrtable { ++ AddrTable64bEntry eswTable64bEntry[2048]; ++} eswAddrTable_t; ++ ++/*unsigned long MCF_ESW_LOOKUP_MEM;*/ ++#define MCF_ESW_REVISION (*(volatile unsigned long *)(0xFC0DC000)) ++#define MCF_ESW_PER (*(volatile unsigned long *)(0xFC0DC008)) ++#define MCF_ESW_VLANV (*(volatile unsigned long *)(0xFC0DC010)) ++#define MCF_ESW_DBCR (*(volatile unsigned long *)(0xFC0DC014)) ++#define MCF_ESW_DMCR (*(volatile unsigned long *)(0xFC0DC018)) ++#define MCF_ESW_BKLR (*(volatile unsigned long *)(0xFC0DC01C)) ++#define MCF_ESW_BMPC (*(volatile unsigned long *)(0xFC0DC020)) ++#define MCF_ESW_MODE (*(volatile unsigned long *)(0xFC0DC024)) ++ ++#define MCF_ESW_ISR (*(volatile unsigned long *)(0xFC0DC400)) ++#define MCF_ESW_IMR (*(volatile unsigned long *)(0xFC0DC404)) ++#define MCF_ESW_TDAR (*(volatile unsigned long *)(0xFC0DC418)) ++#define MCF_ESW_LOOKUP_MEM (*(volatile unsigned long *)(0xFC0E0000)) ++ ++#define MCF_PPMCR0 (*(volatile unsigned short *)(0xFC04002D)) ++#define MCF_PPMHR0 (*(volatile unsigned long *)(0xFC040030)) ++ ++#define MCF_FEC_EIR0 (*(volatile unsigned long *)(0xFC0D4004)) ++#define MCF_FEC_EIR1 (*(volatile unsigned long *)(0xFC0D8004)) ++#define MCF_FEC_EIMR0 (*(volatile unsigned long *)(0xFC0D4008)) ++#define MCF_FEC_EIMR1 (*(volatile unsigned long *)(0xFC0D8008)) ++#define MCF_FEC_MMFR0 (*(volatile unsigned long *)(0xFC0D4040)) ++#define MCF_FEC_MMFR1 (*(volatile unsigned long *)(0xFC0D8040)) ++#define MCF_FEC_MSCR0 (*(volatile unsigned long *)(0xFC0D4044)) ++#define MCF_FEC_MSCR1 (*(volatile unsigned long *)(0xFC0D8044)) ++#define MCF_FEC_RCR0 (*(volatile unsigned long *)(0xFC0D4084)) ++#define MCF_FEC_RCR1 (*(volatile unsigned long *)(0xFC0D8084)) ++#define MCF_FEC_TCR0 (*(volatile unsigned long *)(0xFC0D40C4)) ++#define MCF_FEC_TCR1 (*(volatile unsigned long *)(0xFC0D80C4)) ++#define MCF_FEC_ECR0 (*(volatile unsigned long *)(0xFC0D4024)) ++#define MCF_FEC_ECR1 (*(volatile unsigned long *)(0xFC0D8024)) ++ ++ ++#define MCF_FEC_RCR_PROM (0x00000008) ++#define MCF_FEC_RCR_RMII_MODE (0x00000100) ++#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x00003FFF)<<16) ++#define MCF_FEC_RCR_CRC_FWD (0x00004000) ++ ++#define MCF_FEC_TCR_FDEN (0x00000004) ++ ++#define MCF_FEC_ECR_ETHER_EN (0x00000002) ++#define MCF_FEC_ECR_ENA_1588 (0x00000010) ++ ++/*-------------ioctl command ---------------------------------------*/ ++#define ESW_SET_LEARNING_CONF 0x9101 ++#define ESW_GET_LEARNING_CONF 0x9201 ++#define ESW_SET_BLOCKING_CONF 0x9102 ++#define ESW_GET_BLOCKING_CONF 0x9202 ++#define ESW_SET_MULTICAST_CONF 0x9103 ++#define ESW_GET_MULTICAST_CONF 0x9203 ++#define ESW_SET_BROADCAST_CONF 0x9104 ++#define ESW_GET_BROADCAST_CONF 0x9204 ++#define ESW_SET_PORTENABLE_CONF 0x9105 ++#define ESW_GET_PORTENABLE_CONF 0x9205 ++#define ESW_SET_IP_SNOOP_CONF 0x9106 ++#define ESW_GET_IP_SNOOP_CONF 0x9206 ++#define ESW_SET_PORT_SNOOP_CONF 0x9107 ++#define ESW_GET_PORT_SNOOP_CONF 0x9207 ++#define ESW_SET_PORT_MIRROR_CONF 0x9108 ++#define ESW_GET_PORT_MIRROR_CONF 0x9208 ++#define ESW_SET_PIRORITY_VLAN 0x9109 ++#define ESW_GET_PIRORITY_VLAN 0x9209 ++#define ESW_SET_PIRORITY_IP 0x910A ++#define ESW_GET_PIRORITY_IP 0x920A ++#define ESW_SET_PIRORITY_MAC 0x910B ++#define ESW_GET_PIRORITY_MAC 0x920B ++#define ESW_SET_PIRORITY_DEFAULT 0x910C ++#define ESW_GET_PIRORITY_DEFAULT 0x920C ++#define ESW_SET_P0_FORCED_FORWARD 0x910D ++#define ESW_GET_P0_FORCED_FORWARD 0x920D ++#define ESW_SET_SWITCH_MODE 0x910E ++#define ESW_GET_SWITCH_MODE 0x920E ++#define ESW_SET_BRIDGE_CONFIG 0x910F ++#define ESW_GET_BRIDGE_CONFIG 0x920F ++#define ESW_SET_VLAN_OUTPUT_PROCESS 0x9110 ++#define ESW_GET_VLAN_OUTPUT_PROCESS 0x9210 ++#define ESW_SET_VLAN_INPUT_PROCESS 0x9111 ++#define ESW_GET_VLAN_INPUT_PROCESS 0x9211 ++#define ESW_SET_VLAN_DOMAIN_VERIFICATION 0x9112 ++#define ESW_GET_VLAN_DOMAIN_VERIFICATION 0x9212 ++#define ESW_SET_VLAN_RESOLUTION_TABLE 0x9113 ++#define ESW_GET_VLAN_RESOLUTION_TABLE 0x9213 ++#define ESW_GET_ENTRY_PORT_NUMBER 0x9214 ++#define ESW_GET_LOOKUP_TABLE 0x9215 ++#define ESW_GET_PORT_STATUS 0x9216 ++#define ESW_SET_VLAN_ID 0x9114 ++#define ESW_SET_VLAN_ID_CLEARED 0x9115 ++#define ESW_SET_PORT_IN_VLAN_ID 0x9116 ++#define ESW_SET_PORT_ENTRY_EMPTY 0x9117 ++#define ESW_SET_OTHER_PORT_ENTRY_EMPTY 0x9118 ++#define ESW_GET_PORT_ALL_STATUS 0x9217 ++#define ESW_SET_PORT_MIRROR_CONF_PORT_MATCH 0x9119 ++#define ESW_SET_PORT_MIRROR_CONF_ADDR_MATCH 0x911A ++ ++#define ESW_GET_STATISTICS_STATUS 0x9221 ++#define ESW_SET_OUTPUT_QUEUE_MEMORY 0x9125 ++#define ESW_GET_OUTPUT_QUEUE_STATUS 0x9225 ++#define ESW_UPDATE_STATIC_MACTABLE 0x9226 ++#define ESW_CLEAR_ALL_MACTABLE 0x9227 ++#define ESW_GET_USER_PID 0x9228 ++ ++typedef struct _eswIOCTL_PORT_CONF { ++ int port; ++ int enable; ++} eswIoctlPortConfig; ++ ++typedef struct _eswIOCTL_PORT_EN_CONF { ++ int port; ++ int tx_enable; ++ int rx_enable; ++} eswIoctlPortEnableConfig; ++ ++typedef struct _eswIOCTL_IP_SNOOP_CONF { ++ int mode; ++ unsigned long ip_header_protocol; ++} eswIoctlIpsnoopConfig; ++ ++typedef struct _eswIOCTL_P0_FORCED_FORWARD_CONF { ++ int port1; ++ int port2; ++ int enable; ++} eswIoctlP0ForcedForwardConfig; ++ ++typedef struct _eswIOCTL_PORT_SNOOP_CONF { ++ int mode; ++ unsigned short compare_port; ++ int compare_num; ++} eswIoctlPortsnoopConfig; ++ ++typedef struct _eswIOCTL_PORT_Mirror_CONF { ++ int mirror_port; ++ int port; ++ int egress_en; ++ int ingress_en; ++ int egress_mac_src_en; ++ int egress_mac_des_en; ++ int ingress_mac_src_en; ++ int ingress_mac_des_en; ++ unsigned char *src_mac; ++ unsigned char *des_mac; ++ int mirror_enable; ++} eswIoctlPortMirrorConfig; ++ ++struct eswIoctlMirrorCfgPortMatch { ++ int mirror_port; ++ int port_match_en; ++ int port; ++}; ++ ++struct eswIoctlMirrorCfgAddrMatch { ++ int mirror_port; ++ int addr_match_en; ++ unsigned char *mac_addr; ++}; ++ ++typedef struct _eswIOCTL_PRIORITY_VLAN_CONF { ++ int port; ++ int func_enable; ++ int vlan_pri_table_num; ++ int vlan_pri_table_value; ++} eswIoctlPriorityVlanConfig; ++ ++typedef struct _eswIOCTL_PRIORITY_IP_CONF { ++ int port; ++ int func_enable; ++ int ipv4_en; ++ int ip_priority_num; ++ int ip_priority_value; ++} eswIoctlPriorityIPConfig; ++ ++typedef struct _eswIOCTL_PRIORITY_MAC_CONF { ++ int port; ++} eswIoctlPriorityMacConfig; ++ ++typedef struct _eswIOCTL_PRIORITY_DEFAULT_CONF { ++ int port; ++ unsigned char priority_value; ++} eswIoctlPriorityDefaultConfig; ++ ++typedef struct _eswIOCTL_IRQ_STATUS { ++ unsigned long isr; ++ unsigned long imr; ++ unsigned long rx_buf_pointer; ++ unsigned long tx_buf_pointer; ++ unsigned long rx_max_size; ++ unsigned long rx_buf_active; ++ unsigned long tx_buf_active; ++} eswIoctlIrqStatus; ++ ++typedef struct _eswIOCTL_PORT_Mirror_STATUS { ++ unsigned long ESW_MCR; ++ unsigned long ESW_EGMAP; ++ unsigned long ESW_INGMAP; ++ unsigned long ESW_INGSAL; ++ unsigned long ESW_INGSAH; ++ unsigned long ESW_INGDAL; ++ unsigned long ESW_INGDAH; ++ unsigned long ESW_ENGSAL; ++ unsigned long ESW_ENGSAH; ++ unsigned long ESW_ENGDAL; ++ unsigned long ESW_ENGDAH; ++ unsigned long ESW_MCVAL; ++} eswIoctlPortMirrorStatus; ++ ++typedef struct _eswIOCTL_VLAN_OUTPUT_CONF { ++ int port; ++ int mode; ++} eswIoctlVlanOutputConfig; ++ ++typedef struct _eswIOCTL_VLAN_INPUT_CONF { ++ int port; ++ int mode; ++ unsigned short port_vlanid; ++} eswIoctlVlanInputConfig; ++ ++typedef struct _eswIOCTL_VLAN_DOMAIN_VERIFY_CONF { ++ int port; ++ int vlan_domain_verify_en; ++ int vlan_discard_unknown_en; ++} eswIoctlVlanVerificationConfig; ++ ++typedef struct _eswIOCTL_VLAN_RESOULATION_TABLE { ++ unsigned short port_vlanid; ++ unsigned char vlan_domain_port; ++ unsigned char vlan_domain_num; ++} eswIoctlVlanResoultionTable; ++ ++struct eswVlanTableItem { ++ eswIoctlVlanResoultionTable table[32]; ++ unsigned char valid_num; ++}; ++ ++typedef struct _eswIOCTL_VLAN_INPUT_STATUS { ++ unsigned long ESW_VLANV; ++ unsigned long ESW_PID[3]; ++ unsigned long ESW_VIMSEL; ++ unsigned long ESW_VIMEN; ++ unsigned long ESW_VRES[32]; ++} eswIoctlVlanInputStatus; ++ ++typedef struct _eswIOCTL_Static_MACTable { ++ unsigned char *mac_addr; ++ int port; ++ int priority; ++} eswIoctlUpdateStaticMACtable; ++ ++typedef struct _eswIOCTL_OUTPUT_QUEUE { ++ int fun_num; ++ esw_output_queue_status sOutputQueue; ++} eswIoctlOutputQueue; ++ ++/*=============================================================*/ ++#define LEARNING_AGING_TIMER (10 * HZ) ++/* ++ * Info received from Hardware Learning FIFO, ++ * holding MAC address and corresponding Hash Value and ++ * port number where the frame was received (disassembled). ++ */ ++typedef struct _eswPortInfo { ++ /* MAC lower 32 bits (first byte is 7:0). */ ++ unsigned int maclo; ++ /* MAC upper 16 bits (47:32). */ ++ unsigned int machi; ++ /* the hash value for this MAC address. */ ++ unsigned int hash; ++ /* the port number this MAC address is associated with. */ ++ unsigned int port; ++} eswPortInfo; ++ ++/* ++ * Hardware Look up Address Table 64-bit element. ++ */ ++typedef volatile struct _64bitTableEntry { ++ unsigned int lo; /* lower 32 bits */ ++ unsigned int hi; /* upper 32 bits */ ++} eswTable64bitEntry; ++ ++struct eswAddrTableEntryExample { ++ /* the entry number */ ++ unsigned short entrynum; ++ /* mac address array */ ++ unsigned char mac_addr[6]; ++ unsigned char item1; ++ unsigned short item2; ++}; ++ ++/* ++ * Define the buffer descriptor structure. ++ */ ++typedef struct bufdesc { ++ unsigned short cbd_sc; /* Control and status info */ ++ unsigned short cbd_datlen; /* Data length */ ++ unsigned long cbd_bufaddr; /* Buffer address */ ++#ifdef MODELO_BUFFER ++ unsigned long ebd_status; ++ unsigned short length_proto_type; ++ unsigned short payload_checksum; ++ unsigned long bdu; ++ unsigned long timestamp; ++ unsigned long reserverd_word1; ++ unsigned long reserverd_word2; ++#endif ++} cbd_t; ++ ++/* Forward declarations of some structures to support different PHYs ++ */ ++typedef struct { ++ uint mii_data; ++ void (*funct)(uint mii_reg, struct net_device *dev); ++} phy_cmd_t; ++ ++typedef struct { ++ uint id; ++ char *name; ++ ++ const phy_cmd_t *config; ++ const phy_cmd_t *startup; ++ const phy_cmd_t *ack_int; ++ const phy_cmd_t *shutdown; ++} phy_info_t; ++ ++struct port_status { ++ /* 1: link is up, 0: link is down */ ++ int port1_link_status; ++ int port2_link_status; ++ /* 1: blocking, 0: unblocking */ ++ int port0_block_status; ++ int port1_block_status; ++ int port2_block_status; ++}; ++ ++struct port_all_status { ++ /* 1: link is up, 0: link is down */ ++ int link_status; ++ /* 1: blocking, 0: unblocking */ ++ int block_status; ++ /* 1: unlearning, 0: learning */ ++ int learn_status; ++ /* vlan domain verify 1: enable 0: disable */ ++ int vlan_verify; ++ /* discard unknow 1: enable 0: disable */ ++ int discard_unknown; ++ /* multicast resolution 1: enable 0: disable */ ++ int multi_reso; ++ /* broadcast resolution 1: enable 0: disalbe */ ++ int broad_reso; ++ /* transmit 1: enable 0: disable */ ++ int ftransmit; ++ /* receive 1: enable 0: disable */ ++ int freceive; ++}; ++ ++/* The switch buffer descriptors track the ring buffers. The rx_bd_base and ++ * tx_bd_base always point to the base of the buffer descriptors. The ++ * cur_rx and cur_tx point to the currently available buffer. ++ * The dirty_tx tracks the current buffer that is being sent by the ++ * controller. The cur_tx and dirty_tx are equal under both completely ++ * empty and completely full conditions. The empty/ready indicator in ++ * the buffer descriptor determines the actual condition. ++ */ ++struct switch_enet_private { ++ /* Hardware registers of the switch device */ ++ volatile switch_t *hwp; ++ volatile eswAddrTable_t *hwentry; ++ ++ struct net_device *netdev; ++ struct platform_device *pdev; ++ /* The saved address of a sent-in-place packet/buffer, for skfree(). */ ++ unsigned char *tx_bounce[TX_RING_SIZE]; ++ struct sk_buff *tx_skbuff[TX_RING_SIZE]; ++ ushort skb_cur; ++ ushort skb_dirty; ++ ++ /* CPM dual port RAM relative addresses. ++ */ ++ cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ ++ cbd_t *tx_bd_base; ++ cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ ++ cbd_t *dirty_tx; /* The ring entries to be free()ed. */ ++ uint tx_full; ++ /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ ++ spinlock_t hw_lock; ++ ++ /* hold while accessing the mii_list_t() elements */ ++ spinlock_t mii_lock; ++ struct mii_bus *mdio_bus; ++ struct phy_device *phydev[SWITCH_EPORT_NUMBER]; ++ ++ uint phy_id; ++ uint phy_id_done; ++ uint phy_status; ++ uint phy_speed; ++ phy_info_t const *phy; ++ struct work_struct phy_task; ++ volatile switch_t *phy_hwp; ++ ++ uint sequence_done; ++ uint mii_phy_task_queued; ++ ++ uint phy_addr; ++ ++ int index; ++ int opened; ++ int full_duplex; ++ int msg_enable; ++ int phy1_link; ++ int phy1_old_link; ++ int phy1_duplex; ++ int phy1_speed; ++ ++ int phy2_link; ++ int phy2_old_link; ++ int phy2_duplex; ++ int phy2_speed; ++ /* --------------Statistics--------------------------- */ ++ /* when a new element deleted a element with in ++ * a block due to lack of space */ ++ int atBlockOverflows; ++ /* Peak number of valid entries in the address table */ ++ int atMaxEntries; ++ /* current number of valid entries in the address table */ ++ int atCurrEntries; ++ /* maximum entries within a block found ++ * (updated within ageing)*/ ++ int atMaxEntriesPerBlock; ++ ++ /* -------------------ageing function------------------ */ ++ /* maximum age allowed for an entry */ ++ int ageMax; ++ /* last LUT entry to block that was ++ * inspected by the Ageing task*/ ++ int ageLutIdx; ++ /* last element within block inspected by the Ageing task */ ++ int ageBlockElemIdx; ++ /* complete table has been processed by ageing process */ ++ int ageCompleted; ++ /* delay setting */ ++ int ageDelay; ++ /* current delay Counter */ ++ int ageDelayCnt; ++ ++ /* ----------------timer related---------------------------- */ ++ /* current time (for timestamping) */ ++ int currTime; ++ /* flag set by timer when currTime changed ++ * and cleared by serving function*/ ++ int timeChanged; ++ ++ /**/ ++ /* Timer for Aging */ ++ struct timer_list timer_aging; ++ int learning_irqhandle_enable; ++}; ++ ++struct switch_platform_private { ++ unsigned long quirks; ++ int num_slots; /* Slots on controller */ ++ struct switch_enet_private *fep_host[0]; /* Pointers to hosts */ ++}; ++ ++/******************************************************************************/ ++/* Recieve is empty */ ++#define BD_SC_EMPTY ((unsigned short)0x8000) ++/* Transmit is ready */ ++#define BD_SC_READY ((unsigned short)0x8000) ++/* Last buffer descriptor */ ++#define BD_SC_WRAP ((unsigned short)0x2000) ++/* Interrupt on change */ ++#define BD_SC_INTRPT ((unsigned short)0x1000) ++/* Continous mode */ ++#define BD_SC_CM ((unsigned short)0x0200) ++/* Rec'd too many idles */ ++#define BD_SC_ID ((unsigned short)0x0100) ++/* xmt preamble */ ++#define BD_SC_P ((unsigned short)0x0100) ++/* Break received */ ++#define BD_SC_BR ((unsigned short)0x0020) ++/* Framing error */ ++#define BD_SC_FR ((unsigned short)0x0010) ++/* Parity error */ ++#define BD_SC_PR ((unsigned short)0x0008) ++/* Overrun */ ++#define BD_SC_OV ((unsigned short)0x0002) ++#define BD_SC_CD ((unsigned short)0x0001) ++ ++/* Buffer descriptor control/status used by Ethernet receive. ++*/ ++#define BD_ENET_RX_EMPTY ((unsigned short)0x8000) ++#define BD_ENET_RX_WRAP ((unsigned short)0x2000) ++#define BD_ENET_RX_INTR ((unsigned short)0x1000) ++#define BD_ENET_RX_LAST ((unsigned short)0x0800) ++#define BD_ENET_RX_FIRST ((unsigned short)0x0400) ++#define BD_ENET_RX_MISS ((unsigned short)0x0100) ++#define BD_ENET_RX_LG ((unsigned short)0x0020) ++#define BD_ENET_RX_NO ((unsigned short)0x0010) ++#define BD_ENET_RX_SH ((unsigned short)0x0008) ++#define BD_ENET_RX_CR ((unsigned short)0x0004) ++#define BD_ENET_RX_OV ((unsigned short)0x0002) ++#define BD_ENET_RX_CL ((unsigned short)0x0001) ++/* All status bits */ ++#define BD_ENET_RX_STATS ((unsigned short)0x013f) ++ ++/* Buffer descriptor control/status used by Ethernet transmit. ++*/ ++#define BD_ENET_TX_READY ((unsigned short)0x8000) ++#define BD_ENET_TX_PAD ((unsigned short)0x4000) ++#define BD_ENET_TX_WRAP ((unsigned short)0x2000) ++#define BD_ENET_TX_INTR ((unsigned short)0x1000) ++#define BD_ENET_TX_LAST ((unsigned short)0x0800) ++#define BD_ENET_TX_TC ((unsigned short)0x0400) ++#define BD_ENET_TX_DEF ((unsigned short)0x0200) ++#define BD_ENET_TX_HB ((unsigned short)0x0100) ++#define BD_ENET_TX_LC ((unsigned short)0x0080) ++#define BD_ENET_TX_RL ((unsigned short)0x0040) ++#define BD_ENET_TX_RCMASK ((unsigned short)0x003c) ++#define BD_ENET_TX_UN ((unsigned short)0x0002) ++#define BD_ENET_TX_CSL ((unsigned short)0x0001) ++/* All status bits */ ++#define BD_ENET_TX_STATS ((unsigned short)0x03ff) ++ ++/*Copy from validation code */ ++#define RX_BUFFER_SIZE 1520 ++#define TX_BUFFER_SIZE 1520 ++#define NUM_RXBDS 20 ++#define NUM_TXBDS 20 ++ ++#define TX_BD_R 0x8000 ++#define TX_BD_TO1 0x4000 ++#define TX_BD_W 0x2000 ++#define TX_BD_TO2 0x1000 ++#define TX_BD_L 0x0800 ++#define TX_BD_TC 0x0400 ++ ++#define TX_BD_INT 0x40000000 ++#define TX_BD_TS 0x20000000 ++#define TX_BD_PINS 0x10000000 ++#define TX_BD_IINS 0x08000000 ++#define TX_BD_TXE 0x00008000 ++#define TX_BD_UE 0x00002000 ++#define TX_BD_EE 0x00001000 ++#define TX_BD_FE 0x00000800 ++#define TX_BD_LCE 0x00000400 ++#define TX_BD_OE 0x00000200 ++#define TX_BD_TSE 0x00000100 ++#define TX_BD_BDU 0x80000000 ++ ++#define RX_BD_E 0x8000 ++#define RX_BD_R01 0x4000 ++#define RX_BD_W 0x2000 ++#define RX_BD_R02 0x1000 ++#define RX_BD_L 0x0800 ++#define RX_BD_M 0x0100 ++#define RX_BD_BC 0x0080 ++#define RX_BD_MC 0x0040 ++#define RX_BD_LG 0x0020 ++#define RX_BD_NO 0x0010 ++#define RX_BD_CR 0x0004 ++#define RX_BD_OV 0x0002 ++#define RX_BD_TR 0x0001 ++ ++#define RX_BD_ME 0x80000000 ++#define RX_BD_PE 0x04000000 ++#define RX_BD_CE 0x02000000 ++#define RX_BD_UC 0x01000000 ++#define RX_BD_INT 0x00800000 ++#define RX_BD_ICE 0x00000020 ++#define RX_BD_PCR 0x00000010 ++#define RX_BD_VLAN 0x00000004 ++#define RX_BD_IPV6 0x00000002 ++#define RX_BD_FRAG 0x00000001 ++#define RX_BD_BDU 0x80000000 ++/****************************************************************************/ ++ ++/* Address Table size in bytes(2048 64bit entry ) */ ++#define ESW_ATABLE_MEM_SIZE (2048*8) ++/* How many 64-bit elements fit in the address table */ ++#define ESW_ATABLE_MEM_NUM_ENTRIES (2048) ++/* Address Table Maximum number of entries in each Slot */ ++#define ATABLE_ENTRY_PER_SLOT 8 ++/* log2(ATABLE_ENTRY_PER_SLOT)*/ ++#define ATABLE_ENTRY_PER_SLOT_bits 3 ++/* entry size in byte */ ++#define ATABLE_ENTRY_SIZE 8 ++/* slot size in byte */ ++#define ATABLE_SLOT_SIZE (ATABLE_ENTRY_PER_SLOT * ATABLE_ENTRY_SIZE) ++/* width of timestamp variable (bits) within address table entry */ ++#define AT_DENTRY_TIMESTAMP_WIDTH 10 ++/* number of bits for port number storage */ ++#define AT_DENTRY_PORT_WIDTH 4 ++/* number of bits for port bitmask number storage */ ++#define AT_SENTRY_PORT_WIDTH 7 ++/* address table static entry port bitmask start address bit */ ++#define AT_SENTRY_PORTMASK_shift 21 ++/* number of bits for port priority storage */ ++#define AT_SENTRY_PRIO_WIDTH 7 ++/* address table static entry priority start address bit */ ++#define AT_SENTRY_PRIO_shift 18 ++/* address table dynamic entry port start address bit */ ++#define AT_DENTRY_PORT_shift 28 ++/* address table dynamic entry timestamp start address bit */ ++#define AT_DENTRY_TIME_shift 18 ++/* address table entry record type start address bit */ ++#define AT_ENTRY_TYPE_shift 17 ++/* address table entry record type bit: 1 static, 0 dynamic */ ++#define AT_ENTRY_TYPE_STATIC 1 ++#define AT_ENTRY_TYPE_DYNAMIC 0 ++/* address table entry record valid start address bit */ ++#define AT_ENTRY_VALID_shift 16 ++#define AT_ENTRY_RECORD_VALID 1 ++ ++#define AT_EXTRACT_VALID(x) \ ++ ((x >> AT_ENTRY_VALID_shift) & AT_ENTRY_RECORD_VALID) ++ ++#define AT_EXTRACT_PORTMASK(x) \ ++ ((x >> AT_SENTRY_PORTMASK_shift) & AT_SENTRY_PORT_WIDTH) ++ ++#define AT_EXTRACT_PRIO(x) \ ++ ((x >> AT_SENTRY_PRIO_shift) & AT_SENTRY_PRIO_WIDTH) ++ ++/* return block corresponding to the 8 bit hash value calculated */ ++#define GET_BLOCK_PTR(hash) (hash << 3) ++#define AT_EXTRACT_TIMESTAMP(x) \ ++ ((x >> AT_DENTRY_TIME_shift) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) ++#define AT_EXTRACT_PORT(x) \ ++ ((x >> AT_DENTRY_PORT_shift) & ((1 << AT_DENTRY_PORT_WIDTH)-1)) ++#define AT_SEXTRACT_PORT(x) \ ++ ((~((x >> AT_SENTRY_PORTMASK_shift) & \ ++ ((1 << AT_DENTRY_PORT_WIDTH)-1))) >> 1) ++#define TIMEDELTA(newtime, oldtime) \ ++ ((newtime - oldtime) & \ ++ ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) ++ ++#define AT_EXTRACT_IP_PROTOCOL(x) ((x >> 8) & 0xff) ++#define AT_EXTRACT_TCP_UDP_PORT(x) ((x >> 16) & 0xffff) ++ ++/* increment time value respecting modulo. */ ++#define TIMEINCREMENT(time) \ ++ ((time) = ((time)+1) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) ++/* ------------------------------------------------------------------------- */ ++/* Bit definitions and macros for MCF_ESW_REVISION */ ++#define MCF_ESW_REVISION_CORE_REVISION(x) (((x)&0x0000FFFF)<<0) ++#define MCF_ESW_REVISION_CUSTOMER_REVISION(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_ESW_PER */ ++#define MCF_ESW_PER_TE0 (0x00000001) ++#define MCF_ESW_PER_TE1 (0x00000002) ++#define MCF_ESW_PER_TE2 (0x00000004) ++#define MCF_ESW_PER_RE0 (0x00010000) ++#define MCF_ESW_PER_RE1 (0x00020000) ++#define MCF_ESW_PER_RE2 (0x00040000) ++ ++/* Bit definitions and macros for MCF_ESW_VLANV */ ++#define MCF_ESW_VLANV_VV0 (0x00000001) ++#define MCF_ESW_VLANV_VV1 (0x00000002) ++#define MCF_ESW_VLANV_VV2 (0x00000004) ++#define MCF_ESW_VLANV_DU0 (0x00010000) ++#define MCF_ESW_VLANV_DU1 (0x00020000) ++#define MCF_ESW_VLANV_DU2 (0x00040000) ++ ++/* Bit definitions and macros for MCF_ESW_DBCR */ ++#define MCF_ESW_DBCR_P0 (0x00000001) ++#define MCF_ESW_DBCR_P1 (0x00000002) ++#define MCF_ESW_DBCR_P2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_DMCR */ ++#define MCF_ESW_DMCR_P0 (0x00000001) ++#define MCF_ESW_DMCR_P1 (0x00000002) ++#define MCF_ESW_DMCR_P2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_BKLR */ ++#define MCF_ESW_BKLR_BE0 (0x00000001) ++#define MCF_ESW_BKLR_BE1 (0x00000002) ++#define MCF_ESW_BKLR_BE2 (0x00000004) ++#define MCF_ESW_BKLR_LD0 (0x00010000) ++#define MCF_ESW_BKLR_LD1 (0x00020000) ++#define MCF_ESW_BKLR_LD2 (0x00040000) ++ ++/* Bit definitions and macros for MCF_ESW_BMPC */ ++#define MCF_ESW_BMPC_PORT(x) (((x)&0x0000000F)<<0) ++#define MCF_ESW_BMPC_MSG_TX (0x00000020) ++#define MCF_ESW_BMPC_EN (0x00000040) ++#define MCF_ESW_BMPC_DIS (0x00000080) ++#define MCF_ESW_BMPC_PRIORITY(x) (((x)&0x00000007)<<13) ++#define MCF_ESW_BMPC_PORTMASK(x) (((x)&0x00000007)<<16) ++ ++/* Bit definitions and macros for MCF_ESW_MODE */ ++#define MCF_ESW_MODE_SW_RST (0x00000001) ++#define MCF_ESW_MODE_SW_EN (0x00000002) ++#define MCF_ESW_MODE_STOP (0x00000080) ++#define MCF_ESW_MODE_CRC_TRAN (0x00000100) ++#define MCF_ESW_MODE_P0CT (0x00000200) ++#define MCF_ESW_MODE_STATRST (0x80000000) ++ ++/* Bit definitions and macros for MCF_ESW_VIMSEL */ ++#define MCF_ESW_VIMSEL_IM0(x) (((x)&0x00000003)<<0) ++#define MCF_ESW_VIMSEL_IM1(x) (((x)&0x00000003)<<2) ++#define MCF_ESW_VIMSEL_IM2(x) (((x)&0x00000003)<<4) ++ ++/* Bit definitions and macros for MCF_ESW_VOMSEL */ ++#define MCF_ESW_VOMSEL_OM0(x) (((x)&0x00000003)<<0) ++#define MCF_ESW_VOMSEL_OM1(x) (((x)&0x00000003)<<2) ++#define MCF_ESW_VOMSEL_OM2(x) (((x)&0x00000003)<<4) ++ ++/* Bit definitions and macros for MCF_ESW_VIMEN */ ++#define MCF_ESW_VIMEN_EN0 (0x00000001) ++#define MCF_ESW_VIMEN_EN1 (0x00000002) ++#define MCF_ESW_VIMEN_EN2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_VID */ ++#define MCF_ESW_VID_TAG(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_MCR */ ++#define MCF_ESW_MCR_PORT(x) (((x)&0x0000000F)<<0) ++#define MCF_ESW_MCR_MEN (0x00000010) ++#define MCF_ESW_MCR_INGMAP (0x00000020) ++#define MCF_ESW_MCR_EGMAP (0x00000040) ++#define MCF_ESW_MCR_INGSA (0x00000080) ++#define MCF_ESW_MCR_INGDA (0x00000100) ++#define MCF_ESW_MCR_EGSA (0x00000200) ++#define MCF_ESW_MCR_EGDA (0x00000400) ++ ++/* Bit definitions and macros for MCF_ESW_EGMAP */ ++#define MCF_ESW_EGMAP_EG0 (0x00000001) ++#define MCF_ESW_EGMAP_EG1 (0x00000002) ++#define MCF_ESW_EGMAP_EG2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_INGMAP */ ++#define MCF_ESW_INGMAP_ING0 (0x00000001) ++#define MCF_ESW_INGMAP_ING1 (0x00000002) ++#define MCF_ESW_INGMAP_ING2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_INGSAL */ ++#define MCF_ESW_INGSAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_INGSAH */ ++#define MCF_ESW_INGSAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_INGDAL */ ++#define MCF_ESW_INGDAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_INGDAH */ ++#define MCF_ESW_INGDAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_ENGSAL */ ++#define MCF_ESW_ENGSAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_ENGSAH */ ++#define MCF_ESW_ENGSAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_ENGDAL */ ++#define MCF_ESW_ENGDAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_ENGDAH */ ++#define MCF_ESW_ENGDAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_MCVAL */ ++#define MCF_ESW_MCVAL_COUNT(x) (((x)&0x000000FF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_MMSR */ ++#define MCF_ESW_MMSR_BUSY (0x00000001) ++#define MCF_ESW_MMSR_NOCELL (0x00000002) ++#define MCF_ESW_MMSR_MEMFULL (0x00000004) ++#define MCF_ESW_MMSR_MFLATCH (0x00000008) ++#define MCF_ESW_MMSR_DQ_GRNT (0x00000040) ++#define MCF_ESW_MMSR_CELLS_AVAIL(x) (((x)&0x000000FF)<<16) ++ ++/* Bit definitions and macros for MCF_ESW_LMT */ ++#define MCF_ESW_LMT_THRESH(x) (((x)&0x000000FF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_LFC */ ++#define MCF_ESW_LFC_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_PCSR */ ++#define MCF_ESW_PCSR_PC0 (0x00000001) ++#define MCF_ESW_PCSR_PC1 (0x00000002) ++#define MCF_ESW_PCSR_PC2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_IOSR */ ++#define MCF_ESW_IOSR_OR0 (0x00000001) ++#define MCF_ESW_IOSR_OR1 (0x00000002) ++#define MCF_ESW_IOSR_OR2 (0x00000004) ++ ++/* Bit definitions and macros for MCF_ESW_QWT */ ++#define MCF_ESW_QWT_Q0WT(x) (((x)&0x0000001F)<<0) ++#define MCF_ESW_QWT_Q1WT(x) (((x)&0x0000001F)<<8) ++#define MCF_ESW_QWT_Q2WT(x) (((x)&0x0000001F)<<16) ++#define MCF_ESW_QWT_Q3WT(x) (((x)&0x0000001F)<<24) ++ ++/* Bit definitions and macros for MCF_ESW_P0BCT */ ++#define MCF_ESW_P0BCT_THRESH(x) (((x)&0x000000FF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_P0FFEN */ ++#define MCF_ESW_P0FFEN_FEN (0x00000001) ++#define MCF_ESW_P0FFEN_FD(x) (((x)&0x00000003)<<2) ++ ++/* Bit definitions and macros for MCF_ESW_PSNP */ ++#define MCF_ESW_PSNP_EN (0x00000001) ++#define MCF_ESW_PSNP_MODE(x) (((x)&0x00000003)<<1) ++#define MCF_ESW_PSNP_CD (0x00000008) ++#define MCF_ESW_PSNP_CS (0x00000010) ++#define MCF_ESW_PSNP_PORT_COMPARE(x) (((x)&0x0000FFFF)<<16) ++ ++/* Bit definitions and macros for MCF_ESW_IPSNP */ ++#define MCF_ESW_IPSNP_EN (0x00000001) ++#define MCF_ESW_IPSNP_MODE(x) (((x)&0x00000003)<<1) ++#define MCF_ESW_IPSNP_PROTOCOL(x) (((x)&0x000000FF)<<8) ++ ++/* Bit definitions and macros for MCF_ESW_PVRES */ ++#define MCF_ESW_PVRES_PRI0(x) (((x)&0x00000007)<<0) ++#define MCF_ESW_PVRES_PRI1(x) (((x)&0x00000007)<<3) ++#define MCF_ESW_PVRES_PRI2(x) (((x)&0x00000007)<<6) ++#define MCF_ESW_PVRES_PRI3(x) (((x)&0x00000007)<<9) ++#define MCF_ESW_PVRES_PRI4(x) (((x)&0x00000007)<<12) ++#define MCF_ESW_PVRES_PRI5(x) (((x)&0x00000007)<<15) ++#define MCF_ESW_PVRES_PRI6(x) (((x)&0x00000007)<<18) ++#define MCF_ESW_PVRES_PRI7(x) (((x)&0x00000007)<<21) ++ ++/* Bit definitions and macros for MCF_ESW_IPRES */ ++#define MCF_ESW_IPRES_ADDRESS(x) (((x)&0x000000FF)<<0) ++#define MCF_ESW_IPRES_IPV4SEL (0x00000100) ++#define MCF_ESW_IPRES_PRI0(x) (((x)&0x00000003)<<9) ++#define MCF_ESW_IPRES_PRI1(x) (((x)&0x00000003)<<11) ++#define MCF_ESW_IPRES_PRI2(x) (((x)&0x00000003)<<13) ++#define MCF_ESW_IPRES_READ (0x80000000) ++ ++/* Bit definitions and macros for MCF_ESW_PRES */ ++#define MCF_ESW_PRES_VLAN (0x00000001) ++#define MCF_ESW_PRES_IP (0x00000002) ++#define MCF_ESW_PRES_MAC (0x00000004) ++#define MCF_ESW_PRES_DFLT_PRI(x) (((x)&0x00000007)<<4) ++ ++/* Bit definitions and macros for MCF_ESW_PID */ ++#define MCF_ESW_PID_VLANID(x) (((x)&0x0000FFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_VRES */ ++#define MCF_ESW_VRES_P0 (0x00000001) ++#define MCF_ESW_VRES_P1 (0x00000002) ++#define MCF_ESW_VRES_P2 (0x00000004) ++#define MCF_ESW_VRES_VLANID(x) (((x)&0x00000FFF)<<3) ++ ++/* Bit definitions and macros for MCF_ESW_DISCN */ ++#define MCF_ESW_DISCN_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_DISCB */ ++#define MCF_ESW_DISCB_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_NDISCN */ ++#define MCF_ESW_NDISCN_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_NDISCB */ ++#define MCF_ESW_NDISCB_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_POQC */ ++#define MCF_ESW_POQC_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_PMVID */ ++#define MCF_ESW_PMVID_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_PMVTAG */ ++#define MCF_ESW_PMVTAG_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_PBL */ ++#define MCF_ESW_PBL_COUNT(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_ISR */ ++#define MCF_ESW_ISR_EBERR (0x00000001) ++#define MCF_ESW_ISR_RXB (0x00000002) ++#define MCF_ESW_ISR_RXF (0x00000004) ++#define MCF_ESW_ISR_TXB (0x00000008) ++#define MCF_ESW_ISR_TXF (0x00000010) ++#define MCF_ESW_ISR_QM (0x00000020) ++#define MCF_ESW_ISR_OD0 (0x00000040) ++#define MCF_ESW_ISR_OD1 (0x00000080) ++#define MCF_ESW_ISR_OD2 (0x00000100) ++#define MCF_ESW_ISR_LRN (0x00000200) ++ ++/* Bit definitions and macros for MCF_ESW_IMR */ ++#define MCF_ESW_IMR_EBERR (0x00000001) ++#define MCF_ESW_IMR_RXB (0x00000002) ++#define MCF_ESW_IMR_RXF (0x00000004) ++#define MCF_ESW_IMR_TXB (0x00000008) ++#define MCF_ESW_IMR_TXF (0x00000010) ++#define MCF_ESW_IMR_QM (0x00000020) ++#define MCF_ESW_IMR_OD0 (0x00000040) ++#define MCF_ESW_IMR_OD1 (0x00000080) ++#define MCF_ESW_IMR_OD2 (0x00000100) ++#define MCF_ESW_IMR_LRN (0x00000200) ++ ++/* Bit definitions and macros for MCF_ESW_RDSR */ ++#define MCF_ESW_RDSR_ADDRESS(x) (((x)&0x3FFFFFFF)<<2) ++ ++/* Bit definitions and macros for MCF_ESW_TDSR */ ++#define MCF_ESW_TDSR_ADDRESS(x) (((x)&0x3FFFFFFF)<<2) ++ ++/* Bit definitions and macros for MCF_ESW_MRBR */ ++#define MCF_ESW_MRBR_SIZE(x) (((x)&0x000003FF)<<4) ++ ++/* Bit definitions and macros for MCF_ESW_RDAR */ ++#define MCF_ESW_RDAR_R_DES_ACTIVE (0x01000000) ++ ++/* Bit definitions and macros for MCF_ESW_TDAR */ ++#define MCF_ESW_TDAR_X_DES_ACTIVE (0x01000000) ++ ++/* Bit definitions and macros for MCF_ESW_LREC0 */ ++#define MCF_ESW_LREC0_MACADDR0(x) (((x)&0xFFFFFFFF)<<0) ++ ++/* Bit definitions and macros for MCF_ESW_LREC1 */ ++#define MCF_ESW_LREC1_MACADDR1(x) (((x)&0x0000FFFF)<<0) ++#define MCF_ESW_LREC1_HASH(x) (((x)&0x000000FF)<<16) ++#define MCF_ESW_LREC1_SWPORT(x) (((x)&0x00000003)<<24) ++ ++/* Bit definitions and macros for MCF_ESW_LSR */ ++#define MCF_ESW_LSR_DA (0x00000001) ++ ++/* port mirroring port number match */ ++#define MIRROR_EGRESS_PORT_MATCH 1 ++#define MIRROR_INGRESS_PORT_MATCH 2 ++ ++/* port mirroring mac address match */ ++#define MIRROR_EGRESS_SOURCE_MATCH 1 ++#define MIRROR_INGRESS_SOURCE_MATCH 2 ++#define MIRROR_EGRESS_DESTINATION_MATCH 3 ++#define MIRROR_INGRESS_DESTINATION_MATCH 4 ++ ++#endif /* SWITCH_H */ +--- a/include/linux/fsl_devices.h ++++ b/include/linux/fsl_devices.h +@@ -129,4 +129,21 @@ struct fsl_ata_platform_data { + void (*exit)(void); + int (*get_clk_rate)(void); + }; ++ ++struct net_device; ++struct coldfire_switch_platform_data { ++ int hash_table; ++ unsigned int *switch_hw; ++ void (*request_intrs)(struct net_device *dev, ++ irqreturn_t (*)(int, void *), ++ void *irq_privatedata); ++ void (*set_mii)(struct net_device *dev); ++ void (*get_mac)(struct net_device *dev); ++ void (*enable_phy_intr)(void); ++ void (*disable_phy_intr)(void); ++ void (*phy_ack_intr)(void); ++ void (*localhw_setup)(void); ++ void (*uncache)(unsigned long addr); ++ void (*platform_flush_cache)(void); ++}; + #endif /* _FSL_DEVICE_H_ */ +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -4756,6 +4756,10 @@ static int dev_ifsioc(struct net *net, s + default: + if ((cmd >= SIOCDEVPRIVATE && + cmd <= SIOCDEVPRIVATE + 15) || ++#if defined(CONFIG_MODELO_SWITCH) ++ (cmd >= 0x9101 && ++ cmd <= 0x92ff) || ++#endif + cmd == SIOCBONDENSLAVE || + cmd == SIOCBONDRELEASE || + cmd == SIOCBONDSETHWADDR || +@@ -4948,6 +4952,10 @@ int dev_ioctl(struct net *net, unsigned + */ + default: + if (cmd == SIOCWANDEV || ++#if defined(CONFIG_MODELO_SWITCH) ++ (cmd >= 0x9101 && ++ cmd <= 0x92ff) || ++#endif + (cmd >= SIOCDEVPRIVATE && + cmd <= SIOCDEVPRIVATE + 15)) { + dev_load(net, ifr.ifr_name); diff --git a/target/linux/coldfire/patches/022-Redefine-I-O-read-and-write-functions.patch b/target/linux/coldfire/patches/022-Redefine-I-O-read-and-write-functions.patch new file mode 100644 index 000000000..921891bbd --- /dev/null +++ b/target/linux/coldfire/patches/022-Redefine-I-O-read-and-write-functions.patch @@ -0,0 +1,32 @@ +From f8dab3ef2c0da1c50dee07142c0b8088da61bc82 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:45 +0800 +Subject: [PATCH 22/52] Redefine I/O read and write functions + +Redefine readb(), writeb(), readw(), writew(), readl(), write() +functions. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/cf_io.h | 10 ++++++++++ + 1 files changed, 10 insertions(+), 0 deletions(-) + +--- a/arch/m68k/include/asm/cf_io.h ++++ b/arch/m68k/include/asm/cf_io.h +@@ -20,6 +20,16 @@ + + #include <asm-generic/iomap.h> + ++/* ++ * These should be valid on any ioremap()ed region ++ */ ++#define readb(addr) in_8(addr) ++#define writeb(val, addr) out_8((addr), (val)) ++#define readw(addr) in_le16(addr) ++#define writew(val, addr) out_le16((addr), (val)) ++#define readl(addr) in_le32(addr) ++#define writel(val, addr) out_le32((addr), (val)) ++ + #define readb_relaxed(addr) readb(addr) + #define readw_relaxed(addr) readw(addr) + #define readl_relaxed(addr) readl(addr) diff --git a/target/linux/coldfire/patches/023-Replace-readl-and-writel-for-FEC-driver.patch b/target/linux/coldfire/patches/023-Replace-readl-and-writel-for-FEC-driver.patch new file mode 100644 index 000000000..d8736023c --- /dev/null +++ b/target/linux/coldfire/patches/023-Replace-readl-and-writel-for-FEC-driver.patch @@ -0,0 +1,357 @@ +From f7df9a8f3ce3a600ceeb7302bf0de899f321c818 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:45 +0800 +Subject: [PATCH 23/52] Replace readl and writel for FEC driver + +Replace readl and writel by fec_readl and fec_writel +for FEC driver. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/net/fec.c | 129 ++++++++++++++++++++++++++++------------------------- + 1 files changed, 68 insertions(+), 61 deletions(-) + +--- a/drivers/net/fec.c ++++ b/drivers/net/fec.c +@@ -244,6 +244,11 @@ static void fec_stop(struct net_device * + /* Transmitter timeout */ + #define TX_TIMEOUT (2 * HZ) + ++#define fec_readl(addr) \ ++ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) ++#define fec_writel(b, addr) \ ++ (void)((*(volatile unsigned int *) (addr)) = (b)) ++ + static void *swap_buffer(void *bufaddr, int len) + { + int i; +@@ -347,7 +352,7 @@ fec_enet_start_xmit(struct sk_buff *skb, + bdp->cbd_sc = status; + + /* Trigger transmission start */ +- writel(0, fep->hwp + FEC_X_DES_ACTIVE); ++ fec_writel(0, fep->hwp + FEC_X_DES_ACTIVE); + + /* If this was the last BD in the ring, start at the beginning again. */ + if (status & BD_ENET_TX_WRAP) +@@ -390,8 +395,8 @@ fec_enet_interrupt(int irq, void * dev_i + irqreturn_t ret = IRQ_NONE; + + do { +- int_events = readl(fep->hwp + FEC_IEVENT); +- writel(int_events, fep->hwp + FEC_IEVENT); ++ int_events = fec_readl(fep->hwp + FEC_IEVENT); ++ fec_writel(int_events, fep->hwp + FEC_IEVENT); + + #ifdef CONFIG_FEC_1588 + if (__raw_readb(MCF_DTIM1_DTER) & MCF_DTIM_DTER_REF) +@@ -646,7 +651,7 @@ rx_processing_done: + * incoming frames. On a heavily loaded network, we should be + * able to keep up at the expense of system resources. + */ +- writel(0, fep->hwp + FEC_R_DES_ACTIVE); ++ fec_writel(0, fep->hwp + FEC_R_DES_ACTIVE); + } + fep->cur_rx = bdp; + +@@ -686,9 +691,9 @@ static void __inline__ fec_get_mac(struc + */ + if (!is_valid_ether_addr(iap)) { + *((unsigned long *) &tmpaddr[0]) = +- be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); ++ be32_to_cpu(fec_readl(fep->hwp + FEC_ADDR_LOW)); + *((unsigned short *) &tmpaddr[4]) = +- be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); ++ be16_to_cpu(fec_readl(fep->hwp + FEC_ADDR_HIGH) >> 16); + iap = &tmpaddr[0]; + } + +@@ -740,9 +745,9 @@ static void fec_enet_adjust_link(struct + + if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) + #ifdef CONFIG_FEC_1588 +- writel(0x00000012, fep->hwp + FEC_ECNTRL); ++ fec_writel(0x00000012, fep->hwp + FEC_ECNTRL); + #else +- writel(0x00000002, fep->hwp + FEC_ECNTRL); ++ fec_writel(0x00000002, fep->hwp + FEC_ECNTRL); + #endif + status_change = 1; + } +@@ -763,7 +768,7 @@ static int fec_enet_mdio_read(struct mii + init_completion(&fep->mdio_done); + + /* start a read op */ +- writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | ++ fec_writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); + +@@ -777,7 +782,7 @@ static int fec_enet_mdio_read(struct mii + } + + /* return value */ +- return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); ++ return FEC_MMFR_DATA(fec_readl(fep->hwp + FEC_MII_DATA)); + } + + static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, +@@ -790,7 +795,7 @@ static int fec_enet_mdio_write(struct mi + init_completion(&fep->mdio_done); + + /* start a write op */ +- writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | ++ fec_writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->hwp + FEC_MII_DATA); +@@ -905,7 +910,7 @@ static int fec_enet_mii_init(struct plat + * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) + */ + fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; +- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); ++ fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + + fep->mii_bus = mdiobus_alloc(); + if (fep->mii_bus == NULL) { +@@ -1151,30 +1156,30 @@ static void set_multicast_list(struct ne + unsigned char hash; + + if (dev->flags & IFF_PROMISC) { +- tmp = readl(fep->hwp + FEC_R_CNTRL); ++ tmp = fec_readl(fep->hwp + FEC_R_CNTRL); + tmp |= 0x8; +- writel(tmp, fep->hwp + FEC_R_CNTRL); ++ fec_writel(tmp, fep->hwp + FEC_R_CNTRL); + return; + } + +- tmp = readl(fep->hwp + FEC_R_CNTRL); ++ tmp = fec_readl(fep->hwp + FEC_R_CNTRL); + tmp &= ~0x8; +- writel(tmp, fep->hwp + FEC_R_CNTRL); ++ fec_writel(tmp, fep->hwp + FEC_R_CNTRL); + + if (dev->flags & IFF_ALLMULTI) { + /* Catch all multicast addresses, so set the + * filter to all 1's + */ +- writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); +- writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); ++ fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); ++ fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); + + return; + } + + /* Clear filter and add the addresses in hash register + */ +- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); +- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); ++ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); ++ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); + + netdev_for_each_mc_addr(ha, dev) { + /* Only support group multicast for now */ +@@ -1198,13 +1203,13 @@ static void set_multicast_list(struct ne + hash = (crc >> (32 - HASH_BITS)) & 0x3f; + + if (hash > 31) { +- tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); ++ tmp = fec_readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); + tmp |= 1 << (hash - 32); +- writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); ++ fec_writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); + } else { +- tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); ++ tmp = fec_readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); + tmp |= 1 << hash; +- writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); ++ fec_writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); + } + } + } +@@ -1221,10 +1226,10 @@ fec_set_mac_address(struct net_device *d + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + +- writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | ++ fec_writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | + (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), + fep->hwp + FEC_ADDR_LOW); +- writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), ++ fec_writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), + fep->hwp + FEC_ADDR_HIGH); + return 0; + } +@@ -1323,7 +1328,7 @@ fec_restart(struct net_device *dev, int + u32 val, temp_mac[2]; + + /* Whack a reset. We should wait for this. */ +- writel(1, fep->hwp + FEC_ECNTRL); ++ fec_writel(1, fep->hwp + FEC_ECNTRL); + udelay(10); + + /* +@@ -1332,31 +1337,32 @@ fec_restart(struct net_device *dev, int + */ + if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { + memcpy(&temp_mac, dev->dev_addr, ETH_ALEN); +- writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); +- writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); ++ fec_writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); ++ fec_writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); + } + + #ifdef CONFIG_FEC_1588 +- writel(0x7fff8000, fep->hwp + FEC_IEVENT); ++ fec_writel(0x7fff8000, fep->hwp + FEC_IEVENT); + #else + /* Clear any outstanding interrupt. */ +- writel(0xffc00000, fep->hwp + FEC_IEVENT); ++ fec_writel(0xffc00000, fep->hwp + FEC_IEVENT); + #endif + + /* Reset all multicast. */ +- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); +- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); ++ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); ++ fec_writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); + #ifndef CONFIG_M5272 +- writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); +- writel(0, fep->hwp + FEC_HASH_TABLE_LOW); ++ fec_writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); ++ fec_writel(0, fep->hwp + FEC_HASH_TABLE_LOW); + #endif + + /* Set maximum receive buffer size. */ +- writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); ++ fec_writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); + + /* Set receive and transmit descriptor base. */ +- writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); +- writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, ++ fec_writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); ++ fec_writel((unsigned long)fep->bd_dma + ++ sizeof(struct bufdesc) * RX_RING_SIZE, + fep->hwp + FEC_X_DES_START); + + fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; +@@ -1374,24 +1380,24 @@ fec_restart(struct net_device *dev, int + /* Enable MII mode */ + if (duplex) { + /* MII enable / FD enable */ +- writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); +- writel(0x04, fep->hwp + FEC_X_CNTRL); ++ fec_writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); ++ fec_writel(0x04, fep->hwp + FEC_X_CNTRL); + } else { + /* MII enable / No Rcv on Xmit */ +- writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); +- writel(0x0, fep->hwp + FEC_X_CNTRL); ++ fec_writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); ++ fec_writel(0x0, fep->hwp + FEC_X_CNTRL); + } + fep->full_duplex = duplex; + + /* Set MII speed */ +- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); ++ fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + + /* + * The phy interface and speed need to get configured + * differently on enet-mac. + */ + if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { +- val = readl(fep->hwp + FEC_R_CNTRL); ++ val = fec_readl(fep->hwp + FEC_R_CNTRL); + + /* MII or RMII */ + if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) +@@ -1405,23 +1411,23 @@ fec_restart(struct net_device *dev, int + else + val |= (1 << 9); + +- writel(val, fep->hwp + FEC_R_CNTRL); ++ fec_writel(val, fep->hwp + FEC_R_CNTRL); + } else { + #ifdef FEC_MIIGSK_ENR + if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { + /* disable the gasket and wait */ +- writel(0, fep->hwp + FEC_MIIGSK_ENR); +- while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) ++ fec_writel(0, fep->hwp + FEC_MIIGSK_ENR); ++ while (fec_readl(fep->hwp + FEC_MIIGSK_ENR) & 4) + udelay(1); + + /* + * configure the gasket: + * RMII, 50 MHz, no loopback, no echo + */ +- writel(1, fep->hwp + FEC_MIIGSK_CFGR); ++ fec_writel(1, fep->hwp + FEC_MIIGSK_CFGR); + + /* re-enable the gasket */ +- writel(2, fep->hwp + FEC_MIIGSK_ENR); ++ fec_writel(2, fep->hwp + FEC_MIIGSK_ENR); + } + #endif + } +@@ -1433,22 +1439,22 @@ fec_restart(struct net_device *dev, int + ret = fec_ptp_start(fep->ptp_priv); + if (ret) { + fep->ptimer_present = 0; +- writel(2, fep->hwp + FEC_ECNTRL); ++ fec_writel(2, fep->hwp + FEC_ECNTRL); + } else { +- val = readl(fep->hwp + FEC_ECNTRL); ++ val = fec_readl(fep->hwp + FEC_ECNTRL); + val |= 0x00000012; +- writel(val, fep->hwp + FEC_ECNTRL); ++ fec_writel(val, fep->hwp + FEC_ECNTRL); + } + } else +- writel(2, fep->hwp + FEC_ECNTRL); ++ fec_writel(2, fep->hwp + FEC_ECNTRL); + #else + /* And last, enable the transmit and receive processing */ +- writel(2, fep->hwp + FEC_ECNTRL); ++ fec_writel(2, fep->hwp + FEC_ECNTRL); + #endif +- writel(0, fep->hwp + FEC_R_DES_ACTIVE); ++ fec_writel(0, fep->hwp + FEC_R_DES_ACTIVE); + + /* Enable interrupts we wish to service */ +- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); ++ fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + } + + static void +@@ -1458,21 +1464,22 @@ fec_stop(struct net_device *dev) + + /* We cannot expect a graceful transmit stop without link !!! */ + if (fep->link) { +- writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ ++ /* Graceful transmit stop */ ++ fec_writel(1, fep->hwp + FEC_X_CNTRL); + udelay(10); +- if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) ++ if (!(fec_readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) + printk("fec_stop : Graceful transmit stop did not complete !\n"); + } + + /* Whack a reset. We should wait for this. */ +- writel(1, fep->hwp + FEC_ECNTRL); ++ fec_writel(1, fep->hwp + FEC_ECNTRL); + udelay(10); +- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); ++ fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + #ifdef CONFIG_FEC_1588 + if (fep->ptimer_present) + fec_ptp_stop(fep->ptp_priv); + #endif +- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); ++ fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + } + + static int __devinit diff --git a/target/linux/coldfire/patches/024-Add-SEC-1.1-support-for-MCF547x-and-MCF548x.patch b/target/linux/coldfire/patches/024-Add-SEC-1.1-support-for-MCF547x-and-MCF548x.patch new file mode 100644 index 000000000..53cebe184 --- /dev/null +++ b/target/linux/coldfire/patches/024-Add-SEC-1.1-support-for-MCF547x-and-MCF548x.patch @@ -0,0 +1,2093 @@ +From c925421b8c35357427499f3d298777535c2c6cfd Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:45 +0800 +Subject: [PATCH 24/52] Add SEC 1.1 support for MCF547x and MCF548x + +Add SEC 1.1 support for MCF547x and MCF548x. The SEC driver is +in drivers/crypto. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m547x/mcf548x-devices.c | 2 +- + arch/m68k/include/asm/cf_io.h | 4 + + crypto/testmgr.c | 18 +- + drivers/crypto/Kconfig | 13 + + drivers/crypto/Makefile | 1 + + drivers/crypto/cf_talitos.c | 1727 ++++++++++++++++++++++++++++ + drivers/crypto/cf_talitos.h | 229 ++++ + 7 files changed, 1989 insertions(+), 5 deletions(-) + create mode 100644 drivers/crypto/cf_talitos.c + create mode 100644 drivers/crypto/cf_talitos.h + +--- a/arch/m68k/coldfire/m547x/mcf548x-devices.c ++++ b/arch/m68k/coldfire/m547x/mcf548x-devices.c +@@ -54,7 +54,7 @@ static struct resource coldfire_sec_reso + }; + + static struct platform_device coldfire_sec_device = { +- .name = "fsl-sec1", ++ .name = "talitos", + .id = -1, + .num_resources = ARRAY_SIZE(coldfire_sec_resources), + .resource = coldfire_sec_resources, +--- a/arch/m68k/include/asm/cf_io.h ++++ b/arch/m68k/include/asm/cf_io.h +@@ -192,4 +192,8 @@ static inline void memcpy_toio(volatile + #define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) + #endif /* readb */ + ++/* access ports */ ++#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) ++#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) ++ + #endif /* _IO_H */ +--- a/crypto/testmgr.c ++++ b/crypto/testmgr.c +@@ -212,7 +212,11 @@ static int test_hash(struct crypto_ahash + tcrypt_complete, &tresult); + + j = 0; ++#if defined(CONFIG_CRYPTO_DEV_CF_TALITOS) ++ for (i = 1; i < tcount; i++) { ++#else + for (i = 0; i < tcount; i++) { ++#endif + if (template[i].np) + continue; + +@@ -276,7 +280,9 @@ static int test_hash(struct crypto_ahash + hexdump(result, crypto_ahash_digestsize(tfm)); + ret = -EINVAL; + goto out; +- } ++ } else ++ printk(KERN_INFO "alg: hash: Test %d succeed for %s\n", ++ j, algo); + } + + j = 0; +@@ -344,7 +350,9 @@ static int test_hash(struct crypto_ahash + hexdump(result, crypto_ahash_digestsize(tfm)); + ret = -EINVAL; + goto out; +- } ++ } else ++ printk(KERN_INFO "alg: hash: Chunking test %d " ++ "succeed for %s\n", j, algo); + } + } + +@@ -788,7 +796,6 @@ static int test_skcipher(struct crypto_a + else + e = "decryption"; + +- printk(KERN_INFO "%s testing %s %s\n", __func__, algo, e); + init_completion(&result.completion); + + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); +@@ -963,7 +970,10 @@ static int test_skcipher(struct crypto_a + "%u for %s\n", j, e, k, algo); + hexdump(q, template[i].tap[k]); + goto out; +- } ++ } else ++ printk(KERN_INFO "alg: skcipher: Chunk " ++ "test %d pass on %s for %s\n", ++ j, e, algo); + + q += template[i].tap[k]; + for (n = 0; offset_in_page(q + n) && q[n]; n++) +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -282,6 +282,19 @@ config CRYPTO_DEV_TALITOS + To compile this driver as a module, choose M here: the module + will be called talitos. + ++config CRYPTO_DEV_CF_TALITOS ++ tristate "Talitos Freescale Coldfire Security Engine (SEC)" ++ select CRYPTO_ALGAPI ++ select CRYPTO_AUTHENC ++ select HW_RANDOM ++ depends on (M547X || M548X) ++ help ++ Say 'Y' here to use the Freescale Coldfire Security Engine (SEC) ++ to offload cryptographic algorithm computation. ++ ++ The Freescale SEC is present on Coldfire MCF547x and MCF548x ++ processors. ++ + config CRYPTO_DEV_IXP4XX + tristate "Driver for IXP4xx crypto hardware acceleration" + depends on ARCH_IXP4XX +--- a/drivers/crypto/Makefile ++++ b/drivers/crypto/Makefile +@@ -6,6 +6,7 @@ n2_crypto-y := n2_core.o n2_asm.o + obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o + obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o + obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o ++obj-$(CONFIG_CRYPTO_DEV_CF_TALITOS) += cf_talitos.o + obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o + obj-$(CONFIG_CRYPTO_DEV_MCFCAU) += mcfcau.o + obj-$(CONFIG_CRYPTO_DEV_MCFCAU_DES) += mcfcau-des.o +--- /dev/null ++++ b/drivers/crypto/cf_talitos.c +@@ -0,0 +1,1727 @@ ++/* ++ * cf_talitos - Freescale Coldfire Integrated Security Engine ++ * (SEC) device driver ++ * ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Alison Wang <b18965@freescale.com> ++ * based on talitos.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/mod_devicetable.h> ++#include <linux/device.h> ++#include <linux/interrupt.h> ++#include <linux/crypto.h> ++#include <linux/hw_random.h> ++#include <linux/platform_device.h> ++#include <linux/dma-mapping.h> ++#include <linux/io.h> ++#include <linux/spinlock.h> ++#include <linux/rtnetlink.h> ++#include <linux/slab.h> ++ ++#include <crypto/algapi.h> ++#include <crypto/aes.h> ++#include <crypto/des.h> ++#include <crypto/sha.h> ++#include <crypto/md5.h> ++#include <crypto/aead.h> ++#include <crypto/authenc.h> ++#include <crypto/skcipher.h> ++#include <crypto/hash.h> ++#include <crypto/internal/hash.h> ++#include <crypto/scatterwalk.h> ++ ++#include <asm/m5485sim.h> ++#include "cf_talitos.h" ++ ++#define TALITOS_TIMEOUT 100000 ++#define TALITOS_MAX_DATA_LEN 65535 ++ ++#define DESC_TYPE(desc_hdr) (((desc_hdr) >> 4) & 0xf) ++#define PRIMARY_EU(desc_hdr) (((desc_hdr) >> 28) & 0xf) ++#define SECONDARY_EU(desc_hdr) (((desc_hdr) >> 16) & 0xf) ++ ++#define CF_TALITOS_DEBUG 0 ++#if CF_TALITOS_DEBUG ++#define dprintk(args...) printk(args) ++#else ++#define dprintk(...) ++#endif ++ ++/* descriptor pointer entry */ ++struct talitos_ptr { ++ u32 len; /* length */ ++ u32 ptr; /* address */ ++}; ++ ++static const struct talitos_ptr zero_entry = { ++ .len = 0, ++ .ptr = 0 ++}; ++ ++/* descriptor */ ++struct talitos_desc { ++ u32 hdr; /* header */ ++ struct talitos_ptr ptr[7]; /* ptr/len pair array */ ++ u32 next_hdr; ++}; ++ ++/** ++ * talitos_request - descriptor submission request ++ * @desc: descriptor pointer (kernel virtual) ++ * @dma_desc: descriptor's physical bus address ++ * @callback: whom to call when descriptor processing is done ++ * @context: caller context (optional) ++ */ ++struct talitos_request { ++ struct talitos_desc *desc; ++ dma_addr_t dma_desc; ++ void (*callback) (struct device *dev, struct talitos_desc *desc, ++ void *context, int error); ++ void *context; ++}; ++ ++/* per-channel fifo management */ ++struct talitos_channel { ++ /* request fifo */ ++ struct talitos_request *fifo; ++ ++ /* number of requests pending in channel h/w fifo */ ++ atomic_t submit_count ____cacheline_aligned; ++ ++ /* request submission (head) lock */ ++ spinlock_t head_lock ____cacheline_aligned; ++ /* index to next free descriptor request */ ++ int head; ++ ++ /* request release (tail) lock */ ++ spinlock_t tail_lock ____cacheline_aligned; ++ /* index to next in-progress/done descriptor request */ ++ int tail; ++}; ++ ++struct talitos_private { ++ struct device *dev; ++ struct platform_device *pdev; ++ void __iomem *reg; ++ int irq; ++ ++ /* SEC version geometry (from device tree node) */ ++ unsigned int num_channels; ++ unsigned int chfifo_len; ++ unsigned int exec_units; ++ unsigned int desc_types; ++ ++ /* SEC Compatibility info */ ++ unsigned long features; ++ ++ /* ++ * length of the request fifo ++ * fifo_len is chfifo_len rounded up to next power of 2 ++ * so we can use bitwise ops to wrap ++ */ ++ unsigned int fifo_len; ++ ++ struct talitos_channel *chan; ++ ++ /* next channel to be assigned next incoming descriptor */ ++ atomic_t last_chan ____cacheline_aligned; ++ ++ /* request callback tasklet */ ++ struct tasklet_struct done_task; ++ ++ /* list of registered algorithms */ ++ struct list_head alg_list; ++ ++ /* hwrng device */ ++ struct hwrng rng; ++}; ++ ++/* .features flag */ ++#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001 ++#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002 ++#define TALITOS_FTR_SHA224_HWINIT 0x00000004 ++ ++/* ++ * map virtual single (contiguous) pointer to h/w descriptor pointer ++ */ ++static void map_single_talitos_ptr(struct device *dev, ++ struct talitos_ptr *talitos_ptr, ++ unsigned short len, void *data, ++ unsigned char extent, ++ enum dma_data_direction dir) ++{ ++ dma_addr_t dma_addr = dma_map_single(dev, data, len, dir); ++ ++ talitos_ptr->len = len; ++ talitos_ptr->ptr = dma_addr; ++} ++ ++/* ++ * unmap bus single (contiguous) h/w descriptor pointer ++ */ ++static void unmap_single_talitos_ptr(struct device *dev, ++ struct talitos_ptr *talitos_ptr, ++ enum dma_data_direction dir) ++{ ++ dma_unmap_single(dev, talitos_ptr->ptr, talitos_ptr->len, dir); ++} ++ ++static int reset_channel(struct device *dev, int ch) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ unsigned int timeout = TALITOS_TIMEOUT; ++ ++ setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET); ++ ++ while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & ++ TALITOS_CCCR_RESET) && --timeout) ++ cpu_relax(); ++ ++ if (timeout == 0) { ++ dev_err(dev, "failed to reset channel %d\n", ch); ++ return -EIO; ++ } ++ ++ /* set 36-bit addressing, done writeback enable and done IRQ enable */ ++ setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_NE | ++ TALITOS_CCCR_NT | TALITOS_CCCR_CDWE | ++ TALITOS_CCCR_CDIE); ++ ++ return 0; ++} ++ ++static int reset_device(struct device *dev) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ unsigned int timeout = TALITOS_TIMEOUT; ++ ++ setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR); ++ ++ while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR) ++ && --timeout) ++ cpu_relax(); ++ ++ if (timeout == 0) { ++ dev_err(dev, "failed to reset device\n"); ++ return -EIO; ++ } ++ ++ setbits32(priv->reg + TALITOS_DEURCR, TALITOS_DEURCR_RESET); ++ setbits32(priv->reg + TALITOS_AFEURCR, TALITOS_AFEURCR_RESET); ++ setbits32(priv->reg + TALITOS_AESURCR, TALITOS_AESURCR_RESET); ++ setbits32(priv->reg + TALITOS_MDEURCR, TALITOS_MDEURCR_RESET); ++ setbits32(priv->reg + TALITOS_RNGRCR, TALITOS_RNGRCR_SR); ++ return 0; ++} ++ ++/* ++ * Reset and initialize the device ++ */ ++static int init_device(struct device *dev) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ int ch, err; ++ ++ /* ++ * Master reset ++ * errata documentation: warning: certain SEC interrupts ++ * are not fully cleared by writing the MCR:SWR bit, ++ * set bit twice to completely reset ++ */ ++ err = reset_device(dev); ++ if (err) ++ return err; ++ ++ err = reset_device(dev); ++ if (err) ++ return err; ++ ++ /* reset channels */ ++ for (ch = 0; ch < priv->num_channels; ch++) { ++ err = reset_channel(dev, ch); ++ if (err) ++ return err; ++ } ++ ++ /* enable channel done and error interrupts */ ++ out_be32(priv->reg + TALITOS_IMR, 0); ++ out_be32(priv->reg + TALITOS_IMR_LO, 0); ++ ++ out_be32(priv->reg + TALITOS_ICR, ++ TALITOS_ICR_CHERR | TALITOS_ICR_CHDONE); ++ out_be32(priv->reg + TALITOS_ICR_LO, ++ TALITOS_ICR_LO_CHERR | TALITOS_ICR_LO_CHDONE); ++ ++ return 0; ++} ++ ++/** ++ * talitos_submit - submits a descriptor to the device for processing ++ * @dev: the SEC device to be used ++ * @desc: the descriptor to be processed by the device ++ * @callback: whom to call when processing is complete ++ * @context: a handle for use by caller (optional) ++ * ++ * desc must contain valid dma-mapped (bus physical) address pointers. ++ * callback must check err and feedback in descriptor header ++ * for device processing status. ++ */ ++static int talitos_submit(struct device *dev, struct talitos_desc *desc, ++ void (*callback)(struct device *dev, ++ struct talitos_desc *desc, ++ void *context, int error), ++ void *context) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ struct talitos_request *request; ++ unsigned long flags, ch; ++ int head; ++ ++ /* ignore key parity check in triple DES */ ++ if (((desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_DEU) && ++ (desc->hdr & DESC_HDR_MODE0_DEU_3DES)) ++ setbits32(priv->reg + TALITOS_DEUIMR, TALITOS_DEUIMR_KPE_MASK); ++ ++ /* select done notification */ ++ desc->hdr |= DESC_HDR_DONE; ++ ++ /* emulate SEC's round-robin channel fifo polling scheme */ ++ ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1); ++ ++ spin_lock_irqsave(&priv->chan[ch].head_lock, flags); ++ ++ head = priv->chan[ch].head; ++ request = &priv->chan[ch].fifo[head]; ++ ++ /* map descriptor and save caller data */ ++ request->dma_desc = dma_map_single(dev, desc, sizeof(*desc), ++ DMA_BIDIRECTIONAL); ++ request->callback = callback; ++ request->context = context; ++ ++ /* increment fifo head */ ++ priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1); ++ ++ smp_wmb(); ++ request->desc = desc; ++ ++ /* GO! */ ++ wmb(); ++ out_be32(priv->reg + TALITOS_FF(ch), request->dma_desc); ++ ++ spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags); ++ ++ return -EINPROGRESS; ++} ++ ++/* ++ * process what was done, notify callback of error if not ++ */ ++static void flush_channel(struct device *dev, int ch, int error, int reset_ch) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ struct talitos_request *request, saved_req; ++ unsigned long flags; ++ int tail, status; ++ ++ spin_lock_irqsave(&priv->chan[ch].tail_lock, flags); ++ ++ tail = priv->chan[ch].tail; ++ while (priv->chan[ch].fifo[tail].desc) { ++ request = &priv->chan[ch].fifo[tail]; ++ ++ /* descriptors with their done bits set don't get the error */ ++ rmb(); ++ if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE) ++ status = 0; ++ else ++ if (!error) ++ break; ++ else ++ status = error; ++ ++ dma_unmap_single(dev, request->dma_desc, ++ sizeof(struct talitos_desc), ++ DMA_BIDIRECTIONAL); ++ ++ /* copy entries so we can call callback outside lock */ ++ saved_req.desc = request->desc; ++ saved_req.callback = request->callback; ++ saved_req.context = request->context; ++ ++ /* release request entry in fifo */ ++ smp_wmb(); ++ request->desc = NULL; ++ ++ /* increment fifo tail */ ++ priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1); ++ ++ spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags); ++ ++ atomic_dec(&priv->chan[ch].submit_count); ++ ++ saved_req.callback(dev, saved_req.desc, saved_req.context, ++ status); ++ /* channel may resume processing in single desc error case */ ++ if (error && !reset_ch && status == error) ++ return; ++ spin_lock_irqsave(&priv->chan[ch].tail_lock, flags); ++ tail = priv->chan[ch].tail; ++ } ++ ++ spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags); ++} ++ ++/* ++ * process completed requests for channels that have done status ++ */ ++static void talitos_done(unsigned long data) ++{ ++ struct device *dev = (struct device *)data; ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ int ch; ++ ++ for (ch = 0; ch < priv->num_channels; ch++) ++ flush_channel(dev, ch, 0, 0); ++ ++ /* At this point, all completed channels have been processed. ++ * Unmask done interrupts for channels completed later on. ++ */ ++ out_be32(priv->reg + TALITOS_IMR, 0); ++ out_be32(priv->reg + TALITOS_IMR_LO, 0); ++ ++ out_be32(priv->reg + TALITOS_ICR, ++ TALITOS_ICR_CHERR | TALITOS_ICR_CHDONE); ++ out_be32(priv->reg + TALITOS_ICR_LO, ++ TALITOS_ICR_LO_CHERR | TALITOS_ICR_LO_CHDONE); ++} ++ ++/* ++ * locate current (offending) descriptor ++ */ ++static struct talitos_desc *current_desc(struct device *dev, int ch) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ int tail = priv->chan[ch].tail; ++ dma_addr_t cur_desc; ++ ++ cur_desc = in_be32(priv->reg + TALITOS_CDPR(ch)); ++ ++ while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) { ++ tail = (tail + 1) & (priv->fifo_len - 1); ++ if (tail == priv->chan[ch].tail) { ++ dev_err(dev, "couldn't locate current descriptor\n"); ++ return NULL; ++ } ++ } ++ ++ return priv->chan[ch].fifo[tail].desc; ++} ++ ++/* ++ * user diagnostics; report root cause of error based on execution unit status ++ */ ++static void report_eu_error(struct device *dev, int ch, ++ struct talitos_desc *desc) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ int i; ++ ++ switch (desc->hdr & DESC_HDR_SEL0_MASK) { ++ case DESC_HDR_SEL0_AFEU: ++ dev_err(dev, "AFEUISR 0x%08x\n", ++ in_be32(priv->reg + TALITOS_AFEUISR)); ++ break; ++ case DESC_HDR_SEL0_DEU: ++ dev_err(dev, "DEUISR 0x%08x\n", ++ in_be32(priv->reg + TALITOS_DEUISR)); ++ break; ++ case DESC_HDR_SEL0_MDEU: ++ dev_err(dev, "MDEUISR 0x%08x\n", ++ in_be32(priv->reg + TALITOS_MDEUISR)); ++ break; ++ case DESC_HDR_SEL0_RNG: ++ dev_err(dev, "RNGISR 0x%08x\n", ++ in_be32(priv->reg + TALITOS_RNGISR)); ++ break; ++ case DESC_HDR_SEL0_AESU: ++ dev_err(dev, "AESUISR 0x%08x\n", ++ in_be32(priv->reg + TALITOS_AESUISR)); ++ break; ++ } ++ ++ switch (desc->hdr & DESC_HDR_SEL1_MASK) { ++ case DESC_HDR_SEL1_MDEU: ++ dev_err(dev, "MDEUISR 0x%08x\n", ++ in_be32(priv->reg + TALITOS_MDEUISR)); ++ break; ++ } ++ ++ for (i = 0; i < 8; i++) ++ dev_err(dev, "DESCBUF 0x%08x\n", ++ in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8 * i)); ++} ++ ++/* ++ * recover from error interrupts ++ */ ++static void talitos_error(unsigned long data, u32 isr, u32 isr_lo) ++{ ++ struct device *dev = (struct device *)data; ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ int ch, error, reset_ch = 0; ++ u32 v, v_lo; ++ ++ for (ch = 0; ch < priv->num_channels; ch++) { ++ /* skip channels without errors */ ++ if (!((isr >> 29) & (1 << (ch * 2)))) ++ continue; ++ ++ error = -EINVAL; ++ ++ v = in_be32(priv->reg + TALITOS_CCPSR(ch)); ++ v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch)); ++ ++ if (v_lo & TALITOS_CCPSR_LO_TEA) ++ dev_err(dev, "master data transfer error\n"); ++ if (v_lo & TALITOS_CCPSR_LO_PERR) ++ dev_err(dev, "fetch pointer not complete error\n"); ++ if (v_lo & TALITOS_CCPSR_LO_DERR) ++ dev_err(dev, "illegal descriptor header error\n"); ++ if (v_lo & TALITOS_CCPSR_LO_SERR) ++ dev_err(dev, "static assignment error\n"); ++ if (v_lo & TALITOS_CCPSR_LO_EUERR) ++ report_eu_error(dev, ch, current_desc(dev, ch)); ++ ++ flush_channel(dev, ch, error, reset_ch); ++ ++ if (reset_ch) ++ reset_channel(dev, ch); ++ } ++ ++ /* purge request queues */ ++ for (ch = 0; ch < priv->num_channels; ch++) ++ flush_channel(dev, ch, -EIO, 1); ++ ++ /* reset and reinitialize the device */ ++ init_device(dev); ++} ++ ++static irqreturn_t talitos_interrupt(int irq, void *data) ++{ ++ struct device *dev = data; ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ u32 isr, isr_lo; ++ ++ isr = in_be32(priv->reg + TALITOS_ISR); ++ isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); ++ /* Acknowledge interrupt */ ++ out_be32(priv->reg + TALITOS_ICR, isr); ++ out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); ++ ++ if (unlikely(isr & ~TALITOS_ISR_CHDONE)) { ++ talitos_error((unsigned long)data, isr, isr_lo); ++ } else if (likely(isr & TALITOS_ISR_CHDONE)) { ++ /* mask further done interrupts. */ ++ setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE); ++ /* done_task will unmask done interrupts at exit */ ++ tasklet_schedule(&priv->done_task); ++ } ++ ++ return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++ ++/* ++ * crypto alg ++ */ ++#define TALITOS_CRA_PRIORITY 3000 ++#define TALITOS_MAX_KEY_SIZE 64 ++#define TALITOS_MAX_IV_LENGTH 16 ++#define TALITOS_MAX_OUTPUTDATA_SIZE 64 ++#define TALITOS_MAX_INPUTDATA_SIZE 64 ++ ++#define ARC4_MIN_KEY_SIZE 4 ++#define ARC4_MAX_KEY_SIZE 16 ++#define ARC4_BLOCK_SIZE 64 ++#define MD5_BLOCK_SIZE 64 ++ ++struct talitos_ctx { ++ struct device *dev; ++ __be32 desc_hdr_template; ++ u8 key[TALITOS_MAX_KEY_SIZE]; ++ u8 iv[TALITOS_MAX_IV_LENGTH]; ++ unsigned int keylen; ++ unsigned int enckeylen; ++ unsigned int authkeylen; ++ unsigned int authsize; ++}; ++ ++#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE ++#define TALITOS_MDEU_MAX_CONTEXT_SIZE \ ++ TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 ++ ++struct talitos_ahash_req_ctx { ++ u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; ++ unsigned int hw_context_size; ++ u8 buf[HASH_MAX_BLOCK_SIZE]; ++ u8 bufnext[HASH_MAX_BLOCK_SIZE]; ++ unsigned int swinit; ++ unsigned int first; ++ unsigned int last; ++ unsigned int to_hash_later; ++ u64 nbuf; ++ struct scatterlist bufsl[2]; ++ struct scatterlist *psrc; ++}; ++ ++/* ++ * talitos_edesc - s/w-extended descriptor ++ * @src_nents: number of segments in input scatterlist ++ * @dst_nents: number of segments in output scatterlist ++ * @desc: h/w descriptor ++ * ++ * if decrypting (with authcheck), or either one of src_nents or dst_nents ++ * is greater than 1, an integrity check value is concatenated to the end ++ * of link_tbl data ++ */ ++struct talitos_edesc { ++ int src_nents; ++ int dst_nents; ++ int src_is_chained; ++ int dst_is_chained; ++ struct talitos_desc desc; ++ u8 src_buf[TALITOS_MAX_INPUTDATA_SIZE]; ++ u8 dst_buf[TALITOS_MAX_OUTPUTDATA_SIZE]; ++}; ++ ++static int talitos_map_sg(struct device *dev, struct scatterlist *sg, ++ unsigned int nents, enum dma_data_direction dir, ++ int chained) ++{ ++ if (unlikely(chained)) ++ while (sg) { ++ dma_map_sg(dev, sg, 1, dir); ++ sg = scatterwalk_sg_next(sg); ++ } ++ else ++ dma_map_sg(dev, sg, nents, dir); ++ return nents; ++} ++ ++static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg, ++ enum dma_data_direction dir) ++{ ++ while (sg) { ++ dma_unmap_sg(dev, sg, 1, dir); ++ sg = scatterwalk_sg_next(sg); ++ } ++} ++ ++static void talitos_sg_unmap(struct device *dev, ++ struct talitos_edesc *edesc, ++ struct scatterlist *src, ++ struct scatterlist *dst) ++{ ++ unsigned int src_nents = edesc->src_nents ? : 1; ++ unsigned int dst_nents = edesc->dst_nents ? : 1; ++ ++ if (src != dst) { ++ if (edesc->src_is_chained) ++ talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE); ++ else ++ dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE); ++ ++ if (dst) { ++ if (edesc->dst_is_chained) ++ talitos_unmap_sg_chain(dev, dst, ++ DMA_FROM_DEVICE); ++ else ++ dma_unmap_sg(dev, dst, dst_nents, ++ DMA_FROM_DEVICE); ++ } ++ } else ++ if (edesc->src_is_chained) ++ talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL); ++ else ++ dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL); ++} ++ ++/* ++ * derive number of elements in scatterlist ++ */ ++static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained) ++{ ++ struct scatterlist *sg = sg_list; ++ int sg_nents = 0; ++ ++ *chained = 0; ++ while (nbytes > 0) { ++ sg_nents++; ++ nbytes -= sg->length; ++ if (!sg_is_last(sg) && (sg + 1)->length == 0) ++ *chained = 1; ++ sg = scatterwalk_sg_next(sg); ++ } ++ ++ return sg_nents; ++} ++ ++/** ++ * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer ++ * @sgl: The SG list ++ * @nents: Number of SG entries ++ * @buf: Where to copy to ++ * @buflen: The number of bytes to copy ++ * @skip: The number of bytes to skip before copying. ++ * Note: skip + buflen should equal SG total size. ++ * ++ * Returns the number of copied bytes. ++ * ++ **/ ++static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents, ++ void *buf, size_t buflen, unsigned int skip) ++{ ++ unsigned int offset = 0; ++ unsigned int boffset = 0; ++ struct sg_mapping_iter miter; ++ unsigned long flags; ++ unsigned int sg_flags = SG_MITER_ATOMIC; ++ size_t total_buffer = buflen + skip; ++ ++ sg_flags |= SG_MITER_FROM_SG; ++ ++ sg_miter_start(&miter, sgl, nents, sg_flags); ++ ++ local_irq_save(flags); ++ ++ while (sg_miter_next(&miter) && offset < total_buffer) { ++ unsigned int len; ++ unsigned int ignore; ++ ++ if ((offset + miter.length) > skip) { ++ if (offset < skip) { ++ /* Copy part of this segment */ ++ ignore = skip - offset; ++ len = miter.length - ignore; ++ if (boffset + len > buflen) ++ len = buflen - boffset; ++ memcpy(buf + boffset, miter.addr + ignore, len); ++ } else { ++ /* Copy all of this segment (up to buflen) */ ++ len = miter.length; ++ if (boffset + len > buflen) ++ len = buflen - boffset; ++ memcpy(buf + boffset, miter.addr, len); ++ } ++ boffset += len; ++ } ++ offset += miter.length; ++ } ++ ++ sg_miter_stop(&miter); ++ ++ local_irq_restore(flags); ++ return boffset; ++} ++ ++/* ++ * allocate and map the extended descriptor ++ */ ++static struct talitos_edesc *talitos_edesc_alloc(struct device *dev, ++ struct scatterlist *src, ++ struct scatterlist *dst, ++ int hash_result, ++ unsigned int cryptlen, ++ unsigned int authsize, ++ int icv_stashing, ++ u32 cryptoflags) ++{ ++ struct talitos_edesc *edesc; ++ int src_nents, dst_nents, alloc_len; ++ int src_chained, dst_chained = 0; ++ gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : ++ GFP_ATOMIC; ++ ++ if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) { ++ dev_err(dev, "length exceeds h/w max limit\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ src_nents = sg_count(src, cryptlen + authsize, &src_chained); ++ src_nents = (src_nents == 1) ? 0 : src_nents; ++ ++ if (hash_result) { ++ dst_nents = 0; ++ } else { ++ if (dst == src) { ++ dst_nents = src_nents; ++ } else { ++ dst_nents = sg_count(dst, cryptlen + authsize, ++ &dst_chained); ++ dst_nents = (dst_nents == 1) ? 0 : dst_nents; ++ } ++ } ++ ++ /* ++ * allocate space for base edesc plus the link tables, ++ * allowing for two separate entries for ICV and generated ICV (+ 2), ++ * and the ICV data itself ++ */ ++ alloc_len = sizeof(struct talitos_edesc); ++ ++ edesc = kmalloc(alloc_len, GFP_KERNEL | flags); ++ if (!edesc) { ++ dev_err(dev, "could not allocate edescriptor\n"); ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ edesc->src_nents = src_nents; ++ edesc->dst_nents = dst_nents; ++ edesc->src_is_chained = src_chained; ++ edesc->dst_is_chained = dst_chained; ++ return edesc; ++} ++ ++static int ablkcipher_setkey(struct crypto_ablkcipher *cipher, ++ const u8 *key, unsigned int keylen) ++{ ++ struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher); ++ ++ if (keylen > TALITOS_MAX_KEY_SIZE) ++ goto badkey; ++ ++ if (keylen < alg->min_keysize || keylen > alg->max_keysize) ++ goto badkey; ++ ++ memcpy(&ctx->key, key, keylen); ++ ctx->keylen = keylen; ++ ++ return 0; ++ ++badkey: ++ crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); ++ return -EINVAL; ++} ++ ++static void common_nonsnoop_unmap(struct device *dev, ++ struct talitos_edesc *edesc, ++ struct ablkcipher_request *areq) ++{ ++ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); ++ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE); ++ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE); ++ ++ talitos_sg_unmap(dev, edesc, areq->src, areq->dst); ++} ++ ++static void ablkcipher_done(struct device *dev, ++ struct talitos_desc *desc, void *context, ++ int err) ++{ ++ struct ablkcipher_request *areq = context; ++ struct talitos_edesc *edesc; ++ ++ edesc = container_of(desc, struct talitos_edesc, desc); ++ ++ if (edesc->dst_nents != 0) ++ sg_copy_from_buffer(areq->dst, edesc->dst_nents, ++ edesc->dst_buf, areq->nbytes); ++ ++ common_nonsnoop_unmap(dev, edesc, areq); ++ ++ kfree(edesc); ++ ++ areq->base.complete(&areq->base, err); ++} ++ ++static int common_nonsnoop(struct talitos_edesc *edesc, ++ struct ablkcipher_request *areq, ++ u8 *giv, ++ void (*callback) (struct device *dev, ++ struct talitos_desc *desc, ++ void *context, int error)) ++{ ++ struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct device *dev = ctx->dev; ++ struct talitos_desc *desc = &edesc->desc; ++ unsigned int cryptlen = areq->nbytes; ++ unsigned int ivsize; ++ int sg_count, ret; ++ ++ desc->next_hdr = 0; ++ ++ /* first DWORD empty */ ++ desc->ptr[0] = zero_entry; ++ ++ /* cipher iv */ ++ ivsize = crypto_ablkcipher_ivsize(cipher); ++ map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0, ++ DMA_TO_DEVICE); ++ ++ /* AFEU using a key */ ++ if (((desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AFEU) && ++ ((desc->hdr & DESC_HDR_MODE0_MASK) == ++ DESC_HDR_MODE0_AFEU_USE_KEY)) ++ desc->ptr[1] = zero_entry; ++ ++ /* cipher key */ ++ map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen, ++ (char *)&ctx->key, 0, DMA_TO_DEVICE); ++ ++ /* AFEU using context */ ++ if (((desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AFEU) && ++ ((desc->hdr & DESC_HDR_MODE0_MASK) == ++ DESC_HDR_MODE0_AFEU_USE_CONTEXT)) ++ desc->ptr[2] = zero_entry; ++ ++ /* ++ * cipher in ++ */ ++ desc->ptr[3].len = cpu_to_be16(cryptlen); ++ ++ sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1, ++ (areq->src == areq->dst) ? DMA_BIDIRECTIONAL ++ : DMA_TO_DEVICE, ++ edesc->src_is_chained); ++ ++ if (sg_count == 1) ++ desc->ptr[3].ptr = sg_dma_address(areq->src); ++ else { ++ sg_copy_to_buffer(areq->src, sg_count, edesc->src_buf, ++ desc->ptr[3].len); ++ desc->ptr[3].ptr = (u32)edesc->src_buf; ++ } ++ ++ /* cipher out */ ++ desc->ptr[4].len = cpu_to_be16(cryptlen); ++ ++ if (areq->src != areq->dst) ++ sg_count = talitos_map_sg(dev, areq->dst, ++ edesc->dst_nents ? : 1, ++ DMA_FROM_DEVICE, ++ edesc->dst_is_chained); ++ ++ if (sg_count == 1) ++ desc->ptr[4].ptr = sg_dma_address(areq->dst); ++ else ++ desc->ptr[4].ptr = (u32)edesc->dst_buf; ++ ++ /* iv out */ ++ map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0, ++ DMA_FROM_DEVICE); ++ ++ /* last DWORD empty */ ++ desc->ptr[6] = zero_entry; ++ ++ ret = talitos_submit(dev, desc, callback, areq); ++ if (ret != -EINPROGRESS) { ++ common_nonsnoop_unmap(dev, edesc, areq); ++ kfree(edesc); ++ } ++ return ret; ++} ++ ++static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request * ++ areq) ++{ ++ struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ ++ return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0, ++ areq->nbytes, 0, 0, areq->base.flags); ++} ++ ++static int ablkcipher_encrypt(struct ablkcipher_request *areq) ++{ ++ struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct talitos_edesc *edesc; ++ ++ /* allocate extended descriptor */ ++ edesc = ablkcipher_edesc_alloc(areq); ++ if (IS_ERR(edesc)) ++ return PTR_ERR(edesc); ++ ++ /* set encrypt except AFEU */ ++ if ((ctx->desc_hdr_template & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AFEU) ++ edesc->desc.hdr = ctx->desc_hdr_template; ++ else ++ edesc->desc.hdr = ctx->desc_hdr_template | ++ DESC_HDR_MODE0_ENCRYP; ++ ++ return common_nonsnoop(edesc, areq, NULL, ablkcipher_done); ++} ++ ++static int ablkcipher_decrypt(struct ablkcipher_request *areq) ++{ ++ struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct talitos_edesc *edesc; ++ ++ /* allocate extended descriptor */ ++ edesc = ablkcipher_edesc_alloc(areq); ++ if (IS_ERR(edesc)) ++ return PTR_ERR(edesc); ++ ++ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; ++ ++ return common_nonsnoop(edesc, areq, NULL, ablkcipher_done); ++} ++ ++static void common_nonsnoop_hash_unmap(struct device *dev, ++ struct talitos_edesc *edesc, ++ struct ahash_request *areq) ++{ ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); ++ ++ /* When using hashctx-in, must unmap it. */ ++ if (edesc->desc.ptr[1].len) ++ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], ++ DMA_TO_DEVICE); ++ ++ if (edesc->desc.ptr[2].len) ++ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], ++ DMA_TO_DEVICE); ++ ++ talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL); ++} ++ ++static void ahash_done(struct device *dev, ++ struct talitos_desc *desc, void *context, ++ int err) ++{ ++ struct ahash_request *areq = context; ++ struct talitos_edesc *edesc = ++ container_of(desc, struct talitos_edesc, desc); ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ if (!req_ctx->last && req_ctx->to_hash_later) { ++ /* Position any partial block for next update/final/finup */ ++ memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later); ++ req_ctx->nbuf = req_ctx->to_hash_later; ++ } ++ common_nonsnoop_hash_unmap(dev, edesc, areq); ++ ++ kfree(edesc); ++ ++ areq->base.complete(&areq->base, err); ++} ++ ++static int common_nonsnoop_hash(struct talitos_edesc *edesc, ++ struct ahash_request *areq, unsigned int length, ++ void (*callback) (struct device *dev, ++ struct talitos_desc *desc, ++ void *context, int error)) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm); ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ struct device *dev = ctx->dev; ++ struct talitos_desc *desc = &edesc->desc; ++ int sg_count, ret; ++ ++ desc->next_hdr = 0; ++ ++ /* first DWORD empty */ ++ desc->ptr[0] = zero_entry; ++ ++ /* hash context in */ ++ if (!req_ctx->first || req_ctx->swinit) { ++ map_single_talitos_ptr(dev, &desc->ptr[1], ++ req_ctx->hw_context_size, ++ (char *)req_ctx->hw_context, 0, ++ DMA_TO_DEVICE); ++ req_ctx->swinit = 0; ++ } else { ++ desc->ptr[1] = zero_entry; ++ /* Indicate next op is not the first. */ ++ req_ctx->first = 0; ++ } ++ ++ /* HMAC key */ ++ if (ctx->keylen) ++ map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen, ++ (char *)&ctx->key, 0, DMA_TO_DEVICE); ++ else ++ desc->ptr[2] = zero_entry; ++ ++ /* ++ * data in ++ */ ++ desc->ptr[3].len = length; ++ sg_count = talitos_map_sg(dev, req_ctx->psrc, ++ edesc->src_nents ? : 1, ++ DMA_TO_DEVICE, ++ edesc->src_is_chained); ++ ++ if (sg_count == 1) ++ desc->ptr[3].ptr = sg_dma_address(req_ctx->psrc); ++ else { ++ sg_copy_to_buffer(req_ctx->psrc, sg_count, edesc->src_buf, ++ desc->ptr[3].len); ++ desc->ptr[3].ptr = (u32)edesc->src_buf; ++ } ++ ++ /* fifth DWORD empty */ ++ desc->ptr[4] = zero_entry; ++ ++ /* hash/HMAC out -or- hash context out */ ++ if (req_ctx->last) ++ map_single_talitos_ptr(dev, &desc->ptr[5], ++ crypto_ahash_digestsize(tfm), ++ areq->result, 0, DMA_FROM_DEVICE); ++ else ++ map_single_talitos_ptr(dev, &desc->ptr[5], ++ req_ctx->hw_context_size, ++ req_ctx->hw_context, 0, DMA_FROM_DEVICE); ++ ++ /* last DWORD empty */ ++ desc->ptr[6] = zero_entry; ++ ++ ret = talitos_submit(dev, desc, callback, areq); ++ if (ret != -EINPROGRESS) { ++ common_nonsnoop_hash_unmap(dev, edesc, areq); ++ kfree(edesc); ++ } ++ return ret; ++} ++ ++static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq, ++ unsigned int nbytes) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm); ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1, ++ nbytes, 0, 0, areq->base.flags); ++} ++ ++static int ahash_init(struct ahash_request *areq) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ /* Initialize the context */ ++ req_ctx->nbuf = 0; ++ req_ctx->first = 1; /* first indicates h/w must init its context */ ++ req_ctx->swinit = 0; /* assume h/w init of context */ ++ req_ctx->hw_context_size = ++ (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE) ++ ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 ++ : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; ++ ++ return 0; ++} ++ ++/* ++ * on h/w without explicit sha224 support, we initialize h/w context ++ * manually with sha224 constants, and tell it to run sha256. ++ */ ++static int ahash_init_sha224_swinit(struct ahash_request *areq) ++{ ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ ahash_init(areq); ++ req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/ ++ ++ req_ctx->hw_context[0] = SHA224_H0; ++ req_ctx->hw_context[1] = SHA224_H1; ++ req_ctx->hw_context[2] = SHA224_H2; ++ req_ctx->hw_context[3] = SHA224_H3; ++ req_ctx->hw_context[4] = SHA224_H4; ++ req_ctx->hw_context[5] = SHA224_H5; ++ req_ctx->hw_context[6] = SHA224_H6; ++ req_ctx->hw_context[7] = SHA224_H7; ++ ++ /* init 64-bit count */ ++ req_ctx->hw_context[8] = 0; ++ req_ctx->hw_context[9] = 0; ++ ++ return 0; ++} ++ ++static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm); ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ struct talitos_edesc *edesc; ++ unsigned int blocksize = ++ crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); ++ unsigned int nbytes_to_hash; ++ unsigned int to_hash_later; ++ unsigned int nsg; ++ int chained; ++ ++ if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) { ++ /* Buffer up to one whole block */ ++ sg_copy_to_buffer(areq->src, ++ sg_count(areq->src, nbytes, &chained), ++ req_ctx->buf + req_ctx->nbuf, nbytes); ++ req_ctx->nbuf += nbytes; ++ return 0; ++ } ++ ++ /* At least (blocksize + 1) bytes are available to hash */ ++ nbytes_to_hash = nbytes + req_ctx->nbuf; ++ to_hash_later = nbytes_to_hash & (blocksize - 1); ++ ++ if (req_ctx->last) ++ to_hash_later = 0; ++ else if (to_hash_later) ++ /* There is a partial block. Hash the full block(s) now */ ++ nbytes_to_hash -= to_hash_later; ++ else { ++ /* Keep one block buffered */ ++ nbytes_to_hash -= blocksize; ++ to_hash_later = blocksize; ++ } ++ ++ /* Chain in any previously buffered data */ ++ if (req_ctx->nbuf) { ++ nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1; ++ sg_init_table(req_ctx->bufsl, nsg); ++ sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf); ++ if (nsg > 1) ++ scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src); ++ req_ctx->psrc = req_ctx->bufsl; ++ } else ++ req_ctx->psrc = areq->src; ++ ++ if (to_hash_later) { ++ int nents = sg_count(areq->src, nbytes, &chained); ++ sg_copy_end_to_buffer(areq->src, nents, ++ req_ctx->bufnext, ++ to_hash_later, ++ nbytes - to_hash_later); ++ } ++ req_ctx->to_hash_later = to_hash_later; ++ ++ /* Allocate extended descriptor */ ++ edesc = ahash_edesc_alloc(areq, nbytes_to_hash); ++ if (IS_ERR(edesc)) ++ return PTR_ERR(edesc); ++ ++ edesc->desc.hdr = ctx->desc_hdr_template; ++ ++ /* On last one, request SEC to pad; otherwise continue */ ++ if (req_ctx->last) ++ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD; ++ else ++ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT; ++ ++ /* request SEC to INIT hash. */ ++ if (req_ctx->first && !req_ctx->swinit) ++ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT; ++ ++ /* When the tfm context has a keylen, it's an HMAC. ++ * A first or last (ie. not middle) descriptor must request HMAC. ++ */ ++ if (ctx->keylen && (req_ctx->first || req_ctx->last)) ++ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC; ++ ++ return common_nonsnoop_hash(edesc, areq, nbytes_to_hash, ++ ahash_done); ++} ++ ++static int ahash_update(struct ahash_request *areq) ++{ ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ req_ctx->last = 0; ++ ++ return ahash_process_req(areq, areq->nbytes); ++} ++ ++static int ahash_final(struct ahash_request *areq) ++{ ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ req_ctx->last = 1; ++ ++ return ahash_process_req(areq, 0); ++} ++ ++static int ahash_finup(struct ahash_request *areq) ++{ ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ ++ req_ctx->last = 1; ++ ++ return ahash_process_req(areq, areq->nbytes); ++} ++ ++static int ahash_digest(struct ahash_request *areq) ++{ ++ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq); ++ ++ ahash->init(areq); ++ req_ctx->last = 1; ++ ++ return ahash_process_req(areq, areq->nbytes); ++} ++ ++struct talitos_alg_template { ++ u32 type; ++ union { ++ struct crypto_alg crypto; ++ struct ahash_alg hash; ++ } alg; ++ __be32 desc_hdr_template; ++}; ++ ++static struct talitos_alg_template driver_algs[] = { ++ /* ABLKCIPHER algorithms. */ ++ { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, ++ .alg.crypto = { ++ .cra_name = "ecb(arc4)", ++ .cra_driver_name = "ecb-arc4-talitos", ++ .cra_blocksize = ARC4_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | ++ CRYPTO_ALG_ASYNC, ++ .cra_type = &crypto_ablkcipher_type, ++ .cra_ablkcipher = { ++ .setkey = ablkcipher_setkey, ++ .encrypt = ablkcipher_encrypt, ++ .decrypt = ablkcipher_decrypt, ++ .geniv = "eseqiv", ++ .min_keysize = ARC4_MIN_KEY_SIZE, ++ .max_keysize = ARC4_MAX_KEY_SIZE, ++ .ivsize = ARC4_BLOCK_SIZE, ++ } ++ }, ++ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_AFEU | ++ DESC_HDR_SEL0_AFEU | ++ DESC_HDR_MODE0_AFEU_USE_KEY, ++ }, ++ { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, ++ .alg.crypto = { ++ .cra_name = "cbc(aes)", ++ .cra_driver_name = "cbc-aes-talitos", ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | ++ CRYPTO_ALG_ASYNC, ++ .cra_type = &crypto_ablkcipher_type, ++ .cra_ablkcipher = { ++ .setkey = ablkcipher_setkey, ++ .encrypt = ablkcipher_encrypt, ++ .decrypt = ablkcipher_decrypt, ++ .geniv = "eseqiv", ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ }, ++ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | ++ DESC_HDR_SEL0_AESU | ++ DESC_HDR_MODE0_AESU_CBC, ++ }, ++ { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, ++ .alg.crypto = { ++ .cra_name = "cbc(des)", ++ .cra_driver_name = "cbc-des-talitos", ++ .cra_blocksize = DES_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | ++ CRYPTO_ALG_ASYNC, ++ .cra_type = &crypto_ablkcipher_type, ++ .cra_ablkcipher = { ++ .setkey = ablkcipher_setkey, ++ .encrypt = ablkcipher_encrypt, ++ .decrypt = ablkcipher_decrypt, ++ .geniv = "eseqiv", ++ .min_keysize = DES_KEY_SIZE, ++ .max_keysize = DES_KEY_SIZE, ++ .ivsize = DES_BLOCK_SIZE, ++ } ++ }, ++ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | ++ DESC_HDR_SEL0_DEU | ++ DESC_HDR_MODE0_DEU_CBC, ++ }, ++ { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, ++ .alg.crypto = { ++ .cra_name = "cbc(des3_ede)", ++ .cra_driver_name = "cbc-3des-talitos", ++ .cra_blocksize = DES3_EDE_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | ++ CRYPTO_ALG_ASYNC, ++ .cra_type = &crypto_ablkcipher_type, ++ .cra_ablkcipher = { ++ .setkey = ablkcipher_setkey, ++ .encrypt = ablkcipher_encrypt, ++ .decrypt = ablkcipher_decrypt, ++ .geniv = "eseqiv", ++ .min_keysize = DES3_EDE_KEY_SIZE, ++ .max_keysize = DES3_EDE_KEY_SIZE, ++ .ivsize = DES3_EDE_BLOCK_SIZE, ++ } ++ }, ++ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | ++ DESC_HDR_SEL0_DEU | ++ DESC_HDR_MODE0_DEU_CBC | ++ DESC_HDR_MODE0_DEU_3DES, ++ }, ++ /* AHASH algorithms. */ ++ { .type = CRYPTO_ALG_TYPE_AHASH, ++ .alg.hash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .halg.digestsize = MD5_DIGEST_SIZE, ++ .halg.base = { ++ .cra_name = "md5", ++ .cra_driver_name = "md5-talitos", ++ .cra_blocksize = MD5_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_ASYNC, ++ .cra_type = &crypto_ahash_type ++ } ++ }, ++ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | ++ DESC_HDR_SEL0_MDEU | ++ DESC_HDR_MODE0_MDEU_MD5, ++ }, ++ { .type = CRYPTO_ALG_TYPE_AHASH, ++ .alg.hash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .halg.digestsize = SHA1_DIGEST_SIZE, ++ .halg.base = { ++ .cra_name = "sha1", ++ .cra_driver_name = "sha1-talitos", ++ .cra_blocksize = SHA1_BLOCK_SIZE, ++ .cra_flags = CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_ASYNC, ++ .cra_type = &crypto_ahash_type ++ } ++ }, ++ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | ++ DESC_HDR_SEL0_MDEU | ++ DESC_HDR_MODE0_MDEU_SHA1, ++ }, ++}; ++ ++struct talitos_crypto_alg { ++ struct list_head entry; ++ struct device *dev; ++ struct talitos_alg_template algt; ++}; ++ ++static int talitos_cra_init(struct crypto_tfm *tfm) ++{ ++ struct crypto_alg *alg = tfm->__crt_alg; ++ struct talitos_crypto_alg *talitos_alg; ++ struct talitos_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH) ++ talitos_alg = container_of(__crypto_ahash_alg(alg), ++ struct talitos_crypto_alg, ++ algt.alg.hash); ++ else ++ talitos_alg = container_of(alg, struct talitos_crypto_alg, ++ algt.alg.crypto); ++ ++ /* update context with ptr to dev */ ++ ctx->dev = talitos_alg->dev; ++ ++ /* copy descriptor header template value */ ++ ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template; ++ ++ return 0; ++} ++ ++static int talitos_cra_init_ahash(struct crypto_tfm *tfm) ++{ ++ struct talitos_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ talitos_cra_init(tfm); ++ ++ ctx->keylen = 0; ++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), ++ sizeof(struct talitos_ahash_req_ctx)); ++ ++ return 0; ++} ++ ++/* ++ * given the alg's descriptor header template, determine whether descriptor ++ * type and primary/secondary execution units required match the hw ++ * capabilities description provided in the device tree node. ++ */ ++static int hw_supports(struct device *dev, __be32 desc_hdr_template) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = (DESC_TYPE(desc_hdr_template) & priv->desc_types) && ++ (PRIMARY_EU(desc_hdr_template) & priv->exec_units); ++ ++ if (SECONDARY_EU(desc_hdr_template)) ++ ret = ret && (SECONDARY_EU(desc_hdr_template) ++ & priv->exec_units); ++ ++ return ret; ++} ++ ++static int talitos_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ struct talitos_crypto_alg *t_alg, *n; ++ int i; ++ ++ list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) { ++ switch (t_alg->algt.type) { ++ case CRYPTO_ALG_TYPE_ABLKCIPHER: ++ case CRYPTO_ALG_TYPE_AEAD: ++ crypto_unregister_alg(&t_alg->algt.alg.crypto); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ crypto_unregister_ahash(&t_alg->algt.alg.hash); ++ break; ++ } ++ list_del(&t_alg->entry); ++ kfree(t_alg); ++ } ++ ++ for (i = 0; i < priv->num_channels; i++) ++ kfree(priv->chan[i].fifo); ++ ++ kfree(priv->chan); ++ ++ if (priv->irq != 0) ++ free_irq(priv->irq, dev); ++ ++ tasklet_kill(&priv->done_task); ++ ++ iounmap(priv->reg); ++ ++ dev_set_drvdata(dev, NULL); ++ ++ kfree(priv); ++ ++ return 0; ++} ++ ++static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev, ++ struct talitos_alg_template ++ *template) ++{ ++ struct talitos_private *priv = dev_get_drvdata(dev); ++ struct talitos_crypto_alg *t_alg; ++ struct crypto_alg *alg; ++ ++ t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL); ++ if (!t_alg) ++ return ERR_PTR(-ENOMEM); ++ ++ t_alg->algt = *template; ++ ++ switch (t_alg->algt.type) { ++ case CRYPTO_ALG_TYPE_ABLKCIPHER: ++ alg = &t_alg->algt.alg.crypto; ++ alg->cra_init = talitos_cra_init; ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ alg = &t_alg->algt.alg.hash.halg.base; ++ alg->cra_init = talitos_cra_init_ahash; ++ if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && ++ !strcmp(alg->cra_name, "sha224")) { ++ t_alg->algt.alg.hash.init = ahash_init_sha224_swinit; ++ t_alg->algt.desc_hdr_template = ++ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | ++ DESC_HDR_SEL0_MDEU | ++ DESC_HDR_MODE0_MDEU_SHA256; ++ } ++ break; ++ default: ++ dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ alg->cra_module = THIS_MODULE; ++ alg->cra_priority = TALITOS_CRA_PRIORITY; ++ alg->cra_alignmask = 0; ++ alg->cra_ctxsize = sizeof(struct talitos_ctx); ++ ++ t_alg->dev = dev; ++ ++ return t_alg; ++} ++ ++static int __devinit talitos_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct talitos_private *priv; ++ int prop; ++ struct resource *r; ++ int i, err; ++ ++ priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ dev_set_drvdata(dev, priv); ++ ++ priv->pdev = pdev; ++ ++ tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev); ++ ++ INIT_LIST_HEAD(&priv->alg_list); ++ ++ priv->irq = 64 + ISC_SEC; ++ /* get the irq line */ ++ err = request_irq(priv->irq, talitos_interrupt, IRQF_DISABLED, ++ dev_driver_string(dev), dev); ++ if (err) { ++ dev_err(dev, "failed to request irq %d\n", priv->irq); ++ goto err_out; ++ } else ++ MCF_ICR(ISC_SEC) = ILP_SEC; ++ ++ ++ /* get a pointer to the register memory */ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ priv->reg = ioremap(r->start, (r->end - r->start)); ++ if (!priv->reg) ++ dev_err(dev, "failed to ioremap\n"); ++ ++ /* get SEC version capabilities from device tree */ ++ prop = in_be32(priv->reg + TALITOS_ID); ++ if (prop & TALITOS_ID_SEC_1_1) { ++ priv->num_channels = TALITOS_NCHANNELS_SEC_1_1; ++ priv->chfifo_len = TALITOS_CHFIFOLEN_SEC_1_1; ++ priv->exec_units = TALITOS_HAS_EUS_SEC_1_1; ++ priv->desc_types = TALITOS_HAS_DESCTYPES_SEC_1_1; ++ } else { ++ dev_err(dev, "failed to id device\n"); ++ goto err_out; ++ } ++ ++ priv->chan = kzalloc(sizeof(struct talitos_channel) * ++ priv->num_channels, GFP_KERNEL); ++ if (!priv->chan) { ++ dev_err(dev, "failed to allocate channel management space\n"); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ for (i = 0; i < priv->num_channels; i++) { ++ spin_lock_init(&priv->chan[i].head_lock); ++ spin_lock_init(&priv->chan[i].tail_lock); ++ } ++ ++ priv->fifo_len = roundup_pow_of_two(priv->chfifo_len); ++ ++ for (i = 0; i < priv->num_channels; i++) { ++ priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) * ++ priv->fifo_len, GFP_KERNEL); ++ if (!priv->chan[i].fifo) { ++ dev_err(dev, "failed to allocate request fifo %d\n", i); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ } ++ ++ for (i = 0; i < priv->num_channels; i++) ++ atomic_set(&priv->chan[i].submit_count, ++ -(priv->chfifo_len - 1)); ++ ++ dma_set_mask(dev, DMA_BIT_MASK(36)); ++ ++ /* reset and initialize the h/w */ ++ err = init_device(dev); ++ if (err) { ++ dev_err(dev, "failed to initialize device\n"); ++ goto err_out; ++ } ++ ++ /* register crypto algorithms the device supports */ ++ for (i = 0; i < ARRAY_SIZE(driver_algs); i++) { ++ if (hw_supports(dev, driver_algs[i].desc_hdr_template)) { ++ struct talitos_crypto_alg *t_alg; ++ char *name = NULL; ++ ++ t_alg = talitos_alg_alloc(dev, &driver_algs[i]); ++ if (IS_ERR(t_alg)) { ++ err = PTR_ERR(t_alg); ++ goto err_out; ++ } ++ ++ switch (t_alg->algt.type) { ++ case CRYPTO_ALG_TYPE_ABLKCIPHER: ++ case CRYPTO_ALG_TYPE_AEAD: ++ err = crypto_register_alg( ++ &t_alg->algt.alg.crypto); ++ name = t_alg->algt.alg.crypto.cra_driver_name; ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ err = crypto_register_ahash( ++ &t_alg->algt.alg.hash); ++ name = ++ t_alg->algt.alg.hash.halg.base.cra_driver_name; ++ break; ++ } ++ if (err) { ++ dev_err(dev, "%s alg registration failed\n", ++ name); ++ kfree(t_alg); ++ } else { ++ list_add_tail(&t_alg->entry, &priv->alg_list); ++ dev_info(dev, "%s\n", name); ++ } ++ } ++ } ++ ++ return 0; ++ ++err_out: ++ talitos_remove(pdev); ++ ++ return err; ++} ++ ++static struct platform_driver talitos_driver = { ++ .driver = { ++ .name = "talitos", ++ .owner = THIS_MODULE, ++ }, ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++}; ++ ++static int __init talitos_init(void) ++{ ++ return platform_driver_register(&talitos_driver); ++} ++module_init(talitos_init); ++ ++static void __exit talitos_exit(void) ++{ ++ platform_driver_unregister(&talitos_driver); ++} ++module_exit(talitos_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>"); ++MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver"); +--- /dev/null ++++ b/drivers/crypto/cf_talitos.h +@@ -0,0 +1,229 @@ ++/* ++ * Freescale Coldfire SEC (talitos) device dependent data structures ++ * ++ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++/* device ID register values */ ++#define TALITOS_ID_SEC_1_1 (0x09000000) /* MCF547x and MCF548x */ ++ ++/* ++ * following num_channels, channel-fifo-depth, exec-unit-mask, and ++ * descriptor-types-mask are for forward-compatibility with openfirmware ++ * flat device trees ++ */ ++ ++/* ++ * num_channels : the number of channels available in each SEC version. ++ */ ++ ++/* n.b. this driver requires these values be a power of 2 */ ++#define TALITOS_NCHANNELS_SEC_1_1 2 ++ ++/* ++ * channel-fifo-depth : The number of descriptor ++ * pointers a channel fetch fifo can hold. ++ */ ++#define TALITOS_CHFIFOLEN_SEC_1_1 1 ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_EUS_SEC_1_1 0x7 ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_DESCTYPES_SEC_1_1 0xf ++ ++/* ++ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register ++ */ ++/* global register offset addresses */ ++/* EU Assaginment controller register is useless*/ ++#define TALITOS_EUACR 0x1000 ++#define TALITOS_EUACR_LO 0x1004 ++ ++#define TALITOS_IMR 0x1008 /* interrupt mask register */ ++#define TALITOS_IMR_ALL 0xf8000000 /* enable all interrupts mask */ ++#define TALITOS_IMR_ERR 0xa8000000 /* mask error interrupts */ ++#define TALITOS_IMR_DONE 0x50000000 /* mask done interrupts */ ++#define TALITOS_IMR_LO 0x100C /* interrupt mask register */ ++/* mask all channel interrupts mask */ ++#define TALITOS_IMR_LO_ALL 0x03333340 ++#define TALITOS_IMR_LO_ERR 0x02222240 /* mask error interrupts */ ++#define TALITOS_IMR_LO_DONE 0x01111100 /* mask done interrupts */ ++ ++#define TALITOS_ISR 0x1010 /* interrupt status register */ ++#define TALITOS_ISR_CHERR 0xa8000000 /* errors mask */ ++#define TALITOS_ISR_CHDONE 0x50000000 /* channel(s) done mask */ ++#define TALITOS_ISR_LO 0x1014 /* interrupt status register */ ++ ++#define TALITOS_ICR 0x1018 /* interrupt clear register */ ++#define TALITOS_ICR_CHERR 0xa8000000 /* errors enable */ ++#define TALITOS_ICR_CHDONE 0x50000000 /* channel(s) done enable */ ++#define TALITOS_ICR_LO 0x101C /* interrupt clear register */ ++#define TALITOS_ICR_LO_CHERR 0x02222240 /* errors enable */ ++#define TALITOS_ICR_LO_CHDONE 0x01111100 /* channel(s) done enable */ ++ ++#define TALITOS_ID 0x1020 ++ ++/* EU Assaginment status register is useless*/ ++#define TALITOS_EUASR 0x1028 ++#define TALITOS_EUASR_LO 0x102C ++ ++#define TALITOS_MCR 0x1030 /* master control register */ ++#define TALITOS_MCR_SWR 0x01000000 ++ ++#define TALITOS_MEAR 0x1038 ++ ++/* channel register address stride */ ++#define TALITOS_CH_STRIDE 0x1000 ++ ++/* channel register offset addresses and bits */ ++#define TALITOS_CCCR(ch) (ch * TALITOS_CH_STRIDE + 0x200c) ++#define TALITOS_CCCR_RESET 0x1 /* Channel Reset bit */ ++#define TALITOS_CCCR_CDWE 0x10 /* Channel done writeback enable bit */ ++#define TALITOS_CCCR_NE 0x8 /* Fetch Next Descriptor Enable bit */ ++#define TALITOS_CCCR_NT 0x4 /* Notification type bit */ ++#define TALITOS_CCCR_CDIE 0x2 /* Channel Done Interrupt Enable bit */ ++ ++/* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CCPSR(ch) (ch * TALITOS_CH_STRIDE + 0x2010) ++#define TALITOS_CCPSR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x2014) ++#define TALITOS_CCPSR_LO_TEA 0x2000 /* Transfer error acknowledge */ ++#define TALITOS_CCPSR_LO_PERR 0x1000 /* Pointer not complete error */ ++#define TALITOS_CCPSR_LO_DERR 0x400 /* Descriptor error */ ++#define TALITOS_CCPSR_LO_SERR 0x200 /* Static assignment error */ ++#define TALITOS_CCPSR_LO_EUERR 0x100 /* EU error */ ++ ++/* channel fetch fifo register */ ++#define TALITOS_FF(ch) (ch * TALITOS_CH_STRIDE + 0x204c) ++ ++/* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CDPR(ch) (ch * TALITOS_CH_STRIDE + 0x2044) ++ ++/* Descriptor Buffer (debug) 0x2080-0x20BF*/ ++#define TALITOS_DESCBUF(ch) (ch * TALITOS_CH_STRIDE + 0x2080) ++ ++/* execution unit register offset addresses and bits */ ++#define TALITOS_DEURCR 0xa018 /* DEU reset control register */ ++#define TALITOS_DEURCR_RESET 0x01000000 /* DEU reset bit */ ++#define TALITOS_DEUSR 0xa028 /* DEU status register */ ++#define TALITOS_DEUSR_RESET 0x01000000 /* DEU Reset status bit */ ++#define TALITOS_DEUISR 0xa030 /* DEU interrupt status register */ ++#define TALITOS_DEUIMR 0xa038 /* DEU interrupt mask register */ ++#define TALITOS_DEUIMR_MASK 0xf63f0000 /* DEU interrupt control mask*/ ++#define TALITOS_DEUIMR_KPE_MASK 0x00200000 /* DEU interrupt KPE mask*/ ++ ++#define TALITOS_AESURCR 0x12018 /* AESU reset control register */ ++#define TALITOS_AESURCR_RESET 0x01000000 /* AESU reset bit */ ++#define TALITOS_AESUSR 0x12028 /* AESU status register */ ++#define TALITOS_AESUSR_RESET 0x01000000 /* AESU Reset status bit */ ++#define TALITOS_AESUISR 0x12030 /* AESU interrupt status register */ ++#define TALITOS_AESUIMR 0x12038 /* AESU interrupt mask register */ ++#define TALITOS_AESUIMR_MASK 0xf61f0000 /* AESU interrupt control mask*/ ++ ++#define TALITOS_MDEURCR 0xc018 /* MDEU reset control register */ ++#define TALITOS_MDEURCR_RESET 0x01000000 /* MDEU reset bit */ ++#define TALITOS_MDEUSR 0xc028 /* MDEU status register */ ++#define TALITOS_MDEUSR_RESET 0x01000000 /* MDEU Reset status bit */ ++#define TALITOS_MDEUISR 0xc030 /* MDEU interrupt status register */ ++#define TALITOS_MDEUIMR 0xc038 /* MDEU interrupt mask register */ ++#define TALITOS_MDEUIMR_MASK 0xc41f0000 /* MDEU interrupt control mask*/ ++ ++#define TALITOS_AFEURCR 0x8018 /* AFEU reset control register */ ++#define TALITOS_AFEURCR_RESET 0x01000000 /* AFEU reset bit */ ++#define TALITOS_AFEUSR 0x8028 /* AFEU status register */ ++#define TALITOS_AFEUSR_RESET 0x01000000 /* AFEU Reset status bit */ ++#define TALITOS_AFEUISR 0x8030 /* AFEU interrupt status register */ ++#define TALITOS_AFEUIMR 0x8038 /* AFEU interrupt mask register */ ++#define TALITOS_AFEUIMR_MASK 0xf61f0000 /* AFEU interrupt control mask*/ ++ ++#define TALITOS_RNGRCR 0xe018 /* RNG Reset control register */ ++#define TALITOS_RNGRCR_SR 0x01000000 /* RNG RNGRCR:Software Reset */ ++#define TALITOS_RNGSR 0xe028 /* RNG status register */ ++#define TALITOS_RNGSR_RD 0x01000000 /* RNG Reset done */ ++#define TALITOS_RNGISR 0xe030 /* RNG Interrupt status register */ ++#define TALITOS_RNGIMR 0xe038 /* RNG interrupt mask register */ ++#define TALITOS_RNGIMR_MASK 0xc2100000 /* RNG interrupt control mask*/ ++ ++#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28 ++#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48 ++ ++/***************************RC4*******************/ ++#define ARC4_SEC_MIN_KEY_SIZE 5 ++#define ARC4_SEC_MAX_KEY_SIZE 16 ++#define ARC4_SEC_CONTEXT_LEN 259 ++#define SEC_ALG_AFEU_KEY 0x10200050 ++#define SEC_ALG_AFEU_CONTEXT 0x10700050 ++ ++/* talitos descriptor header (hdr) bits */ ++ ++/* primary execution unit select */ ++#define DESC_HDR_SEL0_MASK 0xf0000000 ++#define DESC_HDR_SEL0_AFEU 0x10000000 ++#define DESC_HDR_SEL0_DEU 0x20000000 ++#define DESC_HDR_SEL0_MDEU 0x30000000 ++#define DESC_HDR_SEL0_RNG 0x40000000 ++#define DESC_HDR_SEL0_AESU 0x60000000 ++ ++/* primary execution unit mode (MODE0) and derivatives */ ++#define DESC_HDR_MODE0_MASK 0x0ff00000 ++#define DESC_HDR_MODE0_ENCRYP 0x00100000 ++#define DESC_HDR_MODE0_AFEU_USE_KEY 0x00200000 ++#define DESC_HDR_MODE0_AFEU_USE_CONTEXT 0x00700000 ++#define DESC_HDR_MODE0_AESU_CBC 0x00200000 ++#define DESC_HDR_MODE0_AESU_ENC 0x00100000 ++#define DESC_HDR_MODE0_DEU_CBC 0x00400000 ++#define DESC_HDR_MODE0_DEU_3DES 0x00200000 ++#define DESC_HDR_MODE0_DEU_ENC 0x00100000 ++#define DESC_HDR_MODE0_MDEU_CONT 0x08000000 ++#define DESC_HDR_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ ++#define DESC_HDR_MODE0_MDEU_HMAC 0x00800000 ++#define DESC_HDR_MODE0_MDEU_PAD 0x00400000 /* PD */ ++#define DESC_HDR_MODE0_MDEU_MD5 0x00200000 ++#define DESC_HDR_MODE0_MDEU_SHA256 0x00100000 ++#define DESC_HDR_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define DESC_HDR_MODE0_MDEU_MD5_HMAC \ ++ (DESC_HDR_MODE0_MDEU_MD5 | DESC_HDR_MODE0_MDEU_HMAC) ++#define DESC_HDR_MODE0_MDEU_SHA256_HMAC \ ++ (DESC_HDR_MODE0_MDEU_SHA256 | DESC_HDR_MODE0_MDEU_HMAC) ++#define DESC_HDR_MODE0_MDEU_SHA1_HMAC \ ++ (DESC_HDR_MODE0_MDEU_SHA1 | DESC_HDR_MODE0_MDEU_HMAC) ++ ++/* secondary execution unit select (SEL1) */ ++/* it's MDEU or nothing */ ++#define DESC_HDR_SEL1_MASK 0x000f0000 ++#define DESC_HDR_SEL1_MDEU 0x00030000 ++ ++/* secondary execution unit mode (MODE1) and derivatives */ ++#define DESC_HDR_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ ++#define DESC_HDR_MODE1_MDEU_HMAC 0x00000800 ++#define DESC_HDR_MODE1_MDEU_PAD 0x00000400 /* PD */ ++#define DESC_HDR_MODE1_MDEU_MD5 0x00000200 ++#define DESC_HDR_MODE1_MDEU_SHA256 0x00000100 ++#define DESC_HDR_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define DESC_HDR_MODE1_MDEU_MD5_HMAC \ ++ (DESC_HDR_MODE1_MDEU_MD5 | DESC_HDR_MODE1_MDEU_HMAC) ++#define DESC_HDR_MODE1_MDEU_SHA256_HMAC \ ++ (DESC_HDR_MODE1_MDEU_SHA256 | DESC_HDR_MODE1_MDEU_HMAC) ++#define DESC_HDR_MODE1_MDEU_SHA1_HMAC \ ++ (DESC_HDR_MODE1_MDEU_SHA1 | DESC_HDR_MODE1_MDEU_HMAC) ++ ++/* direction of overall data flow (DIR) */ ++#define DESC_HDR_DIR_OUTBOUND 0x00000000 ++#define DESC_HDR_DIR_INBOUND 0x00000002 ++ ++/* done notification (DN) */ ++#define DESC_HDR_DONE 0x00000001 ++ ++/* descriptor types */ ++#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP (0 << 4) ++#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU (1 << 4) ++#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU (2 << 4) ++#define DESC_HDR_TYPE_NONHMAC_SNOOP_NO_AFEU (3 << 4) ++#define DESC_HDR_TYPE_COMMON_NONSNOOP_AFEU (5 << 4) ++ ++#define TALITOS_HDR_DONE_BITS 0xff000000 diff --git a/target/linux/coldfire/patches/025-Add-I2C-driver-for-MCF5445x-MCF547x-MCF548x.patch b/target/linux/coldfire/patches/025-Add-I2C-driver-for-MCF5445x-MCF547x-MCF548x.patch new file mode 100644 index 000000000..743af7f2a --- /dev/null +++ b/target/linux/coldfire/patches/025-Add-I2C-driver-for-MCF5445x-MCF547x-MCF548x.patch @@ -0,0 +1,1216 @@ +From a7c7130d916c1f7e0d27ad9b338912496ad53089 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:46 +0800 +Subject: [PATCH 25/52] Add I2C driver for MCF5445x/MCF547x/MCF548x. + +Add common I2C driver for MCF5445x/MCF547x/MCF548x and add I2C slave +mode support for MCF5445x. + +Configure I2C adaptor as slave mode and Support I2C adaptor as a +"eeprom-like" slave device. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/include/asm/mcfi2c.h | 57 +++ + drivers/i2c/busses/Kconfig | 24 ++ + drivers/i2c/busses/Makefile | 2 + + drivers/i2c/busses/i2c-algo-mcf.h | 23 ++ + drivers/i2c/busses/i2c-mcf-slave.c | 358 ++++++++++++++++++ + drivers/i2c/busses/i2c-mcf.c | 698 ++++++++++++++++++++++++++++++++++++ + 6 files changed, 1162 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/include/asm/mcfi2c.h + create mode 100644 drivers/i2c/busses/i2c-algo-mcf.h + create mode 100644 drivers/i2c/busses/i2c-mcf-slave.c + create mode 100644 drivers/i2c/busses/i2c-mcf.c + +--- /dev/null ++++ b/arch/m68k/include/asm/mcfi2c.h +@@ -0,0 +1,57 @@ ++/* ++ * mcfi2c.h -- ColdFire mcfv4/mcfv4e i2c controller support. ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++#ifndef MCF_I2C_H ++#define MCF_I2C_H ++ ++/* Register read/write macros */ ++#if defined(CONFIG_M547X_8X) ++#define MCF_I2AR MCF_REG08(0x008F00) /* I2C Address */ ++#define MCF_I2FDR MCF_REG08(0x008F04) /* I2C Frequency Divider */ ++#define MCF_I2CR MCF_REG08(0x008F08) /* I2C Control */ ++#define MCF_I2SR MCF_REG08(0x008F0C) /* I2C Status */ ++#define MCF_I2DR MCF_REG08(0x008F10) /* I2C Data I/O */ ++#define MCF_I2ICR MCF_REG08(0x008F20) /* I2C Interrupt Control */ ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++#define MCF_I2AR (*(volatile u8 *)(0xFC058000)) /* I2C Address */ ++/* I2C Frequency Divider */ ++#define MCF_I2FDR (*(volatile u8 *)(0xFC058004)) ++#define MCF_I2CR (*(volatile u8 *)(0xFC058008)) /* I2C Control */ ++#define MCF_I2SR (*(volatile u8 *)(0xFC05800C)) /* I2C Status */ ++#define MCF_I2DR (*(volatile u8 *)(0xFC058010)) /* I2C Data I/O */ ++#endif ++ ++/* Bit definitions and macros for MCF_I2C_I2AR */ ++#define MCF_I2AR_ADR(x) (((x)&0x7F)<<1) ++ ++/* Bit definitions and macros for MCF_I2C_I2FDR */ ++#define MCF_I2FDR_IC(x) (((x)&0x3F)<<0) ++ ++/* Bit definitions and macros for MCF_I2C_I2CR */ ++#define MCF_I2CR_RSTA (0x04) ++#define MCF_I2CR_TXAK (0x08) ++#define MCF_I2CR_MTX (0x10) ++#define MCF_I2CR_MSTA (0x20) ++#define MCF_I2CR_IIEN (0x40) ++#define MCF_I2CR_IEN (0x80) ++ ++/* Bit definitions and macros for MCF_I2C_I2SR */ ++#define MCF_I2SR_RXAK (0x01) ++#define MCF_I2SR_IIF (0x02) ++#define MCF_I2SR_SRW (0x04) ++#define MCF_I2SR_IAL (0x10) ++#define MCF_I2SR_IBB (0x20) ++#define MCF_I2SR_IAAS (0x40) ++#define MCF_I2SR_ICF (0x80) ++ ++/* Bit definitions and macros for MCF_I2C_I2ICR */ ++#if defined(CONFIG_M547X_8X) ++#define MCF_I2ICR_IE (0x01) ++#define MCF_I2ICR_RE (0x02) ++#define MCF_I2ICR_TE (0x04) ++#define MCF_I2ICR_BNBE (0x08) ++#endif ++ ++/********************************************************************/ ++#endif +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -431,6 +431,30 @@ config I2C_IXP2000 + This driver is deprecated and will be dropped soon. Use i2c-gpio + instead. + ++config I2C_MCF ++ tristate "MCF ColdFire I2C Interface" ++ depends on I2C && COLDFIRE ++ help ++ If you say yes to this option, support will be included for the ++ I2C on most ColdFire CPUs ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-mcf. ++ ++config I2C_MCF_SLAVE ++ tristate "MCF ColdFire I2C Slave Interface" ++ depends on !(I2C_MCF) ++ default n ++ help ++ mcf i2c adapter slave mode, only supported on mcf5445x platform. ++ ++config I2C_SLAVE_TEST ++ bool "I2C Slave Mode Test Configuration" ++ depends on I2C_MCF_SLAVE ++ default y ++ help ++ This configuration help to test I2C slave mode ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC32 +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -77,5 +77,7 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o + obj-$(CONFIG_I2C_STUB) += i2c-stub.o + obj-$(CONFIG_SCx200_ACB) += scx200_acb.o + obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o ++obj-$(CONFIG_I2C_MCF) += i2c-mcf.o ++obj-$(CONFIG_I2C_MCF_SLAVE) += i2c-mcf-slave.o + + ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG +--- /dev/null ++++ b/drivers/i2c/busses/i2c-algo-mcf.h +@@ -0,0 +1,23 @@ ++#ifndef I2C_ALGO_MCF_H ++#define I2C_ALGO_MCF_H 1 ++ ++/* --- Defines for pcf-adapters --------------------------------------- */ ++#include <linux/i2c.h> ++ ++struct i2c_algo_mcf_data { ++ void *data; /* private data for lolevel routines */ ++ void (*setmcf) (void *data, int ctl, int val); ++ int (*getmcf) (void *data, int ctl); ++ int (*getown) (void *data); ++ int (*getclock) (void *data); ++ void (*waitforpin) (void); ++ /* local settings */ ++ int udelay; ++ int mdelay; ++ int timeout; ++}; ++ ++int i2c_mcf_add_bus(struct i2c_adapter *); ++int i2c_mcf_del_bus(struct i2c_adapter *); ++ ++#endif /* I2C_ALGO_MCF_H */ +--- /dev/null ++++ b/drivers/i2c/busses/i2c-mcf-slave.c +@@ -0,0 +1,358 @@ ++/* ++ * i2c-mcf-slave.c - support adpater slave mode, now only support ++ * mcf5445x platform ++ * ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Lanttor Guo <lanttor.guo@freescale.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++*/ ++ ++#ifdef CONFIG_I2C_SLAVE_TEST ++#define DEBUG ++#endif ++ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/errno.h> ++#include <linux/i2c.h> ++#include <linux/delay.h> ++#include <linux/string.h> ++#include <linux/platform_device.h> ++#include <linux/interrupt.h> ++#include <linux/proc_fs.h> ++#include <linux/types.h> ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++#include <asm/irq.h> ++#include <asm/mcfi2c.h> ++#if defined(CONFIG_M5445X) ++#include <asm/mcf5445x_intc.h> ++#endif ++ ++#define IRQ (64+30) ++#define SLAVE_HANDLER_NAME "mcf-i2c slave handler" ++#define I2C_BUFFER_SIZE 50 ++ ++/* Structure for storing I2C transfer data */ ++struct i2c_buffer { ++ int tx_index; /* TX index */ ++ int rx_index; /* RX index */ ++ u16 length; /* Length of the buffer in bytes */ ++ u8 buf[I2C_BUFFER_SIZE]; /* Data buffer */ ++}; ++ ++struct i2c_buffer i2c_tx_buffer; ++struct i2c_buffer i2c_rx_buffer; ++ ++u8 *tx_string = "abcdefghijklmnopqrstuvwxyz0123456789)!@#$%^&*([]."; ++ ++/* ++ * I2C slave mode interrupt handler ++ * ++ */ ++static irqreturn_t i2c_slave_handler(int this_irq, void *dev_id) ++{ ++ u8 dummy_read; ++ int tmp_index; ++ ++#ifdef DEBUG ++ printk(KERN_INFO "i2c adapter slave mode irq handler.\n"); ++#endif ++ ++ /* Clear I2C interupt flag */ ++ MCF_I2SR = ~MCF_I2SR_IIF; ++ ++ /* Check if this device is in Master or Slave Mode. */ ++ if (MCF_I2CR & MCF_I2CR_MSTA) { ++ /* Master mode, do nothing here */ ++ printk(KERN_INFO "i2c master mode at %s(), do nothing!\n", ++ __func__); ++ return IRQ_NONE; ++ } else { ++ /* Slave Mode - Check if Arbitration Lost. */ ++ if (MCF_I2SR & MCF_I2SR_IAL) { ++ ++ #ifdef DEBUG ++ printk(KERN_INFO "Arbitration Lost.\n"); ++ #endif ++ ++ /* Clear IAL bit */ ++ MCF_I2SR &= ~MCF_I2SR_IAL; ++ ++ /* Arbitration Lost - ++ * Check if this device is being addressed as slave. ++ *(If not, nothing more needs to be done.) ++ */ ++ if (MCF_I2SR & MCF_I2SR_IAAS) { ++ /* Addressed as slave - ++ * Check if master was reading from slave or ++ * writing to slave. ++ */ ++ if (MCF_I2SR & MCF_I2SR_SRW) { ++ /* Set tx_index to 0 */ ++ if (i2c_tx_buffer.length == 0) { ++ i2c_tx_buffer.length = ++ I2C_BUFFER_SIZE; ++ i2c_tx_buffer.tx_index = 0; ++ } ++ ++ /* Master was reading from slave - ++ * Set Transmit Mode. ++ */ ++ MCF_I2CR |= MCF_I2CR_MTX; ++ ++ /* Write data to MBDR. */ ++ tmp_index = i2c_tx_buffer.tx_index++; ++ MCF_I2DR = i2c_tx_buffer.buf[tmp_index]; ++ i2c_tx_buffer.length--; ++ ++ #ifdef DEBUG ++ printk(KERN_INFO "Arbitration Lost: " ++ "Addressed as slave - " ++ "TX mode.\n"); ++ #endif ++ } else { ++ /* Set rx_index to 0 */ ++ i2c_rx_buffer.rx_index = 0; ++ ++ /* Master was writing to slave - ++ Set Receive Mode. */ ++ MCF_I2CR &= ~MCF_I2CR_MTX; ++ ++ /* Dummy read from MBDR, to clear ++ the ICF bit. */ ++ dummy_read = MCF_I2DR; ++ ++ #ifdef DEBUG ++ printk(KERN_INFO "Arbitration Lost: " ++ "Addressed as slave - " ++ "RX mode.\n"); ++ #endif ++ } ++ } ++ ++ } else { ++ /* Arbitration Not Lost - Check if data byte is this ++ devices's Slave Address byte. */ ++ if (MCF_I2SR & MCF_I2SR_IAAS) { ++ /* Data byte is Slave Address byte - ++ Check Slave Read/Write bit. */ ++ if (MCF_I2SR & MCF_I2SR_SRW) { ++ /* Set tx_index to 0 */ ++ if (i2c_tx_buffer.length == 0) { ++ i2c_tx_buffer.length = ++ I2C_BUFFER_SIZE; ++ i2c_tx_buffer.tx_index = 0; ++ } ++ ++ /* Master was reading from slave - ++ Set Transmit Mode. */ ++ MCF_I2CR |= MCF_I2CR_MTX; ++ ++ /* Write data to MBDR. */ ++ tmp_index = i2c_tx_buffer.tx_index++; ++ MCF_I2DR = i2c_tx_buffer.buf[tmp_index]; ++ i2c_tx_buffer.length--; ++ ++ #ifdef DEBUG ++ tmp_index = i2c_tx_buffer.tx_index - 1; ++ printk(KERN_INFO "Slave TX: First byte" ++ " - 0x%02X\n", ++ i2c_tx_buffer.buf[tmp_index]); ++ #endif ++ } else { ++ /* Master has specified Slave Receive ++ Mode. Set Receive Mode. (Writing to ++ MBCR clears IAAS.) */ ++ ++ /* Set rx_index to 0 */ ++ i2c_rx_buffer.rx_index = 0; ++ ++ MCF_I2CR &= ~MCF_I2CR_MTX; ++ ++ /* Dummy read from MBDR, to clear ++ the ICF bit. */ ++ dummy_read = MCF_I2DR; ++ ++ #ifdef DEBUG ++ printk(KERN_INFO "Slave RX: Receive " ++ "address.\n"); ++ #endif ++ } ++ } else { ++ /* Data byte received is not Slave Address byte ++ Check if this device is in Transmit or ++ Receive Mode. */ ++ if (MCF_I2CR & MCF_I2CR_MTX) { ++ /* Last byte received? */ ++ if (MCF_I2SR & MCF_I2SR_RXAK) { ++ MCF_I2CR &= ~MCF_I2CR_MTX; ++ dummy_read = MCF_I2DR; ++ ++ #ifdef DEBUG ++ printk(KERN_INFO "Slave TX: " ++ "Last byte has been " ++ "sent.\n"); ++ #endif ++ } else { ++ /* Write data to MBDR. */ ++ tmp_index = ++ i2c_tx_buffer.tx_index++; ++ MCF_I2DR = ++ i2c_tx_buffer.buf[tmp_index]; ++ i2c_tx_buffer.length--; ++ ++ if (i2c_tx_buffer.length == 0) { ++ i2c_tx_buffer.length = ++ I2C_BUFFER_SIZE; ++ i2c_tx_buffer.tx_index = ++ 0; ++ } ++ ++ } ++ } else { ++ /* Receive Mode - Read data from ++ MBDR and store it. */ ++ tmp_index = i2c_rx_buffer.rx_index++; ++ i2c_rx_buffer.buf[tmp_index] = MCF_I2DR; ++ i2c_rx_buffer.length++; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++ } ++} ++ ++#ifdef CONFIG_PROC_FS ++ ++/* ++ * Info exported via "/proc/driver/i2c". ++ */ ++ ++static int gen_i2c_proc_output(char *buf) ++{ ++ char *p; ++ ++ p = buf; ++ p += sprintf(p, ++ "I2CR: 0x%x\n" ++ "I2SR: 0x%x\n" ++ "I2DR: 0x%x\n", ++ MCF_I2CR, MCF_I2SR, MCF_I2DR); ++ ++ return p - buf; ++} ++ ++static int gen_i2c_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int len = gen_i2c_proc_output(page); ++ if (len <= off+count) ++ *eof = 1; ++ *start = page + off; ++ len -= off; ++ if (len > count) ++ len = count; ++ if (len < 0) ++ len = 0; ++ return len; ++} ++ ++static int __init gen_i2c_proc_init(void) ++{ ++ struct proc_dir_entry *r; ++ ++ r = create_proc_read_entry("driver/i2c-adaptor-register", 0, NULL, ++ gen_i2c_read_proc, NULL); ++ if (!r) ++ return -ENOMEM; ++ return 0; ++} ++#else ++static inline int gen_i2c_proc_init(void) { return 0; } ++#endif /* CONFIG_PROC_FS */ ++ ++/* ++ * Initalize I2C module ++ */ ++static int __init i2c_coldfire_init(void) ++{ ++ int retval; ++ u8 dummy_read; ++ ++#ifdef DEBUG ++ printk(KERN_INFO "init i2c adaptor slave mode!\n"); ++#endif ++ ++ /* Initialize the tx buffer */ ++ strcpy((char *)&i2c_tx_buffer.buf, (const char *)tx_string); ++ i2c_tx_buffer.length = I2C_BUFFER_SIZE; ++ ++#if defined(CONFIG_M5445X) ++ /* ++ * Initialize the GPIOs for I2C ++ */ ++ MCF_GPIO_PAR_FECI2C |= (0 ++ | MCF_GPIO_PAR_FECI2C_PAR_SDA(3) ++ | MCF_GPIO_PAR_FECI2C_PAR_SCL(3)); ++#endif ++ ++ /* Set transmission frequency 0x19 = ~100kHz */ ++ MCF_I2FDR = 0x19; ++ ++ /* set the I2C slave address */ ++ MCF_I2AR = 0x6A; ++ ++ /* Enable I2C module and if IBB is set, do the special initialzation */ ++ /* procedures as are documented */ ++ ++ if ((MCF_I2SR & MCF_I2SR_IBB) == 1) { ++ printk(KERN_INFO "%s - do special I2C init procedures\n", ++ __func__); ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0xA0; ++ dummy_read = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ } ++ ++ MCF_I2CR |= (MCF_I2CR_IEN | MCF_I2CR_IIEN); ++ ++ /* default I2C mode is - slave and receive */ ++ MCF_I2CR &= ~(MCF_I2CR_MSTA | MCF_I2CR_MTX); ++ ++ retval = request_irq(IRQ, i2c_slave_handler, IRQF_DISABLED, ++ SLAVE_HANDLER_NAME, NULL); ++ if (retval < 0) ++ printk(KERN_INFO "request_irq for i2c slave mode failed!\n"); ++ ++ retval = gen_i2c_proc_init(); ++ ++ if (retval < 0) ++ printk(KERN_INFO "gen /proc/i2c-adaptor-register for i2c slave mode failed!\n"); ++ ++ return retval; ++}; ++ ++/* ++ * I2C module exit function ++ */ ++ ++static void __exit i2c_coldfire_exit(void) ++{ ++ /* disable I2C and Interrupt */ ++ MCF_I2CR &= ~(MCF_I2CR_IEN | MCF_I2CR_IIEN); ++ free_irq(IRQ, NULL); ++ ++}; ++ ++MODULE_DESCRIPTION("MCF5445x I2C adaptor slave mode support"); ++MODULE_LICENSE("GPL"); ++ ++module_init(i2c_coldfire_init); ++module_exit(i2c_coldfire_exit); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-mcf.c +@@ -0,0 +1,698 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Lanttor.Guo@freescale.com ++ * ++ * I2C bus driver on mcfv4/mcfv4e platform ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#include <linux/i2c.h> ++#include "i2c-algo-mcf.h" ++ ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/delay.h> ++#include <linux/platform_device.h> ++#include <linux/sched.h> ++#include <linux/interrupt.h> ++#include <linux/io.h> ++#include <linux/proc_fs.h> ++ ++#include <asm/coldfire.h> ++#include <asm/mcfi2c.h> ++ ++#if defined(CONFIG_M547X_8X) ++#include <asm/m5485sim.h> ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++#include <asm/mcfsim.h> ++#endif ++ ++#define get_clock(adap) (clock) ++#define get_own(adap) (own) ++ ++#if defined(CONFIG_M547X_8X) ++static int clock = 0x3b; ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++static int clock = 0x19; ++#endif ++module_param(clock, int, 0); ++MODULE_PARM_DESC(clock, ++ "Set I2C clock in kHz: 400=fast mode (default == 100khz)"); ++ ++static int own = 0x78; ++module_param(own, int, 0); ++MODULE_PARM_DESC(clock, "Set I2C Master controller address"); ++ ++static struct i2c_algo_mcf_data i2c_mcf_board_data = { ++ .timeout = 10000, ++}; ++ ++static struct i2c_adapter i2c_mcf_board_adapter = { ++ .owner = THIS_MODULE, ++ .name = "mcf i2c adapter", ++ .algo_data = &i2c_mcf_board_data, ++ .class = I2C_CLASS_HWMON, ++ .timeout = 100, ++ .retries = 2 ++}; ++/* ++ * static void i2c_start() ++ * ++ * Generates START signal ++ */ ++static void ++i2c_start( ++ struct i2c_algo_mcf_data *adap ++) { ++ MCF_I2CR |= MCF_I2CR_MSTA; ++} ++ ++ ++/* ++ * static void i2c_stop() ++ * ++ * Generates STOP signal ++ */ ++static void ++i2c_stop( ++ struct i2c_algo_mcf_data *adap ++) { ++ MCF_I2CR &= ~MCF_I2CR_MSTA; ++} ++ ++static int ++i2c_getack( ++ struct i2c_algo_mcf_data *adap ++) { ++ return !(MCF_I2SR & MCF_I2SR_RXAK); ++} ++ ++/* ++ * static void wait_for_bb() ++ * ++ * Wait for bus idle state ++ */ ++static int ++wait_for_bb( ++ struct i2c_algo_mcf_data *adap ++) { ++ int i; ++ for (i = 0; i < adap->timeout; i++) { ++ if (!(MCF_I2SR & MCF_I2SR_IBB)) ++ return 0; ++ udelay(100); ++ } ++ printk(KERN_ERR "%s: timeout", __func__); ++ return -ETIMEDOUT; ++} ++ ++/* ++ * static void wait_for_not_bb() ++ * ++ * Wait for bus busy state ++ */ ++static int ++wait_for_not_bb( ++ struct i2c_algo_mcf_data *adap ++) { ++ int i; ++ for (i = 0; i < adap->timeout; i++) { ++ if (MCF_I2SR & MCF_I2SR_IBB) ++ return 0; ++ udelay(100); ++ } ++ printk(KERN_ERR "%s: timeout", __func__); ++ return -ETIMEDOUT; ++} ++ ++/* ++ * static void wait_xfer_done() ++ * ++ * Wait for transfer to complete ++ */ ++static int ++wait_xfer_done( ++ struct i2c_algo_mcf_data *adap ++) { ++ int i; ++ ++ for (i = 0; i < adap->timeout; i++) { ++ if (MCF_I2SR & MCF_I2SR_IIF) { ++ MCF_I2SR &= ~MCF_I2SR_IIF; ++ return 0; ++ } ++ udelay(10); ++ } ++ printk(KERN_ERR "%s: timeout", __func__); ++ return -ETIMEDOUT; ++} ++ ++ ++/* ++ * static void i2c_set_addr() ++ * ++ * Sets slave address to communicate ++ */ ++static int ++i2c_set_addr( ++ struct i2c_algo_mcf_data *adap, ++ struct i2c_msg *msg, ++ int retries ++) { ++ unsigned short flags = msg->flags; ++ unsigned char addr; ++ MCF_I2CR |= MCF_I2CR_MTX; ++ if ((flags & I2C_M_TEN)) { ++ /* 10 bit address not supported yet */ ++ return -EIO; ++ } else { ++ /* normal 7bit address */ ++ addr = (msg->addr << 1); ++ if (flags & I2C_M_RD) ++ addr |= 1; ++ if (flags & I2C_M_REV_DIR_ADDR) ++ addr ^= 1; ++ ++ MCF_I2DR = addr; ++ } ++ return 0; ++} ++ ++ ++/* ++ * static void mcf_i2c_init() ++ * ++ * Perform ColdFire i2c initialization ++ */ ++static void ++mcf_i2c_init(struct i2c_algo_mcf_data *adap) ++{ ++ u8 dummy; ++ ++ /* Setup GPIO lines */ ++#if defined(CONFIG_M547X_8X) ++ MCF_PAR_FECI2CIRQ |= MCF_PAR_SDA; ++ MCF_PAR_FECI2CIRQ |= MCF_PAR_SCL; ++#elif defined(CONFIG_M5445X) ++ MCF_GPIO_PAR_FECI2C |= (0 ++ | MCF_GPIO_PAR_FECI2C_PAR_SDA(3) ++ | MCF_GPIO_PAR_FECI2C_PAR_SCL(3)); ++#elif defined(CONFIG_M5441X) ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK) | ++ MCF_GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL; ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK) | ++ MCF_GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA; ++#endif ++ ++ /* Ensure slaves are in idle state */ ++ if (MCF_I2SR & MCF_I2SR_IBB) { ++#if defined(CONFIG_M547X_8X) ++ MCF_I2ICR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0x0A; ++ dummy = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2ICR = 0x01; ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0xA0; ++ dummy = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0x80; ++#endif ++ } ++ ++ /* setup SCL clock */ ++ MCF_I2FDR = get_clock(adap); ++ ++ /* set slave address */ ++ MCF_I2AR = get_own(adap); ++ ++ /* enable I2C module */ ++#if defined(CONFIG_M5441X) ++ MCF_I2CR = (MCF_I2CR_IEN | MCF_I2CR_IIEN); ++#else ++ MCF_I2CR = MCF_I2CR_IEN; ++#endif ++} ++ ++static int i2c_outb( ++ struct i2c_adapter *i2c_adap, ++ char c ++) { ++ ++ struct i2c_algo_mcf_data *adap = i2c_adap->algo_data; ++ int timeout; ++ /* Put data to be sent */ ++ MCF_I2DR = c; ++ /* Wait for xfer completed*/ ++ timeout = wait_xfer_done(adap); ++ if (timeout) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ printk(KERN_ERR "i2c-algo-mcf: %s i2c_write: " ++ "error - timeout.\n", i2c_adap->name); ++ return -EREMOTEIO; /* got a better one ?? */ ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * static void mcf_sendbytes() ++ * ++ * Perform tx data transfer ++ */ ++static int ++mcf_sendbytes( ++ struct i2c_adapter *i2c_adap, ++ const char *buf, ++ int count, int last ++) { ++ struct i2c_algo_mcf_data *adap = i2c_adap->algo_data; ++ int ret, i; ++ ++ /* Set master TX mode */ ++ MCF_I2CR |= MCF_I2CR_MTX; ++ ++ for (i = 0; i < count; ++i) { ++ printk(KERN_DEBUG "i2c-algo-mcf: %s i2c_write: writing %2.2X\n", ++ i2c_adap->name, buf[i]&0xff); ++ ret = i2c_outb(i2c_adap, buf[i]); ++ if (ret < 0) ++ return ret; ++ } ++ if (last) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ } else { ++ /* i2c_repstart(adap);*/ ++ } ++ ++ return i; ++} ++ ++ ++/* ++ * static void mcf_readbytes() ++ * ++ * Perform rx data transfer ++ */ ++static int ++mcf_readbytes( ++ struct i2c_adapter *i2c_adap, ++ char *buf, ++ int count, int last ++) { ++ int i; ++ struct i2c_algo_mcf_data *adap = i2c_adap->algo_data; ++ u8 dummy; ++ ++ /* Set master RX mode */ ++ MCF_I2CR &= ~MCF_I2CR_MTX; ++ MCF_I2CR &= ~MCF_I2CR_TXAK; ++ dummy = MCF_I2DR; ++ ++ for (i = 0; i < count-1; i++) { ++ if (wait_xfer_done(adap)) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ printk(KERN_DEBUG ++ "i2c-algo-mcf: mcf_readbytes timed out.\n"); ++ return -1; ++ } ++ ++ /* store next data byte */ ++ buf[i] = MCF_I2DR; ++ } ++ ++ if (wait_xfer_done(adap)) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ printk(KERN_DEBUG "i2c-algo-mcf: mcf_readbytes timed out.\n"); ++ return -1; ++ } ++ ++ /* Disable acknowlege (set I2CR.TXAK) */ ++ MCF_I2CR |= MCF_I2CR_TXAK; ++ buf[i] = MCF_I2DR; ++ if (wait_xfer_done(adap)) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ printk(KERN_DEBUG "i2c-algo-mcf: mcf_readbytes timed out.\n"); ++ return -1; ++ } ++ ++ if (last) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ } else { ++ /* i2c_repstart(adap);*/ ++ } ++ ++ return i+1; ++} ++ ++ ++/* ++ * static void mcf_xfer() ++ * ++ * Perform master data I/O transfer ++ */ ++static int ++mcf_xfer( ++ struct i2c_adapter *i2c_adap, ++ struct i2c_msg *msgs, ++ int num) ++{ ++ struct i2c_algo_mcf_data *adap = i2c_adap->algo_data; ++ struct i2c_msg *pmsg; ++ int i; ++ int ret = 0, timeout; ++ ++ /* Skip own address */ ++ if (get_own(adap) == (msgs[0].addr << 1)) ++ return -EIO; ++ ++ /* Ensure slaves are in idle state */ ++ if (MCF_I2SR & MCF_I2SR_IBB) { ++#if defined(CONFIG_M547X_8X) ++ MCF_I2ICR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0x0A; ++ timeout = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2ICR = 0x01; ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0xA0; ++ timeout = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0x80; ++#endif ++ } ++ ++ /* setup SCL clock */ ++ MCF_I2FDR = get_clock(adap); ++ /* set slave address */ ++ MCF_I2AR = get_own(adap); ++ /* enable I2C module */ ++#if defined(CONFIG_M5441X) ++ MCF_I2CR = (MCF_I2CR_IEN | MCF_I2CR_IIEN); ++#else ++ MCF_I2CR = MCF_I2CR_IEN; ++#endif ++ MCF_I2CR |= MCF_I2CR_TXAK; ++ ++ /* Check for bus busy */ ++ wait_for_bb(adap); ++ ++ for (i = 0; ret >= 0 && i < num; i++) { ++ if (MCF_I2SR & MCF_I2SR_IBB) { ++#if defined(CONFIG_M547X_8X) ++ MCF_I2ICR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0x0A; ++ timeout = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2ICR = 0x01; ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0xA0; ++ timeout = MCF_I2DR; ++ MCF_I2SR = 0x00; ++ MCF_I2CR = 0x00; ++ MCF_I2CR = 0x80; ++#endif ++ } ++ /* setup SCL clock */ ++ MCF_I2FDR = get_clock(adap); ++ /* set slave address */ ++ MCF_I2AR = get_own(adap); ++ /* enable I2C module */ ++#if defined(CONFIG_M5441X) ++ MCF_I2CR = (MCF_I2CR_IEN | MCF_I2CR_IIEN); ++#else ++ MCF_I2CR = MCF_I2CR_IEN; ++#endif ++ MCF_I2CR |= MCF_I2CR_TXAK; ++ ++ /* Check for bus busy */ ++ wait_for_bb(adap); ++ ++ pmsg = &msgs[i]; ++ ++ printk(KERN_DEBUG "i2c-algo-mcf: Doing %s %d bytes " ++ "to 0x%02x - %d of %d messages\n", ++ pmsg->flags & I2C_M_RD ? "read" : "write", ++ pmsg->len, pmsg->addr, i + 1, num); ++ ++ /* Send START */ ++ /*if (i == 0)*/ ++ i2c_start(adap); ++ ++ /* Wait for Bus Busy */ ++ wait_for_not_bb(adap); ++ ++ MCF_I2CR |= MCF_I2CR_MTX; ++ ++ ret = i2c_set_addr(adap, pmsg, i2c_adap->retries); ++ if (ret < 0) ++ return ret; ++ ++ /* Wait for address transfer completion */ ++ wait_xfer_done(adap); ++ ++ /* Check for ACK */ ++ if (!i2c_getack(adap)) { ++ i2c_stop(adap); ++ wait_for_bb(adap); ++ printk(KERN_DEBUG "i2c-algo-mcf: No ack after " ++ "send address in mcf_xfer\n"); ++ return -EREMOTEIO; ++ } ++ ++ printk(KERN_DEBUG "i2c-algo-mcf: Msg %d, " ++ "addr = 0x%x, flags = 0x%x, len = %d\n", ++ i, msgs[i].addr, msgs[i].flags, msgs[i].len); ++ /* Read */ ++ if (pmsg->flags & I2C_M_RD) { ++ /* read bytes into buffer*/ ++ ret = mcf_readbytes(i2c_adap, pmsg->buf, pmsg->len, ++ (i + 1 == num)); ++ ++ if (ret != pmsg->len) { ++ printk(KERN_DEBUG "i2c-algo-mcf: fail: " ++ "only read %d bytes.\n", ret); ++ } else { ++ printk(KERN_DEBUG "i2c-algo-mcf: " ++ "read %d bytes.\n", ret); ++ } ++ } else { ++ /* write bytes into buffer*/ ++ ret = mcf_sendbytes(i2c_adap, pmsg->buf, pmsg->len, ++ (i + 1 == num)); ++ if (ret != pmsg->len) { ++ printk(KERN_DEBUG "i2c-algo-mcf: fail: " ++ "only wrote %d bytes.\n", ret); ++ } else { ++ printk(KERN_DEBUG "i2c-algo-mcf: wrote" ++ "%d bytes.\n", ret); ++ } ++ } ++ MCF_I2CR = 0; ++ } ++ ++ /* Disable I2C module */ ++ MCF_I2CR = 0; ++ return i; ++} ++ ++ ++/* ++ * static void mcf_func() ++ * ++ * Return algorithm funtionality ++ */ ++static u32 ++mcf_func( ++ struct i2c_adapter *i2c_adap ++) { ++ return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C; ++} ++ ++/* ++ * ColdFire bus algorithm callbacks ++ */ ++static struct i2c_algorithm mcf_algo = { ++ .master_xfer = mcf_xfer, ++ .functionality = mcf_func, ++}; ++ ++/***********************************************************/ ++struct coldfire_i2c { ++ void __iomem *base; ++ struct resource *irqarea; ++ struct resource *ioarea; ++ u32 irq; ++ struct i2c_adapter *adap; ++ u32 flags; ++}; ++ ++/* ++ * registering functions to load algorithms at runtime ++ */ ++int i2c_mcf_add_bus(struct i2c_adapter *adap) ++{ ++ struct i2c_algo_mcf_data *mcf_adap = adap->algo_data; ++ ++ /*adap->id |= mcf_algo.id;*/ ++ adap->algo = &mcf_algo; ++ adap->timeout = 100; ++ ++ mcf_i2c_init(mcf_adap); ++ ++ i2c_add_numbered_adapter(adap); ++ ++ return 0; ++} ++ ++static int mcf_i2c_probe(struct platform_device *pdev) ++{ ++ struct coldfire_i2c *i2c; ++ int rc = 0; ++ ++ /************************************************************/ ++ i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); ++ if (!i2c) { ++ printk(KERN_ERR "%s kzalloc coldfire_i2c faile\n", ++ __func__); ++ return -ENOMEM; ++ } ++ /****************************************************************/ ++ platform_set_drvdata(pdev, i2c); ++ ++ i2c->adap = &i2c_mcf_board_adapter; ++ i2c->adap->dev.parent = &pdev->dev; ++ i2c->adap->nr = pdev->id; ++ rc = i2c_mcf_add_bus(i2c->adap); ++ if (rc < 0) { ++ printk(KERN_ERR "%s - failed to add adapter\n", __func__); ++ rc = -ENODEV; ++ goto fail_add; ++ } ++ ++ printk(KERN_INFO "i2c-algo-mcf.o: I2C ColdFire algorithm" ++ " module is loaded.\n"); ++ return rc; ++ ++fail_add: ++ kfree(i2c); ++ return rc; ++}; ++ ++static int mcf_i2c_remove(struct platform_device *pdev) ++{ ++ struct coldfire_i2c *i2c = platform_get_drvdata(pdev); ++ ++ i2c_del_adapter(i2c->adap); ++ platform_set_drvdata(pdev, NULL); ++ iounmap(i2c->base); ++ kfree(i2c); ++ return 0; ++}; ++ ++/* Structure for a device driver */ ++static struct platform_driver mcf_i2c_driver = { ++ .probe = mcf_i2c_probe, ++ .remove = mcf_i2c_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "mcf-i2c", ++ }, ++}; ++ ++#ifdef CONFIG_PROC_FS ++ ++/* ++ * Info exported via "/proc/driver/i2c". ++ */ ++ ++static int gen_i2c_proc_output(char *buf) ++{ ++ char *p; ++ ++ p = buf; ++ p += sprintf(p, ++ "I2CR: 0x%x\n" ++ "I2SR: 0x%x\n" ++ "I2DR: 0x%x\n", ++ MCF_I2CR, MCF_I2SR, MCF_I2DR); ++ ++ return p - buf; ++} ++ ++static int gen_i2c_read_proc(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int len = gen_i2c_proc_output(page); ++ if (len <= off+count) ++ *eof = 1; ++ *start = page + off; ++ len -= off; ++ if (len > count) ++ len = count; ++ if (len < 0) ++ len = 0; ++ return len; ++} ++ ++static int __init gen_i2c_proc_init(void) ++{ ++ struct proc_dir_entry *r; ++ ++ r = create_proc_read_entry("driver/i2c-adaptor-register", 0, NULL, ++ gen_i2c_read_proc, NULL); ++ if (!r) ++ return -ENOMEM; ++ return 0; ++} ++#else ++static inline int gen_i2c_proc_init(void) { return 0; } ++#endif /* CONFIG_PROC_FS */ ++ ++static int __init coldfire_i2c_init(void) ++{ ++ int retval; ++ ++ retval = gen_i2c_proc_init(); ++ if (retval < 0) ++ printk(KERN_INFO "generate /proc/i2c-adaptor-register " ++ "for i2c master mode failed!\n"); ++ ++ return platform_driver_register(&mcf_i2c_driver); ++} ++ ++static void __exit coldfire_i2c_exit(void) ++{ ++ platform_driver_unregister(&mcf_i2c_driver); ++} ++ ++module_init(coldfire_i2c_init); ++module_exit(coldfire_i2c_exit); ++ ++MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); ++MODULE_DESCRIPTION("I2C-Bus adapter for MCFV4/MCFV4E processors"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/coldfire/patches/026-Add-RTC-driver-support-for-MCF5445x.patch b/target/linux/coldfire/patches/026-Add-RTC-driver-support-for-MCF5445x.patch new file mode 100644 index 000000000..25b9794ba --- /dev/null +++ b/target/linux/coldfire/patches/026-Add-RTC-driver-support-for-MCF5445x.patch @@ -0,0 +1,627 @@ +From 40563ab5aa698191dbd8a05fe6053aa790eee2a1 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:46 +0800 +Subject: [PATCH 26/52] Add RTC driver support for MCF5445x + +On-chip RTC module support for MCF54451 and MCF54455. +Using internal 32K clock to drive the rtc module. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/rtc/Kconfig | 9 + + drivers/rtc/Makefile | 1 + + drivers/rtc/rtc-mcf.c | 583 +++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 593 insertions(+), 0 deletions(-) + create mode 100644 drivers/rtc/rtc-mcf.c + +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -919,6 +919,15 @@ config RTC_DRV_MV + This driver can also be built as a module. If so, the module + will be called rtc-mv. + ++config RTC_MCF ++ tristate "Freescale Coldfire Real Time Clock" ++ depends on COLDFIRE ++ help ++ If you say yes here you will get support for the on-chip Coldfire ++ Real-Time Clock. ++ ++ If you build it as a module it will be call mcf-rtc. ++ + config RTC_DRV_PS3 + tristate "PS3 RTC" + depends on PPC_PS3 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -102,3 +102,4 @@ obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41 + obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o + obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o + obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o ++obj-$(CONFIG_RTC_MCF) += rtc-mcf.o +--- /dev/null ++++ b/drivers/rtc/rtc-mcf.c +@@ -0,0 +1,583 @@ ++/* ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Implementation based on rtc-mxc.c ++ * This file contains Real Time Clock interface for Linux. ++ * ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/rtc.h> ++#include <linux/module.h> ++#include <linux/fs.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <linux/clk.h> ++#include <linux/uaccess.h> ++#include <asm/mcfsim.h> ++#include <linux/slab.h> ++#include <linux/io.h> ++ ++#ifdef readl ++#undef readl ++#endif ++ ++#ifdef writel ++#undef writel ++#endif ++ ++#define readl(addr) in_be32(addr) ++#define writel(val, addr) out_be32((addr), (val)) ++ ++#define RTC_INPUT_CLK_32768HZ 0x8000 ++#define RTC_INPUT_CLK_32000HZ 0x7D00 ++#define RTC_INPUT_CLK_38400HZ 0x9600 ++#define RTC_INPUT_CLK_48000HZ 0xBB80 ++ ++#define PIT_ALL_ON (MCF_RTC_ISR_2HZ | MCF_RTC_ISR_SAM0 | MCF_RTC_ISR_SAM1 | \ ++ MCF_RTC_ISR_SAM2 | MCF_RTC_ISR_SAM3 | MCF_RTC_ISR_SAM4 | \ ++ MCF_RTC_ISR_SAM5 | MCF_RTC_ISR_SAM6 | MCF_RTC_ISR_SAM7) ++ ++#define MAX_PIE_NUM 9 ++#define MAX_PIE_FREQ 512 ++const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { ++ {2, MCF_RTC_ISR_2HZ}, ++ {4, MCF_RTC_ISR_SAM0}, ++ {8, MCF_RTC_ISR_SAM1}, ++ {16, MCF_RTC_ISR_SAM2}, ++ {32, MCF_RTC_ISR_SAM3}, ++ {64, MCF_RTC_ISR_SAM4}, ++ {128, MCF_RTC_ISR_SAM5}, ++ {256, MCF_RTC_ISR_SAM6}, ++ {MAX_PIE_FREQ, MCF_RTC_ISR_SAM7}, ++}; ++ ++/* Those are the bits from a classic RTC we want to mimic */ ++#define RTC_IRQF 0x80 /* any of the following 3 is active */ ++#define RTC_PF 0x40 /* Periodic interrupt */ ++#define RTC_AF 0x20 /* Alarm interrupt */ ++#define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */ ++ ++#define MCF_RTC_TIME 0 ++#define MCF_RTC_ALARM 1 ++ ++struct rtc_plat_data { ++ struct rtc_device *rtc; ++ int irq; ++ unsigned int irqen; ++ int alrm_sec; ++ int alrm_min; ++ int alrm_hour; ++ int alrm_mday; ++}; ++ ++/*! ++ * @defgroup RTC Real Time Clock (RTC) Driver ++ */ ++/*! ++ * @file rtc-mcf.c ++ * @brief Real Time Clock interface ++ * ++ * This file contains Real Time Clock interface for Linux. ++ * ++ * @ingroup RTC ++ */ ++ ++#define RTC_VERSION "0.1" ++ ++static u32 rtc_freq = 2; /* minimun value for PIE */ ++static unsigned long rtc_status; ++ ++static struct rtc_time g_rtc_alarm = { ++ .tm_year = 0, ++ .tm_mon = 0, ++ .tm_mday = 0, ++ .tm_hour = 0, ++ .tm_mon = 0, ++ .tm_sec = 0, ++}; ++ ++static DEFINE_SPINLOCK(rtc_lock); ++ ++/*! ++ * This function is used to obtain the RTC time or the alarm value in ++ * second. ++ * ++ * @param time_alarm use MCF_RTC_TIME for RTC time value; ++ * MCF_RTC_ALARM for alarm value ++ * ++ * @return The RTC time or alarm time in second. ++ */ ++static u32 get_alarm_or_time(struct device *dev, int time_alarm) ++{ ++ u32 day, hr, min, sec, hr_min; ++ ++ if (time_alarm == MCF_RTC_TIME) { ++ day = MCF_RTC_DAYS_DAYS(readl(MCF_RTC_DAYS)); ++ hr_min = readl(MCF_RTC_HOURMIN); ++ sec = MCF_RTC_SECONDS_SECONDS(readl(MCF_RTC_SECONDS)); ++ } else if (time_alarm == MCF_RTC_ALARM) { ++ day = MCF_RTC_ALRM_DAY_DAYS(readl(MCF_RTC_ALRM_DAY)); ++ hr_min = readl(MCF_RTC_ALRM_HM); ++ sec = MCF_RTC_ALRM_SEC_SECONDS(readl(MCF_RTC_ALRM_SEC)); ++ } else { ++ panic("wrong value for time_alarm=%d\n", time_alarm); ++ } ++ ++ hr = (hr_min >> 8) & 0x001F; ++ min = hr_min & 0x003F; ++ ++ return (((day * 24 + hr) * 60) + min) * 60 + sec; ++} ++ ++/*! ++ * This function sets the RTC alarm value or the time value. ++ * ++ * @param time_alarm the new alarm value to be updated in the RTC ++ * @param time use MCF_RTC_TIME for RTC time value; ++ * MCF_RTC_ALARM for alarm value ++ */ ++static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time) ++{ ++ u32 day, hr, min, sec, temp; ++ ++ day = time / 86400; ++ time -= day * 86400; ++ /* time is within a day now */ ++ hr = time / 3600; ++ time -= hr * 3600; ++ /* time is within an hour now */ ++ min = time / 60; ++ sec = time - min * 60; ++ ++ temp = (hr << 8) + min; ++ ++ if (time_alarm == MCF_RTC_TIME) { ++ writel(day, MCF_RTC_DAYS); ++ writel(sec, MCF_RTC_SECONDS); ++ writel(temp, MCF_RTC_HOURMIN); ++ } else if (time_alarm == MCF_RTC_ALARM) { ++ writel(day, MCF_RTC_ALRM_DAY); ++ writel(sec, MCF_RTC_ALRM_SEC); ++ writel(temp, MCF_RTC_ALRM_HM); ++ } else { ++ panic("wrong value for time_alarm=%d\n", time_alarm); ++ } ++} ++ ++/*! ++ * This function updates the RTC alarm registers and then clears all the ++ * interrupt status bits. ++ * ++ * @param alrm the new alarm value to be updated in the RTC ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) ++{ ++ struct rtc_time alarm_tm, now_tm; ++ unsigned long now, time; ++ int ret; ++ ++ now = get_alarm_or_time(dev, MCF_RTC_TIME); ++ rtc_time_to_tm(now, &now_tm); ++ alarm_tm.tm_year = now_tm.tm_year; ++ alarm_tm.tm_mon = now_tm.tm_mon; ++ alarm_tm.tm_mday = now_tm.tm_mday; ++ alarm_tm.tm_hour = alrm->tm_hour; ++ alarm_tm.tm_min = alrm->tm_min; ++ alarm_tm.tm_sec = alrm->tm_sec; ++ rtc_tm_to_time(&now_tm, &now); ++ rtc_tm_to_time(&alarm_tm, &time); ++ if (time < now) { ++ time += 60 * 60 * 24; ++ rtc_time_to_tm(time, &alarm_tm); ++ } ++ ret = rtc_tm_to_time(&alarm_tm, &time); ++ ++ /* clear all the interrupt status bits */ ++ writel(readl(MCF_RTC_ISR), MCF_RTC_ISR); ++ ++ set_alarm_or_time(dev, MCF_RTC_ALARM, time); ++ ++ return ret; ++} ++ ++/*! ++ * This function is the RTC interrupt service routine. ++ * ++ * @param irq RTC IRQ number ++ * @param dev_id device ID which is not used ++ * ++ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file. ++ */ ++static irqreturn_t mcf_rtc_interrupt(int irq, void *dev_id) ++{ ++ struct platform_device *pdev = dev_id; ++ struct rtc_plat_data *pdata = platform_get_drvdata(pdev); ++ u32 status, events = 0; ++ ++ spin_lock(&rtc_lock); ++ ++ /* clear interrupt sources */ ++ status = readl(MCF_RTC_ISR) & readl(MCF_RTC_IER); ++ writel(status, MCF_RTC_ISR); ++ ++ /* clear alarm interrupt if it has occurred */ ++ if (status & MCF_RTC_ISR_ALM) ++ status &= ~MCF_RTC_ISR_ALM; ++ ++ /* update irq data & counter */ ++ if (status & MCF_RTC_ISR_ALM) ++ events |= (RTC_AF | RTC_IRQF); ++ if (status & MCF_RTC_ISR_1HZ) ++ events |= (RTC_UF | RTC_IRQF); ++ if (status & PIT_ALL_ON) ++ events |= (RTC_PF | RTC_IRQF); ++ ++ if ((status & MCF_RTC_ISR_ALM) && rtc_valid_tm(&g_rtc_alarm)) ++ rtc_update_alarm(&pdev->dev, &g_rtc_alarm); ++ ++ spin_unlock(&rtc_lock); ++ rtc_update_irq(pdata->rtc, 1, events); ++ return IRQ_HANDLED; ++} ++ ++/*! ++ * clear all interrupts and release the IRQ ++ */ ++static void mcf_rtc_release(struct device *dev) ++{ ++ spin_lock_irq(&rtc_lock); ++ writel(0, MCF_RTC_IER); /* Disable all rtc interrupts */ ++ writel(0x0000FFBF, MCF_RTC_ISR); /* Clear all interrupt status */ ++ spin_unlock_irq(&rtc_lock); ++ rtc_status = 0; ++} ++ ++/*! ++ * This function is used to support some ioctl calls directly. ++ * Other ioctl calls are supported indirectly through the ++ * arm/common/rtctime.c file. ++ * ++ * @param cmd ioctl command as defined in include/linux/rtc.h ++ * @param arg value for the ioctl command ++ * ++ * @return 0 if successful or negative value otherwise. ++ */ ++static int mcf_rtc_ioctl(struct device *dev, unsigned int cmd, ++ unsigned long arg) ++{ ++ int i; ++ ++ switch (cmd) { ++ case RTC_PIE_OFF: ++ writel((readl(MCF_RTC_IER) & ~PIT_ALL_ON), MCF_RTC_IER); ++ return 0; ++ case RTC_IRQP_SET: ++ if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0) ++ return -EINVAL; /* Also make sure a power of 2Hz */ ++ if ((arg > 64) && (!capable(CAP_SYS_RESOURCE))) ++ return -EACCES; ++ rtc_freq = arg; ++ return 0; ++ case RTC_IRQP_READ: ++ return put_user(rtc_freq, (u32 *) arg); ++ case RTC_PIE_ON: ++ for (i = 0; i < MAX_PIE_NUM; i++) { ++ if (PIE_BIT_DEF[i][0] == rtc_freq) ++ break; ++ } ++ if (i == MAX_PIE_NUM) ++ return -EACCES; ++ spin_lock_irq(&rtc_lock); ++ writel((readl(MCF_RTC_IER) | PIE_BIT_DEF[i][1]), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ case RTC_AIE_OFF: ++ spin_lock_irq(&rtc_lock); ++ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ ++ case RTC_AIE_ON: ++ spin_lock_irq(&rtc_lock); ++ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ ++ case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */ ++ spin_lock_irq(&rtc_lock); ++ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_1HZ), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ ++ case RTC_UIE_ON: ++ spin_lock_irq(&rtc_lock); ++ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_1HZ), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ } ++ return -ENOIOCTLCMD; ++} ++ ++/*! ++ * This function reads the current RTC time into tm in Gregorian date. ++ * ++ * @param tm contains the RTC time value upon return ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ u32 val; ++ ++ /* Avoid roll-over from reading the different registers */ ++ do { ++ val = get_alarm_or_time(dev, MCF_RTC_TIME); ++ } while (val != get_alarm_or_time(dev, MCF_RTC_TIME)); ++ ++ rtc_time_to_tm(val, tm); ++ return 0; ++} ++ ++/*! ++ * This function sets the internal RTC time based on tm in Gregorian date. ++ * ++ * @param tm the time value to be set in the RTC ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ unsigned long time; ++ int ret; ++ ++ ret = rtc_tm_to_time(tm, &time); ++ if (ret != 0) ++ return ret; ++ ++ /* Avoid roll-over from reading the different registers */ ++ do { ++ set_alarm_or_time(dev, MCF_RTC_TIME, time); ++ } while (time != get_alarm_or_time(dev, MCF_RTC_TIME)); ++ ++ return ret; ++} ++ ++/*! ++ * This function reads the current alarm value into the passed in \b alrm ++ * argument. It updates the \b alrm's pending field value based on the whether ++ * an alarm interrupt occurs or not. ++ * ++ * @param alrm contains the RTC alarm value upon return ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ rtc_time_to_tm(get_alarm_or_time(dev, MCF_RTC_ALARM), &alrm->time); ++ alrm->pending = ((readl(MCF_RTC_ISR) & MCF_RTC_ISR_ALM) != 0) ? 1 : 0; ++ ++ return 0; ++} ++ ++/*! ++ * This function sets the RTC alarm based on passed in alrm. ++ * ++ * @param alrm the alarm value to be set in the RTC ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ int ret; ++ ++ spin_lock_irq(&rtc_lock); ++ if (rtc_valid_tm(&alrm->time)) { ++ if (alrm->time.tm_sec > 59 || ++ alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ret = rtc_update_alarm(dev, &alrm->time); ++ } else { ++ ret = rtc_valid_tm(&alrm->time); ++ if (ret) ++ goto out; ++ ret = rtc_update_alarm(dev, &alrm->time); ++ } ++ ++ if (ret == 0) { ++ memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); ++ ++ if (alrm->enabled) { ++ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_ALM), ++ MCF_RTC_IER); ++ } else { ++ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), ++ MCF_RTC_IER); ++ } ++ } ++out: ++ spin_unlock_irq(&rtc_lock); ++ ++ return ret; ++} ++ ++/*! ++ * This function is used to provide the content for the /proc/driver/rtc ++ * file. ++ * ++ * @param buf the buffer to hold the information that the driver ++ * wants to write ++ * ++ * @return The number of bytes written into the rtc file. ++ */ ++static int mcf_rtc_proc(struct device *dev, struct seq_file *sq) ++{ ++ char *p = sq->buf; ++ ++ p += sprintf(p, "alarm_IRQ\t: %s\n", ++ (((readl(MCF_RTC_IER)) & MCF_RTC_ISR_ALM) != ++ 0) ? "yes" : "no"); ++ p += sprintf(p, "update_IRQ\t: %s\n", ++ (((readl(MCF_RTC_IER)) & MCF_RTC_ISR_1HZ) != ++ 0) ? "yes" : "no"); ++ p += sprintf(p, "periodic_IRQ\t: %s\n", ++ (((readl(MCF_RTC_IER)) & PIT_ALL_ON) != ++ 0) ? "yes" : "no"); ++ p += sprintf(p, "periodic_freq\t: %d\n", rtc_freq); ++ ++ return p - (sq->buf); ++} ++ ++/*! ++ * The RTC driver structure ++ */ ++static struct rtc_class_ops mcf_rtc_ops = { ++ .ioctl = mcf_rtc_ioctl, ++ .read_time = mcf_rtc_read_time, ++ .set_time = mcf_rtc_set_time, ++ .read_alarm = mcf_rtc_read_alarm, ++ .set_alarm = mcf_rtc_set_alarm, ++ .proc = mcf_rtc_proc, ++}; ++ ++static int __devinit mcf_rtc_probe(struct platform_device *pdev) ++{ ++ struct timespec tv; ++ struct rtc_device *rtc; ++ struct rtc_plat_data *pdata = NULL; ++ u32 ret = 0; ++ ++ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) ++ return -ENOMEM; ++ /* External clock is hard wired to 32768Hz. ++ * Clock settings 32K, 38.4K and 48K are defined above. */ ++#if defined(CONFIG_M5227x) | defined(CONFIG_M5445X) ++ writel(0, MCF_RTC_GOCU); ++ writel(RTC_INPUT_CLK_32768HZ, MCF_RTC_GOCL); ++#endif ++ /* Configure and enable the RTC */ ++ pdata->irq = MCFINT_VECBASE + MCFINT_RTC; ++ if (request_irq(pdata->irq, mcf_rtc_interrupt, IRQF_DISABLED, ++ pdev->name, pdev) < 0) { ++ dev_warn(&pdev->dev, "interrupt not available.\n"); ++ pdata->irq = -1; ++ } ++ ++ if (test_and_set_bit(1, &rtc_status)) ++ return -EBUSY; ++ ++ rtc = rtc_device_register(pdev->name, &pdev->dev, &mcf_rtc_ops, ++ THIS_MODULE); ++ if (IS_ERR(rtc)) { ++ ret = PTR_ERR(rtc); ++ if (pdata->irq >= 0) ++ free_irq(pdata->irq, pdev); ++ kfree(pdata); ++ return ret; ++ } ++ pdata->rtc = rtc; ++ platform_set_drvdata(pdev, pdata); ++ ++ tv.tv_nsec = 0; ++ tv.tv_sec = get_alarm_or_time(&pdev->dev, MCF_RTC_TIME); ++ ++#ifdef CONFIG_M5301x ++ writel(RTC_INPUT_CLK_32768HZ, MCF_RTC_GOC); ++ writel(0x08, MCF_RTC_OCEN); ++#endif ++ writeb(4, MCFSIM_ICR_RTC); ++ ++ writel(MCF_RTC_IER_1HZ, MCF_RTC_IER); /* Unmask the 1Hz timer */ ++ ++ writel(MCF_RTC_CR_EN, MCF_RTC_CR); ++ if ((readl(MCF_RTC_CR) & MCF_RTC_CR_EN) == 0) { ++ printk(KERN_ALERT "RTC Hardware couldn't be enabled!\n"); ++ return -EPERM; ++ } ++ ++ printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION); ++ return ret; ++} ++ ++static int __devexit mcf_rtc_remove(struct platform_device *pdev) ++{ ++ struct rtc_plat_data *pdata = platform_get_drvdata(pdev); ++ ++ rtc_device_unregister(pdata->rtc); ++ if (pdata->irq >= 0) ++ free_irq(pdata->irq, pdev); ++ kfree(pdata); ++ mcf_rtc_release(NULL); ++ return 0; ++} ++ ++/*! ++ * Contains pointers to the power management callback functions. ++ */ ++MODULE_ALIAS("mcf-rtc"); ++static struct platform_driver mcf_rtc_driver = { ++ .driver = { ++ .name = "mcf-rtc", ++ .owner = THIS_MODULE, ++ }, ++ .probe = mcf_rtc_probe, ++ .remove = __devexit_p(mcf_rtc_remove), ++}; ++ ++/*! ++ * This function creates the /proc/driver/rtc file and registers the device RTC ++ * in the /dev/misc directory. It also reads the RTC value from external source ++ * and setup the internal RTC properly. ++ * ++ * @return -1 if RTC is failed to initialize; 0 is successful. ++ */ ++static int __init mcf_rtc_init(void) ++{ ++ return platform_driver_register(&mcf_rtc_driver); ++} ++ ++/*! ++ * This function removes the /proc/driver/rtc file and un-registers the ++ * device RTC from the /dev/misc directory. ++ */ ++static void __exit mcf_rtc_exit(void) ++{ ++ platform_driver_unregister(&mcf_rtc_driver); ++ ++} ++ ++module_init(mcf_rtc_init); ++module_exit(mcf_rtc_exit); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("Real Time Clock Driver (MCF)"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/coldfire/patches/027-Add-RTC-driver-support-on-MCF5441x-platform.patch b/target/linux/coldfire/patches/027-Add-RTC-driver-support-on-MCF5441x-platform.patch new file mode 100644 index 000000000..78ae75d35 --- /dev/null +++ b/target/linux/coldfire/patches/027-Add-RTC-driver-support-on-MCF5441x-platform.patch @@ -0,0 +1,681 @@ +From 6462d09dad154b69ea6180c0acb2d009627ff1be Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:46 +0800 +Subject: [PATCH 27/52] Add RTC driver support on MCF5441x platform + +Support on-chip robust-RTC module on MCF5441x platform. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/rtc/Kconfig | 9 + + drivers/rtc/Makefile | 1 + + drivers/rtc/rtc-m5441x.c | 638 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 648 insertions(+), 0 deletions(-) + create mode 100644 drivers/rtc/rtc-m5441x.c + +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -928,6 +928,15 @@ config RTC_MCF + + If you build it as a module it will be call mcf-rtc. + ++config RTC_M5441X ++ tristate "Freescale Coldfire M5441X platform Real Time Clock" ++ depends on COLDFIRE ++ help ++ If you say yes here you will get support for the on-chip Coldfire ++ Real-Time Clock for mcf5441x platform. ++ ++ If you build it as a module it will be call rtc-m5441x. ++ + config RTC_DRV_PS3 + tristate "PS3 RTC" + depends on PPC_PS3 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -103,3 +103,4 @@ obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm83 + obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o + obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o + obj-$(CONFIG_RTC_MCF) += rtc-mcf.o ++obj-$(CONFIG_RTC_M5441X) += rtc-m5441x.o +--- /dev/null ++++ b/drivers/rtc/rtc-m5441x.c +@@ -0,0 +1,638 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Lanttor.Guo@freescale.com ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/* ++ * Implementation based on rtc-mcf.c ++ */ ++ ++/* ++ * RTC Real Time Clock (RTC) Driver ++ * ++ * @file rtc-m5441x.c ++ * @brief Real Time Clock interface ++ * ++ * This file contains Real Time Clock interface for Linux. ++ * ++ */ ++#include <linux/rtc.h> ++#include <linux/module.h> ++#include <linux/fs.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <linux/clk.h> ++#include <linux/uaccess.h> ++#include <asm/mcfsim.h> ++#include <linux/slab.h> ++#include <linux/io.h> ++ ++#ifdef readw ++#undef readw ++#endif ++ ++#ifdef writew ++#undef writew ++#endif ++ ++#define readw(addr) in_be16(addr) ++#define writew(val, addr) out_be16((addr), (val)) ++ ++ ++#define PIT_ALL_ON (MCF_RTC_ISR_2HZ | MCF_RTC_ISR_SAM0 | MCF_RTC_ISR_SAM1 | \ ++ MCF_RTC_ISR_SAM2 | MCF_RTC_ISR_SAM3 | MCF_RTC_ISR_SAM4 | \ ++ MCF_RTC_ISR_SAM5 | MCF_RTC_ISR_SAM6 | MCF_RTC_ISR_SAM7) ++ ++#define MAX_PIE_NUM 9 ++#define MAX_PIE_FREQ 512 ++const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { ++ {2, MCF_RTC_ISR_2HZ}, ++ {4, MCF_RTC_ISR_SAM0}, ++ {8, MCF_RTC_ISR_SAM1}, ++ {16, MCF_RTC_ISR_SAM2}, ++ {32, MCF_RTC_ISR_SAM3}, ++ {64, MCF_RTC_ISR_SAM4}, ++ {128, MCF_RTC_ISR_SAM5}, ++ {256, MCF_RTC_ISR_SAM6}, ++ {MAX_PIE_FREQ, MCF_RTC_ISR_SAM7}, ++}; ++ ++/* Those are the bits from a classic RTC we want to mimic */ ++#define RTC_IRQF 0x80 /* any of the following 3 is active */ ++#define RTC_PF 0x40 /* Periodic interrupt */ ++#define RTC_AF 0x20 /* Alarm interrupt */ ++#define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */ ++ ++#define MCF_RTC_TIME 0 ++#define MCF_RTC_ALARM 1 ++ ++struct rtc_plat_data { ++ struct rtc_device *rtc; ++ int irq; ++ unsigned int irqen; ++ int alrm_sec; ++ int alrm_min; ++ int alrm_hour; ++ int alrm_mday; ++}; ++ ++static const int year_cal_basic = 2112; ++ ++#define RTC_VERSION "0.1" ++ ++static u32 rtc_freq = 2; /* minimun value for PIE */ ++static unsigned long rtc_status; ++ ++static struct rtc_time g_rtc_alarm = { ++ .tm_year = 0, ++ .tm_mon = 0, ++ .tm_mday = 0, ++ .tm_hour = 0, ++ .tm_mon = 0, ++ .tm_sec = 0, ++}; ++ ++static DEFINE_SPINLOCK(rtc_lock); ++ ++ ++/* ++ * This funciton is used to disable RTC register write protection ++ */ ++static void disable_register_write_protection(void) ++{ ++ if (readw(MCF_RTC_SR) & MCF_RTC_SR_WPE) { ++ writew(0x0000, MCF_RTC_CR); ++ writew(0x0001, MCF_RTC_CR); ++ writew(0x0003, MCF_RTC_CR); ++ writew(0x0002, MCF_RTC_CR); ++ } ++ ++} ++ ++/* ++ * This function is used to obtain the RTC time or the alarm value in ++ * second. ++ * ++ * @param time_alarm use MCF_RTC_TIME for RTC time value; ++ * MCF_RTC_ALARM for alarm value ++ * ++ * @return The RTC time or alarm time in second. ++ */ ++static u32 get_alarm_or_time(struct device *dev, int time_alarm, ++ struct rtc_time *tm) ++{ ++ dev_dbg(dev, "debug function %s()!\n", __func__); ++ ++ if (time_alarm == MCF_RTC_TIME) { ++ /*check register information */ ++ dev_dbg(dev, "RTC_YEARMON:0x%x,RTC_DAYS:0x%x,RTC_HOURMIN:0x%x," ++ "RTC_SECONDS:0x%x\n", readw(MCF_RTC_YEARMON), ++ readw(MCF_RTC_DAYS), readw(MCF_RTC_HOURMIN), ++ readw(MCF_RTC_SECONDS)); ++ ++ /* get year */ ++ tm->tm_year = year_cal_basic + ++ (char)(MCF_RTC_YEARMON_YEAR_RD(readw(MCF_RTC_YEARMON))); ++ /* get month */ ++ tm->tm_mon = ++ MCF_RTC_YEARMON_MON_RD(readw(MCF_RTC_YEARMON)) - 1; ++ /* get month day */ ++ tm->tm_mday = MCF_RTC_DAYS_DAY_RD(readw(MCF_RTC_DAYS)); ++ /* get year day */ ++ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, ++ tm->tm_year); ++ /* year minus 1900 */ ++ tm->tm_year = tm->tm_year - 1900; ++ /* get week day */ ++ tm->tm_wday = MCF_RTC_DAYS_DAYWEEK_RD(readw(MCF_RTC_DAYS)); ++ /* get hours */ ++ tm->tm_hour = ++ MCF_RTC_HOURMIN_HOURS_RD(readw(MCF_RTC_HOURMIN)); ++ /* get minutes */ ++ tm->tm_min = ++ MCF_RTC_HOURMIN_MINUTES_RD(readw(MCF_RTC_HOURMIN)); ++ /* get seconds */ ++ tm->tm_sec = ++ MCF_RTC_SECONDS_SECONDS_RD(readw(MCF_RTC_SECONDS)); ++ /* no day saving time */ ++ tm->tm_isdst = -1; ++ ++ /* check rtc_tm fileds information */ ++ dev_dbg(dev, "RTC TIME --> year:%d,yday:%d,mon:%d,mday:%d," ++ "wday:%d,hour:%d,min:%d,sec:%d\n", tm->tm_year, ++ tm->tm_yday, tm->tm_mon, tm->tm_mday, tm->tm_wday, ++ tm->tm_hour, tm->tm_min, tm->tm_sec); ++ ++ } else if (time_alarm == MCF_RTC_ALARM) { ++ tm->tm_year = year_cal_basic + ++ (char)MCF_RTC_YEARMON_YEAR_RD ++ (readw(MCF_RTC_ALRM_YRMON)); ++ tm->tm_mon = ++ MCF_RTC_YEARMON_MON_RD(readw(MCF_RTC_ALRM_YRMON)) - 1; ++ tm->tm_mday = MCF_RTC_DAYS_DAY_RD(readw(MCF_RTC_ALRM_DAYS)); ++ tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, ++ tm->tm_year); ++ tm->tm_year = tm->tm_year - 1900; ++ tm->tm_wday = ++ MCF_RTC_DAYS_DAYWEEK_RD(readw(MCF_RTC_ALRM_DAYS)); ++ tm->tm_hour = ++ MCF_RTC_HOURMIN_HOURS_RD(readw(MCF_RTC_ALRM_HM)); ++ tm->tm_min = ++ MCF_RTC_HOURMIN_MINUTES_RD(readw(MCF_RTC_ALRM_HM)); ++ tm->tm_sec = ++ MCF_RTC_SECONDS_SECONDS_RD(readw(MCF_RTC_ALRM_SEC)); ++ tm->tm_isdst = -1; ++ ++ /* debug information */ ++ dev_dbg(dev, "RTC ALARM --> year:%d,yday:%d,mon:%d,mday:%d," ++ "wday:%d,hour:%d,min:%d,sec:%d\n", tm->tm_year, ++ tm->tm_yday, tm->tm_mon, tm->tm_mday, tm->tm_wday, ++ tm->tm_hour, tm->tm_min, tm->tm_sec); ++ ++ } else { ++ panic("wrong value for time_alarm=%d\n", time_alarm); ++ } ++ ++ return 0; ++} ++ ++/* ++ * This function sets the RTC alarm value or the time value. ++ * ++ * @param time_alarm the new alarm value to be updated in the RTC ++ * @param time use MCF_RTC_TIME for RTC time value; ++ * MCF_RTC_ALARM for alarm value ++ */ ++static void set_alarm_or_time(struct device *dev, int time_alarm, ++ struct rtc_time *tm) ++{ ++ char year; ++ ++ dev_dbg(dev, "debug function %s()!\n", __func__); ++ ++ /* wirte enable setting */ ++ disable_register_write_protection(); ++ ++ if (time_alarm == MCF_RTC_TIME) { ++ /* check rtc_time fields information */ ++ dev_dbg(dev, "RTC TIME --> year:%d,yday:%d,mon:%d,mday:%d," ++ "wday:%d,hour:%d,min:%d,sec:%d\n", tm->tm_year, ++ tm->tm_yday, tm->tm_mon, tm->tm_mday, tm->tm_wday, ++ tm->tm_hour, tm->tm_min, tm->tm_sec); ++ ++ year = ((tm->tm_year + 1900) - year_cal_basic); ++ /* write RTC_YEARMON register */ ++ writew((year << 8) | (tm->tm_mon + 1), MCF_RTC_YEARMON); ++ ++ /* write RTC_DAYS register */ ++ writew(MCF_RTC_DAYS_DAYWEEK_SET(tm->tm_wday) | ++ MCF_RTC_DAYS_DAY_SET(tm->tm_mday), MCF_RTC_DAYS); ++ ++ /* write RTC_HOURMIN register */ ++ writew(MCF_RTC_HOURMIN_HOURS_SET(tm->tm_hour) | ++ MCF_RTC_HOURMIN_MINUTES_SET(tm->tm_min), ++ MCF_RTC_HOURMIN); ++ ++ /* write RTC_SECONDS register */ ++ writew(MCF_RTC_SECONDS_SECONDS_SET ++ (tm->tm_sec), MCF_RTC_SECONDS); ++ ++ /* debug information */ ++ dev_dbg(dev, "RTC_YEARMON:0x%x, RTC_DAYS:0x%x, " ++ "RTC_HOURMIN:0x%x, RTC_SECONDS:0x%x\n", ++ readw(MCF_RTC_YEARMON), readw(MCF_RTC_DAYS), ++ readw(MCF_RTC_HOURMIN), readw(MCF_RTC_SECONDS)); ++ } else if (time_alarm == MCF_RTC_ALARM) { ++ ++ year = ((tm->tm_year + 1900) - year_cal_basic); ++ /* write RTC_YEARMON register */ ++ writew((year << 8) | (tm->tm_mon + 1), MCF_RTC_ALRM_YRMON); ++ ++ /* write RTC_DAYS register */ ++ writew(MCF_RTC_DAYS_DAYWEEK_SET(tm->tm_wday) | ++ MCF_RTC_DAYS_DAY_SET(tm->tm_mday), MCF_RTC_ALRM_DAYS); ++ ++ /* write RTC_HOURMIN register */ ++ writew(MCF_RTC_HOURMIN_HOURS_SET(tm->tm_hour) | ++ MCF_RTC_HOURMIN_MINUTES_SET(tm->tm_min), ++ MCF_RTC_ALRM_HM); ++ ++ /* write RTC_SECONDS register */ ++ writew(MCF_RTC_SECONDS_SECONDS_SET ++ (tm->tm_sec), MCF_RTC_ALRM_SEC); ++ ++ /* debug information */ ++ dev_dbg(dev, "ALRM_YRMON:0x%x,ALRM_DAYS:0x%x,ALRM_HM:0x%x," ++ "ALRM_SEC:0x%x\n", readw(MCF_RTC_ALRM_YRMON), ++ readw(MCF_RTC_ALRM_DAYS), readw(MCF_RTC_ALRM_HM), ++ readw(MCF_RTC_ALRM_SEC)); ++ } else { ++ panic("wrong value for time_alarm=%d\n", time_alarm); ++ } ++} ++ ++/*! ++ * This function updates the RTC alarm registers and then clears all the ++ * interrupt status bits. ++ * ++ * @param alrm the new alarm value to be updated in the RTC ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) ++{ ++ /* clear all the interrupt status bits */ ++ disable_register_write_protection(); ++ ++ writew(readw(MCF_RTC_ISR), MCF_RTC_ISR); ++ ++ set_alarm_or_time(dev, MCF_RTC_ALARM, alrm); ++ ++ return 0; ++} ++ ++/*! ++ * This function is the RTC interrupt service routine. ++ * ++ * @param irq RTC IRQ number ++ * @param dev_id device ID which is not used ++ * ++ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file. ++ */ ++static irqreturn_t mcf_rtc_interrupt(int irq, void *dev_id) ++{ ++ struct platform_device *pdev = dev_id; ++ struct rtc_plat_data *pdata = platform_get_drvdata(pdev); ++ u16 status = 0; ++ u32 events = 0; ++ ++ spin_lock(&rtc_lock); ++ ++ /* clear interrupt sources */ ++ status = readw(MCF_RTC_ISR) & readw(MCF_RTC_IER); ++ ++ disable_register_write_protection(); ++ ++ writew(status, MCF_RTC_ISR); ++ ++ /* clear alarm interrupt if it has occurred */ ++ if (status & MCF_RTC_ISR_ALM) ++ status &= ~MCF_RTC_ISR_ALM; ++ ++ /* update irq data & counter */ ++ if (status & MCF_RTC_ISR_ALM) ++ events |= (RTC_AF | RTC_IRQF); ++ if (status & MCF_RTC_ISR_1HZ) ++ events |= (RTC_UF | RTC_IRQF); ++ if (status & PIT_ALL_ON) ++ events |= (RTC_PF | RTC_IRQF); ++ ++ if ((status & MCF_RTC_ISR_ALM) && rtc_valid_tm(&g_rtc_alarm)) ++ rtc_update_alarm(&pdev->dev, &g_rtc_alarm); ++ ++ spin_unlock(&rtc_lock); ++ rtc_update_irq(pdata->rtc, 1, events); ++ return IRQ_HANDLED; ++} ++ ++/*! ++ * clear all interrupts and release the IRQ ++ */ ++static void mcf_rtc_release(struct device *dev) ++{ ++ spin_lock_irq(&rtc_lock); ++ ++ disable_register_write_protection(); ++ ++ writew(0, MCF_RTC_IER); /* Disable all rtc interrupts */ ++ writew(readw(MCF_RTC_ISR), MCF_RTC_ISR); ++ spin_unlock_irq(&rtc_lock); ++ rtc_status = 0; ++} ++ ++/*! ++ * This function is used to support some ioctl calls directly. ++ * Other ioctl calls are supported indirectly through the ++ * arm/common/rtctime.c file. ++ * ++ * @param cmd ioctl command as defined in include/linux/rtc.h ++ * @param arg value for the ioctl command ++ * ++ * @return 0 if successful or negative value otherwise. ++ */ ++static int mcf_rtc_ioctl(struct device *dev, unsigned int cmd, ++ unsigned long arg) ++{ ++ int i; ++ ++ disable_register_write_protection(); ++ ++ switch (cmd) { ++ case RTC_PIE_OFF: ++ writew((readw(MCF_RTC_IER) & ~PIT_ALL_ON), MCF_RTC_IER); ++ return 0; ++ case RTC_IRQP_SET: ++ if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0) ++ return -EINVAL; /* Also make sure a power of 2Hz */ ++ if ((arg > 64) && (!capable(CAP_SYS_RESOURCE))) ++ return -EACCES; ++ rtc_freq = arg; ++ return 0; ++ case RTC_IRQP_READ: ++ return put_user(rtc_freq, (u32 *) arg); ++ case RTC_PIE_ON: ++ for (i = 0; i < MAX_PIE_NUM; i++) { ++ if (PIE_BIT_DEF[i][0] == rtc_freq) ++ break; ++ } ++ if (i == MAX_PIE_NUM) ++ return -EACCES; ++ spin_lock_irq(&rtc_lock); ++ writew((readw(MCF_RTC_IER) | PIE_BIT_DEF[i][1]), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ case RTC_AIE_OFF: ++ spin_lock_irq(&rtc_lock); ++ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ ++ case RTC_AIE_ON: ++ spin_lock_irq(&rtc_lock); ++ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ ++ case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */ ++ spin_lock_irq(&rtc_lock); ++ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_1HZ), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ ++ case RTC_UIE_ON: ++ spin_lock_irq(&rtc_lock); ++ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_1HZ), MCF_RTC_IER); ++ spin_unlock_irq(&rtc_lock); ++ return 0; ++ } ++ return -ENOIOCTLCMD; ++} ++ ++/*! ++ * This function reads the current RTC time into tm in Gregorian date. ++ * ++ * @param tm contains the RTC time value upon return ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ do { ++ get_alarm_or_time(dev, MCF_RTC_TIME, tm); ++ } while (0); ++ ++ return 0; ++} ++ ++/*! ++ * This function sets the internal RTC time based on tm in Gregorian date. ++ * ++ * @param tm the time value to be set in the RTC ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ do { ++ set_alarm_or_time(dev, MCF_RTC_TIME, tm); ++ } while (0); ++ ++ return 0; ++} ++ ++/*! ++ * This function reads the current alarm value into the passed in \b alrm ++ * argument. It updates the \b alrm's pending field value based on the whether ++ * an alarm interrupt occurs or not. ++ * ++ * @param alrm contains the RTC alarm value upon return ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ do { ++ get_alarm_or_time(dev, MCF_RTC_ALARM, &alrm->time); ++ } while (0); ++ ++ alrm->pending = ((readw(MCF_RTC_ISR) & MCF_RTC_ISR_ALM) != 0) ? 1 : 0; ++ ++ return 0; ++} ++ ++/*! ++ * This function sets the RTC alarm based on passed in alrm. ++ * ++ * @param alrm the alarm value to be set in the RTC ++ * ++ * @return 0 if successful; non-zero otherwise. ++ */ ++static int mcf_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ int ret; ++ ++ spin_lock_irq(&rtc_lock); ++ ++ disable_register_write_protection(); ++ ++ if (rtc_valid_tm(&alrm->time)) { ++ if (alrm->time.tm_sec > 59 || ++ alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ret = rtc_update_alarm(dev, &alrm->time); ++ } else { ++ ret = rtc_valid_tm(&alrm->time); ++ if (ret) ++ goto out; ++ ret = rtc_update_alarm(dev, &alrm->time); ++ } ++ ++ if (ret == 0) { ++ memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); ++ ++ if (alrm->enabled) { ++ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_ALM), ++ MCF_RTC_IER); ++ } else { ++ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), ++ MCF_RTC_IER); ++ } ++ } ++out: ++ spin_unlock_irq(&rtc_lock); ++ ++ return ret; ++} ++ ++/*! ++ * The RTC driver structure ++ */ ++static struct rtc_class_ops mcf_rtc_ops = { ++ .ioctl = mcf_rtc_ioctl, ++ .read_time = mcf_rtc_read_time, ++ .set_time = mcf_rtc_set_time, ++ .read_alarm = mcf_rtc_read_alarm, ++ .set_alarm = mcf_rtc_set_alarm, ++}; ++ ++static int __devinit mcf_rtc_probe(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc; ++ struct rtc_plat_data *pdata = NULL; ++ u32 ret = 0; ++ ++ disable_register_write_protection(); ++ /* Clear interrupt before request irq */ ++ writew(0x0100, MCF_RTC_CR); ++ writew(0x0001, MCF_RTC_IER); ++ ++ if (!(readw(MCF_RTC_CFG_DATA) & MCF_RTC_CFG_DATA_OSCEN)) ++ writew(MCF_RTC_CFG_DATA_OSCEN, MCF_RTC_CFG_DATA); ++ ++ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) ++ return -ENOMEM; ++ ++ pdata->irq = MCFINT_VECBASE + MCFINT_RTC; ++ if (request_irq(pdata->irq, mcf_rtc_interrupt, IRQF_DISABLED, ++ pdev->name, pdev) < 0) { ++ dev_warn(&pdev->dev, "interrupt not available.\n"); ++ pdata->irq = -1; ++ } ++ ++ if (test_and_set_bit(1, &rtc_status)) ++ return -EBUSY; ++ ++ rtc = rtc_device_register(pdev->name, &pdev->dev, &mcf_rtc_ops, ++ THIS_MODULE); ++ if (IS_ERR(rtc)) { ++ ret = PTR_ERR(rtc); ++ if (pdata->irq >= 0) ++ free_irq(pdata->irq, pdev); ++ kfree(pdata); ++ return ret; ++ } ++ pdata->rtc = rtc; ++ platform_set_drvdata(pdev, pdata); ++ ++ dev_dbg(&pdev->dev, "RTC_CR:0x%x, RTC_SR:0x%x\n", readw(MCF_RTC_CR), ++ readw(MCF_RTC_SR)); ++ ++ printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION); ++ return ret; ++} ++ ++static int __devexit mcf_rtc_remove(struct platform_device *pdev) ++{ ++ struct rtc_plat_data *pdata = platform_get_drvdata(pdev); ++ ++ rtc_device_unregister(pdata->rtc); ++ if (pdata->irq >= 0) ++ free_irq(pdata->irq, pdev); ++ kfree(pdata); ++ mcf_rtc_release(NULL); ++ return 0; ++} ++ ++/*! ++ * Contains pointers to the power management callback functions. ++ */ ++MODULE_ALIAS("rtc-m5441x"); ++static struct platform_driver mcf_rtc_driver = { ++ .driver = { ++ .name = "rtc-m5441x", ++ .owner = THIS_MODULE, ++ }, ++ .probe = mcf_rtc_probe, ++ .remove = __devexit_p(mcf_rtc_remove), ++}; ++ ++/*! ++ * This function creates the /proc/driver/rtc file and registers the device RTC ++ * in the /dev/misc directory. It also reads the RTC value from external source ++ * and setup the internal RTC properly. ++ * ++ * @return -1 if RTC is failed to initialize; 0 is successful. ++ */ ++static int __init mcf_rtc_init(void) ++{ ++ return platform_driver_register(&mcf_rtc_driver); ++} ++ ++/*! ++ * This function removes the /proc/driver/rtc file and un-registers the ++ * device RTC from the /dev/misc directory. ++ */ ++static void __exit mcf_rtc_exit(void) ++{ ++ platform_driver_unregister(&mcf_rtc_driver); ++ ++} ++ ++module_init(mcf_rtc_init); ++module_exit(mcf_rtc_exit); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("Real Time Clock Driver (MCF)"); ++MODULE_LICENSE("GPL V2"); diff --git a/target/linux/coldfire/patches/028-Add-SD-MMC-SDIO-over-SPI-support-for-MCF54451-and-MC.patch b/target/linux/coldfire/patches/028-Add-SD-MMC-SDIO-over-SPI-support-for-MCF54451-and-MC.patch new file mode 100644 index 000000000..5cd981da8 --- /dev/null +++ b/target/linux/coldfire/patches/028-Add-SD-MMC-SDIO-over-SPI-support-for-MCF54451-and-MC.patch @@ -0,0 +1,195 @@ +From d1b6aa1480c937e326bef99746299cd004a51f28 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:46 +0800 +Subject: [PATCH 28/52] Add SD/MMC/SDIO over SPI support for MCF54451 and MCF54418 + +Add SD/MMC/SDIO over SPI support for MCF54451 and MCF54418. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/mmc/core/sdio.c | 9 +++++- + drivers/mmc/host/Kconfig | 35 +++++++++++++++++++++ + drivers/mmc/host/mmc_spi.c | 73 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 116 insertions(+), 1 deletions(-) + +--- a/drivers/mmc/core/sdio.c ++++ b/drivers/mmc/core/sdio.c +@@ -566,8 +566,15 @@ static void mmc_sdio_detect(struct mmc_h + /* + * Just check if our card has been removed. + */ ++#if defined(M54451_SD_HW_DETECT) ++ { ++ unsigned char x; ++ err = mmc_io_rw_direct(host->card, 0, 0, ++ SDIO_FBR_BASE(0) + SDIO_FBR_CIS + 0, 0, &x); ++ } ++#else + err = mmc_select_card(host->card); +- ++#endif + mmc_release_host(host); + + /* +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -368,6 +368,41 @@ config MMC_SPI + + If unsure, or if your system has no SPI master driver, say N. + ++config M54451_SD_HW_DETECT ++ tristate "use extern IRQ7 to detect SD/MMC card" ++ depends on MMC_SPI && M54451 ++ default y ++ help ++ MMC/SD interface on 54551evb was over SPI. Enable this option will ++ use irq7 to dectect the card inserting/removing. ++ ++config M5441X_SD_HW_DETECT ++ tristate "use extern IRQ to detect SD/MMC card" ++ depends on MMC_SPI && M5441X ++ help ++ MMC/SD interface on 54418evb was over SPI. Enable this option will ++ use irq7 or irq1 to dectect the card inserting/removing. ++ ++choice ++ prompt "MMC/SD card detect " ++ depends on M5441X_SD_HW_DETECT ++ ++config DETECT_USE_EXTERN_IRQ7 ++ tristate "based extern IRQ7" ++ depends on M5441X_SD_HW_DETECT ++ help ++ MMC/SD cards using spi controller, ++ we use the extern irq7 to detect card. ++ ++config DETECT_USE_EXTERN_IRQ1 ++ tristate "based extern IRQ1" ++ depends on M5441X_SD_HW_DETECT ++ help ++ MMC/SD cards using spi controller, ++ we use the extern irq1 to detect card. ++ ++endchoice ++ + config MMC_S3C + tristate "Samsung S3C SD/MMC Card Interface support" + depends on ARCH_S3C2410 +--- a/drivers/mmc/host/mmc_spi.c ++++ b/drivers/mmc/host/mmc_spi.c +@@ -9,6 +9,10 @@ + * (C) Copyright 2007, ATRON electronic GmbH, + * Jan Nikitenko <jan.nikitenko@gmail.com> + * ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Modified for M54451EVB/M54418TWR boards. ++ * Shrek Wu <b16972@freescale.com> ++ * Jingchang Lu <b22599@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -32,6 +36,14 @@ + #include <linux/crc7.h> + #include <linux/crc-itu-t.h> + #include <linux/scatterlist.h> ++#if defined(CONFIG_M54451_SD_HW_DETECT) ++#include <asm/mcf5445x_eport.h> ++#include <asm/mcf5445x_intc.h> ++#include <asm/mcfsim.h> ++#elif defined(CONFIG_M5441X_SD_HW_DETECT) ++#include <asm/mcf5441x_eport.h> ++#include <asm/mcfsim.h> ++#endif + + #include <linux/mmc/host.h> + #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */ +@@ -268,6 +280,9 @@ static int mmc_spi_response_get(struct m + unsigned short rotator; + int i; + char tag[32]; ++#if defined(CONFIG_M54451_SD_HW_DETECT) || defined(CONFIG_M5441X_SD_HW_DETECT) ++ u8 oldcp_value = 0; ++#endif + + snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s", + cmd->opcode, maptype(cmd)); +@@ -278,6 +293,9 @@ static int mmc_spi_response_get(struct m + * first byte. After STOP_TRANSMISSION command it may include + * two data bits, but otherwise it's all ones. + */ ++#if defined(CONFIG_M54451_SD_HW_DETECT) || defined(CONFIG_M5441X_SD_HW_DETECT) ++ oldcp_value = *cp; ++#endif + cp += 8; + while (cp < end && *cp == 0xff) + cp++; +@@ -310,6 +328,15 @@ static int mmc_spi_response_get(struct m + } + + checkstatus: ++#if defined(CONFIG_M54451_SD_HW_DETECT) || defined(CONFIG_M5441X_SD_HW_DETECT) ++ if ((*cp == 0) && (oldcp_value == 0)) { ++ dev_dbg(&host->spi->dev, "NO CARD in the SD SOCKET, " ++ "new status %02x, old status %02x\n", ++ *cp, oldcp_value); ++ value = -EBADR; ++ goto done; ++ } ++#endif + bitshift = 0; + if (*cp & 0x80) { + /* Houston, we have an ugly card with a bit-shifted response */ +@@ -1313,7 +1340,53 @@ mmc_spi_detect_irq(int irq, void *mmc) + struct mmc_spi_host *host = mmc_priv(mmc); + u16 delay_msec = max(host->pdata->detect_delay, (u16)100); + ++#if defined(CONFIG_M54451_SD_HW_DETECT) ++ dev_dbg(&host->spi->dev, "mmc_spi_detect_irq " ++ "MCF_EPORT_EPPAR %x, MCF_EPORT_EPIER %x," ++ "MCF_INTC0_ICR7 %x, MCF_GPIO_PAR_IRQ %x," ++ "MCF_EPORT_EPDDR %x, MCF_EPORT_EPFR %x\n", ++ MCF_EPORT_EPPAR, MCF_EPORT_EPIER, ++ MCF_INTC0_ICR7, MCF_GPIO_PAR_IRQ, ++ MCF_EPORT_EPDDR, MCF_EPORT_EPFR); ++ ++ MCF_EPORT_EPIER &= (~MCF_EPORT_EPIER_EPIE7); ++#elif defined(CONFIG_M5441X_SD_HW_DETECT) ++#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1) ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE1); ++#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7) ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7); ++#else ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7); ++#endif ++#endif + mmc_detect_change(mmc, msecs_to_jiffies(delay_msec)); ++#if defined(CONFIG_M54451_SD_HW_DETECT) ++ MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ MCF_EPORT_EPFR |= MCF_EPORT_EPFR_EPF7; ++ dev_dbg(&host->spi->dev, "mmc_spi_detect_irq " ++ "MCF_EPORT_EPPAR %x, MCF_EPORT_EPIER %x," ++ "MCF_INTC0_ICR7 %x, MCF_GPIO_PAR_IRQ %x," ++ "MCF_EPORT_EPDDR %x, MCF_EPORT_EPFR %x\n", ++ MCF_EPORT_EPPAR, MCF_EPORT_EPIER, ++ MCF_INTC0_ICR7, MCF_GPIO_PAR_IRQ, ++ MCF_EPORT_EPDDR, MCF_EPORT_EPFR); ++ ++#elif defined(CONFIG_M5441X_SD_HW_DETECT) ++#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1) ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1; ++ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF1; ++#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7) ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7; ++#else ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7; ++#endif ++#endif + return IRQ_HANDLED; + } + diff --git a/target/linux/coldfire/patches/029-Add-eSDHC-driver-for-MCF5441x.patch b/target/linux/coldfire/patches/029-Add-eSDHC-driver-for-MCF5441x.patch new file mode 100644 index 000000000..b1a7d46a3 --- /dev/null +++ b/target/linux/coldfire/patches/029-Add-eSDHC-driver-for-MCF5441x.patch @@ -0,0 +1,2214 @@ +From 73c65ac21faf1b016f8f8ddfab2dc3e58a5618f9 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:46 +0800 +Subject: [PATCH 29/52] Add eSDHC driver for MCF5441x + +Add eSDHC PIO mode(read and write) and DMA mode(read and write) support. +Add card detect using extern irq. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/mmc/host/Kconfig | 35 + + drivers/mmc/host/Makefile | 1 + + drivers/mmc/host/esdhc.c | 1826 +++++++++++++++++++++++++++++++++++++++++++++ + drivers/mmc/host/esdhc.h | 310 ++++++++ + 4 files changed, 2172 insertions(+), 0 deletions(-) + create mode 100644 drivers/mmc/host/esdhc.c + create mode 100644 drivers/mmc/host/esdhc.h + +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -403,6 +403,41 @@ config DETECT_USE_EXTERN_IRQ1 + + endchoice + ++config MMC_ESDHC ++ tristate "Enhanced Secure Digital Host Controller Interface support" ++ depends on M5441X ++ help ++ This select Freescale Enhanced SD Host Controller Interface. ++ The controller is used in MCF5441x. ++ If unsure, say N. ++ ++config ESDHC_FORCE_PIO ++ tristate "eSDHC force to use PIO (no DMA) mode" ++ depends on MMC_ESDHC ++ help ++ This select Freescale Enhanced SD Host Controller Interface. ++ The controller is used in MCF5441x. ++ If unsure, say N. ++ ++choice ++ prompt "MMC/SD card detect " ++ depends on MMC_ESDHC ++ ++config ESDHC_DETECT_USE_EXTERN_IRQ7 ++ bool "based extern IRQ7" ++ depends on MMC_ESDHC ++ help ++ MMC/SD cards using esdhc controller, ++ we use the extern irq7 to detect card. ++config ESDHC_DETECT_USE_EXTERN_IRQ1 ++ bool "based extern IRQ1" ++ depends on MMC_ESDHC ++ help ++ MMC/SD cards using esdhc controller, ++ we use the extern irq7 to detect card. ++ ++endchoice ++ + config MMC_S3C + tristate "Samsung S3C SD/MMC Card Interface support" + depends on ARCH_S3C2410 +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -28,6 +28,7 @@ endif + obj-$(CONFIG_MMC_S3C) += s3cmci.o + obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o + obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o ++obj-$(CONFIG_MMC_ESDHC) += esdhc.o + obj-$(CONFIG_MMC_CB710) += cb710-mmc.o + obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o + obj-$(CONFIG_GPIOMMC) += gpiommc.o +--- /dev/null ++++ b/drivers/mmc/host/esdhc.c +@@ -0,0 +1,1826 @@ ++/* ++ * drivers/mmc/host/esdhc.c ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Chenghu Wu <b16972@freescale.com> ++ * Xiaobo Xie <X.Xie@freescale.com> ++ * ++ * Freescale Enhanced Secure Digital Host Controller driver. ++ * Based on mpc837x/driver/mmc/host/esdhc.c done by Xiaobo Xie ++ * Ported to Coldfire platform by Chenghu Wu ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/ioport.h> ++#include <linux/interrupt.h> ++#include <linux/delay.h> ++#include <linux/highmem.h> ++#include <linux/dma-mapping.h> ++#include <linux/scatterlist.h> ++#include <linux/uaccess.h> ++#include <linux/irq.h> ++#include <linux/io.h> ++#include <linux/slab.h> ++#include <linux/mmc/host.h> ++ ++#include <asm/dma.h> ++#include <asm/page.h> ++ ++#include <linux/platform_device.h> ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++ ++#include "esdhc.h" ++#define DRIVER_NAME "esdhc" ++ ++ ++#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1) ++#define card_detect_extern_irq (64 + 1) ++#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7) ++#define card_detect_extern_irq (64 + 7) ++#else ++#define card_detect_extern_irq (64 + 7) ++#endif ++ ++#undef ESDHC_DMA_KMALLOC ++ ++#define SYS_BUSCLOCK 80000000 ++#define ESDHC_DMA_SIZE 0x10000 ++ ++#undef MMC_ESDHC_DEBUG ++#undef MMC_ESDHC_DEBUG_REG ++ ++#ifdef MMC_ESDHC_DEBUG ++#define DBG(fmt, args...) printk(KERN_INFO "[%s] " fmt "\n", __func__, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#ifdef MMC_ESDHC_DEBUG_REG ++static void esdhc_dumpregs(struct esdhc_host *host) ++{ ++ printk(KERN_INFO "========= REGISTER DUMP ==========\n"); ++ ++ printk(KERN_INFO "Sysaddr: 0x%08x | Blkattr: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_DMA_ADDRESS), ++ fsl_readl(host->ioaddr + ESDHC_BLOCK_ATTR)); ++ printk(KERN_INFO "Argument: 0x%08x | COMMAND: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_ARGUMENT), ++ fsl_readl(host->ioaddr + ESDHC_COMMAND)); ++ printk(KERN_INFO "Present: 0x%08x | DMA ctl: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE), ++ fsl_readl(host->ioaddr + ESDHC_DMA_SYSCTL)); ++ printk(KERN_INFO "PROCTL: 0x%08x | SYSCTL: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL), ++ fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL)); ++ printk(KERN_INFO "Int stat: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_INT_STATUS)); ++ printk(KERN_INFO "Intenab: 0x%08x | Sigenab: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_INT_ENABLE), ++ fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE)); ++ printk(KERN_INFO "AC12 err: 0x%08x | Version: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_ACMD12_ERR), ++ fsl_readl(host->ioaddr + ESDHC_HOST_VERSION)); ++ printk(KERN_INFO "Caps: 0x%08x | Watermark: 0x%08x\n", ++ fsl_readl(host->ioaddr + ESDHC_CAPABILITIES), ++ fsl_readl(host->ioaddr + ESDHC_WML)); ++ printk(KERN_INFO "MCF_INTC1_IPRH: 0x%08x | MCF_INTC1_IPRL: 0x%08x\n", ++ (unsigned int)MCF_INTC1_IPRH, ++ (unsigned int)MCF_INTC1_IPRL); ++ printk(KERN_INFO "MCF_INTC1_IMRH: 0x%08x | MCF_INTC1_IMRL: 0x%08x\n", ++ (unsigned int)MCF_INTC1_IMRH, ++ (unsigned int)MCF_INTC1_IMRL); ++ printk(KERN_INFO "MCF_INTC1_INTFRCH: 0x%08x | MCF_INTC1_INTFRCL: 0x%08x\n", ++ (unsigned int)MCF_INTC1_INTFRCH, ++ (unsigned int)MCF_INTC1_INTFRCL); ++ printk(KERN_INFO "MCF_INTC1_INTFRCH: 0x%08x | MCF_INTC1_INTFRCL: 0x%08x\n", ++ (unsigned int)MCF_INTC1_INTFRCH, ++ (unsigned int)MCF_INTC1_INTFRCL); ++ printk(KERN_INFO "MCF_INTC1_ICR63: 0x%08x | MCF_INTC0_ICR36: 0x%08x\n", ++ (unsigned int)MCF_INTC1_ICR63, ++ (unsigned int)MCF_INTC0_ICR36); ++ ++ printk(KERN_INFO "==================================\n"); ++} ++#else ++static void esdhc_dumpregs(struct esdhc_host *host) ++{ ++ do {} while (0); ++} ++#endif ++ ++ ++static unsigned int debug_nodma; ++static unsigned int debug_forcedma; ++static unsigned int debug_quirks; ++ ++#define ESDHC_QUIRK_CLOCK_BEFORE_RESET (1<<0) ++#define ESDHC_QUIRK_FORCE_DMA (1<<1) ++#define ESDHC_QUIRK_NO_CARD_NO_RESET (1<<2) ++#define ESDHC_QUIRK_SINGLE_POWER_WRITE (1<<3) ++ ++static void esdhc_prepare_data(struct esdhc_host *, struct mmc_data *); ++static void esdhc_finish_data(struct esdhc_host *); ++static irqreturn_t esdhc_irq(int irq, void *dev_id); ++static void esdhc_send_command(struct esdhc_host *, struct mmc_command *); ++static void esdhc_finish_command(struct esdhc_host *); ++ ++/*****************************************************************************\ ++ * * ++ * Low level functions * ++ * * ++\*****************************************************************************/ ++ ++static void esdhc_reset(struct esdhc_host *host, u8 mask) ++{ ++ unsigned long timeout; ++ unsigned int sysctl; ++ ++ if (host->chip->quirks & ESDHC_QUIRK_NO_CARD_NO_RESET) { ++ if (!(fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) & ++ ESDHC_CARD_PRESENT)) ++ return; ++ } ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ timeout = timeout | (mask << ESDHC_RESET_SHIFT); ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout); ++ ++ if (mask & ESDHC_RESET_ALL) { ++ host->clock = 0; ++ host->bus_width = 0; ++ } ++ ++ /* Wait max 100 ms */ ++ timeout = 100; ++ ++ /* hw clears the bit when it's done */ ++ sysctl = (mask << ESDHC_RESET_SHIFT); ++ while (fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL) & sysctl) { ++ if (timeout == 0) { ++ printk(KERN_ERR "%s: Reset 0x%x never completed.\n", ++ mmc_hostname(host->mmc), (int)mask); ++ esdhc_dumpregs(host); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++} ++ ++static void esdhc_init(struct esdhc_host *host) ++{ ++ u32 intmask; ++ /*reset eSDHC chip*/ ++ esdhc_reset(host, ESDHC_RESET_ALL); ++ ++ intmask = fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE); ++ intmask = intmask & 0xF7000000; ++ fsl_writel(host->ioaddr + ESDHC_PRESENT_STATE, intmask); ++ ++ intmask = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ intmask = intmask | ESDHC_CLOCK_INT_EN | ESDHC_CLOCK_INT_STABLE; ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, intmask); ++ ++ intmask = fsl_readl(host->ioaddr + ESDHC_INT_STATUS); ++ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, intmask); ++ ++ intmask = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE); ++ ++ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, intmask); ++ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, intmask); ++ /* Modelo does not support */ ++ /*MCF_ESDHC_SCR = MCF_ESDHC_SCR | ESDHC_DMA_SNOOP | 0xC0;*/ ++ ++ intmask = fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL); ++ intmask &= ~ESDHC_CTRL_D3_DETEC; ++ ++ fsl_writel(host->ioaddr + ESDHC_PROTOCOL_CONTROL, intmask); ++ DBG(" init %x\n", fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL)); ++} ++ ++static void reset_regs(struct esdhc_host *host) ++{ ++ u32 intmask; ++ ++ intmask = fsl_readl(host->ioaddr + ESDHC_INT_STATUS); ++ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, intmask); ++ ++ intmask = ESDHC_INT_DATA_END_BIT | ESDHC_INT_DATA_CRC | ++ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_INDEX | ++ ESDHC_INT_END_BIT | ESDHC_INT_CRC | ESDHC_INT_TIMEOUT | ++ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | ++ ESDHC_INT_DMA_END | ESDHC_INT_DATA_END | ESDHC_INT_RESPONSE; ++ ++ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, intmask); ++ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, intmask); ++ ++ if (host->bus_width == MMC_BUS_WIDTH_4) { ++ intmask = fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL); ++ intmask |= ESDHC_CTRL_4BITBUS; ++ fsl_writel(host->ioaddr + ESDHC_PROTOCOL_CONTROL, intmask); ++ } ++} ++ ++/***************************************************************************** ++ * * ++ * Core functions * ++ * * ++ *****************************************************************************/ ++/* Return the SG's virtual address */ ++static inline char *esdhc_sg_to_buffer(struct esdhc_host *host) ++{ ++ DBG("cur_sg %x virt %x\n", host->cur_sg, sg_virt(host->cur_sg)); ++ return sg_virt(host->cur_sg); ++} ++ ++static inline int esdhc_next_sg(struct esdhc_host *host) ++{ ++ /* ++ * Skip to next SG entry. ++ */ ++ host->cur_sg = sg_next(host->cur_sg); ++ host->num_sg--; ++ ++ /* ++ * Any entries left? ++ */ ++ if (host->num_sg > 0) { ++ host->offset = 0; ++ host->remain = host->cur_sg->length; ++ } ++ ++ DBG("%s: host->remain %x %x\n", __func__, host->remain, host->num_sg); ++ return host->num_sg; ++} ++ ++static void esdhc_read_block_pio(struct esdhc_host *host) ++{ ++ int blksize, chunk_remain; ++ u32 data; ++ char *buffer; ++ int size; ++ ++ DBG("PIO reading\n"); ++ ++ /* Delay prevents data read error in big files */ ++ udelay(100); ++ ++ blksize = host->data->blksz; ++ chunk_remain = 0; ++ data = 0; ++ ++ buffer = esdhc_sg_to_buffer(host) + host->offset; ++ ++ while (blksize) { ++ if (chunk_remain == 0) { ++ data = fsl_readl(host->ioaddr + ESDHC_BUFFER); ++ chunk_remain = min(blksize, 4); ++ } ++ ++ size = min(host->remain, chunk_remain); ++ ++ chunk_remain -= size; ++ blksize -= size; ++ host->offset += size; ++ host->remain -= size; ++ ++ while (size) { ++ *buffer = data & 0xFF; ++ buffer++; ++ data >>= 8; ++ size--; ++ } ++ ++ if (host->remain == 0) { ++ if (esdhc_next_sg(host) == 0) { ++ BUG_ON(blksize != 0); ++ return; ++ } ++ buffer = esdhc_sg_to_buffer(host); ++ } ++ } ++} ++ ++static void esdhc_write_block_pio(struct esdhc_host *host) ++{ ++ int blksize, chunk_remain; ++ u32 data; ++ char *buffer; ++ int bytes, size; ++ ++ DBG("PIO writing\n"); ++ ++ /* Delay necessary when writing large data blocks to SD card */ ++ udelay(100); ++ ++ blksize = host->data->blksz; ++ chunk_remain = 4; ++ data = 0; ++ ++ bytes = 0; ++ buffer = esdhc_sg_to_buffer(host) + host->offset; ++ ++ while (blksize) { ++ size = min(host->remain, chunk_remain); ++ ++ chunk_remain -= size; ++ blksize -= size; ++ host->offset += size; ++ host->remain -= size; ++ ++ while (size) { ++ data >>= 8; ++ data |= (u32)*buffer << 24; ++ buffer++; ++ size--; ++ } ++ ++ if (chunk_remain == 0) { ++ fsl_writel(host->ioaddr + ESDHC_BUFFER, data); ++ chunk_remain = min(blksize, 4); ++ } ++ ++ if (host->remain == 0) { ++ if (esdhc_next_sg(host) == 0) { ++ BUG_ON(blksize != 0); ++ return; ++ } ++ buffer = esdhc_sg_to_buffer(host); ++ } ++ } ++} ++ ++static void esdhc_transfer_pio(struct esdhc_host *host) ++{ ++ u32 mask; ++ ++ BUG_ON(!host->data); ++ ++ if (host->num_sg == 0) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) ++ mask = ESDHC_DATA_AVAILABLE; ++ else ++ mask = ESDHC_SPACE_AVAILABLE; ++ ++ while (fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) & mask) { ++ if (host->data->flags & MMC_DATA_READ) ++ esdhc_read_block_pio(host); ++ else ++ esdhc_write_block_pio(host); ++ ++ if (host->num_sg == 0) ++ break; ++ } ++ ++ DBG("PIO transfer complete.\n"); ++ /* Delay necessary when writing large data blocks to SD card */ ++ udelay(100); ++} ++ ++static void esdhc_prepare_data(struct esdhc_host *host, struct mmc_data *data) ++{ ++ u8 count; ++ unsigned blkattr = 0; ++ unsigned target_timeout, current_timeout; ++ unsigned int sysctl; ++ ++ WARN_ON(host->data); ++ ++ if (data == NULL) ++ return; ++ ++ DBG("blksz %04x blks %04x flags %08x", ++ data->blksz, data->blocks, data->flags); ++ DBG("tsac %d ms nsac %d clk", ++ data->timeout_ns / 1000000, data->timeout_clks); ++ ++ /* Sanity checks */ ++ BUG_ON(data->blksz * data->blocks > 524288); ++ BUG_ON(data->blksz > host->mmc->max_blk_size); ++ BUG_ON(data->blocks > 65535); ++ ++ if (host->clock == 0) ++ return; ++ ++ /* timeout in us */ ++ target_timeout = data->timeout_ns / 1000 + ++ (data->timeout_clks * 1000000) / host->clock; ++ ++ /* ++ * Figure out needed cycles. ++ * We do this in steps in order to fit inside a 32 bit int. ++ * The first step is the minimum timeout, which will have a ++ * minimum resolution of 6 bits: ++ * (1) 2^13*1000 > 2^22, ++ * (2) host->timeout_clk < 2^16 ++ * => ++ * (1) / (2) > 2^6 ++ */ ++ count = 0; ++ host->timeout_clk = host->clock/1000; ++ current_timeout = (1 << 13) * 1000 / host->timeout_clk; ++ while (current_timeout < target_timeout) { ++ count++; ++ current_timeout <<= 1; ++ if (count >= 0xF) ++ break; ++ } ++ ++ if (count >= 0xF) { ++ DBG("%s:Timeout requested is too large!\n", ++ mmc_hostname(host->mmc)); ++ count = 0xE; ++ } ++ ++ if (data->blocks >= 0x50) { ++ DBG("%s:Blocks %x are too large!\n", ++ mmc_hostname(host->mmc), ++ data->blocks); ++ count = 0xE; ++ } ++ ++ if ((data->blocks == 1) && (data->blksz >= 0x200)) { ++ DBG("%s:Blocksize %x is too large\n", ++ mmc_hostname(host->mmc), ++ data->blksz); ++ count = 0xE; ++ } ++ count = 0xE; ++ ++ sysctl = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ sysctl &= (~ESDHC_TIMEOUT_MASK); ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, ++ sysctl | (count<<ESDHC_TIMEOUT_SHIFT)); ++ ++ /* Data transfer*/ ++ if (host->flags & ESDHC_USE_DMA) { ++ int sg_count; ++ unsigned int wml; ++ unsigned int wml_value; ++ unsigned int timeout; ++ ++ /* DMA address eSDHC in Modelo must be 4 bytes aligned */ ++ if ((data->sg->offset & 0x3) == 0) ++ host->offset = 0; ++ else ++ host->offset = 0x4 - (data->sg->offset & 0x3); ++ ++ sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, ++ data->sg_len, ++ (data->flags & MMC_DATA_READ) ++ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ ++ BUG_ON(sg_count != 1); ++ /* The data in SD card is little endian, ++ the SD controller is big endian */ ++ if ((data->flags & MMC_DATA_WRITE) == MMC_DATA_WRITE) { ++ unsigned char *buffer = sg_virt(data->sg); ++ unsigned char *buffer_tx = ++ (unsigned char *)host->dma_tx_buf; ++ int i; ++ /* Each sector is 512 Bytes, write 0x200 sectors */ ++ memset(host->dma_tx_buf, 0, ESDHC_DMA_SIZE); ++ for (i = 0; i < data->sg->length; i = i + 4) { ++ *(buffer_tx + i + 3) = *(buffer + i); ++ *(buffer_tx + i + 2) = *(buffer + i + 1); ++ *(buffer_tx + i + 1) = *(buffer + i + 2); ++ *(buffer_tx + i) = *(buffer + i + 3); ++ } ++ ++ fsl_writel(host->ioaddr + ESDHC_DMA_ADDRESS, ++ (unsigned long)host->dma_tx_dmahandle); ++ } else { ++ fsl_writel(host->ioaddr + ESDHC_DMA_ADDRESS, ++ sg_dma_address(data->sg) + host->offset); ++ } ++ ++ /* Disable the BRR and BWR interrupt */ ++ timeout = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE); ++ timeout = timeout & (~(ESDHC_INT_DATA_AVAIL | ++ ESDHC_INT_SPACE_AVAIL)); ++ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, timeout); ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE); ++ timeout = timeout & (~(ESDHC_INT_DATA_AVAIL | ++ ESDHC_INT_SPACE_AVAIL)); ++ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, timeout); ++ ++ wml_value = data->blksz / 4; ++ if (data->flags & MMC_DATA_READ) { ++ /* Read watermask level, max is 0x10*/ ++ if (wml_value > 0x10) ++ wml_value = 0x10; ++ wml = (wml_value & ESDHC_WML_MASK) | ++ ((0x10 & ESDHC_WML_MASK) ++ << ESDHC_WML_WRITE_SHIFT); ++ } else { ++ if (wml_value > 0x80) ++ wml_value = 0x80; ++ wml = (0x10 & ESDHC_WML_MASK) | ++ (((wml_value) & ESDHC_WML_MASK) ++ << ESDHC_WML_WRITE_SHIFT); ++ } ++ ++ fsl_writel(host->ioaddr + ESDHC_WML, wml); ++ } else { ++ unsigned long timeout; ++ ++ host->cur_sg = data->sg; ++ host->num_sg = data->sg_len; ++ ++ host->offset = 0; ++ host->remain = host->cur_sg->length; ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE); ++ timeout = timeout | ESDHC_INT_DATA_AVAIL ++ | ESDHC_INT_SPACE_AVAIL; ++ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, timeout); ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE); ++ timeout = timeout | ESDHC_INT_DATA_AVAIL ++ | ESDHC_INT_SPACE_AVAIL; ++ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, timeout); ++ } ++ ++ /* We do not handle DMA boundaries */ ++ blkattr = data->blksz; ++ blkattr |= (data->blocks << 16); ++ fsl_writel(host->ioaddr + ESDHC_BLOCK_ATTR, blkattr); ++ esdhc_dumpregs(host); ++} ++ ++static unsigned int esdhc_set_transfer_mode(struct esdhc_host *host, ++ struct mmc_data *data) ++{ ++ u32 mode = 0; ++ ++ WARN_ON(host->data); ++ ++ if (data == NULL) ++ return 0; ++ ++ mode = ESDHC_TRNS_BLK_CNT_EN; ++ if (data->blocks > 1) { ++ if (data->flags & MMC_DATA_READ) ++ mode |= ESDHC_TRNS_MULTI | ESDHC_TRNS_ACMD12; ++ else ++ mode |= ESDHC_TRNS_MULTI; ++ } ++ if (data->flags & MMC_DATA_READ) ++ mode |= ESDHC_TRNS_READ; ++ if (host->flags & ESDHC_USE_DMA) ++ mode |= ESDHC_TRNS_DMA; ++ ++ return mode; ++} ++ ++static void esdhc_finish_data(struct esdhc_host *host) ++{ ++ struct mmc_data *data; ++ u16 blocks; ++ ++ BUG_ON(!host->data); ++ ++ data = host->data; ++ host->data = NULL; ++ ++ if (host->flags & ESDHC_USE_DMA) { ++ unsigned char *buffer = sg_virt(data->sg); ++ unsigned char C0, C1, C2, C3; ++ int i; ++ /* Data in SD card is little endian, ++ SD controller is big endian */ ++ ++ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, ++ (data->flags & MMC_DATA_READ) ++ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ if (((data->flags & MMC_DATA_READ) == MMC_DATA_READ)) { ++ for (i = 0; i < data->sg->length; i = i + 4) { ++ C0 = *(buffer + host->offset + i); ++ C1 = *(buffer + host->offset + i + 1); ++ C2 = *(buffer + host->offset + i + 2); ++ C3 = *(buffer + host->offset + i + 3); ++ *(buffer+i) = C3; ++ *(buffer+i+1) = C2; ++ *(buffer+i+2) = C1; ++ *(buffer+i+3) = C0; ++ } ++ } ++ } ++ /* ++ * Controller doesn't count down when in single block mode. ++ */ ++ if ((data->blocks == 1) && (data->error == MMC_ERR_NONE)) ++ blocks = 0; ++ else { ++ blocks = fsl_readl(host->ioaddr + ESDHC_BLOCK_ATTR) >> 16; ++ blocks = 0; ++ if (data->flags & MMC_DATA_READ) ++ data->stop = 0; ++ } ++ ++ data->bytes_xfered = data->blksz * (data->blocks - blocks); ++ ++ if ((data->error == MMC_ERR_NONE) && blocks) { ++ printk(KERN_ERR"%s: Controller signaled completion even " ++ "though there were blocks left.\n", ++ mmc_hostname(host->mmc)); ++ data->error = MMC_ERR_FAILED; ++ } ++ ++ if ((blocks == 0) && (data->error & MMC_ERR_TIMEOUT)) { ++ printk(KERN_ERR "Controller transmitted completion even " ++ "though there was a timeout error.\n"); ++ data->error &= ~MMC_ERR_TIMEOUT; ++ } ++ ++ if (data->stop) { ++ DBG("%s data->stop %x\n", __func__, data->stop); ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if (data->error != MMC_ERR_NONE) { ++ printk("%s: The controller needs a " ++ "reset of internal state machines\n", ++ __func__); ++ esdhc_reset(host, ESDHC_RESET_CMD); ++ esdhc_reset(host, ESDHC_RESET_DATA); ++ reset_regs(host); ++ } ++ ++ esdhc_send_command(host, data->stop); ++ } else ++ tasklet_schedule(&host->finish_tasklet); ++} ++ ++static void esdhc_send_command(struct esdhc_host *host, struct mmc_command *cmd) ++{ ++ unsigned int flags; ++ u32 mask; ++ unsigned long timeout; ++ ++ WARN_ON(host->cmd); ++ ++ /* Wait max 10 ms */ ++ timeout = 10; ++ ++ mask = ESDHC_CMD_INHIBIT; ++ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) ++ mask |= ESDHC_DATA_INHIBIT; ++ ++ /* We shouldn't wait for data inihibit for stop commands, even ++ though they might use busy signaling */ ++ if (host->mrq->data && (cmd == host->mrq->data->stop)) ++ mask &= ~ESDHC_DATA_INHIBIT; ++ ++ while (fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) & mask) { ++ if (timeout == 0) { ++ printk(KERN_ERR "%s: Controller never released " ++ "inhibit bit(s).\n", mmc_hostname(host->mmc)); ++ esdhc_dumpregs(host); ++ cmd->error = MMC_ERR_FAILED; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ mod_timer(&host->timer, jiffies + 15 * HZ); ++ ++ host->cmd = cmd; ++ ++ esdhc_prepare_data(host, cmd->data); ++ ++ fsl_writel(host->ioaddr + ESDHC_ARGUMENT, cmd->arg); ++ ++ flags = esdhc_set_transfer_mode(host, cmd->data); ++ ++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { ++ printk(KERN_ERR "%s: Unsupported response type!\n", ++ mmc_hostname(host->mmc)); ++ cmd->error = MMC_ERR_INVALID; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (!(cmd->flags & MMC_RSP_PRESENT)) ++ flags |= ESDHC_CMD_RESP_NONE; ++ else if (cmd->flags & MMC_RSP_136) ++ flags |= ESDHC_CMD_RESP_LONG; ++ else if (cmd->flags & MMC_RSP_BUSY) ++ flags |= ESDHC_CMD_RESP_SHORT_BUSY; ++ else ++ flags |= ESDHC_CMD_RESP_SHORT; ++ ++ if (cmd->flags & MMC_RSP_CRC) ++ flags |= ESDHC_CMD_CRC_EN; ++ if (cmd->flags & MMC_RSP_OPCODE) ++ flags |= ESDHC_CMD_INDEX_EN; ++ if (cmd->data) ++ flags |= ESDHC_CMD_DATA; ++ ++ fsl_writel(host->ioaddr + ESDHC_COMMAND, ++ ESDHC_MAKE_CMD(cmd->opcode, flags)); ++} ++ ++static void esdhc_finish_command(struct esdhc_host *host) ++{ ++ int i; ++ ++ BUG_ON(host->cmd == NULL); ++ ++ if (host->cmd->flags & MMC_RSP_PRESENT) { ++ if (host->cmd->flags & MMC_RSP_136) { ++ /* CRC is stripped so we need to do some shifting. */ ++ for (i = 0; i < 4; i++) { ++ host->cmd->resp[i] = fsl_readl(host->ioaddr + ++ ESDHC_RESPONSE + (3-i)*4) << 8; ++ if (i != 3) ++ host->cmd->resp[i] |= ++ (fsl_readl(host->ioaddr ++ + ESDHC_RESPONSE ++ + (2-i)*4) >> 24); ++ } ++ } else ++ host->cmd->resp[0] = fsl_readl(host->ioaddr + ++ ESDHC_RESPONSE); ++ } ++ ++ host->cmd->error = MMC_ERR_NONE; ++ ++ if (host->cmd->data) ++ host->data = host->cmd->data; ++ else ++ tasklet_schedule(&host->finish_tasklet); ++ ++ host->cmd = NULL; ++} ++ ++#define MYCLOCK 1 ++static void esdhc_set_clock(struct esdhc_host *host, unsigned int clock) ++{ ++#if MYCLOCK ++ unsigned long sdrefclk, vco, bestmatch = -1, temp, diff; ++ int dvs, sdclkfs, outdiv; ++ int best_dvs, best_sdclkfs, best_outdiv; ++#else ++ int div, pre_div; ++ unsigned long sys_busclock = SYS_BUSCLOCK; ++#endif ++ unsigned long timeout; ++ u16 clk; ++ ++ DBG("esdhc_set_clock %x\n", clock); ++ if (clock == host->clock) ++ return; ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ timeout = timeout & (~ESDHC_CLOCK_MASK); ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout); ++ ++ if (clock == 0) ++ goto out; ++ ++#if MYCLOCK ++ /* TC: The VCO must obtain from u-boot */ ++ /* ++ * First set the outdiv3 to min 1, then walk through all to ++ * get closer value with SDCLKDIV and DIV combination ++ */ ++ vco = 500000000; ++ MCF_CLOCK_PLL_DR &= 0xFFFF83FF; /* Disable SD Clock */ ++ ++ for (outdiv = 2; outdiv <= 32; outdiv++) { ++ sdrefclk = vco / outdiv; ++ ++ for (sdclkfs = 2; sdclkfs < 257; sdclkfs <<= 1) { ++ for (dvs = 1; dvs < 17; dvs++) { ++ temp = sdrefclk / (sdclkfs * dvs); ++ ++ if (temp > clock) ++ diff = temp - clock; ++ else ++ diff = clock - temp; ++ ++ if (diff <= bestmatch) { ++ bestmatch = diff; ++ best_outdiv = outdiv; ++ best_sdclkfs = sdclkfs; ++ best_dvs = dvs; ++ ++ if (bestmatch == 0) ++ goto end; ++ } ++ } ++ } ++ } ++ ++end: ++#ifdef CONFIG_M5441X ++ best_outdiv = 3; ++ best_sdclkfs = 2; ++ best_dvs = 5; ++#endif ++ MCF_CLOCK_PLL_DR |= ((best_outdiv - 1) << 10); ++ clk = ((best_sdclkfs >> 1) << 8) | ((best_dvs - 1) << 4); ++#else ++ ++ if (sys_busclock / 16 > clock) { ++ for (pre_div = 1; pre_div < 256; pre_div *= 2) { ++ if ((sys_busclock / pre_div) < (clock*16)) ++ break; ++ } ++ } else ++ pre_div = 1; ++ ++ for (div = 1; div <= 16; div++) { ++ if ((sys_busclock / (div*pre_div)) <= clock) ++ break; ++ } ++ ++ pre_div >>= 1; ++ div -= 1; ++ ++ clk = (div << ESDHC_DIVIDER_SHIFT) | (pre_div << ESDHC_PREDIV_SHIFT); ++#endif ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ timeout = timeout | clk; ++ ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout); ++ ++ /* Wait max 10 ms */ ++ timeout = 10; ++ while (timeout) { ++ timeout--; ++ mdelay(1); ++ } ++ ++ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ timeout = timeout | ESDHC_CLOCK_CARD_EN; ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout); ++ ++ esdhc_dumpregs(host); ++ ++out: ++ host->clock = clock; ++ if (host->clock == 0) { ++ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL); ++ timeout = timeout | ESDHC_CLOCK_DEFAULT; ++ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout); ++ } ++} ++ ++static void esdhc_set_power(struct esdhc_host *host, unsigned short power) ++{ ++ if (host->power == power) ++ return; ++ ++ if (power == (unsigned short)-1) ++ host->power = power; ++} ++ ++/*****************************************************************************\ ++ * * ++ * MMC callbacks * ++ * * ++\*****************************************************************************/ ++ ++static void esdhc_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct esdhc_host *host; ++ unsigned long flags; ++ ++ DBG("esdhc_request\n"); ++ host = mmc_priv(mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ esdhc_send_command(host, mrq->cmd); ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void esdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct esdhc_host *host; ++ unsigned long flags; ++ u32 ctrl, irq_status_ena, irq_signal_ena; ++ ++ DBG("ios->power_mode %x, ios->bus_width %x\n", ++ ios->power_mode, ios->bus_width); ++ host = mmc_priv(mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ /* ++ * Reset the chip on each power off. ++ * Should clear out any weird states. ++ */ ++ ++ if (ios->power_mode == MMC_POWER_OFF) { ++ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, 0); ++ esdhc_init(host); ++ } ++ ++ esdhc_set_clock(host, ios->clock); ++ ++ if (ios->power_mode == MMC_POWER_OFF) ++ esdhc_set_power(host, -1); ++ else ++ esdhc_set_power(host, ios->vdd); ++ ++ ctrl = fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL); ++ ++ if (ios->bus_width == MMC_BUS_WIDTH_4) { ++ ctrl |= ESDHC_CTRL_4BITBUS; ++ host->bus_width = MMC_BUS_WIDTH_4; ++ ++ ctrl &= ~ESDHC_CTRL_D3_DETEC; ++ ++ /*when change the config of the CD, ++ * will involve card remove interrupt ++ * So try disable the card remove interrupt. ++ */ ++ irq_status_ena = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE); ++ irq_status_ena &= ~ESDHC_INT_CARD_REMOVE; ++ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, irq_status_ena); ++ ++ irq_signal_ena = fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE); ++ irq_signal_ena &= ~ESDHC_INT_CARD_REMOVE; ++ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, irq_signal_ena); ++ ++ DBG("host->card_insert = 0x%x\n", host->card_insert); ++ ++ ++ } else { ++ ctrl &= ~ESDHC_CTRL_4BITBUS; ++ host->bus_width = MMC_BUS_WIDTH_1; ++ } ++ ++ fsl_writel(host->ioaddr + ESDHC_PROTOCOL_CONTROL, ctrl); ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ esdhc_dumpregs(host); ++} ++ ++static int esdhc_get_ro(struct mmc_host *mmc) ++{ ++ return 0; ++} ++ ++static const struct mmc_host_ops esdhc_ops = { ++ .request = esdhc_request, ++ .set_ios = esdhc_set_ios, ++ .get_ro = esdhc_get_ro, ++}; ++ ++/*****************************************************************************\ ++ * * ++ * Tasklets * ++ * * ++\*****************************************************************************/ ++ ++static void esdhc_tasklet_card(unsigned long param) ++{ ++ struct esdhc_host *host; ++ ++ host = (struct esdhc_host *)param; ++ ++ spin_lock(&host->lock); ++ ++ DBG("esdhc_tasklet_card\n"); ++ if (!(fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) & ++ ESDHC_CARD_PRESENT)) { ++ if (host->mrq) { ++ printk(KERN_ERR "%s: Card removed during transfer!\n", ++ mmc_hostname(host->mmc)); ++ printk(KERN_ERR "%s: Resetting controller.\n", ++ mmc_hostname(host->mmc)); ++ ++ esdhc_reset(host, ESDHC_RESET_CMD); ++ esdhc_reset(host, ESDHC_RESET_DATA); ++ ++ host->mrq->cmd->error = MMC_ERR_FAILED; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ host->card_insert = 0; ++ } else { ++ esdhc_reset(host, ESDHC_INIT_CARD); ++ host->card_insert = 1; ++ } ++ ++ spin_unlock(&host->lock); ++ ++ mmc_detect_change(host->mmc, msecs_to_jiffies(500)); ++} ++ ++static void esdhc_tasklet_finish(unsigned long param) ++{ ++ struct esdhc_host *host; ++ unsigned long flags; ++ struct mmc_request *mrq; ++ ++ host = (struct esdhc_host *)param; ++ DBG("esdhc_tasklet_finish\n"); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ del_timer(&host->timer); ++ ++ mrq = host->mrq; ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if ((mrq->cmd->error != MMC_ERR_NONE) || ++ (mrq->data && ((mrq->data->error != MMC_ERR_NONE) || ++ (mrq->data->stop && ++ (mrq->data->stop->error != MMC_ERR_NONE))))) { ++ ++ /* Some controllers need this kick or reset won't work here */ ++ if (host->chip->quirks & ESDHC_QUIRK_CLOCK_BEFORE_RESET) { ++ unsigned int clock; ++ ++ /* This is to force an update */ ++ clock = host->clock; ++ host->clock = 0; ++ esdhc_set_clock(host, clock); ++ } ++ ++ if (mrq->cmd->error != MMC_ERR_TIMEOUT) { ++ esdhc_reset(host, ESDHC_RESET_CMD); ++ esdhc_reset(host, ESDHC_RESET_DATA); ++ reset_regs(host); ++ esdhc_dumpregs(host); ++ } ++ } ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ mmc_request_done(host->mmc, mrq); ++} ++ ++static void esdhc_timeout_timer(unsigned long data) ++{ ++ struct esdhc_host *host; ++ unsigned long flags; ++ ++ host = (struct esdhc_host *)data; ++ printk(KERN_INFO "esdhc_timeout_timer\n"); ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->mrq) { ++ if (host->data) { ++ host->data->error = MMC_ERR_TIMEOUT; ++ esdhc_finish_data(host); ++ } else { ++ if (host->cmd) ++ host->cmd->error = MMC_ERR_TIMEOUT; ++ else ++ host->mrq->cmd->error = MMC_ERR_TIMEOUT; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ } ++ ++ mmiowb(); ++ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, 0); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++/*****************************************************************************\ ++ * * ++ * Interrupt handling * ++ * * ++\*****************************************************************************/ ++ ++static void esdhc_cmd_irq(struct esdhc_host *host, u32 intmask) ++{ ++ BUG_ON(intmask == 0); ++ ++ if (!host->cmd) { ++ printk(KERN_ERR "%s: Got command interrupt even though no " ++ "command operation was in progress.\n", ++ mmc_hostname(host->mmc)); ++ esdhc_dumpregs(host); ++ return; ++ } ++ ++ if (intmask & ESDHC_INT_TIMEOUT) { ++ host->cmd->error = MMC_ERR_TIMEOUT; ++ DBG("esdhc_cmd_irq MMC_ERR_TIMEOUT\n"); ++ tasklet_schedule(&host->finish_tasklet); ++ } else if (intmask & ESDHC_INT_RESPONSE) ++ esdhc_finish_command(host); ++ else { ++ if (intmask & ESDHC_INT_CRC) ++ host->cmd->error = MMC_ERR_BADCRC; ++ else if (intmask & (ESDHC_INT_END_BIT | ESDHC_INT_INDEX)) ++ host->cmd->error = MMC_ERR_FAILED; ++ else ++ host->cmd->error = MMC_ERR_INVALID; ++ ++ tasklet_schedule(&host->finish_tasklet); ++ } ++} ++ ++static void esdhc_data_irq(struct esdhc_host *host, u32 intmask) ++{ ++ BUG_ON(intmask == 0); ++ if (!host->data) { ++ /* ++ * A data end interrupt is sent together with the response ++ * for the stop command. ++ */ ++ if ((intmask & ESDHC_INT_DATA_END) || ++ (intmask & ESDHC_INT_DMA_END)) { ++ return; ++ } ++ DBG("%s: Got data interrupt even though no " ++ "data operation was in progress.\n", ++ mmc_hostname(host->mmc)); ++ esdhc_dumpregs(host); ++ ++ return; ++ } ++ ++ if (intmask & ESDHC_INT_DATA_TIMEOUT) ++ host->data->error = MMC_ERR_TIMEOUT; ++ else if (intmask & ESDHC_INT_DATA_CRC) ++ host->data->error = MMC_ERR_BADCRC; ++ else if (intmask & ESDHC_INT_DATA_END_BIT) ++ host->data->error = MMC_ERR_FAILED; ++ ++ if (host->data->error != MMC_ERR_NONE) { ++ esdhc_finish_data(host); ++ } else { ++ if (intmask & (ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL)) ++ esdhc_transfer_pio(host); ++ /* ++ * We currently don't do anything fancy with DMA ++ * boundaries, but as we can't disable the feature ++ * we need to at least restart the transfer. ++ */ ++ if (intmask & ESDHC_INT_DMA_END) ++ fsl_writel(host->ioaddr + ESDHC_DMA_ADDRESS, ++ fsl_readl(host->ioaddr + ESDHC_DMA_ADDRESS)); ++ if (intmask & ESDHC_INT_DATA_END) ++ esdhc_finish_data(host); ++ } ++} ++ ++static irqreturn_t esdhc_detect_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result; ++ struct esdhc_host *host = dev_id; ++ u8 irq_status = 0; ++ ++ spin_lock(&host->lock); ++ ++ irq_status = MCF_EPORT_EPPDR & 0x2; ++ DBG("***Extern IRQ %x %x %x %x %x %x\n", MCF_EPORT_EPPAR, ++ MCF_EPORT_EPDDR, MCF_EPORT_EPDR, MCF_EPORT_EPFR, ++ MCF_EPORT_EPIER, MCF_EPORT_EPPDR); ++#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1) ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE1); ++#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7) ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7); ++#else ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7); ++#endif ++ if (irq_status == 0x0) { ++ DBG("*** Card insert interrupt Extern IRQ\n"); ++ esdhc_reset(host, ESDHC_INIT_CARD); ++ host->card_insert = 1; ++ } else /*irq_status == 0x2) */{ ++ DBG("*** Card removed interrupt Extern IRQ\n"); ++ if (host->mrq) { ++ printk(KERN_ERR "%s: Card removed during transfer!\n", ++ mmc_hostname(host->mmc)); ++ printk(KERN_ERR "%s: Resetting controller.\n", ++ mmc_hostname(host->mmc)); ++ ++ esdhc_reset(host, ESDHC_RESET_CMD); ++ esdhc_reset(host, ESDHC_RESET_DATA); ++ ++ host->mrq->cmd->error = MMC_ERR_FAILED; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ host->card_insert = 0; ++ } ++ ++ mmc_detect_change(host->mmc, msecs_to_jiffies(500)); ++#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1) ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1; ++ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF1; ++#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7) ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7; ++#else ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7; ++#endif ++ DBG("***Extern IRQ return %x %x %x %x %x %x\n", MCF_EPORT_EPPAR, ++ MCF_EPORT_EPDDR, MCF_EPORT_EPDR, MCF_EPORT_EPFR, ++ MCF_EPORT_EPIER, MCF_EPORT_EPPDR); ++ ++ result = IRQ_HANDLED; ++ spin_unlock(&host->lock); ++ ++ return result; ++} ++ ++static irqreturn_t esdhc_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result; ++ struct esdhc_host *host = dev_id; ++ u32 status; ++ ++ spin_lock(&host->lock); ++ ++ status = fsl_readl(host->ioaddr + ESDHC_INT_STATUS); ++ ++ if (!status || status == 0xffffffff) { ++ result = IRQ_NONE; ++ goto out; ++ } ++ ++ if (status & ESDHC_INT_CMD_MASK) { ++ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, ++ status & ESDHC_INT_CMD_MASK); ++ esdhc_cmd_irq(host, status & ESDHC_INT_CMD_MASK); ++ } ++ ++ if (status & ESDHC_INT_DATA_MASK) { ++ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, ++ status & ESDHC_INT_DATA_MASK); ++ esdhc_data_irq(host, status & ESDHC_INT_DATA_MASK); ++ } ++ ++ status &= ~(ESDHC_INT_CMD_MASK | ESDHC_INT_DATA_MASK); ++ ++ if (status) { ++ printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", ++ mmc_hostname(host->mmc), status); ++ esdhc_dumpregs(host); ++ ++ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, status); ++ } ++ ++ result = IRQ_HANDLED; ++ ++ mmiowb(); ++out: ++ spin_unlock(&host->lock); ++ ++ return result; ++} ++ ++/*****************************************************************************\ ++ * * ++ * Suspend/resume * ++ * * ++\*****************************************************************************/ ++ ++#ifdef CONFIG_PM ++ ++static int esdhc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct esdhc_chip *chip; ++ int i, ret; ++ ++ chip = platform_get_drvdata(pdev); ++ if (!chip) ++ return 0; ++ ++ DBG("Suspending..."); ++ ++ for (i = 0; i < chip->num_slots; i++) { ++ if (!chip->hosts[i]) ++ continue; ++ ret = mmc_suspend_host(chip->hosts[i]->mmc); ++ if (ret) { ++ for (i--; i >= 0; i--) ++ mmc_resume_host(chip->hosts[i]->mmc); ++ return ret; ++ } ++ } ++ ++ for (i = 0; i < chip->num_slots; i++) { ++ if (!chip->hosts[i]) ++ continue; ++ free_irq(chip->hosts[i]->irq, chip->hosts[i]); ++ } ++ ++ return 0; ++} ++ ++static int esdhc_resume(struct platform_device *pdev) ++{ ++ struct esdhc_chip *chip; ++ int i, ret; ++ ++ chip = platform_get_drvdata(pdev); ++ if (!chip) ++ return 0; ++ ++ DBG("Resuming..."); ++ ++ for (i = 0; i < chip->num_slots; i++) { ++ if (!chip->hosts[i]) ++ continue; ++ ret = request_irq(chip->hosts[i]->irq, esdhc_irq, ++ IRQF_SHARED, chip->hosts[i]->slot_descr, ++ chip->hosts[i]); ++ if (ret) ++ return ret; ++ esdhc_init(chip->hosts[i]); ++ mmiowb(); ++ ret = mmc_resume_host(chip->hosts[i]->mmc); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++#else ++ ++#define esdhc_suspend NULL ++#define esdhc_resume NULL ++ ++#endif ++ ++/*****************************************************************************\ ++ * * ++ * Device probing/removal * ++ * * ++\*****************************************************************************/ ++ ++static int esdhc_probe_slot(struct platform_device *pdev, int slot) ++{ ++ int ret; ++ unsigned int version; ++ struct esdhc_chip *chip; ++ struct mmc_host *mmc; ++ struct esdhc_host *host; ++ struct resource *res; ++ ++ unsigned int caps; ++ ++ chip = platform_get_drvdata(pdev); ++ BUG_ON(!chip); ++ ++ mmc = mmc_alloc_host(sizeof(struct esdhc_host), &(pdev->dev)); ++ if (!mmc) { ++ printk(KERN_ERR "%s mmc_alloc_host failed %x\n", ++ __func__, (unsigned int)mmc); ++ return -ENOMEM; ++ } ++ ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ ++ host->chip = chip; ++ chip->hosts[slot] = host; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ printk(KERN_ERR "%s platform_get_resource MEM failed %x\n", ++ __func__, (unsigned int)res); ++ goto free; ++ } ++ ++ host->addr = res->start; ++ host->size = res->end - res->start + 1; ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq <= 0) { ++ printk(KERN_ERR "%s platform_get_irq failed %x\n", ++ __func__, host->irq); ++ goto free; ++ } ++ ++ printk(KERN_INFO "slot %d at 0x%08lx, irq %d\n", ++ slot, host->addr, host->irq); ++ ++ snprintf(host->slot_descr, 20, "esdhc:slot%d", slot); ++ ++ ret = (int)request_mem_region(host->addr, host->size, DRIVER_NAME); ++ if (!ret) { ++ ret = -EBUSY; ++ printk(KERN_INFO "%s request_mem_region failed %x\n", ++ __func__, (unsigned int)res); ++ goto release; ++ } ++ ++ host->ioaddr = ioremap_nocache(host->addr, host->size); ++ if (!host->ioaddr) { ++ ret = -ENOMEM; ++ printk(KERN_INFO "%s ioremap_nocache failed %x\n", ++ __func__, (unsigned int)host->ioaddr); ++ goto release; ++ } ++ ++ esdhc_reset(host, ESDHC_RESET_ALL); ++ ++ version = fsl_readl(host->ioaddr + ESDHC_HOST_VERSION); ++ if ((version & 1) != 0x01) ++ printk(KERN_INFO "%s: Unknown controller version (%d). " ++ "You may experience problems.\n", host->slot_descr, ++ version); ++ ++ caps = fsl_readl(host->ioaddr + ESDHC_CAPABILITIES); ++ printk(KERN_INFO "%s caps %x %x\n", ++ __func__, caps, (unsigned int)MCF_ESDHC_HOSTCAPBLT); ++ ++#if defined(CONFIG_ESDHC_FORCE_PIO) ++ debug_nodma = 1; ++#endif ++ if (debug_nodma) ++ DBG("DMA forced off\n"); ++ else if (debug_forcedma) { ++ DBG("DMA forced on\n"); ++ host->flags |= ESDHC_USE_DMA; ++ } else if (chip->quirks & ESDHC_QUIRK_FORCE_DMA) { ++ DBG("Controller force DMA capability\n"); ++ host->flags |= ESDHC_USE_DMA; ++ } else if (!(caps & ESDHC_CAN_DO_DMA)) ++ DBG("Controller doesn't have DMA capability\n"); ++ else { ++ host->flags |= ESDHC_USE_DMA; ++ DBG("Controller have DMA capability\n"); ++ } ++ ++ /* ++ * Set host parameters. ++ */ ++#ifdef CONFIG_MPC5441X ++ host->max_clk = 17000000; ++#else ++ host->max_clk = 25000000; ++#endif ++ ++ /* if 4 bit , freq can be 50MHz */ ++ mmc->ops = &esdhc_ops; ++ mmc->f_min = 400000; ++ mmc->f_max = min((int)host->max_clk, 50000000); ++ ++ mmc->caps = MMC_CAP_4_BIT_DATA; ++ ++ mmc->ocr_avail = 0; ++ if (caps & ESDHC_CAN_VDD_330) ++ mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; ++ if (caps & ESDHC_CAN_VDD_300) ++ mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; ++ if (caps & ESDHC_CAN_VDD_180) ++ mmc->ocr_avail |= MMC_VDD_165_195; ++ ++ if (mmc->ocr_avail == 0) { ++ printk(KERN_INFO "%s: Hardware doesn't report any " ++ "support voltages.\n", host->slot_descr); ++ ret = -ENODEV; ++ goto unmap; ++ } ++ ++ spin_lock_init(&host->lock); ++ ++ /* ++ * Maximum number of segments. Hardware cannot do scatter lists. ++ */ ++ if (host->flags & ESDHC_USE_DMA) ++ mmc->max_segs = 1; ++ else ++ mmc->max_segs = 16; ++ ++ /* ++ * Maximum number of sectors in one transfer. Limited by DMA boundary ++ * size (512KiB). ++ */ ++ mmc->max_req_size = 524288; ++ ++ /* ++ * Maximum segment size. Could be one segment with the maximum number ++ * of bytes. ++ */ ++ mmc->max_seg_size = mmc->max_req_size; ++ ++ /* ++ * Maximum block size. This varies from controller to controller and ++ * is specified in the capabilities register. ++ */ ++ mmc->max_blk_size = (caps & ESDHC_MAX_BLOCK_MASK) >> ++ ESDHC_MAX_BLOCK_SHIFT; ++ if (mmc->max_blk_size > 3) { ++ printk(KERN_INFO "%s: Invalid maximum block size.\n", ++ host->slot_descr); ++ ret = -ENODEV; ++ goto unmap; ++ } ++ mmc->max_blk_size = 512 << mmc->max_blk_size; ++ ++ /* ++ * Maximum block count. ++ */ ++ mmc->max_blk_count = /*65535*/0x80; ++ ++ /* ++ * Init tasklets. ++ */ ++ tasklet_init(&host->card_tasklet, ++ esdhc_tasklet_card, (unsigned long)host); ++ tasklet_init(&host->finish_tasklet, ++ esdhc_tasklet_finish, (unsigned long)host); ++ ++ setup_timer(&host->timer, esdhc_timeout_timer, (unsigned long)host); ++ ++ esdhc_init(host); ++ ++ esdhc_dumpregs(host); ++ ++ ret = request_irq(host->irq, esdhc_irq, IRQF_DISABLED, ++ host->slot_descr, host); ++ if (ret) { ++ printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret); ++ goto untasklet; ++ } ++ ++ ret = request_irq(card_detect_extern_irq, ++ esdhc_detect_irq, IRQF_DISABLED, ++ host->slot_descr, host); ++ if (ret) { ++ printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret); ++ goto untasklet1; ++ } ++ ++ mmiowb(); ++ ++ ret = mmc_add_host(mmc); ++ if (ret) { ++ printk(KERN_INFO "%s: mmc_add_host fail %x\n", __func__, ret); ++ goto unaddhost; ++ } ++ ++ printk(KERN_INFO "%s: ESDHC at 0x%08lx irq %d %s\n", mmc_hostname(mmc), ++ host->addr, host->irq, ++ (host->flags & ESDHC_USE_DMA) ? "DMA" : "PIO"); ++ ++#ifdef ESDHC_DMA_KMALLOC ++ host->dma_tx_buf = kmalloc(ESDHC_DMA_SIZE, GFP_DMA); ++ host->dma_tx_dmahandle = virt_to_phys(host->dma_tx_buf); ++#else ++ host->dma_tx_buf = dma_alloc_coherent(NULL, ESDHC_DMA_SIZE, ++ &host->dma_tx_dmahandle, GFP_DMA|GFP_KERNEL); ++#endif ++ ++ if (((unsigned int)host->dma_tx_buf == 0) || ++ ((unsigned int)host->dma_tx_dmahandle == 0)) ++ printk(KERN_ERR "%s DMA alloc error\n", __func__); ++ ++ return 0; ++ ++unaddhost: ++ free_irq(card_detect_extern_irq, host); ++untasklet1: ++ free_irq(host->irq, host); ++untasklet: ++ tasklet_kill(&host->card_tasklet); ++ tasklet_kill(&host->finish_tasklet); ++unmap: ++ iounmap(host->ioaddr); ++release: ++ release_mem_region(host->addr, host->size); ++free: ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static void esdhc_remove_slot(struct platform_device *pdev, int slot) ++{ ++ struct esdhc_chip *chip; ++ struct mmc_host *mmc; ++ struct esdhc_host *host; ++ ++ chip = platform_get_drvdata(pdev); ++ host = chip->hosts[slot]; ++ mmc = host->mmc; ++ ++ chip->hosts[slot] = NULL; ++ ++ mmc_remove_host(mmc); ++ ++ esdhc_reset(host, ESDHC_RESET_ALL); ++ ++ free_irq(card_detect_extern_irq, host); ++ ++ free_irq(host->irq, host); ++ ++ del_timer_sync(&host->timer); ++ ++ tasklet_kill(&host->card_tasklet); ++ tasklet_kill(&host->finish_tasklet); ++ ++ iounmap(host->ioaddr); ++ ++ release_mem_region(host->addr, host->size); ++ ++ mmc_free_host(mmc); ++ DBG("%s: Exit....\n", __func__); ++} ++ ++static int __init esdhc_probe(struct platform_device *pdev) ++{ ++ int ret, i; ++ u8 slots; ++ struct esdhc_chip *chip; ++ ++ BUG_ON(pdev == NULL); ++ ++ /* Slew Rate */ ++ MCF_GPIO_SRCR_SDHC = 3; ++ MCF_GPIO_SRCR_IRQ0 = 3; ++ ++ /* Port Configuration */ ++ MCF_GPIO_PAR_ESDHCH = 0xFF; /* DAT[3:0] */ ++ MCF_GPIO_PAR_ESDHCL = 0x0F; /* CMD, CLK */ ++ ++ MCF_ESDHC_VSR = 2; /* disabled adma and set 3.0V */ ++ ++ MCF_INTC2_ICR31 = 2; /* SDHC irqstat */ ++#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1) ++ /*this is irq1 hardware work round*/ ++ MCF_GPIO_PAR_IRQ0H |= 0x3; ++ ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1; ++ ++ MCF_INTC0_ICR1 = 7; /* IRQ1 */ ++ DBG("MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x " ++ "MCF_EPORT_EPFR %x MCF_EPORT_EPIER %x " ++ "MCF_INTC0_IMRL %x MCF_INTC0_INTFRCL %x " ++ "MCF_INTC0_IPRL %x\n", ++ MCF_INTC0_ICR1, MCF_EPORT_EPPAR, MCF_EPORT_EPFR, ++ MCF_EPORT_EPIER, MCF_INTC0_IMRL, MCF_INTC0_INTFRCL, ++ MCF_INTC0_IPRL); ++#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7) ++ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7; ++ ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ ++ MCF_INTC0_ICR7 = 2; /* IRQ7 */ ++ DBG("MCF_INTC0_ICR7 %x MCF_EPORT_EPPAR %x\n", ++ MCF_INTC0_ICR7, MCF_EPORT_EPPAR); ++#else ++ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7; ++ ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ ++ MCF_INTC0_ICR7 = 2; /* IRQ7 */ ++ DBG("MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x\n", ++ MCF_INTC0_ICR7, MCF_EPORT_EPPAR); ++#endif ++ ++ slots = ESDHC_SLOTS_NUMBER; ++ DBG("found %d slot(s)\n", slots); ++ if (slots == 0) { ++ printk(KERN_INFO "%s: slot err %d\n", __func__, slots); ++ return -ENODEV; ++ } ++ ++ chip = kmalloc(sizeof(struct esdhc_chip) + ++ sizeof(struct esdhc_host *) * slots, GFP_KERNEL); ++ if (!chip) { ++ ret = -ENOMEM; ++ printk(KERN_ERR "%s: kmalloc fail %x\n", __func__, ++ (unsigned int)chip); ++ goto err; ++ } ++ ++ memset(chip, 0, ++ sizeof(struct esdhc_chip) + ++ sizeof(struct esdhc_host *) * slots); ++ ++ chip->pdev = pdev; ++ chip->quirks = ESDHC_QUIRK_NO_CARD_NO_RESET; ++ ++ if (debug_quirks) ++ chip->quirks = debug_quirks; ++ ++ chip->num_slots = slots; ++ platform_set_drvdata(pdev, chip); ++ ++ for (i = 0; i < slots; i++) { ++ ret = esdhc_probe_slot(pdev, i); ++ if (ret) { ++ for (i--; i >= 0; i--) ++ esdhc_remove_slot(pdev, i); ++ goto free; ++ } ++ } ++ ++ return 0; ++ ++free: ++ platform_set_drvdata(pdev, NULL); ++ kfree(chip); ++ ++err: ++ return ret; ++} ++ ++static int esdhc_remove(struct platform_device *pdev) ++{ ++ int i; ++ struct esdhc_chip *chip; ++ ++ chip = platform_get_drvdata(pdev); ++ ++ if (chip) { ++ for (i = 0; i < chip->num_slots; i++) ++ esdhc_remove_slot(pdev, i); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ kfree(chip); ++ } ++ ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++static struct platform_driver esdhc_driver = { ++ .probe = esdhc_probe, ++ .remove = esdhc_remove, ++ .suspend = esdhc_suspend, ++ .resume = esdhc_resume, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++/*****************************************************************************\ ++ * * ++ * Driver init/exit * ++ * * ++\*****************************************************************************/ ++ ++static int __init esdhc_drv_init(void) ++{ ++ printk(KERN_INFO DRIVER_NAME ++ ": Freescale Enhanced Secure Digital Host" ++ " Controller driver\n"); ++ ++ return platform_driver_register(&esdhc_driver); ++} ++ ++static void __exit esdhc_drv_exit(void) ++{ ++ printk(KERN_INFO DRIVER_NAME ++ ": Freescale Enhanced Secure Digital Host" ++ " Controller driver exit\n"); ++ platform_driver_unregister(&esdhc_driver); ++} ++ ++module_init(esdhc_drv_init); ++module_exit(esdhc_drv_exit); ++ ++module_param(debug_nodma, uint, 0444); ++module_param(debug_forcedma, uint, 0444); ++module_param(debug_quirks, uint, 0444); ++ ++MODULE_AUTHOR("Chenghu Wu<b16972@freescale.com>"); ++MODULE_DESCRIPTION("Enhanced Secure Digital Host Controller driver"); ++MODULE_LICENSE("GPL"); ++ ++MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers."); ++MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers."); ++MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); +--- /dev/null ++++ b/drivers/mmc/host/esdhc.h +@@ -0,0 +1,310 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Chenghu Wu <b16972@freescale.com> ++ * Xiaobo Xie <X.Xie@freescale.com> ++ * ++ * Based on mpc837x/driver/mmc/host/esdhc.c done by Xiaobo Xie ++ * Ported to Coldfire platform by Chenghu Wu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or (at ++ * your option) any later version. ++ */ ++#ifndef ESDHC_H ++#define ESDHC_H ++ ++#define MMC_ERR_NONE 0 ++#define MMC_ERR_TIMEOUT 1 ++#define MMC_ERR_BADCRC 2 ++#define MMC_ERR_FIFO 3 ++#define MMC_ERR_FAILED 4 ++#define MMC_ERR_INVALID 5 ++ ++#define MCF_CLOCK_PLL_DR (*(volatile unsigned long *)(0xFC0C0004)) ++#define MCF_ESDHC_HOSTCAPBLT (*(volatile unsigned long *)(0xFC0CC040)) ++#define MCF_ESDHC_ADMAESR (*(volatile unsigned long *)(0xFC0CC054)) ++#define MCF_ESDHC_ADMASAR (*(volatile unsigned long *)(0xFC0CC058)) ++#define MCF_ESDHC_VSR (*(volatile unsigned long *)(0xFC0CC0C0)) ++#define MCF_ESDHC_HOSTVER (*(volatile unsigned long *)(0xFC0CC0FC)) ++/* ++ * Controller registers (Big Endian) ++ */ ++ ++#define MCF_GPIO_PAR_SDHC_DATA3 0x20 ++#define MCF_GPIO_PAR_SDHC_DATA2 0x10 ++#define MCF_GPIO_PAR_SDHC_DATA1 0x08 ++#define MCF_GPIO_PAR_SDHC_DATA0 0x04 ++#define MCF_GPIO_PAR_SDHC_CMD 0x02 ++#define MCF_GPIO_PAR_SDHC_CLK 0x01 ++ ++ ++#define MCF_GPIO_SRCR_SDHC_LOWEST 0x00 ++#define MCF_GPIO_SRCR_SDHC_LOWE 0x01 ++#define MCF_GPIO_SRCR_SDHC_HIGH 0x02 ++#define MCF_GPIO_SRCR_SDHC_HIGHEST 0x03 ++ ++ ++#define MCF_GPIO_PCRL_SDHC_DATA3 0x80 ++#define MCF_GPIO_PCRL_SDHC_DATA2 0x40 ++#define MCF_GPIO_PCRL_SDHC_DATA1 0x20 ++#define MCF_GPIO_PCRL_SDHC_DATA0 0x10 ++#define MCF_GPIO_PCRL_SDHC_CMD 0x08 ++#define MCF_GPIO_PCRL_SDHC_CLK 0x04 ++ ++#define MCF_INT_SDHC 63 ++/* DMA System Address Register */ ++#define ESDHC_DMA_ADDRESS 0x00 ++ ++/* Block Attributes Register */ ++#define ESDHC_BLOCK_ATTR 0x04 ++#define ESDHC_BLOCK_SIZE_MASK 0x00000fff ++#define ESDHC_BLCOK_CNT_MASK 0xffff0000 ++#define ESDHC_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) ++ ++/* Command Argument */ ++#define ESDHC_ARGUMENT 0x08 ++ ++/* Transfer Type Register */ ++#define ESDHC_COMMAND 0x0C ++ ++#define ESDHC_TRNS_DMA 0x00000001 ++#define ESDHC_TRNS_BLK_CNT_EN 0x00000002 ++#define ESDHC_TRNS_ACMD12 0x00000004 ++#define ESDHC_TRNS_READ 0x00000010 ++#define ESDHC_TRNS_MULTI 0x00000020 ++ ++#define ESDHC_CMD_RESP_MASK 0x00030000 ++#define ESDHC_CMD_CRC_EN 0x00080000 ++#define ESDHC_CMD_INDEX_EN 0x00100000 ++#define ESDHC_CMD_DATA 0x00200000 ++#define ESDHC_CMD_TYPE_MASK 0x00c00000 ++#define ESDHC_CMD_INDEX 0x3f000000 ++ ++#define ESDHC_CMD_RESP_NONE 0x00000000 ++#define ESDHC_CMD_RESP_LONG 0x00010000 ++#define ESDHC_CMD_RESP_SHORT 0x00020000 ++#define ESDHC_CMD_RESP_SHORT_BUSY 0x00030000 ++ ++#define ESDHC_MAKE_CMD(c, f) (((c & 0xff) << 24) | (f & 0xfb0037)) ++ ++/* Response Register */ ++#define ESDHC_RESPONSE 0x10 ++ ++/* Buffer Data Port Register */ ++#define ESDHC_BUFFER 0x20 ++ ++/* Present State Register */ ++#define ESDHC_PRESENT_STATE 0x24 ++#define ESDHC_CMD_INHIBIT 0x00000001 ++#define ESDHC_DATA_INHIBIT 0x00000002 ++#define ESDHC_DOING_WRITE 0x00000100 ++#define ESDHC_DOING_READ 0x00000200 ++#define ESDHC_SPACE_AVAILABLE 0x00000400 ++#define ESDHC_DATA_AVAILABLE 0x00000800 ++#define ESDHC_CARD_PRESENT 0x00010000 ++#define ESDHC_WRITE_PROTECT 0x00080000 ++ ++/* Protocol control Register */ ++#define ESDHC_PROTOCOL_CONTROL 0x28 ++ ++#define ESDHC_CTRL_BUS_MASK 0x00000006 ++#define ESDHC_CTRL_4BITBUS 0x00000002 ++#define ESDHC_CTRL_D3_DETEC 0x00000008 ++#define ESDHC_CTRL_DTCT_EN 0x00000080 ++#define ESDHC_CTRL_DTCT_STATUS 0x00000040 ++#define ESDHC_CTRL_WU_CRM 0x04000000 ++#define ESDHC_CTRL_WU_CINS 0x02000000 ++#define ESDHC_CTRL_WU_CINT 0x01000000 ++ ++/* System Control Register */ ++#define ESDHC_SYSTEM_CONTROL 0x2C ++ ++#define ESDHC_CLOCK_MASK 0x0000fff0 ++#define ESDHC_CLOCK_DEFAULT 0x00008000 ++#define ESDHC_PREDIV_SHIFT 8 ++#define ESDHC_DIVIDER_SHIFT 4 ++#define ESDHC_CLOCK_CARD_EN 0x00000004 ++#define ESDHC_CLOCK_INT_STABLE 0x00000002 ++#define ESDHC_CLOCK_INT_EN 0x00000001 ++ ++#define ESDHC_TIMEOUT_MASK 0x000f0000 ++#define ESDHC_TIMEOUT_SHIFT 16 ++ ++#define ESDHC_RESET_SHIFT 24 ++#define ESDHC_RESET_ALL 0x01 ++#define ESDHC_RESET_CMD 0x02 ++#define ESDHC_RESET_DATA 0x04 ++#define ESDHC_INIT_CARD 0x08 ++ ++/* Interrupt Register */ ++#define ESDHC_INT_STATUS 0x30 ++#define ESDHC_INT_ENABLE 0x34 ++#define ESDHC_SIGNAL_ENABLE 0x38 ++ ++#define ESDHC_INT_RESPONSE 0x00000001 ++#define ESDHC_INT_DATA_END 0x00000002 ++#define ESDHC_INT_DMA_END 0x00000008 ++#define ESDHC_INT_SPACE_AVAIL 0x00000010 ++#define ESDHC_INT_DATA_AVAIL 0x00000020 ++#define ESDHC_INT_CARD_INSERT 0x00000040 ++#define ESDHC_INT_CARD_REMOVE 0x00000080 ++#define ESDHC_INT_CARD_INT 0x00000100 ++ ++#define ESDHC_INT_TIMEOUT 0x00010000 ++#define ESDHC_INT_CRC 0x00020000 ++#define ESDHC_INT_END_BIT 0x00040000 ++#define ESDHC_INT_INDEX 0x00080000 ++#define ESDHC_INT_DATA_TIMEOUT 0x00100000 ++#define ESDHC_INT_DATA_CRC 0x00200000 ++#define ESDHC_INT_DATA_END_BIT 0x00400000 ++#define ESDHC_INT_ACMD12ERR 0x01000000 ++#define ESDHC_INT_DMAERR 0x10000000 ++ ++#define ESDHC_INT_NORMAL_MASK 0x00007FFF ++#define ESDHC_INT_ERROR_MASK 0xFFFF8000 ++ ++#define ESDHC_INT_CMD_MASK (ESDHC_INT_RESPONSE | ESDHC_INT_TIMEOUT | \ ++ ESDHC_INT_CRC | ESDHC_INT_END_BIT | ESDHC_INT_INDEX) ++#define ESDHC_INT_DATA_MASK (ESDHC_INT_DATA_END | ESDHC_INT_DMA_END | \ ++ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | \ ++ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_DATA_CRC | \ ++ ESDHC_INT_DATA_END_BIT) ++ ++#define ESDHC_INT_INSERT_MASK (ESDHC_INT_DATA_END_BIT | ESDHC_INT_DATA_CRC | \ ++ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_INDEX | \ ++ ESDHC_INT_END_BIT | ESDHC_INT_CRC | ESDHC_INT_TIMEOUT | \ ++ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | \ ++ ESDHC_INT_DMA_END | ESDHC_INT_DATA_END | \ ++ ESDHC_INT_RESPONSE | ESDHC_INT_CARD_REMOVE) ++ ++#define ESDHC_INT_REMOVE_MASK (ESDHC_INT_DATA_END_BIT | ESDHC_INT_DATA_CRC | \ ++ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_INDEX | \ ++ ESDHC_INT_END_BIT | ESDHC_INT_CRC | ESDHC_INT_TIMEOUT | \ ++ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | \ ++ ESDHC_INT_DMA_END | ESDHC_INT_DATA_END | \ ++ ESDHC_INT_RESPONSE | ESDHC_INT_CARD_INSERT) ++ ++/* Auto CMD12 Error Status Register */ ++#define ESDHC_ACMD12_ERR 0x3C ++ ++/* 3E-3F reserved */ ++/* Host Controller Capabilities */ ++#define ESDHC_CAPABILITIES 0x40 ++ ++#define ESDHC_MAX_BLOCK_MASK 0x00070000 ++#define ESDHC_MAX_BLOCK_SHIFT 16 ++#define ESDHC_CAN_DO_HISPD 0x00200000 ++#define ESDHC_CAN_DO_DMA 0x00400000 ++#define ESDHC_CAN_DO_SUSPEND 0x00800000 ++#define ESDHC_CAN_VDD_330 0x01000000 ++#define ESDHC_CAN_VDD_300 0x02000000 ++#define ESDHC_CAN_VDD_180 0x04000000 ++ ++/* Watermark Level Register */ ++#define ESDHC_WML 0x44 ++#define ESDHC_WML_MASK 0xff ++#define ESDHC_WML_READ_SHIFT 0 ++#define ESDHC_WML_WRITE_SHIFT 16 ++ ++/* 45-4F reserved for more caps and max curren*/ ++ ++/* Force Event Register */ ++#define ESDHC_FORCE_EVENT 0x50 ++ ++/* 54-FB reserved */ ++ ++/* Host Controller Version Register */ ++#define ESDHC_HOST_VERSION 0xFC ++ ++#define ESDHC_VENDOR_VER_MASK 0xFF00 ++#define ESDHC_VENDOR_VER_SHIFT 8 ++#define ESDHC_SPEC_VER_MASK 0x00FF ++#define ESDHC_SPEC_VER_SHIFT 0 ++ ++#define ESDHC_DMA_SYSCTL 0x40C ++#define ESDHC_DMA_SNOOP 0x00000040 ++ ++#define ESDHC_SLOTS_NUMBER 1 ++ ++/* The SCCR[SDHCCM] Register */ ++#define MPC837X_SCCR_OFFS 0xA08 ++#define MPC837X_SDHCCM_MASK 0x0c000000 ++#define MPC837X_SDHCCM_SHIFT 26 ++ ++#define esdhc_readl(addr) \ ++ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) ++ ++#define esdhc_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) ++ ++static inline u32 fsl_readl(unsigned __iomem *addr) ++{ ++ u32 val; ++ /*val = inl(addr);*/ ++ val = esdhc_readl(addr); ++ return val; ++} ++ ++static inline void fsl_writel(unsigned __iomem *addr, u32 val) ++{ ++ /*outl(val, addr);*/ ++ esdhc_writel(val, addr); ++} ++ ++#define setbits32(_addr, _v) outl((_addr), inl(_addr) | (_v)) ++#define clrbits32(_addr, _v) outl((_addr), inl(_addr) & ~(_v)) ++ ++struct esdhc_chip; ++ ++struct esdhc_host { ++ struct esdhc_chip *chip; ++ struct mmc_host *mmc; /* MMC structure */ ++ ++ spinlock_t lock; /* Mutex */ ++ ++ int flags; /* Host attributes */ ++#define ESDHC_USE_DMA (1<<0) ++ ++ unsigned int max_clk; /* Max possible freq (MHz) */ ++ unsigned int timeout_clk; /* Timeout freq (KHz) */ ++ ++ unsigned int clock; /* Current clock (MHz) */ ++ unsigned short power; /* Current voltage */ ++ unsigned short bus_width; /* current bus width */ ++ ++ struct mmc_request *mrq; /* Current request */ ++ struct mmc_command *cmd; /* Current command */ ++ struct mmc_data *data; /* Current data request */ ++ ++ struct scatterlist *cur_sg; /* We're working on this */ ++ int num_sg; /* Entries left */ ++ int offset; /* Offset into current sg */ ++ int remain; /* Bytes left in current */ ++ ++ char slot_descr[20]; /* Name for reservations */ ++ ++ int card_insert; ++ ++ int irq; /* Device IRQ */ ++ unsigned long addr; /* Bus address */ ++ unsigned int size; /* IO size */ ++ void __iomem *ioaddr; /* Mapped address */ ++ ++ struct tasklet_struct card_tasklet; /* Tasklet structures */ ++ struct tasklet_struct finish_tasklet; ++ ++ struct timer_list timer; /* Timer for timeouts */ ++ void *dma_tx_buf; ++ dma_addr_t dma_tx_dmahandle; ++}; ++ ++struct esdhc_chip { ++ struct platform_device *pdev; ++ ++ unsigned long quirks; ++ ++ int num_slots; /* Slots on controller */ ++ struct esdhc_host *hosts[0]; /* Pointers to hosts */ ++}; ++ ++#endif diff --git a/target/linux/coldfire/patches/030-Add-SPI-device-configuration-for-FXS-and-FXO-on-MCF5.patch b/target/linux/coldfire/patches/030-Add-SPI-device-configuration-for-FXS-and-FXO-on-MCF5.patch new file mode 100644 index 000000000..0f4e843e2 --- /dev/null +++ b/target/linux/coldfire/patches/030-Add-SPI-device-configuration-for-FXS-and-FXO-on-MCF5.patch @@ -0,0 +1,38 @@ +From 2a73218ebe0bdca04cc9299da50d7f079ca46a7d Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:47 +0800 +Subject: [PATCH 30/52] Add SPI device configuration for FXS and FXO on MCF54451 platform + +Add SPI device configuration for FXS and FXO on MCF54451 platform. +So FXS and FXO drivers can use SPI subsystem interfaces for the SPI +read and write operations. So as to fix the confliction between FXO/FXS +with other SPI devices. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/spi/Kconfig | 14 ++++++++++++++ + 1 files changed, 14 insertions(+), 0 deletions(-) + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -189,6 +189,20 @@ config SPI_COLDFIRE_DSPI_EDMA + help + Say "yes" if you want DSPI master driver to use eDMA for transfers. + ++config VOIP_FXS ++ boolean "Coldfire VoIP FXS driver" ++ depends on M54451 && SPI_MASTER && SPI_DSPI ++ default n ++ help ++ Say "yes" if you want VoIP FXS driver to use DSPI for transfers. ++ ++config VOIP_FXO ++ boolean "Coldfire VoIP FXO driver" ++ depends on M54451 && SPI_MASTER && SPI_DSPI ++ default n ++ help ++ Say "yes" if you want VoIP FXO driver to use DSPI for transfers. ++ + config SPI_IMX_VER_IMX1 + def_bool y if SOC_IMX1 + diff --git a/target/linux/coldfire/patches/031-Add-watchdog-driver-support-for-MCF5445x-and-MCF547x.patch b/target/linux/coldfire/patches/031-Add-watchdog-driver-support-for-MCF5445x-and-MCF547x.patch new file mode 100644 index 000000000..5362aa333 --- /dev/null +++ b/target/linux/coldfire/patches/031-Add-watchdog-driver-support-for-MCF5445x-and-MCF547x.patch @@ -0,0 +1,338 @@ +From 42bf8a598049f6cb3c90b1f28a2f1b8daebe3de8 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:47 +0800 +Subject: [PATCH 31/52] Add watchdog driver support for MCF5445x and MCF547x/MCF548x + +Add watchdog driver support for MCF5445x and MCF547x/MCF548x. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/watchdog/Kconfig | 9 ++ + drivers/watchdog/Makefile | 1 + + drivers/watchdog/mcf_wdt.c | 292 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 302 insertions(+), 0 deletions(-) + create mode 100644 drivers/watchdog/mcf_wdt.c + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -974,6 +974,15 @@ config BCM63XX_WDT + + # PARISC Architecture + ++# ColdFire Architecture ++ ++config COLDFIRE_WATCHDOG ++ tristate "ColdFire watchdog support" ++ depends on M547X_8X || M5445X || M5441X ++ help ++ To compile this driver as a module, choose M here: the ++ module will be called softdog. ++ + # POWERPC Architecture + + config GEF_WDT +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -107,6 +107,7 @@ obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc + + # M68K Architecture + obj-$(CONFIG_M54xx_WATCHDOG) += m54xx_wdt.o ++obj-$(CONFIG_COLDFIRE_WATCHDOG) += mcf_wdt.o + + # MIPS Architecture + obj-$(CONFIG_ATH79_WDT) += ath79_wdt.o +--- /dev/null ++++ b/drivers/watchdog/mcf_wdt.c +@@ -0,0 +1,292 @@ ++/* ++ * drivers/watchdog/mcf_wdt.c ++ * ++ * Watchdog driver for ColdFire processors ++ * ++ * Copyright (C) 2006-2007, 2009-2011 Freescale Semiconductor, Inc. ++ * All Rights Reserved. ++ * ++ * Author: Shrek Wu<B16972@freesale.com> ++ * ChengJu Cai<B22600@freesale.com> ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/types.h> ++#include <linux/kernel.h> ++#include <linux/fs.h> ++#include <linux/miscdevice.h> ++#include <linux/watchdog.h> ++#include <linux/init.h> ++#include <linux/bitops.h> ++ ++#include <linux/uaccess.h> ++#include <asm/coldfire.h> ++#include <asm/mcfsim.h> ++ ++static int nowayout; ++static unsigned int heartbeat = MCF_GPT_MAX_TIMEOUT; ++static unsigned long wdt_status; ++ ++#define WDT_IN_USE 0 ++#define WDT_OK_TO_CLOSE 1 ++ ++static unsigned long wdt_tick_rate; ++ ++#ifdef CONFIG_M547X_8X ++static int ++wdt_enable(int time) ++{ ++ if (time > 30 || time < 1) ++ return -EINVAL; ++ ++ heartbeat = time; ++ ++ MCF_GPT_GMS0 = 0; ++ MCF_GPT_GCIR0 = MCF_GPT_GCIR_PRE(heartbeat * wdt_tick_rate) | ++ MCF_GPT_GCIR_CNT(0xffff); ++ MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | ++ MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS_GPIO; ++ ++ return 0; ++} ++ ++static void ++wdt_disable(void) ++{ ++ MCF_GPT_GMS0 = 0; ++} ++ ++static void ++wdt_keepalive(void) ++{ ++ MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS0; ++} ++ ++#elif defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ ++/* Enable watchdog and set time-out */ ++static int ++wdt_enable(int time) ++{ ++ unsigned int sign = 0x01 << 31; ++ int i = 0, timeout_n = 31; ++ int max_timeout = sign / MCF_BUSCLK; ++ unsigned int count; ++ ++ if (time > max_timeout || time < 1) ++ return -EINVAL; ++ ++ count = time * MCF_BUSCLK; ++ ++ for (i = 0; i < 31; i++) { ++ if (count & (sign >> i)) { ++ if ((count & (~(sign >> i))) == 0) ++ timeout_n = 31 - i; ++ else ++ timeout_n = 31 - i + 1; ++ break; ++ } ++ } ++ ++ heartbeat = (unsigned int)(0x01 << timeout_n) / MCF_BUSCLK; ++ ++ MCF_SCM_CWCR = MCF_SCM_CWCR_CWE ++ | MCF_SCM_CWCR_CWRI(0x02) ++ | MCF_SCM_CWCR_CWT(timeout_n); ++ ++ return 0; ++} ++ ++/* Disable the watchdog */ ++static void ++wdt_disable(void) ++{ ++ MCF_SCM_CWCR = 0x00; ++} ++ ++/* Reset the watchdog timer counter */ ++static void ++wdt_keepalive(void) ++{ ++ MCF_SCM_CWSR = 0x55; ++ MCF_SCM_CWSR = 0xAA; ++} ++#endif ++ ++static int ++mcf_wdt_open(struct inode *inode, struct file *file) ++{ ++ int ret; ++ if (test_and_set_bit(WDT_IN_USE, &wdt_status)) ++ return -EBUSY; ++ ++ clear_bit(WDT_OK_TO_CLOSE, &wdt_status); ++ ++ ret = wdt_enable(heartbeat); ++ if (ret) ++ return ret; ++ ++ return nonseekable_open(inode, file); ++} ++ ++static ssize_t ++mcf_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) ++{ ++ if (len) { ++ if (!nowayout) { ++ size_t i; ++ ++ clear_bit(WDT_OK_TO_CLOSE, &wdt_status); ++ ++ for (i = 0; i != len; i++) { ++ char c; ++ ++ if (get_user(c, data + i)) ++ return -EFAULT; ++ if (c == 'V') ++ set_bit(WDT_OK_TO_CLOSE, &wdt_status); ++ } ++ } ++ wdt_keepalive(); ++ } ++ ++ return len; ++} ++ ++ ++static struct watchdog_info ident = { ++ .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | ++ WDIOF_KEEPALIVEPING, ++ .identity = "Coldfire Watchdog", ++}; ++ ++static long ++mcf_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long __user arg) ++{ ++ long ret = -ENOIOCTLCMD; ++ int time = 0; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info *)arg, &ident, ++ sizeof(ident)) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_GETSTATUS: ++ ret = put_user(0, (int *)arg); ++ break; ++ ++ case WDIOC_GETBOOTSTATUS: ++ ret = put_user(0, (int *)arg); ++ break; ++ ++ case WDIOC_SETTIMEOUT: ++ ret = get_user(time, (int *)arg); ++ if (ret) ++ break; ++ ++ ret = wdt_enable(time); ++ if (ret) ++ break; ++ ret = put_user(heartbeat, (int *)arg); ++ break; ++ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(heartbeat, (int *)arg); ++ break; ++ ++ case WDIOC_KEEPALIVE: ++ wdt_keepalive(); ++ ret = 0; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int ++mcf_wdt_release(struct inode *inode, struct file *file) ++{ ++ if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) { ++#ifdef CONFIG_M547X_8X ++ MCF_GPT_GCIR0 = (0x0A << 16) | 0x09; ++ MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS0; ++#else ++ wdt_keepalive(); ++#endif ++ } else { ++ printk(KERN_CRIT "WATCHDOG: Device closed unexpectdly\n"); ++ wdt_disable(); ++ } ++ ++ clear_bit(WDT_IN_USE, &wdt_status); ++ clear_bit(WDT_OK_TO_CLOSE, &wdt_status); ++ ++#ifdef CONFIG_M547X_8X ++ /*disable the XLB priority, otherwise the watchdog reset may fail*/ ++ MCF_XARB_PRIEN = 0; ++ /* Also disable the PCI, Ugly! But there is issue between PCI and ++ * watchdog. Otherwise the watchdog reset may fail, only valuable ++ * for testing! ++ */ ++ MCF_SPCR &= ~0x02; ++ asm("tpf"); ++#endif ++ ++ return 0; ++} ++ ++ ++static const struct file_operations mcf_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = mcf_wdt_write, ++ .unlocked_ioctl = mcf_wdt_ioctl, ++ .open = mcf_wdt_open, ++ .release = mcf_wdt_release, ++}; ++ ++static struct miscdevice mcf_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &mcf_wdt_fops, ++}; ++ ++static int __init mcf_wdt_init(void) ++{ ++ wdt_tick_rate = MCF_BUSCLK/0xffff; ++#ifdef CONFIG_WATCHDOG_NOWAYOUT ++ nowayout = 1; ++#else ++ nowayout = 0; ++#endif ++ printk(KERN_INFO "ColdFire watchdog driver is loaded.\n"); ++ ++ return misc_register(&mcf_wdt_miscdev); ++} ++ ++static void __exit mcf_wdt_exit(void) ++{ ++ misc_deregister(&mcf_wdt_miscdev); ++} ++ ++module_init(mcf_wdt_init); ++module_exit(mcf_wdt_exit); ++ ++MODULE_AUTHOR("Deepak Saxena"); ++MODULE_DESCRIPTION("ColdFire Watchdog"); ++ ++module_param(heartbeat, int, 0); ++MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds (default 60s)"); ++ ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); ++ ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++ diff --git a/target/linux/coldfire/patches/032-Change-some-jffs2-warning-to-debug-info.patch b/target/linux/coldfire/patches/032-Change-some-jffs2-warning-to-debug-info.patch new file mode 100644 index 000000000..3d1eabc23 --- /dev/null +++ b/target/linux/coldfire/patches/032-Change-some-jffs2-warning-to-debug-info.patch @@ -0,0 +1,33 @@ +From 8834b24adf7efc8a50fcbc153910276b355fb4e9 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:47 +0800 +Subject: [PATCH 32/52] Change some jffs2 warning to debug info + +As the NFC issue, the jffs2 verify buf may fail sometimes. +This patch move this kind of warning to debug information. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + fs/jffs2/wbuf.c | 8 ++++---- + 1 files changed, 4 insertions(+), 4 deletions(-) + +--- a/fs/jffs2/wbuf.c ++++ b/fs/jffs2/wbuf.c +@@ -246,13 +246,13 @@ static int jffs2_verify_write(struct jff + else + eccstr = "OK or unused"; + +- printk(KERN_WARNING "Write verify error (ECC %s) at %08x. Wrote:\n", ++ printk(KERN_DEBUG "Write verify error (ECC %s) at %08x. Wrote:\n", + eccstr, c->wbuf_ofs); +- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, ++ print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, + c->wbuf, c->wbuf_pagesize, 0); + +- printk(KERN_WARNING "Read back:\n"); +- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, ++ printk(KERN_DEBUG "Read back:\n"); ++ print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, + c->wbuf_verify, c->wbuf_pagesize, 0); + + return -EIO; diff --git a/target/linux/coldfire/patches/033-Fix-structure-fsl_ssd1289_data-definition-bug-for-SS.patch b/target/linux/coldfire/patches/033-Fix-structure-fsl_ssd1289_data-definition-bug-for-SS.patch new file mode 100644 index 000000000..1d1f67705 --- /dev/null +++ b/target/linux/coldfire/patches/033-Fix-structure-fsl_ssd1289_data-definition-bug-for-SS.patch @@ -0,0 +1,49 @@ +From 1ebacc69cb9b9c2508b1e75cb23ef572cda51eec Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:47 +0800 +Subject: [PATCH 33/52] Fix structure fsl_ssd1289_data definition bug for SSD1289 FB driver + +Fix the bug that structure fsl_ssd1289_data definition depends on +DSPI enabled for SSD1289 framebuffer driver. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5441x/devices.c | 20 ++++++++++---------- + 1 files changed, 10 insertions(+), 10 deletions(-) + +--- a/arch/m68k/coldfire/m5441x/devices.c ++++ b/arch/m68k/coldfire/m5441x/devices.c +@@ -138,6 +138,16 @@ static struct platform_device nfc_device + }; + #endif + ++#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE) ++static struct fsl_ssd1289_fb_display fsl_ssd1289_data = { ++ .width = 320, ++ .height = 240, ++ .xres = 320, ++ .yres = 240, ++ .bpp = 16, ++}; ++#endif ++ + /* + * DSPI + */ +@@ -197,16 +207,6 @@ static struct coldfire_dspi_chip at26df0 + }; + #endif + +-#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE) +-static struct fsl_ssd1289_fb_display fsl_ssd1289_data = { +- .width = 320, +- .height = 240, +- .xres = 320, +- .yres = 240, +- .bpp = 16, +-}; +-#endif +- + #if defined(CONFIG_SSD1289_SPI_MODE) + static struct coldfire_dspi_chip ssd1289_chip_info = { + .mode = SPI_MODE_0, diff --git a/target/linux/coldfire/patches/034-Enable-the-NFC-driver-for-soft_ecc.patch b/target/linux/coldfire/patches/034-Enable-the-NFC-driver-for-soft_ecc.patch new file mode 100644 index 000000000..f1f1c5944 --- /dev/null +++ b/target/linux/coldfire/patches/034-Enable-the-NFC-driver-for-soft_ecc.patch @@ -0,0 +1,50 @@ +From 25ebef8c87221774de01d1f1de4fb615fcfc6b54 Mon Sep 17 00:00:00 2001 +From: Jason Jin <Jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 09:59:47 +0800 +Subject: [PATCH 34/52] Enable the NFC driver for soft_ecc. + +If enabled YAFFS2 support, soft ecc should be used for the +nand flash driver. + +Signed-off-by: Jason Jin <Jason.jin@freescale.com> +--- + drivers/mtd/nand/Kconfig | 6 ++++++ + drivers/mtd/nand/fsl_nfc.c | 12 +++++++++--- + 2 files changed, 15 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -481,6 +481,12 @@ config MTD_NAND_FSL_NFC + Enables support for NAND Flash chips wired onto Freescale PowerPC + processor localbus with User-Programmable Machine support. + ++config MTD_NAND_FSL_NFC_SWECC ++ bool "Software ECC" ++ depends on MTD_NAND_FSL_NFC ++ help ++ Use software ECC. ++ + config MTD_NAND_MXC + tristate "MXC NAND support" + depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51 +--- a/drivers/mtd/nand/fsl_nfc.c ++++ b/drivers/mtd/nand/fsl_nfc.c +@@ -403,9 +403,15 @@ fsl_nfc_command(struct mtd_info *mtd, un + if (page != -1) + prv->page = page; + +- nfc_set_field(mtd, NFC_FLASH_CONFIG, +- CONFIG_ECC_MODE_MASK, +- CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); ++ if(hardware_ecc) ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); ++ else ++ /* set ECC BY_PASS */ ++ nfc_set_field(mtd, NFC_FLASH_CONFIG, ++ CONFIG_ECC_MODE_MASK, ++ CONFIG_ECC_MODE_SHIFT, ECC_BYPASS); + + if (!(page%0x40)) { + nfc_set_field(mtd, NFC_FLASH_CONFIG, diff --git a/target/linux/coldfire/patches/036-Add-FlexCAN-support-on-ColdFire-M548X-M54418-platfor.patch b/target/linux/coldfire/patches/036-Add-FlexCAN-support-on-ColdFire-M548X-M54418-platfor.patch new file mode 100644 index 000000000..af5e84f72 --- /dev/null +++ b/target/linux/coldfire/patches/036-Add-FlexCAN-support-on-ColdFire-M548X-M54418-platfor.patch @@ -0,0 +1,764 @@ +From c3b97e08b06be76ee9f2b410b13c045425fc7f3e Mon Sep 17 00:00:00 2001 +From: Jingchang Lu <b35083@freescale.com> +Date: Thu, 4 Aug 2011 09:59:48 +0800 +Subject: [PATCH 36/52] Add FlexCAN support on ColdFire M548X, M54418 platform + +Each cpu core has two FlexCAN interface, and the M54418's FlexCAN +also support Rx message buffer FIFO mode but M548X not. + +Signed-off-by: Jingchang Lu <b35083@freescale.com> +--- + arch/m68k/Kconfig | 2 + + arch/m68k/coldfire/m5441x/Makefile | 4 + + arch/m68k/coldfire/m5441x/mcf-flexcan.c | 121 ++++++++++++++++ + arch/m68k/coldfire/m547x/Makefile | 3 + + arch/m68k/coldfire/m547x/mcf-flexcan.c | 117 +++++++++++++++ + drivers/net/can/Kconfig | 9 ++ + drivers/net/can/flexcan.c | 239 ++++++++++++++++++++++++++++++- + 7 files changed, 489 insertions(+), 6 deletions(-) + create mode 100644 arch/m68k/coldfire/m5441x/mcf-flexcan.c + create mode 100644 arch/m68k/coldfire/m547x/mcf-flexcan.c + +--- a/arch/m68k/Kconfig ++++ b/arch/m68k/Kconfig +@@ -372,6 +372,7 @@ config M547X + config M548X + bool + depends on M547X_8X ++ select HAVE_CAN_FLEXCAN + default n + + choice +@@ -430,6 +431,7 @@ config M5441X + select GENERIC_TIME + select USB_EHCI_FSL + select HAVE_FSL_USB_DR ++ select HAVE_CAN_FLEXCAN + help + This option will add support for the MCF5441x processor with mmu. + +--- a/arch/m68k/coldfire/m5441x/Makefile ++++ b/arch/m68k/coldfire/m5441x/Makefile +@@ -36,3 +36,7 @@ endif + ifneq ($(CONFIG_MODELO_SWITCH),) + obj-y += l2switch.o + endif ++ ++ifneq ($(CONFIG_CAN_FLEXCAN),) ++obj-y += mcf-flexcan.o ++endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/mcf-flexcan.c +@@ -0,0 +1,121 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * Author: Huan Wang, b18965@freescale.com, Fri Aug 08 2008 ++ * ++ * Description: ++ * CAN bus driver for Freescale Coldfire embedded CPU ++ * ++ * Changelog: ++ * Fri Aug 08 2008 Huan Wang <b18965@freescale.com> ++ * - create, support for MCF548x ++ * ++ * Tue Dec 08 2009 ChengJu Cai <b22600@freescale.com> ++ * - support for MCF532x MCF5253 MCF5227x ++ * ++ * July 2011 Jingchang.Lu <b35083@freescale.com> ++ * - Add into kernel CAN driver layer ++ * ++ * This file is part of the Linux kernel ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <asm/mcfsim.h> ++ ++ ++static struct resource mcf5441x_can0_resources[] = { ++ [0] = { ++ .start = 0xFC020000, ++ .end = 0xFC0208C0, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = 0 + 64 + 64, ++ .end = 0 + 64 + 64, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource mcf5441x_can1_resources[] = { ++ [0] = { ++ .start = 0xFC024000, ++ .end = 0xFC0248C0, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = 4 + 64 + 64, ++ .end = 4 + 64 + 64, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device mcf_flexcan[PDEV_MAX] = { ++ [0] = { ++ .name = "flexcan", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(mcf5441x_can0_resources), ++ .resource = mcf5441x_can0_resources, ++ }, ++ [1] = { ++ .name = "flexcan", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(mcf5441x_can1_resources), ++ .resource = mcf5441x_can1_resources, ++ }, ++ ++}; ++ ++ ++static void __init mcf_flexcan_config(void) ++{ ++ MCF_PM_PPMCR0 = 8; /* enable FlexCAN0 clock */ ++ MCF_PM_PPMCR0 = 9; /* enable FlexCAN1 clock */ ++ ++ /* CAN0 */ ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK) | ++ MCF_GPIO_PAR_CANI2C_I2C0SCL_CAN0TX; ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK) | ++ MCF_GPIO_PAR_CANI2C_I2C0SDA_CAN0RX; ++ /* CAN1 */ ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1TX_MASK) | ++ MCF_GPIO_PAR_CANI2C_CAN1TX_CAN1TX; ++ MCF_GPIO_PAR_CANI2C = ++ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1RX_MASK) | ++ MCF_GPIO_PAR_CANI2C_CAN1RX_CAN1RX; ++ ++ ++} ++ ++static int __init flexcan_of_to_pdev(void) ++{ ++ int i, err = -ENODEV; ++ for (i = 0; i < PDEV_MAX; i++) { ++ err = platform_device_register(&mcf_flexcan[i]); ++ if (err) ++ return err; ++ printk(KERN_INFO "ColdFire FlexCAN devices loaded\n"); ++ } ++ return err; ++} ++ ++static int __init mcf_flexcan_init(void) ++{ ++ int err; ++ mcf_flexcan_config(); ++ err = flexcan_of_to_pdev(); ++ ++ return 0; ++} ++ ++arch_initcall(mcf_flexcan_init); +--- a/arch/m68k/coldfire/m547x/Makefile ++++ b/arch/m68k/coldfire/m547x/Makefile +@@ -5,3 +5,6 @@ + obj-$(CONFIG_M547X_8X) += config.o mcf548x-devices.o devices.o + obj-$(CONFIG_PCI) += pci.o pci_dummy.o + obj-$(CONFIG_MCD_DMA) += dma.o ++ifneq ($(CONFIG_CAN_FLEXCAN),) ++obj-y += mcf-flexcan.o ++endif +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/mcf-flexcan.c +@@ -0,0 +1,117 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * Author: Huan Wang, b18965@freescale.com, Fri Aug 08 2008 ++ * ++ * Description: ++ * CAN bus driver for Freescale Coldfire embedded CPU ++ * ++ * Changelog: ++ * Fri Aug 08 2008 Huan Wang <b18965@freescale.com> ++ * - create, support for MCF548x ++ * ++ * Tue Dec 08 2009 ChengJu Cai <b22600@freescale.com> ++ * - support for MCF532x MCF5253 MCF5227x ++ * ++ * July 2011 Jingchang.Lu <b35083@freescale.com> ++ * - Add into kernel CAN driver layer ++ * ++ * This file is part of the Linux kernel ++ * This is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <asm/mcfsim.h> ++ ++ ++static struct resource mcf548x_can0_resources[] = { ++ [0] = { ++ .start = MCF_MBAR + 0x0000A000, ++ .end = MCF_MBAR + 0x0000A7FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = 49 + 64, ++ .end = 49 + 64, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource mcf548x_can1_resources[] = { ++ [0] = { ++ .start = MCF_MBAR + 0x0000A800, ++ .end = MCF_MBAR + 0x0000AFFF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = 55 + 64, ++ .end = 55 + 64, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device mcf_flexcan[PDEV_MAX] = { ++ [0] = { ++ .name = "flexcan", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(mcf548x_can1_resources), ++ .resource = mcf548x_can0_resources, ++ }, ++ [1] = { ++ .name = "flexcan", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(mcf548x_can1_resources), ++ .resource = mcf548x_can1_resources, ++ }, ++ ++}; ++ ++ ++static void __init mcf_flexcan_config(void) ++{ ++ int i; ++ MCF_PAR_TIMER = MCF_PAR_TIMER | 0x28; ++ MCF_PAR_TIMER = MCF_PAR_TIMER & 0xf8; ++ MCF_PAR_DSPI = MCF_PAR_DSPI | 0x0a00; ++ MCF_PAR_FECI2CIRQ = MCF_PAR_FECI2CIRQ | 0x0283; ++ MCF_PAR_PSCn(2) = MCF_PAR_PSCn(2) & 0x0f; ++ MCF_PAR_PSCn(2) = MCF_PAR_PSCn(2) | 0x50; ++ ++ for (i = 0; i < 2; i++) { ++ MCF_ICR(ISC_CANn_MBOR(i)) = 0x33 + 0x01 * i; ++ MCF_ICR(ISC_CANn_ERR(i)) = 0x33 + 0x01 * i; ++ MCF_ICR(ISC_CANn_BUSOFF(i)) = 0x33 + 0x01 * i; ++ } ++ ++ ++} ++ ++static int __init flexcan_of_to_pdev(void) ++{ ++ int i, err = -ENODEV; ++ for (i = 0; i < PDEV_MAX; i++) { ++ err = platform_device_register(&mcf_flexcan[i]); ++ if (err) ++ return err; ++ printk(KERN_INFO "ColdFire FlexCAN devices loaded\n"); ++ } ++ return err; ++} ++ ++static int __init mcf_flexcan_init(void) ++{ ++ int err; ++ mcf_flexcan_config(); ++ err = flexcan_of_to_pdev(); ++ ++ return 0; ++} ++ ++arch_initcall(mcf_flexcan_init); +--- a/drivers/net/can/Kconfig ++++ b/drivers/net/can/Kconfig +@@ -103,6 +103,15 @@ config CAN_FLEXCAN + ---help--- + Say Y here if you want to support for Freescale FlexCAN. + ++config FLEXCAN_NORXFIFO ++ bool "FlexCAN message buffer without Rx FIFO mode" ++ depends on CAN_FLEXCAN && COLDFIRE ++ default n ++ ---help--- ++ Say Y here if you FlexCAN message buffer has no Rx FIFO mode. ++ Freescale Coldfire series have different FlexCAN core version, ++ MCF54418's support Rx FIFO mode while others such as MCF5485 not. ++ + config PCH_CAN + tristate "PCH CAN" + depends on CAN_DEV && PCI +--- a/drivers/net/can/flexcan.c ++++ b/drivers/net/can/flexcan.c +@@ -4,6 +4,7 @@ + * Copyright (c) 2005-2006 Varma Electronics Oy + * Copyright (c) 2009 Sascha Hauer, Pengutronix + * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved. + * + * Based on code originally by Andrey Volkov <avolkov@varma-el.com> + * +@@ -35,8 +36,28 @@ + #include <linux/module.h> + #include <linux/platform_device.h> + ++#ifndef CONFIG_COLDFIRE + #include <mach/clock.h> + ++#else ++#include <asm/mcfsim.h> ++ ++#undef readb ++#undef readw ++#undef readl ++#define readb(addr) __raw_readb(addr) ++#define readw(addr) __raw_readw(addr) ++#define readl(addr) __raw_readl(addr) ++ ++#undef writeb ++#undef writew ++#undef writel ++#define writeb(b, addr) __raw_writeb(b, addr) ++#define writew(b, addr) __raw_writew(b, addr) ++#define writel(b, addr) __raw_writel(b, addr) ++ ++#endif ++ + #define DRV_NAME "flexcan" + + /* 8 for RX fifo and 2 error handling */ +@@ -85,12 +106,34 @@ + #define FLEXCAN_CTRL_LOM BIT(3) + #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) + #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) ++ ++#ifdef CONFIG_COLDFIRE ++ ++# if defined(CONFIG_M548X) ++ ++#define FLEXCAN_CTRL_ERR_STATE FLEXCAN_CTRL_BOFF_MSK ++#define FLEXCAN_CTRL_ERR_ALL \ ++ (FLEXCAN_CTRL_BOFF_MSK | FLEXCAN_CTRL_ERR_MSK) ++ ++# elif defined(CONFIG_M5441X) ++ + #define FLEXCAN_CTRL_ERR_STATE \ + (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ + FLEXCAN_CTRL_BOFF_MSK) + #define FLEXCAN_CTRL_ERR_ALL \ + (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) + ++# endif ++ ++#else /* !CONFIG_COLDFIRE */ ++ ++#define FLEXCAN_CTRL_ERR_STATE \ ++ (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ ++ FLEXCAN_CTRL_BOFF_MSK) ++#define FLEXCAN_CTRL_ERR_ALL \ ++ (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) ++ ++#endif + /* FLEXCAN error and status register (ESR) bits */ + #define FLEXCAN_ESR_TWRN_INT BIT(17) + #define FLEXCAN_ESR_RWRN_INT BIT(16) +@@ -121,6 +164,18 @@ + (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) + + /* FLEXCAN interrupt flag register (IFLAG) bits */ ++ ++#ifdef CONFIG_FLEXCAN_NORXFIFO ++ ++/* MB assignment for no Rx FIFO mode module */ ++#define FLEXCAN_TX_BUF_ID 0 ++#define FLEXCAN_RX_EXT_ID 15 ++#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE 0xfffe ++#define FLEXCAN_IFLAG_DEFAULT \ ++ (FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | (0x01 << FLEXCAN_TX_BUF_ID)) ++ ++#else ++ + #define FLEXCAN_TX_BUF_ID 8 + #define FLEXCAN_IFLAG_BUF(x) BIT(x) + #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) +@@ -130,6 +185,7 @@ + (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ + FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) + ++#endif + /* FLEXCAN message buffers */ + #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) + #define FLEXCAN_MB_CNT_SRR BIT(22) +@@ -163,7 +219,11 @@ struct flexcan_regs { + u32 iflag2; /* 0x2c */ + u32 iflag1; /* 0x30 */ + u32 _reserved2[19]; ++#ifdef CONFIG_COLDFIRE ++ struct flexcan_mb cantxfg[CAN_MB]; ++#else + struct flexcan_mb cantxfg[64]; ++#endif + }; + + struct flexcan_priv { +@@ -181,8 +241,13 @@ struct flexcan_priv { + + static struct can_bittiming_const flexcan_bittiming_const = { + .name = DRV_NAME, ++#ifdef CONFIG_COLDFIRE ++ .tseg1_min = 1, ++ .tseg1_max = 8, ++#else + .tseg1_min = 4, + .tseg1_max = 16, ++#endif + .tseg2_min = 2, + .tseg2_max = 8, + .sjw_max = 4, +@@ -248,7 +313,7 @@ static int flexcan_start_xmit(struct sk_ + struct net_device_stats *stats = &dev->stats; + struct flexcan_regs __iomem *regs = priv->base; + struct can_frame *cf = (struct can_frame *)skb->data; +- u32 can_id; ++ u32 can_id, tmp, tmp1; + u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); + + if (can_dropped_invalid_skb(dev, skb)) +@@ -259,6 +324,11 @@ static int flexcan_start_xmit(struct sk_ + if (cf->can_id & CAN_EFF_FLAG) { + can_id = cf->can_id & CAN_EFF_MASK; + ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; ++#ifdef CONFIG_COLDFIRE ++ tmp = (can_id & CAN_SFF_MASK) << 18; ++ tmp1 = can_id >> 11; ++ can_id = tmp | tmp1; ++#endif + } else { + can_id = (cf->can_id & CAN_SFF_MASK) << 18; + } +@@ -456,6 +526,87 @@ static int flexcan_poll_state(struct net + return 1; + } + ++#ifdef CONFIG_FLEXCAN_NORXFIFO ++/* Get one frame from receive message buffer */ ++static int flexcan_read_frame(struct net_device *dev) ++{ ++ const struct flexcan_priv *priv = netdev_priv(dev); ++ struct flexcan_regs __iomem *regs = priv->base; ++ struct net_device_stats *stats = &dev->stats; ++ struct can_frame *cf; ++ struct sk_buff *skb; ++ struct flexcan_mb __iomem *mb; ++ u32 reg_iflag1, reg_ctrl, reg_id, i; ++ ++ reg_iflag1 = readl(®s->iflag1); ++ ++ /* buf[0] if for TX */ ++ for (i = 0; i < CAN_MB; i++) { ++ if (i == FLEXCAN_TX_BUF_ID) ++ continue; ++ /* find one received message slot */ ++ if (reg_iflag1 & (0x01 << i)) ++ break; ++ } ++ if (i >= CAN_MB) ++ return 0; ++ ++ mb = ®s->cantxfg[i]; ++ ++ skb = alloc_can_skb(dev, &cf); ++ if (unlikely(!skb)) { ++ stats->rx_dropped++; ++ return 0; ++ } ++ ++ reg_ctrl = readl(&mb->can_ctrl); ++ reg_id = readl(&mb->can_id); ++ ++ /* deactive RX buff */ ++ writel(0, &mb->can_ctrl); ++ ++ if (reg_ctrl & FLEXCAN_MB_CNT_IDE) { ++#ifdef CONFIG_COLDFIRE ++ /* Coldfire can_id order */ ++ cf->can_id = (reg_id & CAN_EFF_MASK) >> 18; ++ cf->can_id |= (reg_id & 0x3ffff) << 11; ++ cf->can_id |= CAN_EFF_FLAG; ++#else ++ cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; ++#endif ++ } else ++ cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; ++ ++ if (reg_ctrl & FLEXCAN_MB_CNT_RTR) ++ cf->can_id |= CAN_RTR_FLAG; ++ cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); ++ ++ *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0])); ++ *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1])); ++ ++ /* reactive RX buffer */ ++ if (i == FLEXCAN_RX_EXT_ID) ++ writel(FLEXCAN_MB_CNT_CODE(0x4)|0x600000, ++ ®s->cantxfg[i].can_ctrl); ++ else ++ writel(FLEXCAN_MB_CNT_CODE(0x4), ++ ®s->cantxfg[i].can_ctrl); ++ ++ /* mark as read */ ++ writel((0x01 << i), ®s->iflag1); ++ /* release MB lock */ ++ readl(®s->timer); ++ ++ netif_receive_skb(skb); ++ ++ stats->rx_packets++; ++ stats->rx_bytes += cf->can_dlc; ++ ++ return 1; ++ ++} ++#else ++ + static void flexcan_read_fifo(const struct net_device *dev, + struct can_frame *cf) + { +@@ -466,9 +617,16 @@ static void flexcan_read_fifo(const stru + + reg_ctrl = readl(&mb->can_ctrl); + reg_id = readl(&mb->can_id); +- if (reg_ctrl & FLEXCAN_MB_CNT_IDE) ++ if (reg_ctrl & FLEXCAN_MB_CNT_IDE) { ++#ifdef CONFIG_COLDFIRE ++ /* ColdFire can_id order as follow */ ++ cf->can_id = (reg_id & CAN_EFF_MASK) >> 18; ++ cf->can_id |= (reg_id & 0x3ffff) << 11; ++ cf->can_id |= CAN_EFF_FLAG; ++#else + cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; +- else ++#endif ++ } else + cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; + + if (reg_ctrl & FLEXCAN_MB_CNT_RTR) +@@ -503,6 +661,7 @@ static int flexcan_read_frame(struct net + + return 1; + } ++#endif + + static int flexcan_poll(struct napi_struct *napi, int quota) + { +@@ -554,6 +713,14 @@ static irqreturn_t flexcan_irq(int irq, + reg_iflag1 = readl(®s->iflag1); + reg_esr = readl(®s->esr); + writel(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */ ++#ifdef CONFIG_COLDFIRE ++#ifdef CONFIG_FLEXCAN_NORXFIFO ++ writel(FLEXCAN_ESR_BOFF_INT, ®s->esr); ++#else ++ /* ACK TWRN and RWRN error, and bus-off interrupt*/ ++ writel(FLEXCAN_ESR_ERR_STATE, ®s->esr); ++#endif ++#endif + + /* + * schedule NAPI in case of: +@@ -575,13 +742,14 @@ static irqreturn_t flexcan_irq(int irq, + ®s->ctrl); + napi_schedule(&priv->napi); + } +- ++#ifndef CONFIG_FLEXCAN_NORXFIFO + /* FIFO overflow */ + if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { + writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); + dev->stats.rx_over_errors++; + dev->stats.rx_errors++; + } ++#endif + + /* transmission complete interrupt */ + if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { +@@ -676,9 +844,14 @@ static int flexcan_chip_start(struct net + * + */ + reg_mcr = readl(®s->mcr); ++#ifdef CONFIG_FLEXCAN_NORXFIFO ++ reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | ++ FLEXCAN_MCR_SUPV; ++#else + reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | + FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | + FLEXCAN_MCR_IDAM_C; ++#endif + dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr); + writel(reg_mcr, ®s->mcr); + +@@ -713,9 +886,19 @@ static int flexcan_chip_start(struct net + writel(0, ®s->cantxfg[i].can_id); + writel(0, ®s->cantxfg[i].data[0]); + writel(0, ®s->cantxfg[i].data[1]); +- ++#ifdef CONFIG_FLEXCAN_NORXFIFO ++ if (i == FLEXCAN_TX_BUF_ID) ++ continue; ++ if (i == FLEXCAN_RX_EXT_ID) /* enable receive extend message */ ++ writel(FLEXCAN_MB_CNT_CODE(0x4)|0x600000, ++ ®s->cantxfg[i].can_ctrl); ++ else ++ writel(FLEXCAN_MB_CNT_CODE(0x4), ++ ®s->cantxfg[i].can_ctrl); ++#else + /* put MB into rx queue */ + writel(FLEXCAN_MB_CNT_CODE(0x4), ®s->cantxfg[i].can_ctrl); ++#endif + } + + /* acceptance mask/acceptance code (accept everything) */ +@@ -772,6 +955,7 @@ static void flexcan_chip_stop(struct net + return; + } + ++ + static int flexcan_open(struct net_device *dev) + { + struct flexcan_priv *priv = netdev_priv(dev); +@@ -786,6 +970,24 @@ static int flexcan_open(struct net_devic + err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); + if (err) + goto out_close; ++ err = request_irq(dev->irq + 1, flexcan_irq, \ ++ IRQF_DISABLED, dev->name, dev); ++ if (err) { ++ free_irq(dev->irq, dev); ++ goto out_close; ++ } ++#if defined(CONFIG_M548X) ++ err = request_irq(dev->irq + 2, flexcan_irq, \ ++ IRQF_DISABLED, dev->name, dev); ++#elif defined(CONFIG_M5441X) ++ err = request_irq(dev->irq + 3, flexcan_irq, \ ++ IRQF_DISABLED, dev->name, dev); ++#endif ++ if (err) { ++ free_irq(dev->irq, dev); ++ free_irq(dev->irq + 1, dev); ++ goto out_close; ++ } + + /* start chip and queuing */ + err = flexcan_chip_start(dev); +@@ -813,6 +1015,14 @@ static int flexcan_close(struct net_devi + flexcan_chip_stop(dev); + + free_irq(dev->irq, dev); ++#ifdef CONFIG_COLDFIRE ++ free_irq(dev->irq + 1, dev); ++#if defined(CONFIG_M548X) ++ free_irq(dev->irq + 2, dev); ++#elif defined(CONFIG_M5441X) ++ free_irq(dev->irq + 3, dev); ++#endif ++#endif + clk_disable(priv->clk); + + close_candev(dev); +@@ -854,14 +1064,23 @@ static int __devinit register_flexcandev + + clk_enable(priv->clk); + ++#if !defined(CONFIG_M548X) + /* select "bus clock", chip must be disabled */ + flexcan_chip_disable(priv); + reg = readl(®s->ctrl); + reg |= FLEXCAN_CTRL_CLK_SRC; + writel(reg, ®s->ctrl); ++#endif + + flexcan_chip_enable(priv); + ++#ifdef CONFIG_FLEXCAN_NORXFIFO ++ /* set freeze, halt and restrict register access */ ++ reg = readl(®s->mcr); ++ reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | ++ FLEXCAN_MCR_SUPV; ++ writel(reg, ®s->mcr); ++#else + /* set freeze, halt and activate FIFO, restrict register access */ + reg = readl(®s->mcr); + reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | +@@ -880,6 +1099,7 @@ static int __devinit register_flexcandev + err = -ENODEV; + goto out; + } ++#endif + + err = register_candev(dev); + +@@ -901,17 +1121,19 @@ static int __devinit flexcan_probe(struc + struct net_device *dev; + struct flexcan_priv *priv; + struct resource *mem; +- struct clk *clk; ++ struct clk *clk = NULL; + void __iomem *base; + resource_size_t mem_size; + int err, irq; + ++#ifndef CONFIG_COLDFIRE + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "no clock defined\n"); + err = PTR_ERR(clk); + goto failed_clock; + } ++#endif + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); +@@ -943,7 +1165,12 @@ static int __devinit flexcan_probe(struc + dev->flags |= IFF_ECHO; /* we support local echo in hardware */ + + priv = netdev_priv(dev); ++#ifdef CONFIG_COLDFIRE ++ /* return value is core clock but we need bus clock */ ++ priv->can.clock.freq = (clk_get_rate(clk)/2); ++#else + priv->can.clock.freq = clk_get_rate(clk); ++#endif + priv->can.bittiming_const = &flexcan_bittiming_const; + priv->can.do_set_mode = flexcan_set_mode; + priv->can.do_get_berr_counter = flexcan_get_berr_counter; diff --git a/target/linux/coldfire/patches/037-Add-ColdFire-MCF54455-PATA-interface-support.patch b/target/linux/coldfire/patches/037-Add-ColdFire-MCF54455-PATA-interface-support.patch new file mode 100644 index 000000000..730086eba --- /dev/null +++ b/target/linux/coldfire/patches/037-Add-ColdFire-MCF54455-PATA-interface-support.patch @@ -0,0 +1,934 @@ +From 8e46c06091fd87904205a977be3c784e3ac61e95 Mon Sep 17 00:00:00 2001 +From: Jingchang Lu <b35083@freescale.com> +Date: Thu, 4 Aug 2011 09:59:48 +0800 +Subject: [PATCH 37/52] Add ColdFire MCF54455 PATA interface support + +ColdFire MCF54455 parallel ATA controller support +both uDMA and PIO mode, this driver implements all. + +Signed-off-by: Jingchang Lu <b35083@freescale.com> +--- + arch/m68k/include/asm/pata_fsl.h | 17 + + drivers/ata/Kconfig | 23 +- + drivers/ata/Makefile | 1 + + drivers/ata/pata_fsl.c | 844 ++++++++++++++++++++++++++++++++++++++ + 4 files changed, 884 insertions(+), 1 deletions(-) + create mode 100644 arch/m68k/include/asm/pata_fsl.h + create mode 100644 drivers/ata/pata_fsl.c + +--- /dev/null ++++ b/arch/m68k/include/asm/pata_fsl.h +@@ -0,0 +1,17 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef _ASM_M68K_PATA_FSL_H ++#define _ASM_M68K_PATA_FSL_H ++ ++/* ATA mapped IO address translate function */ ++extern unsigned int io_ata_virt2phys(void *x); ++extern void *io_ata_phys2virt(unsigned int x); ++ ++ ++#endif +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -14,7 +14,7 @@ menuconfig ATA + tristate "Serial ATA and Parallel ATA drivers" + depends on HAS_IOMEM + depends on BLOCK +- depends on !(M32R || M68K) || BROKEN ++ depends on !(M32R) || BROKEN + select SCSI + ---help--- + If you want to use a ATA hard disk, ATA tape drive, ATA CD-ROM or +@@ -687,6 +687,27 @@ config PATA_WINBOND + + If unsure, say N. + ++config PATA_FSL ++ tristate "Freescale on-chip PATA support" ++ depends on (ARCH_MX3 || ARCH_MX27 || PPC_512x || M54455) ++ help ++ Some Freescale processors SOC have parallel ATA controller, ++ such as ColdFire MCF54455. ++ ++ Say Y here if you wish to use the on-chip ATA interface. ++ ++ If you are unsure, say N to this. ++ ++config FSL_PATA_USE_DMA ++ bool "Freescale PATA eDMA support" ++ depends on PATA_FSL && COLDFIRE_EDMA ++ default y ++ help ++ This option enables the uDMA support over PATA interface ++ which can improve performance than PIO mode for read and write. ++ ++ If unsure, say Y. ++ + endif # ATA_BMDMA + + comment "PIO-only SFF controllers" +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -72,6 +72,7 @@ obj-$(CONFIG_PATA_TOSHIBA) += pata_picco + obj-$(CONFIG_PATA_TRIFLEX) += pata_triflex.o + obj-$(CONFIG_PATA_VIA) += pata_via.o + obj-$(CONFIG_PATA_WINBOND) += pata_sl82c105.o ++obj-$(CONFIG_PATA_FSL) += pata_fsl.o + + # SFF PIO only + obj-$(CONFIG_PATA_AT32) += pata_at32.o +--- /dev/null ++++ b/drivers/ata/pata_fsl.c +@@ -0,0 +1,844 @@ ++/* ++ * Freescale integrated PATA driver ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Description: ++ * This driver is for Coldfire MCF54455 on-chip ATA module. ++ * ++ * This is free software; you can redistribute it and/or modify it ++ * under the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at ++ * your option) any later version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/blkdev.h> ++#include <scsi/scsi_host.h> ++#include <linux/ata.h> ++#include <linux/libata.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#ifdef CONFIG_FSL_PATA_USE_DMA ++#include <asm/mcf_edma.h> ++#endif ++#include <asm/pata_fsl.h> ++ ++#define DRV_NAME "pata_fsl" ++#define DRV_VERSION "1.0" ++ ++#ifdef CONFIG_M54455 ++#define WRITE_ATA8(val, reg) \ ++ __raw_writeb(val, (ata_regs + reg)); ++#define WRITE_ATA16(val, reg) \ ++ __raw_writew(val, (ata_regs + reg)); ++#else ++#define WRITE_ATA8(val, reg) \ ++ __raw_writel(val, (ata_regs + reg)); ++#define WRITE_ATA16(val, reg) \ ++ __raw_writel(val, (ata_regs + reg)); ++#endif ++ ++#define MAX_FSL_SG 256 /* MCF_EDMA_TCD_PER_CHAN */ ++ ++struct pata_fsl_priv { ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ int ultra; ++#endif ++ u8 *fsl_ata_regs; ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ int dma_rchan; ++ int dma_wchan; ++ int dma_done; ++ int dma_dir; ++#if 0 ++ int nsg; ++ struct fsl_edma_requestbuf reqbuf[MAX_FSL_SG]; ++#endif ++#endif ++}; ++ ++enum { ++ /* various constants */ ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ FSL_ATA_MAX_SG_LEN = 65534, ++#endif ++ ++ /* offsets to registers */ ++ ++ FSL_ATA_TIMING_REGS = 0x00, ++ FSL_ATA_FIFO_FILL = 0x20, ++ FSL_ATA_CONTROL = 0x24, ++ FSL_ATA_INT_PEND = 0x28, ++ FSL_ATA_INT_EN = 0x2C, ++ FSL_ATA_INT_CLEAR = 0x30, ++ FSL_ATA_FIFO_ALARM = 0x34, ++ FSL_ATA_DRIVE_DATA = 0xA0, ++ FSL_ATA_DRIVE_CONTROL = 0xD8, ++ ++ /* bits within FSL_ATA_CONTROL */ ++ ++ FSL_ATA_CTRL_FIFO_RST_B = 0x80, ++ FSL_ATA_CTRL_ATA_RST_B = 0x40, ++ FSL_ATA_CTRL_FIFO_TX_EN = 0x20, ++ FSL_ATA_CTRL_FIFO_RCV_EN = 0x10, ++ FSL_ATA_CTRL_DMA_PENDING = 0x08, ++ FSL_ATA_CTRL_DMA_ULTRA = 0x04, ++ FSL_ATA_CTRL_DMA_WRITE = 0x02, ++ FSL_ATA_CTRL_IORDY_EN = 0x01, ++ ++ /* bits within the interrupt control registers */ ++ ++ FSL_ATA_INTR_ATA_INTRQ1 = 0x80, ++ FSL_ATA_INTR_FIFO_UNDERFLOW = 0x40, ++ FSL_ATA_INTR_FIFO_OVERFLOW = 0x20, ++ FSL_ATA_INTR_CTRL_IDLE = 0x10, ++ FSL_ATA_INTR_ATA_INTRQ2 = 0x08, ++}; ++ ++/* ++ * This structure contains the timing parameters for ++ * ATA bus timing in the 5 PIO modes. The timings ++ * are in nanoseconds, and are converted to clock ++ * cycles before being stored in the ATA controller ++ * timing registers. ++ */ ++static struct { ++ short t0, t1, t2_8, t2_16, t2i, t4, t9, tA; ++} pio_specs[] = { ++ [0] = { ++ .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 0, ++ .t4 = 30, .t9 = 20, .tA = 50 ++ }, ++ [1] = { ++ .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0, ++ .t4 = 20, .t9 = 15, .tA = 50 ++ }, ++ [2] = { ++ .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0, ++ .t4 = 15, .t9 = 10, .tA = 50 ++ }, ++ [3] = { ++ .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0, ++ .t4 = 10, .t9 = 10, .tA = 50 ++ }, ++ [4] = { ++ .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0, ++ .t4 = 10, .t9 = 10, .tA = 50 ++ }, ++}; ++ ++#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0]) ++ ++/* ++ * This structure contains the timing parameters for ++ * ATA bus timing in the 3 MDMA modes. The timings ++ * are in nanoseconds, and are converted to clock ++ * cycles before being stored in the ATA controller ++ * timing registers. ++ */ ++static struct { ++ short t0M, tD, tH, tJ, tKW, tM, tN, tJNH; ++} mdma_specs[] = { ++ [0] = { ++ .t0M = 480, .tD = 215, .tH = 20, .tJ = 20, .tKW = 215, ++ .tM = 50, .tN = 15, .tJNH = 20 ++ }, ++ [1] = { ++ .t0M = 150, .tD = 80, .tH = 15, .tJ = 5, .tKW = 50, ++ .tM = 30, .tN = 10, .tJNH = 15 ++ }, ++ [2] = { ++ .t0M = 120, .tD = 70, .tH = 10, .tJ = 5, .tKW = 25, ++ .tM = 25, .tN = 10, .tJNH = 10 ++ }, ++}; ++ ++#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0]) ++ ++/* ++ * This structure contains the timing parameters for ++ * ATA bus timing in the 6 UDMA modes. The timings ++ * are in nanoseconds, and are converted to clock ++ * cycles before being stored in the ATA controller ++ * timing registers. ++ */ ++static struct { ++ short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max, ++ tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS; ++} udma_specs[] = { ++ [0] = { ++ .t2CYC = 235, .tCYC = 114, .tDS = 15, .tDH = 5, .tDVS = 70, ++ .tDVH = 6, .tCVS = 70, .tCVH = 6, .tFS_min = 0, ++ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, ++ .tENV_min = 20, .tSR = 50, .tRFS = 75, .tRP = 160, ++ .tACK = 20, .tSS = 50, .tDZFS = 80 ++ }, ++ [1] = { ++ .t2CYC = 156, .tCYC = 75, .tDS = 10, .tDH = 5, .tDVS = 48, ++ .tDVH = 6, .tCVS = 48, .tCVH = 6, .tFS_min = 0, ++ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, ++ .tENV_min = 20, .tSR = 30, .tRFS = 70, .tRP = 125, ++ .tACK = 20, .tSS = 50, .tDZFS = 63 ++ }, ++ [2] = { ++ .t2CYC = 117, .tCYC = 55, .tDS = 7, .tDH = 5, .tDVS = 34, ++ .tDVH = 6, .tCVS = 34, .tCVH = 6, .tFS_min = 0, ++ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, ++ .tENV_min = 20, .tSR = 20, .tRFS = 60, .tRP = 100, ++ .tACK = 20, .tSS = 50, .tDZFS = 47 ++ }, ++ [3] = { ++ .t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 20, ++ .tDVH = 6, .tCVS = 20, .tCVH = 6, .tFS_min = 0, ++ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, ++ .tENV_min = 20, .tSR = 20, .tRFS = 60, .tRP = 100, ++ .tACK = 20, .tSS = 50, .tDZFS = 35 ++ }, ++ [4] = { ++ .t2CYC = 57, .tCYC = 25, .tDS = 5, .tDH = 5, .tDVS = 7, ++ .tDVH = 6, .tCVS = 7, .tCVH = 6, .tFS_min = 0, ++ .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, ++ .tENV_min = 20, .tSR = 50, .tRFS = 60, .tRP = 100, ++ .tACK = 20, .tSS = 50, .tDZFS = 25 ++ }, ++ [5] = { ++ .t2CYC = 38, .tCYC = 17, .tDS = 4, .tDH = 5, .tDVS = 5, ++ .tDVH = 6, .tCVS = 10, .tCVH = 10, .tFS_min = 0, ++ .tLI_max = 75, .tMLI = 20, .tAZ = 10, .tZAH = 20, ++ .tENV_min = 20, .tSR = 20, .tRFS = 50, .tRP = 85, ++ .tACK = 20, .tSS = 50, .tDZFS = 40 ++ }, ++}; ++ ++#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0]) ++ ++struct fsl_ata_time_regs { ++ u8 time_off, time_on, time_1, time_2w; ++ u8 time_2r, time_ax, time_pio_rdx, time_4; ++ u8 time_9, time_m, time_jn, time_d; ++ u8 time_k, time_ack, time_env, time_rpx; ++ u8 time_zah, time_mlix, time_dvh, time_dzfs; ++ u8 time_dvs, time_cvh, time_ss, time_cyc; ++} __packed; ++ ++ ++static void update_timing_config(struct fsl_ata_time_regs *tp, ++ struct ata_host *host) ++{ ++ u32 __iomem *lp = (u32 __iomem *)tp; ++ struct pata_fsl_priv *priv = host->private_data; ++ u32 __iomem *ctlp = (u32 __iomem *)priv->fsl_ata_regs; ++ int i; ++ ++ /* ++ * JKM - this could have endianess issues on BE depending ++ * on how the controller is glued to the bus -- probably ++ * should rewrite this to write byte at a time. ++ */ ++ for (i = 0; i < 6; i++) { ++ __raw_writel(*lp, ctlp); ++ lp++; ++ ctlp++; ++ } ++} ++ ++/*! ++ * Calculate values for the ATA bus timing registers and store ++ * them into the hardware. ++ * ++ * @param xfer_mode specifies XFER xfer_mode ++ * @param pdev specifies platform_device ++ * ++ * @return EINVAL speed out of range, or illegal mode ++ */ ++static int set_ata_bus_timing(u8 xfer_mode, struct platform_device *pdev) ++{ ++ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) ++ pdev->dev.platform_data; ++ struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ ++ /* get the bus clock cycle time, in ns */ ++ int T = 1 * 1000 * 1000 * 1000 / plat->get_clk_rate(); ++ struct fsl_ata_time_regs tr = {0}; ++ DPRINTK("clk_rate = %d T = %d\n", plat->get_clk_rate(), T); ++ ++ /* ++ * every mode gets the same t_off and t_on ++ */ ++ tr.time_off = 3; ++ tr.time_on = 3; ++ ++ if (xfer_mode >= XFER_UDMA_0) { ++ int speed = xfer_mode - XFER_UDMA_0; ++ if (speed >= NR_UDMA_SPECS) ++ return -EINVAL; ++ ++ tr.time_ack = (udma_specs[speed].tACK + T) / T; ++ tr.time_env = (udma_specs[speed].tENV_min + T) / T; ++ tr.time_rpx = (udma_specs[speed].tRP + T) / T + 2; ++ ++ tr.time_zah = (udma_specs[speed].tZAH + T) / T; ++ tr.time_mlix = (udma_specs[speed].tMLI + T) / T; ++ tr.time_dvh = (udma_specs[speed].tDVH + T) / T + 1; ++ tr.time_dzfs = (udma_specs[speed].tDZFS + T) / T; ++ ++ tr.time_dvs = (udma_specs[speed].tDVS + T) / T; ++ tr.time_cvh = (udma_specs[speed].tCVH + T) / T; ++ tr.time_ss = (udma_specs[speed].tSS + T) / T; ++ tr.time_cyc = (udma_specs[speed].tCYC + T) / T; ++ } else if (xfer_mode >= XFER_MW_DMA_0) { ++ int speed = xfer_mode - XFER_MW_DMA_0; ++ if (speed >= NR_MDMA_SPECS) ++ return -EINVAL; ++ ++ tr.time_m = (mdma_specs[speed].tM + T) / T; ++ tr.time_jn = (mdma_specs[speed].tJNH + T) / T; ++ tr.time_d = (mdma_specs[speed].tD + T) / T; ++ ++ tr.time_k = (mdma_specs[speed].tKW + T) / T; ++ } else { ++ int speed = xfer_mode - XFER_PIO_0; ++ if (speed >= NR_PIO_SPECS) ++ return -EINVAL; ++ ++ tr.time_1 = (pio_specs[speed].t1 + T) / T; ++ tr.time_2w = (pio_specs[speed].t2_8 + T) / T; ++ ++ tr.time_2r = (pio_specs[speed].t2_8 + T) / T; ++ tr.time_ax = (pio_specs[speed].tA + T) / T + 2; ++ tr.time_pio_rdx = 1; ++ tr.time_4 = (pio_specs[speed].t4 + T) / T; ++ ++ tr.time_9 = (pio_specs[speed].t9 + T) / T; ++ } ++ ++ update_timing_config(&tr, host); ++ ++ return 0; ++} ++ ++static void pata_fsl_set_piomode(struct ata_port *ap, struct ata_device *adev) ++{ ++ set_ata_bus_timing(adev->pio_mode, to_platform_device(ap->dev)); ++} ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++static void pata_fsl_set_dmamode(struct ata_port *ap, struct ata_device *adev) ++{ ++ struct pata_fsl_priv *priv = ap->host->private_data; ++ ++ priv->ultra = adev->dma_mode >= XFER_UDMA_0; ++ ++ set_ata_bus_timing(adev->dma_mode, to_platform_device(ap->dev)); ++} ++#endif ++ ++static int pata_fsl_port_start(struct ata_port *ap) ++{ ++ return 0; ++} ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ ++static irqreturn_t dma_callback(int channel, void *arg) ++{ ++ struct ata_port *ap = arg; ++ struct pata_fsl_priv *priv = ap->host->private_data; ++ u8 __iomem *ata_regs = priv->fsl_ata_regs; ++ ++ mcf_edma_stop_transfer(channel); ++ priv->dma_done = 1; ++ /* ++ * DMA is finished, so unmask INTRQ from the drive to allow the ++ * normal ISR to fire. ++ */ ++#if 0 ++ __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN); ++#else ++ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN); ++ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL); ++#endif ++ ++ return IRQ_HANDLED; ++} ++ ++static void pata_fsl_bmdma_setup(struct ata_queued_cmd *qc) ++{ ++ int chan; ++ int dma_ultra; ++ u8 ata_control; ++ struct ata_port *ap = qc->ap; ++ struct pata_fsl_priv *priv = ap->host->private_data; ++ u8 __iomem *ata_regs = priv->fsl_ata_regs; ++#if 0 ++ struct scatterlist *sg; ++ struct fsl_edma_requestbuf *pbuf; ++ unsigned int si; ++#endif ++ DPRINTK("ENTER\n"); ++ ++ /* reset the ATA FIFO first */ ++ /* ++ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B,FSL_ATA_CONTROL); ++ */ ++ priv->dma_dir = qc->dma_dir; ++ ++ /* ++ * Configure the on-chip ATA interface hardware. ++ */ ++ dma_ultra = priv->ultra ? ++ FSL_ATA_CTRL_DMA_ULTRA : 0; ++ ++ ata_control = FSL_ATA_CTRL_FIFO_RST_B | ++ FSL_ATA_CTRL_ATA_RST_B | ++ FSL_ATA_CTRL_DMA_PENDING | ++ dma_ultra; ++ ++ if (qc->dma_dir == DMA_TO_DEVICE) { ++ chan = priv->dma_wchan; ++ ata_control |= FSL_ATA_CTRL_FIFO_TX_EN | ++ FSL_ATA_CTRL_DMA_WRITE; ++ } else { ++ chan = priv->dma_rchan; ++ ata_control |= FSL_ATA_CTRL_FIFO_RCV_EN; ++ } ++#if 0 ++ __raw_writel(ata_control, ata_regs + FSL_ATA_CONTROL); ++ __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_FIFO_ALARM); ++ __raw_writel(FSL_ATA_INTR_ATA_INTRQ1, ata_regs + FSL_ATA_INT_EN); ++#else ++ WRITE_ATA8(ata_control, FSL_ATA_CONTROL); ++ WRITE_ATA8(16/*plat->fifo_alarm*/, FSL_ATA_FIFO_ALARM); ++ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ1, FSL_ATA_INT_EN); ++#endif ++ /*mb();*/ ++ ++ /* ++ * Set up the DMA completion callback. ++ */ ++ /* ++ * Copy the sg list to an array. ++ */ ++#if 0 ++ priv->nsg = 0; ++ pbuf = priv->reqbuf; ++ ++ for_each_sg(qc->sg, sg, qc->n_elem, si) { ++ ++ /*dma_map_sg(NULL, sg, 1, priv->dma_dir); */ ++ ++ if (priv->dma_dir == DMA_TO_DEVICE) { /* WRITE */ ++ pbuf->saddr = sg->dma_address; ++ pbuf->daddr = (dma_addr_t)(priv->fsl_ata_regs + 0x18); ++ pbuf->soff = 4; ++ pbuf->doff = 0; ++ } else { /* Read */ ++ pbuf->daddr = sg->dma_address; ++ pbuf->saddr = (dma_addr_t)(priv->fsl_ata_regs + 0x18); ++ pbuf->doff = 4; ++ pbuf->soff = 0; ++ } ++ pbuf->attr = MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ |MCF_EDMA_TCD_ATTR_DSIZE_32BIT; ++ pbuf->minor_loop = 16*4; /* 16 longwords per request*/ ++ pbuf->len = sg_dma_len(sg); ++ ++ pbuf++; ++ priv->nsg++; ++ } ++ ++ BUG_ON(*(unsigned char *)(ata_regs + FSL_ATA_FIFO_FILL)); ++ mcf_edma_sg_config(chan, priv->reqbuf, priv->nsg); ++#else ++ if (priv->dma_dir == DMA_TO_DEVICE) { ++ mcf_edma_sglist_config(chan, qc->sg, qc->n_elem, priv->dma_dir, ++ (dma_addr_t) ++ ((io_ata_virt2phys((void *)priv->fsl_ata_regs)) + 0x18), ++ MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT, ++ 4, 0, 8*4); ++ } else { ++ ++ mcf_edma_sglist_config(chan, qc->sg, qc->n_elem, priv->dma_dir, ++ (dma_addr_t) ++ ((io_ata_virt2phys((void *)priv->fsl_ata_regs)) + 0x18), ++ MCF_EDMA_TCD_ATTR_SSIZE_32BIT ++ | MCF_EDMA_TCD_ATTR_DSIZE_32BIT, ++ 0, 4, 8*4); ++ } ++ ++#endif ++ priv->dma_done = 0; ++ ++ DPRINTK("EXIT\n"); ++ ++} ++ ++static void pata_fsl_bmdma_start(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++ struct pata_fsl_priv *priv = ap->host->private_data; ++ int chan; ++ ++ /* ++ * Start the channel. ++ */ ++ chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : priv->dma_rchan; ++ ++ mcf_edma_enable_transfer(chan); ++ ++ ap->ops->sff_exec_command(ap, &qc->tf); ++} ++ ++static void pata_fsl_bmdma_stop(struct ata_queued_cmd *qc) ++{ ++ struct ata_port *ap = qc->ap; ++/* ++ int chan; ++ ++ chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : priv->dma_rchan; ++ mcf_edma_stop_transfer(chan); ++*/ ++/* do a dummy read as in ata_bmdma_stop */ ++ ata_sff_dma_pause(ap); ++} ++ ++static u8 pata_fsl_bmdma_status(struct ata_port *ap) ++{ ++ struct pata_fsl_priv *priv = ap->host->private_data; ++ ++ return priv->dma_done ? ATA_DMA_INTR : 0; ++} ++ ++static void pata_fsl_dma_init(struct ata_port *ap) ++{ ++ struct pata_fsl_priv *priv = ap->host->private_data; ++ ++ priv->dma_rchan = -1; ++ priv->dma_wchan = -1; ++ ++ priv->dma_rchan = mcf_edma_request_channel(MCF_EDMA_CHAN_ATA_RX, ++ dma_callback, ++ NULL, 0x6, ++ (void *)ap, ++ NULL, ++ "MCF ATA RX"); ++ if (priv->dma_rchan < 0) { ++ dev_printk(KERN_ERR, ap->dev, "couldn't get RX DMA channel\n"); ++ goto err_out; ++ } ++ ++ priv->dma_wchan = mcf_edma_request_channel(MCF_EDMA_CHAN_ATA_TX, ++ dma_callback, ++ NULL, 0x6, ++ (void *)ap, ++ NULL, ++ "MCF ATA TX"); ++ if (priv->dma_wchan < 0) { ++ dev_printk(KERN_ERR, ap->dev, "couldn't get TX DMA channel\n"); ++ goto err_out; ++ } ++ ++ dev_printk(KERN_ERR, ap->dev, "rchan=%d wchan=%d\n", priv->dma_rchan, ++ priv->dma_wchan); ++ return; ++ ++err_out: ++ ap->mwdma_mask = 0; ++ ap->udma_mask = 0; ++ mcf_edma_free_channel(priv->dma_rchan, ap); ++ mcf_edma_free_channel(priv->dma_wchan, ap); ++ kfree(priv); ++} ++#endif /* CONFIG_FSL_PATA_USE_DMA */ ++ ++static void ata_dummy_noret(struct ata_port *ap) { return; } ++ ++static struct scsi_host_template pata_fsl_sht = { ++ ATA_BMDMA_SHT(DRV_NAME), ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ .sg_tablesize = MAX_FSL_SG, ++ .dma_boundary = ATA_DMA_BOUNDARY, ++#endif ++}; ++ ++static struct ata_port_operations pata_fsl_port_ops = { ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ .inherits = &ata_bmdma_port_ops, ++#else ++ .inherits = &ata_sff_port_ops, ++#endif ++ .set_piomode = pata_fsl_set_piomode, ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ .set_dmamode = pata_fsl_set_dmamode, ++#endif ++ .cable_detect = ata_cable_40wire, ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ .bmdma_setup = pata_fsl_bmdma_setup, ++ .bmdma_start = pata_fsl_bmdma_start, ++#endif ++ ++ .sff_data_xfer = ata_sff_data_xfer_noirq, ++ .qc_prep = ata_noop_qc_prep, ++ ++ .port_start = pata_fsl_port_start, ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ .bmdma_stop = pata_fsl_bmdma_stop, ++ .bmdma_status = pata_fsl_bmdma_status, ++#endif ++}; ++ ++static void fsl_setup_port(struct ata_ioports *ioaddr) ++{ ++ unsigned int shift = 2; ++ ++ ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift); ++ ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift); ++ ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift); ++ ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift); ++ ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift); ++ ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift); ++ ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift); ++ ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift); ++ ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift); ++ ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift); ++} ++ ++/** ++ * pata_fsl_probe - attach a platform interface ++ * @pdev: platform device ++ * ++ * Register a platform bus integrated ATA host controller ++ * ++ * The 3 platform device resources are used as follows: ++ * ++ * - I/O Base (IORESOURCE_MEM) virt. addr. of ATA controller regs ++ * - CTL Base (IORESOURCE_MEM) unused ++ * - IRQ (IORESOURCE_IRQ) platform IRQ assigned to ATA ++ * ++ */ ++static int __devinit pata_fsl_probe(struct platform_device *pdev) ++{ ++ struct resource *io_res; ++ struct ata_host *host; ++ struct ata_port *ap; ++ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) ++ pdev->dev.platform_data; ++ struct pata_fsl_priv *priv; ++ u8 *ata_regs; ++ int ret; ++ ++ DPRINTK("ENTER\n"); ++ /* ++ * Get an ata_host structure for this device ++ */ ++ host = ata_host_alloc(&pdev->dev, 1); ++ if (!host) ++ return -ENOMEM; ++ ap = host->ports[0]; ++ /* ++ * Allocate private data ++ */ ++ priv = kzalloc(sizeof(struct pata_fsl_priv), GFP_KERNEL); ++ if (priv == NULL) { ++ /* free(host); */ ++ return -ENOMEM; ++ } ++ host->private_data = priv; ++ ++ /* ++ * Set up resources ++ */ ++ if (unlikely(pdev->num_resources != 3)) { ++ dev_err(&pdev->dev, "invalid number of resources\n"); ++ return -EINVAL; ++ } ++ ++ io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ata_regs = (u8 *)io_res->start; ++ priv->fsl_ata_regs = ata_regs; ++ ap->ioaddr.cmd_addr = (void *)(ata_regs + FSL_ATA_DRIVE_DATA); ++ ap->ioaddr.ctl_addr = (void *)(ata_regs + FSL_ATA_DRIVE_CONTROL); ++ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; ++ ap->ops = &pata_fsl_port_ops; ++ ap->pio_mask = 0x3F; ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ ap->mwdma_mask = 0x07; ++ ap->udma_mask = 0x1F; ++/* ap->udma_mask = plat->udma_mask; */ ++/* pata_fsl_sht.sg_tablesize = plat->max_sg; */ ++#else ++ ap->mwdma_mask = 0x00; ++ ap->udma_mask = 0x00; ++#endif ++ fsl_setup_port(&ap->ioaddr); ++ ++ /* ++ * Do platform-specific initialization (e.g. allocate pins, ++ * turn on clock). After this call it is assumed that ++ * plat->get_clk_rate() can be called to calculate ++ * timing. ++ */ ++ if (plat->init && plat->init(pdev)) { ++ /* REVISIT: don't leak what ata_host_alloc() allocated */ ++ return -ENODEV; ++ } ++ ++ /* Deassert the reset bit to enable the interface */ ++ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL); ++ ++ /* Set initial timing and mode */ ++ set_ata_bus_timing(XFER_PIO_4, pdev); ++ ++#ifdef CONFIG_FSL_PATA_USE_DMA ++ /* get DMA ready */ ++ pata_fsl_dma_init(ap); ++#endif ++ ++ /* ++ * Enable the ATA INTRQ interrupt from the bus, but ++ * only allow the CPU to see it (INTRQ2) at this point. ++ * INTRQ1, which goes to the DMA, will be enabled later. ++ */ ++#if 0 ++ __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN); ++#else ++ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN); ++#endif ++ ++ /* activate */ ++ ret = ata_host_activate(host, platform_get_irq(pdev, 0), ++ ata_sff_interrupt, 0, &pata_fsl_sht); ++ DPRINTK("EXIT ret=%d\n", ret); ++ return ret; ++} ++ ++/** ++ * pata_fsl_remove - unplug a platform interface ++ * @pdev: platform device ++ * ++ * A platform bus ATA device has been unplugged. Perform the needed ++ * cleanup. Also called on module unload for any active devices. ++ */ ++static int __devexit pata_fsl_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct pata_fsl_priv *priv = host->private_data; ++ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) ++ pdev->dev.platform_data; ++ u8 *ata_regs = priv->fsl_ata_regs; ++ ++#if 0 ++ __raw_writel(0, ata_regs + FSL_ATA_INT_EN); /* Disable interrupts */ ++#else ++ WRITE_ATA8(0, FSL_ATA_INT_EN); /* Disable interrupts */ ++#endif ++ ++ ata_host_detach(host); ++ ++ if (plat->exit) ++ plat->exit(); ++ ++ kfree(priv); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int pata_fsl_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct pata_fsl_priv *priv = host->private_data; ++ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) ++ pdev->dev.platform_data; ++ u8 *ata_regs = priv->fsl_ata_regs; ++ ++ /* Disable interrupts. */ ++#if 0 ++ __raw_writel(0, ata_regs + FSL_ATA_INT_EN); ++#else ++ WRITE_ATA8(0, FSL_ATA_INT_EN); ++#endif ++ ++ if (plat->exit) ++ plat->exit(); ++ ++ return 0; ++} ++ ++static int pata_fsl_resume(struct platform_device *pdev) ++{ ++ struct ata_host *host = dev_get_drvdata(&pdev->dev); ++ struct pata_fsl_priv *priv = host->private_data; ++ struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) ++ pdev->dev.platform_data; ++ u8 *ata_regs = priv->fsl_ata_regs; ++ ++ if (plat->init && plat->init(pdev)) ++ return -ENODEV; ++ /* Deassert the reset bit to enable the interface */ ++#if 0 ++ __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL); ++#else ++ WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL); ++#endif ++ ++ /* Set initial timing and mode */ ++ set_ata_bus_timing(XFER_PIO_4, pdev); ++ ++ /* ++ * Enable hardware interrupts. ++ */ ++#if 0 ++ __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN); ++#else ++ WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN); ++#endif ++ ++ return 0; ++} ++#endif ++ ++static struct platform_driver pata_fsl_driver = { ++ .probe = pata_fsl_probe, ++ .remove = __devexit_p(pata_fsl_remove), ++#ifdef CONFIG_PM ++ .suspend = pata_fsl_suspend, ++ .resume = pata_fsl_resume, ++#endif ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init pata_fsl_init(void) ++{ ++ int ret; ++ ++ DPRINTK("ENTER\n"); ++ ret = platform_driver_register(&pata_fsl_driver); ++ DPRINTK("EXIT ret=%d\n", ret); ++ return ret; ++} ++ ++static void __exit pata_fsl_exit(void) ++{ ++ platform_driver_unregister(&pata_fsl_driver); ++} ++module_init(pata_fsl_init); ++module_exit(pata_fsl_exit); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("low-level driver for Freescale ATA"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); diff --git a/target/linux/coldfire/patches/038-Add-PCI-Framebuffer-support-for-Silicon-Motion-s-Lyn.patch b/target/linux/coldfire/patches/038-Add-PCI-Framebuffer-support-for-Silicon-Motion-s-Lyn.patch new file mode 100644 index 000000000..bd0462926 --- /dev/null +++ b/target/linux/coldfire/patches/038-Add-PCI-Framebuffer-support-for-Silicon-Motion-s-Lyn.patch @@ -0,0 +1,1287 @@ +From d984818481320cf4a1b44cefbc99448205cc7673 Mon Sep 17 00:00:00 2001 +From: Jingchang Lu <b35083@freescale.com> +Date: Thu, 4 Aug 2011 09:59:48 +0800 +Subject: [PATCH 38/52] Add PCI Framebuffer support for Silicon Motion's Lynx family + +The driver may support SM710, SM712, SM720, and the SM712 +has been tested on ColdFire M547X_8XEVB. + +Signed-off-by: Alison Wang <b18965@freescale.com> +Signed-off-by: Jingchang Lu <b35083@freescale.com> +--- + drivers/video/Kconfig | 15 + + drivers/video/Makefile | 1 + + drivers/video/console/bitblit.c | 12 + + drivers/video/console/fbcon.c | 4 + + drivers/video/fbmem.c | 2 +- + drivers/video/smifb.c | 963 +++++++++++++++++++++++++++++++++++++++ + drivers/video/smifb.h | 150 ++++++ + include/linux/fb.h | 18 +- + 8 files changed, 1163 insertions(+), 2 deletions(-) + create mode 100644 drivers/video/smifb.c + create mode 100644 drivers/video/smifb.h + +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -204,6 +204,7 @@ config FB_WMT_GE_ROPS + config FB_DEFERRED_IO + bool + depends on FB ++ default y + + config FB_HECUBA + tristate +@@ -262,6 +263,20 @@ config FB_TILEBLITTING + comment "Frame buffer hardware drivers" + depends on FB + ++config FB_SMI ++ tristate "Silicon Motion Lynx support" ++ depends on FB && PCI ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ ---help--- ++ This enables support for the Silicon Motion Lynx family of graphic ++ chips. ++ ++ The SM712 has been tested on ColdFire M547X_8Xevb. ++ ++ If unsure, say N. ++ + config FB_CIRRUS + tristate "Cirrus Logic support" + depends on FB && (ZORRO || PCI) +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_FB_DEFERRED_IO) += fb_def + obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o + + # Hardware specific drivers go first ++obj-$(CONFIG_FB_SMI) += smifb.o + obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o + obj-$(CONFIG_FB_ARC) += arcfb.o + obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o +--- a/drivers/video/console/bitblit.c ++++ b/drivers/video/console/bitblit.c +@@ -79,7 +79,11 @@ static inline void bit_putcs_aligned(str + u32 d_pitch, u32 s_pitch, u32 cellsize, + struct fb_image *image, u8 *buf, u8 *dst) + { ++#ifndef CONFIG_COLDFIRE + u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; ++#else ++ u32 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; ++#endif + u32 idx = vc->vc_font.width >> 3; + u8 *src; + +@@ -112,7 +116,11 @@ static inline void bit_putcs_unaligned(s + struct fb_image *image, u8 *buf, + u8 *dst) + { ++#ifndef CONFIG_COLDFIRE + u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; ++#else ++ u32 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; ++#endif + u32 shift_low = 0, mod = vc->vc_font.width % 8; + u32 shift_high = 8; + u32 idx = vc->vc_font.width >> 3; +@@ -239,7 +247,11 @@ static void bit_cursor(struct vc_data *v + { + struct fb_cursor cursor; + struct fbcon_ops *ops = info->fbcon_par; ++#ifndef CONFIG_COLDFIRE + unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; ++#else ++ unsigned long charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; ++#endif + int w = DIV_ROUND_UP(vc->vc_font.width, 8), c; + int y = real_y(ops->p, vc->vc_y); + int attribute, use_sw = (vc->vc_cursor_type & 0x10); +--- a/drivers/video/console/fbcon.c ++++ b/drivers/video/console/fbcon.c +@@ -2636,7 +2636,11 @@ static int fbcon_set_palette(struct vc_d + { + struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]]; + int i, j, k, depth; ++#ifndef CONFIG_COLDFIRE + u8 val; ++#else ++ u32 val; ++#endif + + if (fbcon_is_inactive(vc, info)) + return -EINVAL; +--- a/drivers/video/fbmem.c ++++ b/drivers/video/fbmem.c +@@ -1433,7 +1433,7 @@ static int fb_check_foreignness(struct f + + fi->flags &= ~FBINFO_FOREIGN_ENDIAN; + +-#ifdef __BIG_ENDIAN ++#if defined(__BIG_ENDIAN) && !defined(CONFIG_COLDFIRE) + fi->flags |= foreign_endian ? 0 : FBINFO_BE_MATH; + #else + fi->flags |= foreign_endian ? FBINFO_BE_MATH : 0; +--- /dev/null ++++ b/drivers/video/smifb.c +@@ -0,0 +1,963 @@ ++/*************************************************************************** ++ smifb.c - Silicon Motion, Inc. LynxEM+ frame buffer device ++ ------------------- ++ begin : Thu Aug 9 2001 ++ copyright : (C) 2001 by Szu-Tao Huang ++ email : johuang@siliconmotion.com ++ ***************************************************************************/ ++/* Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.*/ ++/*************************************************************************** ++ * * ++ * This program is free software; you can redistribute it and/or modify * ++ * it under the terms of the GNU General Public License as published by * ++ * the Free Software Foundation; either version 2 of the License, or * ++ * (at your option) any later version. * ++ * * ++ ***************************************************************************/ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/errno.h> ++#include <linux/string.h> ++#include <linux/mm.h> ++#include <linux/tty.h> ++#include <linux/slab.h> ++#include <linux/delay.h> ++#include <linux/fb.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++ ++#include <linux/io.h> ++#include <asm/irq.h> ++#include <asm/pgtable.h> ++#include <asm/system.h> ++#include <linux/uaccess.h> ++ ++#include "console/fbcon.h" ++ ++/* ++#include <video/fbcon.h> ++#include <video/fbcon-cfb8.h> ++#include <video/fbcon-cfb16.h> ++#include <video/fbcon-cfb24.h> ++*/ ++ ++#include <linux/fb.h> ++/*point to virtual Memory Map IO starting address*/ ++static char *SMIRegs; ++/*point to virtual video memory starting address*/ ++static char *SMILFB; ++/*used to record hardware information*/ ++static struct par_info hw; ++#ifdef DEBUG_FB ++#define debug_printk(x...) printk(x) ++#else ++#define debug_printk(x...) ++#endif ++#include "smifb.h" ++ ++struct ModeInit VGAMode[numVGAModes] = { ++ { ++ /* mode#0: 640 x 480 8Bpp 60Hz */ ++ 640, 480, 8, 60, ++ /* Init_MISC */ ++ 0xE3, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, ++ 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, ++ 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, ++ 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, ++ 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, ++ 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, ++ 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, ++ 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, ++ }, ++ }, ++ { ++ /* mode#1: 640 x 480 16Bpp 60Hz */ ++ 640, 480, 16, 60, ++ /* Init_MISC */ ++ 0xE3, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, ++ 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, ++ 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, ++ 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, ++ 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, ++ 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, ++ 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, ++ 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, ++ }, ++ }, ++ { ++ /* mode#2: 640 x 480 24Bpp 60Hz */ ++ 640, 480, 24, 60, ++ /* Init_MISC */ ++ 0xE3, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, ++ 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, ++ 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, ++ 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, ++ 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, ++ 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, ++ 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, ++ 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, ++ }, ++ }, ++ {/* mode#3: 800 x 600 8Bpp 60Hz */ ++ 800, 600, 8, 60, ++ 0x2B, /* Init_MISC */ ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x24, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24, ++ 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24, ++ 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, ++ 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24, ++ 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, ++ 0x02, 0x45, 0x30, 0x35, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x87, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24, ++ 0x90, 0x01, 0x2C, 0x01, 0xFF, 0x00, 0x24, 0x24, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, ++ 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, ++ 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, ++ 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, ++ 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, ++ }, ++ }, ++ {/* mode#4: 800 x 600 16Bpp 60Hz */ ++ 800, 600, 16, 60, ++ /* Init_MISC */ ++ 0x2B, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x24, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24, ++ 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24, ++ 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, ++ 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24, ++ 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, ++ 0x02, 0x45, 0x30, 0x35, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, ++ 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, ++ 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, ++ 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, ++ 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, ++ }, ++ }, ++ {/* mode#5: 800 x 600 24Bpp 60Hz */ ++ 800, 600, 24, 60, ++ 0x2B, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36, ++ 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, ++ 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, ++ 0x02, 0x45, 0x30, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, ++ 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, ++ 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, ++ 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, ++ 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, ++ }, ++ }, ++}; ++ ++static void smi_set_timing(struct smifb_info *sfb, struct par_info *hw) ++{ ++ int i = 0, j = 0; ++ u32 m_nScreenStride; ++ debug_printk("set timing:hw->width %x,hw->height %x,bpp %x\n", ++ hw->width, hw->height, sfb->fb.var.bits_per_pixel); ++ ++ for (j = 0; j < numVGAModes; j++) { ++ if (VGAMode[j].mmSizeX == hw->width && ++ VGAMode[j].mmSizeY == hw->height && ++ VGAMode[j].bpp == sfb->fb.var.bits_per_pixel && ++ VGAMode[j].hz == hw->hz) { ++ debug_printk("VGAMode[%d]\n", j); ++ smi_mmiowb(0x0, 0x3c6); ++ ++ smi_seqw(0, 0x1); ++ ++ smi_mmiowb(VGAMode[j].Init_MISC, 0x3c2); ++ ++ for (i = 0; i < SIZE_SR00_SR04; i++) { ++ /* init SEQ register SR00 - SR04 */ ++ smi_seqw(i, ++ VGAMode[j].Init_SR00_SR04[i]); ++ } ++ ++ for (i = 0; i < SIZE_SR10_SR24; i++) { ++ /* init SEQ register SR10 - SR24*/ ++ smi_seqw(i + 0x10, ++ VGAMode[j].Init_SR10_SR24[i]); ++ } ++ ++ for (i = 0; i < SIZE_SR30_SR75; i++) { ++ /* init SEQ register SR30 - SR75*/ ++ if (((i + 0x30) != 0x62) && ++ ((i + 0x30) != 0x6a) && ++ ((i + 0x30) != 0x6b)) ++ smi_seqw(i + 0x30, ++ VGAMode[j].Init_SR30_SR75[i]); ++ } ++ for (i = 0; i < SIZE_SR80_SR93; i++) { ++ /* init SEQ register SR80 - SR93*/ ++ smi_seqw(i + 0x80, ++ VGAMode[j].Init_SR80_SR93[i]); ++ } ++ for (i = 0; i < SIZE_SRA0_SRAF; i++) { ++ /* init SEQ register SRA0 - SRAF */ ++ smi_seqw(i + 0xa0, ++ VGAMode[j].Init_SRA0_SRAF[i]); ++ } ++ ++ for (i = 0; i < SIZE_GR00_GR08; i++) { ++ /* init Graphic register GR00 - GR08*/ ++ smi_grphw(i, ++ VGAMode[j].Init_GR00_GR08[i]); ++ } ++ ++ for (i = 0; i < SIZE_AR00_AR14; i++) { ++ /* init Attribute register AR00 - AR14*/ ++ smi_attrw(i, ++ VGAMode[j].Init_AR00_AR14[i]); ++ } ++ ++ for (i = 0; i < SIZE_CR00_CR18; i++) { ++ /* init CRTC register CR00 - CR18 */ ++ smi_crtcw(i, ++ VGAMode[j].Init_CR00_CR18[i]); ++ } ++ ++ for (i = 0; i < SIZE_CR30_CR4D; i++) { ++ /* init CRTC register CR30 - CR4D*/ ++ smi_crtcw(i + 0x30, ++ VGAMode[j].Init_CR30_CR4D[i]); ++ } ++ ++ for (i = 0; i < SIZE_CR90_CRA7; i++) { ++ /*init CRTC register CR90 - CRA7*/ ++ smi_crtcw(i + 0x90, ++ VGAMode[j].Init_CR90_CRA7[i]); ++ } ++ } ++ } ++ smi_mmiowb(0x67, 0x3c2); ++ /* set VPR registers */ ++ writel(0x0, hw->m_pVPR+0x0C); ++ writel(0x0, hw->m_pVPR+0x40); ++ /* set data width */ ++ m_nScreenStride = (hw->width * sfb->fb.var.bits_per_pixel) / 64; ++ switch (sfb->fb.var.bits_per_pixel) { ++ case 8: ++ writel(0x0, hw->m_pVPR+0x0); ++ break; ++ case 16: ++ writel(0x00020000, hw->m_pVPR+0x0); ++ break; ++ case 24: ++ writel(0x00040000, hw->m_pVPR+0x0); ++ break; ++ } ++ writel((u32)(((m_nScreenStride + 2) << 16) | ++ m_nScreenStride), hw->m_pVPR+0x10); ++} ++ ++/* ++ * Set the color palette ++ */ ++static int ++smifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, ++ u_int trans, struct fb_info *info) ++{ ++ struct smifb_info *sfb = (struct smifb_info *)info; ++ u32 *pal; ++ ++ switch (sfb->fb.fix.visual) { ++ case FB_VISUAL_TRUECOLOR: /* RGB 5:6:5 True Colour */ ++ pal = sfb->fb.pseudo_palette; ++ /* System has 16 default color */ ++ if (regno >= 16) ++ return 1; ++ ++ pal[regno] = (red & 0xf800) | ++ ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * smifb_decode_var(): ++ * Get the video params out of 'var'. If a value doesn't fit, round it up, ++ * if it's too big, return -EINVAL. ++ * ++ * Suggestion: Round up in the following order: bits_per_pixel, xres, ++ * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, ++ * bitfields, horizontal timing, vertical timing. ++ */ ++static int smifb_decode_var(struct fb_var_screeninfo *var, ++ struct smifb_info *sfb, struct par_info *hw) ++{ ++ hw->width = var->xres; ++ hw->height = var->yres; ++ hw->hz = 60; ++ ++ return 0; ++} ++ ++static int smifb_set_par(struct fb_info *info) ++{ ++ struct smifb_info *sfb = (struct smifb_info *)info; ++ int err, chgvar = 0; ++ struct fb_var_screeninfo *var = &info->var; ++ struct fb_cmap *cmap; ++ ++ ++ /* ++ * Decode var contents into a par structure, adjusting any ++ * out of range values. ++ */ ++ err = smifb_decode_var(var, sfb, &hw); ++ if (err) ++ return err; ++ ++ if (hw.width != var->xres) ++ chgvar = 1; ++ if (hw.height != var->yres) ++ chgvar = 1; ++ ++ var->activate &= ~FB_ACTIVATE_ALL; ++ ++ smi_set_timing(sfb, &hw); ++ ++ sfb->palette_size = var->bits_per_pixel == 8 ? 256 : 16; ++ cmap = (struct fb_cmap *)fb_default_cmap(sfb->palette_size); ++ fb_set_cmap(cmap, &sfb->fb); ++ ++ return 0; ++} ++ ++static int smifb_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ var->bits_per_pixel += 7; ++ var->bits_per_pixel &= ~7; ++ ++ var->xres_virtual = ++ var->xres_virtual < var->xres ? var->xres : var->xres_virtual; ++ var->yres_virtual = ++ var->yres_virtual < var->yres ? var->yres : var->yres_virtual; ++ debug_printk("var->bits_per_pixel %x\n", var->bits_per_pixel); ++ switch (var->bits_per_pixel) { ++ case 8: ++ case 16: /* RGB 565 */ ++ case 24: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (var->bits_per_pixel) { ++ case 16: ++ var->red.offset = 11; ++ var->red.length = 5; ++ var->green.offset = 5; ++ var->green.length = 6; ++ var->blue.offset = 0; ++ var->blue.length = 5; ++ ++ info->fix.visual = FB_VISUAL_TRUECOLOR; ++ info->fix.line_length = var->xres * 2; ++ ++ break; ++ default: ++ return -EINVAL; ++ /* We don't support anything other than 16bpp for now. --NL */ ++ break; ++ } ++ return 0; ++ ++ /*smifb_set_color_bitfields(var);*/ ++ ++ return 0; ++} ++ ++/* ++ * Formal definition of the VESA spec: ++ * On ++ * This refers to the state of the display when it is in full operation ++ * Stand-By ++ * This defines an optional operating state of minimal power reduction with ++ * the shortest recovery time ++ * Suspend ++ * This refers to a level of power management in which substantial power ++ * reduction is achieved by the display. The display can have a longer ++ * recovery time from this state than from the Stand-by state ++ * Off ++ * This indicates that the display is consuming the lowest level of power ++ * and is non-operational. Recovery from this state may optionally require ++ * the user to manually power on the monitor ++ * ++ * Now, the fbdev driver adds an additional state, (blank), where they ++ * turn off the video (maybe by colormap tricks), but don't mess with the ++ * video itself: think of it semantically between on and Stand-By. ++ * ++ * So here's what we should do in our fbdev blank routine: ++ * ++ * VESA_NO_BLANKING (mode 0) Video on, front/back light on ++ * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off ++ * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off ++ * VESA_POWERDOWN (mode 3) Video off, front/back light off ++ * ++ * This will match the matrox implementation. ++ */ ++/* ++ * smifb_blank(): ++ * Blank the display by setting all palette values to zero. Note, the ++ * 12 and 16 bpp modes don't really use the palette, so this will not ++ * blank the display in all modes. ++ */ ++static int smifb_blank(int blank, struct fb_info *info) ++{ ++/* struct smifb_info *sfb = (struct smifb_info *)info; */ ++#if 0 ++ switch (blank) { ++ case VESA_POWERDOWN: ++ case VESA_VSYNC_SUSPEND: ++ case VESA_HSYNC_SUSPEND: ++ case VESA_NO_BLANKING: ++ } ++#endif ++ return 1; ++} ++ ++static struct fb_ops smifb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = smifb_check_var, ++ .fb_set_par = smifb_set_par, ++ .fb_setcolreg = smifb_setcolreg, ++ .fb_blank = smifb_blank, ++ ++ /* Accelerated functions, using softversions, per se */ ++ .fb_fillrect = cfb_fillrect, ++ .fb_copyarea = cfb_copyarea, ++ .fb_imageblit = cfb_imageblit, ++ .fb_cursor = soft_cursor, ++}; ++ ++/* ++ * Alloc struct smifb_info and assign the default value ++ */ ++static struct smifb_info * __devinit ++smi_alloc_fb_info(struct pci_dev *dev, char *name) ++{ ++ struct smifb_info *sfb; ++ ++ sfb = kmalloc(sizeof(struct smifb_info) + sizeof(u32) * 16, GFP_KERNEL); ++ ++ if (!sfb) ++ return NULL; ++ ++ memset(sfb, 0, sizeof(struct smifb_info)); ++ ++ sfb->currcon = -1; ++ sfb->dev = dev; ++ ++ strcpy(sfb->fb.fix.id, name); ++ ++ sfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ sfb->fb.fix.type_aux = 0; ++ sfb->fb.fix.xpanstep = 0; ++ sfb->fb.fix.ypanstep = 0; ++ sfb->fb.fix.ywrapstep = 0; ++ sfb->fb.fix.accel = FB_ACCEL_NONE; ++ ++ sfb->fb.var.nonstd = 0; ++ sfb->fb.var.activate = FB_ACTIVATE_NOW; ++ sfb->fb.var.height = -1; ++ sfb->fb.var.width = -1; ++ sfb->fb.var.accel_flags = 0; ++ sfb->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ ++ sfb->fb.fbops = &smifb_ops; ++ sfb->fb.flags = FBINFO_FLAG_DEFAULT; ++ sfb->fb.node = -1; ++ sfb->fb.pseudo_palette = (void *)(&sfb->palette_size + 1); ++ ++ return sfb; ++} ++ ++/* ++ * Unmap in the memory mapped IO registers ++ * ++ */ ++ ++static void __devinit ++smi_unmap_mmio(struct smifb_info *sfb) ++{ ++ if (sfb && SMILFB) { ++ iounmap(SMILFB); ++ SMIRegs = NULL; ++ } ++} ++ ++/* ++ * Map in the screen memory ++ * ++ */ ++static int __devinit ++smi_map_smem(struct smifb_info *sfb, struct pci_dev *dev, u_long smem_len) ++{ ++ sfb->fb.fix.smem_start = pci_resource_start(dev, 0); ++ sfb->fb.fix.smem_len = smem_len; ++ ++ debug_printk("%s:smem %x,len %x\n", __func__, ++ sfb->fb.fix.smem_start, ++ sfb->fb.fix.smem_len); ++ ++ sfb->fb.screen_base = SMILFB; ++ ++ if (!sfb->fb.screen_base) { ++ printk("%s: unable to map screen memory\n", sfb->fb.fix.id); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Unmap in the screen memory ++ * ++ */ ++static void __devinit ++smi_unmap_smem(struct smifb_info *sfb) ++{ ++ if (sfb && sfb->fb.screen_base) { ++ iounmap(sfb->fb.screen_base); ++ sfb->fb.screen_base = NULL; ++ } ++} ++ ++/* ++ * We need to wake up the LynxEM+, and make sure its in linear memory mode. ++ */ ++static inline void __devinit ++smi_init_hw(void) ++{ ++ /* The delays prevent the ColdFire PCI host from locking up. :/ --NL */ ++ udelay(1000); ++ outb(0x18, 0x3c4); ++ ++ udelay(1000); ++ outb(0x11, 0x3c5); ++ udelay(1000); ++ ++ debug_printk("%s: 0x3c4 =%x 0x3c5 %x\n", ++ __func__, inw(0x3c4), inw(0x3c5)); ++} ++ ++static void __devinit ++smi_free_fb_info(struct smifb_info *sfb) ++{ ++ if (sfb) { ++ fb_alloc_cmap(&sfb->fb.cmap, 0, 0); ++ kfree(sfb); ++ } ++} ++ ++ ++u16 SMI_ChipIDs[numChipIDs] = {0x710, 0x712, 0x720}; ++ ++int __devinit smifb_init(struct pci_dev *pdev, const struct pci_device_id *ent) ++{ ++ struct smifb_info *sfb; ++ unsigned long smem_size; ++ char name[16]; ++ int err; ++ char *m_pLAW; ++ unsigned long m_pLAWPhysical; ++ ++ debug_printk("%s start\n", __func__); ++ sprintf(name, "smifb"); ++ hw.chipID = pdev->device; ++ err = -ENOMEM; ++ sfb = smi_alloc_fb_info(pdev, name); ++ if (!sfb) ++ goto failed; ++ ++ smi_init_hw(); ++ ++ /* Map address and memory detection */ ++ m_pLAWPhysical = pci_resource_start(pdev, 0); ++ printk(KERN_INFO "%s:Physical addr %x,hw.chipID %x\n", ++ __func__, (unsigned int)m_pLAWPhysical, ++ (unsigned int)hw.chipID); ++ switch (hw.chipID) { ++ case 0x710: ++ case 0x712: ++ sfb->fb.fix.mmio_start = m_pLAWPhysical + 0x00700000; ++ sfb->fb.fix.mmio_len = 0x00100000; ++ ++ hw.m_pLFB = SMILFB = ++ ioremap(m_pLAWPhysical, 0x00800000); ++ debug_printk("%s:SMILFB%x\n", __func__, SMILFB); ++ hw.m_pMMIO = SMIRegs = SMILFB + 0x00700000; ++ hw.m_pDPR = hw.m_pLFB + 0x00408000; ++ hw.m_pVPR = hw.m_pLFB + 0x0040c000; ++ ++ if (!SMIRegs) { ++ printk(KERN_ERR "%s: unable to map " ++ "memory mapped IO\n", sfb->fb.fix.id); ++ return -ENOMEM; ++ } ++ ++ smi_seqw(0x62, 0x7A); ++ smi_seqw(0x6a, 0x0c); ++ smi_seqw(0x6b, 0x02); ++ smem_size = 0x00400000; ++ ++ /* LynxEM+ memory dection */ ++ *(u32 *)(SMILFB + 4) = 0xAA551133; ++ if (*(u32 *)(SMILFB + 4) != 0xAA551133) { ++ smem_size = 0x00200000; ++ /* Program the MCLK to 130 MHz */ ++ smi_seqw(0x6a, 0x12); ++ smi_seqw(0x6b, 0x02); ++ smi_seqw(0x62, 0x3e); ++ } ++ break; ++ case 0x720: ++ sfb->fb.fix.mmio_start = m_pLAWPhysical + 0x000c0000; ++ sfb->fb.fix.mmio_len = 0x00040000; ++ ++ m_pLAW = ioremap(m_pLAWPhysical, 0x00a00000); ++ hw.m_pLFB = SMILFB = m_pLAW + 0x00200000; ++ hw.m_pMMIO = SMIRegs = m_pLAW + 0x000c0000; ++ hw.m_pDPR = m_pLAW; ++ hw.m_pVPR = m_pLAW + 0x800; ++ ++ smi_seqw(0x62, 0xff); ++ smi_seqw(0x6a, 0x0d); ++ smi_seqw(0x6b, 0x02); ++ smem_size = 0x00400000; ++ ++ break; ++ } ++ ++ sfb->fb.var.xres = 640; ++ sfb->fb.var.yres = 480; ++ sfb->fb.var.bits_per_pixel = 16; ++ ++ sfb->fb.var.xres_virtual = sfb->fb.var.xres; ++ ++ sfb->fb.var.yres_virtual = sfb->fb.var.yres; ++ ++ sfb->fb.flags = FBINFO_FLAG_DEFAULT; ++ ++ debug_printk("%s:smem_size %x\n", __func__, smem_size); ++ err = smi_map_smem(sfb, pdev, smem_size); ++ debug_printk("%s:smi_map_smem error %x\n", __func__, err); ++ if (err) ++ goto failed; ++ ++ fb_set_var(&sfb->fb, &sfb->fb.var); ++ smifb_check_var(&sfb->fb.var, &sfb->fb); ++ smifb_set_par((struct fb_info *)sfb); ++ debug_printk("%s:register_framebuffer\n", __func__); ++ err = register_framebuffer(&sfb->fb); ++ if (err < 0) ++ goto failed; ++ ++ printk(KERN_INFO "Silicon Motion, Inc. " ++ "LynxEM+ Init complete.\n"); ++ return 0; ++ ++failed: ++ smi_unmap_smem(sfb); ++ smi_unmap_mmio(sfb); ++ smi_free_fb_info(sfb); ++ printk(KERN_INFO "Silicon Motion, Inc. " ++ "LynxEM+ Init FAILED.n"); ++ ++ return err; ++} ++ ++static DEFINE_PCI_DEVICE_TABLE(smifb_pci_tbl) = { ++ { 0x126f, 0x710, PCI_ANY_ID, PCI_ANY_ID }, ++ { 0x126f, 0x712, PCI_ANY_ID, PCI_ANY_ID }, ++ { 0x126f, 0x720, PCI_ANY_ID, PCI_ANY_ID }, ++ { 0 } ++}; ++ ++MODULE_DEVICE_TABLE(pci, smifb_pci_tbl); ++ ++struct pci_driver smifb_driver = { ++ .name = "smifb", ++ .id_table = smifb_pci_tbl, ++ .probe = smifb_init, ++}; ++ ++int __init smi_init(void) ++{ ++ /*return pci_module_init(&smifb_driver);*/ ++ return pci_register_driver(&smifb_driver); ++} ++ ++module_init(smi_init); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/video/smifb.h +@@ -0,0 +1,150 @@ ++/*************************************************************************** ++ smifb.h - SiliconMotion LynxEM+ frame buffer device ++ ------------------- ++ begin : Thu Aug 9 2001 ++ copyright : (C) 2001 by Szu-Tao Huang ++ email : johuang@siliconmotion.com ++ ***************************************************************************/ ++/* Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.*/ ++/*************************************************************************** ++ * * ++ * This program is free software; you can redistribute it and/or modify * ++ * it under the terms of the GNU General Public License as published by * ++ * the Free Software Foundation; either version 2 of the License, or * ++ * (at your option) any later version. * ++ * * ++ ***************************************************************************/ ++ ++#define smi_mmiowb(dat, reg) writeb(dat, SMIRegs + reg) ++#define smi_mmioww(dat, reg) writew(dat, SMIRegs + reg) ++#define smi_mmiowl(dat, reg) writel(dat, SMIRegs + reg) ++ ++#define smi_mmiorb(reg) readb(SMIRegs + reg) ++#define smi_mmiorw(reg) readw(SMIRegs + reg) ++#define smi_mmiorl(reg) readl(SMIRegs + reg) ++ ++#define SIZE_SR00_SR04 (0x04 - 0x00 + 1) ++#define SIZE_SR10_SR24 (0x24 - 0x10 + 1) ++#define SIZE_SR30_SR75 (0x75 - 0x30 + 1) ++#define SIZE_SR80_SR93 (0x93 - 0x80 + 1) ++#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1) ++#define SIZE_GR00_GR08 (0x08 - 0x00 + 1) ++#define SIZE_AR00_AR14 (0x14 - 0x00 + 1) ++#define SIZE_CR00_CR18 (0x18 - 0x00 + 1) ++#define SIZE_CR30_CR4D (0x4D - 0x30 + 1) ++#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1) ++#define SIZE_VPR (0x6C + 1) ++#define SIZE_DPR (0x44 + 1) ++ ++#define numVGAModes 6 ++#define numChipIDs 3 ++ ++#define NR_PALETTE 256 ++#define NR_RGB 2 ++ ++/* ++ * Minimum X and Y resolutions ++ */ ++#define MIN_XRES 640 ++#define MIN_YRES 480 ++ ++static inline void smi_crtcw(int reg, int val) ++{ ++ smi_mmiowb(reg, 0x3d4); ++ smi_mmiowb(val, 0x3d5); ++} ++ ++static inline unsigned int smi_crtcr(int reg) ++{ ++ smi_mmiowb(reg, 0x3d4); ++ return smi_mmiorb(0x3d5); ++} ++ ++static inline void smi_grphw(int reg, int val) ++{ ++ smi_mmiowb(reg, 0x3ce); ++ smi_mmiowb(val, 0x3cf); ++} ++ ++static inline unsigned int smi_grphr(int reg) ++{ ++ smi_mmiowb(reg, 0x3ce); ++ return smi_mmiorb(0x3cf); ++} ++ ++static inline void smi_attrw(int reg, int val) ++{ ++ smi_mmiorb(0x3da); ++ smi_mmiowb(reg, 0x3c0); ++ smi_mmiorb(0x3c1); ++ smi_mmiowb(val, 0x3c0); ++} ++ ++static inline void smi_seqw(int reg, int val) ++{ ++ smi_mmiowb(reg, 0x3c4); ++ smi_mmiowb(val, 0x3c5); ++} ++ ++static inline unsigned int smi_seqr(int reg) ++{ ++ smi_mmiowb(reg, 0x3c4); ++ return smi_mmiorb(0x3c5); ++} ++/* ++* Private structure ++*/ ++struct smifb_info { ++ /* ++ * The following is a pointer to be passed into the ++ * functions below. The modules outside the main ++ * smifb.c driver have no knowledge as to what ++ * is within this structure. ++ */ ++ struct fb_info fb; ++ struct display_switch *dispsw; ++ struct pci_dev *dev; ++ signed int currcon; ++ ++ struct { ++ u8 red, green, blue; ++ } palette[NR_RGB]; ++ ++ u_int palette_size; ++}; ++ ++struct par_info { ++ /* ++ * Hardware ++ */ ++ u16 chipID; ++ char *m_pLFB; ++ char *m_pMMIO; ++ char *m_pDPR; ++ char *m_pVPR; ++ ++ u_int width; ++ u_int height; ++ u_int hz; ++}; ++ ++/*The next structure holds all information relevant for ++ *a specific video mode. ++ */ ++struct ModeInit { ++ int mmSizeX; ++ int mmSizeY; ++ int bpp; ++ int hz; ++ unsigned char Init_MISC; ++ unsigned char Init_SR00_SR04[SIZE_SR00_SR04]; ++ unsigned char Init_SR10_SR24[SIZE_SR10_SR24]; ++ unsigned char Init_SR30_SR75[SIZE_SR30_SR75]; ++ unsigned char Init_SR80_SR93[SIZE_SR80_SR93]; ++ unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF]; ++ unsigned char Init_GR00_GR08[SIZE_GR00_GR08]; ++ unsigned char Init_AR00_AR14[SIZE_AR00_AR14]; ++ unsigned char Init_CR00_CR18[SIZE_CR00_CR18]; ++ unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D]; ++ unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7]; ++}; +--- a/include/linux/fb.h ++++ b/include/linux/fb.h +@@ -935,6 +935,19 @@ static inline struct apertures_struct *a + #define fb_memcpy_fromfb sbus_memcpy_fromio + #define fb_memcpy_tofb sbus_memcpy_toio + ++#elif defined(CONFIG_COLDFIRE) ++#define fb_readb readb ++#define fb_readw readw ++#define fb_readl readl ++#define fb_readq readq ++#define fb_writeb writeb ++#define fb_writew writew ++#define fb_writel writel ++#define fb_writeq writeq ++#define fb_memset memset_io ++#define fb_memcpy_fromfb memcpy_fromio ++#define fb_memcpy_tofb memcpy_toio ++ + #elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__avr32__) || defined(__bfin__) + + #define fb_readb __raw_readb +@@ -1045,6 +1058,9 @@ extern int fb_deferred_io_fsync(struct f + + static inline bool fb_be_math(struct fb_info *info) + { ++#if defined(CONFIG_COLDFIRE) ++ return false; ++#endif + #ifdef CONFIG_FB_FOREIGN_ENDIAN + #if defined(CONFIG_FB_BOTH_ENDIAN) + return info->flags & FBINFO_BE_MATH; +@@ -1054,7 +1070,7 @@ static inline bool fb_be_math(struct fb_ + return false; + #endif /* CONFIG_FB_BOTH_ENDIAN */ + #else +-#ifdef __BIG_ENDIAN ++#if defined(__BIG_ENDIAN) && !defined(CONFIG_COLDFIRE) + return true; + #else + return false; diff --git a/target/linux/coldfire/patches/039-Add-PCI-bus-driver-for-M54455EVB-and-M547X_8X.patch b/target/linux/coldfire/patches/039-Add-PCI-bus-driver-for-M54455EVB-and-M547X_8X.patch new file mode 100644 index 000000000..6b462fee5 --- /dev/null +++ b/target/linux/coldfire/patches/039-Add-PCI-bus-driver-for-M54455EVB-and-M547X_8X.patch @@ -0,0 +1,3051 @@ +From 3f21ef5f7b72937a1ae293e8ba6ebd0bb0b175e3 Mon Sep 17 00:00:00 2001 +From: Jingchang Lu <b35083@freescale.com> +Date: Thu, 4 Aug 2011 09:59:49 +0800 +Subject: [PATCH 39/52] Add PCI bus driver for M54455EVB and M547X_8X + +Signed-off-by: Jingchang Lu <b35083@freescale.com> +--- + arch/m68k/coldfire/m5445x/devices.c | 9 + + arch/m68k/coldfire/m5445x/mcf5445x-pci.c | 721 +++++++++++++++++++++ + arch/m68k/coldfire/m5445x/pci.c | 247 +++++++ + arch/m68k/coldfire/m547x/pci.c | 1023 ++++++++++++++++++++++++++++++ + arch/m68k/coldfire/m547x/pci_dummy.S | 45 ++ + arch/m68k/include/asm/5445x_pci.h | 111 ++++ + arch/m68k/include/asm/548x_pci.h | 99 +++ + arch/m68k/include/asm/pci.h | 6 + + arch/m68k/kernel/bios32_mcf548x.c | 632 ++++++++++++++++++ + drivers/pci/Makefile | 1 + + drivers/pci/access.c | 18 + + drivers/pci/setup-bus.c | 6 + + lib/iomap.c | 4 + + 13 files changed, 2922 insertions(+), 0 deletions(-) + create mode 100644 arch/m68k/coldfire/m5445x/mcf5445x-pci.c + create mode 100644 arch/m68k/coldfire/m5445x/pci.c + create mode 100644 arch/m68k/coldfire/m547x/pci.c + create mode 100644 arch/m68k/coldfire/m547x/pci_dummy.S + create mode 100644 arch/m68k/include/asm/5445x_pci.h + create mode 100644 arch/m68k/include/asm/548x_pci.h + create mode 100644 arch/m68k/kernel/bios32_mcf548x.c + +--- a/arch/m68k/coldfire/m5445x/devices.c ++++ b/arch/m68k/coldfire/m5445x/devices.c +@@ -25,12 +25,15 @@ + #include <linux/spi/mmc_spi.h> + #endif + ++#include <linux/pci.h> ++ + #include <asm/coldfire.h> + #include <asm/mcfsim.h> + #include <asm/mcfuart.h> + #include <asm/mcfqspi.h> + #include <asm/mcfdspi.h> + #include <asm/cf_io.h> ++#include <asm/pci.h> + + /* ATA Interrupt */ + #define IRQ_ATA (64 + 64 + 54) +@@ -517,6 +520,12 @@ void m5445x_uarts_init(void) + + static int __init init_BSP(void) + { ++#ifndef CONFIG_M54455_PCI_initcall ++#if defined(CONFIG_M54455) && defined(CONFIG_PCI) ++ pci_init(); ++ pcibios_init(); ++#endif ++#endif + m5445x_uarts_init(); + platform_add_devices(m5445x_devices, ARRAY_SIZE(m5445x_devices)); + return 0; +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/mcf5445x-pci.c +@@ -0,0 +1,721 @@ ++/* ++ * arch/m68k/coldfire/m5445x/mcf5445x-pci.c ++ * ++ * Coldfire M5445x specific PCI implementation. ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++ ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++#include <linux/pci.h> ++ ++#include <asm/mcfsim.h> ++#include <asm/pci.h> ++#include <asm/irq.h> ++#include <asm/mcf5445x_pciarb.h> ++#include <asm/mcf5445x_pci.h> ++#include <asm/cf_io.h> ++/* ++ * Layout MCF5445x to PCI memory mappings: ++ * ++ * WIN MCF5445x PCI TYPE ++ * --- -------- --- ---- ++ * [0] 0xA0000000 -> 0xACFFFFFF 0xA0000000 -> 0xACFFFFFF MEM ++ * [1] 0xAC000000 -> 0xAEFFFFFF 0xAC000000 -> 0xAEFFFFFF IO ++ * [2] 0xAF000000 -> 0xAFFFFFFF 0xAF000000 -> 0xAFFFFFFF CONFIG ++ */ ++ ++void __iomem *pci_mem_map; ++unsigned long pci_mem_mapsize = 256 * 1024 * 1024; ++ ++#define MCF5445X_PCI_MEM_BASE ((unsigned int)pci_mem_map) ++#define MCF5445X_PCI_MEM_BASE_PHY 0xA0000000 ++#define MCF5445X_PCI_MEM_SIZE 0x0C000000 ++ ++#define MCF5445X_PCI_IO_BASE \ ++ (MCF5445X_PCI_MEM_BASE + MCF5445X_PCI_MEM_SIZE) ++#define MCF5445X_PCI_IO_SIZE 0x03000000 ++ ++#define MCF5445X_PCI_CONFIG_BASE \ ++ (MCF5445X_PCI_IO_BASE + MCF5445X_PCI_IO_SIZE) ++#define MCF5445X_PCI_CONFIG_SIZE 0x01000000 ++ ++#define HOST_IO_BASE \ ++ (MCF5445X_PCI_MEM_BASE + MCF5445X_PCI_MEM_SIZE) ++#define PCI_IO_MASK (MCF5445X_PCI_IO_SIZE - 1) ++ ++#undef DEBUG ++#ifdef DEBUG ++# define DBG(x...) printk(x) ++#else ++# define DBG(x...) ++#endif ++ ++/* PCI Bus memory resource block */ ++struct resource pci_iomem_resource = { ++ .name = "PCI memory space", ++ .flags = IORESOURCE_MEM, ++}; ++ ++/* PCI Bus ioport resource block */ ++struct resource pci_ioport_resource = { ++ .name = "PCI I/O space", ++ .flags = IORESOURCE_IO, ++}; ++ ++/* ++ * The M54455EVB multiplexes all the PCI interrupts via ++ * the FPGA and routes them to a single interrupt. The ++ * PCI spec requires all PCI interrupt routines be smart ++ * enough to sort out their own interrupts. ++ * The interrupt source from the FPGA is configured ++ * to EPORT 3. ++ */ ++#define MCF5445X_PCI_IRQ 0x43 ++ ++#define PCI_SLOTS 4 ++ ++/* ++ * FPGA Info ++ */ ++#define FPGA_PCI_IRQ_ENABLE (u32 *)0x09000000 ++#define FPGA_PCI_IRQ_STATUS (u32 *)0x09000004 ++#define FPGA_PCI_IRQ_ROUTE (u32 *)0x0900000c ++#define FPGA_SEVEN_LED (u32 *)0x09000014 ++ ++ ++/* ++ * mcf5445x_conf_device(struct pci_dev *dev) ++ * ++ * Machine dependent Configure the given device. ++ * ++ * Parameters: ++ * ++ * dev - the pci device. ++ */ ++void ++mcf5445x_conf_device(struct pci_dev *dev) ++{ ++ set_fpga(FPGA_PCI_IRQ_ENABLE, 0x0f); ++} ++ ++/* ++ * int mcf5445x_pci_config_read(unsigned int seg, unsigned int bus, ++ * unsigned int devfn, int reg, ++ * u32 *value) ++ * ++ * Read from PCI configuration space. ++ * ++ */ ++int mcf5445x_pci_config_read(unsigned int seg, unsigned int bus, ++ unsigned int devfn, int reg, int len, u32 *value) ++{ ++ u32 addr = MCF_PCI_PCICAR_BUSNUM(bus) | ++ MCF_PCI_PCICAR_DEVNUM(PCI_SLOT(devfn)) | ++ MCF_PCI_PCICAR_FUNCNUM(PCI_FUNC(devfn)) | ++ MCF_PCI_PCICAR_DWORD(reg) | ++ MCF_PCI_PCICAR_E; ++ ++ if ((bus > 255) || (devfn > 255) || (reg > 255)) { ++ *value = -1; ++ return -EINVAL; ++ } ++ ++ /* setup for config mode */ ++ MCF_PCI_PCICAR = addr; ++ __asm__ __volatile__("nop"); ++ ++ switch (len) { ++ case 1: ++ *value = *(volatile u8 *)(MCF5445X_PCI_CONFIG_BASE+(reg&3)); ++ break; ++ case 2: ++ *value = le16_to_cpu(*(volatile u16 *) ++ (MCF5445X_PCI_CONFIG_BASE + (reg&2))); ++ break; ++ case 4: ++ *value = le32_to_cpu(*(volatile u32 *) ++ (MCF5445X_PCI_CONFIG_BASE)); ++ break; ++ } ++ ++ /* clear config mode */ ++ MCF_PCI_PCICAR = ~MCF_PCI_PCICAR_E; ++ __asm__ __volatile__("nop"); ++ ++ return 0; ++} ++ ++/* ++ * int mcf5445x_pci_config_write(unsigned int seg, unsigned int bus, ++ * unsigned int devfn, int reg, ++ * u32 *value) ++ * ++ * Write to PCI configuration space ++ */ ++int mcf5445x_pci_config_write(unsigned int seg, unsigned int bus, ++ unsigned int devfn, int reg, int len, u32 value) ++{ ++ u32 addr = MCF_PCI_PCICAR_BUSNUM(bus) | ++ MCF_PCI_PCICAR_DEVNUM(PCI_SLOT(devfn)) | ++ MCF_PCI_PCICAR_FUNCNUM(PCI_FUNC(devfn)) | ++ MCF_PCI_PCICAR_DWORD(reg) | ++ MCF_PCI_PCICAR_E; ++ ++ if ((bus > 255) || (devfn > 255) || (reg > 255)) ++ return -EINVAL; ++ ++ /* setup for config mode */ ++ MCF_PCI_PCICAR = addr; ++ __asm__ __volatile__("nop"); ++ ++ switch (len) { ++ case 1: ++ *(volatile u8 *)(MCF5445X_PCI_CONFIG_BASE+(reg&3)) = (u8)value; ++ break; ++ case 2: ++ *(volatile u16 *)(MCF5445X_PCI_CONFIG_BASE+(reg&2)) = ++ cpu_to_le16((u16)value); ++ break; ++ case 4: ++ *(volatile u32 *)(MCF5445X_PCI_CONFIG_BASE) = ++ cpu_to_le32(value); ++ break; ++ } ++ ++ /* clear config mode */ ++ MCF_PCI_PCICAR = ~MCF_PCI_PCICAR_E; ++ __asm__ __volatile__("nop"); ++ ++ return 0; ++} ++ ++/* hardware operations */ ++static struct pci_raw_ops mcf5445x_pci_ops = { ++ .read = mcf5445x_pci_config_read, ++ .write = mcf5445x_pci_config_write, ++}; ++ ++/************************************************************************/ ++ ++/* ++ * u8 pci_inb() ++ * ++ * Read a byte at specified address from I/O space ++ */ ++unsigned char pci_inb(long addr) ++{ ++ char value; ++ ++ value = *(volatile unsigned char *) (HOST_IO_BASE | ++ (addr & PCI_IO_MASK)); ++ DBG("PCI: inb addr=0x%08X, value=0x%02X\n", addr, value); ++ ++ return (unsigned char) value; ++} ++ ++ ++/* ++ * u16 pci_inw() ++ * ++ * Read a word at specified address from I/O space ++ */ ++unsigned short pci_inw(long addr) ++{ ++ short value; ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = le16_to_cpu(*ptr); ++ ++ DBG("PCI: inw addr=0x%08X, value=0x%04X\n", addr, value); ++ return (unsigned short) value; ++} ++ ++/* ++ * u16 pci_raw_inw() ++ * ++ * Read a raw word at specified address from I/O space ++ */ ++unsigned short pci_raw_inw(long addr) ++{ ++ short value; ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = *ptr; ++ ++ DBG("PCI: raw_inw addr=0x%08X, value=0x%04X\n", addr, value); ++ return (unsigned short) value; ++} ++ ++/* ++ * u32 pci_inl() ++ * ++ * Read a dword at specified address from I/O space ++ */ ++unsigned long pci_inl(long addr) ++{ ++ long value; ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = le32_to_cpu(*ptr); ++ ++ DBG("PCI: inl addr=0x%08X, value=0x%08X\n", addr, value); ++ return (unsigned long) value; ++} ++ ++/* ++ * u32 pci_raw_inl() ++ * ++ * Read a raw dword at specified address from I/O space ++ */ ++unsigned long pci_raw_inl(long addr) ++{ ++ long value; ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = *ptr; ++ ++ DBG("PCI: raw_inl addr=0x%08X, value=0x%08X\n", addr, value); ++ return (unsigned long) value; ++} ++ ++/* ++ * void pci_outb() ++ * ++ * Write a byte value at specified address to I/O space ++ */ ++void pci_outb(unsigned char value, long addr) ++{ ++ ++ *(volatile unsigned char *) (HOST_IO_BASE | (addr & PCI_IO_MASK)) \ ++ = value; ++ DBG("PCI: outb addr=0x%08X, value=0x%02X\n", addr, value); ++} ++ ++ ++/* ++ * void pci_outw() ++ * ++ * Write a word value at specified address to I/O space ++ */ ++void pci_outw(volatile unsigned short value, volatile long addr) ++{ ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = cpu_to_le16(value); ++ DBG("PCI: outw addr=0x%08X, value=0x%04X\n", addr, value); ++} ++ ++/* ++ * void pci_raw_outw() ++ * ++ * Write a raw word value at specified address to I/O space ++ */ ++void pci_raw_outw(volatile unsigned short value, volatile long addr) ++{ ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = value; ++ DBG("PCI: raw_outw addr=0x%08X, value=0x%04X\n", addr, value); ++} ++ ++/* ++ * void pci_outl() ++ * ++ * Write a long word value at specified address to I/O space ++ */ ++void pci_outl(volatile unsigned long value, volatile long addr) ++{ ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = cpu_to_le32(value); ++ DBG("PCI: outl addr=0x%08X, value=0x%08X\n", addr, value); ++} ++ ++/* ++ * void pci_raw_outl() ++ * ++ * Write a raw long word value at specified address to I/O space ++ */ ++void pci_raw_outl(volatile unsigned long value, volatile long addr) ++{ ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = value; ++ DBG("PCI: raw_outl addr=0x%08X, value=0x%08X\n", addr, value); ++} ++ ++/* ++ * void pci_insb() ++ * ++ * Read several byte values from specified I/O port ++ */ ++void pci_insb(volatile unsigned char *addr, unsigned char *buf, int len) ++{ ++ for (; len--; buf++) ++ *buf = pci_inb((unsigned long)addr); ++ DBG("PCI: pci_insb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++ ++/* ++ * void pci_insw() ++ * ++ * Read several word values from specified I/O port ++ */ ++void pci_insw(volatile unsigned short *addr, unsigned short *buf, int len) ++{ ++ for (; len--; buf++) ++ *buf = pci_inw((unsigned long)addr); ++ DBG("PCI: pci_insw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_insl() ++ * ++ * Read several dword values from specified I/O port ++ */ ++void pci_insl(volatile unsigned long *addr, unsigned long *buf, int len) ++{ ++ for (; len--; buf++) ++ *buf = pci_inl((unsigned long)addr); ++ DBG("PCI: pci_insl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_outsb() ++ * ++ * Write several byte values to specified I/O port ++ */ ++void pci_outsb(volatile unsigned char *addr, const unsigned char *buf, int len) ++{ ++ for (; len--; buf++) ++ pci_outb((unsigned long)addr, *buf); ++ DBG("PCI: pci_outsb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_outsw() ++ * ++ * Write several word values to specified I/O port ++ */ ++void ++pci_outsw(volatile unsigned short *addr, const unsigned short *buf, int len) ++{ ++ for (; len--; buf++) ++ pci_outw((unsigned long)addr, *buf); ++ DBG("PCI: pci_outsw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_outsl() ++ * ++ * Write several dword values to specified I/O port ++ */ ++void pci_outsl(volatile unsigned long *addr, const unsigned long *buf, int len) ++{ ++ for (; len--; buf++) ++ pci_outl((unsigned long)addr, *buf); ++ DBG("PCI: pci_outsl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++/* ++ * irqreturn_t mcf5445x_pci_interrupt( int irq, void *dev) ++ * ++ * PCI controller interrupt handler. ++ */ ++static irqreturn_t ++mcf5445x_pci_interrupt(int irq, void *dev) ++{ ++ u32 status = MCF_PCI_PCIGSCR; ++#ifdef DEBUG ++ printk(KERN_INFO "PCI: Controller irq status=0x%08x\n", status); ++#endif ++ /* clear */ ++ MCF_PCI_PCIGSCR = status; ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * irqreturn_t mcf5445x_pci_arb_interrupt( int irq, void *dev) ++ * ++ * PCI Arbiter interrupt handler. ++ */ ++static irqreturn_t ++mcf5445x_pci_arb_interrupt(int irq, void *dev) ++{ ++ u32 status = MCF_PCIARB_PASR; ++#ifdef DEBUG ++ printk(KERN_INFO "PCI: Arbiter irq status=0x%08x\n", status); ++#endif ++ /* clear */ ++ MCF_PCIARB_PASR = status; ++ return IRQ_HANDLED; ++} ++ ++/* ++ * struct pci_bus_info *init_mcf5445x_pci(void) ++ * ++ * Machine specific initialisation: ++ * ++ * - Allocate and initialise a 'pci_bus_info' structure ++ * - Initialize hardware ++ * ++ * Result: pointer to 'pci_bus_info' structure. ++ */ ++int __init ++init_mcf5445x_pci(void) ++{ ++ /* ++ * Initialize the PCI core ++ */ ++ printk(KERN_INFO "init_mcf5445x_pci\n"); ++ ++ /* pci memory mapping */ ++ pci_mem_map = ioremap(MCF5445X_PCI_MEM_BASE_PHY, pci_mem_mapsize); ++ if (!pci_mem_map) { ++ printk(KERN_ERR "PCI memory map failed by ioremap!\n"); ++ return -ENOMEM; ++ } ++ printk(KERN_INFO "MCF5445X_PCI_MEM_BASE value is 0x%x\n", \ ++ MCF5445X_PCI_MEM_BASE); ++ ++ /* Initialize pci resource */ ++ pci_iomem_resource.start = MCF5445X_PCI_MEM_BASE; ++ pci_iomem_resource.end = MCF5445X_PCI_MEM_BASE + \ ++ MCF5445X_PCI_MEM_SIZE - 1; ++ ++ pci_ioport_resource.start = MCF5445X_PCI_IO_BASE; ++ pci_ioport_resource.end = MCF5445X_PCI_IO_BASE + \ ++ MCF5445X_PCI_IO_SIZE - 1; ++ ++ /* ++ * Must Reset!!! If bootloader has PCI enabled, it will cause ++ * problem in linux when it tries to configure/find resources ++ * for the pci devices ++ */ ++ MCF_PCI_PCIGSCR = 1; ++ ++ /* arbitration controller */ ++ MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI | ++ MCF_PCIARB_PACR_EXTMPRI(0x0f) | ++ MCF_PCIARB_PACR_INTMINTEN | ++ MCF_PCIARB_PACR_EXTMINTEN(0x0f); ++ ++ /* pci pin assignment regs */ ++#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) ++ MCF_GPIO_PAR_PCI = MCF_GPIO_PAR_PCI_GNT0 | ++ MCF_GPIO_PAR_PCI_GNT1 | ++ MCF_GPIO_PAR_PCI_GNT2 | ++ MCF_GPIO_PAR_PCI_GNT3_GNT3 | ++ MCF_GPIO_PAR_PCI_REQ0 | ++ MCF_GPIO_PAR_PCI_REQ1 | ++ MCF_GPIO_PAR_PCI_REQ2 | ++ MCF_GPIO_PAR_PCI_REQ3_REQ3; ++ ++ MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI & ++ (MCF_GPIO_PAR_PCI_GNT3_MASK & ++ MCF_GPIO_PAR_PCI_REQ3_MASK)) | ++ MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK | ++ MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ; ++#else ++ MCF_GPIO_PAR_PCI = MCF_GPIO_PAR_PCI_GNT0 | ++ MCF_GPIO_PAR_PCI_GNT1 | ++ MCF_GPIO_PAR_PCI_GNT2 | ++ MCF_GPIO_PAR_PCI_GNT3_GNT3 | ++ MCF_GPIO_PAR_PCI_REQ0 | ++ MCF_GPIO_PAR_PCI_REQ1 | ++ MCF_GPIO_PAR_PCI_REQ2 | ++ MCF_GPIO_PAR_PCI_REQ3_REQ3; ++#endif ++ /* target control reg */ ++ MCF_PCI_PCITCR = MCF_PCI_PCITCR_P | ++ MCF_PCI_PCITCR_WCT(8); ++ ++ /* PCI MEM address */ ++ MCF_PCI_PCIIW0BTAR = MCF5445X_PCI_MEM_BASE_PHY | ++ (MCF5445X_PCI_MEM_BASE >> 16); ++ ++ /* PCI MEM address */ ++ MCF_PCI_PCIIW1BTAR = (MCF5445X_PCI_MEM_BASE_PHY + ++ MCF5445X_PCI_MEM_SIZE) ++ | (MCF5445X_PCI_IO_BASE >> 16); ++ ++ /* PCI IO address */ ++ MCF_PCI_PCIIW2BTAR = (MCF5445X_PCI_MEM_BASE_PHY + ++ MCF5445X_PCI_MEM_SIZE + MCF5445X_PCI_IO_SIZE) ++ | (MCF5445X_PCI_CONFIG_BASE >> 16); ++ ++ /* window control */ ++ MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_ENABLE | ++ MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD | ++ MCF_PCI_PCIIWCR_WINCTRL1_ENABLE | ++ MCF_PCI_PCIIWCR_WINCTRL1_IO | ++ MCF_PCI_PCIIWCR_WINCTRL2_ENABLE | ++ MCF_PCI_PCIIWCR_WINCTRL2_IO; ++ ++ /* initiator control reg */ ++ MCF_PCI_PCIICR = 0; ++ ++ /* type 0 - command */ ++ MCF_PCI_PCISCR = MCF_PCI_PCISCR_MW | /* mem write/inval */ ++ MCF_PCI_PCISCR_B | /* bus master enable */ ++ MCF_PCI_PCISCR_MA | /* clear master abort error */ ++ MCF_PCI_PCISCR_M; /* mem access enable */ ++ ++ /* type 0 - config reg */ ++ MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) | ++ MCF_PCI_PCICR1_LATTIMER(0xFF); ++ /* type 0 - config 2 reg */ ++ MCF_PCI_PCICR2 = 0; ++ ++ /* target control reg */ ++ MCF_PCI_PCITCR2 = MCF_PCI_PCITCR2_B0E | MCF_PCI_PCITCR2_B5E; ++ ++ /* translate addresses from PCI[0] to CF[SDRAM] */ ++ MCF_PCI_PCITBATR0 = 0xFC000000 | MCF_PCI_PCITBATR5_EN; ++ MCF_PCI_PCITBATR5 = MCF_RAMBAR1 | MCF_PCI_PCITBATR5_EN; ++ ++ /* inbound window for memory */ ++ MCF_PCI_PCIBAR0 = 0xFC000000; ++ MCF_PCI_PCIBAR5 = MCF_RAMBAR1; ++ ++ /* setup controller interrupt handlers */ ++ if (request_irq(55+128, mcf5445x_pci_interrupt, IRQF_SHARED, ++ "PCI Controller", NULL)) ++ printk(KERN_ERR "PCI: Unable to register controller irq\n"); ++ ++ if (request_irq(56+128, mcf5445x_pci_arb_interrupt, IRQF_SHARED, ++ "PCI Arbiter", NULL)) ++ printk(KERN_ERR "PCI: Unable to register arbiter irq\n"); ++ ++ /* global control - clear reset bit */ ++ MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_SEE | ++ MCF_PCI_PCIGSCR_PEE; ++ ++ /* let everything settle */ ++ udelay(1000); ++ ++ /* allocate bus ioport resource */ ++ if (request_resource(&ioport_resource, &pci_ioport_resource) < 0) ++ printk(KERN_ERR "PCI: Unable to alloc ioport resource\n"); ++ ++ /* allocate bus iomem resource */ ++ if (request_resource(&iomem_resource, &pci_iomem_resource) < 0) ++ printk(KERN_ERR "PCI: Unable to alloc iomem resource\n"); ++ ++ /* setup FPGA to route PCI to IRQ3(67), SW7 to IRQ7, SW6 to IRQ4 */ ++ set_fpga(FPGA_PCI_IRQ_ENABLE, 0x00000000); ++ set_fpga(FPGA_PCI_IRQ_ROUTE, 0x00000039); ++ set_fpga(FPGA_SEVEN_LED, 0x000000FF); ++ ++ raw_pci_ops = &mcf5445x_pci_ops; ++#ifdef DEBUG ++ mcf5445x_pci_dumpregs(); ++#endif ++ return 0; ++} ++ ++/* ++ * DEBUGGING ++ */ ++ ++#ifdef DEBUG ++struct regdump { ++ u32 addr; ++ char regname[16]; ++}; ++ ++struct regdump type0regs[] = { ++ { 0xfc0a8000, "PCIIDR" }, ++ { 0xfc0a8004, "PCISCR" }, ++ { 0xfc0a8008, "PCICCRIR" }, ++ { 0xfc0a800c, "PCICR1" }, ++ { 0xfc0a8010, "PCIBAR0" }, ++ { 0xfc0a8014, "PCIBAR1" }, ++ { 0xfc0a8018, "PCIBAR2" }, ++ { 0xfc0a801c, "PCIBAR3" }, ++ { 0xfc0a8020, "PCIBAR4" }, ++ { 0xfc0a8024, "PCIBAR5" }, ++ { 0xfc0a8028, "PCICCPR" }, ++ { 0xfc0a802c, "PCISID" }, ++ { 0xfc0a8030, "PCIERBAR" }, ++ { 0xfc0a8034, "PCICPR" }, ++ { 0xfc0a803c, "PCICR2" }, ++ { 0, "" } ++}; ++ ++struct regdump genregs[] = { ++ { 0xfc0a8060, "PCIGSCR" }, ++ { 0xfc0a8064, "PCITBATR0" }, ++ { 0xfc0a8068, "PCITBATR1" }, ++ { 0xfc0a806c, "PCITCR1" }, ++ { 0xfc0a8070, "PCIIW0BTAR" }, ++ { 0xfc0a8074, "PCIIW1BTAR" }, ++ { 0xfc0a8078, "PCIIW2BTAR" }, ++ { 0xfc0a8080, "PCIIWCR" }, ++ { 0xfc0a8084, "PCIICR" }, ++ { 0xfc0a8088, "PCIISR" }, ++ { 0xfc0a808c, "PCITCR2" }, ++ { 0xfc0a8090, "PCITBATR0" }, ++ { 0xfc0a8094, "PCITBATR1" }, ++ { 0xfc0a8098, "PCITBATR2" }, ++ { 0xfc0a809c, "PCITBATR3" }, ++ { 0xfc0a80a0, "PCITBATR4" }, ++ { 0xfc0a80a4, "PCITBATR5" }, ++ { 0xfc0a80a8, "PCIINTR" }, ++ { 0xfc0a80f8, "PCICAR" }, ++ { 0, "" } ++}; ++ ++struct regdump arbregs[] = { ++ { 0xfc0ac000, "PACR" }, ++ { 0xfc0ac004, "PASR" }, /* documentation error */ ++ { 0, "" } ++}; ++ ++/* ++ * void mcf5445x_pci_dumpregs() ++ * ++ * Dump out all the PCI registers ++ */ ++void ++mcf5445x_pci_dumpregs(void) ++{ ++ struct regdump *reg; ++ ++ printk(KERN_INFO "*** MCF5445x PCI TARGET 0 REGISTERS ***\n"); ++ ++ reg = type0regs; ++ while (reg->addr) { ++ printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr, ++ *((u32 *)reg->addr), reg->regname); ++ reg++; ++ } ++ ++ printk(KERN_INFO "\n*** MCF5445x PCI GENERAL REGISTERS ***\n"); ++ reg = genregs; ++ while (reg->addr) { ++ printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr, ++ *((u32 *)reg->addr), reg->regname); ++ reg++; ++ } ++ printk(KERN_INFO "\n*** MCF5445x PCI ARBITER REGISTERS ***\n"); ++ reg = arbregs; ++ while (reg->addr) { ++ printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr, ++ *((u32 *)reg->addr), reg->regname); ++ reg++; ++ } ++} ++#endif /* DEBUG */ +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/pci.c +@@ -0,0 +1,247 @@ ++/* ++ * linux/arch/m68k/coldfire/m5445x/pci.c ++ * ++ * PCI initialization for Coldfire architectures. ++ * ++ * Currently Supported: ++ * M5445x ++ * ++ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/pci.h> ++ ++#include <asm/mcfsim.h> ++#include <asm/pci.h> ++ ++/* pci ops for reading/writing config */ ++struct pci_raw_ops *raw_pci_ops; ++ ++/* pci debug flag */ ++static int debug_pci; ++ ++static int ++pci_read(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, u32 *value) ++{ ++ return raw_pci_ops->read(0, bus->number, devfn, where, size, value); ++} ++ ++static int ++pci_write(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, u32 value) ++{ ++ return raw_pci_ops->write(0, bus->number, devfn, where, size, value); ++} ++ ++struct pci_ops pci_root_ops = { ++ .read = pci_read, ++ .write = pci_write, ++}; ++ ++/* ++ * pcibios_setup(char *) ++ * ++ * Initialize the pcibios based on cmd line params. ++ */ ++char * ++pcibios_setup(char *str) ++{ ++ if (!strcmp(str, "debug")) { ++ debug_pci = 1; ++ return NULL; ++ } ++ return str; ++} ++ ++/* ++ * We need to avoid collisions with `mirrored' VGA ports ++ * and other strange ISA hardware, so we always want the ++ * addresses to be allocated in the 0x000-0x0ff region ++ * modulo 0x400. ++ * ++ * Why? Because some silly external IO cards only decode ++ * the low 10 bits of the IO address. The 0x00-0xff region ++ * is reserved for motherboard devices that decode all 16 ++ * bits, so it's ok to allocate at, say, 0x2800-0x28ff, ++ * but we want to try to avoid allocating at 0x2900-0x2bff ++ * which might have be mirrored at 0x0100-0x03ff.. ++ */ ++resource_size_t ++pcibios_align_resource(void *data, const struct resource *res, ++ resource_size_t size, resource_size_t align) ++{ ++ struct pci_dev *dev = data; ++ resource_size_t start = res->start; ++ ++ if (res->flags & IORESOURCE_IO) { ++ if (size > 0x100) ++ printk(KERN_ERR "PCI: I/O Region %s/%d too large" ++ " (%ld bytes)\n", pci_name(dev), ++ dev->resource - res, (long int)size); ++ ++ if (start & 0x3ff) ++ start = (start + 0x3ff) & ~0x3ff; ++ } ++ ++ return start; ++} ++EXPORT_SYMBOL(pcibios_align_resource); ++ ++/* ++ * Swizzle the device pin each time we cross a bridge ++ * and return the slot number. ++ */ ++static u8 __devinit ++pcibios_swizzle(struct pci_dev *dev, u8 *pin) ++{ ++ return 0; ++} ++ ++/* ++ * Map a slot/pin to an IRQ. ++ */ ++static int ++pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ return 0x43; ++} ++ ++/* ++ * pcibios_update_irq(struct pci_dev *dev, int irq) ++ * ++ * Update a PCI interrupt. ++ */ ++void ++pcibios_update_irq(struct pci_dev *dev, int irq) ++{ ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); ++} ++ ++/* ++ * pcibios_enable_device(struct pci_dev *dev, int mask) ++ * ++ * Enable a device on the PCI bus. ++ */ ++int ++pcibios_enable_device(struct pci_dev *dev, int mask) ++{ ++ u16 cmd, old_cmd; ++ int idx; ++ struct resource *r; ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ old_cmd = cmd; ++ for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) { ++ r = &dev->resource[idx]; ++ if (!r->start && r->end) { ++ printk(KERN_ERR "PCI: Device %s not available because " ++ "of resource collisions\n", pci_name(dev)); ++ return -EINVAL; ++ } ++ if (r->flags & IORESOURCE_IO) ++ cmd |= PCI_COMMAND_IO; ++ if (r->flags & IORESOURCE_MEM) ++ cmd |= PCI_COMMAND_MEMORY; ++ } ++ if (cmd != old_cmd) { ++ printk("PCI: Enabling device %s (%04x -> %04x)\n", ++ pci_name(dev), old_cmd, cmd); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++#ifdef CONFIG_M54455 ++ mcf5445x_conf_device(dev); ++#endif ++ } ++ ++ return 0; ++} ++ ++/* ++ * pcibios_fixup_bus(struct pci_bus *bus) ++ */ ++void ++pcibios_fixup_bus(struct pci_bus *bus) ++{ ++ struct pci_dev *dev = bus->self; ++ ++ if (!dev) { ++ /* Root bus. */ ++#ifdef CONFIG_M54455 ++ bus->resource[0] = &pci_ioport_resource; ++ bus->resource[1] = &pci_iomem_resource; ++#endif ++ } ++} ++ ++/* ++ * pcibios_init(void) ++ * ++ * Allocate/initialize low level pci bus/devices. ++ */ ++#ifdef CONFIG_M54455_PCI_initcall ++static int __init ++#else ++int __init ++#endif ++pcibios_init(void) ++{ ++ struct pci_bus *bus; ++ ++ if (!raw_pci_ops) { ++ printk(KERN_WARNING "PCIBIOS: FATAL: NO PCI Hardware found\n"); ++ return 0; ++ } ++ ++ /* allocate and scan the (only) bus */ ++ bus = pci_scan_bus_parented(NULL, 0, &pci_root_ops, NULL); ++ ++ /* setup everything */ ++ if (bus) { ++ /* compute the bridge window sizes */ ++ pci_bus_size_bridges(bus); ++ ++ /* (re)assign device resources */ ++ pci_bus_assign_resources(bus); ++ ++ /* add the bus to the system */ ++ pci_bus_add_devices(bus); ++ ++ /* fixup irqs */ ++ pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); ++ } ++ ++ return 0; ++} ++ ++/* ++ * pci_init(void) ++ * ++ * Initialize the PCI Hardware. ++ */ ++#ifdef CONFIG_M54455_PCI_initcall ++static int __init ++#else ++int __init ++#endif ++pci_init(void) ++{ ++ printk(KERN_INFO "pci_init\n"); ++#if defined(CONFIG_M54455) ++ init_mcf5445x_pci(); ++#endif ++ if (!raw_pci_ops) ++ printk(KERN_ERR "PCI: FATAL: NO PCI Detected\n"); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_M54455_PCI_initcall ++/* low level hardware (first) */ ++arch_initcall(pci_init); ++ ++/* basic bios init (second) */ ++subsys_initcall(pcibios_init); ++#endif +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/pci.c +@@ -0,0 +1,1023 @@ ++/* ++ * ColdFire 547x/548x PCI Host Controller functions ++ * ++ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Shrek Wu b16972@freescale.com ++ * This code is based on the 2.6.10 version of pci.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/mm.h> ++#include <linux/string.h> ++#include <linux/pci.h> ++#include <linux/ioport.h> ++#include <linux/slab.h> ++#include <linux/version.h> ++#include <linux/interrupt.h> ++#include <linux/delay.h> ++ ++#include <linux/dma-mapping.h> ++#include <asm/coldfire.h> ++#include <linux/io.h> ++#include <asm/m5485sim.h> ++#include <asm/m5485pci.h> ++#include <asm/irq.h> ++#include <linux/pci.h> ++#include <asm/virtconvert.h> ++ ++ ++#undef DEBUG ++/*define DEBUG*/ ++#ifdef DEBUG ++/*#define DBG(x...) printk(KERN_DEBUG x)*/ ++#define DBG(x...) printk(x) ++#else ++#define DBG(x...) ++#endif ++ ++/* ++ * Bridge configration dafaults ++ */ ++#define PCI_RETRIES 0 ++#define PCI_CACHE_LINE 8 ++#define PCI_MINGNT 1 ++#define PCI_MAXLAT 42 ++ ++ ++/* ++ * Initiator windows setting ++ */ ++#define HOST_MEM_BASE 0xD0000000 ++/* ColdFire Memory window base */ ++#define PCI_MEM_BASE 0xD0000000 ++/* PCI Memory window base */ ++#define PCI_MEM_SIZE 0x08000000 ++/* Memory window size (128M) */ ++#define HOST_IO_BASE 0xD8000000 ++/* ColdFire I/O window base */ ++#define PCI_IO_BASE_ADDR 0x00000000 ++/* PCI I/O window base */ ++#define PCI_IO_SIZE 0x00010000 ++/* I/O window size (64K) */ ++/*#define HOST_CFG_BASE 0xD8000000*/ ++#define HOST_CFG_BASE 0xD8008000 ++/* ColdFire config window base */ ++#define HOST_DMA_BASE CONFIG_SDRAM_BASE ++/* ColdFire PCI-DMA window base */ ++#define PCI_HDR_BASE (MCF_MBAR+0xB00) ++/* ColdFire config registers */ ++ ++#define PCI_MEM_MASK (PCI_MEM_SIZE-1) ++#define PCI_IO_MASK (PCI_IO_SIZE-1) ++ ++/* Macro to set initiator window */ ++#define WxBAR(host_address, pci_address, size) \ ++ (((host_address) & 0xff000000) | \ ++ ((((size)-1) & 0xff000000) >> 8) | \ ++ ((pci_address) & 0xff000000) >> 16) ++ ++/* ++ * BIOS internal data ++ */ ++static u8 revision; /* controller revision */ ++ ++/* ++ * Board specific setting ++ */ ++const unsigned int irq_lines[] = { 5, 7 }; ++ ++#define N_SLOTS (sizeof(board_info) / sizeof(board_info[0])) ++#define N_IRQS (sizeof(irq_lines) / sizeof(irq_lines[0])) ++#define BRIDGE_SLOT 0 ++ ++const struct slotinfo { ++ unsigned char idsel; /* device number */ ++ unsigned char irq; /* external IRQ */ ++ unsigned char req; /* REQ line number */ ++ unsigned char gnt; /* GNT line number */ ++} board_info[] = { ++ {0, 0, 0, 0}, /* Bridge */ ++ {17, 5, 1, 1}, /* Slot #1 */ ++ {18, 5, 2, 2}, /* Slot #2 */ ++ {20, 7, 3, 3}, /* Slot #3 */ ++ {21, 7, 4, 4}, /* Slot #4 */ ++}; ++ ++/************************************************************************/ ++ ++/* ++ * static int mk_conf_addr() ++ * ++ * Return type0 or type1 configuration address ++ * by the means of device address and PCI dword location ++ * 0 - for not existing slots ++ */ ++static int mk_conf_addr(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where) ++{ ++ int slot, func, address, idsel, dev_fn; ++ ++ if (bus->number) { ++ address = MCF_PCICAR_E | (bus->number << 16) | ++ (devfn << 8) | (where & 0xfc); ++ } else { ++ slot = PCI_SLOT(devfn); ++ if (slot > N_SLOTS || slot == BRIDGE_SLOT) ++ return 0; ++ else { ++ func = PCI_FUNC(devfn); ++ idsel = board_info[slot].idsel; ++ ++ dev_fn = PCI_DEVFN(idsel, func); ++ address = MCF_PCICAR_E | (bus->number << 16) | ++ (dev_fn << 8) | (where & 0xfc); ++ } ++ } ++ ++ return address; ++} ++ ++/* ++ * static int read_config_byte() ++ * ++ * Read a byte from configuration space of specified device ++ */ ++static int read_config_byte(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where, u8 *value) ++{ ++ int slot; ++ int address; ++ int result; ++ ++ *value = 0xff; ++ result = PCIBIOS_SUCCESSFUL; ++ ++ slot = PCI_SLOT(devfn); ++ if (slot == BRIDGE_SLOT) { ++ if (where <= 0x40) ++ *value = *(volatile u8 *) (PCI_HDR_BASE + ++ (where & 0xfc) + (where & 3)); ++ else ++ *value = 0; ++ } else { ++ address = mk_conf_addr(bus, devfn, where); ++ if (!address) ++ result = PCIBIOS_DEVICE_NOT_FOUND; ++ else { ++ MCF_PCICAR = address; ++ __asm__ __volatile__("nop"); ++ *value = *(volatile u8 *) (HOST_CFG_BASE + (where & 3)); ++ } ++ } ++ __asm("tpf"); ++ MCF_PCICAR &= ~MCF_PCICAR_E; ++ DBG("PCI: read_config_byte bus=%d, dev=%d, fn=%d," ++ " addr=0x%02X, val=0x%02X, ret=%02X\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *value, result); ++ ++ return result; ++} ++ ++/* ++ * static int read_config_word() ++ * ++ * Read a word from configuration space of specified device ++ */ ++static int read_config_word(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where, u16 *value) ++{ ++ int slot; ++ int address; ++ int result; ++ ++ *value = 0xffff; ++ result = PCIBIOS_SUCCESSFUL; ++ ++ if (where & 0x1) ++ result = PCIBIOS_BAD_REGISTER_NUMBER; ++ else { ++ slot = PCI_SLOT(devfn); ++ if (slot == BRIDGE_SLOT) { ++ if (where <= 0x3f) ++ *value = ++ *(volatile u16 *) (PCI_HDR_BASE + ++ (where & 0xfc) + (where & 2)); ++ else ++ *value = 0; ++ } else { ++ address = mk_conf_addr(bus, devfn, where); ++ if (!address) ++ result = PCIBIOS_DEVICE_NOT_FOUND; ++ else { ++ MCF_PCICAR = address; ++ __asm__ __volatile__("nop"); ++ *value = le16_to_cpu(*(volatile u16 *) ++ (HOST_CFG_BASE + ++ (where & 2))); ++ } ++ } ++ } ++ __asm("tpf"); ++ MCF_PCICAR &= ~MCF_PCICAR_E; ++ DBG("PCI: read_config_word bus=%d, dev=%d, fn=%d," ++ " addr=0x%02X, val=0x%04X ret=%02X\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *value, result); ++ ++ return result; ++} ++ ++/* ++ * static int read_config_dword() ++ * ++ * Read a long word from configuration space of specified device ++ */ ++static int read_config_dword(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where, u32 *value) ++{ ++ int slot; ++ int address; ++ int result; ++ ++ *value = 0xffffffff; ++ result = PCIBIOS_SUCCESSFUL; ++ ++ if (where & 0x3) ++ result = PCIBIOS_BAD_REGISTER_NUMBER; ++ else { ++ slot = PCI_SLOT(devfn); ++ if (slot == BRIDGE_SLOT) { ++ if (where <= 0x3d) ++ *value = ++ *(volatile u32 *) (PCI_HDR_BASE + where); ++ else ++ *value = 0; ++ __asm("tpf"); ++ } else { ++ address = mk_conf_addr(bus, devfn, where); ++ if (!address) ++ result = PCIBIOS_DEVICE_NOT_FOUND; ++ else { ++ MCF_PCICAR = address; ++ __asm__ __volatile__("nop"); ++ *value = le32_to_cpu(*(volatile u32 *) ++ (HOST_CFG_BASE)); ++ __asm("tpf"); ++ if (bus->number != 0 && revision < 1) { ++ volatile u32 temp; ++ MCF_PCICAR |= 0xff0000; ++ temp = *(volatile u32 *) ++ (HOST_CFG_BASE); ++ } ++ } ++ } ++ } ++ ++ MCF_PCICAR &= ~MCF_PCICAR_E; ++ DBG("PCI: read_config_dword bus=%d, dev=%d, fn=%d, " ++ "addr=0x%02X, value=0x%08X ret=%02X\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *value, result); ++ ++ return result; ++} ++ ++ ++ ++/* ++ * static int write_config_byte() ++ * ++ * Write a byte to configuration space of specified device ++ */ ++static int write_config_byte(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where, u8 value) ++{ ++ int slot; ++ int address; ++ int result; ++ ++ result = PCIBIOS_SUCCESSFUL; ++ ++ slot = PCI_SLOT(devfn); ++ if (slot == BRIDGE_SLOT) { ++ if (where <= 0x40) ++ *(volatile u8 *) (PCI_HDR_BASE + (where & 0xfc) ++ + (where & 3)) = value; ++ } else { ++ address = mk_conf_addr(bus, devfn, where); ++ if (!address) ++ result = PCIBIOS_DEVICE_NOT_FOUND; ++ else { ++ MCF_PCICAR = address; ++ __asm__ __volatile__("tpf"); ++ *(volatile u8 *) (HOST_CFG_BASE + (where & 3)) = value; ++ } ++ } ++ __asm("tpf"); ++ MCF_PCICAR &= ~MCF_PCICAR_E; ++ pci_dummy_function(); ++ ++ DBG("PCI: write_config_byte bus=%d, dev=%d, fn=%d, " ++ "addr=0x%02X, value=0x%02X ret=%02X\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result); ++ ++ return result; ++} ++ ++/* ++ * static int write_config_word() ++ * ++ * Write a word to configuration space of specified device ++ */ ++static int write_config_word(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where, u16 value) ++{ ++ int slot; ++ int address; ++ int result; ++ ++ result = PCIBIOS_SUCCESSFUL; ++ ++ if (where & 0x1) ++ result = PCIBIOS_BAD_REGISTER_NUMBER; ++ else { ++ slot = PCI_SLOT(devfn); ++ if (slot == BRIDGE_SLOT) { ++ if (where <= 0x3f) ++ *(volatile u16 *) (PCI_HDR_BASE + ++ (where & 0xfc) + (where & 2)) = value; ++ } else { ++ address = mk_conf_addr(bus, devfn, where); ++ if (!address) ++ result = PCIBIOS_DEVICE_NOT_FOUND; ++ else { ++ MCF_PCICAR = address; ++ __asm__ __volatile__("tpf"); ++ *(volatile u16 *) (HOST_CFG_BASE ++ + (where & 2)) = ++ cpu_to_le16(value); ++ } ++ } ++ } ++ __asm("tpf"); ++ MCF_PCICAR &= ~MCF_PCICAR_E; ++ pci_dummy_function(); ++ ++ DBG("PCI: write_config_word bus=%d, dev=%d, fn=%d, " ++ "addr=0x%02X, value=0x%04X ret=%02X\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result); ++ ++ return result; ++} ++ ++/* ++ * static int write_config_dword() ++ * ++ * Write a long word to configuration space of specified device ++ */ ++static int write_config_dword(/*struct pci_dev *dev*/ ++ struct pci_bus *bus, unsigned int devfn, int where, u32 value) ++{ ++ int slot; ++ int address; ++ int result; ++ ++ result = PCIBIOS_SUCCESSFUL; ++ ++ if (where & 0x3) ++ result = PCIBIOS_BAD_REGISTER_NUMBER; ++ else { ++ slot = PCI_SLOT(devfn); ++ if (slot == BRIDGE_SLOT) { ++ if (where <= 0x3d) ++ *(volatile u32 *) (PCI_HDR_BASE + where) = ++ value; ++ } else { ++ address = mk_conf_addr(bus, devfn, where); ++ if (!address) ++ result = PCIBIOS_DEVICE_NOT_FOUND; ++ else { ++ MCF_PCICAR = address; ++ __asm__ __volatile__("tpf"); ++ *(volatile u32 *) (HOST_CFG_BASE) = ++ cpu_to_le32(value); ++ } ++ } ++ } ++ __asm("tpf"); ++ MCF_PCICAR &= ~MCF_PCICAR_E; ++ pci_dummy_function(); ++ ++ DBG("PCI: write_config_dword dev=%d, fn=%d," ++ "addr=0x%02X, value=0x%08X ret=%02X\n", ++ PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result); ++ ++ return result; ++} ++ ++static int config_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *val) ++{ ++ switch (size) { ++ case 1: ++ return read_config_byte(bus, devfn, where, (u8 *) val); ++ case 2: ++ return read_config_word(bus, devfn, where, (u16 *) val); ++ default: ++ return read_config_dword(bus, devfn, where, val); ++ } ++} ++ ++static int config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 val) ++{ ++ switch (size) { ++ case 1: ++ return write_config_byte(bus, devfn, where, (u8) val); ++ case 2: ++ return write_config_word(bus, devfn, where, (u16) val); ++ default: ++ return write_config_dword(bus, devfn, where, val); ++ } ++} ++ ++/* ++ * configuration routines entry points ++ */ ++static struct pci_ops bus_ops = { ++ .read = config_read, ++ .write = config_write, ++}; ++ ++/************************************************************************/ ++ ++/* ++ * u8 pci_inb() ++ * ++ * Read a byte at specified address from I/O space ++ */ ++unsigned char pci_inb(long addr) ++{ ++ char value; ++ ++ value = *(volatile unsigned char *)(HOST_IO_BASE | ++ (addr & PCI_IO_MASK)); ++ DBG("PCI: inb addr=0x%08X, value=0x%02X\n", addr, value); ++ ++ return (unsigned char) value; ++} ++ ++ ++/* ++ * u16 pci_inw() ++ * ++ * Read a word at specified address from I/O space ++ */ ++unsigned short pci_inw(long addr) ++{ ++ short value; ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = le16_to_cpu(*ptr); ++ ++ DBG("PCI: inw addr=0x%08X, value=0x%04X\n", addr, value); ++ return (unsigned short) value; ++} ++ ++/* ++ * u16 pci_raw_inw() ++ * ++ * Read a raw word at specified address from I/O space ++ */ ++unsigned short pci_raw_inw(long addr) ++{ ++ short value; ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = *ptr; ++ ++ DBG("PCI: raw_inw addr=0x%08X, value=0x%04X\n", addr, value); ++ return (unsigned short) value; ++} ++ ++/* ++ * u32 pci_inl() ++ * ++ * Read a dword at specified address from I/O space ++ */ ++unsigned long pci_inl(long addr) ++{ ++ long value; ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = le32_to_cpu(*ptr); ++ ++ DBG("PCI: inl addr=0x%08X, value=0x%08X\n", addr, value); ++ return (unsigned long) value; ++} ++ ++/* ++ * u32 pci_raw_inl() ++ * ++ * Read a raw dword at specified address from I/O space ++ */ ++unsigned long pci_raw_inl(long addr) ++{ ++ long value; ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ value = *ptr; ++ ++ DBG("PCI: raw_inl addr=0x%08X, value=0x%08X\n", addr, value); ++ return (unsigned long) value; ++} ++ ++/* ++ * void pci_outb() ++ * ++ * Write a byte value at specified address to I/O space ++ */ ++void pci_outb(unsigned char value, long addr) ++{ ++ ++ *(volatile unsigned char *)(HOST_IO_BASE | (addr & PCI_IO_MASK)) ++ = value; ++ DBG("PCI: outb addr=0x%08X, value=0x%02X\n", addr, value); ++} ++ ++ ++/* ++ * void pci_outw() ++ * ++ * Write a word value at specified address to I/O space ++ */ ++void pci_outw(volatile unsigned short value, volatile long addr) ++{ ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = cpu_to_le16(value); ++ DBG("PCI: outw addr=0x%08X, value=0x%04X\n", addr, value); ++} ++ ++/* ++ * void pci_raw_outw() ++ * ++ * Write a raw word value at specified address to I/O space ++ */ ++void pci_raw_outw(volatile unsigned short value, volatile long addr) ++{ ++ volatile unsigned short *ptr; ++ ++ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = value; ++ DBG("PCI: raw_outw addr=0x%08X, value=0x%04X\n", addr, value); ++} ++ ++/* ++ * void pci_outl() ++ * ++ * Write a long word value at specified address to I/O space ++ */ ++void pci_outl(volatile unsigned long value, volatile long addr) ++{ ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = cpu_to_le32(value); ++ DBG("PCI: outl addr=0x%08X, value=0x%08X\n", addr, value); ++} ++ ++/* ++ * void pci_raw_outl() ++ * ++ * Write a raw long word value at specified address to I/O space ++ */ ++void pci_raw_outl(volatile unsigned long value, volatile long addr) ++{ ++ volatile unsigned long *ptr; ++ ++ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK)); ++ *ptr = value; ++ DBG("PCI: raw_outl addr=0x%08X, value=0x%08X\n", addr, value); ++} ++ ++/* ++ * void pci_insb() ++ * ++ * Read several byte values from specified I/O port ++ */ ++void pci_insb(volatile unsigned char *addr, unsigned char *buf, int len) ++{ ++ for (; len--; buf++) ++ *buf = pci_inb((unsigned long)addr); ++ DBG("PCI: pci_insb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++ ++/* ++ * void pci_insw() ++ * ++ * Read several word values from specified I/O port ++ */ ++void pci_insw(volatile unsigned short *addr, unsigned short *buf, int len) ++{ ++ for (; len--; buf++) ++ *buf = pci_inw((unsigned long)addr); ++ DBG("PCI: pci_insw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_insl() ++ * ++ * Read several dword values from specified I/O port ++ */ ++void pci_insl(volatile unsigned long *addr, unsigned long *buf, int len) ++{ ++ for (; len--; buf++) ++ *buf = pci_inl((unsigned long)addr); ++ DBG("PCI: pci_insl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_outsb() ++ * ++ * Write several byte values to specified I/O port ++ */ ++void pci_outsb(volatile unsigned char *addr, const unsigned char *buf, int len) ++{ ++ for (; len--; buf++) ++ pci_outb((unsigned long)addr, *buf); ++ DBG("PCI: pci_outsb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_outsw() ++ * ++ * Write several word values to specified I/O port ++ */ ++void pci_outsw(volatile unsigned short *addr, ++ const unsigned short *buf, int len) ++{ ++ for (; len--; buf++) ++ pci_outw((unsigned long)addr, *buf); ++ DBG("PCI: pci_outsw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_outsl() ++ * ++ * Write several dword values to specified I/O port ++ */ ++void pci_outsl(volatile unsigned long *addr, const unsigned long *buf, int len) ++{ ++ for (; len--; buf++) ++ pci_outl((unsigned long)addr, *buf); ++ DBG("PCI: pci_outsl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len); ++} ++ ++/* ++ * void pci_xlb_handler() ++ * ++ * PCI XLB interrupt handler ++ */ ++irqreturn_t xlb_interrupt(int irq, void *dev) ++{ ++ volatile int xlb_error = MCF_PCIISR; ++ ++ /* Acknowlege interrupt */ ++ MCF_PCIISR = xlb_error; ++ ++ /* Dump interrupt reason */ ++ if (xlb_error & MCF_PCIISR_RE) ++ DBG("PCI: Retry Error Received\n"); ++ ++ if (xlb_error & MCF_PCIISR_IA) ++ DBG("PCI: Initiator Abort Received\n"); ++ ++ if (xlb_error & MCF_PCIISR_TA) ++ DBG("PCI: Target Abort Received\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++/* ++ * void pci_arbiter_handler() ++ * ++ * PCI arbiter interrupt handler ++ */ ++irqreturn_t arb_interrupt(int irq, void *dev) ++{ ++ volatile unsigned long arb_error = MCF_PCIARB_PASR; ++ ++ /* Acknowlege interrupt */ ++ printk(KERN_ERR "%s\n", __func__); ++ MCF_PCIARB_PASR = arb_error; ++ ++ if (arb_error & MCF_PCIARB_PASR_ITLMBK) { ++ DBG("PCI: coldfire master time-out\n"); ++ ++ /* Set infinite number of retries */ ++ MCF_PCIICR &= ~0xFF; ++ } ++ ++ if (arb_error & MCF_PCIARB_PASR_EXTMBK(0x1F)) { ++ arb_error >>= 17; ++ DBG("PCI: external master time-out (mask = 0x%X)\n", arb_error); ++ ++ /* raise arbitration priority level */ ++ MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMPRI(arb_error); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++ ++/* ++ * void pci_eint_handler() ++ * ++ * Eport interrupt handler ++ */ ++irqreturn_t eint_handler(int irq, void *dev) ++{ ++ /* Just acknowlege interrupt and exit */ ++ MCF_EPFR = 0x1 << (irq - 64); ++ return IRQ_HANDLED; ++} ++ ++resource_size_t ++pcibios_align_resource(void *data, const struct resource *res, ++ resource_size_t size, resource_size_t align) ++{ ++ struct pci_dev *dev = data; ++ resource_size_t start = res->start; ++ ++ if (res->flags & IORESOURCE_IO) { ++ if (size > 0x100) ++ printk(KERN_ERR "PCI: I/O Region %s/%d too large" ++ " (%ld bytes)\n", pci_name(dev), ++ dev->resource - res, (long int)size); ++ ++ if (start & 0x3ff) ++ start = (start + 0x3ff) & ~0x3ff; ++ } ++ ++ return start; ++} ++EXPORT_SYMBOL(pcibios_align_resource); ++ ++/* ++ * void __init coldfire_fixup(int pci_modify) ++ * ++ * Assign IRQ numbers as used by Linux to the interrupt pins ++ * of the PCI cards. ++ */ ++static void __init coldfire_fixup(int pci_modify) ++{ ++ struct pci_dev *dev; ++ unsigned char slot, pin; ++ ++ DBG("%s\n", __func__); ++#ifdef NL_ORIGINAL ++ pci_for_each_dev(dev) { ++#else ++ dev = NULL; ++ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { ++#endif ++ if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) { ++ slot = PCI_SLOT(dev->devfn); ++ dev->irq = 64 + board_info[slot].irq; ++ ++ /* Check if device needs interrupt */ ++#ifdef NL_ORIGINAL ++ pcibios_read_config_byte( ++ dev->bus->number, dev->devfn, ++ PCI_INTERRUPT_PIN, &pin); ++ ++ if (pin) { ++ pcibios_write_config_byte( ++ dev->bus->number, dev->devfn, ++ PCI_INTERRUPT_LINE, dev->irq); ++ } ++#else ++ pci_read_config_byte(dev, ++ PCI_INTERRUPT_PIN, &pin); ++ ++ if (pin) { ++ pci_write_config_byte(dev, ++ PCI_INTERRUPT_LINE, dev->irq); ++ } ++#endif ++ } ++ } ++} ++ ++static void __init configure_device(struct pci_dev *dev) ++{ ++ /* TODO: This should depend from disable_pci_burst setting */ ++ DBG("%s\n", __func__); ++#ifdef NL_ORIGINAL ++ pcibios_write_config_byte(bus, devfn, ++ PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE); ++#else ++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE); ++ ++ MCF_PCICR1 = MCF_PCICR1_LATTIMER(0xF8) | ++ MCF_PCICR1_CACHELINESIZE(PCI_CACHE_LINE); ++ ++#endif ++} ++ ++ ++struct pci_bus_info *__init init_coldfire_pci(void) ++{ ++ struct pci_bus_info *bus; ++ int i; ++ unsigned long pci_mem_va; ++ static char irq_name[N_IRQS][15]; ++ ++ MCF_SPCR |= 0x02; /*Enable the PCI clock*/ ++ ++ /* Get controller revision */ ++ revision = MCF_PCICCRIR; ++ printk(KERN_INFO "ColdFire PCI Host Bridge " ++ "(Rev. %d) detected:" ++ "MEMBase %x,MEMLen %x,IOBase %x,IOLen %x\n", ++ revision, HOST_MEM_BASE, ++ PCI_MEM_SIZE - 1, 0, PCI_IO_SIZE - 1); ++ ++ bus = (struct pci_bus_info *)kmalloc(sizeof(struct pci_bus_info), ++ GFP_KERNEL); ++ if (!bus) { ++ printk(KERN_ERR "can not alloc mem for pci bus!\n"); ++ return NULL; ++ } ++ ++ /* Setup bus info structure. */ ++ memset(bus, 0, sizeof(struct pci_bus_info)); ++ ++ /* Request intiator memory resource */ ++ bus->mem_space.start = PCI_MEM_BASE;/*HOST_MEM_BASE;*/ ++ bus->mem_space.end = bus->mem_space.start + PCI_MEM_SIZE - 1; ++ bus->mem_space.name = "PCI Bus #0"; ++ if (request_resource(&iomem_resource, ++ &(bus->mem_space)) != 0) { ++ printk(KERN_ERR "Failed to request bridge iomem resource\n"); ++ return NULL; ++ } ++ ++ /* Request intiator memory resource */ ++ /*bus->io_space.start = 0;*/ ++ bus->io_space.start = HOST_IO_BASE; ++ bus->io_space.end = bus->io_space.start + PCI_IO_SIZE - 1; ++ bus->io_space.name = "PCI Bus #0"; ++ if (request_resource(&ioport_resource, ++ &(bus->io_space)) != 0) { ++ printk(KERN_ERR "Failed to request bridge " ++ "ioport resource\n"); ++ return NULL; ++ } ++ ++ /* Must Reset!!! If bootloader has PCI enabled, it will cause ++ * problem in linux when it tries to configure/find resources ++ * for the pci devices. Both registers need to be reset. ++ */ ++ /*MCF_PCIGSCR |= 0x1;*/ ++ MCF_PCIGSCR = 0x1; ++ MCF_PCITCR = 0x00000000; ++ ++ /* Set up the arbiter */ ++ MCF_PCIARB_PACR = 0; /*MCF_PCIARB_PACR_PKMD*/ ++ ++ /* GNT and REQ */ ++ MCF_PAR_PCIBG = 0x3FF; ++ MCF_PAR_PCIBR = 0x3FF; ++ ++ /* Enable bus mastering, memory access and MWI */ ++ MCF_PCISCR = (MCF_PCISCR_B | MCF_PCISCR_M); ++ ++ /* Setup burst parameters */ ++ /*The offset 0x0e normally was header_type, set it to 0 and fix later*/ ++ MCF_PCICR1 = MCF_PCICR1_LATTIMER(0x00) | ++ MCF_PCICR1_CACHELINESIZE(PCI_CACHE_LINE); ++ ++ MCF_PCICR2 = 0; ++ /*MCF_PCICR2_MINGNT(PCI_MINGNT) | ++ MCF_PCICR2_MAXLAT(PCI_MAXLAT); ++ */ ++ /* Turn on error signaling */ ++ MCF_PCIICR = MCF_PCIICR_TAE | MCF_PCIICR_IAE | PCI_RETRIES; ++ MCF_PCIGSCR |= MCF_PCIGSCR_SEE; ++ /* ++ * Configure Initiator Windows ++ * Window 0: 128M PCI Memory @ HOST_MEM_BASE, 1:1 mapping ++ * Window 1: 64K I/O Memory @ HOST_IO_BASE, 1:0 mapping ++ */ ++ MCF_PCIIW0BTAR = WxBAR(HOST_MEM_BASE, PCI_MEM_BASE, PCI_MEM_SIZE); ++ MCF_PCIIW1BTAR = WxBAR(HOST_IO_BASE, PCI_IO_BASE_ADDR, PCI_IO_SIZE); ++ ++ MCF_PCIIWCR = MCF_PCIIWCR_WINCTRL1_IO | ++ MCF_PCIIWCR_WINCTRL0_MEMREAD; ++ ++ /* Target PCI DMA Windows */ ++ MCF_PCIBAR1 = PCI_DMA_BASE; ++ MCF_PCITBATR1 = HOST_DMA_BASE | MCF_PCITBATR1_EN; ++ ++ /* Enable internal PCI controller interrupts */ ++ MCF_ICR(ISC_PCI_XLB) = ILP_PCI_XLB; ++ /*request_irq(64+ISC_PCI_XLB, xlb_interrupt, ++ SA_INTERRUPT, "PCI XL Bus", (void*)-1); ++ enable_irq (64+ISC_PCI_XLB); ++ */ ++ if (request_irq(64+ISC_PCI_XLB, xlb_interrupt, ++ IRQF_DISABLED, "PCI XL Bus", (void *)-1)) { ++ printk(KERN_ERR "Cannot allocate " ++ "ISC_PCI_XLB IRQ\n"); ++ return (struct pci_bus_info *)-EBUSY; ++ } ++ ++ MCF_ICR(ISC_PCI_ARB) = ILP_PCI_ARB; ++ /*request_irq(64+ISC_PCI_ARB, arb_interrupt, ++ SA_INTERRUPT, "PCI Arbiter", (void*)-1); ++ enable_irq (64+ISC_PCI_ARB); ++ */ ++ if (request_irq(64 + ISC_PCI_ARB, arb_interrupt, ++ IRQF_DISABLED, "PCI Arbiter", (void *)-1)) { ++ printk(KERN_ERR "Cannot allocate " ++ "ISC_PCI_ARB IRQ\n"); ++ return (struct pci_bus_info *)-EBUSY; ++ } ++ ++ /* Set slots interrupt setting */ ++ for (i = 0; i < N_IRQS; i++) { ++ /* Set trailing edge for PCI interrupts */ ++ MCF_EPPAR &= ~MCF_EPPAR_EPPA(irq_lines[i], 0x3); ++ if (irq_lines[i] == 5) ++ MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i], ++ MCF_EPPAR_EPPAx_FALLING); ++ else ++ MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i], ++ 0/*MCF_EPPAR_EPPAx_FALLING*/); ++ /* Turn on irq line in eport */ ++ MCF_EPIER |= MCF_EPIER_EPIE(irq_lines[i]); ++ ++ /* Enable irq in gpio */ ++ if (irq_lines[i] == 5) ++ MCF_PAR_FECI2CIRQ |= 1; ++ ++ if (irq_lines[i] == 6) ++ MCF_PAR_FECI2CIRQ |= 2; ++ ++ /* Register external interrupt handlers */ ++ sprintf(irq_name[i], "PCI IRQ%d", irq_lines[i]); ++ /*request_irq(64 + irq_lines[i], eint_handler, ++ SA_SHIRQ, irq_name[i], (void*)-1); ++ enable_irq(64 + irq_lines[i]);*/ ++ if (request_irq(64 + irq_lines[i], eint_handler, ++ IRQF_SHARED, irq_name[i], (void *)-1)) { ++ printk(KERN_ERR "Cannot allocate " ++ "irq_lines[%d] IRQ\n", ++ irq_lines[i]); ++ return (struct pci_bus_info *)-EBUSY; ++ } ++ } ++ ++ /* Clear PCI Reset and wait for devices to reset */ ++ MCF_PCIGSCR &= ~MCF_PCIGSCR_PR; ++ schedule_timeout((5 * HZ)); ++ /* Remap initiator windows (should be 1:1 to the physical memory) */ ++ pci_mem_va = (int) ioremap_nocache(HOST_MEM_BASE, ++ PCI_MEM_SIZE + PCI_IO_SIZE); ++ udelay(1000); /* let every thing effect */ ++#if 1 ++ printk(KERN_INFO "%s: MEMBase_phy %x, Virt %x, len %x\n", ++ __func__, HOST_MEM_BASE, pci_mem_va, ++ PCI_MEM_SIZE + PCI_IO_SIZE); ++#endif ++ BUG_ON(pci_mem_va != HOST_MEM_BASE); ++ ++ /* Setup bios32 and pci bus driver callbacks */ ++ bus->m68k_pci_ops = &bus_ops; ++ bus->fixup = coldfire_fixup; ++ bus->conf_device = configure_device; ++ ++ return bus; ++} +--- /dev/null ++++ b/arch/m68k/coldfire/m547x/pci_dummy.S +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Author: Jason Jin <Jason.jin@freescale.com> ++ * ++ * This routine is the dummy function for PCI errata ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++.global _pci_dummy_function ++.global pci_dummy_function ++.text ++ ++pci_dummy_function: ++_pci_dummy_function: ++ ++/* force function start to 16-byte boundary.Can be done in linker file also */ ++.align 16 ++clr.l %d0 ++move.l %d0, 0xF0000F0C ++/* Must use direct addressing. write to EPORT module ++* xlbus -> slavebus -> eport, writing '0' to register has no ++* effect ++*/ ++ ++rts ++tpf.l #0x0 ++tpf.l #0x0 ++tpf.l #0x0 ++tpf.l #0x0 ++tpf.l #0x0 ++.end +--- /dev/null ++++ b/arch/m68k/include/asm/5445x_pci.h +@@ -0,0 +1,111 @@ ++/* ++ * asm-m68k/pci.h - m68k specific PCI declarations. ++ * ++ * Copyright (C) 2007, 2009-2011 Freescale Semiconductor, Inc. ++ * All Rights Reserved. ++ * Kurt Mahan <kmahan@freescale.com> ++ */ ++#ifndef _ASM_M68K_5445X_PCI_H ++#define _ASM_M68K_5445x_PCI_H ++ ++#ifndef CONFIG_PCI ++/* ++ * The PCI address space does equal the physical memory ++ * address space. The networking and block device layers use ++ * this boolean for bounce buffer decisions. ++ */ ++#define PCI_DMA_BUS_IS_PHYS (1) ++#else ++#include <asm-generic/pci-dma-compat.h> ++ ++#define PCI_DMA_BASE 0 /* PCI-DMA window base */ ++#define NL_ORIGINAL ++/* ++ * The PCI address space does equal the physical memory ++ * address space. The networking and block device layers use ++ * this boolean for bounce buffer decisions. ++ */ ++#define PCI_DMA_BUS_IS_PHYS (1) ++ ++#define PCIBIOS_MIN_IO 0x00004000 ++#define PCIBIOS_MIN_MEM 0x02000000 ++ ++#define pcibios_assign_all_busses() 0 ++#define pcibios_scan_all_fns(a, b) 0 ++ ++struct pci_raw_ops { ++ int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, ++ int reg, int len, u32 *val); ++ int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, ++ int reg, int len, u32 val); ++}; ++ ++extern struct pci_raw_ops *raw_pci_ops; ++ ++static inline void ++pcibios_set_master(struct pci_dev *dev) ++{ ++ /* no special bus mastering setup handling */ ++} ++ ++static inline void ++pcibios_penalize_isa_irq(int irq, int active) ++{ ++ /* no dynamic PCI IRQ allocation */ ++} ++ ++#if 0 ++static inline void ++pcibios_add_platform_entries(struct pci_dev *dev) ++{ ++ /* no special handling */ ++} ++#endif ++ ++static inline void ++pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, ++ struct resource *res) ++{ ++ region->start = res->start; ++ region->end = res->end; ++} ++ ++static inline void ++pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, ++ struct pci_bus_region *region) ++{ ++ res->start = region->start; ++ res->end = region->end; ++} ++ ++static inline struct resource * ++pcibios_select_root(struct pci_dev *pdev, struct resource *res) ++{ ++ struct resource *root = NULL; ++ ++ if (res->flags & IORESOURCE_IO) ++ root = &ioport_resource; ++ if (res->flags & IORESOURCE_MEM) ++ root = &iomem_resource; ++ ++ return root; ++} ++ ++#ifndef CONFIG_M54455_PCI_initcall ++extern int pci_init(void); ++extern int pcibios_init(void); ++#endif ++ ++extern void set_fpga(u32 *addr, u32 val); ++ ++#ifdef CONFIG_M54455 ++extern int init_mcf5445x_pci(void); ++extern void mcf5445x_conf_device(struct pci_dev *dev); ++extern void mcf5445x_pci_dumpregs(void); ++ ++extern struct resource pci_ioport_resource; ++extern struct resource pci_iomem_resource; ++#endif ++ ++#endif /* CONFIG_PCI */ ++#endif /* _ASM_M68K_5445X_PCI_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/548x_pci.h +@@ -0,0 +1,99 @@ ++/* ++ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Written by Wout Klaren. ++ */ ++ ++#ifndef _ASM_M68K_548X_PCI_H ++#define _ASM_M68K_548X_PCI_H ++ ++#include <linux/mm.h> ++#include <asm/scatterlist.h> ++ ++#include <asm-generic/pci.h> ++ ++struct pci_ops; ++ ++/* ++ * Structure with hardware dependent information and functions of the ++ * PCI bus. ++ */ ++ ++struct pci_bus_info { ++ /* ++ * Resources of the PCI bus. ++ */ ++ ++ struct resource mem_space; ++ struct resource io_space; ++ ++ /* ++ * System dependent functions. ++ */ ++ ++ struct pci_ops *m68k_pci_ops; ++ ++ void (*fixup)(int pci_modify); ++ void (*conf_device)(struct pci_dev *dev); ++}; ++ ++#define pcibios_assign_all_busses() 0 ++#define pcibios_scan_all_fns(a, b) 0 ++ ++static inline void pcibios_set_master(struct pci_dev *dev) ++{ ++ /* No special bus mastering setup handling */ ++} ++ ++static inline void pcibios_penalize_isa_irq(int irq) ++{ ++ /* We don't do dynamic PCI IRQ allocation */ ++} ++ ++#ifndef CONFIG_COLDFIRE ++/* The PCI address space does equal the physical memory ++ * address space. The networking and block device layers use ++ * this boolean for bounce buffer decisions. ++ */ ++#define PCI_DMA_BUS_IS_PHYS (1) ++ ++#define PCIBIOS_MIN_IO 0x00004000 ++#define PCIBIOS_MIN_MEM 0x04000000 ++ ++#else /* !CONFIG_COLDFIRE */ ++#include <asm-generic/pci-dma-compat.h> ++#define PCI_DMA_BASE /*0x40000000*/0 ++/* PCI-DMA window base */ ++ ++extern struct pci_bus_info *__init init_coldfire_pci(void); ++extern void *pci_alloc_son(struct pci_dev *, size_t, ++ dma_addr_t *, int); ++/* ++ * The PCI address space equal the virtual memory ++ * address space on m547X/m548X. ++ */ ++#define PCI_DMA_BUS_IS_PHYS (1) ++ ++#define PCIBIOS_MIN_IO 0x00000100 ++#define PCIBIOS_MIN_MEM 0x02000000 ++ ++struct scatterlist; ++ ++ ++/* This is always fine. */ ++#define pci_dac_dma_supported(pci_dev, mask) (1) ++ ++ ++/* These macros should be used after a pci_map_sg call has been done ++ * to get bus addresses of each of the SG entries and their lengths. ++ * You should only work with the number of sg entries pci_map_sg ++ * returns. ++ */ ++#define sg_dma_address(sg) ((sg)->dma_address) ++#define sg_dma_len(sg) ((sg)->length) ++ ++extern void pci_dummy_function(void); ++/*Declarations of hardware specific initialisation functions*/ ++extern struct pci_bus_info *init_hades_pci(void); ++ ++#endif /* !CONFIG_COLDFIRE*/ ++#endif /* _ASM_M68K_548X_PCI_H */ +--- a/arch/m68k/include/asm/pci.h ++++ b/arch/m68k/include/asm/pci.h +@@ -1,7 +1,13 @@ + #ifndef _ASM_M68K_PCI_H + #define _ASM_M68K_PCI_H + ++#if defined(CONFIG_M5445X) ++#include "5445x_pci.h" ++#elif defined(CONFIG_M547X_8X) ++#include "548x_pci.h" ++#else + #include <asm-generic/pci-dma-compat.h> ++#endif + + /* The PCI address space does equal the physical memory + * address space. The networking and block device layers use +--- /dev/null ++++ b/arch/m68k/kernel/bios32_mcf548x.c +@@ -0,0 +1,632 @@ ++/* ++ * bios32.c - PCI BIOS functions for m68k systems. ++ * ++ * Written by Wout Klaren. ++ * ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Shrek Wu B16972@freescale.com ++ * ++ * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger. ++ */ ++#include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/device.h> ++#include <linux/delay.h> ++ ++# define DBG_DEVS(args) ++ ++#ifdef CONFIG_PCI ++ ++/* ++ * PCI support for Linux/m68k. Currently only the Hades is supported. ++ * ++ * The support for PCI bridges in the DEC Alpha version has ++ * been removed in this version. ++ */ ++ ++#include <linux/pci.h> ++#include <linux/slab.h> ++#include <linux/mm.h> ++ ++#include <asm/io.h> ++#include <asm/pci.h> ++#include <asm/uaccess.h> ++ ++#define KB 1024 ++#define MB (1024*KB) ++#define GB (1024*MB) ++ ++#define MAJOR_REV 0 ++#define MINOR_REV 5 ++ ++/* ++ * Align VAL to ALIGN, which must be a power of two. ++ */ ++ ++#define MAX(val1, val2) (((val1) > (val2)) ? val1 : val2) ++ ++/* ++ * Offsets relative to the I/O and memory base addresses from where resources ++ * are allocated. ++ */ ++ ++#ifdef CONFIG_COLDFIRE ++#define IO_ALLOC_OFFSET 0x00000100 ++#define MEM_ALLOC_OFFSET 0x00000000 ++#else /* CONFIG_COLDFIRE */ ++#define IO_ALLOC_OFFSET 0x00004000 ++#define MEM_ALLOC_OFFSET 0x04000000 ++#endif /* CONFIG_COLDFIRE */ ++ ++/* ++ * Bus info structure of the PCI bus. A pointer to this structure is ++ * put in the sysdata member of the pci_bus structure. ++ */ ++ ++static struct pci_bus_info *bus_info; ++ ++static int pci_modify = 1; ++/* If set, layout the PCI bus ourself. */ ++static int skip_vga; ++/* If set do not modify base addresses of vga cards.*/ ++static int disable_pci_burst; ++/* If set do not allow PCI bursts. */ ++ ++static volatile unsigned int io_base; ++static volatile unsigned int mem_base; ++ ++/* ++ * static void disable_dev(struct pci_dev *dev) ++ * ++ * Disable PCI device DEV so that it does not respond to I/O or memory ++ * accesses. ++ * ++ * Parameters: ++ * ++ * dev - device to disable. ++ */ ++ ++static void __init disable_dev(struct pci_dev *dev) ++{ ++ unsigned short cmd; ++ ++ if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) || ++ (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) || ++ (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga) ++ return; ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ ++ cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++} ++ ++/* Stolen from pcibios_enable_resources/i386 */ ++int pcibios_enable_device(struct pci_dev *dev, int mask) ++{ ++ u16 cmd, old_cmd; ++ int idx; ++ struct resource *r; ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ old_cmd = cmd; ++ for (idx = 0; idx < 6; idx++) { ++ /* Only set up the requested stuff */ ++ if (!(mask & (1<<idx))) ++ continue; ++ ++ r = &dev->resource[idx]; ++ if (!r->start && r->end) { ++ printk(KERN_ERR "PCI: Device %s not" ++ " available because" ++ " of resource collisions\n", ++ dev_name(&(dev->dev))); ++ return -EINVAL; ++ } ++ if (r->flags & IORESOURCE_IO) ++ cmd |= PCI_COMMAND_IO; ++ if (r->flags & IORESOURCE_MEM) ++ cmd |= PCI_COMMAND_MEMORY; ++ } ++ if (dev->resource[PCI_ROM_RESOURCE].start) ++ cmd |= PCI_COMMAND_MEMORY; ++ if (cmd != old_cmd) { ++ printk(KERN_ERR "PCI: Enabling device " ++ "%s (%04x -> %04x)\n", ++ dev_name(&(dev->dev)), old_cmd, cmd); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ } ++ return 0; ++} ++ ++/* ++ * static void layout_dev(struct pci_dev *dev) ++ * ++ * Layout memory and I/O for a device. ++ * ++ * Parameters: ++ * ++ * device - device to layout memory and I/O for. ++ */ ++ ++static void __init layout_dev(struct pci_dev *dev) ++{ ++ unsigned short cmd; ++ unsigned int base, mask, size, reg; ++ unsigned int alignto; ++ int i; ++ ++ /* ++ * Skip video cards if requested. ++ */ ++ if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) || ++ (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) || ++ (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga) { ++ printk(KERN_ERR "%s: VGA\n", __func__); ++ return; ++ } ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ ++ for (reg = PCI_BASE_ADDRESS_0, i = 0; ++ reg <= PCI_BASE_ADDRESS_5; reg += 4, i++) { ++ /* ++ * Figure out how much space and of what type this ++ * device wants. ++ */ ++ ++ pci_write_config_dword(dev, reg, 0xffffffff); ++ pci_read_config_dword(dev, reg, &base); ++ if (!base) { ++ /* this base-address register is unused */ ++ dev->resource[i].start = 0; ++ dev->resource[i].end = 0; ++ dev->resource[i].flags = 0; ++ continue; ++ } ++ ++ /* ++ * We've read the base address register back after ++ * writing all ones and so now we must decode it. ++ */ ++ if (base & PCI_BASE_ADDRESS_SPACE_IO) { ++ /* ++ * I/O space base address register. ++ */ ++ ++ cmd |= PCI_COMMAND_IO; ++ ++ base &= PCI_BASE_ADDRESS_IO_MASK; ++ mask = (~base << 1) | 0x1; ++ size = (mask & base) & 0xffffffff; ++ ++ /* ++ * Align to multiple of size of minimum base. ++ */ ++ ++#ifdef CONFIG_COLDFIRE ++ alignto = MAX(PAGE_SIZE, size) ; ++#else /* !CONFIG_COLDFIRE */ ++ alignto = MAX(0x040, size) ; ++#endif /* CONFIG_COLDFIRE */ ++ base = ALIGN(io_base, alignto); ++ io_base = base + size; ++ pci_write_config_dword(dev, reg, ++ base | PCI_BASE_ADDRESS_SPACE_IO); ++ dev->resource[i].start = base; ++ dev->resource[i].end = ++ dev->resource[i].start + size - 1; ++ dev->resource[i].flags = ++ IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; ++ ++ DBG_DEVS(("layout_dev: IO address: %x\n", base)); ++ } else { ++ unsigned int type; ++ ++ /* ++ * Memory space base address register. ++ */ ++ cmd |= PCI_COMMAND_MEMORY; ++ ++ type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK; ++ base &= PCI_BASE_ADDRESS_MEM_MASK; ++ mask = (~base << 1) | 0x1; ++ size = (mask & base) & 0xffffffff; ++ switch (type) { ++ case PCI_BASE_ADDRESS_MEM_TYPE_32: ++ case PCI_BASE_ADDRESS_MEM_TYPE_64: ++ break; ++ ++ case PCI_BASE_ADDRESS_MEM_TYPE_1M: ++ printk(KERN_INFO "bios32 WARNING: slot %d," ++ " function %d " ++ "requests memory below 1MB---don't " ++ "know how to do that.\n", ++ PCI_SLOT(dev->devfn), ++ PCI_FUNC(dev->devfn)); ++ continue; ++ } ++ DBG_DEVS(("%s MEM: base %x,type %x,mask %x,size %x\n", ++ __func__, base, type, mask, size)); ++ /* ++ * Align to multiple of size of minimum base. ++ */ ++ ++ alignto = max_t(unsigned int, 0x1000, size); ++ base = ALIGN(mem_base, alignto); ++ mem_base = base + size; ++ pci_write_config_dword(dev, reg, base); ++ dev->resource[i].start = base; ++ dev->resource[i].end = ++ dev->resource[i].start + size - 1; ++ dev->resource[i].flags = IORESOURCE_MEM; ++ ++ DBG_DEVS(("%s MEM :base %x,size %x\n", ++ __func__, base, size)); ++ if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) { ++ /* ++ * 64-bit address, set the highest 32 bits ++ * to zero. ++ */ ++ ++ reg += 4; ++ pci_write_config_dword(dev, reg, 0); ++ ++ i++; ++ dev->resource[i].start = 0; ++ dev->resource[i].end = 0; ++ dev->resource[i].flags = 0; ++ printk(KERN_ERR "%s:type == 64\n", __func__); ++ } ++ } ++ } ++ /* ++ * Enable device: ++ */ ++ if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED || ++ dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA || ++ dev->class >> 8 == PCI_CLASS_DISPLAY_VGA || ++ dev->class >> 8 == PCI_CLASS_DISPLAY_XGA) { ++ /* ++ * All of these (may) have I/O scattered all around ++ * and may not use i/o-base address registers at all. ++ * So we just have to always enable I/O to these ++ * devices. ++ */ ++ cmd |= PCI_COMMAND_IO; ++ pci_write_config_word(dev, PCI_COMMAND, ++ cmd | PCI_COMMAND_MASTER); ++ } ++ ++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, ++ (disable_pci_burst) ? 0 : 32); ++ ++ if (bus_info != NULL) ++ bus_info->conf_device(dev); ++ /* Machine dependent configuration. */ ++ ++ printk(KERN_INFO "layout_dev: bus %d slot 0x%x " ++ "VID 0x%x DID 0x%x class 0x%x\n", ++ dev->bus->number, PCI_SLOT(dev->devfn), ++ dev->vendor, dev->device, dev->class); ++} ++ ++/* ++ * static void layout_bus(struct pci_bus *bus) ++ * ++ * Layout memory and I/O for all devices on the given bus. ++ * ++ * Parameters: ++ * ++ * bus - bus. ++ */ ++ ++static void __init layout_bus(struct pci_bus *bus) ++{ ++ unsigned int bio, bmem; ++ struct pci_dev *dev; ++ ++ DBG_DEVS(("layout_bus: starting bus %d\n", bus->number)); ++ ++ if (list_empty(&bus->devices) && list_empty(&bus->children)) ++ return; ++ ++ /* ++ * Align the current bases on appropriate boundaries (4K for ++ * IO and 1MB for memory). ++ */ ++ ++ bio = io_base = ALIGN(io_base, 4*KB); ++ bmem = mem_base = ALIGN(mem_base, 1*MB); ++ ++ /* ++ * PCI devices might have been setup by a PCI BIOS emulation ++ * running under TOS. In these cases there is a ++ * window during which two devices may have an overlapping ++ * address range. To avoid this causing trouble, we first ++ * turn off the I/O and memory address decoders for all PCI ++ * devices. They'll be re-enabled only once all address ++ * decoders are programmed consistently. ++ */ ++ ++ DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number)); ++ ++#ifdef NL_ORIGINAL ++ for (dev = bus->devices; dev; dev = dev->sibling) { ++#else ++ dev = NULL; ++ while ((dev = pci_get_device( ++ PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { ++#endif ++ if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) || ++ (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)) ++ disable_dev(dev); ++ } ++ ++ /* ++ * Allocate space to each device: ++ */ ++ ++ DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number)); ++ ++#ifdef NL_ORIGINAL ++ for (dev = bus->devices; dev; dev = dev->sibling) { ++#else ++ dev = NULL; ++ while ((dev = pci_get_device( ++ PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { ++#endif ++ ++ if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) || ++ (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)) ++ layout_dev(dev); ++ } ++ ++ DBG_DEVS(("layout_bus: bus %d finished\n", bus->number)); ++} ++ ++/* ++ * static void pcibios_fixup(void) ++ * ++ * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is ++ * true. This might be necessary because not every m68k machine with a PCI ++ * bus has a PCI BIOS. This function should be called right after ++ * pci_scan_bus() in pcibios_init(). ++ */ ++ ++static void __init pcibios_fixup(void) ++{ ++ DBG_DEVS(("%s\n", __func__)); ++ if (pci_modify) { ++ /* ++ * Set base addresses for allocation of I/O and memory space. ++ */ ++ ++ io_base = bus_info->io_space.start + IO_ALLOC_OFFSET; ++ mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET; ++ ++ /* ++ * Scan the tree, allocating PCI memory and I/O space. ++ */ ++ ++#ifdef NL_ORIGINAL ++ layout_bus(pci_bus_b(pci_root.next)); ++#else ++ layout_bus(pci_bus_b(pci_root_buses.next)); ++#endif ++ } ++ ++ /* ++ * Fix interrupt assignments, etc. ++ */ ++ ++ bus_info->fixup(pci_modify); ++} ++ ++/* ++ * static void pcibios_claim_resources(struct pci_bus *bus) ++ * ++ * Claim all resources that are assigned to devices on the given bus. ++ * ++ * Parameters: ++ * ++ * bus - bus. ++ */ ++ ++static void __init pcibios_claim_resources(struct pci_bus *bus) ++{ ++ struct pci_dev *dev; ++ int i; ++ DBG_DEVS(("%s\n", __func__)); ++#ifdef NL_ORIGINAL ++ while (bus) { ++#else ++ while ((bus = pci_find_next_bus(bus)) != NULL) { ++#endif ++ ++#ifdef NL_ORIGINAL ++ for (dev = bus->devices; (dev != NULL); ++ dev = dev->sibling) { ++#else ++ dev = NULL; ++ while ((dev = pci_get_device( ++ PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { ++#endif ++ for (i = 0; i < PCI_NUM_RESOURCES; i++) { ++ struct resource *r = &dev->resource[i]; ++ struct resource *pr; ++ struct pci_bus_info *bus_info = ++ (struct pci_bus_info *)dev->sysdata; ++ ++ if ((r->start == 0) || (r->parent != NULL)) ++ continue; ++ ++#ifdef CONFIG_COLDFIRE ++ if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) ++ continue; ++#endif /* CONFIG_COLDFIRE */ ++#if 1 ++ if (r->flags & IORESOURCE_IO) ++ pr = &bus_info->io_space; ++ else ++ pr = &bus_info->mem_space; ++#else ++ if (r->flags & IORESOURCE_IO) ++ pr = &ioport_resource; ++ else ++ pr = &iomem_resource; ++#endif ++ if (request_resource(pr, r) < 0) { ++#ifdef NL_ORIGINAL ++ DBG_DEVS(("PCI: Address space" ++ " collision on " ++ "region %d of device %s\n", ++ i, dev->name)); ++#else ++ printk(KERN_INFO "PCI: Address space" ++ " collision on region %d of" ++ " device %s\n", ++ i, dev_name(&(dev->dev))); ++#endif ++ } ++ } ++ ++#ifdef NL_ORIGINAL ++ } ++ if (bus->children) ++ pcibios_claim_resources(bus->children); ++#else ++ } ++ if (!list_empty(&bus->children)) ++ pcibios_claim_resources(pci_bus_b(bus->children.next)); ++#endif ++ ++#ifdef NL_ORIGINAL ++ bus = bus->next; ++#endif ++ } ++} ++ ++/* ++ * int pcibios_assign_resource(struct pci_dev *dev, int i) ++ * ++ * Assign a new address to a PCI resource. ++ * ++ * Parameters: ++ * ++ * dev - device. ++ * i - resource. ++ * ++ * Result: 0 if successful. ++ */ ++ ++int __init pcibios_assign_resource(struct pci_dev *dev, int i) ++{ ++ struct resource *r = &dev->resource[i]; ++ struct resource *pr = pci_find_parent_resource(dev, r); ++ unsigned long size = r->end + 1; ++ DBG_DEVS(("%s:IO_ALLOC_OFFSET %x\n", __func__, IO_ALLOC_OFFSET)); ++ if (!pr) ++ return -EINVAL; ++ ++ if (r->flags & IORESOURCE_IO) { ++ DBG_DEVS(("%s:IORESOURCE_IO:start %x, size %lx\n", ++ __func__, bus_info->io_space.start, size)); ++ if (size > 0x100) ++ return -EFBIG; ++ ++#ifdef NL_ORIGINAL ++ if (allocate_resource(pr, r, size, bus_info->io_space.start + ++ IO_ALLOC_OFFSET, ++ bus_info->io_space.end, ++ 1024)) ++#else ++ if (allocate_resource(pr, r, size, bus_info->io_space.start + ++ IO_ALLOC_OFFSET, ++ bus_info->io_space.end, ++ 1024, NULL, NULL)) ++#endif ++ return -EBUSY; ++ } else { ++ DBG_DEVS(("%s:IORESOURCE_MEM:start %x, size %lx\n", ++ __func__, bus_info->mem_space.start, size)); ++#ifdef NL_ORIGINAL ++ if (allocate_resource(pr, r, size, bus_info->mem_space.start + ++ MEM_ALLOC_OFFSET, ++ bus_info->mem_space.end, size)) ++#else ++ if (allocate_resource(pr, r, size, bus_info->io_space.start + ++ IO_ALLOC_OFFSET, bus_info->io_space.end, ++ 1024, NULL, NULL)) ++#endif ++ return -EBUSY; ++ } ++ ++ if (i < 6) ++ pci_write_config_dword(dev, ++ PCI_BASE_ADDRESS_0 + 4 * i, r->start); ++ ++ return 0; ++} ++ ++void pcibios_fixup_bus(struct pci_bus *bus) ++{ ++ struct pci_dev *dev; ++ void *sysdata; ++ ++ sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata; ++ ++#ifdef NL_ORIGINAL ++ for (dev = bus->devices; (dev != NULL); dev = dev->sibling) ++#else ++ dev = NULL; ++ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) ++#endif ++ dev->sysdata = sysdata; ++} ++ ++int __init pcibios_init(void) ++{ ++ printk(KERN_INFO "Linux/m68k PCI BIOS32 " ++ "revision %x.%02x\n", MAJOR_REV, MINOR_REV); ++ ++ bus_info = NULL; ++#ifdef CONFIG_COLDFIRE ++ bus_info = init_coldfire_pci(); ++#endif /* CONFIG_COLDFIRE */ ++#ifdef CONFIG_HADES ++ if (MACH_IS_HADES) ++ bus_info = init_hades_pci(); ++#endif ++ if (bus_info != NULL) { ++ printk(KERN_ERR "PCI: Probing PCI hardware\n"); ++ pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info); ++ pcibios_fixup(); ++#ifdef NL_ORIGINAL ++ pcibios_claim_resources(pci_root); ++#else ++ pcibios_claim_resources(pci_bus_b(pci_root_buses.next)); ++#endif ++ } else ++ printk(KERN_ERR "PCI: No PCI bus detected\n"); ++ return 0; ++} ++ ++subsys_initcall(pcibios_init); ++ ++char *pcibios_setup(char *str) ++{ ++ if (!strcmp(str, "nomodify")) { ++ pci_modify = 0; ++ return NULL; ++ } else if (!strcmp(str, "skipvga")) { ++ skip_vga = 1; ++ return NULL; ++ } else if (!strcmp(str, "noburst")) { ++ disable_pci_burst = 1; ++ return NULL; ++ } ++ ++ return str; ++} ++#endif /* CONFIG_PCI */ +--- a/drivers/pci/Makefile ++++ b/drivers/pci/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_X86_VISWS) += setup-irq.o + obj-$(CONFIG_MN10300) += setup-bus.o + obj-$(CONFIG_MICROBLAZE) += setup-bus.o + obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o ++obj-$(CONFIG_M54455) += setup-bus.o setup-irq.o + + # + # ACPI Related PCI FW Functions +--- a/drivers/pci/access.c ++++ b/drivers/pci/access.c +@@ -25,6 +25,7 @@ static DEFINE_RAW_SPINLOCK(pci_lock); + #define PCI_word_BAD (pos & 1) + #define PCI_dword_BAD (pos & 3) + ++#ifdef NL_ORIGINAL + #define PCI_OP_READ(size,type,len) \ + int pci_bus_read_config_##size \ + (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ +@@ -39,6 +40,23 @@ int pci_bus_read_config_##size \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ + return res; \ + } ++#else /* NL_ORIGINAL */ ++#define PCI_OP_READ(size, type, len) \ ++ int pci_bus_read_config_##size \ ++ (struct pci_bus *bus, unsigned int devfn, \ ++ int pos, type * value) \ ++{ \ ++ int res; \ ++ unsigned long flags; \ ++ if (PCI_##size##_BAD) \ ++ return PCIBIOS_BAD_REGISTER_NUMBER; \ ++ raw_spin_lock_irqsave(&pci_lock, flags); \ ++ res = bus->ops->read( \ ++ bus, devfn, pos, len, (u32 *)value); \ ++ raw_spin_unlock_irqrestore(&pci_lock, flags); \ ++ return res; \ ++} ++#endif /* NL_ORIGINAL */ + + #define PCI_OP_WRITE(size,type,len) \ + int pci_bus_write_config_##size \ +--- a/drivers/pci/setup-bus.c ++++ b/drivers/pci/setup-bus.c +@@ -77,7 +77,13 @@ static void __dev_sort_resources(struct + u16 class = dev->class >> 8; + + /* Don't touch classless devices or host bridges or ioapics. */ ++#ifdef CONFIG_M5445X ++ if (class == PCI_CLASS_NOT_DEFINED || \ ++ class == PCI_CLASS_BRIDGE_HOST || \ ++ class == PCI_CLASS_BRIDGE_OTHER) ++#else + if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) ++#endif + return; + + /* Don't touch ioapic devices already enabled by firmware */ +--- a/lib/iomap.c ++++ b/lib/iomap.c +@@ -227,9 +227,13 @@ EXPORT_SYMBOL(iowrite32_rep); + /* Create a virtual mapping cookie for an IO port range */ + void __iomem *ioport_map(unsigned long port, unsigned int nr) + { ++#ifndef CONFIG_M54455 + if (port > PIO_MASK) + return NULL; + return (void __iomem *) (unsigned long) (port + PIO_OFFSET); ++#else ++ return (void __iomem *) (unsigned long) port; ++#endif + } + + void ioport_unmap(void __iomem *addr) diff --git a/target/linux/coldfire/patches/040-Add-USB-support-for-MCF5445x-and-MCF54418.patch b/target/linux/coldfire/patches/040-Add-USB-support-for-MCF5445x-and-MCF54418.patch new file mode 100644 index 000000000..98984be2f --- /dev/null +++ b/target/linux/coldfire/patches/040-Add-USB-support-for-MCF5445x-and-MCF54418.patch @@ -0,0 +1,7007 @@ +From 632dc9e46a9ff032138f81fd420c0f01fd6c3cbc Mon Sep 17 00:00:00 2001 +From: Jason Jin <Jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 14:21:29 +0800 +Subject: [PATCH 40/52] Add USB support for MCF5445x and MCF54418 + +The OTG module function with external ULPI of USB3300 +on M5445xEVB and Modelo TWR-SER2, while the Max3353 charge +pump on Modelo TWR-SER1 with version-B CPU board only +function FS/LS tranceiver. +It also support USB host module on Modelo TWR-SER2. +And the host mode on M54455EVB with FS/LS only tranceiver +is supported by p4 interface on the board. + +Signed-off-by: Jingchang Lu <b35083@freescale.com> +--- + arch/m68k/Kconfig | 2 + + arch/m68k/coldfire/m5441x/Makefile | 4 +- + arch/m68k/coldfire/m5441x/max3353.h | 96 +++ + arch/m68k/coldfire/m5441x/max3353_otg.c | 508 +++++++++++++ + arch/m68k/coldfire/m5441x/max3353_xc.c | 310 ++++++++ + arch/m68k/coldfire/m5441x/usb.c | 276 +++++++ + arch/m68k/coldfire/m5441x/usb.h | 76 ++ + arch/m68k/coldfire/m5441x/usb_dr.c | 179 +++++ + arch/m68k/coldfire/m5441x/usb_host.c | 115 +++ + arch/m68k/coldfire/m5441x/xcvr.c | 198 +++++ + arch/m68k/coldfire/m5441x/xcvr_host.c | 53 ++ + arch/m68k/coldfire/m5445x/usb.c | 220 ++++++ + arch/m68k/coldfire/m5445x/usb.h | 107 +++ + arch/m68k/coldfire/m5445x/usb_dr.c | 152 ++++ + arch/m68k/coldfire/m5445x/xcvr.c | 127 ++++ + arch/m68k/include/asm/fsl_usb_gadget.h | 45 ++ + arch/m68k/include/asm/fsl_usb_io.h | 43 ++ + arch/m68k/include/asm/fsl_usb_platform.h | 78 ++ + drivers/Makefile | 1 + + drivers/usb/Kconfig | 2 + + drivers/usb/core/Kconfig | 2 +- + drivers/usb/gadget/Kconfig | 2 +- + drivers/usb/gadget/fsl_udc_core.c | 360 ++++++++- + drivers/usb/gadget/fsl_usb2_udc.h | 16 + + drivers/usb/gadget/serial.c | 40 +- + drivers/usb/host/Kconfig | 72 ++- + drivers/usb/host/ehci-fsl.c | 257 ++++++- + drivers/usb/host/ehci-fsl.h | 7 + + drivers/usb/host/ehci-hub.c | 34 + + drivers/usb/host/ehci.h | 55 ++- + drivers/usb/otg/Makefile | 7 + + drivers/usb/otg/fsl_otg.c | 1212 ++++++++++++++++++++++++++++++ + drivers/usb/otg/fsl_otg.h | 423 +++++++++++ + drivers/usb/otg/otg_fsm.c | 371 +++++++++ + drivers/usb/otg/otg_fsm.h | 151 ++++ + drivers/usb/otg/usb.c | 76 ++ + include/linux/fsl_devices.h | 26 + + include/linux/usb/fsl_usb2.h | 410 ++++++++++ + include/linux/usb/fsl_xcvr.h | 36 + + include/linux/usb/otg.h | 2 +- + 40 files changed, 6087 insertions(+), 64 deletions(-) + create mode 100644 arch/m68k/coldfire/m5441x/max3353.h + create mode 100644 arch/m68k/coldfire/m5441x/max3353_otg.c + create mode 100644 arch/m68k/coldfire/m5441x/max3353_xc.c + create mode 100644 arch/m68k/coldfire/m5441x/usb.c + create mode 100644 arch/m68k/coldfire/m5441x/usb.h + create mode 100644 arch/m68k/coldfire/m5441x/usb_dr.c + create mode 100644 arch/m68k/coldfire/m5441x/usb_host.c + create mode 100644 arch/m68k/coldfire/m5441x/xcvr.c + create mode 100644 arch/m68k/coldfire/m5441x/xcvr_host.c + create mode 100644 arch/m68k/coldfire/m5445x/usb.c + create mode 100644 arch/m68k/coldfire/m5445x/usb.h + create mode 100644 arch/m68k/coldfire/m5445x/usb_dr.c + create mode 100644 arch/m68k/coldfire/m5445x/xcvr.c + create mode 100644 arch/m68k/include/asm/fsl_usb_gadget.h + create mode 100644 arch/m68k/include/asm/fsl_usb_io.h + create mode 100644 arch/m68k/include/asm/fsl_usb_platform.h + create mode 100644 drivers/usb/otg/fsl_otg.c + create mode 100644 drivers/usb/otg/fsl_otg.h + create mode 100644 drivers/usb/otg/otg_fsm.c + create mode 100644 drivers/usb/otg/otg_fsm.h + create mode 100644 drivers/usb/otg/usb.c + create mode 100644 include/linux/usb/fsl_usb2.h + create mode 100644 include/linux/usb/fsl_xcvr.h + +--- a/arch/m68k/Kconfig ++++ b/arch/m68k/Kconfig +@@ -327,6 +327,7 @@ config M5445X + bool "MCF5445x support" + depends on COLDFIRE + select GENERIC_TIME ++ select USB_ARCH_HAS_EHCI + select USB_EHCI_FSL + select HAVE_FSL_USB_DR + help +@@ -430,6 +431,7 @@ config M5441X + depends on COLDFIRE + select GENERIC_TIME + select USB_EHCI_FSL ++ select USB_ARCH_HAS_EHCI + select HAVE_FSL_USB_DR + select HAVE_CAN_FLEXCAN + help +--- a/arch/m68k/coldfire/m5441x/Makefile ++++ b/arch/m68k/coldfire/m5441x/Makefile +@@ -14,9 +14,11 @@ endif + endif + + #ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),) +-ifneq ($(strip $(CONFIG_USB_OTG) $(CONFIG_USB_M5441X_MAX3353_FSLS)),) ++ifneq ($(strip $(CONFIG_USB_OTG)),) ++ifeq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)),) + obj-y += xcvr.o + endif ++endif + ifneq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)), ) + obj-y += max3353_xc.o + ifneq ($(strip $(CONFIG_USB_OTG)),) +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/max3353.h +@@ -0,0 +1,96 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef _MAX3353_H_ ++#define _MAX3353_H_ ++/* registers */ ++ ++/* Manufacturer registers */ ++#define MAX3353_MAN0 0x00 ++#define MAX3353_MAN1 0x01 ++#define MAX3353_MAN2 0x02 ++#define MAX3353_MAN3 0x03 ++ ++/* Product ID registers */ ++#define MAX3353_PID0 0x04 ++#define MAX3353_PID1 0x05 ++#define MAX3353_PID2 0x06 ++#define MAX3353_PID3 0x07 ++ ++/* Control register 1 */ ++#define MAX3353_CR1 0x10 ++#define CR1_DM_PULLDOWN (1 << 7) ++#define CR1_DP_PULLDOWN (1 << 6) ++#define CR1_DM_PULLUP (1 << 5) ++#define CR1_DP_PULLUP (1 << 4) ++#define CR1_BDISC_ACONN (1 << 2) ++#define CR1_IRQ_PUSH_PULL (1 << 1) ++ ++/* Control register 2 */ ++#define MAX3353_CR2 0x11 ++#define CR2_VBUS_DISCHRG (1 << 4) ++#define CR2_VBUS_DRV (1 << 3) ++#define CR2_VBUS_CHG2 (1 << 2) ++#define CR2_VBUS_CHG1 (1 << 1) ++#define CR2_SHUTDOWN (1 << 0) ++ ++/* Status register */ ++#define MAX3353_STATUS 0x13 ++#define STATUS_B_HNP (1 << 6) ++#define STATUS_A_HNP (1 << 5) ++#define STATUS_ID_FLOAT (1 << 4) ++#define STATUS_ID_GND (1 << 3) ++#define STATUS_SESSION_END (1 << 2) ++#define STATUS_SESSION_VALID (1 << 1) ++#define STATUS_VBUS_VALID (1 << 0) ++ ++/* Interrupt mask register */ ++#define MAX3353_INTR_MASK 0x14 ++#define IM_A_HNP_EN (1 << 5) ++#define IM_ID_FLOAT_EN (1 << 4) ++#define IM_ID_GND_EN (1 << 3) ++#define IM_SESSION_END_EN (1 << 2) ++#define IM_SESSION_VLD_EN (1 << 1) ++#define IM_VBUS_VLD_EN (1 << 0) ++ ++/* Interrupt edge register */ ++#define MAX3353_INTR_EDGE 0x15 ++#define IE_SESSION_VALID_ED (1 << 1) ++#define IE_VBUS_VLD_ED (1 << 0) ++ ++/* Interrupt latch register (read-only) */ ++#define MAX3353_INTR_LATCH 0x16 ++#define IL_A_HNP_RQ (1 << 7) ++#define IL_ID_FLOAT_RQ (1 << 6) ++#define IL_ID_GND_RQ (1 << 5) ++#define IL_SESSION_END_RQ (1 << 4) ++#define IL_SESSION_VALID_RN (1 << 3) ++#define IL_VBUS_VALID_RN (1 << 2) ++#define IL_SESSION_VALID_RP (1 << 1) ++#define IL_VBUS_VALID_RP (1 << 0) ++ ++ ++#define MAX3353_DEV_ADDR 0x2c ++#define MAX3353_IRQ (64 + 4) /* IRQ4 */ ++ ++extern u8 max3353_read_reg(u8 reg); ++extern void max3353_write_reg(u8 reg, u8 data); ++extern int max3353_read_id_pin(void); ++extern int otg_set_resources(struct resource *resources); ++ ++#endif /* _MAX3353_H_ */ +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/max3353_otg.c +@@ -0,0 +1,508 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/err.h> ++#include <linux/errno.h> ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/moduleparam.h> ++#include <linux/delay.h> ++#include <linux/sched.h> ++#include <linux/usb.h> ++#include <linux/usb/gadget.h> ++#include <linux/usb/otg.h> ++#include <linux/workqueue.h> ++#include <linux/time.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/usb/fsl_usb2.h> ++#include <linux/usb/otg.h> ++ ++#include <asm/fsl_usb_io.h> ++#include "max3353.h" ++ ++#define DRIVER_VERSION "1.0" ++#define DRIVER_AUTHOR "Freescale Semiconductor Inc." ++#define DRIVER_DESC "Freescale MAX3353 USBOTG Driver" ++#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC ++ ++MODULE_DESCRIPTION("Freescale MAX3353 USBOTG Driver"); ++ ++#if 0 ++#undef pr_debug ++#define pr_debug(x...) printk(x) ++#endif ++ ++static const char driver_name[] = "max3353-otg"; ++ ++const pm_message_t otg_suspend_state = { ++ .event = 1, ++}; ++ ++static volatile struct fsl_usb_device_regs *usb_dr_regs; ++ ++struct otg_fsm { ++ int id; /* 0=host 1=gadget */ ++ struct otg_fsm_ops *ops; ++ struct otg_transceiver *transceiver; ++}; ++ ++struct otg_fsm_ops { ++ int (*start_host)(struct otg_fsm *fsm, int on); ++ int (*start_gadget)(struct otg_fsm *fsm, int on); ++}; ++ ++struct max_otg { ++ struct otg_transceiver otg; ++ struct otg_fsm fsm; ++ struct delayed_work otg_event; ++ struct work_struct work_wq; ++ u8 host_working; ++ int irq; ++}; ++ ++static struct max_otg *max_otg_dev; ++ ++#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate) ++ ++ ++/* Reset controller, not reset the bus */ ++void otg_reset_controller(void) ++{ ++ u32 command; ++ ++ command = fsl_readl(&usb_dr_regs->usbcmd); ++ command |= (1 << 1); ++ fsl_writel(command, &usb_dr_regs->usbcmd); ++ while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1)) ++ ; ++} ++ ++ ++/* Call suspend/resume routines in host driver */ ++static int maxotg_start_host(struct otg_fsm *fsm, int on) ++{ ++ struct otg_transceiver *xceiv = fsm->transceiver; ++ struct device *dev; ++ struct max_otg *otg_dev = container_of(xceiv, struct max_otg, otg); ++ u32 retval = 0; ++ ++ pr_debug("%s: host %s\n", __func__, on ? "on" : "off"); ++ ++ if (!xceiv->host) ++ return -ENODEV; ++ dev = xceiv->host->controller; ++ ++ if (on) { ++ /* start fsl usb host controller */ ++ if (otg_dev->host_working) ++ goto end; ++ else { ++ otg_reset_controller(); ++ pr_debug("host on......\n"); ++ if (dev->driver->resume) ++ retval = dev->driver->resume(dev); ++ ++ otg_dev->host_working = 1; ++ } ++ } else { ++ /* stop fsl usb host controller */ ++ if (!otg_dev->host_working) ++ goto end; ++ else { ++ pr_debug("host off......\n"); ++ if (dev && dev->driver) ++ retval = dev->driver->suspend(dev, ++ otg_suspend_state); ++ otg_dev->host_working = 0; ++ } ++ } ++end: ++ return retval; ++} ++ ++/* Call suspend and resume function in udc driver ++ * to stop and start udc driver. ++ */ ++static int maxotg_start_gadget(struct otg_fsm *fsm, int on) ++{ ++ struct otg_transceiver *xceiv = fsm->transceiver; ++ struct device *dev; ++ ++ pr_debug("%s: gadget %s\n", __func__, on ? "on" : "off"); ++ ++ if (!xceiv->gadget || !xceiv->gadget->dev.parent) ++ return -ENODEV; ++ ++ dev = xceiv->gadget->dev.parent; ++ ++ if (on) ++ dev->driver->resume(dev); ++ else ++ dev->driver->suspend(dev, otg_suspend_state); ++ ++ return 0; ++} ++ ++ ++/* delayed interrupt handler */ ++static void handle_irq(struct work_struct *work) ++{ ++ u8 latch; ++ int id_host; ++ struct otg_fsm *fsm = &max_otg_dev->fsm; ++ struct otg_transceiver *otg = &max_otg_dev->otg; ++ ++ if (max_otg_dev == NULL) ++ return; ++ ++ latch = max3353_read_reg(MAX3353_INTR_LATCH); ++ ++ if (latch) { ++ id_host = max3353_read_id_pin(); ++ fsm->id = !id_host; ++ pr_debug("\t\t\t%s host mode %s\n", __func__, ++ id_host ? "ON" : "OFF"); ++ ++ if (otg->host) ++ otg->host->is_b_host = fsm->id; ++ if (otg->gadget) ++ otg->gadget->is_a_peripheral = !fsm->id; ++ ++ if (fsm->id) { /* switch to gadget */ ++ schedule_delayed_work(&max_otg_dev->otg_event, 100); ++ } else { /* switch to host */ ++ cancel_delayed_work(&max_otg_dev->otg_event); ++ maxotg_start_gadget(fsm, 0); ++ maxotg_start_host(fsm, 1); ++ } ++ } ++ enable_irq(MAX3353_IRQ); ++} ++ ++DECLARE_DELAYED_WORK(max3353_dwq, handle_irq); ++ ++/* ++ * MAX3353 interrupt handler ++ * ++ * We're interested in ID pin changes. Since we can't do i2c ++ * operations from interrupt context, we use a delayed workqueue ++ * routine to clear the interrupt in the MAX3353, and to handle ++ * the role switching. The delay also allows for debouncing the ++ * state of the ID pin. To avoid the flood of interrupts between ++ * the irq and its processing, we disable the irq here, and re-enable ++ * it in the delayed routine. ++ */ ++irqreturn_t max3353_isr(int irq, void *dev_id) ++{ ++ disable_irq(MAX3353_IRQ); ++ schedule_delayed_work(&max3353_dwq, 25); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++/* Called by initialization code of host driver. Register host controller ++ * to the OTG. Suspend host for OTG role detection. ++ */ ++static int set_host(struct otg_transceiver *otg_p, struct usb_bus *host) ++{ ++ struct max_otg *otg_dev = container_of(otg_p, struct max_otg, otg); ++ ++ pr_debug("%s() host %p\n", __func__, host); ++ ++ if (!otg_p || otg_dev != max_otg_dev) ++ return -ENODEV; ++ ++ otg_p->host = host; ++ if (host) { ++ pr_debug("host off......\n"); ++ ++ /* must leave time for khubd to finish its thing ++ * before yanking the host driver out from under it, ++ * so suspend the host after a short delay. ++ */ ++ otg_dev->host_working = 1; ++ schedule_delayed_work(&otg_dev->otg_event, 100); ++ return 0; ++ } else { /* host driver going away */ ++ if (max3353_read_id_pin()) { ++ /* Mini-A cable connected */ ++ otg_p->state = OTG_STATE_UNDEFINED; ++ } ++ } ++ ++ otg_dev->host_working = 0; ++ ++ return 0; ++} ++ ++/* Called by initialization code of udc. Register udc to OTG.*/ ++static int set_peripheral(struct otg_transceiver *otg_p, ++ struct usb_gadget *gadget) ++{ ++ struct max_otg *otg_dev = container_of(otg_p, struct max_otg, otg); ++ ++ pr_debug("%s gadget %p\n", __func__, gadget); ++ ++ pr_debug("otg_dev 0x%x\n", (int)otg_dev); ++ pr_debug("max_otg_dev 0x%x\n", (int)max_otg_dev); ++ ++ if (!otg_p || otg_dev != max_otg_dev) ++ return -ENODEV; ++ ++ if (!gadget) { ++ if (!otg_dev->otg.default_a) ++ otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0); ++ usb_gadget_vbus_disconnect(otg_dev->otg.gadget); ++ otg_dev->otg.gadget = 0; ++ return 0; ++ } ++ ++ otg_p->gadget = gadget; ++ otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id; ++ ++ /* start the gadget right away if the ID pin says Mini-B */ ++ pr_debug("ID pin=%d\n", otg_dev->fsm.id); ++ if (otg_dev->fsm.id == 1) { ++ maxotg_start_host(&otg_dev->fsm, 0); ++ maxotg_start_gadget(&otg_dev->fsm, 1); ++ } ++ ++ return 0; ++} ++ ++/* Set OTG port power, only for B-device */ ++static int set_power(struct otg_transceiver *otg_p, unsigned mA) ++{ ++ return 0; ++} ++ ++/* Delayed pin detect interrupt processing. ++ * ++ * When the Mini-A cable is disconnected from the board, ++ * the pin-detect interrupt happens before the disconnnect ++ * interrupts for the connected device(s). In order to ++ * process the disconnect interrupt(s) prior to switching ++ * roles, the pin-detect interrupts are delayed, and handled ++ * by this routine. ++ */ ++static void maxotg_event(struct work_struct *work) ++{ ++ struct max_otg *og = container_of(work, struct max_otg, otg_event.work); ++ struct otg_fsm *fsm = &og->fsm; ++ ++ if (fsm->id) { /* switch to gadget */ ++ maxotg_start_host(fsm, 0); ++ maxotg_start_gadget(fsm, 1); ++ } ++} ++ ++ ++static struct otg_fsm_ops maxotg_ops = { ++ .start_host = maxotg_start_host, ++ .start_gadget = maxotg_start_gadget, ++}; ++ ++ ++/* Initialize the global variable max_otg_dev and request IRQ for OTG */ ++static int maxotg_conf(struct platform_device *pdev) ++{ ++ int status; ++ struct max_otg *max_otg_tc; ++ struct fsl_usb2_platform_data *pdata; ++ ++ pdata = pdev->dev.platform_data; ++ ++ pr_debug("%s\n", __func__); ++ ++ if (max_otg_dev) ++ return 0; ++ ++ /* allocate space to fsl otg device */ ++ max_otg_tc = kzalloc(sizeof(struct max_otg), GFP_KERNEL); ++ if (!max_otg_tc) ++ return -ENODEV; ++ ++ INIT_DELAYED_WORK(&max_otg_tc->otg_event, maxotg_event); ++ ++ /* Set OTG state machine operations */ ++ max_otg_tc->fsm.ops = &maxotg_ops; ++ ++ /* initialize the otg structure */ ++ max_otg_tc->otg.label = DRIVER_DESC; ++ max_otg_tc->otg.set_host = set_host; ++ max_otg_tc->otg.set_peripheral = set_peripheral; ++ max_otg_tc->otg.set_power = set_power; ++ ++ max_otg_dev = max_otg_tc; ++ pr_debug("%s: set max_otg_dev %p, fsm %p\n", __func__, ++ max_otg_dev, &max_otg_dev->fsm); ++ ++ /* Store the otg transceiver */ ++ status = otg_set_transceiver(&max_otg_tc->otg); ++ if (status) { ++ printk(KERN_WARNING ": unable to register OTG transceiver.\n"); ++ return status; ++ } ++ ++ return 0; ++} ++ ++/* OTG Initialization*/ ++static int maxotg_start(struct platform_device *pdev) ++{ ++ struct max_otg *p_otg; ++ struct otg_transceiver *otg_trans = otg_get_transceiver(); ++ struct otg_fsm *fsm; ++ int status; ++ struct resource *res; ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ ++ p_otg = container_of(otg_trans, struct max_otg, otg); ++ fsm = &p_otg->fsm; ++ ++ /* Initialize the state machine structure with default values */ ++ SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED); ++ fsm->transceiver = &p_otg->otg; ++ ++ /* We don't require predefined MEM/IRQ resource index */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENXIO; ++ ++ /* ++ * We don't request_mem_region here to enable resource sharing ++ * with host/device ++ */ ++ usb_dr_regs = ioremap(res->start, sizeof(struct fsl_usb_device_regs)); ++ pdata->regs = (void *)usb_dr_regs; ++ pr_debug("ioremap %x to %p\n", res->start, pdata->regs); ++ ++ if (pdata->init && pdata->init(pdev) != 0) ++ return -EINVAL; ++ ++ /* grab the irq */ ++ status = request_irq(MAX3353_IRQ, max3353_isr, IRQF_DISABLED, ++ driver_name, p_otg); ++ if (status) { ++ printk(KERN_ERR "max3353: can't get IRQ, rc %d\n", status); ++ return -EINVAL; ++ } ++ ++ /* enable interrupts on the part */ ++ pr_debug("%s: enabling MAX3353 interrupts\n", __func__); ++ max3353_write_reg(MAX3353_INTR_MASK, IM_ID_GND_EN | IM_ID_FLOAT_EN); ++ ++ /* Export DR controller resources */ ++ otg_set_resources(pdev->resource); ++ ++ /* record initial state of ID pin */ ++ p_otg->fsm.id = !max3353_read_id_pin(); ++ if (p_otg->fsm.id) ++ p_otg->otg.state = OTG_STATE_UNDEFINED; ++ else ++ p_otg->otg.state = OTG_STATE_A_IDLE; ++ ++ pr_debug("initial ID pin: fsm.id=%d (%s)\n", p_otg->fsm.id, ++ p_otg->fsm.id ? "gadget" : "host"); ++ ++ return 0; ++} ++ ++static int __init maxotg_probe(struct platform_device *pdev) ++{ ++ int status; ++ struct fsl_usb2_platform_data *pdata; ++ ++ pr_debug("%s: pdev=0x%p\n", __func__, pdev); ++ ++ if (!pdev) ++ return -ENODEV; ++ ++ if (!pdev->dev.platform_data) ++ return -ENOMEM; ++ ++ pdata = pdev->dev.platform_data; ++ fsl_set_usb_accessors(pdata); ++ ++ /* configure the OTG */ ++ status = maxotg_conf(pdev); ++ if (status) { ++ printk(KERN_INFO "Couldn't init OTG module\n"); ++ return -status; ++ } ++ ++ /* start OTG */ ++ status = maxotg_start(pdev); ++ ++ return status; ++} ++ ++static int __exit maxotg_remove(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ ++ /* disable max3353 interrupts */ ++ max3353_write_reg(MAX3353_INTR_MASK, 0); ++ ++ otg_set_transceiver(NULL); ++ free_irq(MAX3353_IRQ, max_otg_dev); ++ ++ iounmap((void *)usb_dr_regs); ++ ++ kfree(max_otg_dev); ++ max_otg_dev = NULL; ++ ++ if (pdata->exit) ++ pdata->exit(pdev); ++ ++ return 0; ++} ++ ++struct platform_driver max3353_otg_driver = { ++ .probe = maxotg_probe, ++ .remove = __exit_p(maxotg_remove), ++ .driver = { ++ .name = driver_name, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++ ++static int __init maxotg_init(void) ++{ ++ printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION); ++ return platform_driver_register(&max3353_otg_driver); ++} ++ ++static void __exit maxotg_exit(void) ++{ ++ platform_driver_unregister(&max3353_otg_driver); ++ printk(KERN_INFO DRIVER_DESC " unloaded\n"); ++} ++ ++module_init(maxotg_init); ++module_exit(maxotg_exit); ++ ++MODULE_DESCRIPTION(DRIVER_INFO); ++MODULE_AUTHOR(DRIVER_AUTHOR); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/max3353_xc.c +@@ -0,0 +1,310 @@ ++/* ++ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++#define DEBUG ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/slab.h> ++#include <linux/io.h> ++#include <linux/i2c.h> ++#include <linux/usb/fsl_xcvr.h> ++#include <asm/mcfsim.h> ++#include "max3353.h" ++ ++#define DRIVER_DESC "Freescale MAX3353 Driver" ++ ++static struct i2c_device_id max3353_id[] = { ++ {"max3353", 0}, ++ {} ++}; ++MODULE_DEVICE_TABLE(i2c, max3353_id); ++ ++struct max3353_state { ++ struct i2c_client *client; ++}; ++ ++static int max3353_probe(struct i2c_client *client, ++ const struct i2c_device_id *id); ++static int __devexit max3353_remove(struct i2c_client *client); ++ ++static struct i2c_driver max3353_i2c_driver = { ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "max3353", ++ }, ++ .probe = max3353_probe, ++ .remove = __devexit_p(max3353_remove), ++ .id_table = max3353_id, ++}; ++ ++static struct i2c_client *max3353_i2c_client; ++ ++/* Write a max3353 register*/ ++void max3353_write_reg(u8 reg, u8 data) ++{ ++ i2c_smbus_write_byte_data(max3353_i2c_client, reg, data); ++} ++EXPORT_SYMBOL(max3353_write_reg); ++ ++/* Read a max3353 register*/ ++u8 max3353_read_reg(u8 reg) ++{ ++ return i2c_smbus_read_byte_data(max3353_i2c_client, reg); ++} ++EXPORT_SYMBOL(max3353_read_reg); ++ ++/* ++ * max3353 I2C probe function ++ */ ++ ++static int max3353_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct max3353_state *state; ++ struct device *dev = &client->dev; ++ ++ state = kzalloc(sizeof(struct max3353_state), GFP_KERNEL); ++ if (state == NULL) { ++ dev_err(dev, "failed to create our state\n"); ++ return -ENOMEM; ++ } ++ ++ state->client = client; ++ i2c_set_clientdata(client, state); ++ ++ max3353_i2c_client = client; ++ ++ /* rest of the initialisation goes here. */ ++ printk(KERN_INFO "MAX3353 USB charge pump detected\n"); ++ pr_debug("MANUF:%02x %02x %02x %02x PID:%02x %02x %02x %02x\n", ++ max3353_read_reg(MAX3353_MAN0), ++ max3353_read_reg(MAX3353_MAN1), ++ max3353_read_reg(MAX3353_MAN2), ++ max3353_read_reg(MAX3353_MAN3), ++ max3353_read_reg(MAX3353_PID0), ++ max3353_read_reg(MAX3353_PID1), ++ max3353_read_reg(MAX3353_PID2), ++ max3353_read_reg(MAX3353_PID3)); ++ pr_debug("%s done\n", __func__); ++ ++ return 0; ++ ++} ++ ++/* ++ * max3353 I2C remove function ++ */ ++static int __devexit max3353_remove(struct i2c_client *client) ++{ ++ struct max3353_state *state = i2c_get_clientdata(client); ++ ++ max3353_i2c_client = NULL; ++ ++ kfree(state); ++ return 0; ++} ++ ++static int max3353_running; ++ ++static void max3353_init(struct fsl_xcvr_ops *this) ++{ ++ int __maybe_unused rc; ++ u8 tmp; ++ ++ pr_debug("%s\n", __func__); ++ ++ if (!max3353_running) { ++ i2c_add_driver(&max3353_i2c_driver); ++ ++ /* disable interrupts on the part */ ++ max3353_write_reg(MAX3353_INTR_MASK, 0); ++ ++ /* configure irq mode */ ++ tmp = max3353_read_reg(MAX3353_CR1); ++ tmp |= CR1_IRQ_PUSH_PULL; ++ max3353_write_reg(MAX3353_CR1, tmp); ++ ++ /* take the part out of shutdown */ ++ tmp = max3353_read_reg(MAX3353_CR2); ++ tmp &= ~CR2_SHUTDOWN; /* turn on the part */ ++ max3353_write_reg(MAX3353_CR2, tmp); ++ } ++ max3353_running++; ++#if 0 ++ /* configure INT2 for max3353 INT */ ++ MCF_GPIO_PAR_IRQ0L = ++ (MCF_GPIO_PAR_IRQ0L & MCF_GPIO_PAR_IRQL_IRQ2_MASK) | ++ MCF_GPIO_PAR_IRQL_IRQ2_IRQ2; ++#else ++ /* ++ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7; ++ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_LEVEL; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7; ++ MCF_INTC0_ICR7 = 2; ++ */ ++ /* use IRQ4 on Twr-Ser1 board by J11 selected */ ++ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ4_IRQ4; ++ MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA4_LEVEL; ++ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE4; ++ MCF_INTC0_ICR4 = 7; ++ ++#endif ++ /* Configure USB_DP_PDOWN/USB_DM_PDOWN */ ++ MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT0; ++ MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT1; ++ MCF_GPIO_PDDR_I |= 0xc0; ++ MCF_GPIO_PODR_I &= 0x3f; ++ ++ /* Enable VBUS_EN and VBUS_OC signals */ ++ MCF_GPIO_PAR_TIMER = ++ (MCF_GPIO_PAR_TIMER & ++ MCF_GPIO_PAR_TIMER_T3IN_MASK) | ++ MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN; ++ ++ MCF_GPIO_PAR_TIMER = ++ (MCF_GPIO_PAR_TIMER & ++ MCF_GPIO_PAR_TIMER_T0IN_MASK) | ++ MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC; ++ ++ /* Setup USB_VBUS_OC signal to be active-low */ ++ MCF_CCM_MISCCR &= (~MCF_CCM_MISCCR_USBOOC); ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBPUE; ++} ++ ++static void max3353_uninit(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s\n", __func__); ++ ++ max3353_running--; ++ if (!max3353_running) ++ i2c_del_driver(&max3353_i2c_driver); ++} ++ ++/* set max3353 as USB host */ ++static inline void max3353_set_host(void) ++{ ++ u8 cr1, cr2, status; ++ pr_debug("%s\n", __func__); ++ ++ /* configure transceiver for host mode */ ++ cr1 = max3353_read_reg(MAX3353_CR1); ++ cr2 = max3353_read_reg(MAX3353_CR2); ++ status = max3353_read_reg(MAX3353_STATUS); ++ pr_debug("before: CR1 %02x CR2 %02x STATUS %02x\n", cr1, cr2, status); ++ ++ cr1 &= ~(CR1_DM_PULLDOWN | CR1_DP_PULLDOWN | ++ CR1_DM_PULLUP | CR1_DP_PULLUP); ++ cr1 |= (CR1_DP_PULLDOWN | CR1_DM_PULLDOWN); ++ max3353_write_reg(MAX3353_CR1, cr1); ++ ++ cr1 = max3353_read_reg(MAX3353_CR1); ++ cr2 = max3353_read_reg(MAX3353_CR2); ++ status = max3353_read_reg(MAX3353_STATUS); ++ pr_debug(" after: CR1 %02x CR2 %02x STATUS %02x\n", cr1, cr2, status); ++} ++ ++/* set max3353 as USB device */ ++static inline void max3353_set_dev(void) ++{ ++ u8 cr1; ++ pr_debug("%s\n", __func__); ++ ++ /* FS mode, DP pull up */ ++ cr1 = max3353_read_reg(MAX3353_CR1); ++ cr1 &= ~(CR1_DM_PULLDOWN | CR1_DM_PULLDOWN | CR1_DP_PULLDOWN); ++ cr1 |= CR1_DP_PULLUP; ++ max3353_write_reg(MAX3353_CR1, cr1); ++ ++} ++ ++static void max3353_set_vbus_power(struct fsl_xcvr_ops *this, int on) ++{ ++ pr_debug("%s(on=%d)\n", __func__, on); ++} ++ ++ ++/* Enable or disable the D+ pullup. */ ++static void max3353_pullup(int on) ++{ ++ u8 cr1; ++ unsigned short ccm; ++ ++ pr_debug("%s(%d)\n", __func__, on); ++ ++ cr1 = max3353_read_reg(MAX3353_CR1); ++ cr1 &= ~(CR1_DM_PULLDOWN | CR1_DP_PULLDOWN | ++ CR1_DM_PULLUP | CR1_DP_PULLUP); ++ ++ ccm = MCF_CCM_UOCSR; ++ if (on) { ++ cr1 |= CR1_DP_PULLUP; ++ ccm |= MCF_CCM_UOCSR_BVLD; ++ ccm &= ~MCF_CCM_UOCSR_SEND; ++ } else { ++ ccm &= ~MCF_CCM_UOCSR_BVLD; ++ } ++ ++ max3353_write_reg(MAX3353_CR1, cr1); ++ MCF_CCM_UOCSR = ccm; ++} ++ ++/* ++ * return the state of the ID pin. ++ * return: 0 Mini-B or nothing connected (Gadget mode) ++ * 1 Mini-A connected (Host mode) ++ */ ++int max3353_read_id_pin(void) ++{ ++ u8 status = max3353_read_reg(MAX3353_STATUS); ++ return !!(status & STATUS_ID_GND); ++} ++EXPORT_SYMBOL(max3353_read_id_pin); ++ ++static struct fsl_xcvr_ops max3353_ops = { ++ .name = "dr-max3353", ++ .init = max3353_init, ++ .uninit = max3353_uninit, ++ .set_host = max3353_set_host, ++ .set_device = max3353_set_dev, ++ .set_vbus_power = max3353_set_vbus_power, ++ .pullup = max3353_pullup, ++}; ++ ++/* module init routine. register the transceiver */ ++static int __init max3353xc_init(void) ++{ ++ pr_debug("%s\n", __func__); ++ ++ fsl_usb_xcvr_register(&max3353_ops); ++ return 0; ++} ++ ++static void __exit max3353xc_exit(void) ++{ ++ pr_debug("%s\n", __func__); ++ fsl_usb_xcvr_unregister(&max3353_ops); ++} ++ ++module_init(max3353xc_init); ++module_exit(max3353xc_exit); ++ ++MODULE_ALIAS("max3353"); ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("max3353 transceiver driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/usb.c +@@ -0,0 +1,276 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/err.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/usb/fsl_xcvr.h> ++#include <asm/mcfsim.h> ++ ++#define MCF_SCM_BCR MCF_REG32(0xFC040024) ++#define MCF_SCM_BCR_GBR (1 << 9) /* global bursts for read */ ++#define MCF_SCM_BCR_GBW (1 << 8) /* global bursts for write */ ++#define MCF_SCM_BCR_SBE_ALL (0xff << 0) /* slave burst enable */ ++ ++#define MAX_XCVR 3 ++struct fsl_xcvr_ops *g_xc_ops[MAX_XCVR] = { NULL }; ++ ++#ifdef ULPI_DEBUG ++void print_ulpi_regs(void) ++{ ++ pr_debug("MCF_SCM_BCR=0x%08lx MCF_CCM_MISCCR=0x%08x " ++ "MCF_CCM_MISSCR2=0x%08x " ++ "MCF_GPIO_PAR_TIMER=0x%08x MCF_GPIO_PAR_FEC=08%08x " ++ "MCF_GPIO_PAR_SIMP0H=08%08x MCF_GPIO_PODR_G=08%08x\n", ++ MCF_SCM_BCR, MCF_CCM_MISCCR, ++ MCF_CCM_MISCCR2, MCF_GPIO_PAR_TIMER, ++ MCF_GPIO_PAR_FEC, MCF_GPIO_PAR_SIMP0H, MCF_GPIO_PODR_G); ++} ++EXPORT_SYMBOL(print_ulpi_regs); ++#endif ++ ++static inline void fsl_usb_enable_clk(void) ++{ ++ pr_debug("%s\n", __func__); ++ ++#if defined(CONFIG_USB_M5441X_MAX3353_FSLS) ++ MCF_PM_PPMCR0 = 0x30; ++ MCF_CCM_MISCCR &= ~(MCF_CCM_MISCCR_USBOOC | MCF_CCM_MISCCR_USBHOC); ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBSRC; ++#elif !defined(CONFIG_USB_M5441X_PLLCLK) ++ /* Use external clock source if PLL isn't a multiple of 60MHz */ ++ MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC; ++ ++ /* Initialize the USB Clock: use USB input clock */ ++ MCF_GPIO_PAR_IRQ0L = ++ (MCF_GPIO_PAR_IRQ0L & ++ MCF_GPIO_PAR_IRQL_IRQ6_MASK) | ++ MCF_GPIO_PAR_IRQL_IRQ6_USBCLKIN; ++#else ++ uint fvco, usbclk; ++ ++ fvco = CONFIG_MCFCLK * ((MCF_PLL_DR & MCF_PLL_DR_OUTDIV1) + 1); ++ usbclk = fvco / (((MCF_PLL_DR & MCF_PLL_DR_OUTDIV4) >> 16) + 1); ++ ++ if (usbclk != 60000000) ++ printk(KERN_ERR, "The usb host clock must be 60MHZ!\n\n"); ++ ++ MCF_PM_PPMCR0 = 0x30; ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBSRC; ++#endif ++} ++ ++static inline void fsl_usb_disable_clk(void) ++{ ++ pr_debug("%s\n", __func__); ++} ++ ++void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) ++{ ++ int i; ++ ++ pr_debug("%s '%s'\n", __func__, xcvr_ops->name); ++ for (i = 0; i < MAX_XCVR; i++) { ++ if (g_xc_ops[i] == NULL) { ++ g_xc_ops[i] = xcvr_ops; ++ return; ++ } ++ } ++ ++ pr_debug("%s failed\n", __func__); ++} ++EXPORT_SYMBOL_GPL(fsl_usb_xcvr_register); ++ ++void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops) ++{ ++ int i; ++ ++ pr_debug("%s '%s'\n", __func__, xcvr_ops->name); ++ for (i = 0; i < MAX_XCVR; i++) { ++ if (g_xc_ops[i] == xcvr_ops) { ++ g_xc_ops[i] = NULL; ++ return; ++ } ++ } ++ ++ pr_debug("%s failed\n", __func__); ++} ++EXPORT_SYMBOL_GPL(fsl_usb_xcvr_unregister); ++ ++static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name) ++{ ++ int i; ++ ++ pr_debug("%s '%s'\n", __func__, name); ++ if (name == NULL) { ++ printk(KERN_ERR "get_xcvr(): No tranceiver name\n"); ++ return NULL; ++ } ++ ++ for (i = 0; i < MAX_XCVR; i++) { ++ if (strcmp(g_xc_ops[i]->name, name) == 0) ++ return g_xc_ops[i]; ++ } ++ pr_debug("Failed %s\n", __func__); ++ return NULL; ++} ++ ++/* The dmamask must be set for EHCI to work */ ++static u64 ehci_dmamask = ~(u32) 0; ++ ++/*! ++ * Register an instance of a USB host platform device. ++ * ++ * @param res: resource pointer ++ * @param n_res: number of resources ++ * @param config: config pointer ++ * ++ * @return newly-registered platform_device ++ * ++ * Each supported host interface is registered as an instance ++ * of the "fsl-ehci" device. Call this function multiple times ++ * to register each host interface. ++ */ ++static int instance_id; ++struct platform_device *host_pdev_register(struct resource *res, int n_res, ++ struct fsl_usb2_platform_data *config) ++{ ++ struct platform_device *pdev; ++ int rc; ++ ++ pr_debug("register host res=0x%p, size=%d\n", res, n_res); ++ ++ pdev = platform_device_register_simple("fsl-ehci", ++ instance_id, res, n_res); ++ if (IS_ERR(pdev)) { ++ printk(KERN_ERR "usb: can't register %s Host, %ld\n", ++ config->name, PTR_ERR(pdev)); ++ return NULL; ++ } ++ ++ pdev->dev.coherent_dma_mask = 0xffffffff; ++ pdev->dev.dma_mask = &ehci_dmamask; ++ ++ rc = platform_device_add_data(pdev, config, ++ sizeof(struct fsl_usb2_platform_data)); ++ if (rc) { ++ platform_device_unregister(pdev); ++ return NULL; ++ } ++ ++ printk(KERN_INFO "usb: %s host (%s) registered\n", config->name, ++ config->transceiver); ++ pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", ++ pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); ++ ++ instance_id++; ++ ++ return pdev; ++} ++ ++int usb_platform_host_init(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ struct fsl_xcvr_ops *xops; ++ ++ xops = fsl_usb_get_xcvr(pdata->transceiver); ++ if (!xops) { ++ printk(KERN_ERR "DR transceiver ops missing\n"); ++ return -EINVAL; ++ } ++ pdata->xcvr_ops = xops; ++ pdata->xcvr_type = xops->xcvr_type; ++ pdata->pdev = pdev; ++ xops->pdata = pdata; ++ ++ if (pdata->gpio_usb_active) ++ if (pdata->gpio_usb_active()) ++ return -EINVAL; ++ ++ /* enable USB read, write and slave bursts */ ++ MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL; ++ fsl_usb_enable_clk(); ++ ++ if (xops->init) ++ xops->init(xops); ++ ++ return 0; ++} ++ ++void usb_platform_host_uninit(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ ++ if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) ++ pdata->xcvr_ops->uninit(pdata->xcvr_ops); ++ ++ pdata->regs = NULL; ++ ++ if (pdata->gpio_usb_inactive) ++ pdata->gpio_usb_inactive(); ++ ++ fsl_usb_disable_clk(); ++} ++ ++ ++static int dr_used; ++ ++int usb_platform_dr_init(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ struct fsl_xcvr_ops *xops; ++ ++ pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); ++ ++ xops = fsl_usb_get_xcvr(pdata->transceiver); ++ if (!xops) { ++ printk(KERN_ERR "DR transceiver ops missing\n"); ++ return -EINVAL; ++ } ++ pdata->xcvr_ops = xops; ++ pdata->xcvr_type = xops->xcvr_type; ++ pdata->pdev = pdev; ++ xops->pdata = pdata; ++ ++ /* enable USB read, write and slave bursts */ ++ MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL; ++ ++ if (!dr_used) { ++ fsl_usb_enable_clk(); ++ ++ if (xops->init) ++ xops->init(xops); ++ } ++ ++ dr_used++; ++ pr_debug("%s: success\n", __func__); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(usb_platform_dr_init); ++ ++void usb_platform_dr_uninit(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ pr_debug("%s\n", __func__); ++ ++ dr_used--; ++ if (!dr_used) { ++ if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) ++ pdata->xcvr_ops->uninit(pdata->xcvr_ops); ++ ++ pdata->regs = NULL; ++ fsl_usb_disable_clk(); ++ } ++} ++EXPORT_SYMBOL_GPL(usb_platform_dr_uninit); +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/usb.h +@@ -0,0 +1,76 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++ ++/* ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++extern int usb_platform_host_init(struct platform_device *pdev); ++extern void usb_platform_host_uninit(struct fsl_usb2_platform_data *pdata); ++extern int usb_platform_dr_init(struct platform_device *pdev); ++extern void usb_platform_dr_uninit(struct fsl_usb2_platform_data *pdata); ++extern struct platform_device *host_pdev_register(struct resource *res, ++ int n_res, struct fsl_usb2_platform_data *config); ++ ++ ++#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_EHCI_HCD_MODULE ++static inline void dr_register_host(struct resource *r, int rs) ++{ ++ PDATA->operating_mode = DR_HOST_MODE; ++ host_pdev_register(r, rs, PDATA); ++} ++#else ++static inline void dr_register_host(struct resource *r, int rs) ++{ ++} ++#endif ++ ++#ifdef CONFIG_USB_GADGET_FSL_USB2 ++static struct platform_device dr_udc_device; ++ ++static inline void dr_register_udc(void) ++{ ++ PDATA->operating_mode = DR_UDC_MODE; ++ dr_udc_device.dev.platform_data = PDATA; ++ ++ if (platform_device_register(&dr_udc_device)) ++ printk(KERN_ERR "usb: can't register DR gadget\n"); ++ else ++ printk(KERN_INFO "usb: DR gadget (%s) registered\n", ++ PDATA->transceiver); ++} ++#else ++static inline void dr_register_udc(void) ++{ ++} ++#endif ++ ++#ifdef CONFIG_USB_OTG ++static struct platform_device dr_otg_device; ++ ++/* ++ * set the proper operating_mode and ++ * platform_data pointer, then register the ++ * device. ++ */ ++static inline void dr_register_otg(void) ++{ ++ PDATA->operating_mode = FSL_USB2_DR_OTG; ++ dr_otg_device.dev.platform_data = PDATA; ++ ++ if (platform_device_register(&dr_otg_device)) ++ printk(KERN_ERR "usb: can't register otg device\n"); ++ else ++ printk(KERN_INFO "usb: DR OTG registered\n"); ++} ++#else ++static inline void dr_register_otg(void) ++{ ++} ++#endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/usb_dr.c +@@ -0,0 +1,179 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <asm/mcfsim.h> ++ ++#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000) ++#define INT_USB (64 + 64 + 64 + 17) /* INTC1:17 17.2.9.1*/ ++#define INT_UOCSR (64 + 64 + 64 + 27) /* INTC1:27 17.2.9.1 */ ++ ++/* ++ * Determine which platform_data struct to use, based on which ++ * transceiver is configured. ++ * PDATA is a pointer to it. ++ */ ++#ifdef CONFIG_USB_M5441X_ULPI ++static struct fsl_usb2_platform_data dr_config_ulpi; ++#define PDATA (&dr_config_ulpi) ++#else ++static struct fsl_usb2_platform_data dr_config_fsls; ++#define PDATA (&dr_config_fsls) ++#endif ++ ++/* ++ * Used to set pdata->operating_mode before registering the platform_device. ++ * If OTG is configured, the controller operates in OTG mode, ++ * otherwise it's either host or device. ++ */ ++#ifdef CONFIG_USB_OTG ++#define DR_UDC_MODE FSL_USB2_DR_OTG ++#define DR_HOST_MODE FSL_USB2_DR_OTG ++#else ++#define DR_UDC_MODE FSL_USB2_DR_DEVICE ++#define DR_HOST_MODE FSL_USB2_DR_HOST ++#endif ++ ++#include "usb.h" ++ ++/* ++ * platform data structs ++ * - Which one to use is determined by CONFIG options in usb.h ++ * - operating_mode plugged at run time ++ */ ++ ++/* off-chip ULPI transceiver */ ++static struct fsl_usb2_platform_data __maybe_unused dr_config_ulpi = { ++ .name = "DR", ++ .init = usb_platform_dr_init, ++ .exit = usb_platform_dr_uninit, ++ .phy_mode = FSL_USB2_PHY_ULPI, ++ .transceiver = "dr-ulpi", ++ .power_budget = 500, ++ .es = 1, ++ .big_endian_mmio = 1, ++ .big_endian_desc = 1, ++ .le_setup_buf = 1, ++}; ++ ++/* on-chip FS/LS serial transceiver */ ++static struct fsl_usb2_platform_data __maybe_unused dr_config_fsls = { ++ .name = "DR", ++ .init = usb_platform_dr_init, ++ .exit = usb_platform_dr_uninit, ++ .phy_mode = FSL_USB2_PHY_SERIAL, ++#ifdef CONFIG_USB_M5441X_MAX3353_FSLS ++ .transceiver = "dr-max3353", ++#else ++ .transceiver = "dr-fsls", ++#endif ++ .power_budget = 500, ++ .es = 1, ++ .big_endian_mmio = 1, ++ .big_endian_desc = 1, ++ .le_setup_buf = 1, ++}; ++ ++/* ++ * resources ++ */ ++static struct resource dr_udc_resources[] = { ++ [0] = { ++ .start = (u32)(&USB_OTGREGS_BASE), ++ .end = (u32)(&USB_OTGREGS_BASE + 0x1ff), ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource dr_otg_resources[] = { ++ [0] = { ++ .start = (u32)(&USB_OTGREGS_BASE), ++ .end = (u32)(&USB_OTGREGS_BASE + 0x1ff), ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource dr_host_resources[] = { ++ [0] = { ++ .start = (u32)(&USB_OTGREGS_BASE), ++ .end = (u32)(&USB_OTGREGS_BASE + 0x1ff), ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 dr_udc_dmamask = ~(u32) 0; ++static void dr_udc_release(struct device *dev) ++{ ++} ++ ++static u64 dr_otg_dmamask = ~(u32) 0; ++static void dr_otg_release(struct device *dev) ++{ ++} ++ ++/* ++ * platform device structs ++ * dev.platform_data field plugged at run time ++ */ ++static struct platform_device __maybe_unused dr_udc_device = { ++ .name = "fsl-usb2-udc", ++ .id = -1, ++ .dev = { ++ .release = dr_udc_release, ++ .dma_mask = &dr_udc_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .resource = dr_udc_resources, ++ .num_resources = ARRAY_SIZE(dr_udc_resources), ++}; ++ ++static struct platform_device __maybe_unused dr_otg_device = { ++#ifdef CONFIG_USB_M5441X_MAX3353_FSLS ++ .name = "max3353-otg", ++#else ++ .name = "fsl-usb2-otg", ++#endif ++ .id = -1, ++ .dev = { ++ .release = dr_otg_release, ++ .dma_mask = &dr_otg_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .resource = dr_otg_resources, ++ .num_resources = ARRAY_SIZE(dr_otg_resources), ++}; ++ ++static int __init usb_dr_init(void) ++{ ++ pr_debug("%s:\n", __func__); ++ ++ dr_register_otg(); ++ dr_register_host(dr_host_resources, ARRAY_SIZE(dr_host_resources)); ++ dr_register_udc(); ++ ++ return 0; ++} ++ ++module_init(usb_dr_init); +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/usb_host.c +@@ -0,0 +1,115 @@ ++/* ++ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <asm/mcfsim.h> ++ ++#define USB_H1REGS_BASE (0xFC0B4000) ++#define INT_USB_HOST (64 + 64 + 64 + 18) /* INTC1:18*/ ++ ++ ++/* ++ * Define Host module platform_data struct to use, based on which ++ * transceiver is configured. ++ * PDATA is a pointer to it. ++ */ ++#if defined(CONFIG_USB_M5441X_H1_FSLS) ++static struct fsl_usb2_platform_data h1_config_fsls; ++#define PDATA (&h1_config_fsls) ++#else ++#warning "Unknow ColdFire USB Host module transceiver!" ++#endif ++/* ++ * Used to set pdata->operating_mode before registering the platform_device. ++ */ ++#define DR_UDC_MODE FSL_USB2_DR_DEVICE ++#define DR_HOST_MODE FSL_USB2_DR_HOST ++ ++#include "usb.h" ++ ++static int h1_gpio_active(void) ++{ ++ /* Configure USB_DP_PDOWN/USB_DM_PDOWN (external resistor) */ ++ MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT0; ++ MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT1; ++ MCF_GPIO_PDDR_I |= 0xc0; ++ MCF_GPIO_PODR_I &= 0x3f; ++ ++ MCF_GPIO_PAR_CS &= 0x0F; /*Enable GPIOB5, GPIOB6*/ ++ ++ MCF_GPIO_PDDR_B &= 0xDF; /*GPIOB5, input, USB_OC*/ ++ MCF_GPIO_PCR_B |= 0x0C00; /*pull up*/ ++ ++ MCF_GPIO_PDDR_B |= 0x40; /*GPIOB6, output*/ ++ MCF_GPIO_PODR_B |= 0x40; /*GPIOB6, output 1, VBUS enable*/ ++ MCF_GPIO_PCR_B &= ~0x3000; /*pull disable*/ ++ ++ return 0; ++} ++ ++static void h1_gpio_inactive(void) ++{ ++ MCF_GPIO_PODR_B &= 0xBF; /*GPIOB6, output 0*/ ++} ++ ++ ++/* ++ * platform data struct ++ * - operating_mode plugged at run time ++ */ ++ ++/* on-chip FS/LS serial transceiver */ ++static struct fsl_usb2_platform_data usbh1_config = { ++ .name = "Host1", ++ .init = usb_platform_host_init, ++ .exit = usb_platform_host_uninit, ++ .operating_mode = FSL_USB2_MPH_HOST, ++ .power_budget = 500, /* MIC2076: 500 mA max power */ ++ .phy_mode = FSL_USB2_PHY_SERIAL, /* FS/LS on-chip xcvr */ ++ .transceiver = "h1-fsls", ++ .gpio_usb_active = h1_gpio_active, ++ .gpio_usb_inactive = h1_gpio_inactive, ++ .es = 1, ++ .big_endian_mmio = 1, ++ .big_endian_desc = 1, ++}; ++ ++/* ++ * resources ++ */ ++static struct resource h1_resources[] = { ++ [0] = { ++ .start = USB_H1REGS_BASE, ++ .end = USB_H1REGS_BASE + 0x1ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB_HOST, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static int __init usbh1_init(void) ++{ ++ host_pdev_register(h1_resources, ARRAY_SIZE(h1_resources), ++ &usbh1_config); ++ return 0; ++} ++module_init(usbh1_init); +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/xcvr.c +@@ -0,0 +1,198 @@ ++/* ++ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/delay.h> ++#include <linux/usb/fsl_xcvr.h> ++#include <asm/mcfsim.h> ++ ++/* Use the configured xcvr_ops */ ++#ifdef CONFIG_USB_M5441X_ULPI ++#define XCVR_OPS (&xcvr_ops_ulpi) ++#elif defined CONFIG_USB_M5441X_FSLS ++#define XCVR_OPS (&xcvr_ops_fsls) ++#else ++#error "Invalid USB transceiver selection." ++#endif ++ ++#define MCF_FEC_ENET0_RCR MCF_REG32(0xFC0D4084) ++ ++/* ++ * Init routine for on-chip FSLS xcvr ++ */ ++static void xcvr_fsls_init(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s: name=%s\n", __func__, this->name); ++ ++ /* Configure USB_DP_PDOWN/USB_DM_PDOWN (external resistor) */ ++ MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT0; ++ MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT1; ++ MCF_GPIO_PDDR_I |= 0xc0; ++ MCF_GPIO_PODR_I &= 0x3f; ++ ++ ++ MCF_GPIO_PAR_CS &= 0x0F; /*Enable GPIOB5, GPIOB6*/ ++ ++ MCF_GPIO_PDDR_B &= 0xDF; /*GPIOB5, input*/ ++ MCF_GPIO_PDDR_B |= 0x40; /*GPIOB6, output*/ ++ ++ MCF_GPIO_PODR_B |= 0x40; /*GPIOB6, output 1*/ ++#if 0 ++ /* Enable VBUS_EN and VBUS_OC signals */ ++ MCF_GPIO_PAR_TIMER = ++ (MCF_GPIO_PAR_TIMER & ++ MCF_GPIO_PAR_TIMER_T3IN_MASK) | ++ MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN; ++ ++ MCF_GPIO_PAR_TIMER = ++ (MCF_GPIO_PAR_TIMER & ++ MCF_GPIO_PAR_TIMER_T0IN_MASK) | ++ MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC; ++ ++ /* Setup USB_VBUS_OC signal to be active-low */ ++ MCF_CCM_MISCCR &= (~MCF_CCM_MISCCR_USBOOC); ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBPUE; ++#endif ++ ++} ++ ++/* ++ * Init routine for off-chip ULPI xcvr ++ */ ++static void xcvr_ulpi_init(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s: name=%s\n", __func__, this->name); ++ ++ /* disable FEC2 clock */ ++ MCF_PM_PPMSR0 = 54; ++ ++ /* enable USB OTG clock*/ ++ MCF_PM_PPMCR0 = 44; ++ ++ /* Chip select for ULPI: GPIO G4 as CS between ULPI and RMII1*/ ++ MCF_GPIO_PAR_SIMP0H = ++ (MCF_GPIO_PAR_SIMP0H & ++ MCF_GPIO_PAR_SIMP0H_DAT_MASK) | ++ MCF_GPIO_PAR_SIMP0H_DAT_GPIO; ++ ++ MCF_GPIO_PDDR_G = ++ (MCF_GPIO_PDDR_G & ++ MCF_GPIO_PDDR_G4_MASK) | ++ MCF_GPIO_PDDR_G4_OUTPUT; ++ ++ MCF_GPIO_PODR_G = ++ (MCF_GPIO_PODR_G & ++ MCF_GPIO_PODR_G4_MASK) | ++ MCF_GPIO_PODR_G4_VAL; ++ ++ /* Enable ULPI */ ++ MCF_CCM_MISCCR2 = MCF_CCM_MISCCR2 & (~MCF_CCM_MISCCR2_ULPI); ++ ++ /* Slew rate setting for OTG */ ++ MCF_GPIO_SRCR_FEC = 0x0f; ++ MCF_GPIO_SRCR_TIMER = 0xc3; ++ MCF_GPIO_SRCR_IRQ0 = 0x03; ++ ++ /* Enable the required ULPI signals */ ++ MCF_GPIO_PAR_TIMER = ++ (MCF_GPIO_PAR_TIMER & ++ MCF_GPIO_PAR_TIMER_T3IN_MASK) | ++ MCF_GPIO_PAR_TIMER_T3IN_ULPI_DIR; ++ ++ MCF_GPIO_PAR_TIMER = ++ (MCF_GPIO_PAR_TIMER & ++ MCF_GPIO_PAR_TIMER_T0IN_MASK) | ++ MCF_GPIO_PAR_TIMER_T0IN_ULPI_NXT; ++ ++ MCF_FEC_ENET0_RCR = 0x104; /* FEC0 as RMII mode */ ++ ++ MCF_GPIO_PAR_FEC = ++ (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC_MASK) | ++ MCF_GPIO_PAR_FEC_FEC_RMII0FUL_ULPI; ++ ++ ++ pr_debug("MCF_GPIO_PAR_TIMER:0x%x, MCF_GPIO_PAR_FEC:0x%x," ++ "MCF_GPIO_PAR_SIMP0H:0x%x, MCF_GPIO_PDDR_G:0x%x," ++ "MCF_GPIO_PODR_G:0x%x, MCF_CCM_MISCCR2:0x%x\n\n", ++ MCF_GPIO_PAR_TIMER, MCF_GPIO_PAR_FEC, ++ MCF_GPIO_PAR_SIMP0H, MCF_GPIO_PDDR_G, ++ MCF_GPIO_PODR_G, MCF_CCM_MISCCR2); ++ ++ pr_debug("OTGSC:0x%lx, PORTSC:0x%lx, USBMODE:0x%lx, " ++ "USBCMD:0x%lx, USBSTS:0x%lx, USBINTR:0x%lx, " ++ "MCF_CCM_UOCSR:0x%x\n\n", ++ MCF_REG32(0xfc0b01a4), MCF_REG32(0xfc0b0184), ++ MCF_REG32(0xfc0b01a8), MCF_REG32(0xfc0b0140), ++ MCF_REG32(0xfc0b0144), MCF_REG32(0xfc0b0148), ++ MCF_CCM_UOCSR); ++} ++ ++static void xcvr_uninit(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s\n", __func__); ++} ++ ++static void xcvr_pullup(int on) ++{ ++ unsigned short ccm = in_be16(&MCF_CCM_UOCSR); ++ ++ pr_debug("%s(%d)\n", __func__, on); ++ ++ ccm = in_be16(&MCF_CCM_UOCSR); ++ if (on) { ++ ccm |= MCF_CCM_UOCSR_BVLD; ++ ccm &= ~MCF_CCM_UOCSR_SEND; ++ out_be16(&MCF_CCM_UOCSR, ccm); ++ } else { ++ ccm &= ~MCF_CCM_UOCSR_BVLD; ++ out_be16(&MCF_CCM_UOCSR, ccm); ++ } ++} ++ ++struct fsl_xcvr_ops xcvr_ops_ulpi = { ++ .init = xcvr_ulpi_init, ++ .uninit = xcvr_uninit, ++ .pullup = xcvr_pullup, ++ .name = "dr-ulpi", ++}; ++ ++struct fsl_xcvr_ops xcvr_ops_fsls = { ++ .init = xcvr_fsls_init, ++ .uninit = xcvr_uninit, ++ .pullup = xcvr_pullup, ++ .name = "dr-fsls", ++}; ++ ++static int __init usb_xcvr_init(void) ++{ ++ struct fsl_xcvr_ops *xops = XCVR_OPS; ++ ++ pr_debug("%s %s\n", __func__, xops->name); ++ fsl_usb_xcvr_register(xops); ++ ++ return 0; ++} ++ ++static void __exit usb_xcvr_exit(void) ++{ ++ fsl_usb_xcvr_unregister(XCVR_OPS); ++} ++ ++module_init(usb_xcvr_init); ++module_exit(usb_xcvr_exit); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("External ULPI xcvr driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/m68k/coldfire/m5441x/xcvr_host.c +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/usb/fsl_xcvr.h> ++#include <asm/mcfsim.h> ++ ++/* ++ * xcvr_ops for the on-chip xcvr on the DR controller ++ * No ops needed. ++ */ ++struct fsl_xcvr_ops xcvr_ops_h1_fsls = { ++ .name = "h1-fsls", ++}; ++ ++ ++static int __init usb_xcvr_host_init(void) ++{ ++ fsl_usb_xcvr_register(&xcvr_ops_h1_fsls); ++ ++ return 0; ++} ++ ++static void __exit usb_xcvr_host_exit(void) ++{ ++ fsl_usb_xcvr_unregister(&xcvr_ops_h1_fsls); ++} ++ ++module_init(usb_xcvr_host_init); ++module_exit(usb_xcvr_host_exit); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("On-chip FS/LS xcvr host driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/usb.c +@@ -0,0 +1,220 @@ ++/* ++ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/err.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <linux/usb/fsl_xcvr.h> ++#include <asm/mcfsim.h> ++ ++#define MCF_SCM_BCR MCF_REG32(0xFC040024) ++#define MCF_SCM_BCR_GBR (1 << 9) /* global bursts for read */ ++#define MCF_SCM_BCR_GBW (1 << 8) /* global bursts for write */ ++#define MCF_SCM_BCR_SBE_ALL (0xff << 0) /* slave burst enable */ ++ ++#define MAX_XCVR 3 ++struct fsl_xcvr_ops *g_xc_ops[MAX_XCVR] = { NULL }; ++ ++#ifdef ULPI_DEBUG ++void print_ulpi_regs(void) ++{ ++ pr_debug("MCF_SCM_BCR=0x%08lx MCF_CCM_MISCCR=0x%08x " ++ "MCF_GPIO_PAR_DMA=0x%08x MCF_GPIO_PAR_USB=08%08x " ++ "MCF_GPIO_PAR_FEC=08%08x\n", ++ MCF_SCM_BCR, MCF_CCM_MISCCR, MCF_GPIO_PAR_DMA, ++ MCF_GPIO_PAR_USB, MCF_GPIO_PAR_FEC); ++} ++EXPORT_SYMBOL(print_ulpi_regs); ++#endif ++ ++static inline void fsl_usb_enable_clk(void) ++{ ++ pr_debug("%s\n", __func__); ++ ++ /* Use external clock source if PLL isn't a multiple of 60MHz */ ++ MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC; ++ ++ /* Initialize the USB Clock: use USB input clock */ ++ MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & MCF_GPIO_PAR_DMA_DREQ1_MASK) | ++ MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN; ++} ++ ++static inline void fsl_usb_disable_clk(void) ++{ ++ pr_debug("%s\n", __func__); ++} ++ ++void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) ++{ ++ int i; ++ ++ pr_debug("%s '%s'\n", __func__, xcvr_ops->name); ++ for (i = 0; i < MAX_XCVR; i++) { ++ if (g_xc_ops[i] == NULL) { ++ g_xc_ops[i] = xcvr_ops; ++ return; ++ } ++ } ++ ++ pr_debug("%s failed\n", __func__); ++} ++EXPORT_SYMBOL_GPL(fsl_usb_xcvr_register); ++ ++void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops) ++{ ++ int i; ++ ++ pr_debug("%s '%s'\n", __func__, xcvr_ops->name); ++ for (i = 0; i < MAX_XCVR; i++) { ++ if (g_xc_ops[i] == xcvr_ops) { ++ g_xc_ops[i] = NULL; ++ return; ++ } ++ } ++ ++ pr_debug("%s failed\n", __func__); ++} ++EXPORT_SYMBOL_GPL(fsl_usb_xcvr_unregister); ++ ++static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name) ++{ ++ int i; ++ ++ pr_debug("%s '%s'\n", __func__, name); ++ if (name == NULL) { ++ printk(KERN_ERR "get_xcvr(): No tranceiver name\n"); ++ return NULL; ++ } ++ ++ for (i = 0; i < MAX_XCVR; i++) { ++ if (strcmp(g_xc_ops[i]->name, name) == 0) ++ return g_xc_ops[i]; ++ } ++ pr_debug("Failed %s\n", __func__); ++ return NULL; ++} ++ ++/* The dmamask must be set for EHCI to work */ ++static u64 ehci_dmamask = ~(u32) 0; ++ ++/*! ++ * Register an instance of a USB host platform device. ++ * ++ * @param res: resource pointer ++ * @param n_res: number of resources ++ * @param config: config pointer ++ * ++ * @return newly-registered platform_device ++ * ++ * Each supported host interface is registered as an instance ++ * of the "fsl-ehci" device. Call this function multiple times ++ * to register each host interface. ++ */ ++static int instance_id; ++struct platform_device *host_pdev_register(struct resource *res, int n_res, ++ struct fsl_usb2_platform_data *config) ++{ ++ struct platform_device *pdev; ++ int rc; ++ ++ pr_debug("register host res=0x%p, size=%d\n", res, n_res); ++ ++ pdev = platform_device_register_simple("fsl-ehci", ++ instance_id, res, n_res); ++ if (IS_ERR(pdev)) { ++ printk(KERN_ERR "usb: can't register %s Host, %ld\n", ++ config->name, PTR_ERR(pdev)); ++ return NULL; ++ } ++ ++ pdev->dev.coherent_dma_mask = 0xffffffff; ++ pdev->dev.dma_mask = &ehci_dmamask; ++ ++ rc = platform_device_add_data(pdev, config, ++ sizeof(struct fsl_usb2_platform_data)); ++ if (rc) { ++ platform_device_unregister(pdev); ++ return NULL; ++ } ++ ++ printk(KERN_INFO "usb: %s host (%s) registered\n", config->name, ++ config->transceiver); ++ pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", ++ pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); ++ ++ instance_id++; ++ ++ return pdev; ++} ++ ++ ++static int dr_used; ++ ++int usb_platform_dr_init(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ struct fsl_xcvr_ops *xops; ++ ++ pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); ++ ++ xops = fsl_usb_get_xcvr(pdata->transceiver); ++ if (!xops) { ++ printk(KERN_ERR "DR transceiver ops missing\n"); ++ return -EINVAL; ++ } ++ pdata->xcvr_ops = xops; ++ pdata->xcvr_type = xops->xcvr_type; ++ pdata->pdev = pdev; ++ xops->pdata = pdata; ++ ++ /* enable USB read, write and slave bursts */ ++ MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL; ++ ++ if (!dr_used) { ++ fsl_usb_enable_clk(); ++ ++ if (xops->init) ++ xops->init(xops); ++ } ++ ++ dr_used++; ++ pr_debug("%s: success\n", __func__); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(usb_platform_dr_init); ++ ++void usb_platform_dr_uninit(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ ++ pr_debug("%s\n", __func__); ++ ++ dr_used--; ++ if (!dr_used) { ++ if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) ++ pdata->xcvr_ops->uninit(pdata->xcvr_ops); ++ ++ pdata->regs = NULL; ++ fsl_usb_disable_clk(); ++ } ++} ++EXPORT_SYMBOL_GPL(usb_platform_dr_uninit); +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/usb.h +@@ -0,0 +1,107 @@ ++/* ++ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++ ++extern int usb_platform_dr_init(struct platform_device *pdev); ++extern void usb_platform_dr_uninit(struct fsl_usb2_platform_data *pdata); ++extern struct platform_device *host_pdev_register(struct resource *res, ++ int n_res, struct fsl_usb2_platform_data *config); ++ ++ ++/* ++ * Determine which platform_data struct to use, based on which ++ * transceiver is configured. ++ * PDATA is a pointer to it. ++ */ ++#ifdef CONFIG_USB_M5445X_ULPI ++static struct fsl_usb2_platform_data dr_config_ulpi; ++#define PDATA (&dr_config_ulpi) ++#else ++static struct fsl_usb2_platform_data dr_config_fsls; ++#define PDATA (&dr_config_fsls) ++#endif ++ ++/* ++ * Used to set pdata->operating_mode before registering the platform_device. ++ * If OTG is configured, the controller operates in OTG mode, ++ * otherwise it's either host or device. ++ */ ++#ifdef CONFIG_USB_OTG ++#define DR_UDC_MODE FSL_USB2_DR_OTG ++#define DR_HOST_MODE FSL_USB2_DR_OTG ++#else ++#define DR_UDC_MODE FSL_USB2_DR_DEVICE ++#define DR_HOST_MODE FSL_USB2_DR_HOST ++#endif ++ ++ ++#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_EHCI_HCD_MODULE ++static inline void dr_register_host(struct resource *r, int rs) ++{ ++ PDATA->operating_mode = DR_HOST_MODE; ++ host_pdev_register(r, rs, PDATA); ++} ++#else ++static inline void dr_register_host(struct resource *r, int rs) ++{ ++} ++#endif ++ ++#ifdef CONFIG_USB_GADGET_FSL_USB2 ++static struct platform_device dr_udc_device; ++ ++static inline void dr_register_udc(void) ++{ ++ PDATA->operating_mode = DR_UDC_MODE; ++ dr_udc_device.dev.platform_data = PDATA; ++ ++ if (platform_device_register(&dr_udc_device)) ++ printk(KERN_ERR "usb: can't register DR gadget\n"); ++ else ++ printk(KERN_INFO "usb: DR gadget (%s) registered\n", ++ PDATA->transceiver); ++} ++#else ++static inline void dr_register_udc(void) ++{ ++} ++#endif ++ ++#ifdef CONFIG_USB_OTG ++static struct platform_device dr_otg_device; ++ ++/* ++ * set the proper operating_mode and ++ * platform_data pointer, then register the ++ * device. ++ */ ++static inline void dr_register_otg(void) ++{ ++ PDATA->operating_mode = FSL_USB2_DR_OTG; ++ dr_otg_device.dev.platform_data = PDATA; ++ ++ if (platform_device_register(&dr_otg_device)) ++ printk(KERN_ERR "usb: can't register otg device\n"); ++ else ++ printk(KERN_INFO "usb: DR OTG registered\n"); ++} ++#else ++static inline void dr_register_otg(void) ++{ ++} ++#endif +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/usb_dr.c +@@ -0,0 +1,152 @@ ++/* ++ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/platform_device.h> ++#include <linux/fsl_devices.h> ++#include <asm/mcfsim.h> ++ ++#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000) ++#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */ ++#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */ ++ ++#include "usb.h" ++ ++/* ++ * platform data structs ++ * - Which one to use is determined by CONFIG options in usb.h ++ * - operating_mode plugged at run time ++ */ ++ ++/* off-chip ULPI transceiver */ ++static struct fsl_usb2_platform_data __maybe_unused dr_config_ulpi = { ++ .name = "DR", ++ .init = usb_platform_dr_init, ++ .exit = usb_platform_dr_uninit, ++ .phy_mode = FSL_USB2_PHY_ULPI, ++ .transceiver = "dr-ulpi", ++ .power_budget = 500, ++ .es = 1, ++ .big_endian_mmio = 1, ++ .big_endian_desc = 1, ++ .le_setup_buf = 1, ++}; ++ ++/* on-chip FS/LS serial transceiver */ ++static struct fsl_usb2_platform_data __maybe_unused dr_config_fsls = { ++ .name = "DR", ++ .init = usb_platform_dr_init, ++ .exit = usb_platform_dr_uninit, ++ .phy_mode = FSL_USB2_PHY_SERIAL, ++ .transceiver = "dr-fsls", ++ .power_budget = 500, ++ .es = 1, ++ .big_endian_mmio = 1, ++ .big_endian_desc = 1, ++ .le_setup_buf = 1, ++}; ++ ++/* ++ * resources ++ */ ++static struct resource dr_host_resources[] = { ++ [0] = { ++ .start = (u32)(&USB_OTGREGS_BASE), ++ .end = (u32)(&USB_OTGREGS_BASE + 0x1ff), ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource dr_otg_resources[] = { ++ [0] = { ++ .start = (u32)(&USB_OTGREGS_BASE), ++ .end = (u32)(&USB_OTGREGS_BASE + 0x1ff), ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource dr_udc_resources[] = { ++ [0] = { ++ .start = (u32)(&USB_OTGREGS_BASE), ++ .end = (u32)(&USB_OTGREGS_BASE + 0x1ff), ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++static u64 dr_udc_dmamask = ~(u32) 0; ++static void dr_udc_release(struct device *dev) ++{ ++} ++ ++static u64 dr_otg_dmamask = ~(u32) 0; ++static void dr_otg_release(struct device *dev) ++{ ++} ++ ++/* ++ * platform device structs ++ * dev.platform_data field plugged at run time ++ */ ++static struct platform_device __maybe_unused dr_udc_device = { ++ .name = "fsl-usb2-udc", ++ .id = -1, ++ .dev = { ++ .release = dr_udc_release, ++ .dma_mask = &dr_udc_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .resource = dr_udc_resources, ++ .num_resources = ARRAY_SIZE(dr_udc_resources), ++}; ++ ++static struct platform_device __maybe_unused dr_otg_device = { ++ .name = "fsl-usb2-otg", ++ .id = -1, ++ .dev = { ++ .release = dr_otg_release, ++ .dma_mask = &dr_otg_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .resource = dr_otg_resources, ++ .num_resources = ARRAY_SIZE(dr_otg_resources), ++}; ++ ++static int __init usb_dr_init(void) ++{ ++ pr_debug("%s:\n", __func__); ++ ++ dr_register_otg(); ++ dr_register_host(dr_host_resources, ARRAY_SIZE(dr_host_resources)); ++ dr_register_udc(); ++ ++ return 0; ++} ++ ++module_init(usb_dr_init); +--- /dev/null ++++ b/arch/m68k/coldfire/m5445x/xcvr.c +@@ -0,0 +1,127 @@ ++/* ++ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/usb/fsl_xcvr.h> ++#include <asm/mcfsim.h> ++ ++/* Use the configured xcvr_ops */ ++#ifdef CONFIG_USB_M5445X_ULPI ++#define XCVR_OPS (&xcvr_ops_ulpi) ++#elif defined CONFIG_USB_M5445X_FSLS ++#define XCVR_OPS (&xcvr_ops_fsls) ++#else ++#error "Invalid USB transceiver selection." ++#endif ++ ++/* ++ * Init routine for on-chip FSLS xcvr ++ */ ++static void xcvr_fsls_init(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s: name=%s\n", __func__, this->name); ++ ++ /* Enable VBUS_EN and VBUS_OC signals */ ++ MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_VBUSEN | ++ MCF_GPIO_PAR_USB_VBUSOC_VBUSOC; ++ ++ /* Setup USB_VBUS_OC signal to be active-low */ ++ MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBOC; ++} ++ ++/* ++ * Init routine for off-chip ULPI xcvr ++ */ ++static void xcvr_ulpi_init(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s: name=%s\n", __func__, this->name); ++ ++ /* Enable the required ULPI signals */ ++ MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & ++ MCF_GPIO_PAR_DMA_DACK1_MASK) | ++ MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR; ++ ++ MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT | ++ MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP; ++ ++ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & ++ MCF_GPIO_PAR_FEC_FEC0_MASK) | ++ MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI; ++} ++ ++static void xcvr_uninit(struct fsl_xcvr_ops *this) ++{ ++ pr_debug("%s\n", __func__); ++} ++ ++static void xcvr_pullup(int on) ++{ ++ unsigned short ccm = in_be16(&MCF_CCM_UOCSR); ++ ++ pr_debug("%s(%d)\n", __func__, on); ++ ++ ccm = in_be16(&MCF_CCM_UOCSR); ++ if (on) { ++ ccm |= MCF_CCM_UOCSR_BVLD; ++ ccm &= ~MCF_CCM_UOCSR_SEND; ++ out_be16(&MCF_CCM_UOCSR, ccm); ++ } else { ++ ccm &= ~MCF_CCM_UOCSR_BVLD; ++ out_be16(&MCF_CCM_UOCSR, ccm); ++ } ++} ++ ++struct fsl_xcvr_ops xcvr_ops_ulpi = { ++ .init = xcvr_ulpi_init, ++ .uninit = xcvr_uninit, ++ .pullup = xcvr_pullup, ++ .name = "dr-ulpi", ++}; ++ ++struct fsl_xcvr_ops xcvr_ops_fsls = { ++ .init = xcvr_fsls_init, ++ .uninit = xcvr_uninit, ++ .pullup = xcvr_pullup, ++ .name = "dr-fsls", ++}; ++ ++static int __init usb_xcvr_init(void) ++{ ++ struct fsl_xcvr_ops *xops = XCVR_OPS; ++ ++ pr_debug("%s %s\n", __func__, xops->name); ++ fsl_usb_xcvr_register(xops); ++ ++ return 0; ++} ++ ++static void __exit usb_xcvr_exit(void) ++{ ++ fsl_usb_xcvr_unregister(XCVR_OPS); ++} ++ ++module_init(usb_xcvr_init); ++module_exit(usb_xcvr_exit); ++ ++MODULE_AUTHOR("Freescale Semiconductor, Inc."); ++MODULE_DESCRIPTION("External ULPI xcvr driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/m68k/include/asm/fsl_usb_gadget.h +@@ -0,0 +1,45 @@ ++/* ++ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/* ++ * USB Gadget side, platform-specific functionality. ++ */ ++ ++#include <linux/usb/fsl_xcvr.h> ++ ++/* Needed for i2c/serial transceivers */ ++static inline void ++fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata) ++{ ++ if (pdata->xcvr_ops && pdata->xcvr_ops->set_device) ++ pdata->xcvr_ops->set_device(); ++} ++ ++static inline void ++fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata) ++{ ++ if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) ++ pdata->xcvr_ops->pullup(1); ++} ++ ++static inline void ++fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata) ++{ ++ if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) ++ pdata->xcvr_ops->pullup(0); ++} +--- /dev/null ++++ b/arch/m68k/include/asm/fsl_usb_io.h +@@ -0,0 +1,43 @@ ++/* Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++#ifndef _FSL_USB_IO_H ++#define _FSL_USB_IO_H ++ ++#undef inb_p ++#undef outb_p ++#undef inl_p ++#undef outl_p ++#define inb_p in_8 ++#define outb_p(b, addr) (void)((*(__force volatile u8 *) (addr)) = (b)) ++#define inl_p in_be32 ++#define outl_p(l, addr) (void)((*(__force volatile u32 *) (addr)) = (l)) ++ ++#define fsl_readl(addr) in_be32((__force unsigned *)(addr)) ++#define fsl_writel(val32, addr) out_be32((__force unsigned *)(addr), (val32)) ++ ++static inline void fsl_set_usb_accessors(struct fsl_usb2_platform_data *pdata) ++{ ++} ++/* ++#ifndef cpu_to_hc32 ++#define cpu_to_hc32(x) (x) ++#endif ++#ifndef hc32_to_cpu ++#define hc32_to_cpu(x) (x) ++#endif ++*/ ++#endif /* _FSL_USB_IO_H */ +--- /dev/null ++++ b/arch/m68k/include/asm/fsl_usb_platform.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++ ++/* ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#ifndef FSL_USB_PLATFORM_H ++#define FSL_USB_PLATFORM_H ++ ++#include <linux/usb/fsl_xcvr.h> ++#include <linux/usb/fsl_usb2.h> ++#include <asm/mcfsim.h> ++ ++extern struct resource *otg_get_resources(void); ++ ++extern struct fsl_usb2_platform_data; ++ ++/* ehci_arc_hc_driver.flags value */ ++#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY) ++ ++static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, ++ enum fsl_usb2_phy_modes phy_mode, ++ unsigned int port_offset); ++ ++static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci) ++{ ++ struct fsl_usb2_platform_data *pdata; ++ ++ pdata = ehci_to_hcd(ehci)->self.controller->platform_data; ++ ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); ++} ++ ++static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) ++{ ++ unsigned int temp; ++ struct fsl_usb2_platform_data *pdata; ++ struct fsl_usb_host_regs *regs; ++ ++ pdata = hcd->self.controller->platform_data; ++ regs = pdata->regs; ++ ++ if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) ++ pdata->xcvr_ops->set_host(); ++ ++ /* set host mode and select "big endian" */ ++ temp = in_be32(®s->usbmode); ++ temp |= USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); ++ out_be32(®s->usbmode, temp); ++ ++ pr_debug("%s: set usbmode to 0x%x\n\n", __func__, ++ in_be32(®s->usbmode)); ++ ++} ++ ++static inline void ++fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) ++{ ++#ifdef CONFIG_USB_M5441X_FSLS ++ MCF_GPIO_PAR_CS &= 0x0F; /*Enable GPIOB5, GPIOB6*/ ++ ++ MCF_GPIO_PDDR_B &= 0xDF; /*GPIOB5, input*/ ++ MCF_GPIO_PDDR_B |= 0x40; /*GPIOB6, output*/ ++ ++ if (on) ++ MCF_GPIO_PODR_B |= 0x40; /*GPIOB6, output 1*/ ++ else ++ MCF_GPIO_PODR_B &= 0xBF; /*GPIOB6, output 0*/ ++#endif ++} ++ ++#endif +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -66,6 +66,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ + obj-$(CONFIG_TC) += tc/ + obj-$(CONFIG_UWB) += uwb/ + obj-$(CONFIG_USB_OTG_UTILS) += usb/otg/ ++obj-$(CONFIG_USB_OTG) += usb/otg/ + obj-$(CONFIG_USB) += usb/ + obj-$(CONFIG_USB_MUSB_HDRC) += usb/musb/ + obj-$(CONFIG_PCI) += usb/ +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -57,6 +57,8 @@ config USB_ARCH_HAS_EHCI + boolean + default y if PPC_83xx + default y if PPC_MPC512x ++ default y if M5445X ++ default y if M5441X + default y if SOC_AU1200 + default y if ARCH_IXP4XX + default y if ARCH_W90X900 +--- a/drivers/usb/core/Kconfig ++++ b/drivers/usb/core/Kconfig +@@ -109,7 +109,7 @@ config USB_SUSPEND + config USB_OTG + bool "OTG support" + depends on USB && EXPERIMENTAL +- depends on USB_SUSPEND ++# depends on USB_SUSPEND + default n + help + The most notable feature of USB OTG is support for a +--- a/drivers/usb/gadget/Kconfig ++++ b/drivers/usb/gadget/Kconfig +@@ -156,7 +156,7 @@ config USB_ATMEL_USBA + + config USB_GADGET_FSL_USB2 + boolean "Freescale Highspeed USB DR Peripheral Controller" +- depends on FSL_SOC || ARCH_MXC ++ depends on FSL_SOC || ARCH_MXC || HAVE_FSL_USB_DR + select USB_GADGET_DUALSPEED + select USB_FSL_MPH_DR_OF if OF + help +--- a/drivers/usb/gadget/fsl_udc_core.c ++++ b/drivers/usb/gadget/fsl_udc_core.c +@@ -1,5 +1,5 @@ + /* +- * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved. ++ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. All rights reserved. + * + * Author: Li Yang <leoli@freescale.com> + * Jiang Bo <tanya.jiang@freescale.com> +@@ -52,6 +52,12 @@ + #define DRIVER_AUTHOR "Li Yang/Jiang Bo" + #define DRIVER_VERSION "Apr 20, 2007" + ++ ++#define USB_MODE_CTRL_MODE_MASK 0x00000003 ++#define USB_MODE_ES 0x00000004 /* (big) Endian */ ++#define cpu_to_hc32(x) (x) ++#define hc32_to_cpu(x) (x) ++ + #define DMA_ADDR_INVALID (~(dma_addr_t)0) + + static const char driver_name[] = "fsl-usb2-udc"; +@@ -62,6 +68,9 @@ static struct usb_dr_device *dr_regs; + static struct usb_sys_interface *usb_sys_regs; + #endif + ++static int fsl_udc_suspend(struct device *dev, pm_message_t state); ++static int fsl_udc_resume(struct device *dev); ++ + /* it is initialized in probe() */ + static struct fsl_udc *udc_controller = NULL; + +@@ -76,6 +85,7 @@ fsl_ep0_desc = { + + static void fsl_ep_fifo_flush(struct usb_ep *_ep); + ++#ifndef CONFIG_COLDFIRE + #ifdef CONFIG_PPC32 + #define fsl_readl(addr) in_le32(addr) + #define fsl_writel(val32, addr) out_le32(addr, val32) +@@ -83,7 +93,7 @@ static void fsl_ep_fifo_flush(struct usb + #define fsl_readl(addr) readl(addr) + #define fsl_writel(val32, addr) writel(val32, addr) + #endif +- ++#endif + /******************************************************************** + * Internal Used Function + ********************************************************************/ +@@ -184,6 +194,12 @@ static int dr_controller_setup(struct fs + unsigned long timeout; + #define FSL_UDC_RESET_TIMEOUT 1000 + ++#ifdef CONFIG_COLDFIRE ++ struct fsl_usb2_platform_data *pdata; ++ if (!udc) ++ return -EINVAL; ++ pdata = udc->pdata; ++#endif + /* Config PHY interface */ + portctrl = fsl_readl(&dr_regs->portsc1); + portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); +@@ -226,11 +242,20 @@ static int dr_controller_setup(struct fs + + /* Set the controller as device mode */ + tmp = fsl_readl(&dr_regs->usbmode); ++#ifdef CONFIG_COLDFIRE ++ tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ ++#endif + tmp |= USB_MODE_CTRL_MODE_DEVICE; + /* Disable Setup Lockout */ + tmp |= USB_MODE_SETUP_LOCK_OFF; ++#ifdef CONFIG_COLDFIRE ++ if (pdata->es) ++ tmp |= USB_MODE_ES; ++#endif + fsl_writel(tmp, &dr_regs->usbmode); +- ++#ifdef CONFIG_COLDFIRE ++ fsl_platform_set_device_mode(pdata); ++#endif + /* Clear the setup status */ + fsl_writel(0, &dr_regs->usbsts); + +@@ -243,7 +268,7 @@ static int dr_controller_setup(struct fs + fsl_readl(&dr_regs->endpointlistaddr)); + + /* Config control enable i/o output, cpu endian register */ +-#ifndef CONFIG_ARCH_MXC ++#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_COLDFIRE) + ctrl = __raw_readl(&usb_sys_regs->control); + ctrl |= USB_CTRL_IOENB; + __raw_writel(ctrl, &usb_sys_regs->control); +@@ -267,7 +292,9 @@ static int dr_controller_setup(struct fs + static void dr_controller_run(struct fsl_udc *udc) + { + u32 temp; +- ++#ifdef CONFIG_COLDFIRE ++ fsl_platform_pullup_enable(udc->pdata); ++#endif + /* Enable DR irq reg */ + temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN + | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN +@@ -277,12 +304,12 @@ static void dr_controller_run(struct fsl + + /* Clear stopped bit */ + udc->stopped = 0; +- ++#ifndef CONFIG_COLDFIRE + /* Set the controller as device mode */ + temp = fsl_readl(&dr_regs->usbmode); + temp |= USB_MODE_CTRL_MODE_DEVICE; + fsl_writel(temp, &dr_regs->usbmode); +- ++#endif + /* Set controller to Run */ + temp = fsl_readl(&dr_regs->usbcmd); + temp |= USB_CMD_RUN_STOP; +@@ -292,7 +319,18 @@ static void dr_controller_run(struct fsl + static void dr_controller_stop(struct fsl_udc *udc) + { + unsigned int tmp; +- ++#ifdef CONFIG_COLDFIRE ++ if (udc->gadget.is_otg) { ++#ifdef CONFIG_USB_M5441X_MAX3353_FSLS ++ if (max3353_read_id_pin()) { ++#else ++ if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) { ++#endif ++ pr_debug("udc: Leaving early\n"); ++ return; ++ } ++ } ++#endif + /* disable all INTR */ + fsl_writel(0, &dr_regs->usbintr); + +@@ -301,7 +339,9 @@ static void dr_controller_stop(struct fs + + /* disable IO output */ + /* usb_sys_regs->control = 0; */ +- ++#ifdef CONFIG_COLDFIRE ++ fsl_platform_pullup_disable(udc->pdata); ++#endif + /* set controller to Stop */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; +@@ -408,10 +448,13 @@ static void struct_ep_qh_setup(struct fs + } + if (zlt) + tmp |= EP_QUEUE_HEAD_ZLT_SEL; +- ++#ifdef CONFIG_COLDFIRE ++ p_QH->max_pkt_length = cpu_to_hc32(tmp); ++#else + p_QH->max_pkt_length = cpu_to_le32(tmp); + p_QH->next_dtd_ptr = 1; + p_QH->size_ioc_int_sts = 0; ++#endif + } + + /* Setup qh structure and ep register for ep0. */ +@@ -616,7 +659,11 @@ static void fsl_queue_td(struct fsl_ep * + struct fsl_req *lastreq; + lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); + lastreq->tail->next_td_ptr = ++#ifdef CONFIG_COLDFIRE ++ cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK); ++#else + cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK); ++#endif + /* Read prime bit, if 1 goto done */ + if (fsl_readl(&dr_regs->endpointprime) & bitmask) + goto out; +@@ -641,11 +688,19 @@ static void fsl_queue_td(struct fsl_ep * + + /* Write dQH next pointer and terminate bit to 0 */ + temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; ++#ifdef CONFIG_COLDFIRE ++ dQH->next_dtd_ptr = cpu_to_hc32(temp); ++#else + dQH->next_dtd_ptr = cpu_to_le32(temp); +- ++#endif + /* Clear active and halt bit */ ++#ifdef CONFIG_COLDFIRE ++ temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE ++ | EP_QUEUE_HEAD_STATUS_HALT)); ++#else + temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE + | EP_QUEUE_HEAD_STATUS_HALT)); ++#endif + dQH->size_ioc_int_sts &= temp; + + /* Ensure that updates to the QH will occure before priming. */ +@@ -682,18 +737,32 @@ static struct ep_td_struct *fsl_build_dt + + dtd->td_dma = *dma; + /* Clear reserved field */ ++#ifdef CONFIG_COLDFIRE ++ swap_temp = hc32_to_cpu(dtd->size_ioc_sts); ++#else + swap_temp = cpu_to_le32(dtd->size_ioc_sts); ++#endif + swap_temp &= ~DTD_RESERVED_FIELDS; ++#ifdef CONFIG_COLDFIRE ++ dtd->size_ioc_sts = cpu_to_hc32(swap_temp); ++#else + dtd->size_ioc_sts = cpu_to_le32(swap_temp); +- ++#endif + /* Init all of buffer page pointers */ + swap_temp = (u32) (req->req.dma + req->req.actual); ++#ifdef CONFIG_COLDFIRE ++ dtd->buff_ptr0 = cpu_to_hc32(swap_temp); ++ dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); ++ dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); ++ dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000); ++ dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000); ++#else + dtd->buff_ptr0 = cpu_to_le32(swap_temp); + dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000); + dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000); + dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000); + dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000); +- ++#endif + req->req.actual += *length; + + /* zlp is needed if req->req.zero is set */ +@@ -715,9 +784,11 @@ static struct ep_td_struct *fsl_build_dt + /* Enable interrupt for the last dtd of a request */ + if (*is_last && !req->req.no_interrupt) + swap_temp |= DTD_IOC; +- ++#ifdef CONFIG_COLDFIRE ++ dtd->size_ioc_sts = cpu_to_hc32(swap_temp); ++#else + dtd->size_ioc_sts = cpu_to_le32(swap_temp); +- ++#endif + mb(); + + VDBG("length = %d address= 0x%x", *length, (int)*dma); +@@ -743,16 +814,22 @@ static int fsl_req_to_dtd(struct fsl_req + is_first = 0; + req->head = dtd; + } else { ++#ifdef CONFIG_COLDFIRE ++ last_dtd->next_td_ptr = cpu_to_hc32(dma); ++#else + last_dtd->next_td_ptr = cpu_to_le32(dma); ++#endif + last_dtd->next_td_virt = dtd; + } + last_dtd = dtd; + + req->dtd_count++; + } while (!is_last); +- ++#ifdef CONFIG_COLDFIRE ++ dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE); ++#else + dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE); +- ++#endif + req->tail = dtd; + + return 0; +@@ -963,7 +1040,39 @@ out: + + return status; + } ++#ifdef CONFIG_COLDFIRE ++static int arcotg_fifo_status(struct usb_ep *_ep) ++{ ++ struct fsl_ep *ep; ++ struct fsl_udc *udc; ++ int size = 0; ++ u32 bitmask; ++ struct ep_queue_head *d_qh; ++ ++ ep = container_of(_ep, struct fsl_ep, ep); ++ if (!_ep || (!ep->desc && ep_index(ep) != 0)) ++ return -ENODEV; ++ ++ udc = (struct fsl_udc *)ep->udc; ++ ++ if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) ++ return -ESHUTDOWN; ++ ++ d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)]; ++ ++ bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) : ++ (1 << (ep_index(ep))); ++ ++ if (fsl_readl(&dr_regs->endptstatus) & bitmask) ++ size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE) ++ >> DTD_LENGTH_BIT_POS; ++ ++ pr_debug("%s %u\n", __func__, size); ++ return size; ++} ++ + ++#endif + static void fsl_ep_fifo_flush(struct usb_ep *_ep) + { + struct fsl_ep *ep; +@@ -1016,6 +1125,9 @@ static struct usb_ep_ops fsl_ep_ops = { + .dequeue = fsl_ep_dequeue, + + .set_halt = fsl_ep_set_halt, ++#ifdef CONFIG_COLDFIRE ++ .fifo_status = arcotg_fifo_status, ++#endif + .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ + }; + +@@ -1396,7 +1508,9 @@ static void tripwire_handler(struct fsl_ + { + u32 temp; + struct ep_queue_head *qh; +- ++#ifdef CONFIG_COLDFIRE ++ struct fsl_usb2_platform_data *pdata = udc->pdata; ++#endif + qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; + + /* Clear bit in ENDPTSETUPSTAT */ +@@ -1410,7 +1524,20 @@ static void tripwire_handler(struct fsl_ + fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); + + /* Copy the setup packet to local buffer */ ++#if CONFIG_COLDFIRE ++ if (pdata->le_setup_buf) { ++ u32 *p = (u32 *)buffer_ptr; ++ u32 *s = (u32 *)qh->setup_buffer; ++ ++ /* Convert little endian setup buffer to CPU endian */ ++ *p++ = le32_to_cpu(*s++); ++ *p = le32_to_cpu(*s); ++ } else { ++ memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); ++ } ++#else + memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); ++#endif + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); + + /* Clear Setup Tripwire */ +@@ -1434,19 +1561,19 @@ static int process_ep_req(struct fsl_udc + actual = curr_req->req.length; + + for (j = 0; j < curr_req->dtd_count; j++) { +- remaining_length = (le32_to_cpu(curr_td->size_ioc_sts) ++ remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts) + & DTD_PACKET_SIZE) + >> DTD_LENGTH_BIT_POS; + actual -= remaining_length; + +- if ((errors = le32_to_cpu(curr_td->size_ioc_sts) & +- DTD_ERROR_MASK)) { ++ errors = hc32_to_cpu(curr_td->size_ioc_sts); ++ if (errors & DTD_ERROR_MASK) { + if (errors & DTD_STATUS_HALTED) { + ERR("dTD error %08x QH=%d\n", errors, pipe); + /* Clear the errors and Halt condition */ +- tmp = le32_to_cpu(curr_qh->size_ioc_int_sts); ++ tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts); + tmp &= ~errors; +- curr_qh->size_ioc_int_sts = cpu_to_le32(tmp); ++ curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp); + status = -EPIPE; + /* FIXME: continue with next queued TD? */ + +@@ -1464,7 +1591,7 @@ static int process_ep_req(struct fsl_udc + ERR("Unknown error has occured (0x%x)!\n", + errors); + +- } else if (le32_to_cpu(curr_td->size_ioc_sts) ++ } else if (hc32_to_cpu(curr_td->size_ioc_sts) + & DTD_STATUS_ACTIVE) { + VDBG("Request not complete"); + status = REQ_UNCOMPLETE; +@@ -1552,7 +1679,10 @@ static void dtd_complete_irq(struct fsl_ + static void port_change_irq(struct fsl_udc *udc) + { + u32 speed; +- ++#ifdef CONFIG_COLDFIRE ++ if (udc->bus_reset) ++ udc->bus_reset = 0; ++#endif + /* Bus resetting is finished */ + if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) { + /* Get the speed */ +@@ -1660,6 +1790,10 @@ static void reset_irq(struct fsl_udc *ud + + if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { + VDBG("Bus reset"); ++#ifdef CONFIG_COLDFIRE ++ /* Bus is reseting */ ++ udc->bus_reset = 1; ++#endif + /* Reset all the queues, include XD, dTD, EP queue + * head and TR Queue */ + reset_queues(udc); +@@ -1793,19 +1927,49 @@ int usb_gadget_probe_driver(struct usb_g + udc_controller->driver = NULL; + goto out; + } +- ++#ifdef CONFIG_COLDFIRE ++ if (udc_controller->transceiver) { ++ /* Suspend the controller until OTG enable it */ ++ udc_controller->stopped = 1; ++ printk(KERN_INFO "Suspend udc for OTG auto detect\n"); ++ ++ /* export udc suspend/resume call to OTG */ ++ udc_controller->gadget.dev.driver->suspend = fsl_udc_suspend; ++ udc_controller->gadget.dev.driver->resume = fsl_udc_resume; ++ ++ /* connect to bus through transceiver */ ++ if (udc_controller->transceiver) { ++ retval = otg_set_peripheral(udc_controller->transceiver, ++ &udc_controller->gadget); ++ if (retval < 0) { ++ ERR("can't bind to transceiver\n"); ++ driver->unbind(&udc_controller->gadget); ++ udc_controller->gadget.dev.driver = 0; ++ udc_controller->driver = 0; ++ return retval; ++ } ++ } ++ } else { ++ /* Enable DR IRQ reg and Set usbcmd reg Run bit */ ++ dr_controller_run(udc_controller); ++ udc_controller->usb_state = USB_STATE_ATTACHED; ++ udc_controller->ep0_state = WAIT_FOR_SETUP; ++ udc_controller->ep0_dir = 0; ++ } ++#else + /* Enable DR IRQ reg and Set usbcmd reg Run bit */ + dr_controller_run(udc_controller); + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_state = WAIT_FOR_SETUP; + udc_controller->ep0_dir = 0; ++#endif + printk(KERN_INFO "%s: bind to driver %s\n", + udc_controller->gadget.name, driver->driver.name); + + out: + if (retval) + printk(KERN_WARNING "gadget driver register failed %d\n", +- retval); ++ retval); + return retval; + } + EXPORT_SYMBOL(usb_gadget_probe_driver); +@@ -2239,7 +2403,7 @@ static int __init fsl_udc_probe(struct p + int ret = -ENODEV; + unsigned int i; + u32 dccparams; +- ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + if (strcmp(pdev->name, driver_name)) { + VDBG("Wrong device"); + return -ENODEV; +@@ -2253,6 +2417,24 @@ static int __init fsl_udc_probe(struct p + + spin_lock_init(&udc_controller->lock); + udc_controller->stopped = 1; ++#ifdef CONFIG_COLDFIRE ++ udc_controller->pdata = pdata; ++#endif ++#ifdef CONFIG_USB_OTG ++ /* Memory and interrupt resources will be passed from OTG */ ++ udc_controller->transceiver = otg_get_transceiver(); ++ if (!udc_controller->transceiver) { ++ printk(KERN_ERR "Can't find OTG driver!\n"); ++ ret = -ENODEV; ++ goto err_kfree; ++ } ++ ++ res = otg_get_resources(); ++ if (!res) { ++ DBG("resource not registered!\n"); ++ return -ENODEV; ++ } ++#else + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -2266,18 +2448,30 @@ static int __init fsl_udc_probe(struct p + ret = -EBUSY; + goto err_kfree; + } +- ++#endif + dr_regs = ioremap(res->start, resource_size(res)); + if (!dr_regs) { + ret = -ENOMEM; + goto err_release_mem_region; + } ++#ifdef CONFIG_COLDFIRE ++ pdata->regs = (void *)dr_regs; ++ fsl_set_usb_accessors(pdata); ++ ++ /* ++ * do platform specific init: check the clock, grab/config pins, etc. ++ */ ++ if (pdata->init && pdata->init(pdev)) { ++ ret = -ENODEV; ++ goto err_iounmap_noclk; ++ } + ++#else + #ifndef CONFIG_ARCH_MXC + usb_sys_regs = (struct usb_sys_interface *) + ((u32)dr_regs + USB_DR_SYS_OFFSET); + #endif +- ++#endif + /* Initialize USB clocks */ + ret = fsl_udc_clk_init(pdev); + if (ret < 0) +@@ -2293,8 +2487,12 @@ static int __init fsl_udc_probe(struct p + /* Get max device endpoints */ + /* DEN is bidirectional ep number, max_ep doubles the number */ + udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2; +- ++#ifdef CONFIG_USB_OTG ++ res++; ++ udc_controller->irq = res->start; ++#else + udc_controller->irq = platform_get_irq(pdev, 0); ++#endif + if (!udc_controller->irq) { + ret = -ENODEV; + goto err_iounmap; +@@ -2314,11 +2512,17 @@ static int __init fsl_udc_probe(struct p + ret = -ENOMEM; + goto err_free_irq; + } +- ++#ifdef CONFIG_COLDFIRE ++ if (!udc_controller->transceiver) { ++ /* initialize usb hw reg except for regs for EP, ++ * leave usbintr reg untouched */ ++ dr_controller_setup(udc_controller); ++ } ++#else + /* initialize usb hw reg except for regs for EP, + * leave usbintr reg untouched */ + dr_controller_setup(udc_controller); +- ++#endif + fsl_udc_clk_finalize(pdev); + + /* Setup gadget structure */ +@@ -2336,7 +2540,10 @@ static int __init fsl_udc_probe(struct p + ret = device_register(&udc_controller->gadget.dev); + if (ret < 0) + goto err_free_irq; +- ++#ifdef CONFIG_COLDFIRE ++ if (udc_controller->transceiver) ++ udc_controller->gadget.is_otg = 1; ++#endif + /* setup QH and epctrl for ep0 */ + ep0_setup(udc_controller); + +@@ -2392,7 +2599,9 @@ err_kfree: + static int __exit fsl_udc_remove(struct platform_device *pdev) + { + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- ++#ifdef CONFIG_COLDFIRE ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++#endif + DECLARE_COMPLETION(done); + + if (!udc_controller) +@@ -2412,31 +2621,103 @@ static int __exit fsl_udc_remove(struct + dma_pool_destroy(udc_controller->td_pool); + free_irq(udc_controller->irq, udc_controller); + iounmap(dr_regs); ++#ifndef CONFIG_USB_OTG + release_mem_region(res->start, res->end - res->start + 1); +- ++#endif + device_unregister(&udc_controller->gadget.dev); + /* free udc --wait for the release() finished */ + wait_for_completion(&done); ++#ifdef CONFIG_COLDFIRE ++ /* ++ * do platform specific un-initialization: ++ * release iomux pins, etc. ++ */ ++ if (pdata->exit) ++ pdata->exit(pdev); ++ ++#endif ++ return 0; ++} ++#ifdef CONFIG_COLDFIRE ++ ++static int udc_suspend(struct fsl_udc *udc) ++{ ++ u32 mode, usbcmd; ++ ++ mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK; ++ usbcmd = fsl_readl(&dr_regs->usbcmd); ++ ++ pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped); ++ ++ /* ++ * If the controller is already stopped, then this must be a ++ * PM suspend. Remember this fact, so that we will leave the ++ * controller stopped at PM resume time. ++ */ ++ if (udc->stopped) { ++ pr_debug("gadget already stopped, leaving early\n"); ++ udc->already_stopped = 1; ++ return 0; ++ } + ++ if (mode != USB_MODE_CTRL_MODE_DEVICE) { ++ pr_debug("gadget not in device mode, leaving early\n"); ++ return 0; ++ } ++ ++ printk(KERN_INFO "USB Gadget suspended\n"); ++ ++ /* stop the controller */ ++ usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP; ++ fsl_writel(usbcmd, &dr_regs->usbcmd); ++ ++ udc->stopped = 1; + return 0; + } + ++#endif + /*----------------------------------------------------------------- + * Modify Power management attributes + * Used by OTG statemachine to disable gadget temporarily + -----------------------------------------------------------------*/ ++#ifdef CONFIG_COLDFIRE ++static int fsl_udc_suspend(struct device *dev, pm_message_t state) ++#else + static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) ++#endif + { ++#ifdef CONFIG_COLDFIRE ++ return udc_suspend(udc_controller); ++#else + dr_controller_stop(udc_controller); + return 0; ++#endif + } + + /*----------------------------------------------------------------- + * Invoked on USB resume. May be called in_interrupt. + * Here we start the DR controller and enable the irq + *-----------------------------------------------------------------*/ ++#ifdef CONFIG_COLDFIRE ++static int fsl_udc_resume(struct device *dev) ++#else + static int fsl_udc_resume(struct platform_device *pdev) ++#endif + { ++#ifdef CONFIG_COLDFIRE ++ pr_debug("%s(): stopped %d already_stopped %d\n", __func__, ++ udc_controller->stopped, udc_controller->already_stopped); ++ ++ /* ++ * If the controller was stopped at suspend time, then ++ * don't resume it now. ++ */ ++ if (udc_controller->already_stopped) { ++ udc_controller->already_stopped = 0; ++ pr_debug("gadget was already stopped, leaving early\n"); ++ return 0; ++ } ++#endif + /* Enable DR irq reg and set controller Run */ + if (udc_controller->stopped) { + dr_controller_setup(udc_controller); +@@ -2445,6 +2726,9 @@ static int fsl_udc_resume(struct platfor + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_state = WAIT_FOR_SETUP; + udc_controller->ep0_dir = 0; ++ ++ printk(KERN_INFO "USB Gadget resumed\n"); ++ + return 0; + } + +@@ -2455,11 +2739,15 @@ static int fsl_udc_resume(struct platfor + static struct platform_driver udc_driver = { + .remove = __exit_p(fsl_udc_remove), + /* these suspend and resume are not usb suspend and resume */ ++#ifndef CONFIG_COLDFIRE + .suspend = fsl_udc_suspend, + .resume = fsl_udc_resume, ++#endif + .driver = { + .name = (char *)driver_name, + .owner = THIS_MODULE, ++ .suspend = fsl_udc_suspend, ++ .resume = fsl_udc_resume, + }, + }; + +--- a/drivers/usb/gadget/fsl_usb2_udc.h ++++ b/drivers/usb/gadget/fsl_usb2_udc.h +@@ -461,6 +461,7 @@ struct fsl_ep { + struct fsl_udc { + struct usb_gadget gadget; + struct usb_gadget_driver *driver; ++ struct fsl_usb2_platform_data *pdata; + struct completion *done; /* to make sure release() is done */ + struct fsl_ep *eps; + unsigned int max_ep; +@@ -473,6 +474,7 @@ struct fsl_udc { + unsigned vbus_active:1; + unsigned stopped:1; + unsigned remote_wakeup:1; ++ unsigned already_stopped:1; + + struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ + struct fsl_req *status_req; /* ep0 status request */ +@@ -482,6 +484,7 @@ struct fsl_udc { + size_t ep_qh_size; /* size after alignment adjustment*/ + dma_addr_t ep_qh_dma; /* dma address of QH */ + ++ u32 bus_reset; /* Device is bus reseting */ + u32 max_pipes; /* Device max pipes */ + u32 resume_state; /* USB state to resume */ + u32 usb_state; /* USB current state */ +@@ -581,4 +584,17 @@ static inline void fsl_udc_clk_release(v + } + #endif + ++#ifdef CONFIG_COLDFIRE ++#include <asm/mcfsim.h> ++#include <asm/fsl_usb_io.h> ++#include <asm/fsl_usb_gadget.h> ++#include <asm/cf_cacheflush.h> ++ ++extern struct resource *otg_get_resources(void); ++#ifdef CONFIG_USB_M5441X_MAX3353_FSLS ++extern int max3353_read_id_pin(void); ++#endif ++ ++#endif ++ + #endif +--- a/drivers/usb/gadget/serial.c ++++ b/drivers/usb/gadget/serial.c +@@ -4,6 +4,7 @@ + * Copyright (C) 2003 Al Borchers (alborchers@steinerpoint.com) + * Copyright (C) 2008 by David Brownell + * Copyright (C) 2008 by Nokia Corporation ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This software is distributed under the terms of the GNU General + * Public License ("GPL") as published by the Free Software Foundation, +@@ -134,7 +135,44 @@ MODULE_PARM_DESC(use_obex, "Use CDC OBEX + static unsigned n_ports = 1; + module_param(n_ports, uint, 0); + MODULE_PARM_DESC(n_ports, "number of ports to create, default=1"); +- ++/*-------------------------------------------------------------------------*/ ++#if 0 ++static void gs_setup_complete_set_line_coding(struct usb_ep *ep, ++ struct usb_request *req) ++{ ++ struct gs_dev *dev = ep->driver_data; ++ struct gs_port *port = dev->dev_port[0]; /* ACM only has one port */ ++ ++ switch (req->status) { ++ case 0: ++ /* normal completion */ ++ if (req->actual != sizeof(port->port_line_coding)) ++ usb_ep_set_halt(ep); ++ else if (port) { ++ struct usb_cdc_line_coding *value = req->buf; ++ ++ /* REVISIT: we currently just remember this data. ++ * If we change that, (a) validate it first, then ++ * (b) update whatever hardware needs updating. ++ */ ++ spin_lock(&port->port_lock); ++ port->port_line_coding = *value; ++ spin_unlock(&port->port_lock); ++ } ++ break; ++ ++ case -ESHUTDOWN: ++ /* disconnect */ ++ gs_free_req(ep, req); ++ break; ++ ++ default: ++ /* unexpected */ ++ break; ++ } ++ return; ++} ++#endif + /*-------------------------------------------------------------------------*/ + + static int __init serial_bind_config(struct usb_configuration *c) +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -95,13 +95,14 @@ config USB_EHCI_BIG_ENDIAN_MMIO + bool + depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \ + ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ +- PPC_MPC512x || CPU_CAVIUM_OCTEON) ++ PPC_MPC512x || CPU_CAVIUM_OCTEON || \ ++ COLDFIRE) + default y + + config USB_EHCI_BIG_ENDIAN_DESC + bool + depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \ +- PPC_MPC512x) ++ PPC_MPC512x || COLDFIRE) + default y + + config XPS_USB_HCD_XILINX +@@ -120,12 +121,77 @@ config USB_FSL_MPH_DR_OF + + config USB_EHCI_FSL + bool "Support for Freescale on-chip EHCI USB controller" +- depends on USB_EHCI_HCD && FSL_SOC ++ depends on USB_EHCI_HCD && (FSL_SOC || COLDFIRE) + select USB_EHCI_ROOT_HUB_TT + select USB_FSL_MPH_DR_OF if OF + ---help--- + Variation of ARC USB block used in some Freescale chips. + ++config USB_M5441X_PLLCLK ++ bool "ColdFire USB module use PLL clock source" ++ depends on M5441X ++ ---help--- ++ Select USB clock source from PLL instead external USBCLKIN, ++ to generate the exact USB module 60MHZ clock, the system clock ++ must be shrink to match the divide requirement which is down ++ in u-boot. ++ ++config USB_M5441X_H1 ++ bool "ColdFire EHCI USB Host module support" ++ depends on USB_EHCI_HCD && M5441X ++ ---help--- ++ Some ColdFire platform have two USB controllers, one is HOST module, ++ the other is OTG module, this config select the HOST module support. ++ ++choice ++ prompt "Selcet ColdFire HOST module transceiver" ++ depends on USB_M5441X_H1 ++ default USB_M5441X_H1_FSLS ++ ++config USB_M5441X_H1_FSLS ++ bool "on-chip (FS/LS only)" ++ depends on M5441X ++ ---help--- ++ Enable support for the on-chip FS/LS transceiver. ++endchoice ++ ++choice ++ prompt "Select ColdiFire OTG module transceiver" ++ depends on M5445X || M5441X ++ default USB_M5445X_ULPI if M5445X ++ default USB_M5441X_ULPI if M5441X ++ ++config USB_M5445X_ULPI ++ bool "External ULPI" ++ depends on M5445X ++ ---help--- ++ Enable support for the external HS ULPI transceiver. ++ ++config USB_M5445X_FSLS ++ bool "On-chip (FL/LS only)" ++ depends on M54455EVB ++ ---help--- ++ Enable support for the on-chip FL/LS transceiver. ++ ++config USB_M5441X_ULPI ++ bool "External ULPI" ++ depends on M5441X ++ ---help--- ++ Enable support for the external HS ULPI transceiver. ++ ++config USB_M5441X_FSLS ++ bool "On-chip (FL/LS only)" ++ depends on M54418EVB ++ ---help--- ++ Enable support for the on-chip FL/LS transceiver. ++ ++config USB_M5441X_MAX3353_FSLS ++ bool "MAX3353 chip charge pump to on-chip (FS/LS only)" ++ depends on M54418EVB ++ ---help--- ++ Max3353 provides charge pump for SER1 board on m54418 platform. ++endchoice ++ + config USB_EHCI_MXC + bool "Support for Freescale on-chip EHCI USB controller" + depends on USB_EHCI_HCD && ARCH_MXC +--- a/drivers/usb/host/ehci-fsl.c ++++ b/drivers/usb/host/ehci-fsl.c +@@ -22,16 +22,21 @@ + * Jerry Huang <Chang-Ming.Huang@freescale.com> and + * Anton Vorontsov <avorontsov@ru.mvista.com>. + */ +- + #include <linux/kernel.h> + #include <linux/types.h> + #include <linux/delay.h> + #include <linux/pm.h> + #include <linux/platform_device.h> + #include <linux/fsl_devices.h> +- ++#include <linux/usb/otg.h> + #include "ehci-fsl.h" + ++#ifdef DEBUG ++#define DBG(X...) printk(X) ++#else ++#define DBG(X...) ++#endif ++ + /* configure so an HC device and id are always provided */ + /* always called with process context; sleeping is OK */ + +@@ -75,7 +80,27 @@ static int usb_hcd_fsl_probe(const struc + dev_name(&pdev->dev)); + return -ENODEV; + } +- ++ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); ++ if (!hcd) { ++ retval = -ENOMEM; ++ goto err1; ++ } ++#ifdef CONFIG_USB_OTG ++ if (pdata->operating_mode == FSL_USB2_DR_OTG) { ++ res = otg_get_resources(); ++ if (!res) { ++ dev_err(&pdev->dev, ++ "Found HC with no IRQ. Check %s setup!\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ goto err2; ++ } ++ irq = res[1].start; ++ hcd->rsrc_start = res[0].start; ++ hcd->rsrc_len = res[0].end - res[0].start + 1; ++ } else ++#endif ++ { + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, +@@ -85,12 +110,6 @@ static int usb_hcd_fsl_probe(const struc + } + irq = res->start; + +- hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); +- if (!hcd) { +- retval = -ENOMEM; +- goto err1; +- } +- + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, +@@ -101,12 +120,15 @@ static int usb_hcd_fsl_probe(const struc + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; ++#ifndef CONFIG_USB_OTG + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + retval = -EBUSY; + goto err2; + } ++#endif ++ } + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + + if (hcd->regs == NULL) { +@@ -124,22 +146,56 @@ static int usb_hcd_fsl_probe(const struc + retval = -ENODEV; + goto err3; + } +- ++#ifndef CONFIG_COLDFIRE + /* Enable USB controller, 83xx or 8536 */ + if (pdata->have_sysif_regs) + setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4); +- ++#endif + /* Don't need to set host mode here. It will be done by tdi_reset() */ +- ++#ifdef CONFIG_COLDFIRE ++ fsl_platform_set_host_mode(hcd); ++ hcd->power_budget = pdata->power_budget; ++#endif + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (retval != 0) + goto err4; ++#ifdef CONFIG_COLDFIRE ++ fsl_platform_set_vbus_power(pdata, 1); ++#endif ++#ifdef CONFIG_USB_OTG ++ if (pdata->operating_mode == FSL_USB2_DR_OTG) { ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ ++ DBG("pdev=0x%p hcd=0x%p ehci=0x%p\n", pdev, hcd, ehci); ++ ++ ehci->transceiver = otg_get_transceiver(); ++ DBG("ehci->transceiver=0x%p\n", ehci->transceiver); ++ ++ if (ehci->transceiver) { ++ retval = otg_set_host(ehci->transceiver, ++ &ehci_to_hcd(ehci)->self); ++ if (retval) { ++ printk(KERN_INFO "otg transceiver set host failed\n"); ++ if (ehci->transceiver) ++ put_device(ehci->transceiver->dev); ++ goto err4; ++ } ++ } else { ++ printk(KERN_ERR "can't find transceiver\n"); ++ retval = -ENODEV; ++ goto err4; ++ } ++ } ++#endif ++ + return retval; + + err4: + iounmap(hcd->regs); + err3: ++#ifndef CONFIG_USB_OTG + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++#endif + err2: + usb_put_hcd(hcd); + err1: +@@ -164,9 +220,24 @@ static void usb_hcd_fsl_remove(struct us + struct platform_device *pdev) + { + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++#ifdef CONFIG_COLDFIRE ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); + ++ /* DDD shouldn't we turn off the power here? */ ++ fsl_platform_set_vbus_power(pdata, 0); ++ ++ if (ehci->transceiver) { ++ (void)otg_set_host(ehci->transceiver, 0); ++ put_device(ehci->transceiver->dev); ++ } else { ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ } ++ ++ ++#endif + usb_remove_hcd(hcd); + ++ usb_put_hcd(hcd); + /* + * do platform specific un-initialization: + * release iomux pins, disable clock, etc. +@@ -174,8 +245,6 @@ static void usb_hcd_fsl_remove(struct us + if (pdata->exit) + pdata->exit(pdev); + iounmap(hcd->regs); +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +- usb_put_hcd(hcd); + } + + static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, +@@ -238,7 +307,7 @@ static void ehci_fsl_usb_setup(struct eh + if ((pdata->operating_mode == FSL_USB2_DR_HOST) || + (pdata->operating_mode == FSL_USB2_DR_OTG)) + ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); +- ++#ifndef CONFIG_COLDFIRE + if (pdata->operating_mode == FSL_USB2_MPH_HOST) { + unsigned int chip, rev, svr; + +@@ -255,7 +324,7 @@ static void ehci_fsl_usb_setup(struct eh + if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) + ehci_fsl_setup_phy(ehci, pdata->phy_mode, 1); + } +- ++#endif + if (pdata->have_sysif_regs) { + #ifdef CONFIG_PPC_85xx + out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008); +@@ -271,7 +340,11 @@ static void ehci_fsl_usb_setup(struct eh + /* called after powerup, by probe or system-pm "wakeup" */ + static int ehci_fsl_reinit(struct ehci_hcd *ehci) + { ++#ifdef CONFIG_COLDFIRE ++ fsl_platform_usb_setup(ehci); ++#else + ehci_fsl_usb_setup(ehci); ++#endif + ehci_port_power(ehci, 0); + + return 0; +@@ -334,7 +407,6 @@ static struct ehci_fsl *hcd_to_ehci_fsl( + + return container_of(ehci, struct ehci_fsl, ehci); + } +- + static int ehci_fsl_drv_suspend(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); +@@ -371,7 +443,6 @@ static int ehci_fsl_drv_resume(struct de + + return 0; + } +- + static int ehci_fsl_drv_restore(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); +@@ -387,6 +458,144 @@ static struct dev_pm_ops ehci_fsl_pm_ops + }; + + #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) ++ ++/* suspend/resume, section 4.3 */ ++ ++/* These routines rely on the bus (pci, platform, etc) ++ * to handle powerdown and wakeup, and currently also on ++ * transceivers that don't need any software attention to set up ++ * the right sort of wakeup. ++ * ++ * They're also used for turning on/off the port when doing OTG. ++ */ ++static int ehci_fsl_suspend(struct device *dev, ++ pm_message_t message) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ u32 tmp; ++ struct fsl_usb2_platform_data *pdata = dev->platform_data; ++ ++#ifdef DEBUG ++ u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); ++ mode &= USBMODE_CM_MASK; ++ tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ ++ ++ DBG(KERN_DEBUG "%s('%s'): suspend=%d already_suspended=%d " ++ "mode=%d usbcmd %08x\n", __func__, pdata->name, ++ pdata->suspended, pdata->already_suspended, mode, tmp); ++#endif ++ /* ++ * If the controller is already suspended, then this must be a ++ * PM suspend. Remember this fact, so that we will leave the ++ * controller suspended at PM resume time. ++ */ ++ if (pdata->suspended) { ++ pr_debug("%s: already suspended, leaving early\n", __func__); ++ pdata->already_suspended = 1; ++ return 0; ++ } ++ ++ pr_debug("%s: suspending...\n", __func__); ++ ++ DBG(KERN_INFO "USB Host suspended\n"); ++ ++ hcd->state = HC_STATE_SUSPENDED; ++ dev->power.power_state = PMSG_SUSPEND; ++ ++ /* ignore non-host interrupts */ ++ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ++ ++ /* stop the controller */ ++ tmp = ehci_readl(ehci, &ehci->regs->command); ++ tmp &= ~CMD_RUN; ++ ehci_writel(ehci, tmp, &ehci->regs->command); ++ ++ /* save EHCI registers */ ++ pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); ++ pdata->pm_command &= ~CMD_RUN; ++ pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); ++ pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); ++ pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); ++ pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); ++ pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); ++ pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); ++ pdata->pm_configured_flag = ++ ehci_readl(ehci, &ehci->regs->configured_flag); ++ pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); ++ ++ /* clear the W1C bits */ ++ pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); ++ ++ pdata->suspended = 1; ++#if 0 ++ /* clear PP to cut power to the port */ ++ tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); ++ tmp &= ~PORT_POWER; ++ ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); ++#endif ++ return 0; ++} ++ ++static int ehci_fsl_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ u32 tmp; ++ struct fsl_usb2_platform_data *pdata = dev->platform_data; ++ ++ pr_debug("%s('%s'): suspend=%d already_suspended=%d\n", __func__, ++ pdata->name, pdata->suspended, pdata->already_suspended); ++ ++ /* ++ * If the controller was already suspended at suspend time, ++ * then don't resume it now. ++ */ ++ if (pdata->already_suspended) { ++ pr_debug("already suspended, leaving early\n"); ++ pdata->already_suspended = 0; ++ return 0; ++ } ++ ++ if (!pdata->suspended) { ++ pr_debug("not suspended, leaving early\n"); ++ return 0; ++ } ++ ++ DBG(KERN_INFO "USB Host resumed\n"); ++ ++ pdata->suspended = 0; ++ ++ pr_debug("%s resuming...\n", __func__); ++ ++ /* set host mode */ ++ fsl_platform_set_host_mode(hcd); ++ ++ ++ /* restore EHCI registers */ ++ ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); ++ ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); ++ ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); ++ ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); ++ ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); ++ ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); ++ ehci_writel(ehci, pdata->pm_configured_flag, ++ &ehci->regs->configured_flag); ++ ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); ++ ++ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ++ hcd->state = HC_STATE_RUNNING; ++ dev->power.power_state = PMSG_ON; ++ ++ tmp = ehci_readl(ehci, &ehci->regs->command); ++ tmp |= CMD_RUN; ++ ehci_writel(ehci, tmp, &ehci->regs->command); ++ ++ usb_hcd_resume_root_hub(hcd); ++ ++ return 0; ++} ++ + #else + #define EHCI_FSL_PM_OPS NULL + #endif /* CONFIG_PM */ +@@ -431,7 +640,11 @@ static const struct hc_driver ehci_fsl_h + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, ++#ifndef CONFIG_COLDFIRE + .port_handed_over = ehci_port_handed_over, ++#else ++ .start_port_reset = ehci_start_port_reset, ++#endif + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, + }; +@@ -460,8 +673,16 @@ static struct platform_driver ehci_fsl_d + .probe = ehci_fsl_drv_probe, + .remove = ehci_fsl_drv_remove, + .shutdown = usb_hcd_platform_shutdown, ++#ifdef CONFIG_PM ++#ifndef CONFIG_COLDFIRE ++ .suspend = ehci_fsl_suspend, ++ .resume = ehci_fsl_resume, ++#endif ++#endif + .driver = { + .name = "fsl-ehci", + .pm = EHCI_FSL_PM_OPS, ++ .suspend = ehci_fsl_suspend, ++ .resume = ehci_fsl_resume, + }, + }; +--- a/drivers/usb/host/ehci-fsl.h ++++ b/drivers/usb/host/ehci-fsl.h +@@ -42,4 +42,11 @@ + #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ + #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ + #define SNOOP_SIZE_2GB 0x1e ++ ++#ifdef CONFIG_COLDFIRE ++#define FSL_SOC_USB_USBMODE 0x1a8 ++ ++#include <asm/fsl_usb_platform.h> ++#include <asm/fsl_usb_io.h> ++#endif + #endif /* _EHCI_FSL_H */ +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -1,5 +1,6 @@ + /* + * Copyright (C) 2001-2004 by David Brownell ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the +@@ -41,6 +42,39 @@ static int ehci_hub_control( + u16 wLength + ); + ++#ifdef CONFIG_COLDFIRE ++ ++#ifdef CONFIG_USB_OTG ++static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ u32 status; ++ ++ if (!port) ++ return -EINVAL; ++ port--; ++ ++ /* start port reset before HNP protocol time out */ ++ status = readl(&ehci->regs->port_status[port]); ++ if (!(status & PORT_CONNECT)) ++ return -ENODEV; ++ ++ /* khubd will finish the reset later */ ++ if (ehci_is_TDI(ehci)) ++ writel(PORT_RESET | (status & ~(PORT_CSC | PORT_PEC ++ | PORT_OCC)), &ehci->regs->port_status[port]); ++ else ++ writel(PORT_RESET, &ehci->regs->port_status[port]); ++ ++ return 0; ++} ++#else ++static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) ++{ ++ return 0; ++} ++#endif /* CONFIG_USB_OTG */ ++#endif + /* After a power loss, ports that were owned by the companion must be + * reset so that the companion can still own them. + */ +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -1,6 +1,7 @@ + /* + * Copyright (c) 2001-2002 by David Brownell +- * ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your +@@ -147,7 +148,9 @@ struct ehci_hcd { /* one per controlle + unsigned has_lpm:1; /* support link power management */ + unsigned has_ppcd:1; /* support per-port change bits */ + u8 sbrn; /* packed release number */ +- ++#if defined(CONFIG_COLDFIRE) ++ struct otg_transceiver *transceiver; ++#endif + /* irq statistics */ + #ifdef EHCI_STATS + struct ehci_stats stats; +@@ -617,6 +620,54 @@ ehci_port_speed(struct ehci_hcd *ehci, u + #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) + #endif + ++#if defined(CONFIG_COLDFIRE) ++ ++#if defined(CONFIG_MMU) ++#include <asm/fsl_usb_io.h> ++/* ++ * Sorry, include/asm-m68k/io.h is messed up. It will give you a ++ * BE readl or a LE readl depending on whether or not CONFIG_PCI is set. ++ * how broken is that? Do the right thing here. ++ */ ++#undef readl ++#undef writel ++ ++#define readl(addr) in_le32((__force unsigned *)(addr)) ++#define writel(val, addr) out_le32((__force unsigned *)(addr), (val)) ++ ++#define readl_be(addr) in_be32((__force unsigned *)(addr)) ++#define writel_be(val, addr) out_be32((__force unsigned *)(addr), (val)) ++ ++#else /* !CONFIG_MMU */ ++ ++#define readl_be(addr) \ ++ ({u32 __v = (*(__force volatile u32 *)addr); __v; }) ++#define writel_be(val, addr) \ ++ (void)((*(__force volatile u32 *)addr) = val) ++ ++#ifndef in_be32 ++#define in_be32(addr) \ ++ ({ u32 __v = (*(__force volatile u32 *)(addr)); __v; }) ++#endif ++ ++#ifndef in_le32 ++#define in_le32(addr) \ ++ ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *)(addr)); __v; }) ++#endif ++ ++#ifndef out_be32 ++#define out_be32(addr, l) (void)((*(__force volatile u32 *)(addr)) = (l)) ++#endif ++ ++#ifndef out_le32 ++#define out_le32(addr, l) \ ++ (void)((*(__force volatile __le32 *)(addr)) = cpu_to_le32(l)) ++#endif ++ ++#endif ++ ++#endif /* CONFIG_COLDFIRE */ ++ + static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, + __u32 __iomem * regs) + { +--- a/drivers/usb/otg/Makefile ++++ b/drivers/usb/otg/Makefile +@@ -18,3 +18,10 @@ obj-$(CONFIG_NOP_USB_XCEIV) += nop-usb-x + obj-$(CONFIG_USB_ULPI) += ulpi.o + obj-$(CONFIG_USB_MSM_OTG_72K) += msm72k_otg.o + obj-$(CONFIG_AB8500_USB) += ab8500-usb.o ++ ++obj-$(CONFIG_USB_OTG) += usb.o ++fsl_usb2_otg-objs := fsl_otg.o otg_fsm.o ++#ifneq ($(CONFIG_USB_OTG),) ++ifneq ($(CONFIG_USB_OTG),) ++obj-m += fsl_usb2_otg.o ++endif +--- /dev/null ++++ b/drivers/usb/otg/fsl_otg.c +@@ -0,0 +1,1212 @@ ++/* ++ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: Li Yang <LeoLi@freescale.com> ++ * Jerry Huang <Chang-Ming.Huang@freescale.com> ++ * ++ * Initialization based on code from Shlomi Gridish. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/kernel.h> ++#include <linux/delay.h> ++#include <linux/ioport.h> ++#include <linux/sched.h> ++#include <linux/slab.h> ++#include <linux/smp_lock.h> ++#include <linux/proc_fs.h> ++#include <linux/errno.h> ++#include <linux/init.h> ++#include <linux/reboot.h> ++#include <linux/timer.h> ++#include <linux/list.h> ++#include <linux/usb.h> ++#include <linux/device.h> ++#include <linux/usb/ch9.h> ++#include <linux/usb/gadget.h> ++#include <linux/workqueue.h> ++#include <linux/time.h> ++#include <linux/fsl_devices.h> ++#include <linux/platform_device.h> ++ ++#include <linux/io.h> ++#include <asm/irq.h> ++#include <asm/system.h> ++#include <asm/byteorder.h> ++#include <linux/uaccess.h> ++#include <asm/unaligned.h> ++ ++#include "fsl_otg.h" ++ ++/* ++#undef DBG ++#undef VDBG ++#define DBG(x...) printk(x) ++#define VDBG(x...) printk(x) ++*/ ++ ++#define CONFIG_USB_OTG_DEBUG_FILES ++#define DRIVER_VERSION "$Revision: 1.55 $" ++#define DRIVER_AUTHOR "Jerry Huang/Li Yang" ++#define DRIVER_DESC "Freescale USB OTG Driver" ++#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC ++ ++MODULE_DESCRIPTION("Freescale USB OTG Transceiver Driver"); ++ ++static const char driver_name[] = "fsl-usb2-otg"; ++ ++const pm_message_t otg_suspend_state = { ++ .event = 1, ++}; ++ ++#define HA_DATA_PULSE 1 ++ ++volatile static struct usb_dr_mmap *usb_dr_regs; ++static struct fsl_otg *fsl_otg_dev; ++static int srp_wait_done; ++ ++/* FSM timers */ ++struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, ++ *b_ase0_brst_tmr, *b_se0_srp_tmr; ++ ++/* Driver specific timers */ ++struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr, ++ *b_srp_wait_tmr, *a_wait_enum_tmr; ++ ++static struct list_head active_timers; ++ ++static struct fsl_otg_config fsl_otg_initdata = { ++ .otg_port = 1, ++}; ++ ++/* Routines to access transceiver ULPI registers */ ++u8 view_ulpi(u8 addr) ++{ ++ u32 temp; ++ ++ temp = 0x40000000 | (addr << 16); ++ temp = cpu_to_le32(temp); ++ fsl_writel(temp, &usb_dr_regs->ulpiview); ++ udelay(1000); ++ while (temp & 0x40) ++ temp = fsl_readl(&usb_dr_regs->ulpiview); ++ return (le32_to_cpu(temp) & 0x0000ff00) >> 8; ++} ++ ++int write_ulpi(u8 addr, u8 data) ++{ ++ u32 temp; ++ ++ temp = 0x60000000 | (addr << 16) | data; ++ temp = cpu_to_hc32(temp); ++ fsl_writel(temp, &usb_dr_regs->ulpiview); ++ return 0; ++} ++ ++/* -------------------------------------------------------------*/ ++/* Operations that will be called from OTG Finite State Machine */ ++ ++/* Charge vbus for vbus pulsing in SRP */ ++void fsl_otg_chrg_vbus(int on) ++{ ++ u32 tmp; ++ ++ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; ++ ++ if (on) ++ /* stop discharging, start charging */ ++ tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) | ++ OTGSC_CTRL_VBUS_CHARGE; ++ else ++ /* stop charging */ ++ tmp &= ~OTGSC_CTRL_VBUS_CHARGE; ++ ++ fsl_writel(tmp, &usb_dr_regs->otgsc); ++} ++ ++/* Discharge vbus through a resistor to ground */ ++void fsl_otg_dischrg_vbus(int on) ++{ ++ u32 tmp; ++ ++ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; ++ ++ if (on) ++ /* stop charging, start discharging */ ++ tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) | ++ OTGSC_CTRL_VBUS_DISCHARGE; ++ else ++ /* stop discharging */ ++ tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE; ++ ++ fsl_writel(tmp, &usb_dr_regs->otgsc); ++} ++ ++/* A-device driver vbus, controlled through PP bit in PORTSC */ ++void fsl_otg_drv_vbus(int on) ++{ ++/* if (on) ++ usb_dr_regs->portsc = ++ cpu_to_le32((le32_to_cpu(usb_dr_regs->portsc) & ++ ~PORTSC_W1C_BITS) | PORTSC_PORT_POWER); ++ else ++ usb_dr_regs->portsc = ++ cpu_to_le32(le32_to_cpu(usb_dr_regs->portsc) & ++ ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER); ++*/ ++} ++ ++/* ++ * Pull-up D+, signalling connect by periperal. Also used in ++ * data-line pulsing in SRP ++ */ ++void fsl_otg_loc_conn(int on) ++{ ++ u32 tmp; ++ ++ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; ++ ++ if (on) ++ tmp |= OTGSC_CTRL_DATA_PULSING; ++ else ++ tmp &= ~OTGSC_CTRL_DATA_PULSING; ++ ++ fsl_writel(tmp, &usb_dr_regs->otgsc); ++} ++ ++/* Generate SOF by host. This is controlled through suspend/resume the ++ * port. In host mode, controller will automatically send SOF. ++ * Suspend will block the data on the port. ++ */ ++void fsl_otg_loc_sof(int on) ++{ ++ u32 tmp; ++ ++ tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS; ++ if (on) ++ tmp |= PORTSC_PORT_FORCE_RESUME; ++ else ++ tmp |= PORTSC_PORT_SUSPEND; ++ ++ fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc); ++ ++} ++ ++/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */ ++void fsl_otg_start_pulse(void) ++{ ++ u32 tmp; ++ ++ srp_wait_done = 0; ++#ifdef HA_DATA_PULSE ++ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; ++ tmp |= OTGSC_HA_DATA_PULSE; ++ fsl_writel(tmp, &usb_dr_regs->otgsc); ++#else ++ fsl_otg_loc_conn(1); ++#endif ++ ++ fsl_otg_add_timer(b_data_pulse_tmr); ++} ++ ++void fsl_otg_pulse_vbus(void); ++ ++void b_data_pulse_end(unsigned long foo) ++{ ++#ifdef HA_DATA_PULSE ++#else ++ fsl_otg_loc_conn(0); ++#endif ++ ++ /* Do VBUS pulse after data pulse */ ++ fsl_otg_pulse_vbus(); ++} ++ ++void fsl_otg_pulse_vbus(void) ++{ ++ srp_wait_done = 0; ++ fsl_otg_chrg_vbus(1); ++ /* start the timer to end vbus charge */ ++ fsl_otg_add_timer(b_vbus_pulse_tmr); ++} ++ ++void b_vbus_pulse_end(unsigned long foo) ++{ ++ fsl_otg_chrg_vbus(0); ++ ++ /* As USB3300 using the same a_sess_vld and b_sess_vld voltage ++ * we need to discharge the bus for a while to distinguish ++ * residual voltage of vbus pulsing and A device pull up */ ++ fsl_otg_dischrg_vbus(1); ++ fsl_otg_add_timer(b_srp_wait_tmr); ++} ++ ++void b_srp_end(unsigned long foo) ++{ ++ fsl_otg_dischrg_vbus(0); ++ srp_wait_done = 1; ++ ++ if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) && ++ fsl_otg_dev->fsm.b_sess_vld) ++ fsl_otg_dev->fsm.b_srp_done = 1; ++} ++ ++/* Workaround for a_host suspending too fast. When a_bus_req=0, ++ * a_host will start by SRP. It needs to set b_hnp_enable before ++ * actually suspending to start HNP ++ */ ++void a_wait_enum(unsigned long foo) ++{ ++ VDBG("a_wait_enum timeout\n"); ++ if (!fsl_otg_dev->otg.host->b_hnp_enable) ++ fsl_otg_add_timer(a_wait_enum_tmr); ++ else ++ otg_statemachine(&fsl_otg_dev->fsm); ++} ++ ++/* ------------------------------------------------------*/ ++ ++/* The timeout callback function to set time out bit */ ++void set_tmout(unsigned long indicator) ++{ ++ *(int *)indicator = 1; ++} ++ ++/* Initialize timers */ ++int fsl_otg_init_timers(struct otg_fsm *fsm) ++{ ++ /* FSM used timers */ ++ a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE, ++ (unsigned long)&fsm->a_wait_vrise_tmout); ++ if (a_wait_vrise_tmr == NULL) ++ return -ENOMEM; ++ ++ a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON, ++ (unsigned long)&fsm->a_wait_bcon_tmout); ++ if (a_wait_bcon_tmr == NULL) ++ return -ENOMEM; ++ ++ a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS, ++ (unsigned long)&fsm->a_aidl_bdis_tmout); ++ if (a_aidl_bdis_tmr == NULL) ++ return -ENOMEM; ++ ++ b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST, ++ (unsigned long)&fsm->b_ase0_brst_tmout); ++ if (b_ase0_brst_tmr == NULL) ++ return -ENOMEM; ++ ++ b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP, ++ (unsigned long)&fsm->b_se0_srp); ++ if (b_se0_srp_tmr == NULL) ++ return -ENOMEM; ++ ++ b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL, ++ (unsigned long)&fsm->b_srp_done); ++ if (b_srp_fail_tmr == NULL) ++ return -ENOMEM; ++ ++ a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10, ++ (unsigned long)&fsm); ++ if (a_wait_enum_tmr == NULL) ++ return -ENOMEM; ++ ++ /* device driver used timers */ ++ b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0); ++ if (b_srp_wait_tmr == NULL) ++ return -ENOMEM; ++ ++ b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end, ++ TB_DATA_PLS, 0); ++ if (b_data_pulse_tmr == NULL) ++ return -ENOMEM; ++ ++ b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end, ++ TB_VBUS_PLS, 0); ++ if (b_vbus_pulse_tmr == NULL) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++/* Uninitialize timers */ ++void fsl_otg_uninit_timers(void) ++{ ++ /* FSM used timers */ ++ if (a_wait_vrise_tmr != NULL) ++ kfree(a_wait_vrise_tmr); ++ if (a_wait_bcon_tmr != NULL) ++ kfree(a_wait_bcon_tmr); ++ if (a_aidl_bdis_tmr != NULL) ++ kfree(a_aidl_bdis_tmr); ++ if (b_ase0_brst_tmr != NULL) ++ kfree(b_ase0_brst_tmr); ++ if (b_se0_srp_tmr != NULL) ++ kfree(b_se0_srp_tmr); ++ if (b_srp_fail_tmr != NULL) ++ kfree(b_srp_fail_tmr); ++ if (a_wait_enum_tmr != NULL) ++ kfree(a_wait_enum_tmr); ++ ++ /* device driver used timers */ ++ if (b_srp_wait_tmr != NULL) ++ kfree(b_srp_wait_tmr); ++ if (b_data_pulse_tmr != NULL) ++ kfree(b_data_pulse_tmr); ++ if (b_vbus_pulse_tmr != NULL) ++ kfree(b_vbus_pulse_tmr); ++} ++ ++/* Add timer to timer list */ ++void fsl_otg_add_timer(void *gtimer) ++{ ++ struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer; ++ struct fsl_otg_timer *tmp_timer; ++ ++ /* Check if the timer is already in the active list, ++ * if so update timer count ++ */ ++ list_for_each_entry(tmp_timer, &active_timers, list) ++ if (tmp_timer == timer) { ++ timer->count = timer->expires; ++ return; ++ } ++ timer->count = timer->expires; ++ list_add_tail(&timer->list, &active_timers); ++} ++ ++/* Remove timer from the timer list; clear timeout status */ ++void fsl_otg_del_timer(void *gtimer) ++{ ++ struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer; ++ struct fsl_otg_timer *tmp_timer, *del_tmp; ++ ++ list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) ++ if (tmp_timer == timer) ++ list_del(&timer->list); ++} ++ ++/* Reduce timer count by 1, and find timeout conditions. ++ * Called by fsl_otg 1ms timer interrupt ++ */ ++int fsl_otg_tick_timer(void) ++{ ++ struct fsl_otg_timer *tmp_timer, *del_tmp; ++ int expired = 0; ++ ++ list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) { ++ tmp_timer->count--; ++ /* check if timer expires */ ++ if (!tmp_timer->count) { ++ list_del(&tmp_timer->list); ++ tmp_timer->function(tmp_timer->data); ++ expired = 1; ++ } ++ } ++ ++ return expired; ++} ++ ++/* Reset controller, not reset the bus */ ++void otg_reset_controller(void) ++{ ++ u32 command; ++ ++ command = fsl_readl(&usb_dr_regs->usbcmd); ++ command |= (1 << 1); ++ fsl_writel(command, &usb_dr_regs->usbcmd); ++ while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1)) ++ ; ++} ++ ++/* Call suspend/resume routines in host driver */ ++int fsl_otg_start_host(struct otg_fsm *fsm, int on) ++{ ++ struct otg_transceiver *xceiv = fsm->transceiver; ++ struct device *dev; ++ struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg); ++ u32 retval = 0; ++ ++ if (!xceiv->host) ++ return -ENODEV; ++ dev = xceiv->host->controller; ++ ++ /* Update a_vbus_vld state as a_vbus_vld int is disabled ++ * in device mode ++ */ ++ fsm->a_vbus_vld = ++ !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID); ++ if (on) { ++ /* start fsl usb host controller */ ++ if (otg_dev->host_working) ++ goto end; ++ else { ++ otg_reset_controller(); ++ VDBG("host on......\n"); ++ if (dev->driver->resume) { ++ retval = dev->driver->resume(dev); ++ if (fsm->id) { ++ /* default-b */ ++ fsl_otg_drv_vbus(1); ++ /* Workaround: b_host can't driver ++ * vbus, but PP in PORTSC needs to ++ * be 1 for host to work. ++ * So we set drv_vbus bit in ++ * transceiver to 0 thru ULPI. */ ++ write_ulpi(0x0c, 0x20); ++ } ++ } ++ ++ otg_dev->host_working = 1; ++ } ++ } else { ++ /* stop fsl usb host controller */ ++ if (!otg_dev->host_working) ++ goto end; ++ else { ++ VDBG("host off......\n"); ++ if (dev && dev->driver) { ++ retval = dev->driver->suspend(dev, ++ otg_suspend_state); ++ if (fsm->id) ++ /* default-b */ ++ fsl_otg_drv_vbus(0); ++ } ++ otg_dev->host_working = 0; ++ } ++ } ++end: ++ return retval; ++} ++ ++/* Call suspend and resume function in udc driver ++ * to stop and start udc driver. ++ */ ++int fsl_otg_start_gadget(struct otg_fsm *fsm, int on) ++{ ++ struct otg_transceiver *xceiv = fsm->transceiver; ++ struct device *dev; ++ ++ if (!xceiv->gadget || !xceiv->gadget->dev.parent) ++ return -ENODEV; ++ ++ VDBG("gadget %s\n", on ? "on" : "off"); ++ dev = xceiv->gadget->dev.parent; ++ ++ if (on) ++ dev->driver->resume(dev); ++ else ++ dev->driver->suspend(dev, otg_suspend_state); ++ ++ return 0; ++} ++ ++/* Called by initialization code of host driver. Register host controller ++ * to the OTG. Suspend host for OTG role detection. ++ */ ++static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host) ++{ ++ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); ++ ++ if (!otg_p || otg_dev != fsl_otg_dev) ++ return -ENODEV; ++ ++ DBG("%s\n", __func__); ++ otg_p->host = host; ++ ++ otg_dev->fsm.a_bus_drop = 0; ++ otg_dev->fsm.a_bus_req = 1; ++ ++ if (host) { ++ VDBG("host off......\n"); ++ ++ otg_p->host->otg_port = fsl_otg_initdata.otg_port; ++ otg_p->host->is_b_host = otg_dev->fsm.id; ++ /* must leave time for khubd to finish its thing ++ * before yanking the host driver out from under it, ++ * so suspend the host after a short delay. ++ */ ++ otg_dev->host_working = 1; ++ schedule_delayed_work(&otg_dev->otg_event, 100); ++ return 0; ++ } else { /* host driver going away */ ++ ++ if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) & ++ OTGSC_STS_USB_ID)) { ++ /* Mini-A cable connected */ ++ struct otg_fsm *fsm = &otg_dev->fsm; ++ ++ otg_p->state = OTG_STATE_UNDEFINED; ++ fsm->protocol = PROTO_UNDEF; ++ } ++ } ++ ++ otg_dev->host_working = 0; ++ ++ otg_statemachine(&otg_dev->fsm); ++ ++ return 0; ++} ++ ++/* Called by initialization code of udc. Register udc to OTG.*/ ++static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p, ++ struct usb_gadget *gadget) ++{ ++ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); ++ ++ DBG("%s\n", __func__); ++ VDBG("otg_dev 0x%x\n", (int)otg_dev); ++ VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev); ++ ++ if (!otg_p || otg_dev != fsl_otg_dev) ++ return -ENODEV; ++ ++ if (!gadget) { ++ if (!otg_dev->otg.default_a) ++ otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0); ++ usb_gadget_vbus_disconnect(otg_dev->otg.gadget); ++ otg_dev->otg.gadget = 0; ++ otg_dev->fsm.b_bus_req = 0; ++ otg_statemachine(&otg_dev->fsm); ++ return 0; ++ } ++ ++ otg_p->gadget = gadget; ++ otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id; ++ ++ otg_dev->fsm.b_bus_req = 1; ++ ++ /* start the gadget right away if the ID pin says Mini-B */ ++ DBG("ID pin=%d\n", otg_dev->fsm.id); ++ if (otg_dev->fsm.id == 1) { ++ fsl_otg_start_host(&otg_dev->fsm, 0); ++ otg_drv_vbus(&otg_dev->fsm, 0); ++ fsl_otg_start_gadget(&otg_dev->fsm, 1); ++ } ++ ++ return 0; ++} ++ ++/* Set OTG port power, only for B-device */ ++static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA) ++{ ++ if (!fsl_otg_dev) ++ return -ENODEV; ++ if (otg_p->state == OTG_STATE_B_PERIPHERAL) ++ printk(KERN_INFO "FSL OTG:Draw %d mA\n", mA); ++ ++ return 0; ++} ++ ++/* Delayed pin detect interrupt processing. ++ * ++ * When the Mini-A cable is disconnected from the board, ++ * the pin-detect interrupt happens before the disconnnect ++ * interrupts for the connected device(s). In order to ++ * process the disconnect interrupt(s) prior to switching ++ * roles, the pin-detect interrupts are delayed, and handled ++ * by this routine. ++ */ ++static void fsl_otg_event(struct work_struct *work) ++{ ++ struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work); ++ struct otg_fsm *fsm = &og->fsm; ++ ++ if (fsm->id) { /* switch to gadget */ ++ fsl_otg_start_host(fsm, 0); ++ otg_drv_vbus(fsm, 0); ++ fsl_otg_start_gadget(fsm, 1); ++ } ++} ++ ++/* B-device start SRP */ ++static int fsl_otg_start_srp(struct otg_transceiver *otg_p) ++{ ++ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); ++ ++ if (!otg_p || otg_dev != fsl_otg_dev ++ || otg_p->state != OTG_STATE_B_IDLE) ++ return -ENODEV; ++ ++ otg_dev->fsm.b_bus_req = 1; ++ otg_statemachine(&otg_dev->fsm); ++ ++ return 0; ++} ++ ++/* A_host suspend will call this function to start hnp */ ++static int fsl_otg_start_hnp(struct otg_transceiver *otg_p) ++{ ++ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); ++ ++ if (!otg_p || otg_dev != fsl_otg_dev) ++ return -ENODEV; ++ ++ /* printk("start_hnp.............\n"); */ ++ /* clear a_bus_req to enter a_suspend state */ ++ otg_dev->fsm.a_bus_req = 0; ++ otg_statemachine(&otg_dev->fsm); ++ ++ return 0; ++} ++ ++/* Interrupt handler. OTG/host/peripheral share the same int line. ++ * OTG driver clears OTGSC interrupts and leaves USB interrupts ++ * intact. It needs to have knowledge of some USB interrupts ++ * such as port change. ++ */ ++irqreturn_t fsl_otg_isr(int irq, void *dev_id) ++{ ++ struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm; ++ struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg; ++ u32 otg_int_src, otg_sc; ++ ++ otg_sc = fsl_readl(&usb_dr_regs->otgsc); ++ otg_int_src = otg_sc & OTGSC_INTSTS_MASK; ++ ++ /* Only clear otg interrupts */ ++ fsl_writel(otg_sc, &usb_dr_regs->otgsc); ++ ++ /*FIXME: ID change not generate when init to 0 */ ++ fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; ++ otg->default_a = (fsm->id == 0); ++ ++ /* process OTG interrupts */ ++ if (otg_int_src) { ++ if (otg_int_src & OTGSC_INTSTS_USB_ID) { ++ fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; ++ otg->default_a = (fsm->id == 0); ++ /* clear conn information */ ++ if (fsm->id) ++ fsm->b_conn = 0; ++ else ++ fsm->a_conn = 0; ++ ++ if (otg->host) ++ otg->host->is_b_host = fsm->id; ++ if (otg->gadget) ++ otg->gadget->is_a_peripheral = !fsm->id; ++ VDBG("ID int (ID is %d)\n", fsm->id); ++ ++ if (fsm->id) { /* switch to gadget */ ++ schedule_delayed_work(&((struct fsl_otg *) ++ dev_id)->otg_event, 100); ++ } else { /* switch to host */ ++ cancel_delayed_work(& ++ ((struct fsl_otg *)dev_id)-> ++ otg_event); ++ fsl_otg_start_gadget(fsm, 0); ++ otg_drv_vbus(fsm, 1); ++ fsl_otg_start_host(fsm, 1); ++ } ++ return IRQ_HANDLED; ++ } ++ } ++ return IRQ_NONE; ++} ++ ++static struct otg_fsm_ops fsl_otg_ops = { ++ .chrg_vbus = fsl_otg_chrg_vbus, ++ .drv_vbus = fsl_otg_drv_vbus, ++ .loc_conn = fsl_otg_loc_conn, ++ .loc_sof = fsl_otg_loc_sof, ++ .start_pulse = fsl_otg_start_pulse, ++ ++ .add_timer = fsl_otg_add_timer, ++ .del_timer = fsl_otg_del_timer, ++ ++ .start_host = fsl_otg_start_host, ++ .start_gadget = fsl_otg_start_gadget, ++}; ++ ++/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */ ++static int fsl_otg_conf(struct platform_device *pdev) ++{ ++ int status; ++ struct fsl_otg *fsl_otg_tc; ++ struct fsl_usb2_platform_data *pdata; ++ ++ pdata = pdev->dev.platform_data; ++ ++ if (fsl_otg_dev) ++ return 0; ++ ++ /* allocate space to fsl otg device */ ++ fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL); ++ if (!fsl_otg_tc) ++ return -ENODEV; ++ ++ INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event); ++ ++ INIT_LIST_HEAD(&active_timers); ++ status = fsl_otg_init_timers(&fsl_otg_tc->fsm); ++ if (status) { ++ printk(KERN_INFO "Couldn't init OTG timers\n"); ++ fsl_otg_uninit_timers(); ++ kfree(fsl_otg_tc); ++ return status; ++ } ++ spin_lock_init(&fsl_otg_tc->fsm.lock); ++ ++ /* Set OTG state machine operations */ ++ fsl_otg_tc->fsm.ops = &fsl_otg_ops; ++ ++ /* initialize the otg structure */ ++ fsl_otg_tc->otg.label = DRIVER_DESC; ++ fsl_otg_tc->otg.set_host = fsl_otg_set_host; ++ fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral; ++ fsl_otg_tc->otg.set_power = fsl_otg_set_power; ++ fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp; ++ fsl_otg_tc->otg.start_srp = fsl_otg_start_srp; ++ ++ fsl_otg_dev = fsl_otg_tc; ++ ++ /* Store the otg transceiver */ ++ status = otg_set_transceiver(&fsl_otg_tc->otg); ++ if (status) { ++ printk(KERN_WARNING ": unable to register OTG transceiver.\n"); ++ return status; ++ } ++ ++ return 0; ++} ++ ++/* OTG Initialization*/ ++int usb_otg_start(struct platform_device *pdev) ++{ ++ struct fsl_otg __iomem *p_otg; ++ struct otg_transceiver *otg_trans = otg_get_transceiver(); ++ struct otg_fsm *fsm; ++ volatile unsigned long *p; ++ int status; ++ struct resource *res; ++ u32 temp; ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ ++ p_otg = container_of(otg_trans, struct fsl_otg, otg); ++ fsm = &p_otg->fsm; ++ ++ /* Initialize the state machine structure with default values */ ++ SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED); ++ fsm->transceiver = &p_otg->otg; ++ ++ /* We don't require predefined MEM/IRQ resource index */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENXIO; ++ ++ /* We don't request_mem_region here to enable resource sharing ++ * with host/device */ ++ ++ usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap)); ++ p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs; ++ pdata->regs = (void *)usb_dr_regs; ++ ++ /* request irq */ ++ p_otg->irq = platform_get_irq(pdev, 0); ++ status = request_irq(p_otg->irq, fsl_otg_isr, ++ IRQF_SHARED, driver_name, p_otg); ++ if (status) { ++ dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n", ++ p_otg->irq, status); ++ iounmap(p_otg->dr_mem_map); ++ kfree(p_otg); ++ return status; ++ } ++ ++ if (pdata->init && pdata->init(pdev) != 0) ++ return -EINVAL; ++ ++ ++ /* Export DR controller resources */ ++ otg_set_resources(pdev->resource); ++ ++ /* stop the controller */ ++ temp = fsl_readl(&p_otg->dr_mem_map->usbcmd); ++ temp &= ~USB_CMD_RUN_STOP; ++ fsl_writel(temp, &p_otg->dr_mem_map->usbcmd); ++ ++ /* reset the controller */ ++ temp = fsl_readl(&p_otg->dr_mem_map->usbcmd); ++ temp |= USB_CMD_CTRL_RESET; ++ fsl_writel(temp, &p_otg->dr_mem_map->usbcmd); ++ ++ /* wait reset completed */ ++ udelay(2); ++ while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET) ++ ; ++ ++ /* configure the VBUSHS as IDLE(both host and device) */ ++ temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0); ++ fsl_writel(temp, &p_otg->dr_mem_map->usbmode); ++ ++ /* configure PHY interface */ ++ temp = fsl_readl(&p_otg->dr_mem_map->portsc); ++ temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW); ++ switch (pdata->phy_mode) { ++ case FSL_USB2_PHY_ULPI: ++ temp |= PORTSC_PTS_ULPI; ++ break; ++ case FSL_USB2_PHY_UTMI_WIDE: ++ temp |= PORTSC_PTW_16BIT; ++ /* fall through */ ++ case FSL_USB2_PHY_UTMI: ++ temp |= PORTSC_PTS_UTMI; ++ /* fall through */ ++ default: ++ break; ++ } ++ fsl_writel(temp, &p_otg->dr_mem_map->portsc); ++ ++ if (pdata->have_sysif_regs) { ++ /* configure control enable IO output, big endian register */ ++ p = (volatile unsigned long *)(&p_otg->dr_mem_map->control); ++ temp = *p; ++ temp |= USB_CTRL_IOENB; ++ *p = temp; ++ } ++ ++ /* disable all interrupt and clear all OTGSC status */ ++ temp = fsl_readl(&p_otg->dr_mem_map->otgsc); ++ temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK; ++ temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE; ++ fsl_writel(temp, &p_otg->dr_mem_map->otgsc); ++ ++ ++ /* ++ * The identification (id) input is FALSE when a Mini-A plug is inserted ++ * in the devices Mini-AB receptacle. Otherwise, this input is TRUE. ++ * Also: record initial state of ID pin ++ */ ++ if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) { ++ p_otg->otg.state = OTG_STATE_UNDEFINED; ++ p_otg->fsm.id = 1; ++ } else { ++ p_otg->otg.state = OTG_STATE_A_IDLE; ++ p_otg->fsm.id = 0; ++ } ++ ++ DBG("initial ID pin=%d\n", p_otg->fsm.id); ++ ++ /* enable OTG ID pin interrupt */ ++ temp = fsl_readl(&p_otg->dr_mem_map->otgsc); ++ temp |= OTGSC_INTR_USB_ID_EN; ++ temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN); ++ fsl_writel(temp, &p_otg->dr_mem_map->otgsc); ++ ++ return 0; ++} ++ ++/*------------------------------------------------------------------------- ++ PROC File System Support ++-------------------------------------------------------------------------*/ ++#ifdef CONFIG_USB_OTG_DEBUG_FILES ++ ++#include <linux/seq_file.h> ++ ++static const char proc_filename[] = "driver/fsl_usb2_otg"; ++ ++static int otg_proc_read(char *page, char **start, off_t off, int count, ++ int *eof, void *_dev) ++{ ++ struct otg_fsm *fsm = &fsl_otg_dev->fsm; ++ char *buf = page; ++ char *next = buf; ++ unsigned size = count; ++ unsigned long flags; ++ int t; ++ u32 tmp_reg; ++ ++ if (off != 0) ++ return 0; ++ ++ spin_lock_irqsave(&fsm->lock, flags); ++ ++ /* ------basic driver infomation ---- */ ++ t = scnprintf(next, size, ++ DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n", ++ DRIVER_VERSION); ++ size -= t; ++ next += t; ++ ++ /* ------ Registers ----- */ ++ tmp_reg = fsl_readl(&usb_dr_regs->otgsc); ++ t = scnprintf(next, size, "OTGSC reg: %08x\n", tmp_reg); ++ size -= t; ++ next += t; ++ ++ tmp_reg = fsl_readl(&usb_dr_regs->portsc); ++ t = scnprintf(next, size, "PORTSC reg: %08x\n", tmp_reg); ++ size -= t; ++ next += t; ++ ++ tmp_reg = fsl_readl(&usb_dr_regs->usbmode); ++ t = scnprintf(next, size, "USBMODE reg: %08x\n", tmp_reg); ++ size -= t; ++ next += t; ++ ++ tmp_reg = fsl_readl(&usb_dr_regs->usbcmd); ++ t = scnprintf(next, size, "USBCMD reg: %08x\n", tmp_reg); ++ size -= t; ++ next += t; ++ ++ tmp_reg = fsl_readl(&usb_dr_regs->usbsts); ++ t = scnprintf(next, size, "USBSTS reg: %08x\n", tmp_reg); ++ size -= t; ++ next += t; ++ ++ tmp_reg = fsl_readl(&usb_dr_regs->usbintr); ++ t = scnprintf(next, size, "USBINTR reg: %08x\n", tmp_reg); ++ size -= t; ++ next += t; ++ ++ /* ------ State ----- */ ++ t = scnprintf(next, size, ++ "OTG state: %s\n\n", ++ state_string(fsl_otg_dev->otg.state)); ++ size -= t; ++ next += t; ++ ++ /* ------ State Machine Variables ----- */ ++ t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld); ++ size -= t; ++ next += t; ++ ++ t = scnprintf(next, size, "id: %d\n", fsm->id); ++ size -= t; ++ next += t; ++ ++ spin_unlock_irqrestore(&fsm->lock, flags); ++ ++ *eof = 1; ++ return count - size; ++} ++ ++#define create_proc_file() create_proc_read_entry(proc_filename, \ ++ 0, NULL, otg_proc_read, NULL) ++ ++#define remove_proc_file() remove_proc_entry(proc_filename, NULL) ++ ++#else /* !CONFIG_USB_OTG_DEBUG_FILES */ ++ ++#define create_proc_file() do {} while (0) ++#define remove_proc_file() do {} while (0) ++ ++#endif /*CONFIG_USB_OTG_DEBUG_FILES */ ++ ++/*----------------------------------------------------------*/ ++/* Char driver interface to control some OTG input */ ++ ++/* This function handle some ioctl command,such as get otg ++ * status and set host suspend ++ */ ++static long fsl_otg_ioctl(struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ u32 retval = 0; ++ ++ switch (cmd) { ++ case GET_OTG_STATUS: ++ retval = fsl_otg_dev->host_working; ++ break; ++ ++ case SET_A_SUSPEND_REQ: ++ fsl_otg_dev->fsm.a_suspend_req = arg; ++ break; ++ ++ case SET_A_BUS_DROP: ++ fsl_otg_dev->fsm.a_bus_drop = arg; ++ break; ++ ++ case SET_A_BUS_REQ: ++ fsl_otg_dev->fsm.a_bus_req = arg; ++ break; ++ ++ case SET_B_BUS_REQ: ++ fsl_otg_dev->fsm.b_bus_req = arg; ++ break; ++ ++ default: ++ break; ++ } ++ ++ otg_statemachine(&fsl_otg_dev->fsm); ++ ++ return retval; ++} ++ ++static int fsl_otg_open(struct inode *inode, struct file *file) ++{ ++ ++ return 0; ++} ++ ++static int fsl_otg_release(struct inode *inode, struct file *file) ++{ ++ ++ return 0; ++} ++ ++static struct file_operations otg_fops = { ++ .owner = THIS_MODULE, ++ .llseek = NULL, ++ .read = NULL, ++ .write = NULL, ++ .unlocked_ioctl = fsl_otg_ioctl, ++ .open = fsl_otg_open, ++ .release = fsl_otg_release, ++}; ++ ++static int __init fsl_otg_probe(struct platform_device *pdev) ++{ ++ int status; ++ struct fsl_usb2_platform_data *pdata; ++ ++ DBG("pdev=0x%p\n", pdev); ++ ++ if (!pdev) ++ return -ENODEV; ++ ++ if (!pdev->dev.platform_data) ++ return -ENOMEM; ++ ++ pdata = pdev->dev.platform_data; ++ fsl_set_usb_accessors(pdata); ++ ++ /* configure the OTG */ ++ status = fsl_otg_conf(pdev); ++ if (status) { ++ printk(KERN_INFO "Couldn't init OTG module\n"); ++ return -status; ++ } ++ ++ /* start OTG */ ++ status = usb_otg_start(pdev); ++ ++ if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) { ++ printk(KERN_WARNING FSL_OTG_NAME ++ ": unable to register FSL OTG device\n"); ++ return -EIO; ++ } ++ ++ create_proc_file(); ++ return status; ++} ++ ++static int __exit fsl_otg_remove(struct platform_device *pdev) ++{ ++ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; ++ ++ otg_set_transceiver(NULL); ++ free_irq(fsl_otg_dev->irq, fsl_otg_dev); ++ ++ iounmap((void *)usb_dr_regs); ++ ++ kfree(fsl_otg_dev); ++ ++ remove_proc_file(); ++ ++ unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME); ++ ++ if (pdata->exit) ++ pdata->exit(pdev); ++ ++ return 0; ++} ++ ++struct platform_driver fsl_otg_driver = { ++ .probe = fsl_otg_probe, ++ .remove = __exit_p(fsl_otg_remove), ++ .driver = { ++ .name = driver_name, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int __init fsl_usb_otg_init(void) ++{ ++ printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION); ++ return platform_driver_register(&fsl_otg_driver); ++} ++ ++static void __exit fsl_usb_otg_exit(void) ++{ ++ platform_driver_unregister(&fsl_otg_driver); ++ printk(KERN_INFO DRIVER_DESC " unloaded\n"); ++} ++ ++module_init(fsl_usb_otg_init); ++module_exit(fsl_usb_otg_exit); ++ ++MODULE_DESCRIPTION(DRIVER_INFO); ++MODULE_AUTHOR(DRIVER_AUTHOR); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/usb/otg/fsl_otg.h +@@ -0,0 +1,423 @@ ++/* Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include "otg_fsm.h" ++#include <linux/usb/otg.h> ++#include <linux/ioctl.h> ++ ++#ifdef CONFIG_PPC32 ++#include <asm/fsl_usb_io.h> ++#elif CONFIG_COLDFIRE ++#include <asm/mcfsim.h> ++#include <asm/fsl_usb_io.h> ++#endif ++ ++#define hc32_to_cpu(x) (x) ++#define cpu_to_hc32(x) (x) ++ ++ /* USB Command Register Bit Masks */ ++#define USB_CMD_RUN_STOP (0x1<<0) ++#define USB_CMD_CTRL_RESET (0x1<<1) ++#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4) ++#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5) ++#define USB_CMD_INT_AA_DOORBELL (0x1<<6) ++#define USB_CMD_ASP (0x3<<8) ++#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11) ++#define USB_CMD_SUTW (0x1<<13) ++#define USB_CMD_ATDTW (0x1<<14) ++#define USB_CMD_ITC (0xFF<<16) ++ ++/* bit 15,3,2 are frame list size */ ++#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2) ++#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) ++#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2) ++#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) ++#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2) ++#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2) ++#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2) ++#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) ++ ++/* bit 9-8 are async schedule park mode count */ ++#define USB_CMD_ASP_00 (0x0<<8) ++#define USB_CMD_ASP_01 (0x1<<8) ++#define USB_CMD_ASP_10 (0x2<<8) ++#define USB_CMD_ASP_11 (0x3<<8) ++#define USB_CMD_ASP_BIT_POS (8) ++ ++/* bit 23-16 are interrupt threshold control */ ++#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16) ++#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16) ++#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16) ++#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16) ++#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16) ++#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16) ++#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16) ++#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16) ++#define USB_CMD_ITC_BIT_POS (16) ++ ++/* USB Status Register Bit Masks */ ++#define USB_STS_INT (0x1<<0) ++#define USB_STS_ERR (0x1<<1) ++#define USB_STS_PORT_CHANGE (0x1<<2) ++#define USB_STS_FRM_LST_ROLL (0x1<<3) ++#define USB_STS_SYS_ERR (0x1<<4) ++#define USB_STS_IAA (0x1<<5) ++#define USB_STS_RESET_RECEIVED (0x1<<6) ++#define USB_STS_SOF (0x1<<7) ++#define USB_STS_DCSUSPEND (0x1<<8) ++#define USB_STS_HC_HALTED (0x1<<12) ++#define USB_STS_RCL (0x1<<13) ++#define USB_STS_PERIODIC_SCHEDULE (0x1<<14) ++#define USB_STS_ASYNC_SCHEDULE (0x1<<15) ++ ++/* USB Interrupt Enable Register Bit Masks */ ++#define USB_INTR_INT_EN (0x1<<0) ++#define USB_INTR_ERR_INT_EN (0x1<<1) ++#define USB_INTR_PC_DETECT_EN (0x1<<2) ++#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3) ++#define USB_INTR_SYS_ERR_EN (0x1<<4) ++#define USB_INTR_ASYN_ADV_EN (0x1<<5) ++#define USB_INTR_RESET_EN (0x1<<6) ++#define USB_INTR_SOF_EN (0x1<<7) ++#define USB_INTR_DEVICE_SUSPEND (0x1<<8) ++ ++/* Device Address bit masks */ ++#define USB_DEVICE_ADDRESS_MASK (0x7F<<25) ++#define USB_DEVICE_ADDRESS_BIT_POS (25) ++/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/ ++#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0) ++#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1) ++#define PORTSC_PORT_ENABLE (0x1<<2) ++#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3) ++#define PORTSC_OVER_CURRENT_ACT (0x1<<4) ++#define PORTSC_OVER_CUURENT_CHG (0x1<<5) ++#define PORTSC_PORT_FORCE_RESUME (0x1<<6) ++#define PORTSC_PORT_SUSPEND (0x1<<7) ++#define PORTSC_PORT_RESET (0x1<<8) ++#define PORTSC_LINE_STATUS_BITS (0x3<<10) ++#define PORTSC_PORT_POWER (0x1<<12) ++#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14) ++#define PORTSC_PORT_TEST_CTRL (0xF<<16) ++#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20) ++#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21) ++#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22) ++#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23) ++#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24) ++#define PORTSC_PORT_SPEED_MASK (0x3<<26) ++#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28) ++#define PORTSC_PHY_TYPE_SEL (0x3<<30) ++/* bit 11-10 are line status */ ++#define PORTSC_LINE_STATUS_SE0 (0x0<<10) ++#define PORTSC_LINE_STATUS_JSTATE (0x1<<10) ++#define PORTSC_LINE_STATUS_KSTATE (0x2<<10) ++#define PORTSC_LINE_STATUS_UNDEF (0x3<<10) ++#define PORTSC_LINE_STATUS_BIT_POS (10) ++ ++/* bit 15-14 are port indicator control */ ++#define PORTSC_PIC_OFF (0x0<<14) ++#define PORTSC_PIC_AMBER (0x1<<14) ++#define PORTSC_PIC_GREEN (0x2<<14) ++#define PORTSC_PIC_UNDEF (0x3<<14) ++#define PORTSC_PIC_BIT_POS (14) ++ ++/* bit 19-16 are port test control */ ++#define PORTSC_PTC_DISABLE (0x0<<16) ++#define PORTSC_PTC_JSTATE (0x1<<16) ++#define PORTSC_PTC_KSTATE (0x2<<16) ++#define PORTSC_PTC_SEQNAK (0x3<<16) ++#define PORTSC_PTC_PACKET (0x4<<16) ++#define PORTSC_PTC_FORCE_EN (0x5<<16) ++#define PORTSC_PTC_BIT_POS (16) ++ ++/* bit 27-26 are port speed */ ++#define PORTSC_PORT_SPEED_FULL (0x0<<26) ++#define PORTSC_PORT_SPEED_LOW (0x1<<26) ++#define PORTSC_PORT_SPEED_HIGH (0x2<<26) ++#define PORTSC_PORT_SPEED_UNDEF (0x3<<26) ++#define PORTSC_SPEED_BIT_POS (26) ++ ++/* bit 28 is parallel transceiver width for UTMI interface */ ++#define PORTSC_PTW (0x1<<28) ++#define PORTSC_PTW_8BIT (0x0<<28) ++#define PORTSC_PTW_16BIT (0x1<<28) ++ ++/* bit 31-30 are port transceiver select */ ++#define PORTSC_PTS_UTMI (0x0<<30) ++#define PORTSC_PTS_ULPI (0x2<<30) ++#define PORTSC_PTS_FSLS_SERIAL (0x3<<30) ++#define PORTSC_PTS_BIT_POS (30) ++ ++#define PORTSC_W1C_BITS \ ++ (PORTSC_CONNECT_STATUS_CHANGE | \ ++ PORTSC_PORT_EN_DIS_CHANGE | \ ++ PORTSC_OVER_CUURENT_CHG) ++ ++/* OTG Status Control Register Bit Masks */ ++#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0) ++#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1) ++#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3) ++#define OTGSC_CTRL_DATA_PULSING (0x1<<4) ++#define OTGSC_CTRL_ID_PULL_EN (0x1<<5) ++#define OTGSC_HA_DATA_PULSE (0x1<<6) ++#define OTGSC_HA_BA (0x1<<7) ++#define OTGSC_STS_USB_ID (0x1<<8) ++#define OTGSC_STS_A_VBUS_VALID (0x1<<9) ++#define OTGSC_STS_A_SESSION_VALID (0x1<<10) ++#define OTGSC_STS_B_SESSION_VALID (0x1<<11) ++#define OTGSC_STS_B_SESSION_END (0x1<<12) ++#define OTGSC_STS_1MS_TOGGLE (0x1<<13) ++#define OTGSC_STS_DATA_PULSING (0x1<<14) ++#define OTGSC_INTSTS_USB_ID (0x1<<16) ++#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17) ++#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18) ++#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19) ++#define OTGSC_INTSTS_B_SESSION_END (0x1<<20) ++#define OTGSC_INTSTS_1MS (0x1<<21) ++#define OTGSC_INTSTS_DATA_PULSING (0x1<<22) ++#define OTGSC_INTR_USB_ID_EN (0x1<<24) ++#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25) ++#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26) ++#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27) ++#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28) ++#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29) ++#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30) ++#define OTGSC_INTSTS_MASK (0x00ff0000) ++ ++/* USB MODE Register Bit Masks */ ++#define USB_MODE_CTRL_MODE_IDLE (0x0<<0) ++#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0) ++#define USB_MODE_CTRL_MODE_HOST (0x3<<0) ++#define USB_MODE_CTRL_MODE_RSV (0x1<<0) ++#define USB_MODE_SETUP_LOCK_OFF (0x1<<3) ++#define USB_MODE_STREAM_DISABLE (0x1<<4) ++#define USB_MODE_ES (0x1<<2) /* (big) Endian Select */ ++ ++#define MPC8349_OTG_IRQ (38) ++#define CFG_IMMR_BASE (0xfe000000) ++#define MPC83xx_USB_DR_BASE (CFG_IMMR_BASE + 0x23000) ++ ++/* control Register Bit Masks */ ++#define USB_CTRL_IOENB (0x1<<2) ++#define USB_CTRL_ULPI_INT0EN (0x1<<0) ++ ++/* BCSR5 */ ++#define BCSR5_INT_USB (0x02) ++ ++/* USB module clk cfg */ ++#define SCCR_OFFS (0xA08) ++#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */ ++#define SCCR_USB_MPHCM_11 (0x00c00000) ++#define SCCR_USB_MPHCM_01 (0x00400000) ++#define SCCR_USB_MPHCM_10 (0x00800000) ++#define SCCR_USB_DRCM_11 (0x00300000) ++#define SCCR_USB_DRCM_01 (0x00100000) ++#define SCCR_USB_DRCM_10 (0x00200000) ++ ++#define SICRL_OFFS (0x114) ++#define SICRL_USB0 (0x40000000) ++#define SICRL_USB1 (0x20000000) ++ ++#define SICRH_OFFS (0x118) ++#define SICRH_USB_UTMI (0x00020000) ++ ++/* OTG interrupt enable bit masks */ ++#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \ ++ (OTGSC_INTR_USB_ID_EN | \ ++ OTGSC_INTR_1MS_TIMER_EN | \ ++ OTGSC_INTR_A_VBUS_VALID_EN | \ ++ OTGSC_INTR_A_SESSION_VALID_EN | \ ++ OTGSC_INTR_B_SESSION_VALID_EN | \ ++ OTGSC_INTR_B_SESSION_END_EN | \ ++ OTGSC_INTR_DATA_PULSING_EN) ++ ++/* OTG interrupt status bit masks */ ++#define OTGSC_INTERRUPT_STATUS_BITS_MASK \ ++ (OTGSC_INTSTS_USB_ID | \ ++ OTGSC_INTR_1MS_TIMER_EN | \ ++ OTGSC_INTSTS_A_VBUS_VALID | \ ++ OTGSC_INTSTS_A_SESSION_VALID | \ ++ OTGSC_INTSTS_B_SESSION_VALID | \ ++ OTGSC_INTSTS_B_SESSION_END | \ ++ OTGSC_INTSTS_DATA_PULSING) ++ ++/* ++ * A-DEVICE timing constants ++ */ ++ ++/* Wait for VBUS Rise */ ++#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */ ++ ++/* Wait for B-Connect */ ++#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2 ++ * This is only used to get out of ++ * OTG_STATE_A_WAIT_BCON state if there was ++ * no connection for these many milliseconds ++ */ ++ ++/* A-Idle to B-Disconnect */ ++/* It is necessary for this timer to be more than 750 ms because of a bug in OPT ++ * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated ++ * in the test description ++ */ ++#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */ ++ ++/* B-Idle to A-Disconnect */ ++#define TA_BIDL_ADIS (12) /* 3 to 200 ms */ ++ ++/* B-device timing constants */ ++ ++ ++/* Data-Line Pulse Time*/ ++#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */ ++#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */ ++#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */ ++ ++/* SRP Initiate Time */ ++#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */ ++ ++/* SRP Fail Time */ ++#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/ ++ ++/* SRP result wait time */ ++#define TB_SRP_WAIT (60) ++ ++/* VBus time */ ++#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */ ++ ++/* Discharge time */ ++/* This time should be less than 10ms. It varies from system to system. */ ++#define TB_VBUS_DSCHRG (8) ++ ++/* A-SE0 to B-Reset */ ++#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */ ++ ++/* A bus suspend timer before we can switch to b_wait_aconn */ ++#define TB_A_SUSPEND (7) ++#define TB_BUS_RESUME (12) ++ ++/* SE0 Time Before SRP */ ++#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */ ++ ++ ++#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate) ++ ++struct usb_dr_mmap { ++ /* Capability register */ ++ u8 res1[256]; ++ u16 caplength; /* Capability Register Length */ ++ u16 hciversion; /* Host Controller Interface Version */ ++ u32 hcsparams; /* Host Controller Structual Parameters */ ++ u32 hccparams; /* Host Controller Capability Parameters */ ++ u8 res2[20]; ++ u32 dciversion; /* Device Controller Interface Version */ ++ u32 dccparams; /* Device Controller Capability Parameters */ ++ u8 res3[24]; ++ /* Operation register */ ++ u32 usbcmd; /* USB Command Register */ ++ u32 usbsts; /* USB Status Register */ ++ u32 usbintr; /* USB Interrupt Enable Register */ ++ u32 frindex; /* Frame Index Register */ ++ u8 res4[4]; ++ u32 deviceaddr; /* Device Address */ ++ u32 endpointlistaddr; /* Endpoint List Address Register */ ++ u8 res5[4]; ++ u32 burstsize; /* Master Interface Data Burst Size Register */ ++ u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ ++ u8 res6[8]; ++ u32 ulpiview; /* ULPI register access */ ++ u8 res7[12]; ++ u32 configflag; /* Configure Flag Register */ ++ u32 portsc; /* Port 1 Status and Control Register */ ++ u8 res8[28]; ++ u32 otgsc; /* On-The-Go Status and Control */ ++ u32 usbmode; /* USB Mode Register */ ++ u32 endptsetupstat; /* Endpoint Setup Status Register */ ++ u32 endpointprime; /* Endpoint Initialization Register */ ++ u32 endptflush; /* Endpoint Flush Register */ ++ u32 endptstatus; /* Endpoint Status Register */ ++ u32 endptcomplete; /* Endpoint Complete Register */ ++ u32 endptctrl[6]; /* Endpoint Control Registers */ ++ u8 res9[552]; ++ u32 snoop1; ++ u32 snoop2; ++ u32 age_cnt_thresh; /* Age Count Threshold Register */ ++ u32 pri_ctrl; /* Priority Control Register */ ++ u32 si_ctrl; /* System Interface Control Register */ ++ u8 res10[236]; ++ u32 control; /* General Purpose Control Register */ ++}; ++ ++ ++struct fsl_otg_timer { ++ unsigned long expires; /* Number of count increase to timeout */ ++ unsigned long count; /* Tick counter */ ++ void (*function)(unsigned long); /* Timeout function */ ++ unsigned long data; /* Data passed to function */ ++ struct list_head list; ++}; ++ ++static inline struct fsl_otg_timer *otg_timer_initializer ++(void (*function)(unsigned long), unsigned long expires, unsigned long data) ++{ ++ struct fsl_otg_timer *timer; ++ timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL); ++ if (timer == NULL) ++ return NULL; ++ timer->function = function; ++ timer->expires = expires; ++ timer->data = data; ++ return timer; ++} ++ ++struct fsl_otg { ++ struct otg_transceiver otg; ++ struct otg_fsm fsm; ++ struct usb_dr_mmap __iomem *dr_mem_map; ++ struct delayed_work otg_event; ++ ++ /* used for usb host */ ++ struct work_struct work_wq; ++ u8 host_working; ++ ++ int irq; ++}; ++ ++struct fsl_otg_config { ++ u8 otg_port; ++}; ++ ++/*For SRP and HNP handle*/ ++#define FSL_OTG_MAJOR 66 ++#define FSL_OTG_NAME "fsl-usb2-otg" ++/*Command to OTG driver(ioctl)*/ ++#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR ++/*if otg work as host,it should return 1,otherwise it return 0*/ ++#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int) ++#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int) ++#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int) ++#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int) ++#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int) ++#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int) ++#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int) ++#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int) ++#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int) ++ ++extern const char *state_string(enum usb_otg_state state); ++extern int otg_set_resources(struct resource *resources); ++/* prototype declaration */ ++extern void fsl_otg_add_timer(void *timer); ++extern void fsl_otg_del_timer(void *timer); +--- /dev/null ++++ b/drivers/usb/otg/otg_fsm.c +@@ -0,0 +1,371 @@ ++/* OTG Finite State Machine from OTG spec ++ * ++ * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: Li Yang <LeoLi@freescale.com> ++ * Jerry Huang <Chang-Ming.Huang@freescale.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/usb/otg.h> ++#include <linux/spinlock.h> ++#include <linux/delay.h> ++#include <linux/usb.h> ++#include <linux/usb/gadget.h> ++ ++#include <linux/types.h> ++#include "otg_fsm.h" ++ ++ ++/* Defined by device specific driver, for different timer implementation */ ++extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, ++ *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr; ++ ++const char *state_string(enum usb_otg_state state) ++{ ++ switch (state) { ++ case OTG_STATE_A_IDLE: return "a_idle"; ++ case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; ++ case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; ++ case OTG_STATE_A_HOST: return "a_host"; ++ case OTG_STATE_A_SUSPEND: return "a_suspend"; ++ case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; ++ case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; ++ case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; ++ case OTG_STATE_B_IDLE: return "b_idle"; ++ case OTG_STATE_B_SRP_INIT: return "b_srp_init"; ++ case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; ++ case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; ++ case OTG_STATE_B_HOST: return "b_host"; ++ default: return "UNDEFINED"; ++ } ++} ++ ++/* Change USB protocol when there is a protocol change */ ++static int otg_set_protocol(struct otg_fsm *fsm, int protocol) ++{ ++ int ret = 0; ++ ++ if (fsm->protocol != protocol) { ++ VDBG("Changing role fsm->protocol= %d; new protocol= %d\n", ++ fsm->protocol, protocol); ++ /* stop old protocol */ ++ if (fsm->protocol == PROTO_HOST) ++ ret = fsm->ops->start_host(fsm, 0); ++ else if (fsm->protocol == PROTO_GADGET) ++ ret = fsm->ops->start_gadget(fsm, 0); ++ if (ret) ++ return ret; ++ ++ /* start new protocol */ ++ if (protocol == PROTO_HOST) ++ ret = fsm->ops->start_host(fsm, 1); ++ else if (protocol == PROTO_GADGET) ++ ret = fsm->ops->start_gadget(fsm, 1); ++ if (ret) ++ return ret; ++ ++ fsm->protocol = protocol; ++ return 0; ++ } ++ ++ return 0; ++} ++ ++static int state_changed; ++ ++/* Called when leaving a state. Do state clean up jobs here */ ++void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state) ++{ ++ switch (old_state) { ++ case OTG_STATE_B_IDLE: ++ otg_del_timer(fsm, b_se0_srp_tmr); ++ fsm->b_se0_srp = 0; ++ break; ++ case OTG_STATE_B_SRP_INIT: ++ fsm->b_srp_done = 0; ++ break; ++ case OTG_STATE_B_PERIPHERAL: ++ break; ++ case OTG_STATE_B_WAIT_ACON: ++ otg_del_timer(fsm, b_ase0_brst_tmr); ++ fsm->b_ase0_brst_tmout = 0; ++ break; ++ case OTG_STATE_B_HOST: ++ break; ++ case OTG_STATE_A_IDLE: ++ break; ++ case OTG_STATE_A_WAIT_VRISE: ++ otg_del_timer(fsm, a_wait_vrise_tmr); ++ fsm->a_wait_vrise_tmout = 0; ++ break; ++ case OTG_STATE_A_WAIT_BCON: ++ otg_del_timer(fsm, a_wait_bcon_tmr); ++ fsm->a_wait_bcon_tmout = 0; ++ break; ++ case OTG_STATE_A_HOST: ++ otg_del_timer(fsm, a_wait_enum_tmr); ++ break; ++ case OTG_STATE_A_SUSPEND: ++ otg_del_timer(fsm, a_aidl_bdis_tmr); ++ fsm->a_aidl_bdis_tmout = 0; ++ fsm->a_suspend_req = 0; ++ break; ++ case OTG_STATE_A_PERIPHERAL: ++ break; ++ case OTG_STATE_A_WAIT_VFALL: ++ otg_del_timer(fsm, a_wait_vrise_tmr); ++ break; ++ case OTG_STATE_A_VBUS_ERR: ++ break; ++ default: ++ break; ++ } ++} ++ ++/* Called when entering a state */ ++int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state) ++{ ++ state_changed = 1; ++ if (fsm->transceiver->state == new_state) ++ return 0; ++ VDBG("Set state: %s\n", state_string(new_state)); ++ otg_leave_state(fsm, fsm->transceiver->state); ++ switch (new_state) { ++ case OTG_STATE_B_IDLE: ++ otg_drv_vbus(fsm, 0); ++ otg_chrg_vbus(fsm, 0); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_UNDEF); ++ otg_add_timer(fsm, b_se0_srp_tmr); ++ break; ++ case OTG_STATE_B_SRP_INIT: ++ otg_start_pulse(fsm); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_UNDEF); ++ otg_add_timer(fsm, b_srp_fail_tmr); ++ break; ++ case OTG_STATE_B_PERIPHERAL: ++ otg_chrg_vbus(fsm, 0); ++ otg_loc_conn(fsm, 1); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_GADGET); ++ break; ++ case OTG_STATE_B_WAIT_ACON: ++ otg_chrg_vbus(fsm, 0); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_HOST); ++ otg_add_timer(fsm, b_ase0_brst_tmr); ++ fsm->a_bus_suspend = 0; ++ break; ++ case OTG_STATE_B_HOST: ++ otg_chrg_vbus(fsm, 0); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 1); ++ otg_set_protocol(fsm, PROTO_HOST); ++ usb_bus_start_enum(fsm->transceiver->host, ++ fsm->transceiver->host->otg_port); ++ break; ++ case OTG_STATE_A_IDLE: ++ otg_drv_vbus(fsm, 0); ++ otg_chrg_vbus(fsm, 0); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_HOST); ++ break; ++ case OTG_STATE_A_WAIT_VRISE: ++ otg_drv_vbus(fsm, 1); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_HOST); ++ otg_add_timer(fsm, a_wait_vrise_tmr); ++ break; ++ case OTG_STATE_A_WAIT_BCON: ++ otg_drv_vbus(fsm, 1); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_HOST); ++ otg_add_timer(fsm, a_wait_bcon_tmr); ++ break; ++ case OTG_STATE_A_HOST: ++ otg_drv_vbus(fsm, 1); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 1); ++ otg_set_protocol(fsm, PROTO_HOST); ++ /* When HNP is triggered while a_bus_req = 0, a_host will ++ * suspend too fast to complete a_set_b_hnp_en */ ++ if (!fsm->a_bus_req || fsm->a_suspend_req) ++ otg_add_timer(fsm, a_wait_enum_tmr); ++ break; ++ case OTG_STATE_A_SUSPEND: ++ otg_drv_vbus(fsm, 1); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_HOST); ++ otg_add_timer(fsm, a_aidl_bdis_tmr); ++ ++ break; ++ case OTG_STATE_A_PERIPHERAL: ++ otg_loc_conn(fsm, 1); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_GADGET); ++ otg_drv_vbus(fsm, 1); ++ break; ++ case OTG_STATE_A_WAIT_VFALL: ++ otg_drv_vbus(fsm, 0); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_HOST); ++ break; ++ case OTG_STATE_A_VBUS_ERR: ++ otg_drv_vbus(fsm, 0); ++ otg_loc_conn(fsm, 0); ++ otg_loc_sof(fsm, 0); ++ otg_set_protocol(fsm, PROTO_UNDEF); ++ break; ++ default: ++ break; ++ } ++ ++ fsm->transceiver->state = new_state; ++ return 0; ++} ++ ++/* State change judgement */ ++int otg_statemachine(struct otg_fsm *fsm) ++{ ++ enum usb_otg_state state; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&fsm->lock, flags); ++ ++ state = fsm->transceiver->state; ++ state_changed = 0; ++ /* State machine state change judgement */ ++ ++ switch (state) { ++ case OTG_STATE_UNDEFINED: ++ VDBG("fsm->id = %d\n", fsm->id); ++ if (fsm->id) ++ otg_set_state(fsm, OTG_STATE_B_IDLE); ++ else ++ otg_set_state(fsm, OTG_STATE_A_IDLE); ++ break; ++ case OTG_STATE_B_IDLE: ++ if (!fsm->id) ++ otg_set_state(fsm, OTG_STATE_A_IDLE); ++ else if (fsm->b_sess_vld && fsm->transceiver->gadget) ++ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); ++ else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp) ++ otg_set_state(fsm, OTG_STATE_B_SRP_INIT); ++ break; ++ case OTG_STATE_B_SRP_INIT: ++ if (!fsm->id || fsm->b_srp_done) ++ otg_set_state(fsm, OTG_STATE_B_IDLE); ++ break; ++ case OTG_STATE_B_PERIPHERAL: ++ if (!fsm->id || !fsm->b_sess_vld) ++ otg_set_state(fsm, OTG_STATE_B_IDLE); ++ else if (fsm->b_bus_req && fsm->transceiver-> ++ gadget->b_hnp_enable && fsm->a_bus_suspend) ++ otg_set_state(fsm, OTG_STATE_B_WAIT_ACON); ++ break; ++ case OTG_STATE_B_WAIT_ACON: ++ if (fsm->a_conn) ++ otg_set_state(fsm, OTG_STATE_B_HOST); ++ else if (!fsm->id || !fsm->b_sess_vld) ++ otg_set_state(fsm, OTG_STATE_B_IDLE); ++ else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) { ++ fsm->b_ase0_brst_tmout = 0; ++ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); ++ } ++ break; ++ case OTG_STATE_B_HOST: ++ if (!fsm->id || !fsm->b_sess_vld) ++ otg_set_state(fsm, OTG_STATE_B_IDLE); ++ else if (!fsm->b_bus_req || !fsm->a_conn) ++ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); ++ break; ++ case OTG_STATE_A_IDLE: ++ if (fsm->id) ++ otg_set_state(fsm, OTG_STATE_B_IDLE); ++ else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det)) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE); ++ break; ++ case OTG_STATE_A_WAIT_VRISE: ++ if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld || ++ fsm->a_wait_vrise_tmout) { ++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); ++ } ++ break; ++ case OTG_STATE_A_WAIT_BCON: ++ if (!fsm->a_vbus_vld) ++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); ++ else if (fsm->b_conn) ++ otg_set_state(fsm, OTG_STATE_A_HOST); ++ else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); ++ break; ++ case OTG_STATE_A_HOST: ++ if ((!fsm->a_bus_req || fsm->a_suspend_req) && ++ fsm->transceiver->host->b_hnp_enable) ++ otg_set_state(fsm, OTG_STATE_A_SUSPEND); ++ else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); ++ else if (!fsm->a_vbus_vld) ++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); ++ break; ++ case OTG_STATE_A_SUSPEND: ++ if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable) ++ otg_set_state(fsm, OTG_STATE_A_PERIPHERAL); ++ else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); ++ else if (fsm->a_bus_req || fsm->b_bus_resume) ++ otg_set_state(fsm, OTG_STATE_A_HOST); ++ else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); ++ else if (!fsm->a_vbus_vld) ++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); ++ break; ++ case OTG_STATE_A_PERIPHERAL: ++ if (fsm->id || fsm->a_bus_drop) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); ++ else if (fsm->b_bus_suspend) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); ++ else if (!fsm->a_vbus_vld) ++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); ++ break; ++ case OTG_STATE_A_WAIT_VFALL: ++ if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld && ++ !fsm->b_conn)) ++ otg_set_state(fsm, OTG_STATE_A_IDLE); ++ break; ++ case OTG_STATE_A_VBUS_ERR: ++ if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err) ++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); ++ break; ++ default: ++ break; ++ } ++ spin_unlock_irqrestore(&fsm->lock, flags); ++ ++ /*VDBG("quit statemachine, changed = %d\n", state_changed); */ ++ return state_changed; ++} +--- /dev/null ++++ b/drivers/usb/otg/otg_fsm.h +@@ -0,0 +1,151 @@ ++/* Copyright 2006-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#if 0 ++#define DEBUG 1 ++#define VERBOSE 1 ++#endif ++ ++#ifdef DEBUG ++#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt , \ ++ __func__, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#ifdef VERBOSE ++#define VDBG DBG ++#else ++#define VDBG(stuff...) do {} while (0) ++#endif ++ ++#ifdef VERBOSE ++#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__) ++#else ++#define MPC_LOC do {} while (0) ++#endif ++ ++#define PROTO_UNDEF (0) ++#define PROTO_HOST (1) ++#define PROTO_GADGET (2) ++ ++/* OTG state machine according to the OTG spec */ ++struct otg_fsm { ++ /* Input */ ++ int a_bus_resume; ++ int a_bus_suspend; ++ int a_conn; ++ int a_sess_vld; ++ int a_srp_det; ++ int a_vbus_vld; ++ int b_bus_resume; ++ int b_bus_suspend; ++ int b_conn; ++ int b_se0_srp; ++ int b_sess_end; ++ int b_sess_vld; ++ int id; ++ ++ /* Internal variables */ ++ int a_set_b_hnp_en; ++ int b_srp_done; ++ int b_hnp_enable; ++ ++ /* Timeout indicator for timers */ ++ int a_wait_vrise_tmout; ++ int a_wait_bcon_tmout; ++ int a_aidl_bdis_tmout; ++ int b_ase0_brst_tmout; ++ ++ /* Informative variables */ ++ int a_bus_drop; ++ int a_bus_req; ++ int a_clr_err; ++ int a_suspend_req; ++ int b_bus_req; ++ ++ /* Output */ ++ int drv_vbus; ++ int loc_conn; ++ int loc_sof; ++ ++ struct otg_fsm_ops *ops; ++ struct otg_transceiver *transceiver; ++ ++ /* Current usb protocol used: 0:undefine; 1:host; 2:client */ ++ int protocol; ++ spinlock_t lock; ++}; ++ ++struct otg_fsm_ops { ++ void (*chrg_vbus)(int on); ++ void (*drv_vbus)(int on); ++ void (*loc_conn)(int on); ++ void (*loc_sof)(int on); ++ void (*start_pulse)(void); ++ void (*add_timer)(void *timer); ++ void (*del_timer)(void *timer); ++ int (*start_host)(struct otg_fsm *fsm, int on); ++ int (*start_gadget)(struct otg_fsm *fsm, int on); ++}; ++ ++ ++static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on) ++{ ++ fsm->ops->chrg_vbus(on); ++} ++ ++static inline void otg_drv_vbus(struct otg_fsm *fsm, int on) ++{ ++ if (fsm->drv_vbus != on) { ++ fsm->drv_vbus = on; ++ fsm->ops->drv_vbus(on); ++ } ++} ++ ++static inline void otg_loc_conn(struct otg_fsm *fsm, int on) ++{ ++ if (fsm->loc_conn != on) { ++ fsm->loc_conn = on; ++ fsm->ops->loc_conn(on); ++ } ++} ++ ++static inline void otg_loc_sof(struct otg_fsm *fsm, int on) ++{ ++ if (fsm->loc_sof != on) { ++ fsm->loc_sof = on; ++ fsm->ops->loc_sof(on); ++ } ++} ++ ++static inline void otg_start_pulse(struct otg_fsm *fsm) ++{ ++ fsm->ops->start_pulse(); ++} ++ ++static inline void otg_add_timer(struct otg_fsm *fsm, void *timer) ++{ ++ fsm->ops->add_timer(timer); ++} ++ ++static inline void otg_del_timer(struct otg_fsm *fsm, void *timer) ++{ ++ fsm->ops->del_timer(timer); ++} ++ ++int otg_statemachine(struct otg_fsm *fsm); +--- /dev/null ++++ b/drivers/usb/otg/usb.c +@@ -0,0 +1,76 @@ ++/* Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Author: Li Yang <LeoLi@freescale.com> ++ * Jerry Huang <Chang-Ming.Huang@freescale.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/usb/otg.h> ++ ++#include <linux/io.h> ++#include <asm/irq.h> ++#include <asm/system.h> ++ ++ ++static struct otg_transceiver *transceiver; ++static struct resource *otg_resources; ++ ++/* ++ * otg_get_transceiver - find the (single) OTG transceiver driver ++ * ++ * Returns the transceiver driver, after getting a refcount to it; or ++ * null if there is no such transceiver. The caller is responsible for ++ * releasing that count. ++ */ ++struct otg_transceiver *otg_get_transceiver(void) ++{ ++ pr_debug("%s transceiver=0x%p\n", __func__, transceiver); ++ if (transceiver) ++ get_device(transceiver->dev); ++ ++ return transceiver; ++} ++EXPORT_SYMBOL(otg_get_transceiver); ++ ++int otg_set_transceiver(struct otg_transceiver *otg) ++{ ++ if (transceiver && otg) ++ return -EBUSY; ++ ++ transceiver = otg; ++ ++ return 0; ++} ++EXPORT_SYMBOL(otg_set_transceiver); ++ ++struct resource *otg_get_resources(void) ++{ ++ return otg_resources; ++} ++EXPORT_SYMBOL(otg_get_resources); ++ ++int otg_set_resources(struct resource *resources) ++{ ++ otg_resources = resources; ++ return 0; ++} ++EXPORT_SYMBOL(otg_set_resources); +--- a/include/linux/fsl_devices.h ++++ b/include/linux/fsl_devices.h +@@ -72,6 +72,18 @@ struct fsl_usb2_platform_data { + void (*exit)(struct platform_device *); + void __iomem *regs; /* ioremap'd register base */ + struct clk *clk; ++#ifdef CONFIG_COLDFIRE ++ u32 xcvr_type; /* PORTSC_PTS_* */ ++ char *name; /* pretty print */ ++ char *transceiver; /* transceiver name */ ++ unsigned power_budget; /* for hcd->power_budget */ ++ struct platform_device *pdev; ++ struct fsl_xcvr_ops *xcvr_ops; ++ ++ int (*gpio_usb_active) (void); ++ void (*gpio_usb_inactive) (void); ++ ++#endif + unsigned big_endian_mmio:1; + unsigned big_endian_desc:1; + unsigned es:1; /* need USBMODE:ES */ +@@ -79,6 +91,20 @@ struct fsl_usb2_platform_data { + unsigned have_sysif_regs:1; + unsigned invert_drvvbus:1; + unsigned invert_pwr_fault:1; ++#ifdef CONFIG_COLDFIRE ++ unsigned suspended:1; ++ unsigned already_suspended:1; ++#endif ++ /* register save area for suspend/resume */ ++ u32 pm_command; ++ u32 pm_status; ++ u32 pm_intr_enable; ++ u32 pm_frame_index; ++ u32 pm_segment; ++ u32 pm_frame_list; ++ u32 pm_async_next; ++ u32 pm_configured_flag; ++ u32 pm_portsc; + }; + + /* Flags in fsl_usb2_mph_platform_data */ +--- /dev/null ++++ b/include/linux/usb/fsl_usb2.h +@@ -0,0 +1,410 @@ ++/* ++ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Freescale USB device/endpoint management registers ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#ifndef __FSL_USB2_H ++#define __FSL_USB2_H ++ ++ ++ /* USB DR device mode registers (Little Endian) */ ++struct fsl_usb_device_regs { ++ /* Capability register */ ++ u32 id; ++ u32 res1[63]; ++ u16 caplength; /* Capability Register Length */ ++ u16 hciversion; /* Host Controller Interface Version */ ++ u32 hcsparams; /* Host Controller Structual Parameters */ ++ u32 hccparams; /* Host Controller Capability Parameters */ ++ u32 res2[5]; ++ u32 dciversion; /* Device Controller Interface Version */ ++ u32 dccparams; /* Device Controller Capability Parameters */ ++ u32 res3[6]; ++ /* Operation register */ ++ u32 usbcmd; /* USB Command Register */ ++ u32 usbsts; /* USB Status Register */ ++ u32 usbintr; /* USB Interrupt Enable Register */ ++ u32 frindex; /* Frame Index Register */ ++ u32 res4; ++ u32 deviceaddr; /* Device Address */ ++ u32 endpointlistaddr; /* Endpoint List Address Register */ ++ u32 res5; ++ u32 burstsize; /* Master Interface Data Burst Size Register */ ++ u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ ++ u32 res6[2]; ++ u32 ulpiview; ++ u32 res7[3]; ++ u32 configflag; /* Configure Flag Register */ ++ u32 portsc1; /* Port 1 Status and Control Register */ ++ u32 res8[7]; ++ u32 otgsc; /* On-The-Go Status and Control */ ++ u32 usbmode; /* USB Mode Register */ ++ u32 endptsetupstat; /* Endpoint Setup Status Register */ ++ u32 endpointprime; /* Endpoint Initialization Register */ ++ u32 endptflush; /* Endpoint Flush Register */ ++ u32 endptstatus; /* Endpoint Status Register */ ++ u32 endptcomplete; /* Endpoint Complete Register */ ++ /* DCCPARAMS:DEN has the real number of device endpoints. */ ++ u32 endptctrl[16]; /* Endpoint Control Registers */ ++}; ++ ++ /* USB DR host mode registers (Little Endian) */ ++struct fsl_usb_host_regs { ++ /* Capability register */ ++ u32 id; ++ u32 res1[63]; ++ u16 caplength; /* Capability Register Length */ ++ u16 hciversion; /* Host Controller Interface Version */ ++ u32 hcsparams; /* Host Controller Structual Parameters */ ++ u32 hccparams; /* Host Controller Capability Parameters */ ++ u32 res2[5]; ++ u32 dciversion; /* Device Controller Interface Version */ ++ u32 dccparams; /* Device Controller Capability Parameters */ ++ u32 res3[6]; ++ /* Operation register */ ++ u32 usbcmd; /* USB Command Register */ ++ u32 usbsts; /* USB Status Register */ ++ u32 usbintr; /* USB Interrupt Enable Register */ ++ u32 frindex; /* Frame Index Register */ ++ u32 res4; ++ u32 periodiclistbase; /* Periodic Frame List Base Address Register */ ++ u32 asynclistaddr; /* Current Asynchronous List Address Register */ ++ u32 res5; ++ u32 burstsize; /* Master Interface Data Burst Size Register */ ++ u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ ++ u32 res6[2]; ++ u32 ulpiview; ++ u32 res7[3]; ++ u32 configflag; /* Configure Flag Register */ ++ u32 portsc1; /* Port 1 Status and Control Register */ ++ u32 res8[7]; ++ u32 otgsc; /* On-The-Go Status and Control */ ++ u32 usbmode; /* USB Mode Register */ ++ u32 endptsetupstat; /* Endpoint Setup Status Register */ ++ u32 endpointprime; /* Endpoint Initialization Register */ ++ u32 endptflush; /* Endpoint Flush Register */ ++ u32 endptstatus; /* Endpoint Status Register */ ++ u32 endptcomplete; /* Endpoint Complete Register */ ++ /* DCCPARAMS:DEN has the real number of device endpoints. */ ++ u32 endptctrl[16]; /* Endpoint Control Registers */ ++}; ++ ++ /* non-EHCI USB system interface registers (Big Endian) */ ++struct usb_sys_interface { ++ u32 snoop1; ++ u32 snoop2; ++ u32 age_cnt_thresh; /* Age Count Threshold Register */ ++ u32 pri_ctrl; /* Priority Control Register */ ++ u32 si_ctrl; /* System Interface Control Register */ ++ u32 res[59]; ++ u32 control; /* General Purpose Control Register */ ++}; ++ ++/* ep0 transfer state */ ++#define WAIT_FOR_SETUP 0 ++#define DATA_STATE_XMIT 1 ++#define DATA_STATE_NEED_ZLP 2 ++#define WAIT_FOR_OUT_STATUS 3 ++#define DATA_STATE_RECV 4 ++ ++/* Frame Index Register Bit Masks */ ++#define USB_FRINDEX_MASKS 0x3fff ++ ++ ++ ++/* USBCMD Register Bit Masks */ ++#define USB_CMD_RUN_STOP 0x00000001 ++#define USB_CMD_CTRL_RESET 0x00000002 ++#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010 ++#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020 ++#define USB_CMD_INT_AA_DOORBELL 0x00000040 ++#define USB_CMD_ASP 0x00000300 ++#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800 ++#define USB_CMD_SUTW 0x00002000 ++#define USB_CMD_ATDTW 0x00004000 ++#define USB_CMD_ITC 0x00FF0000 ++ ++/* bit 15,3,2 are frame list size */ ++#define USB_CMD_FRAME_SIZE_1024 0x00000000 ++#define USB_CMD_FRAME_SIZE_512 0x00000004 ++#define USB_CMD_FRAME_SIZE_256 0x00000008 ++#define USB_CMD_FRAME_SIZE_128 0x0000000C ++#define USB_CMD_FRAME_SIZE_64 0x00008000 ++#define USB_CMD_FRAME_SIZE_32 0x00008004 ++#define USB_CMD_FRAME_SIZE_16 0x00008008 ++#define USB_CMD_FRAME_SIZE_8 0x0000800C ++ ++/* bit 9-8 are async schedule park mode count */ ++#define USB_CMD_ASP_00 0x00000000 ++#define USB_CMD_ASP_01 0x00000100 ++#define USB_CMD_ASP_10 0x00000200 ++#define USB_CMD_ASP_11 0x00000300 ++#define USB_CMD_ASP_BIT_POS 8 ++ ++/* bit 23-16 are interrupt threshold control */ ++#define USB_CMD_ITC_NO_THRESHOLD 0x00000000 ++#define USB_CMD_ITC_1_MICRO_FRM 0x00010000 ++#define USB_CMD_ITC_2_MICRO_FRM 0x00020000 ++#define USB_CMD_ITC_4_MICRO_FRM 0x00040000 ++#define USB_CMD_ITC_8_MICRO_FRM 0x00080000 ++#define USB_CMD_ITC_16_MICRO_FRM 0x00100000 ++#define USB_CMD_ITC_32_MICRO_FRM 0x00200000 ++#define USB_CMD_ITC_64_MICRO_FRM 0x00400000 ++#define USB_CMD_ITC_BIT_POS 16 ++ ++ ++ ++ ++/* USB STS Register Bit Masks */ ++#define USB_STS_INT 0x00000001 ++#define USB_STS_ERR 0x00000002 ++#define USB_STS_PORT_CHANGE 0x00000004 ++#define USB_STS_FRM_LST_ROLL 0x00000008 ++#define USB_STS_SYS_ERR 0x00000010 ++#define USB_STS_IAA 0x00000020 ++#define USB_STS_RESET 0x00000040 ++#define USB_STS_SOF 0x00000080 ++#define USB_STS_SUSPEND 0x00000100 ++#define USB_STS_HC_HALTED 0x00001000 ++#define USB_STS_RCL 0x00002000 ++#define USB_STS_PERIODIC_SCHEDULE 0x00004000 ++#define USB_STS_ASYNC_SCHEDULE 0x00008000 ++ ++/* USB INTR Register Bit Masks */ ++#define USB_INTR_INT_EN 0x00000001 ++#define USB_INTR_ERR_INT_EN 0x00000002 ++#define USB_INTR_PTC_DETECT_EN 0x00000004 ++#define USB_INTR_FRM_LST_ROLL_EN 0x00000008 ++#define USB_INTR_SYS_ERR_EN 0x00000010 ++#define USB_INTR_ASYN_ADV_EN 0x00000020 ++#define USB_INTR_RESET_EN 0x00000040 ++#define USB_INTR_SOF_EN 0x00000080 ++#define USB_INTR_DEVICE_SUSPEND 0x00000100 ++ ++/* Device Address bit masks */ ++#define USB_DEVICE_ADDRESS_MASK 0xFE000000 ++#define USB_DEVICE_ADDRESS_BIT_POS 25 ++ ++/* endpoint list address bit masks */ ++#define USB_EP_LIST_ADDRESS_MASK 0xfffff800 ++ ++ ++/* x_PORTSCx */ ++/* bit 31-30 are port transceiver select */ ++#define PORTSCX_PTS_MASK (3 << 30) /* parallel xcvr select mask */ ++#define PORTSCX_PHY_TYPE_SEL PORTSCX_PTS_MASK ++#define PORTSCX_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */ ++#define PORTSCX_PTS_PHILIPS (1 << 30) /* Philips classic */ ++#define PORTSCX_PTS_ULPI (2 << 30) /* ULPI */ ++#define PORTSCX_PTS_SERIAL (3 << 30) /* serial */ ++#define PORTSCX_PTS_FSLS PORTSCX_PTS_SERIAL ++#define PORTSCX_PTS_ONCHIP PORTSCX_PTS_FSLS ++ ++#define PORTSCX_STS (1 << 29) /* serial xcvr select */ ++ ++/* bit 28 is parallel transceiver width for UTMI interface */ ++#define PORTSCX_PTW_8BIT (0 << 28) /* 8 bit parallel xcvr */ ++#define PORTSCX_PTW_16BIT (1 << 28) /* 16 bi parallel xcvr */ ++ ++/* bit 27-26 are port speed */ ++#define PORTSCX_PORT_SPEED_FULL (0 << 26) ++#define PORTSCX_PORT_SPEED_LOW (1 << 26) ++#define PORTSCX_PORT_SPEED_HIGH (2 << 26) ++#define PORTSCX_PORT_SPEED_UNDEF (3 << 26) ++#define PORTSCX_PORT_SPEED_MASK (3 << 26) ++ ++/* phy low pwr suspend/clk disable */ ++#define PORTSCX_PHY_LOW_POWER_SPD (1 << 23) ++ ++/* bit 19-16 are port test control */ ++#define PORTSCX_PTC_DISABLE (0 << 16) ++#define PORTSCX_PTC_JSTATE (1 << 16) ++#define PORTSCX_PTC_KSTATE (2 << 16) ++#define PORTSCX_PTC_SEQNAK (3 << 16) /* SE0 (host)/NAK (device)*/ ++#define PORTSCX_PTC_PACKET (4 << 16) ++#define PORTSCX_PTC_FORCE_EN_HS (5 << 16) ++#define PORTSCX_PTC_FORCE_EN_FS (6 << 16) ++#define PORTSCX_PTC_FORCE_EN_LS (7 << 16) ++ ++ ++/* bit 15-14 are port indicator control */ ++#define PORTSCX_PIC_OFF (0 << 14) ++#define PORTSCX_PIC_AMBER (1 << 14) ++#define PORTSCX_PIC_GREEN (2 << 14) ++#define PORTSCX_PIC_UNDEF (3 << 14) ++ ++#define PORTSCX_PORT_POWER (1 << 12) /* port power */ ++ ++/* bit 11-10 are line status */ ++#define PORTSCX_LS_MASK (3 << 10) /* Line State mask */ ++#define PORTSCX_LS_SE0 (0 << 10) /* SE0 */ ++#define PORTSCX_LS_K_STATE (1 << 10) /* K-state */ ++#define PORTSCX_LS_J_STATE (2 << 10) /* J-state */ ++ ++#define PORTSCX_PORT_RESET (1 << 8) /* Port reset */ ++#define PORTSCX_PORT_SUSPEND (1 << 7) /* Suspend */ ++#define PORTSCX_PORT_FORCE_RESUME (1 << 6) /* Force port resume */ ++#define PORTSCX_OVER_CURRENT_CHG (1 << 5) /* over current change */ ++#define PORTSCX_OVER_CURRENT_ACT (1 << 4) /* over currrent active */ ++#define PORTSCX_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change*/ ++#define PORTSCX_PORT_ENABLE (1 << 2) /* port enabled */ ++#define PORTSCX_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */ ++#define PORTSCX_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */ ++ ++#define PORTSCX_W1C_BITS \ ++ (PORTSCX_CONNECT_STATUS_CHANGE | \ ++ PORTSCX_PORT_EN_DIS_CHANGE | \ ++ PORTSCX_OVER_CURRENT_CHG) ++ ++ ++ ++/* UOG_OTGSC Register Bits */ ++/* control bits: */ ++#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0) ++#define OTGSC_CTRL_VBUS_CHARGE (1 << 1) ++#define OTGSC_CTRL_OTG_TERM (1 << 3)/* controls DM pulldown */ ++#define OTGSC_CTRL_DATA_PULSING (1 << 4) ++#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */ ++/* current status: (R/O) */ ++#define OTGSC_STS_USB_ID (1 << 8)/* 0=A-device 1=B-device */ ++#define OTGSC_STS_A_VBUS_VALID (1 << 9) ++#define OTGSC_STS_A_SESSION_VALID (1 << 10) ++#define OTGSC_STS_B_SESSION_VALID (1 << 11) ++#define OTGSC_STS_B_SESSION_END (1 << 12) ++#define OTGSC_STS_1ms_TIMER (1 << 13) ++#define OTGSC_STS_DATA_PULSE (1 << 14) ++/* interrupt status: (write to clear) */ ++#define OTGSC_INTSTS_MASK (0x7f << 16) ++#define OTGSC_INTSTS_USB_ID (1 << 16) ++#define OTGSC_INTSTS_A_VBUS_VALID (1 << 17) ++#define OTGSC_INTSTS_A_SESSION_VALID (1 << 18) ++#define OTGSC_INTSTS_B_SESSION_VALID (1 << 19) ++#define OTGSC_INTSTS_B_SESSION_END (1 << 20) ++#define OTGSC_INTSTS_1MS_TIMER (1 << 21) ++#define OTGSC_INTSTS_DATA_PULSE (1 << 22) ++/* interrupt enables: */ ++#define OTGSC_IE_MASK (0x7f << 24) ++#define OTGSC_IE_USB_ID (1 << 24) ++#define OTGSC_IE_A_VBUS_VALID (1 << 25) ++#define OTGSC_IE_A_SESSION_VALID (1 << 26) ++#define OTGSC_IE_B_SESSION_VALID (1 << 27) ++#define OTGSC_IE_B_SESSION_END (1 << 28) ++#define OTGSC_IE_1ms_TIMER (1 << 29) ++#define OTGSC_IE_DATA_PULSE (1 << 30) ++ ++#if 1 /* DDD FIXME these here for compatibility between my names and Leo's */ ++/* OTG interrupt enable bit masks */ ++#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK ++ ++/* OTG interrupt status bit masks */ ++#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_INTSTS_MASK ++#endif ++ ++ ++ ++/* x_USBMODE */ ++#undef USBMODE_SDIS /* defined as bit 3 in drivers/usb/host/ehci.h */ ++#define USBMODE_SDIS (1 << 4) /* stream disable mode */ ++#define USBMODE_SLOM (1 << 3) /* setup lockout mode */ ++#define USBMODE_ES (1 << 2) /* (big) endian select */ ++#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ ++#define USBMODE_CM_HOST (3 << 0) /* host */ ++#define USBMODE_CM_DEVICE (2 << 0) /* device */ ++ ++/* DDD for compatibility for now */ ++#define USB_MODE_CTRL_MODE_IDLE USBMODE_CM_IDLE ++#define USB_MODE_CTRL_MODE_DEVICE USBMODE_CM_DEVICE ++#define USB_MODE_CTRL_MODE_HOST USBMODE_CM_HOST ++#define USB_MODE_SETUP_LOCK_OFF USBMODE_SLOM ++#define USB_MODE_STREAM_DISABLE USBMODE_SDIS ++ ++ ++/* ULPIVIEW register bits */ ++#define ULPIVW_WU (1 << 31) /* Wakeup */ ++#define ULPIVW_RUN (1 << 30) /* read/write run */ ++#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */ ++#define ULPIVW_SS (1 << 27) /* SyncState */ ++#define ULPIVW_PORT_MASK 0x07 /* Port field */ ++#define ULPIVW_PORT_SHIFT 24 ++#define ULPIVW_ADDR_MASK 0xFF /* data address field */ ++#define ULPIVW_ADDR_SHIFT 16 ++#define ULPIVW_RDATA_MASK 0xFF /* read data field */ ++#define ULPIVW_RDATA_SHIFT 8 ++#define ULPIVW_WDATA_MASK 0xFF /* write data field */ ++#define ULPIVW_WDATA_SHIFT 0 ++ ++ ++/* Endpoint Flush Register */ ++#define EPFLUSH_TX_OFFSET 0x00010000 ++#define EPFLUSH_RX_OFFSET 0x00000000 ++ ++/* Endpoint Setup Status bit masks */ ++#define EP_SETUP_STATUS_MASK 0x0000003F ++#define EP_SETUP_STATUS_EP0 0x00000001 ++ ++/* ENDPOINTCTRLx Register Bit Masks */ ++#define EPCTRL_TX_ENABLE 0x00800000 ++#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */ ++#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */ ++#define EPCTRL_TX_TYPE 0x000C0000 ++#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */ ++#define EPCTRL_TX_EP_STALL 0x00010000 ++#define EPCTRL_RX_ENABLE 0x00000080 ++#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */ ++#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */ ++#define EPCTRL_RX_TYPE 0x0000000C ++#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */ ++#define EPCTRL_RX_EP_STALL 0x00000001 ++ ++/* bit 19-18 and 3-2 are endpoint type */ ++#define EPCTRL_EP_TYPE_CONTROL 0 ++#define EPCTRL_EP_TYPE_ISO 1 ++#define EPCTRL_EP_TYPE_BULK 2 ++#define EPCTRL_EP_TYPE_INTERRUPT 3 ++#define EPCTRL_TX_EP_TYPE_SHIFT 18 ++#define EPCTRL_RX_EP_TYPE_SHIFT 2 ++ ++/* pri_ctrl Register Bit Masks */ ++#define PRI_CTRL_PRI_LVL1 0x0000000C ++#define PRI_CTRL_PRI_LVL0 0x00000003 ++ ++/* si_ctrl Register Bit Masks */ ++#define SI_CTRL_ERR_DISABLE 0x00000010 ++#define SI_CTRL_IDRC_DISABLE 0x00000008 ++#define SI_CTRL_RD_SAFE_EN 0x00000004 ++#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002 ++#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001 ++ ++ ++/* control Register Bit Masks */ ++#define USB_CTRL_IOENB 0x00000004 ++#define USB_CTRL_ULPI_INT0EN 0x00000001 ++ ++ ++/* Endpoint Transfer Descriptor bit Masks */ ++#define DTD_NEXT_TERMINATE 0x00000001 ++#define DTD_IOC 0x00008000 ++#define DTD_STATUS_ACTIVE 0x00000080 ++#define DTD_STATUS_HALTED 0x00000040 ++#define DTD_STATUS_DATA_BUFF_ERR 0x00000020 ++#define DTD_STATUS_TRANSACTION_ERR 0x00000008 ++#define DTD_RESERVED_FIELDS 0x80007300 ++#define DTD_ADDR_MASK 0xFFFFFFE0 ++#define DTD_PACKET_SIZE 0x7FFF0000 ++#define DTD_LENGTH_BIT_POS 16 ++#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ ++ DTD_STATUS_DATA_BUFF_ERR | \ ++ DTD_STATUS_TRANSACTION_ERR) ++/* Alignment requirements; must be a power of two */ ++#define DTD_ALIGNMENT 0x20 ++#define QH_ALIGNMENT 2048 ++ ++/* Controller dma boundary */ ++#define UDC_DMA_BOUNDARY 0x1000 ++ ++#endif /* __FSL_USB2_H */ +--- /dev/null ++++ b/include/linux/usb/fsl_xcvr.h +@@ -0,0 +1,36 @@ ++/* ++ * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++/** ++ * struct fsl_xcvr_ops - USB transceiver operations ++ * ++ * @xcvr_type: one of PORTSCX_PTS_{UTMI,SERIAL,ULPI} ++ * @init: transceiver- and board-specific initialization function ++ * @uninit: transceiver- and board-specific uninitialization function ++ * @set_host: ++ * @set_device: ++ * ++ */ ++struct fsl_xcvr_ops { ++ char *name; ++ u32 xcvr_type; ++ struct fsl_usb2_platform_data *pdata; ++ ++ void (*init)(struct fsl_xcvr_ops *ops); ++ void (*uninit)(struct fsl_xcvr_ops *ops); ++ void (*suspend)(struct fsl_xcvr_ops *ops); ++ void (*set_host)(void); ++ void (*set_device)(void); ++ void (*set_vbus_power)(struct fsl_xcvr_ops *ops, int on); ++ void (*set_remote_wakeup)(u32 *view); ++ void (*pullup)(int on); ++}; ++ ++extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); ++extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); +--- a/include/linux/usb/otg.h ++++ b/include/linux/usb/otg.h +@@ -164,7 +164,7 @@ otg_shutdown(struct otg_transceiver *otg + } + + /* for usb host and peripheral controller drivers */ +-#ifdef CONFIG_USB_OTG_UTILS ++#if defined(CONFIG_USB_OTG_UTILS) || defined(CONFIG_COLDFIRE) + extern struct otg_transceiver *otg_get_transceiver(void); + extern void otg_put_transceiver(struct otg_transceiver *); + #else diff --git a/target/linux/coldfire/patches/041-Fix-CAU-driver-bug-for-SHA1-digest-algorithm.patch b/target/linux/coldfire/patches/041-Fix-CAU-driver-bug-for-SHA1-digest-algorithm.patch new file mode 100644 index 000000000..87df7809b --- /dev/null +++ b/target/linux/coldfire/patches/041-Fix-CAU-driver-bug-for-SHA1-digest-algorithm.patch @@ -0,0 +1,25 @@ +From da0df827fa9600b3104d4b8d8cc3edbdd5a0849b Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:53 +0800 +Subject: [PATCH 41/52] Fix CAU driver bug for SHA1 digest algorithm + +Make the compiler to never inline a particular member +function. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/crypto/mcfcau-sha1.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +--- a/drivers/crypto/mcfcau-sha1.c ++++ b/drivers/crypto/mcfcau-sha1.c +@@ -60,7 +60,8 @@ struct mcfcau_sha1_ctx { + u8 buffer[64]; + }; + +-static void mcfcau_sha1_transform(__u32 *digest, const char *in, __u32 *W) ++static noinline void mcfcau_sha1_transform(__u32 *digest, ++ const char *in, __u32 *W) + { + int i; + u32 *tmp_p; diff --git a/target/linux/coldfire/patches/042-Fix-NEED_MULTIPLE_NODES-unmet-direct-dependencies-wa.patch b/target/linux/coldfire/patches/042-Fix-NEED_MULTIPLE_NODES-unmet-direct-dependencies-wa.patch new file mode 100644 index 000000000..336afabf4 --- /dev/null +++ b/target/linux/coldfire/patches/042-Fix-NEED_MULTIPLE_NODES-unmet-direct-dependencies-wa.patch @@ -0,0 +1,24 @@ +From 77910a929baaf0ecba893e6e54857315384dc374 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:54 +0800 +Subject: [PATCH 42/52] Fix NEED_MULTIPLE_NODES unmet direct dependencies warning + +Fix the warning that "(SINGLE_MEMORY_CHUNK) selects NEED_MULTIPLE_NODES +which has unmet direct dependencies (DISCONTIGMEM || NUMA)". + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + mm/Kconfig | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/mm/Kconfig ++++ b/mm/Kconfig +@@ -84,7 +84,7 @@ config FLAT_NODE_MEM_MAP + # + config NEED_MULTIPLE_NODES + def_bool y +- depends on DISCONTIGMEM || NUMA ++ depends on DISCONTIGMEM || NUMA || COLDFIRE + + config HAVE_MEMORY_PRESENT + def_bool y diff --git a/target/linux/coldfire/patches/043-workaround-for-zero-page-used-on-ColdFire-platform.patch b/target/linux/coldfire/patches/043-workaround-for-zero-page-used-on-ColdFire-platform.patch new file mode 100644 index 000000000..0182b096a --- /dev/null +++ b/target/linux/coldfire/patches/043-workaround-for-zero-page-used-on-ColdFire-platform.patch @@ -0,0 +1,33 @@ +From fa27f3e27863e3f4376864b144dc7506de124cf6 Mon Sep 17 00:00:00 2001 +From: Jason Jin <Jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 09:59:54 +0800 +Subject: [PATCH 43/52] workaround for zero page used on ColdFire platform. + +There is some issue for Coldfire platform to use the +zero page for read when there is memory fault. This is +a workaround for this, try to make kernel to use normal +memory instead. + +Signed-off-by: Jason Jin <Jason.jin@freescale.com> +--- + mm/memory.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/mm/memory.c ++++ b/mm/memory.c +@@ -2937,6 +2937,7 @@ static int do_anonymous_page(struct mm_s + if (check_stack_guard_page(vma, address) < 0) + return VM_FAULT_SIGBUS; + ++#ifndef CONFIG_COLDFIRE + /* Use the zero-page for reads */ + if (!(flags & FAULT_FLAG_WRITE)) { + entry = pte_mkspecial(pfn_pte(my_zero_pfn(address), +@@ -2946,6 +2947,7 @@ static int do_anonymous_page(struct mm_s + goto unlock; + goto setpte; + } ++#endif + + /* Allocate our own private page. */ + if (unlikely(anon_vma_prepare(vma))) diff --git a/target/linux/coldfire/patches/044-Fix-Max3353-otg-toggle-bug.patch b/target/linux/coldfire/patches/044-Fix-Max3353-otg-toggle-bug.patch new file mode 100644 index 000000000..218d49cd3 --- /dev/null +++ b/target/linux/coldfire/patches/044-Fix-Max3353-otg-toggle-bug.patch @@ -0,0 +1,26 @@ +From ff4fb46407f3aee09432a897822e4934d5c6b3ff Mon Sep 17 00:00:00 2001 +From: Jingchang Lu <b35083@freescale.com> +Date: Thu, 4 Aug 2011 09:59:54 +0800 +Subject: [PATCH 44/52] Fix Max3353 otg toggle bug + +The max3353 charge pump work with SOC FS/LS transceiver, +during dual role toggle, the root hub port should be powered +off to disable port status detection when suspend host mode, +otherwise it won't work properly when switch to host mode. + +Signed-off-by: Jingchang Lu <b35083@freescale.com> +--- + drivers/usb/host/ehci-fsl.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/drivers/usb/host/ehci-fsl.c ++++ b/drivers/usb/host/ehci-fsl.c +@@ -528,7 +528,7 @@ static int ehci_fsl_suspend(struct devic + pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); + + pdata->suspended = 1; +-#if 0 ++#if defined(CONFIG_USB_M5441X_MAX3353_FSLS) + /* clear PP to cut power to the port */ + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + tmp &= ~PORT_POWER; diff --git a/target/linux/coldfire/patches/045-Add-high-resolution-kernel-timer-support.patch b/target/linux/coldfire/patches/045-Add-high-resolution-kernel-timer-support.patch new file mode 100644 index 000000000..523d157f5 --- /dev/null +++ b/target/linux/coldfire/patches/045-Add-high-resolution-kernel-timer-support.patch @@ -0,0 +1,24 @@ +From aedec75c772919fa77c33854d3389d8ca73c25bf Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:54 +0800 +Subject: [PATCH 45/52] Add high-resolution kernel timer support + +This patch fixed the bug that high-resolution kernel timer +could not be enabled. ARCH_USES_GETTIMEOFFSET is disabled. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/Kconfig | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/m68k/Kconfig ++++ b/arch/m68k/Kconfig +@@ -64,7 +64,7 @@ config HZ + default 100 + + config ARCH_USES_GETTIMEOFFSET +- def_bool y ++ def_bool n + + source "init/Kconfig" + diff --git a/target/linux/coldfire/patches/046-Convert-rtc-drivers-to-use-the-alarm_irq_enable-meth.patch b/target/linux/coldfire/patches/046-Convert-rtc-drivers-to-use-the-alarm_irq_enable-meth.patch new file mode 100644 index 000000000..e1c346cfe --- /dev/null +++ b/target/linux/coldfire/patches/046-Convert-rtc-drivers-to-use-the-alarm_irq_enable-meth.patch @@ -0,0 +1,109 @@ +From ab2284cd4730b9ea29937ee3a0ef1bcdc6b3159d Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:54 +0800 +Subject: [PATCH 46/52] Convert rtc drivers to use the alarm_irq_enable method + +Old rtc drivers use the ioctl method instead of the alarm_irq_enable +method for enabling alarm interupts. With the new virtualized RTC +rework, its important for drivers to use the alarm_irq_enable instead. + +This patch converts the drivers that use the AIE ioctl method to +use the alarm_irq_enable method. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/rtc/rtc-m5441x.c | 22 +++++++++++----------- + drivers/rtc/rtc-mcf.c | 23 +++++++++++------------ + 2 files changed, 22 insertions(+), 23 deletions(-) + +--- a/drivers/rtc/rtc-m5441x.c ++++ b/drivers/rtc/rtc-m5441x.c +@@ -400,17 +400,6 @@ static int mcf_rtc_ioctl(struct device * + writew((readw(MCF_RTC_IER) | PIE_BIT_DEF[i][1]), MCF_RTC_IER); + spin_unlock_irq(&rtc_lock); + return 0; +- case RTC_AIE_OFF: +- spin_lock_irq(&rtc_lock); +- writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER); +- spin_unlock_irq(&rtc_lock); +- return 0; +- +- case RTC_AIE_ON: +- spin_lock_irq(&rtc_lock); +- writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER); +- spin_unlock_irq(&rtc_lock); +- return 0; + + case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */ + spin_lock_irq(&rtc_lock); +@@ -427,6 +416,16 @@ static int mcf_rtc_ioctl(struct device * + return -ENOIOCTLCMD; + } + ++static int mcf_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) ++{ ++ if (enabled) ++ writew((readw(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ else ++ writew((readw(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ ++ return 0; ++} ++ + /*! + * This function reads the current RTC time into tm in Gregorian date. + * +@@ -534,6 +533,7 @@ static struct rtc_class_ops mcf_rtc_ops + .set_time = mcf_rtc_set_time, + .read_alarm = mcf_rtc_read_alarm, + .set_alarm = mcf_rtc_set_alarm, ++ .alarm_irq_enable = mcf_rtc_alarm_irq_enable, + }; + + static int __devinit mcf_rtc_probe(struct platform_device *pdev) +--- a/drivers/rtc/rtc-mcf.c ++++ b/drivers/rtc/rtc-mcf.c +@@ -298,18 +298,6 @@ static int mcf_rtc_ioctl(struct device * + writel((readl(MCF_RTC_IER) | PIE_BIT_DEF[i][1]), MCF_RTC_IER); + spin_unlock_irq(&rtc_lock); + return 0; +- case RTC_AIE_OFF: +- spin_lock_irq(&rtc_lock); +- writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER); +- spin_unlock_irq(&rtc_lock); +- return 0; +- +- case RTC_AIE_ON: +- spin_lock_irq(&rtc_lock); +- writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER); +- spin_unlock_irq(&rtc_lock); +- return 0; +- + case RTC_UIE_OFF: /* UIE is for the 1Hz interrupt */ + spin_lock_irq(&rtc_lock); + writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_1HZ), MCF_RTC_IER); +@@ -325,6 +313,16 @@ static int mcf_rtc_ioctl(struct device * + return -ENOIOCTLCMD; + } + ++static int mcf_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) ++{ ++ if (enabled) ++ writel((readl(MCF_RTC_IER) | MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ else ++ writel((readl(MCF_RTC_IER) & ~MCF_RTC_ISR_ALM), MCF_RTC_IER); ++ ++ return 0; ++} ++ + /*! + * This function reads the current RTC time into tm in Gregorian date. + * +@@ -466,6 +464,7 @@ static struct rtc_class_ops mcf_rtc_ops + .read_alarm = mcf_rtc_read_alarm, + .set_alarm = mcf_rtc_set_alarm, + .proc = mcf_rtc_proc, ++ .alarm_irq_enable = mcf_rtc_alarm_irq_enable, + }; + + static int __devinit mcf_rtc_probe(struct platform_device *pdev) diff --git a/target/linux/coldfire/patches/047-Fix-DSPI-compile-error-for-MCF547x-MCF548x.patch b/target/linux/coldfire/patches/047-Fix-DSPI-compile-error-for-MCF547x-MCF548x.patch new file mode 100644 index 000000000..2ef056edb --- /dev/null +++ b/target/linux/coldfire/patches/047-Fix-DSPI-compile-error-for-MCF547x-MCF548x.patch @@ -0,0 +1,37 @@ +From 7751684dc81d357bc9a226f12b9f12b14c824c54 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:54 +0800 +Subject: [PATCH 47/52] Fix DSPI compile error for MCF547x/MCF548x + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m547x/devices.c | 2 +- + arch/m68k/include/asm/mcfdspi.h | 8 ++++++++ + 2 files changed, 9 insertions(+), 1 deletions(-) + +--- a/arch/m68k/coldfire/m547x/devices.c ++++ b/arch/m68k/coldfire/m547x/devices.c +@@ -17,7 +17,7 @@ + + #include <asm/coldfire.h> + #include <asm/mcfsim.h> +-#include <asm/mcfqspi.h> ++#include <asm/mcfdspi.h> + + + #ifdef CONFIG_SPI +--- a/arch/m68k/include/asm/mcfdspi.h ++++ b/arch/m68k/include/asm/mcfdspi.h +@@ -56,4 +56,12 @@ struct coldfire_spi_master { + u32 *irq_list; + void (*cs_control)(u8 cs, u8 command); + }; ++ ++struct coldfire_spi_chip { ++ u8 mode; ++ u8 bits_per_word; ++ u8 del_cs_to_clk; ++ u8 del_after_trans; ++ u16 void_write_data; ++}; + #endif /*MCFDSPI_H_*/ diff --git a/target/linux/coldfire/patches/048-Fix-i2c-driver-bug-when-reinserting-as-module.patch b/target/linux/coldfire/patches/048-Fix-i2c-driver-bug-when-reinserting-as-module.patch new file mode 100644 index 000000000..a85aa5611 --- /dev/null +++ b/target/linux/coldfire/patches/048-Fix-i2c-driver-bug-when-reinserting-as-module.patch @@ -0,0 +1,75 @@ +From 2c83888b2170d3883c9316c4d94dddc4b7f9ec68 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:55 +0800 +Subject: [PATCH 48/52] Fix i2c driver bug when reinserting as module + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/i2c/busses/i2c-mcf-slave.c | 14 ++++++++++++++ + drivers/i2c/busses/i2c-mcf.c | 14 ++++++++++++++ + 2 files changed, 28 insertions(+), 0 deletions(-) + +--- a/drivers/i2c/busses/i2c-mcf-slave.c ++++ b/drivers/i2c/busses/i2c-mcf-slave.c +@@ -273,8 +273,15 @@ static int __init gen_i2c_proc_init(void + return -ENOMEM; + return 0; + } ++ ++static int gen_i2c_proc_deinit(void) ++{ ++ remove_proc_entry("driver/i2c-adaptor-register", NULL); ++ return 0; ++} + #else + static inline int gen_i2c_proc_init(void) { return 0; } ++static inline int gen_i2c_proc_deinit(void) { return 0; } + #endif /* CONFIG_PROC_FS */ + + /* +@@ -345,6 +352,13 @@ static int __init i2c_coldfire_init(void + + static void __exit i2c_coldfire_exit(void) + { ++ int retval; ++ ++ retval = gen_i2c_proc_deinit(); ++ if (retval < 0) ++ printk(KERN_INFO "remove /proc/i2c-adaptor-register " ++ "for i2c slave mode failed!\n"); ++ + /* disable I2C and Interrupt */ + MCF_I2CR &= ~(MCF_I2CR_IEN | MCF_I2CR_IIEN); + free_irq(IRQ, NULL); +--- a/drivers/i2c/busses/i2c-mcf.c ++++ b/drivers/i2c/busses/i2c-mcf.c +@@ -669,8 +669,15 @@ static int __init gen_i2c_proc_init(void + return -ENOMEM; + return 0; + } ++ ++static int gen_i2c_proc_deinit(void) ++{ ++ remove_proc_entry("driver/i2c-adaptor-register", NULL); ++ return 0; ++} + #else + static inline int gen_i2c_proc_init(void) { return 0; } ++static inline int gen_i2c_proc_deinit(void) { return 0; } + #endif /* CONFIG_PROC_FS */ + + static int __init coldfire_i2c_init(void) +@@ -687,6 +694,13 @@ static int __init coldfire_i2c_init(void + + static void __exit coldfire_i2c_exit(void) + { ++ int retval; ++ ++ retval = gen_i2c_proc_deinit(); ++ if (retval < 0) ++ printk(KERN_INFO "remove /proc/i2c-adaptor-register " ++ "for i2c master mode failed!\n"); ++ + platform_driver_unregister(&mcf_i2c_driver); + } + diff --git a/target/linux/coldfire/patches/049-Update-FEC-driver-for-MCF5445x-and-MCF54418.patch b/target/linux/coldfire/patches/049-Update-FEC-driver-for-MCF5445x-and-MCF54418.patch new file mode 100644 index 000000000..3a25350c0 --- /dev/null +++ b/target/linux/coldfire/patches/049-Update-FEC-driver-for-MCF5445x-and-MCF54418.patch @@ -0,0 +1,113 @@ +From bb6fd2eef9359aff90f78b8791967a37e3284784 Mon Sep 17 00:00:00 2001 +From: Jason Jin <jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 09:59:55 +0800 +Subject: [PATCH 49/52] Update FEC driver for MCF5445x and MCF54418 + +This patch fixed the bug that FEC could not support 10Mbps +for MCF5445x. +This patch also improved FEC performance. + +Signed-off-by: Alison Wang <b18965@freescale.com> +Signed-off-by: Jason Jin <jason.jin@freescale.com> +--- + arch/m68k/coldfire/m5441x/fec.c | 4 ++-- + arch/m68k/coldfire/m5445x/fec.c | 17 +++++++++++++++-- + drivers/net/fec.c | 9 +++++---- + 3 files changed, 22 insertions(+), 8 deletions(-) + +--- a/arch/m68k/coldfire/m5441x/fec.c ++++ b/arch/m68k/coldfire/m5441x/fec.c +@@ -98,7 +98,7 @@ static struct fec_platform_data m54418_f + }; + + static struct platform_device fec0_coldfire_device = { +- .name = "m54418-fec", ++ .name = "coldfire-fec", + .id = 0, + .resource = fec0_resources, + .num_resources = ARRAY_SIZE(fec0_resources), +@@ -109,7 +109,7 @@ static struct platform_device fec0_coldf + + #if defined(CONFIG_FEC2) + static struct platform_device fec1_coldfire_device = { +- .name = "m54418-fec", ++ .name = "coldfire-fec", + .id = 1, + .resource = fec1_resources, + .num_resources = ARRAY_SIZE(fec1_resources), +--- a/arch/m68k/coldfire/m5445x/fec.c ++++ b/arch/m68k/coldfire/m5445x/fec.c +@@ -34,6 +34,10 @@ + #include <linux/skbuff.h> + #include <linux/spinlock.h> + #include <linux/workqueue.h> ++#include <linux/platform_device.h> ++#include <linux/fec.h> ++#include <linux/io.h> ++ + #include <asm/pgtable.h> + + #include <asm/traps.h> +@@ -89,19 +93,28 @@ static struct resource fec1_resources[] + }; + #endif + ++static struct fec_platform_data m5445x_fec_pdata = { ++ .phy = PHY_INTERFACE_MODE_RMII, ++}; + static struct platform_device fec0_coldfire_device = { +- .name = "fec", ++ .name = "coldfire-fec", + .id = 0, + .resource = fec0_resources, + .num_resources = ARRAY_SIZE(fec0_resources), ++ .dev = { ++ .platform_data = &m5445x_fec_pdata, ++ } + }; + + #if defined(CONFIG_FEC2) + static struct platform_device fec1_coldfire_device = { +- .name = "fec", ++ .name = "coldfire-fec", + .id = 1, + .resource = fec1_resources, + .num_resources = ARRAY_SIZE(fec1_resources), ++ .dev = { ++ .platform_data = &m5445x_fec_pdata, ++ } + }; + #endif + +--- a/drivers/net/fec.c ++++ b/drivers/net/fec.c +@@ -76,7 +76,7 @@ static struct platform_device_id fec_dev + .name = "imx28-fec", + .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, + }, { +- .name = "m54418-fec", ++ .name = "coldfire-fec", + .driver_data = FEC_QUIRK_ENET_MAC, + }, + { } +@@ -341,8 +341,9 @@ fec_enet_start_xmit(struct sk_buff *skb, + /* Push the data cache so the CPM does not get stale memory + * data. + */ +- bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, +- FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); ++ bdp->cbd_bufaddr = __pa(bufaddr); ++ flush_dcache_range((unsigned long)skb->data, ++ (unsigned long)skb->data + skb->len); + + /* Send it on its way. Tell FEC it's ready, interrupt when done, + * it's the last BD of the frame, and to put the CRC on the end. +@@ -1074,7 +1075,7 @@ static int fec_enet_alloc_buffers(struct + + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) { +- fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); ++ fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_DMA); + + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; diff --git a/target/linux/coldfire/patches/050-Update-the-DMA-map-function-for-CF-platform.patch b/target/linux/coldfire/patches/050-Update-the-DMA-map-function-for-CF-platform.patch new file mode 100644 index 000000000..a0a7ba7ee --- /dev/null +++ b/target/linux/coldfire/patches/050-Update-the-DMA-map-function-for-CF-platform.patch @@ -0,0 +1,37 @@ +From 2411a3e2b5dfa4784bbe2548f8ef0ce1aea0379e Mon Sep 17 00:00:00 2001 +From: Jason Jin <Jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 09:59:55 +0800 +Subject: [PATCH 50/52] Update the DMA map function for CF platform + +In the DMA map, only the dcache need to be flushed. +Flush both dcache and icache will decrease the system +performance. + +Signed-off-by: Jason Jin <Jason.jin@freescale.com> +--- + arch/m68k/kernel/dma.c | 12 ++++++++++-- + 1 files changed, 10 insertions(+), 2 deletions(-) + +--- a/arch/m68k/kernel/dma.c ++++ b/arch/m68k/kernel/dma.c +@@ -94,10 +94,18 @@ void dma_sync_single_for_device(struct d + { + switch (dir) { + case DMA_TO_DEVICE: +- cache_push(handle, size); ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ flush_dcache_range(handle, handle + size); ++#else ++ flush_dcache(); ++#endif + break; + case DMA_FROM_DEVICE: +- cache_clear(handle, size); ++#if defined(CONFIG_M5445X) || defined(CONFIG_M5441X) ++ cf_dcache_inv_range(handle, handle + size); ++#else ++ flush_dcache(); ++#endif + break; + case PCI_DMA_BIDIRECTIONAL: + flush_dcache(); diff --git a/target/linux/coldfire/patches/051-Update-SD-MMC-over-SPI-driver-for-MCF54451-and-MCF54.patch b/target/linux/coldfire/patches/051-Update-SD-MMC-over-SPI-driver-for-MCF54451-and-MCF54.patch new file mode 100644 index 000000000..a92acdc0f --- /dev/null +++ b/target/linux/coldfire/patches/051-Update-SD-MMC-over-SPI-driver-for-MCF54451-and-MCF54.patch @@ -0,0 +1,105 @@ +From 44d4e083f1527e0acc6d25eadd5258565c3b8a3a Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Thu, 4 Aug 2011 09:59:55 +0800 +Subject: [PATCH 51/52] Update SD/MMC over SPI driver for MCF54451 and MCF54418 + +This patch fixed the errors in initialization and module mode. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5445x/devices.c | 6 +++--- + drivers/mmc/host/Kconfig | 8 ++++---- + drivers/spi/spi.c | 4 ++++ + 3 files changed, 11 insertions(+), 7 deletions(-) + +--- a/arch/m68k/coldfire/m5445x/devices.c ++++ b/arch/m68k/coldfire/m5445x/devices.c +@@ -20,7 +20,7 @@ + + #include <linux/interrupt.h> + #include <linux/init.h> +-#ifdef CONFIG_MMC_SPI ++#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + #include <linux/mmc/host.h> + #include <linux/spi/mmc_spi.h> + #endif +@@ -107,7 +107,7 @@ static struct coldfire_dspi_chip codec_s + }; + #endif + +-#if defined(CONFIG_MMC_SPI) ++#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + int mmc_spi_init(struct device *mmc_spi_device, + irqreturn_t mmc_spi_irq_handler(int irq, void *private), + void *irq_privatedata) +@@ -234,7 +234,7 @@ static struct spi_board_info spi_board_i + }, + #endif + +-#if defined(CONFIG_MMC_SPI) ++#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + { + .modalias = "mmc_spi", + .max_speed_hz = 25000000, +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -369,7 +369,7 @@ config MMC_SPI + If unsure, or if your system has no SPI master driver, say N. + + config M54451_SD_HW_DETECT +- tristate "use extern IRQ7 to detect SD/MMC card" ++ bool "use extern IRQ7 to detect SD/MMC card" + depends on MMC_SPI && M54451 + default y + help +@@ -377,7 +377,7 @@ config M54451_SD_HW_DETECT + use irq7 to dectect the card inserting/removing. + + config M5441X_SD_HW_DETECT +- tristate "use extern IRQ to detect SD/MMC card" ++ bool "use extern IRQ to detect SD/MMC card" + depends on MMC_SPI && M5441X + help + MMC/SD interface on 54418evb was over SPI. Enable this option will +@@ -388,14 +388,14 @@ choice + depends on M5441X_SD_HW_DETECT + + config DETECT_USE_EXTERN_IRQ7 +- tristate "based extern IRQ7" ++ bool "based extern IRQ7" + depends on M5441X_SD_HW_DETECT + help + MMC/SD cards using spi controller, + we use the extern irq7 to detect card. + + config DETECT_USE_EXTERN_IRQ1 +- tristate "based extern IRQ1" ++ bool "based extern IRQ1" + depends on M5441X_SD_HW_DETECT + help + MMC/SD cards using spi controller, +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -725,18 +725,22 @@ EXPORT_SYMBOL_GPL(spi_busnum_to_master); + */ + int spi_setup(struct spi_device *spi) + { ++#ifndef CONFIG_COLDFIRE + unsigned bad_bits; ++#endif + int status; + + /* help drivers fail *cleanly* when they need options + * that aren't supported with their current master + */ ++#ifndef CONFIG_COLDFIRE + bad_bits = spi->mode & ~spi->master->mode_bits; + if (bad_bits) { + dev_err(&spi->dev, "setup: unsupported mode bits %x\n", + bad_bits); + return -EINVAL; + } ++#endif + + if (!spi->bits_per_word) + spi->bits_per_word = 8; diff --git a/target/linux/coldfire/patches/052-Update-the-default-configurations-for-ColdFire-V4-bo.patch b/target/linux/coldfire/patches/052-Update-the-default-configurations-for-ColdFire-V4-bo.patch new file mode 100644 index 000000000..47377cf47 --- /dev/null +++ b/target/linux/coldfire/patches/052-Update-the-default-configurations-for-ColdFire-V4-bo.patch @@ -0,0 +1,6983 @@ +From f8d6deb475cbd61487f2551641d1e0977d0c75bd Mon Sep 17 00:00:00 2001 +From: Jason Jin <Jason.jin@freescale.com> +Date: Thu, 4 Aug 2011 12:38:36 +0800 +Subject: [PATCH 52/52] Update the default configurations for ColdFire V4 boards + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/configs/m54418twr_defconfig | 376 +++++++++++++++-------- + arch/m68k/configs/m54451evb_defconfig | 443 +++++++++++++++++---------- + arch/m68k/configs/m54455evb_defconfig | 524 +++++++++++++++++++++---------- + arch/m68k/configs/m5474lite_defconfig | 403 ++++++++++++++++--------- + arch/m68k/configs/m5475evb_defconfig | 444 +++++++++++++++++++--------- + arch/m68k/configs/m5485evb_defconfig | 544 +++++++++++++++++++++++---------- + 6 files changed, 1842 insertions(+), 892 deletions(-) + +--- a/arch/m68k/configs/m54418twr_defconfig ++++ b/arch/m68k/configs/m54418twr_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit +-# Linux kernel version: 2.6.29 +-# Fri Apr 23 14:36:43 2010 ++# Linux kernel version: 2.6.38 ++# Fri Jul 15 08:51:59 2011 + # + CONFIG_M68K=y + CONFIG_MMU=y +@@ -17,7 +17,9 @@ CONFIG_GENERIC_IOMAP=y + # CONFIG_NO_IOPORT is not set + # CONFIG_NO_DMA is not set + CONFIG_HZ=100 ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_CONSTRUCTORS=y + + # + # General setup +@@ -25,6 +27,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNA + CONFIG_EXPERIMENTAL=y + CONFIG_BROKEN_ON_SMP=y + CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" + CONFIG_LOCALVERSION="" + CONFIG_LOCALVERSION_AUTO=y + CONFIG_SWAP=y +@@ -34,33 +37,35 @@ CONFIG_SYSVIPC_SYSCTL=y + # CONFIG_BSD_PROCESS_ACCT is not set + # CONFIG_TASKSTATS is not set + # CONFIG_AUDIT is not set ++# CONFIG_HAVE_GENERIC_HARDIRQS is not set + + # + # RCU Subsystem + # +-CONFIG_CLASSIC_RCU=y +-# CONFIG_TREE_RCU is not set ++CONFIG_TINY_RCU=y + # CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set + # CONFIG_TREE_RCU_TRACE is not set +-# CONFIG_PREEMPT_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=17 +-CONFIG_GROUP_SCHED=y +-CONFIG_FAIR_GROUP_SCHED=y +-# CONFIG_RT_GROUP_SCHED is not set +-CONFIG_USER_SCHED=y +-# CONFIG_CGROUP_SCHED is not set + # CONFIG_CGROUPS is not set ++# CONFIG_NAMESPACES is not set ++# CONFIG_SCHED_AUTOGROUP is not set + CONFIG_SYSFS_DEPRECATED=y + CONFIG_SYSFS_DEPRECATED_V2=y + # CONFIG_RELAY is not set +-# CONFIG_NAMESPACES is not set + CONFIG_BLK_DEV_INITRD=y + CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set + CONFIG_SYSCTL=y + CONFIG_ANON_INODES=y ++CONFIG_EXPERT=y + CONFIG_EMBEDDED=y + CONFIG_UID16=y + CONFIG_SYSCTL_SYSCALL=y +@@ -78,12 +83,20 @@ CONFIG_TIMERFD=y + CONFIG_EVENTFD=y + CONFIG_SHMEM=y + CONFIG_AIO=y ++ ++# ++# Kernel Performance Events And Counters ++# + CONFIG_VM_EVENT_COUNTERS=y + CONFIG_COMPAT_BRK=y + CONFIG_SLAB=y + # CONFIG_SLUB is not set + # CONFIG_SLOB is not set + # CONFIG_PROFILING is not set ++ ++# ++# GCOV-based kernel profiling ++# + # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set + CONFIG_SLABINFO=y + CONFIG_RT_MUTEXES=y +@@ -95,8 +108,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y + # CONFIG_MODVERSIONS is not set + # CONFIG_MODULE_SRCVERSION_ALL is not set + CONFIG_BLOCK=y +-CONFIG_LBD=y +-# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_BLK_DEV_INTEGRITY is not set + +@@ -104,14 +116,41 @@ CONFIG_LBD=y + # IO Schedulers + # + CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y + CONFIG_IOSCHED_DEADLINE=y + CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set + # CONFIG_DEFAULT_DEADLINE is not set + CONFIG_DEFAULT_CFQ=y + # CONFIG_DEFAULT_NOOP is not set + CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set + # CONFIG_FREEZER is not set + + # +@@ -151,6 +190,10 @@ CONFIG_SDRAM_SIZE=0x08000000 + CONFIG_NOR_FLASH_BASE=0x00000000 + CONFIG_DMA_BASE=0xdf000000 + CONFIG_DMA_SIZE=0x1000000 ++CONFIG_SRAM=y ++CONFIG_SRAM_BASE=0x8ff00000 ++CONFIG_SRAM_SIZE=0x10000 ++CONFIG_SRAM_ALLOC_GRANULARITY=0x200 + # CONFIG_VDSO is not set + # CONFIG_M68KFPU_EMU is not set + CONFIG_ADVANCED=y +@@ -159,18 +202,19 @@ CONFIG_SINGLE_MEMORY_CHUNK=y + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set + CONFIG_SELECT_MEMORY_MODEL=y + CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set + CONFIG_FLATMEM=y + CONFIG_FLAT_NODE_MEM_MAP=y + CONFIG_NEED_MULTIPLE_NODES=y + CONFIG_PAGEFLAGS_EXTENDED=y + CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set + # CONFIG_PHYS_ADDR_T_64BIT is not set + CONFIG_ZONE_DMA_FLAG=1 + CONFIG_BOUNCE=y + CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y + + # + # General setup +@@ -193,9 +237,7 @@ CONFIG_NET=y + # + # Networking options + # +-CONFIG_COMPAT_NET_DEV_OPS=y + CONFIG_PACKET=y +-# CONFIG_PACKET_MMAP is not set + CONFIG_UNIX=y + CONFIG_XFRM=y + # CONFIG_XFRM_USER is not set +@@ -218,7 +260,7 @@ CONFIG_IP_PNP=y + # CONFIG_IP_PNP_BOOTP is not set + # CONFIG_IP_PNP_RARP is not set + # CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE is not set ++# CONFIG_NET_IPGRE_DEMUX is not set + # CONFIG_ARPD is not set + # CONFIG_SYN_COOKIES is not set + CONFIG_INET_AH=y +@@ -238,11 +280,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set + # CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set + # CONFIG_NETFILTER is not set + # CONFIG_IP_DCCP is not set + # CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set + # CONFIG_TIPC is not set + # CONFIG_ATM is not set ++# CONFIG_L2TP is not set + # CONFIG_BRIDGE is not set + # CONFIG_NET_DSA is not set + # CONFIG_VLAN_8021Q is not set +@@ -254,29 +299,61 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_LAPB is not set + # CONFIG_ECONET is not set + # CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set + # CONFIG_NET_SCHED is not set + # CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set + + # + # Network testing + # + # CONFIG_NET_PKTGEN is not set + # CONFIG_HAMRADIO is not set +-# CONFIG_CAN is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++# CONFIG_CAN_BCM is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_SLCAN is not set ++CONFIG_CAN_DEV=y ++CONFIG_CAN_CALC_BITTIMING=y ++# CONFIG_CAN_MCP251X is not set ++CONFIG_HAVE_CAN_FLEXCAN=y ++CONFIG_CAN_FLEXCAN=y ++CONFIG_FLEXCAN_NORXFIFO=y ++# CONFIG_CAN_MSCAN is not set ++# CONFIG_CAN_SJA1000 is not set ++ ++# ++# CAN USB interfaces ++# ++# CONFIG_CAN_EMS_USB is not set ++# CONFIG_CAN_ESD_USB2 is not set ++# CONFIG_CAN_SOFTING is not set ++# CONFIG_CAN_DEBUG_DEVICES is not set + # CONFIG_IRDA is not set + # CONFIG_BT is not set + # CONFIG_AF_RXRPC is not set +-# CONFIG_PHONET is not set + CONFIG_WIRELESS=y + # CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-# CONFIG_WIRELESS_EXT is not set + # CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++ ++# ++# Some wireless drivers require a rate control algorithm ++# + # CONFIG_WIMAX is not set + # CONFIG_RFKILL is not set + # CONFIG_NET_9P is not set +-# CONFIG_KLIPS is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set + + # + # Device Drivers +@@ -286,6 +363,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y + # Generic Driver Options + # + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set + # CONFIG_STANDALONE is not set + CONFIG_PREVENT_FIRMWARE_BUILD=y + CONFIG_FW_LOADER=y +@@ -295,9 +373,9 @@ CONFIG_EXTRA_FIRMWARE="" + # CONFIG_CONNECTOR is not set + CONFIG_MTD=y + # CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_CONCAT is not set + CONFIG_MTD_PARTITIONS=y +-# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_REDBOOT_PARTS is not set + CONFIG_MTD_CMDLINE_PARTS=y + # CONFIG_MTD_AR7_PARTS is not set +@@ -313,6 +391,7 @@ CONFIG_MTD_BLOCK=y + # CONFIG_INFTL is not set + # CONFIG_RFD_FTL is not set + # CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set + # CONFIG_MTD_OOPS is not set + + # +@@ -346,6 +425,7 @@ CONFIG_MTD_CFI_I2=y + # CONFIG_MTD_DATAFLASH is not set + CONFIG_MTD_M25P80=y + CONFIG_M25PXX_USE_FAST_READ=y ++# CONFIG_MTD_SST25L is not set + # CONFIG_MTD_SLRAM is not set + # CONFIG_MTD_PHRAM is not set + # CONFIG_MTD_MTDRAM is not set +@@ -357,9 +437,11 @@ CONFIG_MTD_BLOCK2MTD=y + # CONFIG_MTD_DOC2000 is not set + # CONFIG_MTD_DOC2001 is not set + # CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set + CONFIG_MTD_NAND=y + # CONFIG_MTD_NAND_VERIFY_WRITE is not set +-# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_SM_COMMON is not set + # CONFIG_MTD_NAND_MUSEUM_IDS is not set + CONFIG_MTD_NAND_IDS=y + # CONFIG_MTD_NAND_DISKONCHIP is not set +@@ -367,22 +449,23 @@ CONFIG_MTD_NAND_IDS=y + # CONFIG_MTD_NAND_PLATFORM is not set + # CONFIG_MTD_ALAUDA is not set + CONFIG_MTD_NAND_FSL_NFC=y ++CONFIG_MTD_NAND_FSL_NFC_SWECC=y + # CONFIG_MTD_ONENAND is not set + + # + # LPDDR flash memory drivers + # + # CONFIG_MTD_LPDDR is not set +- +-# +-# UBI - Unsorted block images +-# + # CONFIG_MTD_UBI is not set + # CONFIG_PARPORT is not set + CONFIG_BLK_DEV=y + # CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y + # CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# + # CONFIG_BLK_DEV_NBD is not set + # CONFIG_BLK_DEV_UB is not set + CONFIG_BLK_DEV_RAM=y +@@ -392,6 +475,7 @@ CONFIG_BLK_DEV_RAM_SIZE=64000 + # CONFIG_CDROM_PKTCDVD is not set + # CONFIG_ATA_OVER_ETH is not set + # CONFIG_BLK_DEV_HD is not set ++# CONFIG_BLK_DEV_RBD is not set + # CONFIG_MISC_DEVICES is not set + CONFIG_HAVE_IDE=y + # CONFIG_IDE is not set +@@ -399,6 +483,7 @@ CONFIG_HAVE_IDE=y + # + # SCSI device support + # ++CONFIG_SCSI_MOD=y + # CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y + CONFIG_SCSI_DMA=y +@@ -415,10 +500,6 @@ CONFIG_BLK_DEV_SD=y + # CONFIG_BLK_DEV_SR is not set + # CONFIG_CHR_DEV_SG is not set + # CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_CONSTANTS is not set + # CONFIG_SCSI_LOGGING is not set +@@ -431,15 +512,20 @@ CONFIG_SCSI_WAIT_SCAN=m + # CONFIG_SCSI_SPI_ATTRS is not set + # CONFIG_SCSI_FC_ATTRS is not set + # CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set + # CONFIG_SCSI_SAS_LIBSAS is not set + # CONFIG_SCSI_SRP_ATTRS is not set + CONFIG_SCSI_LOWLEVEL=y + # CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set + # CONFIG_LIBFC is not set ++# CONFIG_LIBFCOE is not set + # CONFIG_SCSI_DEBUG is not set + # CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set + # CONFIG_ATA is not set + # CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set + CONFIG_NETDEVICES=y + # CONFIG_DUMMY is not set + # CONFIG_BONDING is not set +@@ -447,6 +533,7 @@ CONFIG_NETDEVICES=y + # CONFIG_EQUALIZER is not set + # CONFIG_TUN is not set + # CONFIG_VETH is not set ++CONFIG_MII=y + CONFIG_PHYLIB=y + + # +@@ -461,19 +548,21 @@ CONFIG_PHYLIB=y + # CONFIG_SMSC_PHY is not set + # CONFIG_BROADCOM_PHY is not set + # CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_BCM63XX_PHY is not set + # CONFIG_ICPLUS_PHY is not set + # CONFIG_REALTEK_PHY is not set + # CONFIG_NATIONAL_PHY is not set + CONFIG_NATIONAL8364x_PHY=y + CONFIG_NATIONAL8384x_PHY=y +-CONFIG_MicrelKSZ8041_PHY=y + # CONFIG_STE10XP is not set + # CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set + # CONFIG_FIXED_PHY is not set + # CONFIG_MDIO_BITBANG is not set + CONFIG_NET_ETHERNET=y +-CONFIG_MII=y ++# CONFIG_SMC91X is not set + # CONFIG_ENC28J60 is not set ++# CONFIG_ETHOC is not set + # CONFIG_DNET is not set + # CONFIG_IBM_NEW_EMAC_ZMII is not set + # CONFIG_IBM_NEW_EMAC_RGMII is not set +@@ -483,19 +572,16 @@ CONFIG_MII=y + # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set + # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set + # CONFIG_B44 is not set ++# CONFIG_KS8851 is not set ++# CONFIG_KS8851_MLL is not set + CONFIG_FEC=y + CONFIG_FEC2=y +-CONFIG_FEC_SHARED_PHY=y +-# CONFIG_MODELO_SWITCH is not set ++# CONFIG_FEC_1588 is not set + # CONFIG_NETDEV_1000 is not set + # CONFIG_NETDEV_10000 is not set +- +-# +-# Wireless LAN +-# +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set ++CONFIG_WLAN=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_HOSTAP is not set + + # + # Enable WiMAX (Networking options) to see the WiMAX drivers +@@ -509,7 +595,12 @@ CONFIG_FEC_SHARED_PHY=y + # CONFIG_USB_PEGASUS is not set + # CONFIG_USB_RTL8150 is not set + # CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set + # CONFIG_WAN is not set ++ ++# ++# CAIF transport drivers ++# + # CONFIG_PPP is not set + # CONFIG_SLIP is not set + # CONFIG_NETCONSOLE is not set +@@ -524,6 +615,7 @@ CONFIG_FEC_SHARED_PHY=y + CONFIG_INPUT=y + # CONFIG_INPUT_FF_MEMLESS is not set + # CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set + + # + # Userland interfaces +@@ -541,11 +633,12 @@ CONFIG_INPUT_EVDEV=y + # + CONFIG_INPUT_KEYBOARD=y + # CONFIG_KEYBOARD_ATKBD is not set +-# CONFIG_KEYBOARD_SUNKBD is not set + # CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set + # CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_INPUT_MOUSE is not set + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set +@@ -559,6 +652,8 @@ CONFIG_SERIO=y + CONFIG_SERIO_SERPORT=y + # CONFIG_SERIO_LIBPS2 is not set + # CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set + # CONFIG_GAMEPORT is not set + + # +@@ -571,6 +666,7 @@ CONFIG_HW_CONSOLE=y + # CONFIG_VT_HW_CONSOLE_BINDING is not set + CONFIG_DEVKMEM=y + # CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set + + # + # Serial drivers +@@ -580,6 +676,8 @@ CONFIG_DEVKMEM=y + # + # Non-8250 serial port support + # ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX3107 is not set + CONFIG_SERIAL_CORE=y + CONFIG_SERIAL_CORE_CONSOLE=y + # CONFIG_SERIAL_COLDFIRE_IRDA is not set +@@ -597,14 +695,19 @@ CONFIG_SERIAL_MCF_UART0=y + # CONFIG_SERIAL_MCF_UART7 is not set + # CONFIG_SERIAL_MCF_UART8 is not set + # CONFIG_SERIAL_MCF_UART9 is not set ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set + CONFIG_UNIX98_PTYS=y + # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set ++# CONFIG_TTY_PRINTK is not set + # CONFIG_IPMI_HANDLER is not set + # CONFIG_HW_RANDOM is not set + # CONFIG_R3964 is not set + # CONFIG_RAW_DRIVER is not set + # CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set + # CONFIG_I2C is not set + CONFIG_SPI=y + CONFIG_SPI_MASTER=y +@@ -614,18 +717,32 @@ CONFIG_SPI_MASTER=y + # + # CONFIG_SPI_BITBANG is not set + CONFIG_SPI_DSPI=y ++CONFIG_DSPI0=y ++CONFIG_DSP0_SBF_CS=1 ++# CONFIG_DSPI1 is not set + # CONFIG_SPI_COLDFIRE_DSPI_EDMA is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set + + # + # SPI Protocol Masters + # + # CONFIG_SPI_SPIDEV is not set + # CONFIG_SPI_TLE62X0 is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# + # CONFIG_W1 is not set + # CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set + # CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set + CONFIG_WATCHDOG=y + # CONFIG_WATCHDOG_NOWAYOUT is not set + +@@ -645,36 +762,20 @@ CONFIG_SSB_POSSIBLE=y + # Sonics Silicon Backplane + # + # CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# ++CONFIG_MFD_SUPPORT=y + # CONFIG_MFD_CORE is not set + # CONFIG_MFD_SM501 is not set + # CONFIG_HTC_PASIC3 is not set + # CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_MC13XXX is not set ++# CONFIG_ABX500_CORE is not set + # CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-# CONFIG_VIDEO_DEV is not set +-# CONFIG_DVB_CORE is not set +-# CONFIG_VIDEO_MEDIA is not set +- +-# +-# Multimedia drivers +-# +-CONFIG_DAB=y +-# CONFIG_USB_DABUSB is not set ++# CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++# CONFIG_DRM is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=m + # CONFIG_FB is not set +@@ -705,7 +806,6 @@ CONFIG_USB=y + CONFIG_USB_DEVICEFS=y + CONFIG_USB_DEVICE_CLASS=y + # CONFIG_USB_DYNAMIC_MINORS is not set +-CONFIG_USB_SUSPEND=y + CONFIG_USB_OTG=y + # CONFIG_USB_OTG_WHITELIST is not set + # CONFIG_USB_OTG_BLACKLIST_HUB is not set +@@ -723,16 +823,18 @@ CONFIG_USB_EHCI_ROOT_HUB_TT=y + CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y + CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y + CONFIG_USB_EHCI_FSL=y ++# CONFIG_USB_M5441X_PLLCLK is not set ++# CONFIG_USB_M5441X_H1 is not set ++CONFIG_USB_M5441X_ULPI=y ++# CONFIG_USB_M5441X_FSLS is not set ++# CONFIG_USB_M5441X_MAX3353_FSLS is not set + # CONFIG_USB_OXU210HP_HCD is not set + # CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set + # CONFIG_USB_SL811_HCD is not set + # CONFIG_USB_R8A66597_HCD is not set + # CONFIG_USB_HWA_HCD is not set +-# CONFIG_USB_M5445X_ULPI is not set +-# CONFIG_USB_M5445X_FSLS is not set +-CONFIG_USB_M5441X_ULPI=y +-# CONFIG_USB_M5441X_FSLS is not set +-# CONFIG_USB_GADGET_MUSB_HDRC is not set + + # + # USB Device Class drivers +@@ -743,11 +845,11 @@ CONFIG_USB_M5441X_ULPI=y + # CONFIG_USB_TMC is not set + + # +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may + # + + # +-# see USB_STORAGE Help for more information ++# also be needed; see USB_STORAGE Help for more info + # + CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_DEBUG is not set +@@ -762,6 +864,7 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_ONETOUCH is not set + # CONFIG_USB_STORAGE_KARMA is not set + # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_UAS is not set + # CONFIG_USB_LIBUSUAL is not set + + # +@@ -785,11 +888,9 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_RIO500 is not set + # CONFIG_USB_LEGOTOWER is not set + # CONFIG_USB_LCD is not set +-# CONFIG_USB_BERRY_CHARGE is not set + # CONFIG_USB_LED is not set + # CONFIG_USB_CYPRESS_CY7C63 is not set + # CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_PHIDGET is not set + # CONFIG_USB_IDMOUSE is not set + # CONFIG_USB_FTDI_ELAN is not set + # CONFIG_USB_APPLEDISPLAY is not set +@@ -799,50 +900,47 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_IOWARRIOR is not set + # CONFIG_USB_TEST is not set + # CONFIG_USB_ISIGHTFW is not set +-# CONFIG_USB_VST is not set ++# CONFIG_USB_YUREX is not set + CONFIG_USB_GADGET=m + # CONFIG_USB_GADGET_DEBUG_FILES is not set + CONFIG_USB_GADGET_VBUS_DRAW=2 + CONFIG_USB_GADGET_SELECTED=y +-# CONFIG_USB_GADGET_AT91 is not set +-# CONFIG_USB_GADGET_ATMEL_USBA is not set + CONFIG_USB_GADGET_FSL_USB2=y + CONFIG_USB_FSL_USB2=m +-# CONFIG_USB_GADGET_LH7A40X is not set +-# CONFIG_USB_GADGET_OMAP is not set +-# CONFIG_USB_GADGET_PXA25X is not set +-# CONFIG_USB_GADGET_PXA27X is not set +-# CONFIG_USB_GADGET_S3C2410 is not set +-# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_R8A66597 is not set ++# CONFIG_USB_GADGET_PXA_U2O is not set + # CONFIG_USB_GADGET_M66592 is not set +-# CONFIG_USB_GADGET_AMD5536UDC is not set +-# CONFIG_USB_GADGET_FSL_QE is not set +-# CONFIG_USB_GADGET_CI13XXX is not set +-# CONFIG_USB_GADGET_NET2280 is not set +-# CONFIG_USB_GADGET_GOKU is not set + # CONFIG_USB_GADGET_DUMMY_HCD is not set + CONFIG_USB_GADGET_DUALSPEED=y + # CONFIG_USB_ZERO is not set + # CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set + CONFIG_USB_GADGETFS=m ++# CONFIG_USB_FUNCTIONFS is not set + CONFIG_USB_FILE_STORAGE=m + CONFIG_USB_FILE_STORAGE_TEST=y ++# CONFIG_USB_MASS_STORAGE is not set + # CONFIG_USB_G_SERIAL is not set +-# CONFIG_USB_MIDI_GADGET is not set + # CONFIG_USB_G_PRINTER is not set + # CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set + + # + # OTG and related infrastructure + # ++# CONFIG_NOP_USB_XCEIV is not set + CONFIG_MMC=y + # CONFIG_MMC_DEBUG is not set + # CONFIG_MMC_UNSAFE_RESUME is not set ++# CONFIG_MMC_CLKGATE is not set + + # + # MMC/SD/SDIO Card Drivers + # + CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 + CONFIG_MMC_BLOCK_BOUNCE=y + # CONFIG_SDIO_UART is not set + # CONFIG_MMC_TEST is not set +@@ -853,8 +951,10 @@ CONFIG_MMC_BLOCK_BOUNCE=y + # CONFIG_MMC_SDHCI is not set + # CONFIG_MMC_SPI is not set + # CONFIG_MMC_ESDHC is not set ++# CONFIG_MMC_USHC is not set + # CONFIG_MEMSTICK is not set + # CONFIG_NEW_LEDS is not set ++# CONFIG_NFC_DEVICES is not set + # CONFIG_ACCESSIBILITY is not set + CONFIG_RTC_LIB=y + CONFIG_RTC_CLASS=y +@@ -881,6 +981,7 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_R9701 is not set + # CONFIG_RTC_DRV_RS5C348 is not set + # CONFIG_RTC_DRV_DS3234 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set + + # + # Platform RTC drivers +@@ -893,21 +994,27 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_M48T86 is not set + # CONFIG_RTC_DRV_M48T35 is not set + # CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set + # CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set + # CONFIG_RTC_DRV_V3020 is not set + + # + # on-CPU RTC drivers + # ++# CONFIG_RTC_DRV_GENERIC is not set + # CONFIG_RTC_MCF is not set + CONFIG_RTC_M5441X=y + CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set + + # + # DMA Devices + # + CONFIG_COLDFIRE_EDMA=y + CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_TIMB_DMA is not set ++# CONFIG_AUXDISPLAY is not set + # CONFIG_UIO is not set + # CONFIG_STAGING is not set + +@@ -926,6 +1033,7 @@ CONFIG_EXT2_FS=y + # CONFIG_EXT2_FS_XATTR is not set + # CONFIG_EXT2_FS_XIP is not set + CONFIG_EXT3_FS=y ++CONFIG_EXT3_DEFAULTS_TO_ORDERED=y + CONFIG_EXT3_FS_XATTR=y + # CONFIG_EXT3_FS_POSIX_ACL is not set + # CONFIG_EXT3_FS_SECURITY is not set +@@ -934,21 +1042,27 @@ CONFIG_JBD=y + CONFIG_FS_MBCACHE=y + # CONFIG_REISERFS_FS is not set + # CONFIG_JFS_FS is not set +-# CONFIG_FS_POSIX_ACL is not set +-CONFIG_FILE_LOCKING=y + # CONFIG_XFS_FS is not set + # CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set + # CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y + CONFIG_DNOTIFY=y +-CONFIG_INOTIFY=y + CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set + # CONFIG_QUOTA is not set +-# CONFIG_AUTOFS_FS is not set ++# CONFIG_QUOTACTL is not set + # CONFIG_AUTOFS4_FS is not set + # CONFIG_FUSE_FS is not set + + # ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# + # CD-ROM/DVD Filesystems + # + # CONFIG_ISO9660_FS is not set +@@ -986,6 +1100,7 @@ CONFIG_MISC_FILESYSTEMS=y + # CONFIG_BEFS_FS is not set + # CONFIG_BFS_FS is not set + # CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set + CONFIG_JFFS2_FS=y + CONFIG_JFFS2_FS_DEBUG=0 + CONFIG_JFFS2_FS_WRITEBUFFER=y +@@ -997,6 +1112,7 @@ CONFIG_JFFS2_ZLIB=y + # CONFIG_JFFS2_LZO is not set + CONFIG_JFFS2_RTIME=y + # CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set + # CONFIG_CRAMFS is not set + # CONFIG_SQUASHFS is not set + # CONFIG_VXFS_FS is not set +@@ -1016,10 +1132,8 @@ CONFIG_ROOT_NFS=y + CONFIG_LOCKD=y + CONFIG_NFS_COMMON=y + CONFIG_SUNRPC=y +-# CONFIG_SUNRPC_REGISTER_V4 is not set + # CONFIG_RPCSEC_GSS_KRB5 is not set +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-# CONFIG_SMB_FS is not set ++# CONFIG_CEPH_FS is not set + # CONFIG_CIFS is not set + # CONFIG_NCP_FS is not set + # CONFIG_CODA_FS is not set +@@ -1086,7 +1200,6 @@ CONFIG_NLS_ISO8859_1=y + # CONFIG_NLS_KOI8_R is not set + # CONFIG_NLS_KOI8_U is not set + CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set + + # + # Kernel hacking +@@ -1096,19 +1209,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y + # CONFIG_ENABLE_MUST_CHECK is not set + CONFIG_FRAME_WARN=1024 + # CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set + # CONFIG_UNUSED_SYMBOLS is not set + # CONFIG_DEBUG_FS is not set + # CONFIG_HEADERS_CHECK is not set + # CONFIG_DEBUG_KERNEL is not set +-# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++CONFIG_BKL=y ++# CONFIG_SPARSE_RCU_POINTER is not set ++CONFIG_DEBUG_BUGVERBOSE=y + # CONFIG_DEBUG_MEMORY_INIT is not set +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set + # CONFIG_SYSCTL_SYSCALL_CHECK is not set +- +-# +-# Tracers +-# +-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set + # CONFIG_SAMPLES is not set + # CONFIG_BOOTPARAM is not set + +@@ -1116,15 +1228,16 @@ CONFIG_FRAME_WARN=1024 + # Security options + # + # CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set + # CONFIG_SECURITY is not set + # CONFIG_SECURITYFS is not set +-# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" + CONFIG_CRYPTO=y + + # + # Crypto core or helper + # +-# CONFIG_CRYPTO_FIPS is not set + CONFIG_CRYPTO_ALGAPI=y + CONFIG_CRYPTO_ALGAPI2=y + CONFIG_CRYPTO_AEAD=y +@@ -1134,10 +1247,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y + CONFIG_CRYPTO_HASH=y + CONFIG_CRYPTO_HASH2=y + CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y + CONFIG_CRYPTO_MANAGER=y + CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set + # CONFIG_CRYPTO_GF128MUL is not set + # CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y + # CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=y + CONFIG_CRYPTO_TEST=m +@@ -1165,11 +1281,13 @@ CONFIG_CRYPTO_PCBC=m + # + CONFIG_CRYPTO_HMAC=y + # CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set + + # + # Digest + # + CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set + # CONFIG_CRYPTO_MD4 is not set + CONFIG_CRYPTO_MD5=y + # CONFIG_CRYPTO_MICHAEL_MIC is not set +@@ -1186,7 +1304,7 @@ CONFIG_CRYPTO_SHA1=y + # + # Ciphers + # +-# CONFIG_CRYPTO_AES is not set ++CONFIG_CRYPTO_AES=y + # CONFIG_CRYPTO_ANUBIS is not set + # CONFIG_CRYPTO_ARC4 is not set + # CONFIG_CRYPTO_BLOWFISH is not set +@@ -1206,23 +1324,22 @@ CONFIG_CRYPTO_DES=y + # Compression + # + # CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set + # CONFIG_CRYPTO_LZO is not set + + # + # Random Number Generation + # + # CONFIG_CRYPTO_ANSI_CPRNG is not set +- +-# +-# OCF Configuration +-# +-# CONFIG_OCF_OCF is not set +- +-# +-# Talitos Driver +-# ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set + CONFIG_CRYPTO_HW=y +-# CONFIG_CRYPTO_DEV_MCFCAU is not set ++CONFIG_CRYPTO_DEV_MCFCAU=y ++CONFIG_CRYPTO_DEV_MCFCAU_DES=y ++CONFIG_CRYPTO_DEV_MCFCAU_AES=y ++CONFIG_CRYPTO_DEV_MCFCAU_MD5=y ++CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y ++# CONFIG_BINARY_PRINTF is not set + + # + # Library routines +@@ -1238,7 +1355,12 @@ CONFIG_CRC7=y + CONFIG_LIBCRC32C=y + CONFIG_ZLIB_INFLATE=y + CONFIG_ZLIB_DEFLATE=y +-CONFIG_PLIST=y ++# CONFIG_XZ_DEC is not set ++# CONFIG_XZ_DEC_BCJ is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_GENERIC_ALLOCATOR=y + CONFIG_HAS_IOMEM=y + CONFIG_HAS_IOPORT=y + CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y +--- a/arch/m68k/configs/m54451evb_defconfig ++++ b/arch/m68k/configs/m54451evb_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit +-# Linux kernel version: 2.6.29 +-# Tue Aug 24 16:14:20 2010 ++# Linux kernel version: 2.6.38 ++# Tue Aug 2 16:20:36 2011 + # + CONFIG_M68K=y + CONFIG_MMU=y +@@ -17,7 +17,9 @@ CONFIG_GENERIC_IOMAP=y + # CONFIG_NO_IOPORT is not set + # CONFIG_NO_DMA is not set + CONFIG_HZ=100 ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_CONSTRUCTORS=y + + # + # General setup +@@ -25,6 +27,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNA + CONFIG_EXPERIMENTAL=y + CONFIG_BROKEN_ON_SMP=y + CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" + CONFIG_LOCALVERSION="" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SWAP=y +@@ -34,38 +37,40 @@ CONFIG_SYSVIPC_SYSCTL=y + # CONFIG_BSD_PROCESS_ACCT is not set + # CONFIG_TASKSTATS is not set + # CONFIG_AUDIT is not set ++# CONFIG_HAVE_GENERIC_HARDIRQS is not set + + # + # RCU Subsystem + # +-CONFIG_CLASSIC_RCU=y +-# CONFIG_TREE_RCU is not set ++CONFIG_TINY_RCU=y + # CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set + # CONFIG_TREE_RCU_TRACE is not set +-# CONFIG_PREEMPT_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=17 +-CONFIG_GROUP_SCHED=y +-CONFIG_FAIR_GROUP_SCHED=y +-# CONFIG_RT_GROUP_SCHED is not set +-CONFIG_USER_SCHED=y +-# CONFIG_CGROUP_SCHED is not set + # CONFIG_CGROUPS is not set +-CONFIG_SYSFS_DEPRECATED=y +-CONFIG_SYSFS_DEPRECATED_V2=y +-# CONFIG_RELAY is not set + CONFIG_NAMESPACES=y + # CONFIG_UTS_NS is not set + # CONFIG_IPC_NS is not set + # CONFIG_USER_NS is not set + # CONFIG_PID_NS is not set + # CONFIG_NET_NS is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set + CONFIG_BLK_DEV_INITRD=y + CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set + CONFIG_SYSCTL=y + CONFIG_ANON_INODES=y ++CONFIG_EXPERT=y + CONFIG_EMBEDDED=y + CONFIG_UID16=y + CONFIG_SYSCTL_SYSCALL=y +@@ -83,12 +88,20 @@ CONFIG_TIMERFD=y + CONFIG_EVENTFD=y + CONFIG_SHMEM=y + CONFIG_AIO=y ++ ++# ++# Kernel Performance Events And Counters ++# + CONFIG_VM_EVENT_COUNTERS=y + CONFIG_COMPAT_BRK=y + CONFIG_SLAB=y + # CONFIG_SLUB is not set + # CONFIG_SLOB is not set + # CONFIG_PROFILING is not set ++ ++# ++# GCOV-based kernel profiling ++# + # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set + CONFIG_SLABINFO=y + CONFIG_RT_MUTEXES=y +@@ -100,8 +113,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y + # CONFIG_MODVERSIONS is not set + # CONFIG_MODULE_SRCVERSION_ALL is not set + CONFIG_BLOCK=y +-CONFIG_LBD=y +-# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_BLK_DEV_INTEGRITY is not set + +@@ -109,14 +121,41 @@ CONFIG_LBD=y + # IO Schedulers + # + CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y + CONFIG_IOSCHED_DEADLINE=y + CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set + # CONFIG_DEFAULT_DEADLINE is not set + CONFIG_DEFAULT_CFQ=y + # CONFIG_DEFAULT_NOOP is not set + CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set + # CONFIG_FREEZER is not set + + # +@@ -170,18 +209,19 @@ CONFIG_SINGLE_MEMORY_CHUNK=y + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set + CONFIG_SELECT_MEMORY_MODEL=y + CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set + CONFIG_FLATMEM=y + CONFIG_FLAT_NODE_MEM_MAP=y + CONFIG_NEED_MULTIPLE_NODES=y + CONFIG_PAGEFLAGS_EXTENDED=y + CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set + # CONFIG_PHYS_ADDR_T_64BIT is not set + CONFIG_ZONE_DMA_FLAG=1 + CONFIG_BOUNCE=y + CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y + + # + # General setup +@@ -204,9 +244,7 @@ CONFIG_NET=y + # + # Networking options + # +-CONFIG_COMPAT_NET_DEV_OPS=y + CONFIG_PACKET=y +-# CONFIG_PACKET_MMAP is not set + CONFIG_UNIX=y + CONFIG_XFRM=y + # CONFIG_XFRM_USER is not set +@@ -229,7 +267,7 @@ CONFIG_IP_PNP=y + # CONFIG_IP_PNP_BOOTP is not set + # CONFIG_IP_PNP_RARP is not set + # CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE is not set ++# CONFIG_NET_IPGRE_DEMUX is not set + # CONFIG_ARPD is not set + # CONFIG_SYN_COOKIES is not set + CONFIG_INET_AH=y +@@ -249,11 +287,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set + # CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set + # CONFIG_NETFILTER is not set + # CONFIG_IP_DCCP is not set + # CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set + # CONFIG_TIPC is not set + # CONFIG_ATM is not set ++# CONFIG_L2TP is not set + # CONFIG_BRIDGE is not set + # CONFIG_NET_DSA is not set + # CONFIG_VLAN_8021Q is not set +@@ -265,8 +306,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_LAPB is not set + # CONFIG_ECONET is not set + # CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set + # CONFIG_NET_SCHED is not set + # CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set + + # + # Network testing +@@ -277,17 +321,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_IRDA is not set + # CONFIG_BT is not set + # CONFIG_AF_RXRPC is not set +-# CONFIG_PHONET is not set + CONFIG_WIRELESS=y + # CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-# CONFIG_WIRELESS_EXT is not set + # CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++ ++# ++# Some wireless drivers require a rate control algorithm ++# + # CONFIG_WIMAX is not set + # CONFIG_RFKILL is not set + # CONFIG_NET_9P is not set +-# CONFIG_KLIPS is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set + + # + # Device Drivers +@@ -297,6 +346,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y + # Generic Driver Options + # + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set + # CONFIG_STANDALONE is not set + CONFIG_PREVENT_FIRMWARE_BUILD=y + CONFIG_FW_LOADER=y +@@ -306,9 +356,9 @@ CONFIG_EXTRA_FIRMWARE="" + # CONFIG_CONNECTOR is not set + CONFIG_MTD=y + # CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_TESTS is not set + CONFIG_MTD_CONCAT=y + CONFIG_MTD_PARTITIONS=y +-# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_REDBOOT_PARTS is not set + CONFIG_MTD_CMDLINE_PARTS=y + # CONFIG_MTD_AR7_PARTS is not set +@@ -324,6 +374,7 @@ CONFIG_MTD_BLOCK=y + # CONFIG_INFTL is not set + # CONFIG_RFD_FTL is not set + # CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set + # CONFIG_MTD_OOPS is not set + + # +@@ -372,6 +423,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 + # + # CONFIG_MTD_DATAFLASH is not set + # CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SST25L is not set + # CONFIG_MTD_SLRAM is not set + # CONFIG_MTD_PHRAM is not set + # CONFIG_MTD_MTDRAM is not set +@@ -390,16 +442,16 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 + # LPDDR flash memory drivers + # + # CONFIG_MTD_LPDDR is not set +- +-# +-# UBI - Unsorted block images +-# + # CONFIG_MTD_UBI is not set + # CONFIG_PARPORT is not set + CONFIG_BLK_DEV=y + # CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y + # CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# + # CONFIG_BLK_DEV_NBD is not set + # CONFIG_BLK_DEV_UB is not set + CONFIG_BLK_DEV_RAM=y +@@ -409,9 +461,22 @@ CONFIG_BLK_DEV_RAM_SIZE=64000 + # CONFIG_CDROM_PKTCDVD is not set + # CONFIG_ATA_OVER_ETH is not set + # CONFIG_BLK_DEV_HD is not set ++# CONFIG_BLK_DEV_RBD is not set + CONFIG_MISC_DEVICES=y ++# CONFIG_AD525X_DPOT is not set + # CONFIG_ICS932S401 is not set + # CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085 is not set + # CONFIG_C2PORT is not set + + # +@@ -420,13 +485,20 @@ CONFIG_MISC_DEVICES=y + # CONFIG_EEPROM_AT24 is not set + # CONFIG_EEPROM_AT25 is not set + # CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set + # CONFIG_EEPROM_93CX6 is not set ++# CONFIG_IWMC3200TOP is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# + CONFIG_HAVE_IDE=y + # CONFIG_IDE is not set + + # + # SCSI device support + # ++CONFIG_SCSI_MOD=y + # CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y + CONFIG_SCSI_DMA=y +@@ -443,10 +515,6 @@ CONFIG_BLK_DEV_SD=y + # CONFIG_BLK_DEV_SR is not set + # CONFIG_CHR_DEV_SG is not set + # CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_CONSTANTS is not set + # CONFIG_SCSI_LOGGING is not set +@@ -459,15 +527,20 @@ CONFIG_SCSI_WAIT_SCAN=m + # CONFIG_SCSI_SPI_ATTRS is not set + # CONFIG_SCSI_FC_ATTRS is not set + # CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set + # CONFIG_SCSI_SAS_LIBSAS is not set + # CONFIG_SCSI_SRP_ATTRS is not set + CONFIG_SCSI_LOWLEVEL=y + # CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set + # CONFIG_LIBFC is not set ++# CONFIG_LIBFCOE is not set + # CONFIG_SCSI_DEBUG is not set + # CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set + # CONFIG_ATA is not set + # CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set + CONFIG_NETDEVICES=y + # CONFIG_DUMMY is not set + # CONFIG_BONDING is not set +@@ -475,6 +548,7 @@ CONFIG_NETDEVICES=y + # CONFIG_EQUALIZER is not set + # CONFIG_TUN is not set + # CONFIG_VETH is not set ++CONFIG_MII=y + CONFIG_PHYLIB=y + + # +@@ -489,19 +563,21 @@ CONFIG_PHYLIB=y + # CONFIG_SMSC_PHY is not set + # CONFIG_BROADCOM_PHY is not set + # CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_BCM63XX_PHY is not set + # CONFIG_ICPLUS_PHY is not set + # CONFIG_REALTEK_PHY is not set + # CONFIG_NATIONAL_PHY is not set + # CONFIG_NATIONAL8364x_PHY is not set + # CONFIG_NATIONAL8384x_PHY is not set +-CONFIG_MicrelKSZ8041_PHY=y + # CONFIG_STE10XP is not set + # CONFIG_LSI_ET1011C_PHY is not set ++CONFIG_MICREL_PHY=y + # CONFIG_FIXED_PHY is not set + # CONFIG_MDIO_BITBANG is not set + CONFIG_NET_ETHERNET=y +-CONFIG_MII=y ++# CONFIG_SMC91X is not set + # CONFIG_ENC28J60 is not set ++# CONFIG_ETHOC is not set + # CONFIG_DNET is not set + # CONFIG_IBM_NEW_EMAC_ZMII is not set + # CONFIG_IBM_NEW_EMAC_RGMII is not set +@@ -511,16 +587,14 @@ CONFIG_MII=y + # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set + # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set + # CONFIG_B44 is not set ++# CONFIG_KS8851 is not set ++# CONFIG_KS8851_MLL is not set + CONFIG_FEC=y + # CONFIG_NETDEV_1000 is not set + # CONFIG_NETDEV_10000 is not set +- +-# +-# Wireless LAN +-# +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set ++CONFIG_WLAN=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_HOSTAP is not set + + # + # Enable WiMAX (Networking options) to see the WiMAX drivers +@@ -531,21 +605,15 @@ CONFIG_FEC=y + # + # CONFIG_USB_CATC is not set + # CONFIG_USB_KAWETH is not set +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=m +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-# CONFIG_USB_NET_DM9601 is not set +-# CONFIG_USB_NET_SMSC95XX is not set +-# CONFIG_USB_NET_GL620A is not set +-# CONFIG_USB_NET_NET1080 is not set +-# CONFIG_USB_NET_PLUSB is not set +-# CONFIG_USB_NET_MCS7830 is not set +-# CONFIG_USB_NET_RNDIS_HOST is not set +-# CONFIG_USB_NET_CDC_SUBSET is not set +-# CONFIG_USB_NET_ZAURUS is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set + # CONFIG_WAN is not set ++ ++# ++# CAIF transport drivers ++# + # CONFIG_PPP is not set + # CONFIG_SLIP is not set + # CONFIG_NETCONSOLE is not set +@@ -560,6 +628,7 @@ CONFIG_USB_NET_CDCETHER=m + CONFIG_INPUT=y + # CONFIG_INPUT_FF_MEMLESS is not set + # CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set + + # + # Userland interfaces +@@ -576,12 +645,18 @@ CONFIG_INPUT_EVDEV=y + # Input Device Drivers + # + CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set + # CONFIG_KEYBOARD_ATKBD is not set +-# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_QT2160 is not set + # CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set + # CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set + # CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_INPUT_MOUSE is not set + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set +@@ -595,6 +670,8 @@ CONFIG_SERIO=y + CONFIG_SERIO_SERPORT=y + # CONFIG_SERIO_LIBPS2 is not set + # CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set + # CONFIG_GAMEPORT is not set + + # +@@ -608,6 +685,7 @@ CONFIG_HW_CONSOLE=y + CONFIG_DEVKMEM=y + CONFIG_DEVSRAM=m + # CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set + + # + # Serial drivers +@@ -617,6 +695,8 @@ CONFIG_DEVSRAM=m + # + # Non-8250 serial port support + # ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX3107 is not set + CONFIG_SERIAL_CORE=y + CONFIG_SERIAL_CORE_CONSOLE=y + # CONFIG_SERIAL_COLDFIRE_IRDA is not set +@@ -624,17 +704,24 @@ CONFIG_SERIAL_CORE_CONSOLE=y + CONFIG_SERIAL_MCF=y + CONFIG_SERIAL_MCF_BAUDRATE=115200 + CONFIG_SERIAL_MCF_CONSOLE=y ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set + CONFIG_UNIX98_PTYS=y + # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set ++# CONFIG_TTY_PRINTK is not set + # CONFIG_IPMI_HANDLER is not set + # CONFIG_HW_RANDOM is not set + # CONFIG_R3964 is not set + # CONFIG_RAW_DRIVER is not set + # CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set + CONFIG_I2C=y + CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y + CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set + CONFIG_I2C_HELPER_AUTO=y + + # +@@ -646,7 +733,9 @@ CONFIG_I2C_HELPER_AUTO=y + # + CONFIG_I2C_MCF=y + # CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set + + # + # External I2C/SMBus adapter drivers +@@ -658,23 +747,10 @@ CONFIG_I2C_MCF=y + # + # Other I2C/SMBus bus drivers + # +-# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_STUB is not set +- +-# +-# Miscellaneous I2C Chip support +-# +-# CONFIG_DS1682 is not set +-# CONFIG_SENSORS_PCF8574 is not set +-# CONFIG_PCF8575 is not set +-# CONFIG_SENSORS_PCA9539 is not set +-# CONFIG_SENSORS_PCF8591 is not set +-# CONFIG_SENSORS_MAX6875 is not set +-# CONFIG_SENSORS_TSL2550 is not set + # CONFIG_I2C_DEBUG_CORE is not set + # CONFIG_I2C_DEBUG_ALGO is not set + # CONFIG_I2C_DEBUG_BUS is not set +-# CONFIG_I2C_DEBUG_CHIP is not set + CONFIG_SPI=y + CONFIG_SPI_MASTER=y + +@@ -686,17 +762,28 @@ CONFIG_SPI_DSPI=y + CONFIG_SPI_COLDFIRE_DSPI_EDMA=y + # CONFIG_VOIP_FXS is not set + # CONFIG_VOIP_FXO is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set + + # + # SPI Protocol Masters + # + # CONFIG_SPI_SPIDEV is not set + # CONFIG_SPI_TLE62X0 is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# + # CONFIG_W1 is not set + # CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set + # CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set + CONFIG_WATCHDOG=y + # CONFIG_WATCHDOG_NOWAYOUT is not set + +@@ -716,40 +803,26 @@ CONFIG_SSB_POSSIBLE=y + # Sonics Silicon Backplane + # + # CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# ++CONFIG_MFD_SUPPORT=y + # CONFIG_MFD_CORE is not set + # CONFIG_MFD_SM501 is not set + # CONFIG_HTC_PASIC3 is not set ++# CONFIG_TPS6507X is not set + # CONFIG_MFD_TMIO is not set + # CONFIG_PMIC_DA903X is not set ++# CONFIG_PMIC_ADP5520 is not set + # CONFIG_MFD_WM8400 is not set +-# CONFIG_MFD_WM8350_I2C is not set + # CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_MC13XXX is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set + # CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-# CONFIG_VIDEO_DEV is not set +-# CONFIG_DVB_CORE is not set +-# CONFIG_VIDEO_MEDIA is not set +- +-# +-# Multimedia drivers +-# +-CONFIG_DAB=y +-# CONFIG_USB_DABUSB is not set ++# CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++# CONFIG_DRM is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=m + # CONFIG_FB is not set +@@ -766,6 +839,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m + CONFIG_DUMMY_CONSOLE=y + CONFIG_SOUND=y + CONFIG_SOUND_OSS_CORE=y ++CONFIG_SOUND_OSS_CORE_PRECLAIM=y + CONFIG_SND=y + CONFIG_SND_TIMER=y + CONFIG_SND_PCM=y +@@ -780,8 +854,14 @@ CONFIG_SND_SUPPORT_OLD_API=y + CONFIG_SND_VERBOSE_PROCFS=y + # CONFIG_SND_VERBOSE_PRINTK is not set + # CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set + CONFIG_SND_DRIVERS=y + # CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set + # CONFIG_SND_MTPAV is not set + # CONFIG_SND_SERIAL_U16550 is not set + # CONFIG_SND_MPU401 is not set +@@ -793,12 +873,12 @@ CONFIG_SND_COLDFIRE=y + CONFIG_SND_SPI=y + CONFIG_SND_USB=y + # CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set + # CONFIG_SND_USB_CAIAQ is not set + # CONFIG_SND_SOC is not set + # CONFIG_SOUND_PRIME is not set + CONFIG_HID_SUPPORT=y + CONFIG_HID=y +-# CONFIG_HID_DEBUG is not set + # CONFIG_HIDRAW is not set + + # +@@ -811,43 +891,65 @@ CONFIG_USB_HID=y + # + # Special HID drivers + # +-CONFIG_HID_COMPAT=y ++# CONFIG_HID_3M_PCT is not set + # CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX_FF is not set + # CONFIG_HID_APPLE is not set + # CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CANDO is not set + # CONFIG_HID_CHERRY is not set + # CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set + # CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_EGALAX is not set + # CONFIG_HID_EZKEY is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set + # CONFIG_HID_GYRATION is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set + # CONFIG_HID_LOGITECH is not set + # CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MOSART is not set + # CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set + # CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set + # CONFIG_HID_PANTHERLORD is not set + # CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_QUANTA is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_ROCCAT_KONE is not set ++# CONFIG_HID_ROCCAT_KONEPLUS is not set ++# CONFIG_HID_ROCCAT_PYRA is not set + # CONFIG_HID_SAMSUNG is not set + # CONFIG_HID_SONY is not set ++# CONFIG_HID_STANTUM is not set + # CONFIG_HID_SUNPLUS is not set +-# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set + # CONFIG_HID_TOPSEED is not set +-# CONFIG_THRUSTMASTER_FF is not set +-# CONFIG_ZEROPLUS_FF is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set + CONFIG_USB_SUPPORT=y + CONFIG_USB_ARCH_HAS_HCD=y + # CONFIG_USB_ARCH_HAS_OHCI is not set + CONFIG_USB_ARCH_HAS_EHCI=y + CONFIG_USB=y + # CONFIG_USB_DEBUG is not set +-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + + # + # Miscellaneous USB options + # +-CONFIG_USB_DEVICEFS=y +-# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DEVICEFS is not set ++CONFIG_USB_DEVICE_CLASS=y + # CONFIG_USB_DYNAMIC_MINORS is not set +-CONFIG_USB_SUSPEND=y + CONFIG_USB_OTG=y + # CONFIG_USB_OTG_WHITELIST is not set + # CONFIG_USB_OTG_BLACKLIST_HUB is not set +@@ -861,20 +963,18 @@ CONFIG_USB_OTG=y + # CONFIG_USB_C67X00_HCD is not set + CONFIG_USB_EHCI_HCD=m + CONFIG_USB_EHCI_ROOT_HUB_TT=y +-# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_TT_NEWSCHED=y + CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y + CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y + CONFIG_USB_EHCI_FSL=y ++CONFIG_USB_M5445X_ULPI=y + # CONFIG_USB_OXU210HP_HCD is not set + # CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set + # CONFIG_USB_SL811_HCD is not set + # CONFIG_USB_R8A66597_HCD is not set + # CONFIG_USB_HWA_HCD is not set +-CONFIG_USB_M5445X_ULPI=y +-# CONFIG_USB_M5445X_FSLS is not set +-# CONFIG_USB_M5441X_ULPI is not set +-# CONFIG_USB_M5441X_FSLS is not set +-# CONFIG_USB_GADGET_MUSB_HDRC is not set + + # + # USB Device Class drivers +@@ -885,11 +985,11 @@ CONFIG_USB_M5445X_ULPI=y + # CONFIG_USB_TMC is not set + + # +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may + # + + # +-# see USB_STORAGE Help for more information ++# also be needed; see USB_STORAGE Help for more info + # + CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_DEBUG is not set +@@ -904,6 +1004,7 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_ONETOUCH is not set + # CONFIG_USB_STORAGE_KARMA is not set + # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_UAS is not set + # CONFIG_USB_LIBUSUAL is not set + + # +@@ -927,11 +1028,9 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_RIO500 is not set + # CONFIG_USB_LEGOTOWER is not set + # CONFIG_USB_LCD is not set +-# CONFIG_USB_BERRY_CHARGE is not set + # CONFIG_USB_LED is not set + # CONFIG_USB_CYPRESS_CY7C63 is not set + # CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_PHIDGET is not set + # CONFIG_USB_IDMOUSE is not set + # CONFIG_USB_FTDI_ELAN is not set + # CONFIG_USB_APPLEDISPLAY is not set +@@ -941,51 +1040,51 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_IOWARRIOR is not set + # CONFIG_USB_TEST is not set + # CONFIG_USB_ISIGHTFW is not set +-# CONFIG_USB_VST is not set ++# CONFIG_USB_YUREX is not set + CONFIG_USB_GADGET=m + # CONFIG_USB_GADGET_DEBUG_FILES is not set + CONFIG_USB_GADGET_VBUS_DRAW=2 + CONFIG_USB_GADGET_SELECTED=y +-# CONFIG_USB_GADGET_AT91 is not set +-# CONFIG_USB_GADGET_ATMEL_USBA is not set +-CONFIG_USB_GADGET_FSL_USB2=y +-CONFIG_USB_FSL_USB2=m +-# CONFIG_USB_GADGET_LH7A40X is not set +-# CONFIG_USB_GADGET_OMAP is not set +-# CONFIG_USB_GADGET_PXA25X is not set +-# CONFIG_USB_GADGET_PXA27X is not set +-# CONFIG_USB_GADGET_S3C2410 is not set +-# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++CONFIG_USB_GADGET_R8A66597=y ++CONFIG_USB_R8A66597=m ++# CONFIG_USB_GADGET_PXA_U2O is not set + # CONFIG_USB_GADGET_M66592 is not set +-# CONFIG_USB_GADGET_AMD5536UDC is not set +-# CONFIG_USB_GADGET_FSL_QE is not set +-# CONFIG_USB_GADGET_CI13XXX is not set +-# CONFIG_USB_GADGET_NET2280 is not set +-# CONFIG_USB_GADGET_GOKU is not set + # CONFIG_USB_GADGET_DUMMY_HCD is not set + CONFIG_USB_GADGET_DUALSPEED=y + # CONFIG_USB_ZERO is not set ++# CONFIG_USB_AUDIO is not set + CONFIG_USB_ETH=m + CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_ETH_EEM is not set ++# CONFIG_USB_G_NCM is not set + # CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set + CONFIG_USB_FILE_STORAGE=m + # CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_MASS_STORAGE is not set + # CONFIG_USB_G_SERIAL is not set + # CONFIG_USB_MIDI_GADGET is not set + # CONFIG_USB_G_PRINTER is not set + # CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set + + # + # OTG and related infrastructure + # ++# CONFIG_NOP_USB_XCEIV is not set + CONFIG_MMC=y + # CONFIG_MMC_DEBUG is not set + # CONFIG_MMC_UNSAFE_RESUME is not set ++# CONFIG_MMC_CLKGATE is not set + + # + # MMC/SD/SDIO Card Drivers + # + CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 + CONFIG_MMC_BLOCK_BOUNCE=y + CONFIG_SDIO_UART=y + # CONFIG_MMC_TEST is not set +@@ -996,8 +1095,10 @@ CONFIG_SDIO_UART=y + # CONFIG_MMC_SDHCI is not set + CONFIG_MMC_SPI=y + CONFIG_M54451_SD_HW_DETECT=y ++# CONFIG_MMC_USHC is not set + # CONFIG_MEMSTICK is not set + # CONFIG_NEW_LEDS is not set ++# CONFIG_NFC_DEVICES is not set + # CONFIG_ACCESSIBILITY is not set + CONFIG_RTC_LIB=y + CONFIG_RTC_CLASS=y +@@ -1020,16 +1121,20 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_DS1307 is not set + # CONFIG_RTC_DRV_DS1374 is not set + # CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set + # CONFIG_RTC_DRV_MAX6900 is not set + # CONFIG_RTC_DRV_RS5C372 is not set + # CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set + # CONFIG_RTC_DRV_X1205 is not set + # CONFIG_RTC_DRV_PCF8563 is not set + # CONFIG_RTC_DRV_PCF8583 is not set + # CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set + # CONFIG_RTC_DRV_S35390A is not set + # CONFIG_RTC_DRV_FM3130 is not set + # CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set + + # + # SPI RTC drivers +@@ -1041,6 +1146,7 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_R9701 is not set + # CONFIG_RTC_DRV_RS5C348 is not set + # CONFIG_RTC_DRV_DS3234 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set + + # + # Platform RTC drivers +@@ -1053,21 +1159,27 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_M48T86 is not set + # CONFIG_RTC_DRV_M48T35 is not set + # CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set + # CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set + # CONFIG_RTC_DRV_V3020 is not set + + # + # on-CPU RTC drivers + # ++# CONFIG_RTC_DRV_GENERIC is not set + CONFIG_RTC_MCF=y + # CONFIG_RTC_M5441X is not set + CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set + + # + # DMA Devices + # + CONFIG_COLDFIRE_EDMA=y + CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_TIMB_DMA is not set ++# CONFIG_AUXDISPLAY is not set + # CONFIG_UIO is not set + # CONFIG_STAGING is not set + +@@ -1086,6 +1198,7 @@ CONFIG_EXT2_FS=y + # CONFIG_EXT2_FS_XATTR is not set + # CONFIG_EXT2_FS_XIP is not set + CONFIG_EXT3_FS=y ++CONFIG_EXT3_DEFAULTS_TO_ORDERED=y + CONFIG_EXT3_FS_XATTR=y + # CONFIG_EXT3_FS_POSIX_ACL is not set + # CONFIG_EXT3_FS_SECURITY is not set +@@ -1094,21 +1207,27 @@ CONFIG_JBD=y + CONFIG_FS_MBCACHE=y + # CONFIG_REISERFS_FS is not set + # CONFIG_JFS_FS is not set +-# CONFIG_FS_POSIX_ACL is not set +-CONFIG_FILE_LOCKING=y + # CONFIG_XFS_FS is not set + # CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set + # CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y + CONFIG_DNOTIFY=y +-CONFIG_INOTIFY=y + CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set + # CONFIG_QUOTA is not set +-# CONFIG_AUTOFS_FS is not set ++# CONFIG_QUOTACTL is not set + # CONFIG_AUTOFS4_FS is not set + # CONFIG_FUSE_FS is not set + + # ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# + # CD-ROM/DVD Filesystems + # + CONFIG_ISO9660_FS=y +@@ -1148,6 +1267,7 @@ CONFIG_MISC_FILESYSTEMS=y + # CONFIG_BEFS_FS is not set + # CONFIG_BFS_FS is not set + # CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set + CONFIG_JFFS2_FS=y + CONFIG_JFFS2_FS_DEBUG=0 + CONFIG_JFFS2_FS_WRITEBUFFER=y +@@ -1159,6 +1279,7 @@ CONFIG_JFFS2_ZLIB=y + # CONFIG_JFFS2_LZO is not set + CONFIG_JFFS2_RTIME=y + # CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set + # CONFIG_CRAMFS is not set + # CONFIG_SQUASHFS is not set + # CONFIG_VXFS_FS is not set +@@ -1180,10 +1301,8 @@ CONFIG_LOCKD=y + CONFIG_LOCKD_V4=y + CONFIG_NFS_COMMON=y + CONFIG_SUNRPC=y +-# CONFIG_SUNRPC_REGISTER_V4 is not set + # CONFIG_RPCSEC_GSS_KRB5 is not set +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-# CONFIG_SMB_FS is not set ++# CONFIG_CEPH_FS is not set + # CONFIG_CIFS is not set + # CONFIG_NCP_FS is not set + # CONFIG_CODA_FS is not set +@@ -1250,7 +1369,6 @@ CONFIG_NLS_ISO8859_1=y + # CONFIG_NLS_KOI8_R is not set + # CONFIG_NLS_KOI8_U is not set + CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set + + # + # Kernel hacking +@@ -1260,19 +1378,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y + # CONFIG_ENABLE_MUST_CHECK is not set + CONFIG_FRAME_WARN=1024 + # CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set + # CONFIG_UNUSED_SYMBOLS is not set + # CONFIG_DEBUG_FS is not set + # CONFIG_HEADERS_CHECK is not set + # CONFIG_DEBUG_KERNEL is not set +-# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++CONFIG_BKL=y ++# CONFIG_SPARSE_RCU_POINTER is not set ++CONFIG_DEBUG_BUGVERBOSE=y + # CONFIG_DEBUG_MEMORY_INIT is not set +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set + # CONFIG_SYSCTL_SYSCALL_CHECK is not set +- +-# +-# Tracers +-# +-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set + # CONFIG_SAMPLES is not set + # CONFIG_BOOTPARAM is not set + +@@ -1280,15 +1397,16 @@ CONFIG_FRAME_WARN=1024 + # Security options + # + # CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set + # CONFIG_SECURITY is not set + # CONFIG_SECURITYFS is not set +-# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" + CONFIG_CRYPTO=y + + # + # Crypto core or helper + # +-# CONFIG_CRYPTO_FIPS is not set + CONFIG_CRYPTO_ALGAPI=y + CONFIG_CRYPTO_ALGAPI2=y + CONFIG_CRYPTO_AEAD=y +@@ -1298,10 +1416,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y + CONFIG_CRYPTO_HASH=y + CONFIG_CRYPTO_HASH2=y + CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y + CONFIG_CRYPTO_MANAGER=y + CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set + # CONFIG_CRYPTO_GF128MUL is not set + # CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y + # CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=y + CONFIG_CRYPTO_TEST=m +@@ -1329,11 +1450,13 @@ CONFIG_CRYPTO_PCBC=m + # + CONFIG_CRYPTO_HMAC=y + # CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set + + # + # Digest + # + CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set + # CONFIG_CRYPTO_MD4 is not set + CONFIG_CRYPTO_MD5=y + # CONFIG_CRYPTO_MICHAEL_MIC is not set +@@ -1370,26 +1493,22 @@ CONFIG_CRYPTO_DES=y + # Compression + # + # CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set + # CONFIG_CRYPTO_LZO is not set + + # + # Random Number Generation + # + # CONFIG_CRYPTO_ANSI_CPRNG is not set +- +-# +-# OCF Configuration +-# +- +-# +-# Talitos Driver +-# ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set + CONFIG_CRYPTO_HW=y + CONFIG_CRYPTO_DEV_MCFCAU=y + CONFIG_CRYPTO_DEV_MCFCAU_DES=y + CONFIG_CRYPTO_DEV_MCFCAU_AES=y + CONFIG_CRYPTO_DEV_MCFCAU_MD5=y + CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y ++# CONFIG_BINARY_PRINTF is not set + + # + # Library routines +@@ -1405,8 +1524,12 @@ CONFIG_CRC7=y + CONFIG_LIBCRC32C=y + CONFIG_ZLIB_INFLATE=y + CONFIG_ZLIB_DEFLATE=y ++# CONFIG_XZ_DEC is not set ++# CONFIG_XZ_DEC_BCJ is not set ++CONFIG_DECOMPRESS_GZIP=y + CONFIG_GENERIC_ALLOCATOR=y +-CONFIG_PLIST=y + CONFIG_HAS_IOMEM=y + CONFIG_HAS_IOPORT=y + CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y +--- a/arch/m68k/configs/m54455evb_defconfig ++++ b/arch/m68k/configs/m54455evb_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit +-# Linux kernel version: 2.6.29 +-# Tue Aug 24 16:16:14 2010 ++# Linux kernel version: 2.6.38 ++# Thu Jul 14 16:21:08 2011 + # + CONFIG_M68K=y + CONFIG_MMU=y +@@ -17,7 +17,9 @@ CONFIG_GENERIC_IOMAP=y + # CONFIG_NO_IOPORT is not set + # CONFIG_NO_DMA is not set + CONFIG_HZ=100 ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_CONSTRUCTORS=y + + # + # General setup +@@ -25,6 +27,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNA + CONFIG_EXPERIMENTAL=y + CONFIG_BROKEN_ON_SMP=y + CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" + CONFIG_LOCALVERSION="" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SWAP=y +@@ -34,38 +37,40 @@ CONFIG_SYSVIPC_SYSCTL=y + # CONFIG_BSD_PROCESS_ACCT is not set + # CONFIG_TASKSTATS is not set + # CONFIG_AUDIT is not set ++# CONFIG_HAVE_GENERIC_HARDIRQS is not set + + # + # RCU Subsystem + # +-CONFIG_CLASSIC_RCU=y +-# CONFIG_TREE_RCU is not set ++CONFIG_TINY_RCU=y + # CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set + # CONFIG_TREE_RCU_TRACE is not set +-# CONFIG_PREEMPT_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=17 +-CONFIG_GROUP_SCHED=y +-CONFIG_FAIR_GROUP_SCHED=y +-# CONFIG_RT_GROUP_SCHED is not set +-CONFIG_USER_SCHED=y +-# CONFIG_CGROUP_SCHED is not set + # CONFIG_CGROUPS is not set +-CONFIG_SYSFS_DEPRECATED=y +-CONFIG_SYSFS_DEPRECATED_V2=y +-# CONFIG_RELAY is not set + CONFIG_NAMESPACES=y + # CONFIG_UTS_NS is not set + # CONFIG_IPC_NS is not set + # CONFIG_USER_NS is not set + # CONFIG_PID_NS is not set + # CONFIG_NET_NS is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set + CONFIG_BLK_DEV_INITRD=y + CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set + CONFIG_SYSCTL=y + CONFIG_ANON_INODES=y ++CONFIG_EXPERT=y + CONFIG_EMBEDDED=y + CONFIG_UID16=y + CONFIG_SYSCTL_SYSCALL=y +@@ -83,6 +88,10 @@ CONFIG_TIMERFD=y + CONFIG_EVENTFD=y + CONFIG_SHMEM=y + CONFIG_AIO=y ++ ++# ++# Kernel Performance Events And Counters ++# + CONFIG_VM_EVENT_COUNTERS=y + CONFIG_PCI_QUIRKS=y + CONFIG_COMPAT_BRK=y +@@ -90,6 +99,10 @@ CONFIG_SLAB=y + # CONFIG_SLUB is not set + # CONFIG_SLOB is not set + # CONFIG_PROFILING is not set ++ ++# ++# GCOV-based kernel profiling ++# + # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set + CONFIG_SLABINFO=y + CONFIG_RT_MUTEXES=y +@@ -101,8 +114,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y + # CONFIG_MODVERSIONS is not set + # CONFIG_MODULE_SRCVERSION_ALL is not set + CONFIG_BLOCK=y +-CONFIG_LBD=y +-# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_BLK_DEV_INTEGRITY is not set + +@@ -110,14 +122,41 @@ CONFIG_LBD=y + # IO Schedulers + # + CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y + CONFIG_IOSCHED_DEADLINE=y + CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set + # CONFIG_DEFAULT_DEADLINE is not set + CONFIG_DEFAULT_CFQ=y + # CONFIG_DEFAULT_NOOP is not set + CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set + # CONFIG_FREEZER is not set + + # +@@ -172,18 +211,19 @@ CONFIG_SINGLE_MEMORY_CHUNK=y + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set + CONFIG_SELECT_MEMORY_MODEL=y + CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set + CONFIG_FLATMEM=y + CONFIG_FLAT_NODE_MEM_MAP=y + CONFIG_NEED_MULTIPLE_NODES=y + CONFIG_PAGEFLAGS_EXTENDED=y + CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set + # CONFIG_PHYS_ADDR_T_64BIT is not set + CONFIG_ZONE_DMA_FLAG=1 + CONFIG_BOUNCE=y + CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y + + # + # General setup +@@ -196,8 +236,8 @@ CONFIG_HAVE_AOUT=y + CONFIG_PROC_HARDWARE=y + CONFIG_ZONE_DMA=y + # CONFIG_ARCH_SUPPORTS_MSI is not set +-CONFIG_PCI_LEGACY=y + # CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set + + # + # Power management options +@@ -208,9 +248,7 @@ CONFIG_NET=y + # + # Networking options + # +-CONFIG_COMPAT_NET_DEV_OPS=y + CONFIG_PACKET=y +-# CONFIG_PACKET_MMAP is not set + CONFIG_UNIX=y + CONFIG_XFRM=y + # CONFIG_XFRM_USER is not set +@@ -233,7 +271,7 @@ CONFIG_IP_PNP=y + # CONFIG_IP_PNP_BOOTP is not set + # CONFIG_IP_PNP_RARP is not set + # CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE is not set ++# CONFIG_NET_IPGRE_DEMUX is not set + # CONFIG_ARPD is not set + # CONFIG_SYN_COOKIES is not set + CONFIG_INET_AH=y +@@ -253,11 +291,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set + # CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set + # CONFIG_NETFILTER is not set + # CONFIG_IP_DCCP is not set + # CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set + # CONFIG_TIPC is not set + # CONFIG_ATM is not set ++# CONFIG_L2TP is not set + # CONFIG_BRIDGE is not set + # CONFIG_NET_DSA is not set + # CONFIG_VLAN_8021Q is not set +@@ -269,8 +310,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_LAPB is not set + # CONFIG_ECONET is not set + # CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set + # CONFIG_NET_SCHED is not set + # CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set + + # + # Network testing +@@ -281,17 +325,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_IRDA is not set + # CONFIG_BT is not set + # CONFIG_AF_RXRPC is not set +-# CONFIG_PHONET is not set + CONFIG_WIRELESS=y + # CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-# CONFIG_WIRELESS_EXT is not set + # CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++ ++# ++# Some wireless drivers require a rate control algorithm ++# + # CONFIG_WIMAX is not set + # CONFIG_RFKILL is not set + # CONFIG_NET_9P is not set +-# CONFIG_KLIPS is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set + + # + # Device Drivers +@@ -301,6 +350,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y + # Generic Driver Options + # + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set + # CONFIG_STANDALONE is not set + CONFIG_PREVENT_FIRMWARE_BUILD=y + CONFIG_FW_LOADER=y +@@ -310,9 +360,9 @@ CONFIG_EXTRA_FIRMWARE="" + # CONFIG_CONNECTOR is not set + CONFIG_MTD=y + # CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_CONCAT is not set + CONFIG_MTD_PARTITIONS=y +-# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_REDBOOT_PARTS is not set + CONFIG_MTD_CMDLINE_PARTS=y + # CONFIG_MTD_AR7_PARTS is not set +@@ -328,6 +378,7 @@ CONFIG_MTD_BLOCK=y + # CONFIG_INFTL is not set + # CONFIG_RFD_FTL is not set + # CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set + # CONFIG_MTD_OOPS is not set + + # +@@ -373,6 +424,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1 + # CONFIG_MTD_PMC551 is not set + # CONFIG_MTD_DATAFLASH is not set + # CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SST25L is not set + # CONFIG_MTD_SLRAM is not set + # CONFIG_MTD_PHRAM is not set + # CONFIG_MTD_MTDRAM is not set +@@ -391,10 +443,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1 + # LPDDR flash memory drivers + # + # CONFIG_MTD_LPDDR is not set +- +-# +-# UBI - Unsorted block images +-# + # CONFIG_MTD_UBI is not set + # CONFIG_PARPORT is not set + CONFIG_BLK_DEV=y +@@ -405,6 +453,10 @@ CONFIG_BLK_DEV=y + # CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y + # CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# + # CONFIG_BLK_DEV_NBD is not set + # CONFIG_BLK_DEV_SX8 is not set + # CONFIG_BLK_DEV_UB is not set +@@ -415,13 +467,27 @@ CONFIG_BLK_DEV_RAM_SIZE=64000 + # CONFIG_CDROM_PKTCDVD is not set + # CONFIG_ATA_OVER_ETH is not set + # CONFIG_BLK_DEV_HD is not set ++# CONFIG_BLK_DEV_RBD is not set + CONFIG_MISC_DEVICES=y ++# CONFIG_AD525X_DPOT is not set + # CONFIG_PHANTOM is not set + # CONFIG_SGI_IOC4 is not set + # CONFIG_TIFM_CORE is not set + # CONFIG_ICS932S401 is not set + # CONFIG_ENCLOSURE_SERVICES is not set + # CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085 is not set ++# CONFIG_PCH_PHUB is not set + # CONFIG_C2PORT is not set + + # +@@ -430,13 +496,20 @@ CONFIG_MISC_DEVICES=y + # CONFIG_EEPROM_AT24 is not set + # CONFIG_EEPROM_AT25 is not set + # CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set + # CONFIG_EEPROM_93CX6 is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# + CONFIG_HAVE_IDE=y + # CONFIG_IDE is not set + + # + # SCSI device support + # ++CONFIG_SCSI_MOD=y + # CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y + CONFIG_SCSI_DMA=y +@@ -453,10 +526,6 @@ CONFIG_BLK_DEV_SD=y + # CONFIG_BLK_DEV_SR is not set + CONFIG_CHR_DEV_SG=y + # CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_CONSTANTS is not set + # CONFIG_SCSI_LOGGING is not set +@@ -469,33 +538,41 @@ CONFIG_SCSI_WAIT_SCAN=m + # CONFIG_SCSI_SPI_ATTRS is not set + # CONFIG_SCSI_FC_ATTRS is not set + # CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set + # CONFIG_SCSI_SAS_LIBSAS is not set + # CONFIG_SCSI_SRP_ATTRS is not set + CONFIG_SCSI_LOWLEVEL=y + # CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_BNX2_ISCSI is not set ++# CONFIG_BE2ISCSI is not set + # CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_HPSA is not set + # CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_3W_SAS is not set + # CONFIG_SCSI_ACARD is not set + # CONFIG_SCSI_AACRAID is not set + # CONFIG_SCSI_AIC7XXX is not set + # CONFIG_SCSI_AIC7XXX_OLD is not set + # CONFIG_SCSI_AIC79XX is not set + # CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_MVSAS is not set + # CONFIG_SCSI_DPT_I2O is not set + # CONFIG_SCSI_ADVANSYS is not set + # CONFIG_SCSI_ARCMSR is not set + # CONFIG_MEGARAID_NEWGEN is not set + # CONFIG_MEGARAID_LEGACY is not set + # CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_MPT2SAS is not set + # CONFIG_SCSI_HPTIOP is not set + # CONFIG_LIBFC is not set ++# CONFIG_LIBFCOE is not set + # CONFIG_FCOE is not set + # CONFIG_SCSI_DMX3191D is not set + # CONFIG_SCSI_FUTURE_DOMAIN is not set + # CONFIG_SCSI_IPS is not set + # CONFIG_SCSI_INITIO is not set + # CONFIG_SCSI_INIA100 is not set +-# CONFIG_SCSI_MVSAS is not set + # CONFIG_SCSI_STEX is not set + # CONFIG_SCSI_SYM53C8XX_2 is not set + # CONFIG_SCSI_IPR is not set +@@ -507,82 +584,116 @@ CONFIG_SCSI_LOWLEVEL=y + # CONFIG_SCSI_DC390T is not set + # CONFIG_SCSI_NSP32 is not set + # CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_PMCRAID is not set ++# CONFIG_SCSI_PM8001 is not set + # CONFIG_SCSI_SRP is not set ++# CONFIG_SCSI_BFA_FC is not set + # CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set + CONFIG_ATA=y + # CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y + CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# + # CONFIG_SATA_AHCI is not set ++# CONFIG_SATA_AHCI_PLATFORM is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_SATA_ACARD_AHCI is not set + # CONFIG_SATA_SIL24 is not set + CONFIG_ATA_SFF=y +-# CONFIG_SATA_SVW is not set ++ ++# ++# SFF controllers with custom DMA interface ++# ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# + # CONFIG_ATA_PIIX is not set + # CONFIG_SATA_MV is not set + # CONFIG_SATA_NV is not set +-# CONFIG_PDC_ADMA is not set +-# CONFIG_SATA_QSTOR is not set + # CONFIG_SATA_PROMISE is not set +-# CONFIG_SATA_SX4 is not set + # CONFIG_SATA_SIL is not set + # CONFIG_SATA_SIS is not set ++# CONFIG_SATA_SVW is not set + # CONFIG_SATA_ULI is not set + # CONFIG_SATA_VIA is not set + # CONFIG_SATA_VITESSE is not set +-# CONFIG_SATA_INIC162X is not set ++ ++# ++# PATA SFF controllers with BMDMA ++# + # CONFIG_PATA_ALI is not set + # CONFIG_PATA_AMD is not set + # CONFIG_PATA_ARTOP is not set + # CONFIG_PATA_ATIIXP is not set +-# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_ATP867X is not set + # CONFIG_PATA_CMD64X is not set + # CONFIG_PATA_CS5520 is not set + # CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CS5536 is not set + # CONFIG_PATA_CYPRESS is not set + # CONFIG_PATA_EFAR is not set +-# CONFIG_ATA_GENERIC is not set + # CONFIG_PATA_HPT366 is not set + # CONFIG_PATA_HPT37X is not set + # CONFIG_PATA_HPT3X2N is not set + # CONFIG_PATA_HPT3X3 is not set +-# CONFIG_PATA_IT821X is not set + # CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_IT821X is not set + # CONFIG_PATA_JMICRON is not set +-# CONFIG_PATA_TRIFLEX is not set + # CONFIG_PATA_MARVELL is not set +-# CONFIG_PATA_MPIIX is not set +-# CONFIG_PATA_OLDPIIX is not set + # CONFIG_PATA_NETCELL is not set + # CONFIG_PATA_NINJA32 is not set +-# CONFIG_PATA_NS87410 is not set + # CONFIG_PATA_NS87415 is not set +-# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OLDPIIX is not set + # CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC2027X is not set + # CONFIG_PATA_PDC_OLD is not set + # CONFIG_PATA_RADISYS is not set +-# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_RDC is not set + # CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SCH is not set + # CONFIG_PATA_SERVERWORKS is not set +-# CONFIG_PATA_PDC2027X is not set + # CONFIG_PATA_SIL680 is not set + # CONFIG_PATA_SIS is not set ++# CONFIG_PATA_TOSHIBA is not set ++# CONFIG_PATA_TRIFLEX is not set + # CONFIG_PATA_VIA is not set + # CONFIG_PATA_WINBOND is not set +-# CONFIG_PATA_PLATFORM is not set +-# CONFIG_PATA_SCH is not set + CONFIG_PATA_FSL=y + CONFIG_FSL_PATA_USE_DMA=y +-# CONFIG_MD is not set +-# CONFIG_FUSION is not set + + # +-# IEEE 1394 (FireWire) support ++# PIO-only SFF controllers + # ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_PLATFORM is not set ++# CONFIG_PATA_RZ1000 is not set + + # +-# Enable only one of the two stacks, unless you know what you are doing ++# Generic fallback / legacy drivers ++# ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_LEGACY is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support + # + # CONFIG_FIREWIRE is not set +-# CONFIG_IEEE1394 is not set ++# CONFIG_FIREWIRE_NOSY is not set + # CONFIG_I2O is not set + CONFIG_NETDEVICES=y + # CONFIG_DUMMY is not set +@@ -592,6 +703,7 @@ CONFIG_NETDEVICES=y + # CONFIG_TUN is not set + # CONFIG_VETH is not set + # CONFIG_ARCNET is not set ++CONFIG_MII=y + CONFIG_PHYLIB=y + + # +@@ -606,23 +718,25 @@ CONFIG_PHYLIB=y + # CONFIG_SMSC_PHY is not set + # CONFIG_BROADCOM_PHY is not set + # CONFIG_BROADCOM5222_PHY is not set ++# CONFIG_BCM63XX_PHY is not set + # CONFIG_ICPLUS_PHY is not set + # CONFIG_REALTEK_PHY is not set + # CONFIG_NATIONAL_PHY is not set + # CONFIG_NATIONAL8364x_PHY is not set + CONFIG_NATIONAL8384x_PHY=y +-# CONFIG_MicrelKSZ8041_PHY is not set + # CONFIG_STE10XP is not set + # CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set + # CONFIG_FIXED_PHY is not set + # CONFIG_MDIO_BITBANG is not set + CONFIG_NET_ETHERNET=y +-CONFIG_MII=y + # CONFIG_HAPPYMEAL is not set + # CONFIG_SUNGEM is not set + # CONFIG_CASSINI is not set + # CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_SMC91X is not set + # CONFIG_ENC28J60 is not set ++# CONFIG_ETHOC is not set + # CONFIG_DNET is not set + # CONFIG_NET_TULIP is not set + # CONFIG_HP100 is not set +@@ -637,6 +751,7 @@ CONFIG_NET_PCI=y + # CONFIG_PCNET32 is not set + # CONFIG_AMD8111_ETH is not set + # CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_KSZ884X_PCI is not set + # CONFIG_B44 is not set + # CONFIG_FORCEDETH is not set + CONFIG_E100=y +@@ -655,6 +770,8 @@ CONFIG_8139TOO=y + # CONFIG_SMSC9420 is not set + # CONFIG_SUNDANCE is not set + # CONFIG_TLAN is not set ++# CONFIG_KS8851 is not set ++# CONFIG_KS8851_MLL is not set + # CONFIG_VIA_RHINE is not set + # CONFIG_SC92031 is not set + CONFIG_FEC=y +@@ -667,6 +784,7 @@ CONFIG_E1000=y + # CONFIG_E1000E is not set + # CONFIG_IP1000 is not set + # CONFIG_IGB is not set ++# CONFIG_IGBVF is not set + # CONFIG_NS83820 is not set + # CONFIG_HAMACHI is not set + # CONFIG_YELLOWFIN is not set +@@ -677,20 +795,21 @@ CONFIG_E1000=y + # CONFIG_VIA_VELOCITY is not set + # CONFIG_TIGON3 is not set + # CONFIG_BNX2 is not set ++# CONFIG_CNIC is not set + # CONFIG_QLA3XXX is not set + # CONFIG_ATL1 is not set + # CONFIG_ATL1E is not set + # CONFIG_ATL1C is not set + # CONFIG_JME is not set ++# CONFIG_STMMAC_ETH is not set ++# CONFIG_PCH_GBE is not set + # CONFIG_NETDEV_10000 is not set + # CONFIG_TR is not set +- +-# +-# Wireless LAN +-# +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set ++CONFIG_WLAN=y ++# CONFIG_ATMEL is not set ++# CONFIG_PRISM54 is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_HOSTAP is not set + + # + # Enable WiMAX (Networking options) to see the WiMAX drivers +@@ -704,7 +823,12 @@ CONFIG_E1000=y + # CONFIG_USB_PEGASUS is not set + CONFIG_USB_RTL8150=y + # CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set + # CONFIG_WAN is not set ++ ++# ++# CAIF transport drivers ++# + # CONFIG_FDDI is not set + # CONFIG_HIPPI is not set + # CONFIG_PPP is not set +@@ -713,6 +837,7 @@ CONFIG_USB_RTL8150=y + # CONFIG_NETCONSOLE is not set + # CONFIG_NETPOLL is not set + # CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_VMXNET3 is not set + # CONFIG_ISDN is not set + # CONFIG_PHONE is not set + +@@ -722,6 +847,7 @@ CONFIG_USB_RTL8150=y + CONFIG_INPUT=y + # CONFIG_INPUT_FF_MEMLESS is not set + # CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set + + # + # Userland interfaces +@@ -738,12 +864,18 @@ CONFIG_INPUT_EVDEV=y + # Input Device Drivers + # + CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set + # CONFIG_KEYBOARD_ATKBD is not set +-# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_QT2160 is not set + # CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set + # CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set + # CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_INPUT_MOUSE is not set + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set +@@ -758,6 +890,8 @@ CONFIG_SERIO_SERPORT=y + # CONFIG_SERIO_PCIPS2 is not set + # CONFIG_SERIO_LIBPS2 is not set + # CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set + # CONFIG_GAMEPORT is not set + + # +@@ -771,6 +905,7 @@ CONFIG_HW_CONSOLE=y + CONFIG_DEVKMEM=y + CONFIG_DEVSRAM=m + # CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set + # CONFIG_NOZOMI is not set + + # +@@ -781,6 +916,9 @@ CONFIG_DEVSRAM=m + # + # Non-8250 serial port support + # ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX3107 is not set ++# CONFIG_SERIAL_MFD_HSU is not set + CONFIG_SERIAL_CORE=y + CONFIG_SERIAL_CORE_CONSOLE=y + # CONFIG_SERIAL_COLDFIRE_IRDA is not set +@@ -789,9 +927,14 @@ CONFIG_SERIAL_MCF=y + CONFIG_SERIAL_MCF_BAUDRATE=115200 + CONFIG_SERIAL_MCF_CONSOLE=y + # CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_PCH_UART is not set + CONFIG_UNIX98_PTYS=y + # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set ++# CONFIG_TTY_PRINTK is not set + # CONFIG_IPMI_HANDLER is not set + # CONFIG_HW_RANDOM is not set + # CONFIG_GEN_RTC is not set +@@ -799,9 +942,12 @@ CONFIG_UNIX98_PTYS=y + # CONFIG_APPLICOM is not set + # CONFIG_RAW_DRIVER is not set + # CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set + CONFIG_I2C=y + CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y + CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set + CONFIG_I2C_HELPER_AUTO=y + + # +@@ -829,9 +975,13 @@ CONFIG_I2C_HELPER_AUTO=y + # + # I2C system bus drivers (mostly embedded / system-on-chip) + # ++# CONFIG_I2C_INTEL_MID is not set + CONFIG_I2C_MCF=y + # CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++# CONFIG_I2C_EG20T is not set + + # + # External I2C/SMBus adapter drivers +@@ -841,30 +991,12 @@ CONFIG_I2C_MCF=y + # CONFIG_I2C_TINY_USB is not set + + # +-# Graphics adapter I2C/DDC channel drivers +-# +-# CONFIG_I2C_VOODOO3 is not set +- +-# + # Other I2C/SMBus bus drivers + # +-# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_STUB is not set +- +-# +-# Miscellaneous I2C Chip support +-# +-# CONFIG_DS1682 is not set +-# CONFIG_SENSORS_PCF8574 is not set +-# CONFIG_PCF8575 is not set +-# CONFIG_SENSORS_PCA9539 is not set +-# CONFIG_SENSORS_PCF8591 is not set +-# CONFIG_SENSORS_MAX6875 is not set +-# CONFIG_SENSORS_TSL2550 is not set + # CONFIG_I2C_DEBUG_CORE is not set + # CONFIG_I2C_DEBUG_ALGO is not set + # CONFIG_I2C_DEBUG_BUS is not set +-# CONFIG_I2C_DEBUG_CHIP is not set + CONFIG_SPI=y + CONFIG_SPI_MASTER=y + +@@ -874,19 +1006,29 @@ CONFIG_SPI_MASTER=y + # CONFIG_SPI_BITBANG is not set + CONFIG_SPI_DSPI=y + CONFIG_SPI_COLDFIRE_DSPI_EDMA=y +-# CONFIG_VOIP_FXS is not set +-# CONFIG_VOIP_FXO is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_TOPCLIFF_PCH is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set + + # + # SPI Protocol Masters + # + # CONFIG_SPI_SPIDEV is not set + # CONFIG_SPI_TLE62X0 is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# + # CONFIG_W1 is not set + # CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set + # CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set + CONFIG_WATCHDOG=y + # CONFIG_WATCHDOG_NOWAYOUT is not set + +@@ -913,41 +1055,34 @@ CONFIG_SSB_POSSIBLE=y + # Sonics Silicon Backplane + # + # CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# ++CONFIG_MFD_SUPPORT=y + # CONFIG_MFD_CORE is not set + # CONFIG_MFD_SM501 is not set + # CONFIG_HTC_PASIC3 is not set ++# CONFIG_TPS6507X is not set + # CONFIG_MFD_TMIO is not set + # CONFIG_PMIC_DA903X is not set ++# CONFIG_PMIC_ADP5520 is not set + # CONFIG_MFD_WM8400 is not set +-# CONFIG_MFD_WM8350_I2C is not set + # CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_MC13XXX is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_CS5535 is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_WL1273_CORE is not set + # CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-# CONFIG_VIDEO_DEV is not set +-# CONFIG_DVB_CORE is not set +-# CONFIG_VIDEO_MEDIA is not set +- +-# +-# Multimedia drivers +-# +-CONFIG_DAB=y +-# CONFIG_USB_DABUSB is not set ++# CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 + # CONFIG_DRM is not set ++# CONFIG_STUB_POULSBO is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=m + # CONFIG_FB is not set +@@ -964,6 +1099,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m + CONFIG_DUMMY_CONSOLE=y + CONFIG_SOUND=y + CONFIG_SOUND_OSS_CORE=y ++CONFIG_SOUND_OSS_CORE_PRECLAIM=y + CONFIG_SND=y + CONFIG_SND_TIMER=y + CONFIG_SND_PCM=y +@@ -972,14 +1108,19 @@ CONFIG_SND_OSSEMUL=y + # CONFIG_SND_MIXER_OSS is not set + CONFIG_SND_PCM_OSS=y + CONFIG_SND_PCM_OSS_PLUGINS=y +-# CONFIG_SND_HRTIMER is not set + # CONFIG_SND_DYNAMIC_MINORS is not set + CONFIG_SND_SUPPORT_OLD_API=y + CONFIG_SND_VERBOSE_PROCFS=y + # CONFIG_SND_VERBOSE_PRINTK is not set + # CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set + CONFIG_SND_DRIVERS=y + # CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set + # CONFIG_SND_MTPAV is not set + # CONFIG_SND_SERIAL_U16550 is not set + # CONFIG_SND_MPU401 is not set +@@ -1000,6 +1141,8 @@ CONFIG_SND_PCI=y + # CONFIG_SND_OXYGEN is not set + # CONFIG_SND_CS4281 is not set + # CONFIG_SND_CS46XX is not set ++# CONFIG_SND_CS5535AUDIO is not set ++# CONFIG_SND_CTXFI is not set + # CONFIG_SND_DARLA20 is not set + # CONFIG_SND_GINA20 is not set + # CONFIG_SND_LAYLA20 is not set +@@ -1012,6 +1155,8 @@ CONFIG_SND_PCI=y + # CONFIG_SND_INDIGO is not set + # CONFIG_SND_INDIGOIO is not set + # CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set + # CONFIG_SND_EMU10K1 is not set + # CONFIG_SND_EMU10K1X is not set + # CONFIG_SND_ENS1370 is not set +@@ -1022,12 +1167,12 @@ CONFIG_SND_PCI=y + # CONFIG_SND_HDA_INTEL is not set + # CONFIG_SND_HDSP is not set + # CONFIG_SND_HDSPM is not set +-# CONFIG_SND_HIFIER is not set + # CONFIG_SND_ICE1712 is not set + # CONFIG_SND_ICE1724 is not set + # CONFIG_SND_INTEL8X0 is not set + # CONFIG_SND_INTEL8X0M is not set + # CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_LX6464ES is not set + # CONFIG_SND_MAESTRO3 is not set + # CONFIG_SND_MIXART is not set + # CONFIG_SND_NM256 is not set +@@ -1051,12 +1196,12 @@ CONFIG_SND_COLDFIRE=y + CONFIG_SND_SPI=y + CONFIG_SND_USB=y + # CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set + # CONFIG_SND_USB_CAIAQ is not set + # CONFIG_SND_SOC is not set + # CONFIG_SOUND_PRIME is not set + CONFIG_HID_SUPPORT=y + CONFIG_HID=y +-CONFIG_HID_DEBUG=y + # CONFIG_HIDRAW is not set + + # +@@ -1069,28 +1214,51 @@ CONFIG_USB_HID=y + # + # Special HID drivers + # +-CONFIG_HID_COMPAT=y ++# CONFIG_HID_3M_PCT is not set + # CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX_FF is not set + # CONFIG_HID_APPLE is not set + # CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CANDO is not set + # CONFIG_HID_CHERRY is not set + # CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set + # CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_EGALAX is not set + # CONFIG_HID_EZKEY is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set + # CONFIG_HID_GYRATION is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set + # CONFIG_HID_LOGITECH is not set + # CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MOSART is not set + # CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set + # CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set + # CONFIG_HID_PANTHERLORD is not set + # CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_QUANTA is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_ROCCAT_KONE is not set ++# CONFIG_HID_ROCCAT_KONEPLUS is not set ++# CONFIG_HID_ROCCAT_PYRA is not set + # CONFIG_HID_SAMSUNG is not set + # CONFIG_HID_SONY is not set ++# CONFIG_HID_STANTUM is not set + # CONFIG_HID_SUNPLUS is not set +-# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set + # CONFIG_HID_TOPSEED is not set +-# CONFIG_THRUSTMASTER_FF is not set +-# CONFIG_ZEROPLUS_FF is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set + CONFIG_USB_SUPPORT=y + CONFIG_USB_ARCH_HAS_HCD=y + CONFIG_USB_ARCH_HAS_OHCI=y +@@ -1105,7 +1273,6 @@ CONFIG_USB=y + CONFIG_USB_DEVICEFS=y + # CONFIG_USB_DEVICE_CLASS is not set + # CONFIG_USB_DYNAMIC_MINORS is not set +-CONFIG_USB_SUSPEND=y + CONFIG_USB_OTG=y + # CONFIG_USB_OTG_WHITELIST is not set + # CONFIG_USB_OTG_BLACKLIST_HUB is not set +@@ -1117,26 +1284,25 @@ CONFIG_USB_OTG=y + # USB Host Controller Drivers + # + # CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set + CONFIG_USB_EHCI_HCD=m + CONFIG_USB_EHCI_ROOT_HUB_TT=y + # CONFIG_USB_EHCI_TT_NEWSCHED is not set + CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y + CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y + CONFIG_USB_EHCI_FSL=y ++CONFIG_USB_M5445X_ULPI=y ++# CONFIG_USB_M5445X_FSLS is not set + # CONFIG_USB_OXU210HP_HCD is not set + # CONFIG_USB_ISP116X_HCD is not set + # CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set + # CONFIG_USB_OHCI_HCD is not set + # CONFIG_USB_UHCI_HCD is not set + # CONFIG_USB_SL811_HCD is not set + # CONFIG_USB_R8A66597_HCD is not set + # CONFIG_USB_WHCI_HCD is not set + # CONFIG_USB_HWA_HCD is not set +-CONFIG_USB_M5445X_ULPI=y +-# CONFIG_USB_M5445X_FSLS is not set +-# CONFIG_USB_M5441X_ULPI is not set +-# CONFIG_USB_M5441X_FSLS is not set +-# CONFIG_USB_GADGET_MUSB_HDRC is not set + + # + # USB Device Class drivers +@@ -1147,11 +1313,11 @@ CONFIG_USB_M5445X_ULPI=y + # CONFIG_USB_TMC is not set + + # +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may + # + + # +-# see USB_STORAGE Help for more information ++# also be needed; see USB_STORAGE Help for more info + # + CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_DEBUG is not set +@@ -1166,6 +1332,7 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_ONETOUCH is not set + # CONFIG_USB_STORAGE_KARMA is not set + # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_UAS is not set + # CONFIG_USB_LIBUSUAL is not set + + # +@@ -1189,11 +1356,9 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_RIO500 is not set + # CONFIG_USB_LEGOTOWER is not set + # CONFIG_USB_LCD is not set +-# CONFIG_USB_BERRY_CHARGE is not set + # CONFIG_USB_LED is not set + # CONFIG_USB_CYPRESS_CY7C63 is not set + # CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_PHIDGET is not set + # CONFIG_USB_IDMOUSE is not set + # CONFIG_USB_FTDI_ELAN is not set + # CONFIG_USB_APPLEDISPLAY is not set +@@ -1203,57 +1368,65 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_IOWARRIOR is not set + # CONFIG_USB_TEST is not set + # CONFIG_USB_ISIGHTFW is not set +-# CONFIG_USB_VST is not set ++# CONFIG_USB_YUREX is not set + CONFIG_USB_GADGET=m + # CONFIG_USB_GADGET_DEBUG_FILES is not set + CONFIG_USB_GADGET_VBUS_DRAW=2 + CONFIG_USB_GADGET_SELECTED=y +-# CONFIG_USB_GADGET_AT91 is not set +-# CONFIG_USB_GADGET_ATMEL_USBA is not set + CONFIG_USB_GADGET_FSL_USB2=y + CONFIG_USB_FSL_USB2=m +-# CONFIG_USB_GADGET_LH7A40X is not set +-# CONFIG_USB_GADGET_OMAP is not set +-# CONFIG_USB_GADGET_PXA25X is not set +-# CONFIG_USB_GADGET_PXA27X is not set +-# CONFIG_USB_GADGET_S3C2410 is not set +-# CONFIG_USB_GADGET_IMX is not set ++# CONFIG_USB_GADGET_R8A66597 is not set ++# CONFIG_USB_GADGET_PXA_U2O is not set + # CONFIG_USB_GADGET_M66592 is not set + # CONFIG_USB_GADGET_AMD5536UDC is not set +-# CONFIG_USB_GADGET_FSL_QE is not set +-# CONFIG_USB_GADGET_CI13XXX is not set ++# CONFIG_USB_GADGET_CI13XXX_PCI is not set + # CONFIG_USB_GADGET_NET2280 is not set + # CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_LANGWELL is not set ++# CONFIG_USB_GADGET_EG20T is not set + # CONFIG_USB_GADGET_DUMMY_HCD is not set + CONFIG_USB_GADGET_DUALSPEED=y + # CONFIG_USB_ZERO is not set ++# CONFIG_USB_AUDIO is not set + CONFIG_USB_ETH=m + CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_ETH_EEM is not set ++# CONFIG_USB_G_NCM is not set + # CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set + CONFIG_USB_FILE_STORAGE=m + # CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_MASS_STORAGE is not set + # CONFIG_USB_G_SERIAL is not set + # CONFIG_USB_MIDI_GADGET is not set + # CONFIG_USB_G_PRINTER is not set + # CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set + + # + # OTG and related infrastructure + # ++# CONFIG_NOP_USB_XCEIV is not set + # CONFIG_UWB is not set + # CONFIG_MMC is not set + # CONFIG_MEMSTICK is not set + # CONFIG_NEW_LEDS is not set ++# CONFIG_NFC_DEVICES is not set + # CONFIG_ACCESSIBILITY is not set + # CONFIG_INFINIBAND is not set + # CONFIG_RTC_CLASS is not set + CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set + + # + # DMA Devices + # + CONFIG_COLDFIRE_EDMA=y + CONFIG_COLDFIRE_EDMA_TEST=m ++# CONFIG_TIMB_DMA is not set ++# CONFIG_AUXDISPLAY is not set + # CONFIG_UIO is not set + # CONFIG_STAGING is not set + +@@ -1272,6 +1445,7 @@ CONFIG_EXT2_FS=y + # CONFIG_EXT2_FS_XATTR is not set + # CONFIG_EXT2_FS_XIP is not set + CONFIG_EXT3_FS=y ++CONFIG_EXT3_DEFAULTS_TO_ORDERED=y + CONFIG_EXT3_FS_XATTR=y + # CONFIG_EXT3_FS_POSIX_ACL is not set + # CONFIG_EXT3_FS_SECURITY is not set +@@ -1280,21 +1454,27 @@ CONFIG_JBD=y + CONFIG_FS_MBCACHE=y + # CONFIG_REISERFS_FS is not set + # CONFIG_JFS_FS is not set +-# CONFIG_FS_POSIX_ACL is not set +-CONFIG_FILE_LOCKING=y + # CONFIG_XFS_FS is not set + # CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set + # CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y + CONFIG_DNOTIFY=y +-CONFIG_INOTIFY=y + CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set + # CONFIG_QUOTA is not set +-# CONFIG_AUTOFS_FS is not set ++# CONFIG_QUOTACTL is not set + # CONFIG_AUTOFS4_FS is not set + # CONFIG_FUSE_FS is not set + + # ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# + # CD-ROM/DVD Filesystems + # + # CONFIG_ISO9660_FS is not set +@@ -1332,6 +1512,7 @@ CONFIG_MISC_FILESYSTEMS=y + # CONFIG_BEFS_FS is not set + # CONFIG_BFS_FS is not set + # CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set + CONFIG_JFFS2_FS=y + CONFIG_JFFS2_FS_DEBUG=0 + CONFIG_JFFS2_FS_WRITEBUFFER=y +@@ -1343,6 +1524,7 @@ CONFIG_JFFS2_ZLIB=y + # CONFIG_JFFS2_LZO is not set + CONFIG_JFFS2_RTIME=y + # CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set + # CONFIG_CRAMFS is not set + # CONFIG_SQUASHFS is not set + # CONFIG_VXFS_FS is not set +@@ -1364,10 +1546,8 @@ CONFIG_LOCKD=y + CONFIG_LOCKD_V4=y + CONFIG_NFS_COMMON=y + CONFIG_SUNRPC=y +-# CONFIG_SUNRPC_REGISTER_V4 is not set + # CONFIG_RPCSEC_GSS_KRB5 is not set +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-# CONFIG_SMB_FS is not set ++# CONFIG_CEPH_FS is not set + # CONFIG_CIFS is not set + # CONFIG_NCP_FS is not set + # CONFIG_CODA_FS is not set +@@ -1434,7 +1614,6 @@ CONFIG_NLS_ISO8859_1=y + # CONFIG_NLS_KOI8_R is not set + # CONFIG_NLS_KOI8_U is not set + CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set + + # + # Kernel hacking +@@ -1444,19 +1623,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y + # CONFIG_ENABLE_MUST_CHECK is not set + CONFIG_FRAME_WARN=1024 + # CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set + # CONFIG_UNUSED_SYMBOLS is not set + # CONFIG_DEBUG_FS is not set + # CONFIG_HEADERS_CHECK is not set + # CONFIG_DEBUG_KERNEL is not set +-# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++CONFIG_BKL=y ++# CONFIG_SPARSE_RCU_POINTER is not set ++CONFIG_DEBUG_BUGVERBOSE=y + # CONFIG_DEBUG_MEMORY_INIT is not set +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set + # CONFIG_SYSCTL_SYSCALL_CHECK is not set +- +-# +-# Tracers +-# +-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set + # CONFIG_SAMPLES is not set + # CONFIG_BOOTPARAM is not set + +@@ -1464,15 +1642,16 @@ CONFIG_FRAME_WARN=1024 + # Security options + # + # CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set + # CONFIG_SECURITY is not set + # CONFIG_SECURITYFS is not set +-# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" + CONFIG_CRYPTO=y + + # + # Crypto core or helper + # +-# CONFIG_CRYPTO_FIPS is not set + CONFIG_CRYPTO_ALGAPI=y + CONFIG_CRYPTO_ALGAPI2=y + CONFIG_CRYPTO_AEAD=y +@@ -1482,10 +1661,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y + CONFIG_CRYPTO_HASH=y + CONFIG_CRYPTO_HASH2=y + CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y + CONFIG_CRYPTO_MANAGER=y + CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set + # CONFIG_CRYPTO_GF128MUL is not set + # CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y + # CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=y + CONFIG_CRYPTO_TEST=m +@@ -1513,11 +1695,13 @@ CONFIG_CRYPTO_PCBC=m + # + CONFIG_CRYPTO_HMAC=y + # CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set + + # + # Digest + # + CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set + # CONFIG_CRYPTO_MD4 is not set + CONFIG_CRYPTO_MD5=y + # CONFIG_CRYPTO_MICHAEL_MIC is not set +@@ -1554,20 +1738,15 @@ CONFIG_CRYPTO_DES=y + # Compression + # + # CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set + # CONFIG_CRYPTO_LZO is not set + + # + # Random Number Generation + # + # CONFIG_CRYPTO_ANSI_CPRNG is not set +- +-# +-# OCF Configuration +-# +- +-# +-# Talitos Driver +-# ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set + CONFIG_CRYPTO_HW=y + CONFIG_CRYPTO_DEV_MCFCAU=y + CONFIG_CRYPTO_DEV_MCFCAU_DES=y +@@ -1575,6 +1754,7 @@ CONFIG_CRYPTO_DEV_MCFCAU_AES=y + CONFIG_CRYPTO_DEV_MCFCAU_MD5=y + CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y + # CONFIG_CRYPTO_DEV_HIFN_795X is not set ++# CONFIG_BINARY_PRINTF is not set + + # + # Library routines +@@ -1590,8 +1770,12 @@ CONFIG_CRC32=y + CONFIG_LIBCRC32C=y + CONFIG_ZLIB_INFLATE=y + CONFIG_ZLIB_DEFLATE=y ++# CONFIG_XZ_DEC is not set ++# CONFIG_XZ_DEC_BCJ is not set ++CONFIG_DECOMPRESS_GZIP=y + CONFIG_GENERIC_ALLOCATOR=y +-CONFIG_PLIST=y + CONFIG_HAS_IOMEM=y + CONFIG_HAS_IOPORT=y + CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y +--- a/arch/m68k/configs/m5474lite_defconfig ++++ b/arch/m68k/configs/m5474lite_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit +-# Linux kernel version: 2.6.29 +-# Tue Aug 24 16:17:48 2010 ++# Linux kernel version: 2.6.38 ++# Tue Aug 2 16:38:35 2011 + # + CONFIG_M68K=y + CONFIG_MMU=y +@@ -17,7 +17,9 @@ CONFIG_GENERIC_IOMAP=y + # CONFIG_NO_IOPORT is not set + # CONFIG_NO_DMA is not set + CONFIG_HZ=100 ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_CONSTRUCTORS=y + + # + # General setup +@@ -25,6 +27,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNA + CONFIG_EXPERIMENTAL=y + CONFIG_BROKEN_ON_SMP=y + CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" + CONFIG_LOCALVERSION="" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SWAP=y +@@ -34,37 +37,34 @@ CONFIG_SYSVIPC_SYSCTL=y + # CONFIG_BSD_PROCESS_ACCT is not set + # CONFIG_TASKSTATS is not set + # CONFIG_AUDIT is not set ++# CONFIG_HAVE_GENERIC_HARDIRQS is not set + + # + # RCU Subsystem + # +-CONFIG_CLASSIC_RCU=y +-# CONFIG_TREE_RCU is not set ++CONFIG_TINY_RCU=y + # CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set + # CONFIG_TREE_RCU_TRACE is not set +-# CONFIG_PREEMPT_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=17 +-CONFIG_GROUP_SCHED=y +-CONFIG_FAIR_GROUP_SCHED=y +-# CONFIG_RT_GROUP_SCHED is not set +-CONFIG_USER_SCHED=y +-# CONFIG_CGROUP_SCHED is not set + # CONFIG_CGROUPS is not set +-CONFIG_SYSFS_DEPRECATED=y +-CONFIG_SYSFS_DEPRECATED_V2=y +-# CONFIG_RELAY is not set + CONFIG_NAMESPACES=y + # CONFIG_UTS_NS is not set + # CONFIG_IPC_NS is not set + # CONFIG_USER_NS is not set + # CONFIG_PID_NS is not set + # CONFIG_NET_NS is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set + # CONFIG_BLK_DEV_INITRD is not set + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set + CONFIG_SYSCTL=y + CONFIG_ANON_INODES=y ++# CONFIG_EXPERT is not set + # CONFIG_EMBEDDED is not set + CONFIG_UID16=y + CONFIG_SYSCTL_SYSCALL=y +@@ -82,13 +82,20 @@ CONFIG_TIMERFD=y + CONFIG_EVENTFD=y + CONFIG_SHMEM=y + CONFIG_AIO=y ++ ++# ++# Kernel Performance Events And Counters ++# + CONFIG_VM_EVENT_COUNTERS=y + CONFIG_PCI_QUIRKS=y + CONFIG_COMPAT_BRK=y + CONFIG_SLAB=y + # CONFIG_SLUB is not set +-# CONFIG_SLOB is not set + # CONFIG_PROFILING is not set ++ ++# ++# GCOV-based kernel profiling ++# + # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set + CONFIG_SLABINFO=y + CONFIG_RT_MUTEXES=y +@@ -100,8 +107,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y + # CONFIG_MODVERSIONS is not set + # CONFIG_MODULE_SRCVERSION_ALL is not set + CONFIG_BLOCK=y +-CONFIG_LBD=y +-# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_BLK_DEV_INTEGRITY is not set + +@@ -109,14 +115,41 @@ CONFIG_LBD=y + # IO Schedulers + # + CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y + CONFIG_IOSCHED_DEADLINE=y + CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set + # CONFIG_DEFAULT_DEADLINE is not set + CONFIG_DEFAULT_CFQ=y + # CONFIG_DEFAULT_NOOP is not set + CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set + # CONFIG_FREEZER is not set + + # +@@ -180,18 +213,19 @@ CONFIG_SINGLE_MEMORY_CHUNK=y + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set + CONFIG_SELECT_MEMORY_MODEL=y + CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set + CONFIG_FLATMEM=y + CONFIG_FLAT_NODE_MEM_MAP=y + CONFIG_NEED_MULTIPLE_NODES=y + CONFIG_PAGEFLAGS_EXTENDED=y + CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set + # CONFIG_PHYS_ADDR_T_64BIT is not set + CONFIG_ZONE_DMA_FLAG=1 + CONFIG_BOUNCE=y + CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y + + # + # General setup +@@ -204,8 +238,8 @@ CONFIG_HAVE_AOUT=y + CONFIG_PROC_HARDWARE=y + CONFIG_ZONE_DMA=y + # CONFIG_ARCH_SUPPORTS_MSI is not set +-CONFIG_PCI_LEGACY=y + # CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set + + # + # Power management options +@@ -216,9 +250,7 @@ CONFIG_NET=y + # + # Networking options + # +-CONFIG_COMPAT_NET_DEV_OPS=y + CONFIG_PACKET=y +-# CONFIG_PACKET_MMAP is not set + CONFIG_UNIX=y + CONFIG_XFRM=y + # CONFIG_XFRM_USER is not set +@@ -241,7 +273,7 @@ CONFIG_IP_PNP=y + # CONFIG_IP_PNP_BOOTP is not set + # CONFIG_IP_PNP_RARP is not set + # CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE is not set ++# CONFIG_NET_IPGRE_DEMUX is not set + # CONFIG_ARPD is not set + # CONFIG_SYN_COOKIES is not set + CONFIG_INET_AH=y +@@ -261,11 +293,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set + # CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set + # CONFIG_NETFILTER is not set + # CONFIG_IP_DCCP is not set + # CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set + # CONFIG_TIPC is not set + # CONFIG_ATM is not set ++# CONFIG_L2TP is not set + # CONFIG_BRIDGE is not set + # CONFIG_NET_DSA is not set + # CONFIG_VLAN_8021Q is not set +@@ -277,8 +312,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_LAPB is not set + # CONFIG_ECONET is not set + # CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set + # CONFIG_NET_SCHED is not set + # CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set + + # + # Network testing +@@ -293,23 +331,28 @@ CONFIG_CAN_RAW=y + # CAN Device Drivers + # + # CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_SLCAN is not set + # CONFIG_CAN_DEV is not set +-CONFIG_CAN_FLEXCAN=y + # CONFIG_CAN_DEBUG_DEVICES is not set + # CONFIG_IRDA is not set + # CONFIG_BT is not set + # CONFIG_AF_RXRPC is not set +-# CONFIG_PHONET is not set + CONFIG_WIRELESS=y + # CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-# CONFIG_WIRELESS_EXT is not set + # CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++ ++# ++# Some wireless drivers require a rate control algorithm ++# + # CONFIG_WIMAX is not set + # CONFIG_RFKILL is not set + # CONFIG_NET_9P is not set +-# CONFIG_KLIPS is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set + + # + # Device Drivers +@@ -319,6 +362,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y + # Generic Driver Options + # + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set + # CONFIG_STANDALONE is not set + CONFIG_PREVENT_FIRMWARE_BUILD=y + CONFIG_FW_LOADER=y +@@ -328,9 +372,9 @@ CONFIG_EXTRA_FIRMWARE="" + # CONFIG_CONNECTOR is not set + CONFIG_MTD=y + # CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_TESTS is not set + CONFIG_MTD_CONCAT=y + CONFIG_MTD_PARTITIONS=y +-# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_REDBOOT_PARTS is not set + CONFIG_MTD_CMDLINE_PARTS=y + # CONFIG_MTD_AR7_PARTS is not set +@@ -346,6 +390,7 @@ CONFIG_MTD_BLOCK=y + # CONFIG_INFTL is not set + # CONFIG_RFD_FTL is not set + # CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set + # CONFIG_MTD_OOPS is not set + + # +@@ -407,10 +452,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 + # LPDDR flash memory drivers + # + # CONFIG_MTD_LPDDR is not set +- +-# +-# UBI - Unsorted block images +-# + # CONFIG_MTD_UBI is not set + # CONFIG_PARPORT is not set + CONFIG_BLK_DEV=y +@@ -421,6 +462,10 @@ CONFIG_BLK_DEV=y + # CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y + # CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# + # CONFIG_BLK_DEV_NBD is not set + # CONFIG_BLK_DEV_SX8 is not set + CONFIG_BLK_DEV_RAM=y +@@ -430,13 +475,26 @@ CONFIG_BLK_DEV_RAM_SIZE=64000 + # CONFIG_CDROM_PKTCDVD is not set + # CONFIG_ATA_OVER_ETH is not set + # CONFIG_BLK_DEV_HD is not set ++# CONFIG_BLK_DEV_RBD is not set + CONFIG_MISC_DEVICES=y ++# CONFIG_AD525X_DPOT is not set + # CONFIG_PHANTOM is not set + # CONFIG_SGI_IOC4 is not set + # CONFIG_TIFM_CORE is not set + # CONFIG_ICS932S401 is not set + # CONFIG_ENCLOSURE_SERVICES is not set + # CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085 is not set ++# CONFIG_PCH_PHUB is not set + # CONFIG_C2PORT is not set + + # +@@ -444,7 +502,13 @@ CONFIG_MISC_DEVICES=y + # + # CONFIG_EEPROM_AT24 is not set + # CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set + # CONFIG_EEPROM_93CX6 is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# + CONFIG_HAVE_IDE=y + CONFIG_IDE=y + +@@ -498,6 +562,7 @@ CONFIG_IDE_PROC_FS=y + # + # SCSI device support + # ++CONFIG_SCSI_MOD=y + # CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y + CONFIG_SCSI_DMA=y +@@ -514,10 +579,6 @@ CONFIG_BLK_DEV_SD=y + # CONFIG_BLK_DEV_SR is not set + # CONFIG_CHR_DEV_SG is not set + # CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_CONSTANTS is not set + # CONFIG_SCSI_LOGGING is not set +@@ -530,81 +591,113 @@ CONFIG_SCSI_WAIT_SCAN=m + # CONFIG_SCSI_SPI_ATTRS is not set + # CONFIG_SCSI_FC_ATTRS is not set + # CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set + # CONFIG_SCSI_SAS_LIBSAS is not set + # CONFIG_SCSI_SRP_ATTRS is not set + # CONFIG_SCSI_LOWLEVEL is not set + # CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set + CONFIG_ATA=y + # CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y + CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# + # CONFIG_SATA_AHCI is not set ++# CONFIG_SATA_AHCI_PLATFORM is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_SATA_ACARD_AHCI is not set + CONFIG_SATA_SIL24=y + CONFIG_ATA_SFF=y +-# CONFIG_SATA_SVW is not set ++ ++# ++# SFF controllers with custom DMA interface ++# ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# + # CONFIG_ATA_PIIX is not set + # CONFIG_SATA_MV is not set + # CONFIG_SATA_NV is not set +-# CONFIG_PDC_ADMA is not set +-# CONFIG_SATA_QSTOR is not set + # CONFIG_SATA_PROMISE is not set +-# CONFIG_SATA_SX4 is not set + CONFIG_SATA_SIL=y + # CONFIG_SATA_SIS is not set ++# CONFIG_SATA_SVW is not set + # CONFIG_SATA_ULI is not set + # CONFIG_SATA_VIA is not set + # CONFIG_SATA_VITESSE is not set +-# CONFIG_SATA_INIC162X is not set ++ ++# ++# PATA SFF controllers with BMDMA ++# + # CONFIG_PATA_ALI is not set + # CONFIG_PATA_AMD is not set + # CONFIG_PATA_ARTOP is not set + # CONFIG_PATA_ATIIXP is not set +-# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_ATP867X is not set + # CONFIG_PATA_CMD64X is not set + # CONFIG_PATA_CS5520 is not set + # CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CS5536 is not set + # CONFIG_PATA_CYPRESS is not set + # CONFIG_PATA_EFAR is not set +-# CONFIG_ATA_GENERIC is not set + # CONFIG_PATA_HPT366 is not set + # CONFIG_PATA_HPT37X is not set + # CONFIG_PATA_HPT3X2N is not set + # CONFIG_PATA_HPT3X3 is not set +-# CONFIG_PATA_IT821X is not set + # CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_IT821X is not set + # CONFIG_PATA_JMICRON is not set +-# CONFIG_PATA_TRIFLEX is not set + # CONFIG_PATA_MARVELL is not set +-# CONFIG_PATA_MPIIX is not set +-# CONFIG_PATA_OLDPIIX is not set + # CONFIG_PATA_NETCELL is not set + # CONFIG_PATA_NINJA32 is not set +-# CONFIG_PATA_NS87410 is not set + # CONFIG_PATA_NS87415 is not set +-# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OLDPIIX is not set + # CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC2027X is not set + # CONFIG_PATA_PDC_OLD is not set + # CONFIG_PATA_RADISYS is not set +-# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_RDC is not set + # CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SCH is not set + # CONFIG_PATA_SERVERWORKS is not set +-# CONFIG_PATA_PDC2027X is not set + # CONFIG_PATA_SIL680 is not set + # CONFIG_PATA_SIS is not set ++# CONFIG_PATA_TOSHIBA is not set ++# CONFIG_PATA_TRIFLEX is not set + # CONFIG_PATA_VIA is not set + # CONFIG_PATA_WINBOND is not set +-# CONFIG_PATA_SCH is not set +-# CONFIG_MD is not set +-# CONFIG_FUSION is not set + + # +-# IEEE 1394 (FireWire) support ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_RZ1000 is not set ++ + # ++# Generic fallback / legacy drivers ++# ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_LEGACY is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set + + # +-# Enable only one of the two stacks, unless you know what you are doing ++# IEEE 1394 (FireWire) support + # + # CONFIG_FIREWIRE is not set +-# CONFIG_IEEE1394 is not set ++# CONFIG_FIREWIRE_NOSY is not set + # CONFIG_I2O is not set + CONFIG_NETDEVICES=y + # CONFIG_DUMMY is not set +@@ -614,6 +707,7 @@ CONFIG_NETDEVICES=y + # CONFIG_TUN is not set + # CONFIG_VETH is not set + # CONFIG_ARCNET is not set ++CONFIG_MII=y + CONFIG_PHYLIB=y + + # +@@ -628,22 +722,24 @@ CONFIG_PHYLIB=y + # CONFIG_SMSC_PHY is not set + # CONFIG_BROADCOM_PHY is not set + CONFIG_BROADCOM5222_PHY=y ++# CONFIG_BCM63XX_PHY is not set + # CONFIG_ICPLUS_PHY is not set + # CONFIG_REALTEK_PHY is not set + # CONFIG_NATIONAL_PHY is not set + # CONFIG_NATIONAL8364x_PHY is not set + # CONFIG_NATIONAL8384x_PHY is not set +-# CONFIG_MicrelKSZ8041_PHY is not set + # CONFIG_STE10XP is not set + # CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set + # CONFIG_FIXED_PHY is not set + # CONFIG_MDIO_BITBANG is not set + CONFIG_NET_ETHERNET=y +-CONFIG_MII=y + # CONFIG_HAPPYMEAL is not set + # CONFIG_SUNGEM is not set + # CONFIG_CASSINI is not set + # CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_SMC91X is not set ++# CONFIG_ETHOC is not set + # CONFIG_DNET is not set + # CONFIG_NET_TULIP is not set + # CONFIG_HP100 is not set +@@ -658,6 +754,7 @@ CONFIG_NET_PCI=y + # CONFIG_PCNET32 is not set + # CONFIG_AMD8111_ETH is not set + # CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_KSZ884X_PCI is not set + # CONFIG_B44 is not set + # CONFIG_FORCEDETH is not set + CONFIG_E100=y +@@ -676,6 +773,7 @@ CONFIG_8139TOO_PIO=y + # CONFIG_SMSC9420 is not set + # CONFIG_SUNDANCE is not set + # CONFIG_TLAN is not set ++# CONFIG_KS8851_MLL is not set + # CONFIG_VIA_RHINE is not set + # CONFIG_SC92031 is not set + CONFIG_FEC_548x=y +@@ -689,6 +787,7 @@ CONFIG_E1000=y + # CONFIG_E1000E is not set + # CONFIG_IP1000 is not set + # CONFIG_IGB is not set ++# CONFIG_IGBVF is not set + # CONFIG_NS83820 is not set + # CONFIG_HAMACHI is not set + # CONFIG_YELLOWFIN is not set +@@ -699,25 +798,29 @@ CONFIG_E1000=y + # CONFIG_VIA_VELOCITY is not set + # CONFIG_TIGON3 is not set + # CONFIG_BNX2 is not set ++# CONFIG_CNIC is not set + # CONFIG_QLA3XXX is not set + # CONFIG_ATL1 is not set + # CONFIG_ATL1E is not set + # CONFIG_ATL1C is not set + # CONFIG_JME is not set ++# CONFIG_STMMAC_ETH is not set ++# CONFIG_PCH_GBE is not set + # CONFIG_NETDEV_10000 is not set + # CONFIG_TR is not set ++CONFIG_WLAN=y ++# CONFIG_ATMEL is not set ++# CONFIG_PRISM54 is not set ++# CONFIG_HOSTAP is not set + + # +-# Wireless LAN ++# Enable WiMAX (Networking options) to see the WiMAX drivers + # +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_WAN is not set + + # +-# Enable WiMAX (Networking options) to see the WiMAX drivers ++# CAIF transport drivers + # +-# CONFIG_WAN is not set + # CONFIG_FDDI is not set + # CONFIG_HIPPI is not set + # CONFIG_PPP is not set +@@ -726,6 +829,7 @@ CONFIG_E1000=y + # CONFIG_NETCONSOLE is not set + # CONFIG_NETPOLL is not set + # CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_VMXNET3 is not set + # CONFIG_ISDN is not set + # CONFIG_PHONE is not set + +@@ -735,6 +839,7 @@ CONFIG_E1000=y + CONFIG_INPUT=y + # CONFIG_INPUT_FF_MEMLESS is not set + # CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set + + # + # Userland interfaces +@@ -751,12 +856,18 @@ CONFIG_INPUT_EVDEV=y + # Input Device Drivers + # + CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set + # CONFIG_KEYBOARD_ATKBD is not set +-# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_QT2160 is not set + # CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set + # CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set + # CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_INPUT_MOUSE is not set + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set +@@ -770,6 +881,8 @@ CONFIG_SERIO=y + CONFIG_SERIO_SERPORT=y + # CONFIG_SERIO_PCIPS2 is not set + # CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set + # CONFIG_GAMEPORT is not set + + # +@@ -782,6 +895,7 @@ CONFIG_HW_CONSOLE=y + # CONFIG_VT_HW_CONSOLE_BINDING is not set + CONFIG_DEVKMEM=y + # CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set + # CONFIG_NOZOMI is not set + + # +@@ -792,6 +906,7 @@ CONFIG_DEVKMEM=y + # + # Non-8250 serial port support + # ++# CONFIG_SERIAL_MFD_HSU is not set + CONFIG_SERIAL_CORE=y + CONFIG_SERIAL_CORE_CONSOLE=y + # CONFIG_SERIAL_COLDFIRE_IRDA is not set +@@ -800,19 +915,26 @@ CONFIG_SERIAL_MCF=y + CONFIG_SERIAL_MCF_BAUDRATE=115200 + CONFIG_SERIAL_MCF_CONSOLE=y + # CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set + CONFIG_UNIX98_PTYS=y + # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set + # CONFIG_IPMI_HANDLER is not set +-# CONFIG_HW_RANDOM is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set + # CONFIG_GEN_RTC is not set + # CONFIG_R3964 is not set + # CONFIG_APPLICOM is not set + # CONFIG_RAW_DRIVER is not set + # CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set + CONFIG_I2C=y + CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y + # CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set + CONFIG_I2C_HELPER_AUTO=y + + # +@@ -840,9 +962,13 @@ CONFIG_I2C_HELPER_AUTO=y + # + # I2C system bus drivers (mostly embedded / system-on-chip) + # ++# CONFIG_I2C_INTEL_MID is not set + CONFIG_I2C_MCF=y + # CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++# CONFIG_I2C_EG20T is not set + + # + # External I2C/SMBus adapter drivers +@@ -851,36 +977,26 @@ CONFIG_I2C_MCF=y + # CONFIG_I2C_TAOS_EVM is not set + + # +-# Graphics adapter I2C/DDC channel drivers +-# +-# CONFIG_I2C_VOODOO3 is not set +- +-# + # Other I2C/SMBus bus drivers + # +-# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_STUB is not set +- +-# +-# Miscellaneous I2C Chip support +-# +-# CONFIG_DS1682 is not set +-# CONFIG_SENSORS_PCF8574 is not set +-# CONFIG_PCF8575 is not set +-# CONFIG_SENSORS_PCA9539 is not set +-# CONFIG_SENSORS_PCF8591 is not set +-# CONFIG_SENSORS_MAX6875 is not set +-# CONFIG_SENSORS_TSL2550 is not set + # CONFIG_I2C_DEBUG_CORE is not set + # CONFIG_I2C_DEBUG_ALGO is not set + # CONFIG_I2C_DEBUG_BUS is not set +-# CONFIG_I2C_DEBUG_CHIP is not set + # CONFIG_SPI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# + # CONFIG_W1 is not set + # CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set + # CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set + # CONFIG_WATCHDOG is not set + CONFIG_SSB_POSSIBLE=y + +@@ -888,40 +1004,33 @@ CONFIG_SSB_POSSIBLE=y + # Sonics Silicon Backplane + # + # CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# ++CONFIG_MFD_SUPPORT=y + # CONFIG_MFD_CORE is not set + # CONFIG_MFD_SM501 is not set + # CONFIG_HTC_PASIC3 is not set ++# CONFIG_TPS6507X is not set + # CONFIG_MFD_TMIO is not set + # CONFIG_PMIC_DA903X is not set ++# CONFIG_PMIC_ADP5520 is not set + # CONFIG_MFD_WM8400 is not set +-# CONFIG_MFD_WM8350_I2C is not set + # CONFIG_MFD_PCF50633 is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_CS5535 is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_WL1273_CORE is not set + # CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-# CONFIG_VIDEO_DEV is not set +-# CONFIG_DVB_CORE is not set +-# CONFIG_VIDEO_MEDIA is not set +- +-# +-# Multimedia drivers +-# +-CONFIG_DAB=y ++# CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 + # CONFIG_DRM is not set ++# CONFIG_STUB_POULSBO is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=m + # CONFIG_FB is not set +@@ -943,10 +1052,12 @@ CONFIG_DUMMY_CONSOLE=y + # CONFIG_MMC is not set + # CONFIG_MEMSTICK is not set + # CONFIG_NEW_LEDS is not set ++# CONFIG_NFC_DEVICES is not set + # CONFIG_ACCESSIBILITY is not set + # CONFIG_INFINIBAND is not set + # CONFIG_RTC_CLASS is not set + # CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set + # CONFIG_UIO is not set + # CONFIG_STAGING is not set + +@@ -965,6 +1076,7 @@ CONFIG_EXT2_FS=y + # CONFIG_EXT2_FS_XATTR is not set + # CONFIG_EXT2_FS_XIP is not set + CONFIG_EXT3_FS=y ++CONFIG_EXT3_DEFAULTS_TO_ORDERED=y + CONFIG_EXT3_FS_XATTR=y + # CONFIG_EXT3_FS_POSIX_ACL is not set + # CONFIG_EXT3_FS_SECURITY is not set +@@ -973,20 +1085,27 @@ CONFIG_JBD=y + CONFIG_FS_MBCACHE=y + # CONFIG_REISERFS_FS is not set + # CONFIG_JFS_FS is not set +-# CONFIG_FS_POSIX_ACL is not set +-CONFIG_FILE_LOCKING=y + # CONFIG_XFS_FS is not set + # CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set + # CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y + CONFIG_DNOTIFY=y +-# CONFIG_INOTIFY is not set ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set + # CONFIG_QUOTA is not set +-# CONFIG_AUTOFS_FS is not set ++# CONFIG_QUOTACTL is not set + # CONFIG_AUTOFS4_FS is not set + # CONFIG_FUSE_FS is not set + + # ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# + # CD-ROM/DVD Filesystems + # + # CONFIG_ISO9660_FS is not set +@@ -1024,7 +1143,9 @@ CONFIG_MISC_FILESYSTEMS=y + # CONFIG_BEFS_FS is not set + # CONFIG_BFS_FS is not set + # CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set + # CONFIG_JFFS2_FS is not set ++# CONFIG_LOGFS is not set + # CONFIG_CRAMFS is not set + # CONFIG_SQUASHFS is not set + # CONFIG_VXFS_FS is not set +@@ -1033,6 +1154,10 @@ CONFIG_MINIX_FS=y + # CONFIG_HPFS_FS is not set + # CONFIG_QNX4FS_FS is not set + CONFIG_ROMFS_FS=y ++CONFIG_ROMFS_BACKED_BY_BLOCK=y ++# CONFIG_ROMFS_BACKED_BY_MTD is not set ++# CONFIG_ROMFS_BACKED_BY_BOTH is not set ++CONFIG_ROMFS_ON_BLOCK=y + # CONFIG_SYSV_FS is not set + # CONFIG_UFS_FS is not set + CONFIG_NETWORK_FILESYSTEMS=y +@@ -1044,10 +1169,8 @@ CONFIG_ROOT_NFS=y + CONFIG_LOCKD=y + CONFIG_NFS_COMMON=y + CONFIG_SUNRPC=y +-# CONFIG_SUNRPC_REGISTER_V4 is not set + # CONFIG_RPCSEC_GSS_KRB5 is not set +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-# CONFIG_SMB_FS is not set ++# CONFIG_CEPH_FS is not set + # CONFIG_CIFS is not set + # CONFIG_NCP_FS is not set + # CONFIG_CODA_FS is not set +@@ -1114,7 +1237,6 @@ CONFIG_NLS_ISO8859_1=y + # CONFIG_NLS_KOI8_R is not set + # CONFIG_NLS_KOI8_U is not set + CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set + + # + # Kernel hacking +@@ -1124,19 +1246,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y + # CONFIG_ENABLE_MUST_CHECK is not set + CONFIG_FRAME_WARN=1024 + # CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set + # CONFIG_UNUSED_SYMBOLS is not set + # CONFIG_DEBUG_FS is not set + # CONFIG_HEADERS_CHECK is not set + # CONFIG_DEBUG_KERNEL is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++CONFIG_BKL=y ++# CONFIG_SPARSE_RCU_POINTER is not set + CONFIG_DEBUG_BUGVERBOSE=y + CONFIG_DEBUG_MEMORY_INIT=y +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set + # CONFIG_SYSCTL_SYSCALL_CHECK is not set +- +-# +-# Tracers +-# +-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set + # CONFIG_SAMPLES is not set + # CONFIG_BOOTPARAM is not set + +@@ -1144,15 +1265,16 @@ CONFIG_DEBUG_MEMORY_INIT=y + # Security options + # + # CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set + # CONFIG_SECURITY is not set + # CONFIG_SECURITYFS is not set +-# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" + CONFIG_CRYPTO=y + + # + # Crypto core or helper + # +-# CONFIG_CRYPTO_FIPS is not set + CONFIG_CRYPTO_ALGAPI=y + CONFIG_CRYPTO_ALGAPI2=y + CONFIG_CRYPTO_AEAD=y +@@ -1162,10 +1284,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y + CONFIG_CRYPTO_HASH=y + CONFIG_CRYPTO_HASH2=y + CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y + CONFIG_CRYPTO_MANAGER=y + CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set + # CONFIG_CRYPTO_GF128MUL is not set + # CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y + # CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=y + CONFIG_CRYPTO_TEST=m +@@ -1193,11 +1318,13 @@ CONFIG_CRYPTO_CBC=y + # + CONFIG_CRYPTO_HMAC=y + # CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set + + # + # Digest + # + CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set + # CONFIG_CRYPTO_MD4 is not set + CONFIG_CRYPTO_MD5=y + # CONFIG_CRYPTO_MICHAEL_MIC is not set +@@ -1234,22 +1361,17 @@ CONFIG_CRYPTO_DES=y + # Compression + # + # CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set + # CONFIG_CRYPTO_LZO is not set + + # + # Random Number Generation + # + # CONFIG_CRYPTO_ANSI_CPRNG is not set +- +-# +-# OCF Configuration +-# +-# CONFIG_OCF_OCF is not set +- +-# +-# Talitos Driver +-# ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set + # CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set + + # + # Library routines +@@ -1263,7 +1385,10 @@ CONFIG_CRC16=y + CONFIG_CRC32=y + # CONFIG_CRC7 is not set + CONFIG_LIBCRC32C=y +-CONFIG_PLIST=y ++# CONFIG_XZ_DEC is not set ++# CONFIG_XZ_DEC_BCJ is not set + CONFIG_HAS_IOMEM=y + CONFIG_HAS_IOPORT=y + CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y +--- a/arch/m68k/configs/m5475evb_defconfig ++++ b/arch/m68k/configs/m5475evb_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit +-# Linux kernel version: 2.6.29 +-# Tue Aug 24 15:41:10 2010 ++# Linux kernel version: 2.6.38 ++# Tue Aug 2 16:44:38 2011 + # + CONFIG_M68K=y + CONFIG_MMU=y +@@ -17,7 +17,9 @@ CONFIG_GENERIC_IOMAP=y + # CONFIG_NO_IOPORT is not set + # CONFIG_NO_DMA is not set + CONFIG_HZ=100 ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_CONSTRUCTORS=y + + # + # General setup +@@ -25,6 +27,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNA + CONFIG_EXPERIMENTAL=y + CONFIG_BROKEN_ON_SMP=y + CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" + CONFIG_LOCALVERSION="" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SWAP=y +@@ -34,38 +37,40 @@ CONFIG_SYSVIPC_SYSCTL=y + # CONFIG_BSD_PROCESS_ACCT is not set + # CONFIG_TASKSTATS is not set + # CONFIG_AUDIT is not set ++# CONFIG_HAVE_GENERIC_HARDIRQS is not set + + # + # RCU Subsystem + # +-CONFIG_CLASSIC_RCU=y +-# CONFIG_TREE_RCU is not set ++CONFIG_TINY_RCU=y + # CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set + # CONFIG_TREE_RCU_TRACE is not set +-# CONFIG_PREEMPT_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=17 +-CONFIG_GROUP_SCHED=y +-CONFIG_FAIR_GROUP_SCHED=y +-# CONFIG_RT_GROUP_SCHED is not set +-CONFIG_USER_SCHED=y +-# CONFIG_CGROUP_SCHED is not set + # CONFIG_CGROUPS is not set +-CONFIG_SYSFS_DEPRECATED=y +-CONFIG_SYSFS_DEPRECATED_V2=y +-# CONFIG_RELAY is not set + CONFIG_NAMESPACES=y + # CONFIG_UTS_NS is not set + # CONFIG_IPC_NS is not set + # CONFIG_USER_NS is not set + # CONFIG_PID_NS is not set + # CONFIG_NET_NS is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set + CONFIG_BLK_DEV_INITRD=y + CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++CONFIG_RD_BZIP2=y ++CONFIG_RD_LZMA=y ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set + CONFIG_SYSCTL=y + CONFIG_ANON_INODES=y ++# CONFIG_EXPERT is not set + # CONFIG_EMBEDDED is not set + CONFIG_UID16=y + CONFIG_SYSCTL_SYSCALL=y +@@ -83,13 +88,20 @@ CONFIG_TIMERFD=y + CONFIG_EVENTFD=y + CONFIG_SHMEM=y + CONFIG_AIO=y ++ ++# ++# Kernel Performance Events And Counters ++# + CONFIG_VM_EVENT_COUNTERS=y + CONFIG_PCI_QUIRKS=y + CONFIG_COMPAT_BRK=y + CONFIG_SLAB=y + # CONFIG_SLUB is not set +-# CONFIG_SLOB is not set + # CONFIG_PROFILING is not set ++ ++# ++# GCOV-based kernel profiling ++# + # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set + CONFIG_SLABINFO=y + CONFIG_RT_MUTEXES=y +@@ -101,8 +113,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y + # CONFIG_MODVERSIONS is not set + # CONFIG_MODULE_SRCVERSION_ALL is not set + CONFIG_BLOCK=y +-CONFIG_LBD=y +-# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_BLK_DEV_INTEGRITY is not set + +@@ -110,14 +121,41 @@ CONFIG_LBD=y + # IO Schedulers + # + CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y + CONFIG_IOSCHED_DEADLINE=y + CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set + # CONFIG_DEFAULT_DEADLINE is not set + CONFIG_DEFAULT_CFQ=y + # CONFIG_DEFAULT_NOOP is not set + CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set + # CONFIG_FREEZER is not set + + # +@@ -181,18 +219,19 @@ CONFIG_SINGLE_MEMORY_CHUNK=y + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set + CONFIG_SELECT_MEMORY_MODEL=y + CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set + CONFIG_FLATMEM=y + CONFIG_FLAT_NODE_MEM_MAP=y + CONFIG_NEED_MULTIPLE_NODES=y + CONFIG_PAGEFLAGS_EXTENDED=y + CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set + # CONFIG_PHYS_ADDR_T_64BIT is not set + CONFIG_ZONE_DMA_FLAG=1 + CONFIG_BOUNCE=y + CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y + + # + # General setup +@@ -205,8 +244,8 @@ CONFIG_HAVE_AOUT=y + CONFIG_PROC_HARDWARE=y + CONFIG_ZONE_DMA=y + # CONFIG_ARCH_SUPPORTS_MSI is not set +-CONFIG_PCI_LEGACY=y + # CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set + + # + # Power management options +@@ -217,9 +256,7 @@ CONFIG_NET=y + # + # Networking options + # +-CONFIG_COMPAT_NET_DEV_OPS=y + CONFIG_PACKET=y +-# CONFIG_PACKET_MMAP is not set + CONFIG_UNIX=y + CONFIG_XFRM=y + # CONFIG_XFRM_USER is not set +@@ -242,7 +279,7 @@ CONFIG_IP_PNP=y + # CONFIG_IP_PNP_BOOTP is not set + # CONFIG_IP_PNP_RARP is not set + # CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE is not set ++# CONFIG_NET_IPGRE_DEMUX is not set + # CONFIG_ARPD is not set + # CONFIG_SYN_COOKIES is not set + CONFIG_INET_AH=y +@@ -262,11 +299,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set + # CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set + # CONFIG_NETFILTER is not set + # CONFIG_IP_DCCP is not set + # CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set + # CONFIG_TIPC is not set + # CONFIG_ATM is not set ++# CONFIG_L2TP is not set + # CONFIG_BRIDGE is not set + # CONFIG_NET_DSA is not set + # CONFIG_VLAN_8021Q is not set +@@ -278,8 +318,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_LAPB is not set + # CONFIG_ECONET is not set + # CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set + # CONFIG_NET_SCHED is not set + # CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set + + # + # Network testing +@@ -294,23 +337,69 @@ CONFIG_CAN_RAW=y + # CAN Device Drivers + # + # CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_SLCAN is not set + # CONFIG_CAN_DEV is not set +-# CONFIG_CAN_FLEXCAN is not set + # CONFIG_CAN_DEBUG_DEVICES is not set +-# CONFIG_IRDA is not set ++CONFIG_IRDA=y ++ ++# ++# IrDA protocols ++# ++# CONFIG_IRLAN is not set ++CONFIG_IRNET=y ++CONFIG_IRCOMM=y ++# CONFIG_IRDA_ULTRA is not set ++ ++# ++# IrDA options ++# ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++# CONFIG_IRDA_FAST_RR is not set ++# CONFIG_IRDA_DEBUG is not set ++ ++# ++# Infrared-port device drivers ++# ++ ++# ++# SIR device drivers ++# ++CONFIG_IRTTY_SIR=y ++ ++# ++# Dongle support ++# ++# CONFIG_DONGLE is not set ++# CONFIG_KINGSUN_DONGLE is not set ++# CONFIG_KSDAZZLE_DONGLE is not set ++# CONFIG_KS959_DONGLE is not set ++ ++# ++# FIR device drivers ++# ++# CONFIG_USB_IRDA is not set ++# CONFIG_SIGMATEL_FIR is not set ++# CONFIG_TOSHIBA_FIR is not set ++# CONFIG_VLSI_FIR is not set ++# CONFIG_MCS_FIR is not set + # CONFIG_BT is not set + # CONFIG_AF_RXRPC is not set +-# CONFIG_PHONET is not set + CONFIG_WIRELESS=y + # CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-# CONFIG_WIRELESS_EXT is not set + # CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++ ++# ++# Some wireless drivers require a rate control algorithm ++# + # CONFIG_WIMAX is not set + # CONFIG_RFKILL is not set + # CONFIG_NET_9P is not set +-# CONFIG_KLIPS is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set + + # + # Device Drivers +@@ -320,6 +409,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y + # Generic Driver Options + # + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set + # CONFIG_STANDALONE is not set + CONFIG_PREVENT_FIRMWARE_BUILD=y + CONFIG_FW_LOADER=y +@@ -329,9 +419,9 @@ CONFIG_EXTRA_FIRMWARE="" + # CONFIG_CONNECTOR is not set + CONFIG_MTD=y + # CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_CONCAT is not set + CONFIG_MTD_PARTITIONS=y +-# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_REDBOOT_PARTS is not set + CONFIG_MTD_CMDLINE_PARTS=y + # CONFIG_MTD_AR7_PARTS is not set +@@ -347,6 +437,7 @@ CONFIG_MTD_BLOCK=y + # CONFIG_INFTL is not set + # CONFIG_RFD_FTL is not set + # CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set + # CONFIG_MTD_OOPS is not set + + # +@@ -408,10 +499,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 + # LPDDR flash memory drivers + # + # CONFIG_MTD_LPDDR is not set +- +-# +-# UBI - Unsorted block images +-# + # CONFIG_MTD_UBI is not set + # CONFIG_PARPORT is not set + CONFIG_BLK_DEV=y +@@ -422,6 +509,10 @@ CONFIG_BLK_DEV=y + # CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y + # CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# + # CONFIG_BLK_DEV_NBD is not set + # CONFIG_BLK_DEV_SX8 is not set + # CONFIG_BLK_DEV_UB is not set +@@ -432,13 +523,26 @@ CONFIG_BLK_DEV_RAM_SIZE=64000 + # CONFIG_CDROM_PKTCDVD is not set + # CONFIG_ATA_OVER_ETH is not set + # CONFIG_BLK_DEV_HD is not set ++# CONFIG_BLK_DEV_RBD is not set + CONFIG_MISC_DEVICES=y ++# CONFIG_AD525X_DPOT is not set + # CONFIG_PHANTOM is not set + # CONFIG_SGI_IOC4 is not set + # CONFIG_TIFM_CORE is not set + # CONFIG_ICS932S401 is not set + # CONFIG_ENCLOSURE_SERVICES is not set + # CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085 is not set ++# CONFIG_PCH_PHUB is not set + # CONFIG_C2PORT is not set + + # +@@ -446,13 +550,20 @@ CONFIG_MISC_DEVICES=y + # + # CONFIG_EEPROM_AT24 is not set + # CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set + # CONFIG_EEPROM_93CX6 is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# + CONFIG_HAVE_IDE=y + # CONFIG_IDE is not set + + # + # SCSI device support + # ++CONFIG_SCSI_MOD=y + # CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y + CONFIG_SCSI_DMA=y +@@ -469,10 +580,6 @@ CONFIG_BLK_DEV_SD=y + # CONFIG_BLK_DEV_SR is not set + # CONFIG_CHR_DEV_SG is not set + # CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_CONSTANTS is not set + # CONFIG_SCSI_LOGGING is not set +@@ -485,23 +592,22 @@ CONFIG_SCSI_WAIT_SCAN=m + # CONFIG_SCSI_SPI_ATTRS is not set + # CONFIG_SCSI_FC_ATTRS is not set + # CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set + # CONFIG_SCSI_SAS_LIBSAS is not set + # CONFIG_SCSI_SRP_ATTRS is not set + # CONFIG_SCSI_LOWLEVEL is not set + # CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set + # CONFIG_ATA is not set + # CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set + # CONFIG_FUSION is not set + + # + # IEEE 1394 (FireWire) support + # +- +-# +-# Enable only one of the two stacks, unless you know what you are doing +-# + # CONFIG_FIREWIRE is not set +-# CONFIG_IEEE1394 is not set ++# CONFIG_FIREWIRE_NOSY is not set + # CONFIG_I2O is not set + CONFIG_NETDEVICES=y + # CONFIG_DUMMY is not set +@@ -511,6 +617,7 @@ CONFIG_NETDEVICES=y + # CONFIG_TUN is not set + # CONFIG_VETH is not set + # CONFIG_ARCNET is not set ++CONFIG_MII=y + CONFIG_PHYLIB=y + + # +@@ -525,22 +632,24 @@ CONFIG_PHYLIB=y + # CONFIG_SMSC_PHY is not set + # CONFIG_BROADCOM_PHY is not set + CONFIG_BROADCOM5222_PHY=y ++# CONFIG_BCM63XX_PHY is not set + # CONFIG_ICPLUS_PHY is not set + # CONFIG_REALTEK_PHY is not set + # CONFIG_NATIONAL_PHY is not set + # CONFIG_NATIONAL8364x_PHY is not set + # CONFIG_NATIONAL8384x_PHY is not set +-# CONFIG_MicrelKSZ8041_PHY is not set + # CONFIG_STE10XP is not set + # CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set + # CONFIG_FIXED_PHY is not set + # CONFIG_MDIO_BITBANG is not set + CONFIG_NET_ETHERNET=y +-CONFIG_MII=y + # CONFIG_HAPPYMEAL is not set + # CONFIG_SUNGEM is not set + # CONFIG_CASSINI is not set + # CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_SMC91X is not set ++# CONFIG_ETHOC is not set + # CONFIG_DNET is not set + # CONFIG_NET_TULIP is not set + # CONFIG_HP100 is not set +@@ -553,6 +662,7 @@ CONFIG_MII=y + # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set + # CONFIG_NET_PCI is not set + # CONFIG_B44 is not set ++# CONFIG_KS8851_MLL is not set + CONFIG_FEC_548x=y + CONFIG_FEC_548x_ENABLE_FEC2=y + CONFIG_FEC_548x_SHARED_PHY=y +@@ -560,13 +670,11 @@ CONFIG_FEC_548x_SHARED_PHY=y + # CONFIG_NETDEV_1000 is not set + # CONFIG_NETDEV_10000 is not set + # CONFIG_TR is not set +- +-# +-# Wireless LAN +-# +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set ++CONFIG_WLAN=y ++# CONFIG_ATMEL is not set ++# CONFIG_PRISM54 is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_HOSTAP is not set + + # + # Enable WiMAX (Networking options) to see the WiMAX drivers +@@ -580,15 +688,30 @@ CONFIG_FEC_548x_SHARED_PHY=y + # CONFIG_USB_PEGASUS is not set + # CONFIG_USB_RTL8150 is not set + # CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set + # CONFIG_WAN is not set ++ ++# ++# CAIF transport drivers ++# + # CONFIG_FDDI is not set + # CONFIG_HIPPI is not set +-# CONFIG_PPP is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++# CONFIG_PPP_FILTER is not set ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++CONFIG_PPPOE=y + # CONFIG_SLIP is not set ++CONFIG_SLHC=y + # CONFIG_NET_FC is not set + # CONFIG_NETCONSOLE is not set + # CONFIG_NETPOLL is not set + # CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_VMXNET3 is not set + # CONFIG_ISDN is not set + # CONFIG_PHONE is not set + +@@ -598,6 +721,7 @@ CONFIG_FEC_548x_SHARED_PHY=y + CONFIG_INPUT=y + # CONFIG_INPUT_FF_MEMLESS is not set + # CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set + + # + # Userland interfaces +@@ -614,12 +738,18 @@ CONFIG_INPUT_EVDEV=y + # Input Device Drivers + # + CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set + # CONFIG_KEYBOARD_ATKBD is not set +-# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_QT2160 is not set + # CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set + # CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set + # CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_INPUT_MOUSE is not set + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set +@@ -633,6 +763,8 @@ CONFIG_SERIO=y + CONFIG_SERIO_SERPORT=y + # CONFIG_SERIO_PCIPS2 is not set + # CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set + # CONFIG_GAMEPORT is not set + + # +@@ -645,6 +777,7 @@ CONFIG_HW_CONSOLE=y + # CONFIG_VT_HW_CONSOLE_BINDING is not set + CONFIG_DEVKMEM=y + # CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set + # CONFIG_NOZOMI is not set + + # +@@ -655,26 +788,34 @@ CONFIG_DEVKMEM=y + # + # Non-8250 serial port support + # ++# CONFIG_SERIAL_MFD_HSU is not set + CONFIG_SERIAL_CORE=y + CONFIG_SERIAL_CORE_CONSOLE=y +-# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++CONFIG_SERIAL_COLDFIRE_IRDA=y + # CONFIG_SERIAL_COLDFIRE_EDMA is not set + CONFIG_SERIAL_MCF=y + CONFIG_SERIAL_MCF_BAUDRATE=115200 + CONFIG_SERIAL_MCF_CONSOLE=y + # CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set + CONFIG_UNIX98_PTYS=y + # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set + # CONFIG_IPMI_HANDLER is not set +-# CONFIG_HW_RANDOM is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set + # CONFIG_R3964 is not set + # CONFIG_APPLICOM is not set + # CONFIG_RAW_DRIVER is not set + # CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set + CONFIG_I2C=y + CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y + CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set + CONFIG_I2C_HELPER_AUTO=y + + # +@@ -702,9 +843,13 @@ CONFIG_I2C_HELPER_AUTO=y + # + # I2C system bus drivers (mostly embedded / system-on-chip) + # ++# CONFIG_I2C_INTEL_MID is not set + CONFIG_I2C_MCF=y + # CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++# CONFIG_I2C_EG20T is not set + + # + # External I2C/SMBus adapter drivers +@@ -714,36 +859,26 @@ CONFIG_I2C_MCF=y + # CONFIG_I2C_TINY_USB is not set + + # +-# Graphics adapter I2C/DDC channel drivers +-# +-# CONFIG_I2C_VOODOO3 is not set +- +-# + # Other I2C/SMBus bus drivers + # +-# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_STUB is not set +- +-# +-# Miscellaneous I2C Chip support +-# +-# CONFIG_DS1682 is not set +-# CONFIG_SENSORS_PCF8574 is not set +-# CONFIG_PCF8575 is not set +-# CONFIG_SENSORS_PCA9539 is not set +-# CONFIG_SENSORS_PCF8591 is not set +-# CONFIG_SENSORS_MAX6875 is not set +-# CONFIG_SENSORS_TSL2550 is not set + # CONFIG_I2C_DEBUG_CORE is not set + # CONFIG_I2C_DEBUG_ALGO is not set + # CONFIG_I2C_DEBUG_BUS is not set +-# CONFIG_I2C_DEBUG_CHIP is not set + # CONFIG_SPI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# + # CONFIG_W1 is not set + # CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set + # CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set + CONFIG_WATCHDOG=y + # CONFIG_WATCHDOG_NOWAYOUT is not set + +@@ -770,41 +905,33 @@ CONFIG_SSB_POSSIBLE=y + # Sonics Silicon Backplane + # + # CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# ++CONFIG_MFD_SUPPORT=y + # CONFIG_MFD_CORE is not set + # CONFIG_MFD_SM501 is not set + # CONFIG_HTC_PASIC3 is not set ++# CONFIG_TPS6507X is not set + # CONFIG_MFD_TMIO is not set + # CONFIG_PMIC_DA903X is not set ++# CONFIG_PMIC_ADP5520 is not set + # CONFIG_MFD_WM8400 is not set +-# CONFIG_MFD_WM8350_I2C is not set + # CONFIG_MFD_PCF50633 is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_CS5535 is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_WL1273_CORE is not set + # CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-# CONFIG_VIDEO_DEV is not set +-# CONFIG_DVB_CORE is not set +-# CONFIG_VIDEO_MEDIA is not set +- +-# +-# Multimedia drivers +-# +-CONFIG_DAB=y +-# CONFIG_USB_DABUSB is not set ++# CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 + # CONFIG_DRM is not set ++# CONFIG_STUB_POULSBO is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=m + # CONFIG_FB is not set +@@ -835,7 +962,6 @@ CONFIG_USB=y + # CONFIG_USB_DEVICEFS is not set + CONFIG_USB_DEVICE_CLASS=y + # CONFIG_USB_DYNAMIC_MINORS is not set +-# CONFIG_USB_SUSPEND is not set + # CONFIG_USB_OTG is not set + CONFIG_USB_MON=y + # CONFIG_USB_WUSB is not set +@@ -845,12 +971,17 @@ CONFIG_USB_MON=y + # USB Host Controller Drivers + # + # CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set + CONFIG_USB_EHCI_HCD=y + # CONFIG_USB_EHCI_ROOT_HUB_TT is not set + # CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++# CONFIG_USB_EHCI_FSL is not set + # CONFIG_USB_OXU210HP_HCD is not set + # CONFIG_USB_ISP116X_HCD is not set + # CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set + # CONFIG_USB_OHCI_HCD is not set + # CONFIG_USB_UHCI_HCD is not set + # CONFIG_USB_SL811_HCD is not set +@@ -867,11 +998,11 @@ CONFIG_USB_EHCI_HCD=y + # CONFIG_USB_TMC is not set + + # +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may + # + + # +-# see USB_STORAGE Help for more information ++# also be needed; see USB_STORAGE Help for more info + # + CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_DEBUG is not set +@@ -886,6 +1017,7 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_ONETOUCH is not set + # CONFIG_USB_STORAGE_KARMA is not set + # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_UAS is not set + # CONFIG_USB_LIBUSUAL is not set + + # +@@ -909,11 +1041,9 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_RIO500 is not set + # CONFIG_USB_LEGOTOWER is not set + # CONFIG_USB_LCD is not set +-# CONFIG_USB_BERRY_CHARGE is not set + # CONFIG_USB_LED is not set + # CONFIG_USB_CYPRESS_CY7C63 is not set + # CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_PHIDGET is not set + # CONFIG_USB_IDMOUSE is not set + # CONFIG_USB_FTDI_ELAN is not set + # CONFIG_USB_APPLEDISPLAY is not set +@@ -921,17 +1051,20 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_LD is not set + # CONFIG_USB_TRANCEVIBRATOR is not set + # CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set + # CONFIG_USB_ISIGHTFW is not set +-# CONFIG_USB_VST is not set ++# CONFIG_USB_YUREX is not set + # CONFIG_USB_GADGET is not set + + # + # OTG and related infrastructure + # ++# CONFIG_NOP_USB_XCEIV is not set + # CONFIG_UWB is not set + # CONFIG_MMC is not set + # CONFIG_MEMSTICK is not set + # CONFIG_NEW_LEDS is not set ++# CONFIG_NFC_DEVICES is not set + # CONFIG_ACCESSIBILITY is not set + # CONFIG_INFINIBAND is not set + CONFIG_RTC_LIB=y +@@ -955,16 +1088,20 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_DS1307 is not set + # CONFIG_RTC_DRV_DS1374 is not set + # CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set + # CONFIG_RTC_DRV_MAX6900 is not set + CONFIG_RTC_DRV_RS5C372=y + # CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set + # CONFIG_RTC_DRV_X1205 is not set + # CONFIG_RTC_DRV_PCF8563 is not set + # CONFIG_RTC_DRV_PCF8583 is not set + # CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set + # CONFIG_RTC_DRV_S35390A is not set + # CONFIG_RTC_DRV_FM3130 is not set + # CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set + + # + # SPI RTC drivers +@@ -981,15 +1118,19 @@ CONFIG_RTC_DRV_RS5C372=y + # CONFIG_RTC_DRV_M48T86 is not set + # CONFIG_RTC_DRV_M48T35 is not set + # CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set + # CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set + # CONFIG_RTC_DRV_V3020 is not set + + # + # on-CPU RTC drivers + # ++# CONFIG_RTC_DRV_GENERIC is not set + # CONFIG_RTC_MCF is not set + # CONFIG_RTC_M5441X is not set + # CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set + # CONFIG_UIO is not set + # CONFIG_STAGING is not set + +@@ -1008,6 +1149,7 @@ CONFIG_EXT2_FS=y + # CONFIG_EXT2_FS_XATTR is not set + # CONFIG_EXT2_FS_XIP is not set + CONFIG_EXT3_FS=y ++CONFIG_EXT3_DEFAULTS_TO_ORDERED=y + CONFIG_EXT3_FS_XATTR=y + # CONFIG_EXT3_FS_POSIX_ACL is not set + # CONFIG_EXT3_FS_SECURITY is not set +@@ -1016,20 +1158,27 @@ CONFIG_JBD=y + CONFIG_FS_MBCACHE=y + # CONFIG_REISERFS_FS is not set + # CONFIG_JFS_FS is not set +-# CONFIG_FS_POSIX_ACL is not set +-CONFIG_FILE_LOCKING=y + # CONFIG_XFS_FS is not set + # CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set + # CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y + CONFIG_DNOTIFY=y +-# CONFIG_INOTIFY is not set ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set + # CONFIG_QUOTA is not set +-# CONFIG_AUTOFS_FS is not set ++# CONFIG_QUOTACTL is not set + # CONFIG_AUTOFS4_FS is not set + # CONFIG_FUSE_FS is not set + + # ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# + # CD-ROM/DVD Filesystems + # + # CONFIG_ISO9660_FS is not set +@@ -1067,6 +1216,7 @@ CONFIG_MISC_FILESYSTEMS=y + # CONFIG_BEFS_FS is not set + # CONFIG_BFS_FS is not set + # CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set + CONFIG_JFFS2_FS=y + CONFIG_JFFS2_FS_DEBUG=0 + CONFIG_JFFS2_FS_WRITEBUFFER=y +@@ -1078,6 +1228,7 @@ CONFIG_JFFS2_ZLIB=y + # CONFIG_JFFS2_LZO is not set + CONFIG_JFFS2_RTIME=y + # CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set + # CONFIG_CRAMFS is not set + # CONFIG_SQUASHFS is not set + # CONFIG_VXFS_FS is not set +@@ -1086,6 +1237,10 @@ CONFIG_MINIX_FS=y + # CONFIG_HPFS_FS is not set + # CONFIG_QNX4FS_FS is not set + CONFIG_ROMFS_FS=y ++CONFIG_ROMFS_BACKED_BY_BLOCK=y ++# CONFIG_ROMFS_BACKED_BY_MTD is not set ++# CONFIG_ROMFS_BACKED_BY_BOTH is not set ++CONFIG_ROMFS_ON_BLOCK=y + # CONFIG_SYSV_FS is not set + # CONFIG_UFS_FS is not set + CONFIG_NETWORK_FILESYSTEMS=y +@@ -1097,10 +1252,8 @@ CONFIG_ROOT_NFS=y + CONFIG_LOCKD=y + CONFIG_NFS_COMMON=y + CONFIG_SUNRPC=y +-# CONFIG_SUNRPC_REGISTER_V4 is not set + # CONFIG_RPCSEC_GSS_KRB5 is not set +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-# CONFIG_SMB_FS is not set ++# CONFIG_CEPH_FS is not set + # CONFIG_CIFS is not set + # CONFIG_NCP_FS is not set + # CONFIG_CODA_FS is not set +@@ -1167,7 +1320,6 @@ CONFIG_NLS_ISO8859_1=y + # CONFIG_NLS_KOI8_R is not set + # CONFIG_NLS_KOI8_U is not set + CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set + + # + # Kernel hacking +@@ -1177,19 +1329,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y + # CONFIG_ENABLE_MUST_CHECK is not set + CONFIG_FRAME_WARN=1024 + # CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set + # CONFIG_UNUSED_SYMBOLS is not set + # CONFIG_DEBUG_FS is not set + # CONFIG_HEADERS_CHECK is not set + # CONFIG_DEBUG_KERNEL is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++CONFIG_BKL=y ++# CONFIG_SPARSE_RCU_POINTER is not set + CONFIG_DEBUG_BUGVERBOSE=y + CONFIG_DEBUG_MEMORY_INIT=y +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set + # CONFIG_SYSCTL_SYSCALL_CHECK is not set +- +-# +-# Tracers +-# +-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set + # CONFIG_SAMPLES is not set + # CONFIG_BOOTPARAM is not set + +@@ -1197,15 +1348,16 @@ CONFIG_DEBUG_MEMORY_INIT=y + # Security options + # + # CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set + # CONFIG_SECURITY is not set + # CONFIG_SECURITYFS is not set +-# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" + CONFIG_CRYPTO=y + + # + # Crypto core or helper + # +-# CONFIG_CRYPTO_FIPS is not set + CONFIG_CRYPTO_ALGAPI=y + CONFIG_CRYPTO_ALGAPI2=y + CONFIG_CRYPTO_AEAD=y +@@ -1215,10 +1367,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y + CONFIG_CRYPTO_HASH=y + CONFIG_CRYPTO_HASH2=y + CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y + CONFIG_CRYPTO_MANAGER=y + CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set + # CONFIG_CRYPTO_GF128MUL is not set + # CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y + # CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=y + CONFIG_CRYPTO_TEST=m +@@ -1246,11 +1401,13 @@ CONFIG_CRYPTO_CBC=y + # + CONFIG_CRYPTO_HMAC=y + # CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set + + # + # Digest + # + CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set + # CONFIG_CRYPTO_MD4 is not set + CONFIG_CRYPTO_MD5=y + # CONFIG_CRYPTO_MICHAEL_MIC is not set +@@ -1267,9 +1424,9 @@ CONFIG_CRYPTO_SHA1=y + # + # Ciphers + # +-# CONFIG_CRYPTO_AES is not set ++CONFIG_CRYPTO_AES=y + # CONFIG_CRYPTO_ANUBIS is not set +-# CONFIG_CRYPTO_ARC4 is not set ++CONFIG_CRYPTO_ARC4=y + # CONFIG_CRYPTO_BLOWFISH is not set + # CONFIG_CRYPTO_CAMELLIA is not set + # CONFIG_CRYPTO_CAST5 is not set +@@ -1287,22 +1444,19 @@ CONFIG_CRYPTO_DES=y + # Compression + # + # CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set + # CONFIG_CRYPTO_LZO is not set + + # + # Random Number Generation + # + # CONFIG_CRYPTO_ANSI_CPRNG is not set +- +-# +-# OCF Configuration +-# +-# CONFIG_OCF_OCF is not set +- +-# +-# Talitos Driver +-# +-# CONFIG_CRYPTO_HW is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_HIFN_795X is not set ++CONFIG_CRYPTO_DEV_CF_TALITOS=y ++# CONFIG_BINARY_PRINTF is not set + + # + # Library routines +@@ -1318,7 +1472,23 @@ CONFIG_CRC32=y + CONFIG_LIBCRC32C=y + CONFIG_ZLIB_INFLATE=y + CONFIG_ZLIB_DEFLATE=y +-CONFIG_PLIST=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_BZIP2=y ++CONFIG_DECOMPRESS_LZMA=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y + CONFIG_HAS_IOMEM=y + CONFIG_HAS_IOPORT=y + CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y +--- a/arch/m68k/configs/m5485evb_defconfig ++++ b/arch/m68k/configs/m5485evb_defconfig +@@ -1,7 +1,7 @@ + # + # Automatically generated make config: don't edit +-# Linux kernel version: 2.6.29 +-# Tue Aug 24 16:19:05 2010 ++# Linux kernel version: 2.6.38 ++# Tue Aug 2 16:47:50 2011 + # + CONFIG_M68K=y + CONFIG_MMU=y +@@ -17,7 +17,9 @@ CONFIG_GENERIC_IOMAP=y + # CONFIG_NO_IOPORT is not set + # CONFIG_NO_DMA is not set + CONFIG_HZ=100 ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_CONSTRUCTORS=y + + # + # General setup +@@ -25,6 +27,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNA + CONFIG_EXPERIMENTAL=y + CONFIG_BROKEN_ON_SMP=y + CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" + CONFIG_LOCALVERSION="" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SWAP=y +@@ -34,37 +37,34 @@ CONFIG_SYSVIPC_SYSCTL=y + # CONFIG_BSD_PROCESS_ACCT is not set + # CONFIG_TASKSTATS is not set + # CONFIG_AUDIT is not set ++# CONFIG_HAVE_GENERIC_HARDIRQS is not set + + # + # RCU Subsystem + # +-CONFIG_CLASSIC_RCU=y +-# CONFIG_TREE_RCU is not set ++CONFIG_TINY_RCU=y + # CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set + # CONFIG_TREE_RCU_TRACE is not set +-# CONFIG_PREEMPT_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=17 +-CONFIG_GROUP_SCHED=y +-CONFIG_FAIR_GROUP_SCHED=y +-# CONFIG_RT_GROUP_SCHED is not set +-CONFIG_USER_SCHED=y +-# CONFIG_CGROUP_SCHED is not set + # CONFIG_CGROUPS is not set +-CONFIG_SYSFS_DEPRECATED=y +-CONFIG_SYSFS_DEPRECATED_V2=y +-# CONFIG_RELAY is not set + CONFIG_NAMESPACES=y + # CONFIG_UTS_NS is not set + # CONFIG_IPC_NS is not set + # CONFIG_USER_NS is not set + # CONFIG_PID_NS is not set + # CONFIG_NET_NS is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set + # CONFIG_BLK_DEV_INITRD is not set + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set + CONFIG_SYSCTL=y + CONFIG_ANON_INODES=y ++# CONFIG_EXPERT is not set + # CONFIG_EMBEDDED is not set + CONFIG_UID16=y + CONFIG_SYSCTL_SYSCALL=y +@@ -82,13 +82,20 @@ CONFIG_TIMERFD=y + CONFIG_EVENTFD=y + CONFIG_SHMEM=y + CONFIG_AIO=y ++ ++# ++# Kernel Performance Events And Counters ++# + CONFIG_VM_EVENT_COUNTERS=y + CONFIG_PCI_QUIRKS=y + CONFIG_COMPAT_BRK=y + CONFIG_SLAB=y + # CONFIG_SLUB is not set +-# CONFIG_SLOB is not set + # CONFIG_PROFILING is not set ++ ++# ++# GCOV-based kernel profiling ++# + # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set + CONFIG_SLABINFO=y + CONFIG_RT_MUTEXES=y +@@ -100,8 +107,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y + # CONFIG_MODVERSIONS is not set + # CONFIG_MODULE_SRCVERSION_ALL is not set + CONFIG_BLOCK=y +-CONFIG_LBD=y +-# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set + # CONFIG_BLK_DEV_INTEGRITY is not set + +@@ -109,14 +115,41 @@ CONFIG_LBD=y + # IO Schedulers + # + CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y + CONFIG_IOSCHED_DEADLINE=y + CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set + # CONFIG_DEFAULT_DEADLINE is not set + CONFIG_DEFAULT_CFQ=y + # CONFIG_DEFAULT_NOOP is not set + CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set + # CONFIG_FREEZER is not set + + # +@@ -180,18 +213,19 @@ CONFIG_SINGLE_MEMORY_CHUNK=y + # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set + CONFIG_SELECT_MEMORY_MODEL=y + CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set + CONFIG_FLATMEM=y + CONFIG_FLAT_NODE_MEM_MAP=y + CONFIG_NEED_MULTIPLE_NODES=y + CONFIG_PAGEFLAGS_EXTENDED=y + CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set + # CONFIG_PHYS_ADDR_T_64BIT is not set + CONFIG_ZONE_DMA_FLAG=1 + CONFIG_BOUNCE=y + CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y + + # + # General setup +@@ -204,8 +238,8 @@ CONFIG_HAVE_AOUT=y + CONFIG_PROC_HARDWARE=y + CONFIG_ZONE_DMA=y + # CONFIG_ARCH_SUPPORTS_MSI is not set +-CONFIG_PCI_LEGACY=y + # CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set + + # + # Power management options +@@ -216,9 +250,7 @@ CONFIG_NET=y + # + # Networking options + # +-CONFIG_COMPAT_NET_DEV_OPS=y + CONFIG_PACKET=y +-# CONFIG_PACKET_MMAP is not set + CONFIG_UNIX=y + CONFIG_XFRM=y + # CONFIG_XFRM_USER is not set +@@ -241,7 +273,7 @@ CONFIG_IP_PNP=y + # CONFIG_IP_PNP_BOOTP is not set + # CONFIG_IP_PNP_RARP is not set + # CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE is not set ++# CONFIG_NET_IPGRE_DEMUX is not set + # CONFIG_ARPD is not set + # CONFIG_SYN_COOKIES is not set + CONFIG_INET_AH=y +@@ -261,11 +293,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set + # CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set + # CONFIG_NETFILTER is not set + # CONFIG_IP_DCCP is not set + # CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set + # CONFIG_TIPC is not set + # CONFIG_ATM is not set ++# CONFIG_L2TP is not set + # CONFIG_BRIDGE is not set + # CONFIG_NET_DSA is not set + # CONFIG_VLAN_8021Q is not set +@@ -277,8 +312,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" + # CONFIG_LAPB is not set + # CONFIG_ECONET is not set + # CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set + # CONFIG_NET_SCHED is not set + # CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set + + # + # Network testing +@@ -293,25 +331,83 @@ CONFIG_CAN_RAW=y + # CAN Device Drivers + # + # CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_SLCAN is not set + CONFIG_CAN_DEV=y + CONFIG_CAN_CALC_BITTIMING=y ++CONFIG_HAVE_CAN_FLEXCAN=y + CONFIG_CAN_FLEXCAN=y +-CONFIG_CAN_MCF=y ++CONFIG_FLEXCAN_NORXFIFO=y ++# CONFIG_PCH_CAN is not set ++# CONFIG_CAN_MSCAN is not set ++# CONFIG_CAN_SJA1000 is not set ++ ++# ++# CAN USB interfaces ++# ++# CONFIG_CAN_EMS_USB is not set ++# CONFIG_CAN_ESD_USB2 is not set ++# CONFIG_CAN_SOFTING is not set + # CONFIG_CAN_DEBUG_DEVICES is not set +-# CONFIG_IRDA is not set ++CONFIG_IRDA=y ++ ++# ++# IrDA protocols ++# ++# CONFIG_IRLAN is not set ++CONFIG_IRNET=y ++CONFIG_IRCOMM=y ++# CONFIG_IRDA_ULTRA is not set ++ ++# ++# IrDA options ++# ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++# CONFIG_IRDA_FAST_RR is not set ++# CONFIG_IRDA_DEBUG is not set ++ ++# ++# Infrared-port device drivers ++# ++ ++# ++# SIR device drivers ++# ++CONFIG_IRTTY_SIR=y ++ ++# ++# Dongle support ++# ++# CONFIG_DONGLE is not set ++# CONFIG_KINGSUN_DONGLE is not set ++# CONFIG_KSDAZZLE_DONGLE is not set ++# CONFIG_KS959_DONGLE is not set ++ ++# ++# FIR device drivers ++# ++# CONFIG_USB_IRDA is not set ++# CONFIG_SIGMATEL_FIR is not set ++# CONFIG_TOSHIBA_FIR is not set ++# CONFIG_VLSI_FIR is not set ++# CONFIG_MCS_FIR is not set + # CONFIG_BT is not set + # CONFIG_AF_RXRPC is not set +-# CONFIG_PHONET is not set + CONFIG_WIRELESS=y + # CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-# CONFIG_WIRELESS_EXT is not set + # CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++ ++# ++# Some wireless drivers require a rate control algorithm ++# + # CONFIG_WIMAX is not set + # CONFIG_RFKILL is not set + # CONFIG_NET_9P is not set +-# CONFIG_KLIPS is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set + + # + # Device Drivers +@@ -321,6 +417,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y + # Generic Driver Options + # + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set + # CONFIG_STANDALONE is not set + CONFIG_PREVENT_FIRMWARE_BUILD=y + CONFIG_FW_LOADER=y +@@ -330,9 +427,9 @@ CONFIG_EXTRA_FIRMWARE="" + # CONFIG_CONNECTOR is not set + CONFIG_MTD=y + # CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_TESTS is not set + CONFIG_MTD_CONCAT=y + CONFIG_MTD_PARTITIONS=y +-# CONFIG_MTD_TESTS is not set + # CONFIG_MTD_REDBOOT_PARTS is not set + CONFIG_MTD_CMDLINE_PARTS=y + # CONFIG_MTD_AR7_PARTS is not set +@@ -348,6 +445,7 @@ CONFIG_MTD_BLOCK=y + # CONFIG_INFTL is not set + # CONFIG_RFD_FTL is not set + # CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set + # CONFIG_MTD_OOPS is not set + + # +@@ -409,10 +507,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 + # LPDDR flash memory drivers + # + # CONFIG_MTD_LPDDR is not set +- +-# +-# UBI - Unsorted block images +-# + # CONFIG_MTD_UBI is not set + # CONFIG_PARPORT is not set + CONFIG_BLK_DEV=y +@@ -423,6 +517,10 @@ CONFIG_BLK_DEV=y + # CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y + # CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# + # CONFIG_BLK_DEV_NBD is not set + # CONFIG_BLK_DEV_SX8 is not set + # CONFIG_BLK_DEV_UB is not set +@@ -433,13 +531,26 @@ CONFIG_BLK_DEV_RAM_SIZE=64000 + # CONFIG_CDROM_PKTCDVD is not set + # CONFIG_ATA_OVER_ETH is not set + # CONFIG_BLK_DEV_HD is not set ++# CONFIG_BLK_DEV_RBD is not set + CONFIG_MISC_DEVICES=y ++# CONFIG_AD525X_DPOT is not set + # CONFIG_PHANTOM is not set + # CONFIG_SGI_IOC4 is not set + # CONFIG_TIFM_CORE is not set + # CONFIG_ICS932S401 is not set + # CONFIG_ENCLOSURE_SERVICES is not set + # CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085 is not set ++# CONFIG_PCH_PHUB is not set + # CONFIG_C2PORT is not set + + # +@@ -447,7 +558,13 @@ CONFIG_MISC_DEVICES=y + # + # CONFIG_EEPROM_AT24 is not set + # CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set + # CONFIG_EEPROM_93CX6 is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# + CONFIG_HAVE_IDE=y + CONFIG_IDE=y + +@@ -501,6 +618,7 @@ CONFIG_IDE_PROC_FS=y + # + # SCSI device support + # ++CONFIG_SCSI_MOD=y + # CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y + CONFIG_SCSI_DMA=y +@@ -517,10 +635,6 @@ CONFIG_BLK_DEV_SD=y + # CONFIG_BLK_DEV_SR is not set + # CONFIG_CHR_DEV_SG is not set + # CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_CONSTANTS is not set + # CONFIG_SCSI_LOGGING is not set +@@ -533,81 +647,113 @@ CONFIG_SCSI_WAIT_SCAN=m + # CONFIG_SCSI_SPI_ATTRS is not set + # CONFIG_SCSI_FC_ATTRS is not set + # CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set + # CONFIG_SCSI_SAS_LIBSAS is not set + # CONFIG_SCSI_SRP_ATTRS is not set + # CONFIG_SCSI_LOWLEVEL is not set + # CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set + CONFIG_ATA=y + # CONFIG_ATA_NONSTANDARD is not set ++CONFIG_ATA_VERBOSE_ERROR=y + CONFIG_SATA_PMP=y ++ ++# ++# Controllers with non-SFF native interface ++# + # CONFIG_SATA_AHCI is not set ++# CONFIG_SATA_AHCI_PLATFORM is not set ++# CONFIG_SATA_INIC162X is not set ++# CONFIG_SATA_ACARD_AHCI is not set + CONFIG_SATA_SIL24=y + CONFIG_ATA_SFF=y +-# CONFIG_SATA_SVW is not set ++ ++# ++# SFF controllers with custom DMA interface ++# ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_SX4 is not set ++CONFIG_ATA_BMDMA=y ++ ++# ++# SATA SFF controllers with BMDMA ++# + # CONFIG_ATA_PIIX is not set + # CONFIG_SATA_MV is not set + # CONFIG_SATA_NV is not set +-# CONFIG_PDC_ADMA is not set +-# CONFIG_SATA_QSTOR is not set + # CONFIG_SATA_PROMISE is not set +-# CONFIG_SATA_SX4 is not set + CONFIG_SATA_SIL=y + # CONFIG_SATA_SIS is not set ++# CONFIG_SATA_SVW is not set + # CONFIG_SATA_ULI is not set + # CONFIG_SATA_VIA is not set + # CONFIG_SATA_VITESSE is not set +-# CONFIG_SATA_INIC162X is not set ++ ++# ++# PATA SFF controllers with BMDMA ++# + # CONFIG_PATA_ALI is not set + # CONFIG_PATA_AMD is not set + # CONFIG_PATA_ARTOP is not set + # CONFIG_PATA_ATIIXP is not set +-# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_ATP867X is not set + # CONFIG_PATA_CMD64X is not set + # CONFIG_PATA_CS5520 is not set + # CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CS5536 is not set + # CONFIG_PATA_CYPRESS is not set + # CONFIG_PATA_EFAR is not set +-# CONFIG_ATA_GENERIC is not set + # CONFIG_PATA_HPT366 is not set + # CONFIG_PATA_HPT37X is not set + # CONFIG_PATA_HPT3X2N is not set + # CONFIG_PATA_HPT3X3 is not set +-# CONFIG_PATA_IT821X is not set + # CONFIG_PATA_IT8213 is not set ++# CONFIG_PATA_IT821X is not set + # CONFIG_PATA_JMICRON is not set +-# CONFIG_PATA_TRIFLEX is not set + # CONFIG_PATA_MARVELL is not set +-# CONFIG_PATA_MPIIX is not set +-# CONFIG_PATA_OLDPIIX is not set + # CONFIG_PATA_NETCELL is not set + # CONFIG_PATA_NINJA32 is not set +-# CONFIG_PATA_NS87410 is not set + # CONFIG_PATA_NS87415 is not set +-# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OLDPIIX is not set + # CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC2027X is not set + # CONFIG_PATA_PDC_OLD is not set + # CONFIG_PATA_RADISYS is not set +-# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_RDC is not set + # CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SCH is not set + # CONFIG_PATA_SERVERWORKS is not set +-# CONFIG_PATA_PDC2027X is not set + # CONFIG_PATA_SIL680 is not set + # CONFIG_PATA_SIS is not set ++# CONFIG_PATA_TOSHIBA is not set ++# CONFIG_PATA_TRIFLEX is not set + # CONFIG_PATA_VIA is not set + # CONFIG_PATA_WINBOND is not set +-# CONFIG_PATA_SCH is not set +-# CONFIG_MD is not set +-# CONFIG_FUSION is not set + + # +-# IEEE 1394 (FireWire) support ++# PIO-only SFF controllers ++# ++# CONFIG_PATA_CMD640_PCI is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_RZ1000 is not set ++ ++# ++# Generic fallback / legacy drivers + # ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_LEGACY is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set + + # +-# Enable only one of the two stacks, unless you know what you are doing ++# IEEE 1394 (FireWire) support + # + # CONFIG_FIREWIRE is not set +-# CONFIG_IEEE1394 is not set ++# CONFIG_FIREWIRE_NOSY is not set + # CONFIG_I2O is not set + CONFIG_NETDEVICES=y + # CONFIG_DUMMY is not set +@@ -617,6 +763,7 @@ CONFIG_NETDEVICES=y + # CONFIG_TUN is not set + # CONFIG_VETH is not set + # CONFIG_ARCNET is not set ++CONFIG_MII=y + CONFIG_PHYLIB=y + + # +@@ -631,22 +778,24 @@ CONFIG_PHYLIB=y + # CONFIG_SMSC_PHY is not set + # CONFIG_BROADCOM_PHY is not set + CONFIG_BROADCOM5222_PHY=y ++# CONFIG_BCM63XX_PHY is not set + # CONFIG_ICPLUS_PHY is not set + # CONFIG_REALTEK_PHY is not set + # CONFIG_NATIONAL_PHY is not set + # CONFIG_NATIONAL8364x_PHY is not set + # CONFIG_NATIONAL8384x_PHY is not set +-# CONFIG_MicrelKSZ8041_PHY is not set + # CONFIG_STE10XP is not set + # CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set + # CONFIG_FIXED_PHY is not set + # CONFIG_MDIO_BITBANG is not set + CONFIG_NET_ETHERNET=y +-CONFIG_MII=y + # CONFIG_HAPPYMEAL is not set + # CONFIG_SUNGEM is not set + # CONFIG_CASSINI is not set + # CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_SMC91X is not set ++# CONFIG_ETHOC is not set + # CONFIG_DNET is not set + # CONFIG_NET_TULIP is not set + # CONFIG_HP100 is not set +@@ -661,6 +810,7 @@ CONFIG_NET_PCI=y + # CONFIG_PCNET32 is not set + # CONFIG_AMD8111_ETH is not set + # CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_KSZ884X_PCI is not set + # CONFIG_B44 is not set + # CONFIG_FORCEDETH is not set + CONFIG_E100=y +@@ -679,6 +829,7 @@ CONFIG_8139TOO_PIO=y + # CONFIG_SMSC9420 is not set + # CONFIG_SUNDANCE is not set + # CONFIG_TLAN is not set ++# CONFIG_KS8851_MLL is not set + # CONFIG_VIA_RHINE is not set + # CONFIG_SC92031 is not set + CONFIG_FEC_548x=y +@@ -692,6 +843,7 @@ CONFIG_E1000=y + # CONFIG_E1000E is not set + # CONFIG_IP1000 is not set + # CONFIG_IGB is not set ++# CONFIG_IGBVF is not set + # CONFIG_NS83820 is not set + # CONFIG_HAMACHI is not set + # CONFIG_YELLOWFIN is not set +@@ -702,20 +854,21 @@ CONFIG_R8169=y + # CONFIG_VIA_VELOCITY is not set + # CONFIG_TIGON3 is not set + # CONFIG_BNX2 is not set ++# CONFIG_CNIC is not set + # CONFIG_QLA3XXX is not set + # CONFIG_ATL1 is not set + # CONFIG_ATL1E is not set + # CONFIG_ATL1C is not set + # CONFIG_JME is not set ++# CONFIG_STMMAC_ETH is not set ++# CONFIG_PCH_GBE is not set + # CONFIG_NETDEV_10000 is not set + # CONFIG_TR is not set +- +-# +-# Wireless LAN +-# +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set ++CONFIG_WLAN=y ++# CONFIG_ATMEL is not set ++# CONFIG_PRISM54 is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_HOSTAP is not set + + # + # Enable WiMAX (Networking options) to see the WiMAX drivers +@@ -729,15 +882,30 @@ CONFIG_R8169=y + # CONFIG_USB_PEGASUS is not set + # CONFIG_USB_RTL8150 is not set + # CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set + # CONFIG_WAN is not set ++ ++# ++# CAIF transport drivers ++# + # CONFIG_FDDI is not set + # CONFIG_HIPPI is not set +-# CONFIG_PPP is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++# CONFIG_PPP_FILTER is not set ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++CONFIG_PPPOE=y + # CONFIG_SLIP is not set ++CONFIG_SLHC=y + # CONFIG_NET_FC is not set + # CONFIG_NETCONSOLE is not set + # CONFIG_NETPOLL is not set + # CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_VMXNET3 is not set + # CONFIG_ISDN is not set + # CONFIG_PHONE is not set + +@@ -747,6 +915,7 @@ CONFIG_R8169=y + CONFIG_INPUT=y + # CONFIG_INPUT_FF_MEMLESS is not set + # CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set + + # + # Userland interfaces +@@ -763,12 +932,18 @@ CONFIG_INPUT_EVDEV=y + # Input Device Drivers + # + CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set + # CONFIG_KEYBOARD_ATKBD is not set +-# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_QT2160 is not set + # CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set + # CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set + # CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set + # CONFIG_INPUT_MOUSE is not set + # CONFIG_INPUT_JOYSTICK is not set + # CONFIG_INPUT_TABLET is not set +@@ -782,6 +957,8 @@ CONFIG_SERIO=y + CONFIG_SERIO_SERPORT=y + # CONFIG_SERIO_PCIPS2 is not set + # CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set + # CONFIG_GAMEPORT is not set + + # +@@ -794,6 +971,7 @@ CONFIG_HW_CONSOLE=y + # CONFIG_VT_HW_CONSOLE_BINDING is not set + CONFIG_DEVKMEM=y + # CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set + # CONFIG_NOZOMI is not set + + # +@@ -804,26 +982,34 @@ CONFIG_DEVKMEM=y + # + # Non-8250 serial port support + # ++# CONFIG_SERIAL_MFD_HSU is not set + CONFIG_SERIAL_CORE=y + CONFIG_SERIAL_CORE_CONSOLE=y +-# CONFIG_SERIAL_COLDFIRE_IRDA is not set ++CONFIG_SERIAL_COLDFIRE_IRDA=y + # CONFIG_SERIAL_COLDFIRE_EDMA is not set + CONFIG_SERIAL_MCF=y + CONFIG_SERIAL_MCF_BAUDRATE=115200 + CONFIG_SERIAL_MCF_CONSOLE=y + # CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set + CONFIG_UNIX98_PTYS=y + # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set + # CONFIG_IPMI_HANDLER is not set +-# CONFIG_HW_RANDOM is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set + # CONFIG_R3964 is not set + # CONFIG_APPLICOM is not set + # CONFIG_RAW_DRIVER is not set + # CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set + CONFIG_I2C=y + CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y + CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set + CONFIG_I2C_HELPER_AUTO=y + + # +@@ -851,9 +1037,13 @@ CONFIG_I2C_HELPER_AUTO=y + # + # I2C system bus drivers (mostly embedded / system-on-chip) + # ++# CONFIG_I2C_INTEL_MID is not set + CONFIG_I2C_MCF=y + # CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++# CONFIG_I2C_EG20T is not set + + # + # External I2C/SMBus adapter drivers +@@ -863,36 +1053,26 @@ CONFIG_I2C_MCF=y + # CONFIG_I2C_TINY_USB is not set + + # +-# Graphics adapter I2C/DDC channel drivers +-# +-# CONFIG_I2C_VOODOO3 is not set +- +-# + # Other I2C/SMBus bus drivers + # +-# CONFIG_I2C_PCA_PLATFORM is not set + # CONFIG_I2C_STUB is not set +- +-# +-# Miscellaneous I2C Chip support +-# +-# CONFIG_DS1682 is not set +-# CONFIG_SENSORS_PCF8574 is not set +-# CONFIG_PCF8575 is not set +-# CONFIG_SENSORS_PCA9539 is not set +-# CONFIG_SENSORS_PCF8591 is not set +-# CONFIG_SENSORS_MAX6875 is not set +-# CONFIG_SENSORS_TSL2550 is not set + # CONFIG_I2C_DEBUG_CORE is not set + # CONFIG_I2C_DEBUG_ALGO is not set + # CONFIG_I2C_DEBUG_BUS is not set +-# CONFIG_I2C_DEBUG_CHIP is not set + # CONFIG_SPI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# + # CONFIG_W1 is not set + # CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set + # CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set + CONFIG_WATCHDOG=y + # CONFIG_WATCHDOG_NOWAYOUT is not set + +@@ -919,41 +1099,33 @@ CONFIG_SSB_POSSIBLE=y + # Sonics Silicon Backplane + # + # CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# ++CONFIG_MFD_SUPPORT=y + # CONFIG_MFD_CORE is not set + # CONFIG_MFD_SM501 is not set + # CONFIG_HTC_PASIC3 is not set ++# CONFIG_TPS6507X is not set + # CONFIG_MFD_TMIO is not set + # CONFIG_PMIC_DA903X is not set ++# CONFIG_PMIC_ADP5520 is not set + # CONFIG_MFD_WM8400 is not set +-# CONFIG_MFD_WM8350_I2C is not set + # CONFIG_MFD_PCF50633 is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_CS5535 is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_WL1273_CORE is not set + # CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-# CONFIG_VIDEO_DEV is not set +-# CONFIG_DVB_CORE is not set +-# CONFIG_VIDEO_MEDIA is not set +- +-# +-# Multimedia drivers +-# +-CONFIG_DAB=y +-# CONFIG_USB_DABUSB is not set ++# CONFIG_MEDIA_SUPPORT is not set + + # + # Graphics support + # ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 + # CONFIG_DRM is not set ++# CONFIG_STUB_POULSBO is not set + # CONFIG_VGASTATE is not set + CONFIG_VIDEO_OUTPUT_CONTROL=m + CONFIG_FB=y +@@ -969,6 +1141,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y + # CONFIG_FB_SYS_IMAGEBLIT is not set + # CONFIG_FB_FOREIGN_ENDIAN is not set + # CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_WMT_GE_ROPS is not set + CONFIG_FB_DEFERRED_IO=y + # CONFIG_FB_SVGALIB is not set + # CONFIG_FB_MACMODES is not set +@@ -995,7 +1168,6 @@ CONFIG_FB_SMI=y + # CONFIG_FB_S3 is not set + # CONFIG_FB_SAVAGE is not set + # CONFIG_FB_SIS is not set +-# CONFIG_FB_VIA is not set + # CONFIG_FB_NEOMAGIC is not set + # CONFIG_FB_KYRO is not set + # CONFIG_FB_3DFX is not set +@@ -1005,9 +1177,11 @@ CONFIG_FB_SMI=y + # CONFIG_FB_ARK is not set + # CONFIG_FB_PM3 is not set + # CONFIG_FB_CARMINE is not set ++# CONFIG_FB_UDL is not set + # CONFIG_FB_VIRTUAL is not set + # CONFIG_FB_METRONOME is not set + # CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set + + # +@@ -1040,7 +1214,6 @@ CONFIG_LOGO_LINUX_CLUT224=y + # CONFIG_SOUND is not set + CONFIG_HID_SUPPORT=y + CONFIG_HID=y +-CONFIG_HID_DEBUG=y + # CONFIG_HIDRAW is not set + + # +@@ -1053,31 +1226,55 @@ CONFIG_USB_HID=y + # + # Special HID drivers + # +-CONFIG_HID_COMPAT=y ++# CONFIG_HID_3M_PCT is not set + CONFIG_HID_A4TECH=y ++# CONFIG_HID_ACRUX_FF is not set + CONFIG_HID_APPLE=y + CONFIG_HID_BELKIN=y ++# CONFIG_HID_CANDO is not set + CONFIG_HID_CHERRY=y + CONFIG_HID_CHICONY=y + CONFIG_HID_CYPRESS=y ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_EGALAX is not set + CONFIG_HID_EZKEY=y ++CONFIG_HID_KYE=y ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set + CONFIG_HID_GYRATION=y ++# CONFIG_HID_TWINHAN is not set ++CONFIG_HID_KENSINGTON=y + CONFIG_HID_LOGITECH=y + # CONFIG_LOGITECH_FF is not set + # CONFIG_LOGIRUMBLEPAD2_FF is not set ++# CONFIG_LOGIG940_FF is not set ++# CONFIG_LOGIWII_FF is not set + CONFIG_HID_MICROSOFT=y ++# CONFIG_HID_MOSART is not set + CONFIG_HID_MONTEREY=y ++# CONFIG_HID_MULTITOUCH is not set + CONFIG_HID_NTRIG=y ++# CONFIG_HID_ORTEK is not set + CONFIG_HID_PANTHERLORD=y + # CONFIG_PANTHERLORD_FF is not set + CONFIG_HID_PETALYNX=y ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_QUANTA is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_ROCCAT_KONE is not set ++# CONFIG_HID_ROCCAT_KONEPLUS is not set ++# CONFIG_HID_ROCCAT_PYRA is not set + CONFIG_HID_SAMSUNG=y + CONFIG_HID_SONY=y ++# CONFIG_HID_STANTUM is not set + CONFIG_HID_SUNPLUS=y +-# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set + CONFIG_HID_TOPSEED=y +-# CONFIG_THRUSTMASTER_FF is not set +-# CONFIG_ZEROPLUS_FF is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set + CONFIG_USB_SUPPORT=y + CONFIG_USB_ARCH_HAS_HCD=y + CONFIG_USB_ARCH_HAS_OHCI=y +@@ -1092,7 +1289,6 @@ CONFIG_USB=y + CONFIG_USB_DEVICEFS=y + # CONFIG_USB_DEVICE_CLASS is not set + # CONFIG_USB_DYNAMIC_MINORS is not set +-# CONFIG_USB_SUSPEND is not set + # CONFIG_USB_OTG is not set + CONFIG_USB_MON=y + # CONFIG_USB_WUSB is not set +@@ -1102,12 +1298,17 @@ CONFIG_USB_MON=y + # USB Host Controller Drivers + # + # CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_ROOT_HUB_TT=y + # CONFIG_USB_EHCI_TT_NEWSCHED is not set ++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y ++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y ++# CONFIG_USB_EHCI_FSL is not set + # CONFIG_USB_OXU210HP_HCD is not set + # CONFIG_USB_ISP116X_HCD is not set + # CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set + # CONFIG_USB_OHCI_HCD is not set + # CONFIG_USB_UHCI_HCD is not set + # CONFIG_USB_SL811_HCD is not set +@@ -1124,11 +1325,11 @@ CONFIG_USB_EHCI_ROOT_HUB_TT=y + # CONFIG_USB_TMC is not set + + # +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may + # + + # +-# see USB_STORAGE Help for more information ++# also be needed; see USB_STORAGE Help for more info + # + CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_DEBUG is not set +@@ -1143,6 +1344,7 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_STORAGE_ONETOUCH is not set + # CONFIG_USB_STORAGE_KARMA is not set + # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_UAS is not set + # CONFIG_USB_LIBUSUAL is not set + + # +@@ -1166,11 +1368,9 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_RIO500 is not set + # CONFIG_USB_LEGOTOWER is not set + # CONFIG_USB_LCD is not set +-# CONFIG_USB_BERRY_CHARGE is not set + # CONFIG_USB_LED is not set + # CONFIG_USB_CYPRESS_CY7C63 is not set + # CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_PHIDGET is not set + # CONFIG_USB_IDMOUSE is not set + # CONFIG_USB_FTDI_ELAN is not set + # CONFIG_USB_APPLEDISPLAY is not set +@@ -1180,16 +1380,18 @@ CONFIG_USB_STORAGE=y + # CONFIG_USB_IOWARRIOR is not set + # CONFIG_USB_TEST is not set + # CONFIG_USB_ISIGHTFW is not set +-# CONFIG_USB_VST is not set ++# CONFIG_USB_YUREX is not set + # CONFIG_USB_GADGET is not set + + # + # OTG and related infrastructure + # ++# CONFIG_NOP_USB_XCEIV is not set + # CONFIG_UWB is not set + # CONFIG_MMC is not set + # CONFIG_MEMSTICK is not set + # CONFIG_NEW_LEDS is not set ++# CONFIG_NFC_DEVICES is not set + # CONFIG_ACCESSIBILITY is not set + # CONFIG_INFINIBAND is not set + CONFIG_RTC_LIB=y +@@ -1213,16 +1415,20 @@ CONFIG_RTC_INTF_DEV=y + # CONFIG_RTC_DRV_DS1307 is not set + # CONFIG_RTC_DRV_DS1374 is not set + # CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set + # CONFIG_RTC_DRV_MAX6900 is not set + CONFIG_RTC_DRV_RS5C372=y + # CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set + # CONFIG_RTC_DRV_X1205 is not set + # CONFIG_RTC_DRV_PCF8563 is not set + # CONFIG_RTC_DRV_PCF8583 is not set + # CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set + # CONFIG_RTC_DRV_S35390A is not set + # CONFIG_RTC_DRV_FM3130 is not set + # CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set + + # + # SPI RTC drivers +@@ -1239,15 +1445,19 @@ CONFIG_RTC_DRV_RS5C372=y + # CONFIG_RTC_DRV_M48T86 is not set + # CONFIG_RTC_DRV_M48T35 is not set + # CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set + # CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set + # CONFIG_RTC_DRV_V3020 is not set + + # + # on-CPU RTC drivers + # ++# CONFIG_RTC_DRV_GENERIC is not set + # CONFIG_RTC_MCF is not set + # CONFIG_RTC_M5441X is not set + # CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set + # CONFIG_UIO is not set + # CONFIG_STAGING is not set + +@@ -1266,6 +1476,7 @@ CONFIG_EXT2_FS=y + # CONFIG_EXT2_FS_XATTR is not set + # CONFIG_EXT2_FS_XIP is not set + CONFIG_EXT3_FS=y ++CONFIG_EXT3_DEFAULTS_TO_ORDERED=y + CONFIG_EXT3_FS_XATTR=y + # CONFIG_EXT3_FS_POSIX_ACL is not set + # CONFIG_EXT3_FS_SECURITY is not set +@@ -1274,20 +1485,27 @@ CONFIG_JBD=y + CONFIG_FS_MBCACHE=y + # CONFIG_REISERFS_FS is not set + # CONFIG_JFS_FS is not set +-# CONFIG_FS_POSIX_ACL is not set +-CONFIG_FILE_LOCKING=y + # CONFIG_XFS_FS is not set + # CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set + # CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y + CONFIG_DNOTIFY=y +-# CONFIG_INOTIFY is not set ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set + # CONFIG_QUOTA is not set +-# CONFIG_AUTOFS_FS is not set ++# CONFIG_QUOTACTL is not set + # CONFIG_AUTOFS4_FS is not set + # CONFIG_FUSE_FS is not set + + # ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# + # CD-ROM/DVD Filesystems + # + # CONFIG_ISO9660_FS is not set +@@ -1325,6 +1543,7 @@ CONFIG_MISC_FILESYSTEMS=y + # CONFIG_BEFS_FS is not set + # CONFIG_BFS_FS is not set + # CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set + CONFIG_JFFS2_FS=y + CONFIG_JFFS2_FS_DEBUG=0 + CONFIG_JFFS2_FS_WRITEBUFFER=y +@@ -1336,6 +1555,7 @@ CONFIG_JFFS2_ZLIB=y + # CONFIG_JFFS2_LZO is not set + CONFIG_JFFS2_RTIME=y + # CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set + # CONFIG_CRAMFS is not set + # CONFIG_SQUASHFS is not set + # CONFIG_VXFS_FS is not set +@@ -1344,6 +1564,10 @@ CONFIG_MINIX_FS=y + # CONFIG_HPFS_FS is not set + # CONFIG_QNX4FS_FS is not set + CONFIG_ROMFS_FS=y ++CONFIG_ROMFS_BACKED_BY_BLOCK=y ++# CONFIG_ROMFS_BACKED_BY_MTD is not set ++# CONFIG_ROMFS_BACKED_BY_BOTH is not set ++CONFIG_ROMFS_ON_BLOCK=y + # CONFIG_SYSV_FS is not set + # CONFIG_UFS_FS is not set + CONFIG_NETWORK_FILESYSTEMS=y +@@ -1355,10 +1579,8 @@ CONFIG_ROOT_NFS=y + CONFIG_LOCKD=y + CONFIG_NFS_COMMON=y + CONFIG_SUNRPC=y +-# CONFIG_SUNRPC_REGISTER_V4 is not set + # CONFIG_RPCSEC_GSS_KRB5 is not set +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-# CONFIG_SMB_FS is not set ++# CONFIG_CEPH_FS is not set + # CONFIG_CIFS is not set + # CONFIG_NCP_FS is not set + # CONFIG_CODA_FS is not set +@@ -1425,7 +1647,6 @@ CONFIG_NLS_ISO8859_1=y + # CONFIG_NLS_KOI8_R is not set + # CONFIG_NLS_KOI8_U is not set + CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set + + # + # Kernel hacking +@@ -1435,19 +1656,18 @@ CONFIG_ENABLE_WARN_DEPRECATED=y + # CONFIG_ENABLE_MUST_CHECK is not set + CONFIG_FRAME_WARN=1024 + # CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set + # CONFIG_UNUSED_SYMBOLS is not set + # CONFIG_DEBUG_FS is not set + # CONFIG_HEADERS_CHECK is not set + # CONFIG_DEBUG_KERNEL is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++CONFIG_BKL=y ++# CONFIG_SPARSE_RCU_POINTER is not set + CONFIG_DEBUG_BUGVERBOSE=y + CONFIG_DEBUG_MEMORY_INIT=y +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set + # CONFIG_SYSCTL_SYSCALL_CHECK is not set +- +-# +-# Tracers +-# +-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set + # CONFIG_SAMPLES is not set + # CONFIG_BOOTPARAM is not set + +@@ -1455,15 +1675,16 @@ CONFIG_DEBUG_MEMORY_INIT=y + # Security options + # + # CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set + # CONFIG_SECURITY is not set + # CONFIG_SECURITYFS is not set +-# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" + CONFIG_CRYPTO=y + + # + # Crypto core or helper + # +-# CONFIG_CRYPTO_FIPS is not set + CONFIG_CRYPTO_ALGAPI=y + CONFIG_CRYPTO_ALGAPI2=y + CONFIG_CRYPTO_AEAD=y +@@ -1473,10 +1694,13 @@ CONFIG_CRYPTO_BLKCIPHER2=y + CONFIG_CRYPTO_HASH=y + CONFIG_CRYPTO_HASH2=y + CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y + CONFIG_CRYPTO_MANAGER=y + CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set + # CONFIG_CRYPTO_GF128MUL is not set + # CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y + # CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=y + CONFIG_CRYPTO_TEST=m +@@ -1504,11 +1728,13 @@ CONFIG_CRYPTO_CBC=y + # + CONFIG_CRYPTO_HMAC=y + # CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set + + # + # Digest + # + CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set + # CONFIG_CRYPTO_MD4 is not set + CONFIG_CRYPTO_MD5=y + # CONFIG_CRYPTO_MICHAEL_MIC is not set +@@ -1525,9 +1751,9 @@ CONFIG_CRYPTO_SHA1=y + # + # Ciphers + # +-# CONFIG_CRYPTO_AES is not set ++CONFIG_CRYPTO_AES=y + # CONFIG_CRYPTO_ANUBIS is not set +-# CONFIG_CRYPTO_ARC4 is not set ++CONFIG_CRYPTO_ARC4=y + # CONFIG_CRYPTO_BLOWFISH is not set + # CONFIG_CRYPTO_CAMELLIA is not set + # CONFIG_CRYPTO_CAST5 is not set +@@ -1545,22 +1771,19 @@ CONFIG_CRYPTO_DES=y + # Compression + # + # CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set + # CONFIG_CRYPTO_LZO is not set + + # + # Random Number Generation + # + # CONFIG_CRYPTO_ANSI_CPRNG is not set +- +-# +-# OCF Configuration +-# +-# CONFIG_OCF_OCF is not set +- +-# +-# Talitos Driver +-# +-# CONFIG_CRYPTO_HW is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_HIFN_795X is not set ++CONFIG_CRYPTO_DEV_CF_TALITOS=y ++# CONFIG_BINARY_PRINTF is not set + + # + # Library routines +@@ -1576,7 +1799,10 @@ CONFIG_CRC32=y + CONFIG_LIBCRC32C=y + CONFIG_ZLIB_INFLATE=y + CONFIG_ZLIB_DEFLATE=y +-CONFIG_PLIST=y ++# CONFIG_XZ_DEC is not set ++# CONFIG_XZ_DEC_BCJ is not set + CONFIG_HAS_IOMEM=y + CONFIG_HAS_IOPORT=y + CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y diff --git a/target/linux/coldfire/patches/100-kernel-2.6.38-Fix-FEC-driver-bugs-for-MCF547x-MCF548x.patch b/target/linux/coldfire/patches/100-kernel-2.6.38-Fix-FEC-driver-bugs-for-MCF547x-MCF548x.patch new file mode 100644 index 000000000..e7696e29d --- /dev/null +++ b/target/linux/coldfire/patches/100-kernel-2.6.38-Fix-FEC-driver-bugs-for-MCF547x-MCF548x.patch @@ -0,0 +1,180 @@ +From 92b8d976e58fe5e6eb97aedcaa46e80c924fbc04 Mon Sep 17 00:00:00 2001 +From: Wang Huan <wanghuan@zch06.freescale.net> +Date: Mon, 5 Sep 2011 08:59:46 +0800 +Subject: [PATCH] Fix FEC driver bugs for MCF547x/MCF548x + +This patch fixed kernel panic during flood ping with huge packets. +It also fixed the data integrity errors when running iozone on an +NFSv3-mounted file system. + +Signed-off-by: Jason Jin <jason.jin@freescale.com> +--- + arch/m68k/include/asm/cf_548x_cacheflush.h | 45 ++++++++++++++++++++++++--- + drivers/net/fec_m547x.c | 18 +++++----- + 2 files changed, 49 insertions(+), 14 deletions(-) + +--- a/arch/m68k/include/asm/cf_548x_cacheflush.h ++++ b/arch/m68k/include/asm/cf_548x_cacheflush.h +@@ -27,8 +27,8 @@ + unsigned long end_set; \ + \ + start_set = 0; \ +- end_set = (unsigned long)LAST_DCACHE_ADDR; \ +- \ ++ end_set = (unsigned long)LAST_ICACHE_ADDR; \ ++ asm("nop"); \ + for (set = start_set; set <= end_set; set += (0x10 - 3)) {\ + asm volatile("cpushl %%ic,(%0)\n" \ + "\taddq%.l #1,%0\n" \ +@@ -48,7 +48,7 @@ + \ + start_set = 0; \ + end_set = (unsigned long)LAST_DCACHE_ADDR; \ +- \ ++ asm("nop"); \ + for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ + asm volatile("cpushl %%dc,(%0)\n" \ + "\taddq%.l #1,%0\n" \ +@@ -68,7 +68,7 @@ + \ + start_set = 0; \ + end_set = (unsigned long)LAST_DCACHE_ADDR; \ +- \ ++ asm("nop"); \ + for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ + asm volatile("cpushl %%bc,(%0)\n" \ + "\taddq%.l #1,%0\n" \ +@@ -240,12 +240,47 @@ extern inline void flush_icache_range(un + } + } + ++static inline void flush_dcache_range(unsigned long address, ++ unsigned long endaddr) ++{ ++ unsigned long set; ++ unsigned long start_set; ++ unsigned long end_set; ++ ++ start_set = address & _DCACHE_SET_MASK; ++ end_set = endaddr & _DCACHE_SET_MASK; ++ ++ if (start_set > end_set) { ++ /* from the begining to the lowest address */ ++ for (set = 0; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%dc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%dc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%dc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); ++ } ++ /* next loop will finish the cache ie pass the hole */ ++ end_set = LAST_ICACHE_ADDR; ++ } ++ for (set = start_set; set <= end_set; set += (0x10 - 3)) { ++ asm volatile("cpushl %%dc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%dc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%dc,(%0)\n" ++ "\taddq%.l #1,%0\n" ++ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); ++ } ++} ++ + static inline void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) + { + memcpy(dst, src, len); +- flush_icache_user_page(vma, page, vaddr, len); ++ flush_dcache(); + } + static inline void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, +--- a/drivers/net/fec_m547x.c ++++ b/drivers/net/fec_m547x.c +@@ -34,7 +34,7 @@ + #include <asm/m5485sram.h> + #include <asm/virtconvert.h> + #include <asm/irq.h> +- ++#include <asm/cf_cacheflush.h> + #include "fec_m547x.h" + + #ifdef CONFIG_FEC_548x_ENABLE_FEC2 +@@ -97,7 +97,7 @@ static void fec_interrupt_fec_rx_handler + static irqreturn_t fec_interrupt_handler(int irq, void *dev_id); + static void fec_interrupt_fec_tx_handler_fec0(void); + static void fec_interrupt_fec_rx_handler_fec0(void); +-static void fec_interrupt_fec_reinit(unsigned long data); ++static void fec_interrupt_fec_reinit(struct net_device *dev); + + /* default fec0 address */ + unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 }; +@@ -145,6 +145,7 @@ static int coldfire_fec_mdio_read(struct + #ifdef CONFIG_FEC_548x_SHARED_PHY + unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0; + #else ++ struct net_device *dev = bus->priv; + unsigned long base_addr = (unsigned long) dev->base_addr; + #endif + int tries = 100; +@@ -179,6 +180,7 @@ static int coldfire_fec_mdio_write(struc + #ifdef CONFIG_FEC_548x_SHARED_PHY + unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0; + #else ++ struct net_device *dev = bus->priv; + unsigned long base_addr = (unsigned long) dev->base_addr; + #endif + int tries = 100; +@@ -394,9 +396,6 @@ static int mcf547x_fec_open(struct net_d + + dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler); + +- /* init tasklet for controller reinitialization */ +- tasklet_init(&fp->fecpriv_tasklet_reinit, +- fec_interrupt_fec_reinit, (unsigned long) dev); + + /* Reset FIFOs */ + FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL; +@@ -790,6 +789,8 @@ static int mcf547x_fec_start_xmit(struct + + /* flush data cache before initializing + * the descriptor and starting DMA */ ++ flush_dcache_range(virt_to_phys(data_aligned), ++ virt_to_phys(data_aligned) + skb->len); + + spin_lock_irq(&fp->fecpriv_lock); + +@@ -1308,7 +1309,7 @@ irqreturn_t fec_interrupt_handler(int ir + netif_stop_queue(dev); + + /* execute reinitialization as tasklet */ +- tasklet_schedule(&fp->fecpriv_tasklet_reinit); ++ fec_interrupt_fec_reinit(dev); + + fp->fecpriv_stat.rx_dropped++; + } +@@ -1343,10 +1344,9 @@ irqreturn_t fec_interrupt_handler(int ir + * when controller must be reinitialized. + * + *************************************************************************/ +-void fec_interrupt_fec_reinit(unsigned long data) ++void fec_interrupt_fec_reinit(struct net_device *dev) + { + int i; +- struct net_device *dev = (struct net_device *)data; + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + +@@ -1385,7 +1385,7 @@ void fec_interrupt_fec_reinit(unsigned l + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; + + /* flush entire data cache before restarting the DMA */ +- ++ flush_dcache(); + /* restart DMA from beginning */ + MCD_startDma(fp->fecpriv_fec_rx_channel, + (char *) fp->fecpriv_rxdesc, 0, diff --git a/target/linux/coldfire/patches/101-kernel-2.6.38-Fix-LCD-framebuffer-driver-data-swap-bug-for-MCF5441.patch b/target/linux/coldfire/patches/101-kernel-2.6.38-Fix-LCD-framebuffer-driver-data-swap-bug-for-MCF5441.patch new file mode 100644 index 000000000..b948d1f83 --- /dev/null +++ b/target/linux/coldfire/patches/101-kernel-2.6.38-Fix-LCD-framebuffer-driver-data-swap-bug-for-MCF5441.patch @@ -0,0 +1,49 @@ +From 633531cdbaa3ed70a364db78fd7f8ae11da3e394 Mon Sep 17 00:00:00 2001 +From: Wang Huan <wanghuan@zch06.freescale.net> +Date: Wed, 14 Sep 2011 17:40:41 +0800 +Subject: [PATCH] Fix LCD framebuffer driver data swap bug for MCF54418 + +This patch fixed LCD framebuffer driver data swap bug +for MCF54418. + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + drivers/video/fsl-ssd1289-fb.c | 13 ++++++++++--- + 1 files changed, 10 insertions(+), 3 deletions(-) + +--- a/drivers/video/fsl-ssd1289-fb.c ++++ b/drivers/video/fsl-ssd1289-fb.c +@@ -54,8 +54,10 @@ static int ssd1289_spi_writeblock(struct + for (i = 0; i < SPI_LCD_BLOCK_SIZE; i++) { + if (i % 2 == 0) + spi_block_buffer[i] = 0x01; +- else if (flag == 1) +- spi_block_buffer[i] = *(daddr + (i >> 1)); ++ else if ((flag == 1) && (i % 4 == 1)) ++ spi_block_buffer[i] = *(daddr + (i >> 1) + 1); ++ else if ((flag == 1) && (i % 4 == 3)) ++ spi_block_buffer[i] = *(daddr + (i >> 1) - 1); + else if (flag == 0) + spi_block_buffer[i] = 0; + } +@@ -331,6 +333,9 @@ static int ssd1289fbd(void *arg) + int i; + unsigned short *buf_p; + struct fsl_ssd1289_fb_info *fbinfo = info->par; ++#if defined(CONFIG_SSD1289_FLEXBUS_MODE) ++ unsigned short tmp; ++#endif + #if defined(CONFIG_SSD1289_SPI_MODE) + unsigned char *bufspi_p; + int count; +@@ -344,7 +349,9 @@ static int ssd1289fbd(void *arg) + + #if defined(CONFIG_SSD1289_FLEXBUS_MODE) + for (i = 0; i < info->screen_size; i += 2) { +- ssd1289_write(info, *buf_p, 1); ++ tmp = ((((*buf_p) & 0x00ff) << 8) | ++ (((*buf_p) & 0xff00) >> 8)); ++ ssd1289_write(info, tmp, 1); + buf_p++; + } + #elif defined(CONFIG_SSD1289_SPI_MODE) diff --git a/target/linux/coldfire/patches/102-kernel-2.6.38-Fix-SD-MMC-SDIO-over-SPI-driver-bug-when-reinserting.patch b/target/linux/coldfire/patches/102-kernel-2.6.38-Fix-SD-MMC-SDIO-over-SPI-driver-bug-when-reinserting.patch new file mode 100644 index 000000000..4ec2d21bc --- /dev/null +++ b/target/linux/coldfire/patches/102-kernel-2.6.38-Fix-SD-MMC-SDIO-over-SPI-driver-bug-when-reinserting.patch @@ -0,0 +1,34 @@ +From 78f4df7dfe913c68b8329dd84a24325b8f34217b Mon Sep 17 00:00:00 2001 +From: Wang Huan <wanghuan@zch06.freescale.net> +Date: Mon, 8 Aug 2011 09:14:45 +0800 +Subject: [PATCH] Fix SD/MMC/SDIO over SPI driver bug when reinserting as module + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5445x/devices.c | 8 ++++++++ + 1 files changed, 8 insertions(+), 0 deletions(-) + +--- a/arch/m68k/coldfire/m5445x/devices.c ++++ b/arch/m68k/coldfire/m5445x/devices.c +@@ -136,6 +136,13 @@ int mmc_spi_init(struct device *mmc_spi_ + return 0; + } + ++void mmc_spi_exit(struct device *mmc_spi_device, void *irq_privatedata) ++{ ++#if defined(CONFIG_M54451_SD_HW_DETECT) ++ free_irq(64 + 7, irq_privatedata); ++#endif ++} ++ + static struct coldfire_dspi_chip dspi_sd_chip_info = { + .mode = SPI_MODE_0, + .bits_per_word = 8, +@@ -154,6 +161,7 @@ static struct coldfire_dspi_chip dspi_sd + static struct mmc_spi_platform_data mcf54451_mmc_pdata = { + .ocr_mask = MMC_VDD_33_34, + .init = mmc_spi_init, ++ .exit = mmc_spi_exit, + }; + #endif + diff --git a/target/linux/coldfire/patches/103-kernel-2.6.38-Fix-i2c-driver-could-not-work-as-module.patch b/target/linux/coldfire/patches/103-kernel-2.6.38-Fix-i2c-driver-could-not-work-as-module.patch new file mode 100644 index 000000000..8a10ad880 --- /dev/null +++ b/target/linux/coldfire/patches/103-kernel-2.6.38-Fix-i2c-driver-could-not-work-as-module.patch @@ -0,0 +1,30 @@ +From 358154a6d0dd87305c6af92810220f8a17641c07 Mon Sep 17 00:00:00 2001 +From: Wang Huan <wanghuan@zch06.freescale.net> +Date: Mon, 8 Aug 2011 10:49:53 +0800 +Subject: [PATCH] Fix i2c driver could not work as module + +Signed-off-by: Alison Wang <b18965@freescale.com> +--- + arch/m68k/coldfire/m5445x/devices.c | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/m68k/coldfire/m5445x/devices.c ++++ b/arch/m68k/coldfire/m5445x/devices.c +@@ -426,7 +426,7 @@ static inline void mcf5445x_init_pata(vo + /* + * I2C + */ +-#if defined(CONFIG_I2C) ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + static struct resource coldfire_i2c_resources[] = { + { /* I/O */ + .start = 0xFC058000, +@@ -464,7 +464,7 @@ static int __init mcf5445x_init_devices( + mcf5445x_init_pata(); + #endif + +-#if defined(CONFIG_I2C) ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + mcf5445x_init_i2c(); + #endif + return 0; diff --git a/target/linux/coldfire/patches/200-fec_select_phylib.patch b/target/linux/coldfire/patches/200-fec_select_phylib.patch new file mode 100644 index 000000000..4207d98f6 --- /dev/null +++ b/target/linux/coldfire/patches/200-fec_select_phylib.patch @@ -0,0 +1,10 @@ +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -1975,6 +1975,7 @@ + config FEC_548x + tristate "MCF547x/MCF548x Fast Ethernet Controller support" + depends on M547X_8X ++ select PHYLIB + help + The MCF547x and MCF548x have a built-in Fast Ethernet Controller. + Saying Y here will include support for this device in the kernel. |