branch Attitude Adjustment

git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@33625 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 62 insertions, 0 deletions

diff --git a/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch
new file mode 100644
index 000000000..bd9386d8c
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch
@@ -0,0 +1,62 @@
+From 902b348cdddd4c858993e02aced615aa6caf04d0 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 14 Mar 2012 10:45:30 +0100
+Subject: [PATCH 35/47] MIPS: ath79: add PCI registration code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+Cc: linux-mips@linux-mips.org
+Cc: mcgrof@infradead.org
+Patchwork: https://patchwork.linux-mips.org/patch/3516/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig |    2 ++
+ arch/mips/ath79/pci.c   |   13 ++++++++++++-
+ 2 files changed, 14 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -72,6 +72,8 @@ config SOC_AR933X
+ 
+ config SOC_AR934X
+ 	select USB_ARCH_HAS_EHCI
++	select HW_HAS_PCI
++	select PCI_AR724X if PCI
+ 	def_bool n
+ 
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,7 @@
+ 
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+ #include <asm/mach-ath79/pci.h>
+@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct
+ 		if (soc_is_ar71xx()) {
+ 			ath79_pci_irq_map = ar71xx_pci_irq_map;
+ 			ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
+-		} else if (soc_is_ar724x()) {
++		} else if (soc_is_ar724x() ||
++			   soc_is_ar9342() ||
++			   soc_is_ar9344()) {
+ 			ath79_pci_irq_map = ar724x_pci_irq_map;
+ 			ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+ 		} else {
+@@ -115,5 +118,13 @@ int __init ath79_register_pci(void)
+ 	if (soc_is_ar724x())
+ 		return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
+ 
++	if (soc_is_ar9342() || soc_is_ar9344()) {
++		u32 bootstrap;
++
++		bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
++		if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
++			return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
++	}
++
+ 	return -ENODEV;
+ }