branch Attitude Adjustment

git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@33625 3c298f89-4303-0410-b956-a3cf2f4a3e73

14 files changed, 745 insertions, 0 deletions

diff --git a/package/uboot-lantiq/files/include/configs/arcadyan-common.h b/package/uboot-lantiq/files/include/configs/arcadyan-common.h
new file mode 100644
index 000000000..75f5c3863
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arcadyan-common.h
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the Danube reference board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1	/* MIPS32 CPU compatible		*/
+#define CONFIG_MIPS24KEC	1	/* MIPS 24KEc CPU core			*/
+#define CONFIG_DANUBE		1	/* in a Danube/Twinpass Chip		*/
+
+#define CONFIG_SYS_MIPS_MULTI_CPU	1	/* This is a multi cpu system */
+
+#define CONFIG_USE_DDR_RAM
+
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
+
+#ifdef CONFIG_SYS_RAMBOOT
+	//#warning CONFIG_SYS_RAMBOOT
+	#define CONFIG_SKIP_LOWLEVEL_INIT
+#else /* CONFIG_SYS_RAMBOOT */
+	#define CONFIG_SYS_EBU_BOOT
+	#define INFINEON_EBU_BOOTCFG	0x688C688C	/* CMULT = 8 for 150 MHz */
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#if 1
+#ifndef	CPU_CLOCK_RATE
+#define CPU_CLOCK_RATE	(ifx_get_cpuclk())
+#endif
+#endif
+
+#undef CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser		*/
+
+/*
+ * Include common defines/options for all Infineon boards
+ */
+#include "ifx-common.h"
+
+
+#undef CONFIG_EXTRA_ENV_SETTINGS                                       
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+        "ram_addr=0x80500000\0"                                         \
+        "kernel_addr=0xb0020000\0"                                      \
+        "flashargs=setenv bootargs rootfstype=squashfs,jffs2\0"         \
+        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+                "nfsroot=${serverip}:${rootpath} \0"                    \
+        "addip=setenv bootargs ${bootargs} "                            \
+                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+                ":${hostname}:${netdev}:off\0"                          \
+        "addmisc=setenv bootargs ${bootargs} init=/etc/preinit "        \
+                "console=ttyS1,115200 ethaddr=${ethaddr} "              \
+                "${mtdparts}\0"                                         \
+        "flash_flash=run flashargs addip addmisc;"                      \
+                "bootm ${kernel_addr}\0"                                \
+        "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0"    \
+        "net_flash=run load_kernel flashargs addip addmisc;"            \
+                "bootm ${ram_addr}\0"                                   \
+        "net_nfs=run load_kernel nfsargs addip addmisc;"                \
+                "bootm ${ram_addr}\0"                                   \
+        "load_kernel=tftp ${ram_addr} "                                 \
+                "${tftppath}openwrt-ifxmips-uImage\0"                   \
+        "update_uboot=tftp 0x80500000 ${tftppath}u-boot-" CONFIG_ARCADYAN ".bin;era 0xb0000000 +${filesize};" \
+                "cp.b 0x80500000 0xb0000000 ${filesize}\0" \
+        "update_openwrt=tftp ${ram_addr} "                              \
+                "${tftppath}" CONFIG_ARCADYAN "-squashfs.image;"            \
+                "era ${kernel_addr} +${filesize};"                      \
+                "cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
+
+/*
+ * Cache Configuration (cpu/chip specific, Danube)
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE	CONF_CM_CACHABLE_NO_WA
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_IFX_ETOP
+//#define CLK_OUT2_25MHZ
+
+#define CONFIG_MII
+#undef CONFIG_CMD_MII
+
+#define CONFIG_IFX_ASC
+
+#ifdef CONFIG_USE_ASC0
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100400
+#else
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100C00
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+/* Configuration of EBU: */
+/* starting address from 0xb0000000 */
+/* make the flash available from RAM boot */
+#	define CONFIG_EBU_ADDSEL0		0x10000031
+#	define CONFIG_EBU_BUSCON0		0x0001D7FF
+#	define CONFIG_EBU_ADDSEL1		0x14000001
+#	define CONFIG_EBU_BUSCON1		0x4041D7FD
+#endif
+
+#define CONFIG_CMD_HTTPD		/* enable upgrade via HTTPD */
+
+#define CONFIG_IPADDR		192.168.1.1
+#define CONFIG_SERVERIP		192.168.1.101
+#define CONFIG_GATEWAYIP	192.168.1.254
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ROOTPATH		"/export"
+
+#ifdef CONFIG_BOOTSTRAP
+#define CONFIG_BOOTSTRAP_BASE			CONFIG_BOOTSTRAP_TEXT_BASE
+#define CONFIG_BOOTSTRAP_BAUDRATE		CONFIG_BAUDRATE
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOOTSTRAP_LZMA
+//#define CONFIG_BOOTSTRAP_SERIAL
+#endif
+
+
+
+#endif	/* __CONFIG_H */
diff --git a/package/uboot-lantiq/files/include/configs/arv3527P.h b/package/uboot-lantiq/files/include/configs/arv3527P.h
new file mode 100644
index 000000000..f282fc816
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv3527P.h
@@ -0,0 +1,17 @@
+#ifndef __CONFIG_H_3527
+#define __CONFIG_H_3527
+
+#define CONFIG_ARV3527		1
+#define CONFIG_ARCADYAN		"ARV3527P"
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+#define CONFIG_USE_DDR_PSC_32   1
+#define	CONFIG_SYS_PROMPT	"ARV3527 => "
+
+/*#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN	13
+#define CONFIG_BUTTON_LEVEL	0
+*/
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv4518PW.h b/package/uboot-lantiq/files/include/configs/arv4518PW.h
new file mode 100644
index 000000000..30bbf6e46
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv4518PW.h
@@ -0,0 +1,16 @@
+#ifndef __CONFIG_H_4518
+#define __CONFIG_H_4518
+
+#define CONFIG_ARV4518		1
+#define CONFIG_ARCADYAN		"ARV4518PW"
+
+#define CONFIG_SYS_MAX_RAM	64*1024*1024
+#define CONFIG_USE_DDR_PSC_64	1
+#define	CONFIG_SYS_PROMPT	"ARV4518 => "
+
+//#define CONFIG_RMII		1
+#define CONFIG_RTL8306_SWITCH	1
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv4519PW.h b/package/uboot-lantiq/files/include/configs/arv4519PW.h
new file mode 100644
index 000000000..1fbc361dc
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv4519PW.h
@@ -0,0 +1,21 @@
+#ifndef __CONFIG_H_4519
+#define __CONFIG_H_4519
+
+#define CONFIG_ARV4519		1
+#define CONFIG_ARCADYAN		"ARV4519PW"
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+#define CONFIG_USE_DDR_PSC_32	1
+#define	CONFIG_SYS_PROMPT	"ARV4519 => "
+
+#define CONFIG_AR8216_SWITCH	1
+#define CONFIG_EBU_GPIO		0
+#define CONFIG_SWITCH_PORT0
+#define CONFIG_SWITCH_PIN	13
+#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN	12
+#define CONFIG_BUTTON_LEVEL	0
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv4520PW.h b/package/uboot-lantiq/files/include/configs/arv4520PW.h
new file mode 100644
index 000000000..d4b130b9d
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv4520PW.h
@@ -0,0 +1,20 @@
+#ifndef __CONFIG_H_4520
+#define __CONFIG_H_4520
+
+#define CONFIG_ARV4520		1
+#define CONFIG_ARCADYAN		"ARV4520PW"
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+#define CONFIG_USE_DDR_PSC_32   1
+#define	CONFIG_SYS_PROMPT	"ARV4520 => "
+#define CONFIG_RMII		1
+#define CONFIG_ADM6996_SWITCH	1
+#define CONFIG_EBU_GPIO		0x400
+
+#define CONFIG_BUTTON_PORT0
+#define CONFIG_BUTTON_PIN	11
+#define CONFIG_BUTTON_LEVEL	0
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv4525PW.h b/package/uboot-lantiq/files/include/configs/arv4525PW.h
new file mode 100644
index 000000000..63e7d32b4
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv4525PW.h
@@ -0,0 +1,18 @@
+#ifndef __CONFIG_H_4525
+#define __CONFIG_H_4525
+
+#define CONFIG_ARV4525		1
+#define CONFIG_ARCADYAN		"ARV4525PW"
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+#define CONFIG_USE_DDR_PSC_32   1
+#define	CONFIG_SYS_PROMPT	"ARV4525 => "
+
+#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN	13
+#define CONFIG_BUTTON_LEVEL	0
+
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv452CPW.h b/package/uboot-lantiq/files/include/configs/arv452CPW.h
new file mode 100644
index 000000000..579105f97
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv452CPW.h
@@ -0,0 +1,20 @@
+#ifndef __CONFIG_H_452C
+#define __CONFIG_H_452C
+
+#define CONFIG_ARV452C		1
+#define CONFIG_ARCADYAN		"ARV452CPW"
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+#define CONFIG_USE_DDR_PSC_32   1
+#define	CONFIG_SYS_PROMPT	"ARV452c => "
+#define CONFIG_RMII		1
+#define CONFIG_RTL8306_SWITCH	1
+#define CONFIG_EBU_GPIO		0xf00
+
+#define CONFIG_BUTTON_PORT0
+#define CONFIG_BUTTON_PIN	11
+#define CONFIG_BUTTON_LEVEL	0
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv7518PW.h b/package/uboot-lantiq/files/include/configs/arv7518PW.h
new file mode 100644
index 000000000..5d65dbbf9
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv7518PW.h
@@ -0,0 +1,16 @@
+#ifndef __CONFIG_H_7518
+#define __CONFIG_H_7518
+
+#define CONFIG_ARV7518		1
+#define CONFIG_ARCADYAN		"ARV7518PW"
+
+#define CONFIG_SYS_MAX_RAM	64*1024*1024
+#define CONFIG_USE_DDR_PSC_64	1
+#define	CONFIG_SYS_PROMPT	"ARV7518 => "
+
+//#define CONFIG_RMII		1
+#define CONFIG_AR8216_SWITCH	1
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv7525PW.h b/package/uboot-lantiq/files/include/configs/arv7525PW.h
new file mode 100644
index 000000000..ffa59947b
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv7525PW.h
@@ -0,0 +1,18 @@
+#ifndef __CONFIG_H_7525PW
+#define __CONFIG_H_7525PW
+
+#define CONFIG_ARV7525		1
+#define CONFIG_ARCADYAN		"ARV7525PW"
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+#define CONFIG_USE_DDR_PSC_32   1
+#define	CONFIG_SYS_PROMPT	"ARV7525 => "
+
+#define CONFIG_BUTTON_PORT1
+#define CONFIG_BUTTON_PIN	13
+#define CONFIG_BUTTON_LEVEL	0
+
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv752DPW.h b/package/uboot-lantiq/files/include/configs/arv752DPW.h
new file mode 100644
index 000000000..594ce61e6
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv752DPW.h
@@ -0,0 +1,19 @@
+#ifndef __CONFIG_H_752DPW
+#define __CONFIG_H_752DPW
+
+#define CONFIG_ARV752DPW	1
+#define CONFIG_ARCADYAN		"ARV752DPW"
+
+#define CONFIG_SYS_MAX_RAM	64*1024*1024
+#define CONFIG_USE_DDR_PSC_64	1
+#define	CONFIG_SYS_PROMPT	"ARV752DPW => "
+
+#define CONFIG_RMII
+#define CONFIG_RTL8306G_SWITCH	1
+//#define CONFIG_EBU_GPIO		0x2
+//#define CONFIG_BUTTON_PORT0
+//#define CONFIG_BUTTON_PIN	12
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/arv752DPW22.h b/package/uboot-lantiq/files/include/configs/arv752DPW22.h
new file mode 100644
index 000000000..294628dbe
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/arv752DPW22.h
@@ -0,0 +1,21 @@
+#ifndef __CONFIG_H_752DPW22
+#define __CONFIG_H_752DPW22
+
+#define CONFIG_ARV752DPW22	1
+#define CONFIG_ARCADYAN		"ARV752DPW22"
+
+#define CONFIG_SYS_MAX_RAM	64*1024*1024
+#define CONFIG_USE_DDR_PSC_64	1
+#define	CONFIG_SYS_PROMPT	"ARV752DPW22 => "
+
+#define CONFIG_AR8216_SWITCH	1
+#define CONFIG_EBU_GPIO		0x2
+#define CONFIG_SWITCH_PORT1
+#define CONFIG_SWITCH_PIN	3
+#define CONFIG_BUTTON_PORT0
+#define CONFIG_BUTTON_PIN	13
+#define CONFIG_BUTTON_LEVEL	0
+
+#include "arcadyan-common.h"
+
+#endif
diff --git a/package/uboot-lantiq/files/include/configs/easy50712.h b/package/uboot-lantiq/files/include/configs/easy50712.h
new file mode 100644
index 000000000..8eeb6c06a
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/easy50712.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the Danube reference board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* #define DEBUG */
+
+#define CONFIG_MIPS32		1	/* MIPS32 CPU compatible		*/
+#define CONFIG_MIPS24KEC	1	/* MIPS 24KEc CPU core			*/
+#define CONFIG_DANUBE		1	/* in a Danube/Twinpass Chip		*/
+#define CONFIG_EASY50712	1	/* on the Danube Reference Board	*/
+
+#define CONFIG_SYS_MIPS_MULTI_CPU	1	/* This is a multi cpu system */
+
+#define CONFIG_SYS_MAX_RAM	32*1024*1024
+
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
+#ifdef CONFIG_SYS_RAMBOOT
+	//#warning CONFIG_SYS_RAMBOOT
+	#define CONFIG_SKIP_LOWLEVEL_INIT
+#else /* CONFIG_SYS_RAMBOOT */
+
+	#define CONFIG_SYS_EBU_BOOT
+
+	#ifdef CONFIG_USE_DDR_RAM
+		/* FIXME: should not need these workarounds */
+		#define DANUBE_DDR_RAM_SIZE	32	/* 32M DDR-DRAM for reference board */
+	#endif
+
+	#define INFINEON_EBU_BOOTCFG	0x688C688C	/* CMULT = 8 for 150 MHz */
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#if 1
+#ifndef	CPU_CLOCK_RATE
+#define CPU_CLOCK_RATE	(ifx_get_cpuclk())
+#endif
+#endif
+
+#define	CONFIG_SYS_PROMPT	"DANUBE => "	/* Monitor Command Prompt */
+
+#undef CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser		*/
+
+/*
+ * Include common defines/options for all Infineon boards
+ */
+#include "ifx-common.h"
+
+/*
+ * Cache Configuration (cpu/chip specific, Danube)
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE	CONF_CM_CACHABLE_NO_WA
+
+#define CONFIG_NET_MULTI
+#if 0
+#define CONFIG_M4530_ETH
+#define CONFIG_M4530_FPGA
+#endif
+
+#define CONFIG_IFX_ETOP
+#define CLK_OUT2_25MHZ
+#define CONFIG_EXTRA_SWITCH
+
+#define CONFIG_RMII			/*  use interface in RMII mode */
+
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+
+#define CONFIG_IFX_ASC
+
+#ifdef CONFIG_USE_ASC0
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100400
+#else
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100C00
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+/* Configuration of EBU: */
+/* starting address from 0xb0000000 */
+/* make the flash available from RAM boot */
+#	define CONFIG_EBU_ADDSEL0		0x10000031
+#	define CONFIG_EBU_BUSCON0		0x0001D7FF
+#endif
+
+#define CONFIG_CMD_HTTPD		/* enable upgrade via HTTPD */
+
+#endif	/* __CONFIG_H */
diff --git a/package/uboot-lantiq/files/include/configs/easy50812.h b/package/uboot-lantiq/files/include/configs/easy50812.h
new file mode 100644
index 000000000..c7e96c1bc
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/easy50812.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the Danube reference board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* #define DEBUG */
+
+#define CONFIG_MIPS32		1		/* MIPS32 CPU compatible */
+#define CONFIG_MIPS34KC		1		/* MIPS 34Kc CPU core */	
+#define CONFIG_AR9		1		/* an AR9 device */
+#define CONFIG_EASY50812	1		/* on the AR9 reference board */
+#define CONFIG_SYS_MAX_RAM	32*1024*1024 	/* 32 MB */
+#define CONFIG_FLASH_CFI_DRIVER	1		/* using CFI flash driver */
+
+#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
+
+/* use PPL1 and fixed values for CPU / DDR and bus speed */
+#define CONFIG_USE_PLL1
+#define CONFIG_CPU_333M_RAM_166M
+#define CONFIG_CLASS_II_DDR_PAD
+
+#ifdef CONFIG_SYS_RAMBOOT
+	#define CONFIG_SKIP_LOWLEVEL_INIT	/* no cache */
+#else
+	#define CONFIG_SYS_EBU_BOOT
+	#define INFINEON_EBU_BOOTCFG	0x688C688C	/* CMULT = 8 for 150 MHz */
+#endif
+
+#ifndef	CPU_CLOCK_RATE
+#define CPU_CLOCK_RATE		(ifx_get_cpuclk())
+#endif
+
+#define	CONFIG_SYS_PROMPT	"AR9 => "	/* Monitor Command Prompt */
+#undef CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser		*/
+
+/*
+ * Include common defines/options for all Lantiq boards
+ */
+#include "ifx-common.h"
+
+/*
+ * Cache Configuration (cpu/chip specific, ar9)
+ */
+#define CONFIG_SYS_DCACHE_SIZE		(16384)
+#define CONFIG_SYS_ICACHE_SIZE		(16384)
+#define CONFIG_SYS_CACHELINE_SIZE	(32)
+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE	CONF_CM_CACHABLE_NO_WA
+
+#define CONFIG_NET_MULTI
+#if 0
+#define CONFIG_M4530_ETH
+#define CONFIG_M4530_FPGA
+#endif
+
+#define CONFIG_IFX_ETOP			/* lantiq ethernet cpe interface */
+#define CLK_OUT2_25MHZ
+#define CONFIG_EXTRA_SWITCH		/* search for external switches like tantos */
+#define CONFIG_RMII			/*  use interface in RMII mode */
+#define CONFIG_MII
+#define CONFIG_CMD_MII			/* enable MII command */	
+
+#define CONFIG_IFX_ASC			/* use lantiq ASC driver */
+#ifdef CONFIG_USE_ASC0
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100400
+#else
+#define CONFIG_SYS_IFX_ASC_BASE		0x1E100C00
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+/* Configuration of EBU: */
+/* starting address from 0xb0000000 */
+/* make the flash available from RAM boot */
+#	define CONFIG_EBU_ADDSEL0		0x10000031
+#	define CONFIG_EBU_BUSCON0		0x0001D7FF
+#endif
+
+#define CONFIG_CMD_HTTPD		/* enable upgrade via HTTPD */
+
+#endif	/* __CONFIG_H */
diff --git a/package/uboot-lantiq/files/include/configs/ifx-common.h b/package/uboot-lantiq/files/include/configs/ifx-common.h
new file mode 100644
index 000000000..4189031b9
--- /dev/null
+++ b/package/uboot-lantiq/files/include/configs/ifx-common.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Common configuration options for all AMCC boards
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IFX_COMMON_H
+#define __IFX_COMMON_H
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#undef CONFIG_PREBOOT
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ram_addr=0x80500000\0"						\
+	"kernel_addr=0xb0020000\0"					\
+	"mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \
+	"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath} \0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0"				\
+	"addmisc=setenv bootargs ${bootargs} init=/etc/preinit "	\
+		"console=ttyS1,115200 ethaddr=${ethaddr} "		\
+		"${mtdparts}\0"						\
+	"flash_flash=run flashargs addip addmisc;"			\
+		"bootm ${kernel_addr}\0"				\
+	"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0"	\
+	"net_flash=run load_kernel flashargs addip addmisc;"		\
+		"bootm ${ram_addr}\0"					\
+	"net_nfs=run load_kernel nfsargs addip addmisc;"		\
+		"bootm ${ram_addr}\0"					\
+	"load_kernel=tftp ${ram_addr} "					\
+		"${tftppath}openwrt-ifxmips-uImage\0"			\
+	"update_uboot=tftp 0x80500000 ${tftppath}u-boot.bin;era 0xb0000000 +${filesize};" \
+		"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
+	"update_openwrt=tftp ${ram_addr} "				\
+		"${tftppath}openwrt-ifxmips-squashfs.image;"		\
+		"era ${kernel_addr} +${filesize};"			\
+		"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
+
+#define CONFIG_BOOTCOMMAND	"run flash_flash"
+
+/*
+ * TFTP is using fragmented packets
+*/
+#define CONFIG_IP_DEFRAG
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_FLASH        /* flinfo, erase, protect       */
+#define CONFIG_CMD_MEMORY       /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot    */
+#define CONFIG_CMD_RUN          /* run command in env variable  */
+#define CONFIG_CMD_SAVEENV      /* saveenv                      */
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_PING
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_LZMA
+
+#undef CONFIG_SYS_LONGHELP				/* undef to save memory */
+#ifndef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE		512		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+
+#define CONFIG_SYS_MALLOC_LEN		1024*1024
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE/2)
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_LOAD_ADDR		0x80100000	/* default load address	*/
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#undef CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE		/* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+ 
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(140)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1			0xB0000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2			0xB0800000 /* Flash Bank #2 */
+
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_ENV_IS_IN_FLASH		1
+
+/* Address and size of Primary Environment Sector	*/
+#define CONFIG_ENV_ADDR			0xB0010000
+#define CONFIG_ENV_SIZE			0x10000
+
+#ifdef CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_SWAP_ADDR
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define FLASH_FIXUP_ADDR_8(addr)	((void*)((ulong)(addr)^2))
+#define FLASH_FIXUP_ADDR_16(addr)	((void*)((ulong)(addr)^2))
+
+#endif
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#ifdef CONFIG_SYS_EBU_BOOT
+#ifndef INFINEON_EBU_BOOTCFG
+#error Please define INFINEON_EBU_BOOTCFG
+#endif
+#endif
+
+#ifdef CONFIG_BOOTSTRAP
+#define CONFIG_BOOTSTRAP_BASE			CONFIG_BOOTSTRAP_TEXT_BASE
+#define CONFIG_BOOTSTRAP_BAUDRATE		CONFIG_BAUDRATE
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOOTSTRAP_LZMA
+//#define CONFIG_BOOTSTRAP_SERIAL
+#endif
+
+#endif /* __IFX_COMMON_H */