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| -rw-r--r-- | README.txt | 4 | ||||
| -rw-r--r-- | fpga-hacking.rst | 2 |
2 files changed, 3 insertions, 3 deletions
@@ -4,10 +4,10 @@ locally with ``make html`` (you'll need the ``python-sphinx`` package or equivalent on your platform). The output will pop out at ``_build/html/index.html``. -The live version (currently at http://novena-guide.readthedocs.org/) is hosted +The live version (currently at https://novena-guide.readthedocs.org/) is hosted by ReadTheDocs using github hooks for auto builds. For context, and pointers for how to make changes and contributions, see -http://docs.readthedocs.com. +https://docs.readthedocs.org. The sources are hosted at https://github.com/bnewbold/novena-guide. Contributions by patch or pull-request are welcome! Please indicate that you diff --git a/fpga-hacking.rst b/fpga-hacking.rst index 177b004..34294a6 100644 --- a/fpga-hacking.rst +++ b/fpga-hacking.rst @@ -11,7 +11,7 @@ The general purpose FPGA on the Novena mainboard is a Xilinx Spartan6 XC6SLX45 device in the CSG324 BGA package with a ``-3`` speedgrade. It is connected to the ARM CPU via SPI for bitstream configuration, via i2c for low-speed communications, and via a 16-bit memory interface ("EIM") for faster -communications. The FPGA also has it's own DRAM chip and an expansion header to +communications. The FPGA also has its own DRAM chip and an expansion header to which extra hardware can be attached. .. list-table:: Novena FPGA Specifications (from Xilinx) |