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author | bnewbold <bnewbold@robocracy.org> | 2015-03-31 23:11:23 -0700 |
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committer | bnewbold <bnewbold@robocracy.org> | 2015-03-31 23:11:23 -0700 |
commit | 400cbc3e9f01b6233b7a95048dbbe153f8630a96 (patch) | |
tree | d7bb6ae84f53e2c7fd07fa805f6554227273ea58 /fpga-hacking.rst | |
parent | 8acda77289aee8de5c0367fcb79f7599ac9ff5be (diff) | |
parent | ef1e28709a291e86e52877199441b00271a48e91 (diff) | |
download | novena-guide-400cbc3e9f01b6233b7a95048dbbe153f8630a96.tar.gz novena-guide-400cbc3e9f01b6233b7a95048dbbe153f8630a96.zip |
Merge pull request #4 from rillian/fixes
Minor fixups
Diffstat (limited to 'fpga-hacking.rst')
-rw-r--r-- | fpga-hacking.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga-hacking.rst b/fpga-hacking.rst index 177b004..34294a6 100644 --- a/fpga-hacking.rst +++ b/fpga-hacking.rst @@ -11,7 +11,7 @@ The general purpose FPGA on the Novena mainboard is a Xilinx Spartan6 XC6SLX45 device in the CSG324 BGA package with a ``-3`` speedgrade. It is connected to the ARM CPU via SPI for bitstream configuration, via i2c for low-speed communications, and via a 16-bit memory interface ("EIM") for faster -communications. The FPGA also has it's own DRAM chip and an expansion header to +communications. The FPGA also has its own DRAM chip and an expansion header to which extra hardware can be attached. .. list-table:: Novena FPGA Specifications (from Xilinx) |