xilinx.com
projects
coregen
1.0
clkgendcm_720p60hz
Generated by PlanAhead
clkgendcm_720p60hz
1
100.000
false
false
PSEN
BUFG
7
38.461
false
1
LOCKED
false
0.500
CLK_IN_SEL
CLKFX
0.000
false
empty
true
0.010
50.0
20
0.000
false
Single_ended_clock_capable_pin
false
74.285
CLKFX
INPUT_CLK_STOPPED
0.500
OPTIMIZED
10.000
false
false
0.000
CLKFX
1
false
FDBK_AUTO
0
26
BUFG
4
1
1
CLKFB_OUT_N
0
PSINCDEC
0.500
ZHOLD
DRDY
0.000
0.000
0.000
None
false
DIN
false
0.500
CLKFB_OUT_P
CLKFB_IN
0.000
0.010
1
DWE
0.000
false
false
BUFG
true
0.010
0.010
RESET
0.000
false
CLK_IN2
1
PSDONE
SINGLE
CLK0
0.500
DOUT
100.000
false
0.000
false
CLK0
0.010
50.0
2
0.500
CLK0
false
DADDR
POWER_DOWN
0.000
CLKFB_OUT
true
CLK_VALID
1
1X
OPTIMIZED
384.61
CLK0
BUFG
1
4.000
DONE
BUFG
false
CLK0
100.000
1
None
50.0
false
0.000
false
CLK0
false
CLK_OUT1
NONE
PSCLK
DCLK
0.500
INTERNAL
0.000
false
CLKFB_IN_N
CLK_OUT2
0.000
true
DEN
false
Units_MHz
false
MANUAL
UI
0.500
CLK_OUT3
0.000
0.000
100.000
50.0
false
1
false
CLKFB_IN_P
SYSTEM_SYNCHRONOUS
4
CLK_OUT4
2.0
BUFG
false
false
false
1
CLK_OUT5
10.000
1
CLKFBOUT
0.500
CLK_OUT6
false
0.000
false
0.500
None
100.000
50.0
false
CLK_OUT7
0.000
REL_PRIMARY
NONE
false
0.500
false
0.000
4.000
0.010
1
false
false
0.000
false
BUFG
Units_UI
STATUS
50.0
NONE
100.000
0.010
100.000
false
nt64
720p60hzclocksource
1
0.500
false
DCM_CLKGEN
CLK_IN1
0.000
100.0
1
10.000
No_Jitter
No_buffer
false
false
10.000
0.000
0.500
50.0
false
10.000
DCM_CLKGEN
1
PSDONE
CLK_IN1
4
None
0
74.287
N/A
CLK_OUT1
0
MANUAL
0
0.000
CLK_OUT2
50.0
1
0.000
0.000
Units_MHz
100.000
CLK_OUT3
FALSE
1
BUFG
0.500
N/A
0.500
100.000
0.000
Single_ended_clock_capable_pin
CLK_OUT4
2
1
0
0
0.010
CLK_OUT5
50.0
1
0
4.000
FALSE
N/A
CLK_OUT6
100.000
0.000
0.010
CLK_OUT7
DEN
0.500
0.000
PSEN
No_Jitter
CLKFB_OUT_N
26
CLK_IN_SEL
1
FALSE
BUFG
0.500
N/A
50.0
NONE
0.500
10.000
0
Input Clock Input Freq (MHz) Input Jitter (UI)
primary 26 0.010
no secondary input clock
1
0.000
CLKFB_OUT_P
100.000
N/A
CLKFX
0
0.000
0.000
FDBK_AUTO
N/A
NONE
0.000
0.010
0.010
0
FALSE
NONE
0.000
0.500
0
1
BUFG
100.000
N/A
4
N/A
0.500
STATUS
10.000
1
FALSE
DRDY
ZHOLD
1
0.010
nt64
1X
None
384.61
4.000
1
N/A
FALSE
OPTIMIZED
No_buffer
0.000
NONE
7
100.000
38.461
N/A
0.000
0.000
0.000
1
0.500
FALSE
INPUT_CLK_STOPPED
0.500
BUFG
0
0
0.000
1
0.000
N/A
INTERNAL
0
FALSE
0
50.0
CLKOUT1
CLK0
1
LOCKED
DOUT
POWER_DOWN
RESET
0
NONE
100.000
N/A
0
N/A
FALSE
FALSE
CLK_OUT1 74.287 0.000 N/A 200.000 N/A
no CLK_OUT2 output
no CLK_OUT3 output
PSINCDEC
no CLK_OUT4 output
0.000
0
2.000
no CLK_OUT5 output
NONE
no CLK_OUT6 output
no CLK_OUT7 output
N/A
SINGLE
1
0.000
1
10.000
0
NONE
0.000
clkgendcm_720p60hz
0
50.0
CLKFBOUT
CLKFB_IN
0.500
NONE
BUFG
0
DADDR
1
0.500
NONE
20
0
N/A
CLKFB_IN_N
74.285
N/A
CLK_IN2
FALSE
NONE
1
FALSE
DCLK
0.000
None
N/A
Output Output Phase Duty Cycle Pk-to-Pk Phase
CLKFB_IN_P
50.0
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
PSCLK
0.000
0.000
CLKFB_OUT
CLK_VALID
N/A
FALSE
1
DIN
0
SYSTEM_SYNCHRONOUS
0.000
720p60hzclocksource
BUFG
0.500
1
BUFG
0
0.500
DWE
N/A
OPTIMIZED
100.0
50.0
FALSE
coregen
./
./tmp/
./tmp/_cg
xc6slx9
spartan6
tqg144
-2
BusFormatAngleBracketNotRipped
Verilog
true
Other
false
false
false
Ngc
false
Behavioral
Verilog
false
customization_generator
model_parameter_resolution_generator
ip_xco_generator
./clkgendcm_720p60hz.xco
xco
Tue Aug 09 21:40:17 GMT 2011
0x920E017E
generationid_1508053363
ngc_netlist_generator
./clkgendcm_720p60hz/clk_wiz_readme.txt
ignore
txt
Thu Feb 03 22:20:48 GMT 2011
0x63183E2A
generationid_1508053363
./clkgendcm_720p60hz/clkgendcm_720p60hz.ucf
ucf
Tue Aug 09 21:40:20 GMT 2011
0x5EC3B764
generationid_1508053363
./clkgendcm_720p60hz/doc/clk_wiz_ds709.pdf
ignore
pdf
Thu Feb 03 22:20:48 GMT 2011
0xC01920CC
generationid_1508053363
./clkgendcm_720p60hz/doc/clk_wiz_gsg521.pdf
ignore
pdf
Thu Feb 03 22:20:48 GMT 2011
0xBA196AB0
generationid_1508053363
./clkgendcm_720p60hz/example_design/clkgendcm_720p60hz_exdes.v
verilog
Tue Aug 09 21:40:17 GMT 2011
0x53DD6918
generationid_1508053363
./clkgendcm_720p60hz/implement/implement.bat
ignore
unknown
Tue Aug 09 21:40:20 GMT 2011
0x98AE950F
generationid_1508053363
./clkgendcm_720p60hz/implement/implement.sh
ignore
unknown
Tue Aug 09 21:40:19 GMT 2011
0xD7364919
generationid_1508053363
./clkgendcm_720p60hz/implement/planAhead_ise.bat
ignore
unknown
Tue Aug 09 21:40:19 GMT 2011
0x2D87B27F
generationid_1508053363
./clkgendcm_720p60hz/implement/planAhead_ise.sh
ignore
unknown
Tue Aug 09 21:40:19 GMT 2011
0x26D9E0AC
generationid_1508053363
./clkgendcm_720p60hz/implement/planAhead_ise.tcl
ignore
tcl
Tue Aug 09 21:40:19 GMT 2011
0xEE5C7326
generationid_1508053363
./clkgendcm_720p60hz/implement/xst.prj
ignore
unknown
Tue Aug 09 21:40:20 GMT 2011
0x3E535B2C
generationid_1508053363
./clkgendcm_720p60hz/implement/xst.scr
ignore
unknown
Tue Aug 09 21:40:20 GMT 2011
0x392E1A17
generationid_1508053363
./clkgendcm_720p60hz/simulation/clkgendcm_720p60hz_tb.v
ignore
verilog
Tue Aug 09 21:40:17 GMT 2011
0xE300FED0
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/simcmds.tcl
ignore
tcl
Tue Aug 09 21:40:19 GMT 2011
0x522C4A54
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/simulate_isim.bat
ignore
unknown
Tue Aug 09 21:40:18 GMT 2011
0x16B072E8
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/simulate_isim.sh
ignore
unknown
Tue Aug 09 21:40:19 GMT 2011
0x6A4E1E9B
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/simulate_mti.do
ignore
unknown
Tue Aug 09 21:40:18 GMT 2011
0x22B3C2B0
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/simulate_ncsim.sh
ignore
unknown
Tue Aug 09 21:40:18 GMT 2011
0x8FF291AA
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/simulate_vcs.sh
ignore
unknown
Tue Aug 09 21:40:19 GMT 2011
0x6CDC52B7
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/ucli_commands.key
ignore
unknown
Tue Aug 09 21:40:19 GMT 2011
0x15A5CE19
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/vcs_session.tcl
ignore
tcl
Tue Aug 09 21:40:19 GMT 2011
0x1A8D760C
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/wave.do
ignore
unknown
Tue Aug 09 21:40:18 GMT 2011
0xE0FCC1E4
generationid_1508053363
./clkgendcm_720p60hz/simulation/functional/wave.sv
ignore
unknown
Tue Aug 09 21:40:18 GMT 2011
0xF42F3C45
generationid_1508053363
./clkgendcm_720p60hz.ejp
unknown
Tue Aug 09 21:40:17 GMT 2011
0xDEF1B21C
generationid_1508053363
./clkgendcm_720p60hz.v
verilog
Tue Aug 09 21:40:17 GMT 2011
0xBB0CFF9A
generationid_1508053363
./clkgendcm_720p60hz.veo
veo
Tue Aug 09 21:40:17 GMT 2011
0x59A939F4
generationid_1508053363
./clkgendcm_720p60hz_xmdf.tcl
tcl
Tue Aug 09 21:40:18 GMT 2011
0x2BF520E1
generationid_1508053363
instantiation_template_generator
./clkgendcm_720p60hz.veo
veo
Tue Aug 09 21:40:20 GMT 2011
0x59A939F4
generationid_1508053363
asy_generator
./clkgendcm_720p60hz.asy
asy
Tue Aug 09 21:40:24 GMT 2011
0x4709598E
generationid_1508053363
xmdf_generator
ise_generator
./clkgendcm_720p60hz.gise
ignore
gise
Tue Aug 09 21:40:26 GMT 2011
0x62A4AF22
generationid_1508053363
./clkgendcm_720p60hz.xise
ignore
xise
Tue Aug 09 21:40:26 GMT 2011
0x23EDC58D
generationid_1508053363
deliver_readme_generator
flist_generator
./clkgendcm_720p60hz_flist.txt
ignore
txtFlist
txt
Tue Aug 09 21:40:26 GMT 2011
0xC1C72AE1
generationid_1508053363
clk_wiz_v3_1_0
Generated by PlanAhead
clk_wiz_v3_1_0
coregen
./
./tmp/
./tmp/_cg
xc6slx9
spartan6
tqg144
-2
BusFormatAngleBracketNotRipped
Verilog
true
Other
false
false
false
Ngc
false
Behavioral
Verilog
false
coregen
./
./tmp/
./tmp/_cg
xc6slx9
spartan6
tqg144
-2
BusFormatAngleBracketNotRipped
Verilog
true
Other
false
false
false
Ngc
false
Behavioral
Verilog
false