From 889a5a5395872eeb3740d5d3281b56c7afa47a6f Mon Sep 17 00:00:00 2001 From: bnewbold Date: Fri, 20 Jan 2012 19:14:58 -0500 Subject: initial import from NeTV archive This repository is simply a mirror of the file fpga/hdmi_overlay_0xD_src.tgz downloaded from http://www.kosagi.com/netv_hardware/ on Jan 19th, 2011. It seems to contain all the verilog and scripts required to build FPGA firmware for the NeTV HDMI device from Chumby/Sutajio Ko-Usagi; see http://www.kosagi.com/blog/ for more information. Licensing is vague; see ip/license.txt --- ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy | 21 + ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp | 245 +++++++ ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise | 31 + ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v | 133 ++++ ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo | 78 +++ ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ | 133 ++++ ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco | 256 ++++++++ ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise | 405 ++++++++++++ ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt | 33 + ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl | 144 +++++ ip/clk_wiz_v3_1_0/coregen.cgc | 860 +++++++++++++++++++++++++ ip/clk_wiz_v3_1_0/coregen.cgp | 22 + ip/clk_wiz_v3_1_0/coregen.log | 42 ++ ip/clk_wiz_v3_1_0/pa_cg_bom.xml | 61 ++ ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl | 23 + ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl | 17 + 16 files changed, 2504 insertions(+) create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl create mode 100755 ip/clk_wiz_v3_1_0/coregen.cgc create mode 100755 ip/clk_wiz_v3_1_0/coregen.cgp create mode 100755 ip/clk_wiz_v3_1_0/coregen.log create mode 100755 ip/clk_wiz_v3_1_0/pa_cg_bom.xml create mode 100755 ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl create mode 100755 ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl (limited to 'ip/clk_wiz_v3_1_0') diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy new file mode 100755 index 0000000..83e8d5d --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 clkgendcm_720p60hz +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 944 576 944 +PIN 608 944 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp new file mode 100755 index 0000000..b308e6d --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp @@ -0,0 +1,245 @@ +Encore.Project.ProjectDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg +Encore.Project.ElaborationDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg +Encore.Project.TmpDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg +Encore.Project.Path = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg +Encore.Project.FlowVendor = Other +Encore.Project.VhdlSim = false +Encore.Project.VerilogSim = true +Encore.Project.XDevice = xc6slx9 +Encore.Project.XDeviceFamily = spartan6 +Encore.Project.XSpeedGrade = -2 +Encore.Project.XPackage = tqg144 + +c_use_clkout1_bar = 0 +c_use_clkout2_bar = 0 +c_use_clkout3_bar = 0 +c_use_clkout4_bar = 0 +component_name = clkgendcm_720p60hz +c_platform = nt64 +c_use_freq_synth = 1 +c_use_phase_alignment = 0 +c_use_min_o_jitter = 0 +c_use_max_i_jitter = 0 +c_use_dyn_phase_shift = 0 +c_use_inclk_switchover = 0 +c_use_dyn_reconfig = 0 +c_use_spread_spectrum = 0 +c_primtype_sel = DCM_CLKGEN +c_use_clk_valid = 0 +c_prim_in_freq = 26 +c_in_freq_units = Units_MHz +c_secondary_in_freq = 100.000 +c_feedback_source = FDBK_AUTO +c_prim_source = No_buffer +c_secondary_source = Single_ended_clock_capable_pin +c_clkfb_in_signaling = SINGLE +c_use_reset = 1 +c_use_locked = 1 +c_use_inclk_stopped = 0 +c_use_power_down = 0 +c_use_status = 0 +c_use_freeze = 0 +c_num_out_clks = 1 +c_clkout1_drives = BUFG +c_clkout2_drives = BUFG +c_clkout3_drives = BUFG +c_clkout4_drives = BUFG +c_clkout5_drives = BUFG +c_clkout6_drives = BUFG +c_clkout7_drives = BUFG +c_inclk_sum_row0 = Input Clock Input Freq (MHz) Input Jitter (UI) +c_inclk_sum_row1 = primary 26 0.010 +c_inclk_sum_row2 = no secondary input clock +c_outclk_sum_row0a = Output Output Phase Duty Cycle Pk-to-Pk Phase +c_outclk_sum_row0b = Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +c_outclk_sum_row1 = CLK_OUT1 74.287 0.000 N/A 200.000 N/A +c_outclk_sum_row2 = no CLK_OUT2 output +c_outclk_sum_row3 = no CLK_OUT3 output +c_outclk_sum_row4 = no CLK_OUT4 output +c_outclk_sum_row5 = no CLK_OUT5 output +c_outclk_sum_row6 = no CLK_OUT6 output +c_outclk_sum_row7 = no CLK_OUT7 output +c_clkout1_requested_out_freq = 74.285 +c_clkout2_requested_out_freq = 100.000 +c_clkout3_requested_out_freq = 100.000 +c_clkout4_requested_out_freq = 100.000 +c_clkout5_requested_out_freq = 100.000 +c_clkout6_requested_out_freq = 100.000 +c_clkout7_requested_out_freq = 100.000 +c_clkout1_requested_phase = 0.000 +c_clkout2_requested_phase = 0.000 +c_clkout3_requested_phase = 0.000 +c_clkout4_requested_phase = 0.000 +c_clkout5_requested_phase = 0.000 +c_clkout6_requested_phase = 0.000 +c_clkout7_requested_phase = 0.000 +c_clkout1_requested_duty_cycle = 50.0 +c_clkout2_requested_duty_cycle = 50.0 +c_clkout3_requested_duty_cycle = 50.0 +c_clkout4_requested_duty_cycle = 50.0 +c_clkout5_requested_duty_cycle = 50.0 +c_clkout6_requested_duty_cycle = 50.0 +c_clkout7_requested_duty_cycle = 50.0 +c_clkout1_out_freq = 74.287 +c_clkout2_out_freq = N/A +c_clkout3_out_freq = N/A +c_clkout4_out_freq = N/A +c_clkout5_out_freq = N/A +c_clkout6_out_freq = N/A +c_clkout7_out_freq = N/A +c_clkout1_phase = 0.000 +c_clkout2_phase = N/A +c_clkout3_phase = N/A +c_clkout4_phase = N/A +c_clkout5_phase = N/A +c_clkout6_phase = N/A +c_clkout7_phase = N/A +c_clkout1_duty_cycle = N/A +c_clkout2_duty_cycle = N/A +c_clkout3_duty_cycle = N/A +c_clkout4_duty_cycle = N/A +c_clkout5_duty_cycle = N/A +c_clkout6_duty_cycle = N/A +c_clkout7_duty_cycle = N/A +c_mmcm_notes = None +c_mmcm_bandwidth = OPTIMIZED +c_mmcm_clkfbout_mult_f = 4.000 +c_mmcm_clkin1_period = 10.000 +c_mmcm_clkin2_period = 10.000 +c_mmcm_clkout4_cascade = FALSE +c_mmcm_clock_hold = FALSE +c_mmcm_compensation = ZHOLD +c_mmcm_divclk_divide = 1 +c_mmcm_ref_jitter1 = 0.010 +c_mmcm_ref_jitter2 = 0.010 +c_mmcm_startup_wait = FALSE +c_mmcm_clkout0_divide_f = 4.000 +c_mmcm_clkout1_divide = 1 +c_mmcm_clkout2_divide = 1 +c_mmcm_clkout3_divide = 1 +c_mmcm_clkout4_divide = 1 +c_mmcm_clkout5_divide = 1 +c_mmcm_clkout6_divide = 1 +c_mmcm_clkout0_duty_cycle = 0.500 +c_mmcm_clkout1_duty_cycle = 0.500 +c_mmcm_clkout2_duty_cycle = 0.500 +c_mmcm_clkout3_duty_cycle = 0.500 +c_mmcm_clkout4_duty_cycle = 0.500 +c_mmcm_clkout5_duty_cycle = 0.500 +c_mmcm_clkout6_duty_cycle = 0.500 +c_mmcm_clkfbout_phase = 0.000 +c_mmcm_clkout0_phase = 0.000 +c_mmcm_clkout1_phase = 0.000 +c_mmcm_clkout2_phase = 0.000 +c_mmcm_clkout3_phase = 0.000 +c_mmcm_clkout4_phase = 0.000 +c_mmcm_clkout5_phase = 0.000 +c_mmcm_clkout6_phase = 0.000 +c_mmcm_clkfbout_use_fine_ps = FALSE +c_mmcm_clkout0_use_fine_ps = FALSE +c_mmcm_clkout1_use_fine_ps = FALSE +c_mmcm_clkout2_use_fine_ps = FALSE +c_mmcm_clkout3_use_fine_ps = FALSE +c_mmcm_clkout4_use_fine_ps = FALSE +c_mmcm_clkout5_use_fine_ps = FALSE +c_mmcm_clkout6_use_fine_ps = FALSE +c_pll_notes = None +c_pll_bandwidth = OPTIMIZED +c_pll_clk_feedback = CLKFBOUT +c_pll_clkfbout_mult = 4 +c_pll_clkin_period = 10.000 +c_pll_compensation = INTERNAL +c_pll_divclk_divide = 1 +c_pll_ref_jitter = 0.010 +c_pll_clkout0_divide = 1 +c_pll_clkout1_divide = 1 +c_pll_clkout2_divide = 1 +c_pll_clkout3_divide = 1 +c_pll_clkout4_divide = 1 +c_pll_clkout5_divide = 1 +c_pll_clkout0_duty_cycle = 0.500 +c_pll_clkout1_duty_cycle = 0.500 +c_pll_clkout2_duty_cycle = 0.500 +c_pll_clkout3_duty_cycle = 0.500 +c_pll_clkout4_duty_cycle = 0.500 +c_pll_clkout5_duty_cycle = 0.500 +c_pll_clkfbout_phase = 0.000 +c_pll_clkout0_phase = 0.000 +c_pll_clkout1_phase = 0.000 +c_pll_clkout2_phase = 0.000 +c_pll_clkout3_phase = 0.000 +c_pll_clkout4_phase = 0.000 +c_pll_clkout5_phase = 0.000 +c_dcm_notes = None +c_dcm_clkdv_divide = 2.000 +c_dcm_clkfx_divide = 1 +c_dcm_clkfx_multiply = 4 +c_dcm_clkin_divide_by_2 = FALSE +c_dcm_clkin_period = 10.000 +c_dcm_clkout_phase_shift = NONE +c_dcm_clk_feedback = 1X +c_dcm_clk_feedback_port = CLKOUT1 +c_dcm_deskew_adjust = SYSTEM_SYNCHRONOUS +c_dcm_phase_shift = 0 +c_dcm_startup_wait = FALSE +c_dcm_clk_out1_port = CLK0 +c_dcm_clk_out2_port = NONE +c_dcm_clk_out3_port = NONE +c_dcm_clk_out4_port = NONE +c_dcm_clk_out5_port = NONE +c_dcm_clk_out6_port = NONE +c_dcm_clkgen_notes = 720p60hzclocksource +c_dcm_clkgen_clkfxdv_divide = 2 +c_dcm_clkgen_clkfx_divide = 7 +c_dcm_clkgen_clkfx_multiply = 20 +c_dcm_clkgen_dfs_bandwidth = OPTIMIZED +c_dcm_clkgen_prog_md_bandwidth = OPTIMIZED +c_dcm_clkgen_clkin_period = 38.461 +c_dcm_clkgen_clkfx_md_max = 0.000 +c_dcm_clkgen_spread_spectrum = NONE +c_dcm_clkgen_startup_wait = FALSE +c_dcm_clkgen_clk_out1_port = CLKFX +c_dcm_clkgen_clk_out2_port = NONE +c_dcm_clkgen_clk_out3_port = NONE +c_clock_mgr_type = MANUAL +c_override_mmcm = 0 +c_override_pll = 0 +c_override_dcm = 0 +c_override_dcm_clkgen = 1 +c_dcm_pll_cascade = NONE +c_primary_port = CLK_IN1 +c_secondary_port = CLK_IN2 +c_clk_out1_port = CLK_OUT1 +c_clk_out2_port = CLK_OUT2 +c_clk_out3_port = CLK_OUT3 +c_clk_out4_port = CLK_OUT4 +c_clk_out5_port = CLK_OUT5 +c_clk_out6_port = CLK_OUT6 +c_clk_out7_port = CLK_OUT7 +c_reset_port = RESET +c_locked_port = LOCKED +c_clkfb_in_port = CLKFB_IN +c_clkfb_in_p_port = CLKFB_IN_P +c_clkfb_in_n_port = CLKFB_IN_N +c_clkfb_out_port = CLKFB_OUT +c_clkfb_out_p_port = CLKFB_OUT_P +c_clkfb_out_n_port = CLKFB_OUT_N +c_power_down_port = POWER_DOWN +c_daddr_port = DADDR +c_dclk_port = DCLK +c_drdy_port = DRDY +c_dwe_port = DWE +c_din_port = DIN +c_dout_port = DOUT +c_den_port = DEN +c_psclk_port = PSCLK +c_psen_port = PSEN +c_psincdec_port = PSINCDEC +c_psdone_port = PSDONE +c_clk_valid_port = CLK_VALID +c_status_port = STATUS +c_clk_in_sel_port = CLK_IN_SEL +c_input_clk_stopped_port = INPUT_CLK_STOPPED +c_clkin1_jitter_ps = 384.61 +c_clkin2_jitter_ps = 100.0 +ComponentName = clkgendcm_720p60hz diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise new file mode 100755 index 0000000..885900b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v new file mode 100755 index 0000000..ba2ad2f --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v @@ -0,0 +1,133 @@ +// file: clkgendcm_720p60hz.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// 720p60hzclocksource +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// CLK_OUT1 74.287 0.000 N/A 200.000 N/A +// +//---------------------------------------------------------------------------- +// Input Clock Input Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// primary 26 0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *) +module clkgendcm_720p60hz + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + assign clkin1 = CLK_IN1; + + + // Clocking primitive + //------------------------------------ + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [2:1] status_int; + wire clkfx; + wire clkfx180_unused; + wire clkfxdv_unused; + + DCM_CLKGEN + #(.CLKFXDV_DIVIDE (2), + .CLKFX_DIVIDE (7), + .CLKFX_MULTIPLY (20), + .SPREAD_SPECTRUM ("NONE"), + .STARTUP_WAIT ("FALSE"), + .CLKIN_PERIOD (38.461), + .CLKFX_MD_MAX (2.8571)) + dcm_clkgen_inst + // Input clock + (.CLKIN (clkin1), + // Output clocks + .CLKFX (clkfx), + .CLKFX180 (clkfx180_unused), + .CLKFXDV (clkfxdv_unused), + // Ports for dynamic reconfiguration + .PROGCLK (1'b0), + .PROGDATA (PROGDATA), + .PROGEN (PROGEN), + .PROGDONE (progdone_unused), + // Other control and status signals + .FREEZEDCM (1'b0), + .LOCKED (locked_int), + .STATUS (status_int), + .RST (RESET)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkfx)); + + + + +endmodule diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo new file mode 100755 index 0000000..ad61554 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo @@ -0,0 +1,78 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// 720p60hzclocksource +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// CLK_OUT1 74.287 0.000 N/A 200.000 N/A +// +//---------------------------------------------------------------------------- +// Input Clock Input Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// primary 26 0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clkgendcm_720p60hz instance_name + (// Clock in ports + .CLK_IN1(CLK_IN1), // IN + // Clock out ports + .CLK_OUT1(CLK_OUT1), // OUT + // Status and control signals + .RESET(RESET),// IN + .LOCKED(LOCKED)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ new file mode 100755 index 0000000..d6fa44b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ @@ -0,0 +1,133 @@ +// file: clkgendcm_720p60hz.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// 720p60hzclocksource +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// CLK_OUT1 74.287 0.000 N/A 200.000 N/A +// +//---------------------------------------------------------------------------- +// Input Clock Input Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// primary 26 0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *) +module clkgendcm_720p60hz + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + assign clkin1 = CLK_IN1; + + + // Clocking primitive + //------------------------------------ + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [2:1] status_int; + wire clkfx; + wire clkfx180_unused; + wire clkfxdv_unused; + + DCM_CLKGEN + #(.CLKFXDV_DIVIDE (2), + .CLKFX_DIVIDE (7), + .CLKFX_MULTIPLY (20), + .SPREAD_SPECTRUM ("NONE"), + .STARTUP_WAIT ("FALSE"), + .CLKIN_PERIOD (38.461), + .CLKFX_MD_MAX (0.000)) + dcm_clkgen_inst + // Input clock + (.CLKIN (clkin1), + // Output clocks + .CLKFX (clkfx), + .CLKFX180 (clkfx180_unused), + .CLKFXDV (clkfxdv_unused), + // Ports for dynamic reconfiguration + .PROGCLK (1'b0), + .PROGDATA (PROGDATA), + .PROGEN (PROGEN), + .PROGDONE (progdone_unused), + // Other control and status signals + .FREEZEDCM (1'b0), + .LOCKED (locked_int), + .STATUS (status_int), + .RST (RESET)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkfx)); + + + + +endmodule diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco new file mode 100755 index 0000000..5d38e7f --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco @@ -0,0 +1,256 @@ +############################################################## +# +# Xilinx Core Generator version 13.1 +# Date: Tue Aug 09 21:40:17 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard family Xilinx,_Inc. 3.1 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkin1_jitter_ps=384.61 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.0 +CSET clkout1_requested_out_freq=74.285 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.0 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=false +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.0 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=false +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.0 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.0 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.0 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.0 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=MANUAL +CSET component_name=clkgendcm_720p60hz +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLK0 +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=1 +CSET dcm_clkfx_multiply=4 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=7 +CSET dcm_clkgen_clkfx_md_max=0 +CSET dcm_clkgen_clkfx_multiply=20 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=38.461 +CSET dcm_clkgen_notes=720p60hzclocksource +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=10.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=1 +CSET override_dcm=false +CSET override_dcm_clkgen=true +CSET override_mmcm=false +CSET override_pll=false +CSET platform=nt64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=4 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=10.000 +CSET pll_clkout0_divide=1 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=1 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=INTERNAL +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=26 +CSET prim_in_jitter=0.010 +CSET prim_source=No_buffer +CSET primary_port=CLK_IN1 +CSET primtype_sel=DCM_CLKGEN +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=false +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_status=false +# END Parameters +GENERATE +# CRC: fcd26fcc diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise new file mode 100755 index 0000000..38cc24b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise @@ -0,0 +1,405 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt new file mode 100755 index 0000000..2a77c03 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt @@ -0,0 +1,33 @@ +# Output products list for +clkgendcm_720p60hz\clk_wiz_readme.txt +clkgendcm_720p60hz\clkgendcm_720p60hz.ucf +clkgendcm_720p60hz\doc\clk_wiz_ds709.pdf +clkgendcm_720p60hz\doc\clk_wiz_gsg521.pdf +clkgendcm_720p60hz\example_design\clkgendcm_720p60hz_exdes.v +clkgendcm_720p60hz\implement\implement.bat +clkgendcm_720p60hz\implement\implement.sh +clkgendcm_720p60hz\implement\planAhead_ise.bat +clkgendcm_720p60hz\implement\planAhead_ise.sh +clkgendcm_720p60hz\implement\planAhead_ise.tcl +clkgendcm_720p60hz\implement\xst.prj +clkgendcm_720p60hz\implement\xst.scr +clkgendcm_720p60hz\simulation\clkgendcm_720p60hz_tb.v +clkgendcm_720p60hz\simulation\functional\simcmds.tcl +clkgendcm_720p60hz\simulation\functional\simulate_isim.bat +clkgendcm_720p60hz\simulation\functional\simulate_isim.sh +clkgendcm_720p60hz\simulation\functional\simulate_mti.do +clkgendcm_720p60hz\simulation\functional\simulate_ncsim.sh +clkgendcm_720p60hz\simulation\functional\simulate_vcs.sh +clkgendcm_720p60hz\simulation\functional\ucli_commands.key +clkgendcm_720p60hz\simulation\functional\vcs_session.tcl +clkgendcm_720p60hz\simulation\functional\wave.do +clkgendcm_720p60hz\simulation\functional\wave.sv +clkgendcm_720p60hz.asy +clkgendcm_720p60hz.ejp +clkgendcm_720p60hz.gise +clkgendcm_720p60hz.v +clkgendcm_720p60hz.veo +clkgendcm_720p60hz.xco +clkgendcm_720p60hz.xise +clkgendcm_720p60hz_flist.txt +clkgendcm_720p60hz_xmdf.tcl diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl new file mode 100755 index 0000000..6001376 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl @@ -0,0 +1,144 @@ +# The package naming convention is _xmdf +package provide clkgendcm_720p60hz_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::clkgendcm_720p60hz_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::clkgendcm_720p60hz_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name clkgendcm_720p60hz +} +# ::clkgendcm_720p60hz_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::clkgendcm_720p60hz_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/clkgendcm_720p60hz.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/example_design/clkgendcm_720p60hz_exdes.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/clkgendcm_720p60hz_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clkgendcm_720p60hz +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/ip/clk_wiz_v3_1_0/coregen.cgc b/ip/clk_wiz_v3_1_0/coregen.cgc new file mode 100755 index 0000000..0e18e96 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.cgc @@ -0,0 +1,860 @@ + + + xilinx.com + projects + coregen + 1.0 + + + clkgendcm_720p60hz + Generated by PlanAhead + + + clkgendcm_720p60hz + 1 + 100.000 + false + false + PSEN + BUFG + 7 + 38.461 + false + 1 + LOCKED + false + 0.500 + CLK_IN_SEL + CLKFX + 0.000 + false + empty + true + 0.010 + 50.0 + 20 + 0.000 + false + Single_ended_clock_capable_pin + false + 74.285 + CLKFX + INPUT_CLK_STOPPED + 0.500 + OPTIMIZED + 10.000 + false + false + 0.000 + CLKFX + 1 + false + FDBK_AUTO + 0 + 26 + BUFG + 4 + 1 + 1 + CLKFB_OUT_N + 0 + PSINCDEC + 0.500 + ZHOLD + DRDY + 0.000 + 0.000 + 0.000 + None + false + DIN + false + 0.500 + CLKFB_OUT_P + CLKFB_IN + 0.000 + 0.010 + 1 + DWE + 0.000 + false + false + BUFG + true + 0.010 + 0.010 + RESET + 0.000 + false + CLK_IN2 + 1 + PSDONE + SINGLE + CLK0 + 0.500 + DOUT + 100.000 + false + 0.000 + false + CLK0 + 0.010 + 50.0 + 2 + 0.500 + CLK0 + false + DADDR + POWER_DOWN + 0.000 + CLKFB_OUT + true + CLK_VALID + 1 + 1X + OPTIMIZED + 384.61 + CLK0 + BUFG + 1 + 4.000 + DONE + BUFG + false + CLK0 + 100.000 + 1 + None + 50.0 + false + 0.000 + false + CLK0 + false + CLK_OUT1 + NONE + PSCLK + DCLK + 0.500 + INTERNAL + 0.000 + false + CLKFB_IN_N + CLK_OUT2 + 0.000 + true + DEN + false + Units_MHz + false + MANUAL + UI + 0.500 + CLK_OUT3 + 0.000 + 0.000 + 100.000 + 50.0 + false + 1 + false + CLKFB_IN_P + SYSTEM_SYNCHRONOUS + 4 + CLK_OUT4 + 2.0 + BUFG + false + false + false + 1 + CLK_OUT5 + 10.000 + 1 + CLKFBOUT + 0.500 + CLK_OUT6 + false + 0.000 + false + 0.500 + None + 100.000 + 50.0 + false + CLK_OUT7 + 0.000 + REL_PRIMARY + NONE + false + 0.500 + false + 0.000 + 4.000 + 0.010 + 1 + false + false + 0.000 + false + BUFG + Units_UI + STATUS + 50.0 + NONE + 100.000 + 0.010 + 100.000 + false + nt64 + 720p60hzclocksource + 1 + 0.500 + false + DCM_CLKGEN + CLK_IN1 + 0.000 + 100.0 + 1 + 10.000 + No_Jitter + No_buffer + false + false + 10.000 + 0.000 + 0.500 + 50.0 + false + 10.000 + DCM_CLKGEN + 1 + PSDONE + CLK_IN1 + 4 + None + 0 + 74.287 + N/A + CLK_OUT1 + 0 + MANUAL + 0 + 0.000 + CLK_OUT2 + 50.0 + 1 + 0.000 + 0.000 + Units_MHz + 100.000 + CLK_OUT3 + FALSE + 1 + BUFG + 0.500 + N/A + 0.500 + 100.000 + 0.000 + Single_ended_clock_capable_pin + CLK_OUT4 + 2 + 1 + 0 + 0 + 0.010 + CLK_OUT5 + 50.0 + 1 + 0 + 4.000 + FALSE + N/A + CLK_OUT6 + 100.000 + 0.000 + 0.010 + CLK_OUT7 + DEN + 0.500 + 0.000 + PSEN + No_Jitter + CLKFB_OUT_N + 26 + CLK_IN_SEL + 1 + FALSE + BUFG + 0.500 + N/A + 50.0 + NONE + 0.500 + 10.000 + 0 + Input Clock Input Freq (MHz) Input Jitter (UI) + primary 26 0.010 + no secondary input clock + 1 + 0.000 + CLKFB_OUT_P + 100.000 + N/A + CLKFX + 0 + 0.000 + 0.000 + FDBK_AUTO + N/A + NONE + 0.000 + 0.010 + 0.010 + 0 + FALSE + NONE + 0.000 + 0.500 + 0 + 1 + BUFG + 100.000 + N/A + 4 + N/A + 0.500 + STATUS + 10.000 + 1 + FALSE + DRDY + ZHOLD + 1 + 0.010 + nt64 + 1X + None + 384.61 + 4.000 + 1 + N/A + FALSE + OPTIMIZED + No_buffer + 0.000 + NONE + 7 + 100.000 + 38.461 + N/A + 0.000 + 0.000 + 0.000 + 1 + 0.500 + FALSE + INPUT_CLK_STOPPED + 0.500 + BUFG + 0 + 0 + 0.000 + 1 + 0.000 + N/A + INTERNAL + 0 + FALSE + 0 + 50.0 + CLKOUT1 + CLK0 + 1 + LOCKED + DOUT + POWER_DOWN + RESET + 0 + NONE + 100.000 + N/A + 0 + N/A + FALSE + FALSE + CLK_OUT1 74.287 0.000 N/A 200.000 N/A + no CLK_OUT2 output + no CLK_OUT3 output + PSINCDEC + no CLK_OUT4 output + 0.000 + 0 + 2.000 + no CLK_OUT5 output + NONE + no CLK_OUT6 output + no CLK_OUT7 output + N/A + SINGLE + 1 + 0.000 + 1 + 10.000 + 0 + NONE + 0.000 + clkgendcm_720p60hz + 0 + 50.0 + CLKFBOUT + CLKFB_IN + 0.500 + NONE + BUFG + 0 + DADDR + 1 + 0.500 + NONE + 20 + 0 + N/A + CLKFB_IN_N + 74.285 + N/A + CLK_IN2 + FALSE + NONE + 1 + FALSE + DCLK + 0.000 + None + N/A + Output Output Phase Duty Cycle Pk-to-Pk Phase + CLKFB_IN_P + 50.0 + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + PSCLK + 0.000 + 0.000 + CLKFB_OUT + CLK_VALID + N/A + FALSE + 1 + DIN + 0 + SYSTEM_SYNCHRONOUS + 0.000 + 720p60hzclocksource + BUFG + 0.500 + 1 + BUFG + 0 + 0.500 + DWE + N/A + OPTIMIZED + 100.0 + 50.0 + FALSE + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + + + customization_generator + + + model_parameter_resolution_generator + + + ip_xco_generator + + ./clkgendcm_720p60hz.xco + xco + Tue Aug 09 21:40:17 GMT 2011 + 0x920E017E + generationid_1508053363 + + + + ngc_netlist_generator + + ./clkgendcm_720p60hz/clk_wiz_readme.txt + ignore + txt + Thu Feb 03 22:20:48 GMT 2011 + 0x63183E2A + generationid_1508053363 + + + ./clkgendcm_720p60hz/clkgendcm_720p60hz.ucf + ucf + Tue Aug 09 21:40:20 GMT 2011 + 0x5EC3B764 + generationid_1508053363 + + + ./clkgendcm_720p60hz/doc/clk_wiz_ds709.pdf + ignore + pdf + Thu Feb 03 22:20:48 GMT 2011 + 0xC01920CC + generationid_1508053363 + + + ./clkgendcm_720p60hz/doc/clk_wiz_gsg521.pdf + ignore + pdf + Thu Feb 03 22:20:48 GMT 2011 + 0xBA196AB0 + generationid_1508053363 + + + ./clkgendcm_720p60hz/example_design/clkgendcm_720p60hz_exdes.v + verilog + Tue Aug 09 21:40:17 GMT 2011 + 0x53DD6918 + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/implement.bat + ignore + unknown + Tue Aug 09 21:40:20 GMT 2011 + 0x98AE950F + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/implement.sh + ignore + unknown + Tue Aug 09 21:40:19 GMT 2011 + 0xD7364919 + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/planAhead_ise.bat + ignore + unknown + Tue Aug 09 21:40:19 GMT 2011 + 0x2D87B27F + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/planAhead_ise.sh + ignore + unknown + Tue Aug 09 21:40:19 GMT 2011 + 0x26D9E0AC + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/planAhead_ise.tcl + ignore + tcl + Tue Aug 09 21:40:19 GMT 2011 + 0xEE5C7326 + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/xst.prj + ignore + unknown + Tue Aug 09 21:40:20 GMT 2011 + 0x3E535B2C + generationid_1508053363 + + + ./clkgendcm_720p60hz/implement/xst.scr + ignore + unknown + Tue Aug 09 21:40:20 GMT 2011 + 0x392E1A17 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/clkgendcm_720p60hz_tb.v + ignore + verilog + Tue Aug 09 21:40:17 GMT 2011 + 0xE300FED0 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/simcmds.tcl + ignore + tcl + Tue Aug 09 21:40:19 GMT 2011 + 0x522C4A54 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/simulate_isim.bat + ignore + unknown + Tue Aug 09 21:40:18 GMT 2011 + 0x16B072E8 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/simulate_isim.sh + ignore + unknown + Tue Aug 09 21:40:19 GMT 2011 + 0x6A4E1E9B + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/simulate_mti.do + ignore + unknown + Tue Aug 09 21:40:18 GMT 2011 + 0x22B3C2B0 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/simulate_ncsim.sh + ignore + unknown + Tue Aug 09 21:40:18 GMT 2011 + 0x8FF291AA + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/simulate_vcs.sh + ignore + unknown + Tue Aug 09 21:40:19 GMT 2011 + 0x6CDC52B7 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/ucli_commands.key + ignore + unknown + Tue Aug 09 21:40:19 GMT 2011 + 0x15A5CE19 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/vcs_session.tcl + ignore + tcl + Tue Aug 09 21:40:19 GMT 2011 + 0x1A8D760C + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/wave.do + ignore + unknown + Tue Aug 09 21:40:18 GMT 2011 + 0xE0FCC1E4 + generationid_1508053363 + + + ./clkgendcm_720p60hz/simulation/functional/wave.sv + ignore + unknown + Tue Aug 09 21:40:18 GMT 2011 + 0xF42F3C45 + generationid_1508053363 + + + ./clkgendcm_720p60hz.ejp + unknown + Tue Aug 09 21:40:17 GMT 2011 + 0xDEF1B21C + generationid_1508053363 + + + ./clkgendcm_720p60hz.v + verilog + Tue Aug 09 21:40:17 GMT 2011 + 0xBB0CFF9A + generationid_1508053363 + + + ./clkgendcm_720p60hz.veo + veo + Tue Aug 09 21:40:17 GMT 2011 + 0x59A939F4 + generationid_1508053363 + + + ./clkgendcm_720p60hz_xmdf.tcl + tcl + Tue Aug 09 21:40:18 GMT 2011 + 0x2BF520E1 + generationid_1508053363 + + + + instantiation_template_generator + + ./clkgendcm_720p60hz.veo + veo + Tue Aug 09 21:40:20 GMT 2011 + 0x59A939F4 + generationid_1508053363 + + + + asy_generator + + ./clkgendcm_720p60hz.asy + asy + Tue Aug 09 21:40:24 GMT 2011 + 0x4709598E + generationid_1508053363 + + + + xmdf_generator + + + ise_generator + + ./clkgendcm_720p60hz.gise + ignore + gise + Tue Aug 09 21:40:26 GMT 2011 + 0x62A4AF22 + generationid_1508053363 + + + ./clkgendcm_720p60hz.xise + ignore + xise + Tue Aug 09 21:40:26 GMT 2011 + 0x23EDC58D + generationid_1508053363 + + + + deliver_readme_generator + + + flist_generator + + ./clkgendcm_720p60hz_flist.txt + ignore + txtFlist + txt + Tue Aug 09 21:40:26 GMT 2011 + 0xC1C72AE1 + generationid_1508053363 + + + + + + + clk_wiz_v3_1_0 + Generated by PlanAhead + + + clk_wiz_v3_1_0 + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc6slx9 + spartan6 + tqg144 + -2 + + + BusFormatAngleBracketNotRipped + Verilog + true + Other + false + false + false + Ngc + false + + + Behavioral + Verilog + false + + + + diff --git a/ip/clk_wiz_v3_1_0/coregen.cgp b/ip/clk_wiz_v3_1_0/coregen.cgp new file mode 100755 index 0000000..555710a --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.cgp @@ -0,0 +1,22 @@ +# Date: Tue Aug 09 21:35:33 2011 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = ./tmp/ + +# CRC: e7d90245 diff --git a/ip/clk_wiz_v3_1_0/coregen.log b/ip/clk_wiz_v3_1_0/coregen.log new file mode 100755 index 0000000..f93187b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.log @@ -0,0 +1,42 @@ +CoreGen has not been configured with any user repositories. +CoreGen has been configured with the following Xilinx repositories: + - 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\' [] +INFO:sim:927 - Generating component instance 'clkgendcm_720p60hz' of + 'xilinx.com:ip:clk_wiz:3.1' from + 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3 + _1\clk_wiz_v3_1.xcd'. +Resolving generic values... +Initializing IP model... +Loading device for application Rf_Device from file '6slx9.nph' in environment +C:\Xilinx\13.1\ISE_DS\ISE\. +Finished initializing IP model. +Finished resolving generic values. +Generating IP... +WARNING:sim:89 - A core named already exists in the output + directory. Output products for this core may be overwritten. +Skipping VHDL instantiation template for clkgendcm_720p60hz... +Creating ISE instantiation template for clkgendcm_720p60hz... +Collating core files for clkgendcm_720p60hz +Collating core files for clkgendcm_720p60hz +Configuring files for clkgendcm_720p60hz root... +Finished Generation. +Generating IP instantiation template... +Finished generating IP instantiation template. +Generating ASY schematic symbol... +Initializing IP model... +Finished initializing IP model. +Finished generating ASY schematic symbol. +Generating metadata file... +Finished generating metadata file. +Generating ISE project... +WARNING:sim - This core does not have a top level called "/clkgendcm_720p60hz" +WARNING:sim - Top level has been set to "/clkgendcm_720p60hz_exdes" +Finished generating ISE project.Generating README file... +Finished generating README file. +Generating FLIST file... +Finished FLIST file generation. +Preparing output directory... +Finished preparing output directory. +Moving files to output directory... +Finished moving files to output directory +Saved options for project 'coregen'. diff --git a/ip/clk_wiz_v3_1_0/pa_cg_bom.xml b/ip/clk_wiz_v3_1_0/pa_cg_bom.xml new file mode 100755 index 0000000..7a61bc9 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/pa_cg_bom.xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl b/ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl new file mode 100755 index 0000000..d5918a7 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl @@ -0,0 +1,23 @@ +# Tcl script generated by PlanAhead + +set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl" + +set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/coregen.cgc" + +set ipName "clk_wiz_v3_1_0" + +set vlnv "xilinx.com:ip:clk_wiz:3.1" + +set cgPartSpec "6slx9-2tqg144" + +set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/pa_cg_bom.xml" + +set hdlType "Verilog" + +set chains "CUSTOMIZE_CHAIN INSTANTIATION_TEMPLATES_CHAIN" + +# configure the IP +set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_config_core.tcl"] + +exit $result + diff --git a/ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl b/ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl new file mode 100755 index 0000000..f504ffb --- /dev/null +++ b/ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl @@ -0,0 +1,17 @@ +# Tcl script generated by PlanAhead + +set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl" + +set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/coregen.cgc" + +set ipName "clkgendcm_720p60hz" + +set chains "GENERATE_CHAIN" + +set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/pa_cg_bom.xml" + +# generate the IP +set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_gen_core.tcl"] + +exit $result + -- cgit v1.2.3