From 889a5a5395872eeb3740d5d3281b56c7afa47a6f Mon Sep 17 00:00:00 2001 From: bnewbold Date: Fri, 20 Jan 2012 19:14:58 -0500 Subject: initial import from NeTV archive This repository is simply a mirror of the file fpga/hdmi_overlay_0xD_src.tgz downloaded from http://www.kosagi.com/netv_hardware/ on Jan 19th, 2011. It seems to contain all the verilog and scripts required to build FPGA firmware for the NeTV HDMI device from Chumby/Sutajio Ko-Usagi; see http://www.kosagi.com/blog/ for more information. Licensing is vague; see ip/license.txt --- ip/clk_wiz_v3_1_0/coregen.log | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100755 ip/clk_wiz_v3_1_0/coregen.log (limited to 'ip/clk_wiz_v3_1_0/coregen.log') diff --git a/ip/clk_wiz_v3_1_0/coregen.log b/ip/clk_wiz_v3_1_0/coregen.log new file mode 100755 index 0000000..f93187b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.log @@ -0,0 +1,42 @@ +CoreGen has not been configured with any user repositories. +CoreGen has been configured with the following Xilinx repositories: + - 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\' [] +INFO:sim:927 - Generating component instance 'clkgendcm_720p60hz' of + 'xilinx.com:ip:clk_wiz:3.1' from + 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3 + _1\clk_wiz_v3_1.xcd'. +Resolving generic values... +Initializing IP model... +Loading device for application Rf_Device from file '6slx9.nph' in environment +C:\Xilinx\13.1\ISE_DS\ISE\. +Finished initializing IP model. +Finished resolving generic values. +Generating IP... +WARNING:sim:89 - A core named already exists in the output + directory. Output products for this core may be overwritten. +Skipping VHDL instantiation template for clkgendcm_720p60hz... +Creating ISE instantiation template for clkgendcm_720p60hz... +Collating core files for clkgendcm_720p60hz +Collating core files for clkgendcm_720p60hz +Configuring files for clkgendcm_720p60hz root... +Finished Generation. +Generating IP instantiation template... +Finished generating IP instantiation template. +Generating ASY schematic symbol... +Initializing IP model... +Finished initializing IP model. +Finished generating ASY schematic symbol. +Generating metadata file... +Finished generating metadata file. +Generating ISE project... +WARNING:sim - This core does not have a top level called "/clkgendcm_720p60hz" +WARNING:sim - Top level has been set to "/clkgendcm_720p60hz_exdes" +Finished generating ISE project.Generating README file... +Finished generating README file. +Generating FLIST file... +Finished FLIST file generation. +Preparing output directory... +Finished preparing output directory. +Moving files to output directory... +Finished moving files to output directory +Saved options for project 'coregen'. -- cgit v1.2.3