From 889a5a5395872eeb3740d5d3281b56c7afa47a6f Mon Sep 17 00:00:00 2001 From: bnewbold Date: Fri, 20 Jan 2012 19:14:58 -0500 Subject: initial import from NeTV archive This repository is simply a mirror of the file fpga/hdmi_overlay_0xD_src.tgz downloaded from http://www.kosagi.com/netv_hardware/ on Jan 19th, 2011. It seems to contain all the verilog and scripts required to build FPGA firmware for the NeTV HDMI device from Chumby/Sutajio Ko-Usagi; see http://www.kosagi.com/blog/ for more information. Licensing is vague; see ip/license.txt --- ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v | 133 +++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100755 ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v (limited to 'ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v') diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v new file mode 100755 index 0000000..ba2ad2f --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v @@ -0,0 +1,133 @@ +// file: clkgendcm_720p60hz.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// 720p60hzclocksource +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// CLK_OUT1 74.287 0.000 N/A 200.000 N/A +// +//---------------------------------------------------------------------------- +// Input Clock Input Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// primary 26 0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *) +module clkgendcm_720p60hz + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + assign clkin1 = CLK_IN1; + + + // Clocking primitive + //------------------------------------ + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [2:1] status_int; + wire clkfx; + wire clkfx180_unused; + wire clkfxdv_unused; + + DCM_CLKGEN + #(.CLKFXDV_DIVIDE (2), + .CLKFX_DIVIDE (7), + .CLKFX_MULTIPLY (20), + .SPREAD_SPECTRUM ("NONE"), + .STARTUP_WAIT ("FALSE"), + .CLKIN_PERIOD (38.461), + .CLKFX_MD_MAX (2.8571)) + dcm_clkgen_inst + // Input clock + (.CLKIN (clkin1), + // Output clocks + .CLKFX (clkfx), + .CLKFX180 (clkfx180_unused), + .CLKFXDV (clkfxdv_unused), + // Ports for dynamic reconfiguration + .PROGCLK (1'b0), + .PROGDATA (PROGDATA), + .PROGEN (PROGEN), + .PROGDONE (progdone_unused), + // Other control and status signals + .FREEZEDCM (1'b0), + .LOCKED (locked_int), + .STATUS (status_int), + .RST (RESET)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkfx)); + + + + +endmodule -- cgit v1.2.3