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|
1 .syntax unified
2 .cpu cortex-m3
3 .fpu softvfp
4 .eabi_attribute 20, 1
5 .eabi_attribute 21, 1
6 .eabi_attribute 23, 3
7 .eabi_attribute 24, 1
8 .eabi_attribute 25, 1
9 .eabi_attribute 26, 1
10 .eabi_attribute 30, 4
11 .eabi_attribute 18, 4
12 .thumb
13 .file "stm32f10x_rcc.c"
21 .Ltext0:
22 .align 2
23 .global RCC_DeInit
24 .thumb
25 .thumb_func
27 RCC_DeInit:
28 .LFB23:
29 .file 1 "stm32lib/src/stm32f10x_rcc.c"
1:stm32lib/src/stm32f10x_rcc.c **** /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2:stm32lib/src/stm32f10x_rcc.c **** * File Name : stm32f10x_rcc.c
3:stm32lib/src/stm32f10x_rcc.c **** * Author : MCD Application Team
4:stm32lib/src/stm32f10x_rcc.c **** * Version : V2.0.2
5:stm32lib/src/stm32f10x_rcc.c **** * Date : 07/11/2008
6:stm32lib/src/stm32f10x_rcc.c **** * Description : This file provides all the RCC firmware functions.
7:stm32lib/src/stm32f10x_rcc.c **** ********************************************************************************
8:stm32lib/src/stm32f10x_rcc.c **** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9:stm32lib/src/stm32f10x_rcc.c **** * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10:stm32lib/src/stm32f10x_rcc.c **** * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11:stm32lib/src/stm32f10x_rcc.c **** * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12:stm32lib/src/stm32f10x_rcc.c **** * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13:stm32lib/src/stm32f10x_rcc.c **** * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
15:stm32lib/src/stm32f10x_rcc.c ****
16:stm32lib/src/stm32f10x_rcc.c **** /* Includes ------------------------------------------------------------------*/
17:stm32lib/src/stm32f10x_rcc.c **** #include "stm32f10x_rcc.h"
18:stm32lib/src/stm32f10x_rcc.c ****
19:stm32lib/src/stm32f10x_rcc.c **** /* Private typedef -----------------------------------------------------------*/
20:stm32lib/src/stm32f10x_rcc.c **** /* Private define ------------------------------------------------------------*/
21:stm32lib/src/stm32f10x_rcc.c **** /* ------------ RCC registers bit address in the alias region ----------- */
22:stm32lib/src/stm32f10x_rcc.c **** #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
23:stm32lib/src/stm32f10x_rcc.c ****
24:stm32lib/src/stm32f10x_rcc.c **** /* --- CR Register ---*/
25:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of HSION bit */
26:stm32lib/src/stm32f10x_rcc.c **** #define CR_OFFSET (RCC_OFFSET + 0x00)
27:stm32lib/src/stm32f10x_rcc.c **** #define HSION_BitNumber 0x00
28:stm32lib/src/stm32f10x_rcc.c **** #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
29:stm32lib/src/stm32f10x_rcc.c ****
30:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of PLLON bit */
31:stm32lib/src/stm32f10x_rcc.c **** #define PLLON_BitNumber 0x18
32:stm32lib/src/stm32f10x_rcc.c **** #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
33:stm32lib/src/stm32f10x_rcc.c ****
34:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of CSSON bit */
35:stm32lib/src/stm32f10x_rcc.c **** #define CSSON_BitNumber 0x13
36:stm32lib/src/stm32f10x_rcc.c **** #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
37:stm32lib/src/stm32f10x_rcc.c ****
38:stm32lib/src/stm32f10x_rcc.c **** /* --- CFGR Register ---*/
39:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of USBPRE bit */
40:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_OFFSET (RCC_OFFSET + 0x04)
41:stm32lib/src/stm32f10x_rcc.c **** #define USBPRE_BitNumber 0x16
42:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
43:stm32lib/src/stm32f10x_rcc.c ****
44:stm32lib/src/stm32f10x_rcc.c **** /* --- BDCR Register ---*/
45:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of RTCEN bit */
46:stm32lib/src/stm32f10x_rcc.c **** #define BDCR_OFFSET (RCC_OFFSET + 0x20)
47:stm32lib/src/stm32f10x_rcc.c **** #define RTCEN_BitNumber 0x0F
48:stm32lib/src/stm32f10x_rcc.c **** #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
49:stm32lib/src/stm32f10x_rcc.c ****
50:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of BDRST bit */
51:stm32lib/src/stm32f10x_rcc.c **** #define BDRST_BitNumber 0x10
52:stm32lib/src/stm32f10x_rcc.c **** #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
53:stm32lib/src/stm32f10x_rcc.c ****
54:stm32lib/src/stm32f10x_rcc.c **** /* --- CSR Register ---*/
55:stm32lib/src/stm32f10x_rcc.c **** /* Alias word address of LSION bit */
56:stm32lib/src/stm32f10x_rcc.c **** #define CSR_OFFSET (RCC_OFFSET + 0x24)
57:stm32lib/src/stm32f10x_rcc.c **** #define LSION_BitNumber 0x00
58:stm32lib/src/stm32f10x_rcc.c **** #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
59:stm32lib/src/stm32f10x_rcc.c ****
60:stm32lib/src/stm32f10x_rcc.c **** /* ---------------------- RCC registers bit mask ------------------------ */
61:stm32lib/src/stm32f10x_rcc.c **** /* CR register bit mask */
62:stm32lib/src/stm32f10x_rcc.c **** #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
63:stm32lib/src/stm32f10x_rcc.c **** #define CR_HSEBYP_Set ((u32)0x00040000)
64:stm32lib/src/stm32f10x_rcc.c **** #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
65:stm32lib/src/stm32f10x_rcc.c **** #define CR_HSEON_Set ((u32)0x00010000)
66:stm32lib/src/stm32f10x_rcc.c **** #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
67:stm32lib/src/stm32f10x_rcc.c ****
68:stm32lib/src/stm32f10x_rcc.c **** /* CFGR register bit mask */
69:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
70:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PLLMull_Mask ((u32)0x003C0000)
71:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PLLSRC_Mask ((u32)0x00010000)
72:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
73:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_SWS_Mask ((u32)0x0000000C)
74:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
75:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
76:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
77:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
78:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
79:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
80:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
81:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
82:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
83:stm32lib/src/stm32f10x_rcc.c ****
84:stm32lib/src/stm32f10x_rcc.c **** /* CSR register bit mask */
85:stm32lib/src/stm32f10x_rcc.c **** #define CSR_RMVF_Set ((u32)0x01000000)
86:stm32lib/src/stm32f10x_rcc.c ****
87:stm32lib/src/stm32f10x_rcc.c **** /* RCC Flag Mask */
88:stm32lib/src/stm32f10x_rcc.c **** #define FLAG_Mask ((u8)0x1F)
89:stm32lib/src/stm32f10x_rcc.c ****
90:stm32lib/src/stm32f10x_rcc.c **** /* Typical Value of the HSI in Hz */
91:stm32lib/src/stm32f10x_rcc.c **** #define HSI_Value ((u32)8000000)
92:stm32lib/src/stm32f10x_rcc.c ****
93:stm32lib/src/stm32f10x_rcc.c **** /* CIR register byte 2 (Bits[15:8]) base address */
94:stm32lib/src/stm32f10x_rcc.c **** #define CIR_BYTE2_ADDRESS ((u32)0x40021009)
95:stm32lib/src/stm32f10x_rcc.c **** /* CIR register byte 3 (Bits[23:16]) base address */
96:stm32lib/src/stm32f10x_rcc.c **** #define CIR_BYTE3_ADDRESS ((u32)0x4002100A)
97:stm32lib/src/stm32f10x_rcc.c ****
98:stm32lib/src/stm32f10x_rcc.c **** /* CFGR register byte 4 (Bits[31:24]) base address */
99:stm32lib/src/stm32f10x_rcc.c **** #define CFGR_BYTE4_ADDRESS ((u32)0x40021007)
100:stm32lib/src/stm32f10x_rcc.c ****
101:stm32lib/src/stm32f10x_rcc.c **** /* BDCR register base address */
102:stm32lib/src/stm32f10x_rcc.c **** #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
103:stm32lib/src/stm32f10x_rcc.c ****
104:stm32lib/src/stm32f10x_rcc.c **** /* Time out for HSE start up */
105:stm32lib/src/stm32f10x_rcc.c **** #define HSEStartUp_TimeOut ((u16)0x01FF)
106:stm32lib/src/stm32f10x_rcc.c ****
107:stm32lib/src/stm32f10x_rcc.c **** /* Private macro -------------------------------------------------------------*/
108:stm32lib/src/stm32f10x_rcc.c **** /* Private variables ---------------------------------------------------------*/
109:stm32lib/src/stm32f10x_rcc.c **** static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
110:stm32lib/src/stm32f10x_rcc.c **** static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
111:stm32lib/src/stm32f10x_rcc.c ****
112:stm32lib/src/stm32f10x_rcc.c **** static volatile FlagStatus HSEStatus;
113:stm32lib/src/stm32f10x_rcc.c **** static vu32 StartUpCounter = 0;
114:stm32lib/src/stm32f10x_rcc.c ****
115:stm32lib/src/stm32f10x_rcc.c **** /* Private function prototypes -----------------------------------------------*/
116:stm32lib/src/stm32f10x_rcc.c **** /* Private functions ---------------------------------------------------------*/
117:stm32lib/src/stm32f10x_rcc.c ****
118:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
119:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_DeInit
120:stm32lib/src/stm32f10x_rcc.c **** * Description : Resets the RCC clock configuration to the default reset state.
121:stm32lib/src/stm32f10x_rcc.c **** * Input : None
122:stm32lib/src/stm32f10x_rcc.c **** * Output : None
123:stm32lib/src/stm32f10x_rcc.c **** * Return : None
124:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
125:stm32lib/src/stm32f10x_rcc.c **** void RCC_DeInit(void)
126:stm32lib/src/stm32f10x_rcc.c **** {
30 .loc 1 126 0
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
127:stm32lib/src/stm32f10x_rcc.c **** /* Set HSION bit */
128:stm32lib/src/stm32f10x_rcc.c **** RCC->CR |= (u32)0x00000001;
34 .loc 1 128 0
35 0000 0D4A ldr r2, .L3
36 0002 1368 ldr r3, [r2, #0]
37 0004 43F00103 orr r3, r3, #1
38 0008 1360 str r3, [r2, #0]
129:stm32lib/src/stm32f10x_rcc.c ****
130:stm32lib/src/stm32f10x_rcc.c **** /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
131:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR &= (u32)0xF8FF0000;
39 .loc 1 131 0
40 000a 5168 ldr r1, [r2, #4]
41 000c 0B4B ldr r3, .L3+4
42 000e 01EA0303 and r3, r1, r3
43 0012 5360 str r3, [r2, #4]
132:stm32lib/src/stm32f10x_rcc.c ****
133:stm32lib/src/stm32f10x_rcc.c **** /* Reset HSEON, CSSON and PLLON bits */
134:stm32lib/src/stm32f10x_rcc.c **** RCC->CR &= (u32)0xFEF6FFFF;
44 .loc 1 134 0
45 0014 1368 ldr r3, [r2, #0]
46 0016 23F08473 bic r3, r3, #17301504
47 001a 23F48033 bic r3, r3, #65536
48 001e 1360 str r3, [r2, #0]
135:stm32lib/src/stm32f10x_rcc.c ****
136:stm32lib/src/stm32f10x_rcc.c **** /* Reset HSEBYP bit */
137:stm32lib/src/stm32f10x_rcc.c **** RCC->CR &= (u32)0xFFFBFFFF;
49 .loc 1 137 0
50 0020 1368 ldr r3, [r2, #0]
51 0022 23F48023 bic r3, r3, #262144
52 0026 1360 str r3, [r2, #0]
138:stm32lib/src/stm32f10x_rcc.c ****
139:stm32lib/src/stm32f10x_rcc.c **** /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
140:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR &= (u32)0xFF80FFFF;
53 .loc 1 140 0
54 0028 5368 ldr r3, [r2, #4]
55 002a 23F4FE03 bic r3, r3, #8323072
56 002e 5360 str r3, [r2, #4]
141:stm32lib/src/stm32f10x_rcc.c ****
142:stm32lib/src/stm32f10x_rcc.c **** /* Disable all interrupts */
143:stm32lib/src/stm32f10x_rcc.c **** RCC->CIR = 0x00000000;
57 .loc 1 143 0
58 0030 0023 movs r3, #0
59 0032 9360 str r3, [r2, #8]
144:stm32lib/src/stm32f10x_rcc.c **** }
60 .loc 1 144 0
61 0034 7047 bx lr
62 .L4:
63 0036 00BF .align 2
64 .L3:
65 0038 00100240 .word 1073876992
66 003c 0000FFF8 .word -117506048
67 .LFE23:
69 .align 2
70 .global RCC_HSEConfig
71 .thumb
72 .thumb_func
74 RCC_HSEConfig:
75 .LFB24:
145:stm32lib/src/stm32f10x_rcc.c ****
146:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
147:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_HSEConfig
148:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the External High Speed oscillator (HSE).
149:stm32lib/src/stm32f10x_rcc.c **** * HSE can not be stopped if it is used directly or through the
150:stm32lib/src/stm32f10x_rcc.c **** * PLL as system clock.
151:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_HSE: specifies the new state of the HSE.
152:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
153:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HSE_OFF: HSE oscillator OFF
154:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HSE_ON: HSE oscillator ON
155:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HSE_Bypass: HSE oscillator bypassed with external
156:stm32lib/src/stm32f10x_rcc.c **** * clock
157:stm32lib/src/stm32f10x_rcc.c **** * Output : None
158:stm32lib/src/stm32f10x_rcc.c **** * Return : None
159:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
160:stm32lib/src/stm32f10x_rcc.c **** void RCC_HSEConfig(u32 RCC_HSE)
161:stm32lib/src/stm32f10x_rcc.c **** {
76 .loc 1 161 0
77 @ args = 0, pretend = 0, frame = 0
78 @ frame_needed = 0, uses_anonymous_args = 0
79 @ link register save eliminated.
80 .LVL0:
162:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
163:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_HSE(RCC_HSE));
164:stm32lib/src/stm32f10x_rcc.c ****
165:stm32lib/src/stm32f10x_rcc.c **** /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
166:stm32lib/src/stm32f10x_rcc.c **** /* Reset HSEON bit */
167:stm32lib/src/stm32f10x_rcc.c **** RCC->CR &= CR_HSEON_Reset;
81 .loc 1 167 0
82 0040 0C4A ldr r2, .L12
168:stm32lib/src/stm32f10x_rcc.c ****
169:stm32lib/src/stm32f10x_rcc.c **** /* Reset HSEBYP bit */
170:stm32lib/src/stm32f10x_rcc.c **** RCC->CR &= CR_HSEBYP_Reset;
171:stm32lib/src/stm32f10x_rcc.c ****
172:stm32lib/src/stm32f10x_rcc.c **** /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
173:stm32lib/src/stm32f10x_rcc.c **** switch(RCC_HSE)
83 .loc 1 173 0
84 0042 B0F5803F cmp r0, #65536
85 .loc 1 167 0
86 0046 1368 ldr r3, [r2, #0]
87 0048 23F48033 bic r3, r3, #65536
88 004c 1360 str r3, [r2, #0]
89 .loc 1 170 0
90 004e 1368 ldr r3, [r2, #0]
91 0050 23F48023 bic r3, r3, #262144
92 0054 1360 str r3, [r2, #0]
93 .loc 1 173 0
94 0056 03D0 beq .L7
95 0058 B0F5802F cmp r0, #262144
96 005c 08D1 bne .L9
97 005e 03E0 b .L11
98 .L7:
174:stm32lib/src/stm32f10x_rcc.c **** {
175:stm32lib/src/stm32f10x_rcc.c **** case RCC_HSE_ON:
176:stm32lib/src/stm32f10x_rcc.c **** /* Set HSEON bit */
177:stm32lib/src/stm32f10x_rcc.c **** RCC->CR |= CR_HSEON_Set;
99 .loc 1 177 0
100 0060 1368 ldr r3, [r2, #0]
101 0062 43F48033 orr r3, r3, #65536
102 0066 02E0 b .L10
103 .L11:
178:stm32lib/src/stm32f10x_rcc.c **** break;
179:stm32lib/src/stm32f10x_rcc.c ****
180:stm32lib/src/stm32f10x_rcc.c **** case RCC_HSE_Bypass:
181:stm32lib/src/stm32f10x_rcc.c **** /* Set HSEBYP and HSEON bits */
182:stm32lib/src/stm32f10x_rcc.c **** RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
104 .loc 1 182 0
105 0068 1368 ldr r3, [r2, #0]
106 006a 43F4A023 orr r3, r3, #327680
107 .L10:
108 006e 1360 str r3, [r2, #0]
109 .L9:
183:stm32lib/src/stm32f10x_rcc.c **** break;
184:stm32lib/src/stm32f10x_rcc.c ****
185:stm32lib/src/stm32f10x_rcc.c **** default:
186:stm32lib/src/stm32f10x_rcc.c **** break;
187:stm32lib/src/stm32f10x_rcc.c **** }
188:stm32lib/src/stm32f10x_rcc.c **** }
110 .loc 1 188 0
111 0070 7047 bx lr
112 .L13:
113 0072 00BF .align 2
114 .L12:
115 0074 00100240 .word 1073876992
116 .LFE24:
118 .align 2
119 .global RCC_AdjustHSICalibrationValue
120 .thumb
121 .thumb_func
123 RCC_AdjustHSICalibrationValue:
124 .LFB26:
189:stm32lib/src/stm32f10x_rcc.c ****
190:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
191:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_WaitForHSEStartUp
192:stm32lib/src/stm32f10x_rcc.c **** * Description : Waits for HSE start-up.
193:stm32lib/src/stm32f10x_rcc.c **** * Input : None
194:stm32lib/src/stm32f10x_rcc.c **** * Output : None
195:stm32lib/src/stm32f10x_rcc.c **** * Return : An ErrorStatus enumuration value:
196:stm32lib/src/stm32f10x_rcc.c **** * - SUCCESS: HSE oscillator is stable and ready to use
197:stm32lib/src/stm32f10x_rcc.c **** * - ERROR: HSE oscillator not yet ready
198:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
199:stm32lib/src/stm32f10x_rcc.c **** ErrorStatus RCC_WaitForHSEStartUp(void)
200:stm32lib/src/stm32f10x_rcc.c **** {
201:stm32lib/src/stm32f10x_rcc.c **** ErrorStatus status = ERROR;
202:stm32lib/src/stm32f10x_rcc.c ****
203:stm32lib/src/stm32f10x_rcc.c **** /* Wait till HSE is ready and if Time out is reached exit */
204:stm32lib/src/stm32f10x_rcc.c **** do
205:stm32lib/src/stm32f10x_rcc.c **** {
206:stm32lib/src/stm32f10x_rcc.c **** HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
207:stm32lib/src/stm32f10x_rcc.c **** StartUpCounter++;
208:stm32lib/src/stm32f10x_rcc.c **** } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
209:stm32lib/src/stm32f10x_rcc.c ****
210:stm32lib/src/stm32f10x_rcc.c ****
211:stm32lib/src/stm32f10x_rcc.c **** if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
212:stm32lib/src/stm32f10x_rcc.c **** {
213:stm32lib/src/stm32f10x_rcc.c **** status = SUCCESS;
214:stm32lib/src/stm32f10x_rcc.c **** }
215:stm32lib/src/stm32f10x_rcc.c **** else
216:stm32lib/src/stm32f10x_rcc.c **** {
217:stm32lib/src/stm32f10x_rcc.c **** status = ERROR;
218:stm32lib/src/stm32f10x_rcc.c **** }
219:stm32lib/src/stm32f10x_rcc.c ****
220:stm32lib/src/stm32f10x_rcc.c **** return (status);
221:stm32lib/src/stm32f10x_rcc.c **** }
222:stm32lib/src/stm32f10x_rcc.c ****
223:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
224:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_AdjustHSICalibrationValue
225:stm32lib/src/stm32f10x_rcc.c **** * Description : Adjusts the Internal High Speed oscillator (HSI) calibration
226:stm32lib/src/stm32f10x_rcc.c **** * value.
227:stm32lib/src/stm32f10x_rcc.c **** * Input : - HSICalibrationValue: specifies the calibration trimming value.
228:stm32lib/src/stm32f10x_rcc.c **** * This parameter must be a number between 0 and 0x1F.
229:stm32lib/src/stm32f10x_rcc.c **** * Output : None
230:stm32lib/src/stm32f10x_rcc.c **** * Return : None
231:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
232:stm32lib/src/stm32f10x_rcc.c **** void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
233:stm32lib/src/stm32f10x_rcc.c **** {
125 .loc 1 233 0
126 @ args = 0, pretend = 0, frame = 0
127 @ frame_needed = 0, uses_anonymous_args = 0
128 @ link register save eliminated.
129 .LVL1:
234:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
235:stm32lib/src/stm32f10x_rcc.c ****
236:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
237:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
238:stm32lib/src/stm32f10x_rcc.c ****
239:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CR;
130 .loc 1 239 0
131 0078 034A ldr r2, .L16
132 007a 1368 ldr r3, [r2, #0]
133 .LVL2:
240:stm32lib/src/stm32f10x_rcc.c ****
241:stm32lib/src/stm32f10x_rcc.c **** /* Clear HSITRIM[4:0] bits */
242:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CR_HSITRIM_Mask;
134 .loc 1 242 0
135 007c 23F0F803 bic r3, r3, #248
136 .LVL3:
243:stm32lib/src/stm32f10x_rcc.c ****
244:stm32lib/src/stm32f10x_rcc.c **** /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
245:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= (u32)HSICalibrationValue << 3;
137 .loc 1 245 0
138 0080 43EAC003 orr r3, r3, r0, lsl #3
139 .LVL4:
246:stm32lib/src/stm32f10x_rcc.c ****
247:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
248:stm32lib/src/stm32f10x_rcc.c **** RCC->CR = tmpreg;
140 .loc 1 248 0
141 0084 1360 str r3, [r2, #0]
249:stm32lib/src/stm32f10x_rcc.c **** }
142 .loc 1 249 0
143 0086 7047 bx lr
144 .L17:
145 .align 2
146 .L16:
147 0088 00100240 .word 1073876992
148 .LFE26:
150 .align 2
151 .global RCC_HSICmd
152 .thumb
153 .thumb_func
155 RCC_HSICmd:
156 .LFB27:
250:stm32lib/src/stm32f10x_rcc.c ****
251:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
252:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_HSICmd
253:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the Internal High Speed oscillator (HSI).
254:stm32lib/src/stm32f10x_rcc.c **** * HSI can not be stopped if it is used directly or through the
255:stm32lib/src/stm32f10x_rcc.c **** * PLL as system clock.
256:stm32lib/src/stm32f10x_rcc.c **** * Input : - NewState: new state of the HSI.
257:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
258:stm32lib/src/stm32f10x_rcc.c **** * Output : None
259:stm32lib/src/stm32f10x_rcc.c **** * Return : None
260:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
261:stm32lib/src/stm32f10x_rcc.c **** void RCC_HSICmd(FunctionalState NewState)
262:stm32lib/src/stm32f10x_rcc.c **** {
157 .loc 1 262 0
158 @ args = 0, pretend = 0, frame = 0
159 @ frame_needed = 0, uses_anonymous_args = 0
160 @ link register save eliminated.
161 .LVL5:
263:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
264:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
265:stm32lib/src/stm32f10x_rcc.c ****
266:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) CR_HSION_BB = (u32)NewState;
162 .loc 1 266 0
163 008c 014B ldr r3, .L20
164 008e 1860 str r0, [r3, #0]
267:stm32lib/src/stm32f10x_rcc.c **** }
165 .loc 1 267 0
166 0090 7047 bx lr
167 .L21:
168 0092 00BF .align 2
169 .L20:
170 0094 00004242 .word 1111621632
171 .LFE27:
173 .align 2
174 .global RCC_PLLConfig
175 .thumb
176 .thumb_func
178 RCC_PLLConfig:
179 .LFB28:
268:stm32lib/src/stm32f10x_rcc.c ****
269:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
270:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_PLLConfig
271:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the PLL clock source and multiplication factor.
272:stm32lib/src/stm32f10x_rcc.c **** * This function must be used only when the PLL is disabled.
273:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_PLLSource: specifies the PLL entry clock source.
274:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
275:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
276:stm32lib/src/stm32f10x_rcc.c **** * by 2 selected as PLL clock entry
277:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
278:stm32lib/src/stm32f10x_rcc.c **** * as PLL clock entry
279:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
280:stm32lib/src/stm32f10x_rcc.c **** * by 2 selected as PLL clock entry
281:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PLLMul: specifies the PLL multiplication factor.
282:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be RCC_PLLMul_x where x:[2,16]
283:stm32lib/src/stm32f10x_rcc.c **** * Output : None
284:stm32lib/src/stm32f10x_rcc.c **** * Return : None
285:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
286:stm32lib/src/stm32f10x_rcc.c **** void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
287:stm32lib/src/stm32f10x_rcc.c **** {
180 .loc 1 287 0
181 @ args = 0, pretend = 0, frame = 0
182 @ frame_needed = 0, uses_anonymous_args = 0
183 @ link register save eliminated.
184 .LVL6:
288:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
289:stm32lib/src/stm32f10x_rcc.c ****
290:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
291:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
292:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
293:stm32lib/src/stm32f10x_rcc.c ****
294:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR;
185 .loc 1 294 0
186 0098 034B ldr r3, .L24
187 009a 5A68 ldr r2, [r3, #4]
188 .LVL7:
295:stm32lib/src/stm32f10x_rcc.c ****
296:stm32lib/src/stm32f10x_rcc.c **** /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
297:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CFGR_PLL_Mask;
298:stm32lib/src/stm32f10x_rcc.c ****
299:stm32lib/src/stm32f10x_rcc.c **** /* Set the PLL configuration bits */
300:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= RCC_PLLSource | RCC_PLLMul;
189 .loc 1 300 0
190 009c 22F47C12 bic r2, r2, #4128768
191 .LVL8:
192 00a0 1043 orrs r0, r0, r2
193 .LVL9:
194 00a2 0843 orrs r0, r0, r1
195 .LVL10:
301:stm32lib/src/stm32f10x_rcc.c ****
302:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
303:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg;
196 .loc 1 303 0
197 00a4 5860 str r0, [r3, #4]
304:stm32lib/src/stm32f10x_rcc.c **** }
198 .loc 1 304 0
199 00a6 7047 bx lr
200 .L25:
201 .align 2
202 .L24:
203 00a8 00100240 .word 1073876992
204 .LFE28:
206 .align 2
207 .global RCC_PLLCmd
208 .thumb
209 .thumb_func
211 RCC_PLLCmd:
212 .LFB29:
305:stm32lib/src/stm32f10x_rcc.c ****
306:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
307:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_PLLCmd
308:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the PLL.
309:stm32lib/src/stm32f10x_rcc.c **** * The PLL can not be disabled if it is used as system clock.
310:stm32lib/src/stm32f10x_rcc.c **** * Input : - NewState: new state of the PLL.
311:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
312:stm32lib/src/stm32f10x_rcc.c **** * Output : None
313:stm32lib/src/stm32f10x_rcc.c **** * Return : None
314:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
315:stm32lib/src/stm32f10x_rcc.c **** void RCC_PLLCmd(FunctionalState NewState)
316:stm32lib/src/stm32f10x_rcc.c **** {
213 .loc 1 316 0
214 @ args = 0, pretend = 0, frame = 0
215 @ frame_needed = 0, uses_anonymous_args = 0
216 @ link register save eliminated.
217 .LVL11:
317:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
318:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
319:stm32lib/src/stm32f10x_rcc.c ****
320:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) CR_PLLON_BB = (u32)NewState;
218 .loc 1 320 0
219 00ac 014B ldr r3, .L28
220 00ae 1860 str r0, [r3, #0]
321:stm32lib/src/stm32f10x_rcc.c **** }
221 .loc 1 321 0
222 00b0 7047 bx lr
223 .L29:
224 00b2 00BF .align 2
225 .L28:
226 00b4 60004242 .word 1111621728
227 .LFE29:
229 .align 2
230 .global RCC_SYSCLKConfig
231 .thumb
232 .thumb_func
234 RCC_SYSCLKConfig:
235 .LFB30:
322:stm32lib/src/stm32f10x_rcc.c ****
323:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
324:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_SYSCLKConfig
325:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the system clock (SYSCLK).
326:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_SYSCLKSource: specifies the clock source used as system
327:stm32lib/src/stm32f10x_rcc.c **** * clock. This parameter can be one of the following values:
328:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLKSource_HSI: HSI selected as system clock
329:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLKSource_HSE: HSE selected as system clock
330:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
331:stm32lib/src/stm32f10x_rcc.c **** * Output : None
332:stm32lib/src/stm32f10x_rcc.c **** * Return : None
333:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
334:stm32lib/src/stm32f10x_rcc.c **** void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
335:stm32lib/src/stm32f10x_rcc.c **** {
236 .loc 1 335 0
237 @ args = 0, pretend = 0, frame = 0
238 @ frame_needed = 0, uses_anonymous_args = 0
239 @ link register save eliminated.
240 .LVL12:
336:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
337:stm32lib/src/stm32f10x_rcc.c ****
338:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
339:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
340:stm32lib/src/stm32f10x_rcc.c ****
341:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR;
241 .loc 1 341 0
242 00b8 034B ldr r3, .L32
243 00ba 5A68 ldr r2, [r3, #4]
244 .LVL13:
342:stm32lib/src/stm32f10x_rcc.c ****
343:stm32lib/src/stm32f10x_rcc.c **** /* Clear SW[1:0] bits */
344:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CFGR_SW_Mask;
245 .loc 1 344 0
246 00bc 22F00302 bic r2, r2, #3
247 .LVL14:
345:stm32lib/src/stm32f10x_rcc.c ****
346:stm32lib/src/stm32f10x_rcc.c **** /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
347:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= RCC_SYSCLKSource;
248 .loc 1 347 0
249 00c0 1043 orrs r0, r0, r2
250 .LVL15:
348:stm32lib/src/stm32f10x_rcc.c ****
349:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
350:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg;
251 .loc 1 350 0
252 00c2 5860 str r0, [r3, #4]
351:stm32lib/src/stm32f10x_rcc.c **** }
253 .loc 1 351 0
254 00c4 7047 bx lr
255 .L33:
256 00c6 00BF .align 2
257 .L32:
258 00c8 00100240 .word 1073876992
259 .LFE30:
261 .align 2
262 .global RCC_GetSYSCLKSource
263 .thumb
264 .thumb_func
266 RCC_GetSYSCLKSource:
267 .LFB31:
352:stm32lib/src/stm32f10x_rcc.c ****
353:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
354:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_GetSYSCLKSource
355:stm32lib/src/stm32f10x_rcc.c **** * Description : Returns the clock source used as system clock.
356:stm32lib/src/stm32f10x_rcc.c **** * Input : None
357:stm32lib/src/stm32f10x_rcc.c **** * Output : None
358:stm32lib/src/stm32f10x_rcc.c **** * Return : The clock source used as system clock. The returned value can
359:stm32lib/src/stm32f10x_rcc.c **** * be one of the following:
360:stm32lib/src/stm32f10x_rcc.c **** * - 0x00: HSI used as system clock
361:stm32lib/src/stm32f10x_rcc.c **** * - 0x04: HSE used as system clock
362:stm32lib/src/stm32f10x_rcc.c **** * - 0x08: PLL used as system clock
363:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
364:stm32lib/src/stm32f10x_rcc.c **** u8 RCC_GetSYSCLKSource(void)
365:stm32lib/src/stm32f10x_rcc.c **** {
268 .loc 1 365 0
269 @ args = 0, pretend = 0, frame = 0
270 @ frame_needed = 0, uses_anonymous_args = 0
271 @ link register save eliminated.
366:stm32lib/src/stm32f10x_rcc.c **** return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
272 .loc 1 366 0
273 00cc 024B ldr r3, .L36
274 00ce 5868 ldr r0, [r3, #4]
367:stm32lib/src/stm32f10x_rcc.c **** }
275 .loc 1 367 0
276 00d0 00F00C00 and r0, r0, #12
277 00d4 7047 bx lr
278 .L37:
279 00d6 00BF .align 2
280 .L36:
281 00d8 00100240 .word 1073876992
282 .LFE31:
284 .align 2
285 .global RCC_HCLKConfig
286 .thumb
287 .thumb_func
289 RCC_HCLKConfig:
290 .LFB32:
368:stm32lib/src/stm32f10x_rcc.c ****
369:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
370:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_HCLKConfig
371:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the AHB clock (HCLK).
372:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is
373:stm32lib/src/stm32f10x_rcc.c **** * derived from the system clock (SYSCLK).
374:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
375:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
376:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
377:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
378:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
379:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
380:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
381:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
382:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
383:stm32lib/src/stm32f10x_rcc.c **** * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
384:stm32lib/src/stm32f10x_rcc.c **** * Output : None
385:stm32lib/src/stm32f10x_rcc.c **** * Return : None
386:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
387:stm32lib/src/stm32f10x_rcc.c **** void RCC_HCLKConfig(u32 RCC_SYSCLK)
388:stm32lib/src/stm32f10x_rcc.c **** {
291 .loc 1 388 0
292 @ args = 0, pretend = 0, frame = 0
293 @ frame_needed = 0, uses_anonymous_args = 0
294 @ link register save eliminated.
295 .LVL16:
389:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
390:stm32lib/src/stm32f10x_rcc.c ****
391:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
392:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_HCLK(RCC_SYSCLK));
393:stm32lib/src/stm32f10x_rcc.c ****
394:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR;
296 .loc 1 394 0
297 00dc 034B ldr r3, .L40
298 00de 5A68 ldr r2, [r3, #4]
299 .LVL17:
395:stm32lib/src/stm32f10x_rcc.c ****
396:stm32lib/src/stm32f10x_rcc.c **** /* Clear HPRE[3:0] bits */
397:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CFGR_HPRE_Reset_Mask;
300 .loc 1 397 0
301 00e0 22F0F002 bic r2, r2, #240
302 .LVL18:
398:stm32lib/src/stm32f10x_rcc.c ****
399:stm32lib/src/stm32f10x_rcc.c **** /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
400:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= RCC_SYSCLK;
303 .loc 1 400 0
304 00e4 1043 orrs r0, r0, r2
305 .LVL19:
401:stm32lib/src/stm32f10x_rcc.c ****
402:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
403:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg;
306 .loc 1 403 0
307 00e6 5860 str r0, [r3, #4]
404:stm32lib/src/stm32f10x_rcc.c **** }
308 .loc 1 404 0
309 00e8 7047 bx lr
310 .L41:
311 00ea 00BF .align 2
312 .L40:
313 00ec 00100240 .word 1073876992
314 .LFE32:
316 .align 2
317 .global RCC_PCLK1Config
318 .thumb
319 .thumb_func
321 RCC_PCLK1Config:
322 .LFB33:
405:stm32lib/src/stm32f10x_rcc.c ****
406:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
407:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_PCLK1Config
408:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the Low Speed APB clock (PCLK1).
409:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_HCLK: defines the APB1 clock divider. This clock is
410:stm32lib/src/stm32f10x_rcc.c **** * derived from the AHB clock (HCLK).
411:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
412:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div1: APB1 clock = HCLK
413:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div2: APB1 clock = HCLK/2
414:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div4: APB1 clock = HCLK/4
415:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div8: APB1 clock = HCLK/8
416:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div16: APB1 clock = HCLK/16
417:stm32lib/src/stm32f10x_rcc.c **** * Output : None
418:stm32lib/src/stm32f10x_rcc.c **** * Return : None
419:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
420:stm32lib/src/stm32f10x_rcc.c **** void RCC_PCLK1Config(u32 RCC_HCLK)
421:stm32lib/src/stm32f10x_rcc.c **** {
323 .loc 1 421 0
324 @ args = 0, pretend = 0, frame = 0
325 @ frame_needed = 0, uses_anonymous_args = 0
326 @ link register save eliminated.
327 .LVL20:
422:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
423:stm32lib/src/stm32f10x_rcc.c ****
424:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
425:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PCLK(RCC_HCLK));
426:stm32lib/src/stm32f10x_rcc.c ****
427:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR;
328 .loc 1 427 0
329 00f0 034B ldr r3, .L44
330 00f2 5A68 ldr r2, [r3, #4]
331 .LVL21:
428:stm32lib/src/stm32f10x_rcc.c ****
429:stm32lib/src/stm32f10x_rcc.c **** /* Clear PPRE1[2:0] bits */
430:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CFGR_PPRE1_Reset_Mask;
332 .loc 1 430 0
333 00f4 22F4E062 bic r2, r2, #1792
334 .LVL22:
431:stm32lib/src/stm32f10x_rcc.c ****
432:stm32lib/src/stm32f10x_rcc.c **** /* Set PPRE1[2:0] bits according to RCC_HCLK value */
433:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= RCC_HCLK;
335 .loc 1 433 0
336 00f8 1043 orrs r0, r0, r2
337 .LVL23:
434:stm32lib/src/stm32f10x_rcc.c ****
435:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
436:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg;
338 .loc 1 436 0
339 00fa 5860 str r0, [r3, #4]
437:stm32lib/src/stm32f10x_rcc.c **** }
340 .loc 1 437 0
341 00fc 7047 bx lr
342 .L45:
343 00fe 00BF .align 2
344 .L44:
345 0100 00100240 .word 1073876992
346 .LFE33:
348 .align 2
349 .global RCC_PCLK2Config
350 .thumb
351 .thumb_func
353 RCC_PCLK2Config:
354 .LFB34:
438:stm32lib/src/stm32f10x_rcc.c ****
439:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
440:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_PCLK2Config
441:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the High Speed APB clock (PCLK2).
442:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_HCLK: defines the APB2 clock divider. This clock is
443:stm32lib/src/stm32f10x_rcc.c **** * derived from the AHB clock (HCLK).
444:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
445:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div1: APB2 clock = HCLK
446:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div2: APB2 clock = HCLK/2
447:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div4: APB2 clock = HCLK/4
448:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div8: APB2 clock = HCLK/8
449:stm32lib/src/stm32f10x_rcc.c **** * - RCC_HCLK_Div16: APB2 clock = HCLK/16
450:stm32lib/src/stm32f10x_rcc.c **** * Output : None
451:stm32lib/src/stm32f10x_rcc.c **** * Return : None
452:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
453:stm32lib/src/stm32f10x_rcc.c **** void RCC_PCLK2Config(u32 RCC_HCLK)
454:stm32lib/src/stm32f10x_rcc.c **** {
355 .loc 1 454 0
356 @ args = 0, pretend = 0, frame = 0
357 @ frame_needed = 0, uses_anonymous_args = 0
358 @ link register save eliminated.
359 .LVL24:
455:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
456:stm32lib/src/stm32f10x_rcc.c ****
457:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
458:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_PCLK(RCC_HCLK));
459:stm32lib/src/stm32f10x_rcc.c ****
460:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR;
360 .loc 1 460 0
361 0104 034A ldr r2, .L48
362 0106 5368 ldr r3, [r2, #4]
363 .LVL25:
461:stm32lib/src/stm32f10x_rcc.c ****
462:stm32lib/src/stm32f10x_rcc.c **** /* Clear PPRE2[2:0] bits */
463:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CFGR_PPRE2_Reset_Mask;
364 .loc 1 463 0
365 0108 23F46053 bic r3, r3, #14336
366 .LVL26:
464:stm32lib/src/stm32f10x_rcc.c ****
465:stm32lib/src/stm32f10x_rcc.c **** /* Set PPRE2[2:0] bits according to RCC_HCLK value */
466:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= RCC_HCLK << 3;
367 .loc 1 466 0
368 010c 43EAC003 orr r3, r3, r0, lsl #3
369 .LVL27:
467:stm32lib/src/stm32f10x_rcc.c ****
468:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
469:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg;
370 .loc 1 469 0
371 0110 5360 str r3, [r2, #4]
470:stm32lib/src/stm32f10x_rcc.c **** }
372 .loc 1 470 0
373 0112 7047 bx lr
374 .L49:
375 .align 2
376 .L48:
377 0114 00100240 .word 1073876992
378 .LFE34:
380 .align 2
381 .global RCC_ITConfig
382 .thumb
383 .thumb_func
385 RCC_ITConfig:
386 .LFB35:
471:stm32lib/src/stm32f10x_rcc.c ****
472:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
473:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_ITConfig
474:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the specified RCC interrupts.
475:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
476:stm32lib/src/stm32f10x_rcc.c **** * or disabled.
477:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
478:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_LSIRDY: LSI ready interrupt
479:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_LSERDY: LSE ready interrupt
480:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_HSIRDY: HSI ready interrupt
481:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_HSERDY: HSE ready interrupt
482:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_PLLRDY: PLL ready interrupt
483:stm32lib/src/stm32f10x_rcc.c **** * - NewState: new state of the specified RCC interrupts.
484:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
485:stm32lib/src/stm32f10x_rcc.c **** * Output : None
486:stm32lib/src/stm32f10x_rcc.c **** * Return : None
487:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
488:stm32lib/src/stm32f10x_rcc.c **** void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
489:stm32lib/src/stm32f10x_rcc.c **** {
387 .loc 1 489 0
388 @ args = 0, pretend = 0, frame = 0
389 @ frame_needed = 0, uses_anonymous_args = 0
390 @ link register save eliminated.
391 .LVL28:
490:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
491:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_IT(RCC_IT));
492:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
493:stm32lib/src/stm32f10x_rcc.c ****
494:stm32lib/src/stm32f10x_rcc.c **** if (NewState != DISABLE)
392 .loc 1 494 0
393 0118 21B1 cbz r1, .L51
495:stm32lib/src/stm32f10x_rcc.c **** {
496:stm32lib/src/stm32f10x_rcc.c **** /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
497:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
394 .loc 1 497 0
395 011a 054A ldr r2, .L55
396 011c 1378 ldrb r3, [r2, #0] @ zero_extendqisi2
397 011e 40EA0303 orr r3, r0, r3
398 0122 03E0 b .L54
399 .L51:
498:stm32lib/src/stm32f10x_rcc.c **** }
499:stm32lib/src/stm32f10x_rcc.c **** else
500:stm32lib/src/stm32f10x_rcc.c **** {
501:stm32lib/src/stm32f10x_rcc.c **** /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
502:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
400 .loc 1 502 0
401 0124 024A ldr r2, .L55
402 0126 1378 ldrb r3, [r2, #0] @ zero_extendqisi2
403 0128 23EA0003 bic r3, r3, r0
404 .L54:
405 012c 1370 strb r3, [r2, #0]
503:stm32lib/src/stm32f10x_rcc.c **** }
504:stm32lib/src/stm32f10x_rcc.c **** }
406 .loc 1 504 0
407 012e 7047 bx lr
408 .L56:
409 .align 2
410 .L55:
411 0130 09100240 .word 1073877001
412 .LFE35:
414 .align 2
415 .global RCC_USBCLKConfig
416 .thumb
417 .thumb_func
419 RCC_USBCLKConfig:
420 .LFB36:
505:stm32lib/src/stm32f10x_rcc.c ****
506:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
507:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_USBCLKConfig
508:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the USB clock (USBCLK).
509:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
510:stm32lib/src/stm32f10x_rcc.c **** * is derived from the PLL output.
511:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
512:stm32lib/src/stm32f10x_rcc.c **** * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
513:stm32lib/src/stm32f10x_rcc.c **** * selected as USB clock source
514:stm32lib/src/stm32f10x_rcc.c **** * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
515:stm32lib/src/stm32f10x_rcc.c **** * clock source
516:stm32lib/src/stm32f10x_rcc.c **** * Output : None
517:stm32lib/src/stm32f10x_rcc.c **** * Return : None
518:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
519:stm32lib/src/stm32f10x_rcc.c **** void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
520:stm32lib/src/stm32f10x_rcc.c **** {
421 .loc 1 520 0
422 @ args = 0, pretend = 0, frame = 0
423 @ frame_needed = 0, uses_anonymous_args = 0
424 @ link register save eliminated.
425 .LVL29:
521:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
522:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
523:stm32lib/src/stm32f10x_rcc.c ****
524:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
426 .loc 1 524 0
427 0134 014B ldr r3, .L59
428 0136 1860 str r0, [r3, #0]
525:stm32lib/src/stm32f10x_rcc.c **** }
429 .loc 1 525 0
430 0138 7047 bx lr
431 .L60:
432 013a 00BF .align 2
433 .L59:
434 013c D8004242 .word 1111621848
435 .LFE36:
437 .align 2
438 .global RCC_ADCCLKConfig
439 .thumb
440 .thumb_func
442 RCC_ADCCLKConfig:
443 .LFB37:
526:stm32lib/src/stm32f10x_rcc.c ****
527:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
528:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_ADCCLKConfig
529:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the ADC clock (ADCCLK).
530:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_PCLK2: defines the ADC clock divider. This clock is
531:stm32lib/src/stm32f10x_rcc.c **** * derived from the APB2 clock (PCLK2).
532:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
533:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
534:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
535:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
536:stm32lib/src/stm32f10x_rcc.c **** * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
537:stm32lib/src/stm32f10x_rcc.c **** * Output : None
538:stm32lib/src/stm32f10x_rcc.c **** * Return : None
539:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
540:stm32lib/src/stm32f10x_rcc.c **** void RCC_ADCCLKConfig(u32 RCC_PCLK2)
541:stm32lib/src/stm32f10x_rcc.c **** {
444 .loc 1 541 0
445 @ args = 0, pretend = 0, frame = 0
446 @ frame_needed = 0, uses_anonymous_args = 0
447 @ link register save eliminated.
448 .LVL30:
542:stm32lib/src/stm32f10x_rcc.c **** u32 tmpreg = 0;
543:stm32lib/src/stm32f10x_rcc.c ****
544:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
545:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
546:stm32lib/src/stm32f10x_rcc.c ****
547:stm32lib/src/stm32f10x_rcc.c **** tmpreg = RCC->CFGR;
449 .loc 1 547 0
450 0140 034B ldr r3, .L63
451 0142 5A68 ldr r2, [r3, #4]
452 .LVL31:
548:stm32lib/src/stm32f10x_rcc.c ****
549:stm32lib/src/stm32f10x_rcc.c **** /* Clear ADCPRE[1:0] bits */
550:stm32lib/src/stm32f10x_rcc.c **** tmpreg &= CFGR_ADCPRE_Reset_Mask;
453 .loc 1 550 0
454 0144 22F44042 bic r2, r2, #49152
455 .LVL32:
551:stm32lib/src/stm32f10x_rcc.c ****
552:stm32lib/src/stm32f10x_rcc.c **** /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
553:stm32lib/src/stm32f10x_rcc.c **** tmpreg |= RCC_PCLK2;
456 .loc 1 553 0
457 0148 1043 orrs r0, r0, r2
458 .LVL33:
554:stm32lib/src/stm32f10x_rcc.c ****
555:stm32lib/src/stm32f10x_rcc.c **** /* Store the new value */
556:stm32lib/src/stm32f10x_rcc.c **** RCC->CFGR = tmpreg;
459 .loc 1 556 0
460 014a 5860 str r0, [r3, #4]
557:stm32lib/src/stm32f10x_rcc.c **** }
461 .loc 1 557 0
462 014c 7047 bx lr
463 .L64:
464 014e 00BF .align 2
465 .L63:
466 0150 00100240 .word 1073876992
467 .LFE37:
469 .align 2
470 .global RCC_LSEConfig
471 .thumb
472 .thumb_func
474 RCC_LSEConfig:
475 .LFB38:
558:stm32lib/src/stm32f10x_rcc.c ****
559:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
560:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_LSEConfig
561:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the External Low Speed oscillator (LSE).
562:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_LSE: specifies the new state of the LSE.
563:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
564:stm32lib/src/stm32f10x_rcc.c **** * - RCC_LSE_OFF: LSE oscillator OFF
565:stm32lib/src/stm32f10x_rcc.c **** * - RCC_LSE_ON: LSE oscillator ON
566:stm32lib/src/stm32f10x_rcc.c **** * - RCC_LSE_Bypass: LSE oscillator bypassed with external
567:stm32lib/src/stm32f10x_rcc.c **** * clock
568:stm32lib/src/stm32f10x_rcc.c **** * Output : None
569:stm32lib/src/stm32f10x_rcc.c **** * Return : None
570:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
571:stm32lib/src/stm32f10x_rcc.c **** void RCC_LSEConfig(u8 RCC_LSE)
572:stm32lib/src/stm32f10x_rcc.c **** {
476 .loc 1 572 0
477 @ args = 0, pretend = 0, frame = 0
478 @ frame_needed = 0, uses_anonymous_args = 0
479 @ link register save eliminated.
480 .LVL34:
573:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
574:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_LSE(RCC_LSE));
575:stm32lib/src/stm32f10x_rcc.c ****
576:stm32lib/src/stm32f10x_rcc.c **** /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
577:stm32lib/src/stm32f10x_rcc.c **** /* Reset LSEON bit */
578:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
481 .loc 1 578 0
482 0154 064A ldr r2, .L71
483 0156 0023 movs r3, #0
579:stm32lib/src/stm32f10x_rcc.c ****
580:stm32lib/src/stm32f10x_rcc.c **** /* Reset LSEBYP bit */
581:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
582:stm32lib/src/stm32f10x_rcc.c ****
583:stm32lib/src/stm32f10x_rcc.c **** /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
584:stm32lib/src/stm32f10x_rcc.c **** switch(RCC_LSE)
484 .loc 1 584 0
485 0158 0128 cmp r0, #1
486 .loc 1 578 0
487 015a 1370 strb r3, [r2, #0]
488 .loc 1 581 0
489 015c 1370 strb r3, [r2, #0]
490 .loc 1 584 0
491 015e 02D0 beq .L67
492 0160 0428 cmp r0, #4
493 0162 04D1 bne .L69
494 0164 01E0 b .L70
495 .L67:
585:stm32lib/src/stm32f10x_rcc.c **** {
586:stm32lib/src/stm32f10x_rcc.c **** case RCC_LSE_ON:
587:stm32lib/src/stm32f10x_rcc.c **** /* Set LSEON bit */
588:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
496 .loc 1 588 0
497 0166 1070 strb r0, [r2, #0]
498 0168 01E0 b .L69
499 .L70:
589:stm32lib/src/stm32f10x_rcc.c **** break;
590:stm32lib/src/stm32f10x_rcc.c ****
591:stm32lib/src/stm32f10x_rcc.c **** case RCC_LSE_Bypass:
592:stm32lib/src/stm32f10x_rcc.c **** /* Set LSEBYP and LSEON bits */
593:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
500 .loc 1 593 0
501 016a 0523 movs r3, #5
502 016c 1370 strb r3, [r2, #0]
503 .L69:
594:stm32lib/src/stm32f10x_rcc.c **** break;
595:stm32lib/src/stm32f10x_rcc.c ****
596:stm32lib/src/stm32f10x_rcc.c **** default:
597:stm32lib/src/stm32f10x_rcc.c **** break;
598:stm32lib/src/stm32f10x_rcc.c **** }
599:stm32lib/src/stm32f10x_rcc.c **** }
504 .loc 1 599 0
505 016e 7047 bx lr
506 .L72:
507 .align 2
508 .L71:
509 0170 20100240 .word 1073877024
510 .LFE38:
512 .align 2
513 .global RCC_LSICmd
514 .thumb
515 .thumb_func
517 RCC_LSICmd:
518 .LFB39:
600:stm32lib/src/stm32f10x_rcc.c ****
601:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
602:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_LSICmd
603:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the Internal Low Speed oscillator (LSI).
604:stm32lib/src/stm32f10x_rcc.c **** * LSI can not be disabled if the IWDG is running.
605:stm32lib/src/stm32f10x_rcc.c **** * Input : - NewState: new state of the LSI.
606:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
607:stm32lib/src/stm32f10x_rcc.c **** * Output : None
608:stm32lib/src/stm32f10x_rcc.c **** * Return : None
609:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
610:stm32lib/src/stm32f10x_rcc.c **** void RCC_LSICmd(FunctionalState NewState)
611:stm32lib/src/stm32f10x_rcc.c **** {
519 .loc 1 611 0
520 @ args = 0, pretend = 0, frame = 0
521 @ frame_needed = 0, uses_anonymous_args = 0
522 @ link register save eliminated.
523 .LVL35:
612:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
613:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
614:stm32lib/src/stm32f10x_rcc.c ****
615:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) CSR_LSION_BB = (u32)NewState;
524 .loc 1 615 0
525 0174 014B ldr r3, .L75
526 0176 1860 str r0, [r3, #0]
616:stm32lib/src/stm32f10x_rcc.c **** }
527 .loc 1 616 0
528 0178 7047 bx lr
529 .L76:
530 017a 00BF .align 2
531 .L75:
532 017c 80044242 .word 1111622784
533 .LFE39:
535 .align 2
536 .global RCC_RTCCLKConfig
537 .thumb
538 .thumb_func
540 RCC_RTCCLKConfig:
541 .LFB40:
617:stm32lib/src/stm32f10x_rcc.c ****
618:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
619:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_RTCCLKConfig
620:stm32lib/src/stm32f10x_rcc.c **** * Description : Configures the RTC clock (RTCCLK).
621:stm32lib/src/stm32f10x_rcc.c **** * Once the RTC clock is selected it can’t be changed unless the
622:stm32lib/src/stm32f10x_rcc.c **** * Backup domain is reset.
623:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_RTCCLKSource: specifies the RTC clock source.
624:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
625:stm32lib/src/stm32f10x_rcc.c **** * - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
626:stm32lib/src/stm32f10x_rcc.c **** * - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
627:stm32lib/src/stm32f10x_rcc.c **** * - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
628:stm32lib/src/stm32f10x_rcc.c **** * selected as RTC clock
629:stm32lib/src/stm32f10x_rcc.c **** * Output : None
630:stm32lib/src/stm32f10x_rcc.c **** * Return : None
631:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
632:stm32lib/src/stm32f10x_rcc.c **** void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
633:stm32lib/src/stm32f10x_rcc.c **** {
542 .loc 1 633 0
543 @ args = 0, pretend = 0, frame = 0
544 @ frame_needed = 0, uses_anonymous_args = 0
545 @ link register save eliminated.
546 .LVL36:
634:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
635:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
636:stm32lib/src/stm32f10x_rcc.c ****
637:stm32lib/src/stm32f10x_rcc.c **** /* Select the RTC clock source */
638:stm32lib/src/stm32f10x_rcc.c **** RCC->BDCR |= RCC_RTCCLKSource;
547 .loc 1 638 0
548 0180 024B ldr r3, .L79
549 0182 1A6A ldr r2, [r3, #32]
550 0184 1043 orrs r0, r0, r2
551 .LVL37:
552 0186 1862 str r0, [r3, #32]
639:stm32lib/src/stm32f10x_rcc.c **** }
553 .loc 1 639 0
554 0188 7047 bx lr
555 .L80:
556 018a 00BF .align 2
557 .L79:
558 018c 00100240 .word 1073876992
559 .LFE40:
561 .align 2
562 .global RCC_RTCCLKCmd
563 .thumb
564 .thumb_func
566 RCC_RTCCLKCmd:
567 .LFB41:
640:stm32lib/src/stm32f10x_rcc.c ****
641:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
642:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_RTCCLKCmd
643:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the RTC clock.
644:stm32lib/src/stm32f10x_rcc.c **** * This function must be used only after the RTC clock was
645:stm32lib/src/stm32f10x_rcc.c **** * selected using the RCC_RTCCLKConfig function.
646:stm32lib/src/stm32f10x_rcc.c **** * Input : - NewState: new state of the RTC clock.
647:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
648:stm32lib/src/stm32f10x_rcc.c **** * Output : None
649:stm32lib/src/stm32f10x_rcc.c **** * Return : None
650:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
651:stm32lib/src/stm32f10x_rcc.c **** void RCC_RTCCLKCmd(FunctionalState NewState)
652:stm32lib/src/stm32f10x_rcc.c **** {
568 .loc 1 652 0
569 @ args = 0, pretend = 0, frame = 0
570 @ frame_needed = 0, uses_anonymous_args = 0
571 @ link register save eliminated.
572 .LVL38:
653:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
654:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
655:stm32lib/src/stm32f10x_rcc.c ****
656:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
573 .loc 1 656 0
574 0190 014B ldr r3, .L83
575 0192 1860 str r0, [r3, #0]
657:stm32lib/src/stm32f10x_rcc.c **** }
576 .loc 1 657 0
577 0194 7047 bx lr
578 .L84:
579 0196 00BF .align 2
580 .L83:
581 0198 3C044242 .word 1111622716
582 .LFE41:
584 .align 2
585 .global RCC_GetClocksFreq
586 .thumb
587 .thumb_func
589 RCC_GetClocksFreq:
590 .LFB42:
658:stm32lib/src/stm32f10x_rcc.c ****
659:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
660:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_GetClocksFreq
661:stm32lib/src/stm32f10x_rcc.c **** * Description : Returns the frequencies of different on chip clocks.
662:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
663:stm32lib/src/stm32f10x_rcc.c **** * will hold the clocks frequencies.
664:stm32lib/src/stm32f10x_rcc.c **** * Output : None
665:stm32lib/src/stm32f10x_rcc.c **** * Return : None
666:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
667:stm32lib/src/stm32f10x_rcc.c **** void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
668:stm32lib/src/stm32f10x_rcc.c **** {
591 .loc 1 668 0
592 @ args = 0, pretend = 0, frame = 0
593 @ frame_needed = 0, uses_anonymous_args = 0
594 .LVL39:
669:stm32lib/src/stm32f10x_rcc.c **** u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
670:stm32lib/src/stm32f10x_rcc.c ****
671:stm32lib/src/stm32f10x_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/
672:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_SWS_Mask;
595 .loc 1 672 0
596 019c 1D49 ldr r1, .L98
597 .loc 1 668 0
598 019e 10B5 push {r4, lr}
599 .LCFI0:
600 .loc 1 672 0
601 01a0 4B68 ldr r3, [r1, #4]
602 .loc 1 668 0
603 01a2 0446 mov r4, r0
673:stm32lib/src/stm32f10x_rcc.c ****
674:stm32lib/src/stm32f10x_rcc.c **** switch (tmp)
604 .loc 1 674 0
605 01a4 03F00C03 and r3, r3, #12
606 01a8 042B cmp r3, #4
607 01aa 12D0 beq .L94
608 .LVL40:
609 01ac 082B cmp r3, #8
610 01ae 10D1 bne .L94
611 .L89:
675:stm32lib/src/stm32f10x_rcc.c **** {
676:stm32lib/src/stm32f10x_rcc.c **** case 0x00: /* HSI used as system clock */
677:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSI_Value;
678:stm32lib/src/stm32f10x_rcc.c **** break;
679:stm32lib/src/stm32f10x_rcc.c ****
680:stm32lib/src/stm32f10x_rcc.c **** case 0x04: /* HSE used as system clock */
681:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSE_Value;
682:stm32lib/src/stm32f10x_rcc.c **** break;
683:stm32lib/src/stm32f10x_rcc.c ****
684:stm32lib/src/stm32f10x_rcc.c **** case 0x08: /* PLL used as system clock */
685:stm32lib/src/stm32f10x_rcc.c **** /* Get PLL clock source and multiplication factor ----------------------*/
686:stm32lib/src/stm32f10x_rcc.c **** pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
612 .loc 1 686 0
613 01b0 4B68 ldr r3, [r1, #4]
687:stm32lib/src/stm32f10x_rcc.c **** pllmull = ( pllmull >> 18) + 2;
614 .loc 1 687 0
615 01b2 C3F38343 ubfx r3, r3, #18, #4
616 01b6 9A1C adds r2, r3, #2
617 .LVL41:
688:stm32lib/src/stm32f10x_rcc.c ****
689:stm32lib/src/stm32f10x_rcc.c **** pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
618 .loc 1 689 0
619 01b8 4B68 ldr r3, [r1, #4]
690:stm32lib/src/stm32f10x_rcc.c ****
691:stm32lib/src/stm32f10x_rcc.c **** if (pllsource == 0x00)
620 .loc 1 691 0
621 01ba 13F4803F tst r3, #65536
622 01be 03D0 beq .L97
623 .L91:
692:stm32lib/src/stm32f10x_rcc.c **** {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
693:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
694:stm32lib/src/stm32f10x_rcc.c **** }
695:stm32lib/src/stm32f10x_rcc.c **** else
696:stm32lib/src/stm32f10x_rcc.c **** {/* HSE selected as PLL clock entry */
697:stm32lib/src/stm32f10x_rcc.c ****
698:stm32lib/src/stm32f10x_rcc.c **** if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
624 .loc 1 698 0
625 01c0 4B68 ldr r3, [r1, #4]
626 01c2 13F4003F tst r3, #131072
627 01c6 01D0 beq .L92
628 .L97:
699:stm32lib/src/stm32f10x_rcc.c **** {/* HSE oscillator clock divided by 2 */
700:stm32lib/src/stm32f10x_rcc.c ****
701:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
629 .loc 1 701 0
630 01c8 134B ldr r3, .L98+4
631 01ca 00E0 b .L96
632 .L92:
702:stm32lib/src/stm32f10x_rcc.c **** }
703:stm32lib/src/stm32f10x_rcc.c **** else
704:stm32lib/src/stm32f10x_rcc.c **** {
705:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
633 .loc 1 705 0
634 01cc 134B ldr r3, .L98+8
635 .L96:
636 01ce 5343 muls r3, r2, r3
637 01d0 00E0 b .L95
638 .LVL42:
639 .L94:
706:stm32lib/src/stm32f10x_rcc.c **** }
707:stm32lib/src/stm32f10x_rcc.c **** }
708:stm32lib/src/stm32f10x_rcc.c **** break;
709:stm32lib/src/stm32f10x_rcc.c ****
710:stm32lib/src/stm32f10x_rcc.c **** default:
711:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->SYSCLK_Frequency = HSI_Value;
640 .loc 1 711 0
641 01d2 124B ldr r3, .L98+8
642 .LVL43:
643 .L95:
712:stm32lib/src/stm32f10x_rcc.c **** break;
713:stm32lib/src/stm32f10x_rcc.c **** }
714:stm32lib/src/stm32f10x_rcc.c ****
715:stm32lib/src/stm32f10x_rcc.c **** /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
716:stm32lib/src/stm32f10x_rcc.c **** /* Get HCLK prescaler */
717:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
644 .loc 1 717 0
645 01d4 0F48 ldr r0, .L98
646 .loc 1 711 0
647 01d6 2360 str r3, [r4, #0]
648 .loc 1 717 0
649 01d8 4368 ldr r3, [r0, #4]
718:stm32lib/src/stm32f10x_rcc.c **** tmp = tmp >> 4;
719:stm32lib/src/stm32f10x_rcc.c **** presc = APBAHBPrescTable[tmp];
720:stm32lib/src/stm32f10x_rcc.c ****
721:stm32lib/src/stm32f10x_rcc.c **** /* HCLK clock frequency */
722:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
650 .loc 1 722 0
651 01da 1149 ldr r1, .L98+12
652 01dc C3F30313 ubfx r3, r3, #4, #4
653 01e0 CB5C ldrb r3, [r1, r3] @ zero_extendqisi2
654 01e2 2268 ldr r2, [r4, #0]
655 .LVL44:
656 01e4 DA40 lsrs r2, r2, r3
657 01e6 6260 str r2, [r4, #4]
723:stm32lib/src/stm32f10x_rcc.c ****
724:stm32lib/src/stm32f10x_rcc.c **** /* Get PCLK1 prescaler */
725:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
658 .loc 1 725 0
659 01e8 4368 ldr r3, [r0, #4]
726:stm32lib/src/stm32f10x_rcc.c **** tmp = tmp >> 8;
727:stm32lib/src/stm32f10x_rcc.c **** presc = APBAHBPrescTable[tmp];
728:stm32lib/src/stm32f10x_rcc.c ****
729:stm32lib/src/stm32f10x_rcc.c **** /* PCLK1 clock frequency */
730:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
660 .loc 1 730 0
661 01ea C3F30223 ubfx r3, r3, #8, #3
662 01ee CB5C ldrb r3, [r1, r3] @ zero_extendqisi2
663 01f0 32FA03F3 lsrs r3, r2, r3
664 01f4 A360 str r3, [r4, #8]
731:stm32lib/src/stm32f10x_rcc.c ****
732:stm32lib/src/stm32f10x_rcc.c **** /* Get PCLK2 prescaler */
733:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
665 .loc 1 733 0
666 01f6 4368 ldr r3, [r0, #4]
734:stm32lib/src/stm32f10x_rcc.c **** tmp = tmp >> 11;
735:stm32lib/src/stm32f10x_rcc.c **** presc = APBAHBPrescTable[tmp];
736:stm32lib/src/stm32f10x_rcc.c ****
737:stm32lib/src/stm32f10x_rcc.c **** /* PCLK2 clock frequency */
738:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
667 .loc 1 738 0
668 01f8 C3F3C223 ubfx r3, r3, #11, #3
669 01fc CB5C ldrb r3, [r1, r3] @ zero_extendqisi2
670 01fe DA40 lsrs r2, r2, r3
671 0200 E260 str r2, [r4, #12]
739:stm32lib/src/stm32f10x_rcc.c ****
740:stm32lib/src/stm32f10x_rcc.c **** /* Get ADCCLK prescaler */
741:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
672 .loc 1 741 0
673 0202 4368 ldr r3, [r0, #4]
742:stm32lib/src/stm32f10x_rcc.c **** tmp = tmp >> 14;
743:stm32lib/src/stm32f10x_rcc.c **** presc = ADCPrescTable[tmp];
744:stm32lib/src/stm32f10x_rcc.c ****
745:stm32lib/src/stm32f10x_rcc.c **** /* ADCCLK clock frequency */
746:stm32lib/src/stm32f10x_rcc.c **** RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
674 .loc 1 746 0
675 0204 C3F38133 ubfx r3, r3, #14, #2
676 0208 C918 adds r1, r1, r3
677 020a 0B7C ldrb r3, [r1, #16] @ zero_extendqisi2
678 020c B2FBF3F2 udiv r2, r2, r3
679 0210 2261 str r2, [r4, #16]
747:stm32lib/src/stm32f10x_rcc.c **** }
680 .loc 1 747 0
681 0212 10BD pop {r4, pc}
682 .L99:
683 .align 2
684 .L98:
685 0214 00100240 .word 1073876992
686 0218 00093D00 .word 4000000
687 021c 00127A00 .word 8000000
688 0220 00000000 .word .LANCHOR0
689 .LFE42:
691 .align 2
692 .global RCC_AHBPeriphClockCmd
693 .thumb
694 .thumb_func
696 RCC_AHBPeriphClockCmd:
697 .LFB43:
748:stm32lib/src/stm32f10x_rcc.c ****
749:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
750:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_AHBPeriphClockCmd
751:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the AHB peripheral clock.
752:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
753:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
754:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_DMA1
755:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_DMA2
756:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_SRAM
757:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_FLITF
758:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_CRC
759:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_FSMC
760:stm32lib/src/stm32f10x_rcc.c **** * - RCC_AHBPeriph_SDIO
761:stm32lib/src/stm32f10x_rcc.c **** * SRAM and FLITF clock can be disabled only during sleep mode.
762:stm32lib/src/stm32f10x_rcc.c **** * - NewState: new state of the specified peripheral clock.
763:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
764:stm32lib/src/stm32f10x_rcc.c **** * Output : None
765:stm32lib/src/stm32f10x_rcc.c **** * Return : None
766:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
767:stm32lib/src/stm32f10x_rcc.c **** void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
768:stm32lib/src/stm32f10x_rcc.c **** {
698 .loc 1 768 0
699 @ args = 0, pretend = 0, frame = 0
700 @ frame_needed = 0, uses_anonymous_args = 0
701 @ link register save eliminated.
702 .LVL45:
769:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
770:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
771:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
772:stm32lib/src/stm32f10x_rcc.c ****
773:stm32lib/src/stm32f10x_rcc.c **** if (NewState != DISABLE)
703 .loc 1 773 0
704 0224 21B1 cbz r1, .L101
774:stm32lib/src/stm32f10x_rcc.c **** {
775:stm32lib/src/stm32f10x_rcc.c **** RCC->AHBENR |= RCC_AHBPeriph;
705 .loc 1 775 0
706 0226 054A ldr r2, .L105
707 0228 5369 ldr r3, [r2, #20]
708 022a 40EA0303 orr r3, r0, r3
709 022e 03E0 b .L104
710 .L101:
776:stm32lib/src/stm32f10x_rcc.c **** }
777:stm32lib/src/stm32f10x_rcc.c **** else
778:stm32lib/src/stm32f10x_rcc.c **** {
779:stm32lib/src/stm32f10x_rcc.c **** RCC->AHBENR &= ~RCC_AHBPeriph;
711 .loc 1 779 0
712 0230 024A ldr r2, .L105
713 0232 5369 ldr r3, [r2, #20]
714 0234 23EA0003 bic r3, r3, r0
715 .L104:
716 0238 5361 str r3, [r2, #20]
780:stm32lib/src/stm32f10x_rcc.c **** }
781:stm32lib/src/stm32f10x_rcc.c **** }
717 .loc 1 781 0
718 023a 7047 bx lr
719 .L106:
720 .align 2
721 .L105:
722 023c 00100240 .word 1073876992
723 .LFE43:
725 .align 2
726 .global RCC_APB2PeriphClockCmd
727 .thumb
728 .thumb_func
730 RCC_APB2PeriphClockCmd:
731 .LFB44:
782:stm32lib/src/stm32f10x_rcc.c ****
783:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
784:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_APB2PeriphClockCmd
785:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
786:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
787:stm32lib/src/stm32f10x_rcc.c **** * clock.
788:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
789:stm32lib/src/stm32f10x_rcc.c **** * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
790:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
791:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
792:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
793:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
794:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_ALL
795:stm32lib/src/stm32f10x_rcc.c **** * - NewState: new state of the specified peripheral clock.
796:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
797:stm32lib/src/stm32f10x_rcc.c **** * Output : None
798:stm32lib/src/stm32f10x_rcc.c **** * Return : None
799:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
800:stm32lib/src/stm32f10x_rcc.c **** void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
801:stm32lib/src/stm32f10x_rcc.c **** {
732 .loc 1 801 0
733 @ args = 0, pretend = 0, frame = 0
734 @ frame_needed = 0, uses_anonymous_args = 0
735 @ link register save eliminated.
736 .LVL46:
802:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
803:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
804:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
805:stm32lib/src/stm32f10x_rcc.c ****
806:stm32lib/src/stm32f10x_rcc.c **** if (NewState != DISABLE)
737 .loc 1 806 0
738 0240 21B1 cbz r1, .L108
807:stm32lib/src/stm32f10x_rcc.c **** {
808:stm32lib/src/stm32f10x_rcc.c **** RCC->APB2ENR |= RCC_APB2Periph;
739 .loc 1 808 0
740 0242 054A ldr r2, .L112
741 0244 9369 ldr r3, [r2, #24]
742 0246 40EA0303 orr r3, r0, r3
743 024a 03E0 b .L111
744 .L108:
809:stm32lib/src/stm32f10x_rcc.c **** }
810:stm32lib/src/stm32f10x_rcc.c **** else
811:stm32lib/src/stm32f10x_rcc.c **** {
812:stm32lib/src/stm32f10x_rcc.c **** RCC->APB2ENR &= ~RCC_APB2Periph;
745 .loc 1 812 0
746 024c 024A ldr r2, .L112
747 024e 9369 ldr r3, [r2, #24]
748 0250 23EA0003 bic r3, r3, r0
749 .L111:
750 0254 9361 str r3, [r2, #24]
813:stm32lib/src/stm32f10x_rcc.c **** }
814:stm32lib/src/stm32f10x_rcc.c **** }
751 .loc 1 814 0
752 0256 7047 bx lr
753 .L113:
754 .align 2
755 .L112:
756 0258 00100240 .word 1073876992
757 .LFE44:
759 .align 2
760 .global RCC_APB1PeriphClockCmd
761 .thumb
762 .thumb_func
764 RCC_APB1PeriphClockCmd:
765 .LFB45:
815:stm32lib/src/stm32f10x_rcc.c ****
816:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
817:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_APB1PeriphClockCmd
818:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
819:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
820:stm32lib/src/stm32f10x_rcc.c **** * clock.
821:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
822:stm32lib/src/stm32f10x_rcc.c **** * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
823:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
824:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
825:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
826:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
827:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
828:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
829:stm32lib/src/stm32f10x_rcc.c **** * - NewState: new state of the specified peripheral clock.
830:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
831:stm32lib/src/stm32f10x_rcc.c **** * Output : None
832:stm32lib/src/stm32f10x_rcc.c **** * Return : None
833:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
834:stm32lib/src/stm32f10x_rcc.c **** void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
835:stm32lib/src/stm32f10x_rcc.c **** {
766 .loc 1 835 0
767 @ args = 0, pretend = 0, frame = 0
768 @ frame_needed = 0, uses_anonymous_args = 0
769 @ link register save eliminated.
770 .LVL47:
836:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
837:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
838:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
839:stm32lib/src/stm32f10x_rcc.c ****
840:stm32lib/src/stm32f10x_rcc.c **** if (NewState != DISABLE)
771 .loc 1 840 0
772 025c 21B1 cbz r1, .L115
841:stm32lib/src/stm32f10x_rcc.c **** {
842:stm32lib/src/stm32f10x_rcc.c **** RCC->APB1ENR |= RCC_APB1Periph;
773 .loc 1 842 0
774 025e 054A ldr r2, .L119
775 0260 D369 ldr r3, [r2, #28]
776 0262 40EA0303 orr r3, r0, r3
777 0266 03E0 b .L118
778 .L115:
843:stm32lib/src/stm32f10x_rcc.c **** }
844:stm32lib/src/stm32f10x_rcc.c **** else
845:stm32lib/src/stm32f10x_rcc.c **** {
846:stm32lib/src/stm32f10x_rcc.c **** RCC->APB1ENR &= ~RCC_APB1Periph;
779 .loc 1 846 0
780 0268 024A ldr r2, .L119
781 026a D369 ldr r3, [r2, #28]
782 026c 23EA0003 bic r3, r3, r0
783 .L118:
784 0270 D361 str r3, [r2, #28]
847:stm32lib/src/stm32f10x_rcc.c **** }
848:stm32lib/src/stm32f10x_rcc.c **** }
785 .loc 1 848 0
786 0272 7047 bx lr
787 .L120:
788 .align 2
789 .L119:
790 0274 00100240 .word 1073876992
791 .LFE45:
793 .align 2
794 .global RCC_APB2PeriphResetCmd
795 .thumb
796 .thumb_func
798 RCC_APB2PeriphResetCmd:
799 .LFB46:
849:stm32lib/src/stm32f10x_rcc.c ****
850:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
851:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_APB2PeriphResetCmd
852:stm32lib/src/stm32f10x_rcc.c **** * Description : Forces or releases High Speed APB (APB2) peripheral reset.
853:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
854:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
855:stm32lib/src/stm32f10x_rcc.c **** * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
856:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
857:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
858:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
859:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
860:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB2Periph_ALL
861:stm32lib/src/stm32f10x_rcc.c **** * - NewState: new state of the specified peripheral reset.
862:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
863:stm32lib/src/stm32f10x_rcc.c **** * Output : None
864:stm32lib/src/stm32f10x_rcc.c **** * Return : None
865:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
866:stm32lib/src/stm32f10x_rcc.c **** void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
867:stm32lib/src/stm32f10x_rcc.c **** {
800 .loc 1 867 0
801 @ args = 0, pretend = 0, frame = 0
802 @ frame_needed = 0, uses_anonymous_args = 0
803 @ link register save eliminated.
804 .LVL48:
868:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
869:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
870:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
871:stm32lib/src/stm32f10x_rcc.c ****
872:stm32lib/src/stm32f10x_rcc.c **** if (NewState != DISABLE)
805 .loc 1 872 0
806 0278 21B1 cbz r1, .L122
873:stm32lib/src/stm32f10x_rcc.c **** {
874:stm32lib/src/stm32f10x_rcc.c **** RCC->APB2RSTR |= RCC_APB2Periph;
807 .loc 1 874 0
808 027a 054A ldr r2, .L126
809 027c D368 ldr r3, [r2, #12]
810 027e 40EA0303 orr r3, r0, r3
811 0282 03E0 b .L125
812 .L122:
875:stm32lib/src/stm32f10x_rcc.c **** }
876:stm32lib/src/stm32f10x_rcc.c **** else
877:stm32lib/src/stm32f10x_rcc.c **** {
878:stm32lib/src/stm32f10x_rcc.c **** RCC->APB2RSTR &= ~RCC_APB2Periph;
813 .loc 1 878 0
814 0284 024A ldr r2, .L126
815 0286 D368 ldr r3, [r2, #12]
816 0288 23EA0003 bic r3, r3, r0
817 .L125:
818 028c D360 str r3, [r2, #12]
879:stm32lib/src/stm32f10x_rcc.c **** }
880:stm32lib/src/stm32f10x_rcc.c **** }
819 .loc 1 880 0
820 028e 7047 bx lr
821 .L127:
822 .align 2
823 .L126:
824 0290 00100240 .word 1073876992
825 .LFE46:
827 .align 2
828 .global RCC_APB1PeriphResetCmd
829 .thumb
830 .thumb_func
832 RCC_APB1PeriphResetCmd:
833 .LFB47:
881:stm32lib/src/stm32f10x_rcc.c ****
882:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
883:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_APB1PeriphResetCmd
884:stm32lib/src/stm32f10x_rcc.c **** * Description : Forces or releases Low Speed APB (APB1) peripheral reset.
885:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
886:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
887:stm32lib/src/stm32f10x_rcc.c **** * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
888:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
889:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
890:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
891:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
892:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
893:stm32lib/src/stm32f10x_rcc.c **** * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
894:stm32lib/src/stm32f10x_rcc.c **** * - NewState: new state of the specified peripheral clock.
895:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
896:stm32lib/src/stm32f10x_rcc.c **** * Output : None
897:stm32lib/src/stm32f10x_rcc.c **** * Return : None
898:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
899:stm32lib/src/stm32f10x_rcc.c **** void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
900:stm32lib/src/stm32f10x_rcc.c **** {
834 .loc 1 900 0
835 @ args = 0, pretend = 0, frame = 0
836 @ frame_needed = 0, uses_anonymous_args = 0
837 @ link register save eliminated.
838 .LVL49:
901:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
902:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
903:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
904:stm32lib/src/stm32f10x_rcc.c ****
905:stm32lib/src/stm32f10x_rcc.c **** if (NewState != DISABLE)
839 .loc 1 905 0
840 0294 21B1 cbz r1, .L129
906:stm32lib/src/stm32f10x_rcc.c **** {
907:stm32lib/src/stm32f10x_rcc.c **** RCC->APB1RSTR |= RCC_APB1Periph;
841 .loc 1 907 0
842 0296 054A ldr r2, .L133
843 0298 1369 ldr r3, [r2, #16]
844 029a 40EA0303 orr r3, r0, r3
845 029e 03E0 b .L132
846 .L129:
908:stm32lib/src/stm32f10x_rcc.c **** }
909:stm32lib/src/stm32f10x_rcc.c **** else
910:stm32lib/src/stm32f10x_rcc.c **** {
911:stm32lib/src/stm32f10x_rcc.c **** RCC->APB1RSTR &= ~RCC_APB1Periph;
847 .loc 1 911 0
848 02a0 024A ldr r2, .L133
849 02a2 1369 ldr r3, [r2, #16]
850 02a4 23EA0003 bic r3, r3, r0
851 .L132:
852 02a8 1361 str r3, [r2, #16]
912:stm32lib/src/stm32f10x_rcc.c **** }
913:stm32lib/src/stm32f10x_rcc.c **** }
853 .loc 1 913 0
854 02aa 7047 bx lr
855 .L134:
856 .align 2
857 .L133:
858 02ac 00100240 .word 1073876992
859 .LFE47:
861 .align 2
862 .global RCC_BackupResetCmd
863 .thumb
864 .thumb_func
866 RCC_BackupResetCmd:
867 .LFB48:
914:stm32lib/src/stm32f10x_rcc.c ****
915:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
916:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_BackupResetCmd
917:stm32lib/src/stm32f10x_rcc.c **** * Description : Forces or releases the Backup domain reset.
918:stm32lib/src/stm32f10x_rcc.c **** * Input : - NewState: new state of the Backup domain reset.
919:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
920:stm32lib/src/stm32f10x_rcc.c **** * Output : None
921:stm32lib/src/stm32f10x_rcc.c **** * Return : None
922:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
923:stm32lib/src/stm32f10x_rcc.c **** void RCC_BackupResetCmd(FunctionalState NewState)
924:stm32lib/src/stm32f10x_rcc.c **** {
868 .loc 1 924 0
869 @ args = 0, pretend = 0, frame = 0
870 @ frame_needed = 0, uses_anonymous_args = 0
871 @ link register save eliminated.
872 .LVL50:
925:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
926:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
927:stm32lib/src/stm32f10x_rcc.c ****
928:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
873 .loc 1 928 0
874 02b0 014B ldr r3, .L137
875 02b2 1860 str r0, [r3, #0]
929:stm32lib/src/stm32f10x_rcc.c **** }
876 .loc 1 929 0
877 02b4 7047 bx lr
878 .L138:
879 02b6 00BF .align 2
880 .L137:
881 02b8 40044242 .word 1111622720
882 .LFE48:
884 .align 2
885 .global RCC_ClockSecuritySystemCmd
886 .thumb
887 .thumb_func
889 RCC_ClockSecuritySystemCmd:
890 .LFB49:
930:stm32lib/src/stm32f10x_rcc.c ****
931:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
932:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_ClockSecuritySystemCmd
933:stm32lib/src/stm32f10x_rcc.c **** * Description : Enables or disables the Clock Security System.
934:stm32lib/src/stm32f10x_rcc.c **** * Input : - NewState: new state of the Clock Security System..
935:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be: ENABLE or DISABLE.
936:stm32lib/src/stm32f10x_rcc.c **** * Output : None
937:stm32lib/src/stm32f10x_rcc.c **** * Return : None
938:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
939:stm32lib/src/stm32f10x_rcc.c **** void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
940:stm32lib/src/stm32f10x_rcc.c **** {
891 .loc 1 940 0
892 @ args = 0, pretend = 0, frame = 0
893 @ frame_needed = 0, uses_anonymous_args = 0
894 @ link register save eliminated.
895 .LVL51:
941:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
942:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_FUNCTIONAL_STATE(NewState));
943:stm32lib/src/stm32f10x_rcc.c ****
944:stm32lib/src/stm32f10x_rcc.c **** *(vu32 *) CR_CSSON_BB = (u32)NewState;
896 .loc 1 944 0
897 02bc 014B ldr r3, .L141
898 02be 1860 str r0, [r3, #0]
945:stm32lib/src/stm32f10x_rcc.c **** }
899 .loc 1 945 0
900 02c0 7047 bx lr
901 .L142:
902 02c2 00BF .align 2
903 .L141:
904 02c4 4C004242 .word 1111621708
905 .LFE49:
907 .align 2
908 .global RCC_MCOConfig
909 .thumb
910 .thumb_func
912 RCC_MCOConfig:
913 .LFB50:
946:stm32lib/src/stm32f10x_rcc.c ****
947:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
948:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_MCOConfig
949:stm32lib/src/stm32f10x_rcc.c **** * Description : Selects the clock source to output on MCO pin.
950:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_MCO: specifies the clock source to output.
951:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
952:stm32lib/src/stm32f10x_rcc.c **** * - RCC_MCO_NoClock: No clock selected
953:stm32lib/src/stm32f10x_rcc.c **** * - RCC_MCO_SYSCLK: System clock selected
954:stm32lib/src/stm32f10x_rcc.c **** * - RCC_MCO_HSI: HSI oscillator clock selected
955:stm32lib/src/stm32f10x_rcc.c **** * - RCC_MCO_HSE: HSE oscillator clock selected
956:stm32lib/src/stm32f10x_rcc.c **** * - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
957:stm32lib/src/stm32f10x_rcc.c **** * Output : None
958:stm32lib/src/stm32f10x_rcc.c **** * Return : None
959:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
960:stm32lib/src/stm32f10x_rcc.c **** void RCC_MCOConfig(u8 RCC_MCO)
961:stm32lib/src/stm32f10x_rcc.c **** {
914 .loc 1 961 0
915 @ args = 0, pretend = 0, frame = 0
916 @ frame_needed = 0, uses_anonymous_args = 0
917 @ link register save eliminated.
918 .LVL52:
962:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
963:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCO));
964:stm32lib/src/stm32f10x_rcc.c ****
965:stm32lib/src/stm32f10x_rcc.c **** /* Perform Byte access to MCO[2:0] bits to select the MCO source */
966:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO;
919 .loc 1 966 0
920 02c8 014B ldr r3, .L145
921 02ca 1870 strb r0, [r3, #0]
967:stm32lib/src/stm32f10x_rcc.c **** }
922 .loc 1 967 0
923 02cc 7047 bx lr
924 .L146:
925 02ce 00BF .align 2
926 .L145:
927 02d0 07100240 .word 1073876999
928 .LFE50:
930 .align 2
931 .global RCC_GetFlagStatus
932 .thumb
933 .thumb_func
935 RCC_GetFlagStatus:
936 .LFB51:
968:stm32lib/src/stm32f10x_rcc.c ****
969:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
970:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_GetFlagStatus
971:stm32lib/src/stm32f10x_rcc.c **** * Description : Checks whether the specified RCC flag is set or not.
972:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_FLAG: specifies the flag to check.
973:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
974:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_HSIRDY: HSI oscillator clock ready
975:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_HSERDY: HSE oscillator clock ready
976:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_PLLRDY: PLL clock ready
977:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_LSERDY: LSE oscillator clock ready
978:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_LSIRDY: LSI oscillator clock ready
979:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_PINRST: Pin reset
980:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_PORRST: POR/PDR reset
981:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_SFTRST: Software reset
982:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_IWDGRST: Independent Watchdog reset
983:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_WWDGRST: Window Watchdog reset
984:stm32lib/src/stm32f10x_rcc.c **** * - RCC_FLAG_LPWRRST: Low Power reset
985:stm32lib/src/stm32f10x_rcc.c **** * Output : None
986:stm32lib/src/stm32f10x_rcc.c **** * Return : The new state of RCC_FLAG (SET or RESET).
987:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
988:stm32lib/src/stm32f10x_rcc.c **** FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
989:stm32lib/src/stm32f10x_rcc.c **** {
937 .loc 1 989 0
938 @ args = 0, pretend = 0, frame = 0
939 @ frame_needed = 0, uses_anonymous_args = 0
940 @ link register save eliminated.
941 .LVL53:
990:stm32lib/src/stm32f10x_rcc.c **** u32 tmp = 0;
991:stm32lib/src/stm32f10x_rcc.c **** u32 statusreg = 0;
992:stm32lib/src/stm32f10x_rcc.c **** FlagStatus bitstatus = RESET;
993:stm32lib/src/stm32f10x_rcc.c ****
994:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
995:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_FLAG(RCC_FLAG));
996:stm32lib/src/stm32f10x_rcc.c ****
997:stm32lib/src/stm32f10x_rcc.c **** /* Get the RCC register index */
998:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC_FLAG >> 5;
942 .loc 1 998 0
943 02d4 4309 lsrs r3, r0, #5
944 .LVL54:
999:stm32lib/src/stm32f10x_rcc.c ****
1000:stm32lib/src/stm32f10x_rcc.c **** if (tmp == 1) /* The flag to check is in CR register */
945 .loc 1 1000 0
946 02d6 012B cmp r3, #1
947 02d8 02D1 bne .L148
1001:stm32lib/src/stm32f10x_rcc.c **** {
1002:stm32lib/src/stm32f10x_rcc.c **** statusreg = RCC->CR;
948 .loc 1 1002 0
949 02da 084B ldr r3, .L152
950 .LVL55:
951 02dc 1B68 ldr r3, [r3, #0]
952 .LVL56:
953 02de 05E0 b .L149
954 .LVL57:
955 .L148:
1003:stm32lib/src/stm32f10x_rcc.c **** }
1004:stm32lib/src/stm32f10x_rcc.c **** else if (tmp == 2) /* The flag to check is in BDCR register */
956 .loc 1 1004 0
957 02e0 022B cmp r3, #2
1005:stm32lib/src/stm32f10x_rcc.c **** {
1006:stm32lib/src/stm32f10x_rcc.c **** statusreg = RCC->BDCR;
958 .loc 1 1006 0
959 02e2 0BBF itete eq
960 02e4 054B ldreq r3, .L152
961 .LVL58:
1007:stm32lib/src/stm32f10x_rcc.c **** }
1008:stm32lib/src/stm32f10x_rcc.c **** else /* The flag to check is in CSR register */
1009:stm32lib/src/stm32f10x_rcc.c **** {
1010:stm32lib/src/stm32f10x_rcc.c **** statusreg = RCC->CSR;
962 .loc 1 1010 0
963 02e6 054B ldrne r3, .L152
964 .loc 1 1006 0
965 02e8 1B6A ldreq r3, [r3, #32]
966 .LVL59:
967 .loc 1 1010 0
968 02ea 5B6A ldrne r3, [r3, #36]
969 .LVL60:
970 .L149:
971 02ec 00F01F00 and r0, r0, #31
972 .LVL61:
973 02f0 33FA00F0 lsrs r0, r3, r0
1011:stm32lib/src/stm32f10x_rcc.c **** }
1012:stm32lib/src/stm32f10x_rcc.c ****
1013:stm32lib/src/stm32f10x_rcc.c **** /* Get the flag position */
1014:stm32lib/src/stm32f10x_rcc.c **** tmp = RCC_FLAG & FLAG_Mask;
1015:stm32lib/src/stm32f10x_rcc.c ****
1016:stm32lib/src/stm32f10x_rcc.c **** if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
1017:stm32lib/src/stm32f10x_rcc.c **** {
1018:stm32lib/src/stm32f10x_rcc.c **** bitstatus = SET;
1019:stm32lib/src/stm32f10x_rcc.c **** }
1020:stm32lib/src/stm32f10x_rcc.c **** else
1021:stm32lib/src/stm32f10x_rcc.c **** {
1022:stm32lib/src/stm32f10x_rcc.c **** bitstatus = RESET;
1023:stm32lib/src/stm32f10x_rcc.c **** }
1024:stm32lib/src/stm32f10x_rcc.c ****
1025:stm32lib/src/stm32f10x_rcc.c **** /* Return the flag status */
1026:stm32lib/src/stm32f10x_rcc.c **** return bitstatus;
1027:stm32lib/src/stm32f10x_rcc.c **** }
974 .loc 1 1027 0
975 02f4 00F00100 and r0, r0, #1
976 02f8 7047 bx lr
977 .L153:
978 02fa 00BF .align 2
979 .L152:
980 02fc 00100240 .word 1073876992
981 .LFE51:
983 .align 2
984 .global RCC_WaitForHSEStartUp
985 .thumb
986 .thumb_func
988 RCC_WaitForHSEStartUp:
989 .LFB25:
990 .loc 1 200 0
991 @ args = 0, pretend = 0, frame = 0
992 @ frame_needed = 0, uses_anonymous_args = 0
993 0300 10B5 push {r4, lr}
994 .LCFI1:
995 .L156:
996 .loc 1 206 0
997 0302 3120 movs r0, #49
998 0304 FFF7FEFF bl RCC_GetFlagStatus
999 0308 094A ldr r2, .L158
1000 030a 1070 strb r0, [r2, #0]
1001 .loc 1 207 0
1002 030c 5368 ldr r3, [r2, #4]
1003 030e 0133 adds r3, r3, #1
1004 0310 5360 str r3, [r2, #4]
1005 .loc 1 208 0
1006 0312 1378 ldrb r3, [r2, #0] @ zero_extendqisi2
1007 0314 23B9 cbnz r3, .L155
1008 0316 5268 ldr r2, [r2, #4]
1009 0318 40F2FF13 movw r3, #511
1010 031c 9A42 cmp r2, r3
1011 031e F0D1 bne .L156
1012 .L155:
1013 .loc 1 211 0
1014 0320 3120 movs r0, #49
1015 0322 FFF7FEFF bl RCC_GetFlagStatus
1016 .loc 1 221 0
1017 0326 0038 subs r0, r0, #0
1018 0328 18BF it ne
1019 032a 0120 movne r0, #1
1020 032c 10BD pop {r4, pc}
1021 .L159:
1022 032e 00BF .align 2
1023 .L158:
1024 0330 00000000 .word .LANCHOR1
1025 .LFE25:
1027 .align 2
1028 .global RCC_ClearFlag
1029 .thumb
1030 .thumb_func
1032 RCC_ClearFlag:
1033 .LFB52:
1028:stm32lib/src/stm32f10x_rcc.c ****
1029:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
1030:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_ClearFlag
1031:stm32lib/src/stm32f10x_rcc.c **** * Description : Clears the RCC reset flags.
1032:stm32lib/src/stm32f10x_rcc.c **** * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1033:stm32lib/src/stm32f10x_rcc.c **** * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
1034:stm32lib/src/stm32f10x_rcc.c **** * RCC_FLAG_LPWRRST
1035:stm32lib/src/stm32f10x_rcc.c **** * Input : None
1036:stm32lib/src/stm32f10x_rcc.c **** * Output : None
1037:stm32lib/src/stm32f10x_rcc.c **** * Return : None
1038:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
1039:stm32lib/src/stm32f10x_rcc.c **** void RCC_ClearFlag(void)
1040:stm32lib/src/stm32f10x_rcc.c **** {
1034 .loc 1 1040 0
1035 @ args = 0, pretend = 0, frame = 0
1036 @ frame_needed = 0, uses_anonymous_args = 0
1037 @ link register save eliminated.
1041:stm32lib/src/stm32f10x_rcc.c **** /* Set RMVF bit to clear the reset flags */
1042:stm32lib/src/stm32f10x_rcc.c **** RCC->CSR |= CSR_RMVF_Set;
1038 .loc 1 1042 0
1039 0334 024A ldr r2, .L162
1040 0336 536A ldr r3, [r2, #36]
1041 0338 43F08073 orr r3, r3, #16777216
1042 033c 5362 str r3, [r2, #36]
1043:stm32lib/src/stm32f10x_rcc.c **** }
1043 .loc 1 1043 0
1044 033e 7047 bx lr
1045 .L163:
1046 .align 2
1047 .L162:
1048 0340 00100240 .word 1073876992
1049 .LFE52:
1051 .align 2
1052 .global RCC_GetITStatus
1053 .thumb
1054 .thumb_func
1056 RCC_GetITStatus:
1057 .LFB53:
1044:stm32lib/src/stm32f10x_rcc.c ****
1045:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
1046:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_GetITStatus
1047:stm32lib/src/stm32f10x_rcc.c **** * Description : Checks whether the specified RCC interrupt has occurred or not.
1048:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_IT: specifies the RCC interrupt source to check.
1049:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be one of the following values:
1050:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_LSIRDY: LSI ready interrupt
1051:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_LSERDY: LSE ready interrupt
1052:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_HSIRDY: HSI ready interrupt
1053:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_HSERDY: HSE ready interrupt
1054:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_PLLRDY: PLL ready interrupt
1055:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_CSS: Clock Security System interrupt
1056:stm32lib/src/stm32f10x_rcc.c **** * Output : None
1057:stm32lib/src/stm32f10x_rcc.c **** * Return : The new state of RCC_IT (SET or RESET).
1058:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
1059:stm32lib/src/stm32f10x_rcc.c **** ITStatus RCC_GetITStatus(u8 RCC_IT)
1060:stm32lib/src/stm32f10x_rcc.c **** {
1058 .loc 1 1060 0
1059 @ args = 0, pretend = 0, frame = 0
1060 @ frame_needed = 0, uses_anonymous_args = 0
1061 @ link register save eliminated.
1062 .LVL62:
1061:stm32lib/src/stm32f10x_rcc.c **** ITStatus bitstatus = RESET;
1062:stm32lib/src/stm32f10x_rcc.c ****
1063:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
1064:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_GET_IT(RCC_IT));
1065:stm32lib/src/stm32f10x_rcc.c ****
1066:stm32lib/src/stm32f10x_rcc.c **** /* Check the status of the specified RCC interrupt */
1067:stm32lib/src/stm32f10x_rcc.c **** if ((RCC->CIR & RCC_IT) != (u32)RESET)
1063 .loc 1 1067 0
1064 0344 034B ldr r3, .L166
1065 0346 9B68 ldr r3, [r3, #8]
1066 0348 1842 tst r0, r3
1068:stm32lib/src/stm32f10x_rcc.c **** {
1069:stm32lib/src/stm32f10x_rcc.c **** bitstatus = SET;
1070:stm32lib/src/stm32f10x_rcc.c **** }
1071:stm32lib/src/stm32f10x_rcc.c **** else
1072:stm32lib/src/stm32f10x_rcc.c **** {
1073:stm32lib/src/stm32f10x_rcc.c **** bitstatus = RESET;
1074:stm32lib/src/stm32f10x_rcc.c **** }
1075:stm32lib/src/stm32f10x_rcc.c ****
1076:stm32lib/src/stm32f10x_rcc.c **** /* Return the RCC_IT status */
1077:stm32lib/src/stm32f10x_rcc.c **** return bitstatus;
1078:stm32lib/src/stm32f10x_rcc.c **** }
1067 .loc 1 1078 0
1068 034a 0CBF ite eq
1069 034c 0020 moveq r0, #0
1070 034e 0120 movne r0, #1
1071 .LVL63:
1072 0350 7047 bx lr
1073 .L167:
1074 0352 00BF .align 2
1075 .L166:
1076 0354 00100240 .word 1073876992
1077 .LFE53:
1079 .align 2
1080 .global RCC_ClearITPendingBit
1081 .thumb
1082 .thumb_func
1084 RCC_ClearITPendingBit:
1085 .LFB54:
1079:stm32lib/src/stm32f10x_rcc.c ****
1080:stm32lib/src/stm32f10x_rcc.c **** /*******************************************************************************
1081:stm32lib/src/stm32f10x_rcc.c **** * Function Name : RCC_ClearITPendingBit
1082:stm32lib/src/stm32f10x_rcc.c **** * Description : Clears the RCC’s interrupt pending bits.
1083:stm32lib/src/stm32f10x_rcc.c **** * Input : - RCC_IT: specifies the interrupt pending bit to clear.
1084:stm32lib/src/stm32f10x_rcc.c **** * This parameter can be any combination of the following values:
1085:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_LSIRDY: LSI ready interrupt
1086:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_LSERDY: LSE ready interrupt
1087:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_HSIRDY: HSI ready interrupt
1088:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_HSERDY: HSE ready interrupt
1089:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_PLLRDY: PLL ready interrupt
1090:stm32lib/src/stm32f10x_rcc.c **** * - RCC_IT_CSS: Clock Security System interrupt
1091:stm32lib/src/stm32f10x_rcc.c **** * Output : None
1092:stm32lib/src/stm32f10x_rcc.c **** * Return : None
1093:stm32lib/src/stm32f10x_rcc.c **** *******************************************************************************/
1094:stm32lib/src/stm32f10x_rcc.c **** void RCC_ClearITPendingBit(u8 RCC_IT)
1095:stm32lib/src/stm32f10x_rcc.c **** {
1086 .loc 1 1095 0
1087 @ args = 0, pretend = 0, frame = 0
1088 @ frame_needed = 0, uses_anonymous_args = 0
1089 @ link register save eliminated.
1090 .LVL64:
1096:stm32lib/src/stm32f10x_rcc.c **** /* Check the parameters */
1097:stm32lib/src/stm32f10x_rcc.c **** assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1098:stm32lib/src/stm32f10x_rcc.c ****
1099:stm32lib/src/stm32f10x_rcc.c **** /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1100:stm32lib/src/stm32f10x_rcc.c **** pending bits */
1101:stm32lib/src/stm32f10x_rcc.c **** *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT;
1091 .loc 1 1101 0
1092 0358 014B ldr r3, .L170
1093 035a 1870 strb r0, [r3, #0]
1102:stm32lib/src/stm32f10x_rcc.c **** }
1094 .loc 1 1102 0
1095 035c 7047 bx lr
1096 .L171:
1097 035e 00BF .align 2
1098 .L170:
1099 0360 0A100240 .word 1073877002
1100 .LFE54:
1102 .section .rodata
1103 .set .LANCHOR0,. + 0
1106 APBAHBPrescTable:
1107 0000 00 .byte 0
1108 0001 00 .byte 0
1109 0002 00 .byte 0
1110 0003 00 .byte 0
1111 0004 01 .byte 1
1112 0005 02 .byte 2
1113 0006 03 .byte 3
1114 0007 04 .byte 4
1115 0008 01 .byte 1
1116 0009 02 .byte 2
1117 000a 03 .byte 3
1118 000b 04 .byte 4
1119 000c 06 .byte 6
1120 000d 07 .byte 7
1121 000e 08 .byte 8
1122 000f 09 .byte 9
1125 ADCPrescTable:
1126 0010 02 .byte 2
1127 0011 04 .byte 4
1128 0012 06 .byte 6
1129 0013 08 .byte 8
1130 .bss
1131 .align 2
1132 .set .LANCHOR1,. + 0
1135 HSEStatus:
1136 0000 00 .space 1
1137 0001 000000 .space 3
1140 StartUpCounter:
1141 0004 00000000 .space 4
1430 .Letext0:
DEFINED SYMBOLS
*ABS*:00000000 stm32f10x_rcc.c
/tmp/cck1KuUa.s:22 .text:00000000 $t
/tmp/cck1KuUa.s:27 .text:00000000 RCC_DeInit
/tmp/cck1KuUa.s:65 .text:00000038 $d
/tmp/cck1KuUa.s:69 .text:00000040 $t
/tmp/cck1KuUa.s:74 .text:00000040 RCC_HSEConfig
/tmp/cck1KuUa.s:115 .text:00000074 $d
/tmp/cck1KuUa.s:118 .text:00000078 $t
/tmp/cck1KuUa.s:123 .text:00000078 RCC_AdjustHSICalibrationValue
/tmp/cck1KuUa.s:147 .text:00000088 $d
/tmp/cck1KuUa.s:150 .text:0000008c $t
/tmp/cck1KuUa.s:155 .text:0000008c RCC_HSICmd
/tmp/cck1KuUa.s:170 .text:00000094 $d
/tmp/cck1KuUa.s:173 .text:00000098 $t
/tmp/cck1KuUa.s:178 .text:00000098 RCC_PLLConfig
/tmp/cck1KuUa.s:203 .text:000000a8 $d
/tmp/cck1KuUa.s:206 .text:000000ac $t
/tmp/cck1KuUa.s:211 .text:000000ac RCC_PLLCmd
/tmp/cck1KuUa.s:226 .text:000000b4 $d
/tmp/cck1KuUa.s:229 .text:000000b8 $t
/tmp/cck1KuUa.s:234 .text:000000b8 RCC_SYSCLKConfig
/tmp/cck1KuUa.s:258 .text:000000c8 $d
/tmp/cck1KuUa.s:261 .text:000000cc $t
/tmp/cck1KuUa.s:266 .text:000000cc RCC_GetSYSCLKSource
/tmp/cck1KuUa.s:281 .text:000000d8 $d
/tmp/cck1KuUa.s:284 .text:000000dc $t
/tmp/cck1KuUa.s:289 .text:000000dc RCC_HCLKConfig
/tmp/cck1KuUa.s:313 .text:000000ec $d
/tmp/cck1KuUa.s:316 .text:000000f0 $t
/tmp/cck1KuUa.s:321 .text:000000f0 RCC_PCLK1Config
/tmp/cck1KuUa.s:345 .text:00000100 $d
/tmp/cck1KuUa.s:348 .text:00000104 $t
/tmp/cck1KuUa.s:353 .text:00000104 RCC_PCLK2Config
/tmp/cck1KuUa.s:377 .text:00000114 $d
/tmp/cck1KuUa.s:380 .text:00000118 $t
/tmp/cck1KuUa.s:385 .text:00000118 RCC_ITConfig
/tmp/cck1KuUa.s:411 .text:00000130 $d
/tmp/cck1KuUa.s:414 .text:00000134 $t
/tmp/cck1KuUa.s:419 .text:00000134 RCC_USBCLKConfig
/tmp/cck1KuUa.s:434 .text:0000013c $d
/tmp/cck1KuUa.s:437 .text:00000140 $t
/tmp/cck1KuUa.s:442 .text:00000140 RCC_ADCCLKConfig
/tmp/cck1KuUa.s:466 .text:00000150 $d
/tmp/cck1KuUa.s:469 .text:00000154 $t
/tmp/cck1KuUa.s:474 .text:00000154 RCC_LSEConfig
/tmp/cck1KuUa.s:509 .text:00000170 $d
/tmp/cck1KuUa.s:512 .text:00000174 $t
/tmp/cck1KuUa.s:517 .text:00000174 RCC_LSICmd
/tmp/cck1KuUa.s:532 .text:0000017c $d
/tmp/cck1KuUa.s:535 .text:00000180 $t
/tmp/cck1KuUa.s:540 .text:00000180 RCC_RTCCLKConfig
/tmp/cck1KuUa.s:558 .text:0000018c $d
/tmp/cck1KuUa.s:561 .text:00000190 $t
/tmp/cck1KuUa.s:566 .text:00000190 RCC_RTCCLKCmd
/tmp/cck1KuUa.s:581 .text:00000198 $d
/tmp/cck1KuUa.s:584 .text:0000019c $t
/tmp/cck1KuUa.s:589 .text:0000019c RCC_GetClocksFreq
/tmp/cck1KuUa.s:685 .text:00000214 $d
/tmp/cck1KuUa.s:691 .text:00000224 $t
/tmp/cck1KuUa.s:696 .text:00000224 RCC_AHBPeriphClockCmd
/tmp/cck1KuUa.s:722 .text:0000023c $d
/tmp/cck1KuUa.s:725 .text:00000240 $t
/tmp/cck1KuUa.s:730 .text:00000240 RCC_APB2PeriphClockCmd
/tmp/cck1KuUa.s:756 .text:00000258 $d
/tmp/cck1KuUa.s:759 .text:0000025c $t
/tmp/cck1KuUa.s:764 .text:0000025c RCC_APB1PeriphClockCmd
/tmp/cck1KuUa.s:790 .text:00000274 $d
/tmp/cck1KuUa.s:793 .text:00000278 $t
/tmp/cck1KuUa.s:798 .text:00000278 RCC_APB2PeriphResetCmd
/tmp/cck1KuUa.s:824 .text:00000290 $d
/tmp/cck1KuUa.s:827 .text:00000294 $t
/tmp/cck1KuUa.s:832 .text:00000294 RCC_APB1PeriphResetCmd
/tmp/cck1KuUa.s:858 .text:000002ac $d
/tmp/cck1KuUa.s:861 .text:000002b0 $t
/tmp/cck1KuUa.s:866 .text:000002b0 RCC_BackupResetCmd
/tmp/cck1KuUa.s:881 .text:000002b8 $d
/tmp/cck1KuUa.s:884 .text:000002bc $t
/tmp/cck1KuUa.s:889 .text:000002bc RCC_ClockSecuritySystemCmd
/tmp/cck1KuUa.s:904 .text:000002c4 $d
/tmp/cck1KuUa.s:907 .text:000002c8 $t
/tmp/cck1KuUa.s:912 .text:000002c8 RCC_MCOConfig
/tmp/cck1KuUa.s:927 .text:000002d0 $d
/tmp/cck1KuUa.s:930 .text:000002d4 $t
/tmp/cck1KuUa.s:935 .text:000002d4 RCC_GetFlagStatus
/tmp/cck1KuUa.s:980 .text:000002fc $d
/tmp/cck1KuUa.s:983 .text:00000300 $t
/tmp/cck1KuUa.s:988 .text:00000300 RCC_WaitForHSEStartUp
/tmp/cck1KuUa.s:1024 .text:00000330 $d
/tmp/cck1KuUa.s:1027 .text:00000334 $t
/tmp/cck1KuUa.s:1032 .text:00000334 RCC_ClearFlag
/tmp/cck1KuUa.s:1048 .text:00000340 $d
/tmp/cck1KuUa.s:1051 .text:00000344 $t
/tmp/cck1KuUa.s:1056 .text:00000344 RCC_GetITStatus
/tmp/cck1KuUa.s:1076 .text:00000354 $d
/tmp/cck1KuUa.s:1079 .text:00000358 $t
/tmp/cck1KuUa.s:1084 .text:00000358 RCC_ClearITPendingBit
/tmp/cck1KuUa.s:1099 .text:00000360 $d
/tmp/cck1KuUa.s:1106 .rodata:00000000 APBAHBPrescTable
/tmp/cck1KuUa.s:1107 .rodata:00000000 $d
/tmp/cck1KuUa.s:1125 .rodata:00000010 ADCPrescTable
/tmp/cck1KuUa.s:1131 .bss:00000000 $d
/tmp/cck1KuUa.s:1135 .bss:00000000 HSEStatus
/tmp/cck1KuUa.s:1140 .bss:00000004 StartUpCounter
NO UNDEFINED SYMBOLS
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