aboutsummaryrefslogtreecommitdiffstats
path: root/source/libmaple/api/dac.rst
blob: 55c8faf89f303cf3aebda8dbeab770dd85e33390 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
.. highlight:: c
.. _libmaple-dac:

``dac.h``
=========

Digital to Analog Conversion (DAC) support.

.. contents:: Contents
   :local:

Types
-----

.. doxygenstruct:: dac_dev
.. doxygenstruct:: dac_reg_map

Devices
-------

.. doxygenvariable:: DAC

Functions
---------

.. doxygenfunction:: dac_init
.. doxygenfunction:: dac_write_channel
.. doxygenfunction:: dac_enable_channel
.. doxygenfunction:: dac_disable_channel

Register Map Base Pointers
--------------------------

.. doxygendefine:: DAC_BASE

Register Bit Definitions
------------------------

Control register
~~~~~~~~~~~~~~~~

**Channel 1**:

.. doxygendefine:: DAC_CR_EN1
.. doxygendefine:: DAC_CR_BOFF1
.. doxygendefine:: DAC_CR_TEN1
.. doxygendefine:: DAC_CR_TSEL1
.. doxygendefine:: DAC_CR_WAVE1
.. doxygendefine:: DAC_CR_MAMP1
.. doxygendefine:: DAC_CR_DMAEN1

**Channel 2**:

.. doxygendefine:: DAC_CR_EN2
.. doxygendefine:: DAC_CR_BOFF2
.. doxygendefine:: DAC_CR_TEN2
.. doxygendefine:: DAC_CR_TSEL2
.. doxygendefine:: DAC_CR_WAVE2
.. doxygendefine:: DAC_CR_MAMP2
.. doxygendefine:: DAC_CR_DMAEN2

Software trigger register
~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_SWTRIGR_SWTRIG1
.. doxygendefine:: DAC_SWTRIGR_SWTRIG2

Channel 1 12-bit right-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR12R1_DACC1DHR

Channel 1 12-bit left-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR12L1_DACC1DHR

Channel 1 8-bit left-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR8R1_DACC1DHR

Channel 2 12-bit right-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR12R2_DACC2DHR

Channel 2 12-bit left-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR12L2_DACC2DHR

Channel 2 8-bit left-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR8R2_DACC2DHR

Dual DAC 12-bit right-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR12RD_DACC1DHR
.. doxygendefine:: DAC_DHR12RD_DACC2DHR

Dual DAC 12-bit left-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR12LD_DACC1DHR
.. doxygendefine:: DAC_DHR12LD_DACC2DHR

Dual DAC 8-bit left-aligned data holding register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DHR8RD_DACC1DHR
.. doxygendefine:: DAC_DHR8RD_DACC2DHR

Channel 1 data output register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

.. doxygendefine:: DAC_DOR1_DACC1DOR

Channel 1 data output register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. doxygendefine:: DAC_DOR2_DACC2DOR