1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
|
/*
A low-level stress test of SRAM functionality. Uses slow-ish timing
by default (DATAST = ADDSET = 0xF).
Copyright 2011 LeafLabs, LLC.
This code is released into the public domain.
*/
#include <stdio.h>
#include <stddef.h>
#include "wirish.h"
#include "rcc.h"
#include "fsmc.h"
// -- SRAM config -------------------------------------------------------------
// Timing configuration
#define DATAST 0xF
#define ADDSET 0xF
// Number of SRAM chips to test
#define N 1
// How much of each to test
#define MEM_SIZE 0x3FFF
// Their start addresses in FSMC bank 1
__io uint16 *const starts[N] = {
// (__io uint16 *const)FSMC_NOR_PSRAM_REGION1,
// (__io uint16 *const)FSMC_NOR_PSRAM_REGION2,
(__io uint16 *const)FSMC_NOR_PSRAM_REGION3,
// (__io uint16 *const)FSMC_NOR_PSRAM_REGION4,
};
// Corresponding FSMC configuration registers
__io uint32 *const bcrs[N] = {
// &FSMC_NOR_PSRAM1_BASE->BCR,
// &FSMC_NOR_PSRAM2_BASE->BCR,
&FSMC_NOR_PSRAM3_BASE->BCR,
// &FSMC_NOR_PSRAM4_BASE->BCR,
};
// Corresponding FSMC timing registers
__io uint32 *const btrs[N] = {
// &FSMC_NOR_PSRAM1_BASE->BTR,
// &FSMC_NOR_PSRAM2_BASE->BTR,
&FSMC_NOR_PSRAM3_BASE->BTR,
// &FSMC_NOR_PSRAM4_BASE->BTR,
};
// -- Pseudorandom number generation -----------------------------------------
const uint32 seed = 0xDEADBEEF;
uint32 num_rand_calls = 0;
uint32 rand(long n) {
num_rand_calls++;
return random(n);
}
// -- Printing ----------------------------------------------------------------
// For snprintf()
char snprintf_buf[200];
#define ERR(fmt, ...) do { \
snprintf(snprintf_buf, sizeof snprintf_buf, \
"ERROR: " fmt " (seed %d, ncalls %d, line %d)", \
__VA_ARGS__, seed, num_rand_calls, __LINE__); \
SerialUSB.println(snprintf_buf); \
} while (0)
// Set to 1 for more output
#define VERBOSE 0
// -- setup()/loop() ----------------------------------------------------------
void setup() {
fsmc_sram_init_gpios();
rcc_clk_enable(RCC_FSMC);
for (int i = 0; i < N; i++) {
*bcrs[i] = (FSMC_BCR_WREN |
FSMC_BCR_MTYP_SRAM |
FSMC_BCR_MWID_16BITS |
FSMC_BCR_MBKEN);
*btrs[i] = (DATAST << 8) | ADDSET;
}
randomSeed(seed);
SerialUSB.read();
SerialUSB.println("Starting test");
}
// stress_test() and simple_roundtrip() are the available test routines
bool stress_test(void);
bool simple_roundtrip(void);
void loop() {
uint32 count = 0;
uint32 last;
bool ok = true;
bool (*test)(void) = stress_test;
last = millis();
while (true) {
count++;
bool result = test();
ok = ok && result;
if (ok && (millis() - last > 300)) {
snprintf(snprintf_buf, sizeof snprintf_buf,
"everything ok so far, timestamp %d ms", millis());
SerialUSB.println(snprintf_buf);
last = millis();
}
}
}
// -- Test routines -----------------------------------------------------------
bool random_trips();
bool sequential_trips();
bool stress_test(void) {
static int i = 0;
i = !i;
switch (i) {
case 0:
return random_trips();
default:
return sequential_trips();
}
}
bool simple_roundtrip(void) {
uint16 wval = 0xAB;
for (int i = 0; i < N; i++) {
__io uint16 *addr = starts[i] + 4;
snprintf(snprintf_buf, sizeof snprintf_buf, "round-trip 0x%x at %p",
wval, addr);
SerialUSB.println(snprintf_buf);
*addr = wval;
uint16 rval = *addr;
if (rval != wval) {
ERR("wrote 0x%x, read 0x%x, timestamp %d", wval, rval, millis());
return false;
} else {
snprintf(snprintf_buf, sizeof snprintf_buf, "got back 0x%x", rval);
SerialUSB.println(snprintf_buf);
}
}
return true;
}
bool random_trips(void) {
#if VERBOSE
SerialUSB.println("[random]");
#endif
for (int n = 0; n < N; n++) {
__io uint16 *const start = starts[n];
for (int i = 0; i < 1000; i++) {
uint32 offset = rand(MEM_SIZE);
uint32 wval = rand(0xFFFF);
*(start + offset) = wval;
uint32 rval = *(start + offset);
if (rval != wval) {
ERR("wrote 0x%x to 0x%x, read 0x%x", wval, offset, rval);
return false;
}
}
}
return true;
}
bool sequential_trips(void) {
static const uint32 seq_length = 300;
#if VERBOSE
SerialUSB.println("[seq]");
#endif
for (int n = 0; n < N; n++) {
__io uint16 *const start = starts[n];
for (int i = 0; i < 100; i++) {
uint32 start_offset = rand(MEM_SIZE - seq_length);
for (uint32 w = 0; w < seq_length; w++) {
uint32 offset = start_offset + w;
*(start + offset) = w;
uint32 r = *(start + offset);
if (w != r) {
ERR("wrote 0x%x to 0x%x, read 0x%x", w, offset, r);
return false;
}
}
}
}
return true;
}
// ----------------------------------------------------------------------------
__attribute__((constructor)) void premain() {
init();
}
int main(void) {
setup();
while (true) {
loop();
}
return 0;
}
|
