From ccd9833f264d6e20a9f2c81baebe162f07eec996 Mon Sep 17 00:00:00 2001 From: bnewbold Date: Thu, 5 Aug 2010 21:43:41 -0400 Subject: Some refactoring --- support/ld/ram.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'support/ld/ram.ld') diff --git a/support/ld/ram.ld b/support/ld/ram.ld index 6398ea4..872d6f2 100644 --- a/support/ld/ram.ld +++ b/support/ld/ram.ld @@ -25,8 +25,8 @@ /* Define memory spaces. */ MEMORY { - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0K + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K } -- cgit v1.2.3 From 0f55cc0d89dc018aa1a2e7ad1c926889f98ec26d Mon Sep 17 00:00:00 2001 From: bnewbold Date: Thu, 5 Aug 2010 21:47:12 -0400 Subject: partial progress on FSMC for SRAM --- .gitignore | 1 + examples/test-fsmc.cpp | 149 +++++++++++++++++++++++++++++++++++++++++++++++++ libmaple/exc.c | 1 + libmaple/fsmc.c | 120 +++++++++++++++++++++++++++++++++++++++ libmaple/fsmc.h | 86 ++++++++++++++++++++++++++++ libmaple/gpio.c | 3 + libmaple/gpio.h | 3 + libmaple/rcc.h | 34 ++++++++--- libmaple/rules.mk | 1 + libmaple/util.c | 11 ++-- libmaple/util.h | 1 + notes/fsmc.txt | 42 ++++++++++++++ support/ld/flash.ld | 4 +- support/ld/ram.ld | 2 +- 14 files changed, 441 insertions(+), 17 deletions(-) create mode 100644 examples/test-fsmc.cpp create mode 100644 libmaple/fsmc.c create mode 100644 libmaple/fsmc.h create mode 100644 notes/fsmc.txt (limited to 'support/ld/ram.ld') diff --git a/.gitignore b/.gitignore index c764a06..5d7d6ac 100644 --- a/.gitignore +++ b/.gitignore @@ -3,3 +3,4 @@ main.cpp libmaple.layout tags TAGS +*.swp \ No newline at end of file diff --git a/examples/test-fsmc.cpp b/examples/test-fsmc.cpp new file mode 100644 index 0000000..a4e43d6 --- /dev/null +++ b/examples/test-fsmc.cpp @@ -0,0 +1,149 @@ +/* ***************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * ****************************************************************************/ + +/** + * @brief Sample main.cpp file. Sends "Hello world!" out SPI1. + * + * SPI1 is set up to be a master transmitter at 4.5MHz, little endianness, + * and SPI mode 0. + * + * Pin 10 is used as Chip Select + * + */ + +#include "wirish.h" +#include "fsmc.h" +#include "rcc.h" +#include "gpio.h" + +#define LED_PIN 23 +#define DISC_PIN 14 + +// System control block registers +#define SCB_BASE (SCB_Reg*)(0xE000ED00) + +typedef struct { + volatile uint32 CPUID; + volatile uint32 ICSR; + volatile uint32 VTOR; + volatile uint32 AIRCR; + volatile uint32 SCR; + volatile uint32 CCR; + volatile uint32 SHPR1; + volatile uint32 SHPR2; + volatile uint32 SHPR3; + volatile uint32 SHCRS; + volatile uint32 CFSR; + volatile uint32 HFSR; + uint32 pad1; + volatile uint32 MMAR; + volatile uint32 BFAR; +} SCB_Reg; + +SCB_Reg *scb; + +uint16 *ptr; +int toggle = 0; + +void setup() { + uint32 id; + scb = (SCB_Reg*)SCB_BASE; + + rcc_enable_clk_fsmc(); + + pinMode(LED_PIN, OUTPUT); + pinMode(DISC_PIN, OUTPUT); + digitalWrite(DISC_PIN,1); + digitalWrite(LED_PIN,1); + + Serial1.begin(9600); + Serial1.println("Hello World!"); + + Serial1.print("Init... "); + fsmc_native_sram_init(); + Serial1.println("Done."); + + + ptr = (uint16*)(0x60000000); + //ptr = (uint16*)(0x68000000); + //ptr = (uint16*)(0x80000000); + Serial1.print("Writing... "); + + *ptr = 0xFFFF; + Serial1.println("Done."); + + Serial1.print("Reading... "); + id = *ptr; + Serial1.print("Done: "); + Serial1.println(id,BIN); + + /* + Serial1.print("CPUID is at: "); + id = (uint32)(&(scb->CPUID)); + Serial1.println(id,BIN); + */ + + Serial1.print("CPUID: "); + id = scb->CPUID; + Serial1.println(id,BIN); + Serial1.print("ICSR: "); + id = scb->ICSR; + Serial1.println(id,BIN); + Serial1.print("CFSR: "); + id = scb->CFSR; + Serial1.println(id,BIN); + Serial1.print("HFSR: "); + id = scb->HFSR; + Serial1.println(id,BIN); + Serial1.print("MMAR: "); + id = scb->MMAR; + Serial1.println(id,BIN); + Serial1.print("BFAR: "); + id = scb->BFAR; + Serial1.println(id,BIN); + +} + +void loop() { + digitalWrite(LED_PIN, toggle); + toggle ^= 1; + delay(100); + + *ptr = 0xFFFF; + /* + Serial1.print((uint32)(ptr),HEX); + Serial1.print(": "); + Serial1.println(*ptr,BIN); + */ +} + +int main(void) { + init(); + setup(); + + while (1) { + loop(); + } + return 0; +} diff --git a/libmaple/exc.c b/libmaple/exc.c index dd02476..3d01492 100644 --- a/libmaple/exc.c +++ b/libmaple/exc.c @@ -38,6 +38,7 @@ void NMIException(void) { } void HardFaultException(void) { + return; ASSERT(0); while(1) ; diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c new file mode 100644 index 0000000..17431f5 --- /dev/null +++ b/libmaple/fsmc.c @@ -0,0 +1,120 @@ + +/* ***************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * ****************************************************************************/ + +#include "libmaple.h" +#include "rcc.h" +#include "gpio.h" +#include "fsmc.h" + +#define FSMC_ADDSET 0x5 +#define FSMC_DATAST 0x5 + +// Setup the FSMC peripheral to use the SRAM chip on the maple native +// as an external segment of memory space. +// This is for the IS62WV51216BLL 8meg 55ns chip +void fsmc_native_sram_init(void) { + FSMC_Bank *bank; + + // First we setup all the GPIO pins. + // Data lines... + gpio_set_mode(GPIOD_BASE, 0, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 1, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 8, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 9, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 7, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 8, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 9, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP); + // Address lines... + gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 0, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 1, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 2, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 3, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 4, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 5, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOG_BASE, 0, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOG_BASE, 1, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOG_BASE, 2, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOG_BASE, 3, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOG_BASE, 4, MODE_AF_OUTPUT_PP); + gpio_set_mode(GPIOG_BASE, 5, MODE_AF_OUTPUT_PP); + // And control lines... + gpio_set_mode(GPIOD_BASE, 4, MODE_AF_OUTPUT_PP); // NOE + gpio_set_mode(GPIOD_BASE, 5, MODE_AF_OUTPUT_PP); // NWE + + gpio_set_mode(GPIOD_BASE, 7, MODE_AF_OUTPUT_PP); // NE1 + gpio_set_mode(GPIOG_BASE, 9, MODE_AF_OUTPUT_PP); // NE2 + gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP); // NE3 + gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP); // NE4 + + gpio_set_mode(GPIOE_BASE, 0, MODE_AF_OUTPUT_PP); // NBL0 + gpio_set_mode(GPIOE_BASE, 1, MODE_AF_OUTPUT_PP); // NBL1 + + // Then we configure the FSMC SRAM channel 1 peripheral + // (the SRAM part of the FSMC is "bank 1") + bank = (FSMC_Bank*)(FSMC1_BASE); + + // Everything else is cleared (BCR1) + bank->BCR = 0x0000; + + // Memory type is SRAM + bank->BCR &= ~(FSMC_BCR_MTYP); // '00' + + // Databus width is 16bits + bank->BCR &= ~(FSMC_BCR_MWID); + bank->BCR |= 0x1 << 4; // '01' + + // Memory is nonmultiplexed + bank->BCR &= ~(FSMC_BCR_MUXEN); // '0' + + // Set ADDSET + bank->BTR &= ~(FSMC_BTR_ADDSET); + bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET); + + // Set DATAST + bank->BTR &= ~(FSMC_BTR_DATAST); + bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8)); + + // Enable bank1 + bank->BCR |= FSMC_BCR_MBKEN; // '1' + + // FSMC_BWTR3 not used +} + diff --git a/libmaple/fsmc.h b/libmaple/fsmc.h new file mode 100644 index 0000000..0ac4084 --- /dev/null +++ b/libmaple/fsmc.h @@ -0,0 +1,86 @@ +/* ***************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * ****************************************************************************/ + +/* + * See ../notes/fsmc.txt for more info + */ + +#ifndef _FSMC_H_ +#define _FSMC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// There are 4 FSMC chip-select devices; here are the SRAM-specific registers +// for each + +#define FSMC1_BASE 0xA0000000 +#define FSMC2_BASE 0xA0000008 +#define FSMC3_BASE 0xA0000010 +#define FSMC4_BASE 0xA0000018 + +typedef struct { + volatile uint32 BCR; + volatile uint32 BTR; + //uint32 pad[62]; // double check this? + //__io uint32 BWTR; +} FSMC_Bank; + +// And here are the register bit ranges +#define FSMC_BCR_MBKEN 0b00000000000000000000000000000001 +#define FSMC_BCR_MUXEN 0b00000000000000000000000000000010 +#define FSMC_BCR_MTYP 0b00000000000000000000000000001100 +#define FSMC_BCR_MWID 0b00000000000000000000000000110000 +#define FSMC_BCR_FACCEN 0b00000000000000000000000001000000 +#define FSMC_BCR_BURSTEN 0b00000000000000000000000100000000 +#define FSMC_BCR_WAITPOL 0b00000000000000000000001000000000 +#define FSMC_BCR_WRAPMOD 0b00000000000000000000010000000000 +#define FSMC_BCR_WAITCFG 0b00000000000000000000100000000000 +#define FSMC_BCR_WREN 0b00000000000000000001000000000000 +#define FSMC_BCR_WAITEN 0b00000000000000000010000000000000 +#define FSMC_BCR_EXTMOD 0b00000000000000000100000000000000 +#define FSMC_BCR_CBURSTRW 0b00000000000010000000000000000000 +#define FSMC_BTR_ADDSET 0b00000000000000000000000000001111 +#define FSMC_BTR_ADDHOLD 0b00000000000000000000000011110000 +#define FSMC_BTR_DATAST 0b00000000000000001111111100000000 +#define FSMC_BTR_BUSTURN 0b00000000000011110000000000000000 +#define FSMC_BTR_CLKDIV 0b00000000111100000000000000000000 +#define FSMC_BTR_DATALAT 0b00001111000000000000000000000000 +#define FSMC_BTR_ACCMOD 0b00110000000000000000000000000000 +#define FSMC_BWTR_ADDSET 0b00000000000000000000000000001111 +#define FSMC_BWTR_ADDHLD 0b00000000000000000000000011110000 +#define FSMC_BWTR_DATAST 0b00000000000000001111111100000000 +#define FSMC_BWTR_CLKDIV 0b00000000111100000000000000000000 +#define FSMC_BWTR_DATLAT 0b00001111000000000000000000000000 +#define FSMC_BWTR_ACCMOD 0b00110000000000000000000000000000 + +void fsmc_native_sram_init(void); + +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif diff --git a/libmaple/gpio.c b/libmaple/gpio.c index 9334c1e..a47e623 100644 --- a/libmaple/gpio.c +++ b/libmaple/gpio.c @@ -37,6 +37,9 @@ void gpio_init(void) { rcc_enable_clk_gpiob(); rcc_enable_clk_gpioc(); rcc_enable_clk_gpiod(); + rcc_enable_clk_gpioe(); + rcc_enable_clk_gpiof(); + rcc_enable_clk_gpiog(); rcc_enable_clk_afio(); } diff --git a/libmaple/gpio.h b/libmaple/gpio.h index 74320e6..edbd4f0 100644 --- a/libmaple/gpio.h +++ b/libmaple/gpio.h @@ -48,6 +48,9 @@ #define GPIOB_BASE (GPIO_Port*)0x40010C00 #define GPIOC_BASE (GPIO_Port*)0x40011000 #define GPIOD_BASE (GPIO_Port*)0x40011400 +#define GPIOE_BASE (GPIO_Port*)0x40011800 +#define GPIOF_BASE (GPIO_Port*)0x40011C00 +#define GPIOG_BASE (GPIO_Port*)0x40012000 #define GPIO_SPEED_50MHZ (0x3) diff --git a/libmaple/rcc.h b/libmaple/rcc.h index 8e12032..8ad70e5 100644 --- a/libmaple/rcc.h +++ b/libmaple/rcc.h @@ -122,11 +122,13 @@ struct rcc_device { #define RCC_APB2ENR_TIM1EN BIT(11) #define RCC_APB2ENR_ADC2EN BIT(10) #define RCC_APB2ENR_ADC1EN BIT(9) -#define RCC_APB2ENR_IOEEN BIT(6) -#define RCC_APB2ENR_IODEN BIT(5) -#define RCC_APB2ENR_IOCEN BIT(4) -#define RCC_APB2ENR_IOBEN BIT(3) -#define RCC_APB2ENR_IOAEN BIT(2) +#define RCC_APB2ENR_IOPGEN BIT(8) +#define RCC_APB2ENR_IOPFEN BIT(7) +#define RCC_APB2ENR_IOPEEN BIT(6) +#define RCC_APB2ENR_IOPDEN BIT(5) +#define RCC_APB2ENR_IOPCEN BIT(4) +#define RCC_APB2ENR_IOPBEN BIT(3) +#define RCC_APB2ENR_IOPAEN BIT(2) #define RCC_APB2ENR_AFIOEN BIT(0) /* APB1 peripheral clock enable bits */ @@ -138,6 +140,17 @@ struct rcc_device { #define RCC_APB1ENR_SPI2EN BIT(14) #define RCC_APB1ENR_USB BIT(23) +/* AHB peripheral clock enable bits */ +#define RCC_AHBENR_DMA1EN BIT(0) +#define RCC_AHBENR_DMA2EN BIT(1) +#define RCC_AHBENR_SRAMEN BIT(2) +#define RCC_AHBENR_FLITFEN BIT(4) +#define RCC_AHBENR_CRCEN BIT(6) +#define RCC_AHBENR_FSMCEN BIT(8) +#define RCC_AHBENR_SDIOEN BIT(10) + +#define rcc_enable_clk_fsmc() __set_bits(RCC_AHBENR, RCC_AHBENR_FSMCEN) + #define rcc_enable_clk_spi1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_SPI1EN) #define rcc_enable_clk_spi2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_SPI2EN) @@ -146,10 +159,13 @@ struct rcc_device { #define rcc_enable_clk_timer3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM3EN) #define rcc_enable_clk_timer4() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM4EN) -#define rcc_enable_clk_gpioa() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOAEN) -#define rcc_enable_clk_gpiob() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOBEN) -#define rcc_enable_clk_gpioc() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOCEN) -#define rcc_enable_clk_gpiod() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IODEN) +#define rcc_enable_clk_gpioa() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPAEN) +#define rcc_enable_clk_gpiob() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPBEN) +#define rcc_enable_clk_gpioc() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPCEN) +#define rcc_enable_clk_gpiod() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPDEN) +#define rcc_enable_clk_gpioe() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPEEN) +#define rcc_enable_clk_gpiof() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPFEN) +#define rcc_enable_clk_gpiog() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPGEN) #define rcc_enable_clk_afio() __set_bits(RCC_APB2ENR, RCC_APB2ENR_AFIOEN) #define rcc_enable_clk_usart1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_USART1EN) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 60673fe..db9540a 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -25,6 +25,7 @@ cSRCS_$(d) := systick.c \ rcc.c \ flash.c \ spi.c \ + fsmc.c \ usb/usb.c \ usb/usb_callbacks.c \ usb/usb_hardware.c \ diff --git a/libmaple/util.c b/libmaple/util.c index 36173ee..8c25257 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -36,11 +36,11 @@ #include "adc.h" #include "timers.h" -#define ERROR_LED_PORT GPIOA_BASE -#define ERROR_LED_PIN 5 -#define ERROR_USART_NUM 2 +#define ERROR_LED_PORT GPIOC_BASE +#define ERROR_LED_PIN 15 +#define ERROR_USART_NUM 1 #define ERROR_USART_BAUD 9600 -#define ERROR_TX_PIN 2 +#define ERROR_TX_PIN 10 #define ERROR_TX_PORT GPIOA_BASE /* Error assert + fade */ @@ -76,7 +76,8 @@ void _fail(const char* file, int line, const char* exp) { usart_putstr(ERROR_USART_NUM, ": "); usart_putudec(ERROR_USART_NUM, line); usart_putc(ERROR_USART_NUM, '\n'); - + usart_putc(ERROR_USART_NUM, '\r'); + /* Turn on the error LED */ gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_MODE_OUTPUT_PP); diff --git a/libmaple/util.h b/libmaple/util.h index a18fa84..1aae7bd 100644 --- a/libmaple/util.h +++ b/libmaple/util.h @@ -48,6 +48,7 @@ #define BITBAND_PERI_BASE 0x42000000 #define BITBAND_PERI(a,b) ((BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4))) // Convert PERI address + #define COUNTFLAG *((volatile unsigned char*) (BITBAND_PERI(SYSTICK_CSR,2))) #define REG_SET(reg, val) (*(volatile uint32*)(reg) = (val)) diff --git a/notes/fsmc.txt b/notes/fsmc.txt new file mode 100644 index 0000000..583dba2 --- /dev/null +++ b/notes/fsmc.txt @@ -0,0 +1,42 @@ + +FSMC notes (for maple native) +------------------------------------------------------------------------------- + +There is an application note for all this which is helpful; see the ST website. + +Chip details + IS62WV51216BLL + 512k x 16 + 19 address input + 16 data inputs + +For simple debugging, i'm going to set all the access parameters to maximum +time values (aka, slowest). I'm going to use not-extended mode 1 for +read/write. + +Steps from application note: + +- enable bank3: BCR3_MBKEN = '1' +- memory type is SRAM: BCR3_MTYP = '00' +- databuse weidth is 16bits: BCR3_MWID = '01' +- memory is nonmultiplexed: BCR3_MEXEN is reset (= '0') +- everything else is cleared + +Parameters: + + t_wc (write cycle) = 55ns + t_rc (write cycle) = 55ns + t_pwe1 (write enable low pulse) = 40ns + t_aa (address access) = 55ns + +So address setup (ADDSET) = 0x0, data setup (DATAST) = 0x3 + +Using bank1, NOR/PSRAM1 memory starts at 0x60000000. + +Oops, obviously have to turn on the clock for all those GPIO pins... + +Not-super-helpful-link: +http://www.keil.com/support/man/docs/mcbstm32e/mcbstm32e_to_xmemory.htm + +PG9 (which is NE2) is twiddling on reset? + diff --git a/support/ld/flash.ld b/support/ld/flash.ld index b66bdef..473f5a1 100644 --- a/support/ld/flash.ld +++ b/support/ld/flash.ld @@ -25,8 +25,8 @@ /* Define memory spaces. */ MEMORY { - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 500K } OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") diff --git a/support/ld/ram.ld b/support/ld/ram.ld index 872d6f2..d2c05c0 100644 --- a/support/ld/ram.ld +++ b/support/ld/ram.ld @@ -26,7 +26,7 @@ MEMORY { ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 512K } -- cgit v1.2.3 From 0ccec95446d4c7f3ea47a46d267c791fb22bb8d4 Mon Sep 17 00:00:00 2001 From: bnewbold Date: Tue, 31 Aug 2010 22:05:39 -0400 Subject: Portability fixes Still not working but fixed a lot of merge errors --- Makefile | 2 +- libmaple/libmaple.h | 33 +++++++++++++-------------------- libmaple/nvic.c | 7 ++++++- libmaple/nvic.h | 1 + libmaple/usb/usb_config.h | 3 --- libmaple/util.c | 6 +++--- support/ld/flash.ld | 4 ++++ support/ld/jtag.ld | 8 ++++++-- support/ld/ram.ld | 6 +++++- support/make/build-targets.mk | 5 +++-- support/openocd/flash.cfg | 6 +++++- wirish/wirish.c | 2 +- 12 files changed, 48 insertions(+), 35 deletions(-) (limited to 'support/ld/ram.ld') diff --git a/Makefile b/Makefile index 28cd4f3..de6c625 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ # Valid BOARDs: maple, maple_native, ... BOARD ?= maple -MEMORY_TARGET ?= flash +MEMORY_TARGET ?= ram # USB ID for DFU upload VENDOR_ID := 1EAF diff --git a/libmaple/libmaple.h b/libmaple/libmaple.h index 8e072c3..437566f 100644 --- a/libmaple/libmaple.h +++ b/libmaple/libmaple.h @@ -34,7 +34,7 @@ #include "libmaple_types.h" // General configuration -#define MAPLE_DEBUG 0 +#define MAPLE_DEBUG 1 // MCU-specific configuration #ifdef MCU_STM32F103RB // eg, LeafLabs Maple @@ -48,16 +48,21 @@ // Number of timer devices ports, definately used #define NR_TIMERS 4 + // Number of USART ports + #define NR_USART 3 + // Has an FSMC bus? - #define NR_FSMC 1 + #define NR_FSMC 0 // Has an FSMC bus? - #define NR_DAC_PINS 2 + #define NR_DAC_PINS 0 // USB Identifier numbers // Descriptor strings must be modified by hand in usb/descriptors.c for now #define VCOM_ID_VENDOR 0x1EAF #define VCOM_ID_PRODUCT 0x0004 + #define USB_DISC_BANK GPIOC_BASE + #define USB_DISC_PIN 12 #define USB_CONFIG_MAX_POWER (100 >> 1) #define RESET_DELAY (100) @@ -86,36 +91,26 @@ #define BITBAND_PERI_BASE 0x42000000 #endif -#ifdef MCU_STM32F103ZE // eg, LeafLabs Maple Native - - // Number of GPIO ports (GPIOA, GPIOB, etc), definately used +#ifdef MCU_STM32F103ZE + // eg, LeafLabs Maple Native #define NR_GPIO_PORTS 7 - - // Total number of GPIO pins #define NR_GPIO_PINS 63 - - // Number of timer devices ports, definately used #define NR_TIMERS 8 - - // Has an FSMC bus? + #define NR_USART 3 #define NR_FSMC 1 - - // Has an FSMC bus? #define NR_DAC_PINS 2 - // USB Identifier numbers - // Descriptor strings must be modified by hand in usb/descriptors.c for now #define VCOM_ID_VENDOR 0x1EAF #define VCOM_ID_PRODUCT 0x0004 + #define USB_DISC_BANK GPIOB_BASE + #define USB_DISC_PIN 8 #define USB_CONFIG_MAX_POWER (100 >> 1) #define RESET_DELAY (100) - // Where to put usercode (based on space reserved for bootloader) #define USER_ADDR_ROM 0x08005000 #define USER_ADDR_RAM 0x20000C00 #define STACK_TOP 0x20000800 - // Debug port settings (from ASSERT) #define ERROR_LED_PORT GPIOC_BASE #define ERROR_LED_PIN 15 #define ERROR_USART_NUM 1 @@ -123,12 +118,10 @@ #define ERROR_TX_PIN 10 #define ERROR_TX_PORT GPIOA_BASE - // Just in case, most boards have at least some memory #ifndef RAMSIZE # define RAMSIZE (caddr_t)0x50000 #endif - // Bitbanded Memory sections #define BITBAND_SRAM_REF 0x20000000 #define BITBAND_SRAM_BASE 0x22000000 #define BITBAND_PERI_REF 0x40000000 diff --git a/libmaple/nvic.c b/libmaple/nvic.c index 7aef26d..60e7eac 100644 --- a/libmaple/nvic.c +++ b/libmaple/nvic.c @@ -65,7 +65,12 @@ void nvic_irq_disable(uint32 n) { } } - +void nvic_irq_disable_all(void) { + short n; + for(n=0; n<65; n++) { + nvic_irq_disable(n); + } +} /** * @brief Initialice the NVIC at address addr diff --git a/libmaple/nvic.h b/libmaple/nvic.h index a24086a..4e425c5 100644 --- a/libmaple/nvic.h +++ b/libmaple/nvic.h @@ -78,6 +78,7 @@ enum { void nvic_init(void); void nvic_irq_enable(uint32 device); void nvic_irq_disable(uint32 device); +void nvic_irq_disable_all(void); #ifdef __cplusplus } diff --git a/libmaple/usb/usb_config.h b/libmaple/usb/usb_config.h index 27294dc..ba05d42 100644 --- a/libmaple/usb/usb_config.h +++ b/libmaple/usb/usb_config.h @@ -40,9 +40,6 @@ CNTR_ESOFM | \ CNTR_RESETM ) -#define USB_DISC_BANK GPIOB_BASE -#define USB_DISC_PIN 8 - #define F_SUSPEND_ENABLED 1 #endif diff --git a/libmaple/util.c b/libmaple/util.c index 61beab8..a747948 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -44,7 +44,7 @@ void _fail(const char* file, int line, const char* exp) { uint32 i = 0; /* Turn off interrupts */ - nvic_disable_interrupts(); + nvic_irq_disable_all(); /* Turn off timers */ timer_disable_all(); @@ -73,8 +73,8 @@ void _fail(const char* file, int line, const char* exp) { gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_MODE_OUTPUT_PP); /* Turn the USB interrupt back on so the bootloader keeps on functioning */ - nvic_enable_interrupt(NVIC_INT_USBHP); - nvic_enable_interrupt(NVIC_INT_USBLP); + nvic_irq_enable(NVIC_INT_USBHP); + nvic_irq_enable(NVIC_INT_USBLP); /* Error fade */ while (1) { diff --git a/support/ld/flash.ld b/support/ld/flash.ld index 7e1e453..d05aa6c 100644 --- a/support/ld/flash.ld +++ b/support/ld/flash.ld @@ -25,8 +25,12 @@ /* Define memory spaces. */ MEMORY { + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K +/* native ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K rom (rx) : ORIGIN = 0x08005000, LENGTH = 500K +*/ } OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") diff --git a/support/ld/jtag.ld b/support/ld/jtag.ld index 890f18a..2ba3ce6 100644 --- a/support/ld/jtag.ld +++ b/support/ld/jtag.ld @@ -8,8 +8,12 @@ /* Define memory spaces. */ MEMORY { - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K +/* native + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 500K +*/ } OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") diff --git a/support/ld/ram.ld b/support/ld/ram.ld index 168c1da..b9dd4ee 100644 --- a/support/ld/ram.ld +++ b/support/ld/ram.ld @@ -25,8 +25,12 @@ /* Define memory spaces. */ MEMORY { + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K +/* native ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 512K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K +*/ } diff --git a/support/make/build-targets.mk b/support/make/build-targets.mk index 083976a..448b1ee 100644 --- a/support/make/build-targets.mk +++ b/support/make/build-targets.mk @@ -24,8 +24,9 @@ MSG_INFO: @echo "================================================================================" @echo "" @echo " Build info:" - @echo " BOARD:" $(BOARD) - @echo " MEMORY_TARGET:" $(MEMORY_TARGET) + @echo " BOARD: " $(BOARD) + @echo " MCU: " $(MCU) + @echo " MEMORY_TARGET: " $(MEMORY_TARGET) @echo "" @echo " See 'make help' for all possible targets" @echo "" diff --git a/support/openocd/flash.cfg b/support/openocd/flash.cfg index 25fe23f..fcd9561 100644 --- a/support/openocd/flash.cfg +++ b/support/openocd/flash.cfg @@ -62,6 +62,8 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 +# TODO: native $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME @@ -70,7 +72,9 @@ proc flash_chip {} { echo "Halting..." halt echo "Erasing..." - flash erase_address 0x08000000 0x80000 + flash erase_address 0x08000000 0x20000 + # TODO: native + #flash erase_address 0x08000000 0x80000 echo "Flashing image..." flash write_bank 0 build/maple.bin 0 echo "Verifying image..." diff --git a/wirish/wirish.c b/wirish/wirish.c index 41f5db4..9f3b19e 100644 --- a/wirish/wirish.c +++ b/wirish/wirish.c @@ -48,7 +48,7 @@ void init(void) { flash_enable_prefetch(); flash_set_latency(FLASH_WAIT_STATE_2); - #if HAS_FSMC + #if NR_FSMC > 0 fsmc_native_sram_init(); #endif -- cgit v1.2.3