From 214941537f2211d5e2ef16e34440485d7e872d1a Mon Sep 17 00:00:00 2001
From: Perry Hung <iperry@gmail.com>
Date: Sun, 27 Feb 2011 15:49:51 -0500
Subject: Refactor linker scripts. Rename irq and exception handlers.

Add common linker scripts for ram and rom. Add medium and high density
libraries for libcs3.
---
 support/ld/libcs3_stm32_src/Makefile             |  35 ++++
 support/ld/libcs3_stm32_src/start.S              |  27 +++
 support/ld/libcs3_stm32_src/start_c.c            |  58 ++++++
 support/ld/libcs3_stm32_src/stm32_isrs.S         | 235 +++++++++++++++++++++++
 support/ld/libcs3_stm32_src/stm32_vector_table.S |  90 +++++++++
 5 files changed, 445 insertions(+)
 create mode 100644 support/ld/libcs3_stm32_src/Makefile
 create mode 100644 support/ld/libcs3_stm32_src/start.S
 create mode 100644 support/ld/libcs3_stm32_src/start_c.c
 create mode 100644 support/ld/libcs3_stm32_src/stm32_isrs.S
 create mode 100644 support/ld/libcs3_stm32_src/stm32_vector_table.S

(limited to 'support/ld/libcs3_stm32_src')

diff --git a/support/ld/libcs3_stm32_src/Makefile b/support/ld/libcs3_stm32_src/Makefile
new file mode 100644
index 0000000..d5275b9
--- /dev/null
+++ b/support/ld/libcs3_stm32_src/Makefile
@@ -0,0 +1,35 @@
+# setup environment
+
+TARGET_ARCH = -mcpu=cortex-m3 -mthumb
+
+CC = arm-none-eabi-gcc
+CFLAGS =
+
+AS = $(CC) -x assembler-with-cpp -c $(TARGET_ARCH)
+ASFLAGS =
+
+AR = arm-none-eabi-ar
+ARFLAGS = cr
+
+LIB_OBJS = stm32_vector_table.o stm32_isrs.o start.o start_c.o
+
+help:
+	@echo "Targets:"
+	@echo "\t medium-density: Target medium density chips (e.g. Maple)"
+	@echo "\t high-density: Target high density chips (e.g. Maple-native)"
+
+.PHONY: help medium high
+
+medium-density: $(LIB_OBJS)
+	$(AR) $(ARFLAGS) libcs3_stm32_med_density.a $(LIB_OBJS)
+	rm -f $(LIB_OBJS)
+
+high-density: CFLAGS := -DSTM32_HIGH_DENSITY
+high-density: $(LIB_OBJS)
+	$(AR) $(ARFLAGS) libcs3_stm32_high_density.a $(LIB_OBJS)
+	rm -f $(LIB_OBJS)
+
+# clean
+.PHONY: clean
+clean:
+	-rm -f $(LIB_OBJS) *.a
diff --git a/support/ld/libcs3_stm32_src/start.S b/support/ld/libcs3_stm32_src/start.S
new file mode 100644
index 0000000..ae75747
--- /dev/null
+++ b/support/ld/libcs3_stm32_src/start.S
@@ -0,0 +1,27 @@
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+	.text
+	.code 16
+	.thumb_func
+
+	.globl _start
+	.type _start, %function
+_start:
+	.fnstart
+	ldr	r1,=__cs3_stack
+	mov	sp,r1
+	ldr	r1,=__cs3_start_c
+	bx	r1
+	.pool
+	.cantunwind
+	.fnend
diff --git a/support/ld/libcs3_stm32_src/start_c.c b/support/ld/libcs3_stm32_src/start_c.c
new file mode 100644
index 0000000..dff9fa3
--- /dev/null
+++ b/support/ld/libcs3_stm32_src/start_c.c
@@ -0,0 +1,58 @@
+/* CS3 start_c routine.
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include "cs3.h"
+
+extern void __libc_init_array (void);
+
+extern int main (int, char **, char **);
+
+extern void exit (int) __attribute__ ((noreturn, weak));
+
+void  __attribute ((noreturn))
+__cs3_start_c (void)
+{
+  unsigned regions = __cs3_region_num;
+  const struct __cs3_region *rptr = __cs3_regions;
+  int exit_code;
+
+  /* Initialize memory */
+  for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++)
+    {
+      long long *src = (long long *)rptr->init;
+      long long *dst = (long long *)rptr->data;
+      unsigned limit = rptr->init_size;
+      unsigned count;
+
+      if (src != dst)
+	for (count = 0; count != limit; count += sizeof (long long))
+	  *dst++ = *src++;
+      else
+	dst = (long long *)((char *)dst + limit);
+      limit = rptr->zero_size;
+      for (count = 0; count != limit; count += sizeof (long long))
+	*dst++ = 0;
+    }
+
+  /* Run initializers.  */
+  __libc_init_array ();
+
+  exit_code = main (0, NULL, NULL);
+  if (exit)
+    exit (exit_code);
+  /* If exit is NULL, make sure we don't return. */
+  for (;;)
+    continue;
+}
diff --git a/support/ld/libcs3_stm32_src/stm32_isrs.S b/support/ld/libcs3_stm32_src/stm32_isrs.S
new file mode 100644
index 0000000..f95468c
--- /dev/null
+++ b/support/ld/libcs3_stm32_src/stm32_isrs.S
@@ -0,0 +1,235 @@
+/* STM32 ISR weak declarations */
+
+	.thumb
+
+/* Default handler for all non-overridden interrupts and exceptions */
+	.globl	__default_handler
+	.type	__default_handler, %function
+
+__default_handler:
+	b .
+
+	.weak	__exc_nmi
+	.globl	__exc_nmi
+	.set	__exc_nmi, __default_handler
+	.weak	__exc_hardfault
+	.globl	__exc_hardfault
+	.set	__exc_hardfault, __default_handler
+	.weak	__exc_memmanage
+	.globl	__exc_memmanage
+	.set	__exc_memmanage, __default_handler
+	.weak	__exc_busfault
+	.globl	__exc_busfault
+	.set	__exc_busfault, __default_handler
+	.weak	__exc_usagefault
+	.globl	__exc_usagefault
+	.set	__exc_usagefault, __default_handler
+	.weak	__stm32reservedexception7
+	.globl	__stm32reservedexception7
+	.set	__stm32reservedexception7, __default_handler
+	.weak	__stm32reservedexception8
+	.globl	__stm32reservedexception8
+	.set	__stm32reservedexception8, __default_handler
+	.weak	__stm32reservedexception9
+	.globl	__stm32reservedexception9
+	.set	__stm32reservedexception9, __default_handler
+	.weak	__stm32reservedexception10
+	.globl	__stm32reservedexception10
+	.set	__stm32reservedexception10, __default_handler
+	.weak	__exc_svc
+	.globl	__exc_svc
+	.set	__exc_svc, __default_handler
+	.weak	__exc_debug_monitor
+	.globl	__exc_debug_monitor
+	.set	__exc_debug_monitor, __default_handler
+	.weak	__stm32reservedexception13
+	.globl	__stm32reservedexception13
+	.set	__stm32reservedexception13, __default_handler
+	.weak	__exc_pendsv
+	.globl	__exc_pendsv
+	.set	__exc_pendsv, __default_handler
+	.weak	__exc_systick
+	.globl	__exc_systick
+	.set	__exc_systick, __default_handler
+	.weak	__irq_wwdg
+	.globl	__irq_wwdg
+	.set	__irq_wwdg, __default_handler
+	.weak	__irq_pvd
+	.globl	__irq_pvd
+	.set	__irq_pvd, __default_handler
+	.weak	__irq_tamper
+	.globl	__irq_tamper
+	.set	__irq_tamper, __default_handler
+	.weak	__irq_rtc
+	.globl	__irq_rtc
+	.set	__irq_rtc, __default_handler
+	.weak	__irq_flash
+	.globl	__irq_flash
+	.set	__irq_flash, __default_handler
+	.weak	__irq_rcc
+	.globl	__irq_rcc
+	.set	__irq_rcc, __default_handler
+	.weak	__irq_exti0
+	.globl	__irq_exti0
+	.set	__irq_exti0, __default_handler
+	.weak	__irq_exti1
+	.globl	__irq_exti1
+	.set	__irq_exti1, __default_handler
+	.weak	__irq_exti2
+	.globl	__irq_exti2
+	.set	__irq_exti2, __default_handler
+	.weak	__irq_exti3
+	.globl	__irq_exti3
+	.set	__irq_exti3, __default_handler
+	.weak	__irq_exti4
+	.globl	__irq_exti4
+	.set	__irq_exti4, __default_handler
+	.weak	__irq_dma1_channel1
+	.globl	__irq_dma1_channel1
+	.set	__irq_dma1_channel1, __default_handler
+	.weak	__irq_dma1_channel2
+	.globl	__irq_dma1_channel2
+	.set	__irq_dma1_channel2, __default_handler
+	.weak	__irq_dma1_channel3
+	.globl	__irq_dma1_channel3
+	.set	__irq_dma1_channel3, __default_handler
+	.weak	__irq_dma1_channel4
+	.globl	__irq_dma1_channel4
+	.set	__irq_dma1_channel4, __default_handler
+	.weak	__irq_dma1_channel5
+	.globl	__irq_dma1_channel5
+	.set	__irq_dma1_channel5, __default_handler
+	.weak	__irq_dma1_channel6
+	.globl	__irq_dma1_channel6
+	.set	__irq_dma1_channel6, __default_handler
+	.weak	__irq_dma1_channel7
+	.globl	__irq_dma1_channel7
+	.set	__irq_dma1_channel7, __default_handler
+	.weak	__irq_adc
+	.globl	__irq_adc
+	.set	__irq_adc, __default_handler
+	.weak	__irq_usb_hp_can_tx
+	.globl	__irq_usb_hp_can_tx
+	.set	__irq_usb_hp_can_tx, __default_handler
+	.weak	__irq_usb_lp_can_rx0
+	.globl	__irq_usb_lp_can_rx0
+	.set	__irq_usb_lp_can_rx0, __default_handler
+	.weak	__irq_can_rx1
+	.globl	__irq_can_rx1
+	.set	__irq_can_rx1, __default_handler
+	.weak	__irq_can_sce
+	.globl	__irq_can_sce
+	.set	__irq_can_sce, __default_handler
+	.weak	__irq_exti9_5
+	.globl	__irq_exti9_5
+	.set	__irq_exti9_5, __default_handler
+	.weak	__irq_tim1_brk
+	.globl	__irq_tim1_brk
+	.set	__irq_tim1_brk, __default_handler
+	.weak	__irq_tim1_up
+	.globl	__irq_tim1_up
+	.set	__irq_tim1_up, __default_handler
+	.weak	__irq_tim1_trg_com
+	.globl	__irq_tim1_trg_com
+	.set	__irq_tim1_trg_com, __default_handler
+	.weak	__irq_tim1_cc
+	.globl	__irq_tim1_cc
+	.set	__irq_tim1_cc, __default_handler
+	.weak	__irq_tim2
+	.globl	__irq_tim2
+	.set	__irq_tim2, __default_handler
+	.weak	__irq_tim3
+	.globl	__irq_tim3
+	.set	__irq_tim3, __default_handler
+	.weak	__irq_tim4
+	.globl	__irq_tim4
+	.set	__irq_tim4, __default_handler
+	.weak	__irq_i2c1_ev
+	.globl	__irq_i2c1_ev
+	.set	__irq_i2c1_ev, __default_handler
+	.weak	__irq_i2c1_er
+	.globl	__irq_i2c1_er
+	.set	__irq_i2c1_er, __default_handler
+	.weak	__irq_i2c2_ev
+	.globl	__irq_i2c2_ev
+	.set	__irq_i2c2_ev, __default_handler
+	.weak	__irq_i2c2_er
+	.globl	__irq_i2c2_er
+	.set	__irq_i2c2_er, __default_handler
+	.weak	__irq_spi1
+	.globl	__irq_spi1
+	.set	__irq_spi1, __default_handler
+	.weak	__irq_spi2
+	.globl	__irq_spi2
+	.set	__irq_spi2, __default_handler
+	.weak	__irq_usart1
+	.globl	__irq_usart1
+	.set	__irq_usart1, __default_handler
+	.weak	__irq_usart2
+	.globl	__irq_usart2
+	.set	__irq_usart2, __default_handler
+	.weak	__irq_usart3
+	.globl	__irq_usart3
+	.set	__irq_usart3, __default_handler
+	.weak	__irq_exti15_10
+	.globl	__irq_exti15_10
+	.set	__irq_exti15_10, __default_handler
+	.weak	__irq_rtcalarm
+	.globl	__irq_rtcalarm
+	.set	__irq_rtcalarm, __default_handler
+	.weak	__irq_usbwakeup
+	.globl	__irq_usbwakeup
+	.set	__irq_usbwakeup, __default_handler
+#if defined (STM32_HIGH_DENSITY)
+	.weak	__irq_tim8_brk
+	.globl	__irq_tim8_brk
+	.set	__irq_tim8_brk, __default_handler
+	.weak	__irq_tim8_up
+	.globl	__irq_tim8_up
+	.set	__irq_tim8_up, __default_handler
+	.weak	__irq_tim8_trg_com
+	.globl	__irq_tim8_trg_com
+	.set	__irq_tim8_trg_com, __default_handler
+	.weak	__irq_tim8_cc
+	.globl	__irq_tim8_cc
+	.set	__irq_tim8_cc, __default_handler
+	.weak	__irq_adc3
+	.globl	__irq_adc3
+	.set	__irq_adc3, __default_handler
+	.weak	__irq_fsmc
+	.globl	__irq_fsmc
+	.set	__irq_fsmc, __default_handler
+	.weak	__irq_sdio
+	.globl	__irq_sdio
+	.set	__irq_sdio, __default_handler
+	.weak	__irq_tim5
+	.globl	__irq_tim5
+	.set	__irq_tim5, __default_handler
+	.weak	__irq_spi3
+	.globl	__irq_spi3
+	.set	__irq_spi3, __default_handler
+	.weak	__irq_uart4
+	.globl	__irq_uart4
+	.set	__irq_uart4, __default_handler
+	.weak	__irq_uart5
+	.globl	__irq_uart5
+	.set	__irq_uart5, __default_handler
+	.weak	__irq_tim6
+	.globl	__irq_tim6
+	.set	__irq_tim6, __default_handler
+	.weak	__irq_tim7
+	.globl	__irq_tim7
+	.set	__irq_tim7, __default_handler
+	.weak	__irq_dma2_channel1
+	.globl	__irq_dma2_channel1
+	.set	__irq_dma2_channel1, __default_handler
+	.weak	__irq_dma2_channel2
+	.globl	__irq_dma2_channel2
+	.set	__irq_dma2_channel2, __default_handler
+	.weak	__irq_dma2_channel3
+	.globl	__irq_dma2_channel3
+	.set	__irq_dma2_channel3, __default_handler
+	.weak	__irq_dma2_channel4_5
+	.globl	__irq_dma2_channel4_5
+	.set	__irq_dma2_channel4_5, __default_handler
+#endif /* STM32_HIGH_DENSITY */
diff --git a/support/ld/libcs3_stm32_src/stm32_vector_table.S b/support/ld/libcs3_stm32_src/stm32_vector_table.S
new file mode 100644
index 0000000..8c71cb5
--- /dev/null
+++ b/support/ld/libcs3_stm32_src/stm32_vector_table.S
@@ -0,0 +1,90 @@
+/* STM32 vector table */
+
+	.section	".cs3.interrupt_vector"
+
+	.globl	__cs3_stm32_vector_table
+	.type	__cs3_stm32_vector_table, %object
+
+__cs3_stm32_vector_table:
+/* CM3 core interrupts */
+	.long	__cs3_stack
+	.long	__cs3_reset
+	.long	__exc_nmi
+	.long	__exc_hardfault
+	.long	__exc_memmanage
+	.long	__exc_busfault
+	.long	__exc_usagefault
+	.long	__stm32reservedexception7
+	.long	__stm32reservedexception8
+	.long	__stm32reservedexception9
+	.long	__stm32reservedexception10
+	.long	__exc_svc
+	.long	__exc_debug_monitor
+	.long	__stm32reservedexception13
+	.long	__exc_pendsv
+	.long	__exc_systick
+/* Peripheral interrupts */
+	.long	__irq_wwdg
+	.long	__irq_pvd
+	.long	__irq_tamper
+	.long	__irq_rtc
+	.long	__irq_flash
+	.long	__irq_rcc
+	.long	__irq_exti0
+	.long	__irq_exti1
+	.long	__irq_exti2
+	.long	__irq_exti3
+	.long	__irq_exti4
+	.long	__irq_dma1_channel1
+	.long	__irq_dma1_channel2
+	.long	__irq_dma1_channel3
+	.long	__irq_dma1_channel4
+	.long	__irq_dma1_channel5
+	.long	__irq_dma1_channel6
+	.long	__irq_dma1_channel7
+	.long	__irq_adc
+	.long	__irq_usb_hp_can_tx
+	.long	__irq_usb_lp_can_rx0
+	.long	__irq_can_rx1
+	.long	__irq_can_sce
+	.long	__irq_exti9_5
+	.long	__irq_tim1_brk
+	.long	__irq_tim1_up
+	.long	__irq_tim1_trg_com
+	.long	__irq_tim1_cc
+	.long	__irq_tim2
+	.long	__irq_tim3
+	.long	__irq_tim4
+	.long	__irq_i2c1_ev
+	.long	__irq_i2c1_er
+	.long	__irq_i2c2_ev
+	.long	__irq_i2c2_er
+	.long	__irq_spi1
+	.long	__irq_spi2
+	.long	__irq_usart1
+	.long	__irq_usart2
+	.long	__irq_usart3
+	.long	__irq_exti15_10
+	.long	__irq_rtcalarm
+	.long	__irq_usbwakeup
+#if defined (STM32_HIGH_DENSITY)
+	.weak	__irq_tim8_brk
+	.weak	__irq_tim8_up
+	.weak	__irq_tim8_trg_com
+	.weak	__irq_tim8_cc
+	.weak	__irq_adc3
+	.weak	__irq_fsmc
+	.weak	__irq_sdio
+	.weak	__irq_tim5
+	.weak	__irq_spi3
+	.weak	__irq_uart4
+	.weak	__irq_uart5
+	.weak	__irq_tim6
+	.weak	__irq_tim7
+	.weak	__irq_dma2_channel1
+	.weak	__irq_dma2_channel2
+	.weak	__irq_dma2_channel3
+	.weak	__irq_dma2_channel4_5
+#endif /* STM32_HIGH_DENSITY */
+
+	.size	__cs3_stm32_vector_table, . - __cs3_stm32_vector_table
-- 
cgit v1.2.3


From c0cb60b3ff57f60b618433a507116aeac2c21075 Mon Sep 17 00:00:00 2001
From: Perry Hung <iperry@gmail.com>
Date: Tue, 15 Mar 2011 19:36:46 -0400
Subject: support: linker: Fix high density vector table

Entries for high-density interrupt vectors were incorrectly declared to
be .weak instead of .long.

Thanks redfox74!
---
 support/ld/libcs3_stm32_high_density.a           | Bin 9464 -> 9464 bytes
 support/ld/libcs3_stm32_src/stm32_vector_table.S |  34 +++++++++++------------
 2 files changed, 17 insertions(+), 17 deletions(-)

(limited to 'support/ld/libcs3_stm32_src')

diff --git a/support/ld/libcs3_stm32_high_density.a b/support/ld/libcs3_stm32_high_density.a
index 472ed28..a09d7f0 100644
Binary files a/support/ld/libcs3_stm32_high_density.a and b/support/ld/libcs3_stm32_high_density.a differ
diff --git a/support/ld/libcs3_stm32_src/stm32_vector_table.S b/support/ld/libcs3_stm32_src/stm32_vector_table.S
index 8c71cb5..c3f0fc7 100644
--- a/support/ld/libcs3_stm32_src/stm32_vector_table.S
+++ b/support/ld/libcs3_stm32_src/stm32_vector_table.S
@@ -68,23 +68,23 @@ __cs3_stm32_vector_table:
 	.long	__irq_rtcalarm
 	.long	__irq_usbwakeup
 #if defined (STM32_HIGH_DENSITY)
-	.weak	__irq_tim8_brk
-	.weak	__irq_tim8_up
-	.weak	__irq_tim8_trg_com
-	.weak	__irq_tim8_cc
-	.weak	__irq_adc3
-	.weak	__irq_fsmc
-	.weak	__irq_sdio
-	.weak	__irq_tim5
-	.weak	__irq_spi3
-	.weak	__irq_uart4
-	.weak	__irq_uart5
-	.weak	__irq_tim6
-	.weak	__irq_tim7
-	.weak	__irq_dma2_channel1
-	.weak	__irq_dma2_channel2
-	.weak	__irq_dma2_channel3
-	.weak	__irq_dma2_channel4_5
+	.long	__irq_tim8_brk
+	.long	__irq_tim8_up
+	.long	__irq_tim8_trg_com
+	.long	__irq_tim8_cc
+	.long	__irq_adc3
+	.long	__irq_fsmc
+	.long	__irq_sdio
+	.long	__irq_tim5
+	.long	__irq_spi3
+	.long	__irq_uart4
+	.long	__irq_uart5
+	.long	__irq_tim6
+	.long	__irq_tim7
+	.long	__irq_dma2_channel1
+	.long	__irq_dma2_channel2
+	.long	__irq_dma2_channel3
+	.long	__irq_dma2_channel4_5
 #endif /* STM32_HIGH_DENSITY */
 
 	.size	__cs3_stm32_vector_table, . - __cs3_stm32_vector_table
-- 
cgit v1.2.3