From 32e57dac2e61e79b029593eb4d34d727bcc10678 Mon Sep 17 00:00:00 2001 From: iperry Date: Thu, 17 Dec 2009 02:37:07 +0000 Subject: Initial commit of library code, moved from leaftest repo git-svn-id: https://leaflabs.googlecode.com/svn/trunk/library@69 749a229e-a60e-11de-b98f-4500b42dc123 --- src/stm32lib/examples/TIM/6Steps/main.c | 302 ++++++++++++++++++++++++++++++++ 1 file changed, 302 insertions(+) create mode 100755 src/stm32lib/examples/TIM/6Steps/main.c (limited to 'src/stm32lib/examples/TIM/6Steps/main.c') diff --git a/src/stm32lib/examples/TIM/6Steps/main.c b/src/stm32lib/examples/TIM/6Steps/main.c new file mode 100755 index 0000000..b20bf2e --- /dev/null +++ b/src/stm32lib/examples/TIM/6Steps/main.c @@ -0,0 +1,302 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : main.c +* Author : MCD Application Team +* Version : V2.0.1 +* Date : 06/13/2008 +* Description : Main program body +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +TIM_BDTRInitTypeDef TIM_BDTRInitStructure; +u16 CCR1_Val = 32767; +u16 CCR2_Val = 24575; +u16 CCR3_Val = 16383; +u16 CCR4_Val = 8191; +ErrorStatus HSEStartUpStatus; + +/* Private function prototypes -----------------------------------------------*/ +void RCC_Configuration(void); +void GPIO_Configuration(void); +void SysTick_Configuration(void); +void NVIC_Configuration(void); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : main +* Description : Main program +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +int main(void) +{ +#ifdef DEBUG + debug(); +#endif + + /* System Clocks Configuration */ + RCC_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + /* GPIO Configuration */ + GPIO_Configuration(); + + /* SysTick Configuration */ + SysTick_Configuration(); + + /*----------------------------------------------------------------------------- + The STM32F10x TIM1 peripheral offers the possibility to program in advance the + configuration for the next TIM1 outputs behaviour (step) and change the configuration + of all the channels at the same time. This operation is possible when the COM + (commutation) event is used. + The COM event can be generated by software by setting the COM bit in the TIM1_EGR + register or by hardware (on TRC rising edge). + In this example, a software COM event is generated each 100 ms: using the Systick + interrupt. + The TIM1 is configured in Timing Mode, each time a COM event occurs, + a new TIM1 configuration will be set in advance. + The following Table describes the TIM1 Channels states: + ----------------------------------------------- + | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 | + ---------------------------------------------------------- + |Channel1 | 1 | 0 | 0 | 0 | 0 | 1 | + ---------------------------------------------------------- + |Channel1N | 0 | 0 | 1 | 1 | 0 | 0 | + ---------------------------------------------------------- + |Channel2 | 0 | 0 | 0 | 1 | 1 | 0 | + ---------------------------------------------------------- + |Channel2N | 1 | 1 | 0 | 0 | 0 | 0 | + ---------------------------------------------------------- + |Channel3 | 0 | 1 | 1 | 0 | 0 | 0 | + ---------------------------------------------------------- + |Channel3N | 0 | 0 | 0 | 0 | 1 | 1 | + ---------------------------------------------------------- + -----------------------------------------------------------------------------*/ + + /* Time Base configuration */ + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = 4095; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* Channel 1, 2,3 and 4 Configuration in PWM mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OCInitStructure.TIM_Pulse = 2047; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set; + + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = 1023; + TIM_OC2Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = 511; + TIM_OC3Init(TIM1, &TIM_OCInitStructure); + + /* Automatic Output enable, Break, dead time and lock configuration*/ + TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; + TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable; + TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStructure.TIM_DeadTime = 1; + TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable; + TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High; + TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable; + + TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure); + + TIM_CCPreloadControl(TIM1, ENABLE); + + TIM_ITConfig(TIM1, TIM_IT_COM, ENABLE); + + /* TIM1 counter enable */ + TIM_Cmd(TIM1, ENABLE); + + /* Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + while (1) + {} +} + +/******************************************************************************* +* Function Name : RCC_Configuration +* Description : Configures the different system clocks. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_Configuration(void) +{ + /* RCC system reset(for debug purpose) */ + RCC_DeInit(); + + /* Enable HSE */ + RCC_HSEConfig(RCC_HSE_ON); + + /* Wait till HSE is ready */ + HSEStartUpStatus = RCC_WaitForHSEStartUp(); + + if (HSEStartUpStatus == SUCCESS) + { + /* Enable Prefetch Buffer */ + FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); + + /* Flash 2 wait state */ + FLASH_SetLatency(FLASH_Latency_2); + + /* HCLK = SYSCLK */ + RCC_HCLKConfig(RCC_SYSCLK_Div1); + + /* PCLK2 = HCLK */ + RCC_PCLK2Config(RCC_HCLK_Div1); + + /* PCLK1 = HCLK/2 */ + RCC_PCLK1Config(RCC_HCLK_Div2); + + /* PLLCLK = 8MHz * 9 = 72 MHz */ + RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); + + /* Enable PLL */ + RCC_PLLCmd(ENABLE); + + /* Wait till PLL is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) + {} + + /* Select PLL as system clock source */ + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + /* Wait till PLL is used as system clock source */ + while (RCC_GetSYSCLKSource() != 0x08) + {} + } + + /* TIM1, GPIOA and GPIOB clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA | + RCC_APB2Periph_GPIOB, ENABLE); +} + +/******************************************************************************* +* Function Name : GPIO_Configuration +* Description : Configure the TIM1 Pins. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOA Configuration: Channel 1, 2 and 3 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* GPIOB Configuration: BKIN pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(GPIOB, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : SysTick_Configuration +* Description : Configures the SysTick. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_Configuration(void) +{ + /* Configure SysTick to generate an interrupt each 100ms (with HCLK = 72MHz) -*/ + /* Select AHB clock(HCLK) as SysTick clock source */ + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); + + /* SysTick interrupt each 10 Hz with Core clock equal to 72MHz */ + SysTick_SetReload(7200000); + + /* Enable SysTick Counter */ + SysTick_CounterCmd(SysTick_Counter_Enable); + + /* Enable SysTick interrupt */ + SysTick_ITConfig(ENABLE); +} + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures the nested vectored interrupt controller. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x20000000 */ + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); +#endif + + /* Enable the TIM1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + NVIC_SystemHandlerPriorityConfig(SystemHandler_SysTick, 0, 0); +} + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* Input : - file: pointer to the source file name +* - line: assert_param error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(u8* file, u32 line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3