From 32e57dac2e61e79b029593eb4d34d727bcc10678 Mon Sep 17 00:00:00 2001 From: iperry Date: Thu, 17 Dec 2009 02:37:07 +0000 Subject: Initial commit of library code, moved from leaftest repo git-svn-id: https://leaflabs.googlecode.com/svn/trunk/library@69 749a229e-a60e-11de-b98f-4500b42dc123 --- src/stm32lib/examples/FSMC/NOR/main.c | 233 ++++++++++++++++++++++++++++++++++ 1 file changed, 233 insertions(+) create mode 100755 src/stm32lib/examples/FSMC/NOR/main.c (limited to 'src/stm32lib/examples/FSMC/NOR/main.c') diff --git a/src/stm32lib/examples/FSMC/NOR/main.c b/src/stm32lib/examples/FSMC/NOR/main.c new file mode 100755 index 0000000..508fc6f --- /dev/null +++ b/src/stm32lib/examples/FSMC/NOR/main.c @@ -0,0 +1,233 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : main.c +* Author : MCD Application Team +* Version : V2.0.1 +* Date : 06/13/2008 +* Description : Main program body +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "fsmc_nor.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BUFFER_SIZE 0x400 +#define WRITE_READ_ADDR 0x8000 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +GPIO_InitTypeDef GPIO_InitStructure; +ErrorStatus HSEStartUpStatus; + +u16 TxBuffer[BUFFER_SIZE]; +u16 RxBuffer[BUFFER_SIZE]; +u32 WriteReadStatus = 0, Index = 0; +NOR_IDTypeDef NOR_ID; + +/* Private function prototypes -----------------------------------------------*/ +void RCC_Configuration(void); +void NVIC_Configuration(void); + +void Fill_Buffer(u16 *pBuffer, u16 BufferLenght, u32 Offset); + +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : main +* Description : Main program. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +int main(void) +{ +#ifdef DEBUG + debug(); +#endif + + /* System Clocks Configuration */ + RCC_Configuration(); + + /* NVIC Configuration */ + NVIC_Configuration(); + + /* PF.06 and PF.07 config to drive LD1 and LD2 *****************************/ + /* Enable GPIOF clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE); + + /* Configure PF.06 and PF.07 as Output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* Write/read to/from FSMC SRAM memory *************************************/ + /* Enable the FSMC Clock */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); + + /* Configure FSMC Bank1 NOR/SRAM2 */ + FSMC_NOR_Init(); + + /* Read NOR memory ID */ + FSMC_NOR_ReadID(&NOR_ID); + + FSMC_NOR_ReturnToReadMode(); + + /* Erase the NOR memory block to write on */ + FSMC_NOR_EraseBlock(WRITE_READ_ADDR); + + /* Write data to FSMC NOR memory */ + /* Fill the buffer to send */ + Fill_Buffer(TxBuffer, BUFFER_SIZE, 0x3210); + FSMC_NOR_WriteBuffer(TxBuffer, WRITE_READ_ADDR, BUFFER_SIZE); + + /* Read data from FSMC NOR memory */ + FSMC_NOR_ReadBuffer(RxBuffer, WRITE_READ_ADDR, BUFFER_SIZE); + + /* Read back NOR memory and check content correctness */ + for (Index = 0x00; (Index < BUFFER_SIZE) && (WriteReadStatus == 0); Index++) + { + if (RxBuffer[Index] != TxBuffer[Index]) + { + WriteReadStatus = Index + 1; + } + } + + if (WriteReadStatus == 0) + { /* OK */ + /* Turn on LD1 */ + GPIO_SetBits(GPIOF, GPIO_Pin_6); + } + else + { /* KO */ + /* Turn on LD2 */ + GPIO_SetBits(GPIOF, GPIO_Pin_7); + } + + while (1) + { + } +} + +/******************************************************************************* +* Function Name : RCC_Configuration +* Description : Configures the different system clocks. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_Configuration(void) +{ + /* RCC system reset(for debug purpose) */ + RCC_DeInit(); + + /* Enable HSE */ + RCC_HSEConfig(RCC_HSE_ON); + + /* Wait till HSE is ready */ + HSEStartUpStatus = RCC_WaitForHSEStartUp(); + + if(HSEStartUpStatus == SUCCESS) + { + /* Enable Prefetch Buffer */ + FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); + + /* Flash 2 wait state */ + FLASH_SetLatency(FLASH_Latency_2); + + /* HCLK = SYSCLK */ + RCC_HCLKConfig(RCC_SYSCLK_Div1); + + /* PCLK2 = HCLK */ + RCC_PCLK2Config(RCC_HCLK_Div1); + + /* PCLK1 = HCLK/2 */ + RCC_PCLK1Config(RCC_HCLK_Div2); + + /* PLLCLK = 8MHz * 9 = 72 MHz */ + RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); + + /* Enable PLL */ + RCC_PLLCmd(ENABLE); + + /* Wait till PLL is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) + { + } + + /* Select PLL as system clock source */ + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + /* Wait till PLL is used as system clock source */ + while(RCC_GetSYSCLKSource() != 0x08) + { + } + } +} + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x20000000 */ + NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); +#endif +} + +/******************************************************************************* +* Function name : Fill_Buffer +* Description : Fill the global buffer +* Input : - pBuffer: pointer on the Buffer to fill +* - BufferSize: size of the buffer to fill +* - Offset: first value to fill on the Buffer +* Output param : None +*******************************************************************************/ +void Fill_Buffer(u16 *pBuffer, u16 BufferLenght, u32 Offset) +{ + u16 IndexTmp = 0; + + /* Put in global buffer same values */ + for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ ) + { + pBuffer[IndexTmp] = IndexTmp + Offset; + } +} + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* Input : - file: pointer to the source file name +* - line: assert_param error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(u8* file, u32 line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3