From c8da1c3b7b6eb450138a00af9bbbee607f596837 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 7 Mar 2011 13:11:54 -0500 Subject: [WIP] GPIO refactor: seems ok, ready for review --- notes/coding_standard.txt | 85 +++++++++++++++++++++++------------------------ notes/exti.txt | 67 +++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+), 43 deletions(-) create mode 100644 notes/exti.txt (limited to 'notes') diff --git a/notes/coding_standard.txt b/notes/coding_standard.txt index 5cb96c3..372ebf4 100644 --- a/notes/coding_standard.txt +++ b/notes/coding_standard.txt @@ -25,12 +25,11 @@ License ------- - Put an MIT license at the beginning of the file (look at any of our - source files for an example). Copyright should go to either you or - LeafLabs LLC. + source files for an example). Copyright should go either to you or + to LeafLabs, LLC. Emacs: if you don't like seeing the license, you should use - elide-head (which will hide it for you). Here is some elisp you can - modify to make this pleasant: + elide-head (which will hide it for you). You can use the following: (require 'elide-head) (setq programming-mode-hooks '(c-mode-hook c++-mode-hook)) @@ -38,7 +37,7 @@ License '("The MIT License" . "DEALINGS IN\n [*] THE SOFTWARE")) (add-to-list 'elide-head-headers-to-hide '("The MIT License" . "DEALINGS IN THE\n...SOFTWARE")) - (dolist (hook mbolivar-programming-mode-hooks) + (dolist (hook programming-mode-hooks) (add-hook hook (lambda () (elide-head)))) Whitespace/Indentation @@ -46,7 +45,8 @@ Whitespace/Indentation - 4 space indents. [Set in .dir-locals.el] -- Unix newlines. +- Unix newlines. [Some exceptions are currently grandfathered in; + these will go away in time.] - No tab characters. [Set in .dir-locals.el] @@ -76,50 +76,53 @@ Whitespace/Indentation (add-hook 'c-mode-hook c-mode-inextern-lang-hook) - Comments -------- -- Multi-line comments look like this: +- Multi-line comments are pretty flexible. Any of these is fine: - /* text starts here - * continued lines have a '*' before them - * the comment can end after the last line + /* Comment starts here. + * Continued lines have a '*' before them. + * The comment can end after the last line. */ - or this: - - /* comment starts here - * the comment can end on the same line */ + /* Comment starts here. + * The comment can end on the same line. */ -- Doxygen comments are newline comments that begin with /** instead. - It is not required that the "/**" appear on a line by itself. + /* + * You can also place a newline after the opening "/*". + */ -- Single-line comments on the same line are // in c or c++. +- Doxygen comments are multi-line comments that begin with /** instead. -- Single-line comments on their own source line are /* */ in c, but - can also be // in c++. If you think that typing out /* */ is too - slow in emacs, use M-; (comment-dwim) when you're on an empty line, - and it'll ... well... +- Single-line comments on the same line are // in C or C++. - You should be using the (super awesome) comment-dwim; it pretty - much does exactly what you want to the comment on the current - line, including "create one and put it in the right place". +- Single-line comments on their own source line should be /* */ in C, + but can also be // in C++. In Emacs, you can use M-; + (comment-dwim), and it'll Do What You Mean. Braces ------ -- 1TBS. Nothing more need be said. +- Mostly 1TBS: http://en.wikipedia.org/wiki/Indent_style#Variant:_1TBS + The only difference is that the opening brace of a function's + definition occurs exactly one space character after the closing + parenthesis in that function's parameter list. Example: + + void func(void) { + ... + } + Naming conventions ------------------ -- There's always a fight about upper and lower case vs. underscores. - We'll handle this as follows. +There's always a fight about upper and lower case vs. underscores. +We'll handle this as follows. - First, Dammit_Dont_Mix_Like_This, because It_Looks_Really_Ugly, ok? +- First, Dammit_Dont_Mix_Like_This, because It_Looks_Really_Ugly, ok? [There's been some debate about this, and some exceptions are already grandfathered in, so in order to settle it, let's call this a "recommendation" instead of "requirement".] @@ -168,7 +171,7 @@ Naming conventions Documentation ------------- -- Document your code. This should go without saying. +- Document your code! - For complicated peripherals, it would be nice if you put longer-form comments into this directory (notes/), with a comment in the @@ -176,13 +179,8 @@ Documentation example. That lets us keep the source files relatively clean while still allowing new readers to have a starting point. -- At least put a doxygen comment with a nonempty @brief for every .h - file you add. See the existing ones for examples. For now, it'd be - better if you didn't put a @brief into any .c[pp] files, since it - (currently) interferes with our documentation generator in a way - that I won't explain here (though you can look into the LeafLabs or - michaeljones breathe repos on github and potentially figure out - why). +- At least put a Doxygen comment with a nonempty @brief for every .h + file you add. See the existing ones for examples. - Doxygen comments generally just belong on types, functions, etc. that are part of the public user-facing API. This generally @@ -196,8 +194,13 @@ Documentation This should be avoided if at all possible, since it creates a maintenance burden of documenting things in two places at once, and - provides an opportunity for bad documentation to slip in, when the - code comments fall out of sync with the ReST docs. + makes it easier for documentation to go stale. + +- For libmaple proper (the pure C library under libmaple/); the + convention is to document any user-facing entity at the point where + it is defined. In particular, this means you should document an + externally-linked function defined in a .c file in that .c file, not + in the header file where it is declared to the user. General Formatting ------------------ @@ -217,7 +220,3 @@ General Formatting (require 'lineker) (dolist (hook '(c-mode-hook c++-mode-hook)) (add-hook hook (lambda () (lineker-mode 1)))) - - There are only a few exceptional situations. The most important one - is when specifying a lookup table like PIN_MAP where it'd be ugly to - split each entry over multiple lines. diff --git a/notes/exti.txt b/notes/exti.txt new file mode 100644 index 0000000..1ad49ee --- /dev/null +++ b/notes/exti.txt @@ -0,0 +1,67 @@ +External interrupt notes. + +To generate the interrupt, the interrupt line should be configured +and enabled. This is done by programming the two trigger registers +with the desired edge detection and by enabling the interrupt +request by writing a '1' to the corresponding bit in the interrupt +mask register. When the selected edge occurs on the external +interrupt line, an interrupt request is generated. The pending bit +corresponding to the interrupt line is also set. This request is +reset by writing a '1' in the pending register. + +Hardware interrupt selection: + +To configure the 20 lines as interrupt sources, use the following +procedure: + +1) Configure AFIO_EXTICR[y] to select the source input for EXTIx + external interrupt +2) Configure the mask bits of the 20 interrupt lines (EXTI_IMR) +3) Configure the trigger selection bits of the interrupt lines + (EXTI_RTSR and EXTI_FTSR) +4) Configure the enable and mask bits that control the NVIC_IRQ + channel mapped to the External Interrupt Controller (EXTI) so + that an inerrupt coming from one of the 20 lines can be + correctly acknowledged. + +AFIO clock must be on. + +RM0008, page 107: "PD0, PD1 cannot be used for external +interrupt/event generation on 36, 48, 64-bin packages." + +---------------------------------------------------------------------------- +Pin to EXTI Line Mappings: +EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 +-------------------------------------------------------------------------- +D2/PA0 D3/PA1 D1/PA2 D0/A6/PA3 D10/A10/PA4 +D26/EXT7/PB0 D27/EXT8/PB1 D16/A2/PC2 D17/A3/PC3 D18/A4/PC4 +D14/A0/PC0 D15/PC1 D25/EXT5/PD2 + +EXTI5 EXTI6 EXTI7 EXTI8 EXTI9 +---------------------------------------------------------------------------- +D13/A13/PA5 D12/A12/PA6 D11/A11/PA7 D6/PA8 D7/PA9 +D4/PB5 D5/PB6 D9/PB7 D38/PB8 D23/EXT4/PB9 +D19/A5/PC5 D34/EXTI15/PC6 D35/EXT16/PC7 D36/PC8 D37/EXT18/PC9 + +EXTI10 EXTI11 EXTI12 EXTI13 EXTI14 +---------------------------------------------------------------------------- +D8/PA10 D29/EXT10/PB11 D30/EXTI1/PB12 D31/EXTI12/PB13 D32/EXT13/PB14 +D28/PB10 D20/EXTI1/PC13 D21/EXT2/PC14 +D25/PC10 + +EXTI15 +---------------------------------------------------------------------------- +D33/EXTI14/PB15 +D22/EXT3/PC15 + + +The 16 EXTI interrupts are mapped to 7 interrupt handlers. + +EXTI Lines to Interrupt Mapping: +EXTI0 -> EXTI0 +EXTI1 -> EXTI1 +EXTI2 -> EXTI2 +EXTI3 -> EXTI3 +EXTI4 -> EXTI4 +EXTI[5-9] -> EXT9_5 +EXTI[10-15] -> EXT15_10 -- cgit v1.2.3 From 61db54f52f32e63c895d775982fbcdcb67f2dde6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 22 Mar 2011 16:59:29 -0400 Subject: Initial timer refactor. Basic PWM works. Had some problems in testing that might be due to USART bugs. HardwareTimer has been removed from the build for now; I will re-implement it in terms of the new libmaple API, but consider it deprecated. Let's come up with something better. Servo is implemented in terms of HardwareTimer, so it also has been temporarily removed from the build. pwmWrite() likely got a little bit less inefficient due to indirection, but the PIN_MAPs shrank by a pointer per PinMapping. --- Makefile | 2 +- examples/test-session.cpp | 19 +- examples/test-timers.cpp | 372 ++++++++------- libmaple/bitband.h | 5 + libmaple/delay.h | 2 +- libmaple/nvic.h | 101 ++-- libmaple/rules.mk | 2 +- libmaple/spi.h | 3 + libmaple/timer.c | 449 ++++++++++++++++++ libmaple/timer.h | 1010 ++++++++++++++++++++++++++++++++++++++++ libmaple/timers.c | 526 --------------------- libmaple/timers.h | 435 ----------------- libmaple/util.c | 2 +- libraries/Servo/Servo.h | 1 + notes/portable.txt | 94 +--- notes/usb.txt | 4 + notes/vga.txt | 9 +- wirish/boards.cpp | 646 +++++++++---------------- wirish/boards.h | 9 +- wirish/comm/HardwareSPI.cpp | 4 +- wirish/comm/HardwareSerial.cpp | 20 +- wirish/comm/HardwareSerial.h | 12 +- wirish/pwm.cpp | 22 +- wirish/rules.mk | 1 - wirish/wirish.cpp | 122 +++-- wirish/wirish.h | 3 - wirish/wirish_digital.cpp | 6 +- 27 files changed, 2095 insertions(+), 1786 deletions(-) create mode 100644 libmaple/timer.c create mode 100644 libmaple/timer.h delete mode 100644 libmaple/timers.c delete mode 100644 libmaple/timers.h (limited to 'notes') diff --git a/Makefile b/Makefile index d31c9ed..109a126 100644 --- a/Makefile +++ b/Makefile @@ -97,7 +97,7 @@ endif LIBMAPLE_MODULES := $(SRCROOT)/libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish # Official libraries: -LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo +# LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo LIBMAPLE_MODULES += $(SRCROOT)/libraries/LiquidCrystal LIBMAPLE_MODULES += $(SRCROOT)/libraries/Wire diff --git a/examples/test-session.cpp b/examples/test-session.cpp index a147e06..9b4bce4 100644 --- a/examples/test-session.cpp +++ b/examples/test-session.cpp @@ -15,7 +15,6 @@ //#define COMM Serial2 //#define COMM Serial3 - #define ESC ((uint8)27) int rate = 0; @@ -610,17 +609,15 @@ void cmd_servo_sweep(void) { COMM.println("(reset serial port)"); } +static uint16 init_all_timers_prescale = 0; + +static void set_prescale(timer_dev *dev) { + timer_set_prescaler(dev, init_all_timers_prescale); +} + void init_all_timers(uint16 prescale) { - timer_init(TIMER1, prescale); - timer_init(TIMER2, prescale); - timer_init(TIMER3, prescale); - timer_init(TIMER4, prescale); -#ifdef STM32_HIGH_DENSITY - timer_init(TIMER5, prescale); - // timer_init(TIMER6, prescale); - // timer_init(TIMER7, prescale); - timer_init(TIMER8, prescale); -#endif + init_all_timers_prescale = prescale; + timer_foreach(set_prescale); } // Force init to be called *first*, i.e. before static object allocation. diff --git a/examples/test-timers.cpp b/examples/test-timers.cpp index f3cfdcc..a4fbc8a 100644 --- a/examples/test-timers.cpp +++ b/examples/test-timers.cpp @@ -1,8 +1,7 @@ -// Program to test the wirish timers implementation +// Program to test the timer.h implementation's essential functionality. #include "wirish.h" - -#define LED_PIN BOARD_LED_PIN +#include "timer.h" void handler1(void); void handler2(void); @@ -27,208 +26,253 @@ uint16 val2 = 10000; uint16 val3 = 10000; uint16 val4 = 10000; -HardwareTimer Timers[] = {Timer1, Timer2, Timer3, Timer4}; +// FIXME high density timer test (especially basic timers + DAC) +timer_dev *timers[] = {TIMER1, TIMER2, TIMER3, TIMER4}; +voidFuncPtr handlers[] = {handler1, handler2, handler3, handler4}; + +void initTimer(timer_dev *dev); +void setTimerPeriod(timer_dev *dev, uint32 period_us); +void testSetTimerPeriod(uint32 period); +void testTimerChannels(timer_dev *dev); +int timerNumber(timer_dev *dev); -void setup() -{ - /* Set up the LED to blink */ - pinMode(LED_PIN, OUTPUT); +void setup() { + // Set up the LED to blink + pinMode(BOARD_LED_PIN, OUTPUT); // Setup the button as input pinMode(BOARD_BUTTON_PIN, INPUT); - // Wait for user to attach... - waitForButtonPress(0); - - // Send a message out SerialUSB - SerialUSB.println("Beginning timer test..."); - for(int t=0; t<4; t++) { - Timers[t].setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timers[t].setChannel2Mode(TIMER_OUTPUTCOMPARE); - Timers[t].setChannel3Mode(TIMER_OUTPUTCOMPARE); - Timers[t].setChannel4Mode(TIMER_OUTPUTCOMPARE); - } + // Send a message out Serial2 + Serial2.begin(115200); + Serial2.println("*** Initializing timers..."); + Serial2.println("foo"); + timer_foreach(initTimer); + Serial2.println("*** Done. Beginning timer test."); } void loop() { - SerialUSB.println("-----------------------------------------------------"); - SerialUSB.println("Testing setCount/getCount"); - SerialUSB.print("Timer1.getCount() = "); SerialUSB.println(Timer1.getCount()); - SerialUSB.println("Timer1.setCount(1234)"); - Timer1.setCount(1234); - SerialUSB.print("Timer1.getCount() = "); SerialUSB.println(Timer1.getCount()); - // This tests whether the pause/resume functions work; when BUT is held - // down Timer4 is in the "pause" state and the timer doesn't increment, so - // the final counts should reflect the ratio of time that BUT was held down - SerialUSB.println("-----------------------------------------------------"); - SerialUSB.println("Testing Pause/Resume; button roughly controls Timer4"); + Serial2.println("-----------------------------------------------------"); + + Serial2.println("Testing timer_get_count()/timer_set_count()"); + Serial2.print("TIMER1 count = "); + Serial2.println(timer_get_count(TIMER1)); + Serial2.println("timer_set_count(TIMER1, 1234)"); + timer_set_count(TIMER1, 1234); + Serial2.print("timer_get_count(TIMER1) = "); + Serial2.println(timer_get_count(TIMER1)); + + Serial2.println("-----------------------------------------------------"); + Serial2.println("Testing pause/resume; button roughly controls TIMER4"); + // when BUT is held down, TIMER4 is in the "pause" state and the + // timer doesn't increment, so the final counts should reflect the + // ratio of time that BUT was held down. count3 = 0; count4 = 0; - Timer3.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer3.pause(); - Timer4.pause(); - Timer3.setCount(0); - Timer4.setCount(0); - Timer3.setOverflow(30000); - Timer4.setOverflow(30000); - Timer3.setCompare1(1000); - Timer4.setCompare1(1000); - Timer3.attachCompare1Interrupt(handler3b); - Timer4.attachCompare1Interrupt(handler4b); - Timer3.resume(); - Timer4.resume(); - SerialUSB.println("~4 seconds..."); - for(int i = 0; i<4000; i++) { - if(isButtonPressed()) { - Timer4.pause(); + timer_set_mode(TIMER3, TIMER_CH1, TIMER_OUTPUT_COMPARE); + timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE); + timer_pause(TIMER3); + timer_pause(TIMER4); + timer_set_count(TIMER3, 0); + timer_set_count(TIMER4, 0); + timer_set_reload(TIMER3, 30000); + timer_set_reload(TIMER4, 30000); + timer_set_compare(TIMER3, 1, 1000); + timer_set_compare(TIMER4, 1, 1000); + timer_attach_interrupt(TIMER3, TIMER_CC1_INTERRUPT, handler3b); + timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b); + timer_resume(TIMER3); + timer_resume(TIMER4); + + Serial2.println("Testing for ~4 seconds..."); + for(int i = 0; i < 4000; i++) { + if (isButtonPressed()) { + timer_pause(TIMER4); } else { - Timer4.resume(); + timer_resume(TIMER4); } delay(1); } - Timer3.setChannel1Mode(TIMER_DISABLED); - Timer4.setChannel1Mode(TIMER_DISABLED); - SerialUSB.print("Count3: "); SerialUSB.println(count3); - SerialUSB.print("Count4: "); SerialUSB.println(count4); - - // These test the setPeriod auto-configure functionality - SerialUSB.println("-----------------------------------------------------"); - SerialUSB.println("Testing setPeriod"); - Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer4.setCompare1(1); - Timer4.setPeriod(10); - Timer4.pause(); - Timer4.setCount(0); - Timer4.attachCompare1Interrupt(handler4b); - SerialUSB.println("Period 10ms, wait 2 seconds..."); - count4 = 0; - Timer4.resume(); - delay(2000); - Timer4.pause(); - Timer4.setChannel1Mode(TIMER_DISABLED); - SerialUSB.print("Count4: "); SerialUSB.println(count4); - SerialUSB.println("(should be around 2sec/10ms = 200000)"); - Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer4.setCompare1(1); - Timer4.pause(); - Timer4.setPeriod(30000); - Timer4.setCount(0); - Timer4.attachCompare1Interrupt(handler4b); - SerialUSB.println("Period 30000ms, wait 2 seconds..."); - count4 = 0; - Timer4.resume(); - delay(2000); - Timer4.pause(); - Timer4.setChannel1Mode(TIMER_DISABLED); - SerialUSB.print("Count4: "); SerialUSB.println(count4); - SerialUSB.println("(should be around 2sec/30000ms ~ 67)"); - - Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer4.setPeriod(300000); - Timer4.setCompare1(1); - Timer4.pause(); - Timer4.setCount(0); - Timer4.attachCompare1Interrupt(handler4b); - SerialUSB.println("Period 300000ms, wait 2 seconds..."); - count4 = 0; - Timer4.resume(); - delay(2000); - Timer4.pause(); - Timer4.setChannel1Mode(TIMER_DISABLED); - SerialUSB.print("Count4: "); SerialUSB.println(count4); - SerialUSB.println("(should be around 2sec/300000ms ~ 6.7)"); - - Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer4.setPrescaleFactor(33); - Timer4.setOverflow(65454); - Timer4.pause(); - Timer4.setCount(0); - Timer4.setCompare1(1); - Timer4.attachCompare1Interrupt(handler4b); - SerialUSB.println("Period 30000ms, wait 2 seconds..."); + + timer_set_mode(TIMER3, TIMER_CH1, TIMER_DISABLED); + timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED); + + Serial2.print("TIMER3 count: "); + Serial2.println(timer_get_count(TIMER3)); + Serial2.print("TIMER4 count: "); + Serial2.println(timer_get_count(TIMER4)); + + Serial2.println("-----------------------------------------------------"); + Serial2.println("Testing setTimerPeriod()"); + testSetTimerPeriod(10); + testSetTimerPeriod(30000); + testSetTimerPeriod(300000); + testSetTimerPeriod(30000); + + Serial2.println("Sanity check (with hand-coded reload and prescaler for " + "72 MHz timers):"); + timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE); + timer_set_prescaler(TIMER4, 33); + timer_set_reload(TIMER4, 65454); + timer_pause(TIMER4); + timer_set_count(TIMER4, 0); + timer_set_compare(TIMER4, TIMER_CH1, 1); + timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b); + Serial2.println("Period 30000ms, wait 2 seconds..."); count4 = 0; - Timer4.resume(); + timer_resume(TIMER4); delay(2000); - Timer4.pause(); - Timer4.setChannel1Mode(TIMER_DISABLED); - SerialUSB.print("Count4: "); SerialUSB.println(count4); - SerialUSB.println("(should be around 2sec/30000ms ~ 67)"); - - Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timer4.setCompare1(1); - Timer4.setPeriod(30000); - Timer4.pause(); - Timer4.setCount(0); - Timer4.attachCompare1Interrupt(handler4b); - SerialUSB.println("Period 30000ms, wait 2 seconds..."); + timer_pause(TIMER4); + timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED); + Serial2.print("TIMER4 count: "); + Serial2.println(count4); + Serial2.println(" (Should be around 2sec/30000ms ~ 67)"); + + // Test all the individual timer channels + timer_foreach(testTimerChannels); +} + +void initTimer(timer_dev *dev) { + switch (dev->type) { + case TIMER_ADVANCED: + case TIMER_GENERAL: + Serial2.print("Initializing timer "); + Serial2.println(timerNumber(dev)); + for (int c = 1; c <= 4; c++) { + timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE); + } + Serial2.println("Done."); + break; + case TIMER_BASIC: + break; + } +} + +void testSetTimerPeriod(uint32 period) { + timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE); + timer_set_compare(TIMER4, TIMER_CH1, 1); + setTimerPeriod(TIMER4, period); + timer_pause(TIMER4); + timer_set_count(TIMER4, 0); + timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b); + Serial2.println("Period "); + Serial2.print(period); + Serial2.print(" ms. Waiting 2 seconds..."); count4 = 0; - Timer4.resume(); + timer_resume(TIMER4); delay(2000); - Timer4.pause(); - Timer4.setChannel1Mode(TIMER_DISABLED); - SerialUSB.print("Count4: "); SerialUSB.println(count4); - SerialUSB.println("(should be around 2sec/30000ms ~ 67)"); - - // This section is to touch every channel of every timer. The output - // ratios should reflect the ratios of the rate variables. Demonstrates - // that over time the actual timing rates get blown away by other system - // interrupts. - for(t=0; t<4; t++) { - toggleLED(); - delay(100); - SerialUSB.println("-----------------------------------------------------"); - SerialUSB.print("Testing Timer "); SerialUSB.println(t+1); + timer_pause(TIMER4); + timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED); + Serial2.print("TIMER4 count: "); + Serial2.println(timer_get_count(TIMER4)); + Serial2.print(" (Should be around 2 sec / "); + Serial2.print(period); + Serial2.print(" ms = "); + Serial2.print(double(2) / period * 1000); + Serial2.println(", modulo delays due to interrupts)"); +} + +int timerNumber(timer_dev *dev) { + switch (dev->clk_id) { + case RCC_TIMER1: + return 1; + case RCC_TIMER2: + return 2; + case RCC_TIMER3: + return 3; + case RCC_TIMER4: + return 4; +#ifdef STM32_HIGH_DENSITY + case RCC_TIMER5: + return 5; + case RCC_TIMER6: + return 6; + case RCC_TIMER7: + return 7; + case RCC_TIMER8: + return 8; +#endif + default: + ASSERT(0); + return 0; + } +} + +/* This function touches every channel of a given timer. The output + * ratios should reflect the ratios of the rate variables. It + * demonstrates that, over time, the actual timing rates get blown + * away by other system interrupts. */ +void testTimerChannels(timer_dev *dev) { + t = timerNumber(dev); + toggleLED(); + delay(100); + Serial2.println("-----------------------------------------------------"); + switch (dev->type) { + case TIMER_BASIC: + Serial2.print("NOT testing channels for basic timer "); + Serial2.println(t); + break; + case TIMER_ADVANCED: + case TIMER_GENERAL: + Serial2.print("Testing channels for timer "); + Serial2.println(t); + timer_pause(dev); count1 = count2 = count3 = count4 = 0; - Timers[t].setOverflow(0xFFFF); - Timers[t].setPrescaleFactor(1); - Timers[t].setCompare1(65535); - Timers[t].setCompare2(65535); - Timers[t].setCompare3(65535); - Timers[t].setCompare4(65535); - Timers[t].setChannel1Mode(TIMER_OUTPUTCOMPARE); - Timers[t].setChannel2Mode(TIMER_OUTPUTCOMPARE); - Timers[t].setChannel3Mode(TIMER_OUTPUTCOMPARE); - Timers[t].setChannel4Mode(TIMER_OUTPUTCOMPARE); - Timers[t].attachCompare1Interrupt(handler1); - Timers[t].attachCompare2Interrupt(handler2); - Timers[t].attachCompare3Interrupt(handler3); - Timers[t].attachCompare4Interrupt(handler4); - Timers[t].resume(); + timer_set_reload(dev, 0xFFFF); + timer_set_prescaler(dev, 1); + for (int c = 1; c <= 4; c++) { + timer_set_compare(dev, c, 65535); + timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE); + timer_attach_interrupt(dev, c, handlers[c - 1]); + } + timer_resume(dev); delay(3000); - Timers[t].setChannel1Mode(TIMER_DISABLED); - Timers[t].setChannel2Mode(TIMER_DISABLED); - Timers[t].setChannel3Mode(TIMER_DISABLED); - Timers[t].setChannel4Mode(TIMER_DISABLED); - SerialUSB.print("Count1: "); SerialUSB.println(count1); - SerialUSB.print("Count2: "); SerialUSB.println(count2); - SerialUSB.print("Count3: "); SerialUSB.println(count3); - SerialUSB.print("Count4: "); SerialUSB.println(count4); + for (int c = 1; c <= 4; c++) { + timer_set_mode(dev, c, TIMER_DISABLED); + } + Serial2.print("Channel 1 count: "); Serial2.println(count1); + Serial2.print("Channel 2 count: "); Serial2.println(count2); + Serial2.print("Channel 3 count: "); Serial2.println(count3); + Serial2.print("Channel 4 count: "); Serial2.println(count4); + break; + } +} + +// FIXME move this into the new wirish timer implementation +void setTimerPeriod(timer_dev *dev, uint32 period_us) { + if (!period_us) { + // FIXME handle this case + ASSERT(0); + return; } + uint32 cycles = period_us * CYCLES_PER_MICROSECOND; + uint16 pre = (uint16)((cycles >> 16) + 1); + timer_set_prescaler(dev, pre); + timer_set_reload(dev, cycles / pre - 1); } void handler1(void) { val1 += rate1; - Timers[t].setCompare1(val1); + timer_set_compare(timers[t], TIMER_CH1, val1); count1++; } void handler2(void) { val2 += rate2; - Timers[t].setCompare2(val2); + timer_set_compare(timers[t], TIMER_CH2, val2); count2++; } void handler3(void) { val3 += rate3; - Timers[t].setCompare3(val3); + timer_set_compare(timers[t], TIMER_CH3, val3); count3++; } void handler4(void) { val4 += rate4; - Timers[t].setCompare4(val4); + timer_set_compare(timers[t], TIMER_CH4, val4); count4++; } diff --git a/libmaple/bitband.h b/libmaple/bitband.h index 3e02702..870abe9 100644 --- a/libmaple/bitband.h +++ b/libmaple/bitband.h @@ -30,6 +30,9 @@ * @brief Bit-banding utility functions */ +#ifndef _BITBAND_H_ +#define _BITBAND_H_ + #define BB_SRAM_REF 0x20000000 #define BB_SRAM_BASE 0x22000000 #define BB_PERI_REF 0x40000000 @@ -103,3 +106,5 @@ static inline __io uint32* __bb_addr(__io void *address, uint32 bb_ref) { return (__io uint32*)(bb_base + ((uint32)address - bb_ref) * 32 + bit * 4); } + +#endif /* _BITBAND_H_ */ diff --git a/libmaple/delay.h b/libmaple/delay.h index 10839c9..e4d85c5 100644 --- a/libmaple/delay.h +++ b/libmaple/delay.h @@ -1,5 +1,5 @@ /** - * @brief + * @brief Delay implementation */ #ifndef _DELAY_H_ diff --git a/libmaple/nvic.h b/libmaple/nvic.h index fe9990f..cbcd49c 100644 --- a/libmaple/nvic.h +++ b/libmaple/nvic.h @@ -53,9 +53,6 @@ extern "C"{ /* System control registers */ #define SCB_VTOR 0xE000ED08 // Vector table offset register -#define NVIC_VectTab_RAM ((u32)0x20000000) -#define NVIC_VectTab_FLASH ((u32)0x08000000) - #define NVIC_BASE 0xE000E100 #define NVIC ((nvic_reg_map*)NVIC_BASE) @@ -75,52 +72,58 @@ typedef struct nvic_reg_map { __io uint32 STIR; // Software Trigger Interrupt Registers } nvic_reg_map; -enum { - NVIC_NMI = -14, - NVIC_MEM_MANAGE = -12, - NVIC_BUS_FAULT = -11, - NVIC_USAGE_FAULT = -10, - NVIC_SVC = -5, - NVIC_DEBUG_MON = -4, - NVIC_PEND_SVC = -2, - NVIC_SYSTICK = -1, - NVIC_TIMER1 = 27, - NVIC_TIMER2 = 28, - NVIC_TIMER3 = 29, - NVIC_TIMER4 = 30, - NVIC_TIMER5 = 50, // high density only (Maple Native, Maple Audio) - NVIC_TIMER6 = 54, // high density only - NVIC_TIMER7 = 55, // high density only - NVIC_TIMER8 = 46, // high density only - - NVIC_USART1 = 37, - NVIC_USART2 = 38, - NVIC_USART3 = 39, - NVIC_UART4 = 52, // high density only - NVIC_UART5 = 53, // high density only - - NVIC_EXTI0 = 6, - NVIC_EXTI1 = 7, - NVIC_EXTI2 = 8, - NVIC_EXTI3 = 9, - NVIC_EXTI4 = 10, - NVIC_EXTI9_5 = 23, - NVIC_EXTI15_10 = 40, - - NVIC_DMA_CH1 = 11, - NVIC_DMA_CH2 = 12, - NVIC_DMA_CH3 = 13, - NVIC_DMA_CH4 = 14, - NVIC_DMA_CH5 = 15, - NVIC_DMA_CH6 = 16, - NVIC_DMA_CH7 = 17, - - NVIC_I2C1_EV = 31, - NVIC_I2C1_ER = 32, - NVIC_I2C2_EV = 33, - NVIC_I2C2_ER = 34 -}; - +typedef enum nvic_irq_num { + NVIC_NMI = -14, + NVIC_MEM_MANAGE = -12, + NVIC_BUS_FAULT = -11, + NVIC_USAGE_FAULT = -10, + NVIC_SVC = -5, + NVIC_DEBUG_MON = -4, + NVIC_PEND_SVC = -2, + NVIC_SYSTICK = -1, + + NVIC_TIMER1_BRK = 24, + NVIC_TIMER1_UP = 25, + NVIC_TIMER1_TRG_COM = 26, + NVIC_TIMER1_CC = 27, + NVIC_TIMER2 = 28, + NVIC_TIMER3 = 29, + NVIC_TIMER4 = 30, + NVIC_TIMER5 = 50, + NVIC_TIMER6 = 54, + NVIC_TIMER7 = 55, + NVIC_TIMER8_BRK = 43, + NVIC_TIMER8_UP = 44, + NVIC_TIMER8_TRG_COM = 45, + NVIC_TIMER8_CC = 46, + + NVIC_USART1 = 37, + NVIC_USART2 = 38, + NVIC_USART3 = 39, + NVIC_UART4 = 52, + NVIC_UART5 = 53, + + NVIC_EXTI0 = 6, + NVIC_EXTI1 = 7, + NVIC_EXTI2 = 8, + NVIC_EXTI3 = 9, + NVIC_EXTI4 = 10, + NVIC_EXTI9_5 = 23, + NVIC_EXTI15_10 = 40, + + NVIC_DMA_CH1 = 11, + NVIC_DMA_CH2 = 12, + NVIC_DMA_CH3 = 13, + NVIC_DMA_CH4 = 14, + NVIC_DMA_CH5 = 15, + NVIC_DMA_CH6 = 16, + NVIC_DMA_CH7 = 17, + + NVIC_I2C1_EV = 31, + NVIC_I2C1_ER = 32, + NVIC_I2C2_EV = 33, + NVIC_I2C2_ER = 34 +} nvic_irq_num; #define nvic_globalirq_enable() asm volatile("cpsie i") #define nvic_globalirq_disable() asm volatile("cpsid i") diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 48b5ed4..a9d7e50 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -28,7 +28,7 @@ cSRCS_$(d) := adc.c \ spi.c \ syscalls.c \ systick.c \ - timers.c \ + timer.c \ usart.c \ util.c \ usb/descriptors.c \ diff --git a/libmaple/spi.h b/libmaple/spi.h index db8aa9c..5ebf52d 100644 --- a/libmaple/spi.h +++ b/libmaple/spi.h @@ -31,6 +31,9 @@ #ifndef _SPI_H_ #define _SPI_H_ +#include "libmaple_types.h" +#include "util.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/libmaple/timer.c b/libmaple/timer.c new file mode 100644 index 0000000..ad0ec6f --- /dev/null +++ b/libmaple/timer.c @@ -0,0 +1,449 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file timer.c + * @author Marti Bolivar + * @brief New-style timer interface + */ + +#include "timer.h" + +#if defined(STM32_MEDIUM_DENSITY) +#define NR_TIMERS 4 +#elif defined(STM32_HIGH_DENSITY) +#define NR_TIMERS 8 +#endif + +/* Just like the corresponding DIER bits: + * [0] = Update handler; + * [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively; + * [5] = COM; + * [6] = TRG; + * [7] = BRK. */ +#define NR_ADV_HANDLERS 8 +/* Update, capture/compare 1,2,3,4; ; trigger. */ +#define NR_GEN_HANDLERS 6 +/* Update only. */ +#define NR_BAS_HANDLERS 1 + +static timer_dev timer1 = { + .regs = {.adv = TIMER1_BASE}, + .clk_id = RCC_TIMER1, + .type = TIMER_ADVANCED, + .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER1 = &timer1; + +static timer_dev timer2 = { + .regs = {.gen = TIMER2_BASE}, + .clk_id = RCC_TIMER2, + .type = TIMER_GENERAL, + .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER2 = &timer2; + +static timer_dev timer3 = { + .regs = {.gen = TIMER3_BASE}, + .clk_id = RCC_TIMER3, + .type = TIMER_GENERAL, + .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER3 = &timer3; + +static timer_dev timer4 = { + .regs = {.gen = TIMER4_BASE}, + .clk_id = RCC_TIMER4, + .type = TIMER_GENERAL, + .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER4 = &timer4; + +#ifdef STM32_HIGH_DENSITY +static timer_dev timer5 = { + .regs = {.gen = TIMER5_BASE}, + .clk_id = RCC_TIMER5, + .type = TIMER_GENERAL, + .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER5 = &timer5; + +static timer_dev timer6 = { + .regs = {.bas = TIMER6_BASE}, + .clk_id = RCC_TIMER6, + .type = TIMER_BASIC, + .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER6 = &timer6; + +static timer_dev timer7 = { + .regs = {.bas = TIMER7_BASE}, + .clk_id = RCC_TIMER7, + .type = TIMER_BASIC, + .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER7 = &timer7; + +static timer_dev timer8 = { + .regs = {.adv = TIMER8_BASE}, + .clk_id = RCC_TIMER8, + .type = TIMER_ADVANCED, + .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, +}; +timer_dev *TIMER8 = &timer8; +#endif + +/* + * Convenience routines + */ + +static void disable_channel(timer_dev *dev, uint8 channel); +static void pwm_mode(timer_dev *dev, uint8 channel); +static void output_compare_mode(timer_dev *dev, uint8 channel); + +static inline void enable_irq(timer_dev *dev, uint8 interrupt); + +/** + * Initialize a timer, and reset its register map. + * @param dev Timer to initialize + */ +void timer_init(timer_dev *dev) { + rcc_clk_enable(dev->clk_id); + rcc_reset_dev(dev->clk_id); +} + +/** + * @brief Disable a timer. + * + * The timer will stop counting, all DMA requests and interrupts will + * be disabled, and no state changes will be output. + * + * @param dev Timer to disable. + */ +void timer_disable(timer_dev *dev) { + (dev->regs).bas->CR1 = 0; + (dev->regs).bas->DIER = 0; + switch (dev->type) { + case TIMER_ADVANCED: /* fall-through */ + case TIMER_GENERAL: + (dev->regs).gen->CCER = 0; + break; + case TIMER_BASIC: + break; + } +} + +/** + * Sets the mode of an individual timer channel. + * + * Note that not all timers can be configured in every mode. For + * example, basic timers cannot be configured to output compare mode. + * Be sure to use a timer which is appropriate for the mode you want. + * + * @param dev Timer whose channel mode to set + * @param channel Relevant channel + * @param mode New timer mode for channel + */ +void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) { + ASSERT(channel > 0 && channel <= 4); + + /* TODO decide about the basic timers */ + ASSERT(dev->type != TIMER_BASIC); + if (dev->type == TIMER_BASIC) + return; + + switch (mode) { + case TIMER_DISABLED: + disable_channel(dev, channel); + break; + case TIMER_PWM: + pwm_mode(dev, channel); + break; + case TIMER_OUTPUT_COMPARE: + output_compare_mode(dev, channel); + break; + } +} + +/** + * @brief Call a given function on all timers. + * @param fn Function to call on each timer. + */ +void timer_foreach(void (*fn)(timer_dev*)) { + fn(TIMER1); + fn(TIMER2); + fn(TIMER3); + fn(TIMER4); +#ifdef STM32_HIGH_DENSITY + fn(TIMER5); + fn(TIMER6); + fn(TIMER7); + fn(TIMER8); +#endif +} + +/** + * @brief Attach a timer interrupt. + * @param dev Timer device + * @param interrupt Interrupt number to attach to; this may be any + * timer_interrupt_id or timer_channel value appropriate + * for the timer. + * @param handler Handler to attach to the given interrupt. + * @see timer_interrupt_id + * @see timer_channel + */ +void timer_attach_interrupt(timer_dev *dev, + uint8 interrupt, + voidFuncPtr handler) { + dev->handlers[interrupt] = handler; + timer_enable_interrupt(dev, interrupt); + enable_irq(dev, interrupt); +} + +/** + * @brief Detach a timer interrupt. + * @param dev Timer device + * @param interrupt Interrupt number to detach; this may be any + * timer_interrupt_id or timer_channel value appropriate + * for the timer. + * @see timer_interrupt_id + * @see timer_channel + */ +void timer_detach_interrupt(timer_dev *dev, uint8 interrupt) { + timer_disable_interrupt(dev, interrupt); + dev->handlers[interrupt] = NULL; +} + +/* + * IRQ handlers + */ + +static inline void dispatch_adv_brk(timer_dev *dev); +static inline void dispatch_adv_up(timer_dev *dev); +static inline void dispatch_adv_trg_com(timer_dev *dev); +static inline void dispatch_adv_cc(timer_dev *dev); +static inline void dispatch_general(timer_dev *dev); +static inline void dispatch_basic(timer_dev *dev); + +void __irq_tim1_brk(void) { + dispatch_adv_brk(TIMER1); +} + +void __irq_tim1_up(void) { + dispatch_adv_up(TIMER1); +} + +void __irq_tim1_trg_com(void) { + dispatch_adv_trg_com(TIMER1); +} + +void __irq_tim1_cc(void) { + dispatch_adv_cc(TIMER1); +} + +void __irq_tim2(void) { + dispatch_general(TIMER2); +} + +void __irq_tim3(void) { + dispatch_general(TIMER3); +} + +void __irq_tim4(void) { + dispatch_general(TIMER4); +} + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + +void __irq_tim5(void) { + dispatch_general(TIMER5); +} + +void __irq_tim6(void) { + dispatch_basic(TIMER6); +} + +void __irq_tim7(void) { + dispatch_basic(TIMER7); +} + +void __irq_tim8_brk(void) { + dispatch_adv_brk(TIMER8); +} + +void __irq_tim8_up(void) { + dispatch_adv_up(TIMER8); +} + +void __irq_tim8_trg_com(void) { + dispatch_adv_trg_com(TIMER8); +} + +void __irq_tim8_cc(void) { + dispatch_adv_cc(TIMER8); +} +#endif + +static inline void dispatch_irq(timer_dev *dev, uint8 iid, uint8 sr_bit); +static inline void dispatch_cc_irqs(timer_dev *dev); + +static inline void dispatch_adv_brk(timer_dev *dev) { + dispatch_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF_BIT); +} + +static inline void dispatch_adv_up(timer_dev *dev) { + dispatch_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF_BIT); +} + +static inline void dispatch_adv_trg_com(timer_dev *dev) { + dispatch_irq(dev, TIMER_TRG_INTERRUPT, TIMER_SR_TIF_BIT); + dispatch_irq(dev, TIMER_COM_INTERRUPT, TIMER_SR_COMIF_BIT); +} + +static inline void dispatch_adv_cc(timer_dev *dev) { + dispatch_cc_irqs(dev); +} + +static inline void dispatch_general(timer_dev *dev) { + dispatch_irq(dev, TIMER_TRG_INTERRUPT, TIMER_SR_TIF_BIT); + dispatch_cc_irqs(dev); + dispatch_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF_BIT); +} + +static inline void dispatch_basic(timer_dev *dev) { + dispatch_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF_BIT); +} + +static inline void dispatch_irq(timer_dev *dev, uint8 iid, uint8 sr_bit) { + __io uint32 *sr = &(dev->regs).bas->SR; + if (bb_peri_get_bit(sr, sr_bit)) { + if (dev->handlers[iid]) + (dev->handlers[iid])(); + bb_peri_set_bit(sr, sr_bit, 0); + } +} + +static inline void dispatch_cc_irqs(timer_dev *dev) { + uint32 sr = (dev->regs).gen->SR; + uint32 sr_clear = 0; + uint32 b; + + ASSERT(sr & (TIMER_SR_CC1IF | TIMER_SR_CC2IF | + TIMER_SR_CC3IF | TIMER_SR_CC4IF)); + + for (b = TIMER_SR_CC1IF_BIT; b <= TIMER_SR_CC4IF_BIT; b++) { + uint32 mask = BIT(b); + if (sr & mask) { + if (dev->handlers[b]) + (dev->handlers[b])(); + sr_clear |= mask; + } + } + + (dev->regs).gen->SR &= ~sr_clear; +} + +/* + * Utilities + */ + +static void disable_channel(timer_dev *dev, uint8 channel) { + timer_detach_interrupt(dev, channel); + timer_cc_disable(dev, channel); +} + +static void pwm_mode(timer_dev *dev, uint8 channel) { + timer_disable_interrupt(dev, channel); + timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); + timer_cc_enable(dev, channel); +} + +static void output_compare_mode(timer_dev *dev, uint8 channel) { + timer_oc_set_mode(dev, channel, TIMER_OC_MODE_ACTIVE_ON_MATCH, 0); + timer_cc_enable(dev, channel); +} + +static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id); +static void enable_nonmuxed_irq(timer_dev *dev); + +static inline void enable_irq(timer_dev *dev, timer_interrupt_id iid) { + if (dev->type == TIMER_ADVANCED) { + enable_advanced_irq(dev, iid); + } else { + enable_nonmuxed_irq(dev); + } +} + +static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id) { + uint8 is_timer1 = dev->clk_id == RCC_TIMER1; + + switch (id) { + case TIMER_UPDATE_INTERRUPT: + nvic_irq_enable(is_timer1 ? NVIC_TIMER1_UP : NVIC_TIMER8_UP); + break; + case TIMER_CC1_INTERRUPT: + case TIMER_CC2_INTERRUPT: + case TIMER_CC3_INTERRUPT: + case TIMER_CC4_INTERRUPT: + nvic_irq_enable(is_timer1 ? NVIC_TIMER1_CC : NVIC_TIMER8_CC); + break; + case TIMER_COM_INTERRUPT: + case TIMER_TRG_INTERRUPT: + nvic_irq_enable(is_timer1 ? NVIC_TIMER1_TRG_COM : NVIC_TIMER8_TRG_COM); + break; + case TIMER_BREAK_INTERRUPT: + nvic_irq_enable(is_timer1 ? NVIC_TIMER1_BRK : NVIC_TIMER8_BRK); + break; + } +} + +static void enable_nonmuxed_irq(timer_dev *dev) { + switch (dev->clk_id) { + case RCC_TIMER2: + nvic_irq_enable(NVIC_TIMER2); + break; + case RCC_TIMER3: + nvic_irq_enable(NVIC_TIMER3); + break; + case RCC_TIMER4: + nvic_irq_enable(NVIC_TIMER4); + break; +#ifdef STM32_HIGH_DENSITY + case RCC_TIMER5: + nvic_irq_enable(NVIC_TIMER5); + break; + case RCC_TIMER6: + nvic_irq_enable(NVIC_TIMER6); + break; + case RCC_TIMER7: + nvic_irq_enable(NVIC_TIMER7); + break; +#endif + default: + ASSERT(0); + break; + } +} diff --git a/libmaple/timer.h b/libmaple/timer.h new file mode 100644 index 0000000..025bcb0 --- /dev/null +++ b/libmaple/timer.h @@ -0,0 +1,1010 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file timer.h + * @author Marti Bolivar + * @brief New-style timer interface. + * + * Replaces old timers.h implementation. + */ + +#ifndef _TIMERS_H_ +#define _TIMERS_H_ + +#include "libmaple.h" +#include "rcc.h" +#include "nvic.h" +#include "bitband.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Register maps and devices + */ + +/** Advanced control timer register map type */ +typedef struct timer_adv_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SMCR; /**< Slave mode control register */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + __io uint32 CCMR1; /**< Capture/compare mode register 1 */ + __io uint32 CCMR2; /**< Capture/compare mode register 2 */ + __io uint32 CCER; /**< Capture/compare enable register */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ + __io uint32 RCR; /**< Repetition counter register */ + __io uint32 CCR1; /**< Capture/compare register 1 */ + __io uint32 CCR2; /**< Capture/compare register 2 */ + __io uint32 CCR3; /**< Capture/compare register 3 */ + __io uint32 CCR4; /**< Capture/compare register 4 */ + __io uint32 BDTR; /**< Break and dead-time register */ + __io uint32 DCR; /**< DMA control register */ + __io uint32 DMAR; /**< DMA address for full transfer */ +} timer_adv_reg_map; + +/** General purpose timer register map type */ +typedef struct timer_gen_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SMCR; /**< Slave mode control register */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + __io uint32 CCMR1; /**< Capture/compare mode register 1 */ + __io uint32 CCMR2; /**< Capture/compare mode register 2 */ + __io uint32 CCER; /**< Capture/compare enable register */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 CCR1; /**< Capture/compare register 1 */ + __io uint32 CCR2; /**< Capture/compare register 2 */ + __io uint32 CCR3; /**< Capture/compare register 3 */ + __io uint32 CCR4; /**< Capture/compare register 4 */ + const uint32 RESERVED2; /**< Reserved */ + __io uint32 DCR; /**< DMA control register */ + __io uint32 DMAR; /**< DMA address for full transfer */ +} timer_gen_reg_map; + +/** Basic timer register map type */ +typedef struct timer_bas_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + const uint32 RESERVED2; /**< Reserved */ + const uint32 RESERVED3; /**< Reserved */ + const uint32 RESERVED4; /**< Reserved */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ +} timer_bas_reg_map; + +/** Timer 1 register map base pointer */ +#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) +/** Timer 2 register map base pointer */ +#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) +/** Timer 3 register map base pointer */ +#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) +/** Timer 4 register map base pointer */ +#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) +#ifdef STM32_HIGH_DENSITY +/** Timer 5 register map base pointer */ +#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) +/** Timer 6 register map base pointer */ +#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) +/** Timer 7 register map base pointer */ +#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) +/** Timer 8 register map base pointer */ +#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) +#endif + +/* + * Timer devices + */ + +typedef union { + timer_adv_reg_map *adv; + timer_gen_reg_map *gen; + timer_bas_reg_map *bas; +} timer_reg_map_union; + +typedef enum { + TIMER_ADVANCED, + TIMER_GENERAL, + TIMER_BASIC +} timer_type; + +/** Timer device type */ +typedef struct timer_dev { + timer_reg_map_union regs; + rcc_clk_id clk_id; + timer_type type; + voidFuncPtr handlers[]; +} timer_dev; + +/** Timer 1 device (advanced) */ +extern timer_dev *TIMER1; +/** Timer 2 device (general-purpose) */ +extern timer_dev *TIMER2; +/** Timer 3 device (general-purpose) */ +extern timer_dev *TIMER3; +/** Timer 4 device (general-purpose) */ +extern timer_dev *TIMER4; +#ifdef STM32_HIGH_DENSITY +/** Timer 5 device (general-purpose) */ +extern timer_dev *TIMER5; +/** Timer 6 device (basic) */ +extern timer_dev *TIMER6; +/** Timer 7 device (basic) */ +extern timer_dev *TIMER7; +/** Timer 8 device (basic) */ +extern timer_dev *TIMER8; +#endif + +/* + * Register bit definitions + */ + +/* Control register 1 (CR1) */ + +#define TIMER_CR1_ARPE_BIT 7 +#define TIMER_CR1_DIR_BIT 4 +#define TIMER_CR1_OPM_BIT 3 +#define TIMER_CR1_URS_BIT 2 +#define TIMER_CR1_UDIS_BIT 1 +#define TIMER_CR1_CEN_BIT 0 + +#define TIMER_CR1_CKD (0x3 << 8) +#define TIMER_CR1_CKD_1TCKINT (0x0 << 8) +#define TIMER_CR1_CKD_2TCKINT (0x1 << 8) +#define TIMER_CR1_CKD_4TICKINT (0x2 << 8) +#define TIMER_CR1_ARPE BIT(TIMER_CR1_ARPE_BIT) +#define TIMER_CR1_CKD_CMS (0x3 << 5) +#define TIMER_CR1_CKD_CMS_EDGE (0x0 << 5) +#define TIMER_CR1_CKD_CMS_CENTER1 (0x1 << 5) +#define TIMER_CR1_CKD_CMS_CENTER2 (0x2 << 5) +#define TIMER_CR1_CKD_CMS_CENTER3 (0x3 << 5) +#define TIMER_CR1_DIR BIT(TIMER_CR1_DIR_BIT) +#define TIMER_CR1_OPM BIT(TIMER_CR1_OPM_BIT) +#define TIMER_CR1_URS BIT(TIMER_CR1_URS_BIT) +#define TIMER_CR1_UDIS BIT(TIMER_CR1_UDIS_BIT) +#define TIMER_CR1_CEN BIT(TIMER_CR1_CEN_BIT) + +/* Control register 2 (CR2) */ + +#define TIMER_CR2_OIS4_BIT 14 +#define TIMER_CR2_OIS3N_BIT 13 +#define TIMER_CR2_OIS3_BIT 12 +#define TIMER_CR2_OIS2N_BIT 11 +#define TIMER_CR2_OIS2_BIT 10 +#define TIMER_CR2_OIS1N_BIT 9 +#define TIMER_CR2_OIS1_BIT 8 +#define TIMER_CR2_TI1S_BIT 7 /* tills? yikes */ +#define TIMER_CR2_CCDS_BIT 3 +#define TIMER_CR2_CCUS_BIT 2 +#define TIMER_CR2_CCPC_BIT 0 + +#define TIMER_CR2_OIS4 BIT(TIMER_CR2_OIS4_BIT) +#define TIMER_CR2_OIS3N BIT(TIMER_CR2_OIS3N_BIT) +#define TIMER_CR2_OIS3 BIT(TIMER_CR2_OIS3_BIT) +#define TIMER_CR2_OIS2N BIT(TIMER_CR2_OIS2N_BIT) +#define TIMER_CR2_OIS2 BIT(TIMER_CR2_OIS2_BIT) +#define TIMER_CR2_OIS1N BIT(TIMER_CR2_OIS1N_BIT) +#define TIMER_CR2_OIS1 BIT(TIMER_CR2_OIS1_BIT) +#define TIMER_CR2_TI1S BIT(TIMER_CR2_TI1S_BIT) +#define TIMER_CR2_MMS (0x7 << 4) +#define TIMER_CR2_MMS_RESET (0x0 << 4) +#define TIMER_CR2_MMS_ENABLE (0x1 << 4) +#define TIMER_CR2_MMS_UPDATE (0x2 << 4) +#define TIMER_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIMER_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIMER_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIMER_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIMER_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIMER_CR2_CCDS BIT(TIMER_CR2_CCDS_BIT) +#define TIMER_CR2_CCUS BIT(TIMER_CR2_CCUS_BIT) +#define TIMER_CR2_CCPC BIT(TIMER_CR2_CCPC_BIT) + +/* Slave mode control register (SMCR) */ + +#define TIMER_SMCR_ETP_BIT 15 +#define TIMER_SMCR_ECE_BIT 14 +#define TIMER_SMCR_MSM_BIT 7 + +#define TIMER_SMCR_ETP BIT(TIMER_SMCR_ETP_BIT) +#define TIMER_SMCR_ECE BIT(TIMER_SMCR_ECE_BIT) +#define TIMER_SMCR_ETPS (0x3 << 12) +#define TIMER_SMCR_ETPS_OFF (0x0 << 12) +#define TIMER_SMCR_ETPS_DIV2 (0x1 << 12) +#define TIMER_SMCR_ETPS_DIV4 (0x2 << 12) +#define TIMER_SMCR_ETPS_DIV8 (0x3 << 12) +#define TIMER_SMCR_ETF (0xF << 12) +#define TIMER_SMCR_MSM BIT(TIMER_SMCR_MSM_BIT) +#define TIMER_SMCR_TS (0x3 << 4) +#define TIMER_SMCR_TS_ITR0 (0x0 << 4) +#define TIMER_SMCR_TS_ITR1 (0x1 << 4) +#define TIMER_SMCR_TS_ITR2 (0x2 << 4) +#define TIMER_SMCR_TS_ITR3 (0x3 << 4) +#define TIMER_SMCR_TS_TI1F_ED (0x4 << 4) +#define TIMER_SMCR_TS_TI1FP1 (0x5 << 4) +#define TIMER_SMCR_TS_TI2FP2 (0x6 << 4) +#define TIMER_SMCR_TS_ETRF (0x7 << 4) +#define TIMER_SMCR_SMS 0x3 +#define TIMER_SMCR_SMS_DISABLED 0x0 +#define TIMER_SMCR_SMS_ENCODER1 0x1 +#define TIMER_SMCR_SMS_ENCODER2 0x2 +#define TIMER_SMCR_SMS_ENCODER3 0x3 +#define TIMER_SMCR_SMS_RESET 0x4 +#define TIMER_SMCR_SMS_GATED 0x5 +#define TIMER_SMCR_SMS_TRIGGER 0x6 +#define TIMER_SMCR_SMS_EXTERNAL 0x7 + +/* DMA/Interrupt enable register (DIER) */ + +#define TIMER_DIER_TDE_BIT 14 +#define TIMER_DIER_CC4DE_BIT 12 +#define TIMER_DIER_CC3DE_BIT 11 +#define TIMER_DIER_CC2DE_BIT 10 +#define TIMER_DIER_CC1DE_BIT 9 +#define TIMER_DIER_UDE_BIT 8 +#define TIMER_DIER_TIE_BIT 6 +#define TIMER_DIER_CC4IE_BIT 4 +#define TIMER_DIER_CC3IE_BIT 3 +#define TIMER_DIER_CC2IE_BIT 2 +#define TIMER_DIER_CC1IE_BIT 1 +#define TIMER_DIER_UIE_BIT 0 + +#define TIMER_DIER_TDE BIT(TIMER_DIER_TDE_BIT) +#define TIMER_DIER_CC4DE BIT(TIMER_DIER_CC4DE_BIT) +#define TIMER_DIER_CC3DE BIT(TIMER_DIER_CC3DE_BIT) +#define TIMER_DIER_CC2DE BIT(TIMER_DIER_CC2DE_BIT) +#define TIMER_DIER_CC1DE BIT(TIMER_DIER_CC1DE_BIT) +#define TIMER_DIER_UDE BIT(TIMER_DIER_UDE_BIT) +#define TIMER_DIER_TIE BIT(TIMER_DIER_TIE_BIT) +#define TIMER_DIER_CC4IE BIT(TIMER_DIER_CC4IE_BIT) +#define TIMER_DIER_CC3IE BIT(TIMER_DIER_CC3IE_BIT) +#define TIMER_DIER_CC2IE BIT(TIMER_DIER_CC2IE_BIT) +#define TIMER_DIER_CC1IE BIT(TIMER_DIER_CC1IE_BIT) +#define TIMER_DIER_UIE BIT(TIMER_DIER_UIE_BIT) + +/* Status register (SR) */ + +#define TIMER_SR_CC4OF_BIT 12 +#define TIMER_SR_CC3OF_BIT 11 +#define TIMER_SR_CC2OF_BIT 10 +#define TIMER_SR_CC1OF_BIT 9 +#define TIMER_SR_BIF_BIT 7 +#define TIMER_SR_TIF_BIT 6 +#define TIMER_SR_COMIF_BIT 5 +#define TIMER_SR_CC4IF_BIT 4 +#define TIMER_SR_CC3IF_BIT 3 +#define TIMER_SR_CC2IF_BIT 2 +#define TIMER_SR_CC1IF_BIT 1 +#define TIMER_SR_UIF_BIT 0 + +#define TIMER_SR_CC4OF BIT(TIMER_SR_CC4OF_BIT) +#define TIMER_SR_CC3OF BIT(TIMER_SR_CC3OF_BIT) +#define TIMER_SR_CC2OF BIT(TIMER_SR_CC2OF_BIT) +#define TIMER_SR_CC1OF BIT(TIMER_SR_CC1OF_BIT) +#define TIMER_SR_BIF BIT(TIMER_SR_BIF_BIT) +#define TIMER_SR_TIF BIT(TIMER_SR_TIF_BIT) +#define TIMER_SR_COMIF BIT(TIMER_SR_COMIF_BIT) +#define TIMER_SR_CC4IF BIT(TIMER_SR_CC4IF_BIT) +#define TIMER_SR_CC3IF BIT(TIMER_SR_CC3IF_BIT) +#define TIMER_SR_CC2IF BIT(TIMER_SR_CC2IF_BIT) +#define TIMER_SR_CC1IF BIT(TIMER_SR_CC1IF_BIT) +#define TIMER_SR_UIF BIT(TIMER_SR_UIF_BIT) + +/* Event generation register (EGR) */ + +#define TIMER_EGR_TG_BIT 6 +#define TIMER_EGR_CC4G_BIT 4 +#define TIMER_EGR_CC3G_BIT 3 +#define TIMER_EGR_CC2G_BIT 2 +#define TIMER_EGR_CC1G_BIT 1 +#define TIMER_EGR_UG_BIT 0 + +#define TIMER_EGR_TG BIT(TIMER_EGR_TG_BIT) +#define TIMER_EGR_CC4G BIT(TIMER_EGR_CC4G_BIT) +#define TIMER_EGR_CC3G BIT(TIMER_EGR_CC3G_BIT) +#define TIMER_EGR_CC2G BIT(TIMER_EGR_CC2G_BIT) +#define TIMER_EGR_CC1G BIT(TIMER_EGR_CC1G_BIT) +#define TIMER_EGR_UG BIT(TIMER_EGR_UG_BIT) + +/* Capture/compare mode registers, common values */ + +#define TIMER_CCMR_CCS_OUTPUT 0x0 +#define TIMER_CCMR_CCS_INPUT_TI1 0x1 +#define TIMER_CCMR_CCS_INPUT_TI2 0x2 +#define TIMER_CCMR_CCS_INPUT_TRC 0x3 + +/* Capture/compare mode register 1 (CCMR1) */ + +#define TIMER_CCMR1_OC2CE_BIT 15 +#define TIMER_CCMR1_OC2PE_BIT 11 +#define TIMER_CCMR1_OC2FE_BIT 10 +#define TIMER_CCMR1_OC1CE_BIT 7 +#define TIMER_CCMR1_OC1PE_BIT 3 +#define TIMER_CCMR1_OC1FE_BIT 2 + +#define TIMER_CCMR1_OC2CE BIT(TIMER_CCMR1_OC2CE_BIT) +#define TIMER_CCMR1_OC2M (0x3 << 12) +#define TIMER_CCMR1_IC2F (0xF << 12) +#define TIMER_CCMR1_OC2PE BIT(TIMER_CCMR1_OC2PE_BIT) +#define TIMER_CCMR1_OC2FE BIT(TIMER_CCMR1_OC2FE_BIT) +#define TIMER_CCMR1_IC2PSC (0x3 << 10) +#define TIMER_CCMR1_CC2S (0x3 << 8) +#define TIMER_CCMR1_CC2S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) +#define TIMER_CCMR1_OC1CE BIT(TIMER_CCMR1_OC1CE_BIT) +#define TIMER_CCMR1_OC1M (0x3 << 4) +#define TIMER_CCMR1_IC1F (0xF << 4) +#define TIMER_CCMR1_OC1PE BIT(TIMER_CCMR1_OC1PE_BIT) +#define TIMER_CCMR1_OC1FE BIT(TIMER_CCMR1_OC1FE_BIT) +#define TIMER_CCMR1_IC1PSC (0x3 << 2) +#define TIMER_CCMR1_CC1S 0x3 +#define TIMER_CCMR1_CC1S_OUTPUT TIMER_CCMR_CCS_OUTPUT +#define TIMER_CCMR1_CC1S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 +#define TIMER_CCMR1_CC1S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 +#define TIMER_CCMR1_CC1S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC + +/* Capture/compare mode register 2 (CCMR2) */ + +#define TIMER_CCMR2_OC4CE_BIT 15 +#define TIMER_CCMR2_OC4PE_BIT 11 +#define TIMER_CCMR2_OC4FE_BIT 10 +#define TIMER_CCMR2_OC3CE_BIT 7 +#define TIMER_CCMR2_OC3PE_BIT 3 +#define TIMER_CCMR2_OC3FE_BIT 2 + +#define TIMER_CCMR2_OC4CE BIT(TIMER_CCMR2_OC4CE_BIT) +#define TIMER_CCMR2_OC4M (0x3 << 12) +#define TIMER_CCMR2_IC2F (0xF << 12) +#define TIMER_CCMR2_OC4PE BIT(TIMER_CCMR2_OC4PE_BIT) +#define TIMER_CCMR2_OC4FE BIT(TIMER_CCMR2_OC4FE_BIT) +#define TIMER_CCMR2_IC2PSC (0x3 << 10) +#define TIMER_CCMR2_CC4S (0x3 << 8) +#define TIMER_CCMR1_CC4S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) +#define TIMER_CCMR1_CC4S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) +#define TIMER_CCMR1_CC4S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR1_CC4S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) +#define TIMER_CCMR2_OC3CE BIT(TIMER_CCMR2_OC3CE_BIT) +#define TIMER_CCMR2_OC3M (0x3 << 4) +#define TIMER_CCMR2_IC1F (0xF << 4) +#define TIMER_CCMR2_OC3PE BIT(TIMER_CCMR2_OC3PE_BIT) +#define TIMER_CCMR2_OC3FE BIT(TIMER_CCMR2_OC3FE_BIT) +#define TIMER_CCMR2_IC1PSC (0x3 << 2) +#define TIMER_CCMR2_CC3S 0x3 +#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR_CCS_OUTPUT +#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 +#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 +#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC + +/* Capture/compare enable register (CCER) */ + +#define TIMER_CCER_CC4P_BIT 13 +#define TIMER_CCER_CC4E_BIT 12 +#define TIMER_CCER_CC3P_BIT 9 +#define TIMER_CCER_CC3E_BIT 8 +#define TIMER_CCER_CC2P_BIT 5 +#define TIMER_CCER_CC2E_BIT 4 +#define TIMER_CCER_CC1P_BIT 1 +#define TIMER_CCER_CC1E_BIT 0 + +#define TIMER_CCER_CC4P BIT(TIMER_CCER_CC4P_BIT) +#define TIMER_CCER_CC4E BIT(TIMER_CCER_CC4E_BIT) +#define TIMER_CCER_CC3P BIT(TIMER_CCER_CC3P_BIT) +#define TIMER_CCER_CC3E BIT(TIMER_CCER_CC3E_BIT) +#define TIMER_CCER_CC2P BIT(TIMER_CCER_CC2P_BIT) +#define TIMER_CCER_CC2E BIT(TIMER_CCER_CC2E_BIT) +#define TIMER_CCER_CC1P BIT(TIMER_CCER_CC1P_BIT) +#define TIMER_CCER_CC1E BIT(TIMER_CCER_CC1E_BIT) + +/* Break and dead-time register (BDTR) */ + +#define TIMER_BDTR_MOE_BIT 15 +#define TIMER_BDTR_AOE_BIT 14 +#define TIMER_BDTR_BKP_BIT 13 +#define TIMER_BDTR_BKE_BIT 12 +#define TIMER_BDTR_OSSR_BIT 11 +#define TIMER_BDTR_OSSI_BIT 10 + +#define TIMER_BDTR_MOE BIT(TIMER_BDTR_MOE_BIT) +#define TIMER_BDTR_AOE BIT(TIMER_BDTR_AOE_BIT) +#define TIMER_BDTR_BKP BIT(TIMER_BDTR_BKP_BIT) +#define TIMER_BDTR_BKE BIT(TIMER_BDTR_BKE_BIT) +#define TIMER_BDTR_OSSR BIT(TIMER_BDTR_OSSR_BIT) +#define TIMER_BDTR_OSSI BIT(TIMER_BDTR_OSSI_BIT) +#define TIMER_BDTR_LOCK (0x3 << 8) +#define TIMER_BDTR_LOCK_OFF (0x0 << 8) +#define TIMER_BDTR_LOCK_LEVEL1 (0x1 << 8) +#define TIMER_BDTR_LOCK_LEVEL2 (0x2 << 8) +#define TIMER_BDTR_LOCK_LEVEL3 (0x3 << 8) +#define TIMER_BDTR_DTG 0xFF + +/* DMA control register (DCR) */ + +#define TIMER_DCR_DBL (0x1F << 8) +#define TIMER_DCR_DBL_1BYTE (0x0 << 8) +#define TIMER_DCR_DBL_2BYTE (0x1 << 8) +#define TIMER_DCR_DBL_3BYTE (0x2 << 8) +#define TIMER_DCR_DBL_4BYTE (0x3 << 8) +#define TIMER_DCR_DBL_5BYTE (0x4 << 8) +#define TIMER_DCR_DBL_6BYTE (0x5 << 8) +#define TIMER_DCR_DBL_7BYTE (0x6 << 8) +#define TIMER_DCR_DBL_8BYTE (0x7 << 8) +#define TIMER_DCR_DBL_9BYTE (0x8 << 8) +#define TIMER_DCR_DBL_10BYTE (0x9 << 8) +#define TIMER_DCR_DBL_11BYTE (0xA << 8) +#define TIMER_DCR_DBL_12BYTE (0xB << 8) +#define TIMER_DCR_DBL_13BYTE (0xC << 8) +#define TIMER_DCR_DBL_14BYTE (0xD << 8) +#define TIMER_DCR_DBL_15BYTE (0xE << 8) +#define TIMER_DCR_DBL_16BYTE (0xF << 8) +#define TIMER_DCR_DBL_17BYTE (0x10 << 8) +#define TIMER_DCR_DBL_18BYTE (0x11 << 8) +#define TIMER_DCR_DBA 0x1F +#define TIMER_DCR_DBA_CR1 0x0 +#define TIMER_DCR_DBA_CR2 0x1 +#define TIMER_DCR_DBA_SMCR 0x2 +#define TIMER_DCR_DBA_DIER 0x3 +#define TIMER_DCR_DBA_SR 0x4 +#define TIMER_DCR_DBA_EGR 0x5 +#define TIMER_DCR_DBA_CCMR1 0x6 +#define TIMER_DCR_DBA_CCMR2 0x7 +#define TIMER_DCR_DBA_CCER 0x8 +#define TIMER_DCR_DBA_CNT 0x9 +#define TIMER_DCR_DBA_PSC 0xA +#define TIMER_DCR_DBA_ARR 0xB +#define TIMER_DCR_DBA_RCR 0xC +#define TIMER_DCR_DBA_CCR1 0xD +#define TIMER_DCR_DBA_CCR2 0xE +#define TIMER_DCR_DBA_CCR3 0xF +#define TIMER_DCR_DBA_CCR4 0x10 +#define TIMER_DCR_DBA_BDTR 0x11 +#define TIMER_DCR_DBA_DCR 0x12 +#define TIMER_DCR_DBA_DMAR 0x13 + +/* + * Convenience routines + */ + +/** + * Used to configure the behavior of a timer channel. Note that not + * all timers can be configured in every mode. + */ +/* TODO TIMER_PWM_CENTER_ALIGNED, TIMER_INPUT_CAPTURE, TIMER_ONE_PULSE */ +typedef enum timer_mode { + TIMER_DISABLED, /**< In this mode, the timer stops counting, + channel interrupts are detached, and no state + changes are output. */ + TIMER_PWM, /**< PWM output mode. This is the default mode for pins + after initialization. */ + /* TIMER_PWM_CENTER_ALIGNED, /\**< Center-aligned PWM output mode. *\/ */ + TIMER_OUTPUT_COMPARE, /**< In this mode, the timer counts from 0 + to its reload value repeatedly; every + time the counter value reaches one of + the channel compare values, the + corresponding interrupt is fired. */ + /* TIMER_INPUT_CAPTURE, /\**< In this mode, the timer can measure the */ + /* pulse lengths of input signals. *\/ */ + /* TIMER_ONE_PULSE /\**< In this mode, the timer can generate a single */ + /* pulse on a GPIO pin for a specified amount of */ + /* time. *\/ */ +} timer_mode; + +/** Timer channel numbers */ +typedef enum timer_channel { + TIMER_CH1 = 1, /**< Channel 1 */ + TIMER_CH2 = 2, /**< Channel 2 */ + TIMER_CH3 = 3, /**< Channel 3 */ + TIMER_CH4 = 4 /**< Channel 4 */ +} timer_channel; + +/* + * Note: Don't require timer_channel arguments! We want to be able to say + * + * for (int channel = 1; channel <= 4; channel++) { + * ... + * } + * + * without the compiler yelling at us. + */ + +void timer_init(timer_dev *dev); +void timer_disable(timer_dev *dev); +void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode); +void timer_foreach(void (*fn)(timer_dev*)); + +/** + * @brief Timer interrupt number. + * + * Not all timers support all of these values; see the descriptions + * for each value. + */ +typedef enum timer_interrupt_id { + TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */ + TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt, available + on general and advanced timers only. */ + TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt, general and + advanced timers only. */ + TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt, general and + advanced timers only. */ + TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt, general and + advanced timers only. */ + TIMER_COM_INTERRUPT, /**< COM interrupt, advanced timers only */ + TIMER_TRG_INTERRUPT, /**< Trigger interrupt, general and advanced + timers only */ + TIMER_BREAK_INTERRUPT /**< Break interrupt, advanced timers only. */ +} timer_interrupt_id; + +void timer_attach_interrupt(timer_dev *dev, + uint8 interrupt, + voidFuncPtr handler); +void timer_detach_interrupt(timer_dev *dev, uint8 interrupt); + +/** + * Initialize all timer devices on the chip. + */ +static inline void timer_init_all(void) { + timer_foreach(timer_init); +} + +/** + * Disables all timers on the device. + */ +static inline void timer_disable_all(void) { + timer_foreach(timer_disable); +} + +/** + * @brief Stop a timer's counter from changing. + * + * Does not affect the timer's mode or other settings. + * + * @param dev Device whose counter to pause. + */ +static inline void timer_pause(timer_dev *dev) { + *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 0; +} + +/** + * @brief Start a timer's counter. + * + * Does not affect the timer's mode or other settings. + * + * @param dev Device whose counter to resume + */ +static inline void timer_resume(timer_dev *dev) { + *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 1; +} + +/** + * @brief Returns the timer's counter value. + * + * This value is likely to be inaccurate if the counter is running + * with a low prescaler. + * + * @param dev Timer whose counter to return + */ +static inline uint16 timer_get_count(timer_dev *dev) { + return (uint16)(dev->regs).bas->CNT; +} + +/** + * @brief Sets the counter value for the given timer. + * @param timer_num Timer whose counter to set + * @param value New counter value + */ +static inline void timer_set_count(timer_dev *dev, uint16 value) { + (dev->regs).bas->CNT = value; +} + +/** + * @brief Returns the given timer's prescaler. + * + * Note that if the timer's prescaler is set (e.g. via + * timer_set_prescaler() or accessing a TIMx_PSC register), the value + * returned by this function will reflect the new setting, but the + * timer's counter will only reflect the new prescaler at the next + * update event. + * + * @param dev Timer whose prescaler to return + * @see timer_generate_update() + */ +static inline uint16 timer_get_prescaler(timer_dev *dev) { + return (uint16)(dev->regs).bas->PSC; +} + +/** + * @brief Set a timer's prescale value. + * + * The new value will not take effect until the next update event. + * + * @param dev Timer whose prescaler to set + * @param psc New prescaler value + * @see timer_generate_update() + */ +static inline void timer_set_prescaler(timer_dev *dev, uint16 psc) { + (dev->regs).bas->PSC = psc; +} + +/** + * @brief Returns a timer's reload value. + * @param dev Timer whose reload value to return + */ +static inline uint16 timer_get_reload(timer_dev *dev) { + return (uint16)(dev->regs).bas->ARR; +} + +/** + * @brief Set a timer's reload value. + * @param dev Timer whose reload value to set + * @param arr New reload value to use. Takes effect at next update event. + * @see timer_generate_update() + */ +static inline void timer_set_reload(timer_dev *dev, uint16 arr) { + (dev->regs).bas->ARR = arr; +} + +/** + * @brief Get the compare value for the given timer channel. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose compare value to get. + */ +static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) { + __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1); + return *ccr; +} + +/** + * @brief Set the compare value for the given timer channel. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose compare value to set. + * @param value New compare value. + */ +static inline void timer_set_compare(timer_dev *dev, + uint8 channel, + uint16 value) { + __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1); + *ccr = value; +} + +/** + * @brief Generate an update event for the given timer. + * + * Normally, this will cause the prescaler and auto-reload values in + * the PSC and ARR registers to take immediate effect. However, this + * function will do nothing if the UDIS bit is set in the timer's CR1 + * register (UDIS is cleared by default). + * + * @param dev Timer device to generate an update for. + */ +static inline void timer_generate_update(timer_dev *dev) { + *bb_perip(&(dev->regs).bas->EGR, TIMER_EGR_UG_BIT) = 1; +} + +/** + * @brief Enable a timer's trigger DMA request + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + */ +static inline void timer_trigger_dma_enable_request(timer_dev *dev) { + *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 1; +} + +/** + * @brief Disable a timer's trigger DMA request + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + */ +static inline void timer_trigger_dma_disable_request(timer_dev *dev) { + *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 0; +} + +/** + * @brief Enable a timer channel's DMA request. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + * @param channel Channel whose DMA request to enable. + */ +static inline void timer_dma_enable_request(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 1; +} + +/** + * @brief Disable a timer channel's DMA request. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose DMA request to disable. + */ +static inline void timer_dma_disable_request(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 0; +} + +/** + * @brief Enable a timer interrupt. + * @param dev Timer device. + * @param interrupt Interrupt number to enable; this may be any + * timer_interrupt_id value appropriate for the timer. + * @see timer_interrupt_id + * @see timer_channel + */ +static inline void timer_enable_interrupt(timer_dev *dev, uint8 interrupt) { + *bb_perip(&(dev->regs).adv->DIER, interrupt) = 1; +} + +/** + * @brief Disable a timer interrupt. + * @param dev Timer device. + * @param interrupt Interrupt number to disable; this may be any + * timer_interrupt_id value appropriate for the timer. + * @see timer_interrupt_id + * @see timer_channel + */ +static inline void timer_disable_interrupt(timer_dev *dev, uint8 interrupt) { + *bb_perip(&(dev->regs).adv->DIER, interrupt) = 0; +} + +/** + * @brief Enable a timer channel's capture/compare signal. + * + * If the channel is configured as output, the corresponding output + * compare signal will be output on the corresponding output pin. If + * the channel is configured as input, enables capture of the counter + * value into the input capture/compare register. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel to enable, from 1 to 4. + */ +static inline void timer_cc_enable(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 1; +} + +/** + * @brief Disable a timer channel's output compare or input capture signal. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel to disable, from 1 to 4. + * @see timer_cc_enable() + */ +static inline void timer_cc_disable(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 0; +} + +/** + * @brief Get a channel's capture/compare output polarity + * @brief dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @brief channel Channel whose capture/compare output polarity to get. + * @return Polarity, either 0 or 1. + * @see timer_cc_set_polarity() + */ +static inline uint8 timer_cc_get_polarity(timer_dev *dev, uint8 channel) { + return *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1); +} + +/** + * @brief Set a timer channel's capture/compare output polarity. + * + * If the timer channel is configured as output: polarity == 0 means + * the output channel will be active high; polarity == 1 means active + * low. + * + * If the timer channel is configured as input: polarity == 0 means + * capture is done on the rising edge of ICn; when used as an external + * trigger, ICn is non-inverted. polarity == 1 means capture is done + * on the falling edge of ICn; when used as an external trigger, ICn + * is inverted. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose capture/compare output polarity to set. + * @param pol New polarity, 0 or 1. + */ +static inline void timer_cc_set_polarity(timer_dev *dev, + uint8 channel, + uint8 pol) { + *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1) = pol; +} + +/** + * @brief Get a timer's DMA burst length. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @return Number of bytes to be transferred per DMA request, from 1 to 18. + */ +static inline uint8 timer_get_dma_burst_length(timer_dev *dev) { + uint32 dbl = ((dev->regs).gen->DCR & TIMER_DCR_DBL) >> 8; + return dbl + 1; /* 0 means 1 byte, etc. */ +} + +/** + * @brief Set a timer's DMA burst length. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param length DMA burst length; i.e., number of bytes to transfer + * per DMA request, from 1 to 18. + */ +static inline void timer_set_dma_burst_length(timer_dev *dev, uint8 length) { + uint32 tmp = (dev->regs).gen->DCR; + tmp &= ~TIMER_DCR_DBL; + tmp |= (length << 8) - 1; + (dev->regs).gen->DCR = tmp; +} + +/** + * @brief Timer DMA base address. + * + * Defines the base address for DMA transfers. + */ +typedef enum timer_dma_base_address { + TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, /**< Base is control register 1 */ + TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, /**< Base is control register 2 */ + TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, /**< Base is slave mode + control register */ + TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, /**< Base is DMA interrupt enable + register */ + TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, /**< Base is status register */ + TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, /**< Base is event generation + register */ + TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, /**< Base is capture/compare + mode register 1 */ + TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, /**< Base is capture/compare + mode register 2 */ + TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER, /**< Base is capture/compare + enable register */ + TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT, /**< Base is counter */ + TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC, /**< Base is prescaler */ + TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR, /**< Base is auto-reload + register */ + TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR, /**< Base is repetition + counter register */ + TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1, /**< Base is capture/compare + register 1 */ + TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2, /**< Base is capture/compare + register 2 */ + TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3, /**< Base is capture/compare + register 3 */ + TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4, /**< Base is capture/compare + register 4 */ + TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR, /**< Base is break and + dead-time register */ + TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR, /**< Base is DMA control + register */ + TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR /**< Base is DMA address for + full transfer */ +} timer_dma_base_address; + +/** + * @brief Get the timer's DMA base address. + * + * Some restrictions apply; see ST RM0008. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @return DMA base address + */ +static inline timer_dma_base_address +timer_get_dma_base_address(timer_dev *dev) { + uint32 dcr = (dev->regs).gen->DCR; + return (timer_dma_base_address)(dcr & TIMER_DCR_DBA); +} + +/** + * @brief Set the timer's DMA base address. + * + * Some restrictions apply; see ST RM0008. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param dma_base DMA base address. + */ +static inline void +timer_set_dma_base_address(timer_dev *dev, timer_dma_base_address dma_base) { + uint32 tmp = (dev->regs).gen->DCR; + tmp &= ~TIMER_DCR_DBA; + tmp |= dma_base; + (dev->regs).gen->DCR = tmp; +} + +/** + * Timer output compare modes. + */ +typedef enum timer_oc_mode { + TIMER_OC_MODE_FROZEN = 0 << 4, /**< Frozen: comparison between output + compare register and counter has no + effect on the outputs. */ + TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, /**< OCxREF signal is forced + high when the count matches + the channel capture/compare + register. */ + TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, /**< OCxREF signal is forced + low when the counter matches + the channel capture/compare + register. */ + TIMER_OC_MODE_TOGGLE = 3 << 4, /**< OCxREF toggles when counter + matches the cannel capture/compare + register. */ + TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, /**< OCxREF is forced low. */ + TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, /**< OCxREF is forced high. */ + TIMER_OC_MODE_PWM_1 = 6 << 4, /**< PWM mode 1. In upcounting, channel is + active as long as count is less than + channel capture/compare register, else + inactive. In downcounting, channel is + inactive as long as count exceeds + capture/compare register, else + active. */ + TIMER_OC_MODE_PWM_2 = 7 << 4 /**< PWM mode 2. In upcounting, channel is + inactive as long as count is less than + capture/compare register, else active. + In downcounting, channel is active as + long as count exceeds capture/compare + register, else inactive. */ +} timer_oc_mode; + +/** + * Timer output compare mode flags. + * @see timer_oc_set_mode() + */ +typedef enum timer_oc_mode_flags { + TIMER_OC_CE = BIT(7), /**< Output compare clear enable. */ + TIMER_OC_PE = BIT(3), /**< Output compare preload enable. */ + TIMER_OC_FE = BIT(2) /**< Output compare fast enable. */ +} timer_oc_mode_flags; + +/** + * @brief Configure a channel's output compare mode. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel to configure in output compare mode. + * @param flags OR of timer_oc_mode_flags. + * @see timer_oc_mode + * @see timer_oc_mode_flags + */ +static inline void timer_oc_set_mode(timer_dev *dev, + uint8 channel, + timer_oc_mode mode, + uint8 flags) { + uint8 bit0 = channel & 1; + uint8 bit1 = (channel >> 1) & 1; + /* channel == 1,2 -> CCMR1; channel == 3,4 -> CCMR2 */ + __io uint32 *ccmr = &(dev->regs).gen->CCMR1 + bit1; + /* channel == 1,3 -> shift = 0, channel == 2,4 -> shift = 8 */ + uint8 shift = 8 * (1 - bit0); + + uint32 tmp = *ccmr; + tmp &= ~(0xFF << shift); + tmp |= (mode | flags | TIMER_CCMR_CCS_OUTPUT) << shift; + *ccmr = tmp; +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/timers.c b/libmaple/timers.c deleted file mode 100644 index c561d39..0000000 --- a/libmaple/timers.c +++ /dev/null @@ -1,526 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - *****************************************************************************/ - -/** - * @brief General timer routines - */ - -/* TODO: actually support timer5 and timer8 */ - -#include "libmaple.h" -#include "rcc.h" -#include "nvic.h" -#include "timers.h" - -/* Timer descriptor table */ -struct timer_dev timer_dev_table[] = { - [TIMER1] = { - .base = (timer_port*)TIMER1_BASE, - .rcc_dev_num = RCC_TIMER1, - .nvic_dev_num = NVIC_TIMER1 - }, - [TIMER2] = { - .base = (timer_port*)TIMER2_BASE, - .rcc_dev_num = RCC_TIMER2, - .nvic_dev_num = NVIC_TIMER2 - }, - [TIMER3] = { - .base = (timer_port*)TIMER3_BASE, - .rcc_dev_num = RCC_TIMER3, - .nvic_dev_num = NVIC_TIMER3 - }, - [TIMER4] = { - .base = (timer_port*)TIMER4_BASE, - .rcc_dev_num = RCC_TIMER4, - .nvic_dev_num = NVIC_TIMER4 - }, -#ifdef STM32_HIGH_DENSITY - /* High density devices only (eg, Maple Native) */ - [TIMER5] = { - .base = (timer_port*)TIMER5_BASE, - .rcc_dev_num = RCC_TIMER5, - .nvic_dev_num = NVIC_TIMER5 - }, - [TIMER8] = { - .base = (timer_port*)TIMER8_BASE, - .rcc_dev_num = RCC_TIMER8, - .nvic_dev_num = NVIC_TIMER8 - }, -#endif -}; - -/* This function should probably be rewriten to take (timer_num, mode) - * and have prescaler set elsewhere. The mode can be passed through to - * set_mode at the end */ -void timer_init(timer_dev_num timer_num, uint16 prescale) { - /* TODO: doesn't catch 6+7 */ - - timer_port *timer = timer_dev_table[timer_num].base; - uint8 is_advanced = 0; - - if (timer_num == TIMER1) { - is_advanced = 1; - } -#ifdef STM32_HIGH_DENSITY - if (timer_num == TIMER8) { - is_advanced = 1; - } -#endif - - rcc_clk_enable(timer_dev_table[timer_num].rcc_dev_num); - - timer->CR1 = ARPE; // No clock division - // Do not buffer auto-reload preload - // Edge aligned - // Upcounter - // Do not stop counter at update event - // Update events enabled (etc, see bits [1:2]) - // Counter disabled for now - - timer->PSC = prescale; // Prescaling by prescale (duh) - timer->ARR = 0xFFFF; // Max reload cont - - /* initialize all the channels to 50% duty cycle, - * TODO: none of them actually get output unless the gpio pin - * is set, this will probably consume a bit more power but - * we'll worry about that later. */ - timer->CCR1 = 0x8FFF; // PWM start value - timer->CCMR1 |= 0x68; // PWM mode 1, enable preload register. - - timer->CCR2 = 0x8FFF; // PWM start value - timer->CCMR1 |= (0x68 << 8);// PWM mode 1, enable preload register. - - timer->CCR3 = 0x8FFF; // PWM start value - timer->CCMR2 |= 0x68; // PWM mode 1, enable preload register. - - timer->CCR4 = 0x8FFF; // PWM start value - timer->CCMR2 |= (0x68 << 8);// PWM mode 1, enable preload register. - - /* Advanced timer? */ - if (is_advanced) { - timer->BDTR = 0x8000; // moe enable - } - - timer->SR = 0; // clear it - timer->DIER = 0; // disable update interrupt - timer->EGR = 1; // Initialize update event and shadow registers - timer->CR1 |= 1; // Enable timer -} - -/* Stops the counter; the mode and settings are not modified */ -void timer_pause(timer_dev_num timer_num) { - timer_port *timer = timer_dev_table[timer_num].base; - - timer->CR1 &= ~(0x0001); // CEN -} - -/* Starts the counter; the mode and settings are not modified */ -void timer_resume(timer_dev_num timer_num) { - timer_port *timer = timer_dev_table[timer_num].base; - - timer->CR1 |= 0x0001; // CEN -} - -/* Returns the current timer counter value. Probably very inaccurate - * if the counter is running with a low prescaler. */ -uint16 timer_get_count(timer_dev_num timer_num) { - timer_port *timer = timer_dev_table[timer_num].base; - - return timer->CNT; -} - -/* This function sets the counter value via register for the specified - * timer. Can't think of specific usecases except for resetting to - * zero but it's easy to implement and allows for "creative" - * programming */ -void timer_set_count(timer_dev_num timer_num, uint16 value) { - timer_port *timer = timer_dev_table[timer_num].base; - - timer->CNT = value; -} - -/* Get the prescaler buffer value (remember, the actual prescaler - * doesn't get set until an update event). */ -uint16 timer_get_prescaler(timer_dev_num timer_num) { - timer_port *timer = timer_dev_table[timer_num].base; - return timer->PSC; -} - -/* Sets the prescaler */ -void timer_set_prescaler(timer_dev_num timer_num, uint16 prescale) { - timer_port *timer = timer_dev_table[timer_num].base; - - timer->PSC = prescale; -} - -/* Get the reload value for the entire timer. */ -uint16 timer_get_reload(timer_dev_num timer_num) { - timer_port *timer = timer_dev_table[timer_num].base; - return timer->ARR; -} - -/* This sets the "reload" or "overflow" value for the entire timer. We - * should probably settle on either "reload" or "overflow" to prevent - * confusion? */ -void timer_set_reload(timer_dev_num timer_num, uint16 max_reload) { - timer_port *timer = timer_dev_table[timer_num].base; - - timer->ARR = max_reload; -} - -/* This quickly disables all 4 timers, presumably as part of a system shutdown - * or similar to prevent interrupts and PWM output without 16 seperate function - * calls to timer_set_mode */ -void timer_disable_all(void) { - timer_port *timer; -#ifdef STM32_HIGH_DENSITY - timer_port *timers[6] = { (timer_port*)TIMER1_BASE, - (timer_port*)TIMER2_BASE, - (timer_port*)TIMER3_BASE, - (timer_port*)TIMER4_BASE, - (timer_port*)TIMER5_BASE, - (timer_port*)TIMER8_BASE, - }; - uint8 i; - for (i = 0; i < 6; i++) { - timer = timers[i]; - timer->CR1 = 0; - timer->CCER = 0; - } -#else - timer_port *timers[4] = { (timer_port*)TIMER1_BASE, - (timer_port*)TIMER2_BASE, - (timer_port*)TIMER3_BASE, - (timer_port*)TIMER4_BASE, - }; - uint8 i; - for (i = 0; i < 4; i++) { - timer = timers[i]; - timer->CR1 = 0; - timer->CCER = 0; - } -#endif -} - -/* Sets the mode of individual timer channels, including a DISABLE mode */ -void timer_set_mode(timer_dev_num timer_num, uint8 channel, TimerMode mode) { - timer_port *timer = timer_dev_table[timer_num].base; - ASSERT(channel >= 1); - - switch(mode) { - case TIMER_DISABLED: - /* Disable the channel - * Disable any interrupt - * Clear interrupt SR? (TODO) */ - timer->DIER &= ~(1 << channel); // 1-indexed compare nums - timer_detach_interrupt(timer_num, channel); - timer->CCER &= ~(1 << (4*(channel - 1))); // 0-indexed - break; - case TIMER_PWM: - /* Set CCMR mode - * Keep existing reload value - * Disable any interrupt - * Clear interrupt SR? (TODO) - * Enable channel */ - timer->DIER &= ~(1 << channel); // 1-indexed compare nums - switch (channel) { - case 1: - timer->CCMR1 &= ~(0xFF); - timer->CCMR1 |= 0x68; // PWM mode 1, enable preload register. - break; - case 2: - timer->CCMR1 &= ~(0xFF00); - timer->CCMR1 |= (0x68 << 8);// PWM mode 1, enable preload register. - break; - case 3: - timer->CCMR2 &= ~(0xFF); - timer->CCMR2 |= 0x68; // PWM mode 1, enable preload register. - break; - case 4: - timer->CCMR2 &= ~(0xFF00); - timer->CCMR2 |= (0x68 << 8);// PWM mode 1, enable preload register. - break; - default: - ASSERT(0); - } - timer->CCER |= (1 << (4*(channel - 1))); // Enable - break; - case TIMER_OUTPUTCOMPARE: - /* Set CCMR mode - * Keep existing reload value - * Don't modify interrupt (needs to be attached to enable) - * Clear interrupt SR? (TODO) - * Enable channel */ - switch (channel) { - case 1: - timer->CCMR1 &= ~(0xFF); - timer->CCMR1 |= 0x0010; // PWM mode 1, enable preload register. - break; - case 2: - timer->CCMR1 &= ~(0xFF00); - timer->CCMR1 |= 0x1000; // PWM mode 1, enable preload register. - break; - case 3: - timer->CCMR2 &= ~(0xFF); - timer->CCMR2 |= 0x0010; // PWM mode 1, enable preload register. - break; - case 4: - timer->CCMR2 &= ~(0xFF00); - timer->CCMR2 |= 0x1000; // PWM mode 1, enable preload register. - break; - default: - ASSERT(0); - } - timer->CCER |= (1 << (4*(channel - 1))); // Enable - break; - default: - ASSERT(0); - } -} - -uint16 timer_get_compare_value(timer_dev_num timer_num, uint8 channel_num) { - /* faster: just read TIMERx_CHy_CCR (see timers.h) */ - ASSERT(channel_num > 0 && channel_num <= 4); - timer_port *timer = timer_dev_table[timer_num].base; - switch(channel_num) { - case 1: - return timer->CCR1; - case 2: - return timer->CCR2; - case 3: - return timer->CCR3; - case 4: - return timer->CCR4; - default: /* in case ASSERT is disabled */ - return 0; - } -} - -/* This sets the compare value (aka the trigger) for a given timer - * channel */ -void timer_set_compare_value(timer_dev_num timer_num, - uint8 channel_num, - uint16 value) { - ASSERT(channel_num > 0 && channel_num <= 4); - - /* The faster version of this function is the inline - timer_pwm_write_ccr */ - timer_port *timer = timer_dev_table[timer_num].base; - - switch(channel_num) { - case 1: - timer->CCR1 = value; - break; - case 2: - timer->CCR2 = value; - break; - case 3: - timer->CCR3 = value; - break; - case 4: - timer->CCR4 = value; - break; - } -} - -/* Stores a pointer to the passed usercode interrupt function and configures - * the actual ISR so that it will actually be called */ -void timer_attach_interrupt(timer_dev_num timer_num, - uint8 compare_num, - voidFuncPtr handler) { - ASSERT(compare_num > 0 && compare_num <= 4); - - timer_port *timer = timer_dev_table[timer_num].base; - - timer_dev_table[timer_num].handlers[compare_num-1] = handler; - timer->DIER |= (1 << compare_num); // 1-indexed compare nums - nvic_irq_enable(timer_dev_table[timer_num].nvic_dev_num); -} - -void timer_detach_interrupt(timer_dev_num timer_num, uint8 compare_num) { - ASSERT(compare_num > 0 && compare_num <= 4); - - timer_port *timer = timer_dev_table[timer_num].base; - - timer_dev_table[timer_num].handlers[compare_num-1] = 0; - timer->DIER &= ~(1 << compare_num); // 1-indexed compare nums -} - -void timer_generate_update(timer_dev_num timer_num) { - /* cause update event by setting UG bit in EGR. updates prescaler - ratio etc. */ - timer_port *timer = timer_dev_table[timer_num].base; - timer->EGR |= 0x1; -} - -/* The following are the actual interrupt handlers; 1 for each timer which must - * determine which actual compare value (aka channel) was triggered. - * - * These ISRs get called when the timer interrupt is enabled, the - * timer is running, and the timer count equals any of the CCR - * registers /or/ has overflowed. - * - * This is a rather long implementation... */ -void __irq_tim1_cc(void) { - timer_port *timer = (timer_port*)TIMER1_BASE; - uint16 sr_buffer; - sr_buffer = timer->SR; - - /* Simply switch/case-ing here doesn't work because multiple - * CC flags may be high. */ - if(sr_buffer & 0x10){ // CC4 flag - timer->SR &= ~(0x10); - if(timer_dev_table[TIMER1].handlers[3]) { - timer_dev_table[TIMER1].handlers[3](); - } - } - if(sr_buffer & 0x8){ // CC3 flag - timer->SR &= ~(0x8); - if(timer_dev_table[TIMER1].handlers[2]) { - timer_dev_table[TIMER1].handlers[2](); - } - } - if(sr_buffer & 0x4){ // CC2 flag - timer->SR &= ~(0x4); - if(timer_dev_table[TIMER1].handlers[1]) { - timer_dev_table[TIMER1].handlers[1](); - } - } - if(sr_buffer & 0x2){ // CC1 flag - timer->SR &= ~(0x2); - if(timer_dev_table[TIMER1].handlers[0]) { - timer_dev_table[TIMER1].handlers[0](); - } - } - if(sr_buffer & 0x1){ // Update flag - timer->SR &= ~(0x1); - //timer->EGR = 1; - } -} -void __irq_tim2(void) { - /* This is a rather long implementation... */ - timer_port *timer = (timer_port*)TIMER2_BASE; - uint16 sr_buffer; - sr_buffer = timer->SR; - - if(sr_buffer & 0x10){ // CC4 flag - timer->SR &= ~(0x10); - if(timer_dev_table[TIMER2].handlers[3]) { - timer_dev_table[TIMER2].handlers[3](); - } - } - if(sr_buffer & 0x8){ // CC3 flag - timer->SR &= ~(0x8); - if(timer_dev_table[TIMER2].handlers[2]) { - timer_dev_table[TIMER2].handlers[2](); - } - } - if(sr_buffer & 0x4){ // CC2 flag - timer->SR &= ~(0x4); - if(timer_dev_table[TIMER2].handlers[1]) { - timer_dev_table[TIMER2].handlers[1](); - } - } - if(sr_buffer & 0x2){ // CC1 flag - timer->SR &= ~(0x2); - if(timer_dev_table[TIMER2].handlers[0]) { - timer_dev_table[TIMER2].handlers[0](); - } - } - if(sr_buffer & 0x1){ // Update flag - timer->SR &= ~(0x1); - //timer->EGR = 1; - } -} -void __irq_tim3(void) { - /* This is a rather long implementation... */ - timer_port *timer = (timer_port*)TIMER3_BASE; - uint16 sr_buffer; - sr_buffer = timer->SR; - - if(sr_buffer & 0x10){ // CC4 flag - timer->SR &= ~(0x10); - if(timer_dev_table[TIMER3].handlers[3]) { - timer_dev_table[TIMER3].handlers[3](); - } - } - if(sr_buffer & 0x8){ // CC3 flag - timer->SR &= ~(0x8); - if(timer_dev_table[TIMER3].handlers[2]) { - timer_dev_table[TIMER3].handlers[2](); - } - } - if(sr_buffer & 0x4){ // CC2 flag - timer->SR &= ~(0x4); - if(timer_dev_table[TIMER3].handlers[1]) { - timer_dev_table[TIMER3].handlers[1](); - } - } - if(sr_buffer & 0x2){ // CC1 flag - timer->SR &= ~(0x2); - if(timer_dev_table[TIMER3].handlers[0]) { - timer_dev_table[TIMER3].handlers[0](); - } - } - if(sr_buffer & 0x1){ // Update flag - timer->SR &= ~(0x1); - //timer->EGR = 1; - } -} - -void __irq_tim4(void) { - /* This is a rather long implementation... */ - timer_port*timer = (timer_port*)TIMER4_BASE; - uint16 sr_buffer; - sr_buffer = timer->SR; - - if(sr_buffer & 0x10){ // CC4 flag - timer->SR &= ~(0x10); - if(timer_dev_table[TIMER4].handlers[3]) { - timer_dev_table[TIMER4].handlers[3](); - } - } - if(sr_buffer & 0x8){ // CC3 flag - timer->SR &= ~(0x8); - if(timer_dev_table[TIMER4].handlers[2]) { - timer_dev_table[TIMER4].handlers[2](); - } - } - if(sr_buffer & 0x4){ // CC2 flag - timer->SR &= ~(0x4); - if(timer_dev_table[TIMER4].handlers[1]) { - timer_dev_table[TIMER4].handlers[1](); - } - } - if(sr_buffer & 0x2){ // CC1 flag - timer->SR &= ~(0x2); - if(timer_dev_table[TIMER4].handlers[0]) { - timer_dev_table[TIMER4].handlers[0](); - } - } - if(sr_buffer & 0x1){ // Update flag - timer->SR &= ~(0x1); - //timer->EGR = 1; - } -} diff --git a/libmaple/timers.h b/libmaple/timers.h deleted file mode 100644 index 1f6afcd..0000000 --- a/libmaple/timers.h +++ /dev/null @@ -1,435 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - *****************************************************************************/ - -/** - * @file timers.h - * - * @brief Timer prototypes and various definitions - */ - -/* Note to self: - * The timer clock frequencies are automatically fixed by hardware. - * There are two cases: - * 1. if the APB prescaler is 1, the timer clock frequencies are - * set to the same frequency as that of the APB domain to which - * the timers are connected. - * 2. otherwise, they are set to twice (x2) the frequency of the - * APB domain to which the timers are connected. - * See stm32 manual, 77/995 - * - * hence, 72 mhz timers - */ - -/* Maple Timer channels: - * Timer Maple Pin STM32 Pin Type - * TIM1_CH1 D6 PA8 Advanced - * TIM1_CH2 D7 PA9 Advanced - * TIM1_CH3 D8 PA10 Advanced - * - * TIM2_CH1 D2 PA0 - * TIM2_CH2 D3 PA1 - * TIM2_CH3 D1 PA2 - * TIM2_CH4 D0 PA3 - * - * TIM3_CH1 D12 PA6 - * TIM3_CH2 D11 PA7 - * TIM3_CH3 EXT7 PB0 - * TIM3_CH4 EXT8 PB1 - * - * TIM4_CH1 EXT5 PB6 - * TIM4_CH1 EXT9 PB7 - * TIM4_CH1 EXT15 PB8 - * TIM4_CH1 EXT4 PB9 - * - * Not supported: - * TIM1_CH4 USBDM, not available PA11 Advanced - * TIM1_CH1_N EXT12 PB13 - * TIM1_CH2_N EXT13 PB14 - * TIM1_CH3_N EXT14 PB15 - * */ - -/* I don't like the Arduino API for dealing with pin modes. - * How about... - * - * pinMode(digitalPin, PWM); - * pwmWrite(digitalPin) */ - -#ifndef _TIMERS_H_ -#define _TIMERS_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -typedef volatile uint16* TimerCCR; - -#define TIMER1_BASE 0x40012C00 -#define TIMER2_BASE 0x40000000 -#define TIMER3_BASE 0x40000400 -#define TIMER4_BASE 0x40000800 -#define TIMER5_BASE 0x40000C00 // High-density devices only -#define TIMER6_BASE 0x40001000 // High-density devices only -#define TIMER7_BASE 0x40001400 // High-density devices only -#define TIMER8_BASE 0x40013400 // High-density devices only - -#define ARPE BIT(7) // Auto-reload preload enable -#define NOT_A_TIMER 0 - -#define TIMER_CCR(NUM,CHAN) (TIMER ## NUM ## _CH ## CHAN ## _CRR) - -/* Timers 1-4 are present on the entire STM32 line. */ - -#define TIMER1_CH1_CCR ((TimerCCR)(TIMER1_BASE + 0x34)) -#define TIMER1_CH2_CCR ((TimerCCR)(TIMER1_BASE + 0x38)) -#define TIMER1_CH3_CCR ((TimerCCR)(TIMER1_BASE + 0x3C)) -#define TIMER1_CH4_CCR ((TimerCCR)(TIMER1_BASE + 0x40)) - -#define TIMER2_CH1_CCR ((TimerCCR)(TIMER2_BASE + 0x34)) -#define TIMER2_CH2_CCR ((TimerCCR)(TIMER2_BASE + 0x38)) -#define TIMER2_CH3_CCR ((TimerCCR)(TIMER2_BASE + 0x3C)) -#define TIMER2_CH4_CCR ((TimerCCR)(TIMER2_BASE + 0x40)) - -#define TIMER3_CH1_CCR ((TimerCCR)(TIMER3_BASE + 0x34)) -#define TIMER3_CH2_CCR ((TimerCCR)(TIMER3_BASE + 0x38)) -#define TIMER3_CH3_CCR ((TimerCCR)(TIMER3_BASE + 0x3C)) -#define TIMER3_CH4_CCR ((TimerCCR)(TIMER3_BASE + 0x40)) - -#define TIMER4_CH1_CCR ((TimerCCR)(TIMER4_BASE + 0x34)) -#define TIMER4_CH2_CCR ((TimerCCR)(TIMER4_BASE + 0x38)) -#define TIMER4_CH3_CCR ((TimerCCR)(TIMER4_BASE + 0x3C)) -#define TIMER4_CH4_CCR ((TimerCCR)(TIMER4_BASE + 0x40)) - -/* Timers 5 and 8 are in high-density devices only (such as Maple - Native). Timers 6 and 7 in these devices have no output compare - pins. */ - -#define TIMER5_CH1_CCR ((TimerCCR)(TIMER5_BASE + 0x34)) -#define TIMER5_CH2_CCR ((TimerCCR)(TIMER5_BASE + 0x38)) -#define TIMER5_CH3_CCR ((TimerCCR)(TIMER5_BASE + 0x3C)) -#define TIMER5_CH4_CCR ((TimerCCR)(TIMER5_BASE + 0x40)) - -#define TIMER8_CH1_CCR ((TimerCCR)(TIMER8_BASE + 0x34)) -#define TIMER8_CH2_CCR ((TimerCCR)(TIMER8_BASE + 0x38)) -#define TIMER8_CH3_CCR ((TimerCCR)(TIMER8_BASE + 0x3C)) -#define TIMER8_CH4_CCR ((TimerCCR)(TIMER8_BASE + 0x40)) - -/** - * Used to configure the behavior of a timer. - */ -typedef enum TimerMode { - TIMER_DISABLED, /**< In this mode, the timer stops counting, - interrupts are not called, and no state changes - are output. */ - TIMER_PWM, /**< This is the default mode for pins after - initialization. */ - TIMER_OUTPUTCOMPARE, /**< In this mode, the timer counts from 0 to - its reload value repeatedly; every time - the counter value reaches one of the - channel compare values, the corresponding - interrupt is fired. */ -} TimerMode; - -typedef struct { - /* Fields up to ARR common to general purpose (2,3,4,5), advanced - control (1,8) and basic (6, 7) timers: */ - volatile uint16 CR1; - uint16 RESERVED0; - volatile uint16 CR2; - uint16 RESERVED1; - volatile uint16 SMCR; - uint16 RESERVED2; - volatile uint16 DIER; - uint16 RESERVED3; - volatile uint16 SR; - uint16 RESERVED4; - volatile uint16 EGR; - uint16 RESERVED5; - volatile uint16 CCMR1; - uint16 RESERVED6; - volatile uint16 CCMR2; - uint16 RESERVED7; - volatile uint16 CCER; - uint16 RESERVED8; - volatile uint16 CNT; - uint16 RESERVED9; - volatile uint16 PSC; - uint16 RESERVED10; - volatile uint16 ARR; - uint16 RESERVED11; - /* Basic timers have none of the following: */ - volatile uint16 RCR; /* Advanced control timers only */ - uint16 RESERVED12; /* Advanced control timers only */ - volatile uint16 CCR1; - uint16 RESERVED13; - volatile uint16 CCR2; - uint16 RESERVED14; - volatile uint16 CCR3; - uint16 RESERVED15; - volatile uint16 CCR4; - uint16 RESERVED16; - volatile uint16 BDTR; /* Advanced control timers only */ - uint16 RESERVED17; /* Advanced control timers only */ - volatile uint16 DCR; - uint16 RESERVED18; - volatile uint16 DMAR; - uint16 RESERVED19; -} timer_port; - -/** - * Timer device numbers. See STM32 reference manual, chapters 13-15. - */ -/* several locations depend on TIMER1=0, etc.; don't change the - enumerator values to start at 1. */ -typedef enum { - TIMER1, /*< Advanced control timer TIM1 */ - TIMER2, /*< General purpose timer TIM2 */ - TIMER3, /*< General purpose timer TIM3 */ - TIMER4, /*< General purpose timer TIM4 */ -#ifdef STM32_HIGH_DENSITY - TIMER5, /*< General purpose timer TIM5; high density only */ - /* FIXME maple native: put timers 6 and 7 back in and make the - corresponding changes to timers.c */ - /* TIMER6, /\*< Basic timer TIM6; high density only *\/ */ - /* TIMER7, /\*< Basic timer TIM7; high density only *\/ */ - TIMER8, /*< Advanced control timer TIM8; high density only */ -#endif - TIMER_INVALID /* FIXME: this is starting to seem like a bad idea */ -} timer_dev_num; - -/* timer descriptor */ -struct timer_dev { - timer_port *base; - const uint8 rcc_dev_num; - const uint8 nvic_dev_num; - volatile voidFuncPtr handlers[4]; -}; - -extern struct timer_dev timer_dev_table[]; - -/** - * Initializes timer with prescale as the clock divisor. - * - * @param timer_num Timer number. - * - * @param prescale value in the range 1--65535 to use as a prescaler - * for timer counter increment frequency. - * - * @see timer_dev_num - * @see timer_set_prescaler() - * @see timer_set_mode() - */ -void timer_init(timer_dev_num timer_num, uint16 prescale); - -/** - * Quickly disable all timers. Calling this function is faster than, - * e.g., calling timer_set_mode() for all available timers/channels. - */ -void timer_disable_all(void); - -/** - * Returns the timer's counter value. Due to function call overhead, - * this value is likely to be inaccurate if the counter is running - * with a low prescaler. - * - * @param timer_num the timer whose counter to return. - * - * @pre Timer has been initialized. - */ -uint16 timer_get_count(timer_dev_num timer_num); - -/** - * Sets the counter value for the given timer. - * - * @param timer_num the timer whose counter to set. - * - * @param value the new counter value. - * - * @pre Timer has been initialized. - */ -void timer_set_count(timer_dev_num timer_num, uint16 value); - -/** - * Stops the timer's counter from incrementing. Does not modify the - * timer's mode or settings. - * - * @param timer_num the timer to pause. - * - * @see timer_resume() - * - * @pre Timer has been initialized. - */ -void timer_pause(timer_dev_num timer_num); - -/** - * Starts the counter for the given timer. Does not modify the - * timer's mode or settings. The timer will begin counting on the - * first rising clock cycle after it has been re-enabled using this - * function. - * - * @param timer_num the timer to resume. - * - * @see timer_pause() - * - * @pre Timer has been initialized. - */ -void timer_resume(timer_dev_num timer_num); - -/** - * Returns the prescaler for the given timer. - * - * @param timer_num the timer whose prescaler to return. - * - * @see timer_set_prescaler() - * - * @pre Timer has been initialized. - */ -uint16 timer_get_prescaler(timer_dev_num timer_num); - -/** - * Sets the prescaler for the given timer. This value goes into the - * PSC register, so it's 0-based (i.e., a prescale of 0 counts 1 tick - * per clock cycle). This prescale does not take effect until the - * next update event. - * - * @param timer_num the timer whose prescaler to set. - * - * @param prescale the new prescaler. - * - * @pre Timer has been initialized. - */ -void timer_set_prescaler(timer_dev_num timer_num, uint16 prescale); - -/** - * Gets the reload value for the timer. - * - * @see timer_set_reload() - * - * @pre Timer has been initialized. - */ -uint16 timer_get_reload(timer_dev_num timer_num); - -/** - * Sets the reload value for the timer. - * - * After this function returns, the timer's counter will reset to 0 - * after it has reached the value max_reload. - * - * @pre Timer has been initialized. - */ -void timer_set_reload(timer_dev_num timer_num, uint16 max_reload); - -/* TODO: timer_get_mode */ - -/** - * Set the mode of an individual timer channel. - * - * @see timer_disable_all() - * @see TimerMode - * @see timer_dev_num - * @pre Timer has been initialized. - */ -void timer_set_mode(timer_dev_num timer_num, uint8 channel, TimerMode mode); - -/** - * Get the compare value for the given timer channel. - * @see timer_set_compare_value() - * @see timer_dev_num - * @pre Timer has been initialized. - */ -uint16 timer_get_compare_value(timer_dev_num timer_num, uint8 channel); - -/** - * Sets the compare value for a given timer channel. Useful for - * scheduling when interrupt handlers will be called. - * - * @see timer_attach_interrupt() - * @see timer_detach_interrupt() - * @see timer_set_reload() - * @see timer_dev_num - * @pre Timer has been initialized. - */ -void timer_set_compare_value(timer_dev_num timer_num, uint8 channel, - uint16 value); - -/** - * Detach the interrupt handler for the given timer channel, if any. - * After this function returns, any handler attached to the given - * channel will no longer be called. - * - * @see timer_attach_interrupt() - * @pre Timer has been initialized. - * @see timer_dev_num - */ -void timer_detach_interrupt(timer_dev_num timer_num, uint8 channel); - -/** - * Attach an interrupt handler for the given timer and channel. The - * given ISR, handler, will be called whenever the timer's counter - * reaches the compare value for the given timer and channel. - * - * @see timer_set_compare_value() - * @see timer_detach_interrupt() - * @see timer_set_mode() - * @see timer_dev_num - * @see voidFuncPtr - * @pre Timer has been initialized. - * @pre The channel's mode must be set to TIMER_OUTPUTCOMPARE, or the - * interrupt handler will not get called. - */ -void timer_attach_interrupt(timer_dev_num timer_num, uint8 channel, - voidFuncPtr handler); - -/** - * Programmatically generate an update event on the given timer. This - * updates the prescaler, reloads the compare value (in upcounting - * mode, etc.). - * - * @pre Timer has been initialized. - */ -void timer_generate_update(timer_dev_num timer_num); - -/** - * Turn on PWM with duty_cycle. - * - * @param ccr TIMERx_CHn_CCR, where x ranges over timers, and n ranges - * from 1 to 4. - * - * @param duty_cycle: A number between 0 and - * timer_get_compare_value(TIMERx, y), where x and y are as above. - * - * @pre Pin has been set to alternate function output. - * - * @pre Timer has been initialized. - */ -static inline void timer_pwm_write_ccr(TimerCCR ccr, uint16 duty_cycle) { - *ccr = duty_cycle; -} - -#ifdef __cplusplus -} // extern "C" -#endif - - -#endif - diff --git a/libmaple/util.c b/libmaple/util.c index 09fbecd..6b4f216 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -32,7 +32,7 @@ #include "gpio.h" #include "nvic.h" #include "adc.h" -#include "timers.h" +#include "timer.h" /* Failed asserts send out a message on this USART. */ #ifndef ERROR_USART_NUM diff --git a/libraries/Servo/Servo.h b/libraries/Servo/Servo.h index 1c75618..583312e 100644 --- a/libraries/Servo/Servo.h +++ b/libraries/Servo/Servo.h @@ -28,6 +28,7 @@ #include #include "wirish.h" /* hack for IDE compile */ +#include "HardwareTimer.h" /* Note on Arduino compatibility: diff --git a/notes/portable.txt b/notes/portable.txt index 69952d7..cc1f2ac 100644 --- a/notes/portable.txt +++ b/notes/portable.txt @@ -1,98 +1,28 @@ +Board portability is implemented in boards.h, libmaple.h, and stm32.h. -Disclaimer text: // High-density devices only (Maple Native) +At compile time, we currently expect one of STM32_MEDIUM_DENSITY or +STM32_HIGH_DENSITY to be defined. There's no support for low-density +chips. XL-density isn't in the near horizon; patches welcome. You'll +also need to define some BOARD_foo if you expect to use Wirish; this +comes along with some additional assumptions about your board's layout. +The code in usb/ is not very portable at all right now; expect this to +change in the future, but for now, we're focusing on rolling out a +more complete backend. -Board portability is implemented by adding a header file to ./libmaple with the -name of the BOARD target, and then editing libmaple.h to add this file as an -option. - -A pin maple file should be added to ./notes describing the pin numbering - -Files to check by hand: -# adc.c -# adc.h -# exc.c -# exti.c -# exti.h -# flash.c -# flash.h -# gpio.c -# gpio.h -# libmaple_types.h -# nvic.c -# nvic.h -# rcc.c -# rcc.h -# ring_buffer.h -# rules.mk -# spi.c -- spi.h -# syscalls.c -# systick.c -# systick.h -# timers.c -# timers.h -# usart.c -# usart.h -# util.c -# util.h -# libmaple.h -# usb/* - -wirish/: -# bits.h -# boards.h -# cxxabi-compat.cpp -# ext_interrupts.c -# ext_interrupts.h -# HardwareTimer.cpp -# HardwareTimer.h -# io.h -# main.cxx -# Print.cpp -# Print.h -# pwm.c -# pwm.h -# rules.mk -# time.c -# time.h -# usb_serial.cpp -# usb_serial.h -# wirish_analog.c -# wirish.c -# wirish_digital.c -# wirish.h -# wirish_math.cpp -# wirish_math.h -# wirish_shift.c -# WProgram.h -- comm/ - - - -ADC Notes: - only using ADC1? - untested - -EXTI Notes: - need to update huge table in comments? - untested +A file should be added to ./notes describing the pin numbering of any +new board you add. NVIC Notes: - I don't think NVIC_ISER3 and NVIC_ICER3 actually exist? Only CANBUS and USB OTG use interrupts above #63, but I updated the nvic code anyways RCC Notes: Added some clock stuff to all boards even though they aren't usable... blah. SPI Notes: - SPI3 is only in XL chips so didn't really handle that + SPI3 is only in XL chips, so we don't handle that. TIMER Notes: - High-density devices add an advanced timer (TIMER8) and another normal one (TIMER5). - TIMER6 and TIMER7 are much less useful. - There is some partial progress towards adding timer5/timer8 functionality, - but not much. This should probably all be rewritten. The wirish timer implementation should be refactored to use pin numbers. USART Notes: diff --git a/notes/usb.txt b/notes/usb.txt index 5e00354..9552b9f 100644 --- a/notes/usb.txt +++ b/notes/usb.txt @@ -1,3 +1,7 @@ +XXX +XXX This file may be out of date! +XXX + [NOTE: this is a long term proposal. The current implementation just does a 2ms TIMEOUT] diff --git a/notes/vga.txt b/notes/vga.txt index d75281a..43b6830 100644 --- a/notes/vga.txt +++ b/notes/vga.txt @@ -7,8 +7,7 @@ gpio_write_bit() is about 360ns (2.78MHz) Writing to GPIO?_BASE is about 60ns (16.6MHz -> 18MHz) -pwm write 0x0001 is about 30ns (33MHz) with prescaler as 1 (default) -pwm write 0x0001 is about 14ns (72MHz) with prescaler as 0 (!) +PWM write 0x0001 is about 14ns (72MHz) with prescaler as 0 (!) VGA Timing ------------------------------------------------------------------------------ @@ -34,9 +33,3 @@ Crude 640x480 directions: 11 lines front porch 2 lines Vsync (low) 31 lines back porch - -Currently, setting vs. clearing GPIO registers seems to take a different amount -of time? Or perhaps i'm not analyzing branching correctly. Regardless, if you -SET 100x times then UNSET on one line, then UNSET 100x then SET the next line, -the two changes in color will generally not line up. - diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 66f008f..d99b019 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -1,96 +1,56 @@ #include "boards.h" -// think of the poor column numbers +// For concision #define ADCx ADC_INVALID -#define TIMERx TIMER_INVALID #if defined(BOARD_maple) PinMapping PIN_MAP[NR_GPIO_PINS] = { - /* D0/PA3 */ - {GPIOA, 3, 3, TIMER2_CH4_CCR, TIMER2, 4, AFIO_EXTI_PA}, - /* D1/PA2 */ - {GPIOA, 2, 2, TIMER2_CH3_CCR, TIMER2, 3, AFIO_EXTI_PA}, - /* D2/PA0 */ - {GPIOA, 0, 0, TIMER2_CH1_CCR, TIMER2, 1, AFIO_EXTI_PA}, - /* D3/PA1 */ - {GPIOA, 1, 1, TIMER2_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA}, - /* D4/PB5 */ - {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D5/PB6 */ - {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB}, - /* D6/PA8 */ - {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA}, - /* D7/PA9 */ - {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER1, 2, AFIO_EXTI_PA}, - /* D8/PA10 */ - {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA}, - /* D9/PB7 */ - {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB}, - /* D10/PA4 */ - {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D11/PA7 */ - {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA}, - /* D12/PA6 */ - {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA}, - /* D13/PA5 */ - {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D14/PB8 */ - {GPIOB, 8, ADCx, TIMER4_CH3_CCR, TIMER4, 3, AFIO_EXTI_PB}, + {GPIOA, 3, 3, TIMER2, 4, AFIO_EXTI_PA}, /* D0/PA3 */ + {GPIOA, 2, 2, TIMER2, 3, AFIO_EXTI_PA}, /* D1/PA2 */ + {GPIOA, 0, 0, TIMER2, 1, AFIO_EXTI_PA}, /* D2/PA0 */ + {GPIOA, 1, 1, TIMER2, 2, AFIO_EXTI_PA}, /* D3/PA1 */ + {GPIOB, 5, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D4/PB5 */ + {GPIOB, 6, ADCx, TIMER4, 1, AFIO_EXTI_PB}, /* D5/PB6 */ + {GPIOA, 8, ADCx, TIMER1, 1, AFIO_EXTI_PA}, /* D6/PA8 */ + {GPIOA, 9, ADCx, TIMER1, 2, AFIO_EXTI_PA}, /* D7/PA9 */ + {GPIOA, 10, ADCx, TIMER1, 3, AFIO_EXTI_PA}, /* D8/PA10 */ + {GPIOB, 7, ADCx, TIMER4, 2, AFIO_EXTI_PB}, /* D9/PB7 */ + {GPIOA, 4, 4, NULL, 0, AFIO_EXTI_PA}, /* D10/PA4 */ + {GPIOA, 7, 7, TIMER3, 2, AFIO_EXTI_PA}, /* D11/PA7 */ + {GPIOA, 6, 6, TIMER3, 1, AFIO_EXTI_PA}, /* D12/PA6 */ + {GPIOA, 5, 5, NULL, 0, AFIO_EXTI_PA}, /* D13/PA5 (LED) */ + {GPIOB, 8, ADCx, TIMER4, 3, AFIO_EXTI_PB}, /* D14/PB8 */ /* Little header */ - /* D15/PC0 */ - {GPIOC, 0, 10, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D16/PC1 */ - {GPIOC, 1, 11, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D17/PC2 */ - {GPIOC, 2, 12, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D18/PC3 */ - {GPIOC, 3, 13, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D19/PC4 */ - {GPIOC, 4, 14, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D20/PC5 */ - {GPIOC, 5, 15, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, + {GPIOC, 0, 10, NULL, 0, AFIO_EXTI_PC}, /* D15/PC0 */ + {GPIOC, 1, 11, NULL, 0, AFIO_EXTI_PC}, /* D16/PC1 */ + {GPIOC, 2, 12, NULL, 0, AFIO_EXTI_PC}, /* D17/PC2 */ + {GPIOC, 3, 13, NULL, 0, AFIO_EXTI_PC}, /* D18/PC3 */ + {GPIOC, 4, 14, NULL, 0, AFIO_EXTI_PC}, /* D19/PC4 */ + {GPIOC, 5, 15, NULL, 0, AFIO_EXTI_PC}, /* D20/PC5 */ /* External header */ - /* D21/PC13 */ - {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D22/PC14 */ - {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D23/PC15 */ - {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D24/PB9 */ - {GPIOB, 9, ADCx, TIMER4_CH4_CCR, TIMER4, 4, AFIO_EXTI_PB}, - /* D25/PD2 */ - {GPIOD, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D26/PC10 */ - {GPIOC, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D27/PB0 */ - {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB}, - /* D28/PB1 */ - {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB}, - /* D29/PB10 */ - {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D30/PB11 */ - {GPIOB, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D31/PB12 */ - {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D32/PB13 */ - {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D33/PB14 */ - {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D34/PB15 */ - {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D35/PC6 */ - {GPIOC, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D36/PC7 */ - {GPIOC, 7, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D37/PC8 */ - {GPIOC, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D38/PC9 (BUT) */ - {GPIOC, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC} + {GPIOC, 13, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D21/PC13 */ + {GPIOC, 14, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D22/PC14 */ + {GPIOC, 15, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D23/PC15 */ + {GPIOB, 9, ADCx, TIMER4, 4, AFIO_EXTI_PB}, /* D24/PB9 */ + {GPIOD, 2, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D25/PD2 */ + {GPIOC, 10, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D26/PC10 */ + {GPIOB, 0, 8, TIMER3, 3, AFIO_EXTI_PB}, /* D27/PB0 */ + {GPIOB, 1, 9, TIMER3, 4, AFIO_EXTI_PB}, /* D28/PB1 */ + {GPIOB, 10, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D29/PB10 */ + {GPIOB, 11, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D30/PB11 */ + {GPIOB, 12, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D31/PB12 */ + {GPIOB, 13, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D32/PB13 */ + {GPIOB, 14, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D33/PB14 */ + {GPIOB, 15, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D34/PB15 */ + {GPIOC, 6, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D35/PC6 */ + {GPIOC, 7, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D36/PC7 */ + {GPIOC, 8, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D37/PC8 */ + {GPIOC, 9, ADCx, NULL, 0, AFIO_EXTI_PC} /* D38/PC9 (BUT) */ }; #elif defined(BOARD_maple_native) @@ -98,375 +58,207 @@ PinMapping PIN_MAP[NR_GPIO_PINS] = { PinMapping PIN_MAP[NR_GPIO_PINS] = { /* Top header */ - /* D0/PB10 */ - {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D1/PB2 */ - {GPIOB, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D2/PB12 */ - {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D3/PB13 */ - {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D4/PB14 */ - {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D5/PB15 */ - {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D6/PC0 */ - {GPIOC, 0, 10, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D7/PC1 */ - {GPIOC, 1, 11, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D8/PC2 */ - {GPIOC, 2, 12, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D9/PC3 */ - {GPIOC, 3, 13, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D10/PC4 */ - {GPIOC, 4, 14, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D11/PC5 */ - {GPIOC, 5, 15, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D12/PC6 */ - {GPIOC, 6, ADCx, TIMER8_CH1_CCR, TIMER8, 1, AFIO_EXTI_PC}, - /* D13/PC7 */ - {GPIOC, 7, ADCx, TIMER8_CH2_CCR, TIMER8, 2, AFIO_EXTI_PC}, - /* D14/PC8 */ - {GPIOC, 8, ADCx, TIMER8_CH3_CCR, TIMER8, 3, AFIO_EXTI_PC}, - /* D15/PC9 */ - {GPIOC, 9, ADCx, TIMER8_CH4_CCR, TIMER8, 4, AFIO_EXTI_PC}, - /* D16/PC10 */ - {GPIOC, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D17/PC11 */ - {GPIOC, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D18/PC12 */ - {GPIOC, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D19/PC13 */ - {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D20/PC14 */ - {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D21/PC15 */ - {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D22/PA8 */ - {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA}, - /* D23/PA9 */ - {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER1, 2, AFIO_EXTI_PA}, - /* D24/PA10 */ - {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA}, - /* D25/PB9 */ - {GPIOB, 9, ADCx, TIMER4_CH4_CCR, TIMER4, 4, AFIO_EXTI_PB}, + {GPIOB, 10, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D0/PB10 */ + {GPIOB, 2, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D1/PB2 */ + {GPIOB, 12, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D2/PB12 */ + {GPIOB, 13, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D3/PB13 */ + {GPIOB, 14, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D4/PB14 */ + {GPIOB, 15, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D5/PB15 */ + {GPIOC, 0, 10, NULL, 0, AFIO_EXTI_PC}, /* D6/PC0 */ + {GPIOC, 1, 11, NULL, 0, AFIO_EXTI_PC}, /* D7/PC1 */ + {GPIOC, 2, 12, NULL, 0, AFIO_EXTI_PC}, /* D8/PC2 */ + {GPIOC, 3, 13, NULL, 0, AFIO_EXTI_PC}, /* D9/PC3 */ + {GPIOC, 4, 14, NULL, 0, AFIO_EXTI_PC}, /* D10/PC4 */ + {GPIOC, 5, 15, NULL, 0, AFIO_EXTI_PC}, /* D11/PC5 */ + {GPIOC, 6, ADCx, TIMER8, 1, AFIO_EXTI_PC}, /* D12/PC6 */ + {GPIOC, 7, ADCx, TIMER8, 2, AFIO_EXTI_PC}, /* D13/PC7 */ + {GPIOC, 8, ADCx, TIMER8, 3, AFIO_EXTI_PC}, /* D14/PC8 */ + {GPIOC, 9, ADCx, TIMER8, 4, AFIO_EXTI_PC}, /* D15/PC9 */ + {GPIOC, 10, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D16/PC10 */ + {GPIOC, 11, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D17/PC11 */ + {GPIOC, 12, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D18/PC12 */ + {GPIOC, 13, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D19/PC13 */ + {GPIOC, 14, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D20/PC14 */ + {GPIOC, 15, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D21/PC15 */ + {GPIOA, 8, ADCx, TIMER1, 1, AFIO_EXTI_PA}, /* D22/PA8 */ + {GPIOA, 9, ADCx, TIMER1, 2, AFIO_EXTI_PA}, /* D23/PA9 */ + {GPIOA, 10, ADCx, TIMER1, 3, AFIO_EXTI_PA}, /* D24/PA10 */ + {GPIOB, 9, ADCx, TIMER4, 4, AFIO_EXTI_PB}, /* D25/PB9 */ /* Bottom header */ + /* FIXME (?) What about D48--D50 also being TIMER2_CH[234]? */ - /* D26/PD2 */ - {GPIOD, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D27/PD3 */ - {GPIOD, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D28/PD6 */ - {GPIOD, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D29/PG11 */ - {GPIOG, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D30/PG12 */ - {GPIOG, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D31/PG13 */ - {GPIOG, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D32/PG14 */ - {GPIOG, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D33/PG8 */ - {GPIOG, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D34/PG7 */ - {GPIOG, 7, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D35/PG6 */ - {GPIOG, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D36/PB5 */ - {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D37/PB6 */ - {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB}, - /* D38/PB7 */ - {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB}, - /* D39/PF6 */ - {GPIOF, 6, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D40/PF7 */ - {GPIOF, 7, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D41/PF8 */ - {GPIOF, 8, 6, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D42/PF9 */ - {GPIOF, 9, 7, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D43/PF10 */ - {GPIOF, 10, 8, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D44/PF11 */ - {GPIOF, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D45/PB1 */ - {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB}, - /* D46/PB0 */ - {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB}, - /* D47/PA0 */ - {GPIOA, 0, 0, TIMER5_CH1_CCR, TIMER5, 1, AFIO_EXTI_PA}, - /* D48/PA1 */ /* FIXME (?) - What about D48--D50 also being TIMER2_CH[234]? */ - {GPIOA, 1, 1, TIMER5_CH2_CCR, TIMER5, 2, AFIO_EXTI_PA}, - /* D49/PA2 */ - {GPIOA, 2, 2, TIMER5_CH3_CCR, TIMER5, 3, AFIO_EXTI_PA}, - /* D50/PA3 */ - {GPIOA, 3, 3, TIMER5_CH4_CCR, TIMER5, 4, AFIO_EXTI_PA}, - /* D51/PA4 */ - {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D52/PA5 */ - {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D53/PA6 */ - {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA}, - /* D54/PA7 */ - {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA}, + {GPIOD, 2, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D26/PD2 */ + {GPIOD, 3, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D27/PD3 */ + {GPIOD, 6, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D28/PD6 */ + {GPIOG, 11, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D29/PG11 */ + {GPIOG, 12, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D30/PG12 */ + {GPIOG, 13, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D31/PG13 */ + {GPIOG, 14, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D32/PG14 */ + {GPIOG, 8, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D33/PG8 */ + {GPIOG, 7, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D34/PG7 */ + {GPIOG, 6, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D35/PG6 */ + {GPIOB, 5, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D36/PB5 */ + {GPIOB, 6, ADCx, TIMER4, 1, AFIO_EXTI_PB}, /* D37/PB6 */ + {GPIOB, 7, ADCx, TIMER4, 2, AFIO_EXTI_PB}, /* D38/PB7 */ + {GPIOF, 6, 4, NULL, 0, AFIO_EXTI_PF}, /* D39/PF6 */ + {GPIOF, 7, 5, NULL, 0, AFIO_EXTI_PF}, /* D40/PF7 */ + {GPIOF, 8, 6, NULL, 0, AFIO_EXTI_PF}, /* D41/PF8 */ + {GPIOF, 9, 7, NULL, 0, AFIO_EXTI_PF}, /* D42/PF9 */ + {GPIOF, 10, 8, NULL, 0, AFIO_EXTI_PF}, /* D43/PF10 */ + {GPIOF, 11, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D44/PF11 */ + {GPIOB, 1, 9, TIMER3, 4, AFIO_EXTI_PB}, /* D45/PB1 */ + {GPIOB, 0, 8, TIMER3, 3, AFIO_EXTI_PB}, /* D46/PB0 */ + {GPIOA, 0, 0, TIMER5, 1, AFIO_EXTI_PA}, /* D47/PA0 */ + {GPIOA, 1, 1, TIMER5, 2, AFIO_EXTI_PA}, /* D48/PA1 */ + {GPIOA, 2, 2, TIMER5, 3, AFIO_EXTI_PA}, /* D49/PA2 */ + {GPIOA, 3, 3, TIMER5, 4, AFIO_EXTI_PA}, /* D50/PA3 */ + {GPIOA, 4, 4, NULL, 0, AFIO_EXTI_PA}, /* D51/PA4 */ + {GPIOA, 5, 5, NULL, 0, AFIO_EXTI_PA}, /* D52/PA5 */ + {GPIOA, 6, 6, TIMER3, 1, AFIO_EXTI_PA}, /* D53/PA6 */ + {GPIOA, 7, 7, TIMER3, 2, AFIO_EXTI_PA}, /* D54/PA7 */ /* Right (triple) header */ - /* D55/PF0 */ - {GPIOF, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D56/PD11 */ - {GPIOD, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D57/PD14 */ - {GPIOD, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D58/PF1 */ - {GPIOF, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D59/PD12 */ - {GPIOD, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D60/PD15 */ - {GPIOD, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D61/PF2 */ - {GPIOF, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D62/PD13 */ - {GPIOD, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D63/PD0 */ - {GPIOD, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D64/PF3 */ - {GPIOF, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D65/PE3 */ - {GPIOE, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D66/PD1 */ - {GPIOD, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D67/PF4 */ - {GPIOF, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D68/PE4 */ - {GPIOE, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D69/PE7 */ - {GPIOE, 7, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D70/PF5 */ - {GPIOF, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D71/PE5 */ - {GPIOE, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D72/PE8 */ - {GPIOE, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D73/PF12 */ - {GPIOF, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D74/PE6 */ - {GPIOE, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D75/PE9 */ - {GPIOE, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D76/PF13 */ - {GPIOF, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D77/PE10 */ - {GPIOE, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D78/PF14 */ - {GPIOF, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D79/PG9 */ - {GPIOG, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D80/PE11 */ - {GPIOE, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D81/PF15 */ - {GPIOF, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF}, - /* D82/PG10 */ - {GPIOG, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D83/PE12 */ - {GPIOE, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D84/PG0 */ - {GPIOG, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D85/PD5 */ - {GPIOD, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D86/PE13 */ - {GPIOE, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D87/PG1 */ - {GPIOG, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D88/PD4 */ - {GPIOD, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D89/PE14 */ - {GPIOE, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D90/PG2 */ - {GPIOG, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D91/PE1 */ - {GPIOE, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D92/PE15 */ - {GPIOE, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D93/PG3 */ - {GPIOG, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D94/PE0 */ - {GPIOE, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE}, - /* D95/PD8 */ - {GPIOD, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D96/PG4 */ - {GPIOG, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D97/PD9 */ - {GPIOD, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D98/PG5 */ - {GPIOG, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG}, - /* D99/PD10 */ - {GPIOD, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD} + {GPIOF, 0, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D55/PF0 */ + {GPIOD, 11, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D56/PD11 */ + {GPIOD, 14, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D57/PD14 */ + {GPIOF, 1, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D58/PF1 */ + {GPIOD, 12, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D59/PD12 */ + {GPIOD, 15, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D60/PD15 */ + {GPIOF, 2, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D61/PF2 */ + {GPIOD, 13, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D62/PD13 */ + {GPIOD, 0, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D63/PD0 */ + {GPIOF, 3, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D64/PF3 */ + {GPIOE, 3, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D65/PE3 */ + {GPIOD, 1, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D66/PD1 */ + {GPIOF, 4, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D67/PF4 */ + {GPIOE, 4, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D68/PE4 */ + {GPIOE, 7, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D69/PE7 */ + {GPIOF, 5, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D70/PF5 */ + {GPIOE, 5, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D71/PE5 */ + {GPIOE, 8, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D72/PE8 */ + {GPIOF, 12, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D73/PF12 */ + {GPIOE, 6, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D74/PE6 */ + {GPIOE, 9, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D75/PE9 */ + {GPIOF, 13, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D76/PF13 */ + {GPIOE, 10, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D77/PE10 */ + {GPIOF, 14, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D78/PF14 */ + {GPIOG, 9, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D79/PG9 */ + {GPIOE, 11, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D80/PE11 */ + {GPIOF, 15, ADCx, NULL, 0, AFIO_EXTI_PF}, /* D81/PF15 */ + {GPIOG, 10, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D82/PG10 */ + {GPIOE, 12, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D83/PE12 */ + {GPIOG, 0, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D84/PG0 */ + {GPIOD, 5, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D85/PD5 */ + {GPIOE, 13, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D86/PE13 */ + {GPIOG, 1, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D87/PG1 */ + {GPIOD, 4, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D88/PD4 */ + {GPIOE, 14, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D89/PE14 */ + {GPIOG, 2, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D90/PG2 */ + {GPIOE, 1, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D91/PE1 */ + {GPIOE, 15, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D92/PE15 */ + {GPIOG, 3, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D93/PG3 */ + {GPIOE, 0, ADCx, NULL, 0, AFIO_EXTI_PE}, /* D94/PE0 */ + {GPIOD, 8, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D95/PD8 */ + {GPIOG, 4, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D96/PG4 */ + {GPIOD, 9, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D97/PD9 */ + {GPIOG, 5, ADCx, NULL, 0, AFIO_EXTI_PG}, /* D98/PG5 */ + {GPIOD, 10, ADCx, NULL, 0, AFIO_EXTI_PD} /* D99/PD10 */ }; #elif defined(BOARD_maple_mini) PinMapping PIN_MAP[NR_GPIO_PINS] = { - /* D0/PB11 */ - {GPIOB, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D1/PB10 */ - {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D2/PB2 */ - {GPIOB, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D3/PB0 */ - {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB}, - /* D4/PA7 */ - {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA}, - /* D5/PA6 */ - {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA}, - /* D6/PA5 */ - {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D7/PA4 */ - {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D8/PA3 */ - {GPIOA, 3, 3, TIMER2_CH4_CCR, TIMER2, 4, AFIO_EXTI_PA}, - /* D9/PA2 */ - {GPIOA, 2, 2, TIMER2_CH3_CCR, TIMER2, 3, AFIO_EXTI_PA}, - /* D10/PA1 */ - {GPIOA, 1, 1, TIMER2_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA}, - /* D11/PA0 */ - {GPIOA, 0, 0, TIMER2_CH1_CCR, TIMER2, 1, AFIO_EXTI_PA}, - /* D12/PC15 */ - {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D13/PC14 */ - {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D14/PC13 */ - {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D15/PB7 */ - {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB}, - /* D16/PB6 */ - {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB}, - /* D17/PB5 */ - {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D18/PB4 */ - {GPIOB, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D19/PB3 */ - {GPIOB, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D20/PA15 */ - {GPIOA, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D21/PA14 */ - {GPIOA, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D22/PA13 */ - {GPIOA, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D23/PA12 */ - {GPIOA, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D24/PA11 */ - {GPIOA, 11, ADCx, TIMER1_CH4_CCR, TIMER1, 4, AFIO_EXTI_PA}, - /* D25/PA10 */ - {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA}, - /* D26/PA9 */ - {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA}, - /* D27/PA8 */ - {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA}, - /* D28/PB15 */ - {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D29/PB14 */ - {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D30/PB13 */ - {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D31/PB12 */ - {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D32/PB8 */ - {GPIOB, 8, ADCx, TIMER4_CH3_CCR, TIMER4, 3, AFIO_EXTI_PB}, - /* D33/PB1 */ - {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB}, + /* Top header */ + + {GPIOB, 11, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D0/PB11 */ + {GPIOB, 10, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D1/PB10 */ + {GPIOB, 2, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D2/PB2 */ + {GPIOB, 0, 8, TIMER3, 3, AFIO_EXTI_PB}, /* D3/PB0 */ + {GPIOA, 7, 7, TIMER3, 2, AFIO_EXTI_PA}, /* D4/PA7 */ + {GPIOA, 6, 6, TIMER3, 1, AFIO_EXTI_PA}, /* D5/PA6 */ + {GPIOA, 5, 5, NULL, 0, AFIO_EXTI_PA}, /* D6/PA5 */ + {GPIOA, 4, 4, NULL, 0, AFIO_EXTI_PA}, /* D7/PA4 */ + {GPIOA, 3, 3, TIMER2, 4, AFIO_EXTI_PA}, /* D8/PA3 */ + {GPIOA, 2, 2, TIMER2, 3, AFIO_EXTI_PA}, /* D9/PA2 */ + {GPIOA, 1, 1, TIMER2, 2, AFIO_EXTI_PA}, /* D10/PA1 */ + {GPIOA, 0, 0, TIMER2, 1, AFIO_EXTI_PA}, /* D11/PA0 */ + {GPIOC, 15, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D12/PC15 */ + {GPIOC, 14, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D13/PC14 */ + {GPIOC, 13, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D14/PC13 */ + + /* Bottom header */ + + {GPIOB, 7, ADCx, TIMER4, 2, AFIO_EXTI_PB}, /* D15/PB7 */ + {GPIOB, 6, ADCx, TIMER4, 1, AFIO_EXTI_PB}, /* D16/PB6 */ + {GPIOB, 5, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D17/PB5 */ + {GPIOB, 4, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D18/PB4 */ + {GPIOB, 3, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D19/PB3 */ + {GPIOA, 15, ADCx, NULL, 0, AFIO_EXTI_PA}, /* D20/PA15 */ + {GPIOA, 14, ADCx, NULL, 0, AFIO_EXTI_PA}, /* D21/PA14 */ + {GPIOA, 13, ADCx, NULL, 0, AFIO_EXTI_PA}, /* D22/PA13 */ + {GPIOA, 12, ADCx, NULL, 0, AFIO_EXTI_PA}, /* D23/PA12 */ + {GPIOA, 11, ADCx, TIMER1, 4, AFIO_EXTI_PA}, /* D24/PA11 */ + {GPIOA, 10, ADCx, TIMER1, 3, AFIO_EXTI_PA}, /* D25/PA10 */ + {GPIOA, 9, ADCx, TIMER2, 2, AFIO_EXTI_PA}, /* D26/PA9 */ + {GPIOA, 8, ADCx, TIMER1, 1, AFIO_EXTI_PA}, /* D27/PA8 */ + {GPIOB, 15, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D28/PB15 */ + {GPIOB, 14, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D29/PB14 */ + {GPIOB, 13, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D30/PB13 */ + {GPIOB, 12, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D31/PB12 */ + {GPIOB, 8, ADCx, TIMER4, 3, AFIO_EXTI_PB}, /* D32/PB8 */ + {GPIOB, 1, 9, TIMER3, 4, AFIO_EXTI_PB}, /* D33/PB1 */ }; #elif defined(BOARD_maple_RET6) PinMapping PIN_MAP[NR_GPIO_PINS] = { - /* D0/PA3 */ - {GPIOA, 3, 3, TIMER2_CH4_CCR, TIMER2, 4, AFIO_EXTI_PA}, - /* D1/PA2 */ - {GPIOA, 2, 2, TIMER2_CH3_CCR, TIMER2, 3, AFIO_EXTI_PA}, - /* D2/PA0 */ - {GPIOA, 0, 0, TIMER2_CH1_CCR, TIMER2, 1, AFIO_EXTI_PA}, - /* D3/PA1 */ - {GPIOA, 1, 1, TIMER2_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA}, - /* D4/PB5 */ - {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D5/PB6 */ - {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB}, - /* D6/PA8 */ - {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA}, - /* D7/PA9 */ - {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER1, 2, AFIO_EXTI_PA}, - /* D8/PA10 */ - {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA}, - /* D9/PB7 */ - {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB}, - /* D10/PA4 */ - {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D11/PA7 */ - {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA}, - /* D12/PA6 */ - {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA}, - /* D13/PA5 */ - {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA}, - /* D14/PB8 */ - {GPIOB, 8, ADCx, TIMER4_CH3_CCR, TIMER4, 3, AFIO_EXTI_PB}, + {GPIOA, 3, 3, TIMER2, 4, AFIO_EXTI_PA}, /* D0/PA3 */ + {GPIOA, 2, 2, TIMER2, 3, AFIO_EXTI_PA}, /* D1/PA2 */ + {GPIOA, 0, 0, TIMER2, 1, AFIO_EXTI_PA}, /* D2/PA0 */ + {GPIOA, 1, 1, TIMER2, 2, AFIO_EXTI_PA}, /* D3/PA1 */ + {GPIOB, 5, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D4/PB5 */ + {GPIOB, 6, ADCx, TIMER4, 1, AFIO_EXTI_PB}, /* D5/PB6 */ + {GPIOA, 8, ADCx, TIMER1, 1, AFIO_EXTI_PA}, /* D6/PA8 */ + {GPIOA, 9, ADCx, TIMER1, 2, AFIO_EXTI_PA}, /* D7/PA9 */ + {GPIOA, 10, ADCx, TIMER1, 3, AFIO_EXTI_PA}, /* D8/PA10 */ + {GPIOB, 7, ADCx, TIMER4, 2, AFIO_EXTI_PB}, /* D9/PB7 */ + {GPIOA, 4, 4, NULL, 0, AFIO_EXTI_PA}, /* D10/PA4 */ + {GPIOA, 7, 7, TIMER3, 2, AFIO_EXTI_PA}, /* D11/PA7 */ + {GPIOA, 6, 6, TIMER3, 1, AFIO_EXTI_PA}, /* D12/PA6 */ + {GPIOA, 5, 5, NULL, 0, AFIO_EXTI_PA}, /* D13/PA5 (LED) */ + {GPIOB, 8, ADCx, TIMER4, 3, AFIO_EXTI_PB}, /* D14/PB8 */ /* Little header */ - /* D15/PC0 */ - {GPIOC, 0, 10, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D16/PC1 */ - {GPIOC, 1, 11, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D17/PC2 */ - {GPIOC, 2, 12, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D18/PC3 */ - {GPIOC, 3, 13, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D19/PC4 */ - {GPIOC, 4, 14, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D20/PC5 */ - {GPIOC, 5, 15, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, + {GPIOC, 0, 10, NULL, 0, AFIO_EXTI_PC}, /* D15/PC0 */ + {GPIOC, 1, 11, NULL, 0, AFIO_EXTI_PC}, /* D16/PC1 */ + {GPIOC, 2, 12, NULL, 0, AFIO_EXTI_PC}, /* D17/PC2 */ + {GPIOC, 3, 13, NULL, 0, AFIO_EXTI_PC}, /* D18/PC3 */ + {GPIOC, 4, 14, NULL, 0, AFIO_EXTI_PC}, /* D19/PC4 */ + {GPIOC, 5, 15, NULL, 0, AFIO_EXTI_PC}, /* D20/PC5 */ /* External header */ - /* D21/PC13 */ - {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D22/PC14 */ - {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D23/PC15 */ - {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D24/PB9 */ - {GPIOB, 9, ADCx, TIMER4_CH4_CCR, TIMER4, 4, AFIO_EXTI_PB}, - /* D25/PD2 */ - {GPIOD, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD}, - /* D26/PC10 */ - {GPIOC, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}, - /* D27/PB0 */ - {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB}, - /* D28/PB1 */ - {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB}, - /* D29/PB10 */ - {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D30/PB11 */ - {GPIOB, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D31/PB12 */ - {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D32/PB13 */ - {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D33/PB14 */ - {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D34/PB15 */ - {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB}, - /* D35/PC6 */ - {GPIOC, 6, ADCx, TIMER8_CH1_CCR, TIMER8, 1, AFIO_EXTI_PC}, - /* D36/PC7 */ - {GPIOC, 7, ADCx, TIMER8_CH1_CCR, TIMER8, 2, AFIO_EXTI_PC}, - /* D37/PC8 */ - {GPIOC, 8, ADCx, TIMER8_CH1_CCR, TIMER8, 3, AFIO_EXTI_PC}, - /* D38/PC9 (BUT) */ - {GPIOC, 9, ADCx, TIMER8_CH1_CCR, TIMER8, 4, AFIO_EXTI_PC} + {GPIOC, 13, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D21/PC13 */ + {GPIOC, 14, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D22/PC14 */ + {GPIOC, 15, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D23/PC15 */ + {GPIOB, 9, ADCx, TIMER4, 4, AFIO_EXTI_PB}, /* D24/PB9 */ + {GPIOD, 2, ADCx, NULL, 0, AFIO_EXTI_PD}, /* D25/PD2 */ + {GPIOC, 10, ADCx, NULL, 0, AFIO_EXTI_PC}, /* D26/PC10 */ + {GPIOB, 0, 8, TIMER3, 3, AFIO_EXTI_PB}, /* D27/PB0 */ + {GPIOB, 1, 9, TIMER3, 4, AFIO_EXTI_PB}, /* D28/PB1 */ + {GPIOB, 10, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D29/PB10 */ + {GPIOB, 11, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D30/PB11 */ + {GPIOB, 12, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D31/PB12 */ + {GPIOB, 13, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D32/PB13 */ + {GPIOB, 14, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D33/PB14 */ + {GPIOB, 15, ADCx, NULL, 0, AFIO_EXTI_PB}, /* D34/PB15 */ + {GPIOC, 6, ADCx, TIMER8, 1, AFIO_EXTI_PC}, /* D35/PC6 */ + {GPIOC, 7, ADCx, TIMER8, 2, AFIO_EXTI_PC}, /* D36/PC7 */ + {GPIOC, 8, ADCx, TIMER8, 3, AFIO_EXTI_PC}, /* D37/PC8 */ + {GPIOC, 9, ADCx, TIMER8, 4, AFIO_EXTI_PC} /* D38/PC9 (BUT) */ }; #else diff --git a/wirish/boards.h b/wirish/boards.h index 94566fa..d186dc4 100644 --- a/wirish/boards.h +++ b/wirish/boards.h @@ -33,7 +33,8 @@ #include "libmaple.h" #include "gpio.h" -#include "timers.h" +#include "timer.h" +#include "native_sram.h" /* Set of all possible pin names; not all boards have all these (note that we use the Dx convention since all of the Maple's pins are @@ -56,9 +57,8 @@ typedef struct PinMapping { gpio_dev *gpio_device; uint32 pin; uint32 adc_channel; - TimerCCR timer_ccr; - timer_dev_num timer_num; - uint32 timer_chan; + timer_dev* timer_device; + uint8 timer_chan; afio_exti_port ext_port; } PinMapping; @@ -94,6 +94,7 @@ extern PinMapping PIN_MAP[]; #define NR_GPIO_PINS 100 #define BOARD_INIT do { \ + initNativeSRAM(); } while(0) #elif defined(BOARD_maple_mini) diff --git a/wirish/comm/HardwareSPI.cpp b/wirish/comm/HardwareSPI.cpp index 20090f5..aea7734 100644 --- a/wirish/comm/HardwareSPI.cpp +++ b/wirish/comm/HardwareSPI.cpp @@ -47,8 +47,10 @@ * TODO: Do the complementary PWM outputs mess up SPI2? * */ -#include "wirish.h" #include "spi.h" +#include "timer.h" + +#include "wirish.h" #include "HardwareSPI.h" static const uint32 prescaleFactors[MAX_SPI_FREQS] = { diff --git a/wirish/comm/HardwareSerial.cpp b/wirish/comm/HardwareSerial.cpp index 08252d8..97a5ec3 100644 --- a/wirish/comm/HardwareSerial.cpp +++ b/wirish/comm/HardwareSerial.cpp @@ -31,12 +31,10 @@ #include "wirish.h" #include "HardwareSerial.h" #include "usart.h" -#include "gpio.h" -#include "timers.h" -HardwareSerial Serial1(USART1, 4500000UL, GPIOA, 9,10, TIMER1, 2); -HardwareSerial Serial2(USART2, 2250000UL, GPIOA, 2, 3, TIMER2, 3); -HardwareSerial Serial3(USART3, 2250000UL, GPIOB, 10,11, TIMER_INVALID, 0); +HardwareSerial Serial1(USART1, 4500000UL, GPIOA, 9, 10, TIMER1, 2); +HardwareSerial Serial2(USART2, 2250000UL, GPIOA, 2, 3, TIMER2, 3); +HardwareSerial Serial3(USART3, 2250000UL, GPIOB, 10, 11, NULL, 0); // TODO: High density device ports HardwareSerial::HardwareSerial(uint8 usart_num, @@ -44,15 +42,15 @@ HardwareSerial::HardwareSerial(uint8 usart_num, gpio_dev *gpio_device, uint8 tx_pin, uint8 rx_pin, - timer_dev_num timer_num, - uint8 compare_num) { + timer_dev *timer_device, + uint8 channel_num) { this->usart_num = usart_num; this->max_baud = max_baud; this->gpio_device = gpio_device; this->tx_pin = tx_pin; this->rx_pin = rx_pin; - this->timer_num = timer_num; - this->compare_num = compare_num; + this->timer_device = timer_device; + this->channel_num = channel_num; } uint8 HardwareSerial::read(void) { @@ -75,9 +73,9 @@ void HardwareSerial::begin(uint32 baud) { gpio_set_mode(gpio_device, tx_pin, GPIO_AF_OUTPUT_PP); gpio_set_mode(gpio_device, rx_pin, GPIO_INPUT_FLOATING); - if (timer_num != TIMER_INVALID) { + if (timer_device != NULL) { /* turn off any pwm if there's a conflict on this usart */ - timer_set_mode(timer_num, compare_num, TIMER_DISABLED); + timer_set_mode(timer_device, channel_num, TIMER_DISABLED); } usart_init(usart_num, baud); diff --git a/wirish/comm/HardwareSerial.h b/wirish/comm/HardwareSerial.h index ef19a56..7852d51 100644 --- a/wirish/comm/HardwareSerial.h +++ b/wirish/comm/HardwareSerial.h @@ -31,7 +31,9 @@ #ifndef _HARDWARESERIAL_H_ #define _HARDWARESERIAL_H_ -#include "timers.h" +#include "libmaple_types.h" +#include "gpio.h" +#include "timer.h" #include "Print.h" @@ -49,16 +51,16 @@ class HardwareSerial : public Print { gpio_dev *gpio_device; uint8 tx_pin; uint8 rx_pin; - timer_dev_num timer_num; - uint8 compare_num; + timer_dev *timer_device; + uint8 channel_num; public: HardwareSerial(uint8 usart_num, uint32 max_baud, gpio_dev *gpio_device, uint8 tx_pin, uint8 rx_pin, - timer_dev_num timer_num, - uint8 compare_num); + timer_dev *timer_device, + uint8 channel_num); void begin(uint32 baud); void end(void); uint32 available(void); diff --git a/wirish/pwm.cpp b/wirish/pwm.cpp index 072e4cd..6b09cef 100644 --- a/wirish/pwm.cpp +++ b/wirish/pwm.cpp @@ -23,26 +23,20 @@ *****************************************************************************/ /** - * @brief Arduino-compatible PWM implementation. + * @brief Arduino-style PWM implementation. */ -#include "wirish.h" -#include "timers.h" -#include "io.h" +#include "libmaple_types.h" +#include "timer.h" + +#include "boards.h" #include "pwm.h" void pwmWrite(uint8 pin, uint16 duty_cycle) { - TimerCCR ccr; - - if (pin >= NR_GPIO_PINS) { - return; - } - - ccr = PIN_MAP[pin].timer_ccr; - - if (ccr == 0) { + timer_dev *dev = PIN_MAP[pin].timer_device; + if (pin >= NR_GPIO_PINS || dev == NULL || dev->type == TIMER_BASIC) { return; } - timer_pwm_write_ccr(ccr, duty_cycle); + timer_set_compare(dev, PIN_MAP[pin].timer_chan, duty_cycle); } diff --git a/wirish/rules.mk b/wirish/rules.mk index 3dd4b2d..d250cb9 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -18,7 +18,6 @@ cppSRCS_$(d) := wirish_math.cpp \ comm/HardwareSerial.cpp \ comm/HardwareSPI.cpp \ usb_serial.cpp \ - HardwareTimer.cpp \ cxxabi-compat.cpp \ wirish.cpp \ wirish_shift.cpp \ diff --git a/wirish/wirish.cpp b/wirish/wirish.cpp index 65d0262..6dcb1b5 100644 --- a/wirish/wirish.cpp +++ b/wirish/wirish.cpp @@ -23,61 +23,107 @@ *****************************************************************************/ /** - * @brief generic maple board bring up: + * @brief Generic Maple board initialization. * - * By default, we bring up all maple boards running on the stm32 to 72mhz, - * clocked off the PLL, driven by the 8MHz external crystal. - * - * AHB and APB2 are clocked at 72MHz - * APB1 is clocked at 36MHz + * By default, we bring up all Maple boards to 72MHz, clocked off the + * PLL, driven by the 8MHz external crystal. AHB and APB2 are clocked + * at 72MHz. APB1 is clocked at 36MHz. */ #include "wirish.h" + +#include "flash.h" +#include "rcc.h" +#include "nvic.h" #include "systick.h" #include "gpio.h" -#include "nvic.h" +#include "adc.h" +#include "timer.h" #include "usb.h" -#include "rcc.h" -#include "fsmc.h" -#include "dac.h" -#include "flash.h" -#include "native_sram.h" +static void setupFlash(void); +static void setupClocks(void); +static void setupADC(void); +static void setupTimers(void); + +/** + * Board-wide initialization function. Called before main(). + */ void init(void) { - /* make sure the flash is ready before spinning the high speed clock up */ + setupFlash(); + setupClocks(); + nvic_init(); + systick_init(SYSTICK_RELOAD_VAL); + gpio_init_all(); + afio_init(); + setupADC(); + setupTimers(); + setupUSB(); + + BOARD_INIT; +} + +static void setupFlash(void) { flash_enable_prefetch(); flash_set_latency(FLASH_WAIT_STATE_2); +} -#ifdef BOARD_maple_native - initNativeSRAM(); -#endif - - /* initialize clocks */ +/* + * Clock setup. Note that some of this only takes effect if we're + * running bare metal and the bootloader hasn't done it for us + * already. + * + * If you change this function, you MUST change the file-level Doxygen + * comment above. + */ +static void setupClocks() { rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); +} - nvic_init(); - systick_init(SYSTICK_RELOAD_VAL); - gpio_init_all(); - afio_init(); - - /* Initialize the ADC for slow conversions, to allow for high - impedance inputs. */ +/* TODO initialize more ADCs on high density boards. */ +static void setupADC() { adc_init(ADC1, 0); - adc_set_sample_rate(ADC1, ADC_SMPR_55_5); - - timer_init(TIMER1, 1); - timer_init(TIMER2, 1); - timer_init(TIMER3, 1); - timer_init(TIMER4, 1); -#ifdef STM32_HIGH_DENSITY - timer_init(TIMER5, 1); - timer_init(TIMER8, 1); -#endif - setupUSB(); + adc_set_sample_rate(ADC1, ADC_SMPR_55_5); // for high impedance inputs +} - /* include the board-specific init macro */ - BOARD_INIT; +static void timerDefaultConfig(timer_dev*); + +static void setupTimers() { + timer_foreach(timerDefaultConfig); +} + +static void timerDefaultConfig(timer_dev *dev) { + timer_adv_reg_map *regs = (dev->regs).adv; + const uint16 full_overflow = 0xFFFF; + const uint16 half_duty = 0x8FFF; + + timer_init(dev); + timer_pause(dev); + + regs->CR1 = TIMER_CR1_ARPE; + regs->PSC = 1; + regs->SR = 0; + regs->DIER = 0; + regs->EGR = TIMER_EGR_UG; + + switch (dev->type) { + case TIMER_ADVANCED: + regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; + // fall-through + case TIMER_GENERAL: + timer_set_reload(dev, full_overflow); + + for (int channel = 1; channel <= 4; channel++) { + timer_set_compare(dev, channel, half_duty); + timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); + } + // fall-through + case TIMER_BASIC: + break; + } + + timer_resume(dev); } diff --git a/wirish/wirish.h b/wirish/wirish.h index 447b2b6..319df97 100644 --- a/wirish/wirish.h +++ b/wirish/wirish.h @@ -32,7 +32,6 @@ #define _WIRISH_H_ #include "libmaple.h" -#include "timers.h" #include "boards.h" #include "io.h" @@ -44,7 +43,6 @@ #include "HardwareSPI.h" #include "HardwareSerial.h" #include "usb_serial.h" -#include "HardwareTimer.h" /* Arduino wiring macros and bit defines */ #define HIGH 0x1 @@ -69,7 +67,6 @@ typedef uint8 boolean; typedef uint8 byte; void init(void); -void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, byte val); #endif diff --git a/wirish/wirish_digital.cpp b/wirish/wirish_digital.cpp index 0c0bd85..4b68861 100644 --- a/wirish/wirish_digital.cpp +++ b/wirish/wirish_digital.cpp @@ -72,15 +72,15 @@ void pinMode(uint8 pin, WiringPinMode mode) { gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].pin, outputMode); - if (PIN_MAP[pin].timer_num != TIMER_INVALID) { + if (PIN_MAP[pin].timer_device != NULL) { /* enable/disable timer channels if we're switching into or out of pwm */ if (pwm) { - timer_set_mode(PIN_MAP[pin].timer_num, + timer_set_mode(PIN_MAP[pin].timer_device, PIN_MAP[pin].timer_chan, TIMER_PWM); } else { - timer_set_mode(PIN_MAP[pin].timer_num, + timer_set_mode(PIN_MAP[pin].timer_device, PIN_MAP[pin].timer_chan, TIMER_DISABLED); } -- cgit v1.2.3 From f8081eeb04c9cb511adaf58e201c7cfbe1ddfbd4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 25 Mar 2011 20:09:30 -0400 Subject: Final stm32_pin_info design candidate; ADC3 support on Native. Added an adc_dev to struct stm32_pin_info. This was necessary to add support for the channels on the Native which are only connected to ADC3, but it does add a bunch of NULLs to the PIN_MAPs. I don't think any other peripherals need representation on a per-pin basis. Each peripheral library will be responsible for keeping track of related GPIO ports and bits, and we can throw #defines in to boards/*.h for other things (e.g. BOARD_SPI1_MISO_PIN). Fleshed out the ADC refactor and brought it more in keeping with the new design as it evolves. A couple of other tweaks. Notably: waitForButtonPress() now takes a default argument meaning "wait forever". Removed Maple-specific documentation from core functions in io.h; this information will need to go into the individual board docs files. --- examples/test-session.cpp | 50 ++++--- libmaple/adc.c | 65 ++++++--- libmaple/adc.h | 294 +++++++++++++++++++++++++++++---------- libmaple/timer.c | 4 +- notes/coding_standard.txt | 44 ++++++ notes/native-pin-definitions.txt | 201 -------------------------- notes/pin-definitions.txt | 201 ++++++++++++++++++++++++++ wirish/boards.cpp | 145 +++++++++++++++++++ wirish/boards.h | 16 ++- wirish/boards/maple.cpp | 78 +++++------ wirish/boards/maple_RET6.cpp | 81 +++++------ wirish/boards/maple_mini.cpp | 68 ++++----- wirish/boards/maple_native.cpp | 202 +++++++++++++-------------- wirish/ext_interrupts.cpp | 4 +- wirish/io.h | 33 ++--- wirish/pwm.cpp | 2 +- wirish/rules.mk | 4 +- wirish/wirish.cpp | 128 ----------------- wirish/wirish.h | 2 - wirish/wirish_analog.cpp | 9 +- wirish/wirish_digital.cpp | 28 ++-- wirish/wirish_types.h | 26 ++-- 22 files changed, 967 insertions(+), 718 deletions(-) delete mode 100644 notes/native-pin-definitions.txt create mode 100644 notes/pin-definitions.txt create mode 100644 wirish/boards.cpp delete mode 100644 wirish/wirish.cpp (limited to 'notes') diff --git a/examples/test-session.cpp b/examples/test-session.cpp index 28c02f3..110b219 100644 --- a/examples/test-session.cpp +++ b/examples/test-session.cpp @@ -27,16 +27,13 @@ const uint8 adc_pins[] = #elif defined(BOARD_maple_mini) const uint8 pwm_pins[] = {3, 4, 5, 8, 9, 10, 11, 15, 16, 25, 26, 27}; -const uint8 adc_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 33}; // NB: 33 is LED +const uint8 adc_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 33}; #elif defined(BOARD_maple_native) const uint8 pwm_pins[] = {12, 13, 14, 15, 22, 23, 24, 25, 37, 38, 45, 46, 47, 48, 49, 50, 53, 54}; -const uint8 adc_pins[] = {6, 7, 8, 9, 10, 11, - /* the following are on ADC3, which lacks support: - 39, 40, 41, 42, 43, 45, */ +const uint8 adc_pins[] = {6, 7, 8, 9, 10, 11, 39, 40, 41, 42, 43, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54}; - #else #error "Board type has not been selected correctly" @@ -351,21 +348,34 @@ void cmd_everything(void) { // TODO void fast_gpio(int maple_pin) { gpio_dev *dev = PIN_MAP[maple_pin].gpio_device; - uint32 pin = PIN_MAP[maple_pin].gpio_pin; - - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); - gpio_write_bit(dev, pin, 1); gpio_write_bit(dev, pin, 0); + uint32 bit = PIN_MAP[maple_pin].gpio_bit; + + gpio_write_bit(dev, bit, 1); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); + gpio_toggle_bit(dev, bit); } void cmd_serial1_serial3(void) { diff --git a/libmaple/adc.c b/libmaple/adc.c index 3d38596..73dce0a 100644 --- a/libmaple/adc.c +++ b/libmaple/adc.c @@ -59,43 +59,44 @@ adc_dev adc3 = { const adc_dev *ADC3 = &adc3; #endif -static void adc_calibrate(const adc_dev *dev); - /** - * @brief Initialize an ADC peripheral. Only supports software triggered - * conversions. + * @brief Initialize an ADC peripheral. + * + * Initializes the RCC clock line for the given peripheral, using ADC + * prescaler RCC_ADCPRE_PCLK_DIV_6. Resets ADC device registers. + * * @param dev ADC peripheral to initialize - * @param flags unused */ -void adc_init(const adc_dev *dev, uint32 flags) { - /* Spin up the clocks */ +void adc_init(const adc_dev *dev) { rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); rcc_clk_enable(dev->clk_id); rcc_reset_dev(dev->clk_id); - - /* Software triggers conversions, conversion on external events */ - adc_set_extsel(dev, 7); - adc_set_exttrig(dev, 1); - - /* Enable the ADC */ - adc_enable(dev); - - /* Calibrate ADC */ - adc_calibrate(dev); } /** * @brief Set external event select for regular group - * @param dev adc device - * @param trigger event to select. See ADC_CR2 EXTSEL[2:0] bits. + * @param dev ADC device + * @param event Event used to trigger the start of conversion. + * @see adc_extsel_event */ -void adc_set_extsel(const adc_dev *dev, uint8 trigger) { +void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) { uint32 cr2 = dev->regs->CR2; cr2 &= ~ADC_CR2_EXTSEL; - cr2 |= (trigger & 0x7) << 17; + cr2 |= event; dev->regs->CR2 = cr2; } +/** + * @brief Call a function on all ADC devices. + * @param fn Function to call on each ADC device. + */ +void adc_foreach(void (*fn)(const adc_dev*)) { + fn(ADC1); + fn(ADC2); +#ifdef STM32_HIGH_DENSITY + fn(ADC3); +#endif +} /** * @brief Turn the given sample rate into values for ADC_SMPRx. Don't @@ -125,7 +126,7 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) { * @brief Calibrate an ADC peripheral * @param dev adc device */ -static void adc_calibrate(const adc_dev *dev) { +void adc_calibrate(const adc_dev *dev) { __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3); __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2); @@ -137,3 +138,23 @@ static void adc_calibrate(const adc_dev *dev) { while (*cal_bit) ; } + +/** + * @brief Perform a single synchronous software triggered conversion on a + * channel. + * @param dev ADC device to use for reading. + * @param channel channel to convert + * @return conversion result + */ +uint16 adc_read(const adc_dev *dev, uint8 channel) { + adc_reg_map *regs = dev->regs; + + adc_set_reg_seqlen(dev, 1); + + regs->SQR3 = channel; + regs->CR2 |= ADC_CR2_SWSTART; + while(!(regs->SR & ADC_SR_EOC)) + ; + + return (uint16)(regs->DR & ADC_DR_DATA); +} diff --git a/libmaple/adc.h b/libmaple/adc.h index 53ef032..520b982 100644 --- a/libmaple/adc.h +++ b/libmaple/adc.h @@ -79,103 +79,253 @@ extern const adc_dev *ADC3; #endif /* - * ADC peripheral base addresses + * Register map base pointers */ /** ADC1 register map base pointer. */ -#define ADC1_BASE ((adc_reg_map*)0x40012400) +#define ADC1_BASE ((adc_reg_map*)0x40012400) /** ADC2 register map base pointer. */ -#define ADC2_BASE ((adc_reg_map*)0x40012800) +#define ADC2_BASE ((adc_reg_map*)0x40012800) /** ADC3 register map base pointer. */ -#define ADC3_BASE ((adc_reg_map*)0x40013C00) +#define ADC3_BASE ((adc_reg_map*)0x40013C00) /* * Register bit definitions */ /* Status register */ -#define ADC_SR_AWD BIT(0) -#define ADC_SR_EOC BIT(1) -#define ADC_SR_JEOC BIT(2) -#define ADC_SR_JSTRT BIT(3) -#define ADC_SR_STRT BIT(4) + +#define ADC_SR_AWD_BIT 0 +#define ADC_SR_EOC_BIT 1 +#define ADC_SR_JEOC_BIT 2 +#define ADC_SR_JSTRT_BIT 3 +#define ADC_SR_STRT_BIT 4 + +#define ADC_SR_AWD BIT(ADC_SR_AWD_BIT) +#define ADC_SR_EOC BIT(ADC_SR_EOC_BIT) +#define ADC_SR_JEOC BIT(ADC_SR_JEOC_BIT) +#define ADC_SR_JSTRT BIT(ADC_SR_JSTRT_BIT) +#define ADC_SR_STRT BIT(ADC_SR_STRT_BIT) /* Control register 1 */ -#define ADC_CR1_AWDCH (0x1F) -#define ADC_CR1_EOCIE BIT(5) -#define ADC_CR1_AWDIE BIT(6) -#define ADC_CR1_JEOCIE BIT(7) -#define ADC_CR1_SCAN BIT(8) -#define ADC_CR1_AWDSGL BIT(9) -#define ADC_CR1_JAUTO BIT(10) -#define ADC_CR1_DISCEN BIT(11) -#define ADC_CR1_JDISCEN BIT(12) -#define ADC_CR1_DISCNUM (0xE000) -#define ADC_CR1_JAWDEN BIT(22) -#define ADC_CR1_AWDEN BIT(23) + +#define ADC_CR1_EOCIE_BIT 5 +#define ADC_CR1_AWDIE_BIT 6 +#define ADC_CR1_JEOCIE_BIT 7 +#define ADC_CR1_SCAN_BIT 8 +#define ADC_CR1_AWDSGL_BIT 9 +#define ADC_CR1_JAUTO_BIT 10 +#define ADC_CR1_DISCEN_BIT 11 +#define ADC_CR1_JDISCEN_BIT 12 +#define ADC_CR1_JAWDEN_BIT 22 +#define ADC_CR1_AWDEN_BIT 23 + +#define ADC_CR1_AWDCH (0x1F) +#define ADC_CR1_EOCIE BIT(ADC_CR1_EOCIE_BIT) +#define ADC_CR1_AWDIE BIT(ADC_CR1_AWDIE_BIT) +#define ADC_CR1_JEOCIE BIT(ADC_CR1_JEOCIE_BIT) +#define ADC_CR1_SCAN BIT(ADC_CR1_SCAN_BIT) +#define ADC_CR1_AWDSGL BIT(ADC_CR1_AWDSGL_BIT) +#define ADC_CR1_JAUTO BIT(ADC_CR1_JAUTO_BIT) +#define ADC_CR1_DISCEN BIT(ADC_CR1_DISCEN_BIT) +#define ADC_CR1_JDISCEN BIT(ADC_CR1_JDISCEN_BIT) +#define ADC_CR1_DISCNUM (0xE000) +#define ADC_CR1_JAWDEN BIT(ADC_CR1_JAWDEN_BIT) +#define ADC_CR1_AWDEN BIT(ADC_CR1_AWDEN_BIT) /* Control register 2 */ -#define ADC_CR2_ADON BIT(0) -#define ADC_CR2_CONT BIT(1) -#define ADC_CR2_CAL BIT(2) -#define ADC_CR2_RSTCAL BIT(3) -#define ADC_CR2_DMA BIT(8) -#define ADC_CR2_ALIGN BIT(11) -#define ADC_CR2_JEXTSEL (0x7000) -#define ADC_CR2_JEXTTRIG BIT(15) -#define ADC_CR2_EXTSEL (0xE0000) -#define ADC_CR2_EXTTRIG BIT(20) -#define ADC_CR2_JSWSTART BIT(21) -#define ADC_CR2_SWSTART BIT(22) -#define ADC_CR2_TSEREFE BIT(23) - -void adc_init(const adc_dev *dev, uint32 flags); -void adc_set_extsel(const adc_dev *dev, uint8 trigger); -/** ADC per-sample conversion times, in ADC clock cycles */ -typedef enum { - ADC_SMPR_1_5, ///< 1.5 ADC cycles - ADC_SMPR_7_5, ///< 7.5 ADC cycles - ADC_SMPR_13_5, ///< 13.5 ADC cycles - ADC_SMPR_28_5, ///< 28.5 ADC cycles - ADC_SMPR_41_5, ///< 41.5 ADC cycles - ADC_SMPR_55_5, ///< 55.5 ADC cycles - ADC_SMPR_71_5, ///< 71.5 ADC cycles - ADC_SMPR_239_5 ///< 239.5 ADC cycles -} adc_smp_rate; +#define ADC_CR2_ADON_BIT 0 +#define ADC_CR2_CONT_BIT 1 +#define ADC_CR2_CAL_BIT 2 +#define ADC_CR2_RSTCAL_BIT 3 +#define ADC_CR2_DMA_BIT 8 +#define ADC_CR2_ALIGN_BIT 11 +#define ADC_CR2_JEXTTRIG_BIT 15 +#define ADC_CR2_EXTTRIG_BIT 20 +#define ADC_CR2_JSWSTART_BIT 21 +#define ADC_CR2_SWSTART_BIT 22 +#define ADC_CR2_TSEREFE_BIT 23 -void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); +#define ADC_CR2_ADON BIT(ADC_CR2_ADON_BIT) +#define ADC_CR2_CONT BIT(ADC_CR2_CONT_BIT) +#define ADC_CR2_CAL BIT(ADC_CR2_CAL_BIT) +#define ADC_CR2_RSTCAL BIT(ADC_CR2_RSTCAL_BIT) +#define ADC_CR2_DMA BIT(ADC_CR2_DMA_BIT) +#define ADC_CR2_ALIGN BIT(ADC_CR2_ALIGN_BIT) +#define ADC_CR2_JEXTSEL (0x7000) +#define ADC_CR2_JEXTTRIG BIT(ADC_CR2_JEXTTRIG_BIT) +#define ADC_CR2_EXTSEL (0xE0000) +#define ADC_CR2_EXTTRIG BIT(ADC_CR2_EXTTRIG_BIT) +#define ADC_CR2_JSWSTART BIT(ADC_CR2_JSWSTART_BIT) +#define ADC_CR2_SWSTART BIT(ADC_CR2_SWSTART_BIT) +#define ADC_CR2_TSEREFE BIT(ADC_CR2_TSEREFE_BIT) + +/* Sample time register 1 */ + +#define ADC_SMPR1_SMP17 (0x7 << 21) +#define ADC_SMPR1_SMP16 (0x7 << 18) +#define ADC_SMPR1_SMP15 (0x7 << 15) +#define ADC_SMPR1_SMP14 (0x7 << 12) +#define ADC_SMPR1_SMP13 (0x7 << 9) +#define ADC_SMPR1_SMP12 (0x7 << 6) +#define ADC_SMPR1_SMP11 (0x7 << 3) +#define ADC_SMPR1_SMP10 0x7 + +/* Sample time register 2 */ + +#define ADC_SMPR2_SMP9 (0x7 << 27) +#define ADC_SMPR2_SMP8 (0x7 << 24) +#define ADC_SMPR2_SMP7 (0x7 << 21) +#define ADC_SMPR2_SMP6 (0x7 << 18) +#define ADC_SMPR2_SMP5 (0x7 << 15) +#define ADC_SMPR2_SMP4 (0x7 << 12) +#define ADC_SMPR2_SMP3 (0x7 << 9) +#define ADC_SMPR2_SMP2 (0x7 << 6) +#define ADC_SMPR2_SMP1 (0x7 << 3) +#define ADC_SMPR2_SMP0 0x7 + +/* Injected channel data offset register */ + +#define ADC_JOFR_JOFFSET 0x3FF + +/* Watchdog high threshold register */ + +#define ADC_HTR_HT 0x3FF + +/* Watchdog low threshold register */ + +#define ADC_LTR_LT 0x3FF + +/* Regular sequence register 1 */ + +#define ADC_SQR1_L (0x1F << 20) +#define ADC_SQR1_SQ16 (0x1F << 15) +#define ADC_SQR1_SQ15 (0x1F << 10) +#define ADC_SQR1_SQ14 (0x1F << 5) +#define ADC_SQR1_SQ13 0x1F + +/* Regular sequence register 2 */ + +#define ADC_SQR2_SQ12 (0x1F << 25) +#define ADC_SQR2_SQ11 (0x1F << 20) +#define ADC_SQR2_SQ10 (0x1F << 16) +#define ADC_SQR2_SQ9 (0x1F << 10) +#define ADC_SQR2_SQ8 (0x1F << 5) +#define ADC_SQR2_SQ7 0x1F + +/* Regular sequence register 3 */ + +#define ADC_SQR3_SQ6 (0x1F << 25) +#define ADC_SQR3_SQ5 (0x1F << 20) +#define ADC_SQR3_SQ4 (0x1F << 16) +#define ADC_SQR3_SQ3 (0x1F << 10) +#define ADC_SQR3_SQ2 (0x1F << 5) +#define ADC_SQR3_SQ1 0x1F + +/* Injected sequence register */ + +#define ADC_JSQR_JL (0x3 << 20) +#define ADC_JSQR_JL_1CONV (0x0 << 20) +#define ADC_JSQR_JL_2CONV (0x1 << 20) +#define ADC_JSQR_JL_3CONV (0x2 << 20) +#define ADC_JSQR_JL_4CONV (0x3 << 20) +#define ADC_JSQR_JSQ4 (0x1F << 15) +#define ADC_JSQR_JSQ3 (0x1F << 10) +#define ADC_JSQR_JSQ2 (0x1F << 5) +#define ADC_JSQR_JSQ1 0x1F + +/* Injected data registers */ + +#define ADC_JDR_JDATA 0xFFFF + +/* Regular data register */ + +#define ADC_DR_ADC2DATA (0xFFFF << 16) +#define ADC_DR_DATA 0xFFFF + +void adc_init(const adc_dev *dev); /** - * @brief Perform a single synchronous software triggered conversion on a - * channel. - * @param dev ADC device to use for reading. - * @param channel channel to convert - * @return conversion result + * @brief External event selector for regular group conversion. + * @see adc_set_extsel */ -static inline uint32 adc_read(const adc_dev *dev, uint8 channel) { - adc_reg_map *regs = dev->regs; +typedef enum adc_extsel_event { + ADC_ADC12_TIM1_CC1 = (0 << 17), /**< ADC1 and ADC2: Timer 1 CC1 event */ + ADC_ADC12_TIM1_CC2 = (1 << 17), /**< ADC1 and ADC2: Timer 1 CC2 event */ + ADC_ADC12_TIM1_CC3 = (2 << 17), /**< ADC1 and ADC2: Timer 1 CC3 event */ + ADC_ADC12_TIM2_CC2 = (3 << 17), /**< ADC1 and ADC2: Timer 2 CC2 event */ + ADC_ADC12_TIM3_TRGO = (4 << 17), /**< ADC1 and ADC2: Timer 3 TRGO event */ + ADC_ADC12_TIM4_CC4 = (5 << 17), /**< ADC1 and ADC2: Timer 4 CC4 event */ + ADC_ADC12_EXTI11 = (6 << 17), /**< ADC1 and ADC2: EXTI11 event */ +#ifdef STM32_HIGH_DENSITY + ADC_ADC12_TIM8_TRGO = (6 << 17), /**< ADC1 and ADC2: Timer 8 TRGO + event (high density only) */ +#endif + ADC_ADC12_SWSTART = (7 << 17), /**< ADC1 and ADC2: Software start */ +#ifdef STM32_HIGH_DENSITY + ADC_ADC3_TIM3_CC1 = (0 << 17), /**< ADC3: Timer 3 CC1 event + (high density only) */ + ADC_ADC3_TIM2_CC3 = (1 << 17), /**< ADC3: Timer 2 CC3 event + (high density only) */ + ADC_ADC3_TIM1_CC3 = (2 << 17), /**< ADC3: Timer 1 CC3 event + (high density only) */ + ADC_ADC3_TIM8_CC1 = (3 << 17), /**< ADC3: Timer 8 CC1 event + (high density only) */ + ADC_ADC3_TIM8_TRGO = (4 << 17), /**< ADC3: Timer 8 TRGO event + (high density only) */ + ADC_ADC3_TIM5_CC1 = (5 << 17), /**< ADC3: Timer 5 CC1 event + (high density only) */ + ADC_ADC3_TIM5_CC3 = (6 << 17), /**< ADC3: Timer 5 CC3 event + (high density only) */ + ADC_ADC3_SWSTART = (7 << 17), /**< ADC3: Software start (high + density only) */ +#endif + ADC_SWSTART = (7 << 17) /**< ADC1, ADC2, ADC3: Software start */ +} adc_extsel_event; - /* Set target channel */ - regs->SQR3 = channel; +void adc_set_extsel(const adc_dev *dev, adc_extsel_event event); +void adc_foreach(void (*fn)(const adc_dev*)); - /* Start the conversion */ - regs->CR2 |= ADC_CR2_SWSTART; +/** ADC per-sample conversion times, in ADC clock cycles */ +typedef enum { + ADC_SMPR_1_5, /**< 1.5 ADC cycles */ + ADC_SMPR_7_5, /**< 7.5 ADC cycles */ + ADC_SMPR_13_5, /**< 13.5 ADC cycles */ + ADC_SMPR_28_5, /**< 28.5 ADC cycles */ + ADC_SMPR_41_5, /**< 41.5 ADC cycles */ + ADC_SMPR_55_5, /**< 55.5 ADC cycles */ + ADC_SMPR_71_5, /**< 71.5 ADC cycles */ + ADC_SMPR_239_5 /**< 239.5 ADC cycles */ +} adc_smp_rate; - /* Wait for it to finish */ - while((regs->SR & ADC_SR_EOC) == 0) - ; +void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); +void adc_calibrate(const adc_dev *dev); +uint16 adc_read(const adc_dev *dev, uint8 channel); - return regs->DR; +/** + * @brief Set the regular channel sequence length. + * + * Defines the total number of conversions in the regular channel + * conversion sequence. + * + * @param length Regular channel sequence length, from 1 to 16. + */ +static inline void adc_set_reg_seqlen(const adc_dev *dev, uint8 length) { + uint32 tmp = dev->regs->SQR1; + tmp &= ~ADC_SQR1_L; + tmp |= (length - 1) << 20; + dev->regs->SQR1 = tmp; } /** * @brief Set external trigger conversion mode event for regular channels * @param dev ADC device - * @param enable If 1, conversion on external events is enabled, 0 to disable + * @param enable If 1, conversion on external events is enabled; if 0, + * disabled. */ static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) { - *bb_perip(&dev->regs->CR2, 20) = !!enable; + *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable; } /** @@ -183,7 +333,7 @@ static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) { * @param dev ADC device to enable */ static inline void adc_enable(const adc_dev *dev) { - *bb_perip(&dev->regs->CR2, 0) = 1; + *bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 1; } /** @@ -191,18 +341,14 @@ static inline void adc_enable(const adc_dev *dev) { * @param dev ADC device to disable */ static inline void adc_disable(const adc_dev *dev) { - *bb_perip(&dev->regs->CR2, 0) = 0; + *bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 0; } /** - * @brief Disable all ADCs + * @brief Disable all ADC peripherals. */ static inline void adc_disable_all(void) { - adc_disable(ADC1); - adc_disable(ADC2); -#ifdef STM32_HIGH_DENSITY - adc_disable(ADC3); -#endif + adc_foreach(adc_disable); } #ifdef __cplusplus diff --git a/libmaple/timer.c b/libmaple/timer.c index ad0ec6f..a4e4032 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -189,8 +189,8 @@ void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) { } /** - * @brief Call a given function on all timers. - * @param fn Function to call on each timer. + * @brief Call a function on timer devices. + * @param fn Function to call on each timer device. */ void timer_foreach(void (*fn)(timer_dev*)) { fn(TIMER1); diff --git a/notes/coding_standard.txt b/notes/coding_standard.txt index 372ebf4..b81847d 100644 --- a/notes/coding_standard.txt +++ b/notes/coding_standard.txt @@ -220,3 +220,47 @@ General Formatting (require 'lineker) (dolist (hook '(c-mode-hook c++-mode-hook)) (add-hook hook (lambda () (lineker-mode 1)))) + +Language Features and Compiler Extensions +----------------------------------------- + +- In libmaple proper, aim for C99 compatibility. Some GCC extensions + are OK, but let's not go crazy. + +- If you'd like to get code into libmaple which uses a GCC extension + not already in use elsewhere, ask a LeafLabs developer (or another + one, if you are one) what they think about it first. + +- Explicitly approved GCC extensions: + + * asm volatile: + http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html + + * Nested functions: + http://gcc.gnu.org/onlinedocs/gcc/Nested-Functions.html + +- In wirish, generally be very conservative when using C++ features + that aren't part of C. We are forced to use C++ for Arduino + compatibility (and the general Arduino style of pretending that an + object is a library), but it's an angry beast, and we don't want to + provoke it. The mantra is "C with classes". + +- Explicitly approved C++ features: + + * Initializers that aren't constant; e.g. the gpio_dev* values in + PIN_MAPs. + + * Default arguments: e.g., the timeout argument defaulting to 0 + (meaning to wait forever) in waitForButtonPress(). + +- Explicitly forbidden C++ features: + + * Templates + +- C++ features that are conditionally allowed, but require explicit + approval from at least two libmaple developers (one of which may be + yourself): + + * Operator overloading: Never allowed when it's just for style. + Potentially allowed when you're implementing a class that models a + mathematical structure, and you'd like to implement e.g. operator+(). diff --git a/notes/native-pin-definitions.txt b/notes/native-pin-definitions.txt deleted file mode 100644 index b871f89..0000000 --- a/notes/native-pin-definitions.txt +++ /dev/null @@ -1,201 +0,0 @@ -Maple Native (STM32F103ZE) pin definitions, by GPIO bank. - -Source: ST DOC ID 14611, Datasheet for STM32F103xC, STM32F103xD, -STM32F103xE, Table 5, pp. 30--35. - -Some peripherals and extra functionality with less/no libmaple -relevance (at time of writing) are given in "Other" following each -bank's main table. Non-default alternate functions are not listed. If -wirish will/does remap the pin's main function after reset, the main -function is listed under "Other". - -This document was prepared carefully and is believed to be complete -and correct, but the final arbiter of truth is the ST datasheet. - -*** NB: UART 4 and 5 are NOT USART (columns are labeled appropriately). - ---------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C USART SPI DAC 5v? ---------------------------------------------------------------------------- -PA0 123in0 2ch1etr - - - 2cts - - - - 5ch1 - 8etr -PA1 123in1 5ch2 - - - 2rts - - - - 2ch2 -PA2 123in2 5ch3 - - - 2tx - - - - 2ch3 -PA3 123in3 5ch4 - - - 2rx - - - - 2ch4 -PA4 12in4 - - - - 2ck 1nss out1 - -PA5 12in5 - - - - - 1sck out2 - -PA6 12in6 8bkin - - - - 1miso - - - 3ch1 -PA7 12in7 8ch1n - - - - 1mosi - - - 3ch2 -PA8 - 1ch1 - - - 1ck - - Y -PA9 - 1ch2 - - - 1tx - - Y -PA10 - 1ch3 - - - 1rx - - Y -PA11 - 1ch4 - - - 1cts - - Y -PA12 - 1etr - - - 1rts - - Y -PA13 - - - - - - - - Y -PA14 - - - - - - - - Y -PA15 - - - 3ws - - 3nss - Y - -Other: - -PA0: WKUP -PA8: MCO -PA11: USBDM, CAN_RX -PA12: USBDP, CAN_TX -PA13: JTMS-SWDIO (default) -PA14: JTCK-SWCLK (default) -PA15: JTDI (default) - -------------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C USART SPI DAC 5v? SDIO -------------------------------------------------------------------------------- -PB0 12in8 3ch3 - - - - - - - - - 8ch2n -PB1 12in9 3ch4 - - - - - - - - - 8ch3n -PB2 - - - - - - - - Y - -PB3 - - - 3ck - - 3sck - Y - -PB4 - - - - - - 3miso - Y - -PB5 - - - 3sd 1smba - 3mosi - - - -PB6 - 4ch1 - - 1scl - - - Y - -PB7 - 4ch2 NADV - 1sda - - - Y - -PB8 - 4ch3 - - - - - - Y D4 -PB9 - 4ch4 - - - - - - Y D5 -PB10 - - - - 2scl 3tx - - Y - -PB11 - - - - 2sda 3rx - - Y - -PB12 - 1bkin - 2ws 2smba 3ck 2nss - Y - -PB13 - 1ch1n - 2ck - 3cts 2sck - Y - -PB14 - 1ch2n - - - 3rts 2miso - Y - -PB15 - 1ch3n - 2sd - - 2mosi - Y - - -Other: - -PB2: BOOT1 -PB3: JTDO (default) -PB4: NJTRST (default) - -------------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C UART SPI DAC 5v? SDIO -------------------------------------------------------------------------------- -PC0 123in10 - - - - - - - - - -PC1 123in11 - - - - - - - - - -PC2 123in12 - - - - - - - - - -PC3 123in13 - - - - - - - - - -PC4 12in14 - - - - - - - - - -PC5 12in15 - - - - - - - - - -PC6 - 8ch1 - 2mck - - - - Y D6 -PC7 - 8ch2 - 3mck - - - - Y D7 -PC8 - 8ch3 - - - - - - Y D0 -PC9 - 8ch4 - - - - - - Y D1 -PC10 - - - - - 4tx - - Y D2 -PC11 - - - - - 4rx - - Y D3 -PC12 - - - - - 5tx - - Y CK -PC13 - - - - - - - - - - -PC14 - - - - - - - - - - -PC15 - - - - - - - - - - - -Other: - -PC13: TAMPER_RTC -PC14: OSC32_IN -PC15: OSC32_OUT - -------------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C UART SPI DAC 5v? SDIO -------------------------------------------------------------------------------- -PD0 - - D2 - - - - - Y - -PD1 - - D3 - - - - - Y - -PD2 - 3etr - - - 5rx - - Y CMD -PD3 - - CLK - - - - - Y - -PD4 - - NOE - - - - - Y - -PD5 - - NWE - - - - - Y - -PD6 - - NWAIT - - - - - Y - -PD7 - - NE1 - - - - - Y - - NCE2 -PD8 - - D13 - - - - - Y - -PD9 - - D14 - - - - - Y - -PD10 - - D15 - - - - - Y - -PD11 - - A16 - - - - - Y - -PD12 - - A17 - - - - - Y - -PD13 - - A18 - - - - - Y - -PD14 - - D0 - - - - - Y - -PD15 - - D1 - - - - - Y - - -Other: - -PD0: OSC_IN (default) -PD1: OSC_OUT (default) - ---------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C USART SPI DAC 5v? ---------------------------------------------------------------------------- -PE0 - 4etr NBL0 - - - - - Y -PE1 - - NBL1 - - - - - Y -PE2 - - A23 - - - - - Y -PE3 - - A19 - - - - - Y -PE4 - - A20 - - - - - Y -PE5 - - A21 - - - - - Y -PE6 - - A22 - - - - - Y -PE7 - - D4 - - - - - Y -PE8 - - D5 - - - - - Y -PE9 - - D6 - - - - - Y -PE10 - - D7 - - - - - Y -PE11 - - D8 - - - - - Y -PE12 - - D9 - - - - - Y -PE13 - - D10 - - - - - Y -PE14 - - D11 - - - - - Y -PE15 - - D12 - - - - - Y - -Other: -PE2: TRACECK -PE3: TRACED0 -PE4: TRACED1 -PE5: TRACED2 -PE6: TRACED3 - ---------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C USART SPI DAC 5v? ---------------------------------------------------------------------------- -PF0 - - A0 - - - - - Y -PF1 - - A1 - - - - - Y -PF2 - - A2 - - - - - Y -PF3 - - A3 - - - - - Y -PF4 - - A4 - - - - - Y -PF5 - - A5 - - - - - Y -PF6 3in4 - NIORD - - - - - - -PF7 3in5 - NREG - - - - - - -PF8 3in6 - NIOWR - - - - - - -PF9 3in7 - CD - - - - - - -PF10 3in8 - INTR - - - - - - -PF11 - - NIOS16 - - - - - Y -PF12 - - A6 - - - - - Y -PF13 - - A7 - - - - - Y -PF14 - - A8 - - - - - Y -PF15 - - A9 - - - - - Y - ---------------------------------------------------------------------------- -STM32 ADC Timer FSMC I2S I2C USART SPI DAC 5v? ---------------------------------------------------------------------------- -PG0 - - A10 - - - - - Y -PG1 - - A11 - - - - - Y -PG2 - - A12 - - - - - Y -PG3 - - A13 - - - - - Y -PG4 - - A14 - - - - - Y -PG5 - - A15 - - - - - Y -PG6 - - INT2 - - - - - Y -PG7 - - INT3 - - - - - Y -PG8 - - - - - - - - Y -PG9 - - NE2 - - - - - Y - NCE3 -PG10 - - NCE4_1 - - - - - Y - NE3 -PG11 - - NCE4_2 - - - - - Y -PG12 - - NE4 - - - - - Y -PG13 - - A24 - - - - - Y -PG14 - - A25 - - - - - Y -PG15 - - - - - - - - Y diff --git a/notes/pin-definitions.txt b/notes/pin-definitions.txt new file mode 100644 index 0000000..71572ac --- /dev/null +++ b/notes/pin-definitions.txt @@ -0,0 +1,201 @@ +Pin definitions by GPIO bank. + +Source: ST DOC ID 14611, Datasheet for STM32F103xC, STM32F103xD, +STM32F103xE, Table 5, pp. 30--35. + +Some peripherals and extra functionality with less/no libmaple +relevance (at time of writing) are given in "Other" following each +bank's main table. Non-default alternate functions are not listed. If +wirish will/does remap the pin's main function after reset, the main +function is listed under "Other". + +This document was prepared carefully and is believed to be correct, +but the final arbiter of truth is the ST datasheet. + +*** NB: UART 4 and 5 are NOT USART (columns are labeled appropriately). + +--------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C USART SPI DAC 5v? +--------------------------------------------------------------------------- +PA0 123in0 2ch1etr - - - 2cts - - - + 5ch1 + 8etr +PA1 123in1 5ch2 - - - 2rts - - - + 2ch2 +PA2 123in2 5ch3 - - - 2tx - - - + 2ch3 +PA3 123in3 5ch4 - - - 2rx - - - + 2ch4 +PA4 12in4 - - - - 2ck 1nss out1 - +PA5 12in5 - - - - - 1sck out2 - +PA6 12in6 8bkin - - - - 1miso - - + 3ch1 +PA7 12in7 8ch1n - - - - 1mosi - - + 3ch2 +PA8 - 1ch1 - - - 1ck - - Y +PA9 - 1ch2 - - - 1tx - - Y +PA10 - 1ch3 - - - 1rx - - Y +PA11 - 1ch4 - - - 1cts - - Y +PA12 - 1etr - - - 1rts - - Y +PA13 - - - - - - - - Y +PA14 - - - - - - - - Y +PA15 - - - 3ws - - 3nss - Y + +Other: + +PA0: WKUP +PA8: MCO +PA11: USBDM, CAN_RX +PA12: USBDP, CAN_TX +PA13: JTMS-SWDIO (default) +PA14: JTCK-SWCLK (default) +PA15: JTDI (default) + +------------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C USART SPI DAC 5v? SDIO +------------------------------------------------------------------------------- +PB0 12in8 3ch3 - - - - - - - - + 8ch2n +PB1 12in9 3ch4 - - - - - - - - + 8ch3n +PB2 - - - - - - - - Y - +PB3 - - - 3ck - - 3sck - Y - +PB4 - - - - - - 3miso - Y - +PB5 - - - 3sd 1smba - 3mosi - - - +PB6 - 4ch1 - - 1scl - - - Y - +PB7 - 4ch2 NADV - 1sda - - - Y - +PB8 - 4ch3 - - - - - - Y D4 +PB9 - 4ch4 - - - - - - Y D5 +PB10 - - - - 2scl 3tx - - Y - +PB11 - - - - 2sda 3rx - - Y - +PB12 - 1bkin - 2ws 2smba 3ck 2nss - Y - +PB13 - 1ch1n - 2ck - 3cts 2sck - Y - +PB14 - 1ch2n - - - 3rts 2miso - Y - +PB15 - 1ch3n - 2sd - - 2mosi - Y - + +Other: + +PB2: BOOT1 +PB3: JTDO (default) +PB4: NJTRST (default) + +------------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C UART SPI DAC 5v? SDIO +------------------------------------------------------------------------------- +PC0 123in10 - - - - - - - - - +PC1 123in11 - - - - - - - - - +PC2 123in12 - - - - - - - - - +PC3 123in13 - - - - - - - - - +PC4 12in14 - - - - - - - - - +PC5 12in15 - - - - - - - - - +PC6 - 8ch1 - 2mck - - - - Y D6 +PC7 - 8ch2 - 3mck - - - - Y D7 +PC8 - 8ch3 - - - - - - Y D0 +PC9 - 8ch4 - - - - - - Y D1 +PC10 - - - - - 4tx - - Y D2 +PC11 - - - - - 4rx - - Y D3 +PC12 - - - - - 5tx - - Y CK +PC13 - - - - - - - - - - +PC14 - - - - - - - - - - +PC15 - - - - - - - - - - + +Other: + +PC13: TAMPER_RTC +PC14: OSC32_IN +PC15: OSC32_OUT + +------------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C UART SPI DAC 5v? SDIO +------------------------------------------------------------------------------- +PD0 - - D2 - - - - - Y - +PD1 - - D3 - - - - - Y - +PD2 - 3etr - - - 5rx - - Y CMD +PD3 - - CLK - - - - - Y - +PD4 - - NOE - - - - - Y - +PD5 - - NWE - - - - - Y - +PD6 - - NWAIT - - - - - Y - +PD7 - - NE1 - - - - - Y - + NCE2 +PD8 - - D13 - - - - - Y - +PD9 - - D14 - - - - - Y - +PD10 - - D15 - - - - - Y - +PD11 - - A16 - - - - - Y - +PD12 - - A17 - - - - - Y - +PD13 - - A18 - - - - - Y - +PD14 - - D0 - - - - - Y - +PD15 - - D1 - - - - - Y - + +Other: + +PD0: OSC_IN (default) +PD1: OSC_OUT (default) + +--------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C USART SPI DAC 5v? +--------------------------------------------------------------------------- +PE0 - 4etr NBL0 - - - - - Y +PE1 - - NBL1 - - - - - Y +PE2 - - A23 - - - - - Y +PE3 - - A19 - - - - - Y +PE4 - - A20 - - - - - Y +PE5 - - A21 - - - - - Y +PE6 - - A22 - - - - - Y +PE7 - - D4 - - - - - Y +PE8 - - D5 - - - - - Y +PE9 - - D6 - - - - - Y +PE10 - - D7 - - - - - Y +PE11 - - D8 - - - - - Y +PE12 - - D9 - - - - - Y +PE13 - - D10 - - - - - Y +PE14 - - D11 - - - - - Y +PE15 - - D12 - - - - - Y + +Other: +PE2: TRACECK +PE3: TRACED0 +PE4: TRACED1 +PE5: TRACED2 +PE6: TRACED3 + +--------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C USART SPI DAC 5v? +--------------------------------------------------------------------------- +PF0 - - A0 - - - - - Y +PF1 - - A1 - - - - - Y +PF2 - - A2 - - - - - Y +PF3 - - A3 - - - - - Y +PF4 - - A4 - - - - - Y +PF5 - - A5 - - - - - Y +PF6 3in4 - NIORD - - - - - - +PF7 3in5 - NREG - - - - - - +PF8 3in6 - NIOWR - - - - - - +PF9 3in7 - CD - - - - - - +PF10 3in8 - INTR - - - - - - +PF11 - - NIOS16 - - - - - Y +PF12 - - A6 - - - - - Y +PF13 - - A7 - - - - - Y +PF14 - - A8 - - - - - Y +PF15 - - A9 - - - - - Y + +--------------------------------------------------------------------------- +GPIO ADC Timer FSMC I2S I2C USART SPI DAC 5v? +--------------------------------------------------------------------------- +PG0 - - A10 - - - - - Y +PG1 - - A11 - - - - - Y +PG2 - - A12 - - - - - Y +PG3 - - A13 - - - - - Y +PG4 - - A14 - - - - - Y +PG5 - - A15 - - - - - Y +PG6 - - INT2 - - - - - Y +PG7 - - INT3 - - - - - Y +PG8 - - - - - - - - Y +PG9 - - NE2 - - - - - Y + NCE3 +PG10 - - NCE4_1 - - - - - Y + NE3 +PG11 - - NCE4_2 - - - - - Y +PG12 - - NE4 - - - - - Y +PG13 - - A24 - - - - - Y +PG14 - - A25 - - - - - Y +PG15 - - - - - - - - Y diff --git a/wirish/boards.cpp b/wirish/boards.cpp new file mode 100644 index 0000000..17f47c6 --- /dev/null +++ b/wirish/boards.cpp @@ -0,0 +1,145 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + *****************************************************************************/ + +/** + * @brief Generic board initialization routines. + * + * By default, we bring up all Maple boards to 72MHz, clocked off the + * PLL, driven by the 8MHz external crystal. AHB and APB2 are clocked + * at 72MHz. APB1 is clocked at 36MHz. + */ + +#include "wirish.h" + +#include "flash.h" +#include "rcc.h" +#include "nvic.h" +#include "systick.h" +#include "gpio.h" +#include "adc.h" +#include "timer.h" +#include "usb.h" + +static void setupFlash(void); +static void setupClocks(void); +static void setupADC(void); +static void setupTimers(void); + +/** + * @brief Generic board initialization function. + * + * This function is called before main(). It ensures that the clocks + * and peripherals are configured properly for use with wirish, then + * calls boardInit(). + * + * @see boardInit() + */ +void init(void) { + setupFlash(); + setupClocks(); + nvic_init(); + systick_init(SYSTICK_RELOAD_VAL); + gpio_init_all(); + afio_init(); + setupADC(); + setupTimers(); + setupUSB(); + boardInit(); +} + +static void setupFlash(void) { + flash_enable_prefetch(); + flash_set_latency(FLASH_WAIT_STATE_2); +} + +/* + * Clock setup. Note that some of this only takes effect if we're + * running bare metal and the bootloader hasn't done it for us + * already. + * + * If you change this function, you MUST change the file-level Doxygen + * comment above. + */ +static void setupClocks() { + rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); + rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); + rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); + rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); +} + +static void adcDefaultConfig(const adc_dev* dev); + +static void setupADC() { + adc_foreach(adcDefaultConfig); +} + +static void timerDefaultConfig(timer_dev*); + +static void setupTimers() { + timer_foreach(timerDefaultConfig); +} + +static void adcDefaultConfig(const adc_dev *dev) { + adc_init(dev); + + adc_set_extsel(dev, ADC_SWSTART); + adc_set_exttrig(dev, true); + + adc_enable(dev); + adc_calibrate(dev); + adc_set_sample_rate(dev, ADC_SMPR_55_5); +} + +static void timerDefaultConfig(timer_dev *dev) { + timer_adv_reg_map *regs = (dev->regs).adv; + const uint16 full_overflow = 0xFFFF; + const uint16 half_duty = 0x8FFF; + + timer_init(dev); + timer_pause(dev); + + regs->CR1 = TIMER_CR1_ARPE; + regs->PSC = 1; + regs->SR = 0; + regs->DIER = 0; + regs->EGR = TIMER_EGR_UG; + + switch (dev->type) { + case TIMER_ADVANCED: + regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; + // fall-through + case TIMER_GENERAL: + timer_set_reload(dev, full_overflow); + + for (int channel = 1; channel <= 4; channel++) { + timer_set_compare(dev, channel, half_duty); + timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); + } + // fall-through + case TIMER_BASIC: + break; + } + + timer_resume(dev); +} diff --git a/wirish/boards.h b/wirish/boards.h index b72609d..3d023ae 100644 --- a/wirish/boards.h +++ b/wirish/boards.h @@ -60,12 +60,22 @@ enum { D106, D107, D108, D109, D110, D111, }; /** - * @brief Maps each pin to a corresponding struct stm32_pin_info. - * @see struct stm32_pin_info + * @brief Maps each Maple pin to a corresponding stm32_pin_info. + * @see stm32_pin_info */ extern stm32_pin_info PIN_MAP[]; -/** Board-specific initialization function. */ +void init(void); + +/** + * @brief Board-specific initialization function. + * + * This function is called from init() after all generic board + * initialization has been performed. Each board is required to + * define its own. + * + * @see init() + */ extern void boardInit(void); #ifdef BOARD_maple diff --git a/wirish/boards/maple.cpp b/wirish/boards/maple.cpp index cebd222..ba2261b 100644 --- a/wirish/boards/maple.cpp +++ b/wirish/boards/maple.cpp @@ -44,51 +44,51 @@ stm32_pin_info PIN_MAP[NR_GPIO_PINS] = { /* Top header */ - {GPIOA, TIMER2, 3, 4, 3}, /* D0/PA3 */ - {GPIOA, TIMER2, 2, 3, 2}, /* D1/PA2 */ - {GPIOA, TIMER2, 0, 1, 0}, /* D2/PA0 */ - {GPIOA, TIMER2, 1, 2, 1}, /* D3/PA1 */ - {GPIOB, NULL, 5, 0, ADCx}, /* D4/PB5 */ - {GPIOB, TIMER4, 6, 1, ADCx}, /* D5/PB6 */ - {GPIOA, TIMER1, 8, 1, ADCx}, /* D6/PA8 */ - {GPIOA, TIMER1, 9, 2, ADCx}, /* D7/PA9 */ - {GPIOA, TIMER1, 10, 3, ADCx}, /* D8/PA10 */ - {GPIOB, TIMER4, 7, 2, ADCx}, /* D9/PB7 */ - {GPIOA, NULL, 4, 0, 4}, /* D10/PA4 */ - {GPIOA, TIMER3, 7, 2, 7}, /* D11/PA7 */ - {GPIOA, TIMER3, 6, 1, 6}, /* D12/PA6 */ - {GPIOA, NULL, 5, 0, 5}, /* D13/PA5 (LED) */ - {GPIOB, TIMER4, 8, 3, ADCx}, /* D14/PB8 */ + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ /* Little header */ - {GPIOC, NULL, 0, 0, 10}, /* D15/PC0 */ - {GPIOC, NULL, 1, 0, 11}, /* D16/PC1 */ - {GPIOC, NULL, 2, 0, 12}, /* D17/PC2 */ - {GPIOC, NULL, 3, 0, 13}, /* D18/PC3 */ - {GPIOC, NULL, 4, 0, 14}, /* D19/PC4 */ - {GPIOC, NULL, 5, 0, 15}, /* D20/PC5 */ + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ /* External header */ - {GPIOC, NULL, 13, 0, ADCx}, /* D21/PC13 */ - {GPIOC, NULL, 14, 0, ADCx}, /* D22/PC14 */ - {GPIOC, NULL, 15, 0, ADCx}, /* D23/PC15 */ - {GPIOB, TIMER4, 9, 4, ADCx}, /* D24/PB9 */ - {GPIOD, NULL, 2, 0, ADCx}, /* D25/PD2 */ - {GPIOC, NULL, 10, 0, ADCx}, /* D26/PC10 */ - {GPIOB, TIMER3, 0, 3, 8}, /* D27/PB0 */ - {GPIOB, TIMER3, 1, 4, 9}, /* D28/PB1 */ - {GPIOB, NULL, 10, 0, ADCx}, /* D29/PB10 */ - {GPIOB, NULL, 11, 0, ADCx}, /* D30/PB11 */ - {GPIOB, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, NULL, 13, 0, ADCx}, /* D32/PB13 */ - {GPIOB, NULL, 14, 0, ADCx}, /* D33/PB14 */ - {GPIOB, NULL, 15, 0, ADCx}, /* D34/PB15 */ - {GPIOC, NULL, 6, 0, ADCx}, /* D35/PC6 */ - {GPIOC, NULL, 7, 0, ADCx}, /* D36/PC7 */ - {GPIOC, NULL, 8, 0, ADCx}, /* D37/PC8 */ - {GPIOC, NULL, 9, 0, ADCx} /* D38/PC9 (BUT) */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ + {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D35/PC6 */ + {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D36/PC7 */ + {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D37/PC8 */ + {GPIOC, NULL, NULL, 9, 0, ADCx} /* D38/PC9 (BUT) */ }; #endif diff --git a/wirish/boards/maple_RET6.cpp b/wirish/boards/maple_RET6.cpp index ae31ce3..962affc 100644 --- a/wirish/boards/maple_RET6.cpp +++ b/wirish/boards/maple_RET6.cpp @@ -38,51 +38,54 @@ void boardInit(void) { } stm32_pin_info PIN_MAP[NR_GPIO_PINS] = { - {GPIOA, TIMER2, 3, 4, 3}, /* D0/PA3 */ - {GPIOA, TIMER2, 2, 3, 2}, /* D1/PA2 */ - {GPIOA, TIMER2, 0, 1, 0}, /* D2/PA0 */ - {GPIOA, TIMER2, 1, 2, 1}, /* D3/PA1 */ - {GPIOB, NULL, 5, 0, ADCx}, /* D4/PB5 */ - {GPIOB, TIMER4, 6, 1, ADCx}, /* D5/PB6 */ - {GPIOA, TIMER1, 8, 1, ADCx}, /* D6/PA8 */ - {GPIOA, TIMER1, 9, 2, ADCx}, /* D7/PA9 */ - {GPIOA, TIMER1, 10, 3, ADCx}, /* D8/PA10 */ - {GPIOB, TIMER4, 7, 2, ADCx}, /* D9/PB7 */ - {GPIOA, NULL, 4, 0, 4}, /* D10/PA4 */ - {GPIOA, TIMER3, 7, 2, 7}, /* D11/PA7 */ - {GPIOA, TIMER3, 6, 1, 6}, /* D12/PA6 */ - {GPIOA, NULL, 5, 0, 5}, /* D13/PA5 (LED) */ - {GPIOB, TIMER4, 8, 3, ADCx}, /* D14/PB8 */ + + /* Top header */ + + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ /* Little header */ - {GPIOC, NULL, 0, 0, 10}, /* D15/PC0 */ - {GPIOC, NULL, 1, 0, 11}, /* D16/PC1 */ - {GPIOC, NULL, 2, 0, 12}, /* D17/PC2 */ - {GPIOC, NULL, 3, 0, 13}, /* D18/PC3 */ - {GPIOC, NULL, 4, 0, 14}, /* D19/PC4 */ - {GPIOC, NULL, 5, 0, 15}, /* D20/PC5 */ + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ /* External header */ - {GPIOC, NULL, 13, 0, ADCx}, /* D21/PC13 */ - {GPIOC, NULL, 14, 0, ADCx}, /* D22/PC14 */ - {GPIOC, NULL, 15, 0, ADCx}, /* D23/PC15 */ - {GPIOB, TIMER4, 9, 4, ADCx}, /* D24/PB9 */ - {GPIOD, NULL, 2, 0, ADCx}, /* D25/PD2 */ - {GPIOC, NULL, 10, 0, ADCx}, /* D26/PC10 */ - {GPIOB, TIMER3, 0, 3, 8}, /* D27/PB0 */ - {GPIOB, TIMER3, 1, 4, 9}, /* D28/PB1 */ - {GPIOB, NULL, 10, 0, ADCx}, /* D29/PB10 */ - {GPIOB, NULL, 11, 0, ADCx}, /* D30/PB11 */ - {GPIOB, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, NULL, 13, 0, ADCx}, /* D32/PB13 */ - {GPIOB, NULL, 14, 0, ADCx}, /* D33/PB14 */ - {GPIOB, NULL, 15, 0, ADCx}, /* D34/PB15 */ - {GPIOC, TIMER8, 6, 1, ADCx}, /* D35/PC6 */ - {GPIOC, TIMER8, 7, 2, ADCx}, /* D36/PC7 */ - {GPIOC, TIMER8, 8, 3, ADCx}, /* D37/PC8 */ - {GPIOC, TIMER8, 9, 4, ADCx} /* D38/PC9 (BUT) */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ + {GPIOC, TIMER8, NULL, 6, 1, ADCx}, /* D35/PC6 */ + {GPIOC, TIMER8, NULL, 7, 2, ADCx}, /* D36/PC7 */ + {GPIOC, TIMER8, NULL, 8, 3, ADCx}, /* D37/PC8 */ + {GPIOC, TIMER8, NULL, 9, 4, ADCx} /* D38/PC9 (BUT) */ }; #endif diff --git a/wirish/boards/maple_mini.cpp b/wirish/boards/maple_mini.cpp index 8c005cf..66a0997 100644 --- a/wirish/boards/maple_mini.cpp +++ b/wirish/boards/maple_mini.cpp @@ -45,43 +45,43 @@ stm32_pin_info PIN_MAP[NR_GPIO_PINS] = { /* Top header */ - {GPIOB, NULL, 11, 0, ADCx}, /* D0/PB11 */ - {GPIOB, NULL, 10, 0, ADCx}, /* D1/PB10 */ - {GPIOB, NULL, 2, 0, ADCx}, /* D2/PB2 */ - {GPIOB, TIMER3, 0, 3, 8}, /* D3/PB0 */ - {GPIOA, TIMER3, 7, 2, 7}, /* D4/PA7 */ - {GPIOA, TIMER3, 6, 1, 6}, /* D5/PA6 */ - {GPIOA, NULL, 5, 0, 5}, /* D6/PA5 */ - {GPIOA, NULL, 4, 0, 4}, /* D7/PA4 */ - {GPIOA, TIMER2, 3, 4, 3}, /* D8/PA3 */ - {GPIOA, TIMER2, 2, 3, 2}, /* D9/PA2 */ - {GPIOA, TIMER2, 1, 2, 1}, /* D10/PA1 */ - {GPIOA, TIMER2, 0, 1, 0}, /* D11/PA0 */ - {GPIOC, NULL, 15, 0, ADCx}, /* D12/PC15 */ - {GPIOC, NULL, 14, 0, ADCx}, /* D13/PC14 */ - {GPIOC, NULL, 13, 0, ADCx}, /* D14/PC13 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D0/PB11 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D1/PB10 */ + {GPIOB, NULL, NULL, 2, 0, ADCx}, /* D2/PB2 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D3/PB0 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D4/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D5/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D6/PA5 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D7/PA4 */ + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D8/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D9/PA2 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D10/PA1 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D11/PA0 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D12/PC15 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D13/PC14 */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D14/PC13 */ /* Bottom header */ - {GPIOB, TIMER4, 7, 2, ADCx}, /* D15/PB7 */ - {GPIOB, TIMER4, 6, 1, ADCx}, /* D16/PB6 */ - {GPIOB, NULL, 5, 0, ADCx}, /* D17/PB5 */ - {GPIOB, NULL, 4, 0, ADCx}, /* D18/PB4 */ - {GPIOB, NULL, 3, 0, ADCx}, /* D19/PB3 */ - {GPIOA, NULL, 15, 0, ADCx}, /* D20/PA15 */ - {GPIOA, NULL, 14, 0, ADCx}, /* D21/PA14 */ - {GPIOA, NULL, 13, 0, ADCx}, /* D22/PA13 */ - {GPIOA, NULL, 12, 0, ADCx}, /* D23/PA12 */ - {GPIOA, TIMER1, 11, 4, ADCx}, /* D24/PA11 */ - {GPIOA, TIMER1, 10, 3, ADCx}, /* D25/PA10 */ - {GPIOA, TIMER2, 9, 2, ADCx}, /* D26/PA9 */ - {GPIOA, TIMER1, 8, 1, ADCx}, /* D27/PA8 */ - {GPIOB, NULL, 15, 0, ADCx}, /* D28/PB15 */ - {GPIOB, NULL, 14, 0, ADCx}, /* D29/PB14 */ - {GPIOB, NULL, 13, 0, ADCx}, /* D30/PB13 */ - {GPIOB, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, TIMER4, 8, 3, ADCx}, /* D32/PB8 */ - {GPIOB, TIMER3, 1, 4, 9}, /* D33/PB1 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D15/PB7 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D16/PB6 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D17/PB5 */ + {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D18/PB4 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D19/PB3 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D20/PA15 */ + {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D21/PA14 */ + {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D22/PA13 */ + {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D23/PA12 */ + {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D24/PA11 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D25/PA10 */ + {GPIOA, TIMER2, NULL, 9, 2, ADCx}, /* D26/PA9 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D27/PA8 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D28/PB15 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D29/PB14 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D30/PB13 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D32/PB8 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D33/PB1 */ }; #endif diff --git a/wirish/boards/maple_native.cpp b/wirish/boards/maple_native.cpp index c04e98f..75c6a2d 100644 --- a/wirish/boards/maple_native.cpp +++ b/wirish/boards/maple_native.cpp @@ -43,113 +43,113 @@ stm32_pin_info PIN_MAP[NR_GPIO_PINS] = { /* Top header */ - {GPIOB, NULL, 10, 0, ADCx}, /* D0/PB10 */ - {GPIOB, NULL, 2, 0, ADCx}, /* D1/PB2 */ - {GPIOB, NULL, 12, 0, ADCx}, /* D2/PB12 */ - {GPIOB, NULL, 13, 0, ADCx}, /* D3/PB13 */ - {GPIOB, NULL, 14, 0, ADCx}, /* D4/PB14 */ - {GPIOB, NULL, 15, 0, ADCx}, /* D5/PB15 */ - {GPIOC, NULL, 0, 0, 10}, /* D6/PC0 */ - {GPIOC, NULL, 1, 0, 11}, /* D7/PC1 */ - {GPIOC, NULL, 2, 0, 12}, /* D8/PC2 */ - {GPIOC, NULL, 3, 0, 13}, /* D9/PC3 */ - {GPIOC, NULL, 4, 0, 14}, /* D10/PC4 */ - {GPIOC, NULL, 5, 0, 15}, /* D11/PC5 */ - {GPIOC, TIMER8, 6, 1, ADCx}, /* D12/PC6 */ - {GPIOC, TIMER8, 7, 2, ADCx}, /* D13/PC7 */ - {GPIOC, TIMER8, 8, 3, ADCx}, /* D14/PC8 */ - {GPIOC, TIMER8, 9, 4, ADCx}, /* D15/PC9 */ - {GPIOC, NULL, 10, 0, ADCx}, /* D16/PC10 */ - {GPIOC, NULL, 11, 0, ADCx}, /* D17/PC11 */ - {GPIOC, NULL, 12, 0, ADCx}, /* D18/PC12 */ - {GPIOC, NULL, 13, 0, ADCx}, /* D19/PC13 */ - {GPIOC, NULL, 14, 0, ADCx}, /* D20/PC14 */ - {GPIOC, NULL, 15, 0, ADCx}, /* D21/PC15 */ - {GPIOA, TIMER1, 8, 1, ADCx}, /* D22/PA8 */ - {GPIOA, TIMER1, 9, 2, ADCx}, /* D23/PA9 */ - {GPIOA, TIMER1, 10, 3, ADCx}, /* D24/PA10 */ - {GPIOB, TIMER4, 9, 4, ADCx}, /* D25/PB9 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D0/PB10 */ + {GPIOB, NULL, NULL, 2, 0, ADCx}, /* D1/PB2 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D2/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D3/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D4/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D5/PB15 */ + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D6/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D7/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D8/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D9/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D10/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D11/PC5 */ + {GPIOC, TIMER8, NULL, 6, 1, ADCx}, /* D12/PC6 */ + {GPIOC, TIMER8, NULL, 7, 2, ADCx}, /* D13/PC7 */ + {GPIOC, TIMER8, NULL, 8, 3, ADCx}, /* D14/PC8 */ + {GPIOC, TIMER8, NULL, 9, 4, ADCx}, /* D15/PC9 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D16/PC10 */ + {GPIOC, NULL, NULL, 11, 0, ADCx}, /* D17/PC11 */ + {GPIOC, NULL, NULL, 12, 0, ADCx}, /* D18/PC12 */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D19/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D20/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D21/PC15 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D22/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D23/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D24/PA10 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D25/PB9 */ /* Bottom header */ - /* FIXME (?) What about D48--D50 also being TIMER2_CH[234]? */ + /* Note: D{48, 49, 50} are also TIMER2_CH{2, 3, 4}, respectively. */ - {GPIOD, NULL, 2, 0, ADCx}, /* D26/PD2 */ - {GPIOD, NULL, 3, 0, ADCx}, /* D27/PD3 */ - {GPIOD, NULL, 6, 0, ADCx}, /* D28/PD6 */ - {GPIOG, NULL, 11, 0, ADCx}, /* D29/PG11 */ - {GPIOG, NULL, 12, 0, ADCx}, /* D30/PG12 */ - {GPIOG, NULL, 13, 0, ADCx}, /* D31/PG13 */ - {GPIOG, NULL, 14, 0, ADCx}, /* D32/PG14 */ - {GPIOG, NULL, 8, 0, ADCx}, /* D33/PG8 */ - {GPIOG, NULL, 7, 0, ADCx}, /* D34/PG7 */ - {GPIOG, NULL, 6, 0, ADCx}, /* D35/PG6 */ - {GPIOB, NULL, 5, 0, ADCx}, /* D36/PB5 */ - {GPIOB, TIMER4, 6, 1, ADCx}, /* D37/PB6 */ - {GPIOB, TIMER4, 7, 2, ADCx}, /* D38/PB7 */ - {GPIOF, NULL, 6, 0, 4}, /* D39/PF6 */ - {GPIOF, NULL, 7, 0, 5}, /* D40/PF7 */ - {GPIOF, NULL, 8, 0, 6}, /* D41/PF8 */ - {GPIOF, NULL, 9, 0, 7}, /* D42/PF9 */ - {GPIOF, NULL, 10, 0, 8}, /* D43/PF10 */ - {GPIOF, NULL, 11, 0, ADCx}, /* D44/PF11 */ - {GPIOB, TIMER3, 1, 4, 9}, /* D45/PB1 */ - {GPIOB, TIMER3, 0, 3, 8}, /* D46/PB0 */ - {GPIOA, TIMER5, 0, 1, 0}, /* D47/PA0 */ - {GPIOA, TIMER5, 1, 2, 1}, /* D48/PA1 */ - {GPIOA, TIMER5, 2, 3, 2}, /* D49/PA2 */ - {GPIOA, TIMER5, 3, 4, 3}, /* D50/PA3 */ - {GPIOA, NULL, 4, 0, 4}, /* D51/PA4 */ - {GPIOA, NULL, 5, 0, 5}, /* D52/PA5 */ - {GPIOA, TIMER3, 6, 1, 6}, /* D53/PA6 */ - {GPIOA, TIMER3, 7, 2, 7}, /* D54/PA7 */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D26/PD2 */ + {GPIOD, NULL, NULL, 3, 0, ADCx}, /* D27/PD3 */ + {GPIOD, NULL, NULL, 6, 0, ADCx}, /* D28/PD6 */ + {GPIOG, NULL, NULL, 11, 0, ADCx}, /* D29/PG11 */ + {GPIOG, NULL, NULL, 12, 0, ADCx}, /* D30/PG12 */ + {GPIOG, NULL, NULL, 13, 0, ADCx}, /* D31/PG13 */ + {GPIOG, NULL, NULL, 14, 0, ADCx}, /* D32/PG14 */ + {GPIOG, NULL, NULL, 8, 0, ADCx}, /* D33/PG8 */ + {GPIOG, NULL, NULL, 7, 0, ADCx}, /* D34/PG7 */ + {GPIOG, NULL, NULL, 6, 0, ADCx}, /* D35/PG6 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D36/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D37/PB6 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D38/PB7 */ + {GPIOF, NULL, ADC3, 6, 0, 4}, /* D39/PF6 */ + {GPIOF, NULL, ADC3, 7, 0, 5}, /* D40/PF7 */ + {GPIOF, NULL, ADC3, 8, 0, 6}, /* D41/PF8 */ + {GPIOF, NULL, ADC3, 9, 0, 7}, /* D42/PF9 */ + {GPIOF, NULL, ADC3, 10, 0, 8}, /* D43/PF10 */ + {GPIOF, NULL, NULL, 11, 0, ADCx}, /* D44/PF11 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D45/PB1 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D46/PB0 */ + {GPIOA, TIMER5, ADC1, 0, 1, 0}, /* D47/PA0 */ + {GPIOA, TIMER5, ADC1, 1, 2, 1}, /* D48/PA1 */ + {GPIOA, TIMER5, ADC1, 2, 3, 2}, /* D49/PA2 */ + {GPIOA, TIMER5, ADC1, 3, 4, 3}, /* D50/PA3 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D51/PA4 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D52/PA5 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D53/PA6 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D54/PA7 */ /* Right (triple) header */ - {GPIOF, NULL, 0, 0, ADCx}, /* D55/PF0 */ - {GPIOD, NULL, 11, 0, ADCx}, /* D56/PD11 */ - {GPIOD, NULL, 14, 0, ADCx}, /* D57/PD14 */ - {GPIOF, NULL, 1, 0, ADCx}, /* D58/PF1 */ - {GPIOD, NULL, 12, 0, ADCx}, /* D59/PD12 */ - {GPIOD, NULL, 15, 0, ADCx}, /* D60/PD15 */ - {GPIOF, NULL, 2, 0, ADCx}, /* D61/PF2 */ - {GPIOD, NULL, 13, 0, ADCx}, /* D62/PD13 */ - {GPIOD, NULL, 0, 0, ADCx}, /* D63/PD0 */ - {GPIOF, NULL, 3, 0, ADCx}, /* D64/PF3 */ - {GPIOE, NULL, 3, 0, ADCx}, /* D65/PE3 */ - {GPIOD, NULL, 1, 0, ADCx}, /* D66/PD1 */ - {GPIOF, NULL, 4, 0, ADCx}, /* D67/PF4 */ - {GPIOE, NULL, 4, 0, ADCx}, /* D68/PE4 */ - {GPIOE, NULL, 7, 0, ADCx}, /* D69/PE7 */ - {GPIOF, NULL, 5, 0, ADCx}, /* D70/PF5 */ - {GPIOE, NULL, 5, 0, ADCx}, /* D71/PE5 */ - {GPIOE, NULL, 8, 0, ADCx}, /* D72/PE8 */ - {GPIOF, NULL, 12, 0, ADCx}, /* D73/PF12 */ - {GPIOE, NULL, 6, 0, ADCx}, /* D74/PE6 */ - {GPIOE, NULL, 9, 0, ADCx}, /* D75/PE9 */ - {GPIOF, NULL, 13, 0, ADCx}, /* D76/PF13 */ - {GPIOE, NULL, 10, 0, ADCx}, /* D77/PE10 */ - {GPIOF, NULL, 14, 0, ADCx}, /* D78/PF14 */ - {GPIOG, NULL, 9, 0, ADCx}, /* D79/PG9 */ - {GPIOE, NULL, 11, 0, ADCx}, /* D80/PE11 */ - {GPIOF, NULL, 15, 0, ADCx}, /* D81/PF15 */ - {GPIOG, NULL, 10, 0, ADCx}, /* D82/PG10 */ - {GPIOE, NULL, 12, 0, ADCx}, /* D83/PE12 */ - {GPIOG, NULL, 0, 0, ADCx}, /* D84/PG0 */ - {GPIOD, NULL, 5, 0, ADCx}, /* D85/PD5 */ - {GPIOE, NULL, 13, 0, ADCx}, /* D86/PE13 */ - {GPIOG, NULL, 1, 0, ADCx}, /* D87/PG1 */ - {GPIOD, NULL, 4, 0, ADCx}, /* D88/PD4 */ - {GPIOE, NULL, 14, 0, ADCx}, /* D89/PE14 */ - {GPIOG, NULL, 2, 0, ADCx}, /* D90/PG2 */ - {GPIOE, NULL, 1, 0, ADCx}, /* D91/PE1 */ - {GPIOE, NULL, 15, 0, ADCx}, /* D92/PE15 */ - {GPIOG, NULL, 3, 0, ADCx}, /* D93/PG3 */ - {GPIOE, NULL, 0, 0, ADCx}, /* D94/PE0 */ - {GPIOD, NULL, 8, 0, ADCx}, /* D95/PD8 */ - {GPIOG, NULL, 4, 0, ADCx}, /* D96/PG4 */ - {GPIOD, NULL, 9, 0, ADCx}, /* D97/PD9 */ - {GPIOG, NULL, 5, 0, ADCx}, /* D98/PG5 */ - {GPIOD, NULL, 10, 0, ADCx} /* D99/PD10 */ + {GPIOF, NULL, NULL, 0, 0, ADCx}, /* D55/PF0 */ + {GPIOD, NULL, NULL, 11, 0, ADCx}, /* D56/PD11 */ + {GPIOD, NULL, NULL, 14, 0, ADCx}, /* D57/PD14 */ + {GPIOF, NULL, NULL, 1, 0, ADCx}, /* D58/PF1 */ + {GPIOD, NULL, NULL, 12, 0, ADCx}, /* D59/PD12 */ + {GPIOD, NULL, NULL, 15, 0, ADCx}, /* D60/PD15 */ + {GPIOF, NULL, NULL, 2, 0, ADCx}, /* D61/PF2 */ + {GPIOD, NULL, NULL, 13, 0, ADCx}, /* D62/PD13 */ + {GPIOD, NULL, NULL, 0, 0, ADCx}, /* D63/PD0 */ + {GPIOF, NULL, NULL, 3, 0, ADCx}, /* D64/PF3 */ + {GPIOE, NULL, NULL, 3, 0, ADCx}, /* D65/PE3 */ + {GPIOD, NULL, NULL, 1, 0, ADCx}, /* D66/PD1 */ + {GPIOF, NULL, NULL, 4, 0, ADCx}, /* D67/PF4 */ + {GPIOE, NULL, NULL, 4, 0, ADCx}, /* D68/PE4 */ + {GPIOE, NULL, NULL, 7, 0, ADCx}, /* D69/PE7 */ + {GPIOF, NULL, NULL, 5, 0, ADCx}, /* D70/PF5 */ + {GPIOE, NULL, NULL, 5, 0, ADCx}, /* D71/PE5 */ + {GPIOE, NULL, NULL, 8, 0, ADCx}, /* D72/PE8 */ + {GPIOF, NULL, NULL, 12, 0, ADCx}, /* D73/PF12 */ + {GPIOE, NULL, NULL, 6, 0, ADCx}, /* D74/PE6 */ + {GPIOE, NULL, NULL, 9, 0, ADCx}, /* D75/PE9 */ + {GPIOF, NULL, NULL, 13, 0, ADCx}, /* D76/PF13 */ + {GPIOE, NULL, NULL, 10, 0, ADCx}, /* D77/PE10 */ + {GPIOF, NULL, NULL, 14, 0, ADCx}, /* D78/PF14 */ + {GPIOG, NULL, NULL, 9, 0, ADCx}, /* D79/PG9 */ + {GPIOE, NULL, NULL, 11, 0, ADCx}, /* D80/PE11 */ + {GPIOF, NULL, NULL, 15, 0, ADCx}, /* D81/PF15 */ + {GPIOG, NULL, NULL, 10, 0, ADCx}, /* D82/PG10 */ + {GPIOE, NULL, NULL, 12, 0, ADCx}, /* D83/PE12 */ + {GPIOG, NULL, NULL, 0, 0, ADCx}, /* D84/PG0 */ + {GPIOD, NULL, NULL, 5, 0, ADCx}, /* D85/PD5 */ + {GPIOE, NULL, NULL, 13, 0, ADCx}, /* D86/PE13 */ + {GPIOG, NULL, NULL, 1, 0, ADCx}, /* D87/PG1 */ + {GPIOD, NULL, NULL, 4, 0, ADCx}, /* D88/PD4 */ + {GPIOE, NULL, NULL, 14, 0, ADCx}, /* D89/PE14 */ + {GPIOG, NULL, NULL, 2, 0, ADCx}, /* D90/PG2 */ + {GPIOE, NULL, NULL, 1, 0, ADCx}, /* D91/PE1 */ + {GPIOE, NULL, NULL, 15, 0, ADCx}, /* D92/PE15 */ + {GPIOG, NULL, NULL, 3, 0, ADCx}, /* D93/PG3 */ + {GPIOE, NULL, NULL, 0, 0, ADCx}, /* D94/PE0 */ + {GPIOD, NULL, NULL, 8, 0, ADCx}, /* D95/PD8 */ + {GPIOG, NULL, NULL, 4, 0, ADCx}, /* D96/PG4 */ + {GPIOD, NULL, NULL, 9, 0, ADCx}, /* D97/PD9 */ + {GPIOG, NULL, NULL, 5, 0, ADCx}, /* D98/PG5 */ + {GPIOD, NULL, NULL, 10, 0, ADCx} /* D99/PD10 */ }; #endif diff --git a/wirish/ext_interrupts.cpp b/wirish/ext_interrupts.cpp index 060994f..f9ccd39 100644 --- a/wirish/ext_interrupts.cpp +++ b/wirish/ext_interrupts.cpp @@ -49,7 +49,7 @@ void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) { exti_trigger_mode outMode = exti_out_mode(mode); - exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_pin), + exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit), gpio_exti_port(PIN_MAP[pin].gpio_device), handler, outMode); @@ -64,7 +64,7 @@ void detachInterrupt(uint8 pin) { return; } - exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_pin)); + exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit)); } static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) { diff --git a/wirish/io.h b/wirish/io.h index 8dad1d1..7d4fab1 100644 --- a/wirish/io.h +++ b/wirish/io.h @@ -28,8 +28,8 @@ * @brief Arduino-compatible digital pin I/O interface. */ -#ifndef _IO_H -#define _IO_H +#ifndef _IO_H_ +#define _IO_H_ #include "gpio.h" #include "adc.h" @@ -45,8 +45,8 @@ * This enum specifies the complete set of possible configurations; * not every pin can have all of these modes. For example, on the * Maple, pin 15 may be configured as INPUT_ANALOG, but not as PWM. - * See your device's silkscreen and and the GPIO documentation for - * more information. + * See your board's documentation and silkscreen for more information + * on what functionality is available on each pin. * * @see pinMode() */ @@ -114,8 +114,7 @@ typedef enum WiringPinMode { /** * Configure behavior of a GPIO pin. * - * @param pin Pin to configure. One of: 0-38 (pin numbers as labeled - * on silkscreen), or D0-D38 (symbols for same) + * @param pin Number of pin to configure. * @param mode Mode corresponding to desired pin behavior. * @see WiringPinMode */ @@ -136,8 +135,7 @@ void digitalWrite(uint8 pin, uint8 value); * Read a digital value from a pin. The pin must have its mode set to * one of INPUT, INPUT_PULLUP, and INPUT_PULLDOWN. * - * @param pin Pin to read from. One of: 0-38 (pin numbers as labeled - * on silkscreen), or D0-D38 (symbols for same) + * @param pin Pin to read from. * @return LOW or HIGH. * @see pinMode() */ @@ -146,18 +144,14 @@ uint32 digitalRead(uint8 pin); /** * Read an analog value from pin. This function blocks during ADC * conversion, and has 12 bits of resolution. The pin must have its - * mode set to INPUT_ANALOG. Ignoring function call overhead, - * conversion time is 55.5 cycles. + * mode set to INPUT_ANALOG. * - * @param pin Pin to read from. One of: 0, 1, 2, 3, 10, 11, 12, 13, - * 15, 16, 17, 18, 19, 20, 27, 28. - - * @return ADC-converted voltage, in the range 0--4095, inclusive - * (i.e. a 12-bit ADC conversion). - + * @param pin Pin to read from. + * @return Converted voltage, in the range 0--4095, (i.e. a 12-bit ADC + * conversion). * @see pinMode() */ -uint32 analogRead(uint8 pin); +uint16 analogRead(uint8 pin); /** * Toggles the digital value at the given pin. @@ -207,14 +201,15 @@ uint8 isButtonPressed(); * pinMode(BOARD_BUTTON_PIN, INPUT). * * @param timeout_millis Number of milliseconds to wait until the - * button is pressed. If timeout_millis is 0, wait forever. + * button is pressed. If timeout_millis is left out (or 0), wait + * forever. * * @return true, if the button was pressed; false, if the timeout was * reached. * * @see pinMode() */ -uint8 waitForButtonPress(uint32 timeout_millis); +uint8 waitForButtonPress(uint32 timeout_millis=0); /** * Shift out a byte of data, one bit at a time. diff --git a/wirish/pwm.cpp b/wirish/pwm.cpp index 6b09cef..4c803d2 100644 --- a/wirish/pwm.cpp +++ b/wirish/pwm.cpp @@ -38,5 +38,5 @@ void pwmWrite(uint8 pin, uint16 duty_cycle) { return; } - timer_set_compare(dev, PIN_MAP[pin].timer_chan, duty_cycle); + timer_set_compare(dev, PIN_MAP[pin].timer_channel, duty_cycle); } diff --git a/wirish/rules.mk b/wirish/rules.mk index c1d59bc..7715068 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -16,6 +16,7 @@ cSRCS_$(d) := cppSRCS_$(d) := wirish_math.cpp \ Print.cpp \ + boards.cpp \ boards/maple.cpp \ boards/maple_mini.cpp \ boards/maple_native.cpp \ @@ -24,14 +25,13 @@ cppSRCS_$(d) := wirish_math.cpp \ comm/HardwareSPI.cpp \ usb_serial.cpp \ cxxabi-compat.cpp \ - wirish.cpp \ wirish_shift.cpp \ wirish_analog.cpp \ time.cpp \ pwm.cpp \ ext_interrupts.cpp \ wirish_digital.cpp \ - native_sram.cpp \ + native_sram.cpp cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) cppFILES_$(d) := $(cppSRCS_$(d):%=$(d)/%) diff --git a/wirish/wirish.cpp b/wirish/wirish.cpp deleted file mode 100644 index aeed089..0000000 --- a/wirish/wirish.cpp +++ /dev/null @@ -1,128 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - *****************************************************************************/ - -/** - * @brief Generic Maple board initialization. - * - * By default, we bring up all Maple boards to 72MHz, clocked off the - * PLL, driven by the 8MHz external crystal. AHB and APB2 are clocked - * at 72MHz. APB1 is clocked at 36MHz. - */ - -#include "wirish.h" - -#include "flash.h" -#include "rcc.h" -#include "nvic.h" -#include "systick.h" -#include "gpio.h" -#include "adc.h" -#include "timer.h" -#include "usb.h" - -static void setupFlash(void); -static void setupClocks(void); -static void setupADC(void); -static void setupTimers(void); - -/** - * Board-wide initialization function. Called before main(). - */ -void init(void) { - setupFlash(); - setupClocks(); - nvic_init(); - systick_init(SYSTICK_RELOAD_VAL); - gpio_init_all(); - afio_init(); - setupADC(); - setupTimers(); - setupUSB(); - boardInit(); -} - -static void setupFlash(void) { - flash_enable_prefetch(); - flash_set_latency(FLASH_WAIT_STATE_2); -} - -/* - * Clock setup. Note that some of this only takes effect if we're - * running bare metal and the bootloader hasn't done it for us - * already. - * - * If you change this function, you MUST change the file-level Doxygen - * comment above. - */ -static void setupClocks() { - rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); - rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); - rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); - rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); -} - -/* TODO initialize more ADCs on high density boards. */ -static void setupADC() { - adc_init(ADC1, 0); - adc_set_sample_rate(ADC1, ADC_SMPR_55_5); // for high impedance inputs -} - -static void timerDefaultConfig(timer_dev*); - -static void setupTimers() { - timer_foreach(timerDefaultConfig); -} - -static void timerDefaultConfig(timer_dev *dev) { - timer_adv_reg_map *regs = (dev->regs).adv; - const uint16 full_overflow = 0xFFFF; - const uint16 half_duty = 0x8FFF; - - timer_init(dev); - timer_pause(dev); - - regs->CR1 = TIMER_CR1_ARPE; - regs->PSC = 1; - regs->SR = 0; - regs->DIER = 0; - regs->EGR = TIMER_EGR_UG; - - switch (dev->type) { - case TIMER_ADVANCED: - regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; - // fall-through - case TIMER_GENERAL: - timer_set_reload(dev, full_overflow); - - for (int channel = 1; channel <= 4; channel++) { - timer_set_compare(dev, channel, half_duty); - timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); - } - // fall-through - case TIMER_BASIC: - break; - } - - timer_resume(dev); -} diff --git a/wirish/wirish.h b/wirish/wirish.h index 13b14b6..880157d 100644 --- a/wirish/wirish.h +++ b/wirish/wirish.h @@ -67,7 +67,5 @@ typedef uint8 boolean; typedef uint8 byte; -void init(void); - #endif diff --git a/wirish/wirish_analog.cpp b/wirish/wirish_analog.cpp index 9e99aa5..8756caf 100644 --- a/wirish/wirish_analog.cpp +++ b/wirish/wirish_analog.cpp @@ -31,11 +31,12 @@ #include "io.h" /* Assumes that the ADC has been initialized and that the pin is set - * to ANALOG_INPUT */ -uint32 analogRead(uint8 pin) { - if(PIN_MAP[pin].adc_channel == ADCx) { + * to INPUT_ANALOG */ +uint16 analogRead(uint8 pin) { + const adc_dev *dev = PIN_MAP[pin].adc_device; + if (dev == NULL) { return 0; } - return adc_read(ADC1, PIN_MAP[pin].adc_channel); + return adc_read(dev, PIN_MAP[pin].adc_channel); } diff --git a/wirish/wirish_digital.cpp b/wirish/wirish_digital.cpp index 278cf10..115e91e 100644 --- a/wirish/wirish_digital.cpp +++ b/wirish/wirish_digital.cpp @@ -70,20 +70,14 @@ void pinMode(uint8 pin, WiringPinMode mode) { return; } - gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_pin, outputMode); + gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode); if (PIN_MAP[pin].timer_device != NULL) { - /* enable/disable timer channels if we're switching into or - out of pwm */ - if (pwm) { - timer_set_mode(PIN_MAP[pin].timer_device, - PIN_MAP[pin].timer_chan, - TIMER_PWM); - } else { - timer_set_mode(PIN_MAP[pin].timer_device, - PIN_MAP[pin].timer_chan, - TIMER_DISABLED); - } + /* Enable/disable timer channels if we're switching into or + * out of PWM. */ + timer_set_mode(PIN_MAP[pin].timer_device, + PIN_MAP[pin].timer_channel, + pwm ? TIMER_PWM : TIMER_DISABLED); } } @@ -93,7 +87,7 @@ uint32 digitalRead(uint8 pin) { return 0; } - return gpio_read_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_pin) ? + return gpio_read_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit) ? HIGH : LOW; } @@ -102,7 +96,7 @@ void digitalWrite(uint8 pin, uint8 val) { return; } - gpio_write_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_pin, val); + gpio_write_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, val); } void togglePin(uint8 pin) { @@ -110,12 +104,14 @@ void togglePin(uint8 pin) { return; } - gpio_toggle_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_pin); + gpio_toggle_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit); } +#define BUTTON_DEBOUNCE_DELAY 10 + uint8 isButtonPressed() { if (digitalRead(BOARD_BUTTON_PIN)) { - delay(1); + delay(BUTTON_DEBOUNCE_DELAY); while (digitalRead(BOARD_BUTTON_PIN)) ; return true; diff --git a/wirish/wirish_types.h b/wirish/wirish_types.h index 84591ea..7d6e31a 100644 --- a/wirish/wirish_types.h +++ b/wirish/wirish_types.h @@ -32,20 +32,28 @@ #include "gpio.h" #include "timer.h" +#include "adc.h" #ifndef _WIRISH_TYPES_H_ #define _WIRISH_TYPES_H_ -/** Stores STM32-specific information related to a given pin. */ +/** + * Invalid stm32_pin_info adc_channel value. + * @see stm32_pin_info + */ +#define ADCx 0xFF + +/** + * @brief Stores STM32-specific information related to a given Maple pin. + * @see PIN_MAP + */ typedef struct stm32_pin_info { - gpio_dev *gpio_device; /**< Maple pin's GPIO device */ - timer_dev *timer_device; /**< Maple pin's timer device, or NULL if none. */ - uint8 gpio_pin; /**< GPIO pin */ - uint8 timer_chan; /**< Timer channel, or 0 if none. */ - uint8 adc_channel; /**< Pin ADC channel, or ADCx if none. */ + gpio_dev *gpio_device; /**< Maple pin's GPIO device */ + timer_dev *timer_device; /**< Pin's timer device, if any. */ + const adc_dev *adc_device; /**< ADC device, if any. */ + uint8 gpio_bit; /**< Pin's GPIO port bit. */ + uint8 timer_channel; /**< Timer channel, or 0 if none. */ + uint8 adc_channel; /**< Pin ADC channel, or ADCx if none. */ } stm32_pin_info; -/** Invalid adc_channel value */ -#define ADCx 0xFF - #endif -- cgit v1.2.3 From 012d9ba1c2069d4d072685b990cbd01b611bb751 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 6 Apr 2011 11:51:57 -0400 Subject: Updated coding standard. --- notes/coding_standard.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'notes') diff --git a/notes/coding_standard.txt b/notes/coding_standard.txt index b81847d..0accda7 100644 --- a/notes/coding_standard.txt +++ b/notes/coding_standard.txt @@ -122,7 +122,7 @@ Naming conventions There's always a fight about upper and lower case vs. underscores. We'll handle this as follows. -- First, Dammit_Dont_Mix_Like_This, because It_Looks_Really_Ugly, ok? +- First, Dont_Mix_Like_This, because It_Looks_Really_Ugly, ok? [There's been some debate about this, and some exceptions are already grandfathered in, so in order to settle it, let's call this a "recommendation" instead of "requirement".] @@ -140,11 +140,9 @@ We'll handle this as follows. - Functions: C functions are all lowercase, and words are separated by underscores. C++ method names are camel cased (thisIsAnExample). -- Structs: pick a style from "Variables" or "Classes" depending on how - you mean it (since it might be either a simple record type, in which - case do like c variables, or you might be faking an object in c, in - which case do like classes). If it's in a typedef, don't feel - obliged to put "_t" at the end of the name; we don't. +- Structs: Usually like variables (adc_dev, adc_reg_map, etc.), but + it's not crucial. If it's in a typedef, don't feel obliged to put + "_t" at the end of the name; we don't. - Macros and constants: all caps, separated by underscores. Variables with the "const" qualifier aren't considered "constants" for the @@ -196,6 +194,10 @@ Documentation maintenance burden of documenting things in two places at once, and makes it easier for documentation to go stale. + If you do have to document something manually, put a comment in the + source file informing future maintainers about it, so they'll pay + extra attention when making changes. + - For libmaple proper (the pure C library under libmaple/); the convention is to document any user-facing entity at the point where it is defined. In particular, this means you should document an -- cgit v1.2.3 From a2b2ddb50b16400f17d8d36dfc9f4996f466ad94 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Apr 2011 14:43:00 -0400 Subject: Coding standard updates. --- notes/coding_standard.txt | 60 ++++++++++++++++++++++++++++++----------------- 1 file changed, 38 insertions(+), 22 deletions(-) (limited to 'notes') diff --git a/notes/coding_standard.txt b/notes/coding_standard.txt index 0accda7..f762e98 100644 --- a/notes/coding_standard.txt +++ b/notes/coding_standard.txt @@ -95,11 +95,13 @@ Comments - Doxygen comments are multi-line comments that begin with /** instead. -- Single-line comments on the same line are // in C or C++. +- Single-line comments on the same line are // in C++. (That's OK in C + as well). - Single-line comments on their own source line should be /* */ in C, but can also be // in C++. In Emacs, you can use M-; - (comment-dwim), and it'll Do What You Mean. + (comment-dwim), and it'll Do What You Mean. This isn't of great + importance. Braces ------ @@ -131,23 +133,27 @@ We'll handle this as follows. int some_example_name; - It is strongly advised to do it this way in C++ too, but it's not - [yet] mandatory. + User-facing C++ variables should be camel cased (thisIsAnExample, + boardPWMPins, etc.), for consistency with the Arduino style. It's + probably a good idea for you to case non-user facing C++ variables + in the C style; this will help disambiguate what's part of the + Wirish API and what's not. - Classes: Pascal case. So ThisIsAClassName, but thisIsNot, this_is_not, and like I said, Dont_You_DareTryANYTHING_STUPID. - Functions: C functions are all lowercase, and words are separated by - underscores. C++ method names are camel cased (thisIsAnExample). + underscores. C++ method names are camel cased. - Structs: Usually like variables (adc_dev, adc_reg_map, etc.), but - it's not crucial. If it's in a typedef, don't feel obliged to put - "_t" at the end of the name; we don't. + it's not crucial. Don't feel obliged to put "_t" at the end of the + type name; we don't. - Macros and constants: all caps, separated by underscores. Variables with the "const" qualifier aren't considered "constants" for the purposes of this rule; i.e., case them according to the rules for - variables. + variables. (We make an exception for PIN_MAP, but that's because + it's the central data structure for all of Wirish). - foo.h gets #ifdef'ed to _FOO_H_. @@ -157,28 +163,30 @@ We'll handle this as follows. void usb_func() { ... } + void frob_usb_disc() { ... } + class SomethingUSB { void usbInit(); void initUSB(); }; - Never do this: + DON'T do this: class BadUsb { ... }; // say "GoodUSB" instead + void swizzle_USB_disc() { ... } // say "swizzle_usb_disc" instead + Documentation ------------- -- Document your code! - -- For complicated peripherals, it would be nice if you put longer-form - comments into this directory (notes/), with a comment in the - corresponding .h file referring to it. See libmaple/dac.h for an - example. That lets us keep the source files relatively clean while - still allowing new readers to have a starting point. +- You must document your code. At a bare minimum, this means Doxygen + comments on every user-facing function and type. Additionally, you + need to individually document the fields and enumerator values of + structs and enums. See any register map type's definition for an + example. -- At least put a Doxygen comment with a nonempty @brief for every .h - file you add. See the existing ones for examples. +- For libmaple proper, you don't need comments for each register bit + definition (for now). - Doxygen comments generally just belong on types, functions, etc. that are part of the public user-facing API. This generally @@ -198,6 +206,15 @@ Documentation source file informing future maintainers about it, so they'll pay extra attention when making changes. +- For complicated peripherals, it would be nice if you put longer-form + comments into the libmaple notes/ directory, with a comment in the + corresponding .h file referring to it. See libmaple/dac.h for an + example. + + This lets us keep the source files relatively clean while still + allowing new readers to have a starting point. These longer-form + notes also have a habit of turning into user-facing documentation. + - For libmaple proper (the pure C library under libmaple/); the convention is to document any user-facing entity at the point where it is defined. In particular, this means you should document an @@ -208,16 +225,15 @@ General Formatting ------------------ - Keep it 80-column clean. That means Emacs says the largest column - number=79. If you haven't already, you should turn on column - numbers to help you out: + number=79. You should turn on column number mode to help you out: (column-number-mode 1) - You can get more help from lineker-mode. Download it here: + You can get more help from lineker-mode: http://www.helsinki.fi/~sjpaavol/programs/lineker.el - Then put the file somewhere in your load-path, and: + Just put lineker.el somewhere in your load-path, and: (require 'lineker) (dolist (hook '(c-mode-hook c++-mode-hook)) -- cgit v1.2.3 From b04fc94cfc991855544625af7e67ecf07c02f542 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Apr 2011 16:24:25 -0400 Subject: Timer tweaks. --- libmaple/timer.c | 30 +++++------ notes/timers.txt | 152 ++++++++++++++++++++++++++++--------------------------- 2 files changed, 90 insertions(+), 92 deletions(-) (limited to 'notes') diff --git a/libmaple/timer.c b/libmaple/timer.c index a4e4032..b22ffb4 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -32,12 +32,6 @@ #include "timer.h" -#if defined(STM32_MEDIUM_DENSITY) -#define NR_TIMERS 4 -#elif defined(STM32_HIGH_DENSITY) -#define NR_TIMERS 8 -#endif - /* Just like the corresponding DIER bits: * [0] = Update handler; * [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively; @@ -51,7 +45,7 @@ #define NR_BAS_HANDLERS 1 static timer_dev timer1 = { - .regs = {.adv = TIMER1_BASE}, + .regs = { .adv = TIMER1_BASE }, .clk_id = RCC_TIMER1, .type = TIMER_ADVANCED, .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, @@ -59,7 +53,7 @@ static timer_dev timer1 = { timer_dev *TIMER1 = &timer1; static timer_dev timer2 = { - .regs = {.gen = TIMER2_BASE}, + .regs = { .gen = TIMER2_BASE }, .clk_id = RCC_TIMER2, .type = TIMER_GENERAL, .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, @@ -67,7 +61,7 @@ static timer_dev timer2 = { timer_dev *TIMER2 = &timer2; static timer_dev timer3 = { - .regs = {.gen = TIMER3_BASE}, + .regs = { .gen = TIMER3_BASE }, .clk_id = RCC_TIMER3, .type = TIMER_GENERAL, .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, @@ -75,7 +69,7 @@ static timer_dev timer3 = { timer_dev *TIMER3 = &timer3; static timer_dev timer4 = { - .regs = {.gen = TIMER4_BASE}, + .regs = { .gen = TIMER4_BASE }, .clk_id = RCC_TIMER4, .type = TIMER_GENERAL, .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, @@ -84,7 +78,7 @@ timer_dev *TIMER4 = &timer4; #ifdef STM32_HIGH_DENSITY static timer_dev timer5 = { - .regs = {.gen = TIMER5_BASE}, + .regs = { .gen = TIMER5_BASE }, .clk_id = RCC_TIMER5, .type = TIMER_GENERAL, .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, @@ -92,7 +86,7 @@ static timer_dev timer5 = { timer_dev *TIMER5 = &timer5; static timer_dev timer6 = { - .regs = {.bas = TIMER6_BASE}, + .regs = { .bas = TIMER6_BASE }, .clk_id = RCC_TIMER6, .type = TIMER_BASIC, .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, @@ -100,7 +94,7 @@ static timer_dev timer6 = { timer_dev *TIMER6 = &timer6; static timer_dev timer7 = { - .regs = {.bas = TIMER7_BASE}, + .regs = { .bas = TIMER7_BASE }, .clk_id = RCC_TIMER7, .type = TIMER_BASIC, .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, @@ -108,7 +102,7 @@ static timer_dev timer7 = { timer_dev *TIMER7 = &timer7; static timer_dev timer8 = { - .regs = {.adv = TIMER8_BASE}, + .regs = { .adv = TIMER8_BASE }, .clk_id = RCC_TIMER8, .type = TIMER_ADVANCED, .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, @@ -168,7 +162,7 @@ void timer_disable(timer_dev *dev) { * @param mode New timer mode for channel */ void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) { - ASSERT(channel > 0 && channel <= 4); + ASSERT_FAULT(channel > 0 && channel <= 4); /* TODO decide about the basic timers */ ASSERT(dev->type != TIMER_BASIC); @@ -351,8 +345,8 @@ static inline void dispatch_cc_irqs(timer_dev *dev) { uint32 sr_clear = 0; uint32 b; - ASSERT(sr & (TIMER_SR_CC1IF | TIMER_SR_CC2IF | - TIMER_SR_CC3IF | TIMER_SR_CC4IF)); + ASSERT_FAULT(sr & (TIMER_SR_CC1IF | TIMER_SR_CC2IF | + TIMER_SR_CC3IF | TIMER_SR_CC4IF)); for (b = TIMER_SR_CC1IF_BIT; b <= TIMER_SR_CC4IF_BIT; b++) { uint32 mask = BIT(b); @@ -443,7 +437,7 @@ static void enable_nonmuxed_irq(timer_dev *dev) { break; #endif default: - ASSERT(0); + ASSERT_FAULT(0); break; } } diff --git a/notes/timers.txt b/notes/timers.txt index 3f5b9f4..647e92e 100644 --- a/notes/timers.txt +++ b/notes/timers.txt @@ -1,82 +1,87 @@ +Timers +====== -Each timer (1-4) has 4 capture/compare channels (1-4). These are directly used -by PWM but have a ton of other possible functionality. The STM32 implementation -is particularly complicated with, eg, the ability to chain together timers - -Timer1 is an "advanced timer" with many more features. I think if we use just -the "Capture and compare interrupt", and enable MOE during initialization -everything will be ok. There are seperate Break, Update, and Trigger interrupts -as well that we will ignore for now. - -Timer2,Ch 3+4 are D0 and D1, which conflict with Serial2. USART should work -fine as long as pins aren't in output mode? and timers should work fine if -Serial2 isn't in use? - -Caveats ------------------------------------------------------------------------------- -There are probably subtle bugs with the way register settings get read in; eg, -it is often required to have the counter fully overflow before new settings -come into effect? -Getting really good timing is still an art, not a science here... usually you -need to fiddle with an oscilloscope and the exact overflow/compare numbers to -get just the right time values. -Any other interrupts (SysTick, USB, Serial, etc) can blow away all the nice -timing stuff. - -Misc Notes ------------------------------------------------------------------------------- -Implementation with case/switch in the interrupt handlers doesn't work; a lot -of the time multiple interrupt flags are active at the same time (or become -active?) +Medium-density chips have timers 1 through 4. High- and XL-density +chips additionally have timers 5 through 8. XL-density chips +additionally have timers 9--14, which we don't support yet. + +Timer Capabilities +------------------ + +Each of timers 1--4 has 4 capture/compare (C/C) channels (also numbered +1--4). These are directly used by PWM, but may serve other purposes as +well (including handling user-specified periodic interrupts). The +STM32 implementation is particularly featureful, with, e.g., the +ability to chain together timers. + +Timers 1 and 8 are an advanced timers, with many more features. +Wirish just uses just their capture/compare interrupts and enables MOE +during initialization, essentially treating them as general purpose +timers (like timers 2--5). Advanced timers also have separate break, +update, and trigger interrupts that we only provide low-level +(i.e. libmaple proper) support for. + +Timers 6 and 7 are basic timers, without C/C channels. They are still +useful for interrupts (via NVIC_TIMER6, NVIC_TIMER7 IRQs, which can +fire upon an update event), but they're most useful for controlling +periodic DAC output. + +Known Issues and Other Caveats +------------------------------ + +There are some conflicts between timer C/C outputs and USART 1 and 2 +TX/RX. Wirish tries to handle this gracefully, but (as of 7 April +2011) not all the bugs are sorted yet. In particular, if you call +HardwareSerial::disable(), then try to use PWM, the USART TX pins +don't cooperate. + +Resetting the prescaler or reload value only takes effect at the next +update event. You can use timer_generate_update() to generate an +update event via software. + +Other interrupts (SysTick, USB, Serial, etc.) can interfere with +timing-critical applications. If your program requires precise +timing, you should probably at least disable USB and SysTick. Note +that this also disables the bootloader and stops millis()/micros() +from counting. + +Getting really good timing is a bit of an art. If things don't work +at first, you need to fiddle with an oscilloscope and the exact +overflow/compare numbers to get precise behavior. TODO ------------------------------------------------------------------------------- -- document carefully (eg, determine clock-wise and overflow-wise behavior for - each function) -- track down and handle all pin conflicts -- implement the update interrupt as a "5th channel" -- "pulse in" stuff, both c and c++ -- function to read out CCR registers -- allow comparison output to the pin (a la PWM) -- additional modes and configuration (up, down, up/down, etc) - -Possible Wirish implementation ------------------------------------------------------------------------------- -Inspired by Timer1 Library for arduino -http://arduino.cc/pipermail/developers_arduino.cc/2010-June/002845.html +---- + +- Document more carefully (e.g., determine clock-wise and + overflow-wise behavior for each function). - class HardwareTimer { - - public: - - void pause(); - void resume(); - void setPrescaleFactor(uint8 factor); - void setOverflow(uint16 val); // truncates to overflow - void setCount(uint16 val); // truncates to overflow - uint16 getCount(); - uint16 setPeriod(uint32 microseconds); // tries to set prescaler and overflow wisely; returns overflow - void setMode(uint8 mode); - void setCompare1(uint16 val); // truncates to overflow - void setCompare2(uint16 val); // truncates to overflow - void setCompare3(uint16 val); // truncates to overflow - void setCompare4(uint16 val); // truncates to overflow - void attachCompare1Interrupt(void (*f)(void)); - void attachCompare2Interrupt(void (*f)(void)); - void attachCompare3Interrupt(void (*f)(void)); - void attachCompare4Interrupt(void (*f)(void)); - void detachCompare1Interrupt(); - void detachCompare2Interrupt(); - void detachCompare3Interrupt(); - void detachCompare4Interrupt(); - }; - - HardwareTimer Timer1 = HardwareTimer(1); - HardwareTimer Timer2 = HardwareTimer(2); - HardwareTimer Timer3 = HardwareTimer(3); - HardwareTimer Timer4 = HardwareTimer(4); +- Track down and handle pin conflicts. + +- Input capture interface. DON'T WRITE pulseIn() IN TERMS OF THIS. + Do that as a simple, Arduino style implementation that just + busy-waits and uses micros(), to allow a pulseIn() on arbitrary + pins. Eventually, expose the more precise/harder to use timer-based + API via a convenience library. + +- Complementary outputs, with convenient break/dead time interface. + +- Additional modes (center-aligned PWM, one pulse mode, etc.) and + count configuration (down, up/down). + +Alternative Wirish Implementations +---------------------------------- + +The current Wirish API is big and clunky. Its inclusion by default +also threatens making everyone's sketches bigger unnecessarily. We +need to deprecate the parts of it that are bad for 0.0.10, and remove +them when 0.1.0 comes out. + +Current implementation was inspired by Timer1 Library for Arduino: + +http://arduino.cc/pipermail/developers_arduino.cc/2010-June/002845.html Here's one of the more standard libaries out there: + http://www.arduino.cc/playground/Code/Timer1 void initialize(long microseconds=1000000); @@ -89,4 +94,3 @@ http://www.arduino.cc/playground/Code/Timer1 void disablePwm(char pin); void attachInterrupt(void (*isr)(), long microseconds=-1); void detachInterrupt(); - -- cgit v1.2.3 From 686f12ad6728fec15129a98f5d1ec182bab4c6b9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Apr 2011 21:57:15 -0400 Subject: Coding standard tweaks. --- notes/coding_standard.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'notes') diff --git a/notes/coding_standard.txt b/notes/coding_standard.txt index f762e98..5b258f7 100644 --- a/notes/coding_standard.txt +++ b/notes/coding_standard.txt @@ -149,11 +149,11 @@ We'll handle this as follows. it's not crucial. Don't feel obliged to put "_t" at the end of the type name; we don't. -- Macros and constants: all caps, separated by underscores. Variables - with the "const" qualifier aren't considered "constants" for the - purposes of this rule; i.e., case them according to the rules for - variables. (We make an exception for PIN_MAP, but that's because - it's the central data structure for all of Wirish). +- Macros and constants: all caps, separated by underscores. C++ + variables with the "const" qualifier generally aren't considered + "constants" for the purposes of this rule; i.e., they are cased + according to the rules for variables. We make an exception for + PIN_MAP, because it's the central Wirish data structure. - foo.h gets #ifdef'ed to _FOO_H_. @@ -216,7 +216,7 @@ Documentation notes also have a habit of turning into user-facing documentation. - For libmaple proper (the pure C library under libmaple/); the - convention is to document any user-facing entity at the point where + convention is to document any user-facing function at the point where it is defined. In particular, this means you should document an externally-linked function defined in a .c file in that .c file, not in the header file where it is declared to the user. -- cgit v1.2.3 From 79d1ee686324b92036792986c733f733345c38fb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 8 Apr 2011 19:35:21 -0400 Subject: Coding standard updates. Added some content, converted document to .rst. --- notes/coding_standard.rst | 422 ++++++++++++++++++++++++++++++++++++++++++++++ notes/coding_standard.txt | 284 ------------------------------- 2 files changed, 422 insertions(+), 284 deletions(-) create mode 100644 notes/coding_standard.rst delete mode 100644 notes/coding_standard.txt (limited to 'notes') diff --git a/notes/coding_standard.rst b/notes/coding_standard.rst new file mode 100644 index 0000000..1deed03 --- /dev/null +++ b/notes/coding_standard.rst @@ -0,0 +1,422 @@ +libmaple Coding Standards +========================= + +Author: Marti Bolivar (mbolivar@leaflabs.com) + +LeafLabs team members are required to follow these when producing new +code. Community contributors to libmaple are strongly encouraged to +do so; following these rules will greatly increase the probability +that your patches will be folded in. + +In general, do it like this unless there's a really good reason why +not. You being lazy doesn't count as a good reason. Most, if not +all, of these decisions are entirely arbitrary, but it's important for +readability that we be consistent. + +The file ``.dir-locals.el`` in the libmaple root directory already +ensures that many of these standards are followed by default in Emacs +(but not on Windows, where it would need to be named +``_dir_locals.el``, and no way, man). There's also some elisp +scattered about this file which will provide you additional help. + +Vim customizations to do the same thing would be nice (hint, hint)! + +License +------- + +- Put an MIT license at the beginning of the file (look at any of our + source files for an example). Copyright should go either to you or + to LeafLabs, LLC. + +.. highlight:: scheme + + Emacs: if you don't like seeing the license, you should use + elide-head (which will hide it for you). You can use the following:: + + (require 'elide-head) + (setq programming-mode-hooks '(c-mode-hook c++-mode-hook)) + (add-to-list 'elide-head-headers-to-hide + '("The MIT License" . "DEALINGS IN\n [*] THE SOFTWARE")) + (add-to-list 'elide-head-headers-to-hide + '("The MIT License" . "DEALINGS IN THE\n...SOFTWARE")) + (dolist (hook programming-mode-hooks) + (add-hook hook (lambda () (elide-head)))) + +Whitespace/Indentation +---------------------- + +- 4 space indents. [Set in ``.dir-locals.el``] + +- Unix newlines. [Some exceptions are currently grandfathered in; + these will go away in time.] + +- No tab characters. [Set in ``.dir-locals.el``] + +- No trailing whitespace. For help getting this (and no tab + characters) done automatically in Emacs, you can use this: + + http://github.com/mbolivar/code-fascism + + I hear tell you can get something similar in Vim; ask around, I + guess. + +- Files end in exactly one newline. [The presence of a newline at EOF + is already done by ``c-require-final-newline`` in recent versions of + Emacs.] + +- Exactly two newlines separate source paragraphs (you do separate + your code into paragraphs, don't you?). + +- The first line in a function is non-blank. + +.. highlight:: cpp + +- Exactly one space after ``if``, ``else``, ``for``, and ``while``, + before the following ``{`` or ``(``. One space before ``else``, + after the preceding ``}``. For example:: + + // This is good; we like this: + if (foo) { + while (quux) { + bar(); + } + } else { + baz(); + } + + // THIS IS BAD! DON'T DO THIS: + if(foo){ + while(quux){ + bar(); + } + }else{ + baz(); + } + +- Exactly one space in between binary arithmetic, logical, and + comparison operators and their operands, except for the . and -> + operators. Examples:: + + // This is good: + int x = a + b * (c - d); + if (x != 0 && a > 7) { + SerialUSB.println(x); + } + + // THIS IS BAD! + int x = a+b*(c-d); + if (x!=0 && a>7) { + SerialUSB.println(x); + } + + // This is good: + uint32 adc_data = ADC1_BASE->DR; + SerialUSB.println(adc_data); + + // THIS IS BAD! + uint32 adc_data = ADC1_BASE -> DR; + SerialUSB . println(adc_data); + +- No space between a unary operator and its operand. Examples:: + + // Good: + x++; + + // BAD! + x ++; + + // Good: + y = -x; + + // BAD! + y = - x; + +- If you need to break up a long line: + + * Prefer to break up long expressions after a binary operator. Example:: + + // Good: + if (some_really_long_conditional_wow_this_really_goes_on_forever || + maybe_something_else_could_happen_too) { + ... + } + + // BAD! + if (some_really_long_conditional_wow_this_really_goes_on_forever + || maybe_something_else_could_happen_too) { + ... + } + + * When breaking up a function's arguments over multiple lines, align + the arguments on subsequent lines with the first argument. + Example:: + + // Good: + return_type value_i_got = function_with_a_really_long_name(argument1, + argument2, + argument3); + + // BAD! + return_type value_i_got = function_with_a_really_long_name(argument1, + argument2, + argument3); + + // BAD! + return_type value_i_got = function_with_a_really_long_name(argument1, + argument2, + argument3); + +- In function invocations, no space in between the function name and + the opening parenthesis. Example:: + + // Good: + SerialUSB.println("Hello, world!"); + + // BAD! + SerialUSB.println ("Hello, world!"); + +- Don't indent C code within a conditionally-compiled ``extern "C"`` + block. Example:: + + // Good: + #ifdef __cplusplus + extern "C"{ + #endif + + void some_c_function(void); + + #ifdef __cplusplus + } // extern "C" + #endif + + // BAD! + #ifdef __cplusplus + extern "C"{ + #endif + + void some_c_function(void); + + #ifdef __cplusplus + } // extern "C" + #endif + +.. highlight:: scheme + + Emacs does the "bad" behavior by default, which can be very + annoying. You can turn this off with:: + + (defun c-mode-inextern-lang-hook () + (setcdr (assq 'inextern-lang c-offsets-alist) '-)) + (add-hook 'c-mode-hook c-mode-inextern-lang-hook) + +Comments +-------- + +.. highlight:: c++ + +- Multi-line comments are pretty flexible. Any of these is fine:: + + /* Comment starts here. + * Continued lines have a '*' before them. + * The comment can end after the last line. + */ + + /* Comment starts here. + * The comment can end on the same line. */ + + /* + * You can also place a newline after the opening "/*". + */ + +- Doxygen comments are multi-line comments that begin with ``/**`` + instead. + +- Single-line comments on the same line are ``//`` in C++. (That's OK + in C as well). + +- Single-line comments on their own source line should be ``/* */`` in + C, but can also be ``//`` in C++. (This isn't of great importance). + In Emacs, you can use M-; (comment-dwim), and it'll Do What You + Mean. + +Braces +------ + +- Mostly 1TBS: + + http://en.wikipedia.org/wiki/Indent_style#Variant:_1TBS + + The only difference is that the opening brace of a function's + definition occurs exactly one space character after the closing + parenthesis in that function's parameter list. Example:: + + void func(void) { + ... + } + +Naming conventions +------------------ + +There's always a fight about upper and lower case vs. underscores. +We'll handle this as follows. + +- First, ``Dont_Mix_Like_This``, because ``It_Looks_Really_Ugly``, ok? + [There's been some debate about this, and some exceptions are + already grandfathered in, so in order to settle it, let's call this + a "recommendation" instead of "requirement".] + +- Variables: Use underscores to separate words in C identifiers:: + + int some_example_name; + + User-facing C++ variables should be camel cased + (``thisIsAnExample``, ``boardPWMPins``, etc.), for consistency with + the Arduino style. It's probably a good idea for you to case + non-user facing C++ variables in the C style; this will help + disambiguate what's part of the Wirish API and what's not. + +- Classes: Pascal case. So ``ThisIsAClassName``, but ``thisIsNot``, + ``this_is_not``, and like I said, + ``Dont_You_DareTryANYTHING_STUPID``. + +- Functions: C functions are all lowercase, and words are separated by + underscores. C++ method names are camel cased. + +- Structs: Usually like variables (``adc_dev``, ``adc_reg_map``, + etc.), but it's not crucial. Don't feel obliged to put ``_t`` at + the end of the type name; we don't. + +- Macros and constants: all caps, separated by underscores. C++ + variables with the ``const`` qualifier generally aren't considered + "constants" for the purposes of this rule; i.e., they are cased + according to the rules for variables. We make an exception for + ``PIN_MAP``, because it's the central Wirish data structure. + +- foo.h gets ``#ifdef``\ 'ed to ``_FOO_H_``. + +- Acronyms: The case of letters in an acronym is determined by the + case of the first letter in the acronym, which is determined by + following the above rules. Examples:: + + // Good: + void usb_func() { ... } + void frob_usb_disc() { ... } + class SomethingUSB { + void usbInit(); + void initUSB(); + }; + + // BAD: + class BadUsb { ... }; // say "GoodUSB" instead + void swizzle_USB_disc() { ... } // say "swizzle_usb_disc" instead + +Documentation +------------- + +- You **must** document your code. At a bare minimum, this means + Doxygen comments on every user-facing function and type. + Additionally, you need to individually document the fields and + enumerator values of ``struct``\ s and ``enum``\ s. See any + register map type's definition for an example. + +- For libmaple proper, you don't need comments for each register bit + definition (for now). + +- Doxygen comments generally just belong on types, functions, + etc. that are part of the public user-facing API. This generally + means that if there's ReST documentation for it under docs/source/, + it needs Doxygen comments, and that ReST should use Breathe to pull + that Doxygen comment out. (For more info on this, see docs/README). + + There are some exceptions to this rule since Breathe isn't totally + mature yet and Sphinx's C++ domain is still in flux. In these + cases, document the code "manually" in ReST. + + This should be avoided if at all possible, since it creates a + maintenance burden of documenting things in two places at once, and + makes it easier for documentation to go stale. + + If you do have to document something manually, put a comment in the + source file informing future maintainers about it, so they'll pay + extra attention when making changes. + +- When adding peripheral support, it would be nice if you put + longer-form comments into the /notes/ directory, with a comment in + the corresponding .h file referring to it. See /libmaple/dac.h for + an example. + + This lets us keep the source files relatively free of "introductory" + material, while allowing new readers a convenient starting point. + These longer-form notes also have a habit of turning into + user-facing documentation. + +- For libmaple proper (the pure C library under libmaple/); the + convention is to document any user-facing function at the point where + it is defined. In particular, this means you should document an + externally-linked function defined in a .c file in that .c file, not + in the header file where it is declared to the user. + +General Formatting +------------------ + +- Keep it 80-column clean. That means Emacs says the largest column + number=79. You should turn on column number mode to help you out: + +.. highlight:: scheme + + (column-number-mode 1) + + You can get more help from lineker-mode: + + http://www.helsinki.fi/~sjpaavol/programs/lineker.el + + Just put lineker.el somewhere in your load-path, and: + + (require 'lineker) + (dolist (hook '(c-mode-hook c++-mode-hook)) + (add-hook hook (lambda () (lineker-mode 1)))) + +Language Features and Compiler Extensions +----------------------------------------- + +- In libmaple proper, aim for C99 compatibility. Some GCC extensions + are OK, but let's not go crazy. + +- If you'd like to get code into libmaple which uses a GCC extension + not already in use elsewhere, ask a LeafLabs developer (or another + one, if you are one) what they think about it first. + +- Explicitly approved GCC extensions: + + * asm volatile: + http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html + + * Nested functions: + http://gcc.gnu.org/onlinedocs/gcc/Nested-Functions.html + +- In wirish, generally be very conservative when using C++ features + that aren't part of C. We are forced to use C++ for Arduino + compatibility (and the general Arduino style of pretending that an + object is a library), but it's an angry beast, and we don't want to + provoke it. The mantra is "C with classes". + +- Explicitly approved C++ features: + + * Initializers that aren't constant; e.g. the ``gpio_dev*`` values + in a ``PIN_MAP``. + + * Default arguments: e.g., the timeout argument defaulting to 0 + (meaning to wait forever) in ``waitForButtonPress()``. + +- Explicitly forbidden C++ features: + + * Templates + +- C++ features that are conditionally allowed, but require explicit + approval from at least two libmaple developers (one of which may be + yourself): + + * Operator overloading: Never allowed when it's just for style. + Potentially allowed when you're implementing a class that models a + mathematical structure, and you'd like to implement + e.g. ``operator+()``. diff --git a/notes/coding_standard.txt b/notes/coding_standard.txt deleted file mode 100644 index 5b258f7..0000000 --- a/notes/coding_standard.txt +++ /dev/null @@ -1,284 +0,0 @@ -libmaple Coding Standards -========================= - -Author: Marti Bolivar (mbolivar@leaflabs.com) - -LeafLabs team members are required to follow these when producing new -code. Community contributors to libmaple are strongly encouraged to -do so; following these rules will greatly increase the probability -that your patches will be folded in. - -In general, do it like this unless there's a really good reason why -not. You being lazy doesn't count as a good reason. Most, if not -all, of these decisions are entirely arbitrary, but it's important for -readability that we be consistent. - -The file .dir-locals.el in the libmaple root directory already ensures -that many of these standards are followed by default in Emacs (but not -on Windows, where it would need to be named _dir_locals.el, and no -way, man). There's also some elisp scattered about this file which -will provide you additional help. - -Vim customizations to do the same thing would be nice (hint, hint)! - -License -------- - -- Put an MIT license at the beginning of the file (look at any of our - source files for an example). Copyright should go either to you or - to LeafLabs, LLC. - - Emacs: if you don't like seeing the license, you should use - elide-head (which will hide it for you). You can use the following: - - (require 'elide-head) - (setq programming-mode-hooks '(c-mode-hook c++-mode-hook)) - (add-to-list 'elide-head-headers-to-hide - '("The MIT License" . "DEALINGS IN\n [*] THE SOFTWARE")) - (add-to-list 'elide-head-headers-to-hide - '("The MIT License" . "DEALINGS IN THE\n...SOFTWARE")) - (dolist (hook programming-mode-hooks) - (add-hook hook (lambda () (elide-head)))) - -Whitespace/Indentation ----------------------- - -- 4 space indents. [Set in .dir-locals.el] - -- Unix newlines. [Some exceptions are currently grandfathered in; - these will go away in time.] - -- No tab characters. [Set in .dir-locals.el] - -- No trailing whitespace. For help getting this (and no tab - characters) done automatically in Emacs, you can use this: - - http://github.com/mbolivar/code-fascism - - I hear tell you can get something similar in vim; ask around, I - guess. - -- Files end in exactly one newline. [The presence of a newline at EOF - is already done by `c-require-final-newline' in recent versions of - Emacs.] - -- Exactly two newlines separate source paragraphs (you do separate - your code into paragraphs, don't you?). - -- The first line in a function is non-blank. - -- Don't indent C code within a conditionally-compiled extern "C" - block. Emacs does this by default, which can be very annoying; you - can turn this behavior off with - - (defun c-mode-inextern-lang-hook () - (setcdr (assq 'inextern-lang c-offsets-alist) '-)) - - (add-hook 'c-mode-hook c-mode-inextern-lang-hook) - -Comments --------- - -- Multi-line comments are pretty flexible. Any of these is fine: - - /* Comment starts here. - * Continued lines have a '*' before them. - * The comment can end after the last line. - */ - - /* Comment starts here. - * The comment can end on the same line. */ - - /* - * You can also place a newline after the opening "/*". - */ - -- Doxygen comments are multi-line comments that begin with /** instead. - -- Single-line comments on the same line are // in C++. (That's OK in C - as well). - -- Single-line comments on their own source line should be /* */ in C, - but can also be // in C++. In Emacs, you can use M-; - (comment-dwim), and it'll Do What You Mean. This isn't of great - importance. - -Braces ------- - -- Mostly 1TBS: - - http://en.wikipedia.org/wiki/Indent_style#Variant:_1TBS - - The only difference is that the opening brace of a function's - definition occurs exactly one space character after the closing - parenthesis in that function's parameter list. Example: - - void func(void) { - ... - } - -Naming conventions ------------------- - -There's always a fight about upper and lower case vs. underscores. -We'll handle this as follows. - -- First, Dont_Mix_Like_This, because It_Looks_Really_Ugly, ok? - [There's been some debate about this, and some exceptions are - already grandfathered in, so in order to settle it, let's call this - a "recommendation" instead of "requirement".] - -- Variables: Use underscores to separate words in C identifiers: - - int some_example_name; - - User-facing C++ variables should be camel cased (thisIsAnExample, - boardPWMPins, etc.), for consistency with the Arduino style. It's - probably a good idea for you to case non-user facing C++ variables - in the C style; this will help disambiguate what's part of the - Wirish API and what's not. - -- Classes: Pascal case. So ThisIsAClassName, but thisIsNot, - this_is_not, and like I said, Dont_You_DareTryANYTHING_STUPID. - -- Functions: C functions are all lowercase, and words are separated by - underscores. C++ method names are camel cased. - -- Structs: Usually like variables (adc_dev, adc_reg_map, etc.), but - it's not crucial. Don't feel obliged to put "_t" at the end of the - type name; we don't. - -- Macros and constants: all caps, separated by underscores. C++ - variables with the "const" qualifier generally aren't considered - "constants" for the purposes of this rule; i.e., they are cased - according to the rules for variables. We make an exception for - PIN_MAP, because it's the central Wirish data structure. - -- foo.h gets #ifdef'ed to _FOO_H_. - -- Acronyms: The case of letters in an acronym is determined by the - case of the first letter in the acronym, which is determined by - following the above rules. Examples: - - void usb_func() { ... } - - void frob_usb_disc() { ... } - - class SomethingUSB { - void usbInit(); - void initUSB(); - }; - - DON'T do this: - - class BadUsb { ... }; // say "GoodUSB" instead - - void swizzle_USB_disc() { ... } // say "swizzle_usb_disc" instead - -Documentation -------------- - -- You must document your code. At a bare minimum, this means Doxygen - comments on every user-facing function and type. Additionally, you - need to individually document the fields and enumerator values of - structs and enums. See any register map type's definition for an - example. - -- For libmaple proper, you don't need comments for each register bit - definition (for now). - -- Doxygen comments generally just belong on types, functions, - etc. that are part of the public user-facing API. This generally - means that if there's ReST documentation for it under docs/source/, - it needs Doxygen comments, and that ReST should use Breathe to pull - that Doxygen comment out. (For more info on this, see docs/README). - - There are some exceptions to this rule since Breathe isn't totally - mature yet and Sphinx's C++ domain is still in flux. In these - cases, document the code "manually" in ReST. - - This should be avoided if at all possible, since it creates a - maintenance burden of documenting things in two places at once, and - makes it easier for documentation to go stale. - - If you do have to document something manually, put a comment in the - source file informing future maintainers about it, so they'll pay - extra attention when making changes. - -- For complicated peripherals, it would be nice if you put longer-form - comments into the libmaple notes/ directory, with a comment in the - corresponding .h file referring to it. See libmaple/dac.h for an - example. - - This lets us keep the source files relatively clean while still - allowing new readers to have a starting point. These longer-form - notes also have a habit of turning into user-facing documentation. - -- For libmaple proper (the pure C library under libmaple/); the - convention is to document any user-facing function at the point where - it is defined. In particular, this means you should document an - externally-linked function defined in a .c file in that .c file, not - in the header file where it is declared to the user. - -General Formatting ------------------- - -- Keep it 80-column clean. That means Emacs says the largest column - number=79. You should turn on column number mode to help you out: - - (column-number-mode 1) - - You can get more help from lineker-mode: - - http://www.helsinki.fi/~sjpaavol/programs/lineker.el - - Just put lineker.el somewhere in your load-path, and: - - (require 'lineker) - (dolist (hook '(c-mode-hook c++-mode-hook)) - (add-hook hook (lambda () (lineker-mode 1)))) - -Language Features and Compiler Extensions ------------------------------------------ - -- In libmaple proper, aim for C99 compatibility. Some GCC extensions - are OK, but let's not go crazy. - -- If you'd like to get code into libmaple which uses a GCC extension - not already in use elsewhere, ask a LeafLabs developer (or another - one, if you are one) what they think about it first. - -- Explicitly approved GCC extensions: - - * asm volatile: - http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html - - * Nested functions: - http://gcc.gnu.org/onlinedocs/gcc/Nested-Functions.html - -- In wirish, generally be very conservative when using C++ features - that aren't part of C. We are forced to use C++ for Arduino - compatibility (and the general Arduino style of pretending that an - object is a library), but it's an angry beast, and we don't want to - provoke it. The mantra is "C with classes". - -- Explicitly approved C++ features: - - * Initializers that aren't constant; e.g. the gpio_dev* values in - PIN_MAPs. - - * Default arguments: e.g., the timeout argument defaulting to 0 - (meaning to wait forever) in waitForButtonPress(). - -- Explicitly forbidden C++ features: - - * Templates - -- C++ features that are conditionally allowed, but require explicit - approval from at least two libmaple developers (one of which may be - yourself): - - * Operator overloading: Never allowed when it's just for style. - Potentially allowed when you're implementing a class that models a - mathematical structure, and you'd like to implement e.g. operator+(). -- cgit v1.2.3 From be4f7904584da06a5971616034dd3839e433edf8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 11 Apr 2011 12:05:37 -0400 Subject: Coding standard tweaks. It's mostly ready for inclusion in the main body of documentation. --- notes/coding_standard.rst | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'notes') diff --git a/notes/coding_standard.rst b/notes/coding_standard.rst index 1deed03..ced946d 100644 --- a/notes/coding_standard.rst +++ b/notes/coding_standard.rst @@ -21,6 +21,9 @@ scattered about this file which will provide you additional help. Vim customizations to do the same thing would be nice (hint, hint)! +.. contents:: Contents + :local: + License ------- @@ -94,8 +97,8 @@ Whitespace/Indentation } - Exactly one space in between binary arithmetic, logical, and - comparison operators and their operands, except for the . and -> - operators. Examples:: + comparison operators and their operands. This doesn't apply to the + . and -> operators. Examples:: // This is good: int x = a + b * (c - d); -- cgit v1.2.3 From d74098913a9ff210b3f53e6881a38c864892c6af Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Apr 2011 22:23:01 -0400 Subject: DMA checkpoint; dma_attach_interrupt() is broken. Simple USART receiver to SRAM buffer demo partially working. Interrupting when buffer is full fails mysteriously. GDB thinks we ended up in an STM32 reserved exception. --- examples/test-usart-dma.cpp | 127 +++++++++++++ libmaple/dma.c | 397 ++++++++++++++++++++++++++++++--------- libmaple/dma.h | 445 ++++++++++++++++++++++++++++++++++++++------ libmaple/nvic.h | 1 + notes/dma.txt | 99 ++++++++++ 5 files changed, 921 insertions(+), 148 deletions(-) create mode 100644 examples/test-usart-dma.cpp create mode 100644 notes/dma.txt (limited to 'notes') diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp new file mode 100644 index 0000000..b9c03f1 --- /dev/null +++ b/examples/test-usart-dma.cpp @@ -0,0 +1,127 @@ +/** + * @file test-usart-dma.cpp + * @author Marti Bolivar + * + * Simple test of DMA used with a USART receiver. + * + * Configures a USART receiver for use with DMA. Received bytes are + * placed into a buffer, with an interrupt firing when the buffer is + * full. At that point, the USART transmitter will print the contents + * of the byte buffer. The buffer is continually filled and refilled + * in this manner. + * + * This example isn't very robust; don't use it in production. In + * particular, since the buffer keeps filling (DMA_CIRC_MODE is set), + * if you keep typing after filling the buffer, you'll overwrite + * earlier bytes; this may happen before those earlier bytes are done + * printing. + * + * This code is released into the public domain. + */ + +#include "dma.h" +#include "usart.h" +#include "gpio.h" + +#include "wirish.h" + +#define BAUD 9600 + +#define USART USART2 +#define USART_HWSER Serial2 +#define USART_DMA_DEV DMA1 +#define USART_RX_DMA_CHANNEL DMA_CH6 +#define USART_TX BOARD_USART2_TX_PIN +#define USART_RX BOARD_USART2_RX_PIN + +#define BUF_SIZE 8 +uint8 rx_buf[BUF_SIZE]; + +dma_irq_cause irq_cause; + +__io uint32 irq_fired = 0; + +void init_usart(void); +void init_dma_xfer(void); +void rx_dma_irq(void); + +void setup(void) { + pinMode(BOARD_LED_PIN, OUTPUT); + + init_dma_xfer(); + init_usart(); +} + +void loop(void) { + toggleLED(); + delay(100); + + dma_channel_reg_map *ch_regs = dma_channel_regs(USART_DMA_DEV, + USART_RX_DMA_CHANNEL); + if (irq_fired) { + USART_HWSER.println("** IRQ **"); + while (true) + ; + } + USART_HWSER.print("["); + USART_HWSER.print(millis()); + USART_HWSER.print("]\tISR bits: 0x"); + uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); + USART_HWSER.print((int32)isr_bits, HEX); + USART_HWSER.print("\tCCR: 0x"); + USART_HWSER.print((int64)ch_regs->CCR, HEX); + USART_HWSER.print("\tCNDTR: 0x"); + USART_HWSER.print((int64)ch_regs->CNDTR, HEX); + USART_HWSER.print("\tBuffer contents: "); + for (int i = 0; i < BUF_SIZE; i++) { + USART_HWSER.print('\''); + USART_HWSER.print(rx_buf[i]); + USART_HWSER.print('\''); + if (i < BUF_SIZE - 1) USART_HWSER.print(", "); + } + USART_HWSER.println(); + if (isr_bits == 0x7) { + USART_HWSER.println("** Clearing ISR bits."); + dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); + } + + irq_fired = 0; +} + +/* Configure USART receiver for use with DMA */ +void init_usart(void) { + USART_HWSER.begin(BAUD); + USART->regs->CR3 = USART_CR3_DMAR; +} + +/* Configure DMA transmission */ +void init_dma_xfer(void) { + dma_init(USART_DMA_DEV); + dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL, + &USART->regs->DR, DMA_SIZE_8BITS, + rx_buf, DMA_SIZE_8BITS, + (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_TRNS_CMPLT + )); + dma_set_num_transfers(USART_DMA_DEV, USART_RX_DMA_CHANNEL, BUF_SIZE); + // Currently not working: + // dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_CHANNEL, rx_dma_irq); + dma_enable(USART_DMA_DEV, USART_RX_DMA_CHANNEL); +} + +void rx_dma_irq(void) { +} + +// Force init to be called *first*, i.e. before static object allocation. +// Otherwise, statically allocated objects that need libmaple may fail. +__attribute__((constructor)) void premain() { + init(); +} + +int main(void) { + setup(); + + while (true) { + loop(); + } + return 0; +} diff --git a/libmaple/dma.c b/libmaple/dma.c index c71e52c..6ddabcc 100644 --- a/libmaple/dma.c +++ b/libmaple/dma.c @@ -23,126 +23,351 @@ *****************************************************************************/ /** - * @file dma.c - * - * @brief Direct Memory Access peripheral support + * @file dma.c + * @author Marti Bolivar ; + * Original implementation by Michael Hope + * @brief Direct Memory Access peripheral support */ -#include "libmaple.h" #include "dma.h" -#include "rcc.h" -#include "nvic.h" - -#define DMA_EN BIT(0) - -typedef struct dma_regs { - uint32 CCR; - uint32 CNDTR; - uint32 CPAR; - uint32 CMAR; -} dma_regs; - -typedef struct DMAChannel { - void (*handler)(void); - uint32 irq_line; -} DMAChannel; - -volatile static DMAChannel dma_channels[] = { - { .handler = NULL, .irq_line = NVIC_DMA_CH1 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH2 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH3 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH4 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH5 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH6 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH7 } +#include "bitband.h" +#include "util.h" + +/* + * Devices + */ + +static dma_dev dma1 = { + .regs = DMA1_BASE, + .clk_id = RCC_DMA1, + .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH2 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH3 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH4 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH5 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH6 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH7 }} +}; +dma_dev *DMA1 = &dma1; + +#ifdef STM32_HIGH_DENSITY +static dma_dev dma2 = { + .regs = DMA2_BASE, + .clk_id = RCC_DMA2, + .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH2 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH3 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }} /* !@#$ */ }; +dma_dev *DMA2 = &dma2; +#endif -/** Get the base address of the given channel, asserting and returning - * NULL on illegal +/* + * Convenience routines */ -static dma_regs *dma_get_regs(uint8 channel) { - if (channel >= 1 && channel <= 7) { - return (dma_regs *)(DMA1_CCR1 + DMA_CHANNEL_STRIDE * (channel-1)); - } else { - ASSERT(0); - return NULL; - } + +/** + * @brief Initialize a DMA device. + * @param dev Device to initialize. + */ +void dma_init(dma_dev *dev) { + rcc_clk_enable(dev->clk_id); } -/* Zero-based indexing */ -static inline void dispatch_handler(uint8 channel_idx) { - ASSERT(dma_channels[channel_idx].handler); - if (dma_channels[channel_idx].handler) { - (dma_channels[channel_idx].handler)(); - } +/** + * @brief Set up a DMA transfer. + * + * The channel will be disabled before being reconfigured. The + * transfer will have low priority by default. You may choose another + * priority before the transfer begins using dma_set_priority(), as + * well as performing any other configuration you desire. When the + * channel is configured to your liking, enable it using dma_enable(). + * + * @param dev DMA device. + * @param channel DMA channel. + * @param peripheral_address Base address of peripheral data register + * involved in the transfer. + * @param peripheral_size Peripheral data transfer size. + * @param memory_address Base memory address involved in the transfer. + * @param memory_size Memory data transfer size. + * @param mode Logical OR of dma_mode_flags + * @sideeffect Disables the given DMA channel. + * @see dma_xfer_size + * @see dma_mode_flags + * @see dma_set_num_transfers() + * @see dma_set_priority() + * @see dma_attach_interrupt() + * @see dma_enable() + */ +void dma_setup_transfer(dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode) { + dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel); + + dma_disable(dev, channel); /* can't write to CMAR/CPAR otherwise */ + channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode; + channel_regs->CMAR = (uint32)memory_address; + channel_regs->CPAR = (uint32)peripheral_address; +} + +/** + * @brief Set the number of data to be transferred on a DMA channel. + * + * You may not call this function while the channel is enabled. + * + * @param dev DMA device + * @param channel Channel through which the transfer occurs. + * @param num_transfers + */ +void dma_set_num_transfers(dma_dev *dev, + dma_channel channel, + uint16 num_transfers) { + dma_channel_reg_map *channel_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + channel_regs = dma_channel_regs(dev, channel); + channel_regs->CNDTR = num_transfers; } -void __irq_dma1_channel1(void) { - dispatch_handler(0); +/** + * @brief Set the priority of a DMA transfer. + * + * You may not call this function while the channel is enabled. + * + * @param dev DMA device + * @param channel DMA channel + * @param priority priority to set. + */ +void dma_set_priority(dma_dev *dev, + dma_channel channel, + dma_priority priority) { + dma_channel_reg_map *channel_regs; + uint32 ccr; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + channel_regs = dma_channel_regs(dev, channel); + ccr = channel_regs->CCR; + ccr &= ~DMA_CCR_PL; + ccr |= priority; + channel_regs->CCR = ccr; } -void __irq_dma1_channel2(void) { - dispatch_handler(1); +/** + * @brief Attach an interrupt to a DMA transfer. + * + * Interrupts are enabled using appropriate mode flags in + * dma_setup_transfer(). + * + * @param dev DMA device + * @param channel Channel to attach handler to + * @param handler Interrupt handler to call when channel interrupt fires. + * @see dma_setup_transfer() + * @see dma_get_irq_cause() + * @see dma_detach_interrupt() + */ +void dma_attach_interrupt(dma_dev *dev, + dma_channel channel, + void (*handler)(void)) { + dev->handlers[channel - 1].handler = handler; + nvic_irq_enable(dev->handlers[channel - 1].irq_line); } -void __irq_dma2_channel3(void) { - dispatch_handler(2); +/** + * @brief Detach a DMA transfer interrupt handler. + * + * After calling this function, the given channel's interrupts will be + * disabled. + * + * @param dev DMA device + * @param channel Channel whose handler to detach + * @sideffect Clears interrupt enable bits in the channel's CCR register. + * @see dma_attach_interrupt() + */ +void dma_detach_interrupt(dma_dev *dev, dma_channel channel) { + /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */ + dma_channel_regs(dev, channel)->CCR &= ~0xF; + dev->handlers[channel - 1].handler = NULL; } -void __irq_dma2_channel4(void) { - dispatch_handler(3); +/** + * @brief Discover the reason why a DMA interrupt was called. + * + * You may only call this function within an attached interrupt + * handler for the given channel. + * + * This function resets the internal DMA register state which encodes + * the cause of the interrupt; consequently, it can only be called + * once per interrupt handler invocation. + * + * @brief dev DMA device + * @brief channel Channel whose interrupt is being handled. + * @return Reason why the interrupt fired. + * @sideeffect Clears channel status flags in dev->regs->ISR. + * @see dma_attach_interrupt() + * @see dma_irq_cause + */ +dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) { + uint8 status_bits = dma_get_isr_bits(dev, channel); + + /* If the channel global interrupt flag is cleared, then + * something's very wrong. */ + ASSERT(status_bits & BIT(0)); + + dma_clear_isr_bits(dev, channel); + + /* ISR flags get set even if the corresponding interrupt enable + * bits in the channel's configuration register are cleared, so we + * can't use a switch here. + * + * Don't change the order of these if statements. */ + if (status_bits & BIT(3)) { + return DMA_TRANSFER_ERROR; + } else if (status_bits & BIT(1)) { + return DMA_TRANSFER_COMPLETE; + } else if (status_bits & BIT(2)) { + return DMA_TRANSFER_HALF_COMPLETE; + } else if (status_bits & BIT(0)) { + /* Shouldn't happen (unless someone messed up an IFCR write). */ + throb(); + } +#if DEBUG_LEVEL < DEBUG_ALL + else { + /* We shouldn't have been called, but the debug level is too + * low for the above ASSERT() to have had any effect. In + * order to fail fast, mimic the DMA controller's behavior + * when an error occurs. */ + dma_disable(dev, channel); + return DMA_TRANSFER_ERROR; + } +#endif } -void __irq_dma2_channel5(void) { - dispatch_handler(4); +/** + * @brief Enable a DMA channel. + * @param dev DMA device + * @param channel Channel to enable + */ +void dma_enable(dma_dev *dev, dma_channel channel) { + dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); + bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1); } -void __irq_dma2_channel6(void) { - dispatch_handler(5); +/** + * @brief Disable a DMA channel. + * @param dev DMA device + * @param channel Channel to disable + */ +void dma_disable(dma_dev *dev, dma_channel channel) { + dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); + bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0); } -void __irq_dma2_channel7(void) { - dispatch_handler(6); +/** + * @brief Set the base memory address where data will be read from or + * written to. + * + * You must not call this function while the channel is enabled. + * + * If the DMA memory size is 16 bits, the address is automatically + * aligned to a half-word. If the DMA memory size is 32 bits, the + * address is aligned to a word. + * + * @param dev DMA Device + * @param channel Channel whose base memory address to set. + */ +void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) { + dma_channel_reg_map *chan_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + chan_regs = dma_channel_regs(dev, channel); + chan_regs->CMAR = (uint32)addr; } -void dma_init(uint8 channel, volatile void *paddr, - dma_transfer_size psize, dma_transfer_size msize, - int mode) { - volatile dma_regs *regs = dma_get_regs(channel); +/** + * @brief Set the base peripheral address where data will be read from + * or written to. + * + * You must not call this function while the channel is enabled. + * + * If the DMA peripheral size is 16 bits, the address is automatically + * aligned to a half-word. If the DMA peripheral size is 32 bits, the + * address is aligned to a word. + * + * @param dev DMA Device + * @param channel Channel whose peripheral data register base address to set. + */ +void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) { + dma_channel_reg_map *chan_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); - if (regs != NULL) { - rcc_clk_enable(RCC_DMA1); + chan_regs = dma_channel_regs(dev, channel); + chan_regs->CPAR = (uint32)addr; +} - regs->CCR = ((0 << 12) /* Low priority */ - | (msize << 10) - | (psize << 8) - | (0 << 0) /* Disabled (until started) */ - | mode); +/* + * IRQ handlers + */ - regs->CPAR = (uint32)paddr; +static inline void dispatch_handler(dma_dev *dev, dma_channel channel) { + void (*handler)(void) = dev->handlers[channel - 1].handler; + if (handler) { + handler(); + dma_clear_isr_bits(dev, channel); /* in case handler doesn't */ } } -void dma_start(uint8 channel, volatile void *buffer, uint16 count) { - volatile dma_regs *regs = dma_get_regs(channel); +void __irq_dma_channel1(void) { + dispatch_handler(DMA1, DMA_CH1); +} - if (regs != NULL) { - regs->CCR &= ~DMA_EN; /* CMAR may not be written with EN set */ - regs->CMAR = (uint32)buffer; - regs->CNDTR = count; +void __irq_dma_channel2(void) { + dispatch_handler(DMA1, DMA_CH2); +} - regs->CCR |= DMA_EN; - } +void __irq_dma_channel3(void) { + dispatch_handler(DMA1, DMA_CH3); } -void dma_attach_interrupt(uint8 channel, voidFuncPtr handler) { - channel--; /* 1-based -> 0-based indexing */ - dma_channels[channel].handler = handler; - nvic_irq_enable(dma_channels[channel].irq_line); +void __irq_dma_channel4(void) { + dispatch_handler(DMA1, DMA_CH4); +} + +void __irq_dma_channel5(void) { + dispatch_handler(DMA1, DMA_CH5); +} + +void __irq_dma_channel6(void) { + dispatch_handler(DMA1, DMA_CH6); +} + +void __irq_dma_channel7(void) { + dispatch_handler(DMA1, DMA_CH7); +} + +#ifdef STM32_HIGH_DENSITY +void __irq_dma2_channel1(void) { + dispatch_handler(DMA2, DMA_CH1); +} + +void __irq_dma2_channel2(void) { + dispatch_handler(DMA2, DMA_CH2); +} + +void __irq_dma2_channel3(void) { + dispatch_handler(DMA2, DMA_CH3); } -void dma_detach_interrupt(uint8 channel) { - channel--; - nvic_irq_disable(dma_channels[channel].irq_line); - dma_channels[channel].handler = NULL; +void __irq_dma2_channel4_5(void) { + dispatch_handler(DMA2, DMA_CH4); + dispatch_handler(DMA2, DMA_CH5); } +#endif diff --git a/libmaple/dma.h b/libmaple/dma.h index 3417f02..c763672 100644 --- a/libmaple/dma.h +++ b/libmaple/dma.h @@ -23,97 +23,418 @@ *****************************************************************************/ /** - * @file dma.h + * @file dma.h * - * @brief Direct Memory Access peripheral support + * @author Marti Bolivar ; + * Original implementation by Michael Hope * - * TODO: add DMA2 support for high-density devices. + * @brief Direct Memory Access peripheral support + */ + +/* + * See /notes/dma.txt for more information. */ #ifndef _DMA_H_ #define _DMA_H_ #include "libmaple_types.h" +#include "rcc.h" +#include "nvic.h" #ifdef __cplusplus extern "C"{ #endif -/** Base address of the DMA1 peripheral */ -#define DMA1_BASE 0x40020000 -/** DMA Interrupt Status Register */ -#define DMA1_ISR (DMA1_BASE + 0x00) -/** DMA Interrupt Flag Clear Register */ -#define DMA1_IFCR (DMA1_BASE + 0x04) -/** DMA Channel Configuration Register */ -#define DMA1_CCR1 (DMA1_BASE + 0x08) -/** DMA Channel Number of Data Register */ -#define DMA1_CNDTR1 (DMA1_BASE + 0x0C) -/** DMA Channel Peripheral Address Register */ -#define DMA1_CPAR1 (DMA1_BASE + 0x10) -/** DMA Channel Memory Address Register */ -#define DMA1_CMAR1 (DMA1_BASE + 0x14) -/** Spacing between channel registers */ -#define DMA_CHANNEL_STRIDE 20 +/* + * Register maps + */ + +/** + * @brief DMA register map type. + * + * Note that DMA controller 2 (register map base pointer DMA2_BASE) + * only supports channels 1--5. + */ +typedef struct dma_reg_map { + __io uint32 ISR; /**< Interrupt status register */ + __io uint32 IFCR; /**< Interrupt flag clear register */ + __io uint32 CCR1; /**< Channel 1 configuration register */ + __io uint32 CNDTR1; /**< Channel 1 number of data register */ + __io uint32 CPAR1; /**< Channel 1 peripheral address register */ + __io uint32 CMAR1; /**< Channel 1 memory address register */ + const uint32 RESERVED1; /**< Reserved. */ + __io uint32 CCR2; /**< Channel 2 configuration register */ + __io uint32 CNDTR2; /**< Channel 2 number of data register */ + __io uint32 CPAR2; /**< Channel 2 peripheral address register */ + __io uint32 CMAR2; /**< Channel 2 memory address register */ + const uint32 RESERVED2; /**< Reserved. */ + __io uint32 CCR3; /**< Channel 3 configuration register */ + __io uint32 CNDTR3; /**< Channel 3 number of data register */ + __io uint32 CPAR3; /**< Channel 3 peripheral address register */ + __io uint32 CMAR3; /**< Channel 3 memory address register */ + const uint32 RESERVED3; /**< Reserved. */ + __io uint32 CCR4; /**< Channel 4 configuration register */ + __io uint32 CNDTR4; /**< Channel 4 number of data register */ + __io uint32 CPAR4; /**< Channel 4 peripheral address register */ + __io uint32 CMAR4; /**< Channel 4 memory address register */ + const uint32 RESERVED4; /**< Reserved. */ + __io uint32 CCR5; /**< Channel 5 configuration register */ + __io uint32 CNDTR5; /**< Channel 5 number of data register */ + __io uint32 CPAR5; /**< Channel 5 peripheral address register */ + __io uint32 CMAR5; /**< Channel 5 memory address register */ + const uint32 RESERVED5; /**< Reserved. */ + __io uint32 CCR6; /**< Channel 6 configuration register */ + __io uint32 CNDTR6; /**< Channel 6 number of data register */ + __io uint32 CPAR6; /**< Channel 6 peripheral address register */ + __io uint32 CMAR6; /**< Channel 6 memory address register */ + const uint32 RESERVED6; /**< Reserved. */ + __io uint32 CCR7; /**< Channel 7 configuration register */ + __io uint32 CNDTR7; /**< Channel 7 number of data register */ + __io uint32 CPAR7; /**< Channel 7 peripheral address register */ + __io uint32 CMAR7; /**< Channel 7 memory address register */ + const uint32 RESERVED7; /**< Reserved. */ +} dma_reg_map; + +/** DMA controller 1 register map base pointer */ +#define DMA1_BASE ((struct dma_reg_map*)0x40020000) + +#ifdef STM32_HIGH_DENSITY +/** DMA controller 2 register map base pointer */ +#define DMA2_BASE ((struct dma_reg_map*)0x40020400) +#endif + +/* + * Register bit definitions + */ + +/* Interrupt status register */ + +#define DMA_ISR_TEIF7_BIT 27 +#define DMA_ISR_HTIF7_BIT 26 +#define DMA_ISR_TCIF7_BIT 25 +#define DMA_ISR_GIF7_BIT 24 +#define DMA_ISR_TEIF6_BIT 23 +#define DMA_ISR_HTIF6_BIT 22 +#define DMA_ISR_TCIF6_BIT 21 +#define DMA_ISR_GIF6_BIT 20 +#define DMA_ISR_TEIF5_BIT 19 +#define DMA_ISR_HTIF5_BIT 18 +#define DMA_ISR_TCIF5_BIT 17 +#define DMA_ISR_GIF5_BIT 16 +#define DMA_ISR_TEIF4_BIT 15 +#define DMA_ISR_HTIF4_BIT 14 +#define DMA_ISR_TCIF4_BIT 13 +#define DMA_ISR_GIF4_BIT 12 +#define DMA_ISR_TEIF3_BIT 11 +#define DMA_ISR_HTIF3_BIT 10 +#define DMA_ISR_TCIF3_BIT 9 +#define DMA_ISR_GIF3_BIT 8 +#define DMA_ISR_TEIF2_BIT 7 +#define DMA_ISR_HTIF2_BIT 6 +#define DMA_ISR_TCIF2_BIT 5 +#define DMA_ISR_GIF2_BIT 4 +#define DMA_ISR_TEIF1_BIT 3 +#define DMA_ISR_HTIF1_BIT 2 +#define DMA_ISR_TCIF1_BIT 1 +#define DMA_ISR_GIF1_BIT 0 + +#define DMA_ISR_TEIF7 BIT(DMA_ISR_TEIF7_BIT) +#define DMA_ISR_HTIF7 BIT(DMA_ISR_HTIF7_BIT) +#define DMA_ISR_TCIF7 BIT(DMA_ISR_TCIF7_BIT) +#define DMA_ISR_GIF7 BIT(DMA_ISR_GIF7_BIT) +#define DMA_ISR_TEIF6 BIT(DMA_ISR_TEIF6_BIT) +#define DMA_ISR_HTIF6 BIT(DMA_ISR_HTIF6_BIT) +#define DMA_ISR_TCIF6 BIT(DMA_ISR_TCIF6_BIT) +#define DMA_ISR_GIF6 BIT(DMA_ISR_GIF6_BIT) +#define DMA_ISR_TEIF5 BIT(DMA_ISR_TEIF5_BIT) +#define DMA_ISR_HTIF5 BIT(DMA_ISR_HTIF5_BIT) +#define DMA_ISR_TCIF5 BIT(DMA_ISR_TCIF5_BIT) +#define DMA_ISR_GIF5 BIT(DMA_ISR_GIF5_BIT) +#define DMA_ISR_TEIF4 BIT(DMA_ISR_TEIF4_BIT) +#define DMA_ISR_HTIF4 BIT(DMA_ISR_HTIF4_BIT) +#define DMA_ISR_TCIF4 BIT(DMA_ISR_TCIF4_BIT) +#define DMA_ISR_GIF4 BIT(DMA_ISR_GIF4_BIT) +#define DMA_ISR_TEIF3 BIT(DMA_ISR_TEIF3_BIT) +#define DMA_ISR_HTIF3 BIT(DMA_ISR_HTIF3_BIT) +#define DMA_ISR_TCIF3 BIT(DMA_ISR_TCIF3_BIT) +#define DMA_ISR_GIF3 BIT(DMA_ISR_GIF3_BIT) +#define DMA_ISR_TEIF2 BIT(DMA_ISR_TEIF2_BIT) +#define DMA_ISR_HTIF2 BIT(DMA_ISR_HTIF2_BIT) +#define DMA_ISR_TCIF2 BIT(DMA_ISR_TCIF2_BIT) +#define DMA_ISR_GIF2 BIT(DMA_ISR_GIF2_BIT) +#define DMA_ISR_TEIF1 BIT(DMA_ISR_TEIF1_BIT) +#define DMA_ISR_HTIF1 BIT(DMA_ISR_HTIF1_BIT) +#define DMA_ISR_TCIF1 BIT(DMA_ISR_TCIF1_BIT) +#define DMA_ISR_GIF1 BIT(DMA_ISR_GIF1_BIT) + +/* Interrupt flag clear register */ + +#define DMA_IFCR_CTEIF7_BIT 27 +#define DMA_IFCR_CHTIF7_BIT 26 +#define DMA_IFCR_CTCIF7_BIT 25 +#define DMA_IFCR_CGIF7_BIT 24 +#define DMA_IFCR_CTEIF6_BIT 23 +#define DMA_IFCR_CHTIF6_BIT 22 +#define DMA_IFCR_CTCIF6_BIT 21 +#define DMA_IFCR_CGIF6_BIT 20 +#define DMA_IFCR_CTEIF5_BIT 19 +#define DMA_IFCR_CHTIF5_BIT 18 +#define DMA_IFCR_CTCIF5_BIT 17 +#define DMA_IFCR_CGIF5_BIT 16 +#define DMA_IFCR_CTEIF4_BIT 15 +#define DMA_IFCR_CHTIF4_BIT 14 +#define DMA_IFCR_CTCIF4_BIT 13 +#define DMA_IFCR_CGIF4_BIT 12 +#define DMA_IFCR_CTEIF3_BIT 11 +#define DMA_IFCR_CHTIF3_BIT 10 +#define DMA_IFCR_CTCIF3_BIT 9 +#define DMA_IFCR_CGIF3_BIT 8 +#define DMA_IFCR_CTEIF2_BIT 7 +#define DMA_IFCR_CHTIF2_BIT 6 +#define DMA_IFCR_CTCIF2_BIT 5 +#define DMA_IFCR_CGIF2_BIT 4 +#define DMA_IFCR_CTEIF1_BIT 3 +#define DMA_IFCR_CHTIF1_BIT 2 +#define DMA_IFCR_CTCIF1_BIT 1 +#define DMA_IFCR_CGIF1_BIT 0 + +#define DMA_IFCR_CTEIF7 BIT(DMA_IFCR_CTEIF7_BIT) +#define DMA_IFCR_CHTIF7 BIT(DMA_IFCR_CHTIF7_BIT) +#define DMA_IFCR_CTCIF7 BIT(DMA_IFCR_CTCIF7_BIT) +#define DMA_IFCR_CGIF7 BIT(DMA_IFCR_CGIF7_BIT) +#define DMA_IFCR_CTEIF6 BIT(DMA_IFCR_CTEIF6_BIT) +#define DMA_IFCR_CHTIF6 BIT(DMA_IFCR_CHTIF6_BIT) +#define DMA_IFCR_CTCIF6 BIT(DMA_IFCR_CTCIF6_BIT) +#define DMA_IFCR_CGIF6 BIT(DMA_IFCR_CGIF6_BIT) +#define DMA_IFCR_CTEIF5 BIT(DMA_IFCR_CTEIF5_BIT) +#define DMA_IFCR_CHTIF5 BIT(DMA_IFCR_CHTIF5_BIT) +#define DMA_IFCR_CTCIF5 BIT(DMA_IFCR_CTCIF5_BIT) +#define DMA_IFCR_CGIF5 BIT(DMA_IFCR_CGIF5_BIT) +#define DMA_IFCR_CTEIF4 BIT(DMA_IFCR_CTEIF4_BIT) +#define DMA_IFCR_CHTIF4 BIT(DMA_IFCR_CHTIF4_BIT) +#define DMA_IFCR_CTCIF4 BIT(DMA_IFCR_CTCIF4_BIT) +#define DMA_IFCR_CGIF4 BIT(DMA_IFCR_CGIF4_BIT) +#define DMA_IFCR_CTEIF3 BIT(DMA_IFCR_CTEIF3_BIT) +#define DMA_IFCR_CHTIF3 BIT(DMA_IFCR_CHTIF3_BIT) +#define DMA_IFCR_CTCIF3 BIT(DMA_IFCR_CTCIF3_BIT) +#define DMA_IFCR_CGIF3 BIT(DMA_IFCR_CGIF3_BIT) +#define DMA_IFCR_CTEIF2 BIT(DMA_IFCR_CTEIF2_BIT) +#define DMA_IFCR_CHTIF2 BIT(DMA_IFCR_CHTIF2_BIT) +#define DMA_IFCR_CTCIF2 BIT(DMA_IFCR_CTCIF2_BIT) +#define DMA_IFCR_CGIF2 BIT(DMA_IFCR_CGIF2_BIT) +#define DMA_IFCR_CTEIF1 BIT(DMA_IFCR_CTEIF1_BIT) +#define DMA_IFCR_CHTIF1 BIT(DMA_IFCR_CHTIF1_BIT) +#define DMA_IFCR_CTCIF1 BIT(DMA_IFCR_CTCIF1_BIT) +#define DMA_IFCR_CGIF1 BIT(DMA_IFCR_CGIF1_BIT) + +/* Channel configuration register */ + +#define DMA_CCR_MEM2MEM_BIT 14 +#define DMA_CCR_MINC_BIT 7 +#define DMA_CCR_PINC_BIT 6 +#define DMA_CCR_CIRC_BIT 5 +#define DMA_CCR_DIR_BIT 4 +#define DMA_CCR_TEIE_BIT 3 +#define DMA_CCR_HTIE_BIT 2 +#define DMA_CCR_TCIE_BIT 1 +#define DMA_CCR_EN_BIT 0 + +#define DMA_CCR_MEM2MEM BIT(DMA_CCR_MEM2MEM_BIT) +#define DMA_CCR_PL (0x3 << 12) +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +#define DMA_CCR_MSIZE (0x3 << 10) +#define DMA_CCR_MSIZE_8BITS (0x0 << 10) +#define DMA_CCR_MSIZE_16BITS (0x1 << 10) +#define DMA_CCR_MSIZE_32BITS (0x2 << 10) +#define DMA_CCR_PSIZE (0x3 << 8) +#define DMA_CCR_PSIZE_8BITS (0x0 << 8) +#define DMA_CCR_PSIZE_16BITS (0x1 << 8) +#define DMA_CCR_PSIZE_32BITS (0x2 << 8) +#define DMA_CCR_MINC BIT(DMA_CCR_MINC_BIT) +#define DMA_CCR_PINC BIT(DMA_CCR_PINC_BIT) +#define DMA_CCR_CIRC BIT(DMA_CCR_CIRC_BIT) +#define DMA_CCR_DIR BIT(DMA_CCR_DIR_BIT) +#define DMA_CCR_TEIE BIT(DMA_CCR_TEIE_BIT) +#define DMA_CCR_HTIE BIT(DMA_CCR_HTIE_BIT) +#define DMA_CCR_TCIE BIT(DMA_CCR_TCIE_BIT) +#define DMA_CCR_EN BIT(DMA_CCR_EN_BIT) + +/* + * Devices + */ + +/** Encapsulates state related to a DMA channel interrupt. */ +typedef struct dma_handler_config { + void (*handler)(void); + nvic_irq_num irq_line; +} dma_handler_config; + +/** DMA device type */ +typedef struct dma_dev { + dma_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< Clock ID */ + dma_handler_config handlers[]; /**< IRQ handlers and NVIC numbers. */ +} dma_dev; + +/** DMA1 device */ +extern dma_dev *DMA1; +#ifdef STM32_HIGH_DENSITY +/** DMA2 device */ +extern dma_dev *DMA2; +#endif + +/* + * Convenience functions + */ + +void dma_init(dma_dev *dev); /** Flags for DMA transfer configuration. */ typedef enum dma_mode_flags { - DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ - DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ - DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ - DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ - DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ - DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ - DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ + DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ + DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ + DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ + DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ + DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ + DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ + DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ + DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ } dma_mode_flags; /** Source and destination transfer sizes. */ -typedef enum dma_transfer_size { - DMA_SIZE_8BITS = 0, - DMA_SIZE_16BITS = 1, - DMA_SIZE_32BITS = 2 -} dma_transfer_size; +typedef enum dma_xfer_size { + DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ + DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ + DMA_SIZE_32BITS = 2 /**< 32-bit transfers */ +} dma_xfer_size; + +/** DMA channel */ +typedef enum dma_channel { + DMA_CH1 = 1, /**< Channel 1 */ + DMA_CH2 = 2, /**< Channel 2 */ + DMA_CH3 = 3, /**< Channel 3 */ + DMA_CH4 = 4, /**< Channel 4 */ + DMA_CH5 = 5, /**< Channel 5 */ + DMA_CH6 = 6, /**< Channel 6 */ + DMA_CH7 = 7, /**< Channel 7 */ +} dma_channel; + +void dma_setup_transfer(dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode); + +void dma_set_num_transfers(dma_dev *dev, + dma_channel channel, + uint16 num_transfers); + +/** DMA transfer priority. */ +typedef enum dma_priority { + DMA_PRIORITY_LOW = DMA_CCR_PL_LOW, /**< Low priority */ + DMA_PRIORITY_MEDIUM = DMA_CCR_PL_MEDIUM, /**< Medium priority */ + DMA_PRIORITY_HIGH = DMA_CCR_PL_HIGH, /**< High priority */ + DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */ +} dma_priority; + +void dma_set_priority(dma_dev *dev, + dma_channel channel, + dma_priority priority); + +void dma_attach_interrupt(dma_dev *dev, + dma_channel channel, + void (*handler)(void)); +void dma_detach_interrupt(dma_dev *dev, dma_channel channel); + +/** + * Encodes the reason why a DMA interrupt was called. + * @see dma_get_irq_cause() + */ +typedef enum dma_irq_cause { + DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ + DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ + DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ +} dma_irq_cause; + +dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel); + +void dma_enable(dma_dev *dev, dma_channel channel); +void dma_disable(dma_dev *dev, dma_channel channel); + +void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address); +void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address); /** - * Initialize a DMA channel. If desired, attach an interrupt handler - * using dma_attach_interrupt(). Start the transfer using - * dma_start(). + * @brief DMA channel register map type. * - * @param channel the channel number (1..7) - * @param paddr address of the peripheral - * @param psize peripheral size - * @param msize memory size - * @param mode OR of the dma_mode_flags - * @see dma_mode_flags - * @see dma_attach_interrupt() - * @see dma_start() */ -void dma_init(uint8 channel, volatile void *paddr, - dma_transfer_size psize, dma_transfer_size msize, - int mode); + * Provides access to an individual channel's registers. + */ +typedef struct dma_channel_reg_map { + __io uint32 CCR; /**< Channel configuration register */ + __io uint32 CNDTR; /**< Channel number of data register */ + __io uint32 CPAR; /**< Channel peripheral address register */ + __io uint32 CMAR; /**< Channel memory address register */ +} dma_channel_reg_map; + +#define DMA_CHANNEL_NREGS 5 /** - * Begin a DMA transfer initialized with dma_init(). + * @brief Obtain a pointer to an individual DMA channel's registers. * - * @param channel Channel transfer to start. - * @param buffer Buffer to write to (unless DMA_FROM_MEM was set in - * mode argument to dma_init(), in which case, buffer - * to read from). This must be aligned with msize - * argument to dma_init(). - * @param count Number of elements to transfer. - * @see dma_init() */ -void dma_start(uint8 channel, volatile void *buffer, uint16 count); + * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. + * + * @param dev DMA device + * @param channel DMA channel whose channel register map to obtain. + */ +static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev, + dma_channel channel) { + __io uint32 *ccr1 = &dev->regs->CCR1; + return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1)); +} + +/** + * @brief Check if a DMA channel is enabled + * @param dev DMA device + * @param channel Channel whose enabled bit to check. + */ +static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) { + return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN); +} /** - * Attach an interrupt handler for the given DMA channel. - * @param channel DMA channel (1..7) - * @param handler Interrupt handler to attach - * @see voidFuncPtr */ -void dma_attach_interrupt(uint8 channel, voidFuncPtr handler); + * @brief Get the ISR status bits for a DMA channel. + * + * The bits are returned right-aligned, in the following order: + * transfer error flag, half-transfer flag, transfer complete flag, + * global interrupt flag. + * + * If you're attempting to figure out why a DMA interrupt fired; you + * may find dma_get_irq_cause() more convenient. + * + * @see dma_get_irq_cause(). + */ +static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) { + uint8 shift = (channel - 1) * 4; + return (dev->regs->ISR >> shift) & 0xF; +} /** - * Detach any handler associated with the given DMA channel. - * @param channel Channel whose interrupt handler to detach. */ -void dma_detach_interrupt(uint8 channel); + * @brief Clear the ISR status bits for a given DMA channel. + * + * If you're attempting to clean up after yourself in a DMA interrupt, + * you may find dma_get_irq_cause() more convenient. + * + * @see dma_get_irq_cause() + */ +static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) { + dev->regs->IFCR = BIT(4 * (channel - 1)); +} #ifdef __cplusplus } // extern "C" diff --git a/libmaple/nvic.h b/libmaple/nvic.h index df3461b..2e98c9f 100644 --- a/libmaple/nvic.h +++ b/libmaple/nvic.h @@ -31,6 +31,7 @@ #define _NVIC_H_ #include "libmaple_types.h" +#include "util.h" #ifdef __cplusplus extern "C"{ diff --git a/notes/dma.txt b/notes/dma.txt new file mode 100644 index 0000000..97b23a0 --- /dev/null +++ b/notes/dma.txt @@ -0,0 +1,99 @@ +DMA Notes +========= + +Medium-density devices have one DMA controller, DMA1. High-density +devices and up also have DMA2. DMA1 has 7 channels; DMA2 has 5. Each +channel multiplexes DMA requests from various peripherals, like so: + +Channel Capabilities +-------------------- + +DMA1: + + * Channel 1: ADC1, TIM2_CH3, TIM4_CH1 + * Channel 2: USART3_TX, TIM1_CH1, TIM2_UP, TIM3_CH3, SPI1_RX + * Channel 3: USART3_RX, TIM1_CH2, TIM3_CH4, TIM3_UP, SPI1_TX + * Channel 4: USART1_TX, TIM1_CH4, TIM1_TRIG, TIM1_COM, TIM4_CH2, + SPI2/I2S2_RX, I2C2_TX + * Channel 5: USART1_RX, TIM1_UP, TIM2_CH1, TIM4_CH3, + SPI2/I2S2_TX, I2C2_RX + * Channel 6: USART2_RX, TIM1_CH3, TIM3_CH1, TIM3_TRIG, I2C1_TX + * Channel 7: USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX + +DMA2: + + * Channel 1: TIM5_CH4, TIM5_TRIG, TIM8_CH3, TIM8_UP, SPI/I2S3_RX + * Channel 2: TIM8_CH4, TIM8_TRIG, TIM8_COM, TIM5_CH3, TIM5_UP, SPI/I2S3_TX + * Channel 3: TIM8_CH1, UART4_RX, TIM6_UP/DAC_CH1 + * Channel 4: TIM5_CH2, SDIO, TIM7_UP/DAC_CH2 + * Channel 5: ADC3, TIM8_CH2, TIM5_CH1, UART4_TX + +An example usage: via DMA1, channel 1, you can have ADC1 periodically +dump converted data into an array in memory. The DMA controller can +then interrupt you when the array is half-full and full, and if any +error occurred. + +Since channels are multiplexed in hardware, you can't simultaneously +use the same DMA channel to serve requests from two of its peripherals +at the same time. For example, if you are using DMA 1 channel 1 to +serve DMA requests from ADC1, you can't also serve requests from Timer +2 channel 3. + +Channel Priority +---------------- + +An arbiter prioritizes simultaneous channel DMA requests. Channel +priority levels are configurable (4 levels of priority). Ties within +a DMA controller are broken by choosing the lower channel number; +between the controllers, DMA1 has higher priority than DMA2. + +Interrupts +---------- + +You can cause an interrupt to fire once half the transfers are +complete, when all the transfers are complete, if an error occurs +during transfer, or any combination of the three. + +If an error occurs, the transfer is automatically disabled. + +Configuration +------------- + +In order to configure a DMA transfer for DMA controller n, channel x, +ST RM0008 says you should do the following: + + A. Set the peripheral register address in DMAn_BASE->CPARx. + B. Set the memory address in DMAn_BASE->CMARx. + C. Set the number of data to be transferred in DMAn_BASE->CNDTRx. + D. Set the channel priority via the PL bits in DMAn_BASE->CCRx. + E. Configure various other things (e.g. data transfer sizes, what + events cause channel interrupts) in DMAn_BASE->CCRx as desired. + F. Activate the channel by setting ENABLE bit in DMAn_BASE->CCRx. + +The channel will start serving DMA requests as soon as it's activated. + +The DMA library lets you accomplish these tasks as follows: + + **Setup transfer** + + Do (A), (B), and (E) using dma_setup_transfer(). + + This also does (D), but chooses the lowest priority by default. + + **Perform any other desired configuration** + + You can do (C) using dma_set_num_transfers(). + + You can do (D) using dma_set_priority(). + + You can attach interrupt handlers with dma_attach_interrupt(). + + **Activate the channel** + + Do (F) with dma_enable(). + +Once you're all done, you can dma_disable() the channel. If you +dma_detach_interrupt() an interrupt handler, the channel interrupts +will stop firing, but the transfer itself won't stop until it's done +(which never happens if you set the DMA_CIRC_MODE flag when you called +dma_setup_transfer()). -- cgit v1.2.3 From d3949203fe053249d35e0c4125f3ed21818e8c32 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 11 Apr 2011 23:46:44 -0400 Subject: Coding standard. --- notes/coding_standard.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'notes') diff --git a/notes/coding_standard.rst b/notes/coding_standard.rst index ced946d..b0fa91b 100644 --- a/notes/coding_standard.rst +++ b/notes/coding_standard.rst @@ -27,12 +27,12 @@ Vim customizations to do the same thing would be nice (hint, hint)! License ------- +.. highlight:: scheme + - Put an MIT license at the beginning of the file (look at any of our source files for an example). Copyright should go either to you or to LeafLabs, LLC. -.. highlight:: scheme - Emacs: if you don't like seeing the license, you should use elide-head (which will hide it for you). You can use the following:: -- cgit v1.2.3 From 08007e45924c15d4930f13c5f8e3bbe627c1a1bc Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 12 Apr 2011 17:25:12 -0400 Subject: Coding standard. Fixes for github .rst display. --- notes/coding_standard.rst | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'notes') diff --git a/notes/coding_standard.rst b/notes/coding_standard.rst index b0fa91b..f761db7 100644 --- a/notes/coding_standard.rst +++ b/notes/coding_standard.rst @@ -362,11 +362,11 @@ Documentation General Formatting ------------------ +.. highlight:: scheme + - Keep it 80-column clean. That means Emacs says the largest column number=79. You should turn on column number mode to help you out: -.. highlight:: scheme - (column-number-mode 1) You can get more help from lineker-mode: @@ -379,6 +379,8 @@ General Formatting (dolist (hook '(c-mode-hook c++-mode-hook)) (add-hook hook (lambda () (lineker-mode 1)))) +.. highlight:: cpp + Language Features and Compiler Extensions ----------------------------------------- @@ -391,10 +393,10 @@ Language Features and Compiler Extensions - Explicitly approved GCC extensions: - * asm volatile: + * ``asm volatile``: http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html - * Nested functions: + * ``Nested functions``: http://gcc.gnu.org/onlinedocs/gcc/Nested-Functions.html - In wirish, generally be very conservative when using C++ features -- cgit v1.2.3 From bf72983543f446026556e13f62d63aad2092f1ec Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 25 Apr 2011 18:53:42 -0400 Subject: Trivial pin-definitions.txt updates. No corrections made to the pin definitions themselves. --- notes/pin-definitions.txt | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'notes') diff --git a/notes/pin-definitions.txt b/notes/pin-definitions.txt index 71572ac..30f5056 100644 --- a/notes/pin-definitions.txt +++ b/notes/pin-definitions.txt @@ -3,11 +3,8 @@ Pin definitions by GPIO bank. Source: ST DOC ID 14611, Datasheet for STM32F103xC, STM32F103xD, STM32F103xE, Table 5, pp. 30--35. -Some peripherals and extra functionality with less/no libmaple -relevance (at time of writing) are given in "Other" following each -bank's main table. Non-default alternate functions are not listed. If -wirish will/does remap the pin's main function after reset, the main -function is listed under "Other". +Some additional peripheral GPIO information is given in the "Other" +section following each bank's main table. This document was prepared carefully and is believed to be correct, but the final arbiter of truth is the ST datasheet. -- cgit v1.2.3