From c122d16c71d2aa04baa8b4b5a5df7faed93240fb Mon Sep 17 00:00:00 2001
From: Marti Bolivar <mbolivar@leaflabs.com>
Date: Thu, 2 Feb 2012 07:01:41 -0500
Subject: RCC: Add new mechanism for configuring the main PLL.

The new style for configuring the PLL is to initialize
a (series-specific) struct rcc_pll_cfg, and pass a pointer to it to
rcc_configure_pll(). After that's done, you can use
rcc_turn_on_clk(RCC_CLK_PLL) to turn on the main PLL, and busy-wait
until rcc_is_clk_ready(RCC_CLK_PLL) is true to make sure the new
configuration took effect.

- libmaple/rcc.h:

  -- Add struct rcc_pll_cfg, which specifies a PLL configuration. This
     specifies a PLL source and a void pointer to series-specific PLL
     configuration data.

  -- Add rcc_configure_pll(), which takes a pointer to struct
     rcc_pll_cfg, and configures the main PLL. It's up to each series
     to define this function.

- stm32f1/rcc.h: Add struct stm32f1_rcc_pll_data, to store F1-specific
  PLL configuration state.

- stm32f1/rcc.c: Add an implementation for rcc_configure_pll().

- stm32f2/rcc.h: Add struct stm32f2_rcc_pll_data, to store F2-specific
  PLL configuration data.

- stm32f2/rcc.c: Add an implementation for rcc_configure_pll().

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
---
 libmaple/stm32f2/include/series/rcc.h | 66 +++++++++++++++++++++++------------
 1 file changed, 44 insertions(+), 22 deletions(-)

(limited to 'libmaple/stm32f2/include/series')

diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h
index 89fed1d..019bb3e 100644
--- a/libmaple/stm32f2/include/series/rcc.h
+++ b/libmaple/stm32f2/include/series/rcc.h
@@ -738,12 +738,30 @@ typedef struct rcc_reg_map {
 #define RCC_PLLI2SCFGR_PLLI2SN          (0x1FF << 6)
 
 /*
- * Other types
+ * Clock sources, domains, and peripheral clock IDs.
  */
 
-/*
- * Clock sources, domains, and peripheral clock IDs.
+/**
+ * @brief Available clock sources.
  */
+typedef enum rcc_clk {
+    RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL
+                                                       for I2S. */
+    RCC_CLK_PLL    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_PLLON_BIT), /**< Main PLL, clocked by
+                                                    HSI or HSE. */
+    RCC_CLK_HSE    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_HSEON_BIT), /**< High speed external. */
+    RCC_CLK_HSI    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_HSION_BIT), /**< High speed internal. */
+    RCC_CLK_LSE    = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) |
+                              RCC_BDCR_LSEON_BIT), /**< Low-speed external
+                                                    * (32.768 KHz). */
+    RCC_CLK_LSI    = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
+                              RCC_CSR_LSION_BIT), /**< Low-speed internal
+                                                   * (approximately 32 KHz). */
+} rcc_clk;
 
 /**
  * @brief Identifies bus and clock line for a peripheral or peripheral
@@ -915,27 +933,31 @@ typedef enum rcc_ahb_divider {
     RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512,
 } rcc_ahb_divider;
 
+/*
+ * Series-specific PLL configuration.
+ */
+
 /**
- * @brief Available clock sources.
+ * @brief STM32F2-specific PLL configuration values.
+ *
+ * Use this as the "data" field in a struct rcc_pll_cfg.
+ *
+ * @see struct rcc_pll_cfg.
  */
-typedef enum rcc_clk {
-    RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL
-                                                       for I2S. */
-    RCC_CLK_PLL    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_PLLON_BIT), /**< Main PLL, clocked by
-                                                    HSI or HSE. */
-    RCC_CLK_HSE    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_HSEON_BIT), /**< High speed external. */
-    RCC_CLK_HSI    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_HSION_BIT), /**< High speed internal. */
-    RCC_CLK_LSE    = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) |
-                              RCC_BDCR_LSEON_BIT), /**< Low-speed external
-                                                    * (32.768 KHz). */
-    RCC_CLK_LSI    = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
-                              RCC_CSR_LSION_BIT), /**< Low-speed internal
-                                                   * (approximately 32 KHz). */
-} rcc_clk;
+typedef struct stm32f2_rcc_pll_data {
+    uint8 pllq;      /**<
+                      * @brief PLLQ value.
+                      * Allowed values: 4, 5, ..., 15. */
+    uint8 pllp;      /**<
+                      * @brief PLLP value.
+                      * Allowed values: 2, 4, 6, 8. */
+    uint16 plln;     /**<
+                      * @brief PLLN value.
+                      * Allowed values: 192, 193, ..., 432. */
+    uint8 pllm;      /**<
+                      * @brief PLLM value.
+                      * Allowed values: 2, 3, ..., 63. */
+} stm32f2_rcc_pll_data;
 
 #ifdef __cplusplus
 }
-- 
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