From 4dc4d99fdddffdeb3e14e722e935c76c74ff9a15 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 27 Jan 2012 21:31:30 -0500 Subject: RCC: Clean up and sanitize interfaces across F1, F2 series. Additions: - rcc_switch_sysclk(): For changing the clock used as SYSCLK's source. - enum rcc_clk: One for each system and secondary clock source (e.g. HSE, LSE). These are defined on a per-series basis in each of the . - rcc_turn_on_clk(), rcc_turn_off_clk(), rcc_is_clk_ready(): For turning on system and secondary clock sources, and checking whether or not they're ready. Uses enum rcc_clk. Removals: - rcc_clk_init(): There's no way to port this to F2. Move it to the F1 header. This also means we can remove the empty implementation and enum rcc_pll_multiplier from the F2 RCC header, where it doesn't make any sense. Also fix up some includes, and rewrite rcc_clk_init() in terms of the new clock source management functions. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) (limited to 'libmaple/stm32f2/include/series') diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 1557f2d..89fed1d 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -722,7 +722,6 @@ typedef struct rcc_reg_map { /* Spread spectrum clock generation register */ - #define RCC_SSCGR_SSCGEN_BIT 31 #define RCC_SSCGR_SPREADSEL_BIT 30 @@ -742,6 +741,10 @@ typedef struct rcc_reg_map { * Other types */ +/* + * Clock sources, domains, and peripheral clock IDs. + */ + /** * @brief Identifies bus and clock line for a peripheral or peripheral * clock. @@ -819,10 +822,6 @@ typedef enum rcc_pllsrc { RCC_PLLSRC_HSE = RCC_PLLCFGR_PLLSRC, } rcc_pllsrc; -typedef enum rcc_pll_multiplier { /* TODO -- does this make sense anymore? */ - RCC_PLLMUL_XXX, -} rcc_pll_multiplier; - /** * @brief Peripheral clock domains. */ @@ -834,6 +833,10 @@ typedef enum rcc_clk_domain { RCC_AHB3, } rcc_clk_domain; +/* + * Prescalers and dividers. + */ + /** * @brief Prescaler identifiers. */ @@ -912,6 +915,28 @@ typedef enum rcc_ahb_divider { RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512, } rcc_ahb_divider; +/** + * @brief Available clock sources. + */ +typedef enum rcc_clk { + RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL + for I2S. */ + RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLON_BIT), /**< Main PLL, clocked by + HSI or HSE. */ + RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSEON_BIT), /**< High speed external. */ + RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSION_BIT), /**< High speed internal. */ + RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) | + RCC_BDCR_LSEON_BIT), /**< Low-speed external + * (32.768 KHz). */ + RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) | + RCC_CSR_LSION_BIT), /**< Low-speed internal + * (approximately 32 KHz). */ +} rcc_clk; + #ifdef __cplusplus } #endif -- cgit v1.2.3