From 12c351d0561d1f9d4e017bbd3f847906f93b0df7 Mon Sep 17 00:00:00 2001
From: bnewbold <bnewbold@robocracy.org>
Date: Wed, 25 Aug 2010 22:57:46 -0400
Subject: inital portability work

---
 libmaple/rcc.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 62 insertions(+), 13 deletions(-)

(limited to 'libmaple/rcc.h')

diff --git a/libmaple/rcc.h b/libmaple/rcc.h
index e6a28ea..b369f25 100644
--- a/libmaple/rcc.h
+++ b/libmaple/rcc.h
@@ -29,6 +29,48 @@
 #ifndef _RCC_H_
 #define _RCC_H_
 
+/* registers  */
+#define RCC_BASE               0x40021000
+#define RCC_CR                 (RCC_BASE + 0x0)
+#define RCC_CFGR               (RCC_BASE + 0x4)
+#define RCC_CIR                (RCC_BASE + 0x8)
+#define RCC_APB2RSTR           (RCC_BASE + 0xC)
+#define RCC_APB1RSTR           (RCC_BASE + 0x10)
+#define RCC_AHBENR             (RCC_BASE + 0x14)
+#define RCC_APB2ENR            (RCC_BASE + 0x18)
+#define RCC_APB1ENR            (RCC_BASE + 0x1C)
+#define RCC_BDCR               (RCC_BASE + 0x20)
+#define RCC_CSR                (RCC_BASE + 0x24)
+#define RCC_AHBSTR             (RCC_BASE + 0x28)
+#define RCC_CFGR2              (RCC_BASE + 0x2C)
+
+#define RCC_CFGR_USBPRE        (0x1 << 22)
+#define RCC_CFGR_ADCPRE        (0x3 << 14)
+#define RCC_CFGR_PPRE1         (0x7 << 8)
+#define RCC_CFGR_PPRE2         (0x7 << 11)
+#define RCC_CFGR_HPRE          (0xF << 4)
+#define RCC_CFGR_PLLSRC        (0x1 << 16)
+
+#define RCC_CFGR_SWS           (0x3 << 2)
+#define RCC_CFGR_SWS_PLL       (0x2 << 2)
+#define RCC_CFGR_SWS_HSE       (0x1 << 2)
+
+#define RCC_CFGR_SW            (0x3 << 0)
+#define RCC_CFGR_SW_PLL        (0x2 << 0)
+#define RCC_CFGR_SW_HSE        (0x1 << 0)
+
+/* CR status bits  */
+#define RCC_CR_HSEON           (0x1 << 16)
+#define RCC_CR_HSERDY          (0x1 << 17)
+#define RCC_CR_PLLON           (0x1 << 24)
+#define RCC_CR_PLLRDY          (0x1 << 25)
+
+#define RCC_WRITE_CFGR(val)    __write(RCC_CFGR, val)
+#define RCC_READ_CFGR()        __read(RCC_CFGR)
+
+#define RCC_WRITE_CR(val)      __write(RCC_CR, val)
+#define RCC_READ_CR()          __read(RCC_CR)
+
 /* sysclk source  */
 #define RCC_CLKSRC_HSI                          (0x0)
 #define RCC_CLKSRC_HSE                          (0x1)
@@ -87,36 +129,44 @@
 #define RCC_PLLMUL_15                           (0xD << 18)
 #define RCC_PLLMUL_16                           (0xE << 18)
 
-/* device numbers  */
+
+/* prescalers */
+enum {
+   RCC_PRESCALER_AHB,
+   RCC_PRESCALER_APB1,
+   RCC_PRESCALER_APB2,
+   RCC_PRESCALER_USB,
+   RCC_PRESCALER_ADC
+};
+
+// RCC Devices
 enum {
    RCC_GPIOA,
    RCC_GPIOB,
    RCC_GPIOC,
    RCC_GPIOD,
+   RCC_GPIOE,       // High-density devices only (Maple Native)
+   RCC_GPIOF,       // High-density devices only (Maple Native)
+   RCC_GPIOG,       // High-density devices only (Maple Native)
    RCC_AFIO,
    RCC_ADC1,
+   RCC_ADC2,
    RCC_USART1,
    RCC_USART2,
    RCC_USART3,
-   RCC_USART4,
-   RCC_USART5,
+   RCC_USART4,      // High-density devices only (Maple Native)
+   RCC_USART5,      // High-density devices only (Maple Native)
    RCC_TIMER1,
    RCC_TIMER2,
    RCC_TIMER3,
    RCC_TIMER4,
+   RCC_TIMER5,      // High-density devices only (Maple Native)
+   RCC_TIMER6,      // High-density devices only (Maple Native)
+   RCC_TIMER7,      // High-density devices only (Maple Native)
    RCC_SPI1,
    RCC_SPI2,
 };
 
-/* prescalers */
-enum {
-   RCC_PRESCALER_AHB,
-   RCC_PRESCALER_APB1,
-   RCC_PRESCALER_APB2,
-   RCC_PRESCALER_USB,
-   RCC_PRESCALER_ADC
-};
-
 
 void rcc_clk_init(uint32 sysclk_src, uint32 pll_src, uint32 pll_mul);
 void rcc_clk_enable(uint32 dev);
@@ -125,4 +175,3 @@ void rcc_set_prescaler(uint32 prescaler, uint32 divider);
 
 #endif
 
-
-- 
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