From f35c9f71385ba0629e1e3744d08da2cf442b3e9d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 4 May 2011 17:23:54 -0400 Subject: SPI fixups. Initial post-review changes based on thread here: https://github.com/leaflabs/libmaple/commit/77f707d7b87fce284945fc9fe21c824c18c4c93d#comments --- libmaple/spi.c | 75 ++++++++++++++++++--------------------------- libmaple/spi.h | 20 +++++------- wirish/comm/HardwareSPI.cpp | 33 ++++++-------------- wirish/comm/HardwareSPI.h | 2 +- 4 files changed, 47 insertions(+), 83 deletions(-) diff --git a/libmaple/spi.c b/libmaple/spi.c index 2fbc2ac..e58ae91 100644 --- a/libmaple/spi.c +++ b/libmaple/spi.c @@ -34,6 +34,8 @@ #include "spi.h" #include "bitband.h" +static void spi_reconfigure(spi_dev *dev, uint32 cr1_config); + /* * SPI devices */ @@ -75,28 +77,9 @@ void spi_init(spi_dev *dev) { } /** - * @brief Configure GPIO bit modes for use as a SPI bus master's pins. - * @param nss_dev NSS pin's GPIO device - * @param comm_dev SCK, MISO, MOSI pins' GPIO device - * @param nss_bit NSS pin's GPIO bit on nss_dev - * @param sck_bit SCK pin's GPIO bit on comm_dev - * @param miso_bit MISO pin's GPIO bit on comm_dev - * @param mosi_bit MOSI pin's GPIO bit on comm_dev - */ -void spi_master_gpio_cfg(gpio_dev *nss_dev, - gpio_dev *comm_dev, - uint8 nss_bit, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit) { - gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING); - gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP); -} - -/** - * @brief Configure GPIO bit modes for use as a SPI bus slave's pins. + * @brief Configure GPIO bit modes for use as a SPI port's pins. + * @param as_master If true, configure bits for use as a bus master. + * Otherwise, configure bits for use as slave. * @param nss_dev NSS pin's GPIO device * @param comm_dev SCK, MISO, MOSI pins' GPIO device * @param nss_bit NSS pin's GPIO bit on nss_dev @@ -104,20 +87,26 @@ void spi_master_gpio_cfg(gpio_dev *nss_dev, * @param miso_bit MISO pin's GPIO bit on comm_dev * @param mosi_bit MOSI pin's GPIO bit on comm_dev */ -void spi_slave_gpio_cfg(gpio_dev *nss_dev, - gpio_dev *comm_dev, - uint8 nss_bit, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit) { - gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING); - gpio_set_mode(comm_dev, sck_bit, GPIO_INPUT_FLOATING); - gpio_set_mode(comm_dev, miso_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(comm_dev, mosi_bit, GPIO_INPUT_FLOATING); +void spi_gpio_cfg(uint8 as_master, + gpio_dev *nss_dev, + uint8 nss_bit, + gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit) { + if (as_master) { + gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP); + } else { + gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(comm_dev, sck_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(comm_dev, miso_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(comm_dev, mosi_bit, GPIO_INPUT_FLOATING); + } } -static void spi_reconfigure(spi_dev *dev, uint32 cr1_config); - /** * @brief Configure and enable a SPI device as bus master. * @@ -154,23 +143,19 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) { * @brief Nonblocking SPI transmit. * @param dev SPI port to use for transmission * @param buf Buffer to transmit. The sizeof buf's elements are - * inferred from the dev's data frame format (i.e., are + * inferred from dev's data frame format (i.e., are * correctly treated as 8-bit or 16-bit quantities). * @param len Maximum number of elements to transmit. * @return Number of elements transmitted. */ uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) { - spi_reg_map *regs = dev->regs; uint32 txed = 0; - if (spi_dff(dev) == SPI_DFF_16_BIT) { - const uint8 *buf8 = (const uint8*)buf; - while ((regs->SR & SPI_SR_TXE) && (txed < len)) { - regs->DR = buf8[txed++]; - } - } else { - const uint16 *buf16 = (const uint16*)buf; - while ((regs->SR & SPI_SR_TXE) && (txed < len)) { - regs->DR = buf16[txed++]; + uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT; + while (spi_is_tx_empty(dev) && (txed < len)) { + if (byte_frame) { + dev->regs->DR = ((const uint8*)buf)[txed++]; + } else { + dev->regs->DR = ((const uint16*)buf)[txed++]; } } return txed; diff --git a/libmaple/spi.h b/libmaple/spi.h index e2820dd..5c8728f 100644 --- a/libmaple/spi.h +++ b/libmaple/spi.h @@ -222,19 +222,13 @@ extern spi_dev *SPI3; void spi_init(spi_dev *dev); -void spi_master_gpio_cfg(gpio_dev *nss_dev, - gpio_dev *comm_dev, - uint8 nss_bit, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit); - -void spi_slave_gpio_cfg(gpio_dev *nss_dev, - gpio_dev *comm_dev, - uint8 nss_bit, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit); +void spi_gpio_cfg(uint8 as_master, + gpio_dev *nss_dev, + uint8 nss_bit, + gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit); /** * @brief SPI mode configuration. diff --git a/wirish/comm/HardwareSPI.cpp b/wirish/comm/HardwareSPI.cpp index 1b36d21..54b7ab3 100644 --- a/wirish/comm/HardwareSPI.cpp +++ b/wirish/comm/HardwareSPI.cpp @@ -125,11 +125,10 @@ void HardwareSPI::read(uint8 *buf, uint32 len) { } void HardwareSPI::write(uint8 byte) { - uint8 buf[] = {byte}; - this->write(buf, 1); + this->write(&byte, 1); } -void HardwareSPI::write(uint8 *data, uint32 length) { +void HardwareSPI::write(const uint8 *data, uint32 length) { uint32 txed = 0; while (txed < length) { txed += spi_tx(this->spi_d, data + txed, length - txed); @@ -152,7 +151,6 @@ uint8 HardwareSPI::send(uint8 data) { uint8 HardwareSPI::send(uint8 *buf, uint32 len) { if (len == 0) { - ASSERT(0); return 0; } uint32 txed = 0; @@ -183,11 +181,6 @@ static void enable_device(spi_dev *dev, SPIFrequency freq, spi_cfg_flag endianness, spi_mode mode) { - if (freq >= MAX_SPI_FREQS) { - ASSERT(0); - return; - } - spi_baud_rate baud = determine_baud_rate(dev, freq); uint32 cfg_flags = (endianness | SPI_DFF_8_BIT | SPI_SW_SLAVE | (as_master ? SPI_SOFT_SS : 0)); @@ -261,21 +254,13 @@ static void configure_gpios(spi_dev *dev, bool as_master) { disable_pwm(misoi); disable_pwm(mosii); - if (as_master) { - spi_master_gpio_cfg(nssi->gpio_device, - scki->gpio_device, - nssi->gpio_bit, - scki->gpio_bit, - misoi->gpio_bit, - mosii->gpio_bit); - } else { - spi_slave_gpio_cfg(nssi->gpio_device, - scki->gpio_device, - nssi->gpio_bit, - scki->gpio_bit, - misoi->gpio_bit, - mosii->gpio_bit); - } + spi_gpio_cfg(as_master, + nssi->gpio_device, + nssi->gpio_bit, + scki->gpio_device, + scki->gpio_bit, + misoi->gpio_bit, + mosii->gpio_bit); } static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = { diff --git a/wirish/comm/HardwareSPI.h b/wirish/comm/HardwareSPI.h index 1b2a966..3a6def5 100644 --- a/wirish/comm/HardwareSPI.h +++ b/wirish/comm/HardwareSPI.h @@ -140,7 +140,7 @@ public: * @param buffer Bytes to transmit. * @param length Number of bytes in buffer to transmit. */ - void write(uint8 *buffer, uint32 length); + void write(const uint8 *buffer, uint32 length); /** * @brief Transmit a byte, then return the next unread byte. -- cgit v1.2.3