From 526d51aa2b83c7a73a2ecdba8525d2a0847e5587 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 15 Nov 2011 08:50:22 -0500 Subject: Tweak family-specific linker file layout. Move support/ld/stm32/f1/performance/vector_symbols.inc to support/ld/stm32/family/f1/performance/vector_symbols.inc Creating directory "family" under support/ld/stm32 will allow parallel directories (e.g. support/ld/stm32/mcu) to exist, which allows an eventual linker script cleanup to go much more smoothly. Signed-off-by: Marti Bolivar --- support/ld/stm32/f1/performance/vector_symbols.inc | 78 ---------------------- .../stm32/family/f1/performance/vector_symbols.inc | 78 ++++++++++++++++++++++ support/make/target-config.mk | 2 +- 3 files changed, 79 insertions(+), 79 deletions(-) delete mode 100644 support/ld/stm32/f1/performance/vector_symbols.inc create mode 100644 support/ld/stm32/family/f1/performance/vector_symbols.inc diff --git a/support/ld/stm32/f1/performance/vector_symbols.inc b/support/ld/stm32/f1/performance/vector_symbols.inc deleted file mode 100644 index f8519bb..0000000 --- a/support/ld/stm32/f1/performance/vector_symbols.inc +++ /dev/null @@ -1,78 +0,0 @@ -EXTERN(__msp_init) -EXTERN(__exc_reset) -EXTERN(__exc_nmi) -EXTERN(__exc_hardfault) -EXTERN(__exc_memmanage) -EXTERN(__exc_busfault) -EXTERN(__exc_usagefault) -EXTERN(__stm32reservedexception7) -EXTERN(__stm32reservedexception8) -EXTERN(__stm32reservedexception9) -EXTERN(__stm32reservedexception10) -EXTERN(__exc_svc) -EXTERN(__exc_debug_monitor) -EXTERN(__stm32reservedexception13) -EXTERN(__exc_pendsv) -EXTERN(__exc_systick) - -EXTERN(__irq_wwdg) -EXTERN(__irq_pvd) -EXTERN(__irq_tamper) -EXTERN(__irq_rtc) -EXTERN(__irq_flash) -EXTERN(__irq_rcc) -EXTERN(__irq_exti0) -EXTERN(__irq_exti1) -EXTERN(__irq_exti2) -EXTERN(__irq_exti3) -EXTERN(__irq_exti4) -EXTERN(__irq_dma1_channel1) -EXTERN(__irq_dma1_channel2) -EXTERN(__irq_dma1_channel3) -EXTERN(__irq_dma1_channel4) -EXTERN(__irq_dma1_channel5) -EXTERN(__irq_dma1_channel6) -EXTERN(__irq_dma1_channel7) -EXTERN(__irq_adc) -EXTERN(__irq_usb_hp_can_tx) -EXTERN(__irq_usb_lp_can_rx0) -EXTERN(__irq_can_rx1) -EXTERN(__irq_can_sce) -EXTERN(__irq_exti9_5) -EXTERN(__irq_tim1_brk) -EXTERN(__irq_tim1_up) -EXTERN(__irq_tim1_trg_com) -EXTERN(__irq_tim1_cc) -EXTERN(__irq_tim2) -EXTERN(__irq_tim3) -EXTERN(__irq_tim4) -EXTERN(__irq_i2c1_ev) -EXTERN(__irq_i2c1_er) -EXTERN(__irq_i2c2_ev) -EXTERN(__irq_i2c2_er) -EXTERN(__irq_spi1) -EXTERN(__irq_spi2) -EXTERN(__irq_usart1) -EXTERN(__irq_usart2) -EXTERN(__irq_usart3) -EXTERN(__irq_exti15_10) -EXTERN(__irq_rtcalarm) -EXTERN(__irq_usbwakeup) - -EXTERN(__irq_tim8_brk) -EXTERN(__irq_tim8_up) -EXTERN(__irq_tim8_trg_com) -EXTERN(__irq_tim8_cc) -EXTERN(__irq_adc3) -EXTERN(__irq_fsmc) -EXTERN(__irq_sdio) -EXTERN(__irq_tim5) -EXTERN(__irq_spi3) -EXTERN(__irq_uart4) -EXTERN(__irq_uart5) -EXTERN(__irq_tim6) -EXTERN(__irq_tim7) -EXTERN(__irq_dma2_channel1) -EXTERN(__irq_dma2_channel2) -EXTERN(__irq_dma2_channel3) -EXTERN(__irq_dma2_channel4_5) diff --git a/support/ld/stm32/family/f1/performance/vector_symbols.inc b/support/ld/stm32/family/f1/performance/vector_symbols.inc new file mode 100644 index 0000000..f8519bb --- /dev/null +++ b/support/ld/stm32/family/f1/performance/vector_symbols.inc @@ -0,0 +1,78 @@ +EXTERN(__msp_init) +EXTERN(__exc_reset) +EXTERN(__exc_nmi) +EXTERN(__exc_hardfault) +EXTERN(__exc_memmanage) +EXTERN(__exc_busfault) +EXTERN(__exc_usagefault) +EXTERN(__stm32reservedexception7) +EXTERN(__stm32reservedexception8) +EXTERN(__stm32reservedexception9) +EXTERN(__stm32reservedexception10) +EXTERN(__exc_svc) +EXTERN(__exc_debug_monitor) +EXTERN(__stm32reservedexception13) +EXTERN(__exc_pendsv) +EXTERN(__exc_systick) + +EXTERN(__irq_wwdg) +EXTERN(__irq_pvd) +EXTERN(__irq_tamper) +EXTERN(__irq_rtc) +EXTERN(__irq_flash) +EXTERN(__irq_rcc) +EXTERN(__irq_exti0) +EXTERN(__irq_exti1) +EXTERN(__irq_exti2) +EXTERN(__irq_exti3) +EXTERN(__irq_exti4) +EXTERN(__irq_dma1_channel1) +EXTERN(__irq_dma1_channel2) +EXTERN(__irq_dma1_channel3) +EXTERN(__irq_dma1_channel4) +EXTERN(__irq_dma1_channel5) +EXTERN(__irq_dma1_channel6) +EXTERN(__irq_dma1_channel7) +EXTERN(__irq_adc) +EXTERN(__irq_usb_hp_can_tx) +EXTERN(__irq_usb_lp_can_rx0) +EXTERN(__irq_can_rx1) +EXTERN(__irq_can_sce) +EXTERN(__irq_exti9_5) +EXTERN(__irq_tim1_brk) +EXTERN(__irq_tim1_up) +EXTERN(__irq_tim1_trg_com) +EXTERN(__irq_tim1_cc) +EXTERN(__irq_tim2) +EXTERN(__irq_tim3) +EXTERN(__irq_tim4) +EXTERN(__irq_i2c1_ev) +EXTERN(__irq_i2c1_er) +EXTERN(__irq_i2c2_ev) +EXTERN(__irq_i2c2_er) +EXTERN(__irq_spi1) +EXTERN(__irq_spi2) +EXTERN(__irq_usart1) +EXTERN(__irq_usart2) +EXTERN(__irq_usart3) +EXTERN(__irq_exti15_10) +EXTERN(__irq_rtcalarm) +EXTERN(__irq_usbwakeup) + +EXTERN(__irq_tim8_brk) +EXTERN(__irq_tim8_up) +EXTERN(__irq_tim8_trg_com) +EXTERN(__irq_tim8_cc) +EXTERN(__irq_adc3) +EXTERN(__irq_fsmc) +EXTERN(__irq_sdio) +EXTERN(__irq_tim5) +EXTERN(__irq_spi3) +EXTERN(__irq_uart4) +EXTERN(__irq_uart5) +EXTERN(__irq_tim6) +EXTERN(__irq_tim7) +EXTERN(__irq_dma2_channel1) +EXTERN(__irq_dma2_channel2) +EXTERN(__irq_dma2_channel3) +EXTERN(__irq_dma2_channel4_5) diff --git a/support/make/target-config.mk b/support/make/target-config.mk index 592e808..98fc4d0 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -56,7 +56,7 @@ endif # are the only ones we support at this time. If you add support for # STM32F1 connectivity line MCUs or other STM32 families, this section # will need to change. -LD_FAMILY_PATH := $(LDDIR)/stm32/f1/performance +LD_FAMILY_PATH := $(LDDIR)/stm32/family/f1/performance LIBMAPLE_MODULE_FAMILY := $(LIBMAPLE_PATH)/stm32f1 # Memory target-specific configuration values -- cgit v1.2.3 From f36fae273ec84ee2c53a33caa2dddea2d79db0da Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 15 Nov 2011 12:45:43 -0500 Subject: Move public headers to include directories; related cleanups. Move libmaple/*.h to (new) libmaple/include/libmaple/. The new accepted way to include a libmaple header foo.h is with: #include This is more polite in terms of the include namespace. It also allows us to e.g. implement the Arduino SPI library at all (which has header SPI.h; providing it was previously impossible on case-insensitive filesystems due to libmaple's spi.h). Similarly for Wirish. The old include style (#include "header.h") is now deprecated. libmaple/*.h: - Change include guard #defines from _FOO_H_ to _LIBMAPLE_FOO_H_. - Add license headers where they're missing - Add conditional extern "C" { ... } blocks where they're missing (they aren't always necessary, but we might was well do it against the future, while we're at it.). - Change includes from #include "foo.h" to #include . - Move includes after extern "C". - Remove extra trailing newlines Note that this doesn't include the headers under libmaple/usb/ or libmaple/usb/usb_lib. These will get fixed later. libmaple/*.c: - Change includes from #include "foo.h" to #include . Makefile: - Add I$(LIBMAPLE_PATH)/include/libmaple to GLOBAL_FLAGS. This allows for users (including Wirish) to migrate their code, but should go away ASAP, since it slows down compilation. Wirish: - Move wirish/**/*.h to (new) wirish/include/wirish/. This ignores the USB headers, which, as usual, are getting handled after everything else. - Similarly generify wirish/boards/ structure. For each supported board "foo", move wirish/boards/foo.h and wirish/boards/foo.cpp to wirish/boards/foo/include/board/board.h and wirish/boards/foo/board.cpp, respectively. Also remove the #ifdef hacks around the .cpp files. - wirish/rules.mk: put wirish/boards/foo/include in the include path (and add wirish/boards/foo/board.cpp to the list of sources to be compiled). This allows saying: #include instead of the hack currently in place. We can allow the user to override this setting later to make adding custom board definitions easier. - Disable -Werror in libmaple/rules.mk, as the current USB warnings don't let the olimex_stm32_h103 board compile. We can re-enable -Werror once we've moved the board-specific bits out of libmaple proper. libraries, examples: - Update includes accordingly. - Miscellaneous cosmetic fixups. Signed-off-by: Marti Bolivar --- Makefile | 7 + examples/blinky.cpp | 2 +- examples/debug-dtrrts.cpp | 9 +- examples/freertos-blinky.cpp | 2 +- examples/fsmc-stress-test.cpp | 6 +- examples/mini-exti-test.cpp | 2 +- examples/qa-slave-shield.cpp | 2 +- examples/spi_master.cpp | 2 +- examples/test-bkp.cpp | 6 +- examples/test-dac.cpp | 4 +- examples/test-fsmc.cpp | 4 +- examples/test-print.cpp | 2 +- examples/test-ring-buffer-insertion.cpp | 4 +- examples/test-serial-flush.cpp | 2 +- examples/test-serialusb.cpp | 6 +- examples/test-servo.cpp | 2 +- examples/test-session.cpp | 2 +- examples/test-spi-roundtrip.cpp | 2 +- examples/test-systick.cpp | 4 +- examples/test-timers.cpp | 4 +- examples/test-usart-dma.cpp | 8 +- examples/vga-leaf.cpp | 2 +- examples/vga-scope.cpp | 4 +- libmaple/adc.c | 6 +- libmaple/adc.h | 364 ------- libmaple/bitband.h | 120 --- libmaple/bkp.c | 8 +- libmaple/bkp.h | 166 ---- libmaple/dac.c | 6 +- libmaple/dac.h | 168 ---- libmaple/delay.h | 30 - libmaple/dma.c | 6 +- libmaple/dma.h | 453 --------- libmaple/exti.c | 8 +- libmaple/exti.h | 74 -- libmaple/flash.c | 6 +- libmaple/flash.h | 142 --- libmaple/fsmc.c | 4 +- libmaple/fsmc.h | 320 ------- libmaple/gpio.c | 4 +- libmaple/gpio.h | 527 ---------- libmaple/i2c.c | 15 +- libmaple/i2c.h | 348 ------- libmaple/include/libmaple/adc.h | 364 +++++++ libmaple/include/libmaple/bitband.h | 128 +++ libmaple/include/libmaple/bkp.h | 166 ++++ libmaple/include/libmaple/dac.h | 168 ++++ libmaple/include/libmaple/delay.h | 65 ++ libmaple/include/libmaple/dma.h | 453 +++++++++ libmaple/include/libmaple/exti.h | 74 ++ libmaple/include/libmaple/flash.h | 140 +++ libmaple/include/libmaple/fsmc.h | 316 ++++++ libmaple/include/libmaple/gpio.h | 526 ++++++++++ libmaple/include/libmaple/i2c.h | 348 +++++++ libmaple/include/libmaple/iwdg.h | 116 +++ libmaple/include/libmaple/libmaple.h | 57 ++ libmaple/include/libmaple/libmaple_types.h | 64 ++ libmaple/include/libmaple/nvic.h | 241 +++++ libmaple/include/libmaple/pwr.h | 90 ++ libmaple/include/libmaple/rcc.h | 570 +++++++++++ libmaple/include/libmaple/ring_buffer.h | 188 ++++ libmaple/include/libmaple/scb.h | 209 ++++ libmaple/include/libmaple/spi.h | 456 +++++++++ libmaple/include/libmaple/stm32.h | 199 ++++ libmaple/include/libmaple/systick.h | 116 +++ libmaple/include/libmaple/timer.h | 1010 +++++++++++++++++++ libmaple/include/libmaple/usart.h | 336 +++++++ libmaple/include/libmaple/usb.h | 82 ++ libmaple/include/libmaple/util.h | 111 +++ libmaple/iwdg.c | 2 +- libmaple/iwdg.h | 116 --- libmaple/libmaple.h | 50 - libmaple/libmaple_types.h | 57 -- libmaple/nvic.c | 6 +- libmaple/nvic.h | 241 ----- libmaple/pwr.c | 4 +- libmaple/pwr.h | 85 -- libmaple/rcc.c | 8 +- libmaple/rcc.h | 570 ----------- libmaple/ring_buffer.h | 189 ---- libmaple/rules.mk | 7 +- libmaple/scb.h | 201 ---- libmaple/spi.c | 4 +- libmaple/spi.h | 456 --------- libmaple/stm32.h | 191 ---- libmaple/syscalls.c | 2 +- libmaple/systick.c | 2 +- libmaple/systick.h | 117 --- libmaple/timer.c | 2 +- libmaple/timer.h | 1012 -------------------- libmaple/usart.c | 2 +- libmaple/usart.h | 336 ------- libmaple/usb.h | 82 -- libmaple/usb/usb_cdcacm.h | 4 +- libmaple/util.c | 12 +- libmaple/util.h | 111 --- libraries/FreeRTOS/MapleFreeRTOS.h | 2 +- libraries/LiquidCrystal/LiquidCrystal.cpp | 2 +- libraries/LiquidCrystal/LiquidCrystal.h | 4 +- libraries/Servo/Servo.cpp | 8 +- libraries/Servo/Servo.h | 10 +- libraries/Wire/Wire.cpp | 1 - libraries/Wire/Wire.h | 4 +- main.cpp.example | 2 +- wirish/HardwareTimer.cpp | 6 +- wirish/HardwareTimer.h | 331 ------- wirish/Print.cpp | 5 +- wirish/Print.h | 67 -- wirish/WProgram.h | 30 - wirish/bit_constants.h | 579 ----------- wirish/bits.h | 30 - wirish/boards.cpp | 18 +- wirish/boards.h | 155 --- wirish/boards/maple.cpp | 116 --- wirish/boards/maple.h | 92 -- wirish/boards/maple/board.cpp | 112 +++ wirish/boards/maple/include/board/board.h | 92 ++ wirish/boards/maple_RET6.cpp | 118 --- wirish/boards/maple_RET6.h | 91 -- wirish/boards/maple_RET6/board.cpp | 115 +++ wirish/boards/maple_RET6/include/board/board.h | 92 ++ wirish/boards/maple_mini.cpp | 106 -- wirish/boards/maple_mini.h | 76 -- wirish/boards/maple_mini/board.cpp | 103 ++ wirish/boards/maple_mini/include/board/board.h | 77 ++ wirish/boards/maple_native.cpp | 201 ---- wirish/boards/maple_native.h | 83 -- wirish/boards/maple_native/board.cpp | 197 ++++ wirish/boards/maple_native/include/board/board.h | 84 ++ wirish/boards/olimex_stm32_h103.cpp | 122 --- wirish/boards/olimex_stm32_h103.h | 92 -- wirish/boards/olimex_stm32_h103/board.cpp | 119 +++ .../boards/olimex_stm32_h103/include/board/board.h | 92 ++ wirish/comm/HardwareSPI.cpp | 12 +- wirish/comm/HardwareSPI.h | 223 ----- wirish/comm/HardwareSerial.cpp | 11 +- wirish/comm/HardwareSerial.h | 86 -- wirish/ext_interrupts.cpp | 8 +- wirish/ext_interrupts.h | 106 -- wirish/include/wirish/HardwareSPI.h | 222 +++++ wirish/include/wirish/HardwareSerial.h | 86 ++ wirish/include/wirish/HardwareTimer.h | 331 +++++++ wirish/include/wirish/Print.h | 67 ++ wirish/include/wirish/WProgram.h | 35 + wirish/include/wirish/bit_constants.h | 579 +++++++++++ wirish/include/wirish/bits.h | 35 + wirish/include/wirish/boards.h | 122 +++ wirish/include/wirish/ext_interrupts.h | 106 ++ wirish/include/wirish/io.h | 222 +++++ wirish/include/wirish/pwm.h | 57 ++ wirish/include/wirish/usb_serial.h | 64 ++ wirish/include/wirish/wirish.h | 71 ++ wirish/include/wirish/wirish_debug.h | 61 ++ wirish/include/wirish/wirish_math.h | 151 +++ wirish/include/wirish/wirish_time.h | 98 ++ wirish/include/wirish/wirish_types.h | 68 ++ wirish/io.h | 223 ----- wirish/pwm.cpp | 8 +- wirish/pwm.h | 57 -- wirish/rules.mk | 13 +- wirish/usb_serial.cpp | 7 +- wirish/usb_serial.h | 64 -- wirish/wirish.h | 71 -- wirish/wirish_analog.cpp | 6 +- wirish/wirish_debug.h | 61 -- wirish/wirish_digital.cpp | 10 +- wirish/wirish_math.cpp | 2 +- wirish/wirish_math.h | 151 --- wirish/wirish_shift.cpp | 2 +- wirish/wirish_time.cpp | 6 +- wirish/wirish_time.h | 98 -- wirish/wirish_types.h | 68 -- 172 files changed, 10231 insertions(+), 10196 deletions(-) delete mode 100644 libmaple/adc.h delete mode 100644 libmaple/bitband.h delete mode 100644 libmaple/bkp.h delete mode 100644 libmaple/dac.h delete mode 100644 libmaple/delay.h delete mode 100644 libmaple/dma.h delete mode 100644 libmaple/exti.h delete mode 100644 libmaple/flash.h delete mode 100644 libmaple/fsmc.h delete mode 100644 libmaple/gpio.h delete mode 100644 libmaple/i2c.h create mode 100644 libmaple/include/libmaple/adc.h create mode 100644 libmaple/include/libmaple/bitband.h create mode 100644 libmaple/include/libmaple/bkp.h create mode 100644 libmaple/include/libmaple/dac.h create mode 100644 libmaple/include/libmaple/delay.h create mode 100644 libmaple/include/libmaple/dma.h create mode 100644 libmaple/include/libmaple/exti.h create mode 100644 libmaple/include/libmaple/flash.h create mode 100644 libmaple/include/libmaple/fsmc.h create mode 100644 libmaple/include/libmaple/gpio.h create mode 100644 libmaple/include/libmaple/i2c.h create mode 100644 libmaple/include/libmaple/iwdg.h create mode 100644 libmaple/include/libmaple/libmaple.h create mode 100644 libmaple/include/libmaple/libmaple_types.h create mode 100644 libmaple/include/libmaple/nvic.h create mode 100644 libmaple/include/libmaple/pwr.h create mode 100644 libmaple/include/libmaple/rcc.h create mode 100644 libmaple/include/libmaple/ring_buffer.h create mode 100644 libmaple/include/libmaple/scb.h create mode 100644 libmaple/include/libmaple/spi.h create mode 100644 libmaple/include/libmaple/stm32.h create mode 100644 libmaple/include/libmaple/systick.h create mode 100644 libmaple/include/libmaple/timer.h create mode 100644 libmaple/include/libmaple/usart.h create mode 100644 libmaple/include/libmaple/usb.h create mode 100644 libmaple/include/libmaple/util.h delete mode 100644 libmaple/iwdg.h delete mode 100644 libmaple/libmaple.h delete mode 100644 libmaple/libmaple_types.h delete mode 100644 libmaple/nvic.h delete mode 100644 libmaple/pwr.h delete mode 100644 libmaple/rcc.h delete mode 100644 libmaple/ring_buffer.h delete mode 100644 libmaple/scb.h delete mode 100644 libmaple/spi.h delete mode 100644 libmaple/stm32.h delete mode 100644 libmaple/systick.h delete mode 100644 libmaple/timer.h delete mode 100644 libmaple/usart.h delete mode 100644 libmaple/usb.h delete mode 100644 libmaple/util.h delete mode 100644 wirish/HardwareTimer.h delete mode 100644 wirish/Print.h delete mode 100644 wirish/WProgram.h delete mode 100644 wirish/bit_constants.h delete mode 100644 wirish/bits.h delete mode 100644 wirish/boards.h delete mode 100644 wirish/boards/maple.cpp delete mode 100644 wirish/boards/maple.h create mode 100644 wirish/boards/maple/board.cpp create mode 100644 wirish/boards/maple/include/board/board.h delete mode 100644 wirish/boards/maple_RET6.cpp delete mode 100644 wirish/boards/maple_RET6.h create mode 100644 wirish/boards/maple_RET6/board.cpp create mode 100644 wirish/boards/maple_RET6/include/board/board.h delete mode 100644 wirish/boards/maple_mini.cpp delete mode 100644 wirish/boards/maple_mini.h create mode 100644 wirish/boards/maple_mini/board.cpp create mode 100644 wirish/boards/maple_mini/include/board/board.h delete mode 100644 wirish/boards/maple_native.cpp delete mode 100644 wirish/boards/maple_native.h create mode 100644 wirish/boards/maple_native/board.cpp create mode 100644 wirish/boards/maple_native/include/board/board.h delete mode 100644 wirish/boards/olimex_stm32_h103.cpp delete mode 100644 wirish/boards/olimex_stm32_h103.h create mode 100644 wirish/boards/olimex_stm32_h103/board.cpp create mode 100644 wirish/boards/olimex_stm32_h103/include/board/board.h delete mode 100644 wirish/comm/HardwareSPI.h delete mode 100644 wirish/comm/HardwareSerial.h delete mode 100644 wirish/ext_interrupts.h create mode 100644 wirish/include/wirish/HardwareSPI.h create mode 100644 wirish/include/wirish/HardwareSerial.h create mode 100644 wirish/include/wirish/HardwareTimer.h create mode 100644 wirish/include/wirish/Print.h create mode 100644 wirish/include/wirish/WProgram.h create mode 100644 wirish/include/wirish/bit_constants.h create mode 100644 wirish/include/wirish/bits.h create mode 100644 wirish/include/wirish/boards.h create mode 100644 wirish/include/wirish/ext_interrupts.h create mode 100644 wirish/include/wirish/io.h create mode 100644 wirish/include/wirish/pwm.h create mode 100644 wirish/include/wirish/usb_serial.h create mode 100644 wirish/include/wirish/wirish.h create mode 100644 wirish/include/wirish/wirish_debug.h create mode 100644 wirish/include/wirish/wirish_math.h create mode 100644 wirish/include/wirish/wirish_time.h create mode 100644 wirish/include/wirish/wirish_types.h delete mode 100644 wirish/io.h delete mode 100644 wirish/pwm.h delete mode 100644 wirish/usb_serial.h delete mode 100644 wirish/wirish.h delete mode 100644 wirish/wirish_debug.h delete mode 100644 wirish/wirish_math.h delete mode 100644 wirish/wirish_time.h delete mode 100644 wirish/wirish_types.h diff --git a/Makefile b/Makefile index 45b34da..c6a1e07 100644 --- a/Makefile +++ b/Makefile @@ -46,6 +46,13 @@ GLOBAL_FLAGS := -D$(VECT_BASE_ADDR) \ -DERROR_LED_PORT=$(ERROR_LED_PORT) \ -DERROR_LED_PIN=$(ERROR_LED_PIN) \ -D$(DENSITY) +# FIXME: the following allows for deprecated include style, e.g.: +# #include "libmaple.h" +# or +# #include "wirish.h" +# It slows compilation noticeably; remove after 1 release. +GLOBAL_FLAGS += -I$(LIBMAPLE_PATH)/include/libmaple \ + -I$(WIRISH_PATH)/include/wirish GLOBAL_CFLAGS := -Os -g3 -gdwarf-2 -mcpu=cortex-m3 -mthumb -march=armv7-m \ -nostdlib -ffunction-sections -fdata-sections \ -Wl,--gc-sections $(GLOBAL_FLAGS) diff --git a/examples/blinky.cpp b/examples/blinky.cpp index dd72514..fad71f8 100644 --- a/examples/blinky.cpp +++ b/examples/blinky.cpp @@ -1,6 +1,6 @@ // Blinks the built-in LED -#include "wirish.h" +#include void setup() { pinMode(BOARD_LED_PIN, OUTPUT); diff --git a/examples/debug-dtrrts.cpp b/examples/debug-dtrrts.cpp index 3829208..0286212 100644 --- a/examples/debug-dtrrts.cpp +++ b/examples/debug-dtrrts.cpp @@ -1,7 +1,7 @@ // Test sketch for figuring out DTR/RTS behavior on different platforms. -#include "wirish.h" -#include "usb.h" +#include +#include "usb_cdcacm.h" void setup() { /* Set up the LED to blink */ @@ -10,7 +10,6 @@ void setup() { /* Send a message out USART2 */ Serial2.begin(9600); Serial2.println("Debugging DTR/RTS..."); - } void loop() { @@ -18,9 +17,9 @@ void loop() { delay(100); Serial2.print("DTR: "); - Serial2.print(usbGetDTR(), DEC); + Serial2.print(usb_cdcacm_get_dtr(), DEC); Serial2.print("\tRTS: "); - Serial2.println(usbGetRTS(), DEC); + Serial2.println(usb_cdcacm_get_rts(), DEC); } // Force init to be called *first*, i.e. before static object allocation. diff --git a/examples/freertos-blinky.cpp b/examples/freertos-blinky.cpp index 6f82d71..2e7c7f7 100644 --- a/examples/freertos-blinky.cpp +++ b/examples/freertos-blinky.cpp @@ -1,4 +1,4 @@ -#include "wirish.h" +#include #include "libraries/FreeRTOS/MapleFreeRTOS.h" static void vLEDFlashTask(void *pvParameters) { diff --git a/examples/fsmc-stress-test.cpp b/examples/fsmc-stress-test.cpp index 509a02f..20d3fa7 100644 --- a/examples/fsmc-stress-test.cpp +++ b/examples/fsmc-stress-test.cpp @@ -12,9 +12,9 @@ #include #include -#include "wirish.h" -#include "rcc.h" -#include "fsmc.h" +#include +#include +#include // -- SRAM config ------------------------------------------------------------- diff --git a/examples/mini-exti-test.cpp b/examples/mini-exti-test.cpp index 84b323e..54a4dd0 100644 --- a/examples/mini-exti-test.cpp +++ b/examples/mini-exti-test.cpp @@ -10,7 +10,7 @@ #include #include -#include "wirish.h" +#include // test routines void run_exti_test(void); diff --git a/examples/qa-slave-shield.cpp b/examples/qa-slave-shield.cpp index 2da1c04..ec25e49 100644 --- a/examples/qa-slave-shield.cpp +++ b/examples/qa-slave-shield.cpp @@ -1,6 +1,6 @@ // Slave mode for Quality Assurance test -#include "wirish.h" +#include #define INTER_TOGGLE_DELAY_NORMAL 5 #define INTER_TOGGLE_DELAY_SLOW 80 diff --git a/examples/spi_master.cpp b/examples/spi_master.cpp index 100fc53..ea6c990 100644 --- a/examples/spi_master.cpp +++ b/examples/spi_master.cpp @@ -33,7 +33,7 @@ * Pin 10 is used as slave select. */ -#include "wirish.h" +#include #define NSS 10 diff --git a/examples/test-bkp.cpp b/examples/test-bkp.cpp index f5957b7..719cac7 100644 --- a/examples/test-bkp.cpp +++ b/examples/test-bkp.cpp @@ -1,8 +1,8 @@ #include // for snprintf() -#include "wirish.h" -#include "bkp.h" -#include "iwdg.h" +#include +#include +#include void print_bkp_contents(); void write_to_bkp(uint16 val); diff --git a/examples/test-dac.cpp b/examples/test-dac.cpp index 40ae5d5..af188cc 100644 --- a/examples/test-dac.cpp +++ b/examples/test-dac.cpp @@ -6,8 +6,8 @@ * This file is released into the public domain. */ -#include "wirish.h" -#include "dac.h" +#include +#include uint16 count = 0; diff --git a/examples/test-fsmc.cpp b/examples/test-fsmc.cpp index 22f6975..1621317 100644 --- a/examples/test-fsmc.cpp +++ b/examples/test-fsmc.cpp @@ -1,7 +1,7 @@ #include // for ptrdiff_t -#include "wirish.h" -#include "fsmc.h" +#include +#include #ifndef BOARD_maple_native #error "Sorry, this example only works on Maple Native." diff --git a/examples/test-print.cpp b/examples/test-print.cpp index 5477512..bdc1894 100644 --- a/examples/test-print.cpp +++ b/examples/test-print.cpp @@ -8,7 +8,7 @@ * This file is released into the public domain. */ -#include "wirish.h" +#include #undef min #undef max diff --git a/examples/test-ring-buffer-insertion.cpp b/examples/test-ring-buffer-insertion.cpp index e86372a..2188b03 100644 --- a/examples/test-ring-buffer-insertion.cpp +++ b/examples/test-ring-buffer-insertion.cpp @@ -12,9 +12,9 @@ * This file is released into the public domain. */ -#include "wirish.h" +#include -#include "ring_buffer.h" +#include #define BUF_SIZE 64 ring_buffer ring_buf; diff --git a/examples/test-serial-flush.cpp b/examples/test-serial-flush.cpp index adc9c3e..409d1f9 100644 --- a/examples/test-serial-flush.cpp +++ b/examples/test-serial-flush.cpp @@ -2,7 +2,7 @@ * Tests the "flush" Serial function. */ -#include "wirish.h" +#include void setup() { Serial1.begin(9600); diff --git a/examples/test-serialusb.cpp b/examples/test-serialusb.cpp index 15ab913..098e445 100644 --- a/examples/test-serialusb.cpp +++ b/examples/test-serialusb.cpp @@ -1,7 +1,7 @@ // Tests SerialUSB functionality. -#include "wirish.h" -#include "usb.h" +#include +#include "usb_cdcacm.h" #define QUICKPRINT 0 #define BIGSTUFF 1 @@ -37,7 +37,7 @@ void loop() { switch (state) { case QUICKPRINT: for (int i = 0; i < 30; i++) { - usbSendBytes(&c1, 1); + usb_cdcacm_putc((char)c1, 1); SerialUSB.print('.'); SerialUSB.print('|'); } diff --git a/examples/test-servo.cpp b/examples/test-servo.cpp index b6b8cd5..6f6e3ba 100644 --- a/examples/test-servo.cpp +++ b/examples/test-servo.cpp @@ -29,7 +29,7 @@ #include -#include "wirish.h" +#include #include "libraries/Servo/Servo.h" diff --git a/examples/test-session.cpp b/examples/test-session.cpp index 6c7cfff..4316cda 100644 --- a/examples/test-session.cpp +++ b/examples/test-session.cpp @@ -4,7 +4,7 @@ // Useful for testing Maple features and troubleshooting. // Communicates over SerialUSB. -#include "wirish.h" +#include // ASCII escape character #define ESC ((uint8)27) diff --git a/examples/test-spi-roundtrip.cpp b/examples/test-spi-roundtrip.cpp index 71ae658..ddc9875 100644 --- a/examples/test-spi-roundtrip.cpp +++ b/examples/test-spi-roundtrip.cpp @@ -17,7 +17,7 @@ * Author: Marti Bolivar */ -#include "wirish.h" +#include HardwareSPI alice(2); diff --git a/examples/test-systick.cpp b/examples/test-systick.cpp index 78c7307..356f302 100644 --- a/examples/test-systick.cpp +++ b/examples/test-systick.cpp @@ -1,7 +1,7 @@ // Tests the SysTick enable/disable functions -#include "wirish.h" -#include "systick.h" +#include +#include void setup() { pinMode(BOARD_LED_PIN, OUTPUT); diff --git a/examples/test-timers.cpp b/examples/test-timers.cpp index 247cc57..2a8223c 100644 --- a/examples/test-timers.cpp +++ b/examples/test-timers.cpp @@ -1,7 +1,7 @@ // Program to test the timer.h implementation's essential functionality. -#include "wirish.h" -#include "timer.h" +#include +#include void handler1(void); void handler2(void); diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index 5ff5b86..8fbcccb 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -19,11 +19,11 @@ * This code is released into the public domain. */ -#include "dma.h" -#include "usart.h" -#include "gpio.h" +#include +#include +#include -#include "wirish.h" +#include #define BAUD 9600 diff --git a/examples/vga-leaf.cpp b/examples/vga-leaf.cpp index f31dc87..5159956 100644 --- a/examples/vga-leaf.cpp +++ b/examples/vga-leaf.cpp @@ -32,7 +32,7 @@ // FIXME: generalize for Native and Mini -#include "wirish.h" +#include // Pinouts -- you also must change the GPIO macros below if you change // these diff --git a/examples/vga-scope.cpp b/examples/vga-scope.cpp index b5fa8a5..8730cf0 100644 --- a/examples/vga-scope.cpp +++ b/examples/vga-scope.cpp @@ -35,8 +35,8 @@ Marti Bolivar */ -#include "wirish.h" -#include "systick.h" +#include +#include // FIXME: generalize for Native and Mini diff --git a/libmaple/adc.c b/libmaple/adc.c index 2bd2ad1..40369e9 100644 --- a/libmaple/adc.c +++ b/libmaple/adc.c @@ -37,9 +37,9 @@ * See STM32 manual RM0008 for how to calculate this. */ -#include "libmaple.h" -#include "rcc.h" -#include "adc.h" +#include +#include +#include static adc_dev adc1 = { .regs = ADC1_BASE, diff --git a/libmaple/adc.h b/libmaple/adc.h deleted file mode 100644 index d0b85fa..0000000 --- a/libmaple/adc.h +++ /dev/null @@ -1,364 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file adc.h - * - * @brief Analog-to-Digital Conversion (ADC) header. - */ - -#ifndef _ADC_H_ -#define _ADC_H_ - -#include "libmaple.h" -#include "bitband.h" -#include "rcc.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/** ADC register map type. */ -typedef struct adc_reg_map { - __io uint32 SR; ///< Status register - __io uint32 CR1; ///< Control register 1 - __io uint32 CR2; ///< Control register 2 - __io uint32 SMPR1; ///< Sample time register 1 - __io uint32 SMPR2; ///< Sample time register 2 - __io uint32 JOFR1; ///< Injected channel data offset register 1 - __io uint32 JOFR2; ///< Injected channel data offset register 2 - __io uint32 JOFR3; ///< Injected channel data offset register 3 - __io uint32 JOFR4; ///< Injected channel data offset register 4 - __io uint32 HTR; ///< Watchdog high threshold register - __io uint32 LTR; ///< Watchdog low threshold register - __io uint32 SQR1; ///< Regular sequence register 1 - __io uint32 SQR2; ///< Regular sequence register 2 - __io uint32 SQR3; ///< Regular sequence register 3 - __io uint32 JSQR; ///< Injected sequence register - __io uint32 JDR1; ///< Injected data register 1 - __io uint32 JDR2; ///< Injected data register 2 - __io uint32 JDR3; ///< Injected data register 3 - __io uint32 JDR4; ///< Injected data register 4 - __io uint32 DR; ///< Regular data register -} adc_reg_map; - -/** ADC device type. */ -typedef struct adc_dev { - adc_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ -} adc_dev; - -extern const adc_dev *ADC1; -extern const adc_dev *ADC2; -#ifdef STM32_HIGH_DENSITY -extern const adc_dev *ADC3; -#endif - -/* - * Register map base pointers - */ - -/** ADC1 register map base pointer. */ -#define ADC1_BASE ((struct adc_reg_map*)0x40012400) -/** ADC2 register map base pointer. */ -#define ADC2_BASE ((struct adc_reg_map*)0x40012800) -#ifdef STM32_HIGH_DENSITY -/** ADC3 register map base pointer. */ -#define ADC3_BASE ((struct adc_reg_map*)0x40013C00) -#endif - -/* - * Register bit definitions - */ - -/* Status register */ - -#define ADC_SR_AWD_BIT 0 -#define ADC_SR_EOC_BIT 1 -#define ADC_SR_JEOC_BIT 2 -#define ADC_SR_JSTRT_BIT 3 -#define ADC_SR_STRT_BIT 4 - -#define ADC_SR_AWD BIT(ADC_SR_AWD_BIT) -#define ADC_SR_EOC BIT(ADC_SR_EOC_BIT) -#define ADC_SR_JEOC BIT(ADC_SR_JEOC_BIT) -#define ADC_SR_JSTRT BIT(ADC_SR_JSTRT_BIT) -#define ADC_SR_STRT BIT(ADC_SR_STRT_BIT) - -/* Control register 1 */ - -#define ADC_CR1_EOCIE_BIT 5 -#define ADC_CR1_AWDIE_BIT 6 -#define ADC_CR1_JEOCIE_BIT 7 -#define ADC_CR1_SCAN_BIT 8 -#define ADC_CR1_AWDSGL_BIT 9 -#define ADC_CR1_JAUTO_BIT 10 -#define ADC_CR1_DISCEN_BIT 11 -#define ADC_CR1_JDISCEN_BIT 12 -#define ADC_CR1_JAWDEN_BIT 22 -#define ADC_CR1_AWDEN_BIT 23 - -#define ADC_CR1_AWDCH (0x1F) -#define ADC_CR1_EOCIE BIT(ADC_CR1_EOCIE_BIT) -#define ADC_CR1_AWDIE BIT(ADC_CR1_AWDIE_BIT) -#define ADC_CR1_JEOCIE BIT(ADC_CR1_JEOCIE_BIT) -#define ADC_CR1_SCAN BIT(ADC_CR1_SCAN_BIT) -#define ADC_CR1_AWDSGL BIT(ADC_CR1_AWDSGL_BIT) -#define ADC_CR1_JAUTO BIT(ADC_CR1_JAUTO_BIT) -#define ADC_CR1_DISCEN BIT(ADC_CR1_DISCEN_BIT) -#define ADC_CR1_JDISCEN BIT(ADC_CR1_JDISCEN_BIT) -#define ADC_CR1_DISCNUM (0xE000) -#define ADC_CR1_JAWDEN BIT(ADC_CR1_JAWDEN_BIT) -#define ADC_CR1_AWDEN BIT(ADC_CR1_AWDEN_BIT) - -/* Control register 2 */ - -#define ADC_CR2_ADON_BIT 0 -#define ADC_CR2_CONT_BIT 1 -#define ADC_CR2_CAL_BIT 2 -#define ADC_CR2_RSTCAL_BIT 3 -#define ADC_CR2_DMA_BIT 8 -#define ADC_CR2_ALIGN_BIT 11 -#define ADC_CR2_JEXTTRIG_BIT 15 -#define ADC_CR2_EXTTRIG_BIT 20 -#define ADC_CR2_JSWSTART_BIT 21 -#define ADC_CR2_SWSTART_BIT 22 -#define ADC_CR2_TSEREFE_BIT 23 - -#define ADC_CR2_ADON BIT(ADC_CR2_ADON_BIT) -#define ADC_CR2_CONT BIT(ADC_CR2_CONT_BIT) -#define ADC_CR2_CAL BIT(ADC_CR2_CAL_BIT) -#define ADC_CR2_RSTCAL BIT(ADC_CR2_RSTCAL_BIT) -#define ADC_CR2_DMA BIT(ADC_CR2_DMA_BIT) -#define ADC_CR2_ALIGN BIT(ADC_CR2_ALIGN_BIT) -#define ADC_CR2_JEXTSEL (0x7000) -#define ADC_CR2_JEXTTRIG BIT(ADC_CR2_JEXTTRIG_BIT) -#define ADC_CR2_EXTSEL (0xE0000) -#define ADC_CR2_EXTTRIG BIT(ADC_CR2_EXTTRIG_BIT) -#define ADC_CR2_JSWSTART BIT(ADC_CR2_JSWSTART_BIT) -#define ADC_CR2_SWSTART BIT(ADC_CR2_SWSTART_BIT) -#define ADC_CR2_TSEREFE BIT(ADC_CR2_TSEREFE_BIT) - -/* Sample time register 1 */ - -#define ADC_SMPR1_SMP17 (0x7 << 21) -#define ADC_SMPR1_SMP16 (0x7 << 18) -#define ADC_SMPR1_SMP15 (0x7 << 15) -#define ADC_SMPR1_SMP14 (0x7 << 12) -#define ADC_SMPR1_SMP13 (0x7 << 9) -#define ADC_SMPR1_SMP12 (0x7 << 6) -#define ADC_SMPR1_SMP11 (0x7 << 3) -#define ADC_SMPR1_SMP10 0x7 - -/* Sample time register 2 */ - -#define ADC_SMPR2_SMP9 (0x7 << 27) -#define ADC_SMPR2_SMP8 (0x7 << 24) -#define ADC_SMPR2_SMP7 (0x7 << 21) -#define ADC_SMPR2_SMP6 (0x7 << 18) -#define ADC_SMPR2_SMP5 (0x7 << 15) -#define ADC_SMPR2_SMP4 (0x7 << 12) -#define ADC_SMPR2_SMP3 (0x7 << 9) -#define ADC_SMPR2_SMP2 (0x7 << 6) -#define ADC_SMPR2_SMP1 (0x7 << 3) -#define ADC_SMPR2_SMP0 0x7 - -/* Injected channel data offset register */ - -#define ADC_JOFR_JOFFSET 0x3FF - -/* Watchdog high threshold register */ - -#define ADC_HTR_HT 0x3FF - -/* Watchdog low threshold register */ - -#define ADC_LTR_LT 0x3FF - -/* Regular sequence register 1 */ - -#define ADC_SQR1_L (0x1F << 20) -#define ADC_SQR1_SQ16 (0x1F << 15) -#define ADC_SQR1_SQ15 (0x1F << 10) -#define ADC_SQR1_SQ14 (0x1F << 5) -#define ADC_SQR1_SQ13 0x1F - -/* Regular sequence register 2 */ - -#define ADC_SQR2_SQ12 (0x1F << 25) -#define ADC_SQR2_SQ11 (0x1F << 20) -#define ADC_SQR2_SQ10 (0x1F << 16) -#define ADC_SQR2_SQ9 (0x1F << 10) -#define ADC_SQR2_SQ8 (0x1F << 5) -#define ADC_SQR2_SQ7 0x1F - -/* Regular sequence register 3 */ - -#define ADC_SQR3_SQ6 (0x1F << 25) -#define ADC_SQR3_SQ5 (0x1F << 20) -#define ADC_SQR3_SQ4 (0x1F << 16) -#define ADC_SQR3_SQ3 (0x1F << 10) -#define ADC_SQR3_SQ2 (0x1F << 5) -#define ADC_SQR3_SQ1 0x1F - -/* Injected sequence register */ - -#define ADC_JSQR_JL (0x3 << 20) -#define ADC_JSQR_JL_1CONV (0x0 << 20) -#define ADC_JSQR_JL_2CONV (0x1 << 20) -#define ADC_JSQR_JL_3CONV (0x2 << 20) -#define ADC_JSQR_JL_4CONV (0x3 << 20) -#define ADC_JSQR_JSQ4 (0x1F << 15) -#define ADC_JSQR_JSQ3 (0x1F << 10) -#define ADC_JSQR_JSQ2 (0x1F << 5) -#define ADC_JSQR_JSQ1 0x1F - -/* Injected data registers */ - -#define ADC_JDR_JDATA 0xFFFF - -/* Regular data register */ - -#define ADC_DR_ADC2DATA (0xFFFF << 16) -#define ADC_DR_DATA 0xFFFF - -void adc_init(const adc_dev *dev); - -/** - * @brief External event selector for regular group conversion. - * @see adc_set_extsel - */ -typedef enum adc_extsel_event { - ADC_ADC12_TIM1_CC1 = (0 << 17), /**< ADC1 and ADC2: Timer 1 CC1 event */ - ADC_ADC12_TIM1_CC2 = (1 << 17), /**< ADC1 and ADC2: Timer 1 CC2 event */ - ADC_ADC12_TIM1_CC3 = (2 << 17), /**< ADC1 and ADC2: Timer 1 CC3 event */ - ADC_ADC12_TIM2_CC2 = (3 << 17), /**< ADC1 and ADC2: Timer 2 CC2 event */ - ADC_ADC12_TIM3_TRGO = (4 << 17), /**< ADC1 and ADC2: Timer 3 TRGO event */ - ADC_ADC12_TIM4_CC4 = (5 << 17), /**< ADC1 and ADC2: Timer 4 CC4 event */ - ADC_ADC12_EXTI11 = (6 << 17), /**< ADC1 and ADC2: EXTI11 event */ -#ifdef STM32_HIGH_DENSITY - ADC_ADC12_TIM8_TRGO = (6 << 17), /**< ADC1 and ADC2: Timer 8 TRGO - event (high density only) */ -#endif - ADC_ADC12_SWSTART = (7 << 17), /**< ADC1 and ADC2: Software start */ -#ifdef STM32_HIGH_DENSITY - ADC_ADC3_TIM3_CC1 = (0 << 17), /**< ADC3: Timer 3 CC1 event - (high density only) */ - ADC_ADC3_TIM2_CC3 = (1 << 17), /**< ADC3: Timer 2 CC3 event - (high density only) */ - ADC_ADC3_TIM1_CC3 = (2 << 17), /**< ADC3: Timer 1 CC3 event - (high density only) */ - ADC_ADC3_TIM8_CC1 = (3 << 17), /**< ADC3: Timer 8 CC1 event - (high density only) */ - ADC_ADC3_TIM8_TRGO = (4 << 17), /**< ADC3: Timer 8 TRGO event - (high density only) */ - ADC_ADC3_TIM5_CC1 = (5 << 17), /**< ADC3: Timer 5 CC1 event - (high density only) */ - ADC_ADC3_TIM5_CC3 = (6 << 17), /**< ADC3: Timer 5 CC3 event - (high density only) */ - ADC_ADC3_SWSTART = (7 << 17), /**< ADC3: Software start (high - density only) */ -#endif - ADC_SWSTART = (7 << 17) /**< ADC1, ADC2, ADC3: Software start */ -} adc_extsel_event; - -void adc_set_extsel(const adc_dev *dev, adc_extsel_event event); -void adc_foreach(void (*fn)(const adc_dev*)); - -/** - * @brief ADC sample times, in ADC clock cycles - * - * These control the amount of time spent sampling the input voltage. - */ -typedef enum { - ADC_SMPR_1_5, /**< 1.5 ADC cycles */ - ADC_SMPR_7_5, /**< 7.5 ADC cycles */ - ADC_SMPR_13_5, /**< 13.5 ADC cycles */ - ADC_SMPR_28_5, /**< 28.5 ADC cycles */ - ADC_SMPR_41_5, /**< 41.5 ADC cycles */ - ADC_SMPR_55_5, /**< 55.5 ADC cycles */ - ADC_SMPR_71_5, /**< 71.5 ADC cycles */ - ADC_SMPR_239_5 /**< 239.5 ADC cycles */ -} adc_smp_rate; - -void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); -void adc_calibrate(const adc_dev *dev); -uint16 adc_read(const adc_dev *dev, uint8 channel); - -/** - * @brief Set the regular channel sequence length. - * - * Defines the total number of conversions in the regular channel - * conversion sequence. - * - * @param dev ADC device. - * @param length Regular channel sequence length, from 1 to 16. - */ -static inline void adc_set_reg_seqlen(const adc_dev *dev, uint8 length) { - uint32 tmp = dev->regs->SQR1; - tmp &= ~ADC_SQR1_L; - tmp |= (length - 1) << 20; - dev->regs->SQR1 = tmp; -} - -/** - * @brief Set external trigger conversion mode event for regular channels - * @param dev ADC device - * @param enable If 1, conversion on external events is enabled; if 0, - * disabled. - */ -static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) { - *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable; -} - -/** - * @brief Enable an adc peripheral - * @param dev ADC device to enable - */ -static inline void adc_enable(const adc_dev *dev) { - *bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 1; -} - -/** - * @brief Disable an ADC peripheral - * @param dev ADC device to disable - */ -static inline void adc_disable(const adc_dev *dev) { - *bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 0; -} - -/** - * @brief Disable all ADC peripherals. - */ -static inline void adc_disable_all(void) { - adc_foreach(adc_disable); -} - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/bitband.h b/libmaple/bitband.h deleted file mode 100644 index 73941b0..0000000 --- a/libmaple/bitband.h +++ /dev/null @@ -1,120 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file bitband.h - * - * @brief Bit-banding utility functions - */ - -#include "libmaple_types.h" - -#ifndef _BITBAND_H_ -#define _BITBAND_H_ - -#define BB_SRAM_REF 0x20000000 -#define BB_SRAM_BASE 0x22000000 -#define BB_PERI_REF 0x40000000 -#define BB_PERI_BASE 0x42000000 - -static inline volatile uint32* __bb_addr(volatile void*, - uint32, - uint32, - uint32); - -/** - * @brief Obtain a pointer to the bit-band address corresponding to a - * bit in a volatile SRAM address. - * @param address Address in the bit-banded SRAM region - * @param bit Bit in address to bit-band - */ -static inline volatile uint32* bb_sramp(volatile void *address, uint32 bit) { - return __bb_addr(address, bit, BB_SRAM_BASE, BB_SRAM_REF); -} - -/** - * @brief Get a bit from an address in the SRAM bit-band region. - * @param address Address in the SRAM bit-band region to read from - * @param bit Bit in address to read - * @return bit's value in address. - */ -static inline uint8 bb_sram_get_bit(volatile void *address, uint32 bit) { - return *bb_sramp(address, bit); -} - -/** - * @brief Set a bit in an address in the SRAM bit-band region. - * @param address Address in the SRAM bit-band region to write to - * @param bit Bit in address to write to - * @param val Value to write for bit, either 0 or 1. - */ -static inline void bb_sram_set_bit(volatile void *address, - uint32 bit, - uint8 val) { - *bb_sramp(address, bit) = val; -} - -/** - * @brief Obtain a pointer to the bit-band address corresponding to a - * bit in a peripheral address. - * @param address Address in the bit-banded peripheral region - * @param bit Bit in address to bit-band - */ -static inline volatile uint32* bb_perip(volatile void *address, uint32 bit) { - return __bb_addr(address, bit, BB_PERI_BASE, BB_PERI_REF); -} - -/** - * @brief Get a bit from an address in the peripheral bit-band region. - * @param address Address in the peripheral bit-band region to read from - * @param bit Bit in address to read - * @return bit's value in address. - */ -static inline uint8 bb_peri_get_bit(volatile void *address, uint32 bit) { - return *bb_perip(address, bit); -} - -/** - * @brief Set a bit in an address in the peripheral bit-band region. - * @param address Address in the peripheral bit-band region to write to - * @param bit Bit in address to write to - * @param val Value to write for bit, either 0 or 1. - */ -static inline void bb_peri_set_bit(volatile void *address, - uint32 bit, - uint8 val) { - *bb_perip(address, bit) = val; -} - -static inline volatile uint32* __bb_addr(volatile void *address, - uint32 bit, - uint32 bb_base, - uint32 bb_ref) { - return (volatile uint32*)(bb_base + ((uint32)address - bb_ref) * 32 + - bit * 4); -} - -#endif /* _BITBAND_H_ */ diff --git a/libmaple/bkp.c b/libmaple/bkp.c index 7d1ad7f..62783e7 100644 --- a/libmaple/bkp.c +++ b/libmaple/bkp.c @@ -29,10 +29,10 @@ * @brief Backup register support. */ -#include "bkp.h" -#include "pwr.h" -#include "rcc.h" -#include "bitband.h" +#include +#include +#include +#include static inline __io uint32* data_register(uint8 reg); diff --git a/libmaple/bkp.h b/libmaple/bkp.h deleted file mode 100644 index a81267d..0000000 --- a/libmaple/bkp.h +++ /dev/null @@ -1,166 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file bkp.h - * @brief Backup register support. - */ - -#ifndef _BKP_H_ -#define _BKP_H_ - -#include "libmaple.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(STM32_MEDIUM_DENSITY) -#define BKP_NR_DATA_REGS 10 -#elif defined(STM32_HIGH_DENSITY) -#define BKP_NR_DATA_REGS 42 -#endif - -/** Backup peripheral register map type. */ -typedef struct bkp_reg_map { - const uint32 RESERVED1; ///< Reserved - __io uint32 DR1; ///< Data register 1 - __io uint32 DR2; ///< Data register 2 - __io uint32 DR3; ///< Data register 3 - __io uint32 DR4; ///< Data register 4 - __io uint32 DR5; ///< Data register 5 - __io uint32 DR6; ///< Data register 6 - __io uint32 DR7; ///< Data register 7 - __io uint32 DR8; ///< Data register 8 - __io uint32 DR9; ///< Data register 9 - __io uint32 DR10; ///< Data register 10 - __io uint32 RTCCR; ///< RTC control register - __io uint32 CR; ///< Control register - __io uint32 CSR; ///< Control and status register -#ifdef STM32_HIGH_DENSITY - const uint32 RESERVED2; ///< Reserved - const uint32 RESERVED3; ///< Reserved - __io uint32 DR11; ///< Data register 11 - __io uint32 DR12; ///< Data register 12 - __io uint32 DR13; ///< Data register 13 - __io uint32 DR14; ///< Data register 14 - __io uint32 DR15; ///< Data register 15 - __io uint32 DR16; ///< Data register 16 - __io uint32 DR17; ///< Data register 17 - __io uint32 DR18; ///< Data register 18 - __io uint32 DR19; ///< Data register 19 - __io uint32 DR20; ///< Data register 20 - __io uint32 DR21; ///< Data register 21 - __io uint32 DR22; ///< Data register 22 - __io uint32 DR23; ///< Data register 23 - __io uint32 DR24; ///< Data register 24 - __io uint32 DR25; ///< Data register 25 - __io uint32 DR26; ///< Data register 26 - __io uint32 DR27; ///< Data register 27 - __io uint32 DR28; ///< Data register 28 - __io uint32 DR29; ///< Data register 29 - __io uint32 DR30; ///< Data register 30 - __io uint32 DR31; ///< Data register 31 - __io uint32 DR32; ///< Data register 32 - __io uint32 DR33; ///< Data register 33 - __io uint32 DR34; ///< Data register 34 - __io uint32 DR35; ///< Data register 35 - __io uint32 DR36; ///< Data register 36 - __io uint32 DR37; ///< Data register 37 - __io uint32 DR38; ///< Data register 38 - __io uint32 DR39; ///< Data register 39 - __io uint32 DR40; ///< Data register 40 - __io uint32 DR41; ///< Data register 41 - __io uint32 DR42; ///< Data register 42 -#endif -} bkp_reg_map; - -/** Backup peripheral register map base pointer. */ -#define BKP_BASE ((struct bkp_reg_map*)0x40006C00) - -/** Backup peripheral device type. */ -typedef struct bkp_dev { - bkp_reg_map *regs; /**< Register map */ -} bkp_dev; - -extern const bkp_dev *BKP; - -/* - * Register bit definitions - */ - -/* Data Registers */ - -#define BKP_DR_D 0xFFFF - -/* RTC Clock Calibration Register */ - -#define BKP_RTCCR_ASOS_BIT 9 -#define BKP_RTCCR_ASOE_BIT 8 -#define BKP_RTCCR_CCO_BIT 7 - -#define BKP_RTCCR_ASOS BIT(BKP_RTCCR_ASOS_BIT) -#define BKP_RTCCR_ASOE BIT(BKP_RTCCR_ASOE_BIT) -#define BKP_RTCCR_CCO BIT(BKP_RTCCR_CCO_BIT) -#define BKP_RTCCR_CAL 0x7F - -/* Backup control register */ - -#define BKP_CR_TPAL_BIT 1 -#define BKP_CR_TPE_BIT 0 - -#define BKP_CR_TPAL BIT(BKP_CR_TPAL_BIT) -#define BKP_CR_TPE BIT(BKP_CR_TPE_BIT) - -/* Backup control/status register */ - -#define BKP_CSR_TIF_BIT 9 -#define BKP_CSR_TEF_BIT 8 -#define BKP_CSR_TPIE_BIT 2 -#define BKP_CSR_CTI_BIT 1 -#define BKP_CSR_CTE_BIT 0 - -#define BKP_CSR_TIF BIT(BKP_CSR_TIF_BIT) -#define BKP_CSR_TEF BIT(BKP_CSR_TEF_BIT) -#define BKP_CSR_TPIE BIT(BKP_CSR_TPIE_BIT) -#define BKP_CSR_CTI BIT(BKP_CSR_CTI_BIT) -#define BKP_CSR_CTE BIT(BKP_CSR_CTE_BIT) - -/* - * Convenience functions - */ - -void bkp_init(void); -void bkp_enable_writes(void); -void bkp_disable_writes(void); -uint16 bkp_read(uint8 reg); -void bkp_write(uint8 reg, uint16 val); - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif diff --git a/libmaple/dac.c b/libmaple/dac.c index 15e944f..efcba15 100644 --- a/libmaple/dac.c +++ b/libmaple/dac.c @@ -29,9 +29,9 @@ * @brief Digital to analog converter support. */ -#include "libmaple.h" -#include "gpio.h" -#include "dac.h" +#include +#include +#include #ifdef STM32_HIGH_DENSITY diff --git a/libmaple/dac.h b/libmaple/dac.h deleted file mode 100644 index aa04981..0000000 --- a/libmaple/dac.h +++ /dev/null @@ -1,168 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Bryan Newbold. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file dac.h - * @brief Digital to analog converter support. - */ - -/* See notes/dac.txt for more info */ - -#ifndef _DAC_H_ -#define _DAC_H_ - -#include "rcc.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Register maps - */ - -/** DAC register map. */ -typedef struct dac_reg_map { - __io uint32 CR; /**< Control register */ - __io uint32 SWTRIGR; /**< Software trigger register */ - __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data - holding register */ - __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data - holding register */ - __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data - holding register */ - __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data - holding register */ - __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data - holding register */ - __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data - holding register */ - __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data - holding register */ - __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data - holding register */ - __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding - register */ - __io uint32 DOR1; /**< Channel 1 data output register */ - __io uint32 DOR2; /**< Channel 2 data output register */ -} dac_reg_map; - -/** DAC register map base address */ -#define DAC_BASE ((struct dac_reg_map*)0x40007400) - -/* - * Devices - */ - -/** DAC device type. */ -typedef struct dac_dev { - dac_reg_map *regs; /**< Register map */ -} dac_dev; - -extern const dac_dev *DAC; - -/* - * Register bit definitions - */ - -/* Control register */ -/* Channel 1 control */ -#define DAC_CR_EN1 BIT(0) /* Enable */ -#define DAC_CR_BOFF1 BIT(1) /* Output buffer disable */ -#define DAC_CR_TEN1 BIT(2) /* Trigger enable */ -#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */ -#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave enable */ -#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */ -#define DAC_CR_DMAEN1 BIT(12) /* DMA enable */ -/* Channel 2 control */ -#define DAC_CR_EN2 BIT(16) /* Enable */ -#define DAC_CR_BOFF2 BIT(17) /* Output buffer disable */ -#define DAC_CR_TEN2 BIT(18) /* Trigger enable */ -#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */ -#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave generation*/ -#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */ -#define DAC_CR_DMAEN2 BIT(28) /* DMA enable */ - -/* Software trigger register */ -#define DAC_SWTRIGR_SWTRIG1 BIT(0) /* Channel 1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 BIT(1) /* Channel 2 software trigger */ - -/* Channel 1 12-bit right-aligned data holding register */ -#define DAC_DHR12R1_DACC1DHR 0x00000FFF - -/* Channel 1 12-bit left-aligned data holding register */ -#define DAC_DHR12L1_DACC1DHR 0x0000FFF0 - -/* Channel 1 8-bit left-aligned data holding register */ -#define DAC_DHR8R1_DACC1DHR 0x000000FF - -/* Channel 2 12-bit right-aligned data holding register */ -#define DAC_DHR12R2_DACC2DHR 0x00000FFF - -/* Channel 2 12-bit left-aligned data holding register */ -#define DAC_DHR12L2_DACC2DHR 0x0000FFF0 - -/* Channel 2 8-bit left-aligned data holding register */ -#define DAC_DHR8R2_DACC2DHR 0x000000FF - -/* Dual DAC 12-bit right-aligned data holding register */ -#define DAC_DHR12RD_DACC1DHR 0x00000FFF -#define DAC_DHR12RD_DACC2DHR 0x0FFF0000 - -/* Dual DAC 12-bit left-aligned data holding register */ -#define DAC_DHR12LD_DACC1DHR 0x0000FFF0 -#define DAC_DHR12LD_DACC2DHR 0xFFF00000 - -/* Dual DAC 8-bit left-aligned data holding register */ -#define DAC_DHR8RD_DACC1DHR 0x000000FF -#define DAC_DHR8RD_DACC2DHR 0x0000FF00 - -/* Channel 1 data output register */ -#define DAC_DOR1_DACC1DOR 0x00000FFF - -/* Channel 1 data output register */ -#define DAC_DOR2_DACC2DOR 0x00000FFF - -/* - * Convenience functions - */ - -/* We take the dev argument in these convenience functions for - * future-proofing */ - -#define DAC_CH1 0x1 -#define DAC_CH2 0x2 -void dac_init(const dac_dev *dev, uint32 flags); - -void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val); -void dac_enable_channel(const dac_dev *dev, uint8 channel); -void dac_disable_channel(const dac_dev *dev, uint8 channel); - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/delay.h b/libmaple/delay.h deleted file mode 100644 index 6f8b8ba..0000000 --- a/libmaple/delay.h +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file delay.h - * @brief Delay implementation - */ - -#include "libmaple_types.h" -#include "stm32.h" - -#ifndef _DELAY_H_ -#define _DELAY_H_ - -/** - * @brief Delay the given number of microseconds. - * - * @param us Number of microseconds to delay. - */ -static inline void delay_us(uint32 us) { - us *= STM32_DELAY_US_MULT; - - /* fudge for function call overhead */ - us--; - asm volatile(" mov r0, %[us] \n\t" - "1: subs r0, #1 \n\t" - " bhi 1b \n\t" - : - : [us] "r" (us) - : "r0"); -} -#endif - diff --git a/libmaple/dma.c b/libmaple/dma.c index 60f4d47..f20613b 100644 --- a/libmaple/dma.c +++ b/libmaple/dma.c @@ -31,9 +31,9 @@ * @brief Direct Memory Access peripheral support */ -#include "dma.h" -#include "bitband.h" -#include "util.h" +#include +#include +#include /* * Devices diff --git a/libmaple/dma.h b/libmaple/dma.h deleted file mode 100644 index 6e8087f..0000000 --- a/libmaple/dma.h +++ /dev/null @@ -1,453 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Michael Hope. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file dma.h - * - * @author Marti Bolivar ; - * Original implementation by Michael Hope - * - * @brief Direct Memory Access peripheral support - */ - -/* - * See /notes/dma.txt for more information. - */ - -#ifndef _DMA_H_ -#define _DMA_H_ - -#include "libmaple_types.h" -#include "rcc.h" -#include "nvic.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Register maps - */ - -/** - * @brief DMA register map type. - * - * Note that DMA controller 2 (register map base pointer DMA2_BASE) - * only supports channels 1--5. - */ -typedef struct dma_reg_map { - __io uint32 ISR; /**< Interrupt status register */ - __io uint32 IFCR; /**< Interrupt flag clear register */ - __io uint32 CCR1; /**< Channel 1 configuration register */ - __io uint32 CNDTR1; /**< Channel 1 number of data register */ - __io uint32 CPAR1; /**< Channel 1 peripheral address register */ - __io uint32 CMAR1; /**< Channel 1 memory address register */ - const uint32 RESERVED1; /**< Reserved. */ - __io uint32 CCR2; /**< Channel 2 configuration register */ - __io uint32 CNDTR2; /**< Channel 2 number of data register */ - __io uint32 CPAR2; /**< Channel 2 peripheral address register */ - __io uint32 CMAR2; /**< Channel 2 memory address register */ - const uint32 RESERVED2; /**< Reserved. */ - __io uint32 CCR3; /**< Channel 3 configuration register */ - __io uint32 CNDTR3; /**< Channel 3 number of data register */ - __io uint32 CPAR3; /**< Channel 3 peripheral address register */ - __io uint32 CMAR3; /**< Channel 3 memory address register */ - const uint32 RESERVED3; /**< Reserved. */ - __io uint32 CCR4; /**< Channel 4 configuration register */ - __io uint32 CNDTR4; /**< Channel 4 number of data register */ - __io uint32 CPAR4; /**< Channel 4 peripheral address register */ - __io uint32 CMAR4; /**< Channel 4 memory address register */ - const uint32 RESERVED4; /**< Reserved. */ - __io uint32 CCR5; /**< Channel 5 configuration register */ - __io uint32 CNDTR5; /**< Channel 5 number of data register */ - __io uint32 CPAR5; /**< Channel 5 peripheral address register */ - __io uint32 CMAR5; /**< Channel 5 memory address register */ - const uint32 RESERVED5; /**< Reserved. */ - __io uint32 CCR6; /**< Channel 6 configuration register */ - __io uint32 CNDTR6; /**< Channel 6 number of data register */ - __io uint32 CPAR6; /**< Channel 6 peripheral address register */ - __io uint32 CMAR6; /**< Channel 6 memory address register */ - const uint32 RESERVED6; /**< Reserved. */ - __io uint32 CCR7; /**< Channel 7 configuration register */ - __io uint32 CNDTR7; /**< Channel 7 number of data register */ - __io uint32 CPAR7; /**< Channel 7 peripheral address register */ - __io uint32 CMAR7; /**< Channel 7 memory address register */ - const uint32 RESERVED7; /**< Reserved. */ -} dma_reg_map; - -/** DMA controller 1 register map base pointer */ -#define DMA1_BASE ((struct dma_reg_map*)0x40020000) - -#ifdef STM32_HIGH_DENSITY -/** DMA controller 2 register map base pointer */ -#define DMA2_BASE ((struct dma_reg_map*)0x40020400) -#endif - -/* - * Register bit definitions - */ - -/* Interrupt status register */ - -#define DMA_ISR_TEIF7_BIT 27 -#define DMA_ISR_HTIF7_BIT 26 -#define DMA_ISR_TCIF7_BIT 25 -#define DMA_ISR_GIF7_BIT 24 -#define DMA_ISR_TEIF6_BIT 23 -#define DMA_ISR_HTIF6_BIT 22 -#define DMA_ISR_TCIF6_BIT 21 -#define DMA_ISR_GIF6_BIT 20 -#define DMA_ISR_TEIF5_BIT 19 -#define DMA_ISR_HTIF5_BIT 18 -#define DMA_ISR_TCIF5_BIT 17 -#define DMA_ISR_GIF5_BIT 16 -#define DMA_ISR_TEIF4_BIT 15 -#define DMA_ISR_HTIF4_BIT 14 -#define DMA_ISR_TCIF4_BIT 13 -#define DMA_ISR_GIF4_BIT 12 -#define DMA_ISR_TEIF3_BIT 11 -#define DMA_ISR_HTIF3_BIT 10 -#define DMA_ISR_TCIF3_BIT 9 -#define DMA_ISR_GIF3_BIT 8 -#define DMA_ISR_TEIF2_BIT 7 -#define DMA_ISR_HTIF2_BIT 6 -#define DMA_ISR_TCIF2_BIT 5 -#define DMA_ISR_GIF2_BIT 4 -#define DMA_ISR_TEIF1_BIT 3 -#define DMA_ISR_HTIF1_BIT 2 -#define DMA_ISR_TCIF1_BIT 1 -#define DMA_ISR_GIF1_BIT 0 - -#define DMA_ISR_TEIF7 BIT(DMA_ISR_TEIF7_BIT) -#define DMA_ISR_HTIF7 BIT(DMA_ISR_HTIF7_BIT) -#define DMA_ISR_TCIF7 BIT(DMA_ISR_TCIF7_BIT) -#define DMA_ISR_GIF7 BIT(DMA_ISR_GIF7_BIT) -#define DMA_ISR_TEIF6 BIT(DMA_ISR_TEIF6_BIT) -#define DMA_ISR_HTIF6 BIT(DMA_ISR_HTIF6_BIT) -#define DMA_ISR_TCIF6 BIT(DMA_ISR_TCIF6_BIT) -#define DMA_ISR_GIF6 BIT(DMA_ISR_GIF6_BIT) -#define DMA_ISR_TEIF5 BIT(DMA_ISR_TEIF5_BIT) -#define DMA_ISR_HTIF5 BIT(DMA_ISR_HTIF5_BIT) -#define DMA_ISR_TCIF5 BIT(DMA_ISR_TCIF5_BIT) -#define DMA_ISR_GIF5 BIT(DMA_ISR_GIF5_BIT) -#define DMA_ISR_TEIF4 BIT(DMA_ISR_TEIF4_BIT) -#define DMA_ISR_HTIF4 BIT(DMA_ISR_HTIF4_BIT) -#define DMA_ISR_TCIF4 BIT(DMA_ISR_TCIF4_BIT) -#define DMA_ISR_GIF4 BIT(DMA_ISR_GIF4_BIT) -#define DMA_ISR_TEIF3 BIT(DMA_ISR_TEIF3_BIT) -#define DMA_ISR_HTIF3 BIT(DMA_ISR_HTIF3_BIT) -#define DMA_ISR_TCIF3 BIT(DMA_ISR_TCIF3_BIT) -#define DMA_ISR_GIF3 BIT(DMA_ISR_GIF3_BIT) -#define DMA_ISR_TEIF2 BIT(DMA_ISR_TEIF2_BIT) -#define DMA_ISR_HTIF2 BIT(DMA_ISR_HTIF2_BIT) -#define DMA_ISR_TCIF2 BIT(DMA_ISR_TCIF2_BIT) -#define DMA_ISR_GIF2 BIT(DMA_ISR_GIF2_BIT) -#define DMA_ISR_TEIF1 BIT(DMA_ISR_TEIF1_BIT) -#define DMA_ISR_HTIF1 BIT(DMA_ISR_HTIF1_BIT) -#define DMA_ISR_TCIF1 BIT(DMA_ISR_TCIF1_BIT) -#define DMA_ISR_GIF1 BIT(DMA_ISR_GIF1_BIT) - -/* Interrupt flag clear register */ - -#define DMA_IFCR_CTEIF7_BIT 27 -#define DMA_IFCR_CHTIF7_BIT 26 -#define DMA_IFCR_CTCIF7_BIT 25 -#define DMA_IFCR_CGIF7_BIT 24 -#define DMA_IFCR_CTEIF6_BIT 23 -#define DMA_IFCR_CHTIF6_BIT 22 -#define DMA_IFCR_CTCIF6_BIT 21 -#define DMA_IFCR_CGIF6_BIT 20 -#define DMA_IFCR_CTEIF5_BIT 19 -#define DMA_IFCR_CHTIF5_BIT 18 -#define DMA_IFCR_CTCIF5_BIT 17 -#define DMA_IFCR_CGIF5_BIT 16 -#define DMA_IFCR_CTEIF4_BIT 15 -#define DMA_IFCR_CHTIF4_BIT 14 -#define DMA_IFCR_CTCIF4_BIT 13 -#define DMA_IFCR_CGIF4_BIT 12 -#define DMA_IFCR_CTEIF3_BIT 11 -#define DMA_IFCR_CHTIF3_BIT 10 -#define DMA_IFCR_CTCIF3_BIT 9 -#define DMA_IFCR_CGIF3_BIT 8 -#define DMA_IFCR_CTEIF2_BIT 7 -#define DMA_IFCR_CHTIF2_BIT 6 -#define DMA_IFCR_CTCIF2_BIT 5 -#define DMA_IFCR_CGIF2_BIT 4 -#define DMA_IFCR_CTEIF1_BIT 3 -#define DMA_IFCR_CHTIF1_BIT 2 -#define DMA_IFCR_CTCIF1_BIT 1 -#define DMA_IFCR_CGIF1_BIT 0 - -#define DMA_IFCR_CTEIF7 BIT(DMA_IFCR_CTEIF7_BIT) -#define DMA_IFCR_CHTIF7 BIT(DMA_IFCR_CHTIF7_BIT) -#define DMA_IFCR_CTCIF7 BIT(DMA_IFCR_CTCIF7_BIT) -#define DMA_IFCR_CGIF7 BIT(DMA_IFCR_CGIF7_BIT) -#define DMA_IFCR_CTEIF6 BIT(DMA_IFCR_CTEIF6_BIT) -#define DMA_IFCR_CHTIF6 BIT(DMA_IFCR_CHTIF6_BIT) -#define DMA_IFCR_CTCIF6 BIT(DMA_IFCR_CTCIF6_BIT) -#define DMA_IFCR_CGIF6 BIT(DMA_IFCR_CGIF6_BIT) -#define DMA_IFCR_CTEIF5 BIT(DMA_IFCR_CTEIF5_BIT) -#define DMA_IFCR_CHTIF5 BIT(DMA_IFCR_CHTIF5_BIT) -#define DMA_IFCR_CTCIF5 BIT(DMA_IFCR_CTCIF5_BIT) -#define DMA_IFCR_CGIF5 BIT(DMA_IFCR_CGIF5_BIT) -#define DMA_IFCR_CTEIF4 BIT(DMA_IFCR_CTEIF4_BIT) -#define DMA_IFCR_CHTIF4 BIT(DMA_IFCR_CHTIF4_BIT) -#define DMA_IFCR_CTCIF4 BIT(DMA_IFCR_CTCIF4_BIT) -#define DMA_IFCR_CGIF4 BIT(DMA_IFCR_CGIF4_BIT) -#define DMA_IFCR_CTEIF3 BIT(DMA_IFCR_CTEIF3_BIT) -#define DMA_IFCR_CHTIF3 BIT(DMA_IFCR_CHTIF3_BIT) -#define DMA_IFCR_CTCIF3 BIT(DMA_IFCR_CTCIF3_BIT) -#define DMA_IFCR_CGIF3 BIT(DMA_IFCR_CGIF3_BIT) -#define DMA_IFCR_CTEIF2 BIT(DMA_IFCR_CTEIF2_BIT) -#define DMA_IFCR_CHTIF2 BIT(DMA_IFCR_CHTIF2_BIT) -#define DMA_IFCR_CTCIF2 BIT(DMA_IFCR_CTCIF2_BIT) -#define DMA_IFCR_CGIF2 BIT(DMA_IFCR_CGIF2_BIT) -#define DMA_IFCR_CTEIF1 BIT(DMA_IFCR_CTEIF1_BIT) -#define DMA_IFCR_CHTIF1 BIT(DMA_IFCR_CHTIF1_BIT) -#define DMA_IFCR_CTCIF1 BIT(DMA_IFCR_CTCIF1_BIT) -#define DMA_IFCR_CGIF1 BIT(DMA_IFCR_CGIF1_BIT) - -/* Channel configuration register */ - -#define DMA_CCR_MEM2MEM_BIT 14 -#define DMA_CCR_MINC_BIT 7 -#define DMA_CCR_PINC_BIT 6 -#define DMA_CCR_CIRC_BIT 5 -#define DMA_CCR_DIR_BIT 4 -#define DMA_CCR_TEIE_BIT 3 -#define DMA_CCR_HTIE_BIT 2 -#define DMA_CCR_TCIE_BIT 1 -#define DMA_CCR_EN_BIT 0 - -#define DMA_CCR_MEM2MEM BIT(DMA_CCR_MEM2MEM_BIT) -#define DMA_CCR_PL (0x3 << 12) -#define DMA_CCR_PL_LOW (0x0 << 12) -#define DMA_CCR_PL_MEDIUM (0x1 << 12) -#define DMA_CCR_PL_HIGH (0x2 << 12) -#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) -#define DMA_CCR_MSIZE (0x3 << 10) -#define DMA_CCR_MSIZE_8BITS (0x0 << 10) -#define DMA_CCR_MSIZE_16BITS (0x1 << 10) -#define DMA_CCR_MSIZE_32BITS (0x2 << 10) -#define DMA_CCR_PSIZE (0x3 << 8) -#define DMA_CCR_PSIZE_8BITS (0x0 << 8) -#define DMA_CCR_PSIZE_16BITS (0x1 << 8) -#define DMA_CCR_PSIZE_32BITS (0x2 << 8) -#define DMA_CCR_MINC BIT(DMA_CCR_MINC_BIT) -#define DMA_CCR_PINC BIT(DMA_CCR_PINC_BIT) -#define DMA_CCR_CIRC BIT(DMA_CCR_CIRC_BIT) -#define DMA_CCR_DIR BIT(DMA_CCR_DIR_BIT) -#define DMA_CCR_TEIE BIT(DMA_CCR_TEIE_BIT) -#define DMA_CCR_HTIE BIT(DMA_CCR_HTIE_BIT) -#define DMA_CCR_TCIE BIT(DMA_CCR_TCIE_BIT) -#define DMA_CCR_EN BIT(DMA_CCR_EN_BIT) - -/* - * Devices - */ - -/** Encapsulates state related to a DMA channel interrupt. */ -typedef struct dma_handler_config { - void (*handler)(void); /**< User-specified channel interrupt - handler */ - nvic_irq_num irq_line; /**< Channel's NVIC interrupt number */ -} dma_handler_config; - -/** DMA device type */ -typedef struct dma_dev { - dma_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< Clock ID */ - dma_handler_config handlers[]; /**< - * @brief IRQ handlers and NVIC numbers. - * - * @see dma_attach_interrupt() - * @see dma_detach_interrupt() - */ -} dma_dev; - -extern dma_dev *DMA1; -#ifdef STM32_HIGH_DENSITY -extern dma_dev *DMA2; -#endif - -/* - * Convenience functions - */ - -void dma_init(dma_dev *dev); - -/** Flags for DMA transfer configuration. */ -typedef enum dma_mode_flags { - DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ - DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ - DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ - DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ - DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ - DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ - DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ - DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ -} dma_mode_flags; - -/** Source and destination transfer sizes. */ -typedef enum dma_xfer_size { - DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ - DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ - DMA_SIZE_32BITS = 2 /**< 32-bit transfers */ -} dma_xfer_size; - -/** DMA channel */ -typedef enum dma_channel { - DMA_CH1 = 1, /**< Channel 1 */ - DMA_CH2 = 2, /**< Channel 2 */ - DMA_CH3 = 3, /**< Channel 3 */ - DMA_CH4 = 4, /**< Channel 4 */ - DMA_CH5 = 5, /**< Channel 5 */ - DMA_CH6 = 6, /**< Channel 6 */ - DMA_CH7 = 7, /**< Channel 7 */ -} dma_channel; - -void dma_setup_transfer(dma_dev *dev, - dma_channel channel, - __io void *peripheral_address, - dma_xfer_size peripheral_size, - __io void *memory_address, - dma_xfer_size memory_size, - uint32 mode); - -void dma_set_num_transfers(dma_dev *dev, - dma_channel channel, - uint16 num_transfers); - -/** DMA transfer priority. */ -typedef enum dma_priority { - DMA_PRIORITY_LOW = DMA_CCR_PL_LOW, /**< Low priority */ - DMA_PRIORITY_MEDIUM = DMA_CCR_PL_MEDIUM, /**< Medium priority */ - DMA_PRIORITY_HIGH = DMA_CCR_PL_HIGH, /**< High priority */ - DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */ -} dma_priority; - -void dma_set_priority(dma_dev *dev, - dma_channel channel, - dma_priority priority); - -void dma_attach_interrupt(dma_dev *dev, - dma_channel channel, - void (*handler)(void)); -void dma_detach_interrupt(dma_dev *dev, dma_channel channel); - -/** - * Encodes the reason why a DMA interrupt was called. - * @see dma_get_irq_cause() - */ -typedef enum dma_irq_cause { - DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ - DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ - DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ -} dma_irq_cause; - -dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel); - -void dma_enable(dma_dev *dev, dma_channel channel); -void dma_disable(dma_dev *dev, dma_channel channel); - -void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address); -void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address); - -/** - * @brief DMA channel register map type. - * - * Provides access to an individual channel's registers. - */ -typedef struct dma_channel_reg_map { - __io uint32 CCR; /**< Channel configuration register */ - __io uint32 CNDTR; /**< Channel number of data register */ - __io uint32 CPAR; /**< Channel peripheral address register */ - __io uint32 CMAR; /**< Channel memory address register */ -} dma_channel_reg_map; - -#define DMA_CHANNEL_NREGS 5 - -/** - * @brief Obtain a pointer to an individual DMA channel's registers. - * - * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. - * - * @param dev DMA device - * @param channel DMA channel whose channel register map to obtain. - */ -static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev, - dma_channel channel) { - __io uint32 *ccr1 = &dev->regs->CCR1; - return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1)); -} - -/** - * @brief Check if a DMA channel is enabled - * @param dev DMA device - * @param channel Channel whose enabled bit to check. - */ -static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) { - return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN); -} - -/** - * @brief Get the ISR status bits for a DMA channel. - * - * The bits are returned right-aligned, in the following order: - * transfer error flag, half-transfer flag, transfer complete flag, - * global interrupt flag. - * - * If you're attempting to figure out why a DMA interrupt fired; you - * may find dma_get_irq_cause() more convenient. - * - * @param dev DMA device - * @param channel Channel whose ISR bits to return. - * @see dma_get_irq_cause(). - */ -static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) { - uint8 shift = (channel - 1) * 4; - return (dev->regs->ISR >> shift) & 0xF; -} - -/** - * @brief Clear the ISR status bits for a given DMA channel. - * - * If you're attempting to clean up after yourself in a DMA interrupt, - * you may find dma_get_irq_cause() more convenient. - * - * @param dev DMA device - * @param channel Channel whose ISR bits to clear. - * @see dma_get_irq_cause() - */ -static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) { - dev->regs->IFCR = BIT(4 * (channel - 1)); -} - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/exti.c b/libmaple/exti.c index 1fcc35b..00e0df2 100644 --- a/libmaple/exti.c +++ b/libmaple/exti.c @@ -29,10 +29,10 @@ * @brief External interrupt control routines */ -#include "exti.h" -#include "libmaple.h" -#include "nvic.h" -#include "bitband.h" +#include +#include +#include +#include static inline void dispatch_single_exti(uint32 exti_num); static inline void dispatch_extis(uint32 start, uint32 stop); diff --git a/libmaple/exti.h b/libmaple/exti.h deleted file mode 100644 index f225844..0000000 --- a/libmaple/exti.h +++ /dev/null @@ -1,74 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file exti.h - * @brief External interrupt control prototypes and defines - */ - -/* See notes/exti.txt for more info */ - -#include "libmaple.h" -#include "gpio.h" - -#ifndef _EXTI_H_ -#define _EXTI_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -/** EXTI register map type */ -typedef struct exti_reg_map { - __io uint32 IMR; /**< Interrupt mask register */ - __io uint32 EMR; /**< Event mask register */ - __io uint32 RTSR; /**< Rising trigger selection register */ - __io uint32 FTSR; /**< Falling trigger selection register */ - __io uint32 SWIER; /**< Software interrupt event register */ - __io uint32 PR; /**< Pending register */ -} exti_reg_map; - -/** EXTI register map base pointer */ -#define EXTI_BASE ((struct exti_reg_map*)0x40010400) - -/** External interrupt trigger mode */ -typedef enum exti_trigger_mode { - EXTI_RISING, /**< Trigger on the rising edge */ - EXTI_FALLING, /**< Trigger on the falling edge */ - EXTI_RISING_FALLING /**< Trigger on both the rising and falling edges */ -} exti_trigger_mode; - -void exti_attach_interrupt(afio_exti_num num, - afio_exti_port port, - voidFuncPtr handler, - exti_trigger_mode mode); -void exti_detach_interrupt(afio_exti_num num); - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/flash.c b/libmaple/flash.c index a22fbd3..d0e23d0 100644 --- a/libmaple/flash.c +++ b/libmaple/flash.c @@ -29,9 +29,9 @@ * @brief Flash management functions */ -#include "libmaple.h" -#include "flash.h" -#include "bitband.h" +#include +#include +#include /** * @brief Turn on the hardware prefetcher. diff --git a/libmaple/flash.h b/libmaple/flash.h deleted file mode 100644 index 0b4e49b..0000000 --- a/libmaple/flash.h +++ /dev/null @@ -1,142 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file flash.h - * @brief STM32 Medium and high density Flash register map and setup - * routines - */ - -#include "libmaple_types.h" - -#ifndef _FLASH_H_ -#define _FLASH_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -/** Flash register map type */ -typedef struct flash_reg_map { - __io uint32 ACR; /**< Access control register */ - __io uint32 KEYR; /**< Key register */ - __io uint32 OPTKEYR; /**< OPTKEY register */ - __io uint32 SR; /**< Status register */ - __io uint32 CR; /**< Control register */ - __io uint32 AR; /**< Address register */ - __io uint32 OBR; /**< Option byte register */ - __io uint32 WRPR; /**< Write protection register */ -} flash_reg_map; - -/** Flash register map base pointer */ -#define FLASH_BASE ((struct flash_reg_map*)0x40022000) - -/* - * Register bit definitions - */ - -/* Access control register */ - -#define FLASH_ACR_PRFTBS_BIT 5 -#define FLASH_ACR_PRFTBE_BIT 4 -#define FLASH_ACR_HLFCYA_BIT 3 - -#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) -#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) -#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) -#define FLASH_ACR_LATENCY 0x7 - -/* Status register */ - -#define FLASH_SR_EOP_BIT 5 -#define FLASH_SR_WRPRTERR_BIT 4 -#define FLASH_SR_PGERR_BIT 2 -#define FLASH_SR_BSY_BIT 0 - -#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) -#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) -#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) -#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) - -/* Control register */ - -#define FLASH_CR_EOPIE_BIT 12 -#define FLASH_CR_ERRIE_BIT 10 -#define FLASH_CR_OPTWRE_BIT 9 -#define FLASH_CR_LOCK_BIT 7 -#define FLASH_CR_STRT_BIT 6 -#define FLASH_CR_OPTER_BIT 5 -#define FLASH_CR_OPTPG_BIT 4 -#define FLASH_CR_MER_BIT 2 -#define FLASH_CR_PER_BIT 1 -#define FLASH_CR_PG_BIT 0 - -#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) -#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) -#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) -#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) -#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) -#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) -#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) -#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) -#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) -#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) - -/* Option byte register */ - -#define FLASH_OBR_nRST_STDBY_BIT 4 -#define FLASH_OBR_nRST_STOP_BIT 3 -#define FLASH_OBR_WDG_SW_BIT 2 -#define FLASH_OBR_RDPRT_BIT 1 -#define FLASH_OBR_OPTERR_BIT 0 - -#define FLASH_OBR_DATA1 (0xFF << 18) -#define FLASH_OBR_DATA0 (0xFF << 10) -#define FLASH_OBR_USER 0x3FF -#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) -#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) -#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) -#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) -#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) - -/* - * Setup routines - */ - -#define FLASH_WAIT_STATE_0 0x0 -#define FLASH_WAIT_STATE_1 0x1 -#define FLASH_WAIT_STATE_2 0x2 - -void flash_enable_prefetch(void); -void flash_set_latency(uint32 wait_states); - -#ifdef __cplusplus -} -#endif - -#endif - - diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c index 06ca7df..bf4611d 100644 --- a/libmaple/fsmc.c +++ b/libmaple/fsmc.c @@ -29,8 +29,8 @@ * @brief Flexible static memory controller support. */ -#include "fsmc.h" -#include "gpio.h" +#include +#include #ifdef STM32_HIGH_DENSITY diff --git a/libmaple/fsmc.h b/libmaple/fsmc.h deleted file mode 100644 index ef82b08..0000000 --- a/libmaple/fsmc.h +++ /dev/null @@ -1,320 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Bryan Newbold. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file fsmc.h - * @brief Flexible static memory controller support. - */ - -/* - * See ../notes/fsmc.txt for more info - */ - -#include "libmaple_types.h" - -/** - * @file fsmc.h - */ - -#ifndef _FSMC_H_ -#define _FSMC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#ifdef STM32_HIGH_DENSITY - -/* - * Register maps and devices - */ - -/** FSMC register map type */ -typedef struct fsmc_reg_map { - __io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */ - __io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */ - __io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */ - __io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */ - __io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */ - __io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */ - __io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */ - __io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */ - const uint8 RESERVED1[64]; /**< Reserved */ - __io uint32 PCR2; /**< PC Card/NAND Flash control register 2 */ - __io uint32 SR2; /**< FIFO status and interrupt register 2 */ - __io uint32 PMEM2; /**< Common memory space timing register 2 */ - __io uint32 PATT2; /**< Attribute memory space timing register 2 */ - const uint8 RESERVED2[4]; /**< Reserved */ - __io uint32 ECCR2; /**< ECC result register 2 */ - const uint8 RESERVED3[2]; - __io uint32 PCR3; /**< PC Card/NAND Flash control register 3 */ - __io uint32 SR3; /**< FIFO status and interrupt register 3 */ - __io uint32 PMEM3; /**< Common memory space timing register 3 */ - __io uint32 PATT3; /**< Attribute memory space timing register 3 */ - const uint32 RESERVED4; /**< Reserved */ - __io uint32 ECCR3; /**< ECC result register 3 */ - const uint8 RESERVED5[8]; /**< Reserved */ - __io uint32 PCR4; /**< PC Card/NAND Flash control register 4 */ - __io uint32 SR4; /**< FIFO status and interrupt register 4 */ - __io uint32 PMEM4; /**< Common memory space timing register 4 */ - __io uint32 PATT4; /**< Attribute memory space timing register 4 */ - __io uint32 PIO4; /**< I/O space timing register 4 */ - const uint8 RESERVED6[80]; /**< Reserved */ - __io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */ - const uint32 RESERVED7; /**< Reserved */ - __io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */ - const uint32 RESERVED8; /**< Reserved */ - __io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */ - const uint32 RESERVED9; /**< Reserved */ - __io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */ -} __attribute__((packed)) fsmc_reg_map; - -#define __FSMCB 0xA0000000 - -/** FSMC register map base pointer */ -#define FSMC_BASE ((struct fsmc_reg_map*)__FSMCB) - -/** FSMC NOR/PSRAM register map type */ -typedef struct fsmc_nor_psram_reg_map { - __io uint32 BCR; /**< Chip-select control register */ - __io uint32 BTR; /**< Chip-select timing register */ - const uint8 RESERVED[252]; /**< Reserved */ - __io uint32 BWTR; /**< Write timing register */ -} fsmc_nor_psram_reg_map; - -/** FSMC NOR/PSRAM base pointer 1 */ -#define FSMC_NOR_PSRAM1_BASE ((struct fsmc_nor_psram_reg_map*)__FSMCB) - -/** FSMC NOR/PSRAM base pointer 2 */ -#define FSMC_NOR_PSRAM2_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x8)) - -/** FSMC NOR/PSRAM base pointer 3 */ -#define FSMC_NOR_PSRAM3_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x10)) - -/** FSMC NOR/PSRAM base pointer 4 */ -#define FSMC_NOR_PSRAM4_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x18)) - -/* - * Register bit definitions - */ - -/* NOR/PSRAM chip-select control registers */ - -#define FSMC_BCR_CBURSTRW_BIT 19 -#define FSMC_BCR_ASYNCWAIT_BIT 15 -#define FSMC_BCR_EXTMOD_BIT 14 -#define FSMC_BCR_WAITEN_BIT 13 -#define FSMC_BCR_WREN_BIT 12 -#define FSMC_BCR_WAITCFG_BIT 11 -#define FSMC_BCR_WRAPMOD_BIT 10 -#define FSMC_BCR_WAITPOL_BIT 9 -#define FSMC_BCR_BURSTEN_BIT 8 -#define FSMC_BCR_FACCEN_BIT 6 -#define FSMC_BCR_MUXEN_BIT 1 -#define FSMC_BCR_MBKEN_BIT 0 - -#define FSMC_BCR_CBURSTRW BIT(FSMC_BCR_CBURSTRW_BIT) -#define FSMC_BCR_ASYNCWAIT BIT(FSMC_BCR_ASYNCWAIT_BIT) -#define FSMC_BCR_EXTMOD BIT(FSMC_BCR_EXTMOD_BIT) -#define FSMC_BCR_WAITEN BIT(FSMC_BCR_WAITEN_BIT) -#define FSMC_BCR_WREN BIT(FSMC_BCR_WREN_BIT) -#define FSMC_BCR_WAITCFG BIT(FSMC_BCR_WAITCFG_BIT) -#define FSMC_BCR_WRAPMOD BIT(FSMC_BCR_WRAPMOD_BIT) -#define FSMC_BCR_WAITPOL BIT(FSMC_BCR_WAITPOL_BIT) -#define FSMC_BCR_BURSTEN BIT(FSMC_BCR_BURSTEN_BIT) -#define FSMC_BCR_FACCEN BIT(FSMC_BCR_FACCEN_BIT) -#define FSMC_BCR_MWID (0x3 << 4) -#define FSMC_BCR_MWID_8BITS (0x0 << 4) -#define FSMC_BCR_MWID_16BITS (0x1 << 4) -#define FSMC_BCR_MTYP (0x3 << 2) -#define FSMC_BCR_MTYP_SRAM (0x0 << 2) -#define FSMC_BCR_MTYP_PSRAM (0x1 << 2) -#define FSMC_BCR_MTYP_NOR_FLASH (0x2 << 2) -#define FSMC_BCR_MUXEN BIT(FSMC_BCR_MUXEN_BIT) -#define FSMC_BCR_MBKEN BIT(FSMC_BCR_MBKEN_BIT) - -/* SRAM/NOR-Flash chip-select timing registers */ - -#define FSMC_BTR_ACCMOD (0x3 << 28) -#define FSMC_BTR_ACCMOD_A (0x0 << 28) -#define FSMC_BTR_ACCMOD_B (0x1 << 28) -#define FSMC_BTR_ACCMOD_C (0x2 << 28) -#define FSMC_BTR_ACCMOD_D (0x3 << 28) -#define FSMC_BTR_DATLAT (0xF << 24) -#define FSMC_BTR_CLKDIV (0xF << 20) -#define FSMC_BTR_BUSTURN (0xF << 16) -#define FSMC_BTR_DATAST (0xFF << 8) -#define FSMC_BTR_ADDHLD (0xF << 4) -#define FSMC_BTR_ADDSET 0xF - -/* SRAM/NOR-Flash write timing registers */ - -#define FSMC_BWTR_ACCMOD (0x3 << 28) -#define FSMC_BWTR_ACCMOD_A (0x0 << 28) -#define FSMC_BWTR_ACCMOD_B (0x1 << 28) -#define FSMC_BWTR_ACCMOD_C (0x2 << 28) -#define FSMC_BWTR_ACCMOD_D (0x3 << 28) -#define FSMC_BWTR_DATLAT (0xF << 24) -#define FSMC_BWTR_CLKDIV (0xF << 20) -#define FSMC_BWTR_DATAST (0xFF << 8) -#define FSMC_BWTR_ADDHLD (0xF << 4) -#define FSMC_BWTR_ADDSET 0xF - -/* NAND Flash/PC Card controller registers */ - -#define FSMC_PCR_ECCEN_BIT 6 -#define FSMC_PCR_PTYP_BIT 3 -#define FSMC_PCR_PBKEN_BIT 2 -#define FSMC_PCR_PWAITEN_BIT 1 - -#define FSMC_PCR_ECCPS (0x7 << 17) -#define FSMC_PCR_ECCPS_256B (0x0 << 17) -#define FSMC_PCR_ECCPS_512B (0x1 << 17) -#define FSMC_PCR_ECCPS_1024B (0x2 << 17) -#define FSMC_PCR_ECCPS_2048B (0x3 << 17) -#define FSMC_PCR_ECCPS_4096B (0x4 << 17) -#define FSMC_PCR_ECCPS_8192B (0x5 << 17) -#define FSMC_PCR_TAR (0xF << 13) -#define FSMC_PCR_TCLR (0xF << 9) -#define FSMC_PCR_ECCEN BIT(FSMC_PCR_ECCEN_BIT) -#define FSMC_PCR_PWID (0x3 << 4) -#define FSMC_PCR_PWID_8BITS (0x0 << 4) -#define FSMC_PCR_PWID_16BITS (0x1 << 4) -#define FSMC_PCR_PTYP BIT(FSMC_PCR_PTYP_BIT) -#define FSMC_PCR_PTYP_PC_CF_PCMCIA (0x0 << FSMC_PCR_PTYP_BIT) -#define FSMC_PCR_PTYP_NAND (0x1 << FSMC_PCR_PTYP_BIT) -#define FSMC_PCR_PBKEN BIT(FSMC_PCR_PBKEN_BIT) -#define FSMC_PCR_PWAITEN BIT(FSMC_PCR_PWAITEN_BIT) - -/* FIFO status and interrupt registers */ - -#define FSMC_SR_FEMPT_BIT 6 -#define FSMC_SR_IFEN_BIT 5 -#define FSMC_SR_ILEN_BIT 4 -#define FSMC_SR_IREN_BIT 3 -#define FSMC_SR_IFS_BIT 2 -#define FSMC_SR_ILS_BIT 1 -#define FSMC_SR_IRS_BIT 0 - -#define FSMC_SR_FEMPT BIT(FSMC_SR_FEMPT_BIT) -#define FSMC_SR_IFEN BIT(FSMC_SR_IFEN_BIT) -#define FSMC_SR_ILEN BIT(FSMC_SR_ILEN_BIT) -#define FSMC_SR_IREN BIT(FSMC_SR_IREN_BIT) -#define FSMC_SR_IFS BIT(FSMC_SR_IFS_BIT) -#define FSMC_SR_ILS BIT(FSMC_SR_ILS_BIT) -#define FSMC_SR_IRS BIT(FSMC_SR_IRS_BIT) - -/* Common memory space timing registers */ - -#define FSMC_PMEM_MEMHIZ (0xFF << 24) -#define FSMC_PMEM_MEMHOLD (0xFF << 16) -#define FSMC_PMEM_MEMWAIT (0xFF << 8) -#define FSMC_PMEM_MEMSET 0xFF - -/* Attribute memory space timing registers */ - -#define FSMC_PATT_ATTHIZ (0xFF << 24) -#define FSMC_PATT_ATTHOLD (0xFF << 16) -#define FSMC_PATT_ATTWAIT (0xFF << 8) -#define FSMC_PATT_ATTSET 0xFF - -/* I/O space timing register 4 */ - -#define FSMC_PIO_IOHIZ (0xFF << 24) -#define FSMC_PIO_IOHOLD (0xFF << 16) -#define FSMC_PIO_IOWAIT (0xFF << 8) -#define FSMC_PIO_IOSET 0xFF - -/* - * Memory bank boundary addresses - */ - -/** Pointer to base address of FSMC memory bank 1 (split into 4 - * regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip) */ -#define FSMC_BANK1 ((void*)0x60000000) - -/** Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM) */ -#define FSMC_NOR_PSRAM_REGION1 FSMC_BANK1 - -/** Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM) */ -#define FSMC_NOR_PSRAM_REGION2 ((void*)0x64000000) - -/** Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM) */ -#define FSMC_NOR_PSRAM_REGION3 ((void*)0x68000000) - -/** Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM) */ -#define FSMC_NOR_PSRAM_REGION4 ((void*)0x6C000000) - -/** Pointer to base address of FSMC memory bank 2 (for NAND Flash) */ -#define FSMC_BANK2 ((void*)0x70000000) - -/** Pointer to base address of FSMC memory bank 3 (for NAND Flash) */ -#define FSMC_BANK3 ((void*)0x80000000) - -/** Pointer to base address of FSMC memory bank 4 (for PC card devices */ -#define FSMC_BANK4 ((void*)0x90000000) - -/* - * SRAM/NOR Flash routines - */ - -void fsmc_sram_init_gpios(void); - -/** - * Set the DATAST bits in the given NOR/PSRAM register map's - * chip-select timing register (FSMC_BTR). - * - * @param regs NOR Flash/PSRAM register map whose chip-select timing - * register to set. - * @param datast Value to use for DATAST bits. - */ -static inline void fsmc_nor_psram_set_datast(fsmc_nor_psram_reg_map *regs, - uint8 datast) { - regs->BTR &= ~FSMC_BTR_DATAST; - regs->BTR |= datast << 8; -} - -/** - * Set the ADDHLD bits in the given NOR/PSRAM register map's chip - * select timing register (FSMC_BTRx). - * - * @param regs NOR Flash/PSRAM register map whose chip-select timing - * register to set. - * @param addset Value to use for ADDSET bits. - */ -static inline void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map *regs, - uint8 addset) { - regs->BTR &= ~FSMC_BTR_ADDSET; - regs->BTR |= addset & 0xF; -} - -#endif /* STM32_HIGH_DENSITY */ - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif diff --git a/libmaple/gpio.c b/libmaple/gpio.c index e643873..e607595 100644 --- a/libmaple/gpio.c +++ b/libmaple/gpio.c @@ -29,8 +29,8 @@ * @brief GPIO initialization routine */ -#include "gpio.h" -#include "rcc.h" +#include +#include /* * GPIO devices diff --git a/libmaple/gpio.h b/libmaple/gpio.h deleted file mode 100644 index a7859a7..0000000 --- a/libmaple/gpio.h +++ /dev/null @@ -1,527 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. -*****************************************************************************/ - -/** - * @file gpio.h - * - * @brief General purpose I/O (GPIO) and Alternate Function I/O - * (AFIO) prototypes, defines, and inlined access functions. - */ - -#ifndef _GPIO_H_ -#define _GPIO_H_ - -#include "libmaple.h" -#include "rcc.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * GPIO register maps and devices - */ - -/** GPIO register map type */ -typedef struct gpio_reg_map { - __io uint32 CRL; /**< Port configuration register low */ - __io uint32 CRH; /**< Port configuration register high */ - __io uint32 IDR; /**< Port input data register */ - __io uint32 ODR; /**< Port output data register */ - __io uint32 BSRR; /**< Port bit set/reset register */ - __io uint32 BRR; /**< Port bit reset register */ - __io uint32 LCKR; /**< Port configuration lock register */ -} gpio_reg_map; - -/** - * @brief External interrupt line port selector. - * - * Used to determine which GPIO port to map an external interrupt line - * onto. */ -/* (See AFIO sections, below) */ -typedef enum afio_exti_port { - AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ - AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ - AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ - AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ -#ifdef STM32_HIGH_DENSITY - AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ - AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ - AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ -#endif -} afio_exti_port; - -/** GPIO device type */ -typedef struct gpio_dev { - gpio_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ - afio_exti_port exti_port; /**< AFIO external interrupt port value */ -} gpio_dev; - -extern gpio_dev gpioa; -extern gpio_dev* const GPIOA; -extern gpio_dev gpiob; -extern gpio_dev* const GPIOB; -extern gpio_dev gpioc; -extern gpio_dev* const GPIOC; -extern gpio_dev gpiod; -extern gpio_dev* const GPIOD; -#ifdef STM32_HIGH_DENSITY -extern gpio_dev gpioe; -extern gpio_dev* const GPIOE; -extern gpio_dev gpiof; -extern gpio_dev* const GPIOF; -extern gpio_dev gpiog; -extern gpio_dev* const GPIOG; -#endif - -/** GPIO port A register map base pointer */ -#define GPIOA_BASE ((struct gpio_reg_map*)0x40010800) -/** GPIO port B register map base pointer */ -#define GPIOB_BASE ((struct gpio_reg_map*)0x40010C00) -/** GPIO port C register map base pointer */ -#define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) -/** GPIO port D register map base pointer */ -#define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) -#ifdef STM32_HIGH_DENSITY -/** GPIO port E register map base pointer */ -#define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) -/** GPIO port F register map base pointer */ -#define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) -/** GPIO port G register map base pointer */ -#define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) -#endif - -/* - * GPIO register bit definitions - */ - -/* Control registers, low and high */ - -#define GPIO_CR_CNF (0x3 << 2) -#define GPIO_CR_CNF_INPUT_ANALOG (0x0 << 2) -#define GPIO_CR_CNF_INPUT_FLOATING (0x1 << 2) -#define GPIO_CR_CNF_INPUT_PU_PD (0x2 << 2) -#define GPIO_CR_CNF_OUTPUT_PP (0x0 << 2) -#define GPIO_CR_CNF_OUTPUT_OD (0x1 << 2) -#define GPIO_CR_CNF_AF_OUTPUT_PP (0x2 << 2) -#define GPIO_CR_CNF_AF_OUTPUT_OD (0x3 << 2) -#define GPIO_CR_MODE 0x3 -#define GPIO_CR_MODE_INPUT 0x0 -#define GPIO_CR_MODE_OUTPUT_10MHZ 0x1 -#define GPIO_CR_MODE_OUTPUT_2MHZ 0x2 -#define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 - -/** - * @brief GPIO Pin modes. - * - * These only allow for 50MHZ max output speeds; if you want slower, - * use direct register access. - */ -typedef enum gpio_pin_mode { - GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ - GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ - GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output push-pull. */ - GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output open drain. */ - GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | - GPIO_CR_MODE_INPUT), /**< Analog input. */ - GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | - GPIO_CR_MODE_INPUT), /**< Input floating. */ - GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | - GPIO_CR_MODE_INPUT), /**< Input pull-down. */ - GPIO_INPUT_PU /**< Input pull-up. */ - /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ -} gpio_pin_mode; - -/* - * GPIO Convenience routines - */ - -void gpio_init(gpio_dev *dev); -void gpio_init_all(void); -void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode); - -/** - * @brief Get a GPIO port's corresponding afio_exti_port. - * @param dev GPIO device whose afio_exti_port to return. - */ -static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { - return dev->exti_port; -} - -/** - * Set or reset a GPIO pin. - * - * Pin must have previously been configured to output mode. - * - * @param dev GPIO device whose pin to set. - * @param pin Pin on to set or reset - * @param val If true, set the pin. If false, reset the pin. - */ -static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) { - if (val) { - dev->regs->BSRR = BIT(pin); - } else { - dev->regs->BRR = BIT(pin); - } -} - -/** - * Determine whether or not a GPIO pin is set. - * - * Pin must have previously been configured to input mode. - * - * @param dev GPIO device whose pin to test. - * @param pin Pin on dev to test. - * @return True if the pin is set, false otherwise. - */ -static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) { - return dev->regs->IDR & BIT(pin); -} - -/** - * Toggle a pin configured as output push-pull. - * @param dev GPIO device. - * @param pin Pin on dev to toggle. - */ -static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) { - dev->regs->ODR = dev->regs->ODR ^ BIT(pin); -} - -/* - * AFIO register map - */ - -/** AFIO register map */ -typedef struct afio_reg_map { - __io uint32 EVCR; /**< Event control register. */ - __io uint32 MAPR; /**< AF remap and debug I/O configuration - register. */ - __io uint32 EXTICR1; /**< External interrupt configuration - register 1. */ - __io uint32 EXTICR2; /**< External interrupt configuration - register 2. */ - __io uint32 EXTICR3; /**< External interrupt configuration - register 3. */ - __io uint32 EXTICR4; /**< External interrupt configuration - register 4. */ - __io uint32 MAPR2; /**< AF remap and debug I/O configuration - register 2. */ -} afio_reg_map; - -/** AFIO register map base pointer. */ -#define AFIO_BASE ((struct afio_reg_map *)0x40010000) - -/* - * AFIO register bit definitions - */ - -/* Event control register */ - -#define AFIO_EVCR_EVOE (0x1 << 7) -#define AFIO_EVCR_PORT_PA (0x0 << 4) -#define AFIO_EVCR_PORT_PB (0x1 << 4) -#define AFIO_EVCR_PORT_PC (0x2 << 4) -#define AFIO_EVCR_PORT_PD (0x3 << 4) -#define AFIO_EVCR_PORT_PE (0x4 << 4) -#define AFIO_EVCR_PIN_0 0x0 -#define AFIO_EVCR_PIN_1 0x1 -#define AFIO_EVCR_PIN_2 0x2 -#define AFIO_EVCR_PIN_3 0x3 -#define AFIO_EVCR_PIN_4 0x4 -#define AFIO_EVCR_PIN_5 0x5 -#define AFIO_EVCR_PIN_6 0x6 -#define AFIO_EVCR_PIN_7 0x7 -#define AFIO_EVCR_PIN_8 0x8 -#define AFIO_EVCR_PIN_9 0x9 -#define AFIO_EVCR_PIN_10 0xA -#define AFIO_EVCR_PIN_11 0xB -#define AFIO_EVCR_PIN_12 0xC -#define AFIO_EVCR_PIN_13 0xD -#define AFIO_EVCR_PIN_14 0xE -#define AFIO_EVCR_PIN_15 0xF - -/* AF remap and debug I/O configuration register */ - -#define AFIO_MAPR_SWJ_CFG (0x7 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) -#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) -#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) -#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) -#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) -#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) -#define AFIO_MAPR_PD01_REMAP BIT(15) -#define AFIO_MAPR_CAN_REMAP (0x3 << 13) -#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) -#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) -#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) -#define AFIO_MAPR_TIM4_REMAP BIT(12) -#define AFIO_MAPR_TIM3_REMAP (0x3 << 10) -#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) -#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) -#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10) -#define AFIO_MAPR_TIM2_REMAP (0x3 << 8) -#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8) -#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8) -#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8) -#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8) -#define AFIO_MAPR_TIM1_REMAP (0x3 << 6) -#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6) -#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6) -#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6) -#define AFIO_MAPR_USART3_REMAP (0x3 << 4) -#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) -#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) -#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) -#define AFIO_MAPR_USART2_REMAP BIT(3) -#define AFIO_MAPR_USART1_REMAP BIT(2) -#define AFIO_MAPR_I2C1_REMAP BIT(1) -#define AFIO_MAPR_SPI1_REMAP BIT(0) - -/* External interrupt configuration register 1 */ - -#define AFIO_EXTICR1_EXTI3 (0xF << 12) -#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12) -#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12) -#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12) -#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12) -#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12) -#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12) -#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12) -#define AFIO_EXTICR1_EXTI2 (0xF << 8) -#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8) -#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8) -#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8) -#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8) -#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8) -#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8) -#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8) -#define AFIO_EXTICR1_EXTI1 (0xF << 4) -#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4) -#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4) -#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4) -#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4) -#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4) -#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4) -#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4) -#define AFIO_EXTICR1_EXTI0 0xF -#define AFIO_EXTICR1_EXTI0_PA 0x0 -#define AFIO_EXTICR1_EXTI0_PB 0x1 -#define AFIO_EXTICR1_EXTI0_PC 0x2 -#define AFIO_EXTICR1_EXTI0_PD 0x3 -#define AFIO_EXTICR1_EXTI0_PE 0x4 -#define AFIO_EXTICR1_EXTI0_PF 0x5 -#define AFIO_EXTICR1_EXTI0_PG 0x6 - -/* External interrupt configuration register 2 */ - -#define AFIO_EXTICR2_EXTI7 (0xF << 12) -#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12) -#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12) -#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12) -#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12) -#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12) -#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12) -#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12) -#define AFIO_EXTICR2_EXTI6 (0xF << 8) -#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8) -#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8) -#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8) -#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8) -#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8) -#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8) -#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8) -#define AFIO_EXTICR2_EXTI5 (0xF << 4) -#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4) -#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4) -#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4) -#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4) -#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4) -#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4) -#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4) -#define AFIO_EXTICR2_EXTI4 0xF -#define AFIO_EXTICR2_EXTI4_PA 0x0 -#define AFIO_EXTICR2_EXTI4_PB 0x1 -#define AFIO_EXTICR2_EXTI4_PC 0x2 -#define AFIO_EXTICR2_EXTI4_PD 0x3 -#define AFIO_EXTICR2_EXTI4_PE 0x4 -#define AFIO_EXTICR2_EXTI4_PF 0x5 -#define AFIO_EXTICR2_EXTI4_PG 0x6 - -/* AF remap and debug I/O configuration register 2 */ - -#define AFIO_MAPR2_FSMC_NADV BIT(10) -#define AFIO_MAPR2_TIM14_REMAP BIT(9) -#define AFIO_MAPR2_TIM13_REMAP BIT(8) -#define AFIO_MAPR2_TIM11_REMAP BIT(7) -#define AFIO_MAPR2_TIM10_REMAP BIT(6) -#define AFIO_MAPR2_TIM9_REMAP BIT(5) - -/* - * AFIO convenience routines - */ - -void afio_init(void); - -/** - * External interrupt line numbers. - */ -typedef enum afio_exti_num { - AFIO_EXTI_0, /**< External interrupt line 0. */ - AFIO_EXTI_1, /**< External interrupt line 1. */ - AFIO_EXTI_2, /**< External interrupt line 2. */ - AFIO_EXTI_3, /**< External interrupt line 3. */ - AFIO_EXTI_4, /**< External interrupt line 4. */ - AFIO_EXTI_5, /**< External interrupt line 5. */ - AFIO_EXTI_6, /**< External interrupt line 6. */ - AFIO_EXTI_7, /**< External interrupt line 7. */ - AFIO_EXTI_8, /**< External interrupt line 8. */ - AFIO_EXTI_9, /**< External interrupt line 9. */ - AFIO_EXTI_10, /**< External interrupt line 10. */ - AFIO_EXTI_11, /**< External interrupt line 11. */ - AFIO_EXTI_12, /**< External interrupt line 12. */ - AFIO_EXTI_13, /**< External interrupt line 13. */ - AFIO_EXTI_14, /**< External interrupt line 14. */ - AFIO_EXTI_15, /**< External interrupt line 15. */ -} afio_exti_num; - -void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); - -/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and - * not used in either MAPR or MAPR2 */ -#define AFIO_REMAP_USE_MAPR2 (1 << 31) - -/** - * @brief Available peripheral remaps. - * @see afio_remap() - */ -typedef enum afio_remap_peripheral { - AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< - ADC 2 external trigger regular conversion remapping */ - AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< - ADC 2 external trigger injected conversion remapping */ - AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< - ADC 1 external trigger regular conversion remapping */ - AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< - ADC 1 external trigger injected conversion remapping */ - AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< - Timer 5 channel 4 internal remapping */ - AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< - Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< - CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ - AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< - CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ - AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< - Timer 4 remapping */ - AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< - Timer 3 partial remapping */ - AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< - Timer 3 full remapping */ - AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< - Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 - on PA2, CH4 on PA3) */ - AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< - Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 - on PB10, CH4 on PB11) */ - AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< - Timer 2 full remapping */ - AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< - USART 2 remapping */ - AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< - USART 1 remapping */ - AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< - I2C 1 remapping */ - AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< - SPI 1 remapping */ - AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | - AFIO_REMAP_USE_MAPR2), /**< - NADV signal not connected */ - AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 14 remapping */ - AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 13 remapping */ - AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 11 remapping */ - AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 10 remapping */ - AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | - AFIO_REMAP_USE_MAPR2) /**< - Timer 9 */ -} afio_remap_peripheral; - -void afio_remap(afio_remap_peripheral p); - -/** - * @brief Debug port configuration - * - * Used to configure the behavior of JTAG and Serial Wire (SW) debug - * ports and their associated GPIO pins. - * - * @see afio_cfg_debug_ports() - */ -typedef enum afio_debug_cfg { - AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< - Full Serial Wire and JTAG debug */ - AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< - Full Serial Wire and JTAG, but no NJTRST. */ - AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< - Serial Wire debug only (JTAG-DP disabled, - SW-DP enabled) */ - AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< - No debug; all JTAG and SW pins are free - for use as GPIOs. */ -} afio_debug_cfg; - -/** - * @brief Enable or disable the JTAG and SW debug ports. - * @param config Desired debug port configuration - * @see afio_debug_cfg - */ -static inline void afio_cfg_debug_ports(afio_debug_cfg config) { - __io uint32 *mapr = &AFIO_BASE->MAPR; - *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; -} - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/libmaple/i2c.c b/libmaple/i2c.c index e3f3199..ae44532 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -31,13 +31,14 @@ * Currently, only master mode is supported. */ -#include "libmaple.h" -#include "rcc.h" -#include "gpio.h" -#include "nvic.h" -#include "i2c.h" -#include "string.h" -#include "systick.h" +#include +#include +#include +#include +#include +#include + +#include static i2c_dev i2c_dev1 = { .regs = I2C1_BASE, diff --git a/libmaple/i2c.h b/libmaple/i2c.h deleted file mode 100644 index 4c60ad7..0000000 --- a/libmaple/i2c.h +++ /dev/null @@ -1,348 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file i2c.h - * @brief Inter-Integrated Circuit (I2C) peripheral support - */ - -#include "libmaple_types.h" -#include "rcc.h" -#include "nvic.h" -#include "gpio.h" - -#ifndef _I2C_H_ -#define _I2C_H_ - -/** I2C register map type */ -typedef struct i2c_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 OAR1; /**< Own address register 1 */ - __io uint32 OAR2; /**< Own address register 2 */ - __io uint32 DR; /**< Data register */ - __io uint32 SR1; /**< Status register 1 */ - __io uint32 SR2; /**< Status register 2 */ - __io uint32 CCR; /**< Clock control register */ - __io uint32 TRISE; /**< TRISE (rise time) register */ -} i2c_reg_map; - -/** I2C device states */ -typedef enum i2c_state { - I2C_STATE_DISABLED = 0, /**< Disabled */ - I2C_STATE_IDLE = 1, /**< Idle */ - I2C_STATE_XFER_DONE = 2, /**< Done with transfer */ - I2C_STATE_BUSY = 3, /**< Busy */ - I2C_STATE_ERROR = -1 /**< Error occurred */ -} i2c_state; - -/** - * @brief I2C message type - */ -typedef struct i2c_msg { - uint16 addr; /**< Address */ -#define I2C_MSG_READ 0x1 -#define I2C_MSG_10BIT_ADDR 0x2 - uint16 flags; /**< Bitwise OR of I2C_MSG_READ and - I2C_MSG_10BIT_ADDR */ - uint16 length; /**< Message length */ - uint16 xferred; /**< Messages transferred */ - uint8 *data; /**< Data */ -} i2c_msg; - -/** - * @brief I2C device type. - */ -typedef struct i2c_dev { - i2c_reg_map *regs; /**< Register map */ - gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ - uint8 sda_pin; /**< SDA bit on gpio_port */ - uint8 scl_pin; /**< SCL bit on gpio_port */ - rcc_clk_id clk_id; /**< RCC clock information */ - nvic_irq_num ev_nvic_line; /**< Event IRQ number */ - nvic_irq_num er_nvic_line; /**< Error IRQ number */ - volatile i2c_state state; /**< Device state */ - uint16 msgs_left; /**< Messages left */ - i2c_msg *msg; /**< Messages */ - volatile uint32 timestamp; /**< For internal use */ - uint32 error_flags; /**< Error flags, set on I2C error condition */ -} i2c_dev; - -/* - * Devices - */ - -extern i2c_dev* const I2C1; -extern i2c_dev* const I2C2; - -/* - * Register map base pointers - */ - -/** I2C1 register map base pointer */ -#define I2C1_BASE ((struct i2c_reg_map*)0x40005400) -/** I2C2 register map base pointer */ -#define I2C2_BASE ((struct i2c_reg_map*)0x40005800) - -/* - * Register bit definitions - */ - -/* Control register 1 */ - -#define I2C_CR1_SWRST BIT(15) // Software reset -#define I2C_CR1_ALERT BIT(13) // SMBus alert -#define I2C_CR1_PEC BIT(12) // Packet error checking -#define I2C_CR1_POS BIT(11) // Acknowledge/PEC position -#define I2C_CR1_ACK BIT(10) // Acknowledge enable -#define I2C_CR1_START BIT(8) // Start generation -#define I2C_CR1_STOP BIT(9) // Stop generation -#define I2C_CR1_PE BIT(0) // Peripheral Enable - -/* Control register 2 */ - -#define I2C_CR2_LAST BIT(12) // DMA last transfer -#define I2C_CR2_DMAEN BIT(11) // DMA requests enable -#define I2C_CR2_ITBUFEN BIT(10) // Buffer interrupt enable -#define I2C_CR2_ITEVTEN BIT(9) // Event interupt enable -#define I2C_CR2_ITERREN BIT(8) // Error interupt enable -#define I2C_CR2_FREQ 0xFFF // Peripheral input frequency - -/* Clock control register */ - -#define I2C_CCR_FS BIT(15) // Fast mode selection -#define I2C_CCR_DUTY BIT(14) // 16/9 duty ratio -#define I2C_CCR_CCR 0xFFF // Clock control bits - -/* Status register 1 */ - -#define I2C_SR1_SB BIT(0) // Start bit -#define I2C_SR1_ADDR BIT(1) // Address sent/matched -#define I2C_SR1_BTF BIT(2) // Byte transfer finished -#define I2C_SR1_ADD10 BIT(3) // 10-bit header sent -#define I2C_SR1_STOPF BIT(4) // Stop detection -#define I2C_SR1_RXNE BIT(6) // Data register not empty -#define I2C_SR1_TXE BIT(7) // Data register empty -#define I2C_SR1_BERR BIT(8) // Bus error -#define I2C_SR1_ARLO BIT(9) // Arbitration lost -#define I2C_SR1_AF BIT(10) // Acknowledge failure -#define I2C_SR1_OVR BIT(11) // Overrun/underrun -#define I2C_SR1_PECERR BIT(12) // PEC Error in reception -#define I2C_SR1_TIMEOUT BIT(14) // Timeout or Tlow error -#define I2C_SR1_SMBALERT BIT(15) // SMBus alert - -/* Status register 2 */ - -#define I2C_SR2_MSL BIT(0) // Master/slave -#define I2C_SR2_BUSY BIT(1) // Bus busy -#define I2C_SR2_TRA BIT(2) // Transmitter/receiver -#define I2C_SR2_GENCALL BIT(4) // General call address -#define I2C_SR2_SMBDEFAULT BIT(5) // SMBus device default address -#define I2C_SR2_SMBHOST BIT(6) // SMBus host header -#define I2C_SR2_DUALF BIT(7) // Dual flag -#define I2C_SR2_PEC 0xFF00 // Packet error checking register - -/* - * Convenience routines - */ - -#ifdef __cplusplus -extern "C" { -#endif - -void i2c_init(i2c_dev *dev); - -/* I2C enable options */ -#define I2C_FAST_MODE BIT(0) // 400 khz -#define I2C_DUTY_16_9 BIT(1) // 16/9 duty ratio -#define I2C_REMAP BIT(2) // Use alternate pin mapping -#define I2C_BUS_RESET BIT(3) // Perform a bus reset -void i2c_master_enable(i2c_dev *dev, uint32 flags); - -#define I2C_ERROR_PROTOCOL (-1) -#define I2C_ERROR_TIMEOUT (-2) -int32 i2c_master_xfer(i2c_dev *dev, i2c_msg *msgs, uint16 num, uint32 timeout); - -void i2c_bus_reset(const i2c_dev *dev); - -/** - * @brief Disable an I2C device - * - * This function disables the corresponding peripheral and marks dev's - * state as I2C_STATE_DISABLED. - * - * @param dev Device to disable. - */ -static inline void i2c_disable(i2c_dev *dev) { - dev->regs->CR1 &= ~I2C_CR1_PE; - dev->state = I2C_STATE_DISABLED; -} - -/** - * @brief Turn on an I2C peripheral - * @param dev Device to enable - */ -static inline void i2c_peripheral_enable(i2c_dev *dev) { - dev->regs->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Turn off an I2C peripheral - * @param dev Device to turn off - */ -static inline void i2c_peripheral_disable(i2c_dev *dev) { - dev->regs->CR1 &= ~I2C_CR1_PE; -} - -/** - * @brief Fill transmit register - * @param dev I2C device - * @param byte Byte to write - */ -static inline void i2c_write(i2c_dev *dev, uint8 byte) { - dev->regs->DR = byte; -} - -/** - * @brief Set input clock frequency, in MHz - * @param dev I2C device - * @param freq Frequency in megahertz (2-36) - */ -static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) { - uint32 cr2 = dev->regs->CR2; - cr2 &= ~I2C_CR2_FREQ; - cr2 |= freq; - dev->regs->CR2 = freq; -} - -/** - * @brief Set I2C clock control register. See RM008 - * @param dev I2C device - * @param val Value to use for clock control register (in - * Fast/Standard mode) - */ -static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) { - uint32 ccr = dev->regs->CCR; - ccr &= ~I2C_CCR_CCR; - ccr |= val; - dev->regs->CCR = ccr; -} - - -/** - * @brief Set SCL rise time - * @param dev I2C device - * @param trise Maximum rise time in fast/standard mode (see RM0008 - * for relevant formula). - */ -static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) { - dev->regs->TRISE = trise; -} - - -/** - * @brief Generate a start condition on the bus. - * @param dev I2C device - */ -static inline void i2c_start_condition(i2c_dev *dev) { - uint32 cr1; - while ((cr1 = dev->regs->CR1) & (I2C_CR1_START | - I2C_CR1_STOP | - I2C_CR1_PEC)) { - ; - } - dev->regs->CR1 |= I2C_CR1_START; -} - -/** - * @brief Generate a stop condition on the bus - * @param dev I2C device - */ -static inline void i2c_stop_condition(i2c_dev *dev) { - uint32 cr1; - while ((cr1 = dev->regs->CR1) & (I2C_CR1_START | - I2C_CR1_STOP | - I2C_CR1_PEC)) { - ; - } - dev->regs->CR1 |= I2C_CR1_STOP; - while ((cr1 = dev->regs->CR1) & (I2C_CR1_START | - I2C_CR1_STOP | - I2C_CR1_PEC)) { - ; - } - -} - -/** - * @brief Enable one or more I2C interrupts - * @param dev I2C device - * @param irqs Bitwise or of: - * I2C_IRQ_ERROR (error interrupt), - * I2C_IRQ_EVENT (event interrupt), and - * I2C_IRQ_BUFFER (buffer interrupt). - */ -#define I2C_IRQ_ERROR I2C_CR2_ITERREN -#define I2C_IRQ_EVENT I2C_CR2_ITEVTEN -#define I2C_IRQ_BUFFER I2C_CR2_ITBUFEN -static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) { - dev->regs->CR2 |= irqs; -} - -/** - * @brief Disable one or more I2C interrupts - * @param dev I2C device - * @param irqs Bitwise or of: - * I2C_IRQ_ERROR (error interrupt), - * I2C_IRQ_EVENT (event interrupt), and - * I2C_IRQ_BUFFER (buffer interrupt). - */ -static inline void i2c_disable_irq(i2c_dev *dev, uint32 irqs) { - dev->regs->CR2 &= ~irqs; -} - - -/** - * @brief Enable I2C acknowledgment - * @param dev I2C device - */ -static inline void i2c_enable_ack(i2c_dev *dev) { - dev->regs->CR1 |= I2C_CR1_ACK; -} - -/** - * @brief Disable I2C acknowledgment - * @param dev I2C device - */ -static inline void i2c_disable_ack(i2c_dev *dev) { - dev->regs->CR1 &= ~I2C_CR1_ACK; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/include/libmaple/adc.h b/libmaple/include/libmaple/adc.h new file mode 100644 index 0000000..d531d00 --- /dev/null +++ b/libmaple/include/libmaple/adc.h @@ -0,0 +1,364 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file adc.h + * + * @brief Analog-to-Digital Conversion (ADC) header. + */ + +#ifndef _LIBMAPLE_ADC_H_ +#define _LIBMAPLE_ADC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include + +/** ADC register map type. */ +typedef struct adc_reg_map { + __io uint32 SR; ///< Status register + __io uint32 CR1; ///< Control register 1 + __io uint32 CR2; ///< Control register 2 + __io uint32 SMPR1; ///< Sample time register 1 + __io uint32 SMPR2; ///< Sample time register 2 + __io uint32 JOFR1; ///< Injected channel data offset register 1 + __io uint32 JOFR2; ///< Injected channel data offset register 2 + __io uint32 JOFR3; ///< Injected channel data offset register 3 + __io uint32 JOFR4; ///< Injected channel data offset register 4 + __io uint32 HTR; ///< Watchdog high threshold register + __io uint32 LTR; ///< Watchdog low threshold register + __io uint32 SQR1; ///< Regular sequence register 1 + __io uint32 SQR2; ///< Regular sequence register 2 + __io uint32 SQR3; ///< Regular sequence register 3 + __io uint32 JSQR; ///< Injected sequence register + __io uint32 JDR1; ///< Injected data register 1 + __io uint32 JDR2; ///< Injected data register 2 + __io uint32 JDR3; ///< Injected data register 3 + __io uint32 JDR4; ///< Injected data register 4 + __io uint32 DR; ///< Regular data register +} adc_reg_map; + +/** ADC device type. */ +typedef struct adc_dev { + adc_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ +} adc_dev; + +extern const adc_dev *ADC1; +extern const adc_dev *ADC2; +#ifdef STM32_HIGH_DENSITY +extern const adc_dev *ADC3; +#endif + +/* + * Register map base pointers + */ + +/** ADC1 register map base pointer. */ +#define ADC1_BASE ((struct adc_reg_map*)0x40012400) +/** ADC2 register map base pointer. */ +#define ADC2_BASE ((struct adc_reg_map*)0x40012800) +#ifdef STM32_HIGH_DENSITY +/** ADC3 register map base pointer. */ +#define ADC3_BASE ((struct adc_reg_map*)0x40013C00) +#endif + +/* + * Register bit definitions + */ + +/* Status register */ + +#define ADC_SR_AWD_BIT 0 +#define ADC_SR_EOC_BIT 1 +#define ADC_SR_JEOC_BIT 2 +#define ADC_SR_JSTRT_BIT 3 +#define ADC_SR_STRT_BIT 4 + +#define ADC_SR_AWD BIT(ADC_SR_AWD_BIT) +#define ADC_SR_EOC BIT(ADC_SR_EOC_BIT) +#define ADC_SR_JEOC BIT(ADC_SR_JEOC_BIT) +#define ADC_SR_JSTRT BIT(ADC_SR_JSTRT_BIT) +#define ADC_SR_STRT BIT(ADC_SR_STRT_BIT) + +/* Control register 1 */ + +#define ADC_CR1_EOCIE_BIT 5 +#define ADC_CR1_AWDIE_BIT 6 +#define ADC_CR1_JEOCIE_BIT 7 +#define ADC_CR1_SCAN_BIT 8 +#define ADC_CR1_AWDSGL_BIT 9 +#define ADC_CR1_JAUTO_BIT 10 +#define ADC_CR1_DISCEN_BIT 11 +#define ADC_CR1_JDISCEN_BIT 12 +#define ADC_CR1_JAWDEN_BIT 22 +#define ADC_CR1_AWDEN_BIT 23 + +#define ADC_CR1_AWDCH (0x1F) +#define ADC_CR1_EOCIE BIT(ADC_CR1_EOCIE_BIT) +#define ADC_CR1_AWDIE BIT(ADC_CR1_AWDIE_BIT) +#define ADC_CR1_JEOCIE BIT(ADC_CR1_JEOCIE_BIT) +#define ADC_CR1_SCAN BIT(ADC_CR1_SCAN_BIT) +#define ADC_CR1_AWDSGL BIT(ADC_CR1_AWDSGL_BIT) +#define ADC_CR1_JAUTO BIT(ADC_CR1_JAUTO_BIT) +#define ADC_CR1_DISCEN BIT(ADC_CR1_DISCEN_BIT) +#define ADC_CR1_JDISCEN BIT(ADC_CR1_JDISCEN_BIT) +#define ADC_CR1_DISCNUM (0xE000) +#define ADC_CR1_JAWDEN BIT(ADC_CR1_JAWDEN_BIT) +#define ADC_CR1_AWDEN BIT(ADC_CR1_AWDEN_BIT) + +/* Control register 2 */ + +#define ADC_CR2_ADON_BIT 0 +#define ADC_CR2_CONT_BIT 1 +#define ADC_CR2_CAL_BIT 2 +#define ADC_CR2_RSTCAL_BIT 3 +#define ADC_CR2_DMA_BIT 8 +#define ADC_CR2_ALIGN_BIT 11 +#define ADC_CR2_JEXTTRIG_BIT 15 +#define ADC_CR2_EXTTRIG_BIT 20 +#define ADC_CR2_JSWSTART_BIT 21 +#define ADC_CR2_SWSTART_BIT 22 +#define ADC_CR2_TSEREFE_BIT 23 + +#define ADC_CR2_ADON BIT(ADC_CR2_ADON_BIT) +#define ADC_CR2_CONT BIT(ADC_CR2_CONT_BIT) +#define ADC_CR2_CAL BIT(ADC_CR2_CAL_BIT) +#define ADC_CR2_RSTCAL BIT(ADC_CR2_RSTCAL_BIT) +#define ADC_CR2_DMA BIT(ADC_CR2_DMA_BIT) +#define ADC_CR2_ALIGN BIT(ADC_CR2_ALIGN_BIT) +#define ADC_CR2_JEXTSEL (0x7000) +#define ADC_CR2_JEXTTRIG BIT(ADC_CR2_JEXTTRIG_BIT) +#define ADC_CR2_EXTSEL (0xE0000) +#define ADC_CR2_EXTTRIG BIT(ADC_CR2_EXTTRIG_BIT) +#define ADC_CR2_JSWSTART BIT(ADC_CR2_JSWSTART_BIT) +#define ADC_CR2_SWSTART BIT(ADC_CR2_SWSTART_BIT) +#define ADC_CR2_TSEREFE BIT(ADC_CR2_TSEREFE_BIT) + +/* Sample time register 1 */ + +#define ADC_SMPR1_SMP17 (0x7 << 21) +#define ADC_SMPR1_SMP16 (0x7 << 18) +#define ADC_SMPR1_SMP15 (0x7 << 15) +#define ADC_SMPR1_SMP14 (0x7 << 12) +#define ADC_SMPR1_SMP13 (0x7 << 9) +#define ADC_SMPR1_SMP12 (0x7 << 6) +#define ADC_SMPR1_SMP11 (0x7 << 3) +#define ADC_SMPR1_SMP10 0x7 + +/* Sample time register 2 */ + +#define ADC_SMPR2_SMP9 (0x7 << 27) +#define ADC_SMPR2_SMP8 (0x7 << 24) +#define ADC_SMPR2_SMP7 (0x7 << 21) +#define ADC_SMPR2_SMP6 (0x7 << 18) +#define ADC_SMPR2_SMP5 (0x7 << 15) +#define ADC_SMPR2_SMP4 (0x7 << 12) +#define ADC_SMPR2_SMP3 (0x7 << 9) +#define ADC_SMPR2_SMP2 (0x7 << 6) +#define ADC_SMPR2_SMP1 (0x7 << 3) +#define ADC_SMPR2_SMP0 0x7 + +/* Injected channel data offset register */ + +#define ADC_JOFR_JOFFSET 0x3FF + +/* Watchdog high threshold register */ + +#define ADC_HTR_HT 0x3FF + +/* Watchdog low threshold register */ + +#define ADC_LTR_LT 0x3FF + +/* Regular sequence register 1 */ + +#define ADC_SQR1_L (0x1F << 20) +#define ADC_SQR1_SQ16 (0x1F << 15) +#define ADC_SQR1_SQ15 (0x1F << 10) +#define ADC_SQR1_SQ14 (0x1F << 5) +#define ADC_SQR1_SQ13 0x1F + +/* Regular sequence register 2 */ + +#define ADC_SQR2_SQ12 (0x1F << 25) +#define ADC_SQR2_SQ11 (0x1F << 20) +#define ADC_SQR2_SQ10 (0x1F << 16) +#define ADC_SQR2_SQ9 (0x1F << 10) +#define ADC_SQR2_SQ8 (0x1F << 5) +#define ADC_SQR2_SQ7 0x1F + +/* Regular sequence register 3 */ + +#define ADC_SQR3_SQ6 (0x1F << 25) +#define ADC_SQR3_SQ5 (0x1F << 20) +#define ADC_SQR3_SQ4 (0x1F << 16) +#define ADC_SQR3_SQ3 (0x1F << 10) +#define ADC_SQR3_SQ2 (0x1F << 5) +#define ADC_SQR3_SQ1 0x1F + +/* Injected sequence register */ + +#define ADC_JSQR_JL (0x3 << 20) +#define ADC_JSQR_JL_1CONV (0x0 << 20) +#define ADC_JSQR_JL_2CONV (0x1 << 20) +#define ADC_JSQR_JL_3CONV (0x2 << 20) +#define ADC_JSQR_JL_4CONV (0x3 << 20) +#define ADC_JSQR_JSQ4 (0x1F << 15) +#define ADC_JSQR_JSQ3 (0x1F << 10) +#define ADC_JSQR_JSQ2 (0x1F << 5) +#define ADC_JSQR_JSQ1 0x1F + +/* Injected data registers */ + +#define ADC_JDR_JDATA 0xFFFF + +/* Regular data register */ + +#define ADC_DR_ADC2DATA (0xFFFF << 16) +#define ADC_DR_DATA 0xFFFF + +void adc_init(const adc_dev *dev); + +/** + * @brief External event selector for regular group conversion. + * @see adc_set_extsel + */ +typedef enum adc_extsel_event { + ADC_ADC12_TIM1_CC1 = (0 << 17), /**< ADC1 and ADC2: Timer 1 CC1 event */ + ADC_ADC12_TIM1_CC2 = (1 << 17), /**< ADC1 and ADC2: Timer 1 CC2 event */ + ADC_ADC12_TIM1_CC3 = (2 << 17), /**< ADC1 and ADC2: Timer 1 CC3 event */ + ADC_ADC12_TIM2_CC2 = (3 << 17), /**< ADC1 and ADC2: Timer 2 CC2 event */ + ADC_ADC12_TIM3_TRGO = (4 << 17), /**< ADC1 and ADC2: Timer 3 TRGO event */ + ADC_ADC12_TIM4_CC4 = (5 << 17), /**< ADC1 and ADC2: Timer 4 CC4 event */ + ADC_ADC12_EXTI11 = (6 << 17), /**< ADC1 and ADC2: EXTI11 event */ +#ifdef STM32_HIGH_DENSITY + ADC_ADC12_TIM8_TRGO = (6 << 17), /**< ADC1 and ADC2: Timer 8 TRGO + event (high density only) */ +#endif + ADC_ADC12_SWSTART = (7 << 17), /**< ADC1 and ADC2: Software start */ +#ifdef STM32_HIGH_DENSITY + ADC_ADC3_TIM3_CC1 = (0 << 17), /**< ADC3: Timer 3 CC1 event + (high density only) */ + ADC_ADC3_TIM2_CC3 = (1 << 17), /**< ADC3: Timer 2 CC3 event + (high density only) */ + ADC_ADC3_TIM1_CC3 = (2 << 17), /**< ADC3: Timer 1 CC3 event + (high density only) */ + ADC_ADC3_TIM8_CC1 = (3 << 17), /**< ADC3: Timer 8 CC1 event + (high density only) */ + ADC_ADC3_TIM8_TRGO = (4 << 17), /**< ADC3: Timer 8 TRGO event + (high density only) */ + ADC_ADC3_TIM5_CC1 = (5 << 17), /**< ADC3: Timer 5 CC1 event + (high density only) */ + ADC_ADC3_TIM5_CC3 = (6 << 17), /**< ADC3: Timer 5 CC3 event + (high density only) */ + ADC_ADC3_SWSTART = (7 << 17), /**< ADC3: Software start (high + density only) */ +#endif + ADC_SWSTART = (7 << 17) /**< ADC1, ADC2, ADC3: Software start */ +} adc_extsel_event; + +void adc_set_extsel(const adc_dev *dev, adc_extsel_event event); +void adc_foreach(void (*fn)(const adc_dev*)); + +/** + * @brief ADC sample times, in ADC clock cycles + * + * These control the amount of time spent sampling the input voltage. + */ +typedef enum { + ADC_SMPR_1_5, /**< 1.5 ADC cycles */ + ADC_SMPR_7_5, /**< 7.5 ADC cycles */ + ADC_SMPR_13_5, /**< 13.5 ADC cycles */ + ADC_SMPR_28_5, /**< 28.5 ADC cycles */ + ADC_SMPR_41_5, /**< 41.5 ADC cycles */ + ADC_SMPR_55_5, /**< 55.5 ADC cycles */ + ADC_SMPR_71_5, /**< 71.5 ADC cycles */ + ADC_SMPR_239_5 /**< 239.5 ADC cycles */ +} adc_smp_rate; + +void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); +void adc_calibrate(const adc_dev *dev); +uint16 adc_read(const adc_dev *dev, uint8 channel); + +/** + * @brief Set the regular channel sequence length. + * + * Defines the total number of conversions in the regular channel + * conversion sequence. + * + * @param dev ADC device. + * @param length Regular channel sequence length, from 1 to 16. + */ +static inline void adc_set_reg_seqlen(const adc_dev *dev, uint8 length) { + uint32 tmp = dev->regs->SQR1; + tmp &= ~ADC_SQR1_L; + tmp |= (length - 1) << 20; + dev->regs->SQR1 = tmp; +} + +/** + * @brief Set external trigger conversion mode event for regular channels + * @param dev ADC device + * @param enable If 1, conversion on external events is enabled; if 0, + * disabled. + */ +static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) { + *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable; +} + +/** + * @brief Enable an adc peripheral + * @param dev ADC device to enable + */ +static inline void adc_enable(const adc_dev *dev) { + *bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 1; +} + +/** + * @brief Disable an ADC peripheral + * @param dev ADC device to disable + */ +static inline void adc_disable(const adc_dev *dev) { + *bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 0; +} + +/** + * @brief Disable all ADC peripherals. + */ +static inline void adc_disable_all(void) { + adc_foreach(adc_disable); +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/bitband.h b/libmaple/include/libmaple/bitband.h new file mode 100644 index 0000000..607e4eb --- /dev/null +++ b/libmaple/include/libmaple/bitband.h @@ -0,0 +1,128 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file bitband.h + * + * @brief Bit-banding utility functions + */ + +#ifndef _LIBMAPLE_BITBAND_H_ +#define _LIBMAPLE_BITBAND_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define BB_SRAM_REF 0x20000000 +#define BB_SRAM_BASE 0x22000000 +#define BB_PERI_REF 0x40000000 +#define BB_PERI_BASE 0x42000000 + +static inline volatile uint32* __bb_addr(volatile void*, + uint32, + uint32, + uint32); + +/** + * @brief Obtain a pointer to the bit-band address corresponding to a + * bit in a volatile SRAM address. + * @param address Address in the bit-banded SRAM region + * @param bit Bit in address to bit-band + */ +static inline volatile uint32* bb_sramp(volatile void *address, uint32 bit) { + return __bb_addr(address, bit, BB_SRAM_BASE, BB_SRAM_REF); +} + +/** + * @brief Get a bit from an address in the SRAM bit-band region. + * @param address Address in the SRAM bit-band region to read from + * @param bit Bit in address to read + * @return bit's value in address. + */ +static inline uint8 bb_sram_get_bit(volatile void *address, uint32 bit) { + return *bb_sramp(address, bit); +} + +/** + * @brief Set a bit in an address in the SRAM bit-band region. + * @param address Address in the SRAM bit-band region to write to + * @param bit Bit in address to write to + * @param val Value to write for bit, either 0 or 1. + */ +static inline void bb_sram_set_bit(volatile void *address, + uint32 bit, + uint8 val) { + *bb_sramp(address, bit) = val; +} + +/** + * @brief Obtain a pointer to the bit-band address corresponding to a + * bit in a peripheral address. + * @param address Address in the bit-banded peripheral region + * @param bit Bit in address to bit-band + */ +static inline volatile uint32* bb_perip(volatile void *address, uint32 bit) { + return __bb_addr(address, bit, BB_PERI_BASE, BB_PERI_REF); +} + +/** + * @brief Get a bit from an address in the peripheral bit-band region. + * @param address Address in the peripheral bit-band region to read from + * @param bit Bit in address to read + * @return bit's value in address. + */ +static inline uint8 bb_peri_get_bit(volatile void *address, uint32 bit) { + return *bb_perip(address, bit); +} + +/** + * @brief Set a bit in an address in the peripheral bit-band region. + * @param address Address in the peripheral bit-band region to write to + * @param bit Bit in address to write to + * @param val Value to write for bit, either 0 or 1. + */ +static inline void bb_peri_set_bit(volatile void *address, + uint32 bit, + uint8 val) { + *bb_perip(address, bit) = val; +} + +static inline volatile uint32* __bb_addr(volatile void *address, + uint32 bit, + uint32 bb_base, + uint32 bb_ref) { + return (volatile uint32*)(bb_base + ((uint32)address - bb_ref) * 32 + + bit * 4); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/bkp.h b/libmaple/include/libmaple/bkp.h new file mode 100644 index 0000000..92359b6 --- /dev/null +++ b/libmaple/include/libmaple/bkp.h @@ -0,0 +1,166 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file bkp.h + * @brief Backup register support. + */ + +#ifndef _LIBMAPLE_BKP_H_ +#define _LIBMAPLE_BKP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if defined(STM32_MEDIUM_DENSITY) +#define BKP_NR_DATA_REGS 10 +#elif defined(STM32_HIGH_DENSITY) +#define BKP_NR_DATA_REGS 42 +#endif + +/** Backup peripheral register map type. */ +typedef struct bkp_reg_map { + const uint32 RESERVED1; ///< Reserved + __io uint32 DR1; ///< Data register 1 + __io uint32 DR2; ///< Data register 2 + __io uint32 DR3; ///< Data register 3 + __io uint32 DR4; ///< Data register 4 + __io uint32 DR5; ///< Data register 5 + __io uint32 DR6; ///< Data register 6 + __io uint32 DR7; ///< Data register 7 + __io uint32 DR8; ///< Data register 8 + __io uint32 DR9; ///< Data register 9 + __io uint32 DR10; ///< Data register 10 + __io uint32 RTCCR; ///< RTC control register + __io uint32 CR; ///< Control register + __io uint32 CSR; ///< Control and status register +#ifdef STM32_HIGH_DENSITY + const uint32 RESERVED2; ///< Reserved + const uint32 RESERVED3; ///< Reserved + __io uint32 DR11; ///< Data register 11 + __io uint32 DR12; ///< Data register 12 + __io uint32 DR13; ///< Data register 13 + __io uint32 DR14; ///< Data register 14 + __io uint32 DR15; ///< Data register 15 + __io uint32 DR16; ///< Data register 16 + __io uint32 DR17; ///< Data register 17 + __io uint32 DR18; ///< Data register 18 + __io uint32 DR19; ///< Data register 19 + __io uint32 DR20; ///< Data register 20 + __io uint32 DR21; ///< Data register 21 + __io uint32 DR22; ///< Data register 22 + __io uint32 DR23; ///< Data register 23 + __io uint32 DR24; ///< Data register 24 + __io uint32 DR25; ///< Data register 25 + __io uint32 DR26; ///< Data register 26 + __io uint32 DR27; ///< Data register 27 + __io uint32 DR28; ///< Data register 28 + __io uint32 DR29; ///< Data register 29 + __io uint32 DR30; ///< Data register 30 + __io uint32 DR31; ///< Data register 31 + __io uint32 DR32; ///< Data register 32 + __io uint32 DR33; ///< Data register 33 + __io uint32 DR34; ///< Data register 34 + __io uint32 DR35; ///< Data register 35 + __io uint32 DR36; ///< Data register 36 + __io uint32 DR37; ///< Data register 37 + __io uint32 DR38; ///< Data register 38 + __io uint32 DR39; ///< Data register 39 + __io uint32 DR40; ///< Data register 40 + __io uint32 DR41; ///< Data register 41 + __io uint32 DR42; ///< Data register 42 +#endif +} bkp_reg_map; + +/** Backup peripheral register map base pointer. */ +#define BKP_BASE ((struct bkp_reg_map*)0x40006C00) + +/** Backup peripheral device type. */ +typedef struct bkp_dev { + bkp_reg_map *regs; /**< Register map */ +} bkp_dev; + +extern const bkp_dev *BKP; + +/* + * Register bit definitions + */ + +/* Data Registers */ + +#define BKP_DR_D 0xFFFF + +/* RTC Clock Calibration Register */ + +#define BKP_RTCCR_ASOS_BIT 9 +#define BKP_RTCCR_ASOE_BIT 8 +#define BKP_RTCCR_CCO_BIT 7 + +#define BKP_RTCCR_ASOS BIT(BKP_RTCCR_ASOS_BIT) +#define BKP_RTCCR_ASOE BIT(BKP_RTCCR_ASOE_BIT) +#define BKP_RTCCR_CCO BIT(BKP_RTCCR_CCO_BIT) +#define BKP_RTCCR_CAL 0x7F + +/* Backup control register */ + +#define BKP_CR_TPAL_BIT 1 +#define BKP_CR_TPE_BIT 0 + +#define BKP_CR_TPAL BIT(BKP_CR_TPAL_BIT) +#define BKP_CR_TPE BIT(BKP_CR_TPE_BIT) + +/* Backup control/status register */ + +#define BKP_CSR_TIF_BIT 9 +#define BKP_CSR_TEF_BIT 8 +#define BKP_CSR_TPIE_BIT 2 +#define BKP_CSR_CTI_BIT 1 +#define BKP_CSR_CTE_BIT 0 + +#define BKP_CSR_TIF BIT(BKP_CSR_TIF_BIT) +#define BKP_CSR_TEF BIT(BKP_CSR_TEF_BIT) +#define BKP_CSR_TPIE BIT(BKP_CSR_TPIE_BIT) +#define BKP_CSR_CTI BIT(BKP_CSR_CTI_BIT) +#define BKP_CSR_CTE BIT(BKP_CSR_CTE_BIT) + +/* + * Convenience functions + */ + +void bkp_init(void); +void bkp_enable_writes(void); +void bkp_disable_writes(void); +uint16 bkp_read(uint8 reg); +void bkp_write(uint8 reg, uint16 val); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/libmaple/include/libmaple/dac.h b/libmaple/include/libmaple/dac.h new file mode 100644 index 0000000..738bede --- /dev/null +++ b/libmaple/include/libmaple/dac.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file dac.h + * @brief Digital to analog converter support. + */ + +/* See notes/dac.txt for more info */ + +#ifndef _LIBMAPLE_DAC_H_ +#define _LIBMAPLE_DAC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register maps + */ + +/** DAC register map. */ +typedef struct dac_reg_map { + __io uint32 CR; /**< Control register */ + __io uint32 SWTRIGR; /**< Software trigger register */ + __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data + holding register */ + __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data + holding register */ + __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data + holding register */ + __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data + holding register */ + __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data + holding register */ + __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data + holding register */ + __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data + holding register */ + __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data + holding register */ + __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding + register */ + __io uint32 DOR1; /**< Channel 1 data output register */ + __io uint32 DOR2; /**< Channel 2 data output register */ +} dac_reg_map; + +/** DAC register map base address */ +#define DAC_BASE ((struct dac_reg_map*)0x40007400) + +/* + * Devices + */ + +/** DAC device type. */ +typedef struct dac_dev { + dac_reg_map *regs; /**< Register map */ +} dac_dev; + +extern const dac_dev *DAC; + +/* + * Register bit definitions + */ + +/* Control register */ +/* Channel 1 control */ +#define DAC_CR_EN1 BIT(0) /* Enable */ +#define DAC_CR_BOFF1 BIT(1) /* Output buffer disable */ +#define DAC_CR_TEN1 BIT(2) /* Trigger enable */ +#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */ +#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave enable */ +#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */ +#define DAC_CR_DMAEN1 BIT(12) /* DMA enable */ +/* Channel 2 control */ +#define DAC_CR_EN2 BIT(16) /* Enable */ +#define DAC_CR_BOFF2 BIT(17) /* Output buffer disable */ +#define DAC_CR_TEN2 BIT(18) /* Trigger enable */ +#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */ +#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave generation*/ +#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */ +#define DAC_CR_DMAEN2 BIT(28) /* DMA enable */ + +/* Software trigger register */ +#define DAC_SWTRIGR_SWTRIG1 BIT(0) /* Channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 BIT(1) /* Channel 2 software trigger */ + +/* Channel 1 12-bit right-aligned data holding register */ +#define DAC_DHR12R1_DACC1DHR 0x00000FFF + +/* Channel 1 12-bit left-aligned data holding register */ +#define DAC_DHR12L1_DACC1DHR 0x0000FFF0 + +/* Channel 1 8-bit left-aligned data holding register */ +#define DAC_DHR8R1_DACC1DHR 0x000000FF + +/* Channel 2 12-bit right-aligned data holding register */ +#define DAC_DHR12R2_DACC2DHR 0x00000FFF + +/* Channel 2 12-bit left-aligned data holding register */ +#define DAC_DHR12L2_DACC2DHR 0x0000FFF0 + +/* Channel 2 8-bit left-aligned data holding register */ +#define DAC_DHR8R2_DACC2DHR 0x000000FF + +/* Dual DAC 12-bit right-aligned data holding register */ +#define DAC_DHR12RD_DACC1DHR 0x00000FFF +#define DAC_DHR12RD_DACC2DHR 0x0FFF0000 + +/* Dual DAC 12-bit left-aligned data holding register */ +#define DAC_DHR12LD_DACC1DHR 0x0000FFF0 +#define DAC_DHR12LD_DACC2DHR 0xFFF00000 + +/* Dual DAC 8-bit left-aligned data holding register */ +#define DAC_DHR8RD_DACC1DHR 0x000000FF +#define DAC_DHR8RD_DACC2DHR 0x0000FF00 + +/* Channel 1 data output register */ +#define DAC_DOR1_DACC1DOR 0x00000FFF + +/* Channel 1 data output register */ +#define DAC_DOR2_DACC2DOR 0x00000FFF + +/* + * Convenience functions + */ + +/* We take the dev argument in these convenience functions for + * future-proofing */ + +#define DAC_CH1 0x1 +#define DAC_CH2 0x2 +void dac_init(const dac_dev *dev, uint32 flags); + +void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val); +void dac_enable_channel(const dac_dev *dev, uint8 channel); +void dac_disable_channel(const dac_dev *dev, uint8 channel); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/delay.h b/libmaple/include/libmaple/delay.h new file mode 100644 index 0000000..f79655d --- /dev/null +++ b/libmaple/include/libmaple/delay.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file delay.h + * @brief Delay implementation + */ + +#ifndef _LIBMAPLE_DELAY_H_ +#define _LIBMAPLE_DELAY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @brief Delay the given number of microseconds. + * + * @param us Number of microseconds to delay. + */ +static inline void delay_us(uint32 us) { + us *= STM32_DELAY_US_MULT; + + /* fudge for function call overhead */ + us--; + asm volatile(" mov r0, %[us] \n\t" + "1: subs r0, #1 \n\t" + " bhi 1b \n\t" + : + : [us] "r" (us) + : "r0"); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/dma.h b/libmaple/include/libmaple/dma.h new file mode 100644 index 0000000..da2bd4f --- /dev/null +++ b/libmaple/include/libmaple/dma.h @@ -0,0 +1,453 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Michael Hope. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file dma.h + * + * @author Marti Bolivar ; + * Original implementation by Michael Hope + * + * @brief Direct Memory Access peripheral support + */ + +/* + * See /notes/dma.txt for more information. + */ + +#ifndef _LIBMAPLE_DMA_H_ +#define _LIBMAPLE_DMA_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include + +/* + * Register maps + */ + +/** + * @brief DMA register map type. + * + * Note that DMA controller 2 (register map base pointer DMA2_BASE) + * only supports channels 1--5. + */ +typedef struct dma_reg_map { + __io uint32 ISR; /**< Interrupt status register */ + __io uint32 IFCR; /**< Interrupt flag clear register */ + __io uint32 CCR1; /**< Channel 1 configuration register */ + __io uint32 CNDTR1; /**< Channel 1 number of data register */ + __io uint32 CPAR1; /**< Channel 1 peripheral address register */ + __io uint32 CMAR1; /**< Channel 1 memory address register */ + const uint32 RESERVED1; /**< Reserved. */ + __io uint32 CCR2; /**< Channel 2 configuration register */ + __io uint32 CNDTR2; /**< Channel 2 number of data register */ + __io uint32 CPAR2; /**< Channel 2 peripheral address register */ + __io uint32 CMAR2; /**< Channel 2 memory address register */ + const uint32 RESERVED2; /**< Reserved. */ + __io uint32 CCR3; /**< Channel 3 configuration register */ + __io uint32 CNDTR3; /**< Channel 3 number of data register */ + __io uint32 CPAR3; /**< Channel 3 peripheral address register */ + __io uint32 CMAR3; /**< Channel 3 memory address register */ + const uint32 RESERVED3; /**< Reserved. */ + __io uint32 CCR4; /**< Channel 4 configuration register */ + __io uint32 CNDTR4; /**< Channel 4 number of data register */ + __io uint32 CPAR4; /**< Channel 4 peripheral address register */ + __io uint32 CMAR4; /**< Channel 4 memory address register */ + const uint32 RESERVED4; /**< Reserved. */ + __io uint32 CCR5; /**< Channel 5 configuration register */ + __io uint32 CNDTR5; /**< Channel 5 number of data register */ + __io uint32 CPAR5; /**< Channel 5 peripheral address register */ + __io uint32 CMAR5; /**< Channel 5 memory address register */ + const uint32 RESERVED5; /**< Reserved. */ + __io uint32 CCR6; /**< Channel 6 configuration register */ + __io uint32 CNDTR6; /**< Channel 6 number of data register */ + __io uint32 CPAR6; /**< Channel 6 peripheral address register */ + __io uint32 CMAR6; /**< Channel 6 memory address register */ + const uint32 RESERVED6; /**< Reserved. */ + __io uint32 CCR7; /**< Channel 7 configuration register */ + __io uint32 CNDTR7; /**< Channel 7 number of data register */ + __io uint32 CPAR7; /**< Channel 7 peripheral address register */ + __io uint32 CMAR7; /**< Channel 7 memory address register */ + const uint32 RESERVED7; /**< Reserved. */ +} dma_reg_map; + +/** DMA controller 1 register map base pointer */ +#define DMA1_BASE ((struct dma_reg_map*)0x40020000) + +#ifdef STM32_HIGH_DENSITY +/** DMA controller 2 register map base pointer */ +#define DMA2_BASE ((struct dma_reg_map*)0x40020400) +#endif + +/* + * Register bit definitions + */ + +/* Interrupt status register */ + +#define DMA_ISR_TEIF7_BIT 27 +#define DMA_ISR_HTIF7_BIT 26 +#define DMA_ISR_TCIF7_BIT 25 +#define DMA_ISR_GIF7_BIT 24 +#define DMA_ISR_TEIF6_BIT 23 +#define DMA_ISR_HTIF6_BIT 22 +#define DMA_ISR_TCIF6_BIT 21 +#define DMA_ISR_GIF6_BIT 20 +#define DMA_ISR_TEIF5_BIT 19 +#define DMA_ISR_HTIF5_BIT 18 +#define DMA_ISR_TCIF5_BIT 17 +#define DMA_ISR_GIF5_BIT 16 +#define DMA_ISR_TEIF4_BIT 15 +#define DMA_ISR_HTIF4_BIT 14 +#define DMA_ISR_TCIF4_BIT 13 +#define DMA_ISR_GIF4_BIT 12 +#define DMA_ISR_TEIF3_BIT 11 +#define DMA_ISR_HTIF3_BIT 10 +#define DMA_ISR_TCIF3_BIT 9 +#define DMA_ISR_GIF3_BIT 8 +#define DMA_ISR_TEIF2_BIT 7 +#define DMA_ISR_HTIF2_BIT 6 +#define DMA_ISR_TCIF2_BIT 5 +#define DMA_ISR_GIF2_BIT 4 +#define DMA_ISR_TEIF1_BIT 3 +#define DMA_ISR_HTIF1_BIT 2 +#define DMA_ISR_TCIF1_BIT 1 +#define DMA_ISR_GIF1_BIT 0 + +#define DMA_ISR_TEIF7 BIT(DMA_ISR_TEIF7_BIT) +#define DMA_ISR_HTIF7 BIT(DMA_ISR_HTIF7_BIT) +#define DMA_ISR_TCIF7 BIT(DMA_ISR_TCIF7_BIT) +#define DMA_ISR_GIF7 BIT(DMA_ISR_GIF7_BIT) +#define DMA_ISR_TEIF6 BIT(DMA_ISR_TEIF6_BIT) +#define DMA_ISR_HTIF6 BIT(DMA_ISR_HTIF6_BIT) +#define DMA_ISR_TCIF6 BIT(DMA_ISR_TCIF6_BIT) +#define DMA_ISR_GIF6 BIT(DMA_ISR_GIF6_BIT) +#define DMA_ISR_TEIF5 BIT(DMA_ISR_TEIF5_BIT) +#define DMA_ISR_HTIF5 BIT(DMA_ISR_HTIF5_BIT) +#define DMA_ISR_TCIF5 BIT(DMA_ISR_TCIF5_BIT) +#define DMA_ISR_GIF5 BIT(DMA_ISR_GIF5_BIT) +#define DMA_ISR_TEIF4 BIT(DMA_ISR_TEIF4_BIT) +#define DMA_ISR_HTIF4 BIT(DMA_ISR_HTIF4_BIT) +#define DMA_ISR_TCIF4 BIT(DMA_ISR_TCIF4_BIT) +#define DMA_ISR_GIF4 BIT(DMA_ISR_GIF4_BIT) +#define DMA_ISR_TEIF3 BIT(DMA_ISR_TEIF3_BIT) +#define DMA_ISR_HTIF3 BIT(DMA_ISR_HTIF3_BIT) +#define DMA_ISR_TCIF3 BIT(DMA_ISR_TCIF3_BIT) +#define DMA_ISR_GIF3 BIT(DMA_ISR_GIF3_BIT) +#define DMA_ISR_TEIF2 BIT(DMA_ISR_TEIF2_BIT) +#define DMA_ISR_HTIF2 BIT(DMA_ISR_HTIF2_BIT) +#define DMA_ISR_TCIF2 BIT(DMA_ISR_TCIF2_BIT) +#define DMA_ISR_GIF2 BIT(DMA_ISR_GIF2_BIT) +#define DMA_ISR_TEIF1 BIT(DMA_ISR_TEIF1_BIT) +#define DMA_ISR_HTIF1 BIT(DMA_ISR_HTIF1_BIT) +#define DMA_ISR_TCIF1 BIT(DMA_ISR_TCIF1_BIT) +#define DMA_ISR_GIF1 BIT(DMA_ISR_GIF1_BIT) + +/* Interrupt flag clear register */ + +#define DMA_IFCR_CTEIF7_BIT 27 +#define DMA_IFCR_CHTIF7_BIT 26 +#define DMA_IFCR_CTCIF7_BIT 25 +#define DMA_IFCR_CGIF7_BIT 24 +#define DMA_IFCR_CTEIF6_BIT 23 +#define DMA_IFCR_CHTIF6_BIT 22 +#define DMA_IFCR_CTCIF6_BIT 21 +#define DMA_IFCR_CGIF6_BIT 20 +#define DMA_IFCR_CTEIF5_BIT 19 +#define DMA_IFCR_CHTIF5_BIT 18 +#define DMA_IFCR_CTCIF5_BIT 17 +#define DMA_IFCR_CGIF5_BIT 16 +#define DMA_IFCR_CTEIF4_BIT 15 +#define DMA_IFCR_CHTIF4_BIT 14 +#define DMA_IFCR_CTCIF4_BIT 13 +#define DMA_IFCR_CGIF4_BIT 12 +#define DMA_IFCR_CTEIF3_BIT 11 +#define DMA_IFCR_CHTIF3_BIT 10 +#define DMA_IFCR_CTCIF3_BIT 9 +#define DMA_IFCR_CGIF3_BIT 8 +#define DMA_IFCR_CTEIF2_BIT 7 +#define DMA_IFCR_CHTIF2_BIT 6 +#define DMA_IFCR_CTCIF2_BIT 5 +#define DMA_IFCR_CGIF2_BIT 4 +#define DMA_IFCR_CTEIF1_BIT 3 +#define DMA_IFCR_CHTIF1_BIT 2 +#define DMA_IFCR_CTCIF1_BIT 1 +#define DMA_IFCR_CGIF1_BIT 0 + +#define DMA_IFCR_CTEIF7 BIT(DMA_IFCR_CTEIF7_BIT) +#define DMA_IFCR_CHTIF7 BIT(DMA_IFCR_CHTIF7_BIT) +#define DMA_IFCR_CTCIF7 BIT(DMA_IFCR_CTCIF7_BIT) +#define DMA_IFCR_CGIF7 BIT(DMA_IFCR_CGIF7_BIT) +#define DMA_IFCR_CTEIF6 BIT(DMA_IFCR_CTEIF6_BIT) +#define DMA_IFCR_CHTIF6 BIT(DMA_IFCR_CHTIF6_BIT) +#define DMA_IFCR_CTCIF6 BIT(DMA_IFCR_CTCIF6_BIT) +#define DMA_IFCR_CGIF6 BIT(DMA_IFCR_CGIF6_BIT) +#define DMA_IFCR_CTEIF5 BIT(DMA_IFCR_CTEIF5_BIT) +#define DMA_IFCR_CHTIF5 BIT(DMA_IFCR_CHTIF5_BIT) +#define DMA_IFCR_CTCIF5 BIT(DMA_IFCR_CTCIF5_BIT) +#define DMA_IFCR_CGIF5 BIT(DMA_IFCR_CGIF5_BIT) +#define DMA_IFCR_CTEIF4 BIT(DMA_IFCR_CTEIF4_BIT) +#define DMA_IFCR_CHTIF4 BIT(DMA_IFCR_CHTIF4_BIT) +#define DMA_IFCR_CTCIF4 BIT(DMA_IFCR_CTCIF4_BIT) +#define DMA_IFCR_CGIF4 BIT(DMA_IFCR_CGIF4_BIT) +#define DMA_IFCR_CTEIF3 BIT(DMA_IFCR_CTEIF3_BIT) +#define DMA_IFCR_CHTIF3 BIT(DMA_IFCR_CHTIF3_BIT) +#define DMA_IFCR_CTCIF3 BIT(DMA_IFCR_CTCIF3_BIT) +#define DMA_IFCR_CGIF3 BIT(DMA_IFCR_CGIF3_BIT) +#define DMA_IFCR_CTEIF2 BIT(DMA_IFCR_CTEIF2_BIT) +#define DMA_IFCR_CHTIF2 BIT(DMA_IFCR_CHTIF2_BIT) +#define DMA_IFCR_CTCIF2 BIT(DMA_IFCR_CTCIF2_BIT) +#define DMA_IFCR_CGIF2 BIT(DMA_IFCR_CGIF2_BIT) +#define DMA_IFCR_CTEIF1 BIT(DMA_IFCR_CTEIF1_BIT) +#define DMA_IFCR_CHTIF1 BIT(DMA_IFCR_CHTIF1_BIT) +#define DMA_IFCR_CTCIF1 BIT(DMA_IFCR_CTCIF1_BIT) +#define DMA_IFCR_CGIF1 BIT(DMA_IFCR_CGIF1_BIT) + +/* Channel configuration register */ + +#define DMA_CCR_MEM2MEM_BIT 14 +#define DMA_CCR_MINC_BIT 7 +#define DMA_CCR_PINC_BIT 6 +#define DMA_CCR_CIRC_BIT 5 +#define DMA_CCR_DIR_BIT 4 +#define DMA_CCR_TEIE_BIT 3 +#define DMA_CCR_HTIE_BIT 2 +#define DMA_CCR_TCIE_BIT 1 +#define DMA_CCR_EN_BIT 0 + +#define DMA_CCR_MEM2MEM BIT(DMA_CCR_MEM2MEM_BIT) +#define DMA_CCR_PL (0x3 << 12) +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +#define DMA_CCR_MSIZE (0x3 << 10) +#define DMA_CCR_MSIZE_8BITS (0x0 << 10) +#define DMA_CCR_MSIZE_16BITS (0x1 << 10) +#define DMA_CCR_MSIZE_32BITS (0x2 << 10) +#define DMA_CCR_PSIZE (0x3 << 8) +#define DMA_CCR_PSIZE_8BITS (0x0 << 8) +#define DMA_CCR_PSIZE_16BITS (0x1 << 8) +#define DMA_CCR_PSIZE_32BITS (0x2 << 8) +#define DMA_CCR_MINC BIT(DMA_CCR_MINC_BIT) +#define DMA_CCR_PINC BIT(DMA_CCR_PINC_BIT) +#define DMA_CCR_CIRC BIT(DMA_CCR_CIRC_BIT) +#define DMA_CCR_DIR BIT(DMA_CCR_DIR_BIT) +#define DMA_CCR_TEIE BIT(DMA_CCR_TEIE_BIT) +#define DMA_CCR_HTIE BIT(DMA_CCR_HTIE_BIT) +#define DMA_CCR_TCIE BIT(DMA_CCR_TCIE_BIT) +#define DMA_CCR_EN BIT(DMA_CCR_EN_BIT) + +/* + * Devices + */ + +/** Encapsulates state related to a DMA channel interrupt. */ +typedef struct dma_handler_config { + void (*handler)(void); /**< User-specified channel interrupt + handler */ + nvic_irq_num irq_line; /**< Channel's NVIC interrupt number */ +} dma_handler_config; + +/** DMA device type */ +typedef struct dma_dev { + dma_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< Clock ID */ + dma_handler_config handlers[]; /**< + * @brief IRQ handlers and NVIC numbers. + * + * @see dma_attach_interrupt() + * @see dma_detach_interrupt() + */ +} dma_dev; + +extern dma_dev *DMA1; +#ifdef STM32_HIGH_DENSITY +extern dma_dev *DMA2; +#endif + +/* + * Convenience functions + */ + +void dma_init(dma_dev *dev); + +/** Flags for DMA transfer configuration. */ +typedef enum dma_mode_flags { + DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ + DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ + DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ + DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ + DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ + DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ + DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ + DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ +} dma_mode_flags; + +/** Source and destination transfer sizes. */ +typedef enum dma_xfer_size { + DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ + DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ + DMA_SIZE_32BITS = 2 /**< 32-bit transfers */ +} dma_xfer_size; + +/** DMA channel */ +typedef enum dma_channel { + DMA_CH1 = 1, /**< Channel 1 */ + DMA_CH2 = 2, /**< Channel 2 */ + DMA_CH3 = 3, /**< Channel 3 */ + DMA_CH4 = 4, /**< Channel 4 */ + DMA_CH5 = 5, /**< Channel 5 */ + DMA_CH6 = 6, /**< Channel 6 */ + DMA_CH7 = 7, /**< Channel 7 */ +} dma_channel; + +void dma_setup_transfer(dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode); + +void dma_set_num_transfers(dma_dev *dev, + dma_channel channel, + uint16 num_transfers); + +/** DMA transfer priority. */ +typedef enum dma_priority { + DMA_PRIORITY_LOW = DMA_CCR_PL_LOW, /**< Low priority */ + DMA_PRIORITY_MEDIUM = DMA_CCR_PL_MEDIUM, /**< Medium priority */ + DMA_PRIORITY_HIGH = DMA_CCR_PL_HIGH, /**< High priority */ + DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */ +} dma_priority; + +void dma_set_priority(dma_dev *dev, + dma_channel channel, + dma_priority priority); + +void dma_attach_interrupt(dma_dev *dev, + dma_channel channel, + void (*handler)(void)); +void dma_detach_interrupt(dma_dev *dev, dma_channel channel); + +/** + * Encodes the reason why a DMA interrupt was called. + * @see dma_get_irq_cause() + */ +typedef enum dma_irq_cause { + DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ + DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ + DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ +} dma_irq_cause; + +dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel); + +void dma_enable(dma_dev *dev, dma_channel channel); +void dma_disable(dma_dev *dev, dma_channel channel); + +void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address); +void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address); + +/** + * @brief DMA channel register map type. + * + * Provides access to an individual channel's registers. + */ +typedef struct dma_channel_reg_map { + __io uint32 CCR; /**< Channel configuration register */ + __io uint32 CNDTR; /**< Channel number of data register */ + __io uint32 CPAR; /**< Channel peripheral address register */ + __io uint32 CMAR; /**< Channel memory address register */ +} dma_channel_reg_map; + +#define DMA_CHANNEL_NREGS 5 + +/** + * @brief Obtain a pointer to an individual DMA channel's registers. + * + * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. + * + * @param dev DMA device + * @param channel DMA channel whose channel register map to obtain. + */ +static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev, + dma_channel channel) { + __io uint32 *ccr1 = &dev->regs->CCR1; + return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1)); +} + +/** + * @brief Check if a DMA channel is enabled + * @param dev DMA device + * @param channel Channel whose enabled bit to check. + */ +static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) { + return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN); +} + +/** + * @brief Get the ISR status bits for a DMA channel. + * + * The bits are returned right-aligned, in the following order: + * transfer error flag, half-transfer flag, transfer complete flag, + * global interrupt flag. + * + * If you're attempting to figure out why a DMA interrupt fired; you + * may find dma_get_irq_cause() more convenient. + * + * @param dev DMA device + * @param channel Channel whose ISR bits to return. + * @see dma_get_irq_cause(). + */ +static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) { + uint8 shift = (channel - 1) * 4; + return (dev->regs->ISR >> shift) & 0xF; +} + +/** + * @brief Clear the ISR status bits for a given DMA channel. + * + * If you're attempting to clean up after yourself in a DMA interrupt, + * you may find dma_get_irq_cause() more convenient. + * + * @param dev DMA device + * @param channel Channel whose ISR bits to clear. + * @see dma_get_irq_cause() + */ +static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) { + dev->regs->IFCR = BIT(4 * (channel - 1)); +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/exti.h b/libmaple/include/libmaple/exti.h new file mode 100644 index 0000000..0a763d7 --- /dev/null +++ b/libmaple/include/libmaple/exti.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file exti.h + * @brief External interrupt control prototypes and defines + */ + +/* See notes/exti.txt for more info */ + +#ifndef _LIBMAPLE_EXTI_H_ +#define _LIBMAPLE_EXTI_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/** EXTI register map type */ +typedef struct exti_reg_map { + __io uint32 IMR; /**< Interrupt mask register */ + __io uint32 EMR; /**< Event mask register */ + __io uint32 RTSR; /**< Rising trigger selection register */ + __io uint32 FTSR; /**< Falling trigger selection register */ + __io uint32 SWIER; /**< Software interrupt event register */ + __io uint32 PR; /**< Pending register */ +} exti_reg_map; + +/** EXTI register map base pointer */ +#define EXTI_BASE ((struct exti_reg_map*)0x40010400) + +/** External interrupt trigger mode */ +typedef enum exti_trigger_mode { + EXTI_RISING, /**< Trigger on the rising edge */ + EXTI_FALLING, /**< Trigger on the falling edge */ + EXTI_RISING_FALLING /**< Trigger on both the rising and falling edges */ +} exti_trigger_mode; + +void exti_attach_interrupt(afio_exti_num num, + afio_exti_port port, + voidFuncPtr handler, + exti_trigger_mode mode); +void exti_detach_interrupt(afio_exti_num num); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h new file mode 100644 index 0000000..e28ea28 --- /dev/null +++ b/libmaple/include/libmaple/flash.h @@ -0,0 +1,140 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file flash.h + * @brief STM32 Medium and high density Flash register map and setup + * routines + */ + +#ifndef _LIBMAPLE_FLASH_H_ +#define _LIBMAPLE_FLASH_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** Flash register map type */ +typedef struct flash_reg_map { + __io uint32 ACR; /**< Access control register */ + __io uint32 KEYR; /**< Key register */ + __io uint32 OPTKEYR; /**< OPTKEY register */ + __io uint32 SR; /**< Status register */ + __io uint32 CR; /**< Control register */ + __io uint32 AR; /**< Address register */ + __io uint32 OBR; /**< Option byte register */ + __io uint32 WRPR; /**< Write protection register */ +} flash_reg_map; + +/** Flash register map base pointer */ +#define FLASH_BASE ((struct flash_reg_map*)0x40022000) + +/* + * Register bit definitions + */ + +/* Access control register */ + +#define FLASH_ACR_PRFTBS_BIT 5 +#define FLASH_ACR_PRFTBE_BIT 4 +#define FLASH_ACR_HLFCYA_BIT 3 + +#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) +#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) +#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) +#define FLASH_ACR_LATENCY 0x7 + +/* Status register */ + +#define FLASH_SR_EOP_BIT 5 +#define FLASH_SR_WRPRTERR_BIT 4 +#define FLASH_SR_PGERR_BIT 2 +#define FLASH_SR_BSY_BIT 0 + +#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) +#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) +#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) +#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) + +/* Control register */ + +#define FLASH_CR_EOPIE_BIT 12 +#define FLASH_CR_ERRIE_BIT 10 +#define FLASH_CR_OPTWRE_BIT 9 +#define FLASH_CR_LOCK_BIT 7 +#define FLASH_CR_STRT_BIT 6 +#define FLASH_CR_OPTER_BIT 5 +#define FLASH_CR_OPTPG_BIT 4 +#define FLASH_CR_MER_BIT 2 +#define FLASH_CR_PER_BIT 1 +#define FLASH_CR_PG_BIT 0 + +#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) +#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) +#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) +#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) +#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) +#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) +#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) +#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) +#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) +#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) + +/* Option byte register */ + +#define FLASH_OBR_nRST_STDBY_BIT 4 +#define FLASH_OBR_nRST_STOP_BIT 3 +#define FLASH_OBR_WDG_SW_BIT 2 +#define FLASH_OBR_RDPRT_BIT 1 +#define FLASH_OBR_OPTERR_BIT 0 + +#define FLASH_OBR_DATA1 (0xFF << 18) +#define FLASH_OBR_DATA0 (0xFF << 10) +#define FLASH_OBR_USER 0x3FF +#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) +#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) +#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) +#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) +#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) + +/* + * Setup routines + */ + +#define FLASH_WAIT_STATE_0 0x0 +#define FLASH_WAIT_STATE_1 0x1 +#define FLASH_WAIT_STATE_2 0x2 + +void flash_enable_prefetch(void); +void flash_set_latency(uint32 wait_states); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/fsmc.h b/libmaple/include/libmaple/fsmc.h new file mode 100644 index 0000000..95b0d3a --- /dev/null +++ b/libmaple/include/libmaple/fsmc.h @@ -0,0 +1,316 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file fsmc.h + * @brief Flexible static memory controller support. + */ + +/* + * See ../notes/fsmc.txt for more info + */ + +#ifndef _LIBMAPLE_FSMC_H_ +#define _LIBMAPLE_FSMC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +#ifdef STM32_HIGH_DENSITY + +/* + * Register maps and devices + */ + +/** FSMC register map type */ +typedef struct fsmc_reg_map { + __io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */ + __io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */ + __io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */ + __io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */ + __io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */ + __io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */ + __io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */ + __io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */ + const uint8 RESERVED1[64]; /**< Reserved */ + __io uint32 PCR2; /**< PC Card/NAND Flash control register 2 */ + __io uint32 SR2; /**< FIFO status and interrupt register 2 */ + __io uint32 PMEM2; /**< Common memory space timing register 2 */ + __io uint32 PATT2; /**< Attribute memory space timing register 2 */ + const uint8 RESERVED2[4]; /**< Reserved */ + __io uint32 ECCR2; /**< ECC result register 2 */ + const uint8 RESERVED3[2]; + __io uint32 PCR3; /**< PC Card/NAND Flash control register 3 */ + __io uint32 SR3; /**< FIFO status and interrupt register 3 */ + __io uint32 PMEM3; /**< Common memory space timing register 3 */ + __io uint32 PATT3; /**< Attribute memory space timing register 3 */ + const uint32 RESERVED4; /**< Reserved */ + __io uint32 ECCR3; /**< ECC result register 3 */ + const uint8 RESERVED5[8]; /**< Reserved */ + __io uint32 PCR4; /**< PC Card/NAND Flash control register 4 */ + __io uint32 SR4; /**< FIFO status and interrupt register 4 */ + __io uint32 PMEM4; /**< Common memory space timing register 4 */ + __io uint32 PATT4; /**< Attribute memory space timing register 4 */ + __io uint32 PIO4; /**< I/O space timing register 4 */ + const uint8 RESERVED6[80]; /**< Reserved */ + __io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */ + const uint32 RESERVED7; /**< Reserved */ + __io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */ + const uint32 RESERVED8; /**< Reserved */ + __io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */ + const uint32 RESERVED9; /**< Reserved */ + __io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */ +} __attribute__((packed)) fsmc_reg_map; + +#define __FSMCB 0xA0000000 + +/** FSMC register map base pointer */ +#define FSMC_BASE ((struct fsmc_reg_map*)__FSMCB) + +/** FSMC NOR/PSRAM register map type */ +typedef struct fsmc_nor_psram_reg_map { + __io uint32 BCR; /**< Chip-select control register */ + __io uint32 BTR; /**< Chip-select timing register */ + const uint8 RESERVED[252]; /**< Reserved */ + __io uint32 BWTR; /**< Write timing register */ +} fsmc_nor_psram_reg_map; + +/** FSMC NOR/PSRAM base pointer 1 */ +#define FSMC_NOR_PSRAM1_BASE ((struct fsmc_nor_psram_reg_map*)__FSMCB) + +/** FSMC NOR/PSRAM base pointer 2 */ +#define FSMC_NOR_PSRAM2_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x8)) + +/** FSMC NOR/PSRAM base pointer 3 */ +#define FSMC_NOR_PSRAM3_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x10)) + +/** FSMC NOR/PSRAM base pointer 4 */ +#define FSMC_NOR_PSRAM4_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x18)) + +/* + * Register bit definitions + */ + +/* NOR/PSRAM chip-select control registers */ + +#define FSMC_BCR_CBURSTRW_BIT 19 +#define FSMC_BCR_ASYNCWAIT_BIT 15 +#define FSMC_BCR_EXTMOD_BIT 14 +#define FSMC_BCR_WAITEN_BIT 13 +#define FSMC_BCR_WREN_BIT 12 +#define FSMC_BCR_WAITCFG_BIT 11 +#define FSMC_BCR_WRAPMOD_BIT 10 +#define FSMC_BCR_WAITPOL_BIT 9 +#define FSMC_BCR_BURSTEN_BIT 8 +#define FSMC_BCR_FACCEN_BIT 6 +#define FSMC_BCR_MUXEN_BIT 1 +#define FSMC_BCR_MBKEN_BIT 0 + +#define FSMC_BCR_CBURSTRW BIT(FSMC_BCR_CBURSTRW_BIT) +#define FSMC_BCR_ASYNCWAIT BIT(FSMC_BCR_ASYNCWAIT_BIT) +#define FSMC_BCR_EXTMOD BIT(FSMC_BCR_EXTMOD_BIT) +#define FSMC_BCR_WAITEN BIT(FSMC_BCR_WAITEN_BIT) +#define FSMC_BCR_WREN BIT(FSMC_BCR_WREN_BIT) +#define FSMC_BCR_WAITCFG BIT(FSMC_BCR_WAITCFG_BIT) +#define FSMC_BCR_WRAPMOD BIT(FSMC_BCR_WRAPMOD_BIT) +#define FSMC_BCR_WAITPOL BIT(FSMC_BCR_WAITPOL_BIT) +#define FSMC_BCR_BURSTEN BIT(FSMC_BCR_BURSTEN_BIT) +#define FSMC_BCR_FACCEN BIT(FSMC_BCR_FACCEN_BIT) +#define FSMC_BCR_MWID (0x3 << 4) +#define FSMC_BCR_MWID_8BITS (0x0 << 4) +#define FSMC_BCR_MWID_16BITS (0x1 << 4) +#define FSMC_BCR_MTYP (0x3 << 2) +#define FSMC_BCR_MTYP_SRAM (0x0 << 2) +#define FSMC_BCR_MTYP_PSRAM (0x1 << 2) +#define FSMC_BCR_MTYP_NOR_FLASH (0x2 << 2) +#define FSMC_BCR_MUXEN BIT(FSMC_BCR_MUXEN_BIT) +#define FSMC_BCR_MBKEN BIT(FSMC_BCR_MBKEN_BIT) + +/* SRAM/NOR-Flash chip-select timing registers */ + +#define FSMC_BTR_ACCMOD (0x3 << 28) +#define FSMC_BTR_ACCMOD_A (0x0 << 28) +#define FSMC_BTR_ACCMOD_B (0x1 << 28) +#define FSMC_BTR_ACCMOD_C (0x2 << 28) +#define FSMC_BTR_ACCMOD_D (0x3 << 28) +#define FSMC_BTR_DATLAT (0xF << 24) +#define FSMC_BTR_CLKDIV (0xF << 20) +#define FSMC_BTR_BUSTURN (0xF << 16) +#define FSMC_BTR_DATAST (0xFF << 8) +#define FSMC_BTR_ADDHLD (0xF << 4) +#define FSMC_BTR_ADDSET 0xF + +/* SRAM/NOR-Flash write timing registers */ + +#define FSMC_BWTR_ACCMOD (0x3 << 28) +#define FSMC_BWTR_ACCMOD_A (0x0 << 28) +#define FSMC_BWTR_ACCMOD_B (0x1 << 28) +#define FSMC_BWTR_ACCMOD_C (0x2 << 28) +#define FSMC_BWTR_ACCMOD_D (0x3 << 28) +#define FSMC_BWTR_DATLAT (0xF << 24) +#define FSMC_BWTR_CLKDIV (0xF << 20) +#define FSMC_BWTR_DATAST (0xFF << 8) +#define FSMC_BWTR_ADDHLD (0xF << 4) +#define FSMC_BWTR_ADDSET 0xF + +/* NAND Flash/PC Card controller registers */ + +#define FSMC_PCR_ECCEN_BIT 6 +#define FSMC_PCR_PTYP_BIT 3 +#define FSMC_PCR_PBKEN_BIT 2 +#define FSMC_PCR_PWAITEN_BIT 1 + +#define FSMC_PCR_ECCPS (0x7 << 17) +#define FSMC_PCR_ECCPS_256B (0x0 << 17) +#define FSMC_PCR_ECCPS_512B (0x1 << 17) +#define FSMC_PCR_ECCPS_1024B (0x2 << 17) +#define FSMC_PCR_ECCPS_2048B (0x3 << 17) +#define FSMC_PCR_ECCPS_4096B (0x4 << 17) +#define FSMC_PCR_ECCPS_8192B (0x5 << 17) +#define FSMC_PCR_TAR (0xF << 13) +#define FSMC_PCR_TCLR (0xF << 9) +#define FSMC_PCR_ECCEN BIT(FSMC_PCR_ECCEN_BIT) +#define FSMC_PCR_PWID (0x3 << 4) +#define FSMC_PCR_PWID_8BITS (0x0 << 4) +#define FSMC_PCR_PWID_16BITS (0x1 << 4) +#define FSMC_PCR_PTYP BIT(FSMC_PCR_PTYP_BIT) +#define FSMC_PCR_PTYP_PC_CF_PCMCIA (0x0 << FSMC_PCR_PTYP_BIT) +#define FSMC_PCR_PTYP_NAND (0x1 << FSMC_PCR_PTYP_BIT) +#define FSMC_PCR_PBKEN BIT(FSMC_PCR_PBKEN_BIT) +#define FSMC_PCR_PWAITEN BIT(FSMC_PCR_PWAITEN_BIT) + +/* FIFO status and interrupt registers */ + +#define FSMC_SR_FEMPT_BIT 6 +#define FSMC_SR_IFEN_BIT 5 +#define FSMC_SR_ILEN_BIT 4 +#define FSMC_SR_IREN_BIT 3 +#define FSMC_SR_IFS_BIT 2 +#define FSMC_SR_ILS_BIT 1 +#define FSMC_SR_IRS_BIT 0 + +#define FSMC_SR_FEMPT BIT(FSMC_SR_FEMPT_BIT) +#define FSMC_SR_IFEN BIT(FSMC_SR_IFEN_BIT) +#define FSMC_SR_ILEN BIT(FSMC_SR_ILEN_BIT) +#define FSMC_SR_IREN BIT(FSMC_SR_IREN_BIT) +#define FSMC_SR_IFS BIT(FSMC_SR_IFS_BIT) +#define FSMC_SR_ILS BIT(FSMC_SR_ILS_BIT) +#define FSMC_SR_IRS BIT(FSMC_SR_IRS_BIT) + +/* Common memory space timing registers */ + +#define FSMC_PMEM_MEMHIZ (0xFF << 24) +#define FSMC_PMEM_MEMHOLD (0xFF << 16) +#define FSMC_PMEM_MEMWAIT (0xFF << 8) +#define FSMC_PMEM_MEMSET 0xFF + +/* Attribute memory space timing registers */ + +#define FSMC_PATT_ATTHIZ (0xFF << 24) +#define FSMC_PATT_ATTHOLD (0xFF << 16) +#define FSMC_PATT_ATTWAIT (0xFF << 8) +#define FSMC_PATT_ATTSET 0xFF + +/* I/O space timing register 4 */ + +#define FSMC_PIO_IOHIZ (0xFF << 24) +#define FSMC_PIO_IOHOLD (0xFF << 16) +#define FSMC_PIO_IOWAIT (0xFF << 8) +#define FSMC_PIO_IOSET 0xFF + +/* + * Memory bank boundary addresses + */ + +/** Pointer to base address of FSMC memory bank 1 (split into 4 + * regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip) */ +#define FSMC_BANK1 ((void*)0x60000000) + +/** Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM) */ +#define FSMC_NOR_PSRAM_REGION1 FSMC_BANK1 + +/** Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM) */ +#define FSMC_NOR_PSRAM_REGION2 ((void*)0x64000000) + +/** Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM) */ +#define FSMC_NOR_PSRAM_REGION3 ((void*)0x68000000) + +/** Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM) */ +#define FSMC_NOR_PSRAM_REGION4 ((void*)0x6C000000) + +/** Pointer to base address of FSMC memory bank 2 (for NAND Flash) */ +#define FSMC_BANK2 ((void*)0x70000000) + +/** Pointer to base address of FSMC memory bank 3 (for NAND Flash) */ +#define FSMC_BANK3 ((void*)0x80000000) + +/** Pointer to base address of FSMC memory bank 4 (for PC card devices */ +#define FSMC_BANK4 ((void*)0x90000000) + +/* + * SRAM/NOR Flash routines + */ + +void fsmc_sram_init_gpios(void); + +/** + * Set the DATAST bits in the given NOR/PSRAM register map's + * chip-select timing register (FSMC_BTR). + * + * @param regs NOR Flash/PSRAM register map whose chip-select timing + * register to set. + * @param datast Value to use for DATAST bits. + */ +static inline void fsmc_nor_psram_set_datast(fsmc_nor_psram_reg_map *regs, + uint8 datast) { + regs->BTR &= ~FSMC_BTR_DATAST; + regs->BTR |= datast << 8; +} + +/** + * Set the ADDHLD bits in the given NOR/PSRAM register map's chip + * select timing register (FSMC_BTRx). + * + * @param regs NOR Flash/PSRAM register map whose chip-select timing + * register to set. + * @param addset Value to use for ADDSET bits. + */ +static inline void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map *regs, + uint8 addset) { + regs->BTR &= ~FSMC_BTR_ADDSET; + regs->BTR |= addset & 0xF; +} + +#endif /* STM32_HIGH_DENSITY */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/libmaple/include/libmaple/gpio.h b/libmaple/include/libmaple/gpio.h new file mode 100644 index 0000000..685e1b1 --- /dev/null +++ b/libmaple/include/libmaple/gpio.h @@ -0,0 +1,526 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +/** + * @file gpio.h + * + * @brief General purpose I/O (GPIO) and Alternate Function I/O + * (AFIO) prototypes, defines, and inlined access functions. + */ + +#ifndef _LIBMAPLE_GPIO_H_ +#define _LIBMAPLE_GPIO_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/* + * GPIO register maps and devices + */ + +/** GPIO register map type */ +typedef struct gpio_reg_map { + __io uint32 CRL; /**< Port configuration register low */ + __io uint32 CRH; /**< Port configuration register high */ + __io uint32 IDR; /**< Port input data register */ + __io uint32 ODR; /**< Port output data register */ + __io uint32 BSRR; /**< Port bit set/reset register */ + __io uint32 BRR; /**< Port bit reset register */ + __io uint32 LCKR; /**< Port configuration lock register */ +} gpio_reg_map; + +/** + * @brief External interrupt line port selector. + * + * Used to determine which GPIO port to map an external interrupt line + * onto. */ +/* (See AFIO sections, below) */ +typedef enum afio_exti_port { + AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ + AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ + AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ + AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ +#ifdef STM32_HIGH_DENSITY + AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ + AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ + AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ +#endif +} afio_exti_port; + +/** GPIO device type */ +typedef struct gpio_dev { + gpio_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ + afio_exti_port exti_port; /**< AFIO external interrupt port value */ +} gpio_dev; + +extern gpio_dev gpioa; +extern gpio_dev* const GPIOA; +extern gpio_dev gpiob; +extern gpio_dev* const GPIOB; +extern gpio_dev gpioc; +extern gpio_dev* const GPIOC; +extern gpio_dev gpiod; +extern gpio_dev* const GPIOD; +#ifdef STM32_HIGH_DENSITY +extern gpio_dev gpioe; +extern gpio_dev* const GPIOE; +extern gpio_dev gpiof; +extern gpio_dev* const GPIOF; +extern gpio_dev gpiog; +extern gpio_dev* const GPIOG; +#endif + +/** GPIO port A register map base pointer */ +#define GPIOA_BASE ((struct gpio_reg_map*)0x40010800) +/** GPIO port B register map base pointer */ +#define GPIOB_BASE ((struct gpio_reg_map*)0x40010C00) +/** GPIO port C register map base pointer */ +#define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) +/** GPIO port D register map base pointer */ +#define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) +#ifdef STM32_HIGH_DENSITY +/** GPIO port E register map base pointer */ +#define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) +/** GPIO port F register map base pointer */ +#define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) +/** GPIO port G register map base pointer */ +#define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) +#endif + +/* + * GPIO register bit definitions + */ + +/* Control registers, low and high */ + +#define GPIO_CR_CNF (0x3 << 2) +#define GPIO_CR_CNF_INPUT_ANALOG (0x0 << 2) +#define GPIO_CR_CNF_INPUT_FLOATING (0x1 << 2) +#define GPIO_CR_CNF_INPUT_PU_PD (0x2 << 2) +#define GPIO_CR_CNF_OUTPUT_PP (0x0 << 2) +#define GPIO_CR_CNF_OUTPUT_OD (0x1 << 2) +#define GPIO_CR_CNF_AF_OUTPUT_PP (0x2 << 2) +#define GPIO_CR_CNF_AF_OUTPUT_OD (0x3 << 2) +#define GPIO_CR_MODE 0x3 +#define GPIO_CR_MODE_INPUT 0x0 +#define GPIO_CR_MODE_OUTPUT_10MHZ 0x1 +#define GPIO_CR_MODE_OUTPUT_2MHZ 0x2 +#define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 + +/** + * @brief GPIO Pin modes. + * + * These only allow for 50MHZ max output speeds; if you want slower, + * use direct register access. + */ +typedef enum gpio_pin_mode { + GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ + GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ + GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function + output push-pull. */ + GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function + output open drain. */ + GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | + GPIO_CR_MODE_INPUT), /**< Analog input. */ + GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | + GPIO_CR_MODE_INPUT), /**< Input floating. */ + GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | + GPIO_CR_MODE_INPUT), /**< Input pull-down. */ + GPIO_INPUT_PU /**< Input pull-up. */ + /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ +} gpio_pin_mode; + +/* + * GPIO Convenience routines + */ + +void gpio_init(gpio_dev *dev); +void gpio_init_all(void); +void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode); + +/** + * @brief Get a GPIO port's corresponding afio_exti_port. + * @param dev GPIO device whose afio_exti_port to return. + */ +static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { + return dev->exti_port; +} + +/** + * Set or reset a GPIO pin. + * + * Pin must have previously been configured to output mode. + * + * @param dev GPIO device whose pin to set. + * @param pin Pin on to set or reset + * @param val If true, set the pin. If false, reset the pin. + */ +static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) { + if (val) { + dev->regs->BSRR = BIT(pin); + } else { + dev->regs->BRR = BIT(pin); + } +} + +/** + * Determine whether or not a GPIO pin is set. + * + * Pin must have previously been configured to input mode. + * + * @param dev GPIO device whose pin to test. + * @param pin Pin on dev to test. + * @return True if the pin is set, false otherwise. + */ +static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) { + return dev->regs->IDR & BIT(pin); +} + +/** + * Toggle a pin configured as output push-pull. + * @param dev GPIO device. + * @param pin Pin on dev to toggle. + */ +static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) { + dev->regs->ODR = dev->regs->ODR ^ BIT(pin); +} + +/* + * AFIO register map + */ + +/** AFIO register map */ +typedef struct afio_reg_map { + __io uint32 EVCR; /**< Event control register. */ + __io uint32 MAPR; /**< AF remap and debug I/O configuration + register. */ + __io uint32 EXTICR1; /**< External interrupt configuration + register 1. */ + __io uint32 EXTICR2; /**< External interrupt configuration + register 2. */ + __io uint32 EXTICR3; /**< External interrupt configuration + register 3. */ + __io uint32 EXTICR4; /**< External interrupt configuration + register 4. */ + __io uint32 MAPR2; /**< AF remap and debug I/O configuration + register 2. */ +} afio_reg_map; + +/** AFIO register map base pointer. */ +#define AFIO_BASE ((struct afio_reg_map *)0x40010000) + +/* + * AFIO register bit definitions + */ + +/* Event control register */ + +#define AFIO_EVCR_EVOE (0x1 << 7) +#define AFIO_EVCR_PORT_PA (0x0 << 4) +#define AFIO_EVCR_PORT_PB (0x1 << 4) +#define AFIO_EVCR_PORT_PC (0x2 << 4) +#define AFIO_EVCR_PORT_PD (0x3 << 4) +#define AFIO_EVCR_PORT_PE (0x4 << 4) +#define AFIO_EVCR_PIN_0 0x0 +#define AFIO_EVCR_PIN_1 0x1 +#define AFIO_EVCR_PIN_2 0x2 +#define AFIO_EVCR_PIN_3 0x3 +#define AFIO_EVCR_PIN_4 0x4 +#define AFIO_EVCR_PIN_5 0x5 +#define AFIO_EVCR_PIN_6 0x6 +#define AFIO_EVCR_PIN_7 0x7 +#define AFIO_EVCR_PIN_8 0x8 +#define AFIO_EVCR_PIN_9 0x9 +#define AFIO_EVCR_PIN_10 0xA +#define AFIO_EVCR_PIN_11 0xB +#define AFIO_EVCR_PIN_12 0xC +#define AFIO_EVCR_PIN_13 0xD +#define AFIO_EVCR_PIN_14 0xE +#define AFIO_EVCR_PIN_15 0xF + +/* AF remap and debug I/O configuration register */ + +#define AFIO_MAPR_SWJ_CFG (0x7 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) +#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) +#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) +#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) +#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) +#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) +#define AFIO_MAPR_PD01_REMAP BIT(15) +#define AFIO_MAPR_CAN_REMAP (0x3 << 13) +#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) +#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) +#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) +#define AFIO_MAPR_TIM4_REMAP BIT(12) +#define AFIO_MAPR_TIM3_REMAP (0x3 << 10) +#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) +#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) +#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10) +#define AFIO_MAPR_TIM2_REMAP (0x3 << 8) +#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8) +#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8) +#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8) +#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8) +#define AFIO_MAPR_TIM1_REMAP (0x3 << 6) +#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6) +#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6) +#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6) +#define AFIO_MAPR_USART3_REMAP (0x3 << 4) +#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) +#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) +#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) +#define AFIO_MAPR_USART2_REMAP BIT(3) +#define AFIO_MAPR_USART1_REMAP BIT(2) +#define AFIO_MAPR_I2C1_REMAP BIT(1) +#define AFIO_MAPR_SPI1_REMAP BIT(0) + +/* External interrupt configuration register 1 */ + +#define AFIO_EXTICR1_EXTI3 (0xF << 12) +#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12) +#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12) +#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12) +#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12) +#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12) +#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12) +#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12) +#define AFIO_EXTICR1_EXTI2 (0xF << 8) +#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8) +#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8) +#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8) +#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8) +#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8) +#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8) +#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8) +#define AFIO_EXTICR1_EXTI1 (0xF << 4) +#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4) +#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4) +#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4) +#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4) +#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4) +#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4) +#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4) +#define AFIO_EXTICR1_EXTI0 0xF +#define AFIO_EXTICR1_EXTI0_PA 0x0 +#define AFIO_EXTICR1_EXTI0_PB 0x1 +#define AFIO_EXTICR1_EXTI0_PC 0x2 +#define AFIO_EXTICR1_EXTI0_PD 0x3 +#define AFIO_EXTICR1_EXTI0_PE 0x4 +#define AFIO_EXTICR1_EXTI0_PF 0x5 +#define AFIO_EXTICR1_EXTI0_PG 0x6 + +/* External interrupt configuration register 2 */ + +#define AFIO_EXTICR2_EXTI7 (0xF << 12) +#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12) +#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12) +#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12) +#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12) +#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12) +#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12) +#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12) +#define AFIO_EXTICR2_EXTI6 (0xF << 8) +#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8) +#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8) +#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8) +#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8) +#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8) +#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8) +#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8) +#define AFIO_EXTICR2_EXTI5 (0xF << 4) +#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4) +#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4) +#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4) +#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4) +#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4) +#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4) +#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4) +#define AFIO_EXTICR2_EXTI4 0xF +#define AFIO_EXTICR2_EXTI4_PA 0x0 +#define AFIO_EXTICR2_EXTI4_PB 0x1 +#define AFIO_EXTICR2_EXTI4_PC 0x2 +#define AFIO_EXTICR2_EXTI4_PD 0x3 +#define AFIO_EXTICR2_EXTI4_PE 0x4 +#define AFIO_EXTICR2_EXTI4_PF 0x5 +#define AFIO_EXTICR2_EXTI4_PG 0x6 + +/* AF remap and debug I/O configuration register 2 */ + +#define AFIO_MAPR2_FSMC_NADV BIT(10) +#define AFIO_MAPR2_TIM14_REMAP BIT(9) +#define AFIO_MAPR2_TIM13_REMAP BIT(8) +#define AFIO_MAPR2_TIM11_REMAP BIT(7) +#define AFIO_MAPR2_TIM10_REMAP BIT(6) +#define AFIO_MAPR2_TIM9_REMAP BIT(5) + +/* + * AFIO convenience routines + */ + +void afio_init(void); + +/** + * External interrupt line numbers. + */ +typedef enum afio_exti_num { + AFIO_EXTI_0, /**< External interrupt line 0. */ + AFIO_EXTI_1, /**< External interrupt line 1. */ + AFIO_EXTI_2, /**< External interrupt line 2. */ + AFIO_EXTI_3, /**< External interrupt line 3. */ + AFIO_EXTI_4, /**< External interrupt line 4. */ + AFIO_EXTI_5, /**< External interrupt line 5. */ + AFIO_EXTI_6, /**< External interrupt line 6. */ + AFIO_EXTI_7, /**< External interrupt line 7. */ + AFIO_EXTI_8, /**< External interrupt line 8. */ + AFIO_EXTI_9, /**< External interrupt line 9. */ + AFIO_EXTI_10, /**< External interrupt line 10. */ + AFIO_EXTI_11, /**< External interrupt line 11. */ + AFIO_EXTI_12, /**< External interrupt line 12. */ + AFIO_EXTI_13, /**< External interrupt line 13. */ + AFIO_EXTI_14, /**< External interrupt line 14. */ + AFIO_EXTI_15, /**< External interrupt line 15. */ +} afio_exti_num; + +void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); + +/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and + * not used in either MAPR or MAPR2 */ +#define AFIO_REMAP_USE_MAPR2 (1 << 31) + +/** + * @brief Available peripheral remaps. + * @see afio_remap() + */ +typedef enum afio_remap_peripheral { + AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< + ADC 2 external trigger regular conversion remapping */ + AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< + ADC 2 external trigger injected conversion remapping */ + AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< + ADC 1 external trigger regular conversion remapping */ + AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< + ADC 1 external trigger injected conversion remapping */ + AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< + Timer 5 channel 4 internal remapping */ + AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< + Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< + CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ + AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< + CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ + AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< + Timer 4 remapping */ + AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< + Timer 3 partial remapping */ + AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< + Timer 3 full remapping */ + AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< + Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 + on PA2, CH4 on PA3) */ + AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< + Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 + on PB10, CH4 on PB11) */ + AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< + Timer 2 full remapping */ + AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< + USART 2 remapping */ + AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< + USART 1 remapping */ + AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< + I2C 1 remapping */ + AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< + SPI 1 remapping */ + AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | + AFIO_REMAP_USE_MAPR2), /**< + NADV signal not connected */ + AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 14 remapping */ + AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 13 remapping */ + AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 11 remapping */ + AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 10 remapping */ + AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | + AFIO_REMAP_USE_MAPR2) /**< + Timer 9 */ +} afio_remap_peripheral; + +void afio_remap(afio_remap_peripheral p); + +/** + * @brief Debug port configuration + * + * Used to configure the behavior of JTAG and Serial Wire (SW) debug + * ports and their associated GPIO pins. + * + * @see afio_cfg_debug_ports() + */ +typedef enum afio_debug_cfg { + AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< + Full Serial Wire and JTAG debug */ + AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< + Full Serial Wire and JTAG, but no NJTRST. */ + AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< + Serial Wire debug only (JTAG-DP disabled, + SW-DP enabled) */ + AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< + No debug; all JTAG and SW pins are free + for use as GPIOs. */ +} afio_debug_cfg; + +/** + * @brief Enable or disable the JTAG and SW debug ports. + * @param config Desired debug port configuration + * @see afio_debug_cfg + */ +static inline void afio_cfg_debug_ports(afio_debug_cfg config) { + __io uint32 *mapr = &AFIO_BASE->MAPR; + *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h new file mode 100644 index 0000000..35c4628 --- /dev/null +++ b/libmaple/include/libmaple/i2c.h @@ -0,0 +1,348 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file i2c.h + * @brief Inter-Integrated Circuit (I2C) peripheral support + */ + +#ifndef _LIBMAPLE_I2C_H_ +#define _LIBMAPLE_I2C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/** I2C register map type */ +typedef struct i2c_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 OAR1; /**< Own address register 1 */ + __io uint32 OAR2; /**< Own address register 2 */ + __io uint32 DR; /**< Data register */ + __io uint32 SR1; /**< Status register 1 */ + __io uint32 SR2; /**< Status register 2 */ + __io uint32 CCR; /**< Clock control register */ + __io uint32 TRISE; /**< TRISE (rise time) register */ +} i2c_reg_map; + +/** I2C device states */ +typedef enum i2c_state { + I2C_STATE_DISABLED = 0, /**< Disabled */ + I2C_STATE_IDLE = 1, /**< Idle */ + I2C_STATE_XFER_DONE = 2, /**< Done with transfer */ + I2C_STATE_BUSY = 3, /**< Busy */ + I2C_STATE_ERROR = -1 /**< Error occurred */ +} i2c_state; + +/** + * @brief I2C message type + */ +typedef struct i2c_msg { + uint16 addr; /**< Address */ +#define I2C_MSG_READ 0x1 +#define I2C_MSG_10BIT_ADDR 0x2 + uint16 flags; /**< Bitwise OR of I2C_MSG_READ and + I2C_MSG_10BIT_ADDR */ + uint16 length; /**< Message length */ + uint16 xferred; /**< Messages transferred */ + uint8 *data; /**< Data */ +} i2c_msg; + +/** + * @brief I2C device type. + */ +typedef struct i2c_dev { + i2c_reg_map *regs; /**< Register map */ + gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ + uint8 sda_pin; /**< SDA bit on gpio_port */ + uint8 scl_pin; /**< SCL bit on gpio_port */ + rcc_clk_id clk_id; /**< RCC clock information */ + nvic_irq_num ev_nvic_line; /**< Event IRQ number */ + nvic_irq_num er_nvic_line; /**< Error IRQ number */ + volatile i2c_state state; /**< Device state */ + uint16 msgs_left; /**< Messages left */ + i2c_msg *msg; /**< Messages */ + volatile uint32 timestamp; /**< For internal use */ + uint32 error_flags; /**< Error flags, set on I2C error condition */ +} i2c_dev; + +/* + * Devices + */ + +extern i2c_dev* const I2C1; +extern i2c_dev* const I2C2; + +/* + * Register map base pointers + */ + +/** I2C1 register map base pointer */ +#define I2C1_BASE ((struct i2c_reg_map*)0x40005400) +/** I2C2 register map base pointer */ +#define I2C2_BASE ((struct i2c_reg_map*)0x40005800) + +/* + * Register bit definitions + */ + +/* Control register 1 */ + +#define I2C_CR1_SWRST BIT(15) // Software reset +#define I2C_CR1_ALERT BIT(13) // SMBus alert +#define I2C_CR1_PEC BIT(12) // Packet error checking +#define I2C_CR1_POS BIT(11) // Acknowledge/PEC position +#define I2C_CR1_ACK BIT(10) // Acknowledge enable +#define I2C_CR1_START BIT(8) // Start generation +#define I2C_CR1_STOP BIT(9) // Stop generation +#define I2C_CR1_PE BIT(0) // Peripheral Enable + +/* Control register 2 */ + +#define I2C_CR2_LAST BIT(12) // DMA last transfer +#define I2C_CR2_DMAEN BIT(11) // DMA requests enable +#define I2C_CR2_ITBUFEN BIT(10) // Buffer interrupt enable +#define I2C_CR2_ITEVTEN BIT(9) // Event interupt enable +#define I2C_CR2_ITERREN BIT(8) // Error interupt enable +#define I2C_CR2_FREQ 0xFFF // Peripheral input frequency + +/* Clock control register */ + +#define I2C_CCR_FS BIT(15) // Fast mode selection +#define I2C_CCR_DUTY BIT(14) // 16/9 duty ratio +#define I2C_CCR_CCR 0xFFF // Clock control bits + +/* Status register 1 */ + +#define I2C_SR1_SB BIT(0) // Start bit +#define I2C_SR1_ADDR BIT(1) // Address sent/matched +#define I2C_SR1_BTF BIT(2) // Byte transfer finished +#define I2C_SR1_ADD10 BIT(3) // 10-bit header sent +#define I2C_SR1_STOPF BIT(4) // Stop detection +#define I2C_SR1_RXNE BIT(6) // Data register not empty +#define I2C_SR1_TXE BIT(7) // Data register empty +#define I2C_SR1_BERR BIT(8) // Bus error +#define I2C_SR1_ARLO BIT(9) // Arbitration lost +#define I2C_SR1_AF BIT(10) // Acknowledge failure +#define I2C_SR1_OVR BIT(11) // Overrun/underrun +#define I2C_SR1_PECERR BIT(12) // PEC Error in reception +#define I2C_SR1_TIMEOUT BIT(14) // Timeout or Tlow error +#define I2C_SR1_SMBALERT BIT(15) // SMBus alert + +/* Status register 2 */ + +#define I2C_SR2_MSL BIT(0) // Master/slave +#define I2C_SR2_BUSY BIT(1) // Bus busy +#define I2C_SR2_TRA BIT(2) // Transmitter/receiver +#define I2C_SR2_GENCALL BIT(4) // General call address +#define I2C_SR2_SMBDEFAULT BIT(5) // SMBus device default address +#define I2C_SR2_SMBHOST BIT(6) // SMBus host header +#define I2C_SR2_DUALF BIT(7) // Dual flag +#define I2C_SR2_PEC 0xFF00 // Packet error checking register + +/* + * Convenience routines + */ + +void i2c_init(i2c_dev *dev); + +/* I2C enable options */ +#define I2C_FAST_MODE BIT(0) // 400 khz +#define I2C_DUTY_16_9 BIT(1) // 16/9 duty ratio +#define I2C_REMAP BIT(2) // Use alternate pin mapping +#define I2C_BUS_RESET BIT(3) // Perform a bus reset +void i2c_master_enable(i2c_dev *dev, uint32 flags); + +#define I2C_ERROR_PROTOCOL (-1) +#define I2C_ERROR_TIMEOUT (-2) +int32 i2c_master_xfer(i2c_dev *dev, i2c_msg *msgs, uint16 num, uint32 timeout); + +void i2c_bus_reset(const i2c_dev *dev); + +/** + * @brief Disable an I2C device + * + * This function disables the corresponding peripheral and marks dev's + * state as I2C_STATE_DISABLED. + * + * @param dev Device to disable. + */ +static inline void i2c_disable(i2c_dev *dev) { + dev->regs->CR1 &= ~I2C_CR1_PE; + dev->state = I2C_STATE_DISABLED; +} + +/** + * @brief Turn on an I2C peripheral + * @param dev Device to enable + */ +static inline void i2c_peripheral_enable(i2c_dev *dev) { + dev->regs->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Turn off an I2C peripheral + * @param dev Device to turn off + */ +static inline void i2c_peripheral_disable(i2c_dev *dev) { + dev->regs->CR1 &= ~I2C_CR1_PE; +} + +/** + * @brief Fill transmit register + * @param dev I2C device + * @param byte Byte to write + */ +static inline void i2c_write(i2c_dev *dev, uint8 byte) { + dev->regs->DR = byte; +} + +/** + * @brief Set input clock frequency, in MHz + * @param dev I2C device + * @param freq Frequency in megahertz (2-36) + */ +static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) { + uint32 cr2 = dev->regs->CR2; + cr2 &= ~I2C_CR2_FREQ; + cr2 |= freq; + dev->regs->CR2 = freq; +} + +/** + * @brief Set I2C clock control register. See RM008 + * @param dev I2C device + * @param val Value to use for clock control register (in + * Fast/Standard mode) + */ +static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) { + uint32 ccr = dev->regs->CCR; + ccr &= ~I2C_CCR_CCR; + ccr |= val; + dev->regs->CCR = ccr; +} + + +/** + * @brief Set SCL rise time + * @param dev I2C device + * @param trise Maximum rise time in fast/standard mode (see RM0008 + * for relevant formula). + */ +static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) { + dev->regs->TRISE = trise; +} + + +/** + * @brief Generate a start condition on the bus. + * @param dev I2C device + */ +static inline void i2c_start_condition(i2c_dev *dev) { + uint32 cr1; + while ((cr1 = dev->regs->CR1) & (I2C_CR1_START | + I2C_CR1_STOP | + I2C_CR1_PEC)) { + ; + } + dev->regs->CR1 |= I2C_CR1_START; +} + +/** + * @brief Generate a stop condition on the bus + * @param dev I2C device + */ +static inline void i2c_stop_condition(i2c_dev *dev) { + uint32 cr1; + while ((cr1 = dev->regs->CR1) & (I2C_CR1_START | + I2C_CR1_STOP | + I2C_CR1_PEC)) { + ; + } + dev->regs->CR1 |= I2C_CR1_STOP; + while ((cr1 = dev->regs->CR1) & (I2C_CR1_START | + I2C_CR1_STOP | + I2C_CR1_PEC)) { + ; + } + +} + +/** + * @brief Enable one or more I2C interrupts + * @param dev I2C device + * @param irqs Bitwise or of: + * I2C_IRQ_ERROR (error interrupt), + * I2C_IRQ_EVENT (event interrupt), and + * I2C_IRQ_BUFFER (buffer interrupt). + */ +#define I2C_IRQ_ERROR I2C_CR2_ITERREN +#define I2C_IRQ_EVENT I2C_CR2_ITEVTEN +#define I2C_IRQ_BUFFER I2C_CR2_ITBUFEN +static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) { + dev->regs->CR2 |= irqs; +} + +/** + * @brief Disable one or more I2C interrupts + * @param dev I2C device + * @param irqs Bitwise or of: + * I2C_IRQ_ERROR (error interrupt), + * I2C_IRQ_EVENT (event interrupt), and + * I2C_IRQ_BUFFER (buffer interrupt). + */ +static inline void i2c_disable_irq(i2c_dev *dev, uint32 irqs) { + dev->regs->CR2 &= ~irqs; +} + + +/** + * @brief Enable I2C acknowledgment + * @param dev I2C device + */ +static inline void i2c_enable_ack(i2c_dev *dev) { + dev->regs->CR1 |= I2C_CR1_ACK; +} + +/** + * @brief Disable I2C acknowledgment + * @param dev I2C device + */ +static inline void i2c_disable_ack(i2c_dev *dev) { + dev->regs->CR1 &= ~I2C_CR1_ACK; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/iwdg.h b/libmaple/include/libmaple/iwdg.h new file mode 100644 index 0000000..baddf4f --- /dev/null +++ b/libmaple/include/libmaple/iwdg.h @@ -0,0 +1,116 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Michael Hope. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file iwdg.h + * @author Michael Hope, Marti Bolivar + * @brief Independent watchdog support. + * + * To use the independent watchdog, first call iwdg_init() with the + * appropriate prescaler and IWDG counter reload values for your + * application. Afterwards, you must periodically call iwdg_feed() + * before the IWDG counter reaches 0 to reset the counter to its + * reload value. If you do not, the chip will reset. + * + * Once started, the independent watchdog cannot be turned off. + */ + +#ifndef _LIBMAPLE_IWDG_H_ +#define _LIBMAPLE_IWDG_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/* + * Register map + */ + +/** Independent watchdog register map type. */ +typedef struct iwdg_reg_map { + __io uint32 KR; /**< Key register. */ + __io uint32 PR; /**< Prescaler register. */ + __io uint32 RLR; /**< Reload register. */ + __io uint32 SR; /**< Status register */ +} iwdg_reg_map; + +/** Independent watchdog base pointer */ +#define IWDG_BASE ((struct iwdg_reg_map*)0x40003000) + +/* + * Register bit definitions + */ + +/* Key register */ + +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_FEED 0xAAAA +#define IWDG_KR_START 0xCCCC + +/* Prescaler register */ + +#define IWDG_PR_DIV_4 0x0 +#define IWDG_PR_DIV_8 0x1 +#define IWDG_PR_DIV_16 0x2 +#define IWDG_PR_DIV_32 0x3 +#define IWDG_PR_DIV_64 0x4 +#define IWDG_PR_DIV_128 0x5 +#define IWDG_PR_DIV_256 0x6 + +/* Status register */ + +#define IWDG_SR_RVU_BIT 1 +#define IWDG_SR_PVU_BIT 0 + +#define IWDG_SR_RVU BIT(IWDG_SR_RVU_BIT) +#define IWDG_SR_PVU BIT(IWDG_SR_PVU_BIT) + +/** + * @brief Independent watchdog prescalers. + * + * These divide the 40 kHz IWDG clock. + */ +typedef enum iwdg_prescaler { + IWDG_PRE_4 = IWDG_PR_DIV_4, /**< Divide by 4 */ + IWDG_PRE_8 = IWDG_PR_DIV_8, /**< Divide by 8 */ + IWDG_PRE_16 = IWDG_PR_DIV_16, /**< Divide by 16 */ + IWDG_PRE_32 = IWDG_PR_DIV_32, /**< Divide by 32 */ + IWDG_PRE_64 = IWDG_PR_DIV_64, /**< Divide by 64 */ + IWDG_PRE_128 = IWDG_PR_DIV_128, /**< Divide by 128 */ + IWDG_PRE_256 = IWDG_PR_DIV_256 /**< Divide by 256 */ +} iwdg_prescaler; + +void iwdg_init(iwdg_prescaler prescaler, uint16 reload); +void iwdg_feed(void); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/libmaple.h b/libmaple/include/libmaple/libmaple.h new file mode 100644 index 0000000..60b23ed --- /dev/null +++ b/libmaple/include/libmaple/libmaple.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple.h + * @brief General include file for libmaple + */ + +#ifndef _LIBMAPLE_LIBMAPLE_H_ +#define _LIBMAPLE_LIBMAPLE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/* + * Where to put usercode, based on space reserved for bootloader. + * + * FIXME this has no business being here + */ +#define USER_ADDR_ROM 0x08005000 +#define USER_ADDR_RAM 0x20000C00 +#define STACK_TOP 0x20000800 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h new file mode 100644 index 0000000..ae01691 --- /dev/null +++ b/libmaple/include/libmaple/libmaple_types.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple_types.h + * + * @brief libmaple types + */ + +#ifndef _LIBMAPLE_LIBMAPLE_TYPES_H_ +#define _LIBMAPLE_LIBMAPLE_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef unsigned long long uint64; + +typedef signed char int8; +typedef short int16; +typedef int int32; +typedef long long int64; + +typedef void (*voidFuncPtr)(void); + +#define __io volatile +#define __attr_flash __attribute__((section (".USER_FLASH"))) +#define __packed __attribute__((__packed__)) + +#ifndef NULL +#define NULL 0 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h new file mode 100644 index 0000000..d631eeb --- /dev/null +++ b/libmaple/include/libmaple/nvic.h @@ -0,0 +1,241 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file nvic.h + * @brief Nested vector interrupt controller support. + * + * Basic usage: + * + * @code + * // Initialise the interrupt controller and point to the vector + * // table at the start of flash. + * nvic_init(0x08000000, 0); + * // Bind in a timer interrupt handler + * timer_attach_interrupt(TIMER_CC1_INTERRUPT, handler); + * // Optionally set the priority + * nvic_irq_set_priority(NVIC_TIMER1_CC, 5); + * // All done, enable all interrupts + * nvic_globalirq_enable(); + * @endcode + */ + +#ifndef _LIBMAPLE_NVIC_H_ +#define _LIBMAPLE_NVIC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/** NVIC register map type. */ +typedef struct nvic_reg_map { + __io uint32 ISER[8]; /**< Interrupt Set Enable Registers */ + uint32 RESERVED0[24]; /**< Reserved */ + __io uint32 ICER[8]; /**< Interrupt Clear Enable Registers */ + uint32 RSERVED1[24]; /**< Reserved */ + __io uint32 ISPR[8]; /**< Interrupt Set Pending Registers */ + uint32 RESERVED2[24]; /**< Reserved */ + __io uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */ + uint32 RESERVED3[24]; /**< Reserved */ + __io uint32 IABR[8]; /**< Interrupt Active bit Registers */ + uint32 RESERVED4[56]; /**< Reserved */ + __io uint8 IP[240]; /**< Interrupt Priority Registers */ + uint32 RESERVED5[644]; /**< Reserved */ + __io uint32 STIR; /**< Software Trigger Interrupt Registers */ +} nvic_reg_map; + +/** NVIC register map base pointer. */ +#define NVIC_BASE ((struct nvic_reg_map*)0xE000E100) + +/** + * @brief Interrupt vector table interrupt numbers. + * + * Each positive-valued enumerator is the position of the + * corresponding interrupt in the vector table. Negative-valued + * enumerators correspond to interrupts controlled by the system + * handler block. + * + * @see scb.h + */ +typedef enum nvic_irq_num { + NVIC_NMI = -14, /**< Non-maskable interrupt */ + NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ + NVIC_MEM_MANAGE = -12, /**< Memory management */ + NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory + access fault. */ + NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction or + illegal state. */ + NVIC_SVC = -5, /**< System service call via SWI insruction */ + NVIC_DEBUG_MON = -4, /**< Debug monitor */ + NVIC_PEND_SVC = -2, /**< Pendable request for system service */ + NVIC_SYSTICK = -1, /**< System tick timer */ + NVIC_WWDG = 0, /**< Window watchdog interrupt */ + NVIC_PVD = 1, /**< PVD through EXTI line detection */ + NVIC_TAMPER = 2, /**< Tamper */ + NVIC_RTC = 3, /**< Real-time clock */ + NVIC_FLASH = 4, /**< Flash */ + NVIC_RCC = 5, /**< Reset and clock control */ + NVIC_EXTI0 = 6, /**< EXTI line 0 */ + NVIC_EXTI1 = 7, /**< EXTI line 1 */ + NVIC_EXTI2 = 8, /**< EXTI line 2 */ + NVIC_EXTI3 = 9, /**< EXTI line 3 */ + NVIC_EXTI4 = 10, /**< EXTI line 4 */ + NVIC_DMA_CH1 = 11, /**< DMA1 channel 1 */ + NVIC_DMA_CH2 = 12, /**< DMA1 channel 2 */ + NVIC_DMA_CH3 = 13, /**< DMA1 channel 3 */ + NVIC_DMA_CH4 = 14, /**< DMA1 channel 4 */ + NVIC_DMA_CH5 = 15, /**< DMA1 channel 5 */ + NVIC_DMA_CH6 = 16, /**< DMA1 channel 6 */ + NVIC_DMA_CH7 = 17, /**< DMA1 channel 7 */ + NVIC_ADC_1_2 = 18, /**< ADC1 and ADC2 */ + NVIC_USB_HP_CAN_TX = 19, /**< USB high priority or CAN TX */ + NVIC_USB_LP_CAN_RX0 = 20, /**< USB low priority or CAN RX0 */ + NVIC_CAN_RX1 = 21, /**< CAN RX1 */ + NVIC_CAN_SCE = 22, /**< CAN SCE */ + NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ + NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ + NVIC_TIMER1_UP = 25, /**< Timer 1 update */ + NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ + NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ + NVIC_TIMER2 = 28, /**< Timer 2 */ + NVIC_TIMER3 = 29, /**< Timer 3 */ + NVIC_TIMER4 = 30, /**< Timer 4 */ + NVIC_I2C1_EV = 31, /**< I2C1 event */ + NVIC_I2C1_ER = 32, /**< I2C1 error */ + NVIC_I2C2_EV = 33, /**< I2C2 event */ + NVIC_I2C2_ER = 34, /**< I2C2 error */ + NVIC_SPI1 = 35, /**< SPI1 */ + NVIC_SPI2 = 36, /**< SPI2 */ + NVIC_USART1 = 37, /**< USART1 */ + NVIC_USART2 = 38, /**< USART2 */ + NVIC_USART3 = 39, /**< USART3 */ + NVIC_EXTI_15_10 = 40, /**< EXTI line [15:10] */ + NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ + NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through + EXTI line */ + NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ + NVIC_TIMER8_UP = 44, /**< Timer 8 update */ + NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ + NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ +#ifdef STM32_HIGH_DENSITY + NVIC_ADC3 = 47, /**< ADC3 */ + NVIC_FSMC = 48, /**< FSMC */ + NVIC_SDIO = 49, /**< SDIO */ + NVIC_TIMER5 = 50, /**< Timer 5 */ + NVIC_SPI3 = 51, /**< SPI3 */ + NVIC_UART4 = 52, /**< UART4 */ + NVIC_UART5 = 53, /**< UART5 */ + NVIC_TIMER6 = 54, /**< Timer 6 */ + NVIC_TIMER7 = 55, /**< Timer 7 */ + NVIC_DMA2_CH1 = 56, /**< DMA2 channel 1 */ + NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ + NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ + NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ +#endif +} nvic_irq_num; + +/* + * Initialises the interrupt controller and sets all interrupts to the + * lowest priority. + * + * For stand-alone products, the base address is normally the start of + * flash (0x08000000). + * + * @param vector_table_address base address of the vector table + */ +void nvic_init(uint32 vector_table_address, uint32 offset); + +/** + * Sets the base address of the vector table. + */ +void nvic_set_vector_table(uint32 address, uint32 offset); + +void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority); +void nvic_sys_reset(); + +/** + * Enables interrupts and configurable fault handlers (clear PRIMASK). + */ +static inline void nvic_globalirq_enable() { + asm volatile("cpsie i"); +} + +/** + * Disable interrupts and configurable fault handlers (set PRIMASK). + */ +static inline void nvic_globalirq_disable() { + asm volatile("cpsid i"); +} + +/** + * @brief Enable interrupt irq_num + * @param irq_num Interrupt to enable + */ +static inline void nvic_irq_enable(nvic_irq_num irq_num) { + if (irq_num < 0) { + return; + } + NVIC_BASE->ISER[irq_num / 32] = BIT(irq_num % 32); +} + +/** + * @brief Disable interrupt irq_num + * @param irq_num Interrupt to disable + */ +static inline void nvic_irq_disable(nvic_irq_num irq_num) { + if (irq_num < 0) { + return; + } + NVIC_BASE->ICER[irq_num / 32] = BIT(irq_num % 32); +} + +/** + * @brief Quickly disable all interrupts. + * + * Calling this function is significantly faster than calling + * nvic_irq_disable() in a loop. + */ +static inline void nvic_irq_disable_all(void) { + /* Note: This only works up to XL density. The fix for + * connectivity line is: + * + * NVIC_BASE->ICER[2] = 0xF; + * + * We don't support connectivity line devices (yet), so leave it + * alone for now. + */ + NVIC_BASE->ICER[0] = 0xFFFFFFFF; + NVIC_BASE->ICER[1] = 0xFFFFFFFF; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/pwr.h b/libmaple/include/libmaple/pwr.h new file mode 100644 index 0000000..6836e7f --- /dev/null +++ b/libmaple/include/libmaple/pwr.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file pwr.h + * @brief Power control (PWR) defines. + */ + +#ifndef _LIBMAPLE_PWR_H_ +#define _LIBMAPLE_PWR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** Power interface register map. */ +typedef struct pwr_reg_map { + __io uint32 CR; /**< Control register */ + __io uint32 CSR; /**< Control and status register */ +} pwr_reg_map; + +/** Power peripheral register map base pointer. */ +#define PWR_BASE ((struct pwr_reg_map*)0x40007000) + +/* + * Register bit definitions + */ + +/* Control register */ + +/** Disable backup domain write protection bit */ +#define PWR_CR_DBP 8 +/** Power voltage detector enable bit */ +#define PWR_CR_PVDE 4 +/** Clear standby flag bit */ +#define PWR_CR_CSBF 3 +/** Clear wakeup flag bit */ +#define PWR_CR_CWUF 2 +/** Power down deepsleep bit */ +#define PWR_CR_PDDS 1 +/** Low-power deepsleep bit */ +#define PWR_CR_LPDS 0 + +/* Control and status register */ + +/** Enable wakeup pin bit */ +#define PWR_CSR_EWUP 8 +/** PVD output bit */ +#define PWR_CSR_PVDO 2 +/** Standby flag bit */ +#define PWR_CSR_SBF 1 +/** Wakeup flag bit */ +#define PWR_CSR_WUF 0 + +/* + * Convenience functions + */ + +void pwr_init(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h new file mode 100644 index 0000000..ef44b68 --- /dev/null +++ b/libmaple/include/libmaple/rcc.h @@ -0,0 +1,570 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file rcc.h + * @brief reset and clock control definitions and prototypes + */ + +#ifndef _LIBMAPLE_RCC_H_ +#define _LIBMAPLE_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** RCC register map type */ +typedef struct rcc_reg_map { + __io uint32 CR; /**< Clock control register */ + __io uint32 CFGR; /**< Clock configuration register */ + __io uint32 CIR; /**< Clock interrupt register */ + __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ + __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ + __io uint32 AHBENR; /**< AHB peripheral clock enable register */ + __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ + __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ + __io uint32 BDCR; /**< Backup domain control register */ + __io uint32 CSR; /**< Control/status register */ +} rcc_reg_map; + +/** RCC register map base pointer */ +#define RCC_BASE ((struct rcc_reg_map*)0x40021000) + +/* + * Register bit definitions + */ + +/* Clock control register */ + +#define RCC_CR_PLLRDY_BIT 25 +#define RCC_CR_PLLON_BIT 24 +#define RCC_CR_CSSON_BIT 19 +#define RCC_CR_HSEBYP_BIT 18 +#define RCC_CR_HSERDY_BIT 17 +#define RCC_CR_HSEON_BIT 16 +#define RCC_CR_HSIRDY_BIT 1 +#define RCC_CR_HSION_BIT 0 + +#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) +#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) +#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) +#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) +#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) +#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) +#define RCC_CR_HSICAL (0xFF << 8) +#define RCC_CR_HSITRIM (0x1F << 3) +#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) +#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) + +/* Clock configuration register */ + +#define RCC_CFGR_USBPRE_BIT 22 +#define RCC_CFGR_PLLXTPRE_BIT 17 +#define RCC_CFGR_PLLSRC_BIT 16 + +#define RCC_CFGR_MCO (0x3 << 24) +#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) +#define RCC_CFGR_PLLMUL (0xF << 18) +#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) +#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) +#define RCC_CFGR_ADCPRE (0x3 << 14) +#define RCC_CFGR_PPRE2 (0x7 << 11) +#define RCC_CFGR_PPRE1 (0x7 << 8) +#define RCC_CFGR_HPRE (0xF << 4) +#define RCC_CFGR_SWS (0x3 << 2) +#define RCC_CFGR_SWS_PLL (0x2 << 2) +#define RCC_CFGR_SWS_HSE (0x1 << 2) +#define RCC_CFGR_SW 0x3 +#define RCC_CFGR_SW_PLL 0x2 +#define RCC_CFGR_SW_HSE 0x1 + +/* Clock interrupt register */ + +#define RCC_CIR_CSSC_BIT 23 +#define RCC_CIR_PLLRDYC_BIT 20 +#define RCC_CIR_HSERDYC_BIT 19 +#define RCC_CIR_HSIRDYC_BIT 18 +#define RCC_CIR_LSERDYC_BIT 17 +#define RCC_CIR_LSIRDYC_BIT 16 +#define RCC_CIR_PLLRDYIE_BIT 12 +#define RCC_CIR_HSERDYIE_BIT 11 +#define RCC_CIR_HSIRDYIE_BIT 10 +#define RCC_CIR_LSERDYIE_BIT 9 +#define RCC_CIR_LSIRDYIE_BIT 8 +#define RCC_CIR_CSSF_BIT 7 +#define RCC_CIR_PLLRDYF_BIT 4 +#define RCC_CIR_HSERDYF_BIT 3 +#define RCC_CIR_HSIRDYF_BIT 2 +#define RCC_CIR_LSERDYF_BIT 1 +#define RCC_CIR_LSIRDYF_BIT 0 + +#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) +#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) +#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) +#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) +#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) +#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) +#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) +#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) +#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) +#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) +#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) +#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) +#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) +#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) +#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) +#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) +#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM11RST_BIT 21 +#define RCC_APB2RSTR_TIM10RST_BIT 20 +#define RCC_APB2RSTR_TIM9RST_BIT 19 +#define RCC_APB2RSTR_ADC3RST_BIT 15 +#define RCC_APB2RSTR_USART1RST_BIT 14 +#define RCC_APB2RSTR_TIM8RST_BIT 13 +#define RCC_APB2RSTR_SPI1RST_BIT 12 +#define RCC_APB2RSTR_TIM1RST_BIT 11 +#define RCC_APB2RSTR_ADC2RST_BIT 10 +#define RCC_APB2RSTR_ADC1RST_BIT 9 +#define RCC_APB2RSTR_IOPGRST_BIT 8 +#define RCC_APB2RSTR_IOPFRST_BIT 7 +#define RCC_APB2RSTR_IOPERST_BIT 6 +#define RCC_APB2RSTR_IOPDRST_BIT 5 +#define RCC_APB2RSTR_IOPCRST_BIT 4 +#define RCC_APB2RSTR_IOPBRST_BIT 3 +#define RCC_APB2RSTR_IOPARST_BIT 2 +#define RCC_APB2RSTR_AFIORST_BIT 0 + +#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) +#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) +#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) +#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) +#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) +#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) +#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) +#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) +#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) +#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) +#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) +#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) +#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) +#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) +#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) +#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) +#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) +#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) + +/* APB1 peripheral reset register */ + +#define RCC_APB1RSTR_DACRST_BIT 29 +#define RCC_APB1RSTR_PWRRST_BIT 28 +#define RCC_APB1RSTR_BKPRST_BIT 27 +#define RCC_APB1RSTR_CANRST_BIT 25 +#define RCC_APB1RSTR_USBRST_BIT 23 +#define RCC_APB1RSTR_I2C2RST_BIT 22 +#define RCC_APB1RSTR_I2C1RST_BIT 21 +#define RCC_APB1RSTR_UART5RST_BIT 20 +#define RCC_APB1RSTR_UART4RST_BIT 19 +#define RCC_APB1RSTR_USART3RST_BIT 18 +#define RCC_APB1RSTR_USART2RST_BIT 17 +#define RCC_APB1RSTR_SPI3RST_BIT 15 +#define RCC_APB1RSTR_SPI2RST_BIT 14 +#define RCC_APB1RSTR_WWDRST_BIT 11 +#define RCC_APB1RSTR_TIM14RST_BIT 8 +#define RCC_APB1RSTR_TIM13RST_BIT 7 +#define RCC_APB1RSTR_TIM12RST_BIT 6 +#define RCC_APB1RSTR_TIM7RST_BIT 5 +#define RCC_APB1RSTR_TIM6RST_BIT 4 +#define RCC_APB1RSTR_TIM5RST_BIT 3 +#define RCC_APB1RSTR_TIM4RST_BIT 2 +#define RCC_APB1RSTR_TIM3RST_BIT 1 +#define RCC_APB1RSTR_TIM2RST_BIT 0 + +#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) +#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) +#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) +#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) +#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) +#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) +#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) +#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) +#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) +#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) +#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) +#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) +#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) +#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) +#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) +#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) +#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) +#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) +#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) +#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) +#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) +#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) +#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) + +/* AHB peripheral clock enable register */ + +#define RCC_AHBENR_SDIOEN_BIT 10 +#define RCC_AHBENR_FSMCEN_BIT 8 +#define RCC_AHBENR_CRCEN_BIT 7 +#define RCC_AHBENR_FLITFEN_BIT 4 +#define RCC_AHBENR_SRAMEN_BIT 2 +#define RCC_AHBENR_DMA2EN_BIT 1 +#define RCC_AHBENR_DMA1EN_BIT 0 + +#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) +#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) +#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) +#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) +#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) +#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) +#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) + +/* APB2 peripheral clock enable register */ + +#define RCC_APB2ENR_TIM11EN_BIT 21 +#define RCC_APB2ENR_TIM10EN_BIT 20 +#define RCC_APB2ENR_TIM9EN_BIT 19 +#define RCC_APB2ENR_ADC3EN_BIT 15 +#define RCC_APB2ENR_USART1EN_BIT 14 +#define RCC_APB2ENR_TIM8EN_BIT 13 +#define RCC_APB2ENR_SPI1EN_BIT 12 +#define RCC_APB2ENR_TIM1EN_BIT 11 +#define RCC_APB2ENR_ADC2EN_BIT 10 +#define RCC_APB2ENR_ADC1EN_BIT 9 +#define RCC_APB2ENR_IOPGEN_BIT 8 +#define RCC_APB2ENR_IOPFEN_BIT 7 +#define RCC_APB2ENR_IOPEEN_BIT 6 +#define RCC_APB2ENR_IOPDEN_BIT 5 +#define RCC_APB2ENR_IOPCEN_BIT 4 +#define RCC_APB2ENR_IOPBEN_BIT 3 +#define RCC_APB2ENR_IOPAEN_BIT 2 +#define RCC_APB2ENR_AFIOEN_BIT 0 + +#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) +#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) +#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) +#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) +#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) +#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) +#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) +#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) +#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) +#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) +#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) +#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) +#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) +#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) +#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) +#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) +#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) +#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) + +/* APB1 peripheral clock enable register */ + +#define RCC_APB1ENR_DACEN_BIT 29 +#define RCC_APB1ENR_PWREN_BIT 28 +#define RCC_APB1ENR_BKPEN_BIT 27 +#define RCC_APB1ENR_CANEN_BIT 25 +#define RCC_APB1ENR_USBEN_BIT 23 +#define RCC_APB1ENR_I2C2EN_BIT 22 +#define RCC_APB1ENR_I2C1EN_BIT 21 +#define RCC_APB1ENR_UART5EN_BIT 20 +#define RCC_APB1ENR_UART4EN_BIT 19 +#define RCC_APB1ENR_USART3EN_BIT 18 +#define RCC_APB1ENR_USART2EN_BIT 17 +#define RCC_APB1ENR_SPI3EN_BIT 15 +#define RCC_APB1ENR_SPI2EN_BIT 14 +#define RCC_APB1ENR_WWDEN_BIT 11 +#define RCC_APB1ENR_TIM14EN_BIT 8 +#define RCC_APB1ENR_TIM13EN_BIT 7 +#define RCC_APB1ENR_TIM12EN_BIT 6 +#define RCC_APB1ENR_TIM7EN_BIT 5 +#define RCC_APB1ENR_TIM6EN_BIT 4 +#define RCC_APB1ENR_TIM5EN_BIT 3 +#define RCC_APB1ENR_TIM4EN_BIT 2 +#define RCC_APB1ENR_TIM3EN_BIT 1 +#define RCC_APB1ENR_TIM2EN_BIT 0 + +#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) +#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) +#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) +#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) +#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) +#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) +#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) +#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) +#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) +#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) +#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) +#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) +#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) +#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) +#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) +#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) +#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) +#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) +#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) +#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) +#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) +#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) +#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) + +/* Backup domain control register */ + +#define RCC_BDCR_BDRST_BIT 16 +#define RCC_BDCR_RTCEN_BIT 15 +#define RCC_BDCR_LSEBYP_BIT 2 +#define RCC_BDCR_LSERDY_BIT 1 +#define RCC_BDCR_LSEON_BIT 0 + +#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) +#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) +#define RCC_BDCR_RTCSEL (0x3 << 8) +#define RCC_BDCR_RTCSEL_NONE (0x0 << 8) +#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) +#define RCC_BDCR_RTCSEL_HSE (0x3 << 8) +#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) +#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) +#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) + +/* Control/status register */ + +#define RCC_CSR_LPWRRSTF_BIT 31 +#define RCC_CSR_WWDGRSTF_BIT 30 +#define RCC_CSR_IWDGRSTF_BIT 29 +#define RCC_CSR_SFTRSTF_BIT 28 +#define RCC_CSR_PORRSTF_BIT 27 +#define RCC_CSR_PINRSTF_BIT 26 +#define RCC_CSR_RMVF_BIT 24 +#define RCC_CSR_LSIRDY_BIT 1 +#define RCC_CSR_LSION_BIT 0 + +#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) +#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) +#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) +#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) +#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) +#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) +#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) +#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) +#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) + +/* + * Convenience routines + */ + +/** + * SYSCLK sources + * @see rcc_clk_init() + */ +typedef enum rcc_sysclk_src { + RCC_CLKSRC_HSI = 0x0, + RCC_CLKSRC_HSE = 0x1, + RCC_CLKSRC_PLL = 0x2, +} rcc_sysclk_src; + +/** + * PLL entry clock source + * @see rcc_clk_init() + */ +typedef enum rcc_pllsrc { + RCC_PLLSRC_HSE = (0x1 << 16), + RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) +} rcc_pllsrc; + +/** + * PLL multipliers + * @see rcc_clk_init() + */ +typedef enum rcc_pll_multiplier { + RCC_PLLMUL_2 = (0x0 << 18), + RCC_PLLMUL_3 = (0x1 << 18), + RCC_PLLMUL_4 = (0x2 << 18), + RCC_PLLMUL_5 = (0x3 << 18), + RCC_PLLMUL_6 = (0x4 << 18), + RCC_PLLMUL_7 = (0x5 << 18), + RCC_PLLMUL_8 = (0x6 << 18), + RCC_PLLMUL_9 = (0x7 << 18), + RCC_PLLMUL_10 = (0x8 << 18), + RCC_PLLMUL_11 = (0x9 << 18), + RCC_PLLMUL_12 = (0xA << 18), + RCC_PLLMUL_13 = (0xB << 18), + RCC_PLLMUL_14 = (0xC << 18), + RCC_PLLMUL_15 = (0xD << 18), + RCC_PLLMUL_16 = (0xE << 18), +} rcc_pll_multiplier; + +/** + * @brief Identifies bus and clock line for a peripheral. + * + * Also generally useful as a unique identifier for that peripheral + * (or its corresponding device struct). + */ +typedef enum rcc_clk_id { + RCC_GPIOA, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, + RCC_AFIO, + RCC_ADC1, + RCC_ADC2, + RCC_ADC3, + RCC_USART1, + RCC_USART2, + RCC_USART3, + RCC_TIMER1, + RCC_TIMER2, + RCC_TIMER3, + RCC_TIMER4, + RCC_SPI1, + RCC_SPI2, + RCC_DMA1, + RCC_PWR, + RCC_BKP, + RCC_I2C1, + RCC_I2C2, + RCC_CRC, + RCC_FLITF, + RCC_SRAM, + RCC_USB, +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + RCC_GPIOE, + RCC_GPIOF, + RCC_GPIOG, + RCC_UART4, + RCC_UART5, + RCC_TIMER5, + RCC_TIMER6, + RCC_TIMER7, + RCC_TIMER8, + RCC_FSMC, + RCC_DAC, + RCC_DMA2, + RCC_SDIO, + RCC_SPI3, +#endif +#ifdef STM32_XL_DENSITY + RCC_TIMER9, + RCC_TIMER10, + RCC_TIMER11, + RCC_TIMER12, + RCC_TIMER13, + RCC_TIMER14, +#endif +} rcc_clk_id; + +void rcc_clk_init(rcc_sysclk_src sysclk_src, + rcc_pllsrc pll_src, + rcc_pll_multiplier pll_mul); +void rcc_clk_enable(rcc_clk_id device); +void rcc_reset_dev(rcc_clk_id device); + +typedef enum rcc_clk_domain { + RCC_APB1, + RCC_APB2, + RCC_AHB +} rcc_clk_domain; + +rcc_clk_domain rcc_dev_clk(rcc_clk_id device); + +/** + * Prescaler identifiers + * @see rcc_set_prescaler() + */ +typedef enum rcc_prescaler { + RCC_PRESCALER_AHB, + RCC_PRESCALER_APB1, + RCC_PRESCALER_APB2, + RCC_PRESCALER_USB, + RCC_PRESCALER_ADC +} rcc_prescaler; + +/** + * ADC prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_adc_divider { + RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14, + RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14, + RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14, + RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14, +} rcc_adc_divider; + +/** + * APB1 prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_apb1_divider { + RCC_APB1_HCLK_DIV_1 = 0x0 << 8, + RCC_APB1_HCLK_DIV_2 = 0x4 << 8, + RCC_APB1_HCLK_DIV_4 = 0x5 << 8, + RCC_APB1_HCLK_DIV_8 = 0x6 << 8, + RCC_APB1_HCLK_DIV_16 = 0x7 << 8, +} rcc_apb1_divider; + +/** + * APB2 prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_apb2_divider { + RCC_APB2_HCLK_DIV_1 = 0x0 << 11, + RCC_APB2_HCLK_DIV_2 = 0x4 << 11, + RCC_APB2_HCLK_DIV_4 = 0x5 << 11, + RCC_APB2_HCLK_DIV_8 = 0x6 << 11, + RCC_APB2_HCLK_DIV_16 = 0x7 << 11, +} rcc_apb2_divider; + +/** + * AHB prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_ahb_divider { + RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4, + RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4, + RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4, + RCC_AHB_SYSCLK_DIV_8 = 0xA << 4, + RCC_AHB_SYSCLK_DIV_16 = 0xB << 4, + RCC_AHB_SYSCLK_DIV_32 = 0xC << 4, + RCC_AHB_SYSCLK_DIV_64 = 0xD << 4, + RCC_AHB_SYSCLK_DIV_128 = 0xD << 4, + RCC_AHB_SYSCLK_DIV_256 = 0xE << 4, + RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, +} rcc_ahb_divider; + +void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/ring_buffer.h b/libmaple/include/libmaple/ring_buffer.h new file mode 100644 index 0000000..7169e7e --- /dev/null +++ b/libmaple/include/libmaple/ring_buffer.h @@ -0,0 +1,188 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file ring_buffer.h + * @brief Simple circular buffer + * + * This implementation is not thread-safe. In particular, none of + * these functions is guaranteed re-entrant. + */ + +#ifndef _LIBMAPLE_RING_BUFFER_H_ +#define _LIBMAPLE_RING_BUFFER_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Ring buffer type. + * + * The buffer is empty when head == tail. + * + * The buffer is full when the head is one byte in front of the tail, + * modulo buffer length. + * + * One byte is left free to distinguish empty from full. */ +typedef struct ring_buffer { + volatile uint8 *buf; /**< Buffer items are stored into */ + uint16 head; /**< Index of the next item to remove */ + uint16 tail; /**< Index where the next item will get inserted */ + uint16 size; /**< Buffer capacity minus one */ +} ring_buffer; + +/** + * Initialise a ring buffer. + * + * @param rb Instance to initialise + * + * @param size Number of items in buf. The ring buffer will always + * leave one element unoccupied, so the maximum number of + * elements it can store will be size - 1. Thus, size + * must be at least 2. + * + * @param buf Buffer to store items into + */ +static inline void rb_init(ring_buffer *rb, uint16 size, uint8 *buf) { + rb->head = 0; + rb->tail = 0; + rb->size = size - 1; + rb->buf = buf; +} + +/** + * @brief Return the number of elements stored in the ring buffer. + * @param rb Buffer whose elements to count. + */ +static inline uint16 rb_full_count(ring_buffer *rb) { + __io ring_buffer *arb = rb; + int32 size = arb->tail - arb->head; + if (arb->tail < arb->head) { + size += arb->size + 1; + } + return (uint16)size; +} + +/** + * @brief Returns true if and only if the ring buffer is full. + * @param rb Buffer to test. + */ +static inline int rb_is_full(ring_buffer *rb) { + return (rb->tail + 1 == rb->head) || + (rb->tail == rb->size && rb->head == 0); +} + +/** + * @brief Returns true if and only if the ring buffer is empty. + * @param rb Buffer to test. + */ +static inline int rb_is_empty(ring_buffer *rb) { + return rb->head == rb->tail; +} + +/** + * Append element onto the end of a ring buffer. + * @param rb Buffer to append onto. + * @param element Value to append. + */ +static inline void rb_insert(ring_buffer *rb, uint8 element) { + rb->buf[rb->tail] = element; + rb->tail = (rb->tail == rb->size) ? 0 : rb->tail + 1; +} + +/** + * @brief Remove and return the first item from a ring buffer. + * @param rb Buffer to remove from, must contain at least one element. + */ +static inline uint8 rb_remove(ring_buffer *rb) { + uint8 ch = rb->buf[rb->head]; + rb->head = (rb->head == rb->size) ? 0 : rb->head + 1; + return ch; +} + +/** + * @brief Attempt to remove the first item from a ring buffer. + * + * If the ring buffer is nonempty, removes and returns its first item. + * If it is empty, does nothing and returns a negative value. + * + * @param rb Buffer to attempt to remove from. + */ +static inline int16 rb_safe_remove(ring_buffer *rb) { + return rb_is_empty(rb) ? -1 : rb_remove(rb); +} + +/** + * @brief Attempt to insert an element into a ring buffer. + * + * @param rb Buffer to insert into. + * @param element Value to insert into rb. + * @sideeffect If rb is not full, appends element onto buffer. + * @return If element was appended, then true; otherwise, false. */ +static inline int rb_safe_insert(ring_buffer *rb, uint8 element) { + if (rb_is_full(rb)) { + return 0; + } + rb_insert(rb, element); + return 1; +} + +/** + * @brief Append an item onto the end of a non-full ring buffer. + * + * If the buffer is full, removes its first item, then inserts the new + * element at the end. + * + * @param rb Ring buffer to insert into. + * @param element Value to insert into ring buffer. + * @return On success, returns -1. If an element was popped, returns + * the popped value. + */ +static inline int rb_push_insert(ring_buffer *rb, uint8 element) { + int ret = -1; + if (rb_is_full(rb)) { + ret = rb_remove(rb); + } + rb_insert(rb, element); + return ret; +} + +/** + * @brief Discard all items from a ring buffer. + * @param rb Ring buffer to discard all items from. + */ +static inline void rb_reset(ring_buffer *rb) { + rb->tail = rb->head; +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/scb.h b/libmaple/include/libmaple/scb.h new file mode 100644 index 0000000..9c4ee15 --- /dev/null +++ b/libmaple/include/libmaple/scb.h @@ -0,0 +1,209 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file scb.h + * @brief System control block header + */ + +#ifndef _LIBMAPLE_SCB_H_ +#define _LIBMAPLE_SCB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * Register map and base pointer + */ + +/** System control block register map type */ +typedef struct scb_reg_map { + __io uint32 CPUID; /**< CPU ID Base Register */ + __io uint32 ICSR; /**< Interrupt Control State Register */ + __io uint32 VTOR; /**< Vector Table Offset Register */ + __io uint32 AIRCR; /**< Application Interrupt / Reset Control Register */ + __io uint32 SCR; /**< System Control Register */ + __io uint32 CCR; /**< Configuration and Control Register */ + __io uint8 SHP[12]; /**< System Handler Priority Registers + (4-7, 8-11, 12-15) */ + __io uint32 SHCSR; /**< System Handler Control and State Register */ + __io uint32 CFSR; /**< Configurable Fault Status Register */ + __io uint32 HFSR; /**< Hard Fault Status Register */ + /* DFSR is not documented by ST in PM0056 (as of Revision 4), but + * there's a 4 byte hole in the SCB register map docs right where + * it belongs. Since it's specified as "always implemented" in + * the ARM v7-M ARM, I'm assuming its absence is a bug in the ST + * doc, but I haven't proven it. [mbolivar] */ + __io uint32 DFSR; /**< Debug Fault Status Register */ + __io uint32 MMFAR; /**< Mem Manage Address Register */ + __io uint32 BFAR; /**< Bus Fault Address Register */ +#if 0 + /* The following registers are implementation-defined according to + * ARM v7-M, and I can't find evidence of their existence in ST's + * docs. I'm removing them. Feel free to yell at me if they do + * exist. [mbolivar] + */ + __io uint32 AFSR; /**< Auxiliary Fault Status Register */ + __io uint32 PFR[2]; /**< Processor Feature Register */ + __io uint32 DFR; /**< Debug Feature Register */ + __io uint32 AFR; /**< Auxiliary Feature Register */ + __io uint32 MMFR[4]; /**< Memory Model Feature Register */ + __io uint32 ISAR[5]; /**< ISA Feature Register */ +#endif +} scb_reg_map; + +/** System control block register map base pointer */ +#define SCB_BASE ((struct scb_reg_map*)0xE000ED00) + +/* + * Register bit definitions + */ + +/* No SCB_REG_FIELD_BIT macros as the relevant addresses are not in a + * bit-band region. */ + +/* CPUID base register (SCB_CPUID) */ + +#define SCB_CPUID_IMPLEMENTER (0xFF << 24) +#define SCB_CPUID_VARIANT (0xF << 20) +#define SCB_CPUID_CONSTANT (0xF << 16) +#define SCB_CPUID_PARTNO (0xFFF << 4) +#define SCB_CPUID_REVISION 0xF + +/* Interrupt control state register (SCB_ICSR) */ + +#define SCB_ICSR_NMIPENDSET BIT(31) +#define SCB_ICSR_PENDSVSET BIT(28) +#define SCB_ICSR_PENDSVCLR BIT(27) +#define SCB_ICSR_PENDSTSET BIT(26) +#define SCB_ICSR_PENDSTCLR BIT(25) +#define SCB_ICSR_ISRPENDING BIT(22) +#define SCB_ICSR_VECTPENDING (0x3FF << 12) +#define SCB_ICSR_RETOBASE BIT(11) +#define SCB_ICSR_VECTACTIVE 0xFF + +/* Vector table offset register (SCB_VTOR) */ + +#define SCB_VTOR_TBLOFF (0x1FFFFF << 9) + +/* Application interrupt and reset control register (SCB_AIRCR) */ + +#define SCB_AIRCR_VECTKEYSTAT (0x5FA << 16) +#define SCB_AIRCR_VECTKEY (0x5FA << 16) +#define SCB_AIRCR_ENDIANNESS BIT(15) +#define SCB_AIRCR_PRIGROUP (0x3 << 8) +#define SCB_AIRCR_SYSRESETREQ BIT(2) +#define SCB_AIRCR_VECTCLRACTIVE BIT(1) +#define SCB_AIRCR_VECTRESET BIT(0) + +/* System control register (SCB_SCR) */ + +#define SCB_SCR_SEVONPEND BIT(4) +#define SCB_SCR_SLEEPDEEP BIT(2) +#define SCB_SCR_SLEEPONEXIT BIT(1) + +/* Configuration and Control Register (SCB_CCR) */ + +#define SCB_CCR_STKALIGN BIT(9) +#define SCB_CCR_BFHFNMIGN BIT(8) +#define SCB_CCR_DIV_0_TRP BIT(4) +#define SCB_CCR_UNALIGN_TRP BIT(3) +#define SCB_CCR_USERSETMPEND BIT(1) +#define SCB_CCR_NONBASETHRDENA BIT(0) + +/* System handler priority registers (SCB_SHPRx) */ + +#define SCB_SHPR1_PRI6 (0xFF << 16) +#define SCB_SHPR1_PRI5 (0xFF << 8) +#define SCB_SHPR1_PRI4 0xFF + +#define SCB_SHPR2_PRI11 (0xFF << 24) + +#define SCB_SHPR3_PRI15 (0xFF << 24) +#define SCB_SHPR3_PRI14 (0xFF << 16) + +/* System Handler Control and state register (SCB_SHCSR) */ + +#define SCB_SHCSR_USGFAULTENA BIT(18) +#define SCB_SHCSR_BUSFAULTENA BIT(17) +#define SCB_SHCSR_MEMFAULTENA BIT(16) +#define SCB_SHCSR_SVCALLPENDED BIT(15) +#define SCB_SHCSR_BUSFAULTPENDED BIT(14) +#define SCB_SHCSR_MEMFAULTPENDED BIT(13) +#define SCB_SHCSR_USGFAULTPENDED BIT(12) +#define SCB_SHCSR_SYSTICKACT BIT(11) +#define SCB_SHCSR_PENDSVACT BIT(10) +#define SCB_SHCSR_MONITORACT BIT(8) +#define SCB_SHCSR_SVCALLACT BIT(7) +#define SCB_SHCSR_USGFAULTACT BIT(3) +#define SCB_SHCSR_BUSFAULTACT BIT(1) +#define SCB_SHCSR_MEMFAULTACT BIT(0) + +/* Configurable fault status register (SCB_CFSR) */ + +#define SCB_CFSR_DIVBYZERO BIT(25) +#define SCB_CFSR_UNALIGNED BIT(24) +#define SCB_CFSR_NOCP BIT(19) +#define SCB_CFSR_INVPC BIT(18) +#define SCB_CFSR_INVSTATE BIT(17) +#define SCB_CFSR_UNDEFINSTR BIT(16) +#define SCB_CFSR_BFARVALID BIT(15) +#define SCB_CFSR_STKERR BIT(12) +#define SCB_CFSR_UNSTKERR BIT(11) +#define SCB_CFSR_IMPRECISERR BIT(10) +#define SCB_CFSR_PRECISERR BIT(9) +#define SCB_CFSR_IBUSERR BIT(8) +#define SCB_CFSR_MMARVALID BIT(7) +#define SCB_CFSR_MSTKERR BIT(4) +#define SCB_CFSR_MUNSTKERR BIT(3) +#define SCB_CFSR_DACCVIOL BIT(1) +#define SCB_CFSR_IACCVIOL BIT(0) + +/* Hard Fault Status Register (SCB_HFSR) */ + +#define SCB_HFSR_DEBUG_VT BIT(31) +#define SCB_CFSR_FORCED BIT(30) +#define SCB_CFSR_VECTTBL BIT(1) + +/* Debug Fault Status Register */ + +/* Not specified by PM0056, but required by ARM. The bit definitions + * here are based on the names given in the ARM v7-M ARM. */ + +#define SCB_DFSR_EXTERNAL BIT(4) +#define SCB_DFSR_VCATCH BIT(3) +#define SCB_DFSR_DWTTRAP BIT(2) +#define SCB_DFSR_BKPT BIT(1) +#define SCB_DFSR_HALTED BIT(0) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h new file mode 100644 index 0000000..6f509c2 --- /dev/null +++ b/libmaple/include/libmaple/spi.h @@ -0,0 +1,456 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file spi.h + * @author Marti Bolivar + * @brief Serial Peripheral Interface (SPI) and Integrated + * Interchip Sound (I2S) peripheral support. + * + * I2S support is currently limited to register maps and bit definitions. + */ + +#ifndef _LIBMAPLE_SPI_H_ +#define _LIBMAPLE_SPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +/* + * Register maps + */ + +/** SPI register map type. */ +typedef struct spi_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SR; /**< Status register */ + __io uint32 DR; /**< Data register */ + __io uint32 CRCPR; /**< CRC polynomial register */ + __io uint32 RXCRCR; /**< RX CRC register */ + __io uint32 TXCRCR; /**< TX CRC register */ + __io uint32 I2SCFGR; /**< I2S configuration register */ + __io uint32 I2SPR; /**< I2S prescaler register */ +} spi_reg_map; + +/** SPI1 register map base pointer */ +#define SPI1_BASE ((struct spi_reg_map*)0x40013000) +/** SPI2 register map base pointer */ +#define SPI2_BASE ((struct spi_reg_map*)0x40003800) +/** SPI3 register map base pointer */ +#define SPI3_BASE ((struct spi_reg_map*)0x40003C00) + +/* + * Register bit definitions + */ + +/* Control register 1 */ + +#define SPI_CR1_BIDIMODE_BIT 15 +#define SPI_CR1_BIDIOE_BIT 14 +#define SPI_CR1_CRCEN_BIT 13 +#define SPI_CR1_CRCNEXT_BIT 12 +#define SPI_CR1_DFF_BIT 11 +#define SPI_CR1_RXONLY_BIT 10 +#define SPI_CR1_SSM_BIT 9 +#define SPI_CR1_SSI_BIT 8 +#define SPI_CR1_LSBFIRST_BIT 7 +#define SPI_CR1_SPE_BIT 6 +#define SPI_CR1_MSTR_BIT 2 +#define SPI_CR1_CPOL_BIT 1 +#define SPI_CR1_CPHA_BIT 0 + +#define SPI_CR1_BIDIMODE BIT(SPI_CR1_BIDIMODE_BIT) +#define SPI_CR1_BIDIMODE_2_LINE (0x0 << SPI_CR1_BIDIMODE_BIT) +#define SPI_CR1_BIDIMODE_1_LINE (0x1 << SPI_CR1_BIDIMODE_BIT) +#define SPI_CR1_BIDIOE BIT(SPI_CR1_BIDIOE_BIT) +#define SPI_CR1_CRCEN BIT(SPI_CR1_CRCEN_BIT) +#define SPI_CR1_CRCNEXT BIT(SPI_CR1_CRCNEXT_BIT) +#define SPI_CR1_DFF BIT(SPI_CR1_DFF_BIT) +#define SPI_CR1_DFF_8_BIT (0x0 << SPI_CR1_DFF_BIT) +#define SPI_CR1_DFF_16_BIT (0x1 << SPI_CR1_DFF_BIT) +#define SPI_CR1_RXONLY BIT(SPI_CR1_RXONLY_BIT) +#define SPI_CR1_SSM BIT(SPI_CR1_SSM_BIT) +#define SPI_CR1_SSI BIT(SPI_CR1_SSI_BIT) +#define SPI_CR1_LSBFIRST BIT(SPI_CR1_LSBFIRST_BIT) +#define SPI_CR1_SPE BIT(SPI_CR1_SPE_BIT) +#define SPI_CR1_BR (0x7 << 3) +#define SPI_CR1_BR_PCLK_DIV_2 (0x0 << 3) +#define SPI_CR1_BR_PCLK_DIV_4 (0x1 << 3) +#define SPI_CR1_BR_PCLK_DIV_8 (0x2 << 3) +#define SPI_CR1_BR_PCLK_DIV_16 (0x3 << 3) +#define SPI_CR1_BR_PCLK_DIV_32 (0x4 << 3) +#define SPI_CR1_BR_PCLK_DIV_64 (0x5 << 3) +#define SPI_CR1_BR_PCLK_DIV_128 (0x6 << 3) +#define SPI_CR1_BR_PCLK_DIV_256 (0x7 << 3) +#define SPI_CR1_MSTR BIT(SPI_CR1_MSTR_BIT) +#define SPI_CR1_CPOL BIT(SPI_CR1_CPOL_BIT) +#define SPI_CR1_CPOL_LOW (0x0 << SPI_CR1_CPOL_BIT) +#define SPI_CR1_CPOL_HIGH (0x1 << SPI_CR1_CPOL_BIT) +#define SPI_CR1_CPHA BIT(SPI_CR1_CPHA_BIT) + +/* Control register 2 */ + +/* RM0008-ism: SPI CR2 has "TXDMAEN" and "RXDMAEN" bits, while the + * USARTs have CR3 "DMAR" and "DMAT" bits. */ + +#define SPI_CR2_TXEIE_BIT 7 +#define SPI_CR2_RXNEIE_BIT 6 +#define SPI_CR2_ERRIE_BIT 5 +#define SPI_CR2_SSOE_BIT 2 +#define SPI_CR2_TXDMAEN_BIT 1 +#define SPI_CR2_RXDMAEN_BIT 0 + +#define SPI_CR2_TXEIE BIT(SPI_CR2_TXEIE_BIT) +#define SPI_CR2_RXNEIE BIT(SPI_CR2_RXNEIE_BIT) +#define SPI_CR2_ERRIE BIT(SPI_CR2_ERRIE_BIT) +#define SPI_CR2_SSOE BIT(SPI_CR2_SSOE_BIT) +#define SPI_CR2_TXDMAEN BIT(SPI_CR2_TXDMAEN_BIT) +#define SPI_CR2_RXDMAEN BIT(SPI_CR2_RXDMAEN_BIT) + +/* Status register */ + +#define SPI_SR_BSY_BIT 7 +#define SPI_SR_OVR_BIT 6 +#define SPI_SR_MODF_BIT 5 +#define SPI_SR_CRCERR_BIT 4 +#define SPI_SR_UDR_BIT 3 +#define SPI_SR_CHSIDE_BIT 2 +#define SPI_SR_TXE_BIT 1 +#define SPI_SR_RXNE_BIT 0 + +#define SPI_SR_BSY BIT(SPI_SR_BSY_BIT) +#define SPI_SR_OVR BIT(SPI_SR_OVR_BIT) +#define SPI_SR_MODF BIT(SPI_SR_MODF_BIT) +#define SPI_SR_CRCERR BIT(SPI_SR_CRCERR_BIT) +#define SPI_SR_UDR BIT(SPI_SR_UDR_BIT) +#define SPI_SR_CHSIDE BIT(SPI_SR_CHSIDE_BIT) +#define SPI_SR_CHSIDE_LEFT (0x0 << SPI_SR_CHSIDE_BIT) +#define SPI_SR_CHSIDE_RIGHT (0x1 << SPI_SR_CHSIDE_BIT) +#define SPI_SR_TXE BIT(SPI_SR_TXE_BIT) +#define SPI_SR_RXNE BIT(SPI_SR_RXNE_BIT) + +/* I2S configuration register */ + +/* RM0008-ism: CR1 has "CPOL", I2SCFGR has "CKPOL". */ + +#define SPI_I2SCFGR_I2SMOD_BIT 11 +#define SPI_I2SCFGR_I2SE_BIT 10 +#define SPI_I2SCFGR_PCMSYNC_BIT 7 +#define SPI_I2SCFGR_CKPOL_BIT 3 +#define SPI_I2SCFGR_CHLEN_BIT 0 + +#define SPI_I2SCFGR_I2SMOD BIT(SPI_I2SCFGR_I2SMOD_BIT) +#define SPI_I2SCFGR_I2SMOD_SPI (0x0 << SPI_I2SCFGR_I2SMOD_BIT) +#define SPI_I2SCFGR_I2SMOD_I2S (0x1 << SPI_I2SCFGR_I2SMOD_BIT) +#define SPI_I2SCFGR_I2SE BIT(SPI_I2SCFGR_I2SE_BIT) +#define SPI_I2SCFGR_I2SCFG (0x3 << 8) +#define SPI_I2SCFGR_I2SCFG_SLAVE_TX (0x0 << 8) +#define SPI_I2SCFGR_I2SCFG_SLAVE_RX (0x1 << 8) +#define SPI_I2SCFGR_I2SCFG_MASTER_TX (0x2 << 8) +#define SPI_I2SCFGR_I2SCFG_MASTER_RX (0x3 << 8) +#define SPI_I2SCFGR_PCMSYNC BIT(SPI_I2SCFGR_PCMSYNC_BIT) +#define SPI_I2SCFGR_PCMSYNC_SHORT (0x0 << SPI_I2SCFGR_PCMSYNC_BIT) +#define SPI_I2SCFGR_PCMSYNC_LONG (0x1 << SPI_I2SCFGR_PCMSYNC_BIT) +#define SPI_I2SCFGR_I2SSTD (0x3 << 4) +#define SPI_I2SCFGR_I2SSTD_PHILLIPS (0x0 << 4) +#define SPI_I2SCFGR_I2SSTD_MSB (0x1 << 4) +#define SPI_I2SCFGR_I2SSTD_LSB (0x2 << 4) +#define SPI_I2SCFGR_I2SSTD_PCM (0x3 << 4) +#define SPI_I2SCFGR_CKPOL BIT(SPI_I2SCFGR_CKPOL_BIT) +#define SPI_I2SCFGR_CKPOL_LOW (0x0 << SPI_I2SCFGR_CKPOL_BIT) +#define SPI_I2SCFGR_CKPOL_HIGH (0x1 << SPI_I2SCFGR_CKPOL_BIT) +#define SPI_I2SCFGR_DATLEN (0x3 << 1) +#define SPI_I2SCFGR_DATLEN_16_BIT (0x0 << 1) +#define SPI_I2SCFGR_DATLEN_24_BIT (0x1 << 1) +#define SPI_I2SCFGR_DATLEN_32_BIT (0x2 << 1) +#define SPI_I2SCFGR_CHLEN BIT(SPI_I2SCFGR_CHLEN_BIT) +#define SPI_I2SCFGR_CHLEN_16_BIT (0x0 << SPI_I2SCFGR_CHLEN_BIT) +#define SPI_I2SCFGR_CHLEN_32_BIT (0x1 << SPI_I2SCFGR_CHLEN_BIT) + +/* + * Devices + */ + +/** SPI device type */ +typedef struct spi_dev { + spi_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ + nvic_irq_num irq_num; /**< NVIC interrupt number */ +} spi_dev; + +extern spi_dev *SPI1; +extern spi_dev *SPI2; +#ifdef STM32_HIGH_DENSITY +extern spi_dev *SPI3; +#endif + +/* + * SPI Convenience functions + */ + +void spi_init(spi_dev *dev); + +void spi_gpio_cfg(uint8 as_master, + gpio_dev *nss_dev, + uint8 nss_bit, + gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit); + +/** + * @brief SPI mode configuration. + * + * Determines a combination of clock polarity (CPOL), which determines + * idle state of the clock line, and clock phase (CPHA), which + * determines which clock edge triggers data capture. + */ +typedef enum spi_mode { + SPI_MODE_0, /**< Clock line idles low (0), data capture on first + clock transition. */ + SPI_MODE_1, /**< Clock line idles low (0), data capture on second + clock transition */ + SPI_MODE_2, /**< Clock line idles high (1), data capture on first + clock transition. */ + SPI_MODE_3 /**< Clock line idles high (1), data capture on + second clock transition. */ +} spi_mode; + +/** + * @brief SPI baud rate configuration, as a divisor of f_PCLK, the + * PCLK clock frequency. + */ +typedef enum spi_baud_rate { + SPI_BAUD_PCLK_DIV_2 = SPI_CR1_BR_PCLK_DIV_2, /**< f_PCLK/2 */ + SPI_BAUD_PCLK_DIV_4 = SPI_CR1_BR_PCLK_DIV_4, /**< f_PCLK/4 */ + SPI_BAUD_PCLK_DIV_8 = SPI_CR1_BR_PCLK_DIV_8, /**< f_PCLK/8 */ + SPI_BAUD_PCLK_DIV_16 = SPI_CR1_BR_PCLK_DIV_16, /**< f_PCLK/16 */ + SPI_BAUD_PCLK_DIV_32 = SPI_CR1_BR_PCLK_DIV_32, /**< f_PCLK/32 */ + SPI_BAUD_PCLK_DIV_64 = SPI_CR1_BR_PCLK_DIV_64, /**< f_PCLK/64 */ + SPI_BAUD_PCLK_DIV_128 = SPI_CR1_BR_PCLK_DIV_128, /**< f_PCLK/128 */ + SPI_BAUD_PCLK_DIV_256 = SPI_CR1_BR_PCLK_DIV_256, /**< f_PCLK/256 */ +} spi_baud_rate; + +/** + * @brief SPI initialization flags. + * @see spi_master_enable() + * @see spi_slave_enable() + */ +typedef enum spi_cfg_flag { + SPI_BIDIMODE = SPI_CR1_BIDIMODE, /**< Bidirectional mode enable */ + SPI_BIDIOE = SPI_CR1_BIDIOE, /**< Output enable in bidirectional + mode */ + SPI_CRCEN = SPI_CR1_CRCEN, /**< Cyclic redundancy check (CRC) + enable */ + SPI_DFF_8_BIT = SPI_CR1_DFF_8_BIT, /**< 8-bit data frame format (this is + the default) */ + SPI_DFF_16_BIT = SPI_CR1_DFF_16_BIT, /**< 16-bit data frame format */ + SPI_RX_ONLY = SPI_CR1_RXONLY, /**< Receive only */ + SPI_SW_SLAVE = SPI_CR1_SSM, /**< Software slave management */ + SPI_SOFT_SS = SPI_CR1_SSI, /**< Software (internal) slave + select. This flag only has an + effect when used in combination + with SPI_SW_SLAVE. */ + SPI_FRAME_LSB = SPI_CR1_LSBFIRST, /**< LSB-first (little-endian) frame + format */ + SPI_FRAME_MSB = 0, /**< MSB-first (big-endian) frame + format (this is the default) */ +} spi_cfg_flag; + +void spi_master_enable(spi_dev *dev, + spi_baud_rate baud, + spi_mode mode, + uint32 flags); + +void spi_slave_enable(spi_dev *dev, + spi_mode mode, + uint32 flags); + +uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len); + +void spi_foreach(void (*fn)(spi_dev (*dev))); + +void spi_peripheral_enable(spi_dev *dev); +void spi_peripheral_disable(spi_dev *dev); + +void spi_tx_dma_enable(spi_dev *dev); +void spi_tx_dma_disable(spi_dev *dev); + +void spi_rx_dma_enable(spi_dev *dev); +void spi_rx_dma_disable(spi_dev *dev); + +/** + * @brief Determine if a SPI peripheral is enabled. + * @param dev SPI device + * @return True, if and only if dev's peripheral is enabled. + */ +static inline uint8 spi_is_enabled(spi_dev *dev) { + return dev->regs->CR1 & SPI_CR1_SPE_BIT; +} + +/** + * @brief Disable all SPI peripherals + */ +static inline void spi_peripheral_disable_all(void) { + spi_foreach(spi_peripheral_disable); +} + +/** Available SPI interrupts */ +typedef enum spi_interrupt { + SPI_TXE_INTERRUPT = SPI_CR2_TXEIE, /**< TX buffer empty interrupt */ + SPI_RXNE_INTERRUPT = SPI_CR2_RXNEIE, /**< RX buffer not empty interrupt */ + SPI_ERR_INTERRUPT = SPI_CR2_ERRIE /**< + * Error interrupt (CRC, overrun, + * and mode fault errors for SPI; + * underrun, overrun errors for I2S) + */ +} spi_interrupt; + +/** + * @brief Mask for all spi_interrupt values + * @see spi_interrupt + */ +#define SPI_INTERRUPTS_ALL (SPI_TXE_INTERRUPT | \ + SPI_RXNE_INTERRUPT | \ + SPI_ERR_INTERRUPT) + +/** + * @brief Enable SPI interrupt requests + * @param dev SPI device + * @param interrupt_flags Bitwise OR of spi_interrupt values to enable + * @see spi_interrupt + */ +static inline void spi_irq_enable(spi_dev *dev, uint32 interrupt_flags) { + dev->regs->CR2 |= interrupt_flags; + nvic_irq_enable(dev->irq_num); +} + +/** + * @brief Disable SPI interrupt requests + * @param dev SPI device + * @param interrupt_flags Bitwise OR of spi_interrupt values to disable + * @see spi_interrupt + */ +static inline void spi_irq_disable(spi_dev *dev, uint32 interrupt_flags) { + dev->regs->CR2 &= ~interrupt_flags; +} + +/** + * @brief Get the data frame format flags with which a SPI port is + * configured. + * @param dev SPI device whose data frame format to get. + * @return SPI_DFF_8_BIT, if dev has an 8-bit data frame format. + * Otherwise, SPI_DFF_16_BIT. + */ +static inline spi_cfg_flag spi_dff(spi_dev *dev) { + return ((dev->regs->CR1 & SPI_CR1_DFF) == SPI_CR1_DFF_8_BIT ? + SPI_DFF_8_BIT : + SPI_DFF_16_BIT); +} + +/** + * @brief Determine whether the device's peripheral receive (RX) + * register is empty. + * @param dev SPI device + * @return true, iff dev's RX register is empty. + */ +static inline uint8 spi_is_rx_nonempty(spi_dev *dev) { + return dev->regs->SR & SPI_SR_RXNE; +} + +/** + * @brief Retrieve the contents of the device's peripheral receive + * (RX) register. + * + * You may only call this function when the RX register is nonempty. + * Calling this function clears the contents of the RX register. + * + * @param dev SPI device + * @return Contents of dev's peripheral RX register + * @see spi_is_rx_reg_nonempty() + */ +static inline uint16 spi_rx_reg(spi_dev *dev) { + return (uint16)dev->regs->DR; +} + +/** + * @brief Determine whether the device's peripheral transmit (TX) + * register is empty. + * @param dev SPI device + * @return true, iff dev's TX register is empty. + */ +static inline uint8 spi_is_tx_empty(spi_dev *dev) { + return dev->regs->SR & SPI_SR_TXE; +} + +/** + * @brief Load a value into the device's peripheral transmit (TX) register. + * + * You may only call this function when the TX register is empty. + * Calling this function loads val into the peripheral's TX register. + * If the device is properly configured, this will initiate a + * transmission, the completion of which will cause the TX register to + * be empty again. + * + * @param dev SPI device + * @param val Value to load into the TX register. If the SPI data + * frame format is 8 bit, the value must be right-aligned. + * @see spi_is_tx_reg_empty() + * @see spi_init() + * @see spi_master_enable() + * @see spi_slave_enable() + */ +static inline void spi_tx_reg(spi_dev *dev, uint16 val) { + dev->regs->DR = val; +} + +/** + * @brief Determine whether the device's peripheral busy (SPI_SR_BSY) + * flag is set. + * @param dev SPI device + * @return true, iff dev's BSY flag is set. + */ +static inline uint8 spi_is_busy(spi_dev *dev) { + return dev->regs->SR & SPI_SR_BSY; +} + +/* + * I2S convenience functions (TODO) + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h new file mode 100644 index 0000000..53a5d7a --- /dev/null +++ b/libmaple/include/libmaple/stm32.h @@ -0,0 +1,199 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32.h + * @brief STM32 chip-specific definitions + */ + +#ifndef _LIBMAPLE_STM32_H_ +#define _LIBMAPLE_STM32_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * User-specific configuration. + * + * The #defines here depend upon how libmaple is used. Because of the + * potential for a mismatch between them and the actual libmaple + * usage, you should try to keep their number to an absolute minimum. + */ + +#ifdef __DOXYGEN_PREDEFINED_HACK + + /** @brief APB1 clock speed, in Hz. */ + #define STM32_PCLK1 + /** @brief APB2 clock speed, in Hz. */ + #define STM32_PCLK2 + + /** Deprecated. Use STM32_PCLK1 instead. */ + #define PCLK1 + /** Deprecated. Use STM32_PCLK2 instead. */ + #define PCLK2 + +#endif + +#ifndef STM32_PCLK1 +#define STM32_PCLK1 36000000U +#endif +#ifndef PCLK1 +#define PCLK1 STM32_PCLK1 +#endif +#if PCLK1 != STM32_PCLK1 +#error "(Deprecated) PCLK1 differs from STM32_PCLK1" +#endif + +#ifndef STM32_PCLK2 +#define STM32_PCLK2 72000000U +#endif +#ifndef PCLK2 +#define PCLK2 STM32_PCLK2 +#endif +#if PCLK2 != STM32_PCLK2 +#error "(Deprecated) PCLK2 differs from STM32_PCLK2" +#endif + +/* + * Density-specific configuration. + */ + +#ifdef __DOXYGEN_PREDEFINED_HACK + + /** + * @brief Number of interrupts in the NVIC. + * + * This define is automatically generated whenever the proper + * density is defined (currently, this is restricted to defining + * one of STM32_MEDIUM_DENSITY and STM32_HIGH_DENSITY). + */ + #define STM32_NR_INTERRUPTS + + /** Deprecated. Use STM32_NR_INTERRUPTS instead. */ + #define NR_INTERRUPTS + +#endif + +#ifdef STM32_MEDIUM_DENSITY + #define STM32_NR_INTERRUPTS 43 +#elif defined(STM32_HIGH_DENSITY) + #define STM32_NR_INTERRUPTS 60 +#else +#error "No STM32 board type defined!" +#endif + +#define NR_INTERRUPTS STM32_NR_INTERRUPTS + +/* + * MCU-specific configuration. + */ + +#ifdef __DOXYGEN_PREDEFINED_HACK + + /** + * Number of GPIO ports. + */ + #define STM32_NR_GPIO_PORTS + + /** + * @brief Multiplier to convert microseconds into loop iterations + * in delay_us(). + * + * @see delay_us() + */ + #define STM32_DELAY_US_MULT + + /** + * @brief Pointer to end of built-in SRAM. + * + * Points to the address which is 1 byte past the last valid + * SRAM address. + */ + #define STM32_SRAM_END + + /** Deprecated. Use STM32_NR_GPIO_PORTS instead. */ + #define NR_GPIO_PORTS + /** Deprecated. Use STM32_DELAY_US_MULT instead. */ + #define DELAY_US_MULT + +#endif + +#if defined(MCU_STM32F103RB) + /* e.g., LeafLabs Maple */ + + #define STM32_NR_GPIO_PORTS 4 + #define STM32_DELAY_US_MULT 12 + #define STM32_SRAM_END ((void*)0x20005000) + + #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS + #define DELAY_US_MULT STM32_DELAY_US_MULT + +#elif defined(MCU_STM32F103ZE) + /* e.g., LeafLabs Maple Native */ + + #define STM32_NR_GPIO_PORTS 7 + #define STM32_DELAY_US_MULT 12 + #define STM32_SRAM_END ((void*)0x20010000) + + #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS + #define DELAY_US_MULT STM32_DELAY_US_MULT + +#elif defined(MCU_STM32F103CB) + /* e.g., LeafLabs Maple Mini */ + + /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true. + * But only pins 0 and 1 exist, and they're used for OSC on the + * Mini, so we'll live with this for now. */ + #define STM32_NR_GPIO_PORTS 3 + #define STM32_DELAY_US_MULT 12 + #define STM32_SRAM_END ((void*)0x20005000) + + #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS + #define DELAY_US_MULT STM32_DELAY_US_MULT + +#elif defined(MCU_STM32F103RE) + /* e.g., LeafLabs Maple RET6 edition */ + + #define STM32_NR_GPIO_PORTS 4 + #define STM32_DELAY_US_MULT 12 + #define STM32_SRAM_END ((void*)0x20010000) + + #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS + #define DELAY_US_MULT STM32_DELAY_US_MULT + +#else + +#error "No MCU type specified. Add something like -DMCU_STM32F103RB " \ + "to your compiler arguments (probably in a Makefile)." + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/systick.h b/libmaple/include/libmaple/systick.h new file mode 100644 index 0000000..1731c85 --- /dev/null +++ b/libmaple/include/libmaple/systick.h @@ -0,0 +1,116 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file systick.h + * + * @brief System timer definitions + */ + +#ifndef _LIBMAPLE_SYSTICK_H_ +#define _LIBMAPLE_SYSTICK_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/** SysTick register map type */ +typedef struct systick_reg_map { + __io uint32 CSR; /**< Control and status register */ + __io uint32 RVR; /**< Reload value register */ + __io uint32 CNT; /**< Current value register ("count") */ + __io uint32 CVR; /**< Calibration value register */ +} systick_reg_map; + +/** SysTick register map base pointer */ +#define SYSTICK_BASE ((struct systick_reg_map*)0xE000E010) + +/* + * Register bit definitions. + */ + +/* Control and status register */ + +#define SYSTICK_CSR_COUNTFLAG BIT(16) +#define SYSTICK_CSR_CLKSOURCE BIT(2) +#define SYSTICK_CSR_CLKSOURCE_EXTERNAL 0 +#define SYSTICK_CSR_CLKSOURCE_CORE BIT(2) +#define SYSTICK_CSR_TICKINT BIT(1) +#define SYSTICK_CSR_TICKINT_PEND BIT(1) +#define SYSTICK_CSR_TICKINT_NO_PEND 0 +#define SYSTICK_CSR_ENABLE BIT(0) +#define SYSTICK_CSR_ENABLE_MULTISHOT BIT(0) +#define SYSTICK_CSR_ENABLE_DISABLED 0 + +/* Calibration value register */ + +#define SYSTICK_CVR_NOREF BIT(31) +#define SYSTICK_CVR_SKEW BIT(30) +#define SYSTICK_CVR_TENMS 0xFFFFFF + +/** System elapsed time, in milliseconds */ +extern volatile uint32 systick_uptime_millis; + +/** + * @brief Returns the system uptime, in milliseconds. + */ +static inline uint32 systick_uptime(void) { + return systick_uptime_millis; +} + + +void systick_init(uint32 reload_val); +void systick_disable(); +void systick_enable(); + +/** + * @brief Returns the current value of the SysTick counter. + */ +static inline uint32 systick_get_count(void) { + return SYSTICK_BASE->CNT; +} + +/** + * @brief Check for underflow. + * + * This function returns 1 if the SysTick timer has counted to 0 since + * the last time it was called. However, any reads of any part of the + * SysTick Control and Status Register SYSTICK_BASE->CSR will + * interfere with this functionality. See the ARM Cortex M3 Technical + * Reference Manual for more details (e.g. Table 8-3 in revision r1p1). + */ +static inline uint32 systick_check_underflow(void) { + return SYSTICK_BASE->CSR & SYSTICK_CSR_COUNTFLAG; +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h new file mode 100644 index 0000000..9e4e20c --- /dev/null +++ b/libmaple/include/libmaple/timer.h @@ -0,0 +1,1010 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file timer.h + * @author Marti Bolivar + * @brief Timer interface. + */ + +#ifndef _LIBMAPLE_TIMERS_H_ +#define _LIBMAPLE_TIMERS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include + +/* + * Register maps and devices + */ + +/** Advanced control timer register map type */ +typedef struct timer_adv_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SMCR; /**< Slave mode control register */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + __io uint32 CCMR1; /**< Capture/compare mode register 1 */ + __io uint32 CCMR2; /**< Capture/compare mode register 2 */ + __io uint32 CCER; /**< Capture/compare enable register */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ + __io uint32 RCR; /**< Repetition counter register */ + __io uint32 CCR1; /**< Capture/compare register 1 */ + __io uint32 CCR2; /**< Capture/compare register 2 */ + __io uint32 CCR3; /**< Capture/compare register 3 */ + __io uint32 CCR4; /**< Capture/compare register 4 */ + __io uint32 BDTR; /**< Break and dead-time register */ + __io uint32 DCR; /**< DMA control register */ + __io uint32 DMAR; /**< DMA address for full transfer */ +} timer_adv_reg_map; + +/** General purpose timer register map type */ +typedef struct timer_gen_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SMCR; /**< Slave mode control register */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + __io uint32 CCMR1; /**< Capture/compare mode register 1 */ + __io uint32 CCMR2; /**< Capture/compare mode register 2 */ + __io uint32 CCER; /**< Capture/compare enable register */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 CCR1; /**< Capture/compare register 1 */ + __io uint32 CCR2; /**< Capture/compare register 2 */ + __io uint32 CCR3; /**< Capture/compare register 3 */ + __io uint32 CCR4; /**< Capture/compare register 4 */ + const uint32 RESERVED2; /**< Reserved */ + __io uint32 DCR; /**< DMA control register */ + __io uint32 DMAR; /**< DMA address for full transfer */ +} timer_gen_reg_map; + +/** Basic timer register map type */ +typedef struct timer_bas_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + const uint32 RESERVED2; /**< Reserved */ + const uint32 RESERVED3; /**< Reserved */ + const uint32 RESERVED4; /**< Reserved */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ +} timer_bas_reg_map; + +/** Timer 1 register map base pointer */ +#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) +/** Timer 2 register map base pointer */ +#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) +/** Timer 3 register map base pointer */ +#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) +/** Timer 4 register map base pointer */ +#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) +#ifdef STM32_HIGH_DENSITY +/** Timer 5 register map base pointer */ +#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) +/** Timer 6 register map base pointer */ +#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) +/** Timer 7 register map base pointer */ +#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) +/** Timer 8 register map base pointer */ +#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) +#endif + +/* + * Timer devices + */ + +/** + * @brief Timer register map type. + * + * Just holds a pointer to the correct type of register map, based on + * the timer's type. + */ +typedef union timer_reg_map { + timer_adv_reg_map *adv; /**< Advanced register map */ + timer_gen_reg_map *gen; /**< General purpose register map */ + timer_bas_reg_map *bas; /**< Basic register map */ +} timer_reg_map; + +/** + * @brief Timer type + * + * Type marker for timer_dev. + * + * @see timer_dev + */ +typedef enum timer_type { + TIMER_ADVANCED, /**< Advanced type */ + TIMER_GENERAL, /**< General purpose type */ + TIMER_BASIC /**< Basic type */ +} timer_type; + +/** Timer device type */ +typedef struct timer_dev { + timer_reg_map regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ + timer_type type; /**< Timer's type */ + voidFuncPtr handlers[]; /**< User IRQ handlers */ +} timer_dev; + +extern timer_dev *TIMER1; +extern timer_dev *TIMER2; +extern timer_dev *TIMER3; +extern timer_dev *TIMER4; +#ifdef STM32_HIGH_DENSITY +extern timer_dev *TIMER5; +extern timer_dev *TIMER6; +extern timer_dev *TIMER7; +extern timer_dev *TIMER8; +#endif + +/* + * Register bit definitions + */ + +/* Control register 1 (CR1) */ + +#define TIMER_CR1_ARPE_BIT 7 +#define TIMER_CR1_DIR_BIT 4 +#define TIMER_CR1_OPM_BIT 3 +#define TIMER_CR1_URS_BIT 2 +#define TIMER_CR1_UDIS_BIT 1 +#define TIMER_CR1_CEN_BIT 0 + +#define TIMER_CR1_CKD (0x3 << 8) +#define TIMER_CR1_CKD_1TCKINT (0x0 << 8) +#define TIMER_CR1_CKD_2TCKINT (0x1 << 8) +#define TIMER_CR1_CKD_4TICKINT (0x2 << 8) +#define TIMER_CR1_ARPE BIT(TIMER_CR1_ARPE_BIT) +#define TIMER_CR1_CKD_CMS (0x3 << 5) +#define TIMER_CR1_CKD_CMS_EDGE (0x0 << 5) +#define TIMER_CR1_CKD_CMS_CENTER1 (0x1 << 5) +#define TIMER_CR1_CKD_CMS_CENTER2 (0x2 << 5) +#define TIMER_CR1_CKD_CMS_CENTER3 (0x3 << 5) +#define TIMER_CR1_DIR BIT(TIMER_CR1_DIR_BIT) +#define TIMER_CR1_OPM BIT(TIMER_CR1_OPM_BIT) +#define TIMER_CR1_URS BIT(TIMER_CR1_URS_BIT) +#define TIMER_CR1_UDIS BIT(TIMER_CR1_UDIS_BIT) +#define TIMER_CR1_CEN BIT(TIMER_CR1_CEN_BIT) + +/* Control register 2 (CR2) */ + +#define TIMER_CR2_OIS4_BIT 14 +#define TIMER_CR2_OIS3N_BIT 13 +#define TIMER_CR2_OIS3_BIT 12 +#define TIMER_CR2_OIS2N_BIT 11 +#define TIMER_CR2_OIS2_BIT 10 +#define TIMER_CR2_OIS1N_BIT 9 +#define TIMER_CR2_OIS1_BIT 8 +#define TIMER_CR2_TI1S_BIT 7 /* tills? yikes */ +#define TIMER_CR2_CCDS_BIT 3 +#define TIMER_CR2_CCUS_BIT 2 +#define TIMER_CR2_CCPC_BIT 0 + +#define TIMER_CR2_OIS4 BIT(TIMER_CR2_OIS4_BIT) +#define TIMER_CR2_OIS3N BIT(TIMER_CR2_OIS3N_BIT) +#define TIMER_CR2_OIS3 BIT(TIMER_CR2_OIS3_BIT) +#define TIMER_CR2_OIS2N BIT(TIMER_CR2_OIS2N_BIT) +#define TIMER_CR2_OIS2 BIT(TIMER_CR2_OIS2_BIT) +#define TIMER_CR2_OIS1N BIT(TIMER_CR2_OIS1N_BIT) +#define TIMER_CR2_OIS1 BIT(TIMER_CR2_OIS1_BIT) +#define TIMER_CR2_TI1S BIT(TIMER_CR2_TI1S_BIT) +#define TIMER_CR2_MMS (0x7 << 4) +#define TIMER_CR2_MMS_RESET (0x0 << 4) +#define TIMER_CR2_MMS_ENABLE (0x1 << 4) +#define TIMER_CR2_MMS_UPDATE (0x2 << 4) +#define TIMER_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIMER_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIMER_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIMER_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIMER_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIMER_CR2_CCDS BIT(TIMER_CR2_CCDS_BIT) +#define TIMER_CR2_CCUS BIT(TIMER_CR2_CCUS_BIT) +#define TIMER_CR2_CCPC BIT(TIMER_CR2_CCPC_BIT) + +/* Slave mode control register (SMCR) */ + +#define TIMER_SMCR_ETP_BIT 15 +#define TIMER_SMCR_ECE_BIT 14 +#define TIMER_SMCR_MSM_BIT 7 + +#define TIMER_SMCR_ETP BIT(TIMER_SMCR_ETP_BIT) +#define TIMER_SMCR_ECE BIT(TIMER_SMCR_ECE_BIT) +#define TIMER_SMCR_ETPS (0x3 << 12) +#define TIMER_SMCR_ETPS_OFF (0x0 << 12) +#define TIMER_SMCR_ETPS_DIV2 (0x1 << 12) +#define TIMER_SMCR_ETPS_DIV4 (0x2 << 12) +#define TIMER_SMCR_ETPS_DIV8 (0x3 << 12) +#define TIMER_SMCR_ETF (0xF << 12) +#define TIMER_SMCR_MSM BIT(TIMER_SMCR_MSM_BIT) +#define TIMER_SMCR_TS (0x3 << 4) +#define TIMER_SMCR_TS_ITR0 (0x0 << 4) +#define TIMER_SMCR_TS_ITR1 (0x1 << 4) +#define TIMER_SMCR_TS_ITR2 (0x2 << 4) +#define TIMER_SMCR_TS_ITR3 (0x3 << 4) +#define TIMER_SMCR_TS_TI1F_ED (0x4 << 4) +#define TIMER_SMCR_TS_TI1FP1 (0x5 << 4) +#define TIMER_SMCR_TS_TI2FP2 (0x6 << 4) +#define TIMER_SMCR_TS_ETRF (0x7 << 4) +#define TIMER_SMCR_SMS 0x3 +#define TIMER_SMCR_SMS_DISABLED 0x0 +#define TIMER_SMCR_SMS_ENCODER1 0x1 +#define TIMER_SMCR_SMS_ENCODER2 0x2 +#define TIMER_SMCR_SMS_ENCODER3 0x3 +#define TIMER_SMCR_SMS_RESET 0x4 +#define TIMER_SMCR_SMS_GATED 0x5 +#define TIMER_SMCR_SMS_TRIGGER 0x6 +#define TIMER_SMCR_SMS_EXTERNAL 0x7 + +/* DMA/Interrupt enable register (DIER) */ + +#define TIMER_DIER_TDE_BIT 14 +#define TIMER_DIER_CC4DE_BIT 12 +#define TIMER_DIER_CC3DE_BIT 11 +#define TIMER_DIER_CC2DE_BIT 10 +#define TIMER_DIER_CC1DE_BIT 9 +#define TIMER_DIER_UDE_BIT 8 +#define TIMER_DIER_TIE_BIT 6 +#define TIMER_DIER_CC4IE_BIT 4 +#define TIMER_DIER_CC3IE_BIT 3 +#define TIMER_DIER_CC2IE_BIT 2 +#define TIMER_DIER_CC1IE_BIT 1 +#define TIMER_DIER_UIE_BIT 0 + +#define TIMER_DIER_TDE BIT(TIMER_DIER_TDE_BIT) +#define TIMER_DIER_CC4DE BIT(TIMER_DIER_CC4DE_BIT) +#define TIMER_DIER_CC3DE BIT(TIMER_DIER_CC3DE_BIT) +#define TIMER_DIER_CC2DE BIT(TIMER_DIER_CC2DE_BIT) +#define TIMER_DIER_CC1DE BIT(TIMER_DIER_CC1DE_BIT) +#define TIMER_DIER_UDE BIT(TIMER_DIER_UDE_BIT) +#define TIMER_DIER_TIE BIT(TIMER_DIER_TIE_BIT) +#define TIMER_DIER_CC4IE BIT(TIMER_DIER_CC4IE_BIT) +#define TIMER_DIER_CC3IE BIT(TIMER_DIER_CC3IE_BIT) +#define TIMER_DIER_CC2IE BIT(TIMER_DIER_CC2IE_BIT) +#define TIMER_DIER_CC1IE BIT(TIMER_DIER_CC1IE_BIT) +#define TIMER_DIER_UIE BIT(TIMER_DIER_UIE_BIT) + +/* Status register (SR) */ + +#define TIMER_SR_CC4OF_BIT 12 +#define TIMER_SR_CC3OF_BIT 11 +#define TIMER_SR_CC2OF_BIT 10 +#define TIMER_SR_CC1OF_BIT 9 +#define TIMER_SR_BIF_BIT 7 +#define TIMER_SR_TIF_BIT 6 +#define TIMER_SR_COMIF_BIT 5 +#define TIMER_SR_CC4IF_BIT 4 +#define TIMER_SR_CC3IF_BIT 3 +#define TIMER_SR_CC2IF_BIT 2 +#define TIMER_SR_CC1IF_BIT 1 +#define TIMER_SR_UIF_BIT 0 + +#define TIMER_SR_CC4OF BIT(TIMER_SR_CC4OF_BIT) +#define TIMER_SR_CC3OF BIT(TIMER_SR_CC3OF_BIT) +#define TIMER_SR_CC2OF BIT(TIMER_SR_CC2OF_BIT) +#define TIMER_SR_CC1OF BIT(TIMER_SR_CC1OF_BIT) +#define TIMER_SR_BIF BIT(TIMER_SR_BIF_BIT) +#define TIMER_SR_TIF BIT(TIMER_SR_TIF_BIT) +#define TIMER_SR_COMIF BIT(TIMER_SR_COMIF_BIT) +#define TIMER_SR_CC4IF BIT(TIMER_SR_CC4IF_BIT) +#define TIMER_SR_CC3IF BIT(TIMER_SR_CC3IF_BIT) +#define TIMER_SR_CC2IF BIT(TIMER_SR_CC2IF_BIT) +#define TIMER_SR_CC1IF BIT(TIMER_SR_CC1IF_BIT) +#define TIMER_SR_UIF BIT(TIMER_SR_UIF_BIT) + +/* Event generation register (EGR) */ + +#define TIMER_EGR_TG_BIT 6 +#define TIMER_EGR_CC4G_BIT 4 +#define TIMER_EGR_CC3G_BIT 3 +#define TIMER_EGR_CC2G_BIT 2 +#define TIMER_EGR_CC1G_BIT 1 +#define TIMER_EGR_UG_BIT 0 + +#define TIMER_EGR_TG BIT(TIMER_EGR_TG_BIT) +#define TIMER_EGR_CC4G BIT(TIMER_EGR_CC4G_BIT) +#define TIMER_EGR_CC3G BIT(TIMER_EGR_CC3G_BIT) +#define TIMER_EGR_CC2G BIT(TIMER_EGR_CC2G_BIT) +#define TIMER_EGR_CC1G BIT(TIMER_EGR_CC1G_BIT) +#define TIMER_EGR_UG BIT(TIMER_EGR_UG_BIT) + +/* Capture/compare mode registers, common values */ + +#define TIMER_CCMR_CCS_OUTPUT 0x0 +#define TIMER_CCMR_CCS_INPUT_TI1 0x1 +#define TIMER_CCMR_CCS_INPUT_TI2 0x2 +#define TIMER_CCMR_CCS_INPUT_TRC 0x3 + +/* Capture/compare mode register 1 (CCMR1) */ + +#define TIMER_CCMR1_OC2CE_BIT 15 +#define TIMER_CCMR1_OC2PE_BIT 11 +#define TIMER_CCMR1_OC2FE_BIT 10 +#define TIMER_CCMR1_OC1CE_BIT 7 +#define TIMER_CCMR1_OC1PE_BIT 3 +#define TIMER_CCMR1_OC1FE_BIT 2 + +#define TIMER_CCMR1_OC2CE BIT(TIMER_CCMR1_OC2CE_BIT) +#define TIMER_CCMR1_OC2M (0x3 << 12) +#define TIMER_CCMR1_IC2F (0xF << 12) +#define TIMER_CCMR1_OC2PE BIT(TIMER_CCMR1_OC2PE_BIT) +#define TIMER_CCMR1_OC2FE BIT(TIMER_CCMR1_OC2FE_BIT) +#define TIMER_CCMR1_IC2PSC (0x3 << 10) +#define TIMER_CCMR1_CC2S (0x3 << 8) +#define TIMER_CCMR1_CC2S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) +#define TIMER_CCMR1_OC1CE BIT(TIMER_CCMR1_OC1CE_BIT) +#define TIMER_CCMR1_OC1M (0x3 << 4) +#define TIMER_CCMR1_IC1F (0xF << 4) +#define TIMER_CCMR1_OC1PE BIT(TIMER_CCMR1_OC1PE_BIT) +#define TIMER_CCMR1_OC1FE BIT(TIMER_CCMR1_OC1FE_BIT) +#define TIMER_CCMR1_IC1PSC (0x3 << 2) +#define TIMER_CCMR1_CC1S 0x3 +#define TIMER_CCMR1_CC1S_OUTPUT TIMER_CCMR_CCS_OUTPUT +#define TIMER_CCMR1_CC1S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 +#define TIMER_CCMR1_CC1S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 +#define TIMER_CCMR1_CC1S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC + +/* Capture/compare mode register 2 (CCMR2) */ + +#define TIMER_CCMR2_OC4CE_BIT 15 +#define TIMER_CCMR2_OC4PE_BIT 11 +#define TIMER_CCMR2_OC4FE_BIT 10 +#define TIMER_CCMR2_OC3CE_BIT 7 +#define TIMER_CCMR2_OC3PE_BIT 3 +#define TIMER_CCMR2_OC3FE_BIT 2 + +#define TIMER_CCMR2_OC4CE BIT(TIMER_CCMR2_OC4CE_BIT) +#define TIMER_CCMR2_OC4M (0x3 << 12) +#define TIMER_CCMR2_IC2F (0xF << 12) +#define TIMER_CCMR2_OC4PE BIT(TIMER_CCMR2_OC4PE_BIT) +#define TIMER_CCMR2_OC4FE BIT(TIMER_CCMR2_OC4FE_BIT) +#define TIMER_CCMR2_IC2PSC (0x3 << 10) +#define TIMER_CCMR2_CC4S (0x3 << 8) +#define TIMER_CCMR1_CC4S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) +#define TIMER_CCMR1_CC4S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) +#define TIMER_CCMR1_CC4S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR1_CC4S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) +#define TIMER_CCMR2_OC3CE BIT(TIMER_CCMR2_OC3CE_BIT) +#define TIMER_CCMR2_OC3M (0x3 << 4) +#define TIMER_CCMR2_IC1F (0xF << 4) +#define TIMER_CCMR2_OC3PE BIT(TIMER_CCMR2_OC3PE_BIT) +#define TIMER_CCMR2_OC3FE BIT(TIMER_CCMR2_OC3FE_BIT) +#define TIMER_CCMR2_IC1PSC (0x3 << 2) +#define TIMER_CCMR2_CC3S 0x3 +#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR_CCS_OUTPUT +#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 +#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 +#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC + +/* Capture/compare enable register (CCER) */ + +#define TIMER_CCER_CC4P_BIT 13 +#define TIMER_CCER_CC4E_BIT 12 +#define TIMER_CCER_CC3P_BIT 9 +#define TIMER_CCER_CC3E_BIT 8 +#define TIMER_CCER_CC2P_BIT 5 +#define TIMER_CCER_CC2E_BIT 4 +#define TIMER_CCER_CC1P_BIT 1 +#define TIMER_CCER_CC1E_BIT 0 + +#define TIMER_CCER_CC4P BIT(TIMER_CCER_CC4P_BIT) +#define TIMER_CCER_CC4E BIT(TIMER_CCER_CC4E_BIT) +#define TIMER_CCER_CC3P BIT(TIMER_CCER_CC3P_BIT) +#define TIMER_CCER_CC3E BIT(TIMER_CCER_CC3E_BIT) +#define TIMER_CCER_CC2P BIT(TIMER_CCER_CC2P_BIT) +#define TIMER_CCER_CC2E BIT(TIMER_CCER_CC2E_BIT) +#define TIMER_CCER_CC1P BIT(TIMER_CCER_CC1P_BIT) +#define TIMER_CCER_CC1E BIT(TIMER_CCER_CC1E_BIT) + +/* Break and dead-time register (BDTR) */ + +#define TIMER_BDTR_MOE_BIT 15 +#define TIMER_BDTR_AOE_BIT 14 +#define TIMER_BDTR_BKP_BIT 13 +#define TIMER_BDTR_BKE_BIT 12 +#define TIMER_BDTR_OSSR_BIT 11 +#define TIMER_BDTR_OSSI_BIT 10 + +#define TIMER_BDTR_MOE BIT(TIMER_BDTR_MOE_BIT) +#define TIMER_BDTR_AOE BIT(TIMER_BDTR_AOE_BIT) +#define TIMER_BDTR_BKP BIT(TIMER_BDTR_BKP_BIT) +#define TIMER_BDTR_BKE BIT(TIMER_BDTR_BKE_BIT) +#define TIMER_BDTR_OSSR BIT(TIMER_BDTR_OSSR_BIT) +#define TIMER_BDTR_OSSI BIT(TIMER_BDTR_OSSI_BIT) +#define TIMER_BDTR_LOCK (0x3 << 8) +#define TIMER_BDTR_LOCK_OFF (0x0 << 8) +#define TIMER_BDTR_LOCK_LEVEL1 (0x1 << 8) +#define TIMER_BDTR_LOCK_LEVEL2 (0x2 << 8) +#define TIMER_BDTR_LOCK_LEVEL3 (0x3 << 8) +#define TIMER_BDTR_DTG 0xFF + +/* DMA control register (DCR) */ + +#define TIMER_DCR_DBL (0x1F << 8) +#define TIMER_DCR_DBL_1BYTE (0x0 << 8) +#define TIMER_DCR_DBL_2BYTE (0x1 << 8) +#define TIMER_DCR_DBL_3BYTE (0x2 << 8) +#define TIMER_DCR_DBL_4BYTE (0x3 << 8) +#define TIMER_DCR_DBL_5BYTE (0x4 << 8) +#define TIMER_DCR_DBL_6BYTE (0x5 << 8) +#define TIMER_DCR_DBL_7BYTE (0x6 << 8) +#define TIMER_DCR_DBL_8BYTE (0x7 << 8) +#define TIMER_DCR_DBL_9BYTE (0x8 << 8) +#define TIMER_DCR_DBL_10BYTE (0x9 << 8) +#define TIMER_DCR_DBL_11BYTE (0xA << 8) +#define TIMER_DCR_DBL_12BYTE (0xB << 8) +#define TIMER_DCR_DBL_13BYTE (0xC << 8) +#define TIMER_DCR_DBL_14BYTE (0xD << 8) +#define TIMER_DCR_DBL_15BYTE (0xE << 8) +#define TIMER_DCR_DBL_16BYTE (0xF << 8) +#define TIMER_DCR_DBL_17BYTE (0x10 << 8) +#define TIMER_DCR_DBL_18BYTE (0x11 << 8) +#define TIMER_DCR_DBA 0x1F +#define TIMER_DCR_DBA_CR1 0x0 +#define TIMER_DCR_DBA_CR2 0x1 +#define TIMER_DCR_DBA_SMCR 0x2 +#define TIMER_DCR_DBA_DIER 0x3 +#define TIMER_DCR_DBA_SR 0x4 +#define TIMER_DCR_DBA_EGR 0x5 +#define TIMER_DCR_DBA_CCMR1 0x6 +#define TIMER_DCR_DBA_CCMR2 0x7 +#define TIMER_DCR_DBA_CCER 0x8 +#define TIMER_DCR_DBA_CNT 0x9 +#define TIMER_DCR_DBA_PSC 0xA +#define TIMER_DCR_DBA_ARR 0xB +#define TIMER_DCR_DBA_RCR 0xC +#define TIMER_DCR_DBA_CCR1 0xD +#define TIMER_DCR_DBA_CCR2 0xE +#define TIMER_DCR_DBA_CCR3 0xF +#define TIMER_DCR_DBA_CCR4 0x10 +#define TIMER_DCR_DBA_BDTR 0x11 +#define TIMER_DCR_DBA_DCR 0x12 +#define TIMER_DCR_DBA_DMAR 0x13 + +/* + * Convenience routines + */ + +/** + * Used to configure the behavior of a timer channel. Note that not + * all timers can be configured in every mode. + */ +/* TODO TIMER_PWM_CENTER_ALIGNED, TIMER_INPUT_CAPTURE, TIMER_ONE_PULSE */ +typedef enum timer_mode { + TIMER_DISABLED, /**< In this mode, the timer stops counting, + channel interrupts are detached, and no state + changes are output. */ + TIMER_PWM, /**< PWM output mode. This is the default mode for pins + after initialization. */ + /* TIMER_PWM_CENTER_ALIGNED, /\**< Center-aligned PWM output mode. *\/ */ + TIMER_OUTPUT_COMPARE, /**< In this mode, the timer counts from 0 + to its reload value repeatedly; every + time the counter value reaches one of + the channel compare values, the + corresponding interrupt is fired. */ + /* TIMER_INPUT_CAPTURE, /\**< In this mode, the timer can measure the */ + /* pulse lengths of input signals. *\/ */ + /* TIMER_ONE_PULSE /\**< In this mode, the timer can generate a single */ + /* pulse on a GPIO pin for a specified amount of */ + /* time. *\/ */ +} timer_mode; + +/** Timer channel numbers */ +typedef enum timer_channel { + TIMER_CH1 = 1, /**< Channel 1 */ + TIMER_CH2 = 2, /**< Channel 2 */ + TIMER_CH3 = 3, /**< Channel 3 */ + TIMER_CH4 = 4 /**< Channel 4 */ +} timer_channel; + +/* + * Note: Don't require timer_channel arguments! We want to be able to say + * + * for (int channel = 1; channel <= 4; channel++) { + * ... + * } + * + * without the compiler yelling at us. + */ + +void timer_init(timer_dev *dev); +void timer_disable(timer_dev *dev); +void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode); +void timer_foreach(void (*fn)(timer_dev*)); + +/** + * @brief Timer interrupt number. + * + * Not all timers support all of these values; see the descriptions + * for each value. + */ +typedef enum timer_interrupt_id { + TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */ + TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt, available + on general and advanced timers only. */ + TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt, general and + advanced timers only. */ + TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt, general and + advanced timers only. */ + TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt, general and + advanced timers only. */ + TIMER_COM_INTERRUPT, /**< COM interrupt, advanced timers only */ + TIMER_TRG_INTERRUPT, /**< Trigger interrupt, general and advanced + timers only */ + TIMER_BREAK_INTERRUPT /**< Break interrupt, advanced timers only. */ +} timer_interrupt_id; + +void timer_attach_interrupt(timer_dev *dev, + uint8 interrupt, + voidFuncPtr handler); +void timer_detach_interrupt(timer_dev *dev, uint8 interrupt); + +/** + * Initialize all timer devices on the chip. + */ +static inline void timer_init_all(void) { + timer_foreach(timer_init); +} + +/** + * Disables all timers on the device. + */ +static inline void timer_disable_all(void) { + timer_foreach(timer_disable); +} + +/** + * @brief Stop a timer's counter from changing. + * + * Does not affect the timer's mode or other settings. + * + * @param dev Device whose counter to pause. + */ +static inline void timer_pause(timer_dev *dev) { + *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 0; +} + +/** + * @brief Start a timer's counter. + * + * Does not affect the timer's mode or other settings. + * + * @param dev Device whose counter to resume + */ +static inline void timer_resume(timer_dev *dev) { + *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 1; +} + +/** + * @brief Returns the timer's counter value. + * + * This value is likely to be inaccurate if the counter is running + * with a low prescaler. + * + * @param dev Timer whose counter to return + */ +static inline uint16 timer_get_count(timer_dev *dev) { + return (uint16)(dev->regs).bas->CNT; +} + +/** + * @brief Sets the counter value for the given timer. + * @param dev Timer whose counter to set + * @param value New counter value + */ +static inline void timer_set_count(timer_dev *dev, uint16 value) { + (dev->regs).bas->CNT = value; +} + +/** + * @brief Returns the given timer's prescaler. + * + * Note that if the timer's prescaler is set (e.g. via + * timer_set_prescaler() or accessing a TIMx_PSC register), the value + * returned by this function will reflect the new setting, but the + * timer's counter will only reflect the new prescaler at the next + * update event. + * + * @param dev Timer whose prescaler to return + * @see timer_generate_update() + */ +static inline uint16 timer_get_prescaler(timer_dev *dev) { + return (uint16)(dev->regs).bas->PSC; +} + +/** + * @brief Set a timer's prescale value. + * + * Divides the input clock by (PSC+1). The new value will not take + * effect until the next update event. + * + * @param dev Timer whose prescaler to set + * @param psc New prescaler value + * @see timer_generate_update() + */ +static inline void timer_set_prescaler(timer_dev *dev, uint16 psc) { + (dev->regs).bas->PSC = psc; +} + +/** + * @brief Returns a timer's reload value. + * @param dev Timer whose reload value to return + */ +static inline uint16 timer_get_reload(timer_dev *dev) { + return (uint16)(dev->regs).bas->ARR; +} + +/** + * @brief Set a timer's reload value. + * @param dev Timer whose reload value to set + * @param arr New reload value to use. Takes effect at next update event. + * @see timer_generate_update() + */ +static inline void timer_set_reload(timer_dev *dev, uint16 arr) { + (dev->regs).bas->ARR = arr; +} + +/** + * @brief Get the compare value for the given timer channel. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose compare value to get. + */ +static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) { + __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1); + return *ccr; +} + +/** + * @brief Set the compare value for the given timer channel. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose compare value to set. + * @param value New compare value. + */ +static inline void timer_set_compare(timer_dev *dev, + uint8 channel, + uint16 value) { + __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1); + *ccr = value; +} + +/** + * @brief Generate an update event for the given timer. + * + * Normally, this will cause the prescaler and auto-reload values in + * the PSC and ARR registers to take immediate effect. However, this + * function will do nothing if the UDIS bit is set in the timer's CR1 + * register (UDIS is cleared by default). + * + * @param dev Timer device to generate an update for. + */ +static inline void timer_generate_update(timer_dev *dev) { + *bb_perip(&(dev->regs).bas->EGR, TIMER_EGR_UG_BIT) = 1; +} + +/** + * @brief Enable a timer's trigger DMA request + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + */ +static inline void timer_dma_enable_trg_req(timer_dev *dev) { + *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 1; +} + +/** + * @brief Disable a timer's trigger DMA request + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + */ +static inline void timer_dma_disable_trg_req(timer_dev *dev) { + *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 0; +} + +/** + * @brief Enable a timer channel's DMA request. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL + * @param channel Channel whose DMA request to enable. + */ +static inline void timer_dma_enable_req(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 1; +} + +/** + * @brief Disable a timer channel's DMA request. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose DMA request to disable. + */ +static inline void timer_dma_disable_req(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 0; +} + +/** + * @brief Enable a timer interrupt. + * @param dev Timer device. + * @param interrupt Interrupt number to enable; this may be any + * timer_interrupt_id value appropriate for the timer. + * @see timer_interrupt_id + * @see timer_channel + */ +static inline void timer_enable_irq(timer_dev *dev, uint8 interrupt) { + *bb_perip(&(dev->regs).adv->DIER, interrupt) = 1; +} + +/** + * @brief Disable a timer interrupt. + * @param dev Timer device. + * @param interrupt Interrupt number to disable; this may be any + * timer_interrupt_id value appropriate for the timer. + * @see timer_interrupt_id + * @see timer_channel + */ +static inline void timer_disable_irq(timer_dev *dev, uint8 interrupt) { + *bb_perip(&(dev->regs).adv->DIER, interrupt) = 0; +} + +/** + * @brief Enable a timer channel's capture/compare signal. + * + * If the channel is configured as output, the corresponding output + * compare signal will be output on the corresponding output pin. If + * the channel is configured as input, enables capture of the counter + * value into the input capture/compare register. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel to enable, from 1 to 4. + */ +static inline void timer_cc_enable(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 1; +} + +/** + * @brief Disable a timer channel's output compare or input capture signal. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel to disable, from 1 to 4. + * @see timer_cc_enable() + */ +static inline void timer_cc_disable(timer_dev *dev, uint8 channel) { + *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 0; +} + +/** + * @brief Get a channel's capture/compare output polarity + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose capture/compare output polarity to get. + * @return Polarity, either 0 or 1. + * @see timer_cc_set_polarity() + */ +static inline uint8 timer_cc_get_pol(timer_dev *dev, uint8 channel) { + return *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1); +} + +/** + * @brief Set a timer channel's capture/compare output polarity. + * + * If the timer channel is configured as output: polarity == 0 means + * the output channel will be active high; polarity == 1 means active + * low. + * + * If the timer channel is configured as input: polarity == 0 means + * capture is done on the rising edge of ICn; when used as an external + * trigger, ICn is non-inverted. polarity == 1 means capture is done + * on the falling edge of ICn; when used as an external trigger, ICn + * is inverted. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel whose capture/compare output polarity to set. + * @param pol New polarity, 0 or 1. + */ +static inline void timer_cc_set_pol(timer_dev *dev, uint8 channel, uint8 pol) { + *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1) = pol; +} + +/** + * @brief Get a timer's DMA burst length. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @return Number of bytes to be transferred per DMA request, from 1 to 18. + */ +static inline uint8 timer_dma_get_burst_len(timer_dev *dev) { + uint32 dbl = ((dev->regs).gen->DCR & TIMER_DCR_DBL) >> 8; + return dbl + 1; /* 0 means 1 byte, etc. */ +} + +/** + * @brief Set a timer's DMA burst length. + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param length DMA burst length; i.e., number of bytes to transfer + * per DMA request, from 1 to 18. + */ +static inline void timer_dma_set_burst_len(timer_dev *dev, uint8 length) { + uint32 tmp = (dev->regs).gen->DCR; + tmp &= ~TIMER_DCR_DBL; + tmp |= (length - 1) << 8; + (dev->regs).gen->DCR = tmp; +} + +/** + * @brief Timer DMA base address. + * + * Defines the base address for DMA transfers. + */ +typedef enum timer_dma_base_addr { + TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, /**< Base is control register 1 */ + TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, /**< Base is control register 2 */ + TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, /**< Base is slave mode + control register */ + TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, /**< Base is DMA interrupt enable + register */ + TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, /**< Base is status register */ + TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, /**< Base is event generation + register */ + TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, /**< Base is capture/compare + mode register 1 */ + TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, /**< Base is capture/compare + mode register 2 */ + TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER, /**< Base is capture/compare + enable register */ + TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT, /**< Base is counter */ + TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC, /**< Base is prescaler */ + TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR, /**< Base is auto-reload + register */ + TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR, /**< Base is repetition + counter register */ + TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1, /**< Base is capture/compare + register 1 */ + TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2, /**< Base is capture/compare + register 2 */ + TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3, /**< Base is capture/compare + register 3 */ + TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4, /**< Base is capture/compare + register 4 */ + TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR, /**< Base is break and + dead-time register */ + TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR, /**< Base is DMA control + register */ + TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR /**< Base is DMA address for + full transfer */ +} timer_dma_base_addr; + +/** + * @brief Get the timer's DMA base address. + * + * Some restrictions apply; see ST RM0008. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @return DMA base address + */ +static inline timer_dma_base_addr timer_dma_get_base_addr(timer_dev *dev) { + uint32 dcr = (dev->regs).gen->DCR; + return (timer_dma_base_addr)(dcr & TIMER_DCR_DBA); +} + +/** + * @brief Set the timer's DMA base address. + * + * Some restrictions apply; see ST RM0008. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param dma_base DMA base address. + */ +static inline void timer_dma_set_base_addr(timer_dev *dev, + timer_dma_base_addr dma_base) { + uint32 tmp = (dev->regs).gen->DCR; + tmp &= ~TIMER_DCR_DBA; + tmp |= dma_base; + (dev->regs).gen->DCR = tmp; +} + +/** + * Timer output compare modes. + */ +typedef enum timer_oc_mode { + TIMER_OC_MODE_FROZEN = 0 << 4, /**< Frozen: comparison between output + compare register and counter has no + effect on the outputs. */ + TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, /**< OCxREF signal is forced + high when the count matches + the channel capture/compare + register. */ + TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, /**< OCxREF signal is forced + low when the counter matches + the channel capture/compare + register. */ + TIMER_OC_MODE_TOGGLE = 3 << 4, /**< OCxREF toggles when counter + matches the cannel capture/compare + register. */ + TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, /**< OCxREF is forced low. */ + TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, /**< OCxREF is forced high. */ + TIMER_OC_MODE_PWM_1 = 6 << 4, /**< PWM mode 1. In upcounting, channel is + active as long as count is less than + channel capture/compare register, else + inactive. In downcounting, channel is + inactive as long as count exceeds + capture/compare register, else + active. */ + TIMER_OC_MODE_PWM_2 = 7 << 4 /**< PWM mode 2. In upcounting, channel is + inactive as long as count is less than + capture/compare register, else active. + In downcounting, channel is active as + long as count exceeds capture/compare + register, else inactive. */ +} timer_oc_mode; + +/** + * Timer output compare mode flags. + * @see timer_oc_set_mode() + */ +typedef enum timer_oc_mode_flags { + TIMER_OC_CE = BIT(7), /**< Output compare clear enable. */ + TIMER_OC_PE = BIT(3), /**< Output compare preload enable. */ + TIMER_OC_FE = BIT(2) /**< Output compare fast enable. */ +} timer_oc_mode_flags; + +/** + * @brief Configure a channel's output compare mode. + * + * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. + * @param channel Channel to configure in output compare mode. + * @param mode Timer mode to set. + * @param flags OR of timer_oc_mode_flags. + * @see timer_oc_mode + * @see timer_oc_mode_flags + */ +static inline void timer_oc_set_mode(timer_dev *dev, + uint8 channel, + timer_oc_mode mode, + uint8 flags) { + /* channel == 1,2 -> CCMR1; channel == 3,4 -> CCMR2 */ + __io uint32 *ccmr = &(dev->regs).gen->CCMR1 + (((channel - 1) >> 1) & 1); + /* channel == 1,3 -> shift = 0, channel == 2,4 -> shift = 8 */ + uint8 shift = 8 * (1 - (channel & 1)); + + uint32 tmp = *ccmr; + tmp &= ~(0xFF << shift); + tmp |= (mode | flags | TIMER_CCMR_CCS_OUTPUT) << shift; + *ccmr = tmp; +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/usart.h b/libmaple/include/libmaple/usart.h new file mode 100644 index 0000000..f9bdb8b --- /dev/null +++ b/libmaple/include/libmaple/usart.h @@ -0,0 +1,336 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file usart.h + * @author Marti Bolivar , + * Perry Hung + * @brief USART definitions and prototypes + */ + +#ifndef _LIBMAPLE_USART_H_ +#define _LIBMAPLE_USART_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include +#include + +/* + * Register maps and devices + */ + +/** USART register map type */ +typedef struct usart_reg_map { + __io uint32 SR; /**< Status register */ + __io uint32 DR; /**< Data register */ + __io uint32 BRR; /**< Baud rate register */ + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 CR3; /**< Control register 3 */ + __io uint32 GTPR; /**< Guard time and prescaler register */ +} usart_reg_map; + +/** USART1 register map base pointer */ +#define USART1_BASE ((struct usart_reg_map*)0x40013800) +/** USART2 register map base pointer */ +#define USART2_BASE ((struct usart_reg_map*)0x40004400) +/** USART3 register map base pointer */ +#define USART3_BASE ((struct usart_reg_map*)0x40004800) +#ifdef STM32_HIGH_DENSITY +/** UART4 register map base pointer */ +#define UART4_BASE ((struct usart_reg_map*)0x40004C00) +/** UART5 register map base pointer */ +#define UART5_BASE ((struct usart_reg_map*)0x40005000) +#endif + +/* + * Register bit definitions + */ + +/* Status register */ + +#define USART_SR_CTS_BIT 9 +#define USART_SR_LBD_BIT 8 +#define USART_SR_TXE_BIT 7 +#define USART_SR_TC_BIT 6 +#define USART_SR_RXNE_BIT 5 +#define USART_SR_IDLE_BIT 4 +#define USART_SR_ORE_BIT 3 +#define USART_SR_NE_BIT 2 +#define USART_SR_FE_BIT 1 +#define USART_SR_PE_BIT 0 + +#define USART_SR_CTS BIT(USART_SR_CTS_BIT) +#define USART_SR_LBD BIT(USART_SR_LBD_BIT) +#define USART_SR_TXE BIT(USART_SR_TXE_BIT) +#define USART_SR_TC BIT(USART_SR_TC_BIT) +#define USART_SR_RXNE BIT(USART_SR_RXNE_BIT) +#define USART_SR_IDLE BIT(USART_SR_IDLE_BIT) +#define USART_SR_ORE BIT(USART_SR_ORE_BIT) +#define USART_SR_NE BIT(USART_SR_NE_BIT) +#define USART_SR_FE BIT(USART_SR_FE_BIT) +#define USART_SR_PE BIT(USART_SR_PE_BIT) + +/* Data register */ + +#define USART_DR_DR 0xFF + +/* Baud rate register */ + +#define USART_BRR_DIV_MANTISSA (0xFFF << 4) +#define USART_BRR_DIV_FRACTION 0xF + +/* Control register 1 */ + +#define USART_CR1_UE_BIT 13 +#define USART_CR1_M_BIT 12 +#define USART_CR1_WAKE_BIT 11 +#define USART_CR1_PCE_BIT 10 +#define USART_CR1_PS_BIT 9 +#define USART_CR1_PEIE_BIT 8 +#define USART_CR1_TXEIE_BIT 7 +#define USART_CR1_TCIE_BIT 6 +#define USART_CR1_RXNEIE_BIT 5 +#define USART_CR1_IDLEIE_BIT 4 +#define USART_CR1_TE_BIT 3 +#define USART_CR1_RE_BIT 2 +#define USART_CR1_RWU_BIT 1 +#define USART_CR1_SBK_BIT 0 + +#define USART_CR1_UE BIT(USART_CR1_UE_BIT) +#define USART_CR1_M BIT(USART_CR1_M_BIT) +#define USART_CR1_WAKE BIT(USART_CR1_WAKE_BIT) +#define USART_CR1_WAKE_IDLE (0 << USART_CR1_WAKE_BIT) +#define USART_CR1_WAKE_ADDR (1 << USART_CR1_WAKE_BIT) +#define USART_CR1_PCE BIT(USART_CR1_PCE_BIT) +#define USART_CR1_PS BIT(USART_CR1_PS_BIT) +#define USART_CR1_PS_EVEN (0 << USART_CR1_PS_BIT) +#define USART_CR1_PS_ODD (1 << USART_CR1_PS_BIT) +#define USART_CR1_PEIE BIT(USART_CR1_PEIE_BIT) +#define USART_CR1_TXEIE BIT(USART_CR1_TXEIE_BIT) +#define USART_CR1_TCIE BIT(USART_CR1_TCIE_BIT) +#define USART_CR1_RXNEIE BIT(USART_CR1_RXNEIE_BIT) +#define USART_CR1_IDLEIE BIT(USART_CR1_IDLEIE_BIT) +#define USART_CR1_TE BIT(USART_CR1_TE_BIT) +#define USART_CR1_RE BIT(USART_CR1_RE_BIT) +#define USART_CR1_RWU BIT(USART_CR1_RWU_BIT) +#define USART_CR1_RWU_ACTIVE (0 << USART_CR1_RWU_BIT) +#define USART_CR1_RWU_MUTE (1 << USART_CR1_RWU_BIT) +#define USART_CR1_SBK BIT(USART_CR1_SBK_BIT) + +/* Control register 2 */ + +#define USART_CR2_LINEN_BIT 14 +#define USART_CR2_CLKEN_BIT 11 +#define USART_CR2_CPOL_BIT 10 +#define USART_CR2_CPHA_BIT 9 +#define USART_CR2_LBCL_BIT 8 +#define USART_CR2_LBDIE_BIT 6 +#define USART_CR2_LBDL_BIT 5 + +#define USART_CR2_LINEN BIT(USART_CR2_LINEN_BIT) +#define USART_CR2_STOP (0x3 << 12) +#define USART_CR2_STOP_BITS_1 (0x0 << 12) +/* Not on UART4, UART5 */ +#define USART_CR2_STOP_BITS_POINT_5 (0x1 << 12) +/* Not on UART4, UART5 */ +#define USART_CR2_STOP_BITS_1_POINT_5 (0x3 << 12) +#define USART_CR2_STOP_BITS_2 (0x2 << 12) +#define USART_CR2_CLKEN BIT(USART_CR2_CLKEN_BIT) +/* Not on UART4, UART5 */ +#define USART_CR2_CPOL BIT(USART_CR2_CPOL_BIT) +#define USART_CR2_CPOL_LOW (0x0 << USART_CR2_CLKEN_BIT) +#define USART_CR2_CPOL_HIGH (0x1 << USART_CR2_CLKEN_BIT) +/* Not on UART4, UART5 */ +#define USART_CR2_CPHA BIT(USART_CR2_CPHA_BIT) +#define USART_CR2_CPHA_FIRST (0x0 << USART_CR2_CPHA_BIT) +#define USART_CR2_CPHA_SECOND (0x1 << USART_CR2_CPHA_BIT) +/* Not on UART4, UART5 */ +#define USART_CR2_LBCL BIT(USART_CR2_LBCL_BIT) +#define USART_CR2_LBDIE BIT(USART_CR2_LBDIE_BIT) +#define USART_CR2_LBDL BIT(USART_CR2_LBDL_BIT) +#define USART_CR2_LBDL_10_BIT (0 << USART_CR2_LBDL_BIT) +#define USART_CR2_LBDL_11_BIT (1 << USART_CR2_LBDL_BIT) +#define USART_CR2_ADD 0xF + +/* Control register 3 */ + +#define USART_CR3_CTSIE_BIT 10 +#define USART_CR3_CTSE_BIT 9 +#define USART_CR3_RTSE_BIT 8 +#define USART_CR3_DMAT_BIT 7 +#define USART_CR3_DMAR_BIT 6 +#define USART_CR3_SCEN_BIT 5 +#define USART_CR3_NACK_BIT 4 +#define USART_CR3_HDSEL_BIT 3 +#define USART_CR3_IRLP_BIT 2 +#define USART_CR3_IREN_BIT 1 +#define USART_CR3_EIE_BIT 0 + +/* Not on UART4, UART5 */ +#define USART_CR3_CTSIE BIT(USART_CR3_CTSIE_BIT) +/* Not on UART4, UART5 */ +#define USART_CR3_CTSE BIT(USART_CR3_CTSE_BIT) +/* Not on UART4, UART5 */ +#define USART_CR3_RTSE BIT(USART_CR3_RTSE_BIT) +/* Not on UART5 */ +#define USART_CR3_DMAT BIT(USART_CR3_DMAT_BIT) +/* Not on UART5 */ +#define USART_CR3_DMAR BIT(USART_CR3_DMAR_BIT) +/* Not on UART4, UART5 */ +#define USART_CR3_SCEN BIT(USART_CR3_SCEN_BIT) +/* Not on UART4, UART5 */ +#define USART_CR3_NACK BIT(USART_CR3_NACK_BIT) +#define USART_CR3_HDSEL BIT(USART_CR3_HDSEL_BIT) +#define USART_CR3_IRLP BIT(USART_CR3_IRLP_BIT) +#define USART_CR3_IRLP_NORMAL (0 << USART_CR3_IRLP_BIT) +#define USART_CR3_IRLP_LOW_POWER (1 << USART_CR3_IRLP_BIT) +#define USART_CR3_IREN BIT(USART_CR3_IREN_BIT) +#define USART_CR3_EIE BIT(USART_CR3_EIE_BIT) + +/* Guard time and prescaler register */ + +/* Not on UART4, UART5 */ +#define USART_GTPR_GT (0xFF << 8) +/* Not on UART4, UART5 */ +#define USART_GTPR_PSC 0xFF + +/* + * Devices + */ + +#ifndef USART_RX_BUF_SIZE +#define USART_RX_BUF_SIZE 64 +#endif + +/** USART device type */ +typedef struct usart_dev { + usart_reg_map *regs; /**< Register map */ + ring_buffer *rb; /**< RX ring buffer */ + uint32 max_baud; /**< Maximum baud */ + uint8 rx_buf[USART_RX_BUF_SIZE]; /**< @brief Deprecated. + * Actual RX buffer used by rb. + * This field will be removed in + * a future release. */ + rcc_clk_id clk_id; /**< RCC clock information */ + nvic_irq_num irq_num; /**< USART NVIC interrupt */ +} usart_dev; + +extern usart_dev *USART1; +extern usart_dev *USART2; +extern usart_dev *USART3; +#ifdef STM32_HIGH_DENSITY +extern usart_dev *UART4; +extern usart_dev *UART5; +#endif + +void usart_init(usart_dev *dev); +void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud); +void usart_enable(usart_dev *dev); +void usart_disable(usart_dev *dev); +void usart_foreach(void (*fn)(usart_dev *dev)); +uint32 usart_tx(usart_dev *dev, const uint8 *buf, uint32 len); +uint32 usart_rx(usart_dev *dev, uint8 *buf, uint32 len); +void usart_putudec(usart_dev *dev, uint32 val); + +/** + * @brief Disable all serial ports. + */ +static inline void usart_disable_all(void) { + usart_foreach(usart_disable); +} + +/** + * @brief Transmit one character on a serial port. + * + * This function blocks until the character has been successfully + * transmitted. + * + * @param dev Serial port to send on. + * @param byte Byte to transmit. + */ +static inline void usart_putc(usart_dev* dev, uint8 byte) { + while (!usart_tx(dev, &byte, 1)) + ; +} + +/** + * @brief Transmit a character string on a serial port. + * + * This function blocks until str is completely transmitted. + * + * @param dev Serial port to send on + * @param str String to send + */ +static inline void usart_putstr(usart_dev *dev, const char* str) { + uint32 i = 0; + while (str[i] != '\0') { + usart_putc(dev, str[i++]); + } +} + +/** + * @brief Read one character from a serial port. + * + * It's not safe to call this function if the serial port has no data + * available. + * + * @param dev Serial port to read from + * @return byte read + * @see usart_data_available() + */ +static inline uint8 usart_getc(usart_dev *dev) { + return rb_remove(dev->rb); +} + +/** + * @brief Return the amount of data available in a serial port's RX buffer. + * @param dev Serial port to check + * @return Number of bytes in dev's RX buffer. + */ +static inline uint32 usart_data_available(usart_dev *dev) { + return rb_full_count(dev->rb); +} + +/** + * @brief Discard the contents of a serial port's RX buffer. + * @param dev Serial port whose buffer to empty. + */ +static inline void usart_reset_rx(usart_dev *dev) { + rb_reset(dev->rb); +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/include/libmaple/usb.h b/libmaple/include/libmaple/usb.h new file mode 100644 index 0000000..82bace9 --- /dev/null +++ b/libmaple/include/libmaple/usb.h @@ -0,0 +1,82 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* + * NOTE: This API is _unstable_ and will change drastically over time. + */ + +#ifndef _LIBMAPLE_USB_H_ +#define _LIBMAPLE_USB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#ifndef USB_ISR_MSK +/* Handle CTRM, WKUPM, SUSPM, ERRM, SOFM, ESOFM, RESETM */ +#define USB_ISR_MSK 0xBF00 +#endif + +typedef enum usb_dev_state { + USB_UNCONNECTED, + USB_ATTACHED, + USB_POWERED, + USB_SUSPENDED, + USB_ADDRESSED, + USB_CONFIGURED +} usb_dev_state; + +/* Encapsulates global state formerly handled by usb_lib/ */ +typedef struct usblib_dev { + uint32 irq_mask; + void (**ep_int_in)(void); + void (**ep_int_out)(void); + usb_dev_state state; + rcc_clk_id clk_id; +} usblib_dev; + +extern usblib_dev *USBLIB; + +void usb_init_usblib(usblib_dev *dev, + void (**ep_int_in)(void), + void (**ep_int_out)(void)); + +static inline uint8 usb_is_connected(usblib_dev *dev) { + return dev->state != USB_UNCONNECTED; +} + +static inline uint8 usb_is_configured(usblib_dev *dev) { + return dev->state == USB_CONFIGURED; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/include/libmaple/util.h b/libmaple/include/libmaple/util.h new file mode 100644 index 0000000..d0b7b0b --- /dev/null +++ b/libmaple/include/libmaple/util.h @@ -0,0 +1,111 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file util.h + * @brief Miscellaneous utility macros and procedures. + */ + +#ifndef _LIBMAPLE_UTIL_H_ +#define _LIBMAPLE_UTIL_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Bit manipulation + */ + +/** 1 << the bit number */ +#define BIT(shift) (1UL << (shift)) +/** Mask shifted left by 'shift' */ +#define BIT_MASK_SHIFT(mask, shift) ((mask) << (shift)) +/** Bits m to n of x */ +#define GET_BITS(x, m, n) ((((uint32)x) << (31 - (n))) >> ((31 - (n)) + (m))) +/** True if v is a power of two (1, 2, 4, 8, ...) */ +#define IS_POWER_OF_TWO(v) ((v) && !((v) & ((v) - 1))) + +/* + * Failure routines + */ + +void __error(void); +void _fail(const char*, int, const char*); +void throb(void); + +/* + * Asserts and debug levels + */ + +#define DEBUG_NONE 0 +#define DEBUG_FAULT 1 +#define DEBUG_ALL 2 + +/** + * \def DEBUG_LEVEL + * + * Controls the level of assertion checking. + * + * The higher the debug level, the more assertions will be compiled + * in. This increases the amount of debugging information, but slows + * down (and increases the size of) the binary. + * + * The debug levels, from lowest to highest, are DEBUG_NONE, + * DEBUG_FAULT, and DEBUG_ALL. The default level is DEBUG_ALL. + */ + +#ifndef DEBUG_LEVEL +#define DEBUG_LEVEL DEBUG_ALL +#endif + +#if DEBUG_LEVEL >= DEBUG_ALL +#define ASSERT(exp) \ + if (exp) { \ + } else { \ + _fail(__FILE__, __LINE__, #exp); \ + } +#else +#define ASSERT(exp) (void)((0)) +#endif + +#if DEBUG_LEVEL >= DEBUG_FAULT +#define ASSERT_FAULT(exp) \ + if (exp) { \ + } else { \ + _fail(__FILE__, __LINE__, #exp); \ + } +#else +#define ASSERT_FAULT(exp) (void)((0)) +#endif + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/iwdg.c b/libmaple/iwdg.c index 63c1b2b..6dd77fc 100644 --- a/libmaple/iwdg.c +++ b/libmaple/iwdg.c @@ -29,7 +29,7 @@ * @brief Independent watchdog (IWDG) support */ -#include "iwdg.h" +#include /** * @brief Initialise and start the watchdog diff --git a/libmaple/iwdg.h b/libmaple/iwdg.h deleted file mode 100644 index 59e8e18..0000000 --- a/libmaple/iwdg.h +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Michael Hope. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file iwdg.h - * @author Michael Hope, Marti Bolivar - * @brief Independent watchdog support. - * - * To use the independent watchdog, first call iwdg_init() with the - * appropriate prescaler and IWDG counter reload values for your - * application. Afterwards, you must periodically call iwdg_feed() - * before the IWDG counter reaches 0 to reset the counter to its - * reload value. If you do not, the chip will reset. - * - * Once started, the independent watchdog cannot be turned off. - */ - -#ifndef _IWDG_H_ -#define _IWDG_H_ - -#include "libmaple_types.h" -#include "util.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Register map - */ - -/** Independent watchdog register map type. */ -typedef struct iwdg_reg_map { - __io uint32 KR; /**< Key register. */ - __io uint32 PR; /**< Prescaler register. */ - __io uint32 RLR; /**< Reload register. */ - __io uint32 SR; /**< Status register */ -} iwdg_reg_map; - -/** Independent watchdog base pointer */ -#define IWDG_BASE ((struct iwdg_reg_map*)0x40003000) - -/* - * Register bit definitions - */ - -/* Key register */ - -#define IWDG_KR_UNLOCK 0x5555 -#define IWDG_KR_FEED 0xAAAA -#define IWDG_KR_START 0xCCCC - -/* Prescaler register */ - -#define IWDG_PR_DIV_4 0x0 -#define IWDG_PR_DIV_8 0x1 -#define IWDG_PR_DIV_16 0x2 -#define IWDG_PR_DIV_32 0x3 -#define IWDG_PR_DIV_64 0x4 -#define IWDG_PR_DIV_128 0x5 -#define IWDG_PR_DIV_256 0x6 - -/* Status register */ - -#define IWDG_SR_RVU_BIT 1 -#define IWDG_SR_PVU_BIT 0 - -#define IWDG_SR_RVU BIT(IWDG_SR_RVU_BIT) -#define IWDG_SR_PVU BIT(IWDG_SR_PVU_BIT) - -/** - * @brief Independent watchdog prescalers. - * - * These divide the 40 kHz IWDG clock. - */ -typedef enum iwdg_prescaler { - IWDG_PRE_4 = IWDG_PR_DIV_4, /**< Divide by 4 */ - IWDG_PRE_8 = IWDG_PR_DIV_8, /**< Divide by 8 */ - IWDG_PRE_16 = IWDG_PR_DIV_16, /**< Divide by 16 */ - IWDG_PRE_32 = IWDG_PR_DIV_32, /**< Divide by 32 */ - IWDG_PRE_64 = IWDG_PR_DIV_64, /**< Divide by 64 */ - IWDG_PRE_128 = IWDG_PR_DIV_128, /**< Divide by 128 */ - IWDG_PRE_256 = IWDG_PR_DIV_256 /**< Divide by 256 */ -} iwdg_prescaler; - -void iwdg_init(iwdg_prescaler prescaler, uint16 reload); -void iwdg_feed(void); - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/libmaple.h b/libmaple/libmaple.h deleted file mode 100644 index c509f5d..0000000 --- a/libmaple/libmaple.h +++ /dev/null @@ -1,50 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple.h - * @brief General include file for libmaple - */ - -#ifndef _LIBMAPLE_H_ -#define _LIBMAPLE_H_ - -#include "libmaple_types.h" -#include "stm32.h" -#include "util.h" -#include "delay.h" - -/* - * Where to put usercode, based on space reserved for bootloader. - * - * FIXME this has no business being here - */ -#define USER_ADDR_ROM 0x08005000 -#define USER_ADDR_RAM 0x20000C00 -#define STACK_TOP 0x20000800 - -#endif - diff --git a/libmaple/libmaple_types.h b/libmaple/libmaple_types.h deleted file mode 100644 index 08adaff..0000000 --- a/libmaple/libmaple_types.h +++ /dev/null @@ -1,57 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple_types.h - * - * @brief libmaple types - */ - -#ifndef _LIBMAPLE_TYPES_H_ -#define _LIBMAPLE_TYPES_H_ - -typedef unsigned char uint8; -typedef unsigned short uint16; -typedef unsigned int uint32; -typedef unsigned long long uint64; - -typedef signed char int8; -typedef short int16; -typedef int int32; -typedef long long int64; - -typedef void (*voidFuncPtr)(void); - -#define __io volatile -#define __attr_flash __attribute__((section (".USER_FLASH"))) -#define __packed __attribute__((__packed__)) - -#ifndef NULL -#define NULL 0 -#endif - -#endif - diff --git a/libmaple/nvic.c b/libmaple/nvic.c index 345c850..b80751f 100644 --- a/libmaple/nvic.c +++ b/libmaple/nvic.c @@ -29,9 +29,9 @@ * @brief Nested vector interrupt controller support. */ -#include "nvic.h" -#include "scb.h" -#include "stm32.h" +#include +#include +#include /** * @brief Set interrupt priority for an interrupt line diff --git a/libmaple/nvic.h b/libmaple/nvic.h deleted file mode 100644 index feb7335..0000000 --- a/libmaple/nvic.h +++ /dev/null @@ -1,241 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file nvic.h - * @brief Nested vector interrupt controller support. - * - * Basic usage: - * - * @code - * // Initialise the interrupt controller and point to the vector - * // table at the start of flash. - * nvic_init(0x08000000, 0); - * // Bind in a timer interrupt handler - * timer_attach_interrupt(TIMER_CC1_INTERRUPT, handler); - * // Optionally set the priority - * nvic_irq_set_priority(NVIC_TIMER1_CC, 5); - * // All done, enable all interrupts - * nvic_globalirq_enable(); - * @endcode - */ - -#ifndef _NVIC_H_ -#define _NVIC_H_ - -#include "libmaple_types.h" -#include "util.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/** NVIC register map type. */ -typedef struct nvic_reg_map { - __io uint32 ISER[8]; /**< Interrupt Set Enable Registers */ - uint32 RESERVED0[24]; /**< Reserved */ - __io uint32 ICER[8]; /**< Interrupt Clear Enable Registers */ - uint32 RSERVED1[24]; /**< Reserved */ - __io uint32 ISPR[8]; /**< Interrupt Set Pending Registers */ - uint32 RESERVED2[24]; /**< Reserved */ - __io uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */ - uint32 RESERVED3[24]; /**< Reserved */ - __io uint32 IABR[8]; /**< Interrupt Active bit Registers */ - uint32 RESERVED4[56]; /**< Reserved */ - __io uint8 IP[240]; /**< Interrupt Priority Registers */ - uint32 RESERVED5[644]; /**< Reserved */ - __io uint32 STIR; /**< Software Trigger Interrupt Registers */ -} nvic_reg_map; - -/** NVIC register map base pointer. */ -#define NVIC_BASE ((struct nvic_reg_map*)0xE000E100) - -/** - * @brief Interrupt vector table interrupt numbers. - * - * Each positive-valued enumerator is the position of the - * corresponding interrupt in the vector table. Negative-valued - * enumerators correspond to interrupts controlled by the system - * handler block. - * - * @see scb.h - */ -typedef enum nvic_irq_num { - NVIC_NMI = -14, /**< Non-maskable interrupt */ - NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ - NVIC_MEM_MANAGE = -12, /**< Memory management */ - NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory - access fault. */ - NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction or - illegal state. */ - NVIC_SVC = -5, /**< System service call via SWI insruction */ - NVIC_DEBUG_MON = -4, /**< Debug monitor */ - NVIC_PEND_SVC = -2, /**< Pendable request for system service */ - NVIC_SYSTICK = -1, /**< System tick timer */ - NVIC_WWDG = 0, /**< Window watchdog interrupt */ - NVIC_PVD = 1, /**< PVD through EXTI line detection */ - NVIC_TAMPER = 2, /**< Tamper */ - NVIC_RTC = 3, /**< Real-time clock */ - NVIC_FLASH = 4, /**< Flash */ - NVIC_RCC = 5, /**< Reset and clock control */ - NVIC_EXTI0 = 6, /**< EXTI line 0 */ - NVIC_EXTI1 = 7, /**< EXTI line 1 */ - NVIC_EXTI2 = 8, /**< EXTI line 2 */ - NVIC_EXTI3 = 9, /**< EXTI line 3 */ - NVIC_EXTI4 = 10, /**< EXTI line 4 */ - NVIC_DMA_CH1 = 11, /**< DMA1 channel 1 */ - NVIC_DMA_CH2 = 12, /**< DMA1 channel 2 */ - NVIC_DMA_CH3 = 13, /**< DMA1 channel 3 */ - NVIC_DMA_CH4 = 14, /**< DMA1 channel 4 */ - NVIC_DMA_CH5 = 15, /**< DMA1 channel 5 */ - NVIC_DMA_CH6 = 16, /**< DMA1 channel 6 */ - NVIC_DMA_CH7 = 17, /**< DMA1 channel 7 */ - NVIC_ADC_1_2 = 18, /**< ADC1 and ADC2 */ - NVIC_USB_HP_CAN_TX = 19, /**< USB high priority or CAN TX */ - NVIC_USB_LP_CAN_RX0 = 20, /**< USB low priority or CAN RX0 */ - NVIC_CAN_RX1 = 21, /**< CAN RX1 */ - NVIC_CAN_SCE = 22, /**< CAN SCE */ - NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ - NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ - NVIC_TIMER1_UP = 25, /**< Timer 1 update */ - NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ - NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ - NVIC_TIMER2 = 28, /**< Timer 2 */ - NVIC_TIMER3 = 29, /**< Timer 3 */ - NVIC_TIMER4 = 30, /**< Timer 4 */ - NVIC_I2C1_EV = 31, /**< I2C1 event */ - NVIC_I2C1_ER = 32, /**< I2C1 error */ - NVIC_I2C2_EV = 33, /**< I2C2 event */ - NVIC_I2C2_ER = 34, /**< I2C2 error */ - NVIC_SPI1 = 35, /**< SPI1 */ - NVIC_SPI2 = 36, /**< SPI2 */ - NVIC_USART1 = 37, /**< USART1 */ - NVIC_USART2 = 38, /**< USART2 */ - NVIC_USART3 = 39, /**< USART3 */ - NVIC_EXTI_15_10 = 40, /**< EXTI line [15:10] */ - NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ - NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through - EXTI line */ - NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ - NVIC_TIMER8_UP = 44, /**< Timer 8 update */ - NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ - NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ -#ifdef STM32_HIGH_DENSITY - NVIC_ADC3 = 47, /**< ADC3 */ - NVIC_FSMC = 48, /**< FSMC */ - NVIC_SDIO = 49, /**< SDIO */ - NVIC_TIMER5 = 50, /**< Timer 5 */ - NVIC_SPI3 = 51, /**< SPI3 */ - NVIC_UART4 = 52, /**< UART4 */ - NVIC_UART5 = 53, /**< UART5 */ - NVIC_TIMER6 = 54, /**< Timer 6 */ - NVIC_TIMER7 = 55, /**< Timer 7 */ - NVIC_DMA2_CH1 = 56, /**< DMA2 channel 1 */ - NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ - NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ - NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ -#endif -} nvic_irq_num; - -/* - * Initialises the interrupt controller and sets all interrupts to the - * lowest priority. - * - * For stand-alone products, the base address is normally the start of - * flash (0x08000000). - * - * @param vector_table_address base address of the vector table - */ -void nvic_init(uint32 vector_table_address, uint32 offset); - -/** - * Sets the base address of the vector table. - */ -void nvic_set_vector_table(uint32 address, uint32 offset); - -void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority); -void nvic_sys_reset(); - -/** - * Enables interrupts and configurable fault handlers (clear PRIMASK). - */ -static inline void nvic_globalirq_enable() { - asm volatile("cpsie i"); -} - -/** - * Disable interrupts and configurable fault handlers (set PRIMASK). - */ -static inline void nvic_globalirq_disable() { - asm volatile("cpsid i"); -} - -/** - * @brief Enable interrupt irq_num - * @param irq_num Interrupt to enable - */ -static inline void nvic_irq_enable(nvic_irq_num irq_num) { - if (irq_num < 0) { - return; - } - NVIC_BASE->ISER[irq_num / 32] = BIT(irq_num % 32); -} - -/** - * @brief Disable interrupt irq_num - * @param irq_num Interrupt to disable - */ -static inline void nvic_irq_disable(nvic_irq_num irq_num) { - if (irq_num < 0) { - return; - } - NVIC_BASE->ICER[irq_num / 32] = BIT(irq_num % 32); -} - -/** - * @brief Quickly disable all interrupts. - * - * Calling this function is significantly faster than calling - * nvic_irq_disable() in a loop. - */ -static inline void nvic_irq_disable_all(void) { - /* Note: This only works up to XL density. The fix for - * connectivity line is: - * - * NVIC_BASE->ICER[2] = 0xF; - * - * We don't support connectivity line devices (yet), so leave it - * alone for now. - */ - NVIC_BASE->ICER[0] = 0xFFFFFFFF; - NVIC_BASE->ICER[1] = 0xFFFFFFFF; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/pwr.c b/libmaple/pwr.c index ead8b64..f934269 100644 --- a/libmaple/pwr.c +++ b/libmaple/pwr.c @@ -29,8 +29,8 @@ * @brief Power control (PWR) support. */ -#include "pwr.h" -#include "rcc.h" +#include +#include /** * Enables the power interface clock, and resets the power device. diff --git a/libmaple/pwr.h b/libmaple/pwr.h deleted file mode 100644 index 88b49c0..0000000 --- a/libmaple/pwr.h +++ /dev/null @@ -1,85 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file pwr.h - * @brief Power control (PWR) defines. - */ - -#include "libmaple.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Power interface register map. */ -typedef struct pwr_reg_map { - __io uint32 CR; /**< Control register */ - __io uint32 CSR; /**< Control and status register */ -} pwr_reg_map; - -/** Power peripheral register map base pointer. */ -#define PWR_BASE ((struct pwr_reg_map*)0x40007000) - -/* - * Register bit definitions - */ - -/* Control register */ - -/** Disable backup domain write protection bit */ -#define PWR_CR_DBP 8 -/** Power voltage detector enable bit */ -#define PWR_CR_PVDE 4 -/** Clear standby flag bit */ -#define PWR_CR_CSBF 3 -/** Clear wakeup flag bit */ -#define PWR_CR_CWUF 2 -/** Power down deepsleep bit */ -#define PWR_CR_PDDS 1 -/** Low-power deepsleep bit */ -#define PWR_CR_LPDS 0 - -/* Control and status register */ - -/** Enable wakeup pin bit */ -#define PWR_CSR_EWUP 8 -/** PVD output bit */ -#define PWR_CSR_PVDO 2 -/** Standby flag bit */ -#define PWR_CSR_SBF 1 -/** Wakeup flag bit */ -#define PWR_CSR_WUF 0 - -/* - * Convenience functions - */ - -void pwr_init(void); - -#ifdef __cplusplus -} -#endif diff --git a/libmaple/rcc.c b/libmaple/rcc.c index 65abfb6..ed3f11e 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -30,10 +30,10 @@ * stm32, clock enable/disable and peripheral reset commands. */ -#include "libmaple.h" -#include "flash.h" -#include "rcc.h" -#include "bitband.h" +#include +#include +#include +#include #define APB1 RCC_APB1 #define APB2 RCC_APB2 diff --git a/libmaple/rcc.h b/libmaple/rcc.h deleted file mode 100644 index c50686c..0000000 --- a/libmaple/rcc.h +++ /dev/null @@ -1,570 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file rcc.h - * @brief reset and clock control definitions and prototypes - */ - -#include "libmaple_types.h" - -#ifndef _RCC_H_ -#define _RCC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -/** RCC register map type */ -typedef struct rcc_reg_map { - __io uint32 CR; /**< Clock control register */ - __io uint32 CFGR; /**< Clock configuration register */ - __io uint32 CIR; /**< Clock interrupt register */ - __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ - __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ - __io uint32 AHBENR; /**< AHB peripheral clock enable register */ - __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ - __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ - __io uint32 BDCR; /**< Backup domain control register */ - __io uint32 CSR; /**< Control/status register */ -} rcc_reg_map; - -/** RCC register map base pointer */ -#define RCC_BASE ((struct rcc_reg_map*)0x40021000) - -/* - * Register bit definitions - */ - -/* Clock control register */ - -#define RCC_CR_PLLRDY_BIT 25 -#define RCC_CR_PLLON_BIT 24 -#define RCC_CR_CSSON_BIT 19 -#define RCC_CR_HSEBYP_BIT 18 -#define RCC_CR_HSERDY_BIT 17 -#define RCC_CR_HSEON_BIT 16 -#define RCC_CR_HSIRDY_BIT 1 -#define RCC_CR_HSION_BIT 0 - -#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) -#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) -#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) -#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) -#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) -#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) -#define RCC_CR_HSICAL (0xFF << 8) -#define RCC_CR_HSITRIM (0x1F << 3) -#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) -#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) - -/* Clock configuration register */ - -#define RCC_CFGR_USBPRE_BIT 22 -#define RCC_CFGR_PLLXTPRE_BIT 17 -#define RCC_CFGR_PLLSRC_BIT 16 - -#define RCC_CFGR_MCO (0x3 << 24) -#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) -#define RCC_CFGR_PLLMUL (0xF << 18) -#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) -#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) -#define RCC_CFGR_ADCPRE (0x3 << 14) -#define RCC_CFGR_PPRE2 (0x7 << 11) -#define RCC_CFGR_PPRE1 (0x7 << 8) -#define RCC_CFGR_HPRE (0xF << 4) -#define RCC_CFGR_SWS (0x3 << 2) -#define RCC_CFGR_SWS_PLL (0x2 << 2) -#define RCC_CFGR_SWS_HSE (0x1 << 2) -#define RCC_CFGR_SW 0x3 -#define RCC_CFGR_SW_PLL 0x2 -#define RCC_CFGR_SW_HSE 0x1 - -/* Clock interrupt register */ - -#define RCC_CIR_CSSC_BIT 23 -#define RCC_CIR_PLLRDYC_BIT 20 -#define RCC_CIR_HSERDYC_BIT 19 -#define RCC_CIR_HSIRDYC_BIT 18 -#define RCC_CIR_LSERDYC_BIT 17 -#define RCC_CIR_LSIRDYC_BIT 16 -#define RCC_CIR_PLLRDYIE_BIT 12 -#define RCC_CIR_HSERDYIE_BIT 11 -#define RCC_CIR_HSIRDYIE_BIT 10 -#define RCC_CIR_LSERDYIE_BIT 9 -#define RCC_CIR_LSIRDYIE_BIT 8 -#define RCC_CIR_CSSF_BIT 7 -#define RCC_CIR_PLLRDYF_BIT 4 -#define RCC_CIR_HSERDYF_BIT 3 -#define RCC_CIR_HSIRDYF_BIT 2 -#define RCC_CIR_LSERDYF_BIT 1 -#define RCC_CIR_LSIRDYF_BIT 0 - -#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) -#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) -#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) -#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) -#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) -#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) -#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) -#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) -#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) -#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) -#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) -#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) -#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) -#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) -#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) -#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) -#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) - -/* APB2 peripheral reset register */ - -#define RCC_APB2RSTR_TIM11RST_BIT 21 -#define RCC_APB2RSTR_TIM10RST_BIT 20 -#define RCC_APB2RSTR_TIM9RST_BIT 19 -#define RCC_APB2RSTR_ADC3RST_BIT 15 -#define RCC_APB2RSTR_USART1RST_BIT 14 -#define RCC_APB2RSTR_TIM8RST_BIT 13 -#define RCC_APB2RSTR_SPI1RST_BIT 12 -#define RCC_APB2RSTR_TIM1RST_BIT 11 -#define RCC_APB2RSTR_ADC2RST_BIT 10 -#define RCC_APB2RSTR_ADC1RST_BIT 9 -#define RCC_APB2RSTR_IOPGRST_BIT 8 -#define RCC_APB2RSTR_IOPFRST_BIT 7 -#define RCC_APB2RSTR_IOPERST_BIT 6 -#define RCC_APB2RSTR_IOPDRST_BIT 5 -#define RCC_APB2RSTR_IOPCRST_BIT 4 -#define RCC_APB2RSTR_IOPBRST_BIT 3 -#define RCC_APB2RSTR_IOPARST_BIT 2 -#define RCC_APB2RSTR_AFIORST_BIT 0 - -#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) -#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) -#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) -#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) -#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) -#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) -#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) -#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) -#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) -#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) -#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) -#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) -#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) -#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) -#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) -#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) -#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) -#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) - -/* APB1 peripheral reset register */ - -#define RCC_APB1RSTR_DACRST_BIT 29 -#define RCC_APB1RSTR_PWRRST_BIT 28 -#define RCC_APB1RSTR_BKPRST_BIT 27 -#define RCC_APB1RSTR_CANRST_BIT 25 -#define RCC_APB1RSTR_USBRST_BIT 23 -#define RCC_APB1RSTR_I2C2RST_BIT 22 -#define RCC_APB1RSTR_I2C1RST_BIT 21 -#define RCC_APB1RSTR_UART5RST_BIT 20 -#define RCC_APB1RSTR_UART4RST_BIT 19 -#define RCC_APB1RSTR_USART3RST_BIT 18 -#define RCC_APB1RSTR_USART2RST_BIT 17 -#define RCC_APB1RSTR_SPI3RST_BIT 15 -#define RCC_APB1RSTR_SPI2RST_BIT 14 -#define RCC_APB1RSTR_WWDRST_BIT 11 -#define RCC_APB1RSTR_TIM14RST_BIT 8 -#define RCC_APB1RSTR_TIM13RST_BIT 7 -#define RCC_APB1RSTR_TIM12RST_BIT 6 -#define RCC_APB1RSTR_TIM7RST_BIT 5 -#define RCC_APB1RSTR_TIM6RST_BIT 4 -#define RCC_APB1RSTR_TIM5RST_BIT 3 -#define RCC_APB1RSTR_TIM4RST_BIT 2 -#define RCC_APB1RSTR_TIM3RST_BIT 1 -#define RCC_APB1RSTR_TIM2RST_BIT 0 - -#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) -#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) -#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) -#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) -#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) -#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) -#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) -#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) -#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) -#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) -#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) -#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) -#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) -#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) -#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) -#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) -#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) -#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) -#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) -#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) -#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) -#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) -#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) - -/* AHB peripheral clock enable register */ - -#define RCC_AHBENR_SDIOEN_BIT 10 -#define RCC_AHBENR_FSMCEN_BIT 8 -#define RCC_AHBENR_CRCEN_BIT 7 -#define RCC_AHBENR_FLITFEN_BIT 4 -#define RCC_AHBENR_SRAMEN_BIT 2 -#define RCC_AHBENR_DMA2EN_BIT 1 -#define RCC_AHBENR_DMA1EN_BIT 0 - -#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) -#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) -#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) -#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) -#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) -#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) -#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) - -/* APB2 peripheral clock enable register */ - -#define RCC_APB2ENR_TIM11EN_BIT 21 -#define RCC_APB2ENR_TIM10EN_BIT 20 -#define RCC_APB2ENR_TIM9EN_BIT 19 -#define RCC_APB2ENR_ADC3EN_BIT 15 -#define RCC_APB2ENR_USART1EN_BIT 14 -#define RCC_APB2ENR_TIM8EN_BIT 13 -#define RCC_APB2ENR_SPI1EN_BIT 12 -#define RCC_APB2ENR_TIM1EN_BIT 11 -#define RCC_APB2ENR_ADC2EN_BIT 10 -#define RCC_APB2ENR_ADC1EN_BIT 9 -#define RCC_APB2ENR_IOPGEN_BIT 8 -#define RCC_APB2ENR_IOPFEN_BIT 7 -#define RCC_APB2ENR_IOPEEN_BIT 6 -#define RCC_APB2ENR_IOPDEN_BIT 5 -#define RCC_APB2ENR_IOPCEN_BIT 4 -#define RCC_APB2ENR_IOPBEN_BIT 3 -#define RCC_APB2ENR_IOPAEN_BIT 2 -#define RCC_APB2ENR_AFIOEN_BIT 0 - -#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) -#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) -#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) -#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) -#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) -#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) -#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) -#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) -#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) -#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) -#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) -#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) -#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) -#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) -#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) -#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) -#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) -#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) - -/* APB1 peripheral clock enable register */ - -#define RCC_APB1ENR_DACEN_BIT 29 -#define RCC_APB1ENR_PWREN_BIT 28 -#define RCC_APB1ENR_BKPEN_BIT 27 -#define RCC_APB1ENR_CANEN_BIT 25 -#define RCC_APB1ENR_USBEN_BIT 23 -#define RCC_APB1ENR_I2C2EN_BIT 22 -#define RCC_APB1ENR_I2C1EN_BIT 21 -#define RCC_APB1ENR_UART5EN_BIT 20 -#define RCC_APB1ENR_UART4EN_BIT 19 -#define RCC_APB1ENR_USART3EN_BIT 18 -#define RCC_APB1ENR_USART2EN_BIT 17 -#define RCC_APB1ENR_SPI3EN_BIT 15 -#define RCC_APB1ENR_SPI2EN_BIT 14 -#define RCC_APB1ENR_WWDEN_BIT 11 -#define RCC_APB1ENR_TIM14EN_BIT 8 -#define RCC_APB1ENR_TIM13EN_BIT 7 -#define RCC_APB1ENR_TIM12EN_BIT 6 -#define RCC_APB1ENR_TIM7EN_BIT 5 -#define RCC_APB1ENR_TIM6EN_BIT 4 -#define RCC_APB1ENR_TIM5EN_BIT 3 -#define RCC_APB1ENR_TIM4EN_BIT 2 -#define RCC_APB1ENR_TIM3EN_BIT 1 -#define RCC_APB1ENR_TIM2EN_BIT 0 - -#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) -#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) -#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) -#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) -#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) -#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) -#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) -#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) -#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) -#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) -#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) -#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) -#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) -#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) -#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) -#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) -#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) -#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) -#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) -#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) -#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) -#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) -#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) - -/* Backup domain control register */ - -#define RCC_BDCR_BDRST_BIT 16 -#define RCC_BDCR_RTCEN_BIT 15 -#define RCC_BDCR_LSEBYP_BIT 2 -#define RCC_BDCR_LSERDY_BIT 1 -#define RCC_BDCR_LSEON_BIT 0 - -#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) -#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) -#define RCC_BDCR_RTCSEL (0x3 << 8) -#define RCC_BDCR_RTCSEL_NONE (0x0 << 8) -#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) -#define RCC_BDCR_RTCSEL_HSE (0x3 << 8) -#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) -#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) -#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) - -/* Control/status register */ - -#define RCC_CSR_LPWRRSTF_BIT 31 -#define RCC_CSR_WWDGRSTF_BIT 30 -#define RCC_CSR_IWDGRSTF_BIT 29 -#define RCC_CSR_SFTRSTF_BIT 28 -#define RCC_CSR_PORRSTF_BIT 27 -#define RCC_CSR_PINRSTF_BIT 26 -#define RCC_CSR_RMVF_BIT 24 -#define RCC_CSR_LSIRDY_BIT 1 -#define RCC_CSR_LSION_BIT 0 - -#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) -#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) -#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) -#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) -#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) -#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) -#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) -#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) -#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) - -/* - * Convenience routines - */ - -/** - * SYSCLK sources - * @see rcc_clk_init() - */ -typedef enum rcc_sysclk_src { - RCC_CLKSRC_HSI = 0x0, - RCC_CLKSRC_HSE = 0x1, - RCC_CLKSRC_PLL = 0x2, -} rcc_sysclk_src; - -/** - * PLL entry clock source - * @see rcc_clk_init() - */ -typedef enum rcc_pllsrc { - RCC_PLLSRC_HSE = (0x1 << 16), - RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) -} rcc_pllsrc; - -/** - * PLL multipliers - * @see rcc_clk_init() - */ -typedef enum rcc_pll_multiplier { - RCC_PLLMUL_2 = (0x0 << 18), - RCC_PLLMUL_3 = (0x1 << 18), - RCC_PLLMUL_4 = (0x2 << 18), - RCC_PLLMUL_5 = (0x3 << 18), - RCC_PLLMUL_6 = (0x4 << 18), - RCC_PLLMUL_7 = (0x5 << 18), - RCC_PLLMUL_8 = (0x6 << 18), - RCC_PLLMUL_9 = (0x7 << 18), - RCC_PLLMUL_10 = (0x8 << 18), - RCC_PLLMUL_11 = (0x9 << 18), - RCC_PLLMUL_12 = (0xA << 18), - RCC_PLLMUL_13 = (0xB << 18), - RCC_PLLMUL_14 = (0xC << 18), - RCC_PLLMUL_15 = (0xD << 18), - RCC_PLLMUL_16 = (0xE << 18), -} rcc_pll_multiplier; - -/** - * @brief Identifies bus and clock line for a peripheral. - * - * Also generally useful as a unique identifier for that peripheral - * (or its corresponding device struct). - */ -typedef enum rcc_clk_id { - RCC_GPIOA, - RCC_GPIOB, - RCC_GPIOC, - RCC_GPIOD, - RCC_AFIO, - RCC_ADC1, - RCC_ADC2, - RCC_ADC3, - RCC_USART1, - RCC_USART2, - RCC_USART3, - RCC_TIMER1, - RCC_TIMER2, - RCC_TIMER3, - RCC_TIMER4, - RCC_SPI1, - RCC_SPI2, - RCC_DMA1, - RCC_PWR, - RCC_BKP, - RCC_I2C1, - RCC_I2C2, - RCC_CRC, - RCC_FLITF, - RCC_SRAM, - RCC_USB, -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) - RCC_GPIOE, - RCC_GPIOF, - RCC_GPIOG, - RCC_UART4, - RCC_UART5, - RCC_TIMER5, - RCC_TIMER6, - RCC_TIMER7, - RCC_TIMER8, - RCC_FSMC, - RCC_DAC, - RCC_DMA2, - RCC_SDIO, - RCC_SPI3, -#endif -#ifdef STM32_XL_DENSITY - RCC_TIMER9, - RCC_TIMER10, - RCC_TIMER11, - RCC_TIMER12, - RCC_TIMER13, - RCC_TIMER14, -#endif -} rcc_clk_id; - -void rcc_clk_init(rcc_sysclk_src sysclk_src, - rcc_pllsrc pll_src, - rcc_pll_multiplier pll_mul); -void rcc_clk_enable(rcc_clk_id device); -void rcc_reset_dev(rcc_clk_id device); - -typedef enum rcc_clk_domain { - RCC_APB1, - RCC_APB2, - RCC_AHB -} rcc_clk_domain; - -rcc_clk_domain rcc_dev_clk(rcc_clk_id device); - -/** - * Prescaler identifiers - * @see rcc_set_prescaler() - */ -typedef enum rcc_prescaler { - RCC_PRESCALER_AHB, - RCC_PRESCALER_APB1, - RCC_PRESCALER_APB2, - RCC_PRESCALER_USB, - RCC_PRESCALER_ADC -} rcc_prescaler; - -/** - * ADC prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_adc_divider { - RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14, - RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14, - RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14, - RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14, -} rcc_adc_divider; - -/** - * APB1 prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_apb1_divider { - RCC_APB1_HCLK_DIV_1 = 0x0 << 8, - RCC_APB1_HCLK_DIV_2 = 0x4 << 8, - RCC_APB1_HCLK_DIV_4 = 0x5 << 8, - RCC_APB1_HCLK_DIV_8 = 0x6 << 8, - RCC_APB1_HCLK_DIV_16 = 0x7 << 8, -} rcc_apb1_divider; - -/** - * APB2 prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_apb2_divider { - RCC_APB2_HCLK_DIV_1 = 0x0 << 11, - RCC_APB2_HCLK_DIV_2 = 0x4 << 11, - RCC_APB2_HCLK_DIV_4 = 0x5 << 11, - RCC_APB2_HCLK_DIV_8 = 0x6 << 11, - RCC_APB2_HCLK_DIV_16 = 0x7 << 11, -} rcc_apb2_divider; - -/** - * AHB prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_ahb_divider { - RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4, - RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4, - RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4, - RCC_AHB_SYSCLK_DIV_8 = 0xA << 4, - RCC_AHB_SYSCLK_DIV_16 = 0xB << 4, - RCC_AHB_SYSCLK_DIV_32 = 0xC << 4, - RCC_AHB_SYSCLK_DIV_64 = 0xD << 4, - RCC_AHB_SYSCLK_DIV_128 = 0xD << 4, - RCC_AHB_SYSCLK_DIV_256 = 0xE << 4, - RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, -} rcc_ahb_divider; - -void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/ring_buffer.h b/libmaple/ring_buffer.h deleted file mode 100644 index c443bc3..0000000 --- a/libmaple/ring_buffer.h +++ /dev/null @@ -1,189 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file ring_buffer.h - * @brief Simple circular buffer - * - * This implementation is not thread-safe. In particular, none of - * these functions is guaranteed re-entrant. - */ - -#ifndef _RING_BUFFER_H_ -#define _RING_BUFFER_H_ - -#include "libmaple_types.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/** - * Ring buffer type. - * - * The buffer is empty when head == tail. - * - * The buffer is full when the head is one byte in front of the tail, - * modulo buffer length. - * - * One byte is left free to distinguish empty from full. */ -typedef struct ring_buffer { - volatile uint8 *buf; /**< Buffer items are stored into */ - uint16 head; /**< Index of the next item to remove */ - uint16 tail; /**< Index where the next item will get inserted */ - uint16 size; /**< Buffer capacity minus one */ -} ring_buffer; - -/** - * Initialise a ring buffer. - * - * @param rb Instance to initialise - * - * @param size Number of items in buf. The ring buffer will always - * leave one element unoccupied, so the maximum number of - * elements it can store will be size - 1. Thus, size - * must be at least 2. - * - * @param buf Buffer to store items into - */ -static inline void rb_init(ring_buffer *rb, uint16 size, uint8 *buf) { - rb->head = 0; - rb->tail = 0; - rb->size = size - 1; - rb->buf = buf; -} - -/** - * @brief Return the number of elements stored in the ring buffer. - * @param rb Buffer whose elements to count. - */ -static inline uint16 rb_full_count(ring_buffer *rb) { - __io ring_buffer *arb = rb; - int32 size = arb->tail - arb->head; - if (arb->tail < arb->head) { - size += arb->size + 1; - } - return (uint16)size; -} - -/** - * @brief Returns true if and only if the ring buffer is full. - * @param rb Buffer to test. - */ -static inline int rb_is_full(ring_buffer *rb) { - return (rb->tail + 1 == rb->head) || - (rb->tail == rb->size && rb->head == 0); -} - -/** - * @brief Returns true if and only if the ring buffer is empty. - * @param rb Buffer to test. - */ -static inline int rb_is_empty(ring_buffer *rb) { - return rb->head == rb->tail; -} - -/** - * Append element onto the end of a ring buffer. - * @param rb Buffer to append onto. - * @param element Value to append. - */ -static inline void rb_insert(ring_buffer *rb, uint8 element) { - rb->buf[rb->tail] = element; - rb->tail = (rb->tail == rb->size) ? 0 : rb->tail + 1; -} - -/** - * @brief Remove and return the first item from a ring buffer. - * @param rb Buffer to remove from, must contain at least one element. - */ -static inline uint8 rb_remove(ring_buffer *rb) { - uint8 ch = rb->buf[rb->head]; - rb->head = (rb->head == rb->size) ? 0 : rb->head + 1; - return ch; -} - -/** - * @brief Attempt to remove the first item from a ring buffer. - * - * If the ring buffer is nonempty, removes and returns its first item. - * If it is empty, does nothing and returns a negative value. - * - * @param rb Buffer to attempt to remove from. - */ -static inline int16 rb_safe_remove(ring_buffer *rb) { - return rb_is_empty(rb) ? -1 : rb_remove(rb); -} - -/** - * @brief Attempt to insert an element into a ring buffer. - * - * @param rb Buffer to insert into. - * @param element Value to insert into rb. - * @sideeffect If rb is not full, appends element onto buffer. - * @return If element was appended, then true; otherwise, false. */ -static inline int rb_safe_insert(ring_buffer *rb, uint8 element) { - if (rb_is_full(rb)) { - return 0; - } - rb_insert(rb, element); - return 1; -} - -/** - * @brief Append an item onto the end of a non-full ring buffer. - * - * If the buffer is full, removes its first item, then inserts the new - * element at the end. - * - * @param rb Ring buffer to insert into. - * @param element Value to insert into ring buffer. - * @return On success, returns -1. If an element was popped, returns - * the popped value. - */ -static inline int rb_push_insert(ring_buffer *rb, uint8 element) { - int ret = -1; - if (rb_is_full(rb)) { - ret = rb_remove(rb); - } - rb_insert(rb, element); - return ret; -} - -/** - * @brief Discard all items from a ring buffer. - * @param rb Ring buffer to discard all items from. - */ -static inline void rb_reset(ring_buffer *rb) { - rb->tail = rb->head; -} - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif - diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 1ee611d..a6b330a 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -6,10 +6,13 @@ BUILDDIRS += $(BUILD_PATH)/$(d) BUILDDIRS += $(BUILD_PATH)/$(d)/usb BUILDDIRS += $(BUILD_PATH)/$(d)/usb/usb_lib -LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usb -I$(LIBMAPLE_PATH)/usb/usb_lib +LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include +# FIXME: move public USB headers to include/libmaple/usb/ or something. +LIBMAPLE_INCLUDES += -I$(LIBMAPLE_PATH)/usb \ + -I$(LIBMAPLE_PATH)/usb/usb_lib # Local flags -CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror +CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall # -Werror # Local rules and targets cSRCS_$(d) := adc.c \ diff --git a/libmaple/scb.h b/libmaple/scb.h deleted file mode 100644 index feacaa5..0000000 --- a/libmaple/scb.h +++ /dev/null @@ -1,201 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file scb.h - * @brief System control block header - */ - -#include "libmaple_types.h" - -#ifndef _SCB_H_ -#define _SCB_H_ - -/* - * Register map and base pointer - */ - -/** System control block register map type */ -typedef struct scb_reg_map { - __io uint32 CPUID; /**< CPU ID Base Register */ - __io uint32 ICSR; /**< Interrupt Control State Register */ - __io uint32 VTOR; /**< Vector Table Offset Register */ - __io uint32 AIRCR; /**< Application Interrupt / Reset Control Register */ - __io uint32 SCR; /**< System Control Register */ - __io uint32 CCR; /**< Configuration and Control Register */ - __io uint8 SHP[12]; /**< System Handler Priority Registers - (4-7, 8-11, 12-15) */ - __io uint32 SHCSR; /**< System Handler Control and State Register */ - __io uint32 CFSR; /**< Configurable Fault Status Register */ - __io uint32 HFSR; /**< Hard Fault Status Register */ - /* DFSR is not documented by ST in PM0056 (as of Revision 4), but - * there's a 4 byte hole in the SCB register map docs right where - * it belongs. Since it's specified as "always implemented" in - * the ARM v7-M ARM, I'm assuming its absence is a bug in the ST - * doc, but I haven't proven it. [mbolivar] */ - __io uint32 DFSR; /**< Debug Fault Status Register */ - __io uint32 MMFAR; /**< Mem Manage Address Register */ - __io uint32 BFAR; /**< Bus Fault Address Register */ -#if 0 - /* The following registers are implementation-defined according to - * ARM v7-M, and I can't find evidence of their existence in ST's - * docs. I'm removing them. Feel free to yell at me if they do - * exist. [mbolivar] - */ - __io uint32 AFSR; /**< Auxiliary Fault Status Register */ - __io uint32 PFR[2]; /**< Processor Feature Register */ - __io uint32 DFR; /**< Debug Feature Register */ - __io uint32 AFR; /**< Auxiliary Feature Register */ - __io uint32 MMFR[4]; /**< Memory Model Feature Register */ - __io uint32 ISAR[5]; /**< ISA Feature Register */ -#endif -} scb_reg_map; - -/** System control block register map base pointer */ -#define SCB_BASE ((struct scb_reg_map*)0xE000ED00) - -/* - * Register bit definitions - */ - -/* No SCB_REG_FIELD_BIT macros as the relevant addresses are not in a - * bit-band region. */ - -/* CPUID base register (SCB_CPUID) */ - -#define SCB_CPUID_IMPLEMENTER (0xFF << 24) -#define SCB_CPUID_VARIANT (0xF << 20) -#define SCB_CPUID_CONSTANT (0xF << 16) -#define SCB_CPUID_PARTNO (0xFFF << 4) -#define SCB_CPUID_REVISION 0xF - -/* Interrupt control state register (SCB_ICSR) */ - -#define SCB_ICSR_NMIPENDSET BIT(31) -#define SCB_ICSR_PENDSVSET BIT(28) -#define SCB_ICSR_PENDSVCLR BIT(27) -#define SCB_ICSR_PENDSTSET BIT(26) -#define SCB_ICSR_PENDSTCLR BIT(25) -#define SCB_ICSR_ISRPENDING BIT(22) -#define SCB_ICSR_VECTPENDING (0x3FF << 12) -#define SCB_ICSR_RETOBASE BIT(11) -#define SCB_ICSR_VECTACTIVE 0xFF - -/* Vector table offset register (SCB_VTOR) */ - -#define SCB_VTOR_TBLOFF (0x1FFFFF << 9) - -/* Application interrupt and reset control register (SCB_AIRCR) */ - -#define SCB_AIRCR_VECTKEYSTAT (0x5FA << 16) -#define SCB_AIRCR_VECTKEY (0x5FA << 16) -#define SCB_AIRCR_ENDIANNESS BIT(15) -#define SCB_AIRCR_PRIGROUP (0x3 << 8) -#define SCB_AIRCR_SYSRESETREQ BIT(2) -#define SCB_AIRCR_VECTCLRACTIVE BIT(1) -#define SCB_AIRCR_VECTRESET BIT(0) - -/* System control register (SCB_SCR) */ - -#define SCB_SCR_SEVONPEND BIT(4) -#define SCB_SCR_SLEEPDEEP BIT(2) -#define SCB_SCR_SLEEPONEXIT BIT(1) - -/* Configuration and Control Register (SCB_CCR) */ - -#define SCB_CCR_STKALIGN BIT(9) -#define SCB_CCR_BFHFNMIGN BIT(8) -#define SCB_CCR_DIV_0_TRP BIT(4) -#define SCB_CCR_UNALIGN_TRP BIT(3) -#define SCB_CCR_USERSETMPEND BIT(1) -#define SCB_CCR_NONBASETHRDENA BIT(0) - -/* System handler priority registers (SCB_SHPRx) */ - -#define SCB_SHPR1_PRI6 (0xFF << 16) -#define SCB_SHPR1_PRI5 (0xFF << 8) -#define SCB_SHPR1_PRI4 0xFF - -#define SCB_SHPR2_PRI11 (0xFF << 24) - -#define SCB_SHPR3_PRI15 (0xFF << 24) -#define SCB_SHPR3_PRI14 (0xFF << 16) - -/* System Handler Control and state register (SCB_SHCSR) */ - -#define SCB_SHCSR_USGFAULTENA BIT(18) -#define SCB_SHCSR_BUSFAULTENA BIT(17) -#define SCB_SHCSR_MEMFAULTENA BIT(16) -#define SCB_SHCSR_SVCALLPENDED BIT(15) -#define SCB_SHCSR_BUSFAULTPENDED BIT(14) -#define SCB_SHCSR_MEMFAULTPENDED BIT(13) -#define SCB_SHCSR_USGFAULTPENDED BIT(12) -#define SCB_SHCSR_SYSTICKACT BIT(11) -#define SCB_SHCSR_PENDSVACT BIT(10) -#define SCB_SHCSR_MONITORACT BIT(8) -#define SCB_SHCSR_SVCALLACT BIT(7) -#define SCB_SHCSR_USGFAULTACT BIT(3) -#define SCB_SHCSR_BUSFAULTACT BIT(1) -#define SCB_SHCSR_MEMFAULTACT BIT(0) - -/* Configurable fault status register (SCB_CFSR) */ - -#define SCB_CFSR_DIVBYZERO BIT(25) -#define SCB_CFSR_UNALIGNED BIT(24) -#define SCB_CFSR_NOCP BIT(19) -#define SCB_CFSR_INVPC BIT(18) -#define SCB_CFSR_INVSTATE BIT(17) -#define SCB_CFSR_UNDEFINSTR BIT(16) -#define SCB_CFSR_BFARVALID BIT(15) -#define SCB_CFSR_STKERR BIT(12) -#define SCB_CFSR_UNSTKERR BIT(11) -#define SCB_CFSR_IMPRECISERR BIT(10) -#define SCB_CFSR_PRECISERR BIT(9) -#define SCB_CFSR_IBUSERR BIT(8) -#define SCB_CFSR_MMARVALID BIT(7) -#define SCB_CFSR_MSTKERR BIT(4) -#define SCB_CFSR_MUNSTKERR BIT(3) -#define SCB_CFSR_DACCVIOL BIT(1) -#define SCB_CFSR_IACCVIOL BIT(0) - -/* Hard Fault Status Register (SCB_HFSR) */ - -#define SCB_HFSR_DEBUG_VT BIT(31) -#define SCB_CFSR_FORCED BIT(30) -#define SCB_CFSR_VECTTBL BIT(1) - -/* Debug Fault Status Register */ - -/* Not specified by PM0056, but required by ARM. The bit definitions - * here are based on the names given in the ARM v7-M ARM. */ - -#define SCB_DFSR_EXTERNAL BIT(4) -#define SCB_DFSR_VCATCH BIT(3) -#define SCB_DFSR_DWTTRAP BIT(2) -#define SCB_DFSR_BKPT BIT(1) -#define SCB_DFSR_HALTED BIT(0) - -#endif diff --git a/libmaple/spi.c b/libmaple/spi.c index 1c68529..d0aaaf0 100644 --- a/libmaple/spi.c +++ b/libmaple/spi.c @@ -31,8 +31,8 @@ * Currently, there is no Integrated Interchip Sound (I2S) support. */ -#include "spi.h" -#include "bitband.h" +#include +#include static void spi_reconfigure(spi_dev *dev, uint32 cr1_config); diff --git a/libmaple/spi.h b/libmaple/spi.h deleted file mode 100644 index f4fa4b7..0000000 --- a/libmaple/spi.h +++ /dev/null @@ -1,456 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file spi.h - * @author Marti Bolivar - * @brief Serial Peripheral Interface (SPI) and Integrated - * Interchip Sound (I2S) peripheral support. - * - * I2S support is currently limited to register maps and bit definitions. - */ - -#ifndef _SPI_H_ -#define _SPI_H_ - -#include "libmaple_types.h" -#include "rcc.h" -#include "nvic.h" -#include "gpio.h" -#include "util.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Register maps - */ - -/** SPI register map type. */ -typedef struct spi_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 SR; /**< Status register */ - __io uint32 DR; /**< Data register */ - __io uint32 CRCPR; /**< CRC polynomial register */ - __io uint32 RXCRCR; /**< RX CRC register */ - __io uint32 TXCRCR; /**< TX CRC register */ - __io uint32 I2SCFGR; /**< I2S configuration register */ - __io uint32 I2SPR; /**< I2S prescaler register */ -} spi_reg_map; - -/** SPI1 register map base pointer */ -#define SPI1_BASE ((struct spi_reg_map*)0x40013000) -/** SPI2 register map base pointer */ -#define SPI2_BASE ((struct spi_reg_map*)0x40003800) -/** SPI3 register map base pointer */ -#define SPI3_BASE ((struct spi_reg_map*)0x40003C00) - -/* - * Register bit definitions - */ - -/* Control register 1 */ - -#define SPI_CR1_BIDIMODE_BIT 15 -#define SPI_CR1_BIDIOE_BIT 14 -#define SPI_CR1_CRCEN_BIT 13 -#define SPI_CR1_CRCNEXT_BIT 12 -#define SPI_CR1_DFF_BIT 11 -#define SPI_CR1_RXONLY_BIT 10 -#define SPI_CR1_SSM_BIT 9 -#define SPI_CR1_SSI_BIT 8 -#define SPI_CR1_LSBFIRST_BIT 7 -#define SPI_CR1_SPE_BIT 6 -#define SPI_CR1_MSTR_BIT 2 -#define SPI_CR1_CPOL_BIT 1 -#define SPI_CR1_CPHA_BIT 0 - -#define SPI_CR1_BIDIMODE BIT(SPI_CR1_BIDIMODE_BIT) -#define SPI_CR1_BIDIMODE_2_LINE (0x0 << SPI_CR1_BIDIMODE_BIT) -#define SPI_CR1_BIDIMODE_1_LINE (0x1 << SPI_CR1_BIDIMODE_BIT) -#define SPI_CR1_BIDIOE BIT(SPI_CR1_BIDIOE_BIT) -#define SPI_CR1_CRCEN BIT(SPI_CR1_CRCEN_BIT) -#define SPI_CR1_CRCNEXT BIT(SPI_CR1_CRCNEXT_BIT) -#define SPI_CR1_DFF BIT(SPI_CR1_DFF_BIT) -#define SPI_CR1_DFF_8_BIT (0x0 << SPI_CR1_DFF_BIT) -#define SPI_CR1_DFF_16_BIT (0x1 << SPI_CR1_DFF_BIT) -#define SPI_CR1_RXONLY BIT(SPI_CR1_RXONLY_BIT) -#define SPI_CR1_SSM BIT(SPI_CR1_SSM_BIT) -#define SPI_CR1_SSI BIT(SPI_CR1_SSI_BIT) -#define SPI_CR1_LSBFIRST BIT(SPI_CR1_LSBFIRST_BIT) -#define SPI_CR1_SPE BIT(SPI_CR1_SPE_BIT) -#define SPI_CR1_BR (0x7 << 3) -#define SPI_CR1_BR_PCLK_DIV_2 (0x0 << 3) -#define SPI_CR1_BR_PCLK_DIV_4 (0x1 << 3) -#define SPI_CR1_BR_PCLK_DIV_8 (0x2 << 3) -#define SPI_CR1_BR_PCLK_DIV_16 (0x3 << 3) -#define SPI_CR1_BR_PCLK_DIV_32 (0x4 << 3) -#define SPI_CR1_BR_PCLK_DIV_64 (0x5 << 3) -#define SPI_CR1_BR_PCLK_DIV_128 (0x6 << 3) -#define SPI_CR1_BR_PCLK_DIV_256 (0x7 << 3) -#define SPI_CR1_MSTR BIT(SPI_CR1_MSTR_BIT) -#define SPI_CR1_CPOL BIT(SPI_CR1_CPOL_BIT) -#define SPI_CR1_CPOL_LOW (0x0 << SPI_CR1_CPOL_BIT) -#define SPI_CR1_CPOL_HIGH (0x1 << SPI_CR1_CPOL_BIT) -#define SPI_CR1_CPHA BIT(SPI_CR1_CPHA_BIT) - -/* Control register 2 */ - -/* RM0008-ism: SPI CR2 has "TXDMAEN" and "RXDMAEN" bits, while the - * USARTs have CR3 "DMAR" and "DMAT" bits. */ - -#define SPI_CR2_TXEIE_BIT 7 -#define SPI_CR2_RXNEIE_BIT 6 -#define SPI_CR2_ERRIE_BIT 5 -#define SPI_CR2_SSOE_BIT 2 -#define SPI_CR2_TXDMAEN_BIT 1 -#define SPI_CR2_RXDMAEN_BIT 0 - -#define SPI_CR2_TXEIE BIT(SPI_CR2_TXEIE_BIT) -#define SPI_CR2_RXNEIE BIT(SPI_CR2_RXNEIE_BIT) -#define SPI_CR2_ERRIE BIT(SPI_CR2_ERRIE_BIT) -#define SPI_CR2_SSOE BIT(SPI_CR2_SSOE_BIT) -#define SPI_CR2_TXDMAEN BIT(SPI_CR2_TXDMAEN_BIT) -#define SPI_CR2_RXDMAEN BIT(SPI_CR2_RXDMAEN_BIT) - -/* Status register */ - -#define SPI_SR_BSY_BIT 7 -#define SPI_SR_OVR_BIT 6 -#define SPI_SR_MODF_BIT 5 -#define SPI_SR_CRCERR_BIT 4 -#define SPI_SR_UDR_BIT 3 -#define SPI_SR_CHSIDE_BIT 2 -#define SPI_SR_TXE_BIT 1 -#define SPI_SR_RXNE_BIT 0 - -#define SPI_SR_BSY BIT(SPI_SR_BSY_BIT) -#define SPI_SR_OVR BIT(SPI_SR_OVR_BIT) -#define SPI_SR_MODF BIT(SPI_SR_MODF_BIT) -#define SPI_SR_CRCERR BIT(SPI_SR_CRCERR_BIT) -#define SPI_SR_UDR BIT(SPI_SR_UDR_BIT) -#define SPI_SR_CHSIDE BIT(SPI_SR_CHSIDE_BIT) -#define SPI_SR_CHSIDE_LEFT (0x0 << SPI_SR_CHSIDE_BIT) -#define SPI_SR_CHSIDE_RIGHT (0x1 << SPI_SR_CHSIDE_BIT) -#define SPI_SR_TXE BIT(SPI_SR_TXE_BIT) -#define SPI_SR_RXNE BIT(SPI_SR_RXNE_BIT) - -/* I2S configuration register */ - -/* RM0008-ism: CR1 has "CPOL", I2SCFGR has "CKPOL". */ - -#define SPI_I2SCFGR_I2SMOD_BIT 11 -#define SPI_I2SCFGR_I2SE_BIT 10 -#define SPI_I2SCFGR_PCMSYNC_BIT 7 -#define SPI_I2SCFGR_CKPOL_BIT 3 -#define SPI_I2SCFGR_CHLEN_BIT 0 - -#define SPI_I2SCFGR_I2SMOD BIT(SPI_I2SCFGR_I2SMOD_BIT) -#define SPI_I2SCFGR_I2SMOD_SPI (0x0 << SPI_I2SCFGR_I2SMOD_BIT) -#define SPI_I2SCFGR_I2SMOD_I2S (0x1 << SPI_I2SCFGR_I2SMOD_BIT) -#define SPI_I2SCFGR_I2SE BIT(SPI_I2SCFGR_I2SE_BIT) -#define SPI_I2SCFGR_I2SCFG (0x3 << 8) -#define SPI_I2SCFGR_I2SCFG_SLAVE_TX (0x0 << 8) -#define SPI_I2SCFGR_I2SCFG_SLAVE_RX (0x1 << 8) -#define SPI_I2SCFGR_I2SCFG_MASTER_TX (0x2 << 8) -#define SPI_I2SCFGR_I2SCFG_MASTER_RX (0x3 << 8) -#define SPI_I2SCFGR_PCMSYNC BIT(SPI_I2SCFGR_PCMSYNC_BIT) -#define SPI_I2SCFGR_PCMSYNC_SHORT (0x0 << SPI_I2SCFGR_PCMSYNC_BIT) -#define SPI_I2SCFGR_PCMSYNC_LONG (0x1 << SPI_I2SCFGR_PCMSYNC_BIT) -#define SPI_I2SCFGR_I2SSTD (0x3 << 4) -#define SPI_I2SCFGR_I2SSTD_PHILLIPS (0x0 << 4) -#define SPI_I2SCFGR_I2SSTD_MSB (0x1 << 4) -#define SPI_I2SCFGR_I2SSTD_LSB (0x2 << 4) -#define SPI_I2SCFGR_I2SSTD_PCM (0x3 << 4) -#define SPI_I2SCFGR_CKPOL BIT(SPI_I2SCFGR_CKPOL_BIT) -#define SPI_I2SCFGR_CKPOL_LOW (0x0 << SPI_I2SCFGR_CKPOL_BIT) -#define SPI_I2SCFGR_CKPOL_HIGH (0x1 << SPI_I2SCFGR_CKPOL_BIT) -#define SPI_I2SCFGR_DATLEN (0x3 << 1) -#define SPI_I2SCFGR_DATLEN_16_BIT (0x0 << 1) -#define SPI_I2SCFGR_DATLEN_24_BIT (0x1 << 1) -#define SPI_I2SCFGR_DATLEN_32_BIT (0x2 << 1) -#define SPI_I2SCFGR_CHLEN BIT(SPI_I2SCFGR_CHLEN_BIT) -#define SPI_I2SCFGR_CHLEN_16_BIT (0x0 << SPI_I2SCFGR_CHLEN_BIT) -#define SPI_I2SCFGR_CHLEN_32_BIT (0x1 << SPI_I2SCFGR_CHLEN_BIT) - -/* - * Devices - */ - -/** SPI device type */ -typedef struct spi_dev { - spi_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ - nvic_irq_num irq_num; /**< NVIC interrupt number */ -} spi_dev; - -extern spi_dev *SPI1; -extern spi_dev *SPI2; -#ifdef STM32_HIGH_DENSITY -extern spi_dev *SPI3; -#endif - -/* - * SPI Convenience functions - */ - -void spi_init(spi_dev *dev); - -void spi_gpio_cfg(uint8 as_master, - gpio_dev *nss_dev, - uint8 nss_bit, - gpio_dev *comm_dev, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit); - -/** - * @brief SPI mode configuration. - * - * Determines a combination of clock polarity (CPOL), which determines - * idle state of the clock line, and clock phase (CPHA), which - * determines which clock edge triggers data capture. - */ -typedef enum spi_mode { - SPI_MODE_0, /**< Clock line idles low (0), data capture on first - clock transition. */ - SPI_MODE_1, /**< Clock line idles low (0), data capture on second - clock transition */ - SPI_MODE_2, /**< Clock line idles high (1), data capture on first - clock transition. */ - SPI_MODE_3 /**< Clock line idles high (1), data capture on - second clock transition. */ -} spi_mode; - -/** - * @brief SPI baud rate configuration, as a divisor of f_PCLK, the - * PCLK clock frequency. - */ -typedef enum spi_baud_rate { - SPI_BAUD_PCLK_DIV_2 = SPI_CR1_BR_PCLK_DIV_2, /**< f_PCLK/2 */ - SPI_BAUD_PCLK_DIV_4 = SPI_CR1_BR_PCLK_DIV_4, /**< f_PCLK/4 */ - SPI_BAUD_PCLK_DIV_8 = SPI_CR1_BR_PCLK_DIV_8, /**< f_PCLK/8 */ - SPI_BAUD_PCLK_DIV_16 = SPI_CR1_BR_PCLK_DIV_16, /**< f_PCLK/16 */ - SPI_BAUD_PCLK_DIV_32 = SPI_CR1_BR_PCLK_DIV_32, /**< f_PCLK/32 */ - SPI_BAUD_PCLK_DIV_64 = SPI_CR1_BR_PCLK_DIV_64, /**< f_PCLK/64 */ - SPI_BAUD_PCLK_DIV_128 = SPI_CR1_BR_PCLK_DIV_128, /**< f_PCLK/128 */ - SPI_BAUD_PCLK_DIV_256 = SPI_CR1_BR_PCLK_DIV_256, /**< f_PCLK/256 */ -} spi_baud_rate; - -/** - * @brief SPI initialization flags. - * @see spi_master_enable() - * @see spi_slave_enable() - */ -typedef enum spi_cfg_flag { - SPI_BIDIMODE = SPI_CR1_BIDIMODE, /**< Bidirectional mode enable */ - SPI_BIDIOE = SPI_CR1_BIDIOE, /**< Output enable in bidirectional - mode */ - SPI_CRCEN = SPI_CR1_CRCEN, /**< Cyclic redundancy check (CRC) - enable */ - SPI_DFF_8_BIT = SPI_CR1_DFF_8_BIT, /**< 8-bit data frame format (this is - the default) */ - SPI_DFF_16_BIT = SPI_CR1_DFF_16_BIT, /**< 16-bit data frame format */ - SPI_RX_ONLY = SPI_CR1_RXONLY, /**< Receive only */ - SPI_SW_SLAVE = SPI_CR1_SSM, /**< Software slave management */ - SPI_SOFT_SS = SPI_CR1_SSI, /**< Software (internal) slave - select. This flag only has an - effect when used in combination - with SPI_SW_SLAVE. */ - SPI_FRAME_LSB = SPI_CR1_LSBFIRST, /**< LSB-first (little-endian) frame - format */ - SPI_FRAME_MSB = 0, /**< MSB-first (big-endian) frame - format (this is the default) */ -} spi_cfg_flag; - -void spi_master_enable(spi_dev *dev, - spi_baud_rate baud, - spi_mode mode, - uint32 flags); - -void spi_slave_enable(spi_dev *dev, - spi_mode mode, - uint32 flags); - -uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len); - -void spi_foreach(void (*fn)(spi_dev (*dev))); - -void spi_peripheral_enable(spi_dev *dev); -void spi_peripheral_disable(spi_dev *dev); - -void spi_tx_dma_enable(spi_dev *dev); -void spi_tx_dma_disable(spi_dev *dev); - -void spi_rx_dma_enable(spi_dev *dev); -void spi_rx_dma_disable(spi_dev *dev); - -/** - * @brief Determine if a SPI peripheral is enabled. - * @param dev SPI device - * @return True, if and only if dev's peripheral is enabled. - */ -static inline uint8 spi_is_enabled(spi_dev *dev) { - return dev->regs->CR1 & SPI_CR1_SPE_BIT; -} - -/** - * @brief Disable all SPI peripherals - */ -static inline void spi_peripheral_disable_all(void) { - spi_foreach(spi_peripheral_disable); -} - -/** Available SPI interrupts */ -typedef enum spi_interrupt { - SPI_TXE_INTERRUPT = SPI_CR2_TXEIE, /**< TX buffer empty interrupt */ - SPI_RXNE_INTERRUPT = SPI_CR2_RXNEIE, /**< RX buffer not empty interrupt */ - SPI_ERR_INTERRUPT = SPI_CR2_ERRIE /**< - * Error interrupt (CRC, overrun, - * and mode fault errors for SPI; - * underrun, overrun errors for I2S) - */ -} spi_interrupt; - -/** - * @brief Mask for all spi_interrupt values - * @see spi_interrupt - */ -#define SPI_INTERRUPTS_ALL (SPI_TXE_INTERRUPT | \ - SPI_RXNE_INTERRUPT | \ - SPI_ERR_INTERRUPT) - -/** - * @brief Enable SPI interrupt requests - * @param dev SPI device - * @param interrupt_flags Bitwise OR of spi_interrupt values to enable - * @see spi_interrupt - */ -static inline void spi_irq_enable(spi_dev *dev, uint32 interrupt_flags) { - dev->regs->CR2 |= interrupt_flags; - nvic_irq_enable(dev->irq_num); -} - -/** - * @brief Disable SPI interrupt requests - * @param dev SPI device - * @param interrupt_flags Bitwise OR of spi_interrupt values to disable - * @see spi_interrupt - */ -static inline void spi_irq_disable(spi_dev *dev, uint32 interrupt_flags) { - dev->regs->CR2 &= ~interrupt_flags; -} - -/** - * @brief Get the data frame format flags with which a SPI port is - * configured. - * @param dev SPI device whose data frame format to get. - * @return SPI_DFF_8_BIT, if dev has an 8-bit data frame format. - * Otherwise, SPI_DFF_16_BIT. - */ -static inline spi_cfg_flag spi_dff(spi_dev *dev) { - return ((dev->regs->CR1 & SPI_CR1_DFF) == SPI_CR1_DFF_8_BIT ? - SPI_DFF_8_BIT : - SPI_DFF_16_BIT); -} - -/** - * @brief Determine whether the device's peripheral receive (RX) - * register is empty. - * @param dev SPI device - * @return true, iff dev's RX register is empty. - */ -static inline uint8 spi_is_rx_nonempty(spi_dev *dev) { - return dev->regs->SR & SPI_SR_RXNE; -} - -/** - * @brief Retrieve the contents of the device's peripheral receive - * (RX) register. - * - * You may only call this function when the RX register is nonempty. - * Calling this function clears the contents of the RX register. - * - * @param dev SPI device - * @return Contents of dev's peripheral RX register - * @see spi_is_rx_reg_nonempty() - */ -static inline uint16 spi_rx_reg(spi_dev *dev) { - return (uint16)dev->regs->DR; -} - -/** - * @brief Determine whether the device's peripheral transmit (TX) - * register is empty. - * @param dev SPI device - * @return true, iff dev's TX register is empty. - */ -static inline uint8 spi_is_tx_empty(spi_dev *dev) { - return dev->regs->SR & SPI_SR_TXE; -} - -/** - * @brief Load a value into the device's peripheral transmit (TX) register. - * - * You may only call this function when the TX register is empty. - * Calling this function loads val into the peripheral's TX register. - * If the device is properly configured, this will initiate a - * transmission, the completion of which will cause the TX register to - * be empty again. - * - * @param dev SPI device - * @param val Value to load into the TX register. If the SPI data - * frame format is 8 bit, the value must be right-aligned. - * @see spi_is_tx_reg_empty() - * @see spi_init() - * @see spi_master_enable() - * @see spi_slave_enable() - */ -static inline void spi_tx_reg(spi_dev *dev, uint16 val) { - dev->regs->DR = val; -} - -/** - * @brief Determine whether the device's peripheral busy (SPI_SR_BSY) - * flag is set. - * @param dev SPI device - * @return true, iff dev's BSY flag is set. - */ -static inline uint8 spi_is_busy(spi_dev *dev) { - return dev->regs->SR & SPI_SR_BSY; -} - -/* - * I2S convenience functions (TODO) - */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/stm32.h b/libmaple/stm32.h deleted file mode 100644 index 3b54dbc..0000000 --- a/libmaple/stm32.h +++ /dev/null @@ -1,191 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file stm32.h - * @brief STM32 chip-specific definitions - */ - -#ifndef _STM32_H_ -#define _STM32_H_ - -/* - * User-specific configuration. - * - * The #defines here depend upon how libmaple is used. Because of the - * potential for a mismatch between them and the actual libmaple - * usage, you should try to keep their number to an absolute minimum. - */ - -#ifdef __DOXYGEN_PREDEFINED_HACK - - /** @brief APB1 clock speed, in Hz. */ - #define STM32_PCLK1 - /** @brief APB2 clock speed, in Hz. */ - #define STM32_PCLK2 - - /** Deprecated. Use STM32_PCLK1 instead. */ - #define PCLK1 - /** Deprecated. Use STM32_PCLK2 instead. */ - #define PCLK2 - -#endif - -#ifndef STM32_PCLK1 -#define STM32_PCLK1 36000000U -#endif -#ifndef PCLK1 -#define PCLK1 STM32_PCLK1 -#endif -#if PCLK1 != STM32_PCLK1 -#error "(Deprecated) PCLK1 differs from STM32_PCLK1" -#endif - -#ifndef STM32_PCLK2 -#define STM32_PCLK2 72000000U -#endif -#ifndef PCLK2 -#define PCLK2 STM32_PCLK2 -#endif -#if PCLK2 != STM32_PCLK2 -#error "(Deprecated) PCLK2 differs from STM32_PCLK2" -#endif - -/* - * Density-specific configuration. - */ - -#ifdef __DOXYGEN_PREDEFINED_HACK - - /** - * @brief Number of interrupts in the NVIC. - * - * This define is automatically generated whenever the proper - * density is defined (currently, this is restricted to defining - * one of STM32_MEDIUM_DENSITY and STM32_HIGH_DENSITY). - */ - #define STM32_NR_INTERRUPTS - - /** Deprecated. Use STM32_NR_INTERRUPTS instead. */ - #define NR_INTERRUPTS - -#endif - -#ifdef STM32_MEDIUM_DENSITY - #define STM32_NR_INTERRUPTS 43 -#elif defined(STM32_HIGH_DENSITY) - #define STM32_NR_INTERRUPTS 60 -#else -#error "No STM32 board type defined!" -#endif - -#define NR_INTERRUPTS STM32_NR_INTERRUPTS - -/* - * MCU-specific configuration. - */ - -#ifdef __DOXYGEN_PREDEFINED_HACK - - /** - * Number of GPIO ports. - */ - #define STM32_NR_GPIO_PORTS - - /** - * @brief Multiplier to convert microseconds into loop iterations - * in delay_us(). - * - * @see delay_us() - */ - #define STM32_DELAY_US_MULT - - /** - * @brief Pointer to end of built-in SRAM. - * - * Points to the address which is 1 byte past the last valid - * SRAM address. - */ - #define STM32_SRAM_END - - /** Deprecated. Use STM32_NR_GPIO_PORTS instead. */ - #define NR_GPIO_PORTS - /** Deprecated. Use STM32_DELAY_US_MULT instead. */ - #define DELAY_US_MULT - -#endif - -#if defined(MCU_STM32F103RB) - /* e.g., LeafLabs Maple */ - - #define STM32_NR_GPIO_PORTS 4 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20005000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#elif defined(MCU_STM32F103ZE) - /* e.g., LeafLabs Maple Native */ - - #define STM32_NR_GPIO_PORTS 7 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20010000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#elif defined(MCU_STM32F103CB) - /* e.g., LeafLabs Maple Mini */ - - /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true. - * But only pins 0 and 1 exist, and they're used for OSC on the - * Mini, so we'll live with this for now. */ - #define STM32_NR_GPIO_PORTS 3 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20005000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#elif defined(MCU_STM32F103RE) - /* e.g., LeafLabs Maple RET6 edition */ - - #define STM32_NR_GPIO_PORTS 4 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20010000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#else - -#error "No MCU type specified. Add something like -DMCU_STM32F103RB " \ - "to your compiler arguments (probably in a Makefile)." - -#endif - -#endif /* _STM32_H_ */ diff --git a/libmaple/syscalls.c b/libmaple/syscalls.c index 8a57945..86fd8e6 100644 --- a/libmaple/syscalls.c +++ b/libmaple/syscalls.c @@ -30,7 +30,7 @@ * memory allocation. */ -#include "libmaple.h" +#include #include #include diff --git a/libmaple/systick.c b/libmaple/systick.c index 9bb5d50..c6e3cbd 100644 --- a/libmaple/systick.c +++ b/libmaple/systick.c @@ -29,7 +29,7 @@ * @brief System timer interrupt handler and initialization routines */ -#include "systick.h" +#include volatile uint32 systick_uptime_millis; static void (*systick_user_callback)(void); diff --git a/libmaple/systick.h b/libmaple/systick.h deleted file mode 100644 index 6ec3364..0000000 --- a/libmaple/systick.h +++ /dev/null @@ -1,117 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file systick.h - * - * @brief Various system timer definitions - */ - -#ifndef _SYSTICK_H_ -#define _SYSTICK_H_ - -#include "libmaple_types.h" -#include "util.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/** SysTick register map type */ -typedef struct systick_reg_map { - __io uint32 CSR; /**< Control and status register */ - __io uint32 RVR; /**< Reload value register */ - __io uint32 CNT; /**< Current value register ("count") */ - __io uint32 CVR; /**< Calibration value register */ -} systick_reg_map; - -/** SysTick register map base pointer */ -#define SYSTICK_BASE ((struct systick_reg_map*)0xE000E010) - -/* - * Register bit definitions. - */ - -/* Control and status register */ - -#define SYSTICK_CSR_COUNTFLAG BIT(16) -#define SYSTICK_CSR_CLKSOURCE BIT(2) -#define SYSTICK_CSR_CLKSOURCE_EXTERNAL 0 -#define SYSTICK_CSR_CLKSOURCE_CORE BIT(2) -#define SYSTICK_CSR_TICKINT BIT(1) -#define SYSTICK_CSR_TICKINT_PEND BIT(1) -#define SYSTICK_CSR_TICKINT_NO_PEND 0 -#define SYSTICK_CSR_ENABLE BIT(0) -#define SYSTICK_CSR_ENABLE_MULTISHOT BIT(0) -#define SYSTICK_CSR_ENABLE_DISABLED 0 - -/* Calibration value register */ - -#define SYSTICK_CVR_NOREF BIT(31) -#define SYSTICK_CVR_SKEW BIT(30) -#define SYSTICK_CVR_TENMS 0xFFFFFF - -/** System elapsed time, in milliseconds */ -extern volatile uint32 systick_uptime_millis; - -/** - * @brief Returns the system uptime, in milliseconds. - */ -static inline uint32 systick_uptime(void) { - return systick_uptime_millis; -} - - -void systick_init(uint32 reload_val); -void systick_disable(); -void systick_enable(); - -/** - * @brief Returns the current value of the SysTick counter. - */ -static inline uint32 systick_get_count(void) { - return SYSTICK_BASE->CNT; -} - -/** - * @brief Check for underflow. - * - * This function returns 1 if the SysTick timer has counted to 0 since - * the last time it was called. However, any reads of any part of the - * SysTick Control and Status Register SYSTICK_BASE->CSR will - * interfere with this functionality. See the ARM Cortex M3 Technical - * Reference Manual for more details (e.g. Table 8-3 in revision r1p1). - */ -static inline uint32 systick_check_underflow(void) { - return SYSTICK_BASE->CSR & SYSTICK_CSR_COUNTFLAG; -} - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif - diff --git a/libmaple/timer.c b/libmaple/timer.c index 83e9ace..90995e2 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -30,7 +30,7 @@ * @brief New-style timer interface */ -#include "timer.h" +#include /* Just like the corresponding DIER bits: * [0] = Update handler; diff --git a/libmaple/timer.h b/libmaple/timer.h deleted file mode 100644 index 53e2547..0000000 --- a/libmaple/timer.h +++ /dev/null @@ -1,1012 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file timer.h - * @author Marti Bolivar - * @brief New-style timer interface. - * - * Replaces old timers.h implementation. - */ - -#ifndef _TIMERS_H_ -#define _TIMERS_H_ - -#include "libmaple.h" -#include "rcc.h" -#include "nvic.h" -#include "bitband.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Register maps and devices - */ - -/** Advanced control timer register map type */ -typedef struct timer_adv_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 SMCR; /**< Slave mode control register */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ - __io uint32 SR; /**< Status register */ - __io uint32 EGR; /**< Event generation register */ - __io uint32 CCMR1; /**< Capture/compare mode register 1 */ - __io uint32 CCMR2; /**< Capture/compare mode register 2 */ - __io uint32 CCER; /**< Capture/compare enable register */ - __io uint32 CNT; /**< Counter */ - __io uint32 PSC; /**< Prescaler */ - __io uint32 ARR; /**< Auto-reload register */ - __io uint32 RCR; /**< Repetition counter register */ - __io uint32 CCR1; /**< Capture/compare register 1 */ - __io uint32 CCR2; /**< Capture/compare register 2 */ - __io uint32 CCR3; /**< Capture/compare register 3 */ - __io uint32 CCR4; /**< Capture/compare register 4 */ - __io uint32 BDTR; /**< Break and dead-time register */ - __io uint32 DCR; /**< DMA control register */ - __io uint32 DMAR; /**< DMA address for full transfer */ -} timer_adv_reg_map; - -/** General purpose timer register map type */ -typedef struct timer_gen_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 SMCR; /**< Slave mode control register */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ - __io uint32 SR; /**< Status register */ - __io uint32 EGR; /**< Event generation register */ - __io uint32 CCMR1; /**< Capture/compare mode register 1 */ - __io uint32 CCMR2; /**< Capture/compare mode register 2 */ - __io uint32 CCER; /**< Capture/compare enable register */ - __io uint32 CNT; /**< Counter */ - __io uint32 PSC; /**< Prescaler */ - __io uint32 ARR; /**< Auto-reload register */ - const uint32 RESERVED1; /**< Reserved */ - __io uint32 CCR1; /**< Capture/compare register 1 */ - __io uint32 CCR2; /**< Capture/compare register 2 */ - __io uint32 CCR3; /**< Capture/compare register 3 */ - __io uint32 CCR4; /**< Capture/compare register 4 */ - const uint32 RESERVED2; /**< Reserved */ - __io uint32 DCR; /**< DMA control register */ - __io uint32 DMAR; /**< DMA address for full transfer */ -} timer_gen_reg_map; - -/** Basic timer register map type */ -typedef struct timer_bas_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - const uint32 RESERVED1; /**< Reserved */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ - __io uint32 SR; /**< Status register */ - __io uint32 EGR; /**< Event generation register */ - const uint32 RESERVED2; /**< Reserved */ - const uint32 RESERVED3; /**< Reserved */ - const uint32 RESERVED4; /**< Reserved */ - __io uint32 CNT; /**< Counter */ - __io uint32 PSC; /**< Prescaler */ - __io uint32 ARR; /**< Auto-reload register */ -} timer_bas_reg_map; - -/** Timer 1 register map base pointer */ -#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) -/** Timer 2 register map base pointer */ -#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) -/** Timer 3 register map base pointer */ -#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) -/** Timer 4 register map base pointer */ -#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) -#ifdef STM32_HIGH_DENSITY -/** Timer 5 register map base pointer */ -#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) -/** Timer 6 register map base pointer */ -#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) -/** Timer 7 register map base pointer */ -#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) -/** Timer 8 register map base pointer */ -#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) -#endif - -/* - * Timer devices - */ - -/** - * @brief Timer register map type. - * - * Just holds a pointer to the correct type of register map, based on - * the timer's type. - */ -typedef union timer_reg_map { - timer_adv_reg_map *adv; /**< Advanced register map */ - timer_gen_reg_map *gen; /**< General purpose register map */ - timer_bas_reg_map *bas; /**< Basic register map */ -} timer_reg_map; - -/** - * @brief Timer type - * - * Type marker for timer_dev. - * - * @see timer_dev - */ -typedef enum timer_type { - TIMER_ADVANCED, /**< Advanced type */ - TIMER_GENERAL, /**< General purpose type */ - TIMER_BASIC /**< Basic type */ -} timer_type; - -/** Timer device type */ -typedef struct timer_dev { - timer_reg_map regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ - timer_type type; /**< Timer's type */ - voidFuncPtr handlers[]; /**< User IRQ handlers */ -} timer_dev; - -extern timer_dev *TIMER1; -extern timer_dev *TIMER2; -extern timer_dev *TIMER3; -extern timer_dev *TIMER4; -#ifdef STM32_HIGH_DENSITY -extern timer_dev *TIMER5; -extern timer_dev *TIMER6; -extern timer_dev *TIMER7; -extern timer_dev *TIMER8; -#endif - -/* - * Register bit definitions - */ - -/* Control register 1 (CR1) */ - -#define TIMER_CR1_ARPE_BIT 7 -#define TIMER_CR1_DIR_BIT 4 -#define TIMER_CR1_OPM_BIT 3 -#define TIMER_CR1_URS_BIT 2 -#define TIMER_CR1_UDIS_BIT 1 -#define TIMER_CR1_CEN_BIT 0 - -#define TIMER_CR1_CKD (0x3 << 8) -#define TIMER_CR1_CKD_1TCKINT (0x0 << 8) -#define TIMER_CR1_CKD_2TCKINT (0x1 << 8) -#define TIMER_CR1_CKD_4TICKINT (0x2 << 8) -#define TIMER_CR1_ARPE BIT(TIMER_CR1_ARPE_BIT) -#define TIMER_CR1_CKD_CMS (0x3 << 5) -#define TIMER_CR1_CKD_CMS_EDGE (0x0 << 5) -#define TIMER_CR1_CKD_CMS_CENTER1 (0x1 << 5) -#define TIMER_CR1_CKD_CMS_CENTER2 (0x2 << 5) -#define TIMER_CR1_CKD_CMS_CENTER3 (0x3 << 5) -#define TIMER_CR1_DIR BIT(TIMER_CR1_DIR_BIT) -#define TIMER_CR1_OPM BIT(TIMER_CR1_OPM_BIT) -#define TIMER_CR1_URS BIT(TIMER_CR1_URS_BIT) -#define TIMER_CR1_UDIS BIT(TIMER_CR1_UDIS_BIT) -#define TIMER_CR1_CEN BIT(TIMER_CR1_CEN_BIT) - -/* Control register 2 (CR2) */ - -#define TIMER_CR2_OIS4_BIT 14 -#define TIMER_CR2_OIS3N_BIT 13 -#define TIMER_CR2_OIS3_BIT 12 -#define TIMER_CR2_OIS2N_BIT 11 -#define TIMER_CR2_OIS2_BIT 10 -#define TIMER_CR2_OIS1N_BIT 9 -#define TIMER_CR2_OIS1_BIT 8 -#define TIMER_CR2_TI1S_BIT 7 /* tills? yikes */ -#define TIMER_CR2_CCDS_BIT 3 -#define TIMER_CR2_CCUS_BIT 2 -#define TIMER_CR2_CCPC_BIT 0 - -#define TIMER_CR2_OIS4 BIT(TIMER_CR2_OIS4_BIT) -#define TIMER_CR2_OIS3N BIT(TIMER_CR2_OIS3N_BIT) -#define TIMER_CR2_OIS3 BIT(TIMER_CR2_OIS3_BIT) -#define TIMER_CR2_OIS2N BIT(TIMER_CR2_OIS2N_BIT) -#define TIMER_CR2_OIS2 BIT(TIMER_CR2_OIS2_BIT) -#define TIMER_CR2_OIS1N BIT(TIMER_CR2_OIS1N_BIT) -#define TIMER_CR2_OIS1 BIT(TIMER_CR2_OIS1_BIT) -#define TIMER_CR2_TI1S BIT(TIMER_CR2_TI1S_BIT) -#define TIMER_CR2_MMS (0x7 << 4) -#define TIMER_CR2_MMS_RESET (0x0 << 4) -#define TIMER_CR2_MMS_ENABLE (0x1 << 4) -#define TIMER_CR2_MMS_UPDATE (0x2 << 4) -#define TIMER_CR2_MMS_COMPARE_PULSE (0x3 << 4) -#define TIMER_CR2_MMS_COMPARE_OC1REF (0x4 << 4) -#define TIMER_CR2_MMS_COMPARE_OC2REF (0x5 << 4) -#define TIMER_CR2_MMS_COMPARE_OC3REF (0x6 << 4) -#define TIMER_CR2_MMS_COMPARE_OC4REF (0x7 << 4) -#define TIMER_CR2_CCDS BIT(TIMER_CR2_CCDS_BIT) -#define TIMER_CR2_CCUS BIT(TIMER_CR2_CCUS_BIT) -#define TIMER_CR2_CCPC BIT(TIMER_CR2_CCPC_BIT) - -/* Slave mode control register (SMCR) */ - -#define TIMER_SMCR_ETP_BIT 15 -#define TIMER_SMCR_ECE_BIT 14 -#define TIMER_SMCR_MSM_BIT 7 - -#define TIMER_SMCR_ETP BIT(TIMER_SMCR_ETP_BIT) -#define TIMER_SMCR_ECE BIT(TIMER_SMCR_ECE_BIT) -#define TIMER_SMCR_ETPS (0x3 << 12) -#define TIMER_SMCR_ETPS_OFF (0x0 << 12) -#define TIMER_SMCR_ETPS_DIV2 (0x1 << 12) -#define TIMER_SMCR_ETPS_DIV4 (0x2 << 12) -#define TIMER_SMCR_ETPS_DIV8 (0x3 << 12) -#define TIMER_SMCR_ETF (0xF << 12) -#define TIMER_SMCR_MSM BIT(TIMER_SMCR_MSM_BIT) -#define TIMER_SMCR_TS (0x3 << 4) -#define TIMER_SMCR_TS_ITR0 (0x0 << 4) -#define TIMER_SMCR_TS_ITR1 (0x1 << 4) -#define TIMER_SMCR_TS_ITR2 (0x2 << 4) -#define TIMER_SMCR_TS_ITR3 (0x3 << 4) -#define TIMER_SMCR_TS_TI1F_ED (0x4 << 4) -#define TIMER_SMCR_TS_TI1FP1 (0x5 << 4) -#define TIMER_SMCR_TS_TI2FP2 (0x6 << 4) -#define TIMER_SMCR_TS_ETRF (0x7 << 4) -#define TIMER_SMCR_SMS 0x3 -#define TIMER_SMCR_SMS_DISABLED 0x0 -#define TIMER_SMCR_SMS_ENCODER1 0x1 -#define TIMER_SMCR_SMS_ENCODER2 0x2 -#define TIMER_SMCR_SMS_ENCODER3 0x3 -#define TIMER_SMCR_SMS_RESET 0x4 -#define TIMER_SMCR_SMS_GATED 0x5 -#define TIMER_SMCR_SMS_TRIGGER 0x6 -#define TIMER_SMCR_SMS_EXTERNAL 0x7 - -/* DMA/Interrupt enable register (DIER) */ - -#define TIMER_DIER_TDE_BIT 14 -#define TIMER_DIER_CC4DE_BIT 12 -#define TIMER_DIER_CC3DE_BIT 11 -#define TIMER_DIER_CC2DE_BIT 10 -#define TIMER_DIER_CC1DE_BIT 9 -#define TIMER_DIER_UDE_BIT 8 -#define TIMER_DIER_TIE_BIT 6 -#define TIMER_DIER_CC4IE_BIT 4 -#define TIMER_DIER_CC3IE_BIT 3 -#define TIMER_DIER_CC2IE_BIT 2 -#define TIMER_DIER_CC1IE_BIT 1 -#define TIMER_DIER_UIE_BIT 0 - -#define TIMER_DIER_TDE BIT(TIMER_DIER_TDE_BIT) -#define TIMER_DIER_CC4DE BIT(TIMER_DIER_CC4DE_BIT) -#define TIMER_DIER_CC3DE BIT(TIMER_DIER_CC3DE_BIT) -#define TIMER_DIER_CC2DE BIT(TIMER_DIER_CC2DE_BIT) -#define TIMER_DIER_CC1DE BIT(TIMER_DIER_CC1DE_BIT) -#define TIMER_DIER_UDE BIT(TIMER_DIER_UDE_BIT) -#define TIMER_DIER_TIE BIT(TIMER_DIER_TIE_BIT) -#define TIMER_DIER_CC4IE BIT(TIMER_DIER_CC4IE_BIT) -#define TIMER_DIER_CC3IE BIT(TIMER_DIER_CC3IE_BIT) -#define TIMER_DIER_CC2IE BIT(TIMER_DIER_CC2IE_BIT) -#define TIMER_DIER_CC1IE BIT(TIMER_DIER_CC1IE_BIT) -#define TIMER_DIER_UIE BIT(TIMER_DIER_UIE_BIT) - -/* Status register (SR) */ - -#define TIMER_SR_CC4OF_BIT 12 -#define TIMER_SR_CC3OF_BIT 11 -#define TIMER_SR_CC2OF_BIT 10 -#define TIMER_SR_CC1OF_BIT 9 -#define TIMER_SR_BIF_BIT 7 -#define TIMER_SR_TIF_BIT 6 -#define TIMER_SR_COMIF_BIT 5 -#define TIMER_SR_CC4IF_BIT 4 -#define TIMER_SR_CC3IF_BIT 3 -#define TIMER_SR_CC2IF_BIT 2 -#define TIMER_SR_CC1IF_BIT 1 -#define TIMER_SR_UIF_BIT 0 - -#define TIMER_SR_CC4OF BIT(TIMER_SR_CC4OF_BIT) -#define TIMER_SR_CC3OF BIT(TIMER_SR_CC3OF_BIT) -#define TIMER_SR_CC2OF BIT(TIMER_SR_CC2OF_BIT) -#define TIMER_SR_CC1OF BIT(TIMER_SR_CC1OF_BIT) -#define TIMER_SR_BIF BIT(TIMER_SR_BIF_BIT) -#define TIMER_SR_TIF BIT(TIMER_SR_TIF_BIT) -#define TIMER_SR_COMIF BIT(TIMER_SR_COMIF_BIT) -#define TIMER_SR_CC4IF BIT(TIMER_SR_CC4IF_BIT) -#define TIMER_SR_CC3IF BIT(TIMER_SR_CC3IF_BIT) -#define TIMER_SR_CC2IF BIT(TIMER_SR_CC2IF_BIT) -#define TIMER_SR_CC1IF BIT(TIMER_SR_CC1IF_BIT) -#define TIMER_SR_UIF BIT(TIMER_SR_UIF_BIT) - -/* Event generation register (EGR) */ - -#define TIMER_EGR_TG_BIT 6 -#define TIMER_EGR_CC4G_BIT 4 -#define TIMER_EGR_CC3G_BIT 3 -#define TIMER_EGR_CC2G_BIT 2 -#define TIMER_EGR_CC1G_BIT 1 -#define TIMER_EGR_UG_BIT 0 - -#define TIMER_EGR_TG BIT(TIMER_EGR_TG_BIT) -#define TIMER_EGR_CC4G BIT(TIMER_EGR_CC4G_BIT) -#define TIMER_EGR_CC3G BIT(TIMER_EGR_CC3G_BIT) -#define TIMER_EGR_CC2G BIT(TIMER_EGR_CC2G_BIT) -#define TIMER_EGR_CC1G BIT(TIMER_EGR_CC1G_BIT) -#define TIMER_EGR_UG BIT(TIMER_EGR_UG_BIT) - -/* Capture/compare mode registers, common values */ - -#define TIMER_CCMR_CCS_OUTPUT 0x0 -#define TIMER_CCMR_CCS_INPUT_TI1 0x1 -#define TIMER_CCMR_CCS_INPUT_TI2 0x2 -#define TIMER_CCMR_CCS_INPUT_TRC 0x3 - -/* Capture/compare mode register 1 (CCMR1) */ - -#define TIMER_CCMR1_OC2CE_BIT 15 -#define TIMER_CCMR1_OC2PE_BIT 11 -#define TIMER_CCMR1_OC2FE_BIT 10 -#define TIMER_CCMR1_OC1CE_BIT 7 -#define TIMER_CCMR1_OC1PE_BIT 3 -#define TIMER_CCMR1_OC1FE_BIT 2 - -#define TIMER_CCMR1_OC2CE BIT(TIMER_CCMR1_OC2CE_BIT) -#define TIMER_CCMR1_OC2M (0x3 << 12) -#define TIMER_CCMR1_IC2F (0xF << 12) -#define TIMER_CCMR1_OC2PE BIT(TIMER_CCMR1_OC2PE_BIT) -#define TIMER_CCMR1_OC2FE BIT(TIMER_CCMR1_OC2FE_BIT) -#define TIMER_CCMR1_IC2PSC (0x3 << 10) -#define TIMER_CCMR1_CC2S (0x3 << 8) -#define TIMER_CCMR1_CC2S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) -#define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) -#define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) -#define TIMER_CCMR1_CC2S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) -#define TIMER_CCMR1_OC1CE BIT(TIMER_CCMR1_OC1CE_BIT) -#define TIMER_CCMR1_OC1M (0x3 << 4) -#define TIMER_CCMR1_IC1F (0xF << 4) -#define TIMER_CCMR1_OC1PE BIT(TIMER_CCMR1_OC1PE_BIT) -#define TIMER_CCMR1_OC1FE BIT(TIMER_CCMR1_OC1FE_BIT) -#define TIMER_CCMR1_IC1PSC (0x3 << 2) -#define TIMER_CCMR1_CC1S 0x3 -#define TIMER_CCMR1_CC1S_OUTPUT TIMER_CCMR_CCS_OUTPUT -#define TIMER_CCMR1_CC1S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 -#define TIMER_CCMR1_CC1S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 -#define TIMER_CCMR1_CC1S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC - -/* Capture/compare mode register 2 (CCMR2) */ - -#define TIMER_CCMR2_OC4CE_BIT 15 -#define TIMER_CCMR2_OC4PE_BIT 11 -#define TIMER_CCMR2_OC4FE_BIT 10 -#define TIMER_CCMR2_OC3CE_BIT 7 -#define TIMER_CCMR2_OC3PE_BIT 3 -#define TIMER_CCMR2_OC3FE_BIT 2 - -#define TIMER_CCMR2_OC4CE BIT(TIMER_CCMR2_OC4CE_BIT) -#define TIMER_CCMR2_OC4M (0x3 << 12) -#define TIMER_CCMR2_IC2F (0xF << 12) -#define TIMER_CCMR2_OC4PE BIT(TIMER_CCMR2_OC4PE_BIT) -#define TIMER_CCMR2_OC4FE BIT(TIMER_CCMR2_OC4FE_BIT) -#define TIMER_CCMR2_IC2PSC (0x3 << 10) -#define TIMER_CCMR2_CC4S (0x3 << 8) -#define TIMER_CCMR1_CC4S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) -#define TIMER_CCMR1_CC4S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) -#define TIMER_CCMR1_CC4S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) -#define TIMER_CCMR1_CC4S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) -#define TIMER_CCMR2_OC3CE BIT(TIMER_CCMR2_OC3CE_BIT) -#define TIMER_CCMR2_OC3M (0x3 << 4) -#define TIMER_CCMR2_IC1F (0xF << 4) -#define TIMER_CCMR2_OC3PE BIT(TIMER_CCMR2_OC3PE_BIT) -#define TIMER_CCMR2_OC3FE BIT(TIMER_CCMR2_OC3FE_BIT) -#define TIMER_CCMR2_IC1PSC (0x3 << 2) -#define TIMER_CCMR2_CC3S 0x3 -#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR_CCS_OUTPUT -#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 -#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 -#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC - -/* Capture/compare enable register (CCER) */ - -#define TIMER_CCER_CC4P_BIT 13 -#define TIMER_CCER_CC4E_BIT 12 -#define TIMER_CCER_CC3P_BIT 9 -#define TIMER_CCER_CC3E_BIT 8 -#define TIMER_CCER_CC2P_BIT 5 -#define TIMER_CCER_CC2E_BIT 4 -#define TIMER_CCER_CC1P_BIT 1 -#define TIMER_CCER_CC1E_BIT 0 - -#define TIMER_CCER_CC4P BIT(TIMER_CCER_CC4P_BIT) -#define TIMER_CCER_CC4E BIT(TIMER_CCER_CC4E_BIT) -#define TIMER_CCER_CC3P BIT(TIMER_CCER_CC3P_BIT) -#define TIMER_CCER_CC3E BIT(TIMER_CCER_CC3E_BIT) -#define TIMER_CCER_CC2P BIT(TIMER_CCER_CC2P_BIT) -#define TIMER_CCER_CC2E BIT(TIMER_CCER_CC2E_BIT) -#define TIMER_CCER_CC1P BIT(TIMER_CCER_CC1P_BIT) -#define TIMER_CCER_CC1E BIT(TIMER_CCER_CC1E_BIT) - -/* Break and dead-time register (BDTR) */ - -#define TIMER_BDTR_MOE_BIT 15 -#define TIMER_BDTR_AOE_BIT 14 -#define TIMER_BDTR_BKP_BIT 13 -#define TIMER_BDTR_BKE_BIT 12 -#define TIMER_BDTR_OSSR_BIT 11 -#define TIMER_BDTR_OSSI_BIT 10 - -#define TIMER_BDTR_MOE BIT(TIMER_BDTR_MOE_BIT) -#define TIMER_BDTR_AOE BIT(TIMER_BDTR_AOE_BIT) -#define TIMER_BDTR_BKP BIT(TIMER_BDTR_BKP_BIT) -#define TIMER_BDTR_BKE BIT(TIMER_BDTR_BKE_BIT) -#define TIMER_BDTR_OSSR BIT(TIMER_BDTR_OSSR_BIT) -#define TIMER_BDTR_OSSI BIT(TIMER_BDTR_OSSI_BIT) -#define TIMER_BDTR_LOCK (0x3 << 8) -#define TIMER_BDTR_LOCK_OFF (0x0 << 8) -#define TIMER_BDTR_LOCK_LEVEL1 (0x1 << 8) -#define TIMER_BDTR_LOCK_LEVEL2 (0x2 << 8) -#define TIMER_BDTR_LOCK_LEVEL3 (0x3 << 8) -#define TIMER_BDTR_DTG 0xFF - -/* DMA control register (DCR) */ - -#define TIMER_DCR_DBL (0x1F << 8) -#define TIMER_DCR_DBL_1BYTE (0x0 << 8) -#define TIMER_DCR_DBL_2BYTE (0x1 << 8) -#define TIMER_DCR_DBL_3BYTE (0x2 << 8) -#define TIMER_DCR_DBL_4BYTE (0x3 << 8) -#define TIMER_DCR_DBL_5BYTE (0x4 << 8) -#define TIMER_DCR_DBL_6BYTE (0x5 << 8) -#define TIMER_DCR_DBL_7BYTE (0x6 << 8) -#define TIMER_DCR_DBL_8BYTE (0x7 << 8) -#define TIMER_DCR_DBL_9BYTE (0x8 << 8) -#define TIMER_DCR_DBL_10BYTE (0x9 << 8) -#define TIMER_DCR_DBL_11BYTE (0xA << 8) -#define TIMER_DCR_DBL_12BYTE (0xB << 8) -#define TIMER_DCR_DBL_13BYTE (0xC << 8) -#define TIMER_DCR_DBL_14BYTE (0xD << 8) -#define TIMER_DCR_DBL_15BYTE (0xE << 8) -#define TIMER_DCR_DBL_16BYTE (0xF << 8) -#define TIMER_DCR_DBL_17BYTE (0x10 << 8) -#define TIMER_DCR_DBL_18BYTE (0x11 << 8) -#define TIMER_DCR_DBA 0x1F -#define TIMER_DCR_DBA_CR1 0x0 -#define TIMER_DCR_DBA_CR2 0x1 -#define TIMER_DCR_DBA_SMCR 0x2 -#define TIMER_DCR_DBA_DIER 0x3 -#define TIMER_DCR_DBA_SR 0x4 -#define TIMER_DCR_DBA_EGR 0x5 -#define TIMER_DCR_DBA_CCMR1 0x6 -#define TIMER_DCR_DBA_CCMR2 0x7 -#define TIMER_DCR_DBA_CCER 0x8 -#define TIMER_DCR_DBA_CNT 0x9 -#define TIMER_DCR_DBA_PSC 0xA -#define TIMER_DCR_DBA_ARR 0xB -#define TIMER_DCR_DBA_RCR 0xC -#define TIMER_DCR_DBA_CCR1 0xD -#define TIMER_DCR_DBA_CCR2 0xE -#define TIMER_DCR_DBA_CCR3 0xF -#define TIMER_DCR_DBA_CCR4 0x10 -#define TIMER_DCR_DBA_BDTR 0x11 -#define TIMER_DCR_DBA_DCR 0x12 -#define TIMER_DCR_DBA_DMAR 0x13 - -/* - * Convenience routines - */ - -/** - * Used to configure the behavior of a timer channel. Note that not - * all timers can be configured in every mode. - */ -/* TODO TIMER_PWM_CENTER_ALIGNED, TIMER_INPUT_CAPTURE, TIMER_ONE_PULSE */ -typedef enum timer_mode { - TIMER_DISABLED, /**< In this mode, the timer stops counting, - channel interrupts are detached, and no state - changes are output. */ - TIMER_PWM, /**< PWM output mode. This is the default mode for pins - after initialization. */ - /* TIMER_PWM_CENTER_ALIGNED, /\**< Center-aligned PWM output mode. *\/ */ - TIMER_OUTPUT_COMPARE, /**< In this mode, the timer counts from 0 - to its reload value repeatedly; every - time the counter value reaches one of - the channel compare values, the - corresponding interrupt is fired. */ - /* TIMER_INPUT_CAPTURE, /\**< In this mode, the timer can measure the */ - /* pulse lengths of input signals. *\/ */ - /* TIMER_ONE_PULSE /\**< In this mode, the timer can generate a single */ - /* pulse on a GPIO pin for a specified amount of */ - /* time. *\/ */ -} timer_mode; - -/** Timer channel numbers */ -typedef enum timer_channel { - TIMER_CH1 = 1, /**< Channel 1 */ - TIMER_CH2 = 2, /**< Channel 2 */ - TIMER_CH3 = 3, /**< Channel 3 */ - TIMER_CH4 = 4 /**< Channel 4 */ -} timer_channel; - -/* - * Note: Don't require timer_channel arguments! We want to be able to say - * - * for (int channel = 1; channel <= 4; channel++) { - * ... - * } - * - * without the compiler yelling at us. - */ - -void timer_init(timer_dev *dev); -void timer_disable(timer_dev *dev); -void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode); -void timer_foreach(void (*fn)(timer_dev*)); - -/** - * @brief Timer interrupt number. - * - * Not all timers support all of these values; see the descriptions - * for each value. - */ -typedef enum timer_interrupt_id { - TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */ - TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt, available - on general and advanced timers only. */ - TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt, general and - advanced timers only. */ - TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt, general and - advanced timers only. */ - TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt, general and - advanced timers only. */ - TIMER_COM_INTERRUPT, /**< COM interrupt, advanced timers only */ - TIMER_TRG_INTERRUPT, /**< Trigger interrupt, general and advanced - timers only */ - TIMER_BREAK_INTERRUPT /**< Break interrupt, advanced timers only. */ -} timer_interrupt_id; - -void timer_attach_interrupt(timer_dev *dev, - uint8 interrupt, - voidFuncPtr handler); -void timer_detach_interrupt(timer_dev *dev, uint8 interrupt); - -/** - * Initialize all timer devices on the chip. - */ -static inline void timer_init_all(void) { - timer_foreach(timer_init); -} - -/** - * Disables all timers on the device. - */ -static inline void timer_disable_all(void) { - timer_foreach(timer_disable); -} - -/** - * @brief Stop a timer's counter from changing. - * - * Does not affect the timer's mode or other settings. - * - * @param dev Device whose counter to pause. - */ -static inline void timer_pause(timer_dev *dev) { - *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 0; -} - -/** - * @brief Start a timer's counter. - * - * Does not affect the timer's mode or other settings. - * - * @param dev Device whose counter to resume - */ -static inline void timer_resume(timer_dev *dev) { - *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 1; -} - -/** - * @brief Returns the timer's counter value. - * - * This value is likely to be inaccurate if the counter is running - * with a low prescaler. - * - * @param dev Timer whose counter to return - */ -static inline uint16 timer_get_count(timer_dev *dev) { - return (uint16)(dev->regs).bas->CNT; -} - -/** - * @brief Sets the counter value for the given timer. - * @param dev Timer whose counter to set - * @param value New counter value - */ -static inline void timer_set_count(timer_dev *dev, uint16 value) { - (dev->regs).bas->CNT = value; -} - -/** - * @brief Returns the given timer's prescaler. - * - * Note that if the timer's prescaler is set (e.g. via - * timer_set_prescaler() or accessing a TIMx_PSC register), the value - * returned by this function will reflect the new setting, but the - * timer's counter will only reflect the new prescaler at the next - * update event. - * - * @param dev Timer whose prescaler to return - * @see timer_generate_update() - */ -static inline uint16 timer_get_prescaler(timer_dev *dev) { - return (uint16)(dev->regs).bas->PSC; -} - -/** - * @brief Set a timer's prescale value. - * - * Divides the input clock by (PSC+1). The new value will not take - * effect until the next update event. - * - * @param dev Timer whose prescaler to set - * @param psc New prescaler value - * @see timer_generate_update() - */ -static inline void timer_set_prescaler(timer_dev *dev, uint16 psc) { - (dev->regs).bas->PSC = psc; -} - -/** - * @brief Returns a timer's reload value. - * @param dev Timer whose reload value to return - */ -static inline uint16 timer_get_reload(timer_dev *dev) { - return (uint16)(dev->regs).bas->ARR; -} - -/** - * @brief Set a timer's reload value. - * @param dev Timer whose reload value to set - * @param arr New reload value to use. Takes effect at next update event. - * @see timer_generate_update() - */ -static inline void timer_set_reload(timer_dev *dev, uint16 arr) { - (dev->regs).bas->ARR = arr; -} - -/** - * @brief Get the compare value for the given timer channel. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel whose compare value to get. - */ -static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) { - __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1); - return *ccr; -} - -/** - * @brief Set the compare value for the given timer channel. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel whose compare value to set. - * @param value New compare value. - */ -static inline void timer_set_compare(timer_dev *dev, - uint8 channel, - uint16 value) { - __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1); - *ccr = value; -} - -/** - * @brief Generate an update event for the given timer. - * - * Normally, this will cause the prescaler and auto-reload values in - * the PSC and ARR registers to take immediate effect. However, this - * function will do nothing if the UDIS bit is set in the timer's CR1 - * register (UDIS is cleared by default). - * - * @param dev Timer device to generate an update for. - */ -static inline void timer_generate_update(timer_dev *dev) { - *bb_perip(&(dev->regs).bas->EGR, TIMER_EGR_UG_BIT) = 1; -} - -/** - * @brief Enable a timer's trigger DMA request - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL - */ -static inline void timer_dma_enable_trg_req(timer_dev *dev) { - *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 1; -} - -/** - * @brief Disable a timer's trigger DMA request - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL - */ -static inline void timer_dma_disable_trg_req(timer_dev *dev) { - *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 0; -} - -/** - * @brief Enable a timer channel's DMA request. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL - * @param channel Channel whose DMA request to enable. - */ -static inline void timer_dma_enable_req(timer_dev *dev, uint8 channel) { - *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 1; -} - -/** - * @brief Disable a timer channel's DMA request. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel whose DMA request to disable. - */ -static inline void timer_dma_disable_req(timer_dev *dev, uint8 channel) { - *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 0; -} - -/** - * @brief Enable a timer interrupt. - * @param dev Timer device. - * @param interrupt Interrupt number to enable; this may be any - * timer_interrupt_id value appropriate for the timer. - * @see timer_interrupt_id - * @see timer_channel - */ -static inline void timer_enable_irq(timer_dev *dev, uint8 interrupt) { - *bb_perip(&(dev->regs).adv->DIER, interrupt) = 1; -} - -/** - * @brief Disable a timer interrupt. - * @param dev Timer device. - * @param interrupt Interrupt number to disable; this may be any - * timer_interrupt_id value appropriate for the timer. - * @see timer_interrupt_id - * @see timer_channel - */ -static inline void timer_disable_irq(timer_dev *dev, uint8 interrupt) { - *bb_perip(&(dev->regs).adv->DIER, interrupt) = 0; -} - -/** - * @brief Enable a timer channel's capture/compare signal. - * - * If the channel is configured as output, the corresponding output - * compare signal will be output on the corresponding output pin. If - * the channel is configured as input, enables capture of the counter - * value into the input capture/compare register. - * - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel to enable, from 1 to 4. - */ -static inline void timer_cc_enable(timer_dev *dev, uint8 channel) { - *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 1; -} - -/** - * @brief Disable a timer channel's output compare or input capture signal. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel to disable, from 1 to 4. - * @see timer_cc_enable() - */ -static inline void timer_cc_disable(timer_dev *dev, uint8 channel) { - *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 0; -} - -/** - * @brief Get a channel's capture/compare output polarity - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel whose capture/compare output polarity to get. - * @return Polarity, either 0 or 1. - * @see timer_cc_set_polarity() - */ -static inline uint8 timer_cc_get_pol(timer_dev *dev, uint8 channel) { - return *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1); -} - -/** - * @brief Set a timer channel's capture/compare output polarity. - * - * If the timer channel is configured as output: polarity == 0 means - * the output channel will be active high; polarity == 1 means active - * low. - * - * If the timer channel is configured as input: polarity == 0 means - * capture is done on the rising edge of ICn; when used as an external - * trigger, ICn is non-inverted. polarity == 1 means capture is done - * on the falling edge of ICn; when used as an external trigger, ICn - * is inverted. - * - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel whose capture/compare output polarity to set. - * @param pol New polarity, 0 or 1. - */ -static inline void timer_cc_set_pol(timer_dev *dev, uint8 channel, uint8 pol) { - *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1) = pol; -} - -/** - * @brief Get a timer's DMA burst length. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @return Number of bytes to be transferred per DMA request, from 1 to 18. - */ -static inline uint8 timer_dma_get_burst_len(timer_dev *dev) { - uint32 dbl = ((dev->regs).gen->DCR & TIMER_DCR_DBL) >> 8; - return dbl + 1; /* 0 means 1 byte, etc. */ -} - -/** - * @brief Set a timer's DMA burst length. - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param length DMA burst length; i.e., number of bytes to transfer - * per DMA request, from 1 to 18. - */ -static inline void timer_dma_set_burst_len(timer_dev *dev, uint8 length) { - uint32 tmp = (dev->regs).gen->DCR; - tmp &= ~TIMER_DCR_DBL; - tmp |= (length - 1) << 8; - (dev->regs).gen->DCR = tmp; -} - -/** - * @brief Timer DMA base address. - * - * Defines the base address for DMA transfers. - */ -typedef enum timer_dma_base_addr { - TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, /**< Base is control register 1 */ - TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, /**< Base is control register 2 */ - TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, /**< Base is slave mode - control register */ - TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, /**< Base is DMA interrupt enable - register */ - TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, /**< Base is status register */ - TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, /**< Base is event generation - register */ - TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, /**< Base is capture/compare - mode register 1 */ - TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, /**< Base is capture/compare - mode register 2 */ - TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER, /**< Base is capture/compare - enable register */ - TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT, /**< Base is counter */ - TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC, /**< Base is prescaler */ - TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR, /**< Base is auto-reload - register */ - TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR, /**< Base is repetition - counter register */ - TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1, /**< Base is capture/compare - register 1 */ - TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2, /**< Base is capture/compare - register 2 */ - TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3, /**< Base is capture/compare - register 3 */ - TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4, /**< Base is capture/compare - register 4 */ - TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR, /**< Base is break and - dead-time register */ - TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR, /**< Base is DMA control - register */ - TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR /**< Base is DMA address for - full transfer */ -} timer_dma_base_addr; - -/** - * @brief Get the timer's DMA base address. - * - * Some restrictions apply; see ST RM0008. - * - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @return DMA base address - */ -static inline timer_dma_base_addr timer_dma_get_base_addr(timer_dev *dev) { - uint32 dcr = (dev->regs).gen->DCR; - return (timer_dma_base_addr)(dcr & TIMER_DCR_DBA); -} - -/** - * @brief Set the timer's DMA base address. - * - * Some restrictions apply; see ST RM0008. - * - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param dma_base DMA base address. - */ -static inline void timer_dma_set_base_addr(timer_dev *dev, - timer_dma_base_addr dma_base) { - uint32 tmp = (dev->regs).gen->DCR; - tmp &= ~TIMER_DCR_DBA; - tmp |= dma_base; - (dev->regs).gen->DCR = tmp; -} - -/** - * Timer output compare modes. - */ -typedef enum timer_oc_mode { - TIMER_OC_MODE_FROZEN = 0 << 4, /**< Frozen: comparison between output - compare register and counter has no - effect on the outputs. */ - TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, /**< OCxREF signal is forced - high when the count matches - the channel capture/compare - register. */ - TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, /**< OCxREF signal is forced - low when the counter matches - the channel capture/compare - register. */ - TIMER_OC_MODE_TOGGLE = 3 << 4, /**< OCxREF toggles when counter - matches the cannel capture/compare - register. */ - TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, /**< OCxREF is forced low. */ - TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, /**< OCxREF is forced high. */ - TIMER_OC_MODE_PWM_1 = 6 << 4, /**< PWM mode 1. In upcounting, channel is - active as long as count is less than - channel capture/compare register, else - inactive. In downcounting, channel is - inactive as long as count exceeds - capture/compare register, else - active. */ - TIMER_OC_MODE_PWM_2 = 7 << 4 /**< PWM mode 2. In upcounting, channel is - inactive as long as count is less than - capture/compare register, else active. - In downcounting, channel is active as - long as count exceeds capture/compare - register, else inactive. */ -} timer_oc_mode; - -/** - * Timer output compare mode flags. - * @see timer_oc_set_mode() - */ -typedef enum timer_oc_mode_flags { - TIMER_OC_CE = BIT(7), /**< Output compare clear enable. */ - TIMER_OC_PE = BIT(3), /**< Output compare preload enable. */ - TIMER_OC_FE = BIT(2) /**< Output compare fast enable. */ -} timer_oc_mode_flags; - -/** - * @brief Configure a channel's output compare mode. - * - * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param channel Channel to configure in output compare mode. - * @param mode Timer mode to set. - * @param flags OR of timer_oc_mode_flags. - * @see timer_oc_mode - * @see timer_oc_mode_flags - */ -static inline void timer_oc_set_mode(timer_dev *dev, - uint8 channel, - timer_oc_mode mode, - uint8 flags) { - /* channel == 1,2 -> CCMR1; channel == 3,4 -> CCMR2 */ - __io uint32 *ccmr = &(dev->regs).gen->CCMR1 + (((channel - 1) >> 1) & 1); - /* channel == 1,3 -> shift = 0, channel == 2,4 -> shift = 8 */ - uint8 shift = 8 * (1 - (channel & 1)); - - uint32 tmp = *ccmr; - tmp &= ~(0xFF << shift); - tmp |= (mode | flags | TIMER_CCMR_CCS_OUTPUT) << shift; - *ccmr = tmp; -} - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libmaple/usart.c b/libmaple/usart.c index 0bdc37a..ba63b79 100644 --- a/libmaple/usart.c +++ b/libmaple/usart.c @@ -31,7 +31,7 @@ * @brief USART control routines */ -#include "usart.h" +#include /* * Devices diff --git a/libmaple/usart.h b/libmaple/usart.h deleted file mode 100644 index ed00e16..0000000 --- a/libmaple/usart.h +++ /dev/null @@ -1,336 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file usart.h - * @author Marti Bolivar , - * Perry Hung - * @brief USART definitions and prototypes - */ - -#ifndef _USART_H_ -#define _USART_H_ - -#include "libmaple_types.h" -#include "util.h" -#include "rcc.h" -#include "nvic.h" -#include "ring_buffer.h" - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Register maps and devices - */ - -/** USART register map type */ -typedef struct usart_reg_map { - __io uint32 SR; /**< Status register */ - __io uint32 DR; /**< Data register */ - __io uint32 BRR; /**< Baud rate register */ - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 CR3; /**< Control register 3 */ - __io uint32 GTPR; /**< Guard time and prescaler register */ -} usart_reg_map; - -/** USART1 register map base pointer */ -#define USART1_BASE ((struct usart_reg_map*)0x40013800) -/** USART2 register map base pointer */ -#define USART2_BASE ((struct usart_reg_map*)0x40004400) -/** USART3 register map base pointer */ -#define USART3_BASE ((struct usart_reg_map*)0x40004800) -#ifdef STM32_HIGH_DENSITY -/** UART4 register map base pointer */ -#define UART4_BASE ((struct usart_reg_map*)0x40004C00) -/** UART5 register map base pointer */ -#define UART5_BASE ((struct usart_reg_map*)0x40005000) -#endif - -/* - * Register bit definitions - */ - -/* Status register */ - -#define USART_SR_CTS_BIT 9 -#define USART_SR_LBD_BIT 8 -#define USART_SR_TXE_BIT 7 -#define USART_SR_TC_BIT 6 -#define USART_SR_RXNE_BIT 5 -#define USART_SR_IDLE_BIT 4 -#define USART_SR_ORE_BIT 3 -#define USART_SR_NE_BIT 2 -#define USART_SR_FE_BIT 1 -#define USART_SR_PE_BIT 0 - -#define USART_SR_CTS BIT(USART_SR_CTS_BIT) -#define USART_SR_LBD BIT(USART_SR_LBD_BIT) -#define USART_SR_TXE BIT(USART_SR_TXE_BIT) -#define USART_SR_TC BIT(USART_SR_TC_BIT) -#define USART_SR_RXNE BIT(USART_SR_RXNE_BIT) -#define USART_SR_IDLE BIT(USART_SR_IDLE_BIT) -#define USART_SR_ORE BIT(USART_SR_ORE_BIT) -#define USART_SR_NE BIT(USART_SR_NE_BIT) -#define USART_SR_FE BIT(USART_SR_FE_BIT) -#define USART_SR_PE BIT(USART_SR_PE_BIT) - -/* Data register */ - -#define USART_DR_DR 0xFF - -/* Baud rate register */ - -#define USART_BRR_DIV_MANTISSA (0xFFF << 4) -#define USART_BRR_DIV_FRACTION 0xF - -/* Control register 1 */ - -#define USART_CR1_UE_BIT 13 -#define USART_CR1_M_BIT 12 -#define USART_CR1_WAKE_BIT 11 -#define USART_CR1_PCE_BIT 10 -#define USART_CR1_PS_BIT 9 -#define USART_CR1_PEIE_BIT 8 -#define USART_CR1_TXEIE_BIT 7 -#define USART_CR1_TCIE_BIT 6 -#define USART_CR1_RXNEIE_BIT 5 -#define USART_CR1_IDLEIE_BIT 4 -#define USART_CR1_TE_BIT 3 -#define USART_CR1_RE_BIT 2 -#define USART_CR1_RWU_BIT 1 -#define USART_CR1_SBK_BIT 0 - -#define USART_CR1_UE BIT(USART_CR1_UE_BIT) -#define USART_CR1_M BIT(USART_CR1_M_BIT) -#define USART_CR1_WAKE BIT(USART_CR1_WAKE_BIT) -#define USART_CR1_WAKE_IDLE (0 << USART_CR1_WAKE_BIT) -#define USART_CR1_WAKE_ADDR (1 << USART_CR1_WAKE_BIT) -#define USART_CR1_PCE BIT(USART_CR1_PCE_BIT) -#define USART_CR1_PS BIT(USART_CR1_PS_BIT) -#define USART_CR1_PS_EVEN (0 << USART_CR1_PS_BIT) -#define USART_CR1_PS_ODD (1 << USART_CR1_PS_BIT) -#define USART_CR1_PEIE BIT(USART_CR1_PEIE_BIT) -#define USART_CR1_TXEIE BIT(USART_CR1_TXEIE_BIT) -#define USART_CR1_TCIE BIT(USART_CR1_TCIE_BIT) -#define USART_CR1_RXNEIE BIT(USART_CR1_RXNEIE_BIT) -#define USART_CR1_IDLEIE BIT(USART_CR1_IDLEIE_BIT) -#define USART_CR1_TE BIT(USART_CR1_TE_BIT) -#define USART_CR1_RE BIT(USART_CR1_RE_BIT) -#define USART_CR1_RWU BIT(USART_CR1_RWU_BIT) -#define USART_CR1_RWU_ACTIVE (0 << USART_CR1_RWU_BIT) -#define USART_CR1_RWU_MUTE (1 << USART_CR1_RWU_BIT) -#define USART_CR1_SBK BIT(USART_CR1_SBK_BIT) - -/* Control register 2 */ - -#define USART_CR2_LINEN_BIT 14 -#define USART_CR2_CLKEN_BIT 11 -#define USART_CR2_CPOL_BIT 10 -#define USART_CR2_CPHA_BIT 9 -#define USART_CR2_LBCL_BIT 8 -#define USART_CR2_LBDIE_BIT 6 -#define USART_CR2_LBDL_BIT 5 - -#define USART_CR2_LINEN BIT(USART_CR2_LINEN_BIT) -#define USART_CR2_STOP (0x3 << 12) -#define USART_CR2_STOP_BITS_1 (0x0 << 12) -/* Not on UART4, UART5 */ -#define USART_CR2_STOP_BITS_POINT_5 (0x1 << 12) -/* Not on UART4, UART5 */ -#define USART_CR2_STOP_BITS_1_POINT_5 (0x3 << 12) -#define USART_CR2_STOP_BITS_2 (0x2 << 12) -#define USART_CR2_CLKEN BIT(USART_CR2_CLKEN_BIT) -/* Not on UART4, UART5 */ -#define USART_CR2_CPOL BIT(USART_CR2_CPOL_BIT) -#define USART_CR2_CPOL_LOW (0x0 << USART_CR2_CLKEN_BIT) -#define USART_CR2_CPOL_HIGH (0x1 << USART_CR2_CLKEN_BIT) -/* Not on UART4, UART5 */ -#define USART_CR2_CPHA BIT(USART_CR2_CPHA_BIT) -#define USART_CR2_CPHA_FIRST (0x0 << USART_CR2_CPHA_BIT) -#define USART_CR2_CPHA_SECOND (0x1 << USART_CR2_CPHA_BIT) -/* Not on UART4, UART5 */ -#define USART_CR2_LBCL BIT(USART_CR2_LBCL_BIT) -#define USART_CR2_LBDIE BIT(USART_CR2_LBDIE_BIT) -#define USART_CR2_LBDL BIT(USART_CR2_LBDL_BIT) -#define USART_CR2_LBDL_10_BIT (0 << USART_CR2_LBDL_BIT) -#define USART_CR2_LBDL_11_BIT (1 << USART_CR2_LBDL_BIT) -#define USART_CR2_ADD 0xF - -/* Control register 3 */ - -#define USART_CR3_CTSIE_BIT 10 -#define USART_CR3_CTSE_BIT 9 -#define USART_CR3_RTSE_BIT 8 -#define USART_CR3_DMAT_BIT 7 -#define USART_CR3_DMAR_BIT 6 -#define USART_CR3_SCEN_BIT 5 -#define USART_CR3_NACK_BIT 4 -#define USART_CR3_HDSEL_BIT 3 -#define USART_CR3_IRLP_BIT 2 -#define USART_CR3_IREN_BIT 1 -#define USART_CR3_EIE_BIT 0 - -/* Not on UART4, UART5 */ -#define USART_CR3_CTSIE BIT(USART_CR3_CTSIE_BIT) -/* Not on UART4, UART5 */ -#define USART_CR3_CTSE BIT(USART_CR3_CTSE_BIT) -/* Not on UART4, UART5 */ -#define USART_CR3_RTSE BIT(USART_CR3_RTSE_BIT) -/* Not on UART5 */ -#define USART_CR3_DMAT BIT(USART_CR3_DMAT_BIT) -/* Not on UART5 */ -#define USART_CR3_DMAR BIT(USART_CR3_DMAR_BIT) -/* Not on UART4, UART5 */ -#define USART_CR3_SCEN BIT(USART_CR3_SCEN_BIT) -/* Not on UART4, UART5 */ -#define USART_CR3_NACK BIT(USART_CR3_NACK_BIT) -#define USART_CR3_HDSEL BIT(USART_CR3_HDSEL_BIT) -#define USART_CR3_IRLP BIT(USART_CR3_IRLP_BIT) -#define USART_CR3_IRLP_NORMAL (0 << USART_CR3_IRLP_BIT) -#define USART_CR3_IRLP_LOW_POWER (1 << USART_CR3_IRLP_BIT) -#define USART_CR3_IREN BIT(USART_CR3_IREN_BIT) -#define USART_CR3_EIE BIT(USART_CR3_EIE_BIT) - -/* Guard time and prescaler register */ - -/* Not on UART4, UART5 */ -#define USART_GTPR_GT (0xFF << 8) -/* Not on UART4, UART5 */ -#define USART_GTPR_PSC 0xFF - -/* - * Devices - */ - -#ifndef USART_RX_BUF_SIZE -#define USART_RX_BUF_SIZE 64 -#endif - -/** USART device type */ -typedef struct usart_dev { - usart_reg_map *regs; /**< Register map */ - ring_buffer *rb; /**< RX ring buffer */ - uint32 max_baud; /**< Maximum baud */ - uint8 rx_buf[USART_RX_BUF_SIZE]; /**< @brief Deprecated. - * Actual RX buffer used by rb. - * This field will be removed in - * a future release. */ - rcc_clk_id clk_id; /**< RCC clock information */ - nvic_irq_num irq_num; /**< USART NVIC interrupt */ -} usart_dev; - -extern usart_dev *USART1; -extern usart_dev *USART2; -extern usart_dev *USART3; -#ifdef STM32_HIGH_DENSITY -extern usart_dev *UART4; -extern usart_dev *UART5; -#endif - -void usart_init(usart_dev *dev); -void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud); -void usart_enable(usart_dev *dev); -void usart_disable(usart_dev *dev); -void usart_foreach(void (*fn)(usart_dev *dev)); -uint32 usart_tx(usart_dev *dev, const uint8 *buf, uint32 len); -uint32 usart_rx(usart_dev *dev, uint8 *buf, uint32 len); -void usart_putudec(usart_dev *dev, uint32 val); - -/** - * @brief Disable all serial ports. - */ -static inline void usart_disable_all(void) { - usart_foreach(usart_disable); -} - -/** - * @brief Transmit one character on a serial port. - * - * This function blocks until the character has been successfully - * transmitted. - * - * @param dev Serial port to send on. - * @param byte Byte to transmit. - */ -static inline void usart_putc(usart_dev* dev, uint8 byte) { - while (!usart_tx(dev, &byte, 1)) - ; -} - -/** - * @brief Transmit a character string on a serial port. - * - * This function blocks until str is completely transmitted. - * - * @param dev Serial port to send on - * @param str String to send - */ -static inline void usart_putstr(usart_dev *dev, const char* str) { - uint32 i = 0; - while (str[i] != '\0') { - usart_putc(dev, str[i++]); - } -} - -/** - * @brief Read one character from a serial port. - * - * It's not safe to call this function if the serial port has no data - * available. - * - * @param dev Serial port to read from - * @return byte read - * @see usart_data_available() - */ -static inline uint8 usart_getc(usart_dev *dev) { - return rb_remove(dev->rb); -} - -/** - * @brief Return the amount of data available in a serial port's RX buffer. - * @param dev Serial port to check - * @return Number of bytes in dev's RX buffer. - */ -static inline uint32 usart_data_available(usart_dev *dev) { - return rb_full_count(dev->rb); -} - -/** - * @brief Discard the contents of a serial port's RX buffer. - * @param dev Serial port whose buffer to empty. - */ -static inline void usart_reset_rx(usart_dev *dev) { - rb_reset(dev->rb); -} - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif // _USART_H_ diff --git a/libmaple/usb.h b/libmaple/usb.h deleted file mode 100644 index 94579ea..0000000 --- a/libmaple/usb.h +++ /dev/null @@ -1,82 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/* - * NOTE: This API is _unstable_ and will change drastically over time. - */ - -#ifndef _USB_H_ -#define _USB_H_ - -#include "libmaple_types.h" -#include "rcc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef USB_ISR_MSK -/* Handle CTRM, WKUPM, SUSPM, ERRM, SOFM, ESOFM, RESETM */ -#define USB_ISR_MSK 0xBF00 -#endif - -typedef enum usb_dev_state { - USB_UNCONNECTED, - USB_ATTACHED, - USB_POWERED, - USB_SUSPENDED, - USB_ADDRESSED, - USB_CONFIGURED -} usb_dev_state; - -/* Encapsulates global state formerly handled by usb_lib/ */ -typedef struct usblib_dev { - uint32 irq_mask; - void (**ep_int_in)(void); - void (**ep_int_out)(void); - usb_dev_state state; - rcc_clk_id clk_id; -} usblib_dev; - -extern usblib_dev *USBLIB; - -void usb_init_usblib(usblib_dev *dev, - void (**ep_int_in)(void), - void (**ep_int_out)(void)); - -static inline uint8 usb_is_connected(usblib_dev *dev) { - return dev->state != USB_UNCONNECTED; -} - -static inline uint8 usb_is_configured(usblib_dev *dev) { - return dev->state == USB_CONFIGURED; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/usb/usb_cdcacm.h b/libmaple/usb/usb_cdcacm.h index 8ca1c68..ec672a3 100644 --- a/libmaple/usb/usb_cdcacm.h +++ b/libmaple/usb/usb_cdcacm.h @@ -32,8 +32,8 @@ #ifndef _USB_CDCACM_H_ #define _USB_CDCACM_H_ -#include "libmaple_types.h" -#include "gpio.h" +#include +#include #ifdef __cplusplus extern "C" { diff --git a/libmaple/util.c b/libmaple/util.c index b15d658..07e9572 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -30,12 +30,12 @@ * and messages dumped over a UART for failed asserts. */ -#include "libmaple.h" -#include "usart.h" -#include "gpio.h" -#include "nvic.h" -#include "adc.h" -#include "timer.h" +#include +#include +#include +#include +#include +#include /* Failed ASSERT()s send out a message using this USART config. */ #ifndef ERROR_USART diff --git a/libmaple/util.h b/libmaple/util.h deleted file mode 100644 index 7b41769..0000000 --- a/libmaple/util.h +++ /dev/null @@ -1,111 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file util.h - * @brief Miscellaneous utility macros and procedures. - */ - -#include "libmaple_types.h" - -#ifndef _UTIL_H_ -#define _UTIL_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Bit manipulation - */ - -/** 1 << the bit number */ -#define BIT(shift) (1UL << (shift)) -/** Mask shifted left by 'shift' */ -#define BIT_MASK_SHIFT(mask, shift) ((mask) << (shift)) -/** Bits m to n of x */ -#define GET_BITS(x, m, n) ((((uint32)x) << (31 - (n))) >> ((31 - (n)) + (m))) -/** True if v is a power of two (1, 2, 4, 8, ...) */ -#define IS_POWER_OF_TWO(v) ((v) && !((v) & ((v) - 1))) - -/* - * Failure routines - */ - -void __error(void); -void _fail(const char*, int, const char*); -void throb(void); - -/* - * Asserts and debug levels - */ - -#define DEBUG_NONE 0 -#define DEBUG_FAULT 1 -#define DEBUG_ALL 2 - -/** - * \def DEBUG_LEVEL - * - * Controls the level of assertion checking. - * - * The higher the debug level, the more assertions will be compiled - * in. This increases the amount of debugging information, but slows - * down (and increases the size of) the binary. - * - * The debug levels, from lowest to highest, are DEBUG_NONE, - * DEBUG_FAULT, and DEBUG_ALL. The default level is DEBUG_ALL. - */ - -#ifndef DEBUG_LEVEL -#define DEBUG_LEVEL DEBUG_ALL -#endif - -#if DEBUG_LEVEL >= DEBUG_ALL -#define ASSERT(exp) \ - if (exp) { \ - } else { \ - _fail(__FILE__, __LINE__, #exp); \ - } -#else -#define ASSERT(exp) (void)((0)) -#endif - -#if DEBUG_LEVEL >= DEBUG_FAULT -#define ASSERT_FAULT(exp) \ - if (exp) { \ - } else { \ - _fail(__FILE__, __LINE__, #exp); \ - } -#else -#define ASSERT_FAULT(exp) (void)((0)) -#endif - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif diff --git a/libraries/FreeRTOS/MapleFreeRTOS.h b/libraries/FreeRTOS/MapleFreeRTOS.h index 839e3e2..dc06979 100644 --- a/libraries/FreeRTOS/MapleFreeRTOS.h +++ b/libraries/FreeRTOS/MapleFreeRTOS.h @@ -27,7 +27,7 @@ #ifndef __MAPLE_FREERTOS_H__ #define __MAPLE_FREERTOS_H__ -#include "wirish.h" +#include extern "C" { #define GCC_ARMCM3 diff --git a/libraries/LiquidCrystal/LiquidCrystal.cpp b/libraries/LiquidCrystal/LiquidCrystal.cpp index 85e19ef..5cfb1ca 100644 --- a/libraries/LiquidCrystal/LiquidCrystal.cpp +++ b/libraries/LiquidCrystal/LiquidCrystal.cpp @@ -2,7 +2,7 @@ #include #include -#include "WProgram.h" +#include // When the display powers up, it is configured as follows: // diff --git a/libraries/LiquidCrystal/LiquidCrystal.h b/libraries/LiquidCrystal/LiquidCrystal.h index 0baf543..06a159d 100644 --- a/libraries/LiquidCrystal/LiquidCrystal.h +++ b/libraries/LiquidCrystal/LiquidCrystal.h @@ -2,8 +2,8 @@ #define LiquidCrystal_h //#include -#include "wirish.h" -#include "Print.h" +#include +#include // commands #define LCD_CLEARDISPLAY 0x01 diff --git a/libraries/Servo/Servo.cpp b/libraries/Servo/Servo.cpp index 8fbd366..ecb85e6 100644 --- a/libraries/Servo/Servo.cpp +++ b/libraries/Servo/Servo.cpp @@ -26,10 +26,10 @@ #include "Servo.h" -#include "boards.h" -#include "io.h" -#include "pwm.h" -#include "wirish_math.h" +#include +#include +#include +#include // 20 millisecond period config. For a 1-based prescaler, // diff --git a/libraries/Servo/Servo.h b/libraries/Servo/Servo.h index 7753b4b..94e1e00 100644 --- a/libraries/Servo/Servo.h +++ b/libraries/Servo/Servo.h @@ -27,14 +27,10 @@ #ifndef _SERVO_H_ #define _SERVO_H_ -#include "libmaple_types.h" -#include "timer.h" +#include +#include -#include "wirish_types.h" - -#ifdef MAPLE_IDE -#include "wirish.h" /* hack for IDE compile */ -#endif +#include /* * Note on Arduino compatibility: diff --git a/libraries/Wire/Wire.cpp b/libraries/Wire/Wire.cpp index 753f831..8416525 100644 --- a/libraries/Wire/Wire.cpp +++ b/libraries/Wire/Wire.cpp @@ -30,7 +30,6 @@ */ #include "Wire.h" -#include "wirish.h" /* low level conventions: * - SDA/SCL idle high (expected high) diff --git a/libraries/Wire/Wire.h b/libraries/Wire/Wire.h index d2f3608..0640c3b 100644 --- a/libraries/Wire/Wire.h +++ b/libraries/Wire/Wire.h @@ -29,11 +29,11 @@ * interface to I2C (two-wire) communication. */ -#include "wirish.h" - #ifndef _WIRE_H_ #define _WIRE_H_ +#include + typedef struct { uint8 scl; uint8 sda; diff --git a/main.cpp.example b/main.cpp.example index 23d5540..4e44489 100644 --- a/main.cpp.example +++ b/main.cpp.example @@ -1,7 +1,7 @@ // Sample main.cpp file. Blinks the built-in LED, sends a message out // USART2, and turns on PWM on pin 2. -#include "wirish.h" +#include #define PWM_PIN 2 diff --git a/wirish/HardwareTimer.cpp b/wirish/HardwareTimer.cpp index bd61a89..52257bf 100644 --- a/wirish/HardwareTimer.cpp +++ b/wirish/HardwareTimer.cpp @@ -24,9 +24,9 @@ * SOFTWARE. *****************************************************************************/ -#include "HardwareTimer.h" -#include "boards.h" // for CYCLES_PER_MICROSECOND -#include "wirish_math.h" +#include +#include // for CYCLES_PER_MICROSECOND +#include // TODO [0.1.0] Remove deprecated pieces diff --git a/wirish/HardwareTimer.h b/wirish/HardwareTimer.h deleted file mode 100644 index 1c34b9d..0000000 --- a/wirish/HardwareTimer.h +++ /dev/null @@ -1,331 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Bryan Newbold. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @brief Wirish timer class. - */ - -#ifndef _HARDWARETIMER_H_ -#define _HARDWARETIMER_H_ - -// TODO [0.1.0] Remove deprecated pieces, pick a better API - -#include "timer.h" - -/** Timer mode. */ -typedef timer_mode TimerMode; - -/** @brief Deprecated; use TIMER_OUTPUT_COMPARE instead. */ -#define TIMER_OUTPUTCOMPARE TIMER_OUTPUT_COMPARE - -/** - * @brief Interface to one of the 16-bit timer peripherals. - */ -class HardwareTimer { -private: - timer_dev *dev; - -public: - /** - * @brief Construct a new HardwareTimer instance. - * @param timerNum number of the timer to control. - */ - HardwareTimer(uint8 timerNum); - - /** - * @brief Stop the counter, without affecting its configuration. - * - * @see HardwareTimer::resume() - */ - void pause(void); - - /** - * @brief Resume a paused timer, without affecting its configuration. - * - * The timer will resume counting and firing interrupts as - * appropriate. - * - * Note that there is some function call overhead associated with - * using this method, so using it in concert with - * HardwareTimer::pause() is not a robust way to align multiple - * timers to the same count value. - * - * @see HardwareTimer::pause() - */ - void resume(void); - - /** - * @brief Get the timer's prescale factor. - * @return Timer prescaler, from 1 to 65,536. - * @see HardwareTimer::setPrescaleFactor() - */ - uint32 getPrescaleFactor(); - - /** - * @brief Set the timer's prescale factor. - * - * The new value won't take effect until the next time the counter - * overflows. You can force the counter to reset using - * HardwareTimer::refresh(). - * - * @param factor The new prescale value to set, from 1 to 65,536. - * @see HardwareTimer::refresh() - */ - void setPrescaleFactor(uint32 factor); - - /** - * @brief Get the timer overflow value. - * @see HardwareTimer::setOverflow() - */ - uint16 getOverflow(); - - /** - * @brief Set the timer overflow (or "reload") value. - * - * The new value won't take effect until the next time the counter - * overflows. You can force the counter to reset using - * HardwareTimer::refresh(). - * - * @param val The new overflow value to set - * @see HardwareTimer::refresh() - */ - void setOverflow(uint16 val); - - /** - * @brief Get the current timer count. - * - * @return The timer's current count value - */ - uint16 getCount(void); - - /** - * @brief Set the current timer count. - * - * @param val The new count value to set. If this value exceeds - * the timer's overflow value, it is truncated to the - * overflow value. - */ - void setCount(uint16 val); - - /** - * @brief Set the timer's period in microseconds. - * - * Configures the prescaler and overflow values to generate a timer - * reload with a period as close to the given number of - * microseconds as possible. - * - * @param microseconds The desired period of the timer. This must be - * greater than zero. - * @return The new overflow value. - */ - uint16 setPeriod(uint32 microseconds); - - /** - * @brief Configure a timer channel's mode. - * @param channel Timer channel, from 1 to 4 - * @param mode Mode to set - */ - void setMode(int channel, timer_mode mode); - - /** - * @brief Get the compare value for the given channel. - * @see HardwareTimer::setCompare() - */ - uint16 getCompare(int channel); - - /** - * @brief Set the compare value for the given channel. - * - * @param channel the channel whose compare to set, from 1 to 4. - * @param compare The compare value to set. If greater than this - * timer's overflow value, it will be truncated to - * the overflow value. - * - * @see timer_mode - * @see HardwareTimer::setMode() - * @see HardwareTimer::attachInterrupt() - */ - void setCompare(int channel, uint16 compare); - - /** - * @brief Attach an interrupt handler to the given channel. - * - * This interrupt handler will be called when the timer's counter - * reaches the given channel compare value. - * - * @param channel the channel to attach the ISR to, from 1 to 4. - * @param handler The ISR to attach to the given channel. - * @see voidFuncPtr - */ - void attachInterrupt(int channel, voidFuncPtr handler); - - /** - * @brief Remove the interrupt handler attached to the given - * channel, if any. - * - * The handler will no longer be called by this timer. - * - * @param channel the channel whose interrupt to detach, from 1 to 4. - * @see HardwareTimer::attachInterrupt() - */ - void detachInterrupt(int channel); - - /** - * @brief Reset the counter, and update the prescaler and overflow - * values. - * - * This will reset the counter to 0 in upcounting mode (the - * default). It will also update the timer's prescaler and - * overflow, if you have set them up to be changed using - * HardwareTimer::setPrescaleFactor() or - * HardwareTimer::setOverflow(). - * - * @see HardwareTimer::setPrescaleFactor() - * @see HardwareTimer::setOverflow() - */ - void refresh(void); - - /* -- Deprecated methods ----------------------------------------------- */ - - /** @brief Deprecated; use setMode(channel, mode) instead. */ - void setChannelMode(int channel, timer_mode mode) { - setMode(channel, mode); - } - - /** @brief Deprecated; use setMode(TIMER_CH1, mode) instead. */ - void setChannel1Mode(timer_mode mode) { setMode(TIMER_CH1, mode); } - - /** @brief Deprecated; use setMode(TIMER_CH2, mode) instead. */ - void setChannel2Mode(timer_mode mode) { setMode(TIMER_CH2, mode); } - - /** @brief Deprecated; use setMode(TIMER_CH3, mode) instead. */ - void setChannel3Mode(timer_mode mode) { setMode(TIMER_CH3, mode); } - - /** @brief Deprecated; use setMode(TIMER_CH4, mode) instead. */ - void setChannel4Mode(timer_mode mode) { setMode(TIMER_CH4, mode); } - - /** @brief Deprecated; use return getCompare(TIMER_CH1) instead. */ - uint16 getCompare1() { return getCompare(TIMER_CH1); } - - /** @brief Deprecated; use return getCompare(TIMER_CH2) instead. */ - uint16 getCompare2() { return getCompare(TIMER_CH2); } - - /** @brief Deprecated; use return getCompare(TIMER_CH3) instead. */ - uint16 getCompare3() { return getCompare(TIMER_CH3); } - - /** @brief Deprecated; use return getCompare(TIMER_CH4) instead. */ - uint16 getCompare4() { return getCompare(TIMER_CH4); } - - /** @brief Deprecated; use setCompare(TIMER_CH1, compare) instead. */ - void setCompare1(uint16 compare) { setCompare(TIMER_CH1, compare); } - - /** @brief Deprecated; use setCompare(TIMER_CH2, compare) instead. */ - void setCompare2(uint16 compare) { setCompare(TIMER_CH2, compare); } - - /** @brief Deprecated; use setCompare(TIMER_CH3, compare) instead. */ - void setCompare3(uint16 compare) { setCompare(TIMER_CH3, compare); } - - /** @brief Deprecated; use setCompare(TIMER_CH4, compare) instead. */ - void setCompare4(uint16 compare) { setCompare(TIMER_CH4, compare); } - - /** @brief Deprecated; use attachInterrupt(TIMER_CH1, handler) instead. */ - void attachCompare1Interrupt(voidFuncPtr handler) { - attachInterrupt(TIMER_CH1, handler); - } - - /** @brief Deprecated; use attachInterrupt(TIMER_CH2, handler) instead. */ - void attachCompare2Interrupt(voidFuncPtr handler) { - attachInterrupt(TIMER_CH2, handler); - } - - /** @brief Deprecated; use attachInterrupt(TIMER_CH3, handler) instead. */ - void attachCompare3Interrupt(voidFuncPtr handler) { - attachInterrupt(TIMER_CH3, handler); - } - - /** @brief Deprecated; use attachInterrupt(TIMER_CH4, handler) instead. */ - void attachCompare4Interrupt(voidFuncPtr handler) { - attachInterrupt(TIMER_CH4, handler); - } - - /** @brief Deprecated; use detachInterrupt(TIMER_CH1) instead. */ - void detachCompare1Interrupt(void) { detachInterrupt(TIMER_CH1); } - - /** @brief Deprecated; use detachInterrupt(TIMER_CH2) instead. */ - void detachCompare2Interrupt(void) { detachInterrupt(TIMER_CH2); } - - /** @brief Deprecated; use detachInterrupt(TIMER_CH3) instead. */ - void detachCompare3Interrupt(void) { detachInterrupt(TIMER_CH3); } - - /** @brief Deprecated; use detachInterrupt(TIMER_CH4) instead. */ - void detachCompare4Interrupt(void) { detachInterrupt(TIMER_CH4); } - - /** @brief Deprecated; use refresh() instead. */ - void generateUpdate(void) { refresh(); } -}; - -/* -- The rest of this file is deprecated. --------------------------------- */ - -/** - * @brief Deprecated. - * - * Pre-instantiated timer. - */ -extern HardwareTimer Timer1; -/** - * @brief Deprecated. - * - * Pre-instantiated timer. - */ -extern HardwareTimer Timer2; -/** - * @brief Deprecated. - * - * Pre-instantiated timer. - */ -extern HardwareTimer Timer3; -/** - * @brief Deprecated. - * - * Pre-instantiated timer. - */ -extern HardwareTimer Timer4; -#ifdef STM32_HIGH_DENSITY -/** - * @brief Deprecated. - * - * Pre-instantiated timer. - */ -extern HardwareTimer Timer5; -/** - * @brief Deprecated. - * - * Pre-instantiated timer. - */ -extern HardwareTimer Timer8; -#endif - -#endif diff --git a/wirish/Print.cpp b/wirish/Print.cpp index 58c7cc7..1a2bddb 100644 --- a/wirish/Print.cpp +++ b/wirish/Print.cpp @@ -21,8 +21,9 @@ * Modified 12 April 2011 by Marti Bolivar */ -#include "Print.h" +#include +#include #include #ifndef LLONG_MAX @@ -40,8 +41,6 @@ #define LLONG_MAX 9223372036854775807LL #endif -#include "wirish_math.h" - /* * Public methods */ diff --git a/wirish/Print.h b/wirish/Print.h deleted file mode 100644 index c0c63cb..0000000 --- a/wirish/Print.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Print.h - Base class that provides print() and println() - * Copyright (c) 2008 David A. Mellis. All right reserved. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA. - * - * Modified 12 April 2011 by Marti Bolivar - */ - -#ifndef _PRINT_H_ -#define _PRINT_H_ - -#include "libmaple_types.h" - -enum { - BYTE = 0, - BIN = 2, - OCT = 8, - DEC = 10, - HEX = 16 -}; - -class Print { -public: - virtual void write(uint8 ch) = 0; - virtual void write(const char *str); - virtual void write(const void *buf, uint32 len); - void print(char); - void print(const char[]); - void print(uint8, int=DEC); - void print(int, int=DEC); - void print(unsigned int, int=DEC); - void print(long, int=DEC); - void print(unsigned long, int=DEC); - void print(long long, int=DEC); - void print(unsigned long long, int=DEC); - void print(double, int=2); - void println(void); - void println(char); - void println(const char[]); - void println(uint8, int=DEC); - void println(int, int=DEC); - void println(unsigned int, int=DEC); - void println(long, int=DEC); - void println(unsigned long, int=DEC); - void println(long long, int=DEC); - void println(unsigned long long, int=DEC); - void println(double, int=2); -private: - void printNumber(unsigned long long, uint8); - void printFloat(double, uint8); -}; - -#endif diff --git a/wirish/WProgram.h b/wirish/WProgram.h deleted file mode 100644 index 2949a0a..0000000 --- a/wirish/WProgram.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -#include "wirish.h" - -void setup(); -void loop(); diff --git a/wirish/bit_constants.h b/wirish/bit_constants.h deleted file mode 100644 index 8accc6b..0000000 --- a/wirish/bit_constants.h +++ /dev/null @@ -1,579 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @brief BIT[n] and binary literal defines, for Arduino - * compatibility. - */ - -#ifndef _BIT_CONSTANTS_H_ -#define _BIT_CONSTANTS_H_ - -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) -#define BIT8 (1 << 8) -#define BIT9 (1 << 9) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - -#define B0 0 -#define B00 0 -#define B000 0 -#define B0000 0 -#define B00000 0 -#define B000000 0 -#define B0000000 0 -#define B00000000 0 -#define B1 1 -#define B01 1 -#define B001 1 -#define B0001 1 -#define B00001 1 -#define B000001 1 -#define B0000001 1 -#define B00000001 1 -#define B10 2 -#define B010 2 -#define B0010 2 -#define B00010 2 -#define B000010 2 -#define B0000010 2 -#define B00000010 2 -#define B11 3 -#define B011 3 -#define B0011 3 -#define B00011 3 -#define B000011 3 -#define B0000011 3 -#define B00000011 3 -#define B100 4 -#define B0100 4 -#define B00100 4 -#define B000100 4 -#define B0000100 4 -#define B00000100 4 -#define B101 5 -#define B0101 5 -#define B00101 5 -#define B000101 5 -#define B0000101 5 -#define B00000101 5 -#define B110 6 -#define B0110 6 -#define B00110 6 -#define B000110 6 -#define B0000110 6 -#define B00000110 6 -#define B111 7 -#define B0111 7 -#define B00111 7 -#define B000111 7 -#define B0000111 7 -#define B00000111 7 -#define B1000 8 -#define B01000 8 -#define B001000 8 -#define B0001000 8 -#define B00001000 8 -#define B1001 9 -#define B01001 9 -#define B001001 9 -#define B0001001 9 -#define B00001001 9 -#define B1010 10 -#define B01010 10 -#define B001010 10 -#define B0001010 10 -#define B00001010 10 -#define B1011 11 -#define B01011 11 -#define B001011 11 -#define B0001011 11 -#define B00001011 11 -#define B1100 12 -#define B01100 12 -#define B001100 12 -#define B0001100 12 -#define B00001100 12 -#define B1101 13 -#define B01101 13 -#define B001101 13 -#define B0001101 13 -#define B00001101 13 -#define B1110 14 -#define B01110 14 -#define B001110 14 -#define B0001110 14 -#define B00001110 14 -#define B1111 15 -#define B01111 15 -#define B001111 15 -#define B0001111 15 -#define B00001111 15 -#define B10000 16 -#define B010000 16 -#define B0010000 16 -#define B00010000 16 -#define B10001 17 -#define B010001 17 -#define B0010001 17 -#define B00010001 17 -#define B10010 18 -#define B010010 18 -#define B0010010 18 -#define B00010010 18 -#define B10011 19 -#define B010011 19 -#define B0010011 19 -#define B00010011 19 -#define B10100 20 -#define B010100 20 -#define B0010100 20 -#define B00010100 20 -#define B10101 21 -#define B010101 21 -#define B0010101 21 -#define B00010101 21 -#define B10110 22 -#define B010110 22 -#define B0010110 22 -#define B00010110 22 -#define B10111 23 -#define B010111 23 -#define B0010111 23 -#define B00010111 23 -#define B11000 24 -#define B011000 24 -#define B0011000 24 -#define B00011000 24 -#define B11001 25 -#define B011001 25 -#define B0011001 25 -#define B00011001 25 -#define B11010 26 -#define B011010 26 -#define B0011010 26 -#define B00011010 26 -#define B11011 27 -#define B011011 27 -#define B0011011 27 -#define B00011011 27 -#define B11100 28 -#define B011100 28 -#define B0011100 28 -#define B00011100 28 -#define B11101 29 -#define B011101 29 -#define B0011101 29 -#define B00011101 29 -#define B11110 30 -#define B011110 30 -#define B0011110 30 -#define B00011110 30 -#define B11111 31 -#define B011111 31 -#define B0011111 31 -#define B00011111 31 -#define B100000 32 -#define B0100000 32 -#define B00100000 32 -#define B100001 33 -#define B0100001 33 -#define B00100001 33 -#define B100010 34 -#define B0100010 34 -#define B00100010 34 -#define B100011 35 -#define B0100011 35 -#define B00100011 35 -#define B100100 36 -#define B0100100 36 -#define B00100100 36 -#define B100101 37 -#define B0100101 37 -#define B00100101 37 -#define B100110 38 -#define B0100110 38 -#define B00100110 38 -#define B100111 39 -#define B0100111 39 -#define B00100111 39 -#define B101000 40 -#define B0101000 40 -#define B00101000 40 -#define B101001 41 -#define B0101001 41 -#define B00101001 41 -#define B101010 42 -#define B0101010 42 -#define B00101010 42 -#define B101011 43 -#define B0101011 43 -#define B00101011 43 -#define B101100 44 -#define B0101100 44 -#define B00101100 44 -#define B101101 45 -#define B0101101 45 -#define B00101101 45 -#define B101110 46 -#define B0101110 46 -#define B00101110 46 -#define B101111 47 -#define B0101111 47 -#define B00101111 47 -#define B110000 48 -#define B0110000 48 -#define B00110000 48 -#define B110001 49 -#define B0110001 49 -#define B00110001 49 -#define B110010 50 -#define B0110010 50 -#define B00110010 50 -#define B110011 51 -#define B0110011 51 -#define B00110011 51 -#define B110100 52 -#define B0110100 52 -#define B00110100 52 -#define B110101 53 -#define B0110101 53 -#define B00110101 53 -#define B110110 54 -#define B0110110 54 -#define B00110110 54 -#define B110111 55 -#define B0110111 55 -#define B00110111 55 -#define B111000 56 -#define B0111000 56 -#define B00111000 56 -#define B111001 57 -#define B0111001 57 -#define B00111001 57 -#define B111010 58 -#define B0111010 58 -#define B00111010 58 -#define B111011 59 -#define B0111011 59 -#define B00111011 59 -#define B111100 60 -#define B0111100 60 -#define B00111100 60 -#define B111101 61 -#define B0111101 61 -#define B00111101 61 -#define B111110 62 -#define B0111110 62 -#define B00111110 62 -#define B111111 63 -#define B0111111 63 -#define B00111111 63 -#define B1000000 64 -#define B01000000 64 -#define B1000001 65 -#define B01000001 65 -#define B1000010 66 -#define B01000010 66 -#define B1000011 67 -#define B01000011 67 -#define B1000100 68 -#define B01000100 68 -#define B1000101 69 -#define B01000101 69 -#define B1000110 70 -#define B01000110 70 -#define B1000111 71 -#define B01000111 71 -#define B1001000 72 -#define B01001000 72 -#define B1001001 73 -#define B01001001 73 -#define B1001010 74 -#define B01001010 74 -#define B1001011 75 -#define B01001011 75 -#define B1001100 76 -#define B01001100 76 -#define B1001101 77 -#define B01001101 77 -#define B1001110 78 -#define B01001110 78 -#define B1001111 79 -#define B01001111 79 -#define B1010000 80 -#define B01010000 80 -#define B1010001 81 -#define B01010001 81 -#define B1010010 82 -#define B01010010 82 -#define B1010011 83 -#define B01010011 83 -#define B1010100 84 -#define B01010100 84 -#define B1010101 85 -#define B01010101 85 -#define B1010110 86 -#define B01010110 86 -#define B1010111 87 -#define B01010111 87 -#define B1011000 88 -#define B01011000 88 -#define B1011001 89 -#define B01011001 89 -#define B1011010 90 -#define B01011010 90 -#define B1011011 91 -#define B01011011 91 -#define B1011100 92 -#define B01011100 92 -#define B1011101 93 -#define B01011101 93 -#define B1011110 94 -#define B01011110 94 -#define B1011111 95 -#define B01011111 95 -#define B1100000 96 -#define B01100000 96 -#define B1100001 97 -#define B01100001 97 -#define B1100010 98 -#define B01100010 98 -#define B1100011 99 -#define B01100011 99 -#define B1100100 100 -#define B01100100 100 -#define B1100101 101 -#define B01100101 101 -#define B1100110 102 -#define B01100110 102 -#define B1100111 103 -#define B01100111 103 -#define B1101000 104 -#define B01101000 104 -#define B1101001 105 -#define B01101001 105 -#define B1101010 106 -#define B01101010 106 -#define B1101011 107 -#define B01101011 107 -#define B1101100 108 -#define B01101100 108 -#define B1101101 109 -#define B01101101 109 -#define B1101110 110 -#define B01101110 110 -#define B1101111 111 -#define B01101111 111 -#define B1110000 112 -#define B01110000 112 -#define B1110001 113 -#define B01110001 113 -#define B1110010 114 -#define B01110010 114 -#define B1110011 115 -#define B01110011 115 -#define B1110100 116 -#define B01110100 116 -#define B1110101 117 -#define B01110101 117 -#define B1110110 118 -#define B01110110 118 -#define B1110111 119 -#define B01110111 119 -#define B1111000 120 -#define B01111000 120 -#define B1111001 121 -#define B01111001 121 -#define B1111010 122 -#define B01111010 122 -#define B1111011 123 -#define B01111011 123 -#define B1111100 124 -#define B01111100 124 -#define B1111101 125 -#define B01111101 125 -#define B1111110 126 -#define B01111110 126 -#define B1111111 127 -#define B01111111 127 -#define B10000000 128 -#define B10000001 129 -#define B10000010 130 -#define B10000011 131 -#define B10000100 132 -#define B10000101 133 -#define B10000110 134 -#define B10000111 135 -#define B10001000 136 -#define B10001001 137 -#define B10001010 138 -#define B10001011 139 -#define B10001100 140 -#define B10001101 141 -#define B10001110 142 -#define B10001111 143 -#define B10010000 144 -#define B10010001 145 -#define B10010010 146 -#define B10010011 147 -#define B10010100 148 -#define B10010101 149 -#define B10010110 150 -#define B10010111 151 -#define B10011000 152 -#define B10011001 153 -#define B10011010 154 -#define B10011011 155 -#define B10011100 156 -#define B10011101 157 -#define B10011110 158 -#define B10011111 159 -#define B10100000 160 -#define B10100001 161 -#define B10100010 162 -#define B10100011 163 -#define B10100100 164 -#define B10100101 165 -#define B10100110 166 -#define B10100111 167 -#define B10101000 168 -#define B10101001 169 -#define B10101010 170 -#define B10101011 171 -#define B10101100 172 -#define B10101101 173 -#define B10101110 174 -#define B10101111 175 -#define B10110000 176 -#define B10110001 177 -#define B10110010 178 -#define B10110011 179 -#define B10110100 180 -#define B10110101 181 -#define B10110110 182 -#define B10110111 183 -#define B10111000 184 -#define B10111001 185 -#define B10111010 186 -#define B10111011 187 -#define B10111100 188 -#define B10111101 189 -#define B10111110 190 -#define B10111111 191 -#define B11000000 192 -#define B11000001 193 -#define B11000010 194 -#define B11000011 195 -#define B11000100 196 -#define B11000101 197 -#define B11000110 198 -#define B11000111 199 -#define B11001000 200 -#define B11001001 201 -#define B11001010 202 -#define B11001011 203 -#define B11001100 204 -#define B11001101 205 -#define B11001110 206 -#define B11001111 207 -#define B11010000 208 -#define B11010001 209 -#define B11010010 210 -#define B11010011 211 -#define B11010100 212 -#define B11010101 213 -#define B11010110 214 -#define B11010111 215 -#define B11011000 216 -#define B11011001 217 -#define B11011010 218 -#define B11011011 219 -#define B11011100 220 -#define B11011101 221 -#define B11011110 222 -#define B11011111 223 -#define B11100000 224 -#define B11100001 225 -#define B11100010 226 -#define B11100011 227 -#define B11100100 228 -#define B11100101 229 -#define B11100110 230 -#define B11100111 231 -#define B11101000 232 -#define B11101001 233 -#define B11101010 234 -#define B11101011 235 -#define B11101100 236 -#define B11101101 237 -#define B11101110 238 -#define B11101111 239 -#define B11110000 240 -#define B11110001 241 -#define B11110010 242 -#define B11110011 243 -#define B11110100 244 -#define B11110101 245 -#define B11110110 246 -#define B11110111 247 -#define B11111000 248 -#define B11111001 249 -#define B11111010 250 -#define B11111011 251 -#define B11111100 252 -#define B11111101 253 -#define B11111110 254 -#define B11111111 255 - -#endif /* _BIT_CONSTANTS_H_ */ diff --git a/wirish/bits.h b/wirish/bits.h deleted file mode 100644 index 3e755b7..0000000 --- a/wirish/bits.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/* Note: Use of this header file is deprecated. Use bit_constants.h - instead. */ - -#include "bit_constants.h" diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 569ca6d..dbdcf1c 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -32,15 +32,15 @@ * at 72MHz. APB1 is clocked at 36MHz. */ -#include "boards.h" - -#include "flash.h" -#include "rcc.h" -#include "nvic.h" -#include "systick.h" -#include "gpio.h" -#include "adc.h" -#include "timer.h" +#include + +#include +#include +#include +#include +#include +#include +#include #include "usb_cdcacm.h" static void setupFlash(void); diff --git a/wirish/boards.h b/wirish/boards.h deleted file mode 100644 index 9ca4a66..0000000 --- a/wirish/boards.h +++ /dev/null @@ -1,155 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Bryan Newbold. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file boards.h - * @author Bryan Newbold , - * Marti Bolivar - * @brief Board-specific pin information. - * - * To add a new board type, add a new pair of files to - * /wirish/boards/, update the section below with a new "BOARD" type, - * and update /wirish/rules.mk to include your boards/your_board.cpp - * file in the top-level Makefile build. - */ - -#ifndef _BOARDS_H_ -#define _BOARDS_H_ - -#include "libmaple_types.h" - -#include "wirish_types.h" - -/* Set of all possible pin names; not all boards have all these (note - * that we use the Dx convention since all of the Maple's pins are - * "digital" pins (e.g. can be used with digitalRead() and - * digitalWrite()), but not all of them are connected to ADCs. */ -enum { - D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, - D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, - D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46, - D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D58, D59, D60, D61, - D62, D63, D64, D65, D66, D67, D68, D69, D70, D71, D72, D73, D74, D75, D76, - D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D89, D90, D91, - D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105, - D106, D107, D108, D109, D110, D111, }; - -/** - * @brief Maps each Maple pin to a corresponding stm32_pin_info. - * @see stm32_pin_info - */ -extern const stm32_pin_info PIN_MAP[]; - -/** - * @brief Pins capable of PWM output. - * - * Its length is BOARD_NR_PWM_PINS. - */ -extern const uint8 boardPWMPins[]; - -/** - * @brief Array of pins capable of analog input. - * - * Its length is BOARD_NR_ADC_PINS. - */ -extern const uint8 boardADCPins[]; - -/** - * @brief Pins which are connected to external hardware. - * - * For example, on Maple boards, it always at least includes - * BOARD_LED_PIN. Its length is BOARD_NR_USED_PINS. - */ -extern const uint8 boardUsedPins[]; - -/** - * @brief Generic board initialization function. - * - * This function is called before main(). It ensures that the clocks - * and peripherals are configured properly for use with wirish, then - * calls boardInit(). - * - * @see boardInit() - */ -void init(void); - -/** - * @brief Board-specific initialization function. - * - * This function is called from init() after all generic board - * initialization has been performed. Each board is required to - * define its own. - * - * @see init() - */ -extern void boardInit(void); - -/** - * @brief Test if a pin is used for a special purpose on your board. - * @param pin Pin to test - * @return true if the given pin is in boardUsedPins, and false otherwise. - * @see boardUsedPins - */ -bool boardUsesPin(uint8 pin); - -/* Include the appropriate private header from boards/: */ - -/* FIXME HACK put boards/ before these paths once IDE uses make. */ - -#ifdef BOARD_maple -#include "maple.h" -#elif defined(BOARD_maple_native) -#include "maple_native.h" -#elif defined(BOARD_maple_mini) -#include "maple_mini.h" -#elif defined(BOARD_maple_RET6) -/* - * **NOT** MAPLE REV6. This the **Maple RET6 EDITION**, which is a - * Maple with an STM32F103RET6 (...RET6) instead of an STM32F103RBT6 - * (...RBT6) on it. Maple Rev6 (as of March 2011) DOES NOT EXIST. - */ -#include "maple_RET6.h" -#elif defined(BOARD_olimex_stm32_h103) -#include "olimex_stm32_h103.h" -#else -/* - * TODO turn this into a warning so people can: - * - * #include "my_board_config.h" - * #include "wirish.h" - * - * This will enable third-party board support without requiring that - * anybody hack around in libmaple itself. - */ -#error "Board type has not been selected correctly." -#endif - -/* Set derived definitions */ - -#define CLOCK_SPEED_MHZ CYCLES_PER_MICROSECOND -#define CLOCK_SPEED_HZ (CLOCK_SPEED_MHZ * 1000000UL) - -#endif diff --git a/wirish/boards/maple.cpp b/wirish/boards/maple.cpp deleted file mode 100644 index 43d4386..0000000 --- a/wirish/boards/maple.cpp +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple.cpp - * @author Marti Bolivar - * @brief Maple PIN_MAP and boardInit(). - */ - -#ifdef BOARD_maple - -#include "maple.h" - -#include "gpio.h" -#include "timer.h" -#include "wirish_types.h" - -void boardInit(void) { -} - -extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { - - /* Top header */ - - {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ - {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ - {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ - {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ - {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ - {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ - {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ - {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ - {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ - {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ - {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ - {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ - {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ - {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ - {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ - - /* Little header */ - - {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ - {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ - {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ - {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ - {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ - {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ - - /* External header */ - - {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ - {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ - {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ - {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ - {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ - {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ - {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ - {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ - {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ - {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ - {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ - {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ - {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ - {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D35/PC6 */ - {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D36/PC7 */ - {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D37/PC8 */ - {GPIOC, NULL, NULL, 9, 0, ADCx}, /* D38/PC9 (BUT) */ - - /* JTAG header */ - - {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D39/PA13 */ - {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D40/PA14 */ - {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D41/PA15 */ - {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D42/PB3 */ - {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D43/PB4 */ -}; - -extern const uint8 boardPWMPins[] __FLASH__ = { - 0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 27, 28 -}; - -extern const uint8 boardADCPins[] __FLASH__ = { - 0, 1, 2, 3, 10, 11, 12, 15, 16, 17, 18, 19, 20, 27, 28 -}; - -extern const uint8 boardUsedPins[] __FLASH__ = { - BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, - BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN -}; - -#endif diff --git a/wirish/boards/maple.h b/wirish/boards/maple.h deleted file mode 100644 index a986884..0000000 --- a/wirish/boards/maple.h +++ /dev/null @@ -1,92 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple.h - * @author Marti Bolivar - * @brief Private include file for Maple in boards.h - */ - -#ifndef _BOARD_MAPLE_H_ -#define _BOARD_MAPLE_H_ - -#define CYCLES_PER_MICROSECOND 72 -#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ - -#define BOARD_BUTTON_PIN 38 -#define BOARD_LED_PIN 13 - -/* Number of USARTs/UARTs whose pins are broken out to headers */ -#define BOARD_NR_USARTS 3 - -/* Default USART pin numbers (not considering AFIO remap) */ -#define BOARD_USART1_TX_PIN 7 -#define BOARD_USART1_RX_PIN 8 -#define BOARD_USART2_TX_PIN 1 -#define BOARD_USART2_RX_PIN 0 -#define BOARD_USART3_TX_PIN 29 -#define BOARD_USART3_RX_PIN 30 - -/* Number of SPI ports */ -#define BOARD_NR_SPI 2 - -/* Default SPI pin numbers (not considering AFIO remap) */ -#define BOARD_SPI1_NSS_PIN 10 -#define BOARD_SPI1_MOSI_PIN 11 -#define BOARD_SPI1_MISO_PIN 12 -#define BOARD_SPI1_SCK_PIN 13 -#define BOARD_SPI2_NSS_PIN 31 -#define BOARD_SPI2_MOSI_PIN 34 -#define BOARD_SPI2_MISO_PIN 33 -#define BOARD_SPI2_SCK_PIN 32 - -/* Total number of GPIO pins that are broken out to headers and - * intended for general use. */ -#define BOARD_NR_GPIO_PINS 44 - -/* Number of pins capable of PWM output */ -#define BOARD_NR_PWM_PINS 15 - -/* Number of pins capable of ADC conversion */ -#define BOARD_NR_ADC_PINS 15 - -/* Number of pins already connected to external hardware. For Maple, - * these are just BOARD_LED_PIN and BOARD_BUTTON_PIN. */ -#define BOARD_NR_USED_PINS 7 - -/* Debug port pins */ -#define BOARD_JTMS_SWDIO_PIN 39 -#define BOARD_JTCK_SWCLK_PIN 40 -#define BOARD_JTDI_PIN 41 -#define BOARD_JTDO_PIN 42 -#define BOARD_NJTRST_PIN 43 - -/* USB configuration. BOARD_USB_DISC_DEV is the GPIO port containing - * the USB_DISC pin, and BOARD_USB_DISC_BIT is that pin's bit. */ -#define BOARD_USB_DISC_DEV GPIOC -#define BOARD_USB_DISC_BIT 12 - -#endif diff --git a/wirish/boards/maple/board.cpp b/wirish/boards/maple/board.cpp new file mode 100644 index 0000000..256bb90 --- /dev/null +++ b/wirish/boards/maple/board.cpp @@ -0,0 +1,112 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple/board.cpp + * @author Marti Bolivar + * @brief Maple board file. + */ + +#include + +#include +#include +#include + +void boardInit(void) { +} + +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + + /* Top header */ + + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ + + /* Little header */ + + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ + + /* External header */ + + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ + {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D35/PC6 */ + {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D36/PC7 */ + {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D37/PC8 */ + {GPIOC, NULL, NULL, 9, 0, ADCx}, /* D38/PC9 (BUT) */ + + /* JTAG header */ + + {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D39/PA13 */ + {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D40/PA14 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D41/PA15 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D42/PB3 */ + {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D43/PB4 */ +}; + +extern const uint8 boardPWMPins[] __FLASH__ = { + 0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 27, 28 +}; + +extern const uint8 boardADCPins[] __FLASH__ = { + 0, 1, 2, 3, 10, 11, 12, 15, 16, 17, 18, 19, 20, 27, 28 +}; + +extern const uint8 boardUsedPins[] __FLASH__ = { + BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, + BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN +}; diff --git a/wirish/boards/maple/include/board/board.h b/wirish/boards/maple/include/board/board.h new file mode 100644 index 0000000..49f5b9a --- /dev/null +++ b/wirish/boards/maple/include/board/board.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple/include/board/board.h + * @author Marti Bolivar + * @brief Maple board header. + */ + +#ifndef _BOARD_MAPLE_H_ +#define _BOARD_MAPLE_H_ + +#define CYCLES_PER_MICROSECOND 72 +#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ + +#define BOARD_BUTTON_PIN 38 +#define BOARD_LED_PIN 13 + +/* Number of USARTs/UARTs whose pins are broken out to headers */ +#define BOARD_NR_USARTS 3 + +/* Default USART pin numbers (not considering AFIO remap) */ +#define BOARD_USART1_TX_PIN 7 +#define BOARD_USART1_RX_PIN 8 +#define BOARD_USART2_TX_PIN 1 +#define BOARD_USART2_RX_PIN 0 +#define BOARD_USART3_TX_PIN 29 +#define BOARD_USART3_RX_PIN 30 + +/* Number of SPI ports */ +#define BOARD_NR_SPI 2 + +/* Default SPI pin numbers (not considering AFIO remap) */ +#define BOARD_SPI1_NSS_PIN 10 +#define BOARD_SPI1_MOSI_PIN 11 +#define BOARD_SPI1_MISO_PIN 12 +#define BOARD_SPI1_SCK_PIN 13 +#define BOARD_SPI2_NSS_PIN 31 +#define BOARD_SPI2_MOSI_PIN 34 +#define BOARD_SPI2_MISO_PIN 33 +#define BOARD_SPI2_SCK_PIN 32 + +/* Total number of GPIO pins that are broken out to headers and + * intended for general use. */ +#define BOARD_NR_GPIO_PINS 44 + +/* Number of pins capable of PWM output */ +#define BOARD_NR_PWM_PINS 15 + +/* Number of pins capable of ADC conversion */ +#define BOARD_NR_ADC_PINS 15 + +/* Number of pins already connected to external hardware. For Maple, + * these are just BOARD_LED_PIN and BOARD_BUTTON_PIN. */ +#define BOARD_NR_USED_PINS 7 + +/* Debug port pins */ +#define BOARD_JTMS_SWDIO_PIN 39 +#define BOARD_JTCK_SWCLK_PIN 40 +#define BOARD_JTDI_PIN 41 +#define BOARD_JTDO_PIN 42 +#define BOARD_NJTRST_PIN 43 + +/* USB configuration. BOARD_USB_DISC_DEV is the GPIO port containing + * the USB_DISC pin, and BOARD_USB_DISC_BIT is that pin's bit. */ +#define BOARD_USB_DISC_DEV GPIOC +#define BOARD_USB_DISC_BIT 12 + +#endif diff --git a/wirish/boards/maple_RET6.cpp b/wirish/boards/maple_RET6.cpp deleted file mode 100644 index cbd7e25..0000000 --- a/wirish/boards/maple_RET6.cpp +++ /dev/null @@ -1,118 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple_RET6.cpp - * @author Marti Bolivar - * @brief Maple RET6 Edition board file - */ - -#ifdef BOARD_maple_RET6 - -#include "maple_RET6.h" - -#include "gpio.h" -#include "timer.h" -#include "wirish_types.h" - -void boardInit(void) { -} - -extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { - - /* Top header */ - - {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ - {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ - {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ - {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ - {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ - {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ - {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ - {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ - {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ - {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ - {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ - {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ - {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ - {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ - {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ - - /* Little header */ - - {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ - {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ - {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ - {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ - {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ - {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ - - /* External header */ - - {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ - {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ - {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ - {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ - {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ - {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ - {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ - {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ - {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ - {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ - {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ - {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ - {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ - {GPIOC, TIMER8, NULL, 6, 1, ADCx}, /* D35/PC6 */ - {GPIOC, TIMER8, NULL, 7, 2, ADCx}, /* D36/PC7 */ - {GPIOC, TIMER8, NULL, 8, 3, ADCx}, /* D37/PC8 */ - {GPIOC, TIMER8, NULL, 9, 4, ADCx}, /* D38/PC9 (BUT) */ - - /* JTAG header */ - - {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D39/PA13 */ - {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D40/PA14 */ - {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D41/PA15 */ - {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D42/PB3 */ - {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D43/PB4 */ -}; - -/* Note: Do NOT include pin 38 (TIM8_CH4), as that's BOARD_BUTTON_PIN - * and thus not broken out to a header. */ -extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = { - 0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 27, 28, 35, 36, 37 -}; - -extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = { - 0, 1, 2, 3, 10, 11, 12, 15, 16, 17, 18, 19, 20, 27, 28 -}; - -extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = { - BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, - BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN -}; - -#endif diff --git a/wirish/boards/maple_RET6.h b/wirish/boards/maple_RET6.h deleted file mode 100644 index 9e7ce9d..0000000 --- a/wirish/boards/maple_RET6.h +++ /dev/null @@ -1,91 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple_RET6.h - * @author Marti Bolivar - * @brief Private include file for Maple RET6 Edition in boards.h - * - * See maple.h for more information on these definitions. - */ - -#ifndef _BOARDS_MAPLE_RET6_H_ -#define _BOARDS_MAPLE_RET6_H_ - -/* A few of these values will seem strange given that it's a - * high-density board. */ - -#define CYCLES_PER_MICROSECOND 72 -#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ - -#define BOARD_BUTTON_PIN 38 -#define BOARD_LED_PIN 13 - -/* Note: UART4 and UART5 have pins which aren't broken out :( */ -#define BOARD_NR_USARTS 3 -#define BOARD_USART1_TX_PIN 7 -#define BOARD_USART1_RX_PIN 8 -#define BOARD_USART2_TX_PIN 1 -#define BOARD_USART2_RX_PIN 0 -#define BOARD_USART3_TX_PIN 29 -#define BOARD_USART3_RX_PIN 30 - -/* Note: - * - * SPI3 is unusable due to pin 43 (PB4) and NRST tie-together :(, but - * leave the definitions so as not to clutter things up. This is only - * OK since RET6 Ed. is specifically advertised as a beta board. */ -#define BOARD_NR_SPI 2 -#define BOARD_SPI1_NSS_PIN 10 -#define BOARD_SPI1_MOSI_PIN 11 -#define BOARD_SPI1_MISO_PIN 12 -#define BOARD_SPI1_SCK_PIN 13 -#define BOARD_SPI2_NSS_PIN 31 -#define BOARD_SPI2_MOSI_PIN 34 -#define BOARD_SPI2_MISO_PIN 33 -#define BOARD_SPI2_SCK_PIN 32 -#define BOARD_SPI3_NSS_PIN 41 -#define BOARD_SPI3_MOSI_PIN 4 -#define BOARD_SPI3_MISO_PIN 43 -#define BOARD_SPI3_SCK_PIN 42 - -#define BOARD_NR_GPIO_PINS 44 -/* Note: NOT 19. The missing one is D38 a.k.a. BOARD_BUTTON_PIN, which - * isn't broken out to a header and is thus unusable for PWM. */ -#define BOARD_NR_PWM_PINS 18 -#define BOARD_NR_ADC_PINS 15 -#define BOARD_NR_USED_PINS 7 - -#define BOARD_JTMS_SWDIO_PIN 39 -#define BOARD_JTCK_SWCLK_PIN 40 -#define BOARD_JTDI_PIN 41 -#define BOARD_JTDO_PIN 42 -#define BOARD_NJTRST_PIN 43 - -#define BOARD_USB_DISC_DEV GPIOC -#define BOARD_USB_DISC_BIT 12 - -#endif diff --git a/wirish/boards/maple_RET6/board.cpp b/wirish/boards/maple_RET6/board.cpp new file mode 100644 index 0000000..2ef7de7 --- /dev/null +++ b/wirish/boards/maple_RET6/board.cpp @@ -0,0 +1,115 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple_RET6/board.cpp + * @author Marti Bolivar + * @brief Maple RET6 Edition board file + */ + +#include + +#include +#include + +#include + +void boardInit(void) { +} + +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + + /* Top header */ + + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ + + /* Little header */ + + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ + + /* External header */ + + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ + {GPIOC, TIMER8, NULL, 6, 1, ADCx}, /* D35/PC6 */ + {GPIOC, TIMER8, NULL, 7, 2, ADCx}, /* D36/PC7 */ + {GPIOC, TIMER8, NULL, 8, 3, ADCx}, /* D37/PC8 */ + {GPIOC, TIMER8, NULL, 9, 4, ADCx}, /* D38/PC9 (BUT) */ + + /* JTAG header */ + + {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D39/PA13 */ + {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D40/PA14 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D41/PA15 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D42/PB3 */ + {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D43/PB4 */ +}; + +/* Note: Do NOT include pin 38 (TIM8_CH4), as that's BOARD_BUTTON_PIN + * and thus not broken out to a header. */ +extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = { + 0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 27, 28, 35, 36, 37 +}; + +extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = { + 0, 1, 2, 3, 10, 11, 12, 15, 16, 17, 18, 19, 20, 27, 28 +}; + +extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = { + BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, + BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN +}; diff --git a/wirish/boards/maple_RET6/include/board/board.h b/wirish/boards/maple_RET6/include/board/board.h new file mode 100644 index 0000000..1a0365a --- /dev/null +++ b/wirish/boards/maple_RET6/include/board/board.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple_RET6/include/board/board.h + * @author Marti Bolivar + * @brief Maple RET6 Edition board header. + * + * See wirish/boards/maple/include/board/board.h for more information + * on these definitions. + */ + +#ifndef _BOARDS_MAPLE_RET6_H_ +#define _BOARDS_MAPLE_RET6_H_ + +/* A few of these values will seem strange given that it's a + * high-density board. */ + +#define CYCLES_PER_MICROSECOND 72 +#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ + +#define BOARD_BUTTON_PIN 38 +#define BOARD_LED_PIN 13 + +/* Note: UART4 and UART5 have pins which aren't broken out :( */ +#define BOARD_NR_USARTS 3 +#define BOARD_USART1_TX_PIN 7 +#define BOARD_USART1_RX_PIN 8 +#define BOARD_USART2_TX_PIN 1 +#define BOARD_USART2_RX_PIN 0 +#define BOARD_USART3_TX_PIN 29 +#define BOARD_USART3_RX_PIN 30 + +/* Note: + * + * SPI3 is unusable due to pin 43 (PB4) and NRST tie-together :(, but + * leave the definitions so as not to clutter things up. This is only + * OK since RET6 Ed. is specifically advertised as a beta board. */ +#define BOARD_NR_SPI 2 +#define BOARD_SPI1_NSS_PIN 10 +#define BOARD_SPI1_MOSI_PIN 11 +#define BOARD_SPI1_MISO_PIN 12 +#define BOARD_SPI1_SCK_PIN 13 +#define BOARD_SPI2_NSS_PIN 31 +#define BOARD_SPI2_MOSI_PIN 34 +#define BOARD_SPI2_MISO_PIN 33 +#define BOARD_SPI2_SCK_PIN 32 +#define BOARD_SPI3_NSS_PIN 41 +#define BOARD_SPI3_MOSI_PIN 4 +#define BOARD_SPI3_MISO_PIN 43 +#define BOARD_SPI3_SCK_PIN 42 + +#define BOARD_NR_GPIO_PINS 44 +/* Note: NOT 19. The missing one is D38 a.k.a. BOARD_BUTTON_PIN, which + * isn't broken out to a header and is thus unusable for PWM. */ +#define BOARD_NR_PWM_PINS 18 +#define BOARD_NR_ADC_PINS 15 +#define BOARD_NR_USED_PINS 7 + +#define BOARD_JTMS_SWDIO_PIN 39 +#define BOARD_JTCK_SWCLK_PIN 40 +#define BOARD_JTDI_PIN 41 +#define BOARD_JTDO_PIN 42 +#define BOARD_NJTRST_PIN 43 + +#define BOARD_USB_DISC_DEV GPIOC +#define BOARD_USB_DISC_BIT 12 + +#endif diff --git a/wirish/boards/maple_mini.cpp b/wirish/boards/maple_mini.cpp deleted file mode 100644 index f111a14..0000000 --- a/wirish/boards/maple_mini.cpp +++ /dev/null @@ -1,106 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple_mini.cpp - * @author Marti Bolivar - * @brief Maple Mini board file. - */ - -#ifdef BOARD_maple_mini - -#include "maple_mini.h" - -#include "gpio.h" -#include "timer.h" -#include "wirish_debug.h" -#include "wirish_types.h" - -/* Since we want the Serial Wire/JTAG pins as GPIOs, disable both SW - * and JTAG debug support */ -void boardInit(void) { - disableDebugPorts(); -} - -extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { - - /* Top header */ - - {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D0/PB11 */ - {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D1/PB10 */ - {GPIOB, NULL, NULL, 2, 0, ADCx}, /* D2/PB2 */ - {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D3/PB0 */ - {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D4/PA7 */ - {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D5/PA6 */ - {GPIOA, NULL, ADC1, 5, 0, 5}, /* D6/PA5 */ - {GPIOA, NULL, ADC1, 4, 0, 4}, /* D7/PA4 */ - {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D8/PA3 */ - {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D9/PA2 */ - {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D10/PA1 */ - {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D11/PA0 */ - {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D12/PC15 */ - {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D13/PC14 */ - {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D14/PC13 */ - - /* Bottom header */ - - {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D15/PB7 */ - {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D16/PB6 */ - {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D17/PB5 */ - {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D18/PB4 */ - {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D19/PB3 */ - {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D20/PA15 */ - {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D21/PA14 */ - {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D22/PA13 */ - {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D23/PA12 */ - {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D24/PA11 */ - {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D25/PA10 */ - {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D26/PA9 */ - {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D27/PA8 */ - {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D28/PB15 */ - {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D29/PB14 */ - {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D30/PB13 */ - {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D32/PB8 */ - {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D33/PB1 */ -}; - -extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = { - 3, 4, 5, 8, 9, 10, 11, 15, 16, 25, 26, 27 -}; - -extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = { - 3, 4, 5, 6, 7, 8, 9, 10, 11 -}; - -#define USB_DP 23 -#define USB_DM 24 - -extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = { - BOARD_LED_PIN, BOARD_BUTTON_PIN, USB_DP, USB_DM -}; - -#endif diff --git a/wirish/boards/maple_mini.h b/wirish/boards/maple_mini.h deleted file mode 100644 index 40f507b..0000000 --- a/wirish/boards/maple_mini.h +++ /dev/null @@ -1,76 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple_mini.h - * @author Marti Bolivar - * @brief Private include file for Maple Mini in boards.h - * - * See maple.h for more information on these definitions. - */ - -#ifndef _BOARD_MAPLE_MINI_H_ -#define _BOARD_MAPLE_MINI_H_ - -#define CYCLES_PER_MICROSECOND 72 -#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ - -#define BOARD_BUTTON_PIN 32 -#define BOARD_LED_PIN 33 - -#define BOARD_NR_USARTS 3 -#define BOARD_USART1_TX_PIN 26 -#define BOARD_USART1_RX_PIN 25 -#define BOARD_USART2_TX_PIN 9 -#define BOARD_USART2_RX_PIN 8 -#define BOARD_USART3_TX_PIN 1 -#define BOARD_USART3_RX_PIN 0 - -#define BOARD_NR_SPI 2 -#define BOARD_SPI1_NSS_PIN 7 -#define BOARD_SPI1_MOSI_PIN 4 -#define BOARD_SPI1_MISO_PIN 5 -#define BOARD_SPI1_SCK_PIN 6 -#define BOARD_SPI2_NSS_PIN 31 -#define BOARD_SPI2_MOSI_PIN 28 -#define BOARD_SPI2_MISO_PIN 29 -#define BOARD_SPI2_SCK_PIN 30 - -#define BOARD_NR_GPIO_PINS 34 -#define BOARD_NR_PWM_PINS 12 -#define BOARD_NR_ADC_PINS 9 -#define BOARD_NR_USED_PINS 4 - -#define BOARD_JTMS_SWDIO_PIN 22 -#define BOARD_JTCK_SWCLK_PIN 21 -#define BOARD_JTDI_PIN 20 -#define BOARD_JTDO_PIN 19 -#define BOARD_NJTRST_PIN 18 - -#define BOARD_USB_DISC_DEV GPIOB -#define BOARD_USB_DISC_BIT 9 - -#endif diff --git a/wirish/boards/maple_mini/board.cpp b/wirish/boards/maple_mini/board.cpp new file mode 100644 index 0000000..599cb66 --- /dev/null +++ b/wirish/boards/maple_mini/board.cpp @@ -0,0 +1,103 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple_mini/board.cpp + * @author Marti Bolivar + * @brief Maple Mini board file. + */ + +#include + +#include +#include + +#include +#include + +/* Since we want the Serial Wire/JTAG pins as GPIOs, disable both SW + * and JTAG debug support */ +void boardInit(void) { + disableDebugPorts(); +} + +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + + /* Top header */ + + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D0/PB11 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D1/PB10 */ + {GPIOB, NULL, NULL, 2, 0, ADCx}, /* D2/PB2 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D3/PB0 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D4/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D5/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D6/PA5 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D7/PA4 */ + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D8/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D9/PA2 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D10/PA1 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D11/PA0 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D12/PC15 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D13/PC14 */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D14/PC13 */ + + /* Bottom header */ + + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D15/PB7 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D16/PB6 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D17/PB5 */ + {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D18/PB4 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D19/PB3 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D20/PA15 */ + {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D21/PA14 */ + {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D22/PA13 */ + {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D23/PA12 */ + {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D24/PA11 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D25/PA10 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D26/PA9 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D27/PA8 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D28/PB15 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D29/PB14 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D30/PB13 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D32/PB8 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D33/PB1 */ +}; + +extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = { + 3, 4, 5, 8, 9, 10, 11, 15, 16, 25, 26, 27 +}; + +extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = { + 3, 4, 5, 6, 7, 8, 9, 10, 11 +}; + +#define USB_DP 23 +#define USB_DM 24 + +extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = { + BOARD_LED_PIN, BOARD_BUTTON_PIN, USB_DP, USB_DM +}; diff --git a/wirish/boards/maple_mini/include/board/board.h b/wirish/boards/maple_mini/include/board/board.h new file mode 100644 index 0000000..bfba46d --- /dev/null +++ b/wirish/boards/maple_mini/include/board/board.h @@ -0,0 +1,77 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple_mini/include/board/board.h + * @author Marti Bolivar + * @brief Maple Mini board header. + * + * See wirish/boards/maple/include/board/board.h for more information + * on these definitions. + */ + +#ifndef _BOARD_MAPLE_MINI_H_ +#define _BOARD_MAPLE_MINI_H_ + +#define CYCLES_PER_MICROSECOND 72 +#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ + +#define BOARD_BUTTON_PIN 32 +#define BOARD_LED_PIN 33 + +#define BOARD_NR_USARTS 3 +#define BOARD_USART1_TX_PIN 26 +#define BOARD_USART1_RX_PIN 25 +#define BOARD_USART2_TX_PIN 9 +#define BOARD_USART2_RX_PIN 8 +#define BOARD_USART3_TX_PIN 1 +#define BOARD_USART3_RX_PIN 0 + +#define BOARD_NR_SPI 2 +#define BOARD_SPI1_NSS_PIN 7 +#define BOARD_SPI1_MOSI_PIN 4 +#define BOARD_SPI1_MISO_PIN 5 +#define BOARD_SPI1_SCK_PIN 6 +#define BOARD_SPI2_NSS_PIN 31 +#define BOARD_SPI2_MOSI_PIN 28 +#define BOARD_SPI2_MISO_PIN 29 +#define BOARD_SPI2_SCK_PIN 30 + +#define BOARD_NR_GPIO_PINS 34 +#define BOARD_NR_PWM_PINS 12 +#define BOARD_NR_ADC_PINS 9 +#define BOARD_NR_USED_PINS 4 + +#define BOARD_JTMS_SWDIO_PIN 22 +#define BOARD_JTCK_SWCLK_PIN 21 +#define BOARD_JTDI_PIN 20 +#define BOARD_JTDO_PIN 19 +#define BOARD_NJTRST_PIN 18 + +#define BOARD_USB_DISC_DEV GPIOB +#define BOARD_USB_DISC_BIT 9 + +#endif diff --git a/wirish/boards/maple_native.cpp b/wirish/boards/maple_native.cpp deleted file mode 100644 index 821be77..0000000 --- a/wirish/boards/maple_native.cpp +++ /dev/null @@ -1,201 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple_native.cpp - * @author Marti Bolivar - * @brief Maple Native board file. - */ - -#ifdef BOARD_maple_native - -#include "maple_native.h" - -#include "fsmc.h" -#include "gpio.h" -#include "rcc.h" -#include "timer.h" - -#include "wirish_types.h" - -static void initSRAMChip(void); - -void boardInit(void) { - initSRAMChip(); -} - -extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { - - /* Top header */ - - {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D0/PB10 */ - {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D1/PB11 */ - {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D2/PB12 */ - {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D3/PB13 */ - {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D4/PB14 */ - {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D5/PB15 */ - {GPIOG, NULL, NULL, 15, 0, ADCx}, /* D6/PG15 (BUT) */ - {GPIOC, NULL, ADC1, 0, 0, 10}, /* D7/PC0 */ - {GPIOC, NULL, ADC1, 1, 0, 11}, /* D8/PC1 */ - {GPIOC, NULL, ADC1, 2, 0, 12}, /* D9/PC2 */ - {GPIOC, NULL, ADC1, 3, 0, 13}, /* D10/PC3 */ - {GPIOC, NULL, ADC1, 4, 0, 14}, /* D11/PC4 */ - {GPIOC, NULL, ADC1, 5, 0, 15}, /* D12/PC5 */ - {GPIOC, TIMER8, NULL, 6, 1, ADCx}, /* D13/PC6 */ - {GPIOC, TIMER8, NULL, 7, 2, ADCx}, /* D14/PC7 */ - {GPIOC, TIMER8, NULL, 8, 3, ADCx}, /* D15/PC8 */ - {GPIOC, TIMER8, NULL, 9, 4, ADCx}, /* D16/PC9 */ - {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D17/PC10 */ - {GPIOC, NULL, NULL, 11, 0, ADCx}, /* D18/PC11 */ - {GPIOC, NULL, NULL, 12, 0, ADCx}, /* D19/PC12 */ - {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D20/PC13 */ - {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D21/PC14 */ - {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D22/PC15 (LED) */ - {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D23/PA8 */ - {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D24/PA9 */ - {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D25/PA10 */ - {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D26/PB9 */ - - /* Bottom header */ - /* Note: D{48, 49, 50, 51} are also TIMER2_CH{1, 2, 3, 4}, respectively. */ - /* TODO remap timer 2 in boardInit(); make the appropriate changes here */ - - {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D27/PD2 */ - {GPIOD, NULL, NULL, 3, 0, ADCx}, /* D28/PD3 */ - {GPIOD, NULL, NULL, 6, 0, ADCx}, /* D29/PD6 */ - {GPIOG, NULL, NULL, 11, 0, ADCx}, /* D30/PG11 */ - {GPIOG, NULL, NULL, 12, 0, ADCx}, /* D31/PG12 */ - {GPIOG, NULL, NULL, 13, 0, ADCx}, /* D32/PG13 */ - {GPIOG, NULL, NULL, 14, 0, ADCx}, /* D33/PG14 */ - {GPIOG, NULL, NULL, 8, 0, ADCx}, /* D34/PG8 */ - {GPIOG, NULL, NULL, 7, 0, ADCx}, /* D35/PG7 */ - {GPIOG, NULL, NULL, 6, 0, ADCx}, /* D36/PG6 */ - {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D37/PB5 */ - {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D38/PB6 */ - {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D39/PB7 */ - {GPIOF, NULL, NULL, 11, 0, ADCx}, /* D40/PF11 */ - {GPIOF, NULL, ADC3, 6, 0, 4}, /* D41/PF6 */ - {GPIOF, NULL, ADC3, 7, 0, 5}, /* D42/PF7 */ - {GPIOF, NULL, ADC3, 8, 0, 6}, /* D43/PF8 */ - {GPIOF, NULL, ADC3, 9, 0, 7}, /* D44/PF9 */ - {GPIOF, NULL, ADC3, 10, 0, 8}, /* D45/PF10 */ - {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D46/PB1 */ - {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D47/PB0 */ - {GPIOA, TIMER5, ADC1, 0, 1, 0}, /* D48/PA0 */ - {GPIOA, TIMER5, ADC1, 1, 2, 1}, /* D49/PA1 */ - {GPIOA, TIMER5, ADC1, 2, 3, 2}, /* D50/PA2 */ - {GPIOA, TIMER5, ADC1, 3, 4, 3}, /* D51/PA3 */ - {GPIOA, NULL, ADC1, 4, 0, 4}, /* D52/PA4 */ - {GPIOA, NULL, ADC1, 5, 0, 5}, /* D53/PA5 */ - {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D54/PA6 */ - {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D55/PA7 */ - - /* FSMC (triple) header */ - - {GPIOF, NULL, NULL, 0, 0, ADCx}, /* D56/PF0 */ - {GPIOD, NULL, NULL, 11, 0, ADCx}, /* D57/PD11 */ - {GPIOD, NULL, NULL, 14, 0, ADCx}, /* D58/PD14 */ - {GPIOF, NULL, NULL, 1, 0, ADCx}, /* D59/PF1 */ - {GPIOD, NULL, NULL, 12, 0, ADCx}, /* D60/PD12 */ - {GPIOD, NULL, NULL, 15, 0, ADCx}, /* D61/PD15 */ - {GPIOF, NULL, NULL, 2, 0, ADCx}, /* D62/PF2 */ - {GPIOD, NULL, NULL, 13, 0, ADCx}, /* D63/PD13 */ - {GPIOD, NULL, NULL, 0, 0, ADCx}, /* D64/PD0 */ - {GPIOF, NULL, NULL, 3, 0, ADCx}, /* D65/PF3 */ - {GPIOE, NULL, NULL, 3, 0, ADCx}, /* D66/PE3 */ - {GPIOD, NULL, NULL, 1, 0, ADCx}, /* D67/PD1 */ - {GPIOF, NULL, NULL, 4, 0, ADCx}, /* D68/PF4 */ - {GPIOE, NULL, NULL, 4, 0, ADCx}, /* D69/PE4 */ - {GPIOE, NULL, NULL, 7, 0, ADCx}, /* D70/PE7 */ - {GPIOF, NULL, NULL, 5, 0, ADCx}, /* D71/PF5 */ - {GPIOE, NULL, NULL, 5, 0, ADCx}, /* D72/PE5 */ - {GPIOE, NULL, NULL, 8, 0, ADCx}, /* D73/PE8 */ - {GPIOF, NULL, NULL, 12, 0, ADCx}, /* D74/PF12 */ - {GPIOE, NULL, NULL, 6, 0, ADCx}, /* D75/PE6 */ - {GPIOE, NULL, NULL, 9, 0, ADCx}, /* D76/PE9 */ - {GPIOF, NULL, NULL, 13, 0, ADCx}, /* D77/PF13 */ - {GPIOE, NULL, NULL, 10, 0, ADCx}, /* D78/PE10 */ - {GPIOF, NULL, NULL, 14, 0, ADCx}, /* D79/PF14 */ - {GPIOG, NULL, NULL, 9, 0, ADCx}, /* D80/PG9 */ - {GPIOE, NULL, NULL, 11, 0, ADCx}, /* D81/PE11 */ - {GPIOF, NULL, NULL, 15, 0, ADCx}, /* D82/PF15 */ - {GPIOG, NULL, NULL, 10, 0, ADCx}, /* D83/PG10 */ - {GPIOE, NULL, NULL, 12, 0, ADCx}, /* D84/PE12 */ - {GPIOG, NULL, NULL, 0, 0, ADCx}, /* D85/PG0 */ - {GPIOD, NULL, NULL, 5, 0, ADCx}, /* D86/PD5 */ - {GPIOE, NULL, NULL, 13, 0, ADCx}, /* D87/PE13 */ - {GPIOG, NULL, NULL, 1, 0, ADCx}, /* D88/PG1 */ - {GPIOD, NULL, NULL, 4, 0, ADCx}, /* D89/PD4 */ - {GPIOE, NULL, NULL, 14, 0, ADCx}, /* D90/PE14 */ - {GPIOG, NULL, NULL, 2, 0, ADCx}, /* D91/PG2 */ - {GPIOE, NULL, NULL, 1, 0, ADCx}, /* D92/PE1 */ - {GPIOE, NULL, NULL, 15, 0, ADCx}, /* D93/PE15 */ - {GPIOG, NULL, NULL, 3, 0, ADCx}, /* D94/PG3 */ - {GPIOE, NULL, NULL, 0, 0, ADCx}, /* D95/PE0 */ - {GPIOD, NULL, NULL, 8, 0, ADCx}, /* D96/PD8 */ - {GPIOG, NULL, NULL, 4, 0, ADCx}, /* D97/PG4 */ - {GPIOD, NULL, NULL, 9, 0, ADCx}, /* D98/PD9 */ - {GPIOG, NULL, NULL, 5, 0, ADCx}, /* D99/PG5 */ - {GPIOD, NULL, NULL, 10, 0, ADCx}, /* D100/PD10 */ - - /* JTAG header */ - - {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D101/PA13 */ - {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D102/PA14 */ - {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D103/PA15 */ - {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D104/PB3 */ - {GPIOB, NULL, NULL, 4, 0, ADCx} /* D105/PB4 */ -}; - -extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = { - 13, 14, 15, 16, 23, 24, 25, 26, 38, 39, 46, 47, 48, 49, 50, 51, 54, 55 -}; - -extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = { - 7, 8, 9, 10, 11, 12, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, - 54, 55 -}; - -extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = { - BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, - BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN, - 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 78, 79, 81, - 82, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 -}; - -static void initSRAMChip(void) { - fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE; - - fsmc_sram_init_gpios(); - rcc_clk_enable(RCC_FSMC); - - regs->BCR = (FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MTYP_SRAM | - FSMC_BCR_MBKEN); - fsmc_nor_psram_set_addset(regs, 0); - fsmc_nor_psram_set_datast(regs, 3); -} - -#endif diff --git a/wirish/boards/maple_native.h b/wirish/boards/maple_native.h deleted file mode 100644 index 7c09014..0000000 --- a/wirish/boards/maple_native.h +++ /dev/null @@ -1,83 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file maple_native.h - * @author Marti Bolivar - * @brief Private include file for Maple Native in boards.h - * - * See maple.h for more information on these definitions. - */ - -#ifndef _BOARD_MAPLE_NATIVE_H_ -#define _BOARD_MAPLE_NATIVE_H_ - -#define CYCLES_PER_MICROSECOND 72 -#define SYSTICK_RELOAD_VAL 71999 - -#define BOARD_LED_PIN 22 -#define BOARD_BUTTON_PIN 6 - -#define BOARD_NR_USARTS 5 -#define BOARD_USART1_TX_PIN 24 -#define BOARD_USART1_RX_PIN 25 -#define BOARD_USART2_TX_PIN 50 -#define BOARD_USART2_RX_PIN 51 -#define BOARD_USART3_TX_PIN 0 -#define BOARD_USART3_RX_PIN 1 -#define BOARD_UART4_TX_PIN 17 -#define BOARD_UART4_RX_PIN 18 -#define BOARD_UART5_TX_PIN 19 -#define BOARD_UART5_RX_PIN 27 - -#define BOARD_NR_SPI 3 -#define BOARD_SPI1_NSS_PIN 52 -#define BOARD_SPI1_MOSI_PIN 55 -#define BOARD_SPI1_MISO_PIN 54 -#define BOARD_SPI1_SCK_PIN 53 -#define BOARD_SPI2_NSS_PIN 2 -#define BOARD_SPI2_MOSI_PIN 5 -#define BOARD_SPI2_MISO_PIN 4 -#define BOARD_SPI2_SCK_PIN 3 -#define BOARD_SPI3_NSS_PIN 103 -#define BOARD_SPI3_MOSI_PIN 37 -#define BOARD_SPI3_MISO_PIN 105 -#define BOARD_SPI3_SCK_PIN 104 - -#define BOARD_NR_GPIO_PINS 106 -#define BOARD_NR_PWM_PINS 18 -#define BOARD_NR_ADC_PINS 21 -#define BOARD_NR_USED_PINS 43 -#define BOARD_JTMS_SWDIO_PIN 101 -#define BOARD_JTCK_SWCLK_PIN 102 -#define BOARD_JTDI_PIN 103 -#define BOARD_JTDO_PIN 104 -#define BOARD_NJTRST_PIN 105 - -#define BOARD_USB_DISC_DEV GPIOB -#define BOARD_USB_DISC_BIT 8 - -#endif diff --git a/wirish/boards/maple_native/board.cpp b/wirish/boards/maple_native/board.cpp new file mode 100644 index 0000000..515cf5b --- /dev/null +++ b/wirish/boards/maple_native/board.cpp @@ -0,0 +1,197 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple_native/board.cpp + * @author Marti Bolivar + * @brief Maple Native board file. + */ + +#include + +#include +#include +#include +#include + +#include + +static void initSRAMChip(void); + +void boardInit(void) { + initSRAMChip(); +} + +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + + /* Top header */ + + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D0/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D1/PB11 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D2/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D3/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D4/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D5/PB15 */ + {GPIOG, NULL, NULL, 15, 0, ADCx}, /* D6/PG15 (BUT) */ + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D7/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D8/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D9/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D10/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D11/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D12/PC5 */ + {GPIOC, TIMER8, NULL, 6, 1, ADCx}, /* D13/PC6 */ + {GPIOC, TIMER8, NULL, 7, 2, ADCx}, /* D14/PC7 */ + {GPIOC, TIMER8, NULL, 8, 3, ADCx}, /* D15/PC8 */ + {GPIOC, TIMER8, NULL, 9, 4, ADCx}, /* D16/PC9 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D17/PC10 */ + {GPIOC, NULL, NULL, 11, 0, ADCx}, /* D18/PC11 */ + {GPIOC, NULL, NULL, 12, 0, ADCx}, /* D19/PC12 */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D20/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D21/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D22/PC15 (LED) */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D23/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D24/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D25/PA10 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D26/PB9 */ + + /* Bottom header */ + /* Note: D{48, 49, 50, 51} are also TIMER2_CH{1, 2, 3, 4}, respectively. */ + /* TODO remap timer 2 in boardInit(); make the appropriate changes here */ + + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D27/PD2 */ + {GPIOD, NULL, NULL, 3, 0, ADCx}, /* D28/PD3 */ + {GPIOD, NULL, NULL, 6, 0, ADCx}, /* D29/PD6 */ + {GPIOG, NULL, NULL, 11, 0, ADCx}, /* D30/PG11 */ + {GPIOG, NULL, NULL, 12, 0, ADCx}, /* D31/PG12 */ + {GPIOG, NULL, NULL, 13, 0, ADCx}, /* D32/PG13 */ + {GPIOG, NULL, NULL, 14, 0, ADCx}, /* D33/PG14 */ + {GPIOG, NULL, NULL, 8, 0, ADCx}, /* D34/PG8 */ + {GPIOG, NULL, NULL, 7, 0, ADCx}, /* D35/PG7 */ + {GPIOG, NULL, NULL, 6, 0, ADCx}, /* D36/PG6 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D37/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D38/PB6 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D39/PB7 */ + {GPIOF, NULL, NULL, 11, 0, ADCx}, /* D40/PF11 */ + {GPIOF, NULL, ADC3, 6, 0, 4}, /* D41/PF6 */ + {GPIOF, NULL, ADC3, 7, 0, 5}, /* D42/PF7 */ + {GPIOF, NULL, ADC3, 8, 0, 6}, /* D43/PF8 */ + {GPIOF, NULL, ADC3, 9, 0, 7}, /* D44/PF9 */ + {GPIOF, NULL, ADC3, 10, 0, 8}, /* D45/PF10 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D46/PB1 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D47/PB0 */ + {GPIOA, TIMER5, ADC1, 0, 1, 0}, /* D48/PA0 */ + {GPIOA, TIMER5, ADC1, 1, 2, 1}, /* D49/PA1 */ + {GPIOA, TIMER5, ADC1, 2, 3, 2}, /* D50/PA2 */ + {GPIOA, TIMER5, ADC1, 3, 4, 3}, /* D51/PA3 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D52/PA4 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D53/PA5 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D54/PA6 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D55/PA7 */ + + /* FSMC (triple) header */ + + {GPIOF, NULL, NULL, 0, 0, ADCx}, /* D56/PF0 */ + {GPIOD, NULL, NULL, 11, 0, ADCx}, /* D57/PD11 */ + {GPIOD, NULL, NULL, 14, 0, ADCx}, /* D58/PD14 */ + {GPIOF, NULL, NULL, 1, 0, ADCx}, /* D59/PF1 */ + {GPIOD, NULL, NULL, 12, 0, ADCx}, /* D60/PD12 */ + {GPIOD, NULL, NULL, 15, 0, ADCx}, /* D61/PD15 */ + {GPIOF, NULL, NULL, 2, 0, ADCx}, /* D62/PF2 */ + {GPIOD, NULL, NULL, 13, 0, ADCx}, /* D63/PD13 */ + {GPIOD, NULL, NULL, 0, 0, ADCx}, /* D64/PD0 */ + {GPIOF, NULL, NULL, 3, 0, ADCx}, /* D65/PF3 */ + {GPIOE, NULL, NULL, 3, 0, ADCx}, /* D66/PE3 */ + {GPIOD, NULL, NULL, 1, 0, ADCx}, /* D67/PD1 */ + {GPIOF, NULL, NULL, 4, 0, ADCx}, /* D68/PF4 */ + {GPIOE, NULL, NULL, 4, 0, ADCx}, /* D69/PE4 */ + {GPIOE, NULL, NULL, 7, 0, ADCx}, /* D70/PE7 */ + {GPIOF, NULL, NULL, 5, 0, ADCx}, /* D71/PF5 */ + {GPIOE, NULL, NULL, 5, 0, ADCx}, /* D72/PE5 */ + {GPIOE, NULL, NULL, 8, 0, ADCx}, /* D73/PE8 */ + {GPIOF, NULL, NULL, 12, 0, ADCx}, /* D74/PF12 */ + {GPIOE, NULL, NULL, 6, 0, ADCx}, /* D75/PE6 */ + {GPIOE, NULL, NULL, 9, 0, ADCx}, /* D76/PE9 */ + {GPIOF, NULL, NULL, 13, 0, ADCx}, /* D77/PF13 */ + {GPIOE, NULL, NULL, 10, 0, ADCx}, /* D78/PE10 */ + {GPIOF, NULL, NULL, 14, 0, ADCx}, /* D79/PF14 */ + {GPIOG, NULL, NULL, 9, 0, ADCx}, /* D80/PG9 */ + {GPIOE, NULL, NULL, 11, 0, ADCx}, /* D81/PE11 */ + {GPIOF, NULL, NULL, 15, 0, ADCx}, /* D82/PF15 */ + {GPIOG, NULL, NULL, 10, 0, ADCx}, /* D83/PG10 */ + {GPIOE, NULL, NULL, 12, 0, ADCx}, /* D84/PE12 */ + {GPIOG, NULL, NULL, 0, 0, ADCx}, /* D85/PG0 */ + {GPIOD, NULL, NULL, 5, 0, ADCx}, /* D86/PD5 */ + {GPIOE, NULL, NULL, 13, 0, ADCx}, /* D87/PE13 */ + {GPIOG, NULL, NULL, 1, 0, ADCx}, /* D88/PG1 */ + {GPIOD, NULL, NULL, 4, 0, ADCx}, /* D89/PD4 */ + {GPIOE, NULL, NULL, 14, 0, ADCx}, /* D90/PE14 */ + {GPIOG, NULL, NULL, 2, 0, ADCx}, /* D91/PG2 */ + {GPIOE, NULL, NULL, 1, 0, ADCx}, /* D92/PE1 */ + {GPIOE, NULL, NULL, 15, 0, ADCx}, /* D93/PE15 */ + {GPIOG, NULL, NULL, 3, 0, ADCx}, /* D94/PG3 */ + {GPIOE, NULL, NULL, 0, 0, ADCx}, /* D95/PE0 */ + {GPIOD, NULL, NULL, 8, 0, ADCx}, /* D96/PD8 */ + {GPIOG, NULL, NULL, 4, 0, ADCx}, /* D97/PG4 */ + {GPIOD, NULL, NULL, 9, 0, ADCx}, /* D98/PD9 */ + {GPIOG, NULL, NULL, 5, 0, ADCx}, /* D99/PG5 */ + {GPIOD, NULL, NULL, 10, 0, ADCx}, /* D100/PD10 */ + + /* JTAG header */ + + {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D101/PA13 */ + {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D102/PA14 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D103/PA15 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D104/PB3 */ + {GPIOB, NULL, NULL, 4, 0, ADCx} /* D105/PB4 */ +}; + +extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = { + 13, 14, 15, 16, 23, 24, 25, 26, 38, 39, 46, 47, 48, 49, 50, 51, 54, 55 +}; + +extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = { + 7, 8, 9, 10, 11, 12, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, + 54, 55 +}; + +extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = { + BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, + BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN, + 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 78, 79, 81, + 82, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 +}; + +static void initSRAMChip(void) { + fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE; + + fsmc_sram_init_gpios(); + rcc_clk_enable(RCC_FSMC); + + regs->BCR = (FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MTYP_SRAM | + FSMC_BCR_MBKEN); + fsmc_nor_psram_set_addset(regs, 0); + fsmc_nor_psram_set_datast(regs, 3); +} diff --git a/wirish/boards/maple_native/include/board/board.h b/wirish/boards/maple_native/include/board/board.h new file mode 100644 index 0000000..397afaf --- /dev/null +++ b/wirish/boards/maple_native/include/board/board.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/maple_native/include/board/board.h. + * @author Marti Bolivar + * @brief Maple Native board header file. + * + * See wirish/boards/maple/include/board/board.h for more information + * on these definitions. + */ + +#ifndef _BOARD_MAPLE_NATIVE_H_ +#define _BOARD_MAPLE_NATIVE_H_ + +#define CYCLES_PER_MICROSECOND 72 +#define SYSTICK_RELOAD_VAL 71999 + +#define BOARD_LED_PIN 22 +#define BOARD_BUTTON_PIN 6 + +#define BOARD_NR_USARTS 5 +#define BOARD_USART1_TX_PIN 24 +#define BOARD_USART1_RX_PIN 25 +#define BOARD_USART2_TX_PIN 50 +#define BOARD_USART2_RX_PIN 51 +#define BOARD_USART3_TX_PIN 0 +#define BOARD_USART3_RX_PIN 1 +#define BOARD_UART4_TX_PIN 17 +#define BOARD_UART4_RX_PIN 18 +#define BOARD_UART5_TX_PIN 19 +#define BOARD_UART5_RX_PIN 27 + +#define BOARD_NR_SPI 3 +#define BOARD_SPI1_NSS_PIN 52 +#define BOARD_SPI1_MOSI_PIN 55 +#define BOARD_SPI1_MISO_PIN 54 +#define BOARD_SPI1_SCK_PIN 53 +#define BOARD_SPI2_NSS_PIN 2 +#define BOARD_SPI2_MOSI_PIN 5 +#define BOARD_SPI2_MISO_PIN 4 +#define BOARD_SPI2_SCK_PIN 3 +#define BOARD_SPI3_NSS_PIN 103 +#define BOARD_SPI3_MOSI_PIN 37 +#define BOARD_SPI3_MISO_PIN 105 +#define BOARD_SPI3_SCK_PIN 104 + +#define BOARD_NR_GPIO_PINS 106 +#define BOARD_NR_PWM_PINS 18 +#define BOARD_NR_ADC_PINS 21 +#define BOARD_NR_USED_PINS 43 +#define BOARD_JTMS_SWDIO_PIN 101 +#define BOARD_JTCK_SWCLK_PIN 102 +#define BOARD_JTDI_PIN 103 +#define BOARD_JTDO_PIN 104 +#define BOARD_NJTRST_PIN 105 + +#define BOARD_USB_DISC_DEV GPIOB +#define BOARD_USB_DISC_BIT 8 + +#endif diff --git a/wirish/boards/olimex_stm32_h103.cpp b/wirish/boards/olimex_stm32_h103.cpp deleted file mode 100644 index a9f0936..0000000 --- a/wirish/boards/olimex_stm32_h103.cpp +++ /dev/null @@ -1,122 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * Copyright (c) 2011 David Kiliani. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file olimex_stm32_h103.cpp - * @author David Kiliani - * @brief Olimex STM32_H103 PIN_MAP and boardInit(). - */ - -#ifdef BOARD_olimex_stm32_h103 - -#include "olimex_stm32_h103.h" - -#include "gpio.h" -#include "timer.h" -#include "wirish_types.h" - -void boardInit(void) { -} - -extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { - - /* Header EXT1 */ - - {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D0/EXT1_1/PA11 (USBDM) */ - {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D1/EXT1_2/PA8 */ - {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D2/EXT1_3/PA12 (USBDP) */ - {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D3/EXT1_4/PA9 */ - - {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D4/EXT1_7/PA10 */ - {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D5/EXT1_8/PC10 */ - {GPIOC, NULL, NULL, 11, 0, ADCx}, /* D6/EXT1_9/PC11 (USBpull) */ - {GPIOC, NULL, NULL, 12, 0, ADCx}, /* D7/EXT1_10/PC12 (LED) */ - {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D8/EXT1_11/PD2 */ - {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D9/EXT1_12/PB5 */ - {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D10/EXT1_13/PB6 */ - {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D11/EXT1_14/PA6 */ - {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D12/EXT1_15/PB7 */ - {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D13/EXT1_16/PB8 */ - {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D14/EXT1_17/PB9 */ - {GPIOA, NULL, ADC1, 5, 0, 5}, /* D15/EXT1_18/PA5 */ - {GPIOC, NULL, ADC1, 0, 0, 10}, /* D16/EXT1_19/PC0 */ - {GPIOC, NULL, ADC1, 1, 0, 11}, /* D17/EXT1_20/PC1 */ - {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D18/EXT1_21/PB0 */ - {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D19/EXT1_22/PA7 */ - - {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D20/EXT1_24/PC13 */ - - {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D21/EXT1_26/PB1 */ - - /* Header EXT2 */ - - {GPIOC, NULL, ADC1, 2, 0, 12}, /* D22/EXT2_2/PC2 */ - - {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D23/EXT2_4/PA0 (BUT) */ - - {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D24/EXT2_7/PA2 */ - {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D25/EXT2_8/PA1 */ - {GPIOC, NULL, ADC1, 3, 0, 13}, /* D26/EXT2_9/PC3 */ - {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D27/EXT2_10/PA3 */ - {GPIOA, NULL, ADC1, 4, 0, 4}, /* D28/EXT2_11/PA4 */ - {GPIOC, NULL, ADC1, 4, 0, 14}, /* D29/EXT2_12/PC4 (USB-P) */ - {GPIOC, NULL, ADC1, 5, 0, 15}, /* D30/EXT2_13/PC5 */ - {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D31/EXT2_14/PB10 */ - {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D32/EXT2_15/PB11 */ - {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D33/EXT2_16/PB13 */ - {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D34/EXT2_17/PB12 */ - {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D35/EXT2_18/PB14 */ - {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D36/EXT2_19/PB15 */ - {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D37/EXT2_20/PC6 */ - {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D38/EXT2_21/PC7 */ - {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D39/EXT2_22/PC8 */ - - {GPIOC, NULL, NULL, 9, 0, ADCx}, /* D40/EXT2_24/PC9 */ - - /* JTAG header */ - - {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D41/JTAG7/PA13 */ - {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D42/JTAG9/PA14 */ - {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D43/JTAG5/PA15 */ - {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D44/JTAG13/PB3 */ - {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D45/JTAG3/PB4 */ -}; - -extern const uint8 boardPWMPins[] __FLASH__ = { - 0, 1, 3, 4, 10, 11, 12, 13, 14, 18, 19, 21, 23, 24, 25, 27 -}; - -extern const uint8 boardADCPins[] __FLASH__ = { - 11, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 -}; - -extern const uint8 boardUsedPins[] __FLASH__ = { - BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, - BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN -}; - -#endif diff --git a/wirish/boards/olimex_stm32_h103.h b/wirish/boards/olimex_stm32_h103.h deleted file mode 100644 index d2b5fcc..0000000 --- a/wirish/boards/olimex_stm32_h103.h +++ /dev/null @@ -1,92 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * Copyright (c) 2011 David Kiliani. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file olimex_stm32_h103.h - * @author David Kiliani - * @brief Private include file for Olimex STM32_H103 in boards.h - */ - -#ifndef _BOARD_OLIMEX_STM32_H103_H_ -#define _BOARD_OLIMEX_STM32_H103_H_ - -#define CYCLES_PER_MICROSECOND 72 -#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ - -#define BOARD_BUTTON_PIN 23 -#define BOARD_LED_PIN 7 - -/* Number of USARTs/UARTs whose pins are broken out to headers */ -#define BOARD_NR_USARTS 3 - -/* Default USART pin numbers (not considering AFIO remap) */ -#define BOARD_USART1_TX_PIN 3 -#define BOARD_USART1_RX_PIN 4 -#define BOARD_USART2_TX_PIN 24 -#define BOARD_USART2_RX_PIN 27 -#define BOARD_USART3_TX_PIN 31 -#define BOARD_USART3_RX_PIN 32 - -/* Number of SPI ports */ -#define BOARD_NR_SPI 2 - -/* Default SPI pin numbers (not considering AFIO remap) */ -#define BOARD_SPI1_NSS_PIN 28 -#define BOARD_SPI1_MOSI_PIN 19 -#define BOARD_SPI1_MISO_PIN 11 -#define BOARD_SPI1_SCK_PIN 15 -#define BOARD_SPI2_NSS_PIN 34 -#define BOARD_SPI2_MOSI_PIN 36 -#define BOARD_SPI2_MISO_PIN 35 -#define BOARD_SPI2_SCK_PIN 33 - -/* Total number of GPIO pins that are broken out to headers and - * intended for general use. */ -#define BOARD_NR_GPIO_PINS 46 - -/* Number of pins capable of PWM output */ -#define BOARD_NR_PWM_PINS 16 - -/* Number of pins capable of ADC conversion */ -#define BOARD_NR_ADC_PINS 16 - -/* Number of pins already connected to external hardware. For Maple, - * these are just BOARD_LED_PIN and BOARD_BUTTON_PIN. */ -#define BOARD_NR_USED_PINS 7 - -/* Debug port pins */ -#define BOARD_JTMS_SWDIO_PIN 41 -#define BOARD_JTCK_SWCLK_PIN 42 -#define BOARD_JTDI_PIN 43 -#define BOARD_JTDO_PIN 44 -#define BOARD_NJTRST_PIN 45 - -/* USB configuration */ -#define BOARD_USB_DISC_DEV GPIOC -#define BOARD_USB_DISC_BIT 11 - -#endif diff --git a/wirish/boards/olimex_stm32_h103/board.cpp b/wirish/boards/olimex_stm32_h103/board.cpp new file mode 100644 index 0000000..d9b8033 --- /dev/null +++ b/wirish/boards/olimex_stm32_h103/board.cpp @@ -0,0 +1,119 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011 David Kiliani. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/olimex_stm32_h103/board.cpp + * @author David Kiliani + * @brief Olimex STM32_H103 board file. + */ + +#include + +#include +#include + +#include + +void boardInit(void) { +} + +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + + /* Header EXT1 */ + + {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D0/EXT1_1/PA11 (USBDM) */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D1/EXT1_2/PA8 */ + {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D2/EXT1_3/PA12 (USBDP) */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D3/EXT1_4/PA9 */ + + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D4/EXT1_7/PA10 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D5/EXT1_8/PC10 */ + {GPIOC, NULL, NULL, 11, 0, ADCx}, /* D6/EXT1_9/PC11 (USBpull) */ + {GPIOC, NULL, NULL, 12, 0, ADCx}, /* D7/EXT1_10/PC12 (LED) */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D8/EXT1_11/PD2 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D9/EXT1_12/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D10/EXT1_13/PB6 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D11/EXT1_14/PA6 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D12/EXT1_15/PB7 */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D13/EXT1_16/PB8 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D14/EXT1_17/PB9 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D15/EXT1_18/PA5 */ + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D16/EXT1_19/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D17/EXT1_20/PC1 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D18/EXT1_21/PB0 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D19/EXT1_22/PA7 */ + + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D20/EXT1_24/PC13 */ + + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D21/EXT1_26/PB1 */ + + /* Header EXT2 */ + + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D22/EXT2_2/PC2 */ + + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D23/EXT2_4/PA0 (BUT) */ + + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D24/EXT2_7/PA2 */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D25/EXT2_8/PA1 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D26/EXT2_9/PC3 */ + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D27/EXT2_10/PA3 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D28/EXT2_11/PA4 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D29/EXT2_12/PC4 (USB-P) */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D30/EXT2_13/PC5 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D31/EXT2_14/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D32/EXT2_15/PB11 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D33/EXT2_16/PB13 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D34/EXT2_17/PB12 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D35/EXT2_18/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D36/EXT2_19/PB15 */ + {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D37/EXT2_20/PC6 */ + {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D38/EXT2_21/PC7 */ + {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D39/EXT2_22/PC8 */ + + {GPIOC, NULL, NULL, 9, 0, ADCx}, /* D40/EXT2_24/PC9 */ + + /* JTAG header */ + + {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D41/JTAG7/PA13 */ + {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D42/JTAG9/PA14 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D43/JTAG5/PA15 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D44/JTAG13/PB3 */ + {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D45/JTAG3/PB4 */ +}; + +extern const uint8 boardPWMPins[] __FLASH__ = { + 0, 1, 3, 4, 10, 11, 12, 13, 14, 18, 19, 21, 23, 24, 25, 27 +}; + +extern const uint8 boardADCPins[] __FLASH__ = { + 11, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 +}; + +extern const uint8 boardUsedPins[] __FLASH__ = { + BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, + BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN +}; diff --git a/wirish/boards/olimex_stm32_h103/include/board/board.h b/wirish/boards/olimex_stm32_h103/include/board/board.h new file mode 100644 index 0000000..b312e26 --- /dev/null +++ b/wirish/boards/olimex_stm32_h103/include/board/board.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011 David Kiliani. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/olimex_stm32_h103/include/board/board.h + * @author David Kiliani + * @brief Olimex STM32_H103 board header. + */ + +#ifndef _BOARD_OLIMEX_STM32_H103_H_ +#define _BOARD_OLIMEX_STM32_H103_H_ + +#define CYCLES_PER_MICROSECOND 72 +#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ + +#define BOARD_BUTTON_PIN 23 +#define BOARD_LED_PIN 7 + +/* Number of USARTs/UARTs whose pins are broken out to headers */ +#define BOARD_NR_USARTS 3 + +/* Default USART pin numbers (not considering AFIO remap) */ +#define BOARD_USART1_TX_PIN 3 +#define BOARD_USART1_RX_PIN 4 +#define BOARD_USART2_TX_PIN 24 +#define BOARD_USART2_RX_PIN 27 +#define BOARD_USART3_TX_PIN 31 +#define BOARD_USART3_RX_PIN 32 + +/* Number of SPI ports */ +#define BOARD_NR_SPI 2 + +/* Default SPI pin numbers (not considering AFIO remap) */ +#define BOARD_SPI1_NSS_PIN 28 +#define BOARD_SPI1_MOSI_PIN 19 +#define BOARD_SPI1_MISO_PIN 11 +#define BOARD_SPI1_SCK_PIN 15 +#define BOARD_SPI2_NSS_PIN 34 +#define BOARD_SPI2_MOSI_PIN 36 +#define BOARD_SPI2_MISO_PIN 35 +#define BOARD_SPI2_SCK_PIN 33 + +/* Total number of GPIO pins that are broken out to headers and + * intended for general use. */ +#define BOARD_NR_GPIO_PINS 46 + +/* Number of pins capable of PWM output */ +#define BOARD_NR_PWM_PINS 16 + +/* Number of pins capable of ADC conversion */ +#define BOARD_NR_ADC_PINS 16 + +/* Number of pins already connected to external hardware. For Maple, + * these are just BOARD_LED_PIN and BOARD_BUTTON_PIN. */ +#define BOARD_NR_USED_PINS 7 + +/* Debug port pins */ +#define BOARD_JTMS_SWDIO_PIN 41 +#define BOARD_JTCK_SWCLK_PIN 42 +#define BOARD_JTDI_PIN 43 +#define BOARD_JTDO_PIN 44 +#define BOARD_NJTRST_PIN 45 + +/* USB configuration */ +#define BOARD_USB_DISC_DEV GPIOC +#define BOARD_USB_DISC_BIT 11 + +#endif diff --git a/wirish/comm/HardwareSPI.cpp b/wirish/comm/HardwareSPI.cpp index 21ae180..e1f186e 100644 --- a/wirish/comm/HardwareSPI.cpp +++ b/wirish/comm/HardwareSPI.cpp @@ -29,14 +29,14 @@ * @brief Wirish SPI implementation. */ -#include "HardwareSPI.h" +#include -#include "timer.h" -#include "util.h" -#include "rcc.h" +#include +#include +#include -#include "wirish.h" -#include "boards.h" +#include +#include struct spi_pins { uint8 nss; diff --git a/wirish/comm/HardwareSPI.h b/wirish/comm/HardwareSPI.h deleted file mode 100644 index d138910..0000000 --- a/wirish/comm/HardwareSPI.h +++ /dev/null @@ -1,223 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file HardwareSPI.h - * @brief High-level SPI interface - * - * This is a "bare essentials" polling driver for now. - */ - -/* TODO [0.1.0] Remove deprecated methods. */ - -#include "libmaple_types.h" -#include "spi.h" - -#include "boards.h" - -#ifndef _HARDWARESPI_H_ -#define _HARDWARESPI_H_ - -/** - * @brief Defines the possible SPI communication speeds. - */ -typedef enum SPIFrequency { - SPI_18MHZ = 0, /**< 18 MHz */ - SPI_9MHZ = 1, /**< 9 MHz */ - SPI_4_5MHZ = 2, /**< 4.5 MHz */ - SPI_2_25MHZ = 3, /**< 2.25 MHz */ - SPI_1_125MHZ = 4, /**< 1.125 MHz */ - SPI_562_500KHZ = 5, /**< 562.500 KHz */ - SPI_281_250KHZ = 6, /**< 281.250 KHz */ - SPI_140_625KHZ = 7, /**< 140.625 KHz */ -} SPIFrequency; - -#define MAX_SPI_FREQS 8 - -#if CYCLES_PER_MICROSECOND != 72 -/* TODO [0.2.0?] something smarter than this */ -#warning "Unexpected clock speed; SPI frequency calculation will be incorrect" -#endif - -/** - * @brief Wirish SPI interface. - * - * This implementation uses software slave management, so the caller - * is responsible for controlling the slave select line. - */ -class HardwareSPI { -public: - /** - * @param spiPortNumber Number of the SPI port to manage. - */ - HardwareSPI(uint32 spiPortNumber); - - /* - * Set up/tear down - */ - - /** - * @brief Turn on a SPI port and set its GPIO pin modes for use as master. - * - * SPI port is enabled in full duplex mode, with software slave management. - * - * @param frequency Communication frequency - * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST (big-endian) - * @param mode SPI mode to use, one of SPI_MODE_0, SPI_MODE_1, - * SPI_MODE_2, and SPI_MODE_3. - */ - void begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode); - - /** - * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0). - */ - void begin(void); - - /** - * @brief Turn on a SPI port and set its GPIO pin modes for use as a slave. - * - * SPI port is enabled in full duplex mode, with software slave management. - * - * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST(big-endian) - * @param mode SPI mode to use - */ - void beginSlave(uint32 bitOrder, uint32 mode); - - /** - * @brief Equivalent to beginSlave(MSBFIRST, 0). - */ - void beginSlave(void); - - /** - * @brief Disables the SPI port, but leaves its GPIO pin modes unchanged. - */ - void end(void); - - /* - * I/O - */ - - /** - * @brief Return the next unread byte. - * - * If there is no unread byte waiting, this function will block - * until one is received. - */ - uint8 read(void); - - /** - * @brief Read length bytes, storing them into buffer. - * @param buffer Buffer to store received bytes into. - * @param length Number of bytes to store in buffer. This - * function will block until the desired number of - * bytes have been read. - */ - void read(uint8 *buffer, uint32 length); - - /** - * @brief Transmit a byte. - * @param data Byte to transmit. - */ - void write(uint8 data); - - /** - * @brief Transmit multiple bytes. - * @param buffer Bytes to transmit. - * @param length Number of bytes in buffer to transmit. - */ - void write(const uint8 *buffer, uint32 length); - - /** - * @brief Transmit a byte, then return the next unread byte. - * - * This function transmits before receiving. - * - * @param data Byte to transmit. - * @return Next unread byte. - */ - uint8 transfer(uint8 data); - - /* - * Pin accessors - */ - - /** - * @brief Return the number of the MISO (master in, slave out) pin - */ - uint8 misoPin(void); - - /** - * @brief Return the number of the MOSI (master out, slave in) pin - */ - uint8 mosiPin(void); - - /** - * @brief Return the number of the SCK (serial clock) pin - */ - uint8 sckPin(void); - - /** - * @brief Return the number of the NSS (slave select) pin - */ - uint8 nssPin(void); - - /* -- The following methods are deprecated --------------------------- */ - - /** - * @brief Deprecated. - * - * Use HardwareSPI::transfer() instead. - * - * @see HardwareSPI::transfer() - */ - uint8 send(uint8 data); - - /** - * @brief Deprecated. - * - * Use HardwareSPI::write() in combination with - * HardwareSPI::read() (or HardwareSPI::transfer()) instead. - * - * @see HardwareSPI::write() - * @see HardwareSPI::read() - * @see HardwareSPI::transfer() - */ - uint8 send(uint8 *data, uint32 length); - - /** - * @brief Deprecated. - * - * Use HardwareSPI::read() instead. - * - * @see HardwareSPI::read() - */ - uint8 recv(void); -private: - spi_dev *spi_d; -}; - -#endif - diff --git a/wirish/comm/HardwareSerial.cpp b/wirish/comm/HardwareSerial.cpp index 6ef9222..a9eb763 100644 --- a/wirish/comm/HardwareSerial.cpp +++ b/wirish/comm/HardwareSerial.cpp @@ -29,12 +29,13 @@ * @brief Wirish serial port implementation. */ -#include "libmaple.h" -#include "gpio.h" -#include "timer.h" +#include -#include "HardwareSerial.h" -#include "boards.h" +#include +#include +#include + +#include #define TX1 BOARD_USART1_TX_PIN #define RX1 BOARD_USART1_RX_PIN diff --git a/wirish/comm/HardwareSerial.h b/wirish/comm/HardwareSerial.h deleted file mode 100644 index f69b67a..0000000 --- a/wirish/comm/HardwareSerial.h +++ /dev/null @@ -1,86 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file HardwareSerial.h - * @brief Wirish serial port interface. - */ - -#ifndef _HARDWARESERIAL_H_ -#define _HARDWARESERIAL_H_ - -#include "libmaple_types.h" -#include "usart.h" - -#include "Print.h" - -/* - * IMPORTANT: - * - * This class documented "by hand" (i.e., not using Doxygen) in the - * leaflabs-docs/ repository. - * - * If you alter the public HardwareSerial interface, you MUST update - * the documentation accordingly. - */ - -class HardwareSerial : public Print { -public: - HardwareSerial(usart_dev *usart_device, - uint8 tx_pin, - uint8 rx_pin, - uint32 clock_speed); - - /* Set up/tear down */ - void begin(uint32 baud); - void end(void); - - /* I/O */ - uint32 available(void); - uint8 read(void); - void flush(void); - virtual void write(unsigned char); - using Print::write; - - /* Pin accessors */ - int txPin(void) { return this->tx_pin; } - int rxPin(void) { return this->rx_pin; } -private: - usart_dev *usart_device; - uint8 tx_pin; - uint8 rx_pin; - uint32 clock_speed; -}; - -extern HardwareSerial Serial1; -extern HardwareSerial Serial2; -extern HardwareSerial Serial3; -#if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6) -extern HardwareSerial Serial4; -extern HardwareSerial Serial5; -#endif - -#endif diff --git a/wirish/ext_interrupts.cpp b/wirish/ext_interrupts.cpp index b7f96f9..8f8c768 100644 --- a/wirish/ext_interrupts.cpp +++ b/wirish/ext_interrupts.cpp @@ -30,12 +30,12 @@ * @brief Wiring-like interface for external interrupts */ -#include "ext_interrupts.h" +#include -#include "gpio.h" -#include "exti.h" +#include +#include -#include "boards.h" +#include static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode); diff --git a/wirish/ext_interrupts.h b/wirish/ext_interrupts.h deleted file mode 100644 index b5c6f98..0000000 --- a/wirish/ext_interrupts.h +++ /dev/null @@ -1,106 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -#include "libmaple_types.h" -#include "nvic.h" - -/** - * @file ext_interrupts.h - * - * @brief Wiring-like external interrupt prototypes and types. - */ - -#ifndef _EXT_INTERRUPTS_H_ -#define _EXT_INTERRUPTS_H_ - -/** - * The kind of transition on an external pin which should trigger an - * interrupt. - */ -typedef enum ExtIntTriggerMode { - RISING, /**< To trigger an interrupt when the pin transitions LOW - to HIGH */ - FALLING, /**< To trigger an interrupt when the pin transitions - HIGH to LOW */ - CHANGE /**< To trigger an interrupt when the pin transitions from - LOW to HIGH or HIGH to LOW (i.e., when the pin - changes). */ -} ExtIntTriggerMode; - -/** - * @brief Registers an interrupt handler on a pin. - * - * The interrupt will be triggered on a given transition on the pin, - * as specified by the mode parameter. The handler runs in interrupt - * context. The new handler will replace whatever handler is - * currently registered for the pin, if any. - * - * @param pin Maple pin number - * @param handler Function to run upon external interrupt trigger. - * The handler should take no arguments, and have void return type. - * @param mode Type of transition to trigger on, e.g. falling, rising, etc. - * - * @sideeffect Registers a handler - * @see detachInterrupt() - */ -void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode); - -/** - * @brief Disable any registered external interrupt. - * @param pin Maple pin number - * @sideeffect unregisters external interrupt handler - * @see attachInterrupt() - */ -void detachInterrupt(uint8 pin); - -/** - * Re-enable interrupts. - * - * Call this after noInterrupts() to re-enable interrupt handling, - * after you have finished with a timing-critical section of code. - * - * @see noInterrupts() - */ -static inline void interrupts() { - nvic_globalirq_enable(); -} - -/** - * Disable interrupts. - * - * After calling this function, all user-programmable interrupts will - * be disabled. You can call this function before a timing-critical - * section of code, then call interrupts() to re-enable interrupt - * handling. - * - * @see interrupts() - */ -static inline void noInterrupts() { - nvic_globalirq_disable(); -} - -#endif - diff --git a/wirish/include/wirish/HardwareSPI.h b/wirish/include/wirish/HardwareSPI.h new file mode 100644 index 0000000..ad95191 --- /dev/null +++ b/wirish/include/wirish/HardwareSPI.h @@ -0,0 +1,222 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file HardwareSPI.h + * @brief High-level SPI interface + * + * This is a "bare essentials" polling driver for now. + */ + +/* TODO [0.1.0] Remove deprecated methods. */ + +#include +#include + +#include + +#ifndef _WIRISH_HARDWARESPI_H_ +#define _WIRISH_HARDWARESPI_H_ + +/** + * @brief Defines the possible SPI communication speeds. + */ +typedef enum SPIFrequency { + SPI_18MHZ = 0, /**< 18 MHz */ + SPI_9MHZ = 1, /**< 9 MHz */ + SPI_4_5MHZ = 2, /**< 4.5 MHz */ + SPI_2_25MHZ = 3, /**< 2.25 MHz */ + SPI_1_125MHZ = 4, /**< 1.125 MHz */ + SPI_562_500KHZ = 5, /**< 562.500 KHz */ + SPI_281_250KHZ = 6, /**< 281.250 KHz */ + SPI_140_625KHZ = 7, /**< 140.625 KHz */ +} SPIFrequency; + +#define MAX_SPI_FREQS 8 + +#if CYCLES_PER_MICROSECOND != 72 +/* TODO [0.2.0?] something smarter than this */ +#warning "Unexpected clock speed; SPI frequency calculation will be incorrect" +#endif + +/** + * @brief Wirish SPI interface. + * + * This implementation uses software slave management, so the caller + * is responsible for controlling the slave select line. + */ +class HardwareSPI { +public: + /** + * @param spiPortNumber Number of the SPI port to manage. + */ + HardwareSPI(uint32 spiPortNumber); + + /* + * Set up/tear down + */ + + /** + * @brief Turn on a SPI port and set its GPIO pin modes for use as master. + * + * SPI port is enabled in full duplex mode, with software slave management. + * + * @param frequency Communication frequency + * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST (big-endian) + * @param mode SPI mode to use, one of SPI_MODE_0, SPI_MODE_1, + * SPI_MODE_2, and SPI_MODE_3. + */ + void begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode); + + /** + * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0). + */ + void begin(void); + + /** + * @brief Turn on a SPI port and set its GPIO pin modes for use as a slave. + * + * SPI port is enabled in full duplex mode, with software slave management. + * + * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST(big-endian) + * @param mode SPI mode to use + */ + void beginSlave(uint32 bitOrder, uint32 mode); + + /** + * @brief Equivalent to beginSlave(MSBFIRST, 0). + */ + void beginSlave(void); + + /** + * @brief Disables the SPI port, but leaves its GPIO pin modes unchanged. + */ + void end(void); + + /* + * I/O + */ + + /** + * @brief Return the next unread byte. + * + * If there is no unread byte waiting, this function will block + * until one is received. + */ + uint8 read(void); + + /** + * @brief Read length bytes, storing them into buffer. + * @param buffer Buffer to store received bytes into. + * @param length Number of bytes to store in buffer. This + * function will block until the desired number of + * bytes have been read. + */ + void read(uint8 *buffer, uint32 length); + + /** + * @brief Transmit a byte. + * @param data Byte to transmit. + */ + void write(uint8 data); + + /** + * @brief Transmit multiple bytes. + * @param buffer Bytes to transmit. + * @param length Number of bytes in buffer to transmit. + */ + void write(const uint8 *buffer, uint32 length); + + /** + * @brief Transmit a byte, then return the next unread byte. + * + * This function transmits before receiving. + * + * @param data Byte to transmit. + * @return Next unread byte. + */ + uint8 transfer(uint8 data); + + /* + * Pin accessors + */ + + /** + * @brief Return the number of the MISO (master in, slave out) pin + */ + uint8 misoPin(void); + + /** + * @brief Return the number of the MOSI (master out, slave in) pin + */ + uint8 mosiPin(void); + + /** + * @brief Return the number of the SCK (serial clock) pin + */ + uint8 sckPin(void); + + /** + * @brief Return the number of the NSS (slave select) pin + */ + uint8 nssPin(void); + + /* -- The following methods are deprecated --------------------------- */ + + /** + * @brief Deprecated. + * + * Use HardwareSPI::transfer() instead. + * + * @see HardwareSPI::transfer() + */ + uint8 send(uint8 data); + + /** + * @brief Deprecated. + * + * Use HardwareSPI::write() in combination with + * HardwareSPI::read() (or HardwareSPI::transfer()) instead. + * + * @see HardwareSPI::write() + * @see HardwareSPI::read() + * @see HardwareSPI::transfer() + */ + uint8 send(uint8 *data, uint32 length); + + /** + * @brief Deprecated. + * + * Use HardwareSPI::read() instead. + * + * @see HardwareSPI::read() + */ + uint8 recv(void); +private: + spi_dev *spi_d; +}; + +#endif diff --git a/wirish/include/wirish/HardwareSerial.h b/wirish/include/wirish/HardwareSerial.h new file mode 100644 index 0000000..c25fd6e --- /dev/null +++ b/wirish/include/wirish/HardwareSerial.h @@ -0,0 +1,86 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file HardwareSerial.h + * @brief Wirish serial port interface. + */ + +#ifndef _WIRISH_HARDWARESERIAL_H_ +#define _WIRISH_HARDWARESERIAL_H_ + +#include +#include + +#include + +/* + * IMPORTANT: + * + * This class documented "by hand" (i.e., not using Doxygen) in the + * leaflabs-docs/ repository. + * + * If you alter the public HardwareSerial interface, you MUST update + * the documentation accordingly. + */ + +class HardwareSerial : public Print { +public: + HardwareSerial(usart_dev *usart_device, + uint8 tx_pin, + uint8 rx_pin, + uint32 clock_speed); + + /* Set up/tear down */ + void begin(uint32 baud); + void end(void); + + /* I/O */ + uint32 available(void); + uint8 read(void); + void flush(void); + virtual void write(unsigned char); + using Print::write; + + /* Pin accessors */ + int txPin(void) { return this->tx_pin; } + int rxPin(void) { return this->rx_pin; } +private: + usart_dev *usart_device; + uint8 tx_pin; + uint8 rx_pin; + uint32 clock_speed; +}; + +extern HardwareSerial Serial1; +extern HardwareSerial Serial2; +extern HardwareSerial Serial3; +#if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6) +extern HardwareSerial Serial4; +extern HardwareSerial Serial5; +#endif + +#endif diff --git a/wirish/include/wirish/HardwareTimer.h b/wirish/include/wirish/HardwareTimer.h new file mode 100644 index 0000000..bdcca5d --- /dev/null +++ b/wirish/include/wirish/HardwareTimer.h @@ -0,0 +1,331 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @brief Wirish timer class. + */ + +#ifndef _WIRISH_HARDWARETIMER_H_ +#define _WIRISH_HARDWARETIMER_H_ + +// TODO [0.1.0] Remove deprecated pieces, pick a better API + +#include + +/** Timer mode. */ +typedef timer_mode TimerMode; + +/** @brief Deprecated; use TIMER_OUTPUT_COMPARE instead. */ +#define TIMER_OUTPUTCOMPARE TIMER_OUTPUT_COMPARE + +/** + * @brief Interface to one of the 16-bit timer peripherals. + */ +class HardwareTimer { +private: + timer_dev *dev; + +public: + /** + * @brief Construct a new HardwareTimer instance. + * @param timerNum number of the timer to control. + */ + HardwareTimer(uint8 timerNum); + + /** + * @brief Stop the counter, without affecting its configuration. + * + * @see HardwareTimer::resume() + */ + void pause(void); + + /** + * @brief Resume a paused timer, without affecting its configuration. + * + * The timer will resume counting and firing interrupts as + * appropriate. + * + * Note that there is some function call overhead associated with + * using this method, so using it in concert with + * HardwareTimer::pause() is not a robust way to align multiple + * timers to the same count value. + * + * @see HardwareTimer::pause() + */ + void resume(void); + + /** + * @brief Get the timer's prescale factor. + * @return Timer prescaler, from 1 to 65,536. + * @see HardwareTimer::setPrescaleFactor() + */ + uint32 getPrescaleFactor(); + + /** + * @brief Set the timer's prescale factor. + * + * The new value won't take effect until the next time the counter + * overflows. You can force the counter to reset using + * HardwareTimer::refresh(). + * + * @param factor The new prescale value to set, from 1 to 65,536. + * @see HardwareTimer::refresh() + */ + void setPrescaleFactor(uint32 factor); + + /** + * @brief Get the timer overflow value. + * @see HardwareTimer::setOverflow() + */ + uint16 getOverflow(); + + /** + * @brief Set the timer overflow (or "reload") value. + * + * The new value won't take effect until the next time the counter + * overflows. You can force the counter to reset using + * HardwareTimer::refresh(). + * + * @param val The new overflow value to set + * @see HardwareTimer::refresh() + */ + void setOverflow(uint16 val); + + /** + * @brief Get the current timer count. + * + * @return The timer's current count value + */ + uint16 getCount(void); + + /** + * @brief Set the current timer count. + * + * @param val The new count value to set. If this value exceeds + * the timer's overflow value, it is truncated to the + * overflow value. + */ + void setCount(uint16 val); + + /** + * @brief Set the timer's period in microseconds. + * + * Configures the prescaler and overflow values to generate a timer + * reload with a period as close to the given number of + * microseconds as possible. + * + * @param microseconds The desired period of the timer. This must be + * greater than zero. + * @return The new overflow value. + */ + uint16 setPeriod(uint32 microseconds); + + /** + * @brief Configure a timer channel's mode. + * @param channel Timer channel, from 1 to 4 + * @param mode Mode to set + */ + void setMode(int channel, timer_mode mode); + + /** + * @brief Get the compare value for the given channel. + * @see HardwareTimer::setCompare() + */ + uint16 getCompare(int channel); + + /** + * @brief Set the compare value for the given channel. + * + * @param channel the channel whose compare to set, from 1 to 4. + * @param compare The compare value to set. If greater than this + * timer's overflow value, it will be truncated to + * the overflow value. + * + * @see timer_mode + * @see HardwareTimer::setMode() + * @see HardwareTimer::attachInterrupt() + */ + void setCompare(int channel, uint16 compare); + + /** + * @brief Attach an interrupt handler to the given channel. + * + * This interrupt handler will be called when the timer's counter + * reaches the given channel compare value. + * + * @param channel the channel to attach the ISR to, from 1 to 4. + * @param handler The ISR to attach to the given channel. + * @see voidFuncPtr + */ + void attachInterrupt(int channel, voidFuncPtr handler); + + /** + * @brief Remove the interrupt handler attached to the given + * channel, if any. + * + * The handler will no longer be called by this timer. + * + * @param channel the channel whose interrupt to detach, from 1 to 4. + * @see HardwareTimer::attachInterrupt() + */ + void detachInterrupt(int channel); + + /** + * @brief Reset the counter, and update the prescaler and overflow + * values. + * + * This will reset the counter to 0 in upcounting mode (the + * default). It will also update the timer's prescaler and + * overflow, if you have set them up to be changed using + * HardwareTimer::setPrescaleFactor() or + * HardwareTimer::setOverflow(). + * + * @see HardwareTimer::setPrescaleFactor() + * @see HardwareTimer::setOverflow() + */ + void refresh(void); + + /* -- Deprecated methods ----------------------------------------------- */ + + /** @brief Deprecated; use setMode(channel, mode) instead. */ + void setChannelMode(int channel, timer_mode mode) { + setMode(channel, mode); + } + + /** @brief Deprecated; use setMode(TIMER_CH1, mode) instead. */ + void setChannel1Mode(timer_mode mode) { setMode(TIMER_CH1, mode); } + + /** @brief Deprecated; use setMode(TIMER_CH2, mode) instead. */ + void setChannel2Mode(timer_mode mode) { setMode(TIMER_CH2, mode); } + + /** @brief Deprecated; use setMode(TIMER_CH3, mode) instead. */ + void setChannel3Mode(timer_mode mode) { setMode(TIMER_CH3, mode); } + + /** @brief Deprecated; use setMode(TIMER_CH4, mode) instead. */ + void setChannel4Mode(timer_mode mode) { setMode(TIMER_CH4, mode); } + + /** @brief Deprecated; use return getCompare(TIMER_CH1) instead. */ + uint16 getCompare1() { return getCompare(TIMER_CH1); } + + /** @brief Deprecated; use return getCompare(TIMER_CH2) instead. */ + uint16 getCompare2() { return getCompare(TIMER_CH2); } + + /** @brief Deprecated; use return getCompare(TIMER_CH3) instead. */ + uint16 getCompare3() { return getCompare(TIMER_CH3); } + + /** @brief Deprecated; use return getCompare(TIMER_CH4) instead. */ + uint16 getCompare4() { return getCompare(TIMER_CH4); } + + /** @brief Deprecated; use setCompare(TIMER_CH1, compare) instead. */ + void setCompare1(uint16 compare) { setCompare(TIMER_CH1, compare); } + + /** @brief Deprecated; use setCompare(TIMER_CH2, compare) instead. */ + void setCompare2(uint16 compare) { setCompare(TIMER_CH2, compare); } + + /** @brief Deprecated; use setCompare(TIMER_CH3, compare) instead. */ + void setCompare3(uint16 compare) { setCompare(TIMER_CH3, compare); } + + /** @brief Deprecated; use setCompare(TIMER_CH4, compare) instead. */ + void setCompare4(uint16 compare) { setCompare(TIMER_CH4, compare); } + + /** @brief Deprecated; use attachInterrupt(TIMER_CH1, handler) instead. */ + void attachCompare1Interrupt(voidFuncPtr handler) { + attachInterrupt(TIMER_CH1, handler); + } + + /** @brief Deprecated; use attachInterrupt(TIMER_CH2, handler) instead. */ + void attachCompare2Interrupt(voidFuncPtr handler) { + attachInterrupt(TIMER_CH2, handler); + } + + /** @brief Deprecated; use attachInterrupt(TIMER_CH3, handler) instead. */ + void attachCompare3Interrupt(voidFuncPtr handler) { + attachInterrupt(TIMER_CH3, handler); + } + + /** @brief Deprecated; use attachInterrupt(TIMER_CH4, handler) instead. */ + void attachCompare4Interrupt(voidFuncPtr handler) { + attachInterrupt(TIMER_CH4, handler); + } + + /** @brief Deprecated; use detachInterrupt(TIMER_CH1) instead. */ + void detachCompare1Interrupt(void) { detachInterrupt(TIMER_CH1); } + + /** @brief Deprecated; use detachInterrupt(TIMER_CH2) instead. */ + void detachCompare2Interrupt(void) { detachInterrupt(TIMER_CH2); } + + /** @brief Deprecated; use detachInterrupt(TIMER_CH3) instead. */ + void detachCompare3Interrupt(void) { detachInterrupt(TIMER_CH3); } + + /** @brief Deprecated; use detachInterrupt(TIMER_CH4) instead. */ + void detachCompare4Interrupt(void) { detachInterrupt(TIMER_CH4); } + + /** @brief Deprecated; use refresh() instead. */ + void generateUpdate(void) { refresh(); } +}; + +/* -- The rest of this file is deprecated. --------------------------------- */ + +/** + * @brief Deprecated. + * + * Pre-instantiated timer. + */ +extern HardwareTimer Timer1; +/** + * @brief Deprecated. + * + * Pre-instantiated timer. + */ +extern HardwareTimer Timer2; +/** + * @brief Deprecated. + * + * Pre-instantiated timer. + */ +extern HardwareTimer Timer3; +/** + * @brief Deprecated. + * + * Pre-instantiated timer. + */ +extern HardwareTimer Timer4; +#ifdef STM32_HIGH_DENSITY +/** + * @brief Deprecated. + * + * Pre-instantiated timer. + */ +extern HardwareTimer Timer5; +/** + * @brief Deprecated. + * + * Pre-instantiated timer. + */ +extern HardwareTimer Timer8; +#endif + +#endif diff --git a/wirish/include/wirish/Print.h b/wirish/include/wirish/Print.h new file mode 100644 index 0000000..5fd0b7a --- /dev/null +++ b/wirish/include/wirish/Print.h @@ -0,0 +1,67 @@ +/* + * Print.h - Base class that provides print() and println() + * Copyright (c) 2008 David A. Mellis. All right reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA. + * + * Modified 12 April 2011 by Marti Bolivar + */ + +#ifndef _WIRISH_PRINT_H_ +#define _WIRISH_PRINT_H_ + +#include + +enum { + BYTE = 0, + BIN = 2, + OCT = 8, + DEC = 10, + HEX = 16 +}; + +class Print { +public: + virtual void write(uint8 ch) = 0; + virtual void write(const char *str); + virtual void write(const void *buf, uint32 len); + void print(char); + void print(const char[]); + void print(uint8, int=DEC); + void print(int, int=DEC); + void print(unsigned int, int=DEC); + void print(long, int=DEC); + void print(unsigned long, int=DEC); + void print(long long, int=DEC); + void print(unsigned long long, int=DEC); + void print(double, int=2); + void println(void); + void println(char); + void println(const char[]); + void println(uint8, int=DEC); + void println(int, int=DEC); + void println(unsigned int, int=DEC); + void println(long, int=DEC); + void println(unsigned long, int=DEC); + void println(long long, int=DEC); + void println(unsigned long long, int=DEC); + void println(double, int=2); +private: + void printNumber(unsigned long long, uint8); + void printFloat(double, uint8); +}; + +#endif diff --git a/wirish/include/wirish/WProgram.h b/wirish/include/wirish/WProgram.h new file mode 100644 index 0000000..b24ec2a --- /dev/null +++ b/wirish/include/wirish/WProgram.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#ifndef _WIRISH_WPROGRAM_H_ +#define _WIRISH_WPROGRAM_H_ + +#include + +void setup(); +void loop(); + +#endif diff --git a/wirish/include/wirish/bit_constants.h b/wirish/include/wirish/bit_constants.h new file mode 100644 index 0000000..4638f76 --- /dev/null +++ b/wirish/include/wirish/bit_constants.h @@ -0,0 +1,579 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @brief BIT[n] and binary literal defines, for Arduino + * compatibility. + */ + +#ifndef _WIRISH_BIT_CONSTANTS_H_ +#define _WIRISH_BIT_CONSTANTS_H_ + +#define BIT0 (1 << 0) +#define BIT1 (1 << 1) +#define BIT2 (1 << 2) +#define BIT3 (1 << 3) +#define BIT4 (1 << 4) +#define BIT5 (1 << 5) +#define BIT6 (1 << 6) +#define BIT7 (1 << 7) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) +#define BIT10 (1 << 10) +#define BIT11 (1 << 11) +#define BIT12 (1 << 12) +#define BIT13 (1 << 13) +#define BIT14 (1 << 14) +#define BIT15 (1 << 15) +#define BIT16 (1 << 16) +#define BIT17 (1 << 17) +#define BIT18 (1 << 18) +#define BIT19 (1 << 19) +#define BIT20 (1 << 20) +#define BIT21 (1 << 21) +#define BIT22 (1 << 22) +#define BIT23 (1 << 23) +#define BIT24 (1 << 24) +#define BIT25 (1 << 25) +#define BIT26 (1 << 26) +#define BIT27 (1 << 27) +#define BIT28 (1 << 28) +#define BIT29 (1 << 29) +#define BIT30 (1 << 30) +#define BIT31 (1 << 31) + +#define B0 0 +#define B00 0 +#define B000 0 +#define B0000 0 +#define B00000 0 +#define B000000 0 +#define B0000000 0 +#define B00000000 0 +#define B1 1 +#define B01 1 +#define B001 1 +#define B0001 1 +#define B00001 1 +#define B000001 1 +#define B0000001 1 +#define B00000001 1 +#define B10 2 +#define B010 2 +#define B0010 2 +#define B00010 2 +#define B000010 2 +#define B0000010 2 +#define B00000010 2 +#define B11 3 +#define B011 3 +#define B0011 3 +#define B00011 3 +#define B000011 3 +#define B0000011 3 +#define B00000011 3 +#define B100 4 +#define B0100 4 +#define B00100 4 +#define B000100 4 +#define B0000100 4 +#define B00000100 4 +#define B101 5 +#define B0101 5 +#define B00101 5 +#define B000101 5 +#define B0000101 5 +#define B00000101 5 +#define B110 6 +#define B0110 6 +#define B00110 6 +#define B000110 6 +#define B0000110 6 +#define B00000110 6 +#define B111 7 +#define B0111 7 +#define B00111 7 +#define B000111 7 +#define B0000111 7 +#define B00000111 7 +#define B1000 8 +#define B01000 8 +#define B001000 8 +#define B0001000 8 +#define B00001000 8 +#define B1001 9 +#define B01001 9 +#define B001001 9 +#define B0001001 9 +#define B00001001 9 +#define B1010 10 +#define B01010 10 +#define B001010 10 +#define B0001010 10 +#define B00001010 10 +#define B1011 11 +#define B01011 11 +#define B001011 11 +#define B0001011 11 +#define B00001011 11 +#define B1100 12 +#define B01100 12 +#define B001100 12 +#define B0001100 12 +#define B00001100 12 +#define B1101 13 +#define B01101 13 +#define B001101 13 +#define B0001101 13 +#define B00001101 13 +#define B1110 14 +#define B01110 14 +#define B001110 14 +#define B0001110 14 +#define B00001110 14 +#define B1111 15 +#define B01111 15 +#define B001111 15 +#define B0001111 15 +#define B00001111 15 +#define B10000 16 +#define B010000 16 +#define B0010000 16 +#define B00010000 16 +#define B10001 17 +#define B010001 17 +#define B0010001 17 +#define B00010001 17 +#define B10010 18 +#define B010010 18 +#define B0010010 18 +#define B00010010 18 +#define B10011 19 +#define B010011 19 +#define B0010011 19 +#define B00010011 19 +#define B10100 20 +#define B010100 20 +#define B0010100 20 +#define B00010100 20 +#define B10101 21 +#define B010101 21 +#define B0010101 21 +#define B00010101 21 +#define B10110 22 +#define B010110 22 +#define B0010110 22 +#define B00010110 22 +#define B10111 23 +#define B010111 23 +#define B0010111 23 +#define B00010111 23 +#define B11000 24 +#define B011000 24 +#define B0011000 24 +#define B00011000 24 +#define B11001 25 +#define B011001 25 +#define B0011001 25 +#define B00011001 25 +#define B11010 26 +#define B011010 26 +#define B0011010 26 +#define B00011010 26 +#define B11011 27 +#define B011011 27 +#define B0011011 27 +#define B00011011 27 +#define B11100 28 +#define B011100 28 +#define B0011100 28 +#define B00011100 28 +#define B11101 29 +#define B011101 29 +#define B0011101 29 +#define B00011101 29 +#define B11110 30 +#define B011110 30 +#define B0011110 30 +#define B00011110 30 +#define B11111 31 +#define B011111 31 +#define B0011111 31 +#define B00011111 31 +#define B100000 32 +#define B0100000 32 +#define B00100000 32 +#define B100001 33 +#define B0100001 33 +#define B00100001 33 +#define B100010 34 +#define B0100010 34 +#define B00100010 34 +#define B100011 35 +#define B0100011 35 +#define B00100011 35 +#define B100100 36 +#define B0100100 36 +#define B00100100 36 +#define B100101 37 +#define B0100101 37 +#define B00100101 37 +#define B100110 38 +#define B0100110 38 +#define B00100110 38 +#define B100111 39 +#define B0100111 39 +#define B00100111 39 +#define B101000 40 +#define B0101000 40 +#define B00101000 40 +#define B101001 41 +#define B0101001 41 +#define B00101001 41 +#define B101010 42 +#define B0101010 42 +#define B00101010 42 +#define B101011 43 +#define B0101011 43 +#define B00101011 43 +#define B101100 44 +#define B0101100 44 +#define B00101100 44 +#define B101101 45 +#define B0101101 45 +#define B00101101 45 +#define B101110 46 +#define B0101110 46 +#define B00101110 46 +#define B101111 47 +#define B0101111 47 +#define B00101111 47 +#define B110000 48 +#define B0110000 48 +#define B00110000 48 +#define B110001 49 +#define B0110001 49 +#define B00110001 49 +#define B110010 50 +#define B0110010 50 +#define B00110010 50 +#define B110011 51 +#define B0110011 51 +#define B00110011 51 +#define B110100 52 +#define B0110100 52 +#define B00110100 52 +#define B110101 53 +#define B0110101 53 +#define B00110101 53 +#define B110110 54 +#define B0110110 54 +#define B00110110 54 +#define B110111 55 +#define B0110111 55 +#define B00110111 55 +#define B111000 56 +#define B0111000 56 +#define B00111000 56 +#define B111001 57 +#define B0111001 57 +#define B00111001 57 +#define B111010 58 +#define B0111010 58 +#define B00111010 58 +#define B111011 59 +#define B0111011 59 +#define B00111011 59 +#define B111100 60 +#define B0111100 60 +#define B00111100 60 +#define B111101 61 +#define B0111101 61 +#define B00111101 61 +#define B111110 62 +#define B0111110 62 +#define B00111110 62 +#define B111111 63 +#define B0111111 63 +#define B00111111 63 +#define B1000000 64 +#define B01000000 64 +#define B1000001 65 +#define B01000001 65 +#define B1000010 66 +#define B01000010 66 +#define B1000011 67 +#define B01000011 67 +#define B1000100 68 +#define B01000100 68 +#define B1000101 69 +#define B01000101 69 +#define B1000110 70 +#define B01000110 70 +#define B1000111 71 +#define B01000111 71 +#define B1001000 72 +#define B01001000 72 +#define B1001001 73 +#define B01001001 73 +#define B1001010 74 +#define B01001010 74 +#define B1001011 75 +#define B01001011 75 +#define B1001100 76 +#define B01001100 76 +#define B1001101 77 +#define B01001101 77 +#define B1001110 78 +#define B01001110 78 +#define B1001111 79 +#define B01001111 79 +#define B1010000 80 +#define B01010000 80 +#define B1010001 81 +#define B01010001 81 +#define B1010010 82 +#define B01010010 82 +#define B1010011 83 +#define B01010011 83 +#define B1010100 84 +#define B01010100 84 +#define B1010101 85 +#define B01010101 85 +#define B1010110 86 +#define B01010110 86 +#define B1010111 87 +#define B01010111 87 +#define B1011000 88 +#define B01011000 88 +#define B1011001 89 +#define B01011001 89 +#define B1011010 90 +#define B01011010 90 +#define B1011011 91 +#define B01011011 91 +#define B1011100 92 +#define B01011100 92 +#define B1011101 93 +#define B01011101 93 +#define B1011110 94 +#define B01011110 94 +#define B1011111 95 +#define B01011111 95 +#define B1100000 96 +#define B01100000 96 +#define B1100001 97 +#define B01100001 97 +#define B1100010 98 +#define B01100010 98 +#define B1100011 99 +#define B01100011 99 +#define B1100100 100 +#define B01100100 100 +#define B1100101 101 +#define B01100101 101 +#define B1100110 102 +#define B01100110 102 +#define B1100111 103 +#define B01100111 103 +#define B1101000 104 +#define B01101000 104 +#define B1101001 105 +#define B01101001 105 +#define B1101010 106 +#define B01101010 106 +#define B1101011 107 +#define B01101011 107 +#define B1101100 108 +#define B01101100 108 +#define B1101101 109 +#define B01101101 109 +#define B1101110 110 +#define B01101110 110 +#define B1101111 111 +#define B01101111 111 +#define B1110000 112 +#define B01110000 112 +#define B1110001 113 +#define B01110001 113 +#define B1110010 114 +#define B01110010 114 +#define B1110011 115 +#define B01110011 115 +#define B1110100 116 +#define B01110100 116 +#define B1110101 117 +#define B01110101 117 +#define B1110110 118 +#define B01110110 118 +#define B1110111 119 +#define B01110111 119 +#define B1111000 120 +#define B01111000 120 +#define B1111001 121 +#define B01111001 121 +#define B1111010 122 +#define B01111010 122 +#define B1111011 123 +#define B01111011 123 +#define B1111100 124 +#define B01111100 124 +#define B1111101 125 +#define B01111101 125 +#define B1111110 126 +#define B01111110 126 +#define B1111111 127 +#define B01111111 127 +#define B10000000 128 +#define B10000001 129 +#define B10000010 130 +#define B10000011 131 +#define B10000100 132 +#define B10000101 133 +#define B10000110 134 +#define B10000111 135 +#define B10001000 136 +#define B10001001 137 +#define B10001010 138 +#define B10001011 139 +#define B10001100 140 +#define B10001101 141 +#define B10001110 142 +#define B10001111 143 +#define B10010000 144 +#define B10010001 145 +#define B10010010 146 +#define B10010011 147 +#define B10010100 148 +#define B10010101 149 +#define B10010110 150 +#define B10010111 151 +#define B10011000 152 +#define B10011001 153 +#define B10011010 154 +#define B10011011 155 +#define B10011100 156 +#define B10011101 157 +#define B10011110 158 +#define B10011111 159 +#define B10100000 160 +#define B10100001 161 +#define B10100010 162 +#define B10100011 163 +#define B10100100 164 +#define B10100101 165 +#define B10100110 166 +#define B10100111 167 +#define B10101000 168 +#define B10101001 169 +#define B10101010 170 +#define B10101011 171 +#define B10101100 172 +#define B10101101 173 +#define B10101110 174 +#define B10101111 175 +#define B10110000 176 +#define B10110001 177 +#define B10110010 178 +#define B10110011 179 +#define B10110100 180 +#define B10110101 181 +#define B10110110 182 +#define B10110111 183 +#define B10111000 184 +#define B10111001 185 +#define B10111010 186 +#define B10111011 187 +#define B10111100 188 +#define B10111101 189 +#define B10111110 190 +#define B10111111 191 +#define B11000000 192 +#define B11000001 193 +#define B11000010 194 +#define B11000011 195 +#define B11000100 196 +#define B11000101 197 +#define B11000110 198 +#define B11000111 199 +#define B11001000 200 +#define B11001001 201 +#define B11001010 202 +#define B11001011 203 +#define B11001100 204 +#define B11001101 205 +#define B11001110 206 +#define B11001111 207 +#define B11010000 208 +#define B11010001 209 +#define B11010010 210 +#define B11010011 211 +#define B11010100 212 +#define B11010101 213 +#define B11010110 214 +#define B11010111 215 +#define B11011000 216 +#define B11011001 217 +#define B11011010 218 +#define B11011011 219 +#define B11011100 220 +#define B11011101 221 +#define B11011110 222 +#define B11011111 223 +#define B11100000 224 +#define B11100001 225 +#define B11100010 226 +#define B11100011 227 +#define B11100100 228 +#define B11100101 229 +#define B11100110 230 +#define B11100111 231 +#define B11101000 232 +#define B11101001 233 +#define B11101010 234 +#define B11101011 235 +#define B11101100 236 +#define B11101101 237 +#define B11101110 238 +#define B11101111 239 +#define B11110000 240 +#define B11110001 241 +#define B11110010 242 +#define B11110011 243 +#define B11110100 244 +#define B11110101 245 +#define B11110110 246 +#define B11110111 247 +#define B11111000 248 +#define B11111001 249 +#define B11111010 250 +#define B11111011 251 +#define B11111100 252 +#define B11111101 253 +#define B11111110 254 +#define B11111111 255 + +#endif /* _BIT_CONSTANTS_H_ */ diff --git a/wirish/include/wirish/bits.h b/wirish/include/wirish/bits.h new file mode 100644 index 0000000..0a63c58 --- /dev/null +++ b/wirish/include/wirish/bits.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* Note: Use of this header file is deprecated. Use bit_constants.h + instead. */ + +#ifndef _WIRISH_BITS_H_ +#define _WIRISH_BITS_H_ + +#include + +#endif diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h new file mode 100644 index 0000000..e708f79 --- /dev/null +++ b/wirish/include/wirish/boards.h @@ -0,0 +1,122 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file boards.h + * @author Bryan Newbold , + * Marti Bolivar + * @brief Board-specific pin information. + * + * To add a new board type, add a new pair of files to + * /wirish/boards/, update the section below with a new "BOARD" type, + * and update /wirish/rules.mk to include your boards/your_board.cpp + * file in the top-level Makefile build. + */ + +#ifndef _WIRISH_BOARDS_H_ +#define _WIRISH_BOARDS_H_ + +#include +#include +#include + +/* Set of all possible pin names; not all boards have all these (note + * that we use the Dx convention since all of the Maple's pins are + * "digital" pins (e.g. can be used with digitalRead() and + * digitalWrite()), but not all of them are connected to ADCs. */ +enum { + D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, + D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, + D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46, + D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D58, D59, D60, D61, + D62, D63, D64, D65, D66, D67, D68, D69, D70, D71, D72, D73, D74, D75, D76, + D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D89, D90, D91, + D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105, + D106, D107, D108, D109, D110, D111, }; + +/** + * @brief Maps each Maple pin to a corresponding stm32_pin_info. + * @see stm32_pin_info + */ +extern const stm32_pin_info PIN_MAP[]; + +/** + * @brief Pins capable of PWM output. + * + * Its length is BOARD_NR_PWM_PINS. + */ +extern const uint8 boardPWMPins[]; + +/** + * @brief Array of pins capable of analog input. + * + * Its length is BOARD_NR_ADC_PINS. + */ +extern const uint8 boardADCPins[]; + +/** + * @brief Pins which are connected to external hardware. + * + * For example, on Maple boards, it always at least includes + * BOARD_LED_PIN. Its length is BOARD_NR_USED_PINS. + */ +extern const uint8 boardUsedPins[]; + +/** + * @brief Generic board initialization function. + * + * This function is called before main(). It ensures that the clocks + * and peripherals are configured properly for use with wirish, then + * calls boardInit(). + * + * @see boardInit() + */ +void init(void); + +/** + * @brief Board-specific initialization function. + * + * This function is called from init() after all generic board + * initialization has been performed. Each board is required to + * define its own. + * + * @see init() + */ +extern void boardInit(void); + +/** + * @brief Test if a pin is used for a special purpose on your board. + * @param pin Pin to test + * @return true if the given pin is in boardUsedPins, and false otherwise. + * @see boardUsedPins + */ +bool boardUsesPin(uint8 pin); + +/* Set derived definitions */ +#define CLOCK_SPEED_MHZ CYCLES_PER_MICROSECOND +#define CLOCK_SPEED_HZ (CLOCK_SPEED_MHZ * 1000000UL) + +#endif diff --git a/wirish/include/wirish/ext_interrupts.h b/wirish/include/wirish/ext_interrupts.h new file mode 100644 index 0000000..617e43d --- /dev/null +++ b/wirish/include/wirish/ext_interrupts.h @@ -0,0 +1,106 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file ext_interrupts.h + * + * @brief Wiring-like external interrupt prototypes and types. + */ + +#ifndef _WIRISH_EXT_INTERRUPTS_H_ +#define _WIRISH_EXT_INTERRUPTS_H_ + +#include +#include + +/** + * The kind of transition on an external pin which should trigger an + * interrupt. + */ +typedef enum ExtIntTriggerMode { + RISING, /**< To trigger an interrupt when the pin transitions LOW + to HIGH */ + FALLING, /**< To trigger an interrupt when the pin transitions + HIGH to LOW */ + CHANGE /**< To trigger an interrupt when the pin transitions from + LOW to HIGH or HIGH to LOW (i.e., when the pin + changes). */ +} ExtIntTriggerMode; + +/** + * @brief Registers an interrupt handler on a pin. + * + * The interrupt will be triggered on a given transition on the pin, + * as specified by the mode parameter. The handler runs in interrupt + * context. The new handler will replace whatever handler is + * currently registered for the pin, if any. + * + * @param pin Maple pin number + * @param handler Function to run upon external interrupt trigger. + * The handler should take no arguments, and have void return type. + * @param mode Type of transition to trigger on, e.g. falling, rising, etc. + * + * @sideeffect Registers a handler + * @see detachInterrupt() + */ +void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode); + +/** + * @brief Disable any registered external interrupt. + * @param pin Maple pin number + * @sideeffect unregisters external interrupt handler + * @see attachInterrupt() + */ +void detachInterrupt(uint8 pin); + +/** + * Re-enable interrupts. + * + * Call this after noInterrupts() to re-enable interrupt handling, + * after you have finished with a timing-critical section of code. + * + * @see noInterrupts() + */ +static inline void interrupts() { + nvic_globalirq_enable(); +} + +/** + * Disable interrupts. + * + * After calling this function, all user-programmable interrupts will + * be disabled. You can call this function before a timing-critical + * section of code, then call interrupts() to re-enable interrupt + * handling. + * + * @see interrupts() + */ +static inline void noInterrupts() { + nvic_globalirq_disable(); +} + +#endif + diff --git a/wirish/include/wirish/io.h b/wirish/include/wirish/io.h new file mode 100644 index 0000000..de56a49 --- /dev/null +++ b/wirish/include/wirish/io.h @@ -0,0 +1,222 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file io.h + * + * @brief Arduino-compatible digital pin I/O interface. + */ + +#ifndef _WIRISH_IO_H_ +#define _WIRISH_IO_H_ + +#include +#include + +/** + * Specifies a GPIO pin behavior. + * @see pinMode() + */ +typedef enum WiringPinMode { + OUTPUT, /**< Basic digital output: when the pin is HIGH, the + voltage is held at +3.3v (Vcc) and when it is LOW, it + is pulled down to ground. */ + + OUTPUT_OPEN_DRAIN, /**< In open drain mode, the pin indicates + "low" by accepting current flow to ground + and "high" by providing increased + impedance. An example use would be to + connect a pin to a bus line (which is pulled + up to a positive voltage by a separate + supply through a large resistor). When the + pin is high, not much current flows through + to ground and the line stays at positive + voltage; when the pin is low, the bus + "drains" to ground with a small amount of + current constantly flowing through the large + resistor from the external supply. In this + mode, no current is ever actually sourced + from the pin. */ + + INPUT, /**< Basic digital input. The pin voltage is sampled; when + it is closer to 3.3v (Vcc) the pin status is high, and + when it is closer to 0v (ground) it is low. If no + external circuit is pulling the pin voltage to high or + low, it will tend to randomly oscillate and be very + sensitive to noise (e.g., a breath of air across the pin + might cause the state to flip). */ + + INPUT_ANALOG, /**< This is a special mode for when the pin will be + used for analog (not digital) reads. Enables ADC + conversion to be performed on the voltage at the + pin. */ + + INPUT_PULLUP, /**< The state of the pin in this mode is reported + the same way as with INPUT, but the pin voltage + is gently "pulled up" towards +3.3v. This means + the state will be high unless an external device + is specifically pulling the pin down to ground, + in which case the "gentle" pull up will not + affect the state of the input. */ + + INPUT_PULLDOWN, /**< The state of the pin in this mode is reported + the same way as with INPUT, but the pin voltage + is gently "pulled down" towards 0v. This means + the state will be low unless an external device + is specifically pulling the pin up to 3.3v, in + which case the "gentle" pull down will not + affect the state of the input. */ + + INPUT_FLOATING, /**< Synonym for INPUT. */ + + PWM, /**< This is a special mode for when the pin will be used for + PWM output (a special case of digital output). */ + + PWM_OPEN_DRAIN, /**< Like PWM, except that instead of alternating + cycles of LOW and HIGH, the voltage on the pin + consists of alternating cycles of LOW and + floating (disconnected). */ +} WiringPinMode; + +/** + * Configure behavior of a GPIO pin. + * + * @param pin Number of pin to configure. + * @param mode Mode corresponding to desired pin behavior. + * @see WiringPinMode + */ +void pinMode(uint8 pin, WiringPinMode mode); + +#define HIGH 0x1 +#define LOW 0x0 + +/** + * Writes a (digital) value to a pin. The pin must have its + * mode set to OUTPUT or OUTPUT_OPEN_DRAIN. + * + * @param pin Pin to write to. + * @param value Either LOW (write a 0) or HIGH (write a 1). + * @see pinMode() + */ +void digitalWrite(uint8 pin, uint8 value); + +/** + * Read a digital value from a pin. The pin must have its mode set to + * one of INPUT, INPUT_PULLUP, and INPUT_PULLDOWN. + * + * @param pin Pin to read from. + * @return LOW or HIGH. + * @see pinMode() + */ +uint32 digitalRead(uint8 pin); + +/** + * Read an analog value from pin. This function blocks during ADC + * conversion, and has 12 bits of resolution. The pin must have its + * mode set to INPUT_ANALOG. + * + * @param pin Pin to read from. + * @return Converted voltage, in the range 0--4095, (i.e. a 12-bit ADC + * conversion). + * @see pinMode() + */ +uint16 analogRead(uint8 pin); + +/** + * Toggles the digital value at the given pin. + * + * The pin must have its mode set to OUTPUT. + * + * @param pin the pin to toggle. If the pin is HIGH, set it LOW. If + * it is LOW, set it HIGH. + * + * @see pinMode() + */ +void togglePin(uint8 pin); + +/** + * Toggle the LED. + * + * If the LED is on, turn it off. If it is off, turn it on. + * + * The LED must its mode set to OUTPUT. This can be accomplished + * portably over all LeafLabs boards by calling pinMode(BOARD_LED_PIN, + * OUTPUT) before calling this function. + * + * @see pinMode() + */ +static inline void toggleLED() { + togglePin(BOARD_LED_PIN); +} + +/** + * If the button is currently pressed, waits until the button is no + * longer being pressed, and returns true. Otherwise, returns false. + * + * The button pin must have its mode set to INPUT. This can be + * accomplished portably over all LeafLabs boards by calling + * pinMode(BOARD_BUTTON_PIN, INPUT). + * + * @see pinMode() + */ +uint8 isButtonPressed(); + +/** + * Wait until the button is pressed and released, timing out if no + * press occurs. + * + * The button pin must have its mode set to INPUT. This can be + * accomplished portably over all LeafLabs boards by calling + * pinMode(BOARD_BUTTON_PIN, INPUT). + * + * @param timeout_millis Number of milliseconds to wait until the + * button is pressed. If timeout_millis is left out (or 0), wait + * forever. + * + * @return true, if the button was pressed; false, if the timeout was + * reached. + * + * @see pinMode() + */ +uint8 waitForButtonPress(uint32 timeout_millis=0); + +/** + * Shift out a byte of data, one bit at a time. + * + * This function starts at either the most significant or least + * significant bit in a byte value, and shifts out each byte in order + * onto a data pin. After each bit is written to the data pin, a + * separate clock pin is pulsed to indicate that the new bit is + * available. + * + * @param dataPin Pin to shift data out on + * @param clockPin Pin to pulse after each bit is shifted out + * @param bitOrder Either MSBFIRST (big-endian) or LSBFIRST (little-endian). + * @param value Value to shift out + */ +void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value); + +#endif diff --git a/wirish/include/wirish/pwm.h b/wirish/include/wirish/pwm.h new file mode 100644 index 0000000..e7130fb --- /dev/null +++ b/wirish/include/wirish/pwm.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file pwm.h + * + * @brief Arduino-compatible PWM interface. + */ + +#ifndef _WIRISH_PWM_H_ +#define _WIRISH_PWM_H_ + +#include + +/** + * As a convenience, analogWrite is an alias of pwmWrite to ease + * porting Arduino code. However, period and duty will have to be + * recalibrated. + */ +#define analogWrite pwmWrite + +/** + * Set the PWM duty on the given pin. + * + * User code is expected to determine and honor the maximum value + * (based on the configured period). + * + * @param pin PWM output pin + * @param duty_cycle Duty cycle to set. + */ +void pwmWrite(uint8 pin, uint16 duty_cycle); + +#endif + diff --git a/wirish/include/wirish/usb_serial.h b/wirish/include/wirish/usb_serial.h new file mode 100644 index 0000000..81e9e97 --- /dev/null +++ b/wirish/include/wirish/usb_serial.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @brief Wirish virtual serial port + */ + +#ifndef _WIRISH_USB_SERIAL_H_ +#define _WIRISH_USB_SERIAL_H_ + +#include + +/** + * @brief Virtual serial terminal. + */ +class USBSerial : public Print { +public: + USBSerial(void); + + void begin(void); + void end(void); + + uint32 available(void); + + uint32 read(void *buf, uint32 len); + uint8 read(void); + + void write(uint8); + void write(const char *str); + void write(const void*, uint32); + + uint8 getRTS(); + uint8 getDTR(); + uint8 isConnected(); + uint8 pending(); +}; + +extern USBSerial SerialUSB; + +#endif + diff --git a/wirish/include/wirish/wirish.h b/wirish/include/wirish/wirish.h new file mode 100644 index 0000000..4097ce1 --- /dev/null +++ b/wirish/include/wirish/wirish.h @@ -0,0 +1,71 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @brief Main include file for the Wirish core. + * + * Includes most of Wirish, and (transitively or otherwise) + * substantial pieces of libmaple proper. + */ + +#ifndef _WIRISH_WIRISH_H_ +#define _WIRISH_WIRISH_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Wiring macros and bit defines */ + +#define true 0x1 +#define false 0x0 + +#define LSBFIRST 0 +#define MSBFIRST 1 + +#define lowByte(w) ((w) & 0xFF) +#define highByte(w) (((w) >> 8) & 0xFF) +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : \ + bitClear(value, bit)) +#define bit(b) (1UL << (b)) + +#endif + diff --git a/wirish/include/wirish/wirish_debug.h b/wirish/include/wirish/wirish_debug.h new file mode 100644 index 0000000..c8bc077 --- /dev/null +++ b/wirish/include/wirish/wirish_debug.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish_debug.h + * @brief High level debug port configuration + */ + +#ifndef _WIRISH_WIRISH_DEBUG_H_ +#define _WIRISH_WIRISH_DEBUG_H_ + +#include + +/** + * @brief Disable the JTAG and Serial Wire (SW) debug ports. + * + * You can call this function in order to use the JTAG and SW debug + * pins as ordinary GPIOs. + * + * @see enableDebugPorts() + */ +static inline void disableDebugPorts(void) { + afio_cfg_debug_ports(AFIO_DEBUG_NONE); +} + +/** + * @brief Enable the JTAG and Serial Wire (SW) debug ports. + * + * After you call this function, the JTAG and SW debug pins will no + * longer be usable as GPIOs. + * + * @see disableDebugPorts() + */ +static inline void enableDebugPorts(void) { + afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ); +} + +#endif diff --git a/wirish/include/wirish/wirish_math.h b/wirish/include/wirish/wirish_math.h new file mode 100644 index 0000000..3820cab --- /dev/null +++ b/wirish/include/wirish/wirish_math.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish_math.h + * @brief Includes ; provides Arduino-compatible math routines. + */ + +#ifndef _WIRISH_WIRISH_MATH_H_ +#define _WIRISH_WIRISH_MATH_H_ + +#include + +/** + * @brief Initialize the pseudo-random number generator. + * @param seed the number used to initialize the seed; cannot be zero. + */ +void randomSeed(unsigned int seed); + +/** + * @brief Generate a pseudo-random number with upper bound. + * @param max An upper bound on the returned value, exclusive. + * @return A pseudo-random number in the range [0,max). + * @see randomSeed() + */ +long random(long max); + +/** + * @brief Generate a pseudo-random number with lower and upper bounds. + * @param min Lower bound on the returned value, inclusive. + * @param max Upper bound on the returned value, exclusive. + * @return A pseudo-random number in the range [min, max). + * @see randomSeed() + */ +long random(long min, long max); + +/** + * @brief Remap a number from one range to another. + * + * That is, a value equal to fromStart gets mapped to toStart, a value + * of fromEnd to toEnd, and other values are mapped proportionately. + * + * Does not constrain value to lie within [fromStart, fromEnd]. + * + * If a "start" value is larger than its corresponding "end", the + * ranges are reversed, so map(n, 1, 10, 10, 1) would reverse the + * range [1,10]. + * + * Negative numbers may appear as any argument. + * + * @param value the value to map. + * @param fromStart the beginning of the value's current range. + * @param fromEnd the end of the value's current range. + * @param toStart the beginning of the value's mapped range. + * @param toEnd the end of the value's mapped range. + * @return the mapped value. + */ +static inline long map(long value, long fromStart, long fromEnd, + long toStart, long toEnd) { + return (value - fromStart) * (toEnd - toStart) / (fromEnd - fromStart) + + toStart; +} + +#define PI 3.1415926535897932384626433832795 +#define HALF_PI 1.5707963267948966192313216916398 +#define TWO_PI 6.283185307179586476925286766559 +#define DEG_TO_RAD 0.017453292519943295769236907684886 +#define RAD_TO_DEG 57.295779513082320876798154814105 + +#define min(a,b) ((a)<(b)?(a):(b)) +#define max(a,b) ((a)>(b)?(a):(b)) +#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt))) +#define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5)) +#define radians(deg) ((deg)*DEG_TO_RAD) +#define degrees(rad) ((rad)*RAD_TO_DEG) +#define sq(x) ((x)*(x)) + +/* undefine stdlib's abs if encountered */ +#ifdef abs +#undef abs +#endif +#define abs(x) (((x) > 0) ? (x) : -(x)) + +/* Following are duplicate declarations (with Doxygen comments) for + * some of the math.h functions; this is for the convenience of the + * Sphinx docs. + */ + +/** + * Compute the cosine of an angle, in radians. + * @param x The radian measure of the angle. + * @return The cosine of x. This value will be between -1 and 1. + */ +double cos(double x); + +/** + * Compute the sine of an angle, in radians. + * @param x The radian measure of the angle. + * @return The sine of x. This value will be between -1 and 1. + */ +double sin(double x); + +/** + * Compute the tangent of an angle, in radians. + * @param x The radian measure of the angle. + * @return The tangent of x. There are no limits on the return value + * of this function. + */ +double tan(double x); + +/** + * Compute the square root of a number. + * @param x The number whose square root to find. This value cannot + * be negative. + * @return The square root of x. The return value is never negative. + */ +double sqrt(double x); + +/** + * Compute an exponentiation. + * @param x the base. This value cannot be zero if y <= 0. This value + * cannot be negative if y is not an integral value. + * @param y the exponent. + * @return x raised to the power y. + */ +double pow(double x, double y); + +#endif diff --git a/wirish/include/wirish/wirish_time.h b/wirish/include/wirish/wirish_time.h new file mode 100644 index 0000000..a81075c --- /dev/null +++ b/wirish/include/wirish/wirish_time.h @@ -0,0 +1,98 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish_time.h + * @brief Timing and delay functions. + */ + +#ifndef _WIRISH_WIRISH_TIME_H_ +#define _WIRISH_WIRISH_TIME_H_ + +#include +#include + +#include + +#define US_PER_MS 1000 + +/** + * Returns time (in milliseconds) since the beginning of program + * execution. On overflow, restarts at 0. + * @see micros() + */ +static inline uint32 millis(void) { + return systick_uptime(); +} + +/** + * Returns time (in microseconds) since the beginning of program + * execution. On overflow, restarts at 0. + * @see millis() + */ +static inline uint32 micros(void) { + uint32 ms; + uint32 cycle_cnt; + uint32 res; + + do { + ms = millis(); + cycle_cnt = systick_get_count(); + } while (ms != millis()); + + /* SYSTICK_RELOAD_VAL is 1 less than the number of cycles it + * actually takes to complete a SysTick reload */ + res = (ms * US_PER_MS) + + (SYSTICK_RELOAD_VAL + 1 - cycle_cnt) / CYCLES_PER_MICROSECOND; + + return res; +} + +/** + * Delay for at least the given number of milliseconds. + * + * Interrupts, etc. may cause the actual number of milliseconds to + * exceed ms. However, this function will return no less than ms + * milliseconds from the time it is called. + * + * @param ms the number of milliseconds to delay. + * @see delayMicroseconds() + */ +void delay(unsigned long ms); + +/** + * Delay for at least the given number of microseconds. + * + * Interrupts, etc. may cause the actual number of microseconds to + * exceed us. However, this function will return no less than us + * microseconds from the time it is called. + * + * @param us the number of microseconds to delay. + * @see delay() + */ +void delayMicroseconds(uint32 us); + +#endif diff --git a/wirish/include/wirish/wirish_types.h b/wirish/include/wirish/wirish_types.h new file mode 100644 index 0000000..d70b26f --- /dev/null +++ b/wirish/include/wirish/wirish_types.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish_types.h + * @author Marti Bolivar + * @brief Wirish library type definitions. + */ + +#ifndef _WIRISH_WIRISH_TYPES_H_ +#define _WIRISH_WIRISH_TYPES_H_ + +#include +#include +#include +#include + +/** + * Invalid stm32_pin_info adc_channel value. + * @see stm32_pin_info + */ +#define ADCx 0xFF + +/** + * @brief Stores STM32-specific information related to a given Maple pin. + * @see PIN_MAP + */ +typedef struct stm32_pin_info { + gpio_dev *gpio_device; /**< Maple pin's GPIO device */ + timer_dev *timer_device; /**< Pin's timer device, if any. */ + const adc_dev *adc_device; /**< ADC device, if any. */ + uint8 gpio_bit; /**< Pin's GPIO port bit. */ + uint8 timer_channel; /**< Timer channel, or 0 if none. */ + uint8 adc_channel; /**< Pin ADC channel, or ADCx if none. */ +} stm32_pin_info; + +/** + * Variable attribute, instructs the linker to place the marked + * variable in Flash instead of RAM. */ +#define __FLASH__ __attr_flash + +typedef uint8 boolean; +typedef uint8 byte; + +#endif diff --git a/wirish/io.h b/wirish/io.h deleted file mode 100644 index 0cb9c04..0000000 --- a/wirish/io.h +++ /dev/null @@ -1,223 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file io.h - * - * @brief Arduino-compatible digital pin I/O interface. - */ - -#ifndef _IO_H_ -#define _IO_H_ - -#include "libmaple_types.h" - -#include "boards.h" - -/** - * Specifies a GPIO pin behavior. - * @see pinMode() - */ -typedef enum WiringPinMode { - OUTPUT, /**< Basic digital output: when the pin is HIGH, the - voltage is held at +3.3v (Vcc) and when it is LOW, it - is pulled down to ground. */ - - OUTPUT_OPEN_DRAIN, /**< In open drain mode, the pin indicates - "low" by accepting current flow to ground - and "high" by providing increased - impedance. An example use would be to - connect a pin to a bus line (which is pulled - up to a positive voltage by a separate - supply through a large resistor). When the - pin is high, not much current flows through - to ground and the line stays at positive - voltage; when the pin is low, the bus - "drains" to ground with a small amount of - current constantly flowing through the large - resistor from the external supply. In this - mode, no current is ever actually sourced - from the pin. */ - - INPUT, /**< Basic digital input. The pin voltage is sampled; when - it is closer to 3.3v (Vcc) the pin status is high, and - when it is closer to 0v (ground) it is low. If no - external circuit is pulling the pin voltage to high or - low, it will tend to randomly oscillate and be very - sensitive to noise (e.g., a breath of air across the pin - might cause the state to flip). */ - - INPUT_ANALOG, /**< This is a special mode for when the pin will be - used for analog (not digital) reads. Enables ADC - conversion to be performed on the voltage at the - pin. */ - - INPUT_PULLUP, /**< The state of the pin in this mode is reported - the same way as with INPUT, but the pin voltage - is gently "pulled up" towards +3.3v. This means - the state will be high unless an external device - is specifically pulling the pin down to ground, - in which case the "gentle" pull up will not - affect the state of the input. */ - - INPUT_PULLDOWN, /**< The state of the pin in this mode is reported - the same way as with INPUT, but the pin voltage - is gently "pulled down" towards 0v. This means - the state will be low unless an external device - is specifically pulling the pin up to 3.3v, in - which case the "gentle" pull down will not - affect the state of the input. */ - - INPUT_FLOATING, /**< Synonym for INPUT. */ - - PWM, /**< This is a special mode for when the pin will be used for - PWM output (a special case of digital output). */ - - PWM_OPEN_DRAIN, /**< Like PWM, except that instead of alternating - cycles of LOW and HIGH, the voltage on the pin - consists of alternating cycles of LOW and - floating (disconnected). */ -} WiringPinMode; - -/** - * Configure behavior of a GPIO pin. - * - * @param pin Number of pin to configure. - * @param mode Mode corresponding to desired pin behavior. - * @see WiringPinMode - */ -void pinMode(uint8 pin, WiringPinMode mode); - -#define HIGH 0x1 -#define LOW 0x0 - -/** - * Writes a (digital) value to a pin. The pin must have its - * mode set to OUTPUT or OUTPUT_OPEN_DRAIN. - * - * @param pin Pin to write to. - * @param value Either LOW (write a 0) or HIGH (write a 1). - * @see pinMode() - */ -void digitalWrite(uint8 pin, uint8 value); - -/** - * Read a digital value from a pin. The pin must have its mode set to - * one of INPUT, INPUT_PULLUP, and INPUT_PULLDOWN. - * - * @param pin Pin to read from. - * @return LOW or HIGH. - * @see pinMode() - */ -uint32 digitalRead(uint8 pin); - -/** - * Read an analog value from pin. This function blocks during ADC - * conversion, and has 12 bits of resolution. The pin must have its - * mode set to INPUT_ANALOG. - * - * @param pin Pin to read from. - * @return Converted voltage, in the range 0--4095, (i.e. a 12-bit ADC - * conversion). - * @see pinMode() - */ -uint16 analogRead(uint8 pin); - -/** - * Toggles the digital value at the given pin. - * - * The pin must have its mode set to OUTPUT. - * - * @param pin the pin to toggle. If the pin is HIGH, set it LOW. If - * it is LOW, set it HIGH. - * - * @see pinMode() - */ -void togglePin(uint8 pin); - -/** - * Toggle the LED. - * - * If the LED is on, turn it off. If it is off, turn it on. - * - * The LED must its mode set to OUTPUT. This can be accomplished - * portably over all LeafLabs boards by calling pinMode(BOARD_LED_PIN, - * OUTPUT) before calling this function. - * - * @see pinMode() - */ -static inline void toggleLED() { - togglePin(BOARD_LED_PIN); -} - -/** - * If the button is currently pressed, waits until the button is no - * longer being pressed, and returns true. Otherwise, returns false. - * - * The button pin must have its mode set to INPUT. This can be - * accomplished portably over all LeafLabs boards by calling - * pinMode(BOARD_BUTTON_PIN, INPUT). - * - * @see pinMode() - */ -uint8 isButtonPressed(); - -/** - * Wait until the button is pressed and released, timing out if no - * press occurs. - * - * The button pin must have its mode set to INPUT. This can be - * accomplished portably over all LeafLabs boards by calling - * pinMode(BOARD_BUTTON_PIN, INPUT). - * - * @param timeout_millis Number of milliseconds to wait until the - * button is pressed. If timeout_millis is left out (or 0), wait - * forever. - * - * @return true, if the button was pressed; false, if the timeout was - * reached. - * - * @see pinMode() - */ -uint8 waitForButtonPress(uint32 timeout_millis=0); - -/** - * Shift out a byte of data, one bit at a time. - * - * This function starts at either the most significant or least - * significant bit in a byte value, and shifts out each byte in order - * onto a data pin. After each bit is written to the data pin, a - * separate clock pin is pulsed to indicate that the new bit is - * available. - * - * @param dataPin Pin to shift data out on - * @param clockPin Pin to pulse after each bit is shifted out - * @param bitOrder Either MSBFIRST (big-endian) or LSBFIRST (little-endian). - * @param value Value to shift out - */ -void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value); - -#endif diff --git a/wirish/pwm.cpp b/wirish/pwm.cpp index 7e8a535..a55f245 100644 --- a/wirish/pwm.cpp +++ b/wirish/pwm.cpp @@ -28,12 +28,12 @@ * @brief Arduino-style PWM implementation. */ -#include "pwm.h" +#include -#include "libmaple_types.h" -#include "timer.h" +#include +#include -#include "boards.h" +#include void pwmWrite(uint8 pin, uint16 duty_cycle) { timer_dev *dev = PIN_MAP[pin].timer_device; diff --git a/wirish/pwm.h b/wirish/pwm.h deleted file mode 100644 index a7705ab..0000000 --- a/wirish/pwm.h +++ /dev/null @@ -1,57 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file pwm.h - * - * @brief Arduino-compatible PWM interface. - */ - -#ifndef _PWM_H_ -#define _PWM_H_ - -#include "libmaple_types.h" - -/** - * As a convenience, analogWrite is an alias of pwmWrite to ease - * porting Arduino code. However, period and duty will have to be - * recalibrated. - */ -#define analogWrite pwmWrite - -/** - * Set the PWM duty on the given pin. - * - * User code is expected to determine and honor the maximum value - * (based on the configured period). - * - * @param pin PWM output pin - * @param duty_cycle Duty cycle to set. - */ -void pwmWrite(uint8 pin, uint16 duty_cycle); - -#endif - diff --git a/wirish/rules.mk b/wirish/rules.mk index 1bf6245..923c17b 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -4,9 +4,12 @@ dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) BUILDDIRS += $(BUILD_PATH)/$(d)/comm -BUILDDIRS += $(BUILD_PATH)/$(d)/boards -WIRISH_INCLUDES := -I$(d) -I$(d)/comm -I$(d)/boards +# Board config -- TODO allow user override +WIRISH_BOARD_PATH := boards/$(BOARD) +BUILDDIRS += $(BUILD_PATH)/$(d)/$(WIRISH_BOARD_PATH) + +WIRISH_INCLUDES := -I$(d)/include -I$(d)/$(WIRISH_BOARD_PATH)/include # Local flags CFLAGS_$(d) := $(WIRISH_INCLUDES) $(LIBMAPLE_INCLUDES) @@ -18,11 +21,6 @@ cSRCS_$(d) := start_c.c cppSRCS_$(d) := wirish_math.cpp \ Print.cpp \ boards.cpp \ - boards/maple.cpp \ - boards/maple_mini.cpp \ - boards/maple_native.cpp \ - boards/maple_RET6.cpp \ - boards/olimex_stm32_h103.cpp \ comm/HardwareSerial.cpp \ comm/HardwareSPI.cpp \ HardwareTimer.cpp \ @@ -34,6 +32,7 @@ cppSRCS_$(d) := wirish_math.cpp \ pwm.cpp \ ext_interrupts.cpp \ wirish_digital.cpp +cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) diff --git a/wirish/usb_serial.cpp b/wirish/usb_serial.cpp index b66b992..1fd6e65 100644 --- a/wirish/usb_serial.cpp +++ b/wirish/usb_serial.cpp @@ -28,11 +28,14 @@ * @brief USB virtual serial terminal */ +#include + #include -#include "wirish.h" #include "usb_cdcacm.h" -#include "usb.h" +#include + +#include #define USB_TIMEOUT 50 diff --git a/wirish/usb_serial.h b/wirish/usb_serial.h deleted file mode 100644 index d43b288..0000000 --- a/wirish/usb_serial.h +++ /dev/null @@ -1,64 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @brief Wirish virtual serial port - */ - -#ifndef _USB_SERIAL_H_ -#define _USB_SERIAL_H_ - -#include "Print.h" - -/** - * @brief Virtual serial terminal. - */ -class USBSerial : public Print { -public: - USBSerial(void); - - void begin(void); - void end(void); - - uint32 available(void); - - uint32 read(void *buf, uint32 len); - uint8 read(void); - - void write(uint8); - void write(const char *str); - void write(const void*, uint32); - - uint8 getRTS(); - uint8 getDTR(); - uint8 isConnected(); - uint8 pending(); -}; - -extern USBSerial SerialUSB; - -#endif - diff --git a/wirish/wirish.h b/wirish/wirish.h deleted file mode 100644 index d024f3b..0000000 --- a/wirish/wirish.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @brief Main include file for the Wirish core. - * - * Includes most of Wirish, and (transitively or otherwise) - * substantial pieces of libmaple proper. - */ - -#ifndef _WIRISH_H_ -#define _WIRISH_H_ - -#include "boards.h" -#include "io.h" -#include "bit_constants.h" -#include "pwm.h" -#include "ext_interrupts.h" -#include "wirish_debug.h" -#include "wirish_math.h" -#include "wirish_time.h" -#include "HardwareSPI.h" -#include "HardwareSerial.h" -#include "HardwareTimer.h" -#include "usb_serial.h" - -#include "libmaple.h" -#include "wirish_types.h" - -/* Arduino wiring macros and bit defines */ - -#define true 0x1 -#define false 0x0 - -#define LSBFIRST 0 -#define MSBFIRST 1 - -#define lowByte(w) ((w) & 0xFF) -#define highByte(w) (((w) >> 8) & 0xFF) -#define bitRead(value, bit) (((value) >> (bit)) & 0x01) -#define bitSet(value, bit) ((value) |= (1UL << (bit))) -#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) -#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : \ - bitClear(value, bit)) -#define bit(b) (1UL << (b)) - -#endif - diff --git a/wirish/wirish_analog.cpp b/wirish/wirish_analog.cpp index e5b9ffc..7a12156 100644 --- a/wirish/wirish_analog.cpp +++ b/wirish/wirish_analog.cpp @@ -28,11 +28,11 @@ * @brief Arduino-compatible ADC implementation. */ -#include "io.h" +#include -#include "adc.h" +#include -#include "boards.h" +#include /* Assumes that the ADC has been initialized and that the pin is set * to INPUT_ANALOG */ diff --git a/wirish/wirish_debug.h b/wirish/wirish_debug.h deleted file mode 100644 index 3f92b02..0000000 --- a/wirish/wirish_debug.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file wirish_debug.h - * @brief High level debug port configuration - */ - -#ifndef _WIRISH_DEBUG_H_ -#define _WIRISH_DEBUG_H_ - -#include "gpio.h" - -/** - * @brief Disable the JTAG and Serial Wire (SW) debug ports. - * - * You can call this function in order to use the JTAG and SW debug - * pins as ordinary GPIOs. - * - * @see enableDebugPorts() - */ -static inline void disableDebugPorts(void) { - afio_cfg_debug_ports(AFIO_DEBUG_NONE); -} - -/** - * @brief Enable the JTAG and Serial Wire (SW) debug ports. - * - * After you call this function, the JTAG and SW debug pins will no - * longer be usable as GPIOs. - * - * @see disableDebugPorts() - */ -static inline void enableDebugPorts(void) { - afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ); -} - -#endif diff --git a/wirish/wirish_digital.cpp b/wirish/wirish_digital.cpp index 6a0577c..6be1a29 100644 --- a/wirish/wirish_digital.cpp +++ b/wirish/wirish_digital.cpp @@ -28,13 +28,13 @@ * Arduino-compatible digital I/O implementation. */ -#include "io.h" +#include -#include "gpio.h" -#include "timer.h" +#include +#include -#include "wirish_time.h" -#include "boards.h" +#include +#include void pinMode(uint8 pin, WiringPinMode mode) { gpio_pin_mode outputMode; diff --git a/wirish/wirish_math.cpp b/wirish/wirish_math.cpp index 5aa6510..1443b3c 100644 --- a/wirish/wirish_math.cpp +++ b/wirish/wirish_math.cpp @@ -22,7 +22,7 @@ */ #include -#include "math.h" +#include void randomSeed(unsigned int seed) { if (seed != 0) { diff --git a/wirish/wirish_math.h b/wirish/wirish_math.h deleted file mode 100644 index a85b30a..0000000 --- a/wirish/wirish_math.h +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file wirish_math.h - * @brief Includes ; provides Arduino-compatible math routines. - */ - -#ifndef _WIRING_MATH_H_ -#define _WIRING_MATH_H_ - -#include - -/** - * @brief Initialize the pseudo-random number generator. - * @param seed the number used to initialize the seed; cannot be zero. - */ -void randomSeed(unsigned int seed); - -/** - * @brief Generate a pseudo-random number with upper bound. - * @param max An upper bound on the returned value, exclusive. - * @return A pseudo-random number in the range [0,max). - * @see randomSeed() - */ -long random(long max); - -/** - * @brief Generate a pseudo-random number with lower and upper bounds. - * @param min Lower bound on the returned value, inclusive. - * @param max Upper bound on the returned value, exclusive. - * @return A pseudo-random number in the range [min, max). - * @see randomSeed() - */ -long random(long min, long max); - -/** - * @brief Remap a number from one range to another. - * - * That is, a value equal to fromStart gets mapped to toStart, a value - * of fromEnd to toEnd, and other values are mapped proportionately. - * - * Does not constrain value to lie within [fromStart, fromEnd]. - * - * If a "start" value is larger than its corresponding "end", the - * ranges are reversed, so map(n, 1, 10, 10, 1) would reverse the - * range [1,10]. - * - * Negative numbers may appear as any argument. - * - * @param value the value to map. - * @param fromStart the beginning of the value's current range. - * @param fromEnd the end of the value's current range. - * @param toStart the beginning of the value's mapped range. - * @param toEnd the end of the value's mapped range. - * @return the mapped value. - */ -static inline long map(long value, long fromStart, long fromEnd, - long toStart, long toEnd) { - return (value - fromStart) * (toEnd - toStart) / (fromEnd - fromStart) + - toStart; -} - -#define PI 3.1415926535897932384626433832795 -#define HALF_PI 1.5707963267948966192313216916398 -#define TWO_PI 6.283185307179586476925286766559 -#define DEG_TO_RAD 0.017453292519943295769236907684886 -#define RAD_TO_DEG 57.295779513082320876798154814105 - -#define min(a,b) ((a)<(b)?(a):(b)) -#define max(a,b) ((a)>(b)?(a):(b)) -#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt))) -#define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5)) -#define radians(deg) ((deg)*DEG_TO_RAD) -#define degrees(rad) ((rad)*RAD_TO_DEG) -#define sq(x) ((x)*(x)) - -/* undefine stdlib's abs if encountered */ -#ifdef abs -#undef abs -#endif -#define abs(x) (((x) > 0) ? (x) : -(x)) - -/* Following are duplicate declarations (with Doxygen comments) for - * some of the math.h functions; this is for the convenience of the - * Sphinx docs. - */ - -/** - * Compute the cosine of an angle, in radians. - * @param x The radian measure of the angle. - * @return The cosine of x. This value will be between -1 and 1. - */ -double cos(double x); - -/** - * Compute the sine of an angle, in radians. - * @param x The radian measure of the angle. - * @return The sine of x. This value will be between -1 and 1. - */ -double sin(double x); - -/** - * Compute the tangent of an angle, in radians. - * @param x The radian measure of the angle. - * @return The tangent of x. There are no limits on the return value - * of this function. - */ -double tan(double x); - -/** - * Compute the square root of a number. - * @param x The number whose square root to find. This value cannot - * be negative. - * @return The square root of x. The return value is never negative. - */ -double sqrt(double x); - -/** - * Compute an exponentiation. - * @param x the base. This value cannot be zero if y <= 0. This value - * cannot be negative if y is not an integral value. - * @param y the exponent. - * @return x raised to the power y. - */ -double pow(double x, double y); - -#endif diff --git a/wirish/wirish_shift.cpp b/wirish/wirish_shift.cpp index f67364d..0f24f59 100644 --- a/wirish/wirish_shift.cpp +++ b/wirish/wirish_shift.cpp @@ -22,7 +22,7 @@ * $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ */ -#include "wirish.h" +#include void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 val) { int i; diff --git a/wirish/wirish_time.cpp b/wirish/wirish_time.cpp index c9f10a8..9ce934b 100644 --- a/wirish/wirish_time.cpp +++ b/wirish/wirish_time.cpp @@ -28,10 +28,10 @@ * @brief Delay implementation. */ -#include "wirish_time.h" +#include -#include "libmaple_types.h" -#include "delay.h" +#include +#include void delay(unsigned long ms) { uint32 i; diff --git a/wirish/wirish_time.h b/wirish/wirish_time.h deleted file mode 100644 index 719a775..0000000 --- a/wirish/wirish_time.h +++ /dev/null @@ -1,98 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file wirish_time.h - * @brief Timing and delay functions. - */ - -#ifndef _TIME_H_ -#define _TIME_H_ - -#include "libmaple_types.h" -#include "systick.h" - -#include "boards.h" - -#define US_PER_MS 1000 - -/** - * Returns time (in milliseconds) since the beginning of program - * execution. On overflow, restarts at 0. - * @see micros() - */ -static inline uint32 millis(void) { - return systick_uptime(); -} - -/** - * Returns time (in microseconds) since the beginning of program - * execution. On overflow, restarts at 0. - * @see millis() - */ -static inline uint32 micros(void) { - uint32 ms; - uint32 cycle_cnt; - uint32 res; - - do { - ms = millis(); - cycle_cnt = systick_get_count(); - } while (ms != millis()); - - /* SYSTICK_RELOAD_VAL is 1 less than the number of cycles it - * actually takes to complete a SysTick reload */ - res = (ms * US_PER_MS) + - (SYSTICK_RELOAD_VAL + 1 - cycle_cnt) / CYCLES_PER_MICROSECOND; - - return res; -} - -/** - * Delay for at least the given number of milliseconds. - * - * Interrupts, etc. may cause the actual number of milliseconds to - * exceed ms. However, this function will return no less than ms - * milliseconds from the time it is called. - * - * @param ms the number of milliseconds to delay. - * @see delayMicroseconds() - */ -void delay(unsigned long ms); - -/** - * Delay for at least the given number of microseconds. - * - * Interrupts, etc. may cause the actual number of microseconds to - * exceed us. However, this function will return no less than us - * microseconds from the time it is called. - * - * @param us the number of microseconds to delay. - * @see delay() - */ -void delayMicroseconds(uint32 us); - -#endif diff --git a/wirish/wirish_types.h b/wirish/wirish_types.h deleted file mode 100644 index 43a6525..0000000 --- a/wirish/wirish_types.h +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file wirish_types.h - * @author Marti Bolivar - * @brief Wirish library type definitions. - */ - -#include "libmaple_types.h" -#include "gpio.h" -#include "timer.h" -#include "adc.h" - -#ifndef _WIRISH_TYPES_H_ -#define _WIRISH_TYPES_H_ - -/** - * Invalid stm32_pin_info adc_channel value. - * @see stm32_pin_info - */ -#define ADCx 0xFF - -/** - * @brief Stores STM32-specific information related to a given Maple pin. - * @see PIN_MAP - */ -typedef struct stm32_pin_info { - gpio_dev *gpio_device; /**< Maple pin's GPIO device */ - timer_dev *timer_device; /**< Pin's timer device, if any. */ - const adc_dev *adc_device; /**< ADC device, if any. */ - uint8 gpio_bit; /**< Pin's GPIO port bit. */ - uint8 timer_channel; /**< Timer channel, or 0 if none. */ - uint8 adc_channel; /**< Pin ADC channel, or ADCx if none. */ -} stm32_pin_info; - -/** - * Variable attribute, instructs the linker to place the marked - * variable in Flash instead of RAM. */ -#define __FLASH__ __attr_flash - -typedef uint8 boolean; -typedef uint8 byte; - -#endif -- cgit v1.2.3 From cb2f3071fcd49590499888c27c8f325699eafda9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 15 Nov 2011 16:05:12 -0500 Subject: Move wirish/comm/*.cpp into wirish. The wirish/comm/ directory is stupid. Signed-off-by: Marti Bolivar --- wirish/HardwareSPI.cpp | 319 +++++++++++++++++++++++++++++++++++++++++ wirish/HardwareSerial.cpp | 120 ++++++++++++++++ wirish/comm/HardwareSPI.cpp | 319 ----------------------------------------- wirish/comm/HardwareSerial.cpp | 120 ---------------- wirish/rules.mk | 5 +- 5 files changed, 441 insertions(+), 442 deletions(-) create mode 100644 wirish/HardwareSPI.cpp create mode 100644 wirish/HardwareSerial.cpp delete mode 100644 wirish/comm/HardwareSPI.cpp delete mode 100644 wirish/comm/HardwareSerial.cpp diff --git a/wirish/HardwareSPI.cpp b/wirish/HardwareSPI.cpp new file mode 100644 index 0000000..e1f186e --- /dev/null +++ b/wirish/HardwareSPI.cpp @@ -0,0 +1,319 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @author Marti Bolivar + * @brief Wirish SPI implementation. + */ + +#include + +#include +#include +#include + +#include +#include + +struct spi_pins { + uint8 nss; + uint8 sck; + uint8 miso; + uint8 mosi; +}; + +static const spi_pins* dev_to_spi_pins(spi_dev *dev); + +static void enable_device(spi_dev *dev, + bool as_master, + SPIFrequency frequency, + spi_cfg_flag endianness, + spi_mode mode); + +static const spi_pins board_spi_pins[] __FLASH__ = { + {BOARD_SPI1_NSS_PIN, + BOARD_SPI1_SCK_PIN, + BOARD_SPI1_MISO_PIN, + BOARD_SPI1_MOSI_PIN}, + {BOARD_SPI2_NSS_PIN, + BOARD_SPI2_SCK_PIN, + BOARD_SPI2_MISO_PIN, + BOARD_SPI2_MOSI_PIN}, +#ifdef STM32_HIGH_DENSITY + {BOARD_SPI3_NSS_PIN, + BOARD_SPI3_SCK_PIN, + BOARD_SPI3_MISO_PIN, + BOARD_SPI3_MOSI_PIN}, +#endif +}; + + +/* + * Constructor + */ + +HardwareSPI::HardwareSPI(uint32 spi_num) { + switch (spi_num) { + case 1: + this->spi_d = SPI1; + break; + case 2: + this->spi_d = SPI2; + break; +#ifdef STM32_HIGH_DENSITY + case 3: + this->spi_d = SPI3; + break; +#endif + default: + ASSERT(0); + } +} + +/* + * Set up/tear down + */ + +void HardwareSPI::begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode) { + if (mode >= 4) { + ASSERT(0); + return; + } + spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB; + spi_mode m = (spi_mode)mode; + enable_device(this->spi_d, true, frequency, end, m); +} + +void HardwareSPI::begin(void) { + this->begin(SPI_1_125MHZ, MSBFIRST, 0); +} + +void HardwareSPI::beginSlave(uint32 bitOrder, uint32 mode) { + if (mode >= 4) { + ASSERT(0); + return; + } + spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB; + spi_mode m = (spi_mode)mode; + enable_device(this->spi_d, false, (SPIFrequency)0, end, m); +} + +void HardwareSPI::beginSlave(void) { + this->beginSlave(MSBFIRST, 0); +} + +void HardwareSPI::end(void) { + if (!spi_is_enabled(this->spi_d)) { + return; + } + + // Follows RM0008's sequence for disabling a SPI in master/slave + // full duplex mode. + while (spi_is_rx_nonempty(this->spi_d)) { + // FIXME [0.1.0] remove this once you have an interrupt based driver + volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d); + } + while (!spi_is_tx_empty(this->spi_d)) + ; + while (spi_is_busy(this->spi_d)) + ; + spi_peripheral_disable(this->spi_d); +} + +/* + * I/O + */ + +uint8 HardwareSPI::read(void) { + uint8 buf[1]; + this->read(buf, 1); + return buf[0]; +} + +void HardwareSPI::read(uint8 *buf, uint32 len) { + uint32 rxed = 0; + while (rxed < len) { + while (!spi_is_rx_nonempty(this->spi_d)) + ; + buf[rxed++] = (uint8)spi_rx_reg(this->spi_d); + } +} + +void HardwareSPI::write(uint8 byte) { + this->write(&byte, 1); +} + +void HardwareSPI::write(const uint8 *data, uint32 length) { + uint32 txed = 0; + while (txed < length) { + txed += spi_tx(this->spi_d, data + txed, length - txed); + } +} + +uint8 HardwareSPI::transfer(uint8 byte) { + this->write(byte); + return this->read(); +} + +/* + * Pin accessors + */ + +uint8 HardwareSPI::misoPin(void) { + return dev_to_spi_pins(this->spi_d)->miso; +} + +uint8 HardwareSPI::mosiPin(void) { + return dev_to_spi_pins(this->spi_d)->mosi; +} + +uint8 HardwareSPI::sckPin(void) { + return dev_to_spi_pins(this->spi_d)->sck; +} + +uint8 HardwareSPI::nssPin(void) { + return dev_to_spi_pins(this->spi_d)->nss; +} + +/* + * Deprecated functions + */ + +uint8 HardwareSPI::send(uint8 data) { + uint8 buf[] = {data}; + return this->send(buf, 1); +} + +uint8 HardwareSPI::send(uint8 *buf, uint32 len) { + uint32 txed = 0; + uint8 ret = 0; + while (txed < len) { + this->write(buf[txed++]); + ret = this->read(); + } + return ret; +} + +uint8 HardwareSPI::recv(void) { + return this->read(); +} + +/* + * Auxiliary functions + */ + +static void configure_gpios(spi_dev *dev, bool as_master); +static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq); + +static const spi_pins* dev_to_spi_pins(spi_dev *dev) { + switch (dev->clk_id) { + case RCC_SPI1: return board_spi_pins; + case RCC_SPI2: return board_spi_pins + 1; +#ifdef STM32_HIGH_DENSITY + case RCC_SPI3: return board_spi_pins + 2; +#endif + default: return NULL; + } +} + +/* Enables the device in master or slave full duplex mode. If you + * change this code, you must ensure that appropriate changes are made + * to HardwareSPI::end(). */ +static void enable_device(spi_dev *dev, + bool as_master, + SPIFrequency freq, + spi_cfg_flag endianness, + spi_mode mode) { + spi_baud_rate baud = determine_baud_rate(dev, freq); + uint32 cfg_flags = (endianness | SPI_DFF_8_BIT | SPI_SW_SLAVE | + (as_master ? SPI_SOFT_SS : 0)); + + spi_init(dev); + configure_gpios(dev, as_master); + if (as_master) { + spi_master_enable(dev, baud, mode, cfg_flags); + } else { + spi_slave_enable(dev, mode, cfg_flags); + } +} + +static void disable_pwm(const stm32_pin_info *i) { + if (i->timer_device) { + timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED); + } +} + +static void configure_gpios(spi_dev *dev, bool as_master) { + const spi_pins *pins = dev_to_spi_pins(dev); + + if (!pins) { + return; + } + + const stm32_pin_info *nssi = &PIN_MAP[pins->nss]; + const stm32_pin_info *scki = &PIN_MAP[pins->sck]; + const stm32_pin_info *misoi = &PIN_MAP[pins->miso]; + const stm32_pin_info *mosii = &PIN_MAP[pins->mosi]; + + disable_pwm(nssi); + disable_pwm(scki); + disable_pwm(misoi); + disable_pwm(mosii); + + spi_gpio_cfg(as_master, + nssi->gpio_device, + nssi->gpio_bit, + scki->gpio_device, + scki->gpio_bit, + misoi->gpio_bit, + mosii->gpio_bit); +} + +static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = { + SPI_BAUD_PCLK_DIV_2, + SPI_BAUD_PCLK_DIV_4, + SPI_BAUD_PCLK_DIV_8, + SPI_BAUD_PCLK_DIV_16, + SPI_BAUD_PCLK_DIV_32, + SPI_BAUD_PCLK_DIV_64, + SPI_BAUD_PCLK_DIV_128, + SPI_BAUD_PCLK_DIV_256, +}; + +/* + * Note: This assumes you're on a LeafLabs-style board + * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz). + */ +static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq) { + if (rcc_dev_clk(dev->clk_id) == RCC_APB2 && freq == SPI_140_625KHZ) { + /* APB2 peripherals are too fast for 140.625 KHz */ + ASSERT(0); + return (spi_baud_rate)~0; + } + return (rcc_dev_clk(dev->clk_id) == RCC_APB2 ? + baud_rates[freq + 1] : + baud_rates[freq]); +} diff --git a/wirish/HardwareSerial.cpp b/wirish/HardwareSerial.cpp new file mode 100644 index 0000000..a9eb763 --- /dev/null +++ b/wirish/HardwareSerial.cpp @@ -0,0 +1,120 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file HardwareSerial.cpp + * @brief Wirish serial port implementation. + */ + +#include + +#include +#include +#include + +#include + +#define TX1 BOARD_USART1_TX_PIN +#define RX1 BOARD_USART1_RX_PIN +#define TX2 BOARD_USART2_TX_PIN +#define RX2 BOARD_USART2_RX_PIN +#define TX3 BOARD_USART3_TX_PIN +#define RX3 BOARD_USART3_RX_PIN +#if defined STM32_HIGH_DENSITY && !defined(BOARD_maple_RET6) +#define TX4 BOARD_UART4_TX_PIN +#define RX4 BOARD_UART4_RX_PIN +#define TX5 BOARD_UART5_TX_PIN +#define RX5 BOARD_UART5_RX_PIN +#endif + +HardwareSerial Serial1(USART1, TX1, RX1, STM32_PCLK2); +HardwareSerial Serial2(USART2, TX2, RX2, STM32_PCLK1); +HardwareSerial Serial3(USART3, TX3, RX3, STM32_PCLK1); +#if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6) +HardwareSerial Serial4(UART4, TX4, RX4, STM32_PCLK1); +HardwareSerial Serial5(UART5, TX5, RX5, STM32_PCLK1); +#endif + +HardwareSerial::HardwareSerial(usart_dev *usart_device, + uint8 tx_pin, + uint8 rx_pin, + uint32 clock_speed) { + this->usart_device = usart_device; + this->clock_speed = clock_speed; + this->tx_pin = tx_pin; + this->rx_pin = rx_pin; +} + +/* + * Set up/tear down + */ + +void HardwareSerial::begin(uint32 baud) { + ASSERT(baud <= usart_device->max_baud); + + if (baud > usart_device->max_baud) { + return; + } + + const stm32_pin_info *txi = &PIN_MAP[tx_pin]; + const stm32_pin_info *rxi = &PIN_MAP[rx_pin]; + + gpio_set_mode(txi->gpio_device, txi->gpio_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, GPIO_INPUT_FLOATING); + + if (txi->timer_device != NULL) { + /* Turn off any PWM if there's a conflict on this GPIO bit. */ + timer_set_mode(txi->timer_device, txi->timer_channel, TIMER_DISABLED); + } + + usart_init(usart_device); + usart_set_baud_rate(usart_device, clock_speed, baud); + usart_enable(usart_device); +} + +void HardwareSerial::end(void) { + usart_disable(usart_device); +} + +/* + * I/O + */ + +uint8 HardwareSerial::read(void) { + return usart_getc(usart_device); +} + +uint32 HardwareSerial::available(void) { + return usart_data_available(usart_device); +} + +void HardwareSerial::write(unsigned char ch) { + usart_putc(usart_device, ch); +} + +void HardwareSerial::flush(void) { + usart_reset_rx(usart_device); +} diff --git a/wirish/comm/HardwareSPI.cpp b/wirish/comm/HardwareSPI.cpp deleted file mode 100644 index e1f186e..0000000 --- a/wirish/comm/HardwareSPI.cpp +++ /dev/null @@ -1,319 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @author Marti Bolivar - * @brief Wirish SPI implementation. - */ - -#include - -#include -#include -#include - -#include -#include - -struct spi_pins { - uint8 nss; - uint8 sck; - uint8 miso; - uint8 mosi; -}; - -static const spi_pins* dev_to_spi_pins(spi_dev *dev); - -static void enable_device(spi_dev *dev, - bool as_master, - SPIFrequency frequency, - spi_cfg_flag endianness, - spi_mode mode); - -static const spi_pins board_spi_pins[] __FLASH__ = { - {BOARD_SPI1_NSS_PIN, - BOARD_SPI1_SCK_PIN, - BOARD_SPI1_MISO_PIN, - BOARD_SPI1_MOSI_PIN}, - {BOARD_SPI2_NSS_PIN, - BOARD_SPI2_SCK_PIN, - BOARD_SPI2_MISO_PIN, - BOARD_SPI2_MOSI_PIN}, -#ifdef STM32_HIGH_DENSITY - {BOARD_SPI3_NSS_PIN, - BOARD_SPI3_SCK_PIN, - BOARD_SPI3_MISO_PIN, - BOARD_SPI3_MOSI_PIN}, -#endif -}; - - -/* - * Constructor - */ - -HardwareSPI::HardwareSPI(uint32 spi_num) { - switch (spi_num) { - case 1: - this->spi_d = SPI1; - break; - case 2: - this->spi_d = SPI2; - break; -#ifdef STM32_HIGH_DENSITY - case 3: - this->spi_d = SPI3; - break; -#endif - default: - ASSERT(0); - } -} - -/* - * Set up/tear down - */ - -void HardwareSPI::begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode) { - if (mode >= 4) { - ASSERT(0); - return; - } - spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB; - spi_mode m = (spi_mode)mode; - enable_device(this->spi_d, true, frequency, end, m); -} - -void HardwareSPI::begin(void) { - this->begin(SPI_1_125MHZ, MSBFIRST, 0); -} - -void HardwareSPI::beginSlave(uint32 bitOrder, uint32 mode) { - if (mode >= 4) { - ASSERT(0); - return; - } - spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB; - spi_mode m = (spi_mode)mode; - enable_device(this->spi_d, false, (SPIFrequency)0, end, m); -} - -void HardwareSPI::beginSlave(void) { - this->beginSlave(MSBFIRST, 0); -} - -void HardwareSPI::end(void) { - if (!spi_is_enabled(this->spi_d)) { - return; - } - - // Follows RM0008's sequence for disabling a SPI in master/slave - // full duplex mode. - while (spi_is_rx_nonempty(this->spi_d)) { - // FIXME [0.1.0] remove this once you have an interrupt based driver - volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d); - } - while (!spi_is_tx_empty(this->spi_d)) - ; - while (spi_is_busy(this->spi_d)) - ; - spi_peripheral_disable(this->spi_d); -} - -/* - * I/O - */ - -uint8 HardwareSPI::read(void) { - uint8 buf[1]; - this->read(buf, 1); - return buf[0]; -} - -void HardwareSPI::read(uint8 *buf, uint32 len) { - uint32 rxed = 0; - while (rxed < len) { - while (!spi_is_rx_nonempty(this->spi_d)) - ; - buf[rxed++] = (uint8)spi_rx_reg(this->spi_d); - } -} - -void HardwareSPI::write(uint8 byte) { - this->write(&byte, 1); -} - -void HardwareSPI::write(const uint8 *data, uint32 length) { - uint32 txed = 0; - while (txed < length) { - txed += spi_tx(this->spi_d, data + txed, length - txed); - } -} - -uint8 HardwareSPI::transfer(uint8 byte) { - this->write(byte); - return this->read(); -} - -/* - * Pin accessors - */ - -uint8 HardwareSPI::misoPin(void) { - return dev_to_spi_pins(this->spi_d)->miso; -} - -uint8 HardwareSPI::mosiPin(void) { - return dev_to_spi_pins(this->spi_d)->mosi; -} - -uint8 HardwareSPI::sckPin(void) { - return dev_to_spi_pins(this->spi_d)->sck; -} - -uint8 HardwareSPI::nssPin(void) { - return dev_to_spi_pins(this->spi_d)->nss; -} - -/* - * Deprecated functions - */ - -uint8 HardwareSPI::send(uint8 data) { - uint8 buf[] = {data}; - return this->send(buf, 1); -} - -uint8 HardwareSPI::send(uint8 *buf, uint32 len) { - uint32 txed = 0; - uint8 ret = 0; - while (txed < len) { - this->write(buf[txed++]); - ret = this->read(); - } - return ret; -} - -uint8 HardwareSPI::recv(void) { - return this->read(); -} - -/* - * Auxiliary functions - */ - -static void configure_gpios(spi_dev *dev, bool as_master); -static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq); - -static const spi_pins* dev_to_spi_pins(spi_dev *dev) { - switch (dev->clk_id) { - case RCC_SPI1: return board_spi_pins; - case RCC_SPI2: return board_spi_pins + 1; -#ifdef STM32_HIGH_DENSITY - case RCC_SPI3: return board_spi_pins + 2; -#endif - default: return NULL; - } -} - -/* Enables the device in master or slave full duplex mode. If you - * change this code, you must ensure that appropriate changes are made - * to HardwareSPI::end(). */ -static void enable_device(spi_dev *dev, - bool as_master, - SPIFrequency freq, - spi_cfg_flag endianness, - spi_mode mode) { - spi_baud_rate baud = determine_baud_rate(dev, freq); - uint32 cfg_flags = (endianness | SPI_DFF_8_BIT | SPI_SW_SLAVE | - (as_master ? SPI_SOFT_SS : 0)); - - spi_init(dev); - configure_gpios(dev, as_master); - if (as_master) { - spi_master_enable(dev, baud, mode, cfg_flags); - } else { - spi_slave_enable(dev, mode, cfg_flags); - } -} - -static void disable_pwm(const stm32_pin_info *i) { - if (i->timer_device) { - timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED); - } -} - -static void configure_gpios(spi_dev *dev, bool as_master) { - const spi_pins *pins = dev_to_spi_pins(dev); - - if (!pins) { - return; - } - - const stm32_pin_info *nssi = &PIN_MAP[pins->nss]; - const stm32_pin_info *scki = &PIN_MAP[pins->sck]; - const stm32_pin_info *misoi = &PIN_MAP[pins->miso]; - const stm32_pin_info *mosii = &PIN_MAP[pins->mosi]; - - disable_pwm(nssi); - disable_pwm(scki); - disable_pwm(misoi); - disable_pwm(mosii); - - spi_gpio_cfg(as_master, - nssi->gpio_device, - nssi->gpio_bit, - scki->gpio_device, - scki->gpio_bit, - misoi->gpio_bit, - mosii->gpio_bit); -} - -static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = { - SPI_BAUD_PCLK_DIV_2, - SPI_BAUD_PCLK_DIV_4, - SPI_BAUD_PCLK_DIV_8, - SPI_BAUD_PCLK_DIV_16, - SPI_BAUD_PCLK_DIV_32, - SPI_BAUD_PCLK_DIV_64, - SPI_BAUD_PCLK_DIV_128, - SPI_BAUD_PCLK_DIV_256, -}; - -/* - * Note: This assumes you're on a LeafLabs-style board - * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz). - */ -static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq) { - if (rcc_dev_clk(dev->clk_id) == RCC_APB2 && freq == SPI_140_625KHZ) { - /* APB2 peripherals are too fast for 140.625 KHz */ - ASSERT(0); - return (spi_baud_rate)~0; - } - return (rcc_dev_clk(dev->clk_id) == RCC_APB2 ? - baud_rates[freq + 1] : - baud_rates[freq]); -} diff --git a/wirish/comm/HardwareSerial.cpp b/wirish/comm/HardwareSerial.cpp deleted file mode 100644 index a9eb763..0000000 --- a/wirish/comm/HardwareSerial.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file HardwareSerial.cpp - * @brief Wirish serial port implementation. - */ - -#include - -#include -#include -#include - -#include - -#define TX1 BOARD_USART1_TX_PIN -#define RX1 BOARD_USART1_RX_PIN -#define TX2 BOARD_USART2_TX_PIN -#define RX2 BOARD_USART2_RX_PIN -#define TX3 BOARD_USART3_TX_PIN -#define RX3 BOARD_USART3_RX_PIN -#if defined STM32_HIGH_DENSITY && !defined(BOARD_maple_RET6) -#define TX4 BOARD_UART4_TX_PIN -#define RX4 BOARD_UART4_RX_PIN -#define TX5 BOARD_UART5_TX_PIN -#define RX5 BOARD_UART5_RX_PIN -#endif - -HardwareSerial Serial1(USART1, TX1, RX1, STM32_PCLK2); -HardwareSerial Serial2(USART2, TX2, RX2, STM32_PCLK1); -HardwareSerial Serial3(USART3, TX3, RX3, STM32_PCLK1); -#if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6) -HardwareSerial Serial4(UART4, TX4, RX4, STM32_PCLK1); -HardwareSerial Serial5(UART5, TX5, RX5, STM32_PCLK1); -#endif - -HardwareSerial::HardwareSerial(usart_dev *usart_device, - uint8 tx_pin, - uint8 rx_pin, - uint32 clock_speed) { - this->usart_device = usart_device; - this->clock_speed = clock_speed; - this->tx_pin = tx_pin; - this->rx_pin = rx_pin; -} - -/* - * Set up/tear down - */ - -void HardwareSerial::begin(uint32 baud) { - ASSERT(baud <= usart_device->max_baud); - - if (baud > usart_device->max_baud) { - return; - } - - const stm32_pin_info *txi = &PIN_MAP[tx_pin]; - const stm32_pin_info *rxi = &PIN_MAP[rx_pin]; - - gpio_set_mode(txi->gpio_device, txi->gpio_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, GPIO_INPUT_FLOATING); - - if (txi->timer_device != NULL) { - /* Turn off any PWM if there's a conflict on this GPIO bit. */ - timer_set_mode(txi->timer_device, txi->timer_channel, TIMER_DISABLED); - } - - usart_init(usart_device); - usart_set_baud_rate(usart_device, clock_speed, baud); - usart_enable(usart_device); -} - -void HardwareSerial::end(void) { - usart_disable(usart_device); -} - -/* - * I/O - */ - -uint8 HardwareSerial::read(void) { - return usart_getc(usart_device); -} - -uint32 HardwareSerial::available(void) { - return usart_data_available(usart_device); -} - -void HardwareSerial::write(unsigned char ch) { - usart_putc(usart_device, ch); -} - -void HardwareSerial::flush(void) { - usart_reset_rx(usart_device); -} diff --git a/wirish/rules.mk b/wirish/rules.mk index 923c17b..6fa3a28 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -3,7 +3,6 @@ sp := $(sp).x dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) -BUILDDIRS += $(BUILD_PATH)/$(d)/comm # Board config -- TODO allow user override WIRISH_BOARD_PATH := boards/$(BOARD) @@ -21,8 +20,8 @@ cSRCS_$(d) := start_c.c cppSRCS_$(d) := wirish_math.cpp \ Print.cpp \ boards.cpp \ - comm/HardwareSerial.cpp \ - comm/HardwareSPI.cpp \ + HardwareSerial.cpp \ + HardwareSPI.cpp \ HardwareTimer.cpp \ usb_serial.cpp \ cxxabi-compat.cpp \ -- cgit v1.2.3 From 5f06399e4ca2266841f888d3efd2740a2fdcc6fb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 11:40:22 -0500 Subject: target-config.mk: Remove FLASH_SIZE, SRAM_SIZE settings. Unused. Signed-off-by: Marti Bolivar --- support/make/target-config.mk | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/support/make/target-config.mk b/support/make/target-config.mk index 98fc4d0..1ca6057 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -6,8 +6,6 @@ ifeq ($(BOARD), maple) ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 DENSITY := STM32_MEDIUM_DENSITY - FLASH_SIZE := 131072 - SRAM_SIZE := 20480 endif ifeq ($(BOARD), maple_native) @@ -16,8 +14,6 @@ ifeq ($(BOARD), maple_native) ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 15 DENSITY := STM32_HIGH_DENSITY - FLASH_SIZE := 524288 - SRAM_SIZE := 65536 endif ifeq ($(BOARD), maple_mini) @@ -26,8 +22,6 @@ ifeq ($(BOARD), maple_mini) ERROR_LED_PORT := GPIOB ERROR_LED_PIN := 1 DENSITY := STM32_MEDIUM_DENSITY - FLASH_SIZE := 131072 - SRAM_SIZE := 20480 endif ifeq ($(BOARD), maple_RET6) @@ -36,8 +30,6 @@ ifeq ($(BOARD), maple_RET6) ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 DENSITY := STM32_HIGH_DENSITY - FLASH_SIZE := 524288 - SRAM_SIZE := 65536 endif ifeq ($(BOARD), olimex_stm32_h103) @@ -46,8 +38,6 @@ ifeq ($(BOARD), olimex_stm32_h103) ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 12 DENSITY := STM32_MEDIUM_DENSITY - FLASH_SIZE := 131072 - SRAM_SIZE := 20480 endif # STM32 family-specific configuration values. -- cgit v1.2.3 From ef61050e57256bc65474b7c741a8b356d1fae7db Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 12:07:38 -0500 Subject: usb_cdcacm.c: Fix warning for non-LeafLabs boards. Signed-off-by: Marti Bolivar --- libmaple/usb/usb_cdcacm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/libmaple/usb/usb_cdcacm.c b/libmaple/usb/usb_cdcacm.c index b41753a..dc7b79e 100644 --- a/libmaple/usb/usb_cdcacm.c +++ b/libmaple/usb/usb_cdcacm.c @@ -59,12 +59,8 @@ #if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) || \ defined(BOARD_maple_mini) || defined(BOARD_maple_native)) - -#warning ("Warning! USB VCOM relies on LeafLabs board-specific " \ - "configuration right now. If you want, you can pretend " \ - "you're one of our boards; i.e., #define BOARD_maple, " \ - "BOARD_maple_mini, etc. according to what matches your MCU " \ - "best." +#warning USB CDC ACM relies on LeafLabs board-specific configuration.\ + You may have problems on non-LeafLabs boards. #endif static void vcomDataTxCb(void); -- cgit v1.2.3 From 62e4ce256e1f2ea18cf2d576ed8110d6553c7fc1 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 12:54:22 -0500 Subject: Revert "Added libs in libraries/ to the include path" This reverts commit 628750bf82135cc1ca25784c8b39eb771ae87024. Don't mess with LIBMAPLE_INCLUDES. This variable comprises include directories for libmaple proper, not for libraries that depend upon libmaple. --- support/make/build-templates.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/support/make/build-templates.mk b/support/make/build-templates.mk index fcf83a1..4371f13 100644 --- a/support/make/build-templates.mk +++ b/support/make/build-templates.mk @@ -1,6 +1,5 @@ define LIBMAPLE_MODULE_template dir := $(1) -LIBMAPLE_INCLUDES += -I$$(dir) include $$(dir)/rules.mk endef -- cgit v1.2.3 From 844665608fbeeab270e3d1a4bd797afd24302a10 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 13:26:34 -0500 Subject: Make USB its own submodule. Add libmaple/usb/rules.mk, which compiles the USB FS device firmware submodule. Move the logic for compiling the USB stack from libmaple/rules.mk into libmaple/usb/rules.mk. Move libmaple/usb/usb_cdacm.h to libmaple/include/libmaple/. Its API is sufficiently general that we'll be able to port it over to USB OTG (either FS or HS) eventually, and that lets us include it from Wirish using the new style for libmaple headers. Fix the includes for public libmaple headers within libmaple/usb. Signed-off-by: Marti Bolivar --- Makefile | 1 + libmaple/include/libmaple/usb_cdcacm.h | 59 ++++++++++++++++++++++++++++++++++ libmaple/rules.mk | 14 +------- libmaple/usb/rules.mk | 36 +++++++++++++++++++++ libmaple/usb/usb.c | 8 +++-- libmaple/usb/usb_cdcacm.c | 10 +++--- libmaple/usb/usb_cdcacm.h | 59 ---------------------------------- libmaple/usb/usb_descriptors.h | 2 +- libmaple/usb/usb_lib_globals.h | 1 + libmaple/usb/usb_reg_map.h | 4 +-- wirish/boards.cpp | 2 +- wirish/usb_serial.cpp | 2 +- 12 files changed, 114 insertions(+), 84 deletions(-) create mode 100644 libmaple/include/libmaple/usb_cdcacm.h create mode 100644 libmaple/usb/rules.mk delete mode 100644 libmaple/usb/usb_cdcacm.h diff --git a/Makefile b/Makefile index c6a1e07..c2a60dd 100644 --- a/Makefile +++ b/Makefile @@ -80,6 +80,7 @@ ifeq ($(LIBMAPLE_MODULES),) else LIBMAPLE_MODULES += $(SRCROOT)/libmaple endif +LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # USB FS device LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_FAMILY) # family submodule in libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish # Official libraries: diff --git a/libmaple/include/libmaple/usb_cdcacm.h b/libmaple/include/libmaple/usb_cdcacm.h new file mode 100644 index 0000000..2dbcbea --- /dev/null +++ b/libmaple/include/libmaple/usb_cdcacm.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file usb_cdcacm.h + * @brief USB CDC ACM (virtual serial terminal) support + */ + +#ifndef _LIBMAPLE_USB_CDCACM_H_ +#define _LIBMAPLE_USB_CDCACM_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void usb_cdcacm_enable(gpio_dev*, uint8); +void usb_cdcacm_disable(gpio_dev*, uint8); + +void usb_cdcacm_putc(char ch); +uint32 usb_cdcacm_tx(const uint8* buf, uint32 len); +uint32 usb_cdcacm_rx(uint8* buf, uint32 len); + +uint32 usb_cdcacm_data_available(void); /* in RX buffer */ +uint16 usb_cdcacm_get_pending(void); + +uint8 usb_cdcacm_get_dtr(void); +uint8 usb_cdcacm_get_rts(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/rules.mk b/libmaple/rules.mk index a6b330a..3dcf0ce 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -3,13 +3,8 @@ sp := $(sp).x dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) -BUILDDIRS += $(BUILD_PATH)/$(d)/usb -BUILDDIRS += $(BUILD_PATH)/$(d)/usb/usb_lib LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include -# FIXME: move public USB headers to include/libmaple/usb/ or something. -LIBMAPLE_INCLUDES += -I$(LIBMAPLE_PATH)/usb \ - -I$(LIBMAPLE_PATH)/usb/usb_lib # Local flags CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall # -Werror @@ -33,14 +28,7 @@ cSRCS_$(d) := adc.c \ systick.c \ timer.c \ usart.c \ - util.c \ - usb/usb.c \ - usb/usb_reg_map.c \ - usb/usb_cdcacm.c \ - usb/usb_lib/usb_core.c \ - usb/usb_lib/usb_init.c \ - usb/usb_lib/usb_mem.c \ - usb/usb_lib/usb_regs.c + util.c sSRCS_$(d) := exc.S diff --git a/libmaple/usb/rules.mk b/libmaple/usb/rules.mk new file mode 100644 index 0000000..9ef8d70 --- /dev/null +++ b/libmaple/usb/rules.mk @@ -0,0 +1,36 @@ +# Standard things +sp := $(sp).x +dirstack_$(sp) := $(d) +d := $(dir) +BUILDDIRS += $(BUILD_PATH)/$(d) +BUILDDIRS += $(BUILD_PATH)/$(d)/usb_lib + +# Local flags +CFLAGS_$(d) = -I$(d) -I$(d)/usb_lib $(LIBMAPLE_INCLUDES) -Wall + +# Local rules and targets +sSRCS_$(d) := +cSRCS_$(d) := usb.c \ + usb_reg_map.c \ + usb_cdcacm.c \ + usb_lib/usb_core.c \ + usb_lib/usb_init.c \ + usb_lib/usb_mem.c \ + usb_lib/usb_regs.c + +sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) +cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) + +OBJS_$(d) := $(sFILES_$(d):%.S=$(BUILD_PATH)/%.o) \ + $(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) +DEPS_$(d) := $(OBJS_$(d):%.o=%.d) + +$(OBJS_$(d)): TGT_CFLAGS := $(CFLAGS_$(d)) +$(OBJS_$(d)): TGT_ASFLAGS := + +TGT_BIN += $(OBJS_$(d)) + +# Standard things +-include $(DEPS_$(d)) +d := $(dirstack_$(sp)) +sp := $(basename $(sp)) diff --git a/libmaple/usb/usb.c b/libmaple/usb/usb.c index 667b11f..6f23848 100644 --- a/libmaple/usb/usb.c +++ b/libmaple/usb/usb.c @@ -29,14 +29,16 @@ * @brief USB support. */ -#include "usb.h" +#include -#include "libmaple.h" -#include "rcc.h" +#include +#include +/* Private headers */ #include "usb_reg_map.h" #include "usb_lib_globals.h" +/* usb_lib headers */ #include "usb_type.h" #include "usb_core.h" diff --git a/libmaple/usb/usb_cdcacm.c b/libmaple/usb/usb_cdcacm.c index dc7b79e..07d2bc8 100644 --- a/libmaple/usb/usb_cdcacm.c +++ b/libmaple/usb/usb_cdcacm.c @@ -31,16 +31,18 @@ * routines. */ -#include "usb_cdcacm.h" +#include -#include "nvic.h" -#include "delay.h" +#include +#include +#include -#include "usb.h" +/* Private headers */ #include "usb_descriptors.h" #include "usb_lib_globals.h" #include "usb_reg_map.h" +/* usb_lib headers */ #include "usb_type.h" #include "usb_core.h" #include "usb_def.h" diff --git a/libmaple/usb/usb_cdcacm.h b/libmaple/usb/usb_cdcacm.h deleted file mode 100644 index ec672a3..0000000 --- a/libmaple/usb/usb_cdcacm.h +++ /dev/null @@ -1,59 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file usb_cdcacm.h - * @brief USB CDC ACM (virtual serial terminal) support - */ - -#ifndef _USB_CDCACM_H_ -#define _USB_CDCACM_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void usb_cdcacm_enable(gpio_dev*, uint8); -void usb_cdcacm_disable(gpio_dev*, uint8); - -void usb_cdcacm_putc(char ch); -uint32 usb_cdcacm_tx(const uint8* buf, uint32 len); -uint32 usb_cdcacm_rx(uint8* buf, uint32 len); - -uint32 usb_cdcacm_data_available(void); /* in RX buffer */ -uint16 usb_cdcacm_get_pending(void); - -uint8 usb_cdcacm_get_dtr(void); -uint8 usb_cdcacm_get_rts(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/usb/usb_descriptors.h b/libmaple/usb/usb_descriptors.h index 405588a..9bcb2b6 100644 --- a/libmaple/usb/usb_descriptors.h +++ b/libmaple/usb/usb_descriptors.h @@ -27,7 +27,7 @@ #ifndef _USB_DESCRIPTORS_H_ #define _USB_DESCRIPTORS_H_ -#include "libmaple.h" +#include #define USB_DESCRIPTOR_TYPE_DEVICE 0x01 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02 diff --git a/libmaple/usb/usb_lib_globals.h b/libmaple/usb/usb_lib_globals.h index a494817..1cd2754 100644 --- a/libmaple/usb/usb_lib_globals.h +++ b/libmaple/usb/usb_lib_globals.h @@ -27,6 +27,7 @@ #ifndef _USB_LIB_GLOBALS_H_ #define _USB_LIB_GLOBALS_H_ +/* usb_lib headers */ #include "usb_type.h" #include "usb_core.h" diff --git a/libmaple/usb/usb_reg_map.h b/libmaple/usb/usb_reg_map.h index 5bf5d96..ce80842 100644 --- a/libmaple/usb/usb_reg_map.h +++ b/libmaple/usb/usb_reg_map.h @@ -24,8 +24,8 @@ * SOFTWARE. *****************************************************************************/ -#include "libmaple_types.h" -#include "util.h" +#include +#include #ifndef _USB_REG_MAP_H_ #define _USB_REG_MAP_H_ diff --git a/wirish/boards.cpp b/wirish/boards.cpp index dbdcf1c..1f97119 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -41,7 +41,7 @@ #include #include #include -#include "usb_cdcacm.h" +#include static void setupFlash(void); static void setupClocks(void); diff --git a/wirish/usb_serial.cpp b/wirish/usb_serial.cpp index 1fd6e65..388c739 100644 --- a/wirish/usb_serial.cpp +++ b/wirish/usb_serial.cpp @@ -32,7 +32,7 @@ #include -#include "usb_cdcacm.h" +#include #include #include -- cgit v1.2.3 From bdf0c087c0172dd911bb1cda7531b2bd46312700 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 14:48:12 -0500 Subject: libmaple/rules.mk: Reinstate -Werror. This is OK across all boards now that USB is its own submodule. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 3dcf0ce..cdc0614 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -7,7 +7,7 @@ BUILDDIRS += $(BUILD_PATH)/$(d) LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include # Local flags -CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall # -Werror +CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c \ -- cgit v1.2.3 From b6290890b64d5188f75527b979c5c7912547be9b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 15:14:03 -0500 Subject: Move RCC support for STM32F1 to libmaple/stm32f1/. This is a backwards-compatible change. Modify libmaple/rules.mk to include the family's include directory. This allows libmaple/include/libmaple/rcc.h to include the STM32F1 RCC header with #include . We'll use this convention henceforth to distinguish between top-level and family-specific headers. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 523 ++------------------------------ libmaple/rcc.c | 206 ------------- libmaple/rules.mk | 3 +- libmaple/stm32f1/include/family/rcc.h | 553 ++++++++++++++++++++++++++++++++++ libmaple/stm32f1/rcc.c | 205 +++++++++++++ libmaple/stm32f1/rules.mk | 9 +- 6 files changed, 784 insertions(+), 715 deletions(-) delete mode 100644 libmaple/rcc.c create mode 100644 libmaple/stm32f1/include/family/rcc.h create mode 100644 libmaple/stm32f1/rcc.c diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index ef44b68..a4b66e5 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -26,7 +26,7 @@ /** * @file rcc.h - * @brief reset and clock control definitions and prototypes + * @brief Reset and Clock Control (RCC) interface. */ #ifndef _LIBMAPLE_RCC_H_ @@ -37,350 +37,23 @@ extern "C"{ #endif #include +#include -/** RCC register map type */ -typedef struct rcc_reg_map { - __io uint32 CR; /**< Clock control register */ - __io uint32 CFGR; /**< Clock configuration register */ - __io uint32 CIR; /**< Clock interrupt register */ - __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ - __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ - __io uint32 AHBENR; /**< AHB peripheral clock enable register */ - __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ - __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ - __io uint32 BDCR; /**< Backup domain control register */ - __io uint32 CSR; /**< Control/status register */ -} rcc_reg_map; - -/** RCC register map base pointer */ -#define RCC_BASE ((struct rcc_reg_map*)0x40021000) - -/* - * Register bit definitions - */ - -/* Clock control register */ - -#define RCC_CR_PLLRDY_BIT 25 -#define RCC_CR_PLLON_BIT 24 -#define RCC_CR_CSSON_BIT 19 -#define RCC_CR_HSEBYP_BIT 18 -#define RCC_CR_HSERDY_BIT 17 -#define RCC_CR_HSEON_BIT 16 -#define RCC_CR_HSIRDY_BIT 1 -#define RCC_CR_HSION_BIT 0 - -#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) -#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) -#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) -#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) -#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) -#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) -#define RCC_CR_HSICAL (0xFF << 8) -#define RCC_CR_HSITRIM (0x1F << 3) -#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) -#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) - -/* Clock configuration register */ - -#define RCC_CFGR_USBPRE_BIT 22 -#define RCC_CFGR_PLLXTPRE_BIT 17 -#define RCC_CFGR_PLLSRC_BIT 16 - -#define RCC_CFGR_MCO (0x3 << 24) -#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) -#define RCC_CFGR_PLLMUL (0xF << 18) -#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) -#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) -#define RCC_CFGR_ADCPRE (0x3 << 14) -#define RCC_CFGR_PPRE2 (0x7 << 11) -#define RCC_CFGR_PPRE1 (0x7 << 8) -#define RCC_CFGR_HPRE (0xF << 4) -#define RCC_CFGR_SWS (0x3 << 2) -#define RCC_CFGR_SWS_PLL (0x2 << 2) -#define RCC_CFGR_SWS_HSE (0x1 << 2) -#define RCC_CFGR_SW 0x3 -#define RCC_CFGR_SW_PLL 0x2 -#define RCC_CFGR_SW_HSE 0x1 - -/* Clock interrupt register */ - -#define RCC_CIR_CSSC_BIT 23 -#define RCC_CIR_PLLRDYC_BIT 20 -#define RCC_CIR_HSERDYC_BIT 19 -#define RCC_CIR_HSIRDYC_BIT 18 -#define RCC_CIR_LSERDYC_BIT 17 -#define RCC_CIR_LSIRDYC_BIT 16 -#define RCC_CIR_PLLRDYIE_BIT 12 -#define RCC_CIR_HSERDYIE_BIT 11 -#define RCC_CIR_HSIRDYIE_BIT 10 -#define RCC_CIR_LSERDYIE_BIT 9 -#define RCC_CIR_LSIRDYIE_BIT 8 -#define RCC_CIR_CSSF_BIT 7 -#define RCC_CIR_PLLRDYF_BIT 4 -#define RCC_CIR_HSERDYF_BIT 3 -#define RCC_CIR_HSIRDYF_BIT 2 -#define RCC_CIR_LSERDYF_BIT 1 -#define RCC_CIR_LSIRDYF_BIT 0 - -#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) -#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) -#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) -#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) -#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) -#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) -#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) -#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) -#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) -#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) -#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) -#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) -#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) -#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) -#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) -#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) -#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) - -/* APB2 peripheral reset register */ - -#define RCC_APB2RSTR_TIM11RST_BIT 21 -#define RCC_APB2RSTR_TIM10RST_BIT 20 -#define RCC_APB2RSTR_TIM9RST_BIT 19 -#define RCC_APB2RSTR_ADC3RST_BIT 15 -#define RCC_APB2RSTR_USART1RST_BIT 14 -#define RCC_APB2RSTR_TIM8RST_BIT 13 -#define RCC_APB2RSTR_SPI1RST_BIT 12 -#define RCC_APB2RSTR_TIM1RST_BIT 11 -#define RCC_APB2RSTR_ADC2RST_BIT 10 -#define RCC_APB2RSTR_ADC1RST_BIT 9 -#define RCC_APB2RSTR_IOPGRST_BIT 8 -#define RCC_APB2RSTR_IOPFRST_BIT 7 -#define RCC_APB2RSTR_IOPERST_BIT 6 -#define RCC_APB2RSTR_IOPDRST_BIT 5 -#define RCC_APB2RSTR_IOPCRST_BIT 4 -#define RCC_APB2RSTR_IOPBRST_BIT 3 -#define RCC_APB2RSTR_IOPARST_BIT 2 -#define RCC_APB2RSTR_AFIORST_BIT 0 - -#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) -#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) -#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) -#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) -#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) -#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) -#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) -#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) -#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) -#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) -#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) -#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) -#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) -#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) -#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) -#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) -#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) -#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) - -/* APB1 peripheral reset register */ - -#define RCC_APB1RSTR_DACRST_BIT 29 -#define RCC_APB1RSTR_PWRRST_BIT 28 -#define RCC_APB1RSTR_BKPRST_BIT 27 -#define RCC_APB1RSTR_CANRST_BIT 25 -#define RCC_APB1RSTR_USBRST_BIT 23 -#define RCC_APB1RSTR_I2C2RST_BIT 22 -#define RCC_APB1RSTR_I2C1RST_BIT 21 -#define RCC_APB1RSTR_UART5RST_BIT 20 -#define RCC_APB1RSTR_UART4RST_BIT 19 -#define RCC_APB1RSTR_USART3RST_BIT 18 -#define RCC_APB1RSTR_USART2RST_BIT 17 -#define RCC_APB1RSTR_SPI3RST_BIT 15 -#define RCC_APB1RSTR_SPI2RST_BIT 14 -#define RCC_APB1RSTR_WWDRST_BIT 11 -#define RCC_APB1RSTR_TIM14RST_BIT 8 -#define RCC_APB1RSTR_TIM13RST_BIT 7 -#define RCC_APB1RSTR_TIM12RST_BIT 6 -#define RCC_APB1RSTR_TIM7RST_BIT 5 -#define RCC_APB1RSTR_TIM6RST_BIT 4 -#define RCC_APB1RSTR_TIM5RST_BIT 3 -#define RCC_APB1RSTR_TIM4RST_BIT 2 -#define RCC_APB1RSTR_TIM3RST_BIT 1 -#define RCC_APB1RSTR_TIM2RST_BIT 0 - -#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) -#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) -#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) -#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) -#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) -#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) -#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) -#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) -#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) -#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) -#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) -#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) -#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) -#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) -#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) -#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) -#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) -#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) -#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) -#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) -#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) -#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) -#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) - -/* AHB peripheral clock enable register */ - -#define RCC_AHBENR_SDIOEN_BIT 10 -#define RCC_AHBENR_FSMCEN_BIT 8 -#define RCC_AHBENR_CRCEN_BIT 7 -#define RCC_AHBENR_FLITFEN_BIT 4 -#define RCC_AHBENR_SRAMEN_BIT 2 -#define RCC_AHBENR_DMA2EN_BIT 1 -#define RCC_AHBENR_DMA1EN_BIT 0 - -#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) -#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) -#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) -#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) -#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) -#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) -#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) - -/* APB2 peripheral clock enable register */ - -#define RCC_APB2ENR_TIM11EN_BIT 21 -#define RCC_APB2ENR_TIM10EN_BIT 20 -#define RCC_APB2ENR_TIM9EN_BIT 19 -#define RCC_APB2ENR_ADC3EN_BIT 15 -#define RCC_APB2ENR_USART1EN_BIT 14 -#define RCC_APB2ENR_TIM8EN_BIT 13 -#define RCC_APB2ENR_SPI1EN_BIT 12 -#define RCC_APB2ENR_TIM1EN_BIT 11 -#define RCC_APB2ENR_ADC2EN_BIT 10 -#define RCC_APB2ENR_ADC1EN_BIT 9 -#define RCC_APB2ENR_IOPGEN_BIT 8 -#define RCC_APB2ENR_IOPFEN_BIT 7 -#define RCC_APB2ENR_IOPEEN_BIT 6 -#define RCC_APB2ENR_IOPDEN_BIT 5 -#define RCC_APB2ENR_IOPCEN_BIT 4 -#define RCC_APB2ENR_IOPBEN_BIT 3 -#define RCC_APB2ENR_IOPAEN_BIT 2 -#define RCC_APB2ENR_AFIOEN_BIT 0 - -#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) -#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) -#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) -#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) -#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) -#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) -#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) -#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) -#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) -#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) -#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) -#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) -#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) -#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) -#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) -#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) -#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) -#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) - -/* APB1 peripheral clock enable register */ - -#define RCC_APB1ENR_DACEN_BIT 29 -#define RCC_APB1ENR_PWREN_BIT 28 -#define RCC_APB1ENR_BKPEN_BIT 27 -#define RCC_APB1ENR_CANEN_BIT 25 -#define RCC_APB1ENR_USBEN_BIT 23 -#define RCC_APB1ENR_I2C2EN_BIT 22 -#define RCC_APB1ENR_I2C1EN_BIT 21 -#define RCC_APB1ENR_UART5EN_BIT 20 -#define RCC_APB1ENR_UART4EN_BIT 19 -#define RCC_APB1ENR_USART3EN_BIT 18 -#define RCC_APB1ENR_USART2EN_BIT 17 -#define RCC_APB1ENR_SPI3EN_BIT 15 -#define RCC_APB1ENR_SPI2EN_BIT 14 -#define RCC_APB1ENR_WWDEN_BIT 11 -#define RCC_APB1ENR_TIM14EN_BIT 8 -#define RCC_APB1ENR_TIM13EN_BIT 7 -#define RCC_APB1ENR_TIM12EN_BIT 6 -#define RCC_APB1ENR_TIM7EN_BIT 5 -#define RCC_APB1ENR_TIM6EN_BIT 4 -#define RCC_APB1ENR_TIM5EN_BIT 3 -#define RCC_APB1ENR_TIM4EN_BIT 2 -#define RCC_APB1ENR_TIM3EN_BIT 1 -#define RCC_APB1ENR_TIM2EN_BIT 0 - -#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) -#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) -#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) -#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) -#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) -#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) -#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) -#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) -#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) -#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) -#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) -#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) -#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) -#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) -#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) -#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) -#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) -#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) -#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) -#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) -#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) -#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) -#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) - -/* Backup domain control register */ - -#define RCC_BDCR_BDRST_BIT 16 -#define RCC_BDCR_RTCEN_BIT 15 -#define RCC_BDCR_LSEBYP_BIT 2 -#define RCC_BDCR_LSERDY_BIT 1 -#define RCC_BDCR_LSEON_BIT 0 - -#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) -#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) -#define RCC_BDCR_RTCSEL (0x3 << 8) -#define RCC_BDCR_RTCSEL_NONE (0x0 << 8) -#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) -#define RCC_BDCR_RTCSEL_HSE (0x3 << 8) -#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) -#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) -#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) - -/* Control/status register */ - -#define RCC_CSR_LPWRRSTF_BIT 31 -#define RCC_CSR_WWDGRSTF_BIT 30 -#define RCC_CSR_IWDGRSTF_BIT 29 -#define RCC_CSR_SFTRSTF_BIT 28 -#define RCC_CSR_PORRSTF_BIT 27 -#define RCC_CSR_PINRSTF_BIT 26 -#define RCC_CSR_RMVF_BIT 24 -#define RCC_CSR_LSIRDY_BIT 1 -#define RCC_CSR_LSION_BIT 0 - -#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) -#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) -#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) -#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) -#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) -#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) -#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) -#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) -#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) - -/* - * Convenience routines +/* Note: Beyond the usual (registers, etc.), it's up to the family + * header to define the following types: + * + * - rcc_pllsrc: For each PLL source (passed to rcc_clk_init()). + * + * - rcc_pll_multiplier: If appropriate (TODO verify this makes sense). + * + * - rcc_clk_id: For each available peripheral. These are widely used + * as unique IDs (TODO extricate from RCC?). Peripherals which are + * common across families should use the same token for their + * rcc_clk_id in each family header. + * + * - rcc_clk_domain: For each clock domain (returned by rcc_dev_clk()). + * + * - rcc_prescaler (and a suitable set of dividers): for rcc_set_prescaler(). */ /** @@ -393,174 +66,12 @@ typedef enum rcc_sysclk_src { RCC_CLKSRC_PLL = 0x2, } rcc_sysclk_src; -/** - * PLL entry clock source - * @see rcc_clk_init() - */ -typedef enum rcc_pllsrc { - RCC_PLLSRC_HSE = (0x1 << 16), - RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) -} rcc_pllsrc; - -/** - * PLL multipliers - * @see rcc_clk_init() - */ -typedef enum rcc_pll_multiplier { - RCC_PLLMUL_2 = (0x0 << 18), - RCC_PLLMUL_3 = (0x1 << 18), - RCC_PLLMUL_4 = (0x2 << 18), - RCC_PLLMUL_5 = (0x3 << 18), - RCC_PLLMUL_6 = (0x4 << 18), - RCC_PLLMUL_7 = (0x5 << 18), - RCC_PLLMUL_8 = (0x6 << 18), - RCC_PLLMUL_9 = (0x7 << 18), - RCC_PLLMUL_10 = (0x8 << 18), - RCC_PLLMUL_11 = (0x9 << 18), - RCC_PLLMUL_12 = (0xA << 18), - RCC_PLLMUL_13 = (0xB << 18), - RCC_PLLMUL_14 = (0xC << 18), - RCC_PLLMUL_15 = (0xD << 18), - RCC_PLLMUL_16 = (0xE << 18), -} rcc_pll_multiplier; - -/** - * @brief Identifies bus and clock line for a peripheral. - * - * Also generally useful as a unique identifier for that peripheral - * (or its corresponding device struct). - */ -typedef enum rcc_clk_id { - RCC_GPIOA, - RCC_GPIOB, - RCC_GPIOC, - RCC_GPIOD, - RCC_AFIO, - RCC_ADC1, - RCC_ADC2, - RCC_ADC3, - RCC_USART1, - RCC_USART2, - RCC_USART3, - RCC_TIMER1, - RCC_TIMER2, - RCC_TIMER3, - RCC_TIMER4, - RCC_SPI1, - RCC_SPI2, - RCC_DMA1, - RCC_PWR, - RCC_BKP, - RCC_I2C1, - RCC_I2C2, - RCC_CRC, - RCC_FLITF, - RCC_SRAM, - RCC_USB, -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) - RCC_GPIOE, - RCC_GPIOF, - RCC_GPIOG, - RCC_UART4, - RCC_UART5, - RCC_TIMER5, - RCC_TIMER6, - RCC_TIMER7, - RCC_TIMER8, - RCC_FSMC, - RCC_DAC, - RCC_DMA2, - RCC_SDIO, - RCC_SPI3, -#endif -#ifdef STM32_XL_DENSITY - RCC_TIMER9, - RCC_TIMER10, - RCC_TIMER11, - RCC_TIMER12, - RCC_TIMER13, - RCC_TIMER14, -#endif -} rcc_clk_id; - void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul); void rcc_clk_enable(rcc_clk_id device); void rcc_reset_dev(rcc_clk_id device); - -typedef enum rcc_clk_domain { - RCC_APB1, - RCC_APB2, - RCC_AHB -} rcc_clk_domain; - rcc_clk_domain rcc_dev_clk(rcc_clk_id device); - -/** - * Prescaler identifiers - * @see rcc_set_prescaler() - */ -typedef enum rcc_prescaler { - RCC_PRESCALER_AHB, - RCC_PRESCALER_APB1, - RCC_PRESCALER_APB2, - RCC_PRESCALER_USB, - RCC_PRESCALER_ADC -} rcc_prescaler; - -/** - * ADC prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_adc_divider { - RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14, - RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14, - RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14, - RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14, -} rcc_adc_divider; - -/** - * APB1 prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_apb1_divider { - RCC_APB1_HCLK_DIV_1 = 0x0 << 8, - RCC_APB1_HCLK_DIV_2 = 0x4 << 8, - RCC_APB1_HCLK_DIV_4 = 0x5 << 8, - RCC_APB1_HCLK_DIV_8 = 0x6 << 8, - RCC_APB1_HCLK_DIV_16 = 0x7 << 8, -} rcc_apb1_divider; - -/** - * APB2 prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_apb2_divider { - RCC_APB2_HCLK_DIV_1 = 0x0 << 11, - RCC_APB2_HCLK_DIV_2 = 0x4 << 11, - RCC_APB2_HCLK_DIV_4 = 0x5 << 11, - RCC_APB2_HCLK_DIV_8 = 0x6 << 11, - RCC_APB2_HCLK_DIV_16 = 0x7 << 11, -} rcc_apb2_divider; - -/** - * AHB prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_ahb_divider { - RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4, - RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4, - RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4, - RCC_AHB_SYSCLK_DIV_8 = 0xA << 4, - RCC_AHB_SYSCLK_DIV_16 = 0xB << 4, - RCC_AHB_SYSCLK_DIV_32 = 0xC << 4, - RCC_AHB_SYSCLK_DIV_64 = 0xD << 4, - RCC_AHB_SYSCLK_DIV_128 = 0xD << 4, - RCC_AHB_SYSCLK_DIV_256 = 0xE << 4, - RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, -} rcc_ahb_divider; - void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); #ifdef __cplusplus diff --git a/libmaple/rcc.c b/libmaple/rcc.c deleted file mode 100644 index ed3f11e..0000000 --- a/libmaple/rcc.c +++ /dev/null @@ -1,206 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file rcc.c - * @brief Implements pretty much only the basic clock setup on the - * stm32, clock enable/disable and peripheral reset commands. - */ - -#include -#include -#include -#include - -#define APB1 RCC_APB1 -#define APB2 RCC_APB2 -#define AHB RCC_AHB - -struct rcc_dev_info { - const rcc_clk_domain clk_domain; - const uint8 line_num; -}; - -/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset - * register bit numbers. */ -static const struct rcc_dev_info rcc_dev_table[] = { - [RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 }, - [RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 }, - [RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 }, - [RCC_GPIOD] = { .clk_domain = APB2, .line_num = 5 }, - [RCC_AFIO] = { .clk_domain = APB2, .line_num = 0 }, - [RCC_ADC1] = { .clk_domain = APB2, .line_num = 9 }, - [RCC_ADC2] = { .clk_domain = APB2, .line_num = 10 }, - [RCC_ADC3] = { .clk_domain = APB2, .line_num = 15 }, - [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 }, - [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 }, - [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 }, - [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 }, - [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 }, - [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 }, - [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 }, - [RCC_SPI1] = { .clk_domain = APB2, .line_num = 12 }, - [RCC_SPI2] = { .clk_domain = APB1, .line_num = 14 }, - [RCC_DMA1] = { .clk_domain = AHB, .line_num = 0 }, - [RCC_PWR] = { .clk_domain = APB1, .line_num = 28}, - [RCC_BKP] = { .clk_domain = APB1, .line_num = 27}, - [RCC_I2C1] = { .clk_domain = APB1, .line_num = 21 }, - [RCC_I2C2] = { .clk_domain = APB1, .line_num = 22 }, - [RCC_CRC] = { .clk_domain = AHB, .line_num = 6}, - [RCC_FLITF] = { .clk_domain = AHB, .line_num = 4}, - [RCC_SRAM] = { .clk_domain = AHB, .line_num = 2}, - [RCC_USB] = { .clk_domain = APB1, .line_num = 23}, -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) - [RCC_GPIOE] = { .clk_domain = APB2, .line_num = 6 }, - [RCC_GPIOF] = { .clk_domain = APB2, .line_num = 7 }, - [RCC_GPIOG] = { .clk_domain = APB2, .line_num = 8 }, - [RCC_UART4] = { .clk_domain = APB1, .line_num = 19 }, - [RCC_UART5] = { .clk_domain = APB1, .line_num = 20 }, - [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 }, - [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 }, - [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 }, - [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 }, - [RCC_FSMC] = { .clk_domain = AHB, .line_num = 8 }, - [RCC_DAC] = { .clk_domain = APB1, .line_num = 29 }, - [RCC_DMA2] = { .clk_domain = AHB, .line_num = 1 }, - [RCC_SDIO] = { .clk_domain = AHB, .line_num = 10 }, - [RCC_SPI3] = { .clk_domain = APB1, .line_num = 15 }, -#endif -#ifdef STM32_XL_DENSITY - [RCC_TIMER9] = { .clk_domain = APB2, .line_num = 19 }, - [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 }, - [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 }, - [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 }, - [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 }, - [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 }, -#endif -}; - -/** - * @brief Initialize the clock control system. Initializes the system - * clock source to use the PLL driven by an external oscillator - * @param sysclk_src system clock source, must be PLL - * @param pll_src pll clock source, must be HSE - * @param pll_mul pll multiplier - */ -void rcc_clk_init(rcc_sysclk_src sysclk_src, - rcc_pllsrc pll_src, - rcc_pll_multiplier pll_mul) { - uint32 cfgr = 0; - uint32 cr; - - /* Assume that we're going to clock the chip off the PLL, fed by - * the HSE */ - ASSERT(sysclk_src == RCC_CLKSRC_PLL && - pll_src == RCC_PLLSRC_HSE); - - RCC_BASE->CFGR = pll_src | pll_mul; - - /* Turn on the HSE */ - cr = RCC_BASE->CR; - cr |= RCC_CR_HSEON; - RCC_BASE->CR = cr; - while (!(RCC_BASE->CR & RCC_CR_HSERDY)) - ; - - /* Now the PLL */ - cr |= RCC_CR_PLLON; - RCC_BASE->CR = cr; - while (!(RCC_BASE->CR & RCC_CR_PLLRDY)) - ; - - /* Finally, let's switch over to the PLL */ - cfgr &= ~RCC_CFGR_SW; - cfgr |= RCC_CFGR_SW_PLL; - RCC_BASE->CFGR = cfgr; - while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) - ; -} - -/** - * @brief Turn on the clock line on a peripheral - * @param id Clock ID of the peripheral to turn on. - */ -void rcc_clk_enable(rcc_clk_id id) { - static const __io uint32* enable_regs[] = { - [APB1] = &RCC_BASE->APB1ENR, - [APB2] = &RCC_BASE->APB2ENR, - [AHB] = &RCC_BASE->AHBENR, - }; - - rcc_clk_domain clk_domain = rcc_dev_clk(id); - __io uint32* enr = (__io uint32*)enable_regs[clk_domain]; - uint8 lnum = rcc_dev_table[id].line_num; - - bb_peri_set_bit(enr, lnum, 1); -} - -/** - * @brief Reset a peripheral. - * @param id Clock ID of the peripheral to reset. - */ -void rcc_reset_dev(rcc_clk_id id) { - static const __io uint32* reset_regs[] = { - [APB1] = &RCC_BASE->APB1RSTR, - [APB2] = &RCC_BASE->APB2RSTR, - }; - - rcc_clk_domain clk_domain = rcc_dev_clk(id); - __io void* addr = (__io void*)reset_regs[clk_domain]; - uint8 lnum = rcc_dev_table[id].line_num; - - bb_peri_set_bit(addr, lnum, 1); - bb_peri_set_bit(addr, lnum, 0); -} - -/** - * @brief Get a peripheral's clock domain - * @param id Clock ID of the peripheral whose clock domain to return - * @return Clock source for the given clock ID - */ -rcc_clk_domain rcc_dev_clk(rcc_clk_id id) { - return rcc_dev_table[id].clk_domain; -} - -/** - * @brief Set the divider on a peripheral prescaler - * @param prescaler prescaler to set - * @param divider prescaler divider - */ -void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { - static const uint32 masks[] = { - [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE, - [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1, - [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2, - [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE, - [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE, - }; - - uint32 cfgr = RCC_BASE->CFGR; - cfgr &= ~masks[prescaler]; - cfgr |= divider; - RCC_BASE->CFGR = cfgr; -} diff --git a/libmaple/rules.mk b/libmaple/rules.mk index cdc0614..cf95b48 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -4,7 +4,7 @@ dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) -LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include +LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include -I$(LIBMAPLE_MODULE_FAMILY)/include # Local flags CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror @@ -22,7 +22,6 @@ cSRCS_$(d) := adc.c \ nvic.c \ pwr.c \ i2c.c \ - rcc.c \ spi.c \ syscalls.c \ systick.c \ diff --git a/libmaple/stm32f1/include/family/rcc.h b/libmaple/stm32f1/include/family/rcc.h new file mode 100644 index 0000000..261dc5d --- /dev/null +++ b/libmaple/stm32f1/include/family/rcc.h @@ -0,0 +1,553 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/rcc.h + * @brief STM32F1 reset and clock control (RCC) header. + */ + +#ifndef _LIBMAPLE_STM32F1_RCC_H_ +#define _LIBMAPLE_STM32F1_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Register map + */ + +/** RCC register map type */ +typedef struct rcc_reg_map { + __io uint32 CR; /**< Clock control register */ + __io uint32 CFGR; /**< Clock configuration register */ + __io uint32 CIR; /**< Clock interrupt register */ + __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ + __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ + __io uint32 AHBENR; /**< AHB peripheral clock enable register */ + __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ + __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ + __io uint32 BDCR; /**< Backup domain control register */ + __io uint32 CSR; /**< Control/status register */ +} rcc_reg_map; + +/** RCC register map base pointer */ +#define RCC_BASE ((struct rcc_reg_map*)0x40021000) + +/* + * Register bit definitions + */ + +/* Clock control register */ + +#define RCC_CR_PLLRDY_BIT 25 +#define RCC_CR_PLLON_BIT 24 +#define RCC_CR_CSSON_BIT 19 +#define RCC_CR_HSEBYP_BIT 18 +#define RCC_CR_HSERDY_BIT 17 +#define RCC_CR_HSEON_BIT 16 +#define RCC_CR_HSIRDY_BIT 1 +#define RCC_CR_HSION_BIT 0 + +#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) +#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) +#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) +#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) +#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) +#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) +#define RCC_CR_HSICAL (0xFF << 8) +#define RCC_CR_HSITRIM (0x1F << 3) +#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) +#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) + +/* Clock configuration register */ + +#define RCC_CFGR_USBPRE_BIT 22 +#define RCC_CFGR_PLLXTPRE_BIT 17 +#define RCC_CFGR_PLLSRC_BIT 16 + +#define RCC_CFGR_MCO (0x3 << 24) +#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) +#define RCC_CFGR_PLLMUL (0xF << 18) +#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) +#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) +#define RCC_CFGR_ADCPRE (0x3 << 14) +#define RCC_CFGR_PPRE2 (0x7 << 11) +#define RCC_CFGR_PPRE1 (0x7 << 8) +#define RCC_CFGR_HPRE (0xF << 4) +#define RCC_CFGR_SWS (0x3 << 2) +#define RCC_CFGR_SWS_PLL (0x2 << 2) +#define RCC_CFGR_SWS_HSE (0x1 << 2) +#define RCC_CFGR_SW 0x3 +#define RCC_CFGR_SW_PLL 0x2 +#define RCC_CFGR_SW_HSE 0x1 + +/* Clock interrupt register */ + +#define RCC_CIR_CSSC_BIT 23 +#define RCC_CIR_PLLRDYC_BIT 20 +#define RCC_CIR_HSERDYC_BIT 19 +#define RCC_CIR_HSIRDYC_BIT 18 +#define RCC_CIR_LSERDYC_BIT 17 +#define RCC_CIR_LSIRDYC_BIT 16 +#define RCC_CIR_PLLRDYIE_BIT 12 +#define RCC_CIR_HSERDYIE_BIT 11 +#define RCC_CIR_HSIRDYIE_BIT 10 +#define RCC_CIR_LSERDYIE_BIT 9 +#define RCC_CIR_LSIRDYIE_BIT 8 +#define RCC_CIR_CSSF_BIT 7 +#define RCC_CIR_PLLRDYF_BIT 4 +#define RCC_CIR_HSERDYF_BIT 3 +#define RCC_CIR_HSIRDYF_BIT 2 +#define RCC_CIR_LSERDYF_BIT 1 +#define RCC_CIR_LSIRDYF_BIT 0 + +#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) +#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) +#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) +#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) +#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) +#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) +#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) +#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) +#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) +#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) +#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) +#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) +#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) +#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) +#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) +#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) +#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM11RST_BIT 21 +#define RCC_APB2RSTR_TIM10RST_BIT 20 +#define RCC_APB2RSTR_TIM9RST_BIT 19 +#define RCC_APB2RSTR_ADC3RST_BIT 15 +#define RCC_APB2RSTR_USART1RST_BIT 14 +#define RCC_APB2RSTR_TIM8RST_BIT 13 +#define RCC_APB2RSTR_SPI1RST_BIT 12 +#define RCC_APB2RSTR_TIM1RST_BIT 11 +#define RCC_APB2RSTR_ADC2RST_BIT 10 +#define RCC_APB2RSTR_ADC1RST_BIT 9 +#define RCC_APB2RSTR_IOPGRST_BIT 8 +#define RCC_APB2RSTR_IOPFRST_BIT 7 +#define RCC_APB2RSTR_IOPERST_BIT 6 +#define RCC_APB2RSTR_IOPDRST_BIT 5 +#define RCC_APB2RSTR_IOPCRST_BIT 4 +#define RCC_APB2RSTR_IOPBRST_BIT 3 +#define RCC_APB2RSTR_IOPARST_BIT 2 +#define RCC_APB2RSTR_AFIORST_BIT 0 + +#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) +#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) +#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) +#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) +#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) +#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) +#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) +#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) +#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) +#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) +#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) +#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) +#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) +#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) +#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) +#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) +#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) +#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) + +/* APB1 peripheral reset register */ + +#define RCC_APB1RSTR_DACRST_BIT 29 +#define RCC_APB1RSTR_PWRRST_BIT 28 +#define RCC_APB1RSTR_BKPRST_BIT 27 +#define RCC_APB1RSTR_CANRST_BIT 25 +#define RCC_APB1RSTR_USBRST_BIT 23 +#define RCC_APB1RSTR_I2C2RST_BIT 22 +#define RCC_APB1RSTR_I2C1RST_BIT 21 +#define RCC_APB1RSTR_UART5RST_BIT 20 +#define RCC_APB1RSTR_UART4RST_BIT 19 +#define RCC_APB1RSTR_USART3RST_BIT 18 +#define RCC_APB1RSTR_USART2RST_BIT 17 +#define RCC_APB1RSTR_SPI3RST_BIT 15 +#define RCC_APB1RSTR_SPI2RST_BIT 14 +#define RCC_APB1RSTR_WWDRST_BIT 11 +#define RCC_APB1RSTR_TIM14RST_BIT 8 +#define RCC_APB1RSTR_TIM13RST_BIT 7 +#define RCC_APB1RSTR_TIM12RST_BIT 6 +#define RCC_APB1RSTR_TIM7RST_BIT 5 +#define RCC_APB1RSTR_TIM6RST_BIT 4 +#define RCC_APB1RSTR_TIM5RST_BIT 3 +#define RCC_APB1RSTR_TIM4RST_BIT 2 +#define RCC_APB1RSTR_TIM3RST_BIT 1 +#define RCC_APB1RSTR_TIM2RST_BIT 0 + +#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) +#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) +#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) +#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) +#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) +#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) +#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) +#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) +#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) +#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) +#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) +#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) +#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) +#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) +#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) +#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) +#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) +#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) +#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) +#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) +#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) +#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) +#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) + +/* AHB peripheral clock enable register */ + +#define RCC_AHBENR_SDIOEN_BIT 10 +#define RCC_AHBENR_FSMCEN_BIT 8 +#define RCC_AHBENR_CRCEN_BIT 7 +#define RCC_AHBENR_FLITFEN_BIT 4 +#define RCC_AHBENR_SRAMEN_BIT 2 +#define RCC_AHBENR_DMA2EN_BIT 1 +#define RCC_AHBENR_DMA1EN_BIT 0 + +#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) +#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) +#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) +#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) +#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) +#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) +#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) + +/* APB2 peripheral clock enable register */ + +#define RCC_APB2ENR_TIM11EN_BIT 21 +#define RCC_APB2ENR_TIM10EN_BIT 20 +#define RCC_APB2ENR_TIM9EN_BIT 19 +#define RCC_APB2ENR_ADC3EN_BIT 15 +#define RCC_APB2ENR_USART1EN_BIT 14 +#define RCC_APB2ENR_TIM8EN_BIT 13 +#define RCC_APB2ENR_SPI1EN_BIT 12 +#define RCC_APB2ENR_TIM1EN_BIT 11 +#define RCC_APB2ENR_ADC2EN_BIT 10 +#define RCC_APB2ENR_ADC1EN_BIT 9 +#define RCC_APB2ENR_IOPGEN_BIT 8 +#define RCC_APB2ENR_IOPFEN_BIT 7 +#define RCC_APB2ENR_IOPEEN_BIT 6 +#define RCC_APB2ENR_IOPDEN_BIT 5 +#define RCC_APB2ENR_IOPCEN_BIT 4 +#define RCC_APB2ENR_IOPBEN_BIT 3 +#define RCC_APB2ENR_IOPAEN_BIT 2 +#define RCC_APB2ENR_AFIOEN_BIT 0 + +#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) +#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) +#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) +#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) +#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) +#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) +#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) +#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) +#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) +#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) +#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) +#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) +#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) +#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) +#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) +#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) +#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) +#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) + +/* APB1 peripheral clock enable register */ + +#define RCC_APB1ENR_DACEN_BIT 29 +#define RCC_APB1ENR_PWREN_BIT 28 +#define RCC_APB1ENR_BKPEN_BIT 27 +#define RCC_APB1ENR_CANEN_BIT 25 +#define RCC_APB1ENR_USBEN_BIT 23 +#define RCC_APB1ENR_I2C2EN_BIT 22 +#define RCC_APB1ENR_I2C1EN_BIT 21 +#define RCC_APB1ENR_UART5EN_BIT 20 +#define RCC_APB1ENR_UART4EN_BIT 19 +#define RCC_APB1ENR_USART3EN_BIT 18 +#define RCC_APB1ENR_USART2EN_BIT 17 +#define RCC_APB1ENR_SPI3EN_BIT 15 +#define RCC_APB1ENR_SPI2EN_BIT 14 +#define RCC_APB1ENR_WWDEN_BIT 11 +#define RCC_APB1ENR_TIM14EN_BIT 8 +#define RCC_APB1ENR_TIM13EN_BIT 7 +#define RCC_APB1ENR_TIM12EN_BIT 6 +#define RCC_APB1ENR_TIM7EN_BIT 5 +#define RCC_APB1ENR_TIM6EN_BIT 4 +#define RCC_APB1ENR_TIM5EN_BIT 3 +#define RCC_APB1ENR_TIM4EN_BIT 2 +#define RCC_APB1ENR_TIM3EN_BIT 1 +#define RCC_APB1ENR_TIM2EN_BIT 0 + +#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) +#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) +#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) +#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) +#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) +#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) +#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) +#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) +#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) +#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) +#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) +#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) +#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) +#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) +#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) +#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) +#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) +#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) +#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) +#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) +#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) +#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) +#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) + +/* Backup domain control register */ + +#define RCC_BDCR_BDRST_BIT 16 +#define RCC_BDCR_RTCEN_BIT 15 +#define RCC_BDCR_LSEBYP_BIT 2 +#define RCC_BDCR_LSERDY_BIT 1 +#define RCC_BDCR_LSEON_BIT 0 + +#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) +#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) +#define RCC_BDCR_RTCSEL (0x3 << 8) +#define RCC_BDCR_RTCSEL_NONE (0x0 << 8) +#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) +#define RCC_BDCR_RTCSEL_HSE (0x3 << 8) +#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) +#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) +#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) + +/* Control/status register */ + +#define RCC_CSR_LPWRRSTF_BIT 31 +#define RCC_CSR_WWDGRSTF_BIT 30 +#define RCC_CSR_IWDGRSTF_BIT 29 +#define RCC_CSR_SFTRSTF_BIT 28 +#define RCC_CSR_PORRSTF_BIT 27 +#define RCC_CSR_PINRSTF_BIT 26 +#define RCC_CSR_RMVF_BIT 24 +#define RCC_CSR_LSIRDY_BIT 1 +#define RCC_CSR_LSION_BIT 0 + +#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) +#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) +#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) +#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) +#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) +#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) +#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) +#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) +#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) + +/* + * Other types + */ + +/** + * @brief Identifies bus and clock line for a peripheral. + * + * Also generally useful as a unique identifier for that peripheral + * (or its corresponding device struct). + */ +typedef enum rcc_clk_id { + RCC_GPIOA, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, + RCC_AFIO, + RCC_ADC1, + RCC_ADC2, + RCC_ADC3, + RCC_USART1, + RCC_USART2, + RCC_USART3, + RCC_TIMER1, + RCC_TIMER2, + RCC_TIMER3, + RCC_TIMER4, + RCC_SPI1, + RCC_SPI2, + RCC_DMA1, + RCC_PWR, + RCC_BKP, + RCC_I2C1, + RCC_I2C2, + RCC_CRC, + RCC_FLITF, + RCC_SRAM, + RCC_USB, +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + RCC_GPIOE, + RCC_GPIOF, + RCC_GPIOG, + RCC_UART4, + RCC_UART5, + RCC_TIMER5, + RCC_TIMER6, + RCC_TIMER7, + RCC_TIMER8, + RCC_FSMC, + RCC_DAC, + RCC_DMA2, + RCC_SDIO, + RCC_SPI3, +#endif +#ifdef STM32_XL_DENSITY + RCC_TIMER9, + RCC_TIMER10, + RCC_TIMER11, + RCC_TIMER12, + RCC_TIMER13, + RCC_TIMER14, +#endif +} rcc_clk_id; + +/** + * PLL multipliers + * @see rcc_clk_init() + */ +typedef enum rcc_pll_multiplier { + RCC_PLLMUL_2 = (0x0 << 18), + RCC_PLLMUL_3 = (0x1 << 18), + RCC_PLLMUL_4 = (0x2 << 18), + RCC_PLLMUL_5 = (0x3 << 18), + RCC_PLLMUL_6 = (0x4 << 18), + RCC_PLLMUL_7 = (0x5 << 18), + RCC_PLLMUL_8 = (0x6 << 18), + RCC_PLLMUL_9 = (0x7 << 18), + RCC_PLLMUL_10 = (0x8 << 18), + RCC_PLLMUL_11 = (0x9 << 18), + RCC_PLLMUL_12 = (0xA << 18), + RCC_PLLMUL_13 = (0xB << 18), + RCC_PLLMUL_14 = (0xC << 18), + RCC_PLLMUL_15 = (0xD << 18), + RCC_PLLMUL_16 = (0xE << 18), +} rcc_pll_multiplier; + +/** + * PLL entry clock source + * @see rcc_clk_init() + */ +typedef enum rcc_pllsrc { + RCC_PLLSRC_HSE = (0x1 << 16), + RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) +} rcc_pllsrc; + +typedef enum rcc_clk_domain { + RCC_APB1, + RCC_APB2, + RCC_AHB +} rcc_clk_domain; + +/** + * Prescaler identifiers + * @see rcc_set_prescaler() + */ +typedef enum rcc_prescaler { + RCC_PRESCALER_AHB, + RCC_PRESCALER_APB1, + RCC_PRESCALER_APB2, + RCC_PRESCALER_USB, + RCC_PRESCALER_ADC +} rcc_prescaler; + +/** + * ADC prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_adc_divider { + RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14, + RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14, + RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14, + RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14, +} rcc_adc_divider; + +/** + * APB1 prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_apb1_divider { + RCC_APB1_HCLK_DIV_1 = 0x0 << 8, + RCC_APB1_HCLK_DIV_2 = 0x4 << 8, + RCC_APB1_HCLK_DIV_4 = 0x5 << 8, + RCC_APB1_HCLK_DIV_8 = 0x6 << 8, + RCC_APB1_HCLK_DIV_16 = 0x7 << 8, +} rcc_apb1_divider; + +/** + * APB2 prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_apb2_divider { + RCC_APB2_HCLK_DIV_1 = 0x0 << 11, + RCC_APB2_HCLK_DIV_2 = 0x4 << 11, + RCC_APB2_HCLK_DIV_4 = 0x5 << 11, + RCC_APB2_HCLK_DIV_8 = 0x6 << 11, + RCC_APB2_HCLK_DIV_16 = 0x7 << 11, +} rcc_apb2_divider; + +/** + * AHB prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_ahb_divider { + RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4, + RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4, + RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4, + RCC_AHB_SYSCLK_DIV_8 = 0xA << 4, + RCC_AHB_SYSCLK_DIV_16 = 0xB << 4, + RCC_AHB_SYSCLK_DIV_32 = 0xC << 4, + RCC_AHB_SYSCLK_DIV_64 = 0xD << 4, + RCC_AHB_SYSCLK_DIV_128 = 0xD << 4, + RCC_AHB_SYSCLK_DIV_256 = 0xE << 4, + RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, +} rcc_ahb_divider; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c new file mode 100644 index 0000000..c40d52f --- /dev/null +++ b/libmaple/stm32f1/rcc.c @@ -0,0 +1,205 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/rcc.c + * @brief STM32F1 RCC routines. + */ + +#include +#include +#include + +struct rcc_dev_info { + const rcc_clk_domain clk_domain; + const uint8 line_num; +}; + +#define APB1 RCC_APB1 +#define APB2 RCC_APB2 +#define AHB RCC_AHB + +/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset + * register bit numbers. */ +static const struct rcc_dev_info rcc_dev_table[] = { + [RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 }, + [RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 }, + [RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 }, + [RCC_GPIOD] = { .clk_domain = APB2, .line_num = 5 }, + [RCC_AFIO] = { .clk_domain = APB2, .line_num = 0 }, + [RCC_ADC1] = { .clk_domain = APB2, .line_num = 9 }, + [RCC_ADC2] = { .clk_domain = APB2, .line_num = 10 }, + [RCC_ADC3] = { .clk_domain = APB2, .line_num = 15 }, + [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 }, + [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 }, + [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 }, + [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 }, + [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 }, + [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 }, + [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 }, + [RCC_SPI1] = { .clk_domain = APB2, .line_num = 12 }, + [RCC_SPI2] = { .clk_domain = APB1, .line_num = 14 }, + [RCC_DMA1] = { .clk_domain = AHB, .line_num = 0 }, + [RCC_PWR] = { .clk_domain = APB1, .line_num = 28}, + [RCC_BKP] = { .clk_domain = APB1, .line_num = 27}, + [RCC_I2C1] = { .clk_domain = APB1, .line_num = 21 }, + [RCC_I2C2] = { .clk_domain = APB1, .line_num = 22 }, + [RCC_CRC] = { .clk_domain = AHB, .line_num = 6}, + [RCC_FLITF] = { .clk_domain = AHB, .line_num = 4}, + [RCC_SRAM] = { .clk_domain = AHB, .line_num = 2}, + [RCC_USB] = { .clk_domain = APB1, .line_num = 23}, +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + [RCC_GPIOE] = { .clk_domain = APB2, .line_num = 6 }, + [RCC_GPIOF] = { .clk_domain = APB2, .line_num = 7 }, + [RCC_GPIOG] = { .clk_domain = APB2, .line_num = 8 }, + [RCC_UART4] = { .clk_domain = APB1, .line_num = 19 }, + [RCC_UART5] = { .clk_domain = APB1, .line_num = 20 }, + [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 }, + [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 }, + [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 }, + [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 }, + [RCC_FSMC] = { .clk_domain = AHB, .line_num = 8 }, + [RCC_DAC] = { .clk_domain = APB1, .line_num = 29 }, + [RCC_DMA2] = { .clk_domain = AHB, .line_num = 1 }, + [RCC_SDIO] = { .clk_domain = AHB, .line_num = 10 }, + [RCC_SPI3] = { .clk_domain = APB1, .line_num = 15 }, +#endif +#ifdef STM32_XL_DENSITY + [RCC_TIMER9] = { .clk_domain = APB2, .line_num = 19 }, + [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 }, + [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 }, + [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 }, + [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 }, + [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 }, +#endif +}; + +/** + * @brief Initialize the clock control system. Initializes the system + * clock source to use the PLL driven by an external oscillator + * @param sysclk_src system clock source, must be PLL + * @param pll_src pll clock source, must be HSE + * @param pll_mul pll multiplier + */ +void rcc_clk_init(rcc_sysclk_src sysclk_src, + rcc_pllsrc pll_src, + rcc_pll_multiplier pll_mul) { + uint32 cfgr = 0; + uint32 cr; + + /* Assume that we're going to clock the chip off the PLL, fed by + * the HSE */ + ASSERT(sysclk_src == RCC_CLKSRC_PLL && + pll_src == RCC_PLLSRC_HSE); + + RCC_BASE->CFGR = pll_src | pll_mul; + + /* Turn on the HSE */ + cr = RCC_BASE->CR; + cr |= RCC_CR_HSEON; + RCC_BASE->CR = cr; + while (!(RCC_BASE->CR & RCC_CR_HSERDY)) + ; + + /* Now the PLL */ + cr |= RCC_CR_PLLON; + RCC_BASE->CR = cr; + while (!(RCC_BASE->CR & RCC_CR_PLLRDY)) + ; + + /* Finally, let's switch over to the PLL */ + cfgr &= ~RCC_CFGR_SW; + cfgr |= RCC_CFGR_SW_PLL; + RCC_BASE->CFGR = cfgr; + while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) + ; +} + +/** + * @brief Turn on the clock line on a peripheral + * @param id Clock ID of the peripheral to turn on. + */ +void rcc_clk_enable(rcc_clk_id id) { + static const __io uint32* enable_regs[] = { + [APB1] = &RCC_BASE->APB1ENR, + [APB2] = &RCC_BASE->APB2ENR, + [AHB] = &RCC_BASE->AHBENR, + }; + + rcc_clk_domain clk_domain = rcc_dev_clk(id); + __io uint32* enr = (__io uint32*)enable_regs[clk_domain]; + uint8 lnum = rcc_dev_table[id].line_num; + + bb_peri_set_bit(enr, lnum, 1); +} + +/** + * @brief Reset a peripheral. + * @param id Clock ID of the peripheral to reset. + */ +void rcc_reset_dev(rcc_clk_id id) { + static const __io uint32* reset_regs[] = { + [APB1] = &RCC_BASE->APB1RSTR, + [APB2] = &RCC_BASE->APB2RSTR, + }; + + rcc_clk_domain clk_domain = rcc_dev_clk(id); + __io void* addr = (__io void*)reset_regs[clk_domain]; + uint8 lnum = rcc_dev_table[id].line_num; + + bb_peri_set_bit(addr, lnum, 1); + bb_peri_set_bit(addr, lnum, 0); +} + +/** + * @brief Get a peripheral's clock domain + * @param id Clock ID of the peripheral whose clock domain to return + * @return Clock source for the given clock ID + */ +rcc_clk_domain rcc_dev_clk(rcc_clk_id id) { + return rcc_dev_table[id].clk_domain; +} + +/** + * @brief Set the divider on a peripheral prescaler + * @param prescaler prescaler to set + * @param divider prescaler divider + */ +void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { + static const uint32 masks[] = { + [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE, + [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1, + [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2, + [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE, + [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE, + }; + + uint32 cfgr = RCC_BASE->CFGR; + cfgr &= ~masks[prescaler]; + cfgr |= divider; + RCC_BASE->CFGR = cfgr; +} diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 5cadefd..3c87920 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -4,16 +4,23 @@ dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) +# Local flags +CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror + # Local rules and targets sSRCS_$(d) := isrs_performance.S \ vector_table_performance.S +cSRCS_$(d) := rcc.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) +cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -OBJS_$(d) := $(sFILES_$(d):%.S=$(BUILD_PATH)/%.o) +OBJS_$(d) := $(sFILES_$(d):%.S=$(BUILD_PATH)/%.o) \ + $(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) DEPS_$(d) := $(OBJS_$(d):%.o=%.d) $(OBJS_$(d)): TGT_ASFLAGS := +$(OBJS_$(d)): TGT_CFLAGS := $(CFLAGS_$(d)) TGT_BIN += $(OBJS_$(d)) -- cgit v1.2.3 From fa7a177a0cb6c1201912d9fcdfe6d86edffb9d79 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 13:51:55 -0500 Subject: Move Flash support for STM32F1 to libmaple/stm32f1/. This is a backwards-compatible change. The Flash registers on the STM32F2 line are different than on STM32F1. Therefore, move the register map and bit definitions to new libmaple/stm32f1/include/family/flash.h. Move flash_enable_prefetch() from libmaple/flash.c to new libmaple/stm32f1/flash.c. The remaining pieces of libmaple/flash.c use a common subset of the Flash registers, so they're's portable to F2, and that's all we're currently interested in. Signed-off-by: Marti Bolivar --- libmaple/flash.c | 12 +-- libmaple/include/libmaple/flash.h | 84 +------------------- libmaple/stm32f1/flash.c | 41 ++++++++++ libmaple/stm32f1/include/family/flash.h | 135 ++++++++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 2 + 5 files changed, 181 insertions(+), 93 deletions(-) create mode 100644 libmaple/stm32f1/flash.c create mode 100644 libmaple/stm32f1/include/family/flash.h diff --git a/libmaple/flash.c b/libmaple/flash.c index d0e23d0..0ade4cb 100644 --- a/libmaple/flash.c +++ b/libmaple/flash.c @@ -25,20 +25,12 @@ *****************************************************************************/ /** - * @file flash.c + * @file libmaple/flash.c * @brief Flash management functions */ -#include +#include #include -#include - -/** - * @brief Turn on the hardware prefetcher. - */ -void flash_enable_prefetch(void) { - *bb_perip(&FLASH_BASE->ACR, FLASH_ACR_PRFTBE_BIT) = 1; -} /** * @brief Set flash wait states diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index e28ea28..bbe516d 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -37,91 +37,9 @@ extern "C"{ #endif +#include #include -/** Flash register map type */ -typedef struct flash_reg_map { - __io uint32 ACR; /**< Access control register */ - __io uint32 KEYR; /**< Key register */ - __io uint32 OPTKEYR; /**< OPTKEY register */ - __io uint32 SR; /**< Status register */ - __io uint32 CR; /**< Control register */ - __io uint32 AR; /**< Address register */ - __io uint32 OBR; /**< Option byte register */ - __io uint32 WRPR; /**< Write protection register */ -} flash_reg_map; - -/** Flash register map base pointer */ -#define FLASH_BASE ((struct flash_reg_map*)0x40022000) - -/* - * Register bit definitions - */ - -/* Access control register */ - -#define FLASH_ACR_PRFTBS_BIT 5 -#define FLASH_ACR_PRFTBE_BIT 4 -#define FLASH_ACR_HLFCYA_BIT 3 - -#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) -#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) -#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) -#define FLASH_ACR_LATENCY 0x7 - -/* Status register */ - -#define FLASH_SR_EOP_BIT 5 -#define FLASH_SR_WRPRTERR_BIT 4 -#define FLASH_SR_PGERR_BIT 2 -#define FLASH_SR_BSY_BIT 0 - -#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) -#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) -#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) -#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) - -/* Control register */ - -#define FLASH_CR_EOPIE_BIT 12 -#define FLASH_CR_ERRIE_BIT 10 -#define FLASH_CR_OPTWRE_BIT 9 -#define FLASH_CR_LOCK_BIT 7 -#define FLASH_CR_STRT_BIT 6 -#define FLASH_CR_OPTER_BIT 5 -#define FLASH_CR_OPTPG_BIT 4 -#define FLASH_CR_MER_BIT 2 -#define FLASH_CR_PER_BIT 1 -#define FLASH_CR_PG_BIT 0 - -#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) -#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) -#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) -#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) -#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) -#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) -#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) -#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) -#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) -#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) - -/* Option byte register */ - -#define FLASH_OBR_nRST_STDBY_BIT 4 -#define FLASH_OBR_nRST_STOP_BIT 3 -#define FLASH_OBR_WDG_SW_BIT 2 -#define FLASH_OBR_RDPRT_BIT 1 -#define FLASH_OBR_OPTERR_BIT 0 - -#define FLASH_OBR_DATA1 (0xFF << 18) -#define FLASH_OBR_DATA0 (0xFF << 10) -#define FLASH_OBR_USER 0x3FF -#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) -#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) -#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) -#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) -#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) - /* * Setup routines */ diff --git a/libmaple/stm32f1/flash.c b/libmaple/stm32f1/flash.c new file mode 100644 index 0000000..73fc93f --- /dev/null +++ b/libmaple/stm32f1/flash.c @@ -0,0 +1,41 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/flash.c + * @brief Flash management functions + */ + +#include +#include + +/** + * @brief Turn on the hardware prefetcher. + */ +void flash_enable_prefetch(void) { + *bb_perip(&FLASH_BASE->ACR, FLASH_ACR_PRFTBE_BIT) = 1; +} diff --git a/libmaple/stm32f1/include/family/flash.h b/libmaple/stm32f1/include/family/flash.h new file mode 100644 index 0000000..aedb326 --- /dev/null +++ b/libmaple/stm32f1/include/family/flash.h @@ -0,0 +1,135 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/flash.h + * @brief STM32F1 Flash header. + * + * Provides register map, base pointer, and register bit definitions + * for the Flash controller on the STM32F1 line. + */ + +#ifndef _LIBMAPLE_STM32F1_FLASH_H_ +#define _LIBMAPLE_STM32F1_FLASH_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register map + */ + +/** Flash register map type */ +typedef struct flash_reg_map { + __io uint32 ACR; /**< Access control register */ + __io uint32 KEYR; /**< Key register */ + __io uint32 OPTKEYR; /**< OPTKEY register */ + __io uint32 SR; /**< Status register */ + __io uint32 CR; /**< Control register */ + __io uint32 AR; /**< Address register */ + __io uint32 OBR; /**< Option byte register */ + __io uint32 WRPR; /**< Write protection register */ +} flash_reg_map; + +/** Flash register map base pointer */ +#define FLASH_BASE ((struct flash_reg_map*)0x40022000) + +/* + * Register bit definitions + */ + +/* Access control register */ + +#define FLASH_ACR_PRFTBS_BIT 5 +#define FLASH_ACR_PRFTBE_BIT 4 +#define FLASH_ACR_HLFCYA_BIT 3 + +#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) +#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) +#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) +#define FLASH_ACR_LATENCY 0x7 + +/* Status register */ + +#define FLASH_SR_EOP_BIT 5 +#define FLASH_SR_WRPRTERR_BIT 4 +#define FLASH_SR_PGERR_BIT 2 +#define FLASH_SR_BSY_BIT 0 + +#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) +#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) +#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) +#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) + +/* Control register */ + +#define FLASH_CR_EOPIE_BIT 12 +#define FLASH_CR_ERRIE_BIT 10 +#define FLASH_CR_OPTWRE_BIT 9 +#define FLASH_CR_LOCK_BIT 7 +#define FLASH_CR_STRT_BIT 6 +#define FLASH_CR_OPTER_BIT 5 +#define FLASH_CR_OPTPG_BIT 4 +#define FLASH_CR_MER_BIT 2 +#define FLASH_CR_PER_BIT 1 +#define FLASH_CR_PG_BIT 0 + +#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) +#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) +#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) +#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) +#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) +#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) +#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) +#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) +#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) +#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) + +/* Option byte register */ + +#define FLASH_OBR_nRST_STDBY_BIT 4 +#define FLASH_OBR_nRST_STOP_BIT 3 +#define FLASH_OBR_WDG_SW_BIT 2 +#define FLASH_OBR_RDPRT_BIT 1 +#define FLASH_OBR_OPTERR_BIT 0 + +#define FLASH_OBR_DATA1 (0xFF << 18) +#define FLASH_OBR_DATA0 (0xFF << 10) +#define FLASH_OBR_USER 0x3FF +#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) +#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) +#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) +#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) +#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 3c87920..2bdc423 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -10,7 +10,9 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets sSRCS_$(d) := isrs_performance.S \ vector_table_performance.S + cSRCS_$(d) := rcc.c +cSRCS_$(d) += flash.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From a4ae6eea2fe541d4e457574d589b441b61fd7d9b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 18:12:49 -0500 Subject: Move NVIC support for STM32F1 to libmaple/stm32f1. Backwards-compatible. Only the headers need to change. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/nvic.h | 122 +++-------------------------- libmaple/stm32f1/include/family/nvic.h | 139 +++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+), 111 deletions(-) create mode 100644 libmaple/stm32f1/include/family/nvic.h diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h index d631eeb..afcb769 100644 --- a/libmaple/include/libmaple/nvic.h +++ b/libmaple/include/libmaple/nvic.h @@ -26,7 +26,7 @@ /** * @file nvic.h - * @brief Nested vector interrupt controller support. + * @brief Nested vectored interrupt controller support. * * Basic usage: * @@ -73,109 +73,20 @@ typedef struct nvic_reg_map { /** NVIC register map base pointer. */ #define NVIC_BASE ((struct nvic_reg_map*)0xE000E100) -/** - * @brief Interrupt vector table interrupt numbers. - * - * Each positive-valued enumerator is the position of the - * corresponding interrupt in the vector table. Negative-valued - * enumerators correspond to interrupts controlled by the system - * handler block. - * - * @see scb.h - */ -typedef enum nvic_irq_num { - NVIC_NMI = -14, /**< Non-maskable interrupt */ - NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ - NVIC_MEM_MANAGE = -12, /**< Memory management */ - NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory - access fault. */ - NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction or - illegal state. */ - NVIC_SVC = -5, /**< System service call via SWI insruction */ - NVIC_DEBUG_MON = -4, /**< Debug monitor */ - NVIC_PEND_SVC = -2, /**< Pendable request for system service */ - NVIC_SYSTICK = -1, /**< System tick timer */ - NVIC_WWDG = 0, /**< Window watchdog interrupt */ - NVIC_PVD = 1, /**< PVD through EXTI line detection */ - NVIC_TAMPER = 2, /**< Tamper */ - NVIC_RTC = 3, /**< Real-time clock */ - NVIC_FLASH = 4, /**< Flash */ - NVIC_RCC = 5, /**< Reset and clock control */ - NVIC_EXTI0 = 6, /**< EXTI line 0 */ - NVIC_EXTI1 = 7, /**< EXTI line 1 */ - NVIC_EXTI2 = 8, /**< EXTI line 2 */ - NVIC_EXTI3 = 9, /**< EXTI line 3 */ - NVIC_EXTI4 = 10, /**< EXTI line 4 */ - NVIC_DMA_CH1 = 11, /**< DMA1 channel 1 */ - NVIC_DMA_CH2 = 12, /**< DMA1 channel 2 */ - NVIC_DMA_CH3 = 13, /**< DMA1 channel 3 */ - NVIC_DMA_CH4 = 14, /**< DMA1 channel 4 */ - NVIC_DMA_CH5 = 15, /**< DMA1 channel 5 */ - NVIC_DMA_CH6 = 16, /**< DMA1 channel 6 */ - NVIC_DMA_CH7 = 17, /**< DMA1 channel 7 */ - NVIC_ADC_1_2 = 18, /**< ADC1 and ADC2 */ - NVIC_USB_HP_CAN_TX = 19, /**< USB high priority or CAN TX */ - NVIC_USB_LP_CAN_RX0 = 20, /**< USB low priority or CAN RX0 */ - NVIC_CAN_RX1 = 21, /**< CAN RX1 */ - NVIC_CAN_SCE = 22, /**< CAN SCE */ - NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ - NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ - NVIC_TIMER1_UP = 25, /**< Timer 1 update */ - NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ - NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ - NVIC_TIMER2 = 28, /**< Timer 2 */ - NVIC_TIMER3 = 29, /**< Timer 3 */ - NVIC_TIMER4 = 30, /**< Timer 4 */ - NVIC_I2C1_EV = 31, /**< I2C1 event */ - NVIC_I2C1_ER = 32, /**< I2C1 error */ - NVIC_I2C2_EV = 33, /**< I2C2 event */ - NVIC_I2C2_ER = 34, /**< I2C2 error */ - NVIC_SPI1 = 35, /**< SPI1 */ - NVIC_SPI2 = 36, /**< SPI2 */ - NVIC_USART1 = 37, /**< USART1 */ - NVIC_USART2 = 38, /**< USART2 */ - NVIC_USART3 = 39, /**< USART3 */ - NVIC_EXTI_15_10 = 40, /**< EXTI line [15:10] */ - NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ - NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through - EXTI line */ - NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ - NVIC_TIMER8_UP = 44, /**< Timer 8 update */ - NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ - NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ -#ifdef STM32_HIGH_DENSITY - NVIC_ADC3 = 47, /**< ADC3 */ - NVIC_FSMC = 48, /**< FSMC */ - NVIC_SDIO = 49, /**< SDIO */ - NVIC_TIMER5 = 50, /**< Timer 5 */ - NVIC_SPI3 = 51, /**< SPI3 */ - NVIC_UART4 = 52, /**< UART4 */ - NVIC_UART5 = 53, /**< UART5 */ - NVIC_TIMER6 = 54, /**< Timer 6 */ - NVIC_TIMER7 = 55, /**< Timer 7 */ - NVIC_DMA2_CH1 = 56, /**< DMA2 channel 1 */ - NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ - NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ - NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ -#endif -} nvic_irq_num; - /* - * Initialises the interrupt controller and sets all interrupts to the - * lowest priority. + * Note: The family header must define enum nvic_irq_num, which gives + * descriptive names to the interrupts and exceptions from NMI (-14) + * to the largest interrupt available in the family, where the value + * for nonnegative enumerators corresponds to its position in the + * vector table. * - * For stand-alone products, the base address is normally the start of - * flash (0x08000000). - * - * @param vector_table_address base address of the vector table + * It also must define a static inline nvic_irq_disable_all(), which + * writes 0xFFFFFFFF to all ICE registers available in the family. */ -void nvic_init(uint32 vector_table_address, uint32 offset); +#include -/** - * Sets the base address of the vector table. - */ +void nvic_init(uint32 address, uint32 offset); void nvic_set_vector_table(uint32 address, uint32 offset); - void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority); void nvic_sys_reset(); @@ -221,18 +132,7 @@ static inline void nvic_irq_disable(nvic_irq_num irq_num) { * Calling this function is significantly faster than calling * nvic_irq_disable() in a loop. */ -static inline void nvic_irq_disable_all(void) { - /* Note: This only works up to XL density. The fix for - * connectivity line is: - * - * NVIC_BASE->ICER[2] = 0xF; - * - * We don't support connectivity line devices (yet), so leave it - * alone for now. - */ - NVIC_BASE->ICER[0] = 0xFFFFFFFF; - NVIC_BASE->ICER[1] = 0xFFFFFFFF; -} +static inline void nvic_irq_disable_all(void); #ifdef __cplusplus } diff --git a/libmaple/stm32f1/include/family/nvic.h b/libmaple/stm32f1/include/family/nvic.h new file mode 100644 index 0000000..69fd945 --- /dev/null +++ b/libmaple/stm32f1/include/family/nvic.h @@ -0,0 +1,139 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/nvic.h + * @brief STM32F1 Nested Vectored Interrupt Controller (NVIC) support. + */ + +#ifndef _LIBMAPLE_STM32F1_NVIC_H_ +#define _LIBMAPLE_STM32F1_NVIC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * @brief Interrupt vector table interrupt numbers. + * @see + */ +typedef enum nvic_irq_num { + NVIC_NMI = -14, /**< Non-maskable interrupt */ + NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ + NVIC_MEM_MANAGE = -12, /**< Memory management */ + NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory + access fault. */ + NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction or + illegal state. */ + NVIC_SVC = -5, /**< System service call via SWI insruction */ + NVIC_DEBUG_MON = -4, /**< Debug monitor */ + NVIC_PEND_SVC = -2, /**< Pendable request for system service */ + NVIC_SYSTICK = -1, /**< System tick timer */ + NVIC_WWDG = 0, /**< Window watchdog interrupt */ + NVIC_PVD = 1, /**< PVD through EXTI line detection */ + NVIC_TAMPER = 2, /**< Tamper */ + NVIC_RTC = 3, /**< Real-time clock */ + NVIC_FLASH = 4, /**< Flash */ + NVIC_RCC = 5, /**< Reset and clock control */ + NVIC_EXTI0 = 6, /**< EXTI line 0 */ + NVIC_EXTI1 = 7, /**< EXTI line 1 */ + NVIC_EXTI2 = 8, /**< EXTI line 2 */ + NVIC_EXTI3 = 9, /**< EXTI line 3 */ + NVIC_EXTI4 = 10, /**< EXTI line 4 */ + NVIC_DMA_CH1 = 11, /**< DMA1 channel 1 */ + NVIC_DMA_CH2 = 12, /**< DMA1 channel 2 */ + NVIC_DMA_CH3 = 13, /**< DMA1 channel 3 */ + NVIC_DMA_CH4 = 14, /**< DMA1 channel 4 */ + NVIC_DMA_CH5 = 15, /**< DMA1 channel 5 */ + NVIC_DMA_CH6 = 16, /**< DMA1 channel 6 */ + NVIC_DMA_CH7 = 17, /**< DMA1 channel 7 */ + NVIC_ADC_1_2 = 18, /**< ADC1 and ADC2 */ + NVIC_USB_HP_CAN_TX = 19, /**< USB high priority or CAN TX */ + NVIC_USB_LP_CAN_RX0 = 20, /**< USB low priority or CAN RX0 */ + NVIC_CAN_RX1 = 21, /**< CAN RX1 */ + NVIC_CAN_SCE = 22, /**< CAN SCE */ + NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ + NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ + NVIC_TIMER1_UP = 25, /**< Timer 1 update */ + NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ + NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ + NVIC_TIMER2 = 28, /**< Timer 2 */ + NVIC_TIMER3 = 29, /**< Timer 3 */ + NVIC_TIMER4 = 30, /**< Timer 4 */ + NVIC_I2C1_EV = 31, /**< I2C1 event */ + NVIC_I2C1_ER = 32, /**< I2C1 error */ + NVIC_I2C2_EV = 33, /**< I2C2 event */ + NVIC_I2C2_ER = 34, /**< I2C2 error */ + NVIC_SPI1 = 35, /**< SPI1 */ + NVIC_SPI2 = 36, /**< SPI2 */ + NVIC_USART1 = 37, /**< USART1 */ + NVIC_USART2 = 38, /**< USART2 */ + NVIC_USART3 = 39, /**< USART3 */ + NVIC_EXTI_15_10 = 40, /**< EXTI line [15:10] */ + NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ + NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through + EXTI line */ + NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ + NVIC_TIMER8_UP = 44, /**< Timer 8 update */ + NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ + NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ +#ifdef STM32_HIGH_DENSITY + NVIC_ADC3 = 47, /**< ADC3 */ + NVIC_FSMC = 48, /**< FSMC */ + NVIC_SDIO = 49, /**< SDIO */ + NVIC_TIMER5 = 50, /**< Timer 5 */ + NVIC_SPI3 = 51, /**< SPI3 */ + NVIC_UART4 = 52, /**< UART4 */ + NVIC_UART5 = 53, /**< UART5 */ + NVIC_TIMER6 = 54, /**< Timer 6 */ + NVIC_TIMER7 = 55, /**< Timer 7 */ + NVIC_DMA2_CH1 = 56, /**< DMA2 channel 1 */ + NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ + NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ + NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ +#endif +} nvic_irq_num; + +static inline void nvic_irq_disable_all(void) { + /* Note: This only works up to XL density. The fix for + * connectivity line is: + * + * NVIC_BASE->ICER[2] = 0xF; + * + * We don't support connectivity line devices (yet), so leave it + * alone for now. + */ + NVIC_BASE->ICER[0] = 0xFFFFFFFF; + NVIC_BASE->ICER[1] = 0xFFFFFFFF; +} + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.2.3 From 57a73728b93e297fee80574fc04c4a07ddc325df Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 18:12:57 -0500 Subject: libmaple/nvic.c: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/nvic.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/libmaple/nvic.c b/libmaple/nvic.c index b80751f..e3f79a3 100644 --- a/libmaple/nvic.c +++ b/libmaple/nvic.c @@ -46,7 +46,7 @@ */ void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority) { if (irqn < 0) { - /* This interrupt is in the system handler block */ + /* This interrupt is in the system handler block */ SCB_BASE->SHP[((uint32)irqn & 0xF) - 4] = (priority & 0xF) << 4; } else { NVIC_BASE->IP[irqn] = (priority & 0xF) << 4; @@ -54,16 +54,12 @@ void nvic_irq_set_priority(nvic_irq_num irqn, uint8 priority) { } /** - * @brief Initialize the NVIC - * @param vector_table_address Vector table base address. - * @param offset Offset from vector_table_address. Some restrictions - * apply to the use of nonzero offsets; see ST RM0008 - * and the ARM Cortex M3 Technical Reference Manual. + * @brief Initialize the NVIC, setting interrupts to a default priority. */ -void nvic_init(uint32 vector_table_address, uint32 offset) { +void nvic_init(uint32 address, uint32 offset) { uint32 i; - nvic_set_vector_table(vector_table_address, offset); + nvic_set_vector_table(address, offset); /* * Lower priority level for all peripheral interrupts to lowest @@ -78,10 +74,18 @@ void nvic_init(uint32 vector_table_address, uint32 offset) { } /** - * Reset the vector table address. + * @brief Set the vector table base address. + * + * For stand-alone products, the vector table base address is normally + * the start of Flash (0x08000000). + * + * @param address Vector table base address. + * @param offset Offset from address. Some restrictions apply to the + * use of nonzero offsets; see the ARM Cortex M3 + * Technical Reference Manual. */ -void nvic_set_vector_table(uint32 addr, uint32 offset) { - SCB_BASE->VTOR = addr | (offset & 0x1FFFFF80); +void nvic_set_vector_table(uint32 address, uint32 offset) { + SCB_BASE->VTOR = address | (offset & 0x1FFFFF80); } /** -- cgit v1.2.3 From bb657c68e77a1c597b45c35978e4c833739144e9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 16 Nov 2011 18:49:52 -0500 Subject: Move GPIO support for STM32F1 to libmaple/stm32f1. Make a new family header, libmaple/stm32f1/include/family/gpio.h, and supporting libmaple/stm32f1/gpio.c. Beyond registers and devices, these also include anything mentioning AFIO, which doesn't exist on F2. Update libmaple/stm32f1/rules.mk for new gpio.c. Alter gpio_write_bit() to use dev->regs->BSRR only. BRRs are not present on STM32F2. Signed-off-by: Marti Bolivar --- libmaple/gpio.c | 151 +---------- libmaple/include/libmaple/gpio.h | 450 +------------------------------ libmaple/stm32f1/gpio.c | 184 +++++++++++++ libmaple/stm32f1/include/family/gpio.h | 479 +++++++++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 1 + 5 files changed, 676 insertions(+), 589 deletions(-) create mode 100644 libmaple/stm32f1/gpio.c create mode 100644 libmaple/stm32f1/include/family/gpio.h diff --git a/libmaple/gpio.c b/libmaple/gpio.c index e607595..64b2d54 100644 --- a/libmaple/gpio.c +++ b/libmaple/gpio.c @@ -26,76 +26,14 @@ /** * @file gpio.c - * @brief GPIO initialization routine + * @brief Generic STM32 GPIO support. */ #include #include /* - * GPIO devices - */ - -gpio_dev gpioa = { - .regs = GPIOA_BASE, - .clk_id = RCC_GPIOA, - .exti_port = AFIO_EXTI_PA, -}; -/** GPIO port A device. */ -gpio_dev* const GPIOA = &gpioa; - -gpio_dev gpiob = { - .regs = GPIOB_BASE, - .clk_id = RCC_GPIOB, - .exti_port = AFIO_EXTI_PB, -}; -/** GPIO port B device. */ -gpio_dev* const GPIOB = &gpiob; - -gpio_dev gpioc = { - .regs = GPIOC_BASE, - .clk_id = RCC_GPIOC, - .exti_port = AFIO_EXTI_PC, -}; -/** GPIO port C device. */ -gpio_dev* const GPIOC = &gpioc; - -gpio_dev gpiod = { - .regs = GPIOD_BASE, - .clk_id = RCC_GPIOD, - .exti_port = AFIO_EXTI_PD, -}; -/** GPIO port D device. */ -gpio_dev* const GPIOD = &gpiod; - -#ifdef STM32_HIGH_DENSITY -gpio_dev gpioe = { - .regs = GPIOE_BASE, - .clk_id = RCC_GPIOE, - .exti_port = AFIO_EXTI_PE, -}; -/** GPIO port E device. */ -gpio_dev* const GPIOE = &gpioe; - -gpio_dev gpiof = { - .regs = GPIOF_BASE, - .clk_id = RCC_GPIOF, - .exti_port = AFIO_EXTI_PF, -}; -/** GPIO port F device. */ -gpio_dev* const GPIOF = &gpiof; - -gpio_dev gpiog = { - .regs = GPIOG_BASE, - .clk_id = RCC_GPIOG, - .exti_port = AFIO_EXTI_PG, -}; -/** GPIO port G device. */ -gpio_dev* const GPIOG = &gpiog; -#endif - -/* - * GPIO convenience routines + * GPIO routines */ /** @@ -109,88 +47,3 @@ void gpio_init(gpio_dev *dev) { rcc_clk_enable(dev->clk_id); rcc_reset_dev(dev->clk_id); } - -/** - * Initialize and reset all available GPIO devices. - */ -void gpio_init_all(void) { - gpio_init(GPIOA); - gpio_init(GPIOB); - gpio_init(GPIOC); - gpio_init(GPIOD); -#ifdef STM32_HIGH_DENSITY - gpio_init(GPIOE); - gpio_init(GPIOF); - gpio_init(GPIOG); -#endif -} - -/** - * Set the mode of a GPIO pin. - * - * @param dev GPIO device. - * @param pin Pin on the device whose mode to set, 0--15. - * @param mode General purpose or alternate function mode to set the pin to. - * @see gpio_pin_mode - */ -void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) { - gpio_reg_map *regs = dev->regs; - __io uint32 *cr = ®s->CRL + (pin >> 3); - uint32 shift = (pin & 0x7) * 4; - uint32 tmp = *cr; - - tmp &= ~(0xF << shift); - tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift; - *cr = tmp; - - if (mode == GPIO_INPUT_PD) { - regs->ODR &= ~BIT(pin); - } else if (mode == GPIO_INPUT_PU) { - regs->ODR |= BIT(pin); - } -} - -/* - * AFIO - */ - -/** - * @brief Initialize the AFIO clock, and reset the AFIO registers. - */ -void afio_init(void) { - rcc_clk_enable(RCC_AFIO); - rcc_reset_dev(RCC_AFIO); -} - -#define AFIO_EXTI_SEL_MASK 0xF - -/** - * @brief Select a source input for an external interrupt. - * - * @param exti External interrupt. - * @param gpio_port Port which contains pin to use as source input. - * @see afio_exti_num - * @see afio_exti_port - */ -void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) { - __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4; - uint32 shift = 4 * (exti % 4); - uint32 cr = *exti_cr; - - cr &= ~(AFIO_EXTI_SEL_MASK << shift); - cr |= gpio_port << shift; - *exti_cr = cr; -} - -/** - * @brief Perform an alternate function remap. - * @param remapping Remapping to perform. - */ -void afio_remap(afio_remap_peripheral remapping) { - if (remapping & AFIO_REMAP_USE_MAPR2) { - remapping &= ~AFIO_REMAP_USE_MAPR2; - AFIO_BASE->MAPR2 |= remapping; - } else { - AFIO_BASE->MAPR |= remapping; - } -} diff --git a/libmaple/include/libmaple/gpio.h b/libmaple/include/libmaple/gpio.h index 685e1b1..e821ad4 100644 --- a/libmaple/include/libmaple/gpio.h +++ b/libmaple/include/libmaple/gpio.h @@ -25,10 +25,8 @@ *****************************************************************************/ /** - * @file gpio.h - * - * @brief General purpose I/O (GPIO) and Alternate Function I/O - * (AFIO) prototypes, defines, and inlined access functions. + * @file gpio.h + * @brief General Purpose I/O (GPIO) interace. */ #ifndef _LIBMAPLE_GPIO_H_ @@ -38,129 +36,13 @@ extern "C"{ #endif -#include -#include - /* - * GPIO register maps and devices - */ - -/** GPIO register map type */ -typedef struct gpio_reg_map { - __io uint32 CRL; /**< Port configuration register low */ - __io uint32 CRH; /**< Port configuration register high */ - __io uint32 IDR; /**< Port input data register */ - __io uint32 ODR; /**< Port output data register */ - __io uint32 BSRR; /**< Port bit set/reset register */ - __io uint32 BRR; /**< Port bit reset register */ - __io uint32 LCKR; /**< Port configuration lock register */ -} gpio_reg_map; - -/** - * @brief External interrupt line port selector. - * - * Used to determine which GPIO port to map an external interrupt line - * onto. */ -/* (See AFIO sections, below) */ -typedef enum afio_exti_port { - AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ - AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ - AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ - AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ -#ifdef STM32_HIGH_DENSITY - AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ - AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ - AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ -#endif -} afio_exti_port; - -/** GPIO device type */ -typedef struct gpio_dev { - gpio_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ - afio_exti_port exti_port; /**< AFIO external interrupt port value */ -} gpio_dev; - -extern gpio_dev gpioa; -extern gpio_dev* const GPIOA; -extern gpio_dev gpiob; -extern gpio_dev* const GPIOB; -extern gpio_dev gpioc; -extern gpio_dev* const GPIOC; -extern gpio_dev gpiod; -extern gpio_dev* const GPIOD; -#ifdef STM32_HIGH_DENSITY -extern gpio_dev gpioe; -extern gpio_dev* const GPIOE; -extern gpio_dev gpiof; -extern gpio_dev* const GPIOF; -extern gpio_dev gpiog; -extern gpio_dev* const GPIOG; -#endif - -/** GPIO port A register map base pointer */ -#define GPIOA_BASE ((struct gpio_reg_map*)0x40010800) -/** GPIO port B register map base pointer */ -#define GPIOB_BASE ((struct gpio_reg_map*)0x40010C00) -/** GPIO port C register map base pointer */ -#define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) -/** GPIO port D register map base pointer */ -#define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) -#ifdef STM32_HIGH_DENSITY -/** GPIO port E register map base pointer */ -#define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) -/** GPIO port F register map base pointer */ -#define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) -/** GPIO port G register map base pointer */ -#define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) -#endif - -/* - * GPIO register bit definitions - */ - -/* Control registers, low and high */ - -#define GPIO_CR_CNF (0x3 << 2) -#define GPIO_CR_CNF_INPUT_ANALOG (0x0 << 2) -#define GPIO_CR_CNF_INPUT_FLOATING (0x1 << 2) -#define GPIO_CR_CNF_INPUT_PU_PD (0x2 << 2) -#define GPIO_CR_CNF_OUTPUT_PP (0x0 << 2) -#define GPIO_CR_CNF_OUTPUT_OD (0x1 << 2) -#define GPIO_CR_CNF_AF_OUTPUT_PP (0x2 << 2) -#define GPIO_CR_CNF_AF_OUTPUT_OD (0x3 << 2) -#define GPIO_CR_MODE 0x3 -#define GPIO_CR_MODE_INPUT 0x0 -#define GPIO_CR_MODE_OUTPUT_10MHZ 0x1 -#define GPIO_CR_MODE_OUTPUT_2MHZ 0x2 -#define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 - -/** - * @brief GPIO Pin modes. - * - * These only allow for 50MHZ max output speeds; if you want slower, - * use direct register access. + * Note: Family header must define: + * - struct gpio_dev (and declare extern pointers to family-provided ones) + * - enum gpio_pin_mode (TODO think hard on this) */ -typedef enum gpio_pin_mode { - GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ - GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ - GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output push-pull. */ - GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output open drain. */ - GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | - GPIO_CR_MODE_INPUT), /**< Analog input. */ - GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | - GPIO_CR_MODE_INPUT), /**< Input floating. */ - GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | - GPIO_CR_MODE_INPUT), /**< Input pull-down. */ - GPIO_INPUT_PU /**< Input pull-up. */ - /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ -} gpio_pin_mode; +#include +#include /* * GPIO Convenience routines @@ -168,16 +50,9 @@ typedef enum gpio_pin_mode { void gpio_init(gpio_dev *dev); void gpio_init_all(void); +/* TODO deprecate this? We should probably take a flags argument. */ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode); -/** - * @brief Get a GPIO port's corresponding afio_exti_port. - * @param dev GPIO device whose afio_exti_port to return. - */ -static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { - return dev->exti_port; -} - /** * Set or reset a GPIO pin. * @@ -188,11 +63,8 @@ static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { * @param val If true, set the pin. If false, reset the pin. */ static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) { - if (val) { - dev->regs->BSRR = BIT(pin); - } else { - dev->regs->BRR = BIT(pin); - } + val = !!val; + dev->regs->BSRR = BIT(pin) << (16 * val); } /** @@ -217,308 +89,6 @@ static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) { dev->regs->ODR = dev->regs->ODR ^ BIT(pin); } -/* - * AFIO register map - */ - -/** AFIO register map */ -typedef struct afio_reg_map { - __io uint32 EVCR; /**< Event control register. */ - __io uint32 MAPR; /**< AF remap and debug I/O configuration - register. */ - __io uint32 EXTICR1; /**< External interrupt configuration - register 1. */ - __io uint32 EXTICR2; /**< External interrupt configuration - register 2. */ - __io uint32 EXTICR3; /**< External interrupt configuration - register 3. */ - __io uint32 EXTICR4; /**< External interrupt configuration - register 4. */ - __io uint32 MAPR2; /**< AF remap and debug I/O configuration - register 2. */ -} afio_reg_map; - -/** AFIO register map base pointer. */ -#define AFIO_BASE ((struct afio_reg_map *)0x40010000) - -/* - * AFIO register bit definitions - */ - -/* Event control register */ - -#define AFIO_EVCR_EVOE (0x1 << 7) -#define AFIO_EVCR_PORT_PA (0x0 << 4) -#define AFIO_EVCR_PORT_PB (0x1 << 4) -#define AFIO_EVCR_PORT_PC (0x2 << 4) -#define AFIO_EVCR_PORT_PD (0x3 << 4) -#define AFIO_EVCR_PORT_PE (0x4 << 4) -#define AFIO_EVCR_PIN_0 0x0 -#define AFIO_EVCR_PIN_1 0x1 -#define AFIO_EVCR_PIN_2 0x2 -#define AFIO_EVCR_PIN_3 0x3 -#define AFIO_EVCR_PIN_4 0x4 -#define AFIO_EVCR_PIN_5 0x5 -#define AFIO_EVCR_PIN_6 0x6 -#define AFIO_EVCR_PIN_7 0x7 -#define AFIO_EVCR_PIN_8 0x8 -#define AFIO_EVCR_PIN_9 0x9 -#define AFIO_EVCR_PIN_10 0xA -#define AFIO_EVCR_PIN_11 0xB -#define AFIO_EVCR_PIN_12 0xC -#define AFIO_EVCR_PIN_13 0xD -#define AFIO_EVCR_PIN_14 0xE -#define AFIO_EVCR_PIN_15 0xF - -/* AF remap and debug I/O configuration register */ - -#define AFIO_MAPR_SWJ_CFG (0x7 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) -#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) -#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) -#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) -#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) -#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) -#define AFIO_MAPR_PD01_REMAP BIT(15) -#define AFIO_MAPR_CAN_REMAP (0x3 << 13) -#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) -#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) -#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) -#define AFIO_MAPR_TIM4_REMAP BIT(12) -#define AFIO_MAPR_TIM3_REMAP (0x3 << 10) -#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) -#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) -#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10) -#define AFIO_MAPR_TIM2_REMAP (0x3 << 8) -#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8) -#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8) -#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8) -#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8) -#define AFIO_MAPR_TIM1_REMAP (0x3 << 6) -#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6) -#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6) -#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6) -#define AFIO_MAPR_USART3_REMAP (0x3 << 4) -#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) -#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) -#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) -#define AFIO_MAPR_USART2_REMAP BIT(3) -#define AFIO_MAPR_USART1_REMAP BIT(2) -#define AFIO_MAPR_I2C1_REMAP BIT(1) -#define AFIO_MAPR_SPI1_REMAP BIT(0) - -/* External interrupt configuration register 1 */ - -#define AFIO_EXTICR1_EXTI3 (0xF << 12) -#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12) -#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12) -#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12) -#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12) -#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12) -#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12) -#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12) -#define AFIO_EXTICR1_EXTI2 (0xF << 8) -#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8) -#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8) -#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8) -#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8) -#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8) -#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8) -#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8) -#define AFIO_EXTICR1_EXTI1 (0xF << 4) -#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4) -#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4) -#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4) -#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4) -#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4) -#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4) -#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4) -#define AFIO_EXTICR1_EXTI0 0xF -#define AFIO_EXTICR1_EXTI0_PA 0x0 -#define AFIO_EXTICR1_EXTI0_PB 0x1 -#define AFIO_EXTICR1_EXTI0_PC 0x2 -#define AFIO_EXTICR1_EXTI0_PD 0x3 -#define AFIO_EXTICR1_EXTI0_PE 0x4 -#define AFIO_EXTICR1_EXTI0_PF 0x5 -#define AFIO_EXTICR1_EXTI0_PG 0x6 - -/* External interrupt configuration register 2 */ - -#define AFIO_EXTICR2_EXTI7 (0xF << 12) -#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12) -#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12) -#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12) -#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12) -#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12) -#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12) -#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12) -#define AFIO_EXTICR2_EXTI6 (0xF << 8) -#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8) -#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8) -#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8) -#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8) -#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8) -#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8) -#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8) -#define AFIO_EXTICR2_EXTI5 (0xF << 4) -#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4) -#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4) -#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4) -#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4) -#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4) -#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4) -#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4) -#define AFIO_EXTICR2_EXTI4 0xF -#define AFIO_EXTICR2_EXTI4_PA 0x0 -#define AFIO_EXTICR2_EXTI4_PB 0x1 -#define AFIO_EXTICR2_EXTI4_PC 0x2 -#define AFIO_EXTICR2_EXTI4_PD 0x3 -#define AFIO_EXTICR2_EXTI4_PE 0x4 -#define AFIO_EXTICR2_EXTI4_PF 0x5 -#define AFIO_EXTICR2_EXTI4_PG 0x6 - -/* AF remap and debug I/O configuration register 2 */ - -#define AFIO_MAPR2_FSMC_NADV BIT(10) -#define AFIO_MAPR2_TIM14_REMAP BIT(9) -#define AFIO_MAPR2_TIM13_REMAP BIT(8) -#define AFIO_MAPR2_TIM11_REMAP BIT(7) -#define AFIO_MAPR2_TIM10_REMAP BIT(6) -#define AFIO_MAPR2_TIM9_REMAP BIT(5) - -/* - * AFIO convenience routines - */ - -void afio_init(void); - -/** - * External interrupt line numbers. - */ -typedef enum afio_exti_num { - AFIO_EXTI_0, /**< External interrupt line 0. */ - AFIO_EXTI_1, /**< External interrupt line 1. */ - AFIO_EXTI_2, /**< External interrupt line 2. */ - AFIO_EXTI_3, /**< External interrupt line 3. */ - AFIO_EXTI_4, /**< External interrupt line 4. */ - AFIO_EXTI_5, /**< External interrupt line 5. */ - AFIO_EXTI_6, /**< External interrupt line 6. */ - AFIO_EXTI_7, /**< External interrupt line 7. */ - AFIO_EXTI_8, /**< External interrupt line 8. */ - AFIO_EXTI_9, /**< External interrupt line 9. */ - AFIO_EXTI_10, /**< External interrupt line 10. */ - AFIO_EXTI_11, /**< External interrupt line 11. */ - AFIO_EXTI_12, /**< External interrupt line 12. */ - AFIO_EXTI_13, /**< External interrupt line 13. */ - AFIO_EXTI_14, /**< External interrupt line 14. */ - AFIO_EXTI_15, /**< External interrupt line 15. */ -} afio_exti_num; - -void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); - -/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and - * not used in either MAPR or MAPR2 */ -#define AFIO_REMAP_USE_MAPR2 (1 << 31) - -/** - * @brief Available peripheral remaps. - * @see afio_remap() - */ -typedef enum afio_remap_peripheral { - AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< - ADC 2 external trigger regular conversion remapping */ - AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< - ADC 2 external trigger injected conversion remapping */ - AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< - ADC 1 external trigger regular conversion remapping */ - AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< - ADC 1 external trigger injected conversion remapping */ - AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< - Timer 5 channel 4 internal remapping */ - AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< - Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< - CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ - AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< - CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ - AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< - Timer 4 remapping */ - AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< - Timer 3 partial remapping */ - AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< - Timer 3 full remapping */ - AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< - Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 - on PA2, CH4 on PA3) */ - AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< - Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 - on PB10, CH4 on PB11) */ - AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< - Timer 2 full remapping */ - AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< - USART 2 remapping */ - AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< - USART 1 remapping */ - AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< - I2C 1 remapping */ - AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< - SPI 1 remapping */ - AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | - AFIO_REMAP_USE_MAPR2), /**< - NADV signal not connected */ - AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 14 remapping */ - AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 13 remapping */ - AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 11 remapping */ - AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 10 remapping */ - AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | - AFIO_REMAP_USE_MAPR2) /**< - Timer 9 */ -} afio_remap_peripheral; - -void afio_remap(afio_remap_peripheral p); - -/** - * @brief Debug port configuration - * - * Used to configure the behavior of JTAG and Serial Wire (SW) debug - * ports and their associated GPIO pins. - * - * @see afio_cfg_debug_ports() - */ -typedef enum afio_debug_cfg { - AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< - Full Serial Wire and JTAG debug */ - AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< - Full Serial Wire and JTAG, but no NJTRST. */ - AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< - Serial Wire debug only (JTAG-DP disabled, - SW-DP enabled) */ - AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< - No debug; all JTAG and SW pins are free - for use as GPIOs. */ -} afio_debug_cfg; - -/** - * @brief Enable or disable the JTAG and SW debug ports. - * @param config Desired debug port configuration - * @see afio_debug_cfg - */ -static inline void afio_cfg_debug_ports(afio_debug_cfg config) { - __io uint32 *mapr = &AFIO_BASE->MAPR; - *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; -} - #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/gpio.c b/libmaple/stm32f1/gpio.c new file mode 100644 index 0000000..01a4028 --- /dev/null +++ b/libmaple/stm32f1/gpio.c @@ -0,0 +1,184 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/gpio.c + * @brief GPIO support for STM32F1 line. + */ + +#include +#include + +/* + * GPIO devices + */ + +gpio_dev gpioa = { + .regs = GPIOA_BASE, + .clk_id = RCC_GPIOA, + .exti_port = AFIO_EXTI_PA, +}; +/** GPIO port A device. */ +gpio_dev* const GPIOA = &gpioa; + +gpio_dev gpiob = { + .regs = GPIOB_BASE, + .clk_id = RCC_GPIOB, + .exti_port = AFIO_EXTI_PB, +}; +/** GPIO port B device. */ +gpio_dev* const GPIOB = &gpiob; + +gpio_dev gpioc = { + .regs = GPIOC_BASE, + .clk_id = RCC_GPIOC, + .exti_port = AFIO_EXTI_PC, +}; +/** GPIO port C device. */ +gpio_dev* const GPIOC = &gpioc; + +gpio_dev gpiod = { + .regs = GPIOD_BASE, + .clk_id = RCC_GPIOD, + .exti_port = AFIO_EXTI_PD, +}; +/** GPIO port D device. */ +gpio_dev* const GPIOD = &gpiod; + +#ifdef STM32_HIGH_DENSITY +gpio_dev gpioe = { + .regs = GPIOE_BASE, + .clk_id = RCC_GPIOE, + .exti_port = AFIO_EXTI_PE, +}; +/** GPIO port E device. */ +gpio_dev* const GPIOE = &gpioe; + +gpio_dev gpiof = { + .regs = GPIOF_BASE, + .clk_id = RCC_GPIOF, + .exti_port = AFIO_EXTI_PF, +}; +/** GPIO port F device. */ +gpio_dev* const GPIOF = &gpiof; + +gpio_dev gpiog = { + .regs = GPIOG_BASE, + .clk_id = RCC_GPIOG, + .exti_port = AFIO_EXTI_PG, +}; +/** GPIO port G device. */ +gpio_dev* const GPIOG = &gpiog; +#endif + +/* + * GPIO routines + */ + +/** + * Initialize and reset all available GPIO devices. + */ +void gpio_init_all(void) { + gpio_init(GPIOA); + gpio_init(GPIOB); + gpio_init(GPIOC); + gpio_init(GPIOD); +#ifdef STM32_HIGH_DENSITY + gpio_init(GPIOE); + gpio_init(GPIOF); + gpio_init(GPIOG); +#endif +} + +/** + * Set the mode of a GPIO pin. + * + * @param dev GPIO device. + * @param pin Pin on the device whose mode to set, 0--15. + * @param mode General purpose or alternate function mode to set the pin to. + * @see gpio_pin_mode + */ +void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) { + gpio_reg_map *regs = dev->regs; + __io uint32 *cr = ®s->CRL + (pin >> 3); + uint32 shift = (pin & 0x7) * 4; + uint32 tmp = *cr; + + tmp &= ~(0xF << shift); + tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift; + *cr = tmp; + + if (mode == GPIO_INPUT_PD) { + regs->ODR &= ~BIT(pin); + } else if (mode == GPIO_INPUT_PU) { + regs->ODR |= BIT(pin); + } +} + +/* + * AFIO + */ + +/** + * @brief Initialize the AFIO clock, and reset the AFIO registers. + */ +void afio_init(void) { + rcc_clk_enable(RCC_AFIO); + rcc_reset_dev(RCC_AFIO); +} + +#define AFIO_EXTI_SEL_MASK 0xF + +/** + * @brief Select a source input for an external interrupt. + * + * @param exti External interrupt. + * @param gpio_port Port which contains pin to use as source input. + * @see afio_exti_num + * @see afio_exti_port + */ +void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) { + __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4; + uint32 shift = 4 * (exti % 4); + uint32 cr = *exti_cr; + + cr &= ~(AFIO_EXTI_SEL_MASK << shift); + cr |= gpio_port << shift; + *exti_cr = cr; +} + +/** + * @brief Perform an alternate function remap. + * @param remapping Remapping to perform. + */ +void afio_remap(afio_remap_peripheral remapping) { + if (remapping & AFIO_REMAP_USE_MAPR2) { + remapping &= ~AFIO_REMAP_USE_MAPR2; + AFIO_BASE->MAPR2 |= remapping; + } else { + AFIO_BASE->MAPR |= remapping; + } +} diff --git a/libmaple/stm32f1/include/family/gpio.h b/libmaple/stm32f1/include/family/gpio.h new file mode 100644 index 0000000..c10244d --- /dev/null +++ b/libmaple/stm32f1/include/family/gpio.h @@ -0,0 +1,479 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +/** + * @file libmaple/stm32f1/gpio.h + * @brief General purpose I/O (GPIO) and Alternate Function I/O + * (AFIO) prototypes, defines, and inlined access functions. + */ + +#ifndef _LIBMAPLE_STM32F1_GPIO_H_ +#define _LIBMAPLE_STM32F1_GPIO_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/* + * GPIO register maps and devices + */ + +/** GPIO register map type */ +typedef struct gpio_reg_map { + __io uint32 CRL; /**< Port configuration register low */ + __io uint32 CRH; /**< Port configuration register high */ + __io uint32 IDR; /**< Port input data register */ + __io uint32 ODR; /**< Port output data register */ + __io uint32 BSRR; /**< Port bit set/reset register */ + __io uint32 BRR; /**< Port bit reset register */ + __io uint32 LCKR; /**< Port configuration lock register */ +} gpio_reg_map; + +/** + * @brief External interrupt line port selector. + * + * Used to determine which GPIO port to map an external interrupt line + * onto. */ +/* (See AFIO sections, below) */ +typedef enum afio_exti_port { + AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ + AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ + AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ + AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ +#ifdef STM32_HIGH_DENSITY + AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ + AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ + AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ +#endif +} afio_exti_port; + +/** GPIO device type */ +typedef struct gpio_dev { + gpio_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ + afio_exti_port exti_port; /**< AFIO external interrupt port value */ +} gpio_dev; + +extern gpio_dev gpioa; +extern gpio_dev* const GPIOA; +extern gpio_dev gpiob; +extern gpio_dev* const GPIOB; +extern gpio_dev gpioc; +extern gpio_dev* const GPIOC; +extern gpio_dev gpiod; +extern gpio_dev* const GPIOD; +#ifdef STM32_HIGH_DENSITY +extern gpio_dev gpioe; +extern gpio_dev* const GPIOE; +extern gpio_dev gpiof; +extern gpio_dev* const GPIOF; +extern gpio_dev gpiog; +extern gpio_dev* const GPIOG; +#endif + +/** GPIO port A register map base pointer */ +#define GPIOA_BASE ((struct gpio_reg_map*)0x40010800) +/** GPIO port B register map base pointer */ +#define GPIOB_BASE ((struct gpio_reg_map*)0x40010C00) +/** GPIO port C register map base pointer */ +#define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) +/** GPIO port D register map base pointer */ +#define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) +#ifdef STM32_HIGH_DENSITY +/** GPIO port E register map base pointer */ +#define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) +/** GPIO port F register map base pointer */ +#define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) +/** GPIO port G register map base pointer */ +#define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) +#endif + +/* + * GPIO register bit definitions + */ + +/* Control registers, low and high */ + +#define GPIO_CR_CNF (0x3 << 2) +#define GPIO_CR_CNF_INPUT_ANALOG (0x0 << 2) +#define GPIO_CR_CNF_INPUT_FLOATING (0x1 << 2) +#define GPIO_CR_CNF_INPUT_PU_PD (0x2 << 2) +#define GPIO_CR_CNF_OUTPUT_PP (0x0 << 2) +#define GPIO_CR_CNF_OUTPUT_OD (0x1 << 2) +#define GPIO_CR_CNF_AF_OUTPUT_PP (0x2 << 2) +#define GPIO_CR_CNF_AF_OUTPUT_OD (0x3 << 2) +#define GPIO_CR_MODE 0x3 +#define GPIO_CR_MODE_INPUT 0x0 +#define GPIO_CR_MODE_OUTPUT_10MHZ 0x1 +#define GPIO_CR_MODE_OUTPUT_2MHZ 0x2 +#define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 + +/** + * @brief GPIO Pin modes. + * + * These only allow for 50MHZ max output speeds; if you want slower, + * use direct register access. + */ +typedef enum gpio_pin_mode { + GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ + GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ + GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function + output push-pull. */ + GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function + output open drain. */ + GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | + GPIO_CR_MODE_INPUT), /**< Analog input. */ + GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | + GPIO_CR_MODE_INPUT), /**< Input floating. */ + GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | + GPIO_CR_MODE_INPUT), /**< Input pull-down. */ + GPIO_INPUT_PU /**< Input pull-up. */ + /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ +} gpio_pin_mode; + +/** + * @brief Get a GPIO port's corresponding afio_exti_port. + * @param dev GPIO device whose afio_exti_port to return. + */ +static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { + return dev->exti_port; +} + +/* + * AFIO register map + */ + +/** AFIO register map */ +typedef struct afio_reg_map { + __io uint32 EVCR; /**< Event control register. */ + __io uint32 MAPR; /**< AF remap and debug I/O configuration + register. */ + __io uint32 EXTICR1; /**< External interrupt configuration + register 1. */ + __io uint32 EXTICR2; /**< External interrupt configuration + register 2. */ + __io uint32 EXTICR3; /**< External interrupt configuration + register 3. */ + __io uint32 EXTICR4; /**< External interrupt configuration + register 4. */ + __io uint32 MAPR2; /**< AF remap and debug I/O configuration + register 2. */ +} afio_reg_map; + +/** AFIO register map base pointer. */ +#define AFIO_BASE ((struct afio_reg_map *)0x40010000) + +/* + * AFIO register bit definitions + */ + +/* Event control register */ + +#define AFIO_EVCR_EVOE (0x1 << 7) +#define AFIO_EVCR_PORT_PA (0x0 << 4) +#define AFIO_EVCR_PORT_PB (0x1 << 4) +#define AFIO_EVCR_PORT_PC (0x2 << 4) +#define AFIO_EVCR_PORT_PD (0x3 << 4) +#define AFIO_EVCR_PORT_PE (0x4 << 4) +#define AFIO_EVCR_PIN_0 0x0 +#define AFIO_EVCR_PIN_1 0x1 +#define AFIO_EVCR_PIN_2 0x2 +#define AFIO_EVCR_PIN_3 0x3 +#define AFIO_EVCR_PIN_4 0x4 +#define AFIO_EVCR_PIN_5 0x5 +#define AFIO_EVCR_PIN_6 0x6 +#define AFIO_EVCR_PIN_7 0x7 +#define AFIO_EVCR_PIN_8 0x8 +#define AFIO_EVCR_PIN_9 0x9 +#define AFIO_EVCR_PIN_10 0xA +#define AFIO_EVCR_PIN_11 0xB +#define AFIO_EVCR_PIN_12 0xC +#define AFIO_EVCR_PIN_13 0xD +#define AFIO_EVCR_PIN_14 0xE +#define AFIO_EVCR_PIN_15 0xF + +/* AF remap and debug I/O configuration register */ + +#define AFIO_MAPR_SWJ_CFG (0x7 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) +#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) +#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) +#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) +#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) +#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) +#define AFIO_MAPR_PD01_REMAP BIT(15) +#define AFIO_MAPR_CAN_REMAP (0x3 << 13) +#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) +#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) +#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) +#define AFIO_MAPR_TIM4_REMAP BIT(12) +#define AFIO_MAPR_TIM3_REMAP (0x3 << 10) +#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) +#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) +#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10) +#define AFIO_MAPR_TIM2_REMAP (0x3 << 8) +#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8) +#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8) +#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8) +#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8) +#define AFIO_MAPR_TIM1_REMAP (0x3 << 6) +#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6) +#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6) +#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6) +#define AFIO_MAPR_USART3_REMAP (0x3 << 4) +#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) +#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) +#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) +#define AFIO_MAPR_USART2_REMAP BIT(3) +#define AFIO_MAPR_USART1_REMAP BIT(2) +#define AFIO_MAPR_I2C1_REMAP BIT(1) +#define AFIO_MAPR_SPI1_REMAP BIT(0) + +/* External interrupt configuration register 1 */ + +#define AFIO_EXTICR1_EXTI3 (0xF << 12) +#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12) +#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12) +#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12) +#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12) +#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12) +#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12) +#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12) +#define AFIO_EXTICR1_EXTI2 (0xF << 8) +#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8) +#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8) +#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8) +#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8) +#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8) +#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8) +#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8) +#define AFIO_EXTICR1_EXTI1 (0xF << 4) +#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4) +#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4) +#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4) +#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4) +#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4) +#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4) +#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4) +#define AFIO_EXTICR1_EXTI0 0xF +#define AFIO_EXTICR1_EXTI0_PA 0x0 +#define AFIO_EXTICR1_EXTI0_PB 0x1 +#define AFIO_EXTICR1_EXTI0_PC 0x2 +#define AFIO_EXTICR1_EXTI0_PD 0x3 +#define AFIO_EXTICR1_EXTI0_PE 0x4 +#define AFIO_EXTICR1_EXTI0_PF 0x5 +#define AFIO_EXTICR1_EXTI0_PG 0x6 + +/* External interrupt configuration register 2 */ + +#define AFIO_EXTICR2_EXTI7 (0xF << 12) +#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12) +#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12) +#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12) +#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12) +#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12) +#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12) +#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12) +#define AFIO_EXTICR2_EXTI6 (0xF << 8) +#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8) +#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8) +#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8) +#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8) +#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8) +#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8) +#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8) +#define AFIO_EXTICR2_EXTI5 (0xF << 4) +#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4) +#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4) +#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4) +#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4) +#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4) +#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4) +#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4) +#define AFIO_EXTICR2_EXTI4 0xF +#define AFIO_EXTICR2_EXTI4_PA 0x0 +#define AFIO_EXTICR2_EXTI4_PB 0x1 +#define AFIO_EXTICR2_EXTI4_PC 0x2 +#define AFIO_EXTICR2_EXTI4_PD 0x3 +#define AFIO_EXTICR2_EXTI4_PE 0x4 +#define AFIO_EXTICR2_EXTI4_PF 0x5 +#define AFIO_EXTICR2_EXTI4_PG 0x6 + +/* AF remap and debug I/O configuration register 2 */ + +#define AFIO_MAPR2_FSMC_NADV BIT(10) +#define AFIO_MAPR2_TIM14_REMAP BIT(9) +#define AFIO_MAPR2_TIM13_REMAP BIT(8) +#define AFIO_MAPR2_TIM11_REMAP BIT(7) +#define AFIO_MAPR2_TIM10_REMAP BIT(6) +#define AFIO_MAPR2_TIM9_REMAP BIT(5) + +/* + * AFIO convenience routines + */ + +void afio_init(void); + +/** + * External interrupt line numbers. + */ +typedef enum afio_exti_num { + AFIO_EXTI_0, /**< External interrupt line 0. */ + AFIO_EXTI_1, /**< External interrupt line 1. */ + AFIO_EXTI_2, /**< External interrupt line 2. */ + AFIO_EXTI_3, /**< External interrupt line 3. */ + AFIO_EXTI_4, /**< External interrupt line 4. */ + AFIO_EXTI_5, /**< External interrupt line 5. */ + AFIO_EXTI_6, /**< External interrupt line 6. */ + AFIO_EXTI_7, /**< External interrupt line 7. */ + AFIO_EXTI_8, /**< External interrupt line 8. */ + AFIO_EXTI_9, /**< External interrupt line 9. */ + AFIO_EXTI_10, /**< External interrupt line 10. */ + AFIO_EXTI_11, /**< External interrupt line 11. */ + AFIO_EXTI_12, /**< External interrupt line 12. */ + AFIO_EXTI_13, /**< External interrupt line 13. */ + AFIO_EXTI_14, /**< External interrupt line 14. */ + AFIO_EXTI_15, /**< External interrupt line 15. */ +} afio_exti_num; + +void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); + +/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and + * not used in either MAPR or MAPR2 */ +#define AFIO_REMAP_USE_MAPR2 (1 << 31) + +/** + * @brief Available peripheral remaps. + * @see afio_remap() + */ +typedef enum afio_remap_peripheral { + AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< + ADC 2 external trigger regular conversion remapping */ + AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< + ADC 2 external trigger injected conversion remapping */ + AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< + ADC 1 external trigger regular conversion remapping */ + AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< + ADC 1 external trigger injected conversion remapping */ + AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< + Timer 5 channel 4 internal remapping */ + AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< + Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< + CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ + AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< + CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ + AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< + Timer 4 remapping */ + AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< + Timer 3 partial remapping */ + AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< + Timer 3 full remapping */ + AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< + Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 + on PA2, CH4 on PA3) */ + AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< + Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 + on PB10, CH4 on PB11) */ + AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< + Timer 2 full remapping */ + AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< + USART 2 remapping */ + AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< + USART 1 remapping */ + AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< + I2C 1 remapping */ + AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< + SPI 1 remapping */ + AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | + AFIO_REMAP_USE_MAPR2), /**< + NADV signal not connected */ + AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 14 remapping */ + AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 13 remapping */ + AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 11 remapping */ + AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 10 remapping */ + AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | + AFIO_REMAP_USE_MAPR2) /**< + Timer 9 */ +} afio_remap_peripheral; + +void afio_remap(afio_remap_peripheral p); + +/** + * @brief Debug port configuration + * + * Used to configure the behavior of JTAG and Serial Wire (SW) debug + * ports and their associated GPIO pins. + * + * @see afio_cfg_debug_ports() + */ +typedef enum afio_debug_cfg { + AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< + Full Serial Wire and JTAG debug */ + AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< + Full Serial Wire and JTAG, but no NJTRST. */ + AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< + Serial Wire debug only (JTAG-DP disabled, + SW-DP enabled) */ + AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< + No debug; all JTAG and SW pins are free + for use as GPIOs. */ +} afio_debug_cfg; + +/** + * @brief Enable or disable the JTAG and SW debug ports. + * @param config Desired debug port configuration + * @see afio_debug_cfg + */ +static inline void afio_cfg_debug_ports(afio_debug_cfg config) { + __io uint32 *mapr = &AFIO_BASE->MAPR; + *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 2bdc423..03d2f95 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -13,6 +13,7 @@ sSRCS_$(d) := isrs_performance.S \ cSRCS_$(d) := rcc.c cSRCS_$(d) += flash.c +cSRCS_$(d) += gpio.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 748edc3887c714dcc92768556aac7ac563b6247e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 17 Nov 2011 15:39:15 -0500 Subject: libmaple: Add build infrastructure for private headers. libmaple/rules.mk: Add LIBMAPLE_PRIVATE_INCLUDES, a place for storing headers which should be commonly available throughout libmaple, but not made public. Currently, this is just the libmaple directory. Add LIBMAPLE_PRIVATE_INCLUDES to the target flags in the STM32F1 and USB submodules. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 3 ++- libmaple/stm32f1/rules.mk | 2 +- libmaple/usb/rules.mk | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index cf95b48..cbff931 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -5,9 +5,10 @@ d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include -I$(LIBMAPLE_MODULE_FAMILY)/include +LIBMAPLE_PRIVATE_INCLUDES := -I$(LIBMAPLE_PATH) # Local flags -CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror +CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c \ diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 03d2f95..5267e9b 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -5,7 +5,7 @@ d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) # Local flags -CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) -Wall -Werror +CFLAGS_$(d) = -I$(d) $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets sSRCS_$(d) := isrs_performance.S \ diff --git a/libmaple/usb/rules.mk b/libmaple/usb/rules.mk index 9ef8d70..816fad6 100644 --- a/libmaple/usb/rules.mk +++ b/libmaple/usb/rules.mk @@ -6,7 +6,7 @@ BUILDDIRS += $(BUILD_PATH)/$(d) BUILDDIRS += $(BUILD_PATH)/$(d)/usb_lib # Local flags -CFLAGS_$(d) = -I$(d) -I$(d)/usb_lib $(LIBMAPLE_INCLUDES) -Wall +CFLAGS_$(d) = -I$(d) -I$(d)/usb_lib $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall # Local rules and targets sSRCS_$(d) := -- cgit v1.2.3 From 5337e01c09e19573758efbc57a7f7e972d78ab3f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 17:24:14 -0500 Subject: RCC: Break out some portable functionality from stm32f1/. Portions of rcc_clk_enable(), rcc_reset_dev(), and rcc_set_prescaler() are portable; break these into static inline helpers in rcc_private.h. These guts of these are portable, but the arrays of registers etc. are not. Also add an extern declaration for rcc_dev_table into rcc_private.h. This lets us put rcc_dev_clk() into a newly resurrected libmaple/rcc.c, since that's portable. Signed-off-by: Marti Bolivar --- libmaple/rcc.c | 44 +++++++++++++++++++++++++++++++++ libmaple/rcc_private.h | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++ libmaple/rules.mk | 1 + libmaple/stm32f1/rcc.c | 41 ++++++------------------------ 4 files changed, 119 insertions(+), 34 deletions(-) create mode 100644 libmaple/rcc.c create mode 100644 libmaple/rcc_private.h diff --git a/libmaple/rcc.c b/libmaple/rcc.c new file mode 100644 index 0000000..d6ed2d6 --- /dev/null +++ b/libmaple/rcc.c @@ -0,0 +1,44 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/rcc.c + * @brief Portable RCC routines. + */ + +#include + +#include "rcc_private.h" + +/** + * @brief Get a peripheral's clock domain + * @param id Clock ID of the peripheral whose clock domain to return + * @return Clock source for the given clock ID + */ +rcc_clk_domain rcc_dev_clk(rcc_clk_id id) { + return rcc_dev_table[id].clk_domain; +} diff --git a/libmaple/rcc_private.h b/libmaple/rcc_private.h new file mode 100644 index 0000000..66eaf00 --- /dev/null +++ b/libmaple/rcc_private.h @@ -0,0 +1,67 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* + * RCC private header. + */ + +#ifndef _LIBMAPLE_PRIVATE_RCC_H_ +#define _LIBMAPLE_PRIVATE_RCC_H_ + +#include + +struct rcc_dev_info { + const rcc_clk_domain clk_domain; + const uint8 line_num; +}; + +extern const struct rcc_dev_info rcc_dev_table[]; + +static inline void rcc_do_clk_enable(__io uint32** enable_regs, + rcc_clk_id id) { + __io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)]; + uint8 line_num = rcc_dev_table[id].line_num; + bb_peri_set_bit(enable_reg, line_num, 1); +} + +static inline void rcc_do_reset_dev(__io uint32** reset_regs, + rcc_clk_id id) { + __io uint32 *reset_reg = reset_regs[rcc_dev_clk(id)]; + uint8 line_num = rcc_dev_table[id].line_num; + bb_peri_set_bit(reset_reg, line_num, 1); + bb_peri_set_bit(reset_reg, line_num, 0); +} + +static inline void rcc_do_set_prescaler(const uint32 *masks, + rcc_prescaler prescaler, + uint32 divider) { + uint32 cfgr = RCC_BASE->CFGR; + cfgr &= ~masks[prescaler]; + cfgr |= divider; + RCC_BASE->CFGR = cfgr; +} + +#endif diff --git a/libmaple/rules.mk b/libmaple/rules.mk index cbff931..3ca5b3a 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -23,6 +23,7 @@ cSRCS_$(d) := adc.c \ nvic.c \ pwr.c \ i2c.c \ + rcc.c \ spi.c \ syscalls.c \ systick.c \ diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index c40d52f..c8d24c6 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -34,10 +34,7 @@ #include #include -struct rcc_dev_info { - const rcc_clk_domain clk_domain; - const uint8 line_num; -}; +#include "rcc_private.h" #define APB1 RCC_APB1 #define APB2 RCC_APB2 @@ -45,7 +42,7 @@ struct rcc_dev_info { /* Device descriptor table, maps rcc_clk_id onto bus and enable/reset * register bit numbers. */ -static const struct rcc_dev_info rcc_dev_table[] = { +const struct rcc_dev_info rcc_dev_table[] = { [RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 }, [RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 }, [RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 }, @@ -144,17 +141,12 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src, * @param id Clock ID of the peripheral to turn on. */ void rcc_clk_enable(rcc_clk_id id) { - static const __io uint32* enable_regs[] = { + static __io uint32* enable_regs[] = { [APB1] = &RCC_BASE->APB1ENR, [APB2] = &RCC_BASE->APB2ENR, [AHB] = &RCC_BASE->AHBENR, }; - - rcc_clk_domain clk_domain = rcc_dev_clk(id); - __io uint32* enr = (__io uint32*)enable_regs[clk_domain]; - uint8 lnum = rcc_dev_table[id].line_num; - - bb_peri_set_bit(enr, lnum, 1); + rcc_do_clk_enable(enable_regs, id); } /** @@ -162,26 +154,11 @@ void rcc_clk_enable(rcc_clk_id id) { * @param id Clock ID of the peripheral to reset. */ void rcc_reset_dev(rcc_clk_id id) { - static const __io uint32* reset_regs[] = { + static __io uint32* reset_regs[] = { [APB1] = &RCC_BASE->APB1RSTR, [APB2] = &RCC_BASE->APB2RSTR, }; - - rcc_clk_domain clk_domain = rcc_dev_clk(id); - __io void* addr = (__io void*)reset_regs[clk_domain]; - uint8 lnum = rcc_dev_table[id].line_num; - - bb_peri_set_bit(addr, lnum, 1); - bb_peri_set_bit(addr, lnum, 0); -} - -/** - * @brief Get a peripheral's clock domain - * @param id Clock ID of the peripheral whose clock domain to return - * @return Clock source for the given clock ID - */ -rcc_clk_domain rcc_dev_clk(rcc_clk_id id) { - return rcc_dev_table[id].clk_domain; + rcc_do_reset_dev(reset_regs, id); } /** @@ -197,9 +174,5 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE, [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE, }; - - uint32 cfgr = RCC_BASE->CFGR; - cfgr &= ~masks[prescaler]; - cfgr |= divider; - RCC_BASE->CFGR = cfgr; + rcc_do_set_prescaler(masks, prescaler, divider); } -- cgit v1.2.3 From 4d8c90939f8bb91390967e25187228f81ea1e71b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 18:37:44 -0500 Subject: stm32f1/rcc.c: Add cautionary comment. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/rcc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index c8d24c6..2b78e89 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -151,6 +151,10 @@ void rcc_clk_enable(rcc_clk_id id) { /** * @brief Reset a peripheral. + * + * Caution: not all rcc_clk_id values refer to a peripheral which can + * be reset. + * * @param id Clock ID of the peripheral to reset. */ void rcc_reset_dev(rcc_clk_id id) { -- cgit v1.2.3 From 23ab3693e37af790497f62ad4d6a605e2a151aba Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 19:21:44 -0500 Subject: stm32f1: License headers, portability markers. Add license headers to libmaple/stm32f1/isrs_performance.S and libmaple/stm32f1/vector_table_performance.S. Copyright to Perry Hung. I was present when Perry wrote these files. Also mark these as STM32F1 specific (rather than "STM32", say "STM32F1"). Signed-off-by: Marti Bolivar --- libmaple/stm32f1/isrs_performance.S | 28 +++++++++++++++++++++++++++- libmaple/stm32f1/vector_table_performance.S | 28 +++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/libmaple/stm32f1/isrs_performance.S b/libmaple/stm32f1/isrs_performance.S index be102e7..af39198 100644 --- a/libmaple/stm32f1/isrs_performance.S +++ b/libmaple/stm32f1/isrs_performance.S @@ -1,4 +1,30 @@ -/* STM32 ISR weak declarations */ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F1 ISR weak declarations */ .thumb diff --git a/libmaple/stm32f1/vector_table_performance.S b/libmaple/stm32f1/vector_table_performance.S index 0392a02..55cf44f 100644 --- a/libmaple/stm32f1/vector_table_performance.S +++ b/libmaple/stm32f1/vector_table_performance.S @@ -1,4 +1,30 @@ -/* STM32 vector table */ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F1 vector table */ .section ".stm32.interrupt_vector" -- cgit v1.2.3 From df223dde202f340f3885dafe60d1de22a13b27d9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 19 Nov 2011 16:22:15 -0500 Subject: libmaple/nvic.h: Explanatory commenting. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/nvic.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h index afcb769..23425df 100644 --- a/libmaple/include/libmaple/nvic.h +++ b/libmaple/include/libmaple/nvic.h @@ -81,7 +81,9 @@ typedef struct nvic_reg_map { * vector table. * * It also must define a static inline nvic_irq_disable_all(), which - * writes 0xFFFFFFFF to all ICE registers available in the family. + * writes 0xFFFFFFFF to all ICE registers available in the family. (We + * place the include here to give the family header access to + * NVIC_BASE, in order to let it do so). */ #include -- cgit v1.2.3 From 35d55def21b78dc9f1416a19edd98b48c53754ee Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 21 Nov 2011 17:12:45 -0500 Subject: Rename GLOBAL_FLAGS to TARGET_FLAGS, remove from Makefile. Move into target-config.mk. Build it up bit-by-bit as the build goes on. Repeat the DENSITY defines once per board in target-config.mk, since they don't make sense on STM32F2. Signed-off-by: Marti Bolivar --- Makefile | 13 ++++--------- support/make/target-config.mk | 15 +++++++++++++++ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index c2a60dd..2525c2e 100644 --- a/Makefile +++ b/Makefile @@ -41,24 +41,19 @@ include $(MAKEDIR)/target-config.mk ## Compilation flags ## -GLOBAL_FLAGS := -D$(VECT_BASE_ADDR) \ - -DBOARD_$(BOARD) -DMCU_$(MCU) \ - -DERROR_LED_PORT=$(ERROR_LED_PORT) \ - -DERROR_LED_PIN=$(ERROR_LED_PIN) \ - -D$(DENSITY) # FIXME: the following allows for deprecated include style, e.g.: # #include "libmaple.h" # or # #include "wirish.h" # It slows compilation noticeably; remove after 1 release. -GLOBAL_FLAGS += -I$(LIBMAPLE_PATH)/include/libmaple \ +TARGET_FLAGS += -I$(LIBMAPLE_PATH)/include/libmaple \ -I$(WIRISH_PATH)/include/wirish GLOBAL_CFLAGS := -Os -g3 -gdwarf-2 -mcpu=cortex-m3 -mthumb -march=armv7-m \ -nostdlib -ffunction-sections -fdata-sections \ - -Wl,--gc-sections $(GLOBAL_FLAGS) -GLOBAL_CXXFLAGS := -fno-rtti -fno-exceptions -Wall $(GLOBAL_FLAGS) + -Wl,--gc-sections $(TARGET_FLAGS) +GLOBAL_CXXFLAGS := -fno-rtti -fno-exceptions -Wall $(TARGET_FLAGS) GLOBAL_ASFLAGS := -mcpu=cortex-m3 -march=armv7-m -mthumb \ - -x assembler-with-cpp $(GLOBAL_FLAGS) + -x assembler-with-cpp $(TARGET_FLAGS) LDFLAGS = -T$(LDDIR)/$(LDSCRIPT) -L$(LDDIR) \ -mcpu=cortex-m3 -mthumb -Xlinker -L $(LD_FAMILY_PATH) \ --gc-sections --print-gc-sections --march=armv7-m -Wall diff --git a/support/make/target-config.mk b/support/make/target-config.mk index 1ca6057..ea81b3b 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -1,3 +1,7 @@ +# TARGET_FLAGS are to be passed while compiling, assembling, linking. + +TARGET_FLAGS := + # Board-specific configuration values. Flash and SRAM sizes in bytes. ifeq ($(BOARD), maple) @@ -6,6 +10,7 @@ ifeq ($(BOARD), maple) ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 DENSITY := STM32_MEDIUM_DENSITY + TARGET_FLAGS += -D$(DENSITY) endif ifeq ($(BOARD), maple_native) @@ -14,6 +19,7 @@ ifeq ($(BOARD), maple_native) ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 15 DENSITY := STM32_HIGH_DENSITY + TARGET_FLAGS += -D$(DENSITY) endif ifeq ($(BOARD), maple_mini) @@ -22,6 +28,7 @@ ifeq ($(BOARD), maple_mini) ERROR_LED_PORT := GPIOB ERROR_LED_PIN := 1 DENSITY := STM32_MEDIUM_DENSITY + TARGET_FLAGS += -D$(DENSITY) endif ifeq ($(BOARD), maple_RET6) @@ -30,6 +37,7 @@ ifeq ($(BOARD), maple_RET6) ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 DENSITY := STM32_HIGH_DENSITY + TARGET_FLAGS += -D$(DENSITY) endif ifeq ($(BOARD), olimex_stm32_h103) @@ -38,8 +46,13 @@ ifeq ($(BOARD), olimex_stm32_h103) ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 12 DENSITY := STM32_MEDIUM_DENSITY + TARGET_FLAGS += -D$(DENSITY) endif +TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ + -DERROR_LED_PORT=$(ERROR_LED_PORT) \ + -DERROR_LED_PIN=$(ERROR_LED_PIN) + # STM32 family-specific configuration values. # NB: these only work for STM32F1 performance line chips, but those @@ -63,3 +76,5 @@ ifeq ($(MEMORY_TARGET), jtag) LDSCRIPT := $(BOARD)/jtag.ld VECT_BASE_ADDR := VECT_TAB_BASE endif + +TARGET_FLAGS += -D$(VECT_BASE_ADDR) -- cgit v1.2.3 From 95e12215caec0b4dba9a1d394e6cf7210ce6c30b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 28 Nov 2011 22:42:06 -0500 Subject: Move nonportable bits of libmaple/stm32.h into libmaple/stm32f1. These go in a new family header, libmaple/stm32f1/include/family/stm32.h. While we're at it, do some reorganizing. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 203 +++++++++++--------------------- libmaple/stm32f1/include/family/stm32.h | 100 ++++++++++++++++ 2 files changed, 168 insertions(+), 135 deletions(-) create mode 100644 libmaple/stm32f1/include/family/stm32.h diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 53a5d7a..5efb670 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -36,162 +36,95 @@ extern "C" { #endif -/* - * User-specific configuration. - * - * The #defines here depend upon how libmaple is used. Because of the - * potential for a mismatch between them and the actual libmaple - * usage, you should try to keep their number to an absolute minimum. - */ +/* Everything enclosed in the following __DOXYGEN_PREDEFINED_HACK + * conditional block must be defined in the family header. */ +#include #ifdef __DOXYGEN_PREDEFINED_HACK - /** @brief APB1 clock speed, in Hz. */ - #define STM32_PCLK1 - /** @brief APB2 clock speed, in Hz. */ - #define STM32_PCLK2 - - /** Deprecated. Use STM32_PCLK1 instead. */ - #define PCLK1 - /** Deprecated. Use STM32_PCLK2 instead. */ - #define PCLK2 +/* + * Clock configuration. + * + * These defines depend upon how the MCU is configured. Because of + * the potential for a mismatch between them and the actual clock + * configuration, keep their number to a minimum. + */ -#endif +/** + * @brief APB1 clock speed, in Hz. + */ +#define STM32_PCLK1 -#ifndef STM32_PCLK1 -#define STM32_PCLK1 36000000U -#endif -#ifndef PCLK1 -#define PCLK1 STM32_PCLK1 -#endif -#if PCLK1 != STM32_PCLK1 -#error "(Deprecated) PCLK1 differs from STM32_PCLK1" -#endif +/** + * @brief APB2 clock speed, in Hz. + */ +#define STM32_PCLK2 -#ifndef STM32_PCLK2 -#define STM32_PCLK2 72000000U -#endif -#ifndef PCLK2 -#define PCLK2 STM32_PCLK2 -#endif -#if PCLK2 != STM32_PCLK2 -#error "(Deprecated) PCLK2 differs from STM32_PCLK2" -#endif +/** @brief Deprecated. Use STM32_PCLK1 instead. */ +#define PCLK1 +/** @brief Deprecated. Use STM32_PCLK2 instead. */ +#define PCLK2 /* - * Density-specific configuration. + * Family- and MCU-specific values. */ -#ifdef __DOXYGEN_PREDEFINED_HACK - - /** - * @brief Number of interrupts in the NVIC. - * - * This define is automatically generated whenever the proper - * density is defined (currently, this is restricted to defining - * one of STM32_MEDIUM_DENSITY and STM32_HIGH_DENSITY). - */ - #define STM32_NR_INTERRUPTS +/** + * @brief Number of interrupts in the vector table. + * + * This does not include Cortex-M interrupts (NMI, HardFault, etc.). + */ +#define STM32_NR_INTERRUPTS - /** Deprecated. Use STM32_NR_INTERRUPTS instead. */ - #define NR_INTERRUPTS +/** + * Number of GPIO ports. + */ +#define STM32_NR_GPIO_PORTS -#endif +/** + * @brief Multiplier to convert microseconds into loop iterations + * in delay_us(). + * + * @see delay_us() + */ +#define STM32_DELAY_US_MULT -#ifdef STM32_MEDIUM_DENSITY - #define STM32_NR_INTERRUPTS 43 -#elif defined(STM32_HIGH_DENSITY) - #define STM32_NR_INTERRUPTS 60 -#else -#error "No STM32 board type defined!" -#endif +/** + * @brief Pointer to end of built-in SRAM. + * + * Points to the address which is 1 byte past the last valid + * SRAM address. + */ +#define STM32_SRAM_END -#define NR_INTERRUPTS STM32_NR_INTERRUPTS +#endif /* __DOXYGEN_PREDEFINED_HACK */ /* - * MCU-specific configuration. + * The following are for backwards compatibility only. */ -#ifdef __DOXYGEN_PREDEFINED_HACK - - /** - * Number of GPIO ports. - */ - #define STM32_NR_GPIO_PORTS - - /** - * @brief Multiplier to convert microseconds into loop iterations - * in delay_us(). - * - * @see delay_us() - */ - #define STM32_DELAY_US_MULT - - /** - * @brief Pointer to end of built-in SRAM. - * - * Points to the address which is 1 byte past the last valid - * SRAM address. - */ - #define STM32_SRAM_END - - /** Deprecated. Use STM32_NR_GPIO_PORTS instead. */ - #define NR_GPIO_PORTS - /** Deprecated. Use STM32_DELAY_US_MULT instead. */ - #define DELAY_US_MULT - +/* PCLK1 and PCLK2 are for backwards compatibility only; don't use in + * new code. */ +#ifndef PCLK1 +#define PCLK1 STM32_PCLK1 #endif - -#if defined(MCU_STM32F103RB) - /* e.g., LeafLabs Maple */ - - #define STM32_NR_GPIO_PORTS 4 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20005000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#elif defined(MCU_STM32F103ZE) - /* e.g., LeafLabs Maple Native */ - - #define STM32_NR_GPIO_PORTS 7 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20010000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#elif defined(MCU_STM32F103CB) - /* e.g., LeafLabs Maple Mini */ - - /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true. - * But only pins 0 and 1 exist, and they're used for OSC on the - * Mini, so we'll live with this for now. */ - #define STM32_NR_GPIO_PORTS 3 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20005000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#elif defined(MCU_STM32F103RE) - /* e.g., LeafLabs Maple RET6 edition */ - - #define STM32_NR_GPIO_PORTS 4 - #define STM32_DELAY_US_MULT 12 - #define STM32_SRAM_END ((void*)0x20010000) - - #define NR_GPIO_PORTS STM32_NR_GPIO_PORTS - #define DELAY_US_MULT STM32_DELAY_US_MULT - -#else - -#error "No MCU type specified. Add something like -DMCU_STM32F103RB " \ - "to your compiler arguments (probably in a Makefile)." - +#if PCLK1 != STM32_PCLK1 +#error "PCLK1 (which is deprecated) differs from STM32_PCLK1." +#endif +#ifndef PCLK2 +#define PCLK2 STM32_PCLK2 +#endif +#if PCLK2 != STM32_PCLK2 +#error "PCLK2 (which is deprecated) differs from STM32_PCLK2." #endif +/** @brief Deprecated. Use STM32_NR_INTERRUPTS instead. */ +#define NR_INTERRUPTS STM32_NR_INTERRUPTS +/** @brief Deprecated. Use STM32_NR_GPIO_PORTS instead. */ +#define NR_GPIO_PORTS STM32_NR_GPIO_PORTS +/** @brief Deprecated. Use STM32_DELAY_US_MULT instead. */ +#define DELAY_US_MULT STM32_DELAY_US_MULT + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/include/family/stm32.h b/libmaple/stm32f1/include/family/stm32.h new file mode 100644 index 0000000..0b77ca0 --- /dev/null +++ b/libmaple/stm32f1/include/family/stm32.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010, 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/stm32.h + * @brief STM32F1 chip- and family-specific definitions. + */ + +#ifndef _LIBMAPLE_STM32F1_H_ +#define _LIBMAPLE_STM32F1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Clock configuration. + */ + +#ifndef STM32_PCLK1 +#define STM32_PCLK1 36000000U +#endif + +#ifndef STM32_PCLK2 +#define STM32_PCLK2 72000000U +#endif + +#ifndef STM32_DELAY_US_MULT +#define STM32_DELAY_US_MULT 12 /* FIXME: value is incorrect. */ +#endif + +/* + * Density-specific values. + */ + +#ifdef STM32_MEDIUM_DENSITY +# define STM32_NR_INTERRUPTS 43 +#elif defined(STM32_HIGH_DENSITY) +# define STM32_NR_INTERRUPTS 60 +#else +#error "Unsupported STM32F1 density, or no density specified. Add something " \ + "like -DSTM32_MEDIUM_DENSITY to your compiler arguments." +#endif + +/* + * MCU-specific values. + */ + +#if defined(MCU_STM32F103RB) +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20005000) + +#elif defined(MCU_STM32F103ZE) +# define STM32_NR_GPIO_PORTS 7 +# define STM32_SRAM_END ((void*)0x20010000) + +#elif defined(MCU_STM32F103CB) + /* This STM32_NR_GPIO_PORTS is not stricly true, but only pins 0 + * and exist, and they're used for OSC (e.g. on e.g. LeafLabs + * Maple Mini), so we'll live with this for now. */ +# define STM32_NR_GPIO_PORTS 3 +# define STM32_SRAM_END ((void*)0x20005000) + +#elif defined(MCU_STM32F103RE) +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20010000) + +#else +#error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ + "-DMCU_STM32F103RB to your compiler arguments." +#endif + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.2.3 From a614806f9a02967bf1b91561dcb3d02a2f735c66 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 28 Nov 2011 23:01:56 -0500 Subject: libmaple/flash.h: Doxygen fixups. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index bbe516d..01d45f5 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -25,9 +25,8 @@ *****************************************************************************/ /** - * @file flash.h - * @brief STM32 Medium and high density Flash register map and setup - * routines + * @file libmaple/flash.h + * @brief Flash support. */ #ifndef _LIBMAPLE_FLASH_H_ -- cgit v1.2.3 From ea175caf4bbcc3b32c161dd52cb773fa8fdba707 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 28 Nov 2011 23:21:21 -0500 Subject: libmaple/flash: Add family-specific FLASH_SAFE_WAIT_STATES. This is the smallest wait state value that is safe for use when the MCU is at its fastest rate, not considering overclocking. This requires moving the FLASH_WAIT_STATE defines above the family include, so do that, and add the missing #defines (for wait states up to 7). For the STM32F1, the correct value for FLASH_SAFE_WAIT_STATES is FLASH_WAIT_STATE_2; say so in the F1-family flash.h. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 19 ++++++++++++++----- libmaple/stm32f1/include/family/flash.h | 9 ++++++++- 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index 01d45f5..66d5b8e 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -36,16 +36,25 @@ extern "C"{ #endif -#include #include -/* - * Setup routines - */ - #define FLASH_WAIT_STATE_0 0x0 #define FLASH_WAIT_STATE_1 0x1 #define FLASH_WAIT_STATE_2 0x2 +#define FLASH_WAIT_STATE_3 0x3 +#define FLASH_WAIT_STATE_4 0x4 +#define FLASH_WAIT_STATE_5 0x5 +#define FLASH_WAIT_STATE_6 0x6 +#define FLASH_WAIT_STATE_7 0x7 + +/* The family header must define FLASH_SAFE_WAIT_STATES, the smallest + * number of wait states that it is safe to use when the MCU clock is + * at its fastest rate (not considering overclocking). */ +#include + +/* + * Setup routines + */ void flash_enable_prefetch(void); void flash_set_latency(uint32 wait_states); diff --git a/libmaple/stm32f1/include/family/flash.h b/libmaple/stm32f1/include/family/flash.h index aedb326..918a434 100644 --- a/libmaple/stm32f1/include/family/flash.h +++ b/libmaple/stm32f1/include/family/flash.h @@ -29,7 +29,8 @@ * @brief STM32F1 Flash header. * * Provides register map, base pointer, and register bit definitions - * for the Flash controller on the STM32F1 line. + * for the Flash controller on the STM32F1 line, along with + * family-specific configuration values. */ #ifndef _LIBMAPLE_STM32F1_FLASH_H_ @@ -128,6 +129,12 @@ typedef struct flash_reg_map { #define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) #define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) +/* + * Family-specific configuration values. + */ + +#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_2 + #ifdef __cplusplus } #endif -- cgit v1.2.3 From fc966dffb9840f73b74112e5ee121fc1443544d4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 28 Nov 2011 23:21:58 -0500 Subject: wirish/boards.cpp: Use FLASH_SAFE_WAIT_STATES. Do this instead of hard-coding a number of wait states to use in setupFlash(), which is called by init(). This helps future-proof. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 1f97119..dd3f21d 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -75,7 +75,7 @@ bool boardUsesPin(uint8 pin) { static void setupFlash(void) { flash_enable_prefetch(); - flash_set_latency(FLASH_WAIT_STATE_2); + flash_set_latency(FLASH_SAFE_WAIT_STATES); } /* -- cgit v1.2.3 From 626f742037878dfe67c3c133fc9768fa0c0e6d88 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 00:48:52 -0500 Subject: boards.cpp: Remove implementation details from Doxygen comments. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/wirish/boards.cpp b/wirish/boards.cpp index dd3f21d..5d5ecb5 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -27,9 +27,15 @@ /** * @brief Generic board initialization routines. * - * By default, we bring up all Maple boards to 72MHz, clocked off the - * PLL, driven by the 8MHz external crystal. AHB and APB2 are clocked - * at 72MHz. APB1 is clocked at 36MHz. + * This file is mostly interesting for the init() function, which + * configures Flash, the core sytem clocks, and a variety of other + * available peripherals on the board so the rest of Wirish doesn't + * have to turn things on before using them. + * + * Prior to returning, init() calls boardInit(), which allows boards + * to perform any initialization they need to. + * + * Specifically how init() works varies across boards and MCUs. */ #include @@ -82,9 +88,6 @@ static void setupFlash(void) { * Clock setup. Note that some of this only takes effect if we're * running bare metal and the bootloader hasn't done it for us * already. - * - * If you change this function, you MUST change the file-level Doxygen - * comment above. */ static void setupClocks() { rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); -- cgit v1.2.3 From c2a937bbb56294df10eec082ab23c353edf4629b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 02:06:33 -0500 Subject: Great renaming: use "series" instead of "family". This is for greater consistency with the ST application notes, which refer to migrating "across" series (e.g. F1 to F2), but compatibility "within" a family (e.g. F1). So: - Move libmaple/stm32x/include/family to .../include/series/ and fix up includes appropriately. - Refer to "family" headers as "series" headers in comments. - Make similar "find and replace"-style changes to build system variable names and comments. - Move support/ld/stm32/family to .../stm32/series. Signed-off-by: Marti Bolivar --- Makefile | 4 +- libmaple/include/libmaple/flash.h | 4 +- libmaple/include/libmaple/gpio.h | 6 +- libmaple/include/libmaple/nvic.h | 10 +- libmaple/include/libmaple/rcc.h | 6 +- libmaple/include/libmaple/stm32.h | 6 +- libmaple/rules.mk | 2 +- libmaple/stm32f1/include/family/flash.h | 142 ------ libmaple/stm32f1/include/family/gpio.h | 479 ------------------ libmaple/stm32f1/include/family/nvic.h | 139 ------ libmaple/stm32f1/include/family/rcc.h | 553 --------------------- libmaple/stm32f1/include/family/stm32.h | 100 ---- libmaple/stm32f1/include/series/flash.h | 142 ++++++ libmaple/stm32f1/include/series/gpio.h | 479 ++++++++++++++++++ libmaple/stm32f1/include/series/nvic.h | 139 ++++++ libmaple/stm32f1/include/series/rcc.h | 553 +++++++++++++++++++++ libmaple/stm32f1/include/series/stm32.h | 100 ++++ .../stm32/family/f1/performance/vector_symbols.inc | 78 --- .../stm32/series/f1/performance/vector_symbols.inc | 78 +++ support/make/target-config.mk | 6 +- 20 files changed, 1513 insertions(+), 1513 deletions(-) delete mode 100644 libmaple/stm32f1/include/family/flash.h delete mode 100644 libmaple/stm32f1/include/family/gpio.h delete mode 100644 libmaple/stm32f1/include/family/nvic.h delete mode 100644 libmaple/stm32f1/include/family/rcc.h delete mode 100644 libmaple/stm32f1/include/family/stm32.h create mode 100644 libmaple/stm32f1/include/series/flash.h create mode 100644 libmaple/stm32f1/include/series/gpio.h create mode 100644 libmaple/stm32f1/include/series/nvic.h create mode 100644 libmaple/stm32f1/include/series/rcc.h create mode 100644 libmaple/stm32f1/include/series/stm32.h delete mode 100644 support/ld/stm32/family/f1/performance/vector_symbols.inc create mode 100644 support/ld/stm32/series/f1/performance/vector_symbols.inc diff --git a/Makefile b/Makefile index 2525c2e..1e00ed6 100644 --- a/Makefile +++ b/Makefile @@ -55,7 +55,7 @@ GLOBAL_CXXFLAGS := -fno-rtti -fno-exceptions -Wall $(TARGET_FLAGS) GLOBAL_ASFLAGS := -mcpu=cortex-m3 -march=armv7-m -mthumb \ -x assembler-with-cpp $(TARGET_FLAGS) LDFLAGS = -T$(LDDIR)/$(LDSCRIPT) -L$(LDDIR) \ - -mcpu=cortex-m3 -mthumb -Xlinker -L $(LD_FAMILY_PATH) \ + -mcpu=cortex-m3 -mthumb -Xlinker -L $(LD_SERIES_PATH) \ --gc-sections --print-gc-sections --march=armv7-m -Wall ## @@ -76,7 +76,7 @@ else LIBMAPLE_MODULES += $(SRCROOT)/libmaple endif LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # USB FS device -LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_FAMILY) # family submodule in libmaple +LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_SERIES) # STM32 series submodule in libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish # Official libraries: LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index 66d5b8e..97bfa26 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -47,10 +47,10 @@ extern "C"{ #define FLASH_WAIT_STATE_6 0x6 #define FLASH_WAIT_STATE_7 0x7 -/* The family header must define FLASH_SAFE_WAIT_STATES, the smallest +/* The series header must define FLASH_SAFE_WAIT_STATES, the smallest * number of wait states that it is safe to use when the MCU clock is * at its fastest rate (not considering overclocking). */ -#include +#include /* * Setup routines diff --git a/libmaple/include/libmaple/gpio.h b/libmaple/include/libmaple/gpio.h index e821ad4..609320f 100644 --- a/libmaple/include/libmaple/gpio.h +++ b/libmaple/include/libmaple/gpio.h @@ -37,11 +37,11 @@ extern "C"{ #endif /* - * Note: Family header must define: - * - struct gpio_dev (and declare extern pointers to family-provided ones) + * Note: Series header must define: + * - struct gpio_dev (and declare extern pointers to series-provided ones) * - enum gpio_pin_mode (TODO think hard on this) */ -#include +#include #include /* diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h index 23425df..1a1a4ed 100644 --- a/libmaple/include/libmaple/nvic.h +++ b/libmaple/include/libmaple/nvic.h @@ -74,18 +74,18 @@ typedef struct nvic_reg_map { #define NVIC_BASE ((struct nvic_reg_map*)0xE000E100) /* - * Note: The family header must define enum nvic_irq_num, which gives + * Note: The series header must define enum nvic_irq_num, which gives * descriptive names to the interrupts and exceptions from NMI (-14) - * to the largest interrupt available in the family, where the value + * to the largest interrupt available in the series, where the value * for nonnegative enumerators corresponds to its position in the * vector table. * * It also must define a static inline nvic_irq_disable_all(), which - * writes 0xFFFFFFFF to all ICE registers available in the family. (We - * place the include here to give the family header access to + * writes 0xFFFFFFFF to all ICE registers available in the series. (We + * place the include here to give the series header access to * NVIC_BASE, in order to let it do so). */ -#include +#include void nvic_init(uint32 address, uint32 offset); void nvic_set_vector_table(uint32 address, uint32 offset); diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index a4b66e5..08f7c7e 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -37,9 +37,9 @@ extern "C"{ #endif #include -#include +#include -/* Note: Beyond the usual (registers, etc.), it's up to the family +/* Note: Beyond the usual (registers, etc.), it's up to the series * header to define the following types: * * - rcc_pllsrc: For each PLL source (passed to rcc_clk_init()). @@ -49,7 +49,7 @@ extern "C"{ * - rcc_clk_id: For each available peripheral. These are widely used * as unique IDs (TODO extricate from RCC?). Peripherals which are * common across families should use the same token for their - * rcc_clk_id in each family header. + * rcc_clk_id in each series header. * * - rcc_clk_domain: For each clock domain (returned by rcc_dev_clk()). * diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 5efb670..356a360 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -37,8 +37,8 @@ extern "C" { #endif /* Everything enclosed in the following __DOXYGEN_PREDEFINED_HACK - * conditional block must be defined in the family header. */ -#include + * conditional block must be defined in the series header. */ +#include #ifdef __DOXYGEN_PREDEFINED_HACK @@ -66,7 +66,7 @@ extern "C" { #define PCLK2 /* - * Family- and MCU-specific values. + * Series- and MCU-specific values. */ /** diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 3ca5b3a..f0776a7 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -4,7 +4,7 @@ dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) -LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include -I$(LIBMAPLE_MODULE_FAMILY)/include +LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH)/include -I$(LIBMAPLE_MODULE_SERIES)/include LIBMAPLE_PRIVATE_INCLUDES := -I$(LIBMAPLE_PATH) # Local flags diff --git a/libmaple/stm32f1/include/family/flash.h b/libmaple/stm32f1/include/family/flash.h deleted file mode 100644 index 918a434..0000000 --- a/libmaple/stm32f1/include/family/flash.h +++ /dev/null @@ -1,142 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f1/flash.h - * @brief STM32F1 Flash header. - * - * Provides register map, base pointer, and register bit definitions - * for the Flash controller on the STM32F1 line, along with - * family-specific configuration values. - */ - -#ifndef _LIBMAPLE_STM32F1_FLASH_H_ -#define _LIBMAPLE_STM32F1_FLASH_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/* - * Register map - */ - -/** Flash register map type */ -typedef struct flash_reg_map { - __io uint32 ACR; /**< Access control register */ - __io uint32 KEYR; /**< Key register */ - __io uint32 OPTKEYR; /**< OPTKEY register */ - __io uint32 SR; /**< Status register */ - __io uint32 CR; /**< Control register */ - __io uint32 AR; /**< Address register */ - __io uint32 OBR; /**< Option byte register */ - __io uint32 WRPR; /**< Write protection register */ -} flash_reg_map; - -/** Flash register map base pointer */ -#define FLASH_BASE ((struct flash_reg_map*)0x40022000) - -/* - * Register bit definitions - */ - -/* Access control register */ - -#define FLASH_ACR_PRFTBS_BIT 5 -#define FLASH_ACR_PRFTBE_BIT 4 -#define FLASH_ACR_HLFCYA_BIT 3 - -#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) -#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) -#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) -#define FLASH_ACR_LATENCY 0x7 - -/* Status register */ - -#define FLASH_SR_EOP_BIT 5 -#define FLASH_SR_WRPRTERR_BIT 4 -#define FLASH_SR_PGERR_BIT 2 -#define FLASH_SR_BSY_BIT 0 - -#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) -#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) -#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) -#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) - -/* Control register */ - -#define FLASH_CR_EOPIE_BIT 12 -#define FLASH_CR_ERRIE_BIT 10 -#define FLASH_CR_OPTWRE_BIT 9 -#define FLASH_CR_LOCK_BIT 7 -#define FLASH_CR_STRT_BIT 6 -#define FLASH_CR_OPTER_BIT 5 -#define FLASH_CR_OPTPG_BIT 4 -#define FLASH_CR_MER_BIT 2 -#define FLASH_CR_PER_BIT 1 -#define FLASH_CR_PG_BIT 0 - -#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) -#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) -#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) -#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) -#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) -#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) -#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) -#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) -#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) -#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) - -/* Option byte register */ - -#define FLASH_OBR_nRST_STDBY_BIT 4 -#define FLASH_OBR_nRST_STOP_BIT 3 -#define FLASH_OBR_WDG_SW_BIT 2 -#define FLASH_OBR_RDPRT_BIT 1 -#define FLASH_OBR_OPTERR_BIT 0 - -#define FLASH_OBR_DATA1 (0xFF << 18) -#define FLASH_OBR_DATA0 (0xFF << 10) -#define FLASH_OBR_USER 0x3FF -#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) -#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) -#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) -#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) -#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) - -/* - * Family-specific configuration values. - */ - -#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_2 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/stm32f1/include/family/gpio.h b/libmaple/stm32f1/include/family/gpio.h deleted file mode 100644 index c10244d..0000000 --- a/libmaple/stm32f1/include/family/gpio.h +++ /dev/null @@ -1,479 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. -*****************************************************************************/ - -/** - * @file libmaple/stm32f1/gpio.h - * @brief General purpose I/O (GPIO) and Alternate Function I/O - * (AFIO) prototypes, defines, and inlined access functions. - */ - -#ifndef _LIBMAPLE_STM32F1_GPIO_H_ -#define _LIBMAPLE_STM32F1_GPIO_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include -#include - -/* - * GPIO register maps and devices - */ - -/** GPIO register map type */ -typedef struct gpio_reg_map { - __io uint32 CRL; /**< Port configuration register low */ - __io uint32 CRH; /**< Port configuration register high */ - __io uint32 IDR; /**< Port input data register */ - __io uint32 ODR; /**< Port output data register */ - __io uint32 BSRR; /**< Port bit set/reset register */ - __io uint32 BRR; /**< Port bit reset register */ - __io uint32 LCKR; /**< Port configuration lock register */ -} gpio_reg_map; - -/** - * @brief External interrupt line port selector. - * - * Used to determine which GPIO port to map an external interrupt line - * onto. */ -/* (See AFIO sections, below) */ -typedef enum afio_exti_port { - AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ - AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ - AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ - AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ -#ifdef STM32_HIGH_DENSITY - AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ - AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ - AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ -#endif -} afio_exti_port; - -/** GPIO device type */ -typedef struct gpio_dev { - gpio_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ - afio_exti_port exti_port; /**< AFIO external interrupt port value */ -} gpio_dev; - -extern gpio_dev gpioa; -extern gpio_dev* const GPIOA; -extern gpio_dev gpiob; -extern gpio_dev* const GPIOB; -extern gpio_dev gpioc; -extern gpio_dev* const GPIOC; -extern gpio_dev gpiod; -extern gpio_dev* const GPIOD; -#ifdef STM32_HIGH_DENSITY -extern gpio_dev gpioe; -extern gpio_dev* const GPIOE; -extern gpio_dev gpiof; -extern gpio_dev* const GPIOF; -extern gpio_dev gpiog; -extern gpio_dev* const GPIOG; -#endif - -/** GPIO port A register map base pointer */ -#define GPIOA_BASE ((struct gpio_reg_map*)0x40010800) -/** GPIO port B register map base pointer */ -#define GPIOB_BASE ((struct gpio_reg_map*)0x40010C00) -/** GPIO port C register map base pointer */ -#define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) -/** GPIO port D register map base pointer */ -#define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) -#ifdef STM32_HIGH_DENSITY -/** GPIO port E register map base pointer */ -#define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) -/** GPIO port F register map base pointer */ -#define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) -/** GPIO port G register map base pointer */ -#define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) -#endif - -/* - * GPIO register bit definitions - */ - -/* Control registers, low and high */ - -#define GPIO_CR_CNF (0x3 << 2) -#define GPIO_CR_CNF_INPUT_ANALOG (0x0 << 2) -#define GPIO_CR_CNF_INPUT_FLOATING (0x1 << 2) -#define GPIO_CR_CNF_INPUT_PU_PD (0x2 << 2) -#define GPIO_CR_CNF_OUTPUT_PP (0x0 << 2) -#define GPIO_CR_CNF_OUTPUT_OD (0x1 << 2) -#define GPIO_CR_CNF_AF_OUTPUT_PP (0x2 << 2) -#define GPIO_CR_CNF_AF_OUTPUT_OD (0x3 << 2) -#define GPIO_CR_MODE 0x3 -#define GPIO_CR_MODE_INPUT 0x0 -#define GPIO_CR_MODE_OUTPUT_10MHZ 0x1 -#define GPIO_CR_MODE_OUTPUT_2MHZ 0x2 -#define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 - -/** - * @brief GPIO Pin modes. - * - * These only allow for 50MHZ max output speeds; if you want slower, - * use direct register access. - */ -typedef enum gpio_pin_mode { - GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ - GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ - GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output push-pull. */ - GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output open drain. */ - GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | - GPIO_CR_MODE_INPUT), /**< Analog input. */ - GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | - GPIO_CR_MODE_INPUT), /**< Input floating. */ - GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | - GPIO_CR_MODE_INPUT), /**< Input pull-down. */ - GPIO_INPUT_PU /**< Input pull-up. */ - /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ -} gpio_pin_mode; - -/** - * @brief Get a GPIO port's corresponding afio_exti_port. - * @param dev GPIO device whose afio_exti_port to return. - */ -static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { - return dev->exti_port; -} - -/* - * AFIO register map - */ - -/** AFIO register map */ -typedef struct afio_reg_map { - __io uint32 EVCR; /**< Event control register. */ - __io uint32 MAPR; /**< AF remap and debug I/O configuration - register. */ - __io uint32 EXTICR1; /**< External interrupt configuration - register 1. */ - __io uint32 EXTICR2; /**< External interrupt configuration - register 2. */ - __io uint32 EXTICR3; /**< External interrupt configuration - register 3. */ - __io uint32 EXTICR4; /**< External interrupt configuration - register 4. */ - __io uint32 MAPR2; /**< AF remap and debug I/O configuration - register 2. */ -} afio_reg_map; - -/** AFIO register map base pointer. */ -#define AFIO_BASE ((struct afio_reg_map *)0x40010000) - -/* - * AFIO register bit definitions - */ - -/* Event control register */ - -#define AFIO_EVCR_EVOE (0x1 << 7) -#define AFIO_EVCR_PORT_PA (0x0 << 4) -#define AFIO_EVCR_PORT_PB (0x1 << 4) -#define AFIO_EVCR_PORT_PC (0x2 << 4) -#define AFIO_EVCR_PORT_PD (0x3 << 4) -#define AFIO_EVCR_PORT_PE (0x4 << 4) -#define AFIO_EVCR_PIN_0 0x0 -#define AFIO_EVCR_PIN_1 0x1 -#define AFIO_EVCR_PIN_2 0x2 -#define AFIO_EVCR_PIN_3 0x3 -#define AFIO_EVCR_PIN_4 0x4 -#define AFIO_EVCR_PIN_5 0x5 -#define AFIO_EVCR_PIN_6 0x6 -#define AFIO_EVCR_PIN_7 0x7 -#define AFIO_EVCR_PIN_8 0x8 -#define AFIO_EVCR_PIN_9 0x9 -#define AFIO_EVCR_PIN_10 0xA -#define AFIO_EVCR_PIN_11 0xB -#define AFIO_EVCR_PIN_12 0xC -#define AFIO_EVCR_PIN_13 0xD -#define AFIO_EVCR_PIN_14 0xE -#define AFIO_EVCR_PIN_15 0xF - -/* AF remap and debug I/O configuration register */ - -#define AFIO_MAPR_SWJ_CFG (0x7 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) -#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) -#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) -#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) -#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) -#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) -#define AFIO_MAPR_PD01_REMAP BIT(15) -#define AFIO_MAPR_CAN_REMAP (0x3 << 13) -#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) -#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) -#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) -#define AFIO_MAPR_TIM4_REMAP BIT(12) -#define AFIO_MAPR_TIM3_REMAP (0x3 << 10) -#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) -#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) -#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10) -#define AFIO_MAPR_TIM2_REMAP (0x3 << 8) -#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8) -#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8) -#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8) -#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8) -#define AFIO_MAPR_TIM1_REMAP (0x3 << 6) -#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6) -#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6) -#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6) -#define AFIO_MAPR_USART3_REMAP (0x3 << 4) -#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) -#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) -#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) -#define AFIO_MAPR_USART2_REMAP BIT(3) -#define AFIO_MAPR_USART1_REMAP BIT(2) -#define AFIO_MAPR_I2C1_REMAP BIT(1) -#define AFIO_MAPR_SPI1_REMAP BIT(0) - -/* External interrupt configuration register 1 */ - -#define AFIO_EXTICR1_EXTI3 (0xF << 12) -#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12) -#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12) -#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12) -#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12) -#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12) -#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12) -#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12) -#define AFIO_EXTICR1_EXTI2 (0xF << 8) -#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8) -#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8) -#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8) -#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8) -#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8) -#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8) -#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8) -#define AFIO_EXTICR1_EXTI1 (0xF << 4) -#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4) -#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4) -#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4) -#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4) -#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4) -#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4) -#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4) -#define AFIO_EXTICR1_EXTI0 0xF -#define AFIO_EXTICR1_EXTI0_PA 0x0 -#define AFIO_EXTICR1_EXTI0_PB 0x1 -#define AFIO_EXTICR1_EXTI0_PC 0x2 -#define AFIO_EXTICR1_EXTI0_PD 0x3 -#define AFIO_EXTICR1_EXTI0_PE 0x4 -#define AFIO_EXTICR1_EXTI0_PF 0x5 -#define AFIO_EXTICR1_EXTI0_PG 0x6 - -/* External interrupt configuration register 2 */ - -#define AFIO_EXTICR2_EXTI7 (0xF << 12) -#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12) -#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12) -#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12) -#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12) -#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12) -#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12) -#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12) -#define AFIO_EXTICR2_EXTI6 (0xF << 8) -#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8) -#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8) -#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8) -#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8) -#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8) -#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8) -#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8) -#define AFIO_EXTICR2_EXTI5 (0xF << 4) -#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4) -#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4) -#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4) -#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4) -#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4) -#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4) -#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4) -#define AFIO_EXTICR2_EXTI4 0xF -#define AFIO_EXTICR2_EXTI4_PA 0x0 -#define AFIO_EXTICR2_EXTI4_PB 0x1 -#define AFIO_EXTICR2_EXTI4_PC 0x2 -#define AFIO_EXTICR2_EXTI4_PD 0x3 -#define AFIO_EXTICR2_EXTI4_PE 0x4 -#define AFIO_EXTICR2_EXTI4_PF 0x5 -#define AFIO_EXTICR2_EXTI4_PG 0x6 - -/* AF remap and debug I/O configuration register 2 */ - -#define AFIO_MAPR2_FSMC_NADV BIT(10) -#define AFIO_MAPR2_TIM14_REMAP BIT(9) -#define AFIO_MAPR2_TIM13_REMAP BIT(8) -#define AFIO_MAPR2_TIM11_REMAP BIT(7) -#define AFIO_MAPR2_TIM10_REMAP BIT(6) -#define AFIO_MAPR2_TIM9_REMAP BIT(5) - -/* - * AFIO convenience routines - */ - -void afio_init(void); - -/** - * External interrupt line numbers. - */ -typedef enum afio_exti_num { - AFIO_EXTI_0, /**< External interrupt line 0. */ - AFIO_EXTI_1, /**< External interrupt line 1. */ - AFIO_EXTI_2, /**< External interrupt line 2. */ - AFIO_EXTI_3, /**< External interrupt line 3. */ - AFIO_EXTI_4, /**< External interrupt line 4. */ - AFIO_EXTI_5, /**< External interrupt line 5. */ - AFIO_EXTI_6, /**< External interrupt line 6. */ - AFIO_EXTI_7, /**< External interrupt line 7. */ - AFIO_EXTI_8, /**< External interrupt line 8. */ - AFIO_EXTI_9, /**< External interrupt line 9. */ - AFIO_EXTI_10, /**< External interrupt line 10. */ - AFIO_EXTI_11, /**< External interrupt line 11. */ - AFIO_EXTI_12, /**< External interrupt line 12. */ - AFIO_EXTI_13, /**< External interrupt line 13. */ - AFIO_EXTI_14, /**< External interrupt line 14. */ - AFIO_EXTI_15, /**< External interrupt line 15. */ -} afio_exti_num; - -void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); - -/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and - * not used in either MAPR or MAPR2 */ -#define AFIO_REMAP_USE_MAPR2 (1 << 31) - -/** - * @brief Available peripheral remaps. - * @see afio_remap() - */ -typedef enum afio_remap_peripheral { - AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< - ADC 2 external trigger regular conversion remapping */ - AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< - ADC 2 external trigger injected conversion remapping */ - AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< - ADC 1 external trigger regular conversion remapping */ - AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< - ADC 1 external trigger injected conversion remapping */ - AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< - Timer 5 channel 4 internal remapping */ - AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< - Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< - CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ - AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< - CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ - AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< - Timer 4 remapping */ - AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< - Timer 3 partial remapping */ - AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< - Timer 3 full remapping */ - AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< - Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 - on PA2, CH4 on PA3) */ - AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< - Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 - on PB10, CH4 on PB11) */ - AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< - Timer 2 full remapping */ - AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< - USART 2 remapping */ - AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< - USART 1 remapping */ - AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< - I2C 1 remapping */ - AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< - SPI 1 remapping */ - AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | - AFIO_REMAP_USE_MAPR2), /**< - NADV signal not connected */ - AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 14 remapping */ - AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 13 remapping */ - AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 11 remapping */ - AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 10 remapping */ - AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | - AFIO_REMAP_USE_MAPR2) /**< - Timer 9 */ -} afio_remap_peripheral; - -void afio_remap(afio_remap_peripheral p); - -/** - * @brief Debug port configuration - * - * Used to configure the behavior of JTAG and Serial Wire (SW) debug - * ports and their associated GPIO pins. - * - * @see afio_cfg_debug_ports() - */ -typedef enum afio_debug_cfg { - AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< - Full Serial Wire and JTAG debug */ - AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< - Full Serial Wire and JTAG, but no NJTRST. */ - AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< - Serial Wire debug only (JTAG-DP disabled, - SW-DP enabled) */ - AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< - No debug; all JTAG and SW pins are free - for use as GPIOs. */ -} afio_debug_cfg; - -/** - * @brief Enable or disable the JTAG and SW debug ports. - * @param config Desired debug port configuration - * @see afio_debug_cfg - */ -static inline void afio_cfg_debug_ports(afio_debug_cfg config) { - __io uint32 *mapr = &AFIO_BASE->MAPR; - *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/stm32f1/include/family/nvic.h b/libmaple/stm32f1/include/family/nvic.h deleted file mode 100644 index 69fd945..0000000 --- a/libmaple/stm32f1/include/family/nvic.h +++ /dev/null @@ -1,139 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f1/nvic.h - * @brief STM32F1 Nested Vectored Interrupt Controller (NVIC) support. - */ - -#ifndef _LIBMAPLE_STM32F1_NVIC_H_ -#define _LIBMAPLE_STM32F1_NVIC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/** - * @brief Interrupt vector table interrupt numbers. - * @see - */ -typedef enum nvic_irq_num { - NVIC_NMI = -14, /**< Non-maskable interrupt */ - NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ - NVIC_MEM_MANAGE = -12, /**< Memory management */ - NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory - access fault. */ - NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction or - illegal state. */ - NVIC_SVC = -5, /**< System service call via SWI insruction */ - NVIC_DEBUG_MON = -4, /**< Debug monitor */ - NVIC_PEND_SVC = -2, /**< Pendable request for system service */ - NVIC_SYSTICK = -1, /**< System tick timer */ - NVIC_WWDG = 0, /**< Window watchdog interrupt */ - NVIC_PVD = 1, /**< PVD through EXTI line detection */ - NVIC_TAMPER = 2, /**< Tamper */ - NVIC_RTC = 3, /**< Real-time clock */ - NVIC_FLASH = 4, /**< Flash */ - NVIC_RCC = 5, /**< Reset and clock control */ - NVIC_EXTI0 = 6, /**< EXTI line 0 */ - NVIC_EXTI1 = 7, /**< EXTI line 1 */ - NVIC_EXTI2 = 8, /**< EXTI line 2 */ - NVIC_EXTI3 = 9, /**< EXTI line 3 */ - NVIC_EXTI4 = 10, /**< EXTI line 4 */ - NVIC_DMA_CH1 = 11, /**< DMA1 channel 1 */ - NVIC_DMA_CH2 = 12, /**< DMA1 channel 2 */ - NVIC_DMA_CH3 = 13, /**< DMA1 channel 3 */ - NVIC_DMA_CH4 = 14, /**< DMA1 channel 4 */ - NVIC_DMA_CH5 = 15, /**< DMA1 channel 5 */ - NVIC_DMA_CH6 = 16, /**< DMA1 channel 6 */ - NVIC_DMA_CH7 = 17, /**< DMA1 channel 7 */ - NVIC_ADC_1_2 = 18, /**< ADC1 and ADC2 */ - NVIC_USB_HP_CAN_TX = 19, /**< USB high priority or CAN TX */ - NVIC_USB_LP_CAN_RX0 = 20, /**< USB low priority or CAN RX0 */ - NVIC_CAN_RX1 = 21, /**< CAN RX1 */ - NVIC_CAN_SCE = 22, /**< CAN SCE */ - NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ - NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ - NVIC_TIMER1_UP = 25, /**< Timer 1 update */ - NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ - NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ - NVIC_TIMER2 = 28, /**< Timer 2 */ - NVIC_TIMER3 = 29, /**< Timer 3 */ - NVIC_TIMER4 = 30, /**< Timer 4 */ - NVIC_I2C1_EV = 31, /**< I2C1 event */ - NVIC_I2C1_ER = 32, /**< I2C1 error */ - NVIC_I2C2_EV = 33, /**< I2C2 event */ - NVIC_I2C2_ER = 34, /**< I2C2 error */ - NVIC_SPI1 = 35, /**< SPI1 */ - NVIC_SPI2 = 36, /**< SPI2 */ - NVIC_USART1 = 37, /**< USART1 */ - NVIC_USART2 = 38, /**< USART2 */ - NVIC_USART3 = 39, /**< USART3 */ - NVIC_EXTI_15_10 = 40, /**< EXTI line [15:10] */ - NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ - NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through - EXTI line */ - NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ - NVIC_TIMER8_UP = 44, /**< Timer 8 update */ - NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ - NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ -#ifdef STM32_HIGH_DENSITY - NVIC_ADC3 = 47, /**< ADC3 */ - NVIC_FSMC = 48, /**< FSMC */ - NVIC_SDIO = 49, /**< SDIO */ - NVIC_TIMER5 = 50, /**< Timer 5 */ - NVIC_SPI3 = 51, /**< SPI3 */ - NVIC_UART4 = 52, /**< UART4 */ - NVIC_UART5 = 53, /**< UART5 */ - NVIC_TIMER6 = 54, /**< Timer 6 */ - NVIC_TIMER7 = 55, /**< Timer 7 */ - NVIC_DMA2_CH1 = 56, /**< DMA2 channel 1 */ - NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ - NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ - NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ -#endif -} nvic_irq_num; - -static inline void nvic_irq_disable_all(void) { - /* Note: This only works up to XL density. The fix for - * connectivity line is: - * - * NVIC_BASE->ICER[2] = 0xF; - * - * We don't support connectivity line devices (yet), so leave it - * alone for now. - */ - NVIC_BASE->ICER[0] = 0xFFFFFFFF; - NVIC_BASE->ICER[1] = 0xFFFFFFFF; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/stm32f1/include/family/rcc.h b/libmaple/stm32f1/include/family/rcc.h deleted file mode 100644 index 261dc5d..0000000 --- a/libmaple/stm32f1/include/family/rcc.h +++ /dev/null @@ -1,553 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f1/rcc.h - * @brief STM32F1 reset and clock control (RCC) header. - */ - -#ifndef _LIBMAPLE_STM32F1_RCC_H_ -#define _LIBMAPLE_STM32F1_RCC_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -/* - * Register map - */ - -/** RCC register map type */ -typedef struct rcc_reg_map { - __io uint32 CR; /**< Clock control register */ - __io uint32 CFGR; /**< Clock configuration register */ - __io uint32 CIR; /**< Clock interrupt register */ - __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ - __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ - __io uint32 AHBENR; /**< AHB peripheral clock enable register */ - __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ - __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ - __io uint32 BDCR; /**< Backup domain control register */ - __io uint32 CSR; /**< Control/status register */ -} rcc_reg_map; - -/** RCC register map base pointer */ -#define RCC_BASE ((struct rcc_reg_map*)0x40021000) - -/* - * Register bit definitions - */ - -/* Clock control register */ - -#define RCC_CR_PLLRDY_BIT 25 -#define RCC_CR_PLLON_BIT 24 -#define RCC_CR_CSSON_BIT 19 -#define RCC_CR_HSEBYP_BIT 18 -#define RCC_CR_HSERDY_BIT 17 -#define RCC_CR_HSEON_BIT 16 -#define RCC_CR_HSIRDY_BIT 1 -#define RCC_CR_HSION_BIT 0 - -#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) -#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) -#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) -#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) -#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) -#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) -#define RCC_CR_HSICAL (0xFF << 8) -#define RCC_CR_HSITRIM (0x1F << 3) -#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) -#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) - -/* Clock configuration register */ - -#define RCC_CFGR_USBPRE_BIT 22 -#define RCC_CFGR_PLLXTPRE_BIT 17 -#define RCC_CFGR_PLLSRC_BIT 16 - -#define RCC_CFGR_MCO (0x3 << 24) -#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) -#define RCC_CFGR_PLLMUL (0xF << 18) -#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) -#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) -#define RCC_CFGR_ADCPRE (0x3 << 14) -#define RCC_CFGR_PPRE2 (0x7 << 11) -#define RCC_CFGR_PPRE1 (0x7 << 8) -#define RCC_CFGR_HPRE (0xF << 4) -#define RCC_CFGR_SWS (0x3 << 2) -#define RCC_CFGR_SWS_PLL (0x2 << 2) -#define RCC_CFGR_SWS_HSE (0x1 << 2) -#define RCC_CFGR_SW 0x3 -#define RCC_CFGR_SW_PLL 0x2 -#define RCC_CFGR_SW_HSE 0x1 - -/* Clock interrupt register */ - -#define RCC_CIR_CSSC_BIT 23 -#define RCC_CIR_PLLRDYC_BIT 20 -#define RCC_CIR_HSERDYC_BIT 19 -#define RCC_CIR_HSIRDYC_BIT 18 -#define RCC_CIR_LSERDYC_BIT 17 -#define RCC_CIR_LSIRDYC_BIT 16 -#define RCC_CIR_PLLRDYIE_BIT 12 -#define RCC_CIR_HSERDYIE_BIT 11 -#define RCC_CIR_HSIRDYIE_BIT 10 -#define RCC_CIR_LSERDYIE_BIT 9 -#define RCC_CIR_LSIRDYIE_BIT 8 -#define RCC_CIR_CSSF_BIT 7 -#define RCC_CIR_PLLRDYF_BIT 4 -#define RCC_CIR_HSERDYF_BIT 3 -#define RCC_CIR_HSIRDYF_BIT 2 -#define RCC_CIR_LSERDYF_BIT 1 -#define RCC_CIR_LSIRDYF_BIT 0 - -#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) -#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) -#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) -#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) -#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) -#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) -#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) -#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) -#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) -#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) -#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) -#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) -#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) -#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) -#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) -#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) -#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) - -/* APB2 peripheral reset register */ - -#define RCC_APB2RSTR_TIM11RST_BIT 21 -#define RCC_APB2RSTR_TIM10RST_BIT 20 -#define RCC_APB2RSTR_TIM9RST_BIT 19 -#define RCC_APB2RSTR_ADC3RST_BIT 15 -#define RCC_APB2RSTR_USART1RST_BIT 14 -#define RCC_APB2RSTR_TIM8RST_BIT 13 -#define RCC_APB2RSTR_SPI1RST_BIT 12 -#define RCC_APB2RSTR_TIM1RST_BIT 11 -#define RCC_APB2RSTR_ADC2RST_BIT 10 -#define RCC_APB2RSTR_ADC1RST_BIT 9 -#define RCC_APB2RSTR_IOPGRST_BIT 8 -#define RCC_APB2RSTR_IOPFRST_BIT 7 -#define RCC_APB2RSTR_IOPERST_BIT 6 -#define RCC_APB2RSTR_IOPDRST_BIT 5 -#define RCC_APB2RSTR_IOPCRST_BIT 4 -#define RCC_APB2RSTR_IOPBRST_BIT 3 -#define RCC_APB2RSTR_IOPARST_BIT 2 -#define RCC_APB2RSTR_AFIORST_BIT 0 - -#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) -#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) -#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) -#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) -#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) -#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) -#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) -#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) -#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) -#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) -#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) -#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) -#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) -#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) -#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) -#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) -#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) -#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) - -/* APB1 peripheral reset register */ - -#define RCC_APB1RSTR_DACRST_BIT 29 -#define RCC_APB1RSTR_PWRRST_BIT 28 -#define RCC_APB1RSTR_BKPRST_BIT 27 -#define RCC_APB1RSTR_CANRST_BIT 25 -#define RCC_APB1RSTR_USBRST_BIT 23 -#define RCC_APB1RSTR_I2C2RST_BIT 22 -#define RCC_APB1RSTR_I2C1RST_BIT 21 -#define RCC_APB1RSTR_UART5RST_BIT 20 -#define RCC_APB1RSTR_UART4RST_BIT 19 -#define RCC_APB1RSTR_USART3RST_BIT 18 -#define RCC_APB1RSTR_USART2RST_BIT 17 -#define RCC_APB1RSTR_SPI3RST_BIT 15 -#define RCC_APB1RSTR_SPI2RST_BIT 14 -#define RCC_APB1RSTR_WWDRST_BIT 11 -#define RCC_APB1RSTR_TIM14RST_BIT 8 -#define RCC_APB1RSTR_TIM13RST_BIT 7 -#define RCC_APB1RSTR_TIM12RST_BIT 6 -#define RCC_APB1RSTR_TIM7RST_BIT 5 -#define RCC_APB1RSTR_TIM6RST_BIT 4 -#define RCC_APB1RSTR_TIM5RST_BIT 3 -#define RCC_APB1RSTR_TIM4RST_BIT 2 -#define RCC_APB1RSTR_TIM3RST_BIT 1 -#define RCC_APB1RSTR_TIM2RST_BIT 0 - -#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) -#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) -#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) -#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) -#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) -#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) -#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) -#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) -#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) -#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) -#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) -#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) -#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) -#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) -#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) -#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) -#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) -#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) -#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) -#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) -#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) -#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) -#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) - -/* AHB peripheral clock enable register */ - -#define RCC_AHBENR_SDIOEN_BIT 10 -#define RCC_AHBENR_FSMCEN_BIT 8 -#define RCC_AHBENR_CRCEN_BIT 7 -#define RCC_AHBENR_FLITFEN_BIT 4 -#define RCC_AHBENR_SRAMEN_BIT 2 -#define RCC_AHBENR_DMA2EN_BIT 1 -#define RCC_AHBENR_DMA1EN_BIT 0 - -#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) -#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) -#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) -#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) -#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) -#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) -#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) - -/* APB2 peripheral clock enable register */ - -#define RCC_APB2ENR_TIM11EN_BIT 21 -#define RCC_APB2ENR_TIM10EN_BIT 20 -#define RCC_APB2ENR_TIM9EN_BIT 19 -#define RCC_APB2ENR_ADC3EN_BIT 15 -#define RCC_APB2ENR_USART1EN_BIT 14 -#define RCC_APB2ENR_TIM8EN_BIT 13 -#define RCC_APB2ENR_SPI1EN_BIT 12 -#define RCC_APB2ENR_TIM1EN_BIT 11 -#define RCC_APB2ENR_ADC2EN_BIT 10 -#define RCC_APB2ENR_ADC1EN_BIT 9 -#define RCC_APB2ENR_IOPGEN_BIT 8 -#define RCC_APB2ENR_IOPFEN_BIT 7 -#define RCC_APB2ENR_IOPEEN_BIT 6 -#define RCC_APB2ENR_IOPDEN_BIT 5 -#define RCC_APB2ENR_IOPCEN_BIT 4 -#define RCC_APB2ENR_IOPBEN_BIT 3 -#define RCC_APB2ENR_IOPAEN_BIT 2 -#define RCC_APB2ENR_AFIOEN_BIT 0 - -#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) -#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) -#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) -#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) -#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) -#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) -#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) -#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) -#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) -#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) -#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) -#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) -#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) -#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) -#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) -#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) -#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) -#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) - -/* APB1 peripheral clock enable register */ - -#define RCC_APB1ENR_DACEN_BIT 29 -#define RCC_APB1ENR_PWREN_BIT 28 -#define RCC_APB1ENR_BKPEN_BIT 27 -#define RCC_APB1ENR_CANEN_BIT 25 -#define RCC_APB1ENR_USBEN_BIT 23 -#define RCC_APB1ENR_I2C2EN_BIT 22 -#define RCC_APB1ENR_I2C1EN_BIT 21 -#define RCC_APB1ENR_UART5EN_BIT 20 -#define RCC_APB1ENR_UART4EN_BIT 19 -#define RCC_APB1ENR_USART3EN_BIT 18 -#define RCC_APB1ENR_USART2EN_BIT 17 -#define RCC_APB1ENR_SPI3EN_BIT 15 -#define RCC_APB1ENR_SPI2EN_BIT 14 -#define RCC_APB1ENR_WWDEN_BIT 11 -#define RCC_APB1ENR_TIM14EN_BIT 8 -#define RCC_APB1ENR_TIM13EN_BIT 7 -#define RCC_APB1ENR_TIM12EN_BIT 6 -#define RCC_APB1ENR_TIM7EN_BIT 5 -#define RCC_APB1ENR_TIM6EN_BIT 4 -#define RCC_APB1ENR_TIM5EN_BIT 3 -#define RCC_APB1ENR_TIM4EN_BIT 2 -#define RCC_APB1ENR_TIM3EN_BIT 1 -#define RCC_APB1ENR_TIM2EN_BIT 0 - -#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) -#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) -#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) -#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) -#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) -#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) -#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) -#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) -#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) -#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) -#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) -#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) -#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) -#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) -#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) -#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) -#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) -#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) -#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) -#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) -#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) -#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) -#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) - -/* Backup domain control register */ - -#define RCC_BDCR_BDRST_BIT 16 -#define RCC_BDCR_RTCEN_BIT 15 -#define RCC_BDCR_LSEBYP_BIT 2 -#define RCC_BDCR_LSERDY_BIT 1 -#define RCC_BDCR_LSEON_BIT 0 - -#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) -#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) -#define RCC_BDCR_RTCSEL (0x3 << 8) -#define RCC_BDCR_RTCSEL_NONE (0x0 << 8) -#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) -#define RCC_BDCR_RTCSEL_HSE (0x3 << 8) -#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) -#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) -#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) - -/* Control/status register */ - -#define RCC_CSR_LPWRRSTF_BIT 31 -#define RCC_CSR_WWDGRSTF_BIT 30 -#define RCC_CSR_IWDGRSTF_BIT 29 -#define RCC_CSR_SFTRSTF_BIT 28 -#define RCC_CSR_PORRSTF_BIT 27 -#define RCC_CSR_PINRSTF_BIT 26 -#define RCC_CSR_RMVF_BIT 24 -#define RCC_CSR_LSIRDY_BIT 1 -#define RCC_CSR_LSION_BIT 0 - -#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) -#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) -#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) -#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) -#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) -#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) -#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) -#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) -#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) - -/* - * Other types - */ - -/** - * @brief Identifies bus and clock line for a peripheral. - * - * Also generally useful as a unique identifier for that peripheral - * (or its corresponding device struct). - */ -typedef enum rcc_clk_id { - RCC_GPIOA, - RCC_GPIOB, - RCC_GPIOC, - RCC_GPIOD, - RCC_AFIO, - RCC_ADC1, - RCC_ADC2, - RCC_ADC3, - RCC_USART1, - RCC_USART2, - RCC_USART3, - RCC_TIMER1, - RCC_TIMER2, - RCC_TIMER3, - RCC_TIMER4, - RCC_SPI1, - RCC_SPI2, - RCC_DMA1, - RCC_PWR, - RCC_BKP, - RCC_I2C1, - RCC_I2C2, - RCC_CRC, - RCC_FLITF, - RCC_SRAM, - RCC_USB, -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) - RCC_GPIOE, - RCC_GPIOF, - RCC_GPIOG, - RCC_UART4, - RCC_UART5, - RCC_TIMER5, - RCC_TIMER6, - RCC_TIMER7, - RCC_TIMER8, - RCC_FSMC, - RCC_DAC, - RCC_DMA2, - RCC_SDIO, - RCC_SPI3, -#endif -#ifdef STM32_XL_DENSITY - RCC_TIMER9, - RCC_TIMER10, - RCC_TIMER11, - RCC_TIMER12, - RCC_TIMER13, - RCC_TIMER14, -#endif -} rcc_clk_id; - -/** - * PLL multipliers - * @see rcc_clk_init() - */ -typedef enum rcc_pll_multiplier { - RCC_PLLMUL_2 = (0x0 << 18), - RCC_PLLMUL_3 = (0x1 << 18), - RCC_PLLMUL_4 = (0x2 << 18), - RCC_PLLMUL_5 = (0x3 << 18), - RCC_PLLMUL_6 = (0x4 << 18), - RCC_PLLMUL_7 = (0x5 << 18), - RCC_PLLMUL_8 = (0x6 << 18), - RCC_PLLMUL_9 = (0x7 << 18), - RCC_PLLMUL_10 = (0x8 << 18), - RCC_PLLMUL_11 = (0x9 << 18), - RCC_PLLMUL_12 = (0xA << 18), - RCC_PLLMUL_13 = (0xB << 18), - RCC_PLLMUL_14 = (0xC << 18), - RCC_PLLMUL_15 = (0xD << 18), - RCC_PLLMUL_16 = (0xE << 18), -} rcc_pll_multiplier; - -/** - * PLL entry clock source - * @see rcc_clk_init() - */ -typedef enum rcc_pllsrc { - RCC_PLLSRC_HSE = (0x1 << 16), - RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) -} rcc_pllsrc; - -typedef enum rcc_clk_domain { - RCC_APB1, - RCC_APB2, - RCC_AHB -} rcc_clk_domain; - -/** - * Prescaler identifiers - * @see rcc_set_prescaler() - */ -typedef enum rcc_prescaler { - RCC_PRESCALER_AHB, - RCC_PRESCALER_APB1, - RCC_PRESCALER_APB2, - RCC_PRESCALER_USB, - RCC_PRESCALER_ADC -} rcc_prescaler; - -/** - * ADC prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_adc_divider { - RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14, - RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14, - RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14, - RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14, -} rcc_adc_divider; - -/** - * APB1 prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_apb1_divider { - RCC_APB1_HCLK_DIV_1 = 0x0 << 8, - RCC_APB1_HCLK_DIV_2 = 0x4 << 8, - RCC_APB1_HCLK_DIV_4 = 0x5 << 8, - RCC_APB1_HCLK_DIV_8 = 0x6 << 8, - RCC_APB1_HCLK_DIV_16 = 0x7 << 8, -} rcc_apb1_divider; - -/** - * APB2 prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_apb2_divider { - RCC_APB2_HCLK_DIV_1 = 0x0 << 11, - RCC_APB2_HCLK_DIV_2 = 0x4 << 11, - RCC_APB2_HCLK_DIV_4 = 0x5 << 11, - RCC_APB2_HCLK_DIV_8 = 0x6 << 11, - RCC_APB2_HCLK_DIV_16 = 0x7 << 11, -} rcc_apb2_divider; - -/** - * AHB prescaler dividers - * @see rcc_set_prescaler() - */ -typedef enum rcc_ahb_divider { - RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4, - RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4, - RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4, - RCC_AHB_SYSCLK_DIV_8 = 0xA << 4, - RCC_AHB_SYSCLK_DIV_16 = 0xB << 4, - RCC_AHB_SYSCLK_DIV_32 = 0xC << 4, - RCC_AHB_SYSCLK_DIV_64 = 0xD << 4, - RCC_AHB_SYSCLK_DIV_128 = 0xD << 4, - RCC_AHB_SYSCLK_DIV_256 = 0xE << 4, - RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, -} rcc_ahb_divider; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/stm32f1/include/family/stm32.h b/libmaple/stm32f1/include/family/stm32.h deleted file mode 100644 index 0b77ca0..0000000 --- a/libmaple/stm32f1/include/family/stm32.h +++ /dev/null @@ -1,100 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010, 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f1/stm32.h - * @brief STM32F1 chip- and family-specific definitions. - */ - -#ifndef _LIBMAPLE_STM32F1_H_ -#define _LIBMAPLE_STM32F1_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Clock configuration. - */ - -#ifndef STM32_PCLK1 -#define STM32_PCLK1 36000000U -#endif - -#ifndef STM32_PCLK2 -#define STM32_PCLK2 72000000U -#endif - -#ifndef STM32_DELAY_US_MULT -#define STM32_DELAY_US_MULT 12 /* FIXME: value is incorrect. */ -#endif - -/* - * Density-specific values. - */ - -#ifdef STM32_MEDIUM_DENSITY -# define STM32_NR_INTERRUPTS 43 -#elif defined(STM32_HIGH_DENSITY) -# define STM32_NR_INTERRUPTS 60 -#else -#error "Unsupported STM32F1 density, or no density specified. Add something " \ - "like -DSTM32_MEDIUM_DENSITY to your compiler arguments." -#endif - -/* - * MCU-specific values. - */ - -#if defined(MCU_STM32F103RB) -# define STM32_NR_GPIO_PORTS 4 -# define STM32_SRAM_END ((void*)0x20005000) - -#elif defined(MCU_STM32F103ZE) -# define STM32_NR_GPIO_PORTS 7 -# define STM32_SRAM_END ((void*)0x20010000) - -#elif defined(MCU_STM32F103CB) - /* This STM32_NR_GPIO_PORTS is not stricly true, but only pins 0 - * and exist, and they're used for OSC (e.g. on e.g. LeafLabs - * Maple Mini), so we'll live with this for now. */ -# define STM32_NR_GPIO_PORTS 3 -# define STM32_SRAM_END ((void*)0x20005000) - -#elif defined(MCU_STM32F103RE) -# define STM32_NR_GPIO_PORTS 4 -# define STM32_SRAM_END ((void*)0x20010000) - -#else -#error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ - "-DMCU_STM32F103RB to your compiler arguments." -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/stm32f1/include/series/flash.h b/libmaple/stm32f1/include/series/flash.h new file mode 100644 index 0000000..efa608c --- /dev/null +++ b/libmaple/stm32f1/include/series/flash.h @@ -0,0 +1,142 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/flash.h + * @brief STM32F1 Flash header. + * + * Provides register map, base pointer, and register bit definitions + * for the Flash controller on the STM32F1 line, along with + * series-specific configuration values. + */ + +#ifndef _LIBMAPLE_STM32F1_FLASH_H_ +#define _LIBMAPLE_STM32F1_FLASH_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register map + */ + +/** Flash register map type */ +typedef struct flash_reg_map { + __io uint32 ACR; /**< Access control register */ + __io uint32 KEYR; /**< Key register */ + __io uint32 OPTKEYR; /**< OPTKEY register */ + __io uint32 SR; /**< Status register */ + __io uint32 CR; /**< Control register */ + __io uint32 AR; /**< Address register */ + __io uint32 OBR; /**< Option byte register */ + __io uint32 WRPR; /**< Write protection register */ +} flash_reg_map; + +/** Flash register map base pointer */ +#define FLASH_BASE ((struct flash_reg_map*)0x40022000) + +/* + * Register bit definitions + */ + +/* Access control register */ + +#define FLASH_ACR_PRFTBS_BIT 5 +#define FLASH_ACR_PRFTBE_BIT 4 +#define FLASH_ACR_HLFCYA_BIT 3 + +#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) +#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) +#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) +#define FLASH_ACR_LATENCY 0x7 + +/* Status register */ + +#define FLASH_SR_EOP_BIT 5 +#define FLASH_SR_WRPRTERR_BIT 4 +#define FLASH_SR_PGERR_BIT 2 +#define FLASH_SR_BSY_BIT 0 + +#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) +#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) +#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) +#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) + +/* Control register */ + +#define FLASH_CR_EOPIE_BIT 12 +#define FLASH_CR_ERRIE_BIT 10 +#define FLASH_CR_OPTWRE_BIT 9 +#define FLASH_CR_LOCK_BIT 7 +#define FLASH_CR_STRT_BIT 6 +#define FLASH_CR_OPTER_BIT 5 +#define FLASH_CR_OPTPG_BIT 4 +#define FLASH_CR_MER_BIT 2 +#define FLASH_CR_PER_BIT 1 +#define FLASH_CR_PG_BIT 0 + +#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) +#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) +#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) +#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) +#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) +#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) +#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) +#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) +#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) +#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) + +/* Option byte register */ + +#define FLASH_OBR_nRST_STDBY_BIT 4 +#define FLASH_OBR_nRST_STOP_BIT 3 +#define FLASH_OBR_WDG_SW_BIT 2 +#define FLASH_OBR_RDPRT_BIT 1 +#define FLASH_OBR_OPTERR_BIT 0 + +#define FLASH_OBR_DATA1 (0xFF << 18) +#define FLASH_OBR_DATA0 (0xFF << 10) +#define FLASH_OBR_USER 0x3FF +#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) +#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) +#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) +#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) +#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) + +/* + * Series-specific configuration values. + */ + +#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_2 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/include/series/gpio.h b/libmaple/stm32f1/include/series/gpio.h new file mode 100644 index 0000000..c10244d --- /dev/null +++ b/libmaple/stm32f1/include/series/gpio.h @@ -0,0 +1,479 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +/** + * @file libmaple/stm32f1/gpio.h + * @brief General purpose I/O (GPIO) and Alternate Function I/O + * (AFIO) prototypes, defines, and inlined access functions. + */ + +#ifndef _LIBMAPLE_STM32F1_GPIO_H_ +#define _LIBMAPLE_STM32F1_GPIO_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/* + * GPIO register maps and devices + */ + +/** GPIO register map type */ +typedef struct gpio_reg_map { + __io uint32 CRL; /**< Port configuration register low */ + __io uint32 CRH; /**< Port configuration register high */ + __io uint32 IDR; /**< Port input data register */ + __io uint32 ODR; /**< Port output data register */ + __io uint32 BSRR; /**< Port bit set/reset register */ + __io uint32 BRR; /**< Port bit reset register */ + __io uint32 LCKR; /**< Port configuration lock register */ +} gpio_reg_map; + +/** + * @brief External interrupt line port selector. + * + * Used to determine which GPIO port to map an external interrupt line + * onto. */ +/* (See AFIO sections, below) */ +typedef enum afio_exti_port { + AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ + AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ + AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ + AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ +#ifdef STM32_HIGH_DENSITY + AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ + AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ + AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ +#endif +} afio_exti_port; + +/** GPIO device type */ +typedef struct gpio_dev { + gpio_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ + afio_exti_port exti_port; /**< AFIO external interrupt port value */ +} gpio_dev; + +extern gpio_dev gpioa; +extern gpio_dev* const GPIOA; +extern gpio_dev gpiob; +extern gpio_dev* const GPIOB; +extern gpio_dev gpioc; +extern gpio_dev* const GPIOC; +extern gpio_dev gpiod; +extern gpio_dev* const GPIOD; +#ifdef STM32_HIGH_DENSITY +extern gpio_dev gpioe; +extern gpio_dev* const GPIOE; +extern gpio_dev gpiof; +extern gpio_dev* const GPIOF; +extern gpio_dev gpiog; +extern gpio_dev* const GPIOG; +#endif + +/** GPIO port A register map base pointer */ +#define GPIOA_BASE ((struct gpio_reg_map*)0x40010800) +/** GPIO port B register map base pointer */ +#define GPIOB_BASE ((struct gpio_reg_map*)0x40010C00) +/** GPIO port C register map base pointer */ +#define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) +/** GPIO port D register map base pointer */ +#define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) +#ifdef STM32_HIGH_DENSITY +/** GPIO port E register map base pointer */ +#define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) +/** GPIO port F register map base pointer */ +#define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) +/** GPIO port G register map base pointer */ +#define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) +#endif + +/* + * GPIO register bit definitions + */ + +/* Control registers, low and high */ + +#define GPIO_CR_CNF (0x3 << 2) +#define GPIO_CR_CNF_INPUT_ANALOG (0x0 << 2) +#define GPIO_CR_CNF_INPUT_FLOATING (0x1 << 2) +#define GPIO_CR_CNF_INPUT_PU_PD (0x2 << 2) +#define GPIO_CR_CNF_OUTPUT_PP (0x0 << 2) +#define GPIO_CR_CNF_OUTPUT_OD (0x1 << 2) +#define GPIO_CR_CNF_AF_OUTPUT_PP (0x2 << 2) +#define GPIO_CR_CNF_AF_OUTPUT_OD (0x3 << 2) +#define GPIO_CR_MODE 0x3 +#define GPIO_CR_MODE_INPUT 0x0 +#define GPIO_CR_MODE_OUTPUT_10MHZ 0x1 +#define GPIO_CR_MODE_OUTPUT_2MHZ 0x2 +#define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 + +/** + * @brief GPIO Pin modes. + * + * These only allow for 50MHZ max output speeds; if you want slower, + * use direct register access. + */ +typedef enum gpio_pin_mode { + GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ + GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ + GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function + output push-pull. */ + GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | + GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function + output open drain. */ + GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | + GPIO_CR_MODE_INPUT), /**< Analog input. */ + GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | + GPIO_CR_MODE_INPUT), /**< Input floating. */ + GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | + GPIO_CR_MODE_INPUT), /**< Input pull-down. */ + GPIO_INPUT_PU /**< Input pull-up. */ + /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ +} gpio_pin_mode; + +/** + * @brief Get a GPIO port's corresponding afio_exti_port. + * @param dev GPIO device whose afio_exti_port to return. + */ +static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { + return dev->exti_port; +} + +/* + * AFIO register map + */ + +/** AFIO register map */ +typedef struct afio_reg_map { + __io uint32 EVCR; /**< Event control register. */ + __io uint32 MAPR; /**< AF remap and debug I/O configuration + register. */ + __io uint32 EXTICR1; /**< External interrupt configuration + register 1. */ + __io uint32 EXTICR2; /**< External interrupt configuration + register 2. */ + __io uint32 EXTICR3; /**< External interrupt configuration + register 3. */ + __io uint32 EXTICR4; /**< External interrupt configuration + register 4. */ + __io uint32 MAPR2; /**< AF remap and debug I/O configuration + register 2. */ +} afio_reg_map; + +/** AFIO register map base pointer. */ +#define AFIO_BASE ((struct afio_reg_map *)0x40010000) + +/* + * AFIO register bit definitions + */ + +/* Event control register */ + +#define AFIO_EVCR_EVOE (0x1 << 7) +#define AFIO_EVCR_PORT_PA (0x0 << 4) +#define AFIO_EVCR_PORT_PB (0x1 << 4) +#define AFIO_EVCR_PORT_PC (0x2 << 4) +#define AFIO_EVCR_PORT_PD (0x3 << 4) +#define AFIO_EVCR_PORT_PE (0x4 << 4) +#define AFIO_EVCR_PIN_0 0x0 +#define AFIO_EVCR_PIN_1 0x1 +#define AFIO_EVCR_PIN_2 0x2 +#define AFIO_EVCR_PIN_3 0x3 +#define AFIO_EVCR_PIN_4 0x4 +#define AFIO_EVCR_PIN_5 0x5 +#define AFIO_EVCR_PIN_6 0x6 +#define AFIO_EVCR_PIN_7 0x7 +#define AFIO_EVCR_PIN_8 0x8 +#define AFIO_EVCR_PIN_9 0x9 +#define AFIO_EVCR_PIN_10 0xA +#define AFIO_EVCR_PIN_11 0xB +#define AFIO_EVCR_PIN_12 0xC +#define AFIO_EVCR_PIN_13 0xD +#define AFIO_EVCR_PIN_14 0xE +#define AFIO_EVCR_PIN_15 0xF + +/* AF remap and debug I/O configuration register */ + +#define AFIO_MAPR_SWJ_CFG (0x7 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) +#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) +#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) +#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) +#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) +#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) +#define AFIO_MAPR_PD01_REMAP BIT(15) +#define AFIO_MAPR_CAN_REMAP (0x3 << 13) +#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) +#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) +#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) +#define AFIO_MAPR_TIM4_REMAP BIT(12) +#define AFIO_MAPR_TIM3_REMAP (0x3 << 10) +#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) +#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) +#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10) +#define AFIO_MAPR_TIM2_REMAP (0x3 << 8) +#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8) +#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8) +#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8) +#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8) +#define AFIO_MAPR_TIM1_REMAP (0x3 << 6) +#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6) +#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6) +#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6) +#define AFIO_MAPR_USART3_REMAP (0x3 << 4) +#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) +#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) +#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) +#define AFIO_MAPR_USART2_REMAP BIT(3) +#define AFIO_MAPR_USART1_REMAP BIT(2) +#define AFIO_MAPR_I2C1_REMAP BIT(1) +#define AFIO_MAPR_SPI1_REMAP BIT(0) + +/* External interrupt configuration register 1 */ + +#define AFIO_EXTICR1_EXTI3 (0xF << 12) +#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12) +#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12) +#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12) +#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12) +#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12) +#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12) +#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12) +#define AFIO_EXTICR1_EXTI2 (0xF << 8) +#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8) +#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8) +#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8) +#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8) +#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8) +#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8) +#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8) +#define AFIO_EXTICR1_EXTI1 (0xF << 4) +#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4) +#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4) +#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4) +#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4) +#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4) +#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4) +#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4) +#define AFIO_EXTICR1_EXTI0 0xF +#define AFIO_EXTICR1_EXTI0_PA 0x0 +#define AFIO_EXTICR1_EXTI0_PB 0x1 +#define AFIO_EXTICR1_EXTI0_PC 0x2 +#define AFIO_EXTICR1_EXTI0_PD 0x3 +#define AFIO_EXTICR1_EXTI0_PE 0x4 +#define AFIO_EXTICR1_EXTI0_PF 0x5 +#define AFIO_EXTICR1_EXTI0_PG 0x6 + +/* External interrupt configuration register 2 */ + +#define AFIO_EXTICR2_EXTI7 (0xF << 12) +#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12) +#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12) +#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12) +#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12) +#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12) +#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12) +#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12) +#define AFIO_EXTICR2_EXTI6 (0xF << 8) +#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8) +#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8) +#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8) +#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8) +#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8) +#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8) +#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8) +#define AFIO_EXTICR2_EXTI5 (0xF << 4) +#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4) +#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4) +#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4) +#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4) +#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4) +#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4) +#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4) +#define AFIO_EXTICR2_EXTI4 0xF +#define AFIO_EXTICR2_EXTI4_PA 0x0 +#define AFIO_EXTICR2_EXTI4_PB 0x1 +#define AFIO_EXTICR2_EXTI4_PC 0x2 +#define AFIO_EXTICR2_EXTI4_PD 0x3 +#define AFIO_EXTICR2_EXTI4_PE 0x4 +#define AFIO_EXTICR2_EXTI4_PF 0x5 +#define AFIO_EXTICR2_EXTI4_PG 0x6 + +/* AF remap and debug I/O configuration register 2 */ + +#define AFIO_MAPR2_FSMC_NADV BIT(10) +#define AFIO_MAPR2_TIM14_REMAP BIT(9) +#define AFIO_MAPR2_TIM13_REMAP BIT(8) +#define AFIO_MAPR2_TIM11_REMAP BIT(7) +#define AFIO_MAPR2_TIM10_REMAP BIT(6) +#define AFIO_MAPR2_TIM9_REMAP BIT(5) + +/* + * AFIO convenience routines + */ + +void afio_init(void); + +/** + * External interrupt line numbers. + */ +typedef enum afio_exti_num { + AFIO_EXTI_0, /**< External interrupt line 0. */ + AFIO_EXTI_1, /**< External interrupt line 1. */ + AFIO_EXTI_2, /**< External interrupt line 2. */ + AFIO_EXTI_3, /**< External interrupt line 3. */ + AFIO_EXTI_4, /**< External interrupt line 4. */ + AFIO_EXTI_5, /**< External interrupt line 5. */ + AFIO_EXTI_6, /**< External interrupt line 6. */ + AFIO_EXTI_7, /**< External interrupt line 7. */ + AFIO_EXTI_8, /**< External interrupt line 8. */ + AFIO_EXTI_9, /**< External interrupt line 9. */ + AFIO_EXTI_10, /**< External interrupt line 10. */ + AFIO_EXTI_11, /**< External interrupt line 11. */ + AFIO_EXTI_12, /**< External interrupt line 12. */ + AFIO_EXTI_13, /**< External interrupt line 13. */ + AFIO_EXTI_14, /**< External interrupt line 14. */ + AFIO_EXTI_15, /**< External interrupt line 15. */ +} afio_exti_num; + +void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); + +/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and + * not used in either MAPR or MAPR2 */ +#define AFIO_REMAP_USE_MAPR2 (1 << 31) + +/** + * @brief Available peripheral remaps. + * @see afio_remap() + */ +typedef enum afio_remap_peripheral { + AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< + ADC 2 external trigger regular conversion remapping */ + AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< + ADC 2 external trigger injected conversion remapping */ + AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< + ADC 1 external trigger regular conversion remapping */ + AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< + ADC 1 external trigger injected conversion remapping */ + AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< + Timer 5 channel 4 internal remapping */ + AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< + Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< + CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ + AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< + CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ + AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< + Timer 4 remapping */ + AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< + Timer 3 partial remapping */ + AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< + Timer 3 full remapping */ + AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< + Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 + on PA2, CH4 on PA3) */ + AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< + Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 + on PB10, CH4 on PB11) */ + AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< + Timer 2 full remapping */ + AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< + USART 2 remapping */ + AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< + USART 1 remapping */ + AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< + I2C 1 remapping */ + AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< + SPI 1 remapping */ + AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | + AFIO_REMAP_USE_MAPR2), /**< + NADV signal not connected */ + AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 14 remapping */ + AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 13 remapping */ + AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 11 remapping */ + AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | + AFIO_REMAP_USE_MAPR2), /**< + Timer 10 remapping */ + AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | + AFIO_REMAP_USE_MAPR2) /**< + Timer 9 */ +} afio_remap_peripheral; + +void afio_remap(afio_remap_peripheral p); + +/** + * @brief Debug port configuration + * + * Used to configure the behavior of JTAG and Serial Wire (SW) debug + * ports and their associated GPIO pins. + * + * @see afio_cfg_debug_ports() + */ +typedef enum afio_debug_cfg { + AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< + Full Serial Wire and JTAG debug */ + AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< + Full Serial Wire and JTAG, but no NJTRST. */ + AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< + Serial Wire debug only (JTAG-DP disabled, + SW-DP enabled) */ + AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< + No debug; all JTAG and SW pins are free + for use as GPIOs. */ +} afio_debug_cfg; + +/** + * @brief Enable or disable the JTAG and SW debug ports. + * @param config Desired debug port configuration + * @see afio_debug_cfg + */ +static inline void afio_cfg_debug_ports(afio_debug_cfg config) { + __io uint32 *mapr = &AFIO_BASE->MAPR; + *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/include/series/nvic.h b/libmaple/stm32f1/include/series/nvic.h new file mode 100644 index 0000000..69fd945 --- /dev/null +++ b/libmaple/stm32f1/include/series/nvic.h @@ -0,0 +1,139 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/nvic.h + * @brief STM32F1 Nested Vectored Interrupt Controller (NVIC) support. + */ + +#ifndef _LIBMAPLE_STM32F1_NVIC_H_ +#define _LIBMAPLE_STM32F1_NVIC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * @brief Interrupt vector table interrupt numbers. + * @see + */ +typedef enum nvic_irq_num { + NVIC_NMI = -14, /**< Non-maskable interrupt */ + NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ + NVIC_MEM_MANAGE = -12, /**< Memory management */ + NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory + access fault. */ + NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction or + illegal state. */ + NVIC_SVC = -5, /**< System service call via SWI insruction */ + NVIC_DEBUG_MON = -4, /**< Debug monitor */ + NVIC_PEND_SVC = -2, /**< Pendable request for system service */ + NVIC_SYSTICK = -1, /**< System tick timer */ + NVIC_WWDG = 0, /**< Window watchdog interrupt */ + NVIC_PVD = 1, /**< PVD through EXTI line detection */ + NVIC_TAMPER = 2, /**< Tamper */ + NVIC_RTC = 3, /**< Real-time clock */ + NVIC_FLASH = 4, /**< Flash */ + NVIC_RCC = 5, /**< Reset and clock control */ + NVIC_EXTI0 = 6, /**< EXTI line 0 */ + NVIC_EXTI1 = 7, /**< EXTI line 1 */ + NVIC_EXTI2 = 8, /**< EXTI line 2 */ + NVIC_EXTI3 = 9, /**< EXTI line 3 */ + NVIC_EXTI4 = 10, /**< EXTI line 4 */ + NVIC_DMA_CH1 = 11, /**< DMA1 channel 1 */ + NVIC_DMA_CH2 = 12, /**< DMA1 channel 2 */ + NVIC_DMA_CH3 = 13, /**< DMA1 channel 3 */ + NVIC_DMA_CH4 = 14, /**< DMA1 channel 4 */ + NVIC_DMA_CH5 = 15, /**< DMA1 channel 5 */ + NVIC_DMA_CH6 = 16, /**< DMA1 channel 6 */ + NVIC_DMA_CH7 = 17, /**< DMA1 channel 7 */ + NVIC_ADC_1_2 = 18, /**< ADC1 and ADC2 */ + NVIC_USB_HP_CAN_TX = 19, /**< USB high priority or CAN TX */ + NVIC_USB_LP_CAN_RX0 = 20, /**< USB low priority or CAN RX0 */ + NVIC_CAN_RX1 = 21, /**< CAN RX1 */ + NVIC_CAN_SCE = 22, /**< CAN SCE */ + NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ + NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ + NVIC_TIMER1_UP = 25, /**< Timer 1 update */ + NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ + NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ + NVIC_TIMER2 = 28, /**< Timer 2 */ + NVIC_TIMER3 = 29, /**< Timer 3 */ + NVIC_TIMER4 = 30, /**< Timer 4 */ + NVIC_I2C1_EV = 31, /**< I2C1 event */ + NVIC_I2C1_ER = 32, /**< I2C1 error */ + NVIC_I2C2_EV = 33, /**< I2C2 event */ + NVIC_I2C2_ER = 34, /**< I2C2 error */ + NVIC_SPI1 = 35, /**< SPI1 */ + NVIC_SPI2 = 36, /**< SPI2 */ + NVIC_USART1 = 37, /**< USART1 */ + NVIC_USART2 = 38, /**< USART2 */ + NVIC_USART3 = 39, /**< USART3 */ + NVIC_EXTI_15_10 = 40, /**< EXTI line [15:10] */ + NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ + NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through + EXTI line */ + NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ + NVIC_TIMER8_UP = 44, /**< Timer 8 update */ + NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ + NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ +#ifdef STM32_HIGH_DENSITY + NVIC_ADC3 = 47, /**< ADC3 */ + NVIC_FSMC = 48, /**< FSMC */ + NVIC_SDIO = 49, /**< SDIO */ + NVIC_TIMER5 = 50, /**< Timer 5 */ + NVIC_SPI3 = 51, /**< SPI3 */ + NVIC_UART4 = 52, /**< UART4 */ + NVIC_UART5 = 53, /**< UART5 */ + NVIC_TIMER6 = 54, /**< Timer 6 */ + NVIC_TIMER7 = 55, /**< Timer 7 */ + NVIC_DMA2_CH1 = 56, /**< DMA2 channel 1 */ + NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ + NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ + NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ +#endif +} nvic_irq_num; + +static inline void nvic_irq_disable_all(void) { + /* Note: This only works up to XL density. The fix for + * connectivity line is: + * + * NVIC_BASE->ICER[2] = 0xF; + * + * We don't support connectivity line devices (yet), so leave it + * alone for now. + */ + NVIC_BASE->ICER[0] = 0xFFFFFFFF; + NVIC_BASE->ICER[1] = 0xFFFFFFFF; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h new file mode 100644 index 0000000..261dc5d --- /dev/null +++ b/libmaple/stm32f1/include/series/rcc.h @@ -0,0 +1,553 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/rcc.h + * @brief STM32F1 reset and clock control (RCC) header. + */ + +#ifndef _LIBMAPLE_STM32F1_RCC_H_ +#define _LIBMAPLE_STM32F1_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Register map + */ + +/** RCC register map type */ +typedef struct rcc_reg_map { + __io uint32 CR; /**< Clock control register */ + __io uint32 CFGR; /**< Clock configuration register */ + __io uint32 CIR; /**< Clock interrupt register */ + __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ + __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ + __io uint32 AHBENR; /**< AHB peripheral clock enable register */ + __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ + __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ + __io uint32 BDCR; /**< Backup domain control register */ + __io uint32 CSR; /**< Control/status register */ +} rcc_reg_map; + +/** RCC register map base pointer */ +#define RCC_BASE ((struct rcc_reg_map*)0x40021000) + +/* + * Register bit definitions + */ + +/* Clock control register */ + +#define RCC_CR_PLLRDY_BIT 25 +#define RCC_CR_PLLON_BIT 24 +#define RCC_CR_CSSON_BIT 19 +#define RCC_CR_HSEBYP_BIT 18 +#define RCC_CR_HSERDY_BIT 17 +#define RCC_CR_HSEON_BIT 16 +#define RCC_CR_HSIRDY_BIT 1 +#define RCC_CR_HSION_BIT 0 + +#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) +#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) +#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) +#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) +#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) +#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) +#define RCC_CR_HSICAL (0xFF << 8) +#define RCC_CR_HSITRIM (0x1F << 3) +#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) +#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) + +/* Clock configuration register */ + +#define RCC_CFGR_USBPRE_BIT 22 +#define RCC_CFGR_PLLXTPRE_BIT 17 +#define RCC_CFGR_PLLSRC_BIT 16 + +#define RCC_CFGR_MCO (0x3 << 24) +#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) +#define RCC_CFGR_PLLMUL (0xF << 18) +#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) +#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) +#define RCC_CFGR_ADCPRE (0x3 << 14) +#define RCC_CFGR_PPRE2 (0x7 << 11) +#define RCC_CFGR_PPRE1 (0x7 << 8) +#define RCC_CFGR_HPRE (0xF << 4) +#define RCC_CFGR_SWS (0x3 << 2) +#define RCC_CFGR_SWS_PLL (0x2 << 2) +#define RCC_CFGR_SWS_HSE (0x1 << 2) +#define RCC_CFGR_SW 0x3 +#define RCC_CFGR_SW_PLL 0x2 +#define RCC_CFGR_SW_HSE 0x1 + +/* Clock interrupt register */ + +#define RCC_CIR_CSSC_BIT 23 +#define RCC_CIR_PLLRDYC_BIT 20 +#define RCC_CIR_HSERDYC_BIT 19 +#define RCC_CIR_HSIRDYC_BIT 18 +#define RCC_CIR_LSERDYC_BIT 17 +#define RCC_CIR_LSIRDYC_BIT 16 +#define RCC_CIR_PLLRDYIE_BIT 12 +#define RCC_CIR_HSERDYIE_BIT 11 +#define RCC_CIR_HSIRDYIE_BIT 10 +#define RCC_CIR_LSERDYIE_BIT 9 +#define RCC_CIR_LSIRDYIE_BIT 8 +#define RCC_CIR_CSSF_BIT 7 +#define RCC_CIR_PLLRDYF_BIT 4 +#define RCC_CIR_HSERDYF_BIT 3 +#define RCC_CIR_HSIRDYF_BIT 2 +#define RCC_CIR_LSERDYF_BIT 1 +#define RCC_CIR_LSIRDYF_BIT 0 + +#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) +#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) +#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) +#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) +#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) +#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) +#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) +#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) +#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) +#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) +#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) +#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) +#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) +#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) +#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) +#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) +#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM11RST_BIT 21 +#define RCC_APB2RSTR_TIM10RST_BIT 20 +#define RCC_APB2RSTR_TIM9RST_BIT 19 +#define RCC_APB2RSTR_ADC3RST_BIT 15 +#define RCC_APB2RSTR_USART1RST_BIT 14 +#define RCC_APB2RSTR_TIM8RST_BIT 13 +#define RCC_APB2RSTR_SPI1RST_BIT 12 +#define RCC_APB2RSTR_TIM1RST_BIT 11 +#define RCC_APB2RSTR_ADC2RST_BIT 10 +#define RCC_APB2RSTR_ADC1RST_BIT 9 +#define RCC_APB2RSTR_IOPGRST_BIT 8 +#define RCC_APB2RSTR_IOPFRST_BIT 7 +#define RCC_APB2RSTR_IOPERST_BIT 6 +#define RCC_APB2RSTR_IOPDRST_BIT 5 +#define RCC_APB2RSTR_IOPCRST_BIT 4 +#define RCC_APB2RSTR_IOPBRST_BIT 3 +#define RCC_APB2RSTR_IOPARST_BIT 2 +#define RCC_APB2RSTR_AFIORST_BIT 0 + +#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) +#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) +#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) +#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) +#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) +#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) +#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) +#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) +#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) +#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) +#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) +#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) +#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) +#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) +#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) +#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) +#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) +#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) + +/* APB1 peripheral reset register */ + +#define RCC_APB1RSTR_DACRST_BIT 29 +#define RCC_APB1RSTR_PWRRST_BIT 28 +#define RCC_APB1RSTR_BKPRST_BIT 27 +#define RCC_APB1RSTR_CANRST_BIT 25 +#define RCC_APB1RSTR_USBRST_BIT 23 +#define RCC_APB1RSTR_I2C2RST_BIT 22 +#define RCC_APB1RSTR_I2C1RST_BIT 21 +#define RCC_APB1RSTR_UART5RST_BIT 20 +#define RCC_APB1RSTR_UART4RST_BIT 19 +#define RCC_APB1RSTR_USART3RST_BIT 18 +#define RCC_APB1RSTR_USART2RST_BIT 17 +#define RCC_APB1RSTR_SPI3RST_BIT 15 +#define RCC_APB1RSTR_SPI2RST_BIT 14 +#define RCC_APB1RSTR_WWDRST_BIT 11 +#define RCC_APB1RSTR_TIM14RST_BIT 8 +#define RCC_APB1RSTR_TIM13RST_BIT 7 +#define RCC_APB1RSTR_TIM12RST_BIT 6 +#define RCC_APB1RSTR_TIM7RST_BIT 5 +#define RCC_APB1RSTR_TIM6RST_BIT 4 +#define RCC_APB1RSTR_TIM5RST_BIT 3 +#define RCC_APB1RSTR_TIM4RST_BIT 2 +#define RCC_APB1RSTR_TIM3RST_BIT 1 +#define RCC_APB1RSTR_TIM2RST_BIT 0 + +#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) +#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) +#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) +#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) +#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) +#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) +#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) +#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) +#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) +#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) +#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) +#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) +#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) +#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) +#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) +#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) +#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) +#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) +#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) +#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) +#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) +#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) +#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) + +/* AHB peripheral clock enable register */ + +#define RCC_AHBENR_SDIOEN_BIT 10 +#define RCC_AHBENR_FSMCEN_BIT 8 +#define RCC_AHBENR_CRCEN_BIT 7 +#define RCC_AHBENR_FLITFEN_BIT 4 +#define RCC_AHBENR_SRAMEN_BIT 2 +#define RCC_AHBENR_DMA2EN_BIT 1 +#define RCC_AHBENR_DMA1EN_BIT 0 + +#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) +#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) +#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) +#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) +#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) +#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) +#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) + +/* APB2 peripheral clock enable register */ + +#define RCC_APB2ENR_TIM11EN_BIT 21 +#define RCC_APB2ENR_TIM10EN_BIT 20 +#define RCC_APB2ENR_TIM9EN_BIT 19 +#define RCC_APB2ENR_ADC3EN_BIT 15 +#define RCC_APB2ENR_USART1EN_BIT 14 +#define RCC_APB2ENR_TIM8EN_BIT 13 +#define RCC_APB2ENR_SPI1EN_BIT 12 +#define RCC_APB2ENR_TIM1EN_BIT 11 +#define RCC_APB2ENR_ADC2EN_BIT 10 +#define RCC_APB2ENR_ADC1EN_BIT 9 +#define RCC_APB2ENR_IOPGEN_BIT 8 +#define RCC_APB2ENR_IOPFEN_BIT 7 +#define RCC_APB2ENR_IOPEEN_BIT 6 +#define RCC_APB2ENR_IOPDEN_BIT 5 +#define RCC_APB2ENR_IOPCEN_BIT 4 +#define RCC_APB2ENR_IOPBEN_BIT 3 +#define RCC_APB2ENR_IOPAEN_BIT 2 +#define RCC_APB2ENR_AFIOEN_BIT 0 + +#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) +#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) +#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) +#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) +#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) +#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) +#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) +#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) +#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) +#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) +#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) +#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) +#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) +#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) +#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) +#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) +#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) +#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) + +/* APB1 peripheral clock enable register */ + +#define RCC_APB1ENR_DACEN_BIT 29 +#define RCC_APB1ENR_PWREN_BIT 28 +#define RCC_APB1ENR_BKPEN_BIT 27 +#define RCC_APB1ENR_CANEN_BIT 25 +#define RCC_APB1ENR_USBEN_BIT 23 +#define RCC_APB1ENR_I2C2EN_BIT 22 +#define RCC_APB1ENR_I2C1EN_BIT 21 +#define RCC_APB1ENR_UART5EN_BIT 20 +#define RCC_APB1ENR_UART4EN_BIT 19 +#define RCC_APB1ENR_USART3EN_BIT 18 +#define RCC_APB1ENR_USART2EN_BIT 17 +#define RCC_APB1ENR_SPI3EN_BIT 15 +#define RCC_APB1ENR_SPI2EN_BIT 14 +#define RCC_APB1ENR_WWDEN_BIT 11 +#define RCC_APB1ENR_TIM14EN_BIT 8 +#define RCC_APB1ENR_TIM13EN_BIT 7 +#define RCC_APB1ENR_TIM12EN_BIT 6 +#define RCC_APB1ENR_TIM7EN_BIT 5 +#define RCC_APB1ENR_TIM6EN_BIT 4 +#define RCC_APB1ENR_TIM5EN_BIT 3 +#define RCC_APB1ENR_TIM4EN_BIT 2 +#define RCC_APB1ENR_TIM3EN_BIT 1 +#define RCC_APB1ENR_TIM2EN_BIT 0 + +#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) +#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) +#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) +#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) +#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) +#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) +#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) +#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) +#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) +#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) +#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) +#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) +#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) +#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) +#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) +#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) +#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) +#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) +#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) +#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) +#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) +#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) +#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) + +/* Backup domain control register */ + +#define RCC_BDCR_BDRST_BIT 16 +#define RCC_BDCR_RTCEN_BIT 15 +#define RCC_BDCR_LSEBYP_BIT 2 +#define RCC_BDCR_LSERDY_BIT 1 +#define RCC_BDCR_LSEON_BIT 0 + +#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) +#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) +#define RCC_BDCR_RTCSEL (0x3 << 8) +#define RCC_BDCR_RTCSEL_NONE (0x0 << 8) +#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) +#define RCC_BDCR_RTCSEL_HSE (0x3 << 8) +#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) +#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) +#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) + +/* Control/status register */ + +#define RCC_CSR_LPWRRSTF_BIT 31 +#define RCC_CSR_WWDGRSTF_BIT 30 +#define RCC_CSR_IWDGRSTF_BIT 29 +#define RCC_CSR_SFTRSTF_BIT 28 +#define RCC_CSR_PORRSTF_BIT 27 +#define RCC_CSR_PINRSTF_BIT 26 +#define RCC_CSR_RMVF_BIT 24 +#define RCC_CSR_LSIRDY_BIT 1 +#define RCC_CSR_LSION_BIT 0 + +#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) +#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) +#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) +#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) +#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) +#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) +#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) +#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) +#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) + +/* + * Other types + */ + +/** + * @brief Identifies bus and clock line for a peripheral. + * + * Also generally useful as a unique identifier for that peripheral + * (or its corresponding device struct). + */ +typedef enum rcc_clk_id { + RCC_GPIOA, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, + RCC_AFIO, + RCC_ADC1, + RCC_ADC2, + RCC_ADC3, + RCC_USART1, + RCC_USART2, + RCC_USART3, + RCC_TIMER1, + RCC_TIMER2, + RCC_TIMER3, + RCC_TIMER4, + RCC_SPI1, + RCC_SPI2, + RCC_DMA1, + RCC_PWR, + RCC_BKP, + RCC_I2C1, + RCC_I2C2, + RCC_CRC, + RCC_FLITF, + RCC_SRAM, + RCC_USB, +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + RCC_GPIOE, + RCC_GPIOF, + RCC_GPIOG, + RCC_UART4, + RCC_UART5, + RCC_TIMER5, + RCC_TIMER6, + RCC_TIMER7, + RCC_TIMER8, + RCC_FSMC, + RCC_DAC, + RCC_DMA2, + RCC_SDIO, + RCC_SPI3, +#endif +#ifdef STM32_XL_DENSITY + RCC_TIMER9, + RCC_TIMER10, + RCC_TIMER11, + RCC_TIMER12, + RCC_TIMER13, + RCC_TIMER14, +#endif +} rcc_clk_id; + +/** + * PLL multipliers + * @see rcc_clk_init() + */ +typedef enum rcc_pll_multiplier { + RCC_PLLMUL_2 = (0x0 << 18), + RCC_PLLMUL_3 = (0x1 << 18), + RCC_PLLMUL_4 = (0x2 << 18), + RCC_PLLMUL_5 = (0x3 << 18), + RCC_PLLMUL_6 = (0x4 << 18), + RCC_PLLMUL_7 = (0x5 << 18), + RCC_PLLMUL_8 = (0x6 << 18), + RCC_PLLMUL_9 = (0x7 << 18), + RCC_PLLMUL_10 = (0x8 << 18), + RCC_PLLMUL_11 = (0x9 << 18), + RCC_PLLMUL_12 = (0xA << 18), + RCC_PLLMUL_13 = (0xB << 18), + RCC_PLLMUL_14 = (0xC << 18), + RCC_PLLMUL_15 = (0xD << 18), + RCC_PLLMUL_16 = (0xE << 18), +} rcc_pll_multiplier; + +/** + * PLL entry clock source + * @see rcc_clk_init() + */ +typedef enum rcc_pllsrc { + RCC_PLLSRC_HSE = (0x1 << 16), + RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) +} rcc_pllsrc; + +typedef enum rcc_clk_domain { + RCC_APB1, + RCC_APB2, + RCC_AHB +} rcc_clk_domain; + +/** + * Prescaler identifiers + * @see rcc_set_prescaler() + */ +typedef enum rcc_prescaler { + RCC_PRESCALER_AHB, + RCC_PRESCALER_APB1, + RCC_PRESCALER_APB2, + RCC_PRESCALER_USB, + RCC_PRESCALER_ADC +} rcc_prescaler; + +/** + * ADC prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_adc_divider { + RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14, + RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14, + RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14, + RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14, +} rcc_adc_divider; + +/** + * APB1 prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_apb1_divider { + RCC_APB1_HCLK_DIV_1 = 0x0 << 8, + RCC_APB1_HCLK_DIV_2 = 0x4 << 8, + RCC_APB1_HCLK_DIV_4 = 0x5 << 8, + RCC_APB1_HCLK_DIV_8 = 0x6 << 8, + RCC_APB1_HCLK_DIV_16 = 0x7 << 8, +} rcc_apb1_divider; + +/** + * APB2 prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_apb2_divider { + RCC_APB2_HCLK_DIV_1 = 0x0 << 11, + RCC_APB2_HCLK_DIV_2 = 0x4 << 11, + RCC_APB2_HCLK_DIV_4 = 0x5 << 11, + RCC_APB2_HCLK_DIV_8 = 0x6 << 11, + RCC_APB2_HCLK_DIV_16 = 0x7 << 11, +} rcc_apb2_divider; + +/** + * AHB prescaler dividers + * @see rcc_set_prescaler() + */ +typedef enum rcc_ahb_divider { + RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4, + RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4, + RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4, + RCC_AHB_SYSCLK_DIV_8 = 0xA << 4, + RCC_AHB_SYSCLK_DIV_16 = 0xB << 4, + RCC_AHB_SYSCLK_DIV_32 = 0xC << 4, + RCC_AHB_SYSCLK_DIV_64 = 0xD << 4, + RCC_AHB_SYSCLK_DIV_128 = 0xD << 4, + RCC_AHB_SYSCLK_DIV_256 = 0xE << 4, + RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, +} rcc_ahb_divider; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h new file mode 100644 index 0000000..f0ca616 --- /dev/null +++ b/libmaple/stm32f1/include/series/stm32.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010, 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/stm32.h + * @brief STM32F1 chip- and series-specific definitions. + */ + +#ifndef _LIBMAPLE_STM32F1_H_ +#define _LIBMAPLE_STM32F1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Clock configuration. + */ + +#ifndef STM32_PCLK1 +#define STM32_PCLK1 36000000U +#endif + +#ifndef STM32_PCLK2 +#define STM32_PCLK2 72000000U +#endif + +#ifndef STM32_DELAY_US_MULT +#define STM32_DELAY_US_MULT 12 /* FIXME: value is incorrect. */ +#endif + +/* + * Density-specific values. + */ + +#ifdef STM32_MEDIUM_DENSITY +# define STM32_NR_INTERRUPTS 43 +#elif defined(STM32_HIGH_DENSITY) +# define STM32_NR_INTERRUPTS 60 +#else +#error "Unsupported STM32F1 density, or no density specified. Add something " \ + "like -DSTM32_MEDIUM_DENSITY to your compiler arguments." +#endif + +/* + * MCU-specific values. + */ + +#if defined(MCU_STM32F103RB) +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20005000) + +#elif defined(MCU_STM32F103ZE) +# define STM32_NR_GPIO_PORTS 7 +# define STM32_SRAM_END ((void*)0x20010000) + +#elif defined(MCU_STM32F103CB) + /* This STM32_NR_GPIO_PORTS is not stricly true, but only pins 0 + * and exist, and they're used for OSC (e.g. on e.g. LeafLabs + * Maple Mini), so we'll live with this for now. */ +# define STM32_NR_GPIO_PORTS 3 +# define STM32_SRAM_END ((void*)0x20005000) + +#elif defined(MCU_STM32F103RE) +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20010000) + +#else +#error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ + "-DMCU_STM32F103RB to your compiler arguments." +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/support/ld/stm32/family/f1/performance/vector_symbols.inc b/support/ld/stm32/family/f1/performance/vector_symbols.inc deleted file mode 100644 index f8519bb..0000000 --- a/support/ld/stm32/family/f1/performance/vector_symbols.inc +++ /dev/null @@ -1,78 +0,0 @@ -EXTERN(__msp_init) -EXTERN(__exc_reset) -EXTERN(__exc_nmi) -EXTERN(__exc_hardfault) -EXTERN(__exc_memmanage) -EXTERN(__exc_busfault) -EXTERN(__exc_usagefault) -EXTERN(__stm32reservedexception7) -EXTERN(__stm32reservedexception8) -EXTERN(__stm32reservedexception9) -EXTERN(__stm32reservedexception10) -EXTERN(__exc_svc) -EXTERN(__exc_debug_monitor) -EXTERN(__stm32reservedexception13) -EXTERN(__exc_pendsv) -EXTERN(__exc_systick) - -EXTERN(__irq_wwdg) -EXTERN(__irq_pvd) -EXTERN(__irq_tamper) -EXTERN(__irq_rtc) -EXTERN(__irq_flash) -EXTERN(__irq_rcc) -EXTERN(__irq_exti0) -EXTERN(__irq_exti1) -EXTERN(__irq_exti2) -EXTERN(__irq_exti3) -EXTERN(__irq_exti4) -EXTERN(__irq_dma1_channel1) -EXTERN(__irq_dma1_channel2) -EXTERN(__irq_dma1_channel3) -EXTERN(__irq_dma1_channel4) -EXTERN(__irq_dma1_channel5) -EXTERN(__irq_dma1_channel6) -EXTERN(__irq_dma1_channel7) -EXTERN(__irq_adc) -EXTERN(__irq_usb_hp_can_tx) -EXTERN(__irq_usb_lp_can_rx0) -EXTERN(__irq_can_rx1) -EXTERN(__irq_can_sce) -EXTERN(__irq_exti9_5) -EXTERN(__irq_tim1_brk) -EXTERN(__irq_tim1_up) -EXTERN(__irq_tim1_trg_com) -EXTERN(__irq_tim1_cc) -EXTERN(__irq_tim2) -EXTERN(__irq_tim3) -EXTERN(__irq_tim4) -EXTERN(__irq_i2c1_ev) -EXTERN(__irq_i2c1_er) -EXTERN(__irq_i2c2_ev) -EXTERN(__irq_i2c2_er) -EXTERN(__irq_spi1) -EXTERN(__irq_spi2) -EXTERN(__irq_usart1) -EXTERN(__irq_usart2) -EXTERN(__irq_usart3) -EXTERN(__irq_exti15_10) -EXTERN(__irq_rtcalarm) -EXTERN(__irq_usbwakeup) - -EXTERN(__irq_tim8_brk) -EXTERN(__irq_tim8_up) -EXTERN(__irq_tim8_trg_com) -EXTERN(__irq_tim8_cc) -EXTERN(__irq_adc3) -EXTERN(__irq_fsmc) -EXTERN(__irq_sdio) -EXTERN(__irq_tim5) -EXTERN(__irq_spi3) -EXTERN(__irq_uart4) -EXTERN(__irq_uart5) -EXTERN(__irq_tim6) -EXTERN(__irq_tim7) -EXTERN(__irq_dma2_channel1) -EXTERN(__irq_dma2_channel2) -EXTERN(__irq_dma2_channel3) -EXTERN(__irq_dma2_channel4_5) diff --git a/support/ld/stm32/series/f1/performance/vector_symbols.inc b/support/ld/stm32/series/f1/performance/vector_symbols.inc new file mode 100644 index 0000000..f8519bb --- /dev/null +++ b/support/ld/stm32/series/f1/performance/vector_symbols.inc @@ -0,0 +1,78 @@ +EXTERN(__msp_init) +EXTERN(__exc_reset) +EXTERN(__exc_nmi) +EXTERN(__exc_hardfault) +EXTERN(__exc_memmanage) +EXTERN(__exc_busfault) +EXTERN(__exc_usagefault) +EXTERN(__stm32reservedexception7) +EXTERN(__stm32reservedexception8) +EXTERN(__stm32reservedexception9) +EXTERN(__stm32reservedexception10) +EXTERN(__exc_svc) +EXTERN(__exc_debug_monitor) +EXTERN(__stm32reservedexception13) +EXTERN(__exc_pendsv) +EXTERN(__exc_systick) + +EXTERN(__irq_wwdg) +EXTERN(__irq_pvd) +EXTERN(__irq_tamper) +EXTERN(__irq_rtc) +EXTERN(__irq_flash) +EXTERN(__irq_rcc) +EXTERN(__irq_exti0) +EXTERN(__irq_exti1) +EXTERN(__irq_exti2) +EXTERN(__irq_exti3) +EXTERN(__irq_exti4) +EXTERN(__irq_dma1_channel1) +EXTERN(__irq_dma1_channel2) +EXTERN(__irq_dma1_channel3) +EXTERN(__irq_dma1_channel4) +EXTERN(__irq_dma1_channel5) +EXTERN(__irq_dma1_channel6) +EXTERN(__irq_dma1_channel7) +EXTERN(__irq_adc) +EXTERN(__irq_usb_hp_can_tx) +EXTERN(__irq_usb_lp_can_rx0) +EXTERN(__irq_can_rx1) +EXTERN(__irq_can_sce) +EXTERN(__irq_exti9_5) +EXTERN(__irq_tim1_brk) +EXTERN(__irq_tim1_up) +EXTERN(__irq_tim1_trg_com) +EXTERN(__irq_tim1_cc) +EXTERN(__irq_tim2) +EXTERN(__irq_tim3) +EXTERN(__irq_tim4) +EXTERN(__irq_i2c1_ev) +EXTERN(__irq_i2c1_er) +EXTERN(__irq_i2c2_ev) +EXTERN(__irq_i2c2_er) +EXTERN(__irq_spi1) +EXTERN(__irq_spi2) +EXTERN(__irq_usart1) +EXTERN(__irq_usart2) +EXTERN(__irq_usart3) +EXTERN(__irq_exti15_10) +EXTERN(__irq_rtcalarm) +EXTERN(__irq_usbwakeup) + +EXTERN(__irq_tim8_brk) +EXTERN(__irq_tim8_up) +EXTERN(__irq_tim8_trg_com) +EXTERN(__irq_tim8_cc) +EXTERN(__irq_adc3) +EXTERN(__irq_fsmc) +EXTERN(__irq_sdio) +EXTERN(__irq_tim5) +EXTERN(__irq_spi3) +EXTERN(__irq_uart4) +EXTERN(__irq_uart5) +EXTERN(__irq_tim6) +EXTERN(__irq_tim7) +EXTERN(__irq_dma2_channel1) +EXTERN(__irq_dma2_channel2) +EXTERN(__irq_dma2_channel3) +EXTERN(__irq_dma2_channel4_5) diff --git a/support/make/target-config.mk b/support/make/target-config.mk index ea81b3b..2e360ea 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -53,14 +53,14 @@ TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ -DERROR_LED_PORT=$(ERROR_LED_PORT) \ -DERROR_LED_PIN=$(ERROR_LED_PIN) -# STM32 family-specific configuration values. +# STM32 series-specific configuration values. # NB: these only work for STM32F1 performance line chips, but those # are the only ones we support at this time. If you add support for # STM32F1 connectivity line MCUs or other STM32 families, this section # will need to change. -LD_FAMILY_PATH := $(LDDIR)/stm32/family/f1/performance -LIBMAPLE_MODULE_FAMILY := $(LIBMAPLE_PATH)/stm32f1 +LD_SERIES_PATH := $(LDDIR)/stm32/series/f1/performance +LIBMAPLE_MODULE_SERIES := $(LIBMAPLE_PATH)/stm32f1 # Memory target-specific configuration values -- cgit v1.2.3 From 3cbf2d87bfbf2d5c680525197dee861fe9a6c575 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 02:26:22 -0500 Subject: libmaple/stm32: Add enum stm32_series, STM32_MCU_SERIES. enum stm32_series gives a tag to each STM32 series, including the ones we don't yet support. STM32_MCU_SERIES is a define which the series stm32.h header must provide, identifying the series of the MCU being targeted. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 22 ++++++++++++++++++++-- libmaple/stm32f1/include/series/stm32.h | 4 +++- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 356a360..4c0898b 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -36,8 +36,21 @@ extern "C" { #endif -/* Everything enclosed in the following __DOXYGEN_PREDEFINED_HACK - * conditional block must be defined in the series header. */ +/** + * @brief STM32 series identifiers. + */ +typedef enum stm32_series { + STM32_SERIES_F1, /**< F1 series */ + STM32_SERIES_F2, /**< F2 series */ + STM32_SERIES_L1, /**< L1 series */ + STM32_SERIES_F4, /**< F4 series */ +} stm32_series; + +/* The series header is responsible for defining: + * + * - Everything enclosed in the following __DOXYGEN_PREDEFINED_HACK + * conditional block. + */ #include #ifdef __DOXYGEN_PREDEFINED_HACK @@ -69,6 +82,11 @@ extern "C" { * Series- and MCU-specific values. */ +/** + * @brief enum stm32_series value for the MCU being targeted. + */ +#define STM32_MCU_SERIES + /** * @brief Number of interrupts in the vector table. * diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index f0ca616..86f0294 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -66,9 +66,11 @@ extern "C" { #endif /* - * MCU-specific values. + * Series- and MCU-specific values. */ +#define STM32_MCU_SERIES STM32_SERIES_F1 + #if defined(MCU_STM32F103RB) # define STM32_NR_GPIO_PORTS 4 # define STM32_SRAM_END ((void*)0x20005000) -- cgit v1.2.3 From a39a5af1cbc6f729f5577c52589538533de7c311 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 02:48:58 -0500 Subject: build system: Add board include files for target-config.mk. target-config.mk is getting a little long with all the boards in it. Break out the board-specific bits into individual files under support/make/board-includes. This has the added benefit that adding a new board requires less dirtying of the working tree, which is nice for jumping around branches with an experimental board. Signed-off-by: Marti Bolivar --- support/make/board-includes/maple.mk | 6 +++ support/make/board-includes/maple_RET6.mk | 6 +++ support/make/board-includes/maple_mini.mk | 6 +++ support/make/board-includes/maple_native.mk | 6 +++ support/make/board-includes/olimex_stm32_h103.mk | 6 +++ support/make/target-config.mk | 48 ++---------------------- 6 files changed, 33 insertions(+), 45 deletions(-) create mode 100644 support/make/board-includes/maple.mk create mode 100644 support/make/board-includes/maple_RET6.mk create mode 100644 support/make/board-includes/maple_mini.mk create mode 100644 support/make/board-includes/maple_native.mk create mode 100644 support/make/board-includes/olimex_stm32_h103.mk diff --git a/support/make/board-includes/maple.mk b/support/make/board-includes/maple.mk new file mode 100644 index 0000000..3c83ee7 --- /dev/null +++ b/support/make/board-includes/maple.mk @@ -0,0 +1,6 @@ +MCU := STM32F103RB +PRODUCT_ID := 0003 +ERROR_LED_PORT := GPIOA +ERROR_LED_PIN := 5 +DENSITY := STM32_MEDIUM_DENSITY +TARGET_FLAGS += -D$(DENSITY) diff --git a/support/make/board-includes/maple_RET6.mk b/support/make/board-includes/maple_RET6.mk new file mode 100644 index 0000000..3f61867 --- /dev/null +++ b/support/make/board-includes/maple_RET6.mk @@ -0,0 +1,6 @@ +MCU := STM32F103RE +PRODUCT_ID := 0003 +ERROR_LED_PORT := GPIOA +ERROR_LED_PIN := 5 +DENSITY := STM32_HIGH_DENSITY +TARGET_FLAGS += -D$(DENSITY) diff --git a/support/make/board-includes/maple_mini.mk b/support/make/board-includes/maple_mini.mk new file mode 100644 index 0000000..b1afa4f --- /dev/null +++ b/support/make/board-includes/maple_mini.mk @@ -0,0 +1,6 @@ +MCU := STM32F103CB +PRODUCT_ID := 0003 +ERROR_LED_PORT := GPIOB +ERROR_LED_PIN := 1 +DENSITY := STM32_MEDIUM_DENSITY +TARGET_FLAGS += -D$(DENSITY) diff --git a/support/make/board-includes/maple_native.mk b/support/make/board-includes/maple_native.mk new file mode 100644 index 0000000..555d71b --- /dev/null +++ b/support/make/board-includes/maple_native.mk @@ -0,0 +1,6 @@ +MCU := STM32F103ZE +PRODUCT_ID := 0003 +ERROR_LED_PORT := GPIOC +ERROR_LED_PIN := 15 +DENSITY := STM32_HIGH_DENSITY +TARGET_FLAGS += -D$(DENSITY) diff --git a/support/make/board-includes/olimex_stm32_h103.mk b/support/make/board-includes/olimex_stm32_h103.mk new file mode 100644 index 0000000..6b45c17 --- /dev/null +++ b/support/make/board-includes/olimex_stm32_h103.mk @@ -0,0 +1,6 @@ +MCU := STM32F103RB +PRODUCT_ID := 0003 +ERROR_LED_PORT := GPIOC +ERROR_LED_PIN := 12 +DENSITY := STM32_MEDIUM_DENSITY +TARGET_FLAGS += -D$(DENSITY) diff --git a/support/make/target-config.mk b/support/make/target-config.mk index 2e360ea..fcedd3e 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -2,52 +2,10 @@ TARGET_FLAGS := -# Board-specific configuration values. Flash and SRAM sizes in bytes. +# Board-specific configuration values. Punt these to board-specific +# include files. -ifeq ($(BOARD), maple) - MCU := STM32F103RB - PRODUCT_ID := 0003 - ERROR_LED_PORT := GPIOA - ERROR_LED_PIN := 5 - DENSITY := STM32_MEDIUM_DENSITY - TARGET_FLAGS += -D$(DENSITY) -endif - -ifeq ($(BOARD), maple_native) - MCU := STM32F103ZE - PRODUCT_ID := 0003 - ERROR_LED_PORT := GPIOC - ERROR_LED_PIN := 15 - DENSITY := STM32_HIGH_DENSITY - TARGET_FLAGS += -D$(DENSITY) -endif - -ifeq ($(BOARD), maple_mini) - MCU := STM32F103CB - PRODUCT_ID := 0003 - ERROR_LED_PORT := GPIOB - ERROR_LED_PIN := 1 - DENSITY := STM32_MEDIUM_DENSITY - TARGET_FLAGS += -D$(DENSITY) -endif - -ifeq ($(BOARD), maple_RET6) - MCU := STM32F103RE - PRODUCT_ID := 0003 - ERROR_LED_PORT := GPIOA - ERROR_LED_PIN := 5 - DENSITY := STM32_HIGH_DENSITY - TARGET_FLAGS += -D$(DENSITY) -endif - -ifeq ($(BOARD), olimex_stm32_h103) - MCU := STM32F103RB - PRODUCT_ID := 0003 - ERROR_LED_PORT := GPIOC - ERROR_LED_PIN := 12 - DENSITY := STM32_MEDIUM_DENSITY - TARGET_FLAGS += -D$(DENSITY) -endif +include $(MAKEDIR)/board-includes/$(BOARD).mk TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ -DERROR_LED_PORT=$(ERROR_LED_PORT) \ -- cgit v1.2.3 From fe0a91587655c639443f42be6a9792d81a0b7982 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 02:49:16 -0500 Subject: Makefile: use $(MAKEDIR) instead of $(SUPPORT_PATH)/make. Signed-off-by: Marti Bolivar --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 1e00ed6..9b37580 100644 --- a/Makefile +++ b/Makefile @@ -62,8 +62,8 @@ LDFLAGS = -T$(LDDIR)/$(LDSCRIPT) -L$(LDDIR) \ ## Build rules and useful templates ## -include $(SUPPORT_PATH)/make/build-rules.mk -include $(SUPPORT_PATH)/make/build-templates.mk +include $(MAKEDIR)/build-rules.mk +include $(MAKEDIR)/build-templates.mk ## ## Set all submodules here -- cgit v1.2.3 From 3b127a9bcdcfee2c6648b3014585b6ed60060c10 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 18 Jan 2012 18:43:58 -0500 Subject: Delete .gdbinit. This is specific to openocd; it shouldn't be here. Signed-off-by: Marti Bolivar --- .gdbinit | 9 --------- 1 file changed, 9 deletions(-) delete mode 100644 .gdbinit diff --git a/.gdbinit b/.gdbinit deleted file mode 100644 index 9e88d09..0000000 --- a/.gdbinit +++ /dev/null @@ -1,9 +0,0 @@ -target remote localhost:3333 -symbol-file build/maple.elf -source test.gdb -delete breakpoints -##break main.cpp:setup() -##monitor reset halt -#display/i $pc -# display/x *0xe000ed2c -# display/x *0xE000ED28 -- cgit v1.2.3 From a7652cebf2603007e01d3af166a5c17596e8f207 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 14:31:31 -0500 Subject: Add build support for targeting multiple STM32 series. Add an MCU_SERIES variable to each of the files under support/make/board-includes, which declares the series as "stm32f1" in each case. Use this in target-config.mk when determining LD_SERIES_PATH (with a hack since we only support performance line) and LIBMAPLE_MODULE_SERIES. We must move support/ld/stm32/series/f1 to .../series/stm32f1 as a side-effect. Adding support for other series (e.g. "stm32f2") should now be a matter of filling in the contents of libmaple// and support/ld/stm32// appropriately (along with moving the rest of the nonportable code out of the libmaple core and into the STM32F1 series submodule). Signed-off-by: Marti Bolivar --- .../stm32/series/f1/performance/vector_symbols.inc | 78 ---------------------- .../series/stm32f1/performance/vector_symbols.inc | 78 ++++++++++++++++++++++ support/make/board-includes/maple.mk | 1 + support/make/board-includes/maple_RET6.mk | 1 + support/make/board-includes/maple_mini.mk | 1 + support/make/board-includes/maple_native.mk | 1 + support/make/board-includes/olimex_stm32_h103.mk | 1 + support/make/target-config.mk | 13 ++-- 8 files changed, 90 insertions(+), 84 deletions(-) delete mode 100644 support/ld/stm32/series/f1/performance/vector_symbols.inc create mode 100644 support/ld/stm32/series/stm32f1/performance/vector_symbols.inc diff --git a/support/ld/stm32/series/f1/performance/vector_symbols.inc b/support/ld/stm32/series/f1/performance/vector_symbols.inc deleted file mode 100644 index f8519bb..0000000 --- a/support/ld/stm32/series/f1/performance/vector_symbols.inc +++ /dev/null @@ -1,78 +0,0 @@ -EXTERN(__msp_init) -EXTERN(__exc_reset) -EXTERN(__exc_nmi) -EXTERN(__exc_hardfault) -EXTERN(__exc_memmanage) -EXTERN(__exc_busfault) -EXTERN(__exc_usagefault) -EXTERN(__stm32reservedexception7) -EXTERN(__stm32reservedexception8) -EXTERN(__stm32reservedexception9) -EXTERN(__stm32reservedexception10) -EXTERN(__exc_svc) -EXTERN(__exc_debug_monitor) -EXTERN(__stm32reservedexception13) -EXTERN(__exc_pendsv) -EXTERN(__exc_systick) - -EXTERN(__irq_wwdg) -EXTERN(__irq_pvd) -EXTERN(__irq_tamper) -EXTERN(__irq_rtc) -EXTERN(__irq_flash) -EXTERN(__irq_rcc) -EXTERN(__irq_exti0) -EXTERN(__irq_exti1) -EXTERN(__irq_exti2) -EXTERN(__irq_exti3) -EXTERN(__irq_exti4) -EXTERN(__irq_dma1_channel1) -EXTERN(__irq_dma1_channel2) -EXTERN(__irq_dma1_channel3) -EXTERN(__irq_dma1_channel4) -EXTERN(__irq_dma1_channel5) -EXTERN(__irq_dma1_channel6) -EXTERN(__irq_dma1_channel7) -EXTERN(__irq_adc) -EXTERN(__irq_usb_hp_can_tx) -EXTERN(__irq_usb_lp_can_rx0) -EXTERN(__irq_can_rx1) -EXTERN(__irq_can_sce) -EXTERN(__irq_exti9_5) -EXTERN(__irq_tim1_brk) -EXTERN(__irq_tim1_up) -EXTERN(__irq_tim1_trg_com) -EXTERN(__irq_tim1_cc) -EXTERN(__irq_tim2) -EXTERN(__irq_tim3) -EXTERN(__irq_tim4) -EXTERN(__irq_i2c1_ev) -EXTERN(__irq_i2c1_er) -EXTERN(__irq_i2c2_ev) -EXTERN(__irq_i2c2_er) -EXTERN(__irq_spi1) -EXTERN(__irq_spi2) -EXTERN(__irq_usart1) -EXTERN(__irq_usart2) -EXTERN(__irq_usart3) -EXTERN(__irq_exti15_10) -EXTERN(__irq_rtcalarm) -EXTERN(__irq_usbwakeup) - -EXTERN(__irq_tim8_brk) -EXTERN(__irq_tim8_up) -EXTERN(__irq_tim8_trg_com) -EXTERN(__irq_tim8_cc) -EXTERN(__irq_adc3) -EXTERN(__irq_fsmc) -EXTERN(__irq_sdio) -EXTERN(__irq_tim5) -EXTERN(__irq_spi3) -EXTERN(__irq_uart4) -EXTERN(__irq_uart5) -EXTERN(__irq_tim6) -EXTERN(__irq_tim7) -EXTERN(__irq_dma2_channel1) -EXTERN(__irq_dma2_channel2) -EXTERN(__irq_dma2_channel3) -EXTERN(__irq_dma2_channel4_5) diff --git a/support/ld/stm32/series/stm32f1/performance/vector_symbols.inc b/support/ld/stm32/series/stm32f1/performance/vector_symbols.inc new file mode 100644 index 0000000..f8519bb --- /dev/null +++ b/support/ld/stm32/series/stm32f1/performance/vector_symbols.inc @@ -0,0 +1,78 @@ +EXTERN(__msp_init) +EXTERN(__exc_reset) +EXTERN(__exc_nmi) +EXTERN(__exc_hardfault) +EXTERN(__exc_memmanage) +EXTERN(__exc_busfault) +EXTERN(__exc_usagefault) +EXTERN(__stm32reservedexception7) +EXTERN(__stm32reservedexception8) +EXTERN(__stm32reservedexception9) +EXTERN(__stm32reservedexception10) +EXTERN(__exc_svc) +EXTERN(__exc_debug_monitor) +EXTERN(__stm32reservedexception13) +EXTERN(__exc_pendsv) +EXTERN(__exc_systick) + +EXTERN(__irq_wwdg) +EXTERN(__irq_pvd) +EXTERN(__irq_tamper) +EXTERN(__irq_rtc) +EXTERN(__irq_flash) +EXTERN(__irq_rcc) +EXTERN(__irq_exti0) +EXTERN(__irq_exti1) +EXTERN(__irq_exti2) +EXTERN(__irq_exti3) +EXTERN(__irq_exti4) +EXTERN(__irq_dma1_channel1) +EXTERN(__irq_dma1_channel2) +EXTERN(__irq_dma1_channel3) +EXTERN(__irq_dma1_channel4) +EXTERN(__irq_dma1_channel5) +EXTERN(__irq_dma1_channel6) +EXTERN(__irq_dma1_channel7) +EXTERN(__irq_adc) +EXTERN(__irq_usb_hp_can_tx) +EXTERN(__irq_usb_lp_can_rx0) +EXTERN(__irq_can_rx1) +EXTERN(__irq_can_sce) +EXTERN(__irq_exti9_5) +EXTERN(__irq_tim1_brk) +EXTERN(__irq_tim1_up) +EXTERN(__irq_tim1_trg_com) +EXTERN(__irq_tim1_cc) +EXTERN(__irq_tim2) +EXTERN(__irq_tim3) +EXTERN(__irq_tim4) +EXTERN(__irq_i2c1_ev) +EXTERN(__irq_i2c1_er) +EXTERN(__irq_i2c2_ev) +EXTERN(__irq_i2c2_er) +EXTERN(__irq_spi1) +EXTERN(__irq_spi2) +EXTERN(__irq_usart1) +EXTERN(__irq_usart2) +EXTERN(__irq_usart3) +EXTERN(__irq_exti15_10) +EXTERN(__irq_rtcalarm) +EXTERN(__irq_usbwakeup) + +EXTERN(__irq_tim8_brk) +EXTERN(__irq_tim8_up) +EXTERN(__irq_tim8_trg_com) +EXTERN(__irq_tim8_cc) +EXTERN(__irq_adc3) +EXTERN(__irq_fsmc) +EXTERN(__irq_sdio) +EXTERN(__irq_tim5) +EXTERN(__irq_spi3) +EXTERN(__irq_uart4) +EXTERN(__irq_uart5) +EXTERN(__irq_tim6) +EXTERN(__irq_tim7) +EXTERN(__irq_dma2_channel1) +EXTERN(__irq_dma2_channel2) +EXTERN(__irq_dma2_channel3) +EXTERN(__irq_dma2_channel4_5) diff --git a/support/make/board-includes/maple.mk b/support/make/board-includes/maple.mk index 3c83ee7..a84f0ac 100644 --- a/support/make/board-includes/maple.mk +++ b/support/make/board-includes/maple.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 DENSITY := STM32_MEDIUM_DENSITY TARGET_FLAGS += -D$(DENSITY) +MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/maple_RET6.mk b/support/make/board-includes/maple_RET6.mk index 3f61867..8bd9b90 100644 --- a/support/make/board-includes/maple_RET6.mk +++ b/support/make/board-includes/maple_RET6.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 DENSITY := STM32_HIGH_DENSITY TARGET_FLAGS += -D$(DENSITY) +MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/maple_mini.mk b/support/make/board-includes/maple_mini.mk index b1afa4f..4a3e2ab 100644 --- a/support/make/board-includes/maple_mini.mk +++ b/support/make/board-includes/maple_mini.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOB ERROR_LED_PIN := 1 DENSITY := STM32_MEDIUM_DENSITY TARGET_FLAGS += -D$(DENSITY) +MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/maple_native.mk b/support/make/board-includes/maple_native.mk index 555d71b..cd07c21 100644 --- a/support/make/board-includes/maple_native.mk +++ b/support/make/board-includes/maple_native.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 15 DENSITY := STM32_HIGH_DENSITY TARGET_FLAGS += -D$(DENSITY) +MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/olimex_stm32_h103.mk b/support/make/board-includes/olimex_stm32_h103.mk index 6b45c17..1d84cc2 100644 --- a/support/make/board-includes/olimex_stm32_h103.mk +++ b/support/make/board-includes/olimex_stm32_h103.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 12 DENSITY := STM32_MEDIUM_DENSITY TARGET_FLAGS += -D$(DENSITY) +MCU_SERIES := stm32f1 diff --git a/support/make/target-config.mk b/support/make/target-config.mk index fcedd3e..48a33de 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -13,12 +13,13 @@ TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ # STM32 series-specific configuration values. -# NB: these only work for STM32F1 performance line chips, but those -# are the only ones we support at this time. If you add support for -# STM32F1 connectivity line MCUs or other STM32 families, this section -# will need to change. -LD_SERIES_PATH := $(LDDIR)/stm32/series/f1/performance -LIBMAPLE_MODULE_SERIES := $(LIBMAPLE_PATH)/stm32f1 +LD_SERIES_PATH := $(LDDIR)/stm32/series/$(MCU_SERIES) +ifeq ($(MCU_SERIES), stm32f1) + # Hack: force F1 to performance line; this will need to change if + # you add connectivity etc. line support. + LD_SERIES_PATH := $(LD_SERIES_PATH)/performance +endif +LIBMAPLE_MODULE_SERIES := $(LIBMAPLE_PATH)/$(MCU_SERIES) # Memory target-specific configuration values -- cgit v1.2.3 From 9fadd89bd9ce6de5377a493f46ba5212097b2204 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 15:54:59 -0500 Subject: Make BKP support STM32F1-only. - libmaple/bkp.h: Mark availability restriction. - Move libmaple/bkp.c to libmaple/stm32f1; adjust rules.mk files accordingly. Signed-off-by: Marti Bolivar --- libmaple/bkp.c | 129 ---------------------------------------- libmaple/include/libmaple/bkp.h | 2 +- libmaple/rules.mk | 1 - libmaple/stm32f1/bkp.c | 129 ++++++++++++++++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 1 + 5 files changed, 131 insertions(+), 131 deletions(-) delete mode 100644 libmaple/bkp.c create mode 100644 libmaple/stm32f1/bkp.c diff --git a/libmaple/bkp.c b/libmaple/bkp.c deleted file mode 100644 index 62783e7..0000000 --- a/libmaple/bkp.c +++ /dev/null @@ -1,129 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file bkp.c - * @brief Backup register support. - */ - -#include -#include -#include -#include - -static inline __io uint32* data_register(uint8 reg); - -bkp_dev bkp = { - .regs = BKP_BASE, -}; -/** Backup device. */ -const bkp_dev *BKP = &bkp; - -/** - * @brief Initialize backup interface. - * - * Enables the power and backup interface clocks, and resets the - * backup device. - */ -void bkp_init(void) { - /* Don't call pwr_init(), or you'll reset the device. We just - * need the clock. */ - rcc_clk_enable(RCC_PWR); - rcc_clk_enable(RCC_BKP); - rcc_reset_dev(RCC_BKP); -} - -/** - * Enable write access to the backup registers. Backup interface must - * be initialized for subsequent register writes to work. - * @see bkp_init() - */ -void bkp_enable_writes(void) { - *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 1; -} - -/** - * Disable write access to the backup registers. - */ -void bkp_disable_writes(void) { - *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 0; -} - -/** - * Read a value from given backup data register. - * @param reg Data register to read, from 1 to BKP_NR_DATA_REGS (10 on - * medium-density devices, 42 on high-density devices). - */ -uint16 bkp_read(uint8 reg) { - __io uint32* dr = data_register(reg); - if (!dr) { - ASSERT(0); /* nonexistent register */ - return 0; - } - return (uint16)*dr; -} - -/** - * @brief Write a value to given data register. - * - * Write access to backup registers must be enabled. - * - * @param reg Data register to write, from 1 to BKP_NR_DATA_REGS (10 - * on medium-density devices, 42 on high-density devices). - * @param val Value to write into the register. - * @see bkp_enable_writes() - */ -void bkp_write(uint8 reg, uint16 val) { - __io uint32* dr = data_register(reg); - if (!dr) { - ASSERT(0); /* nonexistent register */ - return; - } - *dr = (uint32)val; -} - -/* - * Data register memory layout is not contiguous. It's split up from - * 1--NR_LOW_DRS, beginning at BKP_BASE->DR1, through to - * (NR_LOW_DRS+1)--BKP_NR_DATA_REGS, beginning at BKP_BASE->DR11. - */ -#define NR_LOW_DRS 10 - -static inline __io uint32* data_register(uint8 reg) { - if (reg < 1 || reg > BKP_NR_DATA_REGS) { - return 0; - } - -#if BKP_NR_DATA_REGS == NR_LOW_DRS - return (uint32*)BKP_BASE + reg; -#else - if (reg <= NR_LOW_DRS) { - return (uint32*)BKP_BASE + reg; - } else { - return (uint32*)&(BKP_BASE->DR11) + (reg - NR_LOW_DRS - 1); - } -#endif -} diff --git a/libmaple/include/libmaple/bkp.h b/libmaple/include/libmaple/bkp.h index 92359b6..7f90c0c 100644 --- a/libmaple/include/libmaple/bkp.h +++ b/libmaple/include/libmaple/bkp.h @@ -26,7 +26,7 @@ /** * @file bkp.h - * @brief Backup register support. + * @brief Backup register support (STM32F1 only). */ #ifndef _LIBMAPLE_BKP_H_ diff --git a/libmaple/rules.mk b/libmaple/rules.mk index f0776a7..61d4edd 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -12,7 +12,6 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c \ - bkp.c \ dac.c \ dma.c \ exti.c \ diff --git a/libmaple/stm32f1/bkp.c b/libmaple/stm32f1/bkp.c new file mode 100644 index 0000000..62783e7 --- /dev/null +++ b/libmaple/stm32f1/bkp.c @@ -0,0 +1,129 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file bkp.c + * @brief Backup register support. + */ + +#include +#include +#include +#include + +static inline __io uint32* data_register(uint8 reg); + +bkp_dev bkp = { + .regs = BKP_BASE, +}; +/** Backup device. */ +const bkp_dev *BKP = &bkp; + +/** + * @brief Initialize backup interface. + * + * Enables the power and backup interface clocks, and resets the + * backup device. + */ +void bkp_init(void) { + /* Don't call pwr_init(), or you'll reset the device. We just + * need the clock. */ + rcc_clk_enable(RCC_PWR); + rcc_clk_enable(RCC_BKP); + rcc_reset_dev(RCC_BKP); +} + +/** + * Enable write access to the backup registers. Backup interface must + * be initialized for subsequent register writes to work. + * @see bkp_init() + */ +void bkp_enable_writes(void) { + *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 1; +} + +/** + * Disable write access to the backup registers. + */ +void bkp_disable_writes(void) { + *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 0; +} + +/** + * Read a value from given backup data register. + * @param reg Data register to read, from 1 to BKP_NR_DATA_REGS (10 on + * medium-density devices, 42 on high-density devices). + */ +uint16 bkp_read(uint8 reg) { + __io uint32* dr = data_register(reg); + if (!dr) { + ASSERT(0); /* nonexistent register */ + return 0; + } + return (uint16)*dr; +} + +/** + * @brief Write a value to given data register. + * + * Write access to backup registers must be enabled. + * + * @param reg Data register to write, from 1 to BKP_NR_DATA_REGS (10 + * on medium-density devices, 42 on high-density devices). + * @param val Value to write into the register. + * @see bkp_enable_writes() + */ +void bkp_write(uint8 reg, uint16 val) { + __io uint32* dr = data_register(reg); + if (!dr) { + ASSERT(0); /* nonexistent register */ + return; + } + *dr = (uint32)val; +} + +/* + * Data register memory layout is not contiguous. It's split up from + * 1--NR_LOW_DRS, beginning at BKP_BASE->DR1, through to + * (NR_LOW_DRS+1)--BKP_NR_DATA_REGS, beginning at BKP_BASE->DR11. + */ +#define NR_LOW_DRS 10 + +static inline __io uint32* data_register(uint8 reg) { + if (reg < 1 || reg > BKP_NR_DATA_REGS) { + return 0; + } + +#if BKP_NR_DATA_REGS == NR_LOW_DRS + return (uint32*)BKP_BASE + reg; +#else + if (reg <= NR_LOW_DRS) { + return (uint32*)BKP_BASE + reg; + } else { + return (uint32*)&(BKP_BASE->DR11) + (reg - NR_LOW_DRS - 1); + } +#endif +} diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 5267e9b..32b3a2c 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -14,6 +14,7 @@ sSRCS_$(d) := isrs_performance.S \ cSRCS_$(d) := rcc.c cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c +cSRCS_$(d) += bkp.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 2173140656b28e60cabfddd808301df301e32cd5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 19:58:59 -0500 Subject: support/ld: Add STM32F2 vector symbols. Signed-off-by: Marti Bolivar --- support/ld/stm32/series/stm32f2/vector_symbols.inc | 98 ++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 support/ld/stm32/series/stm32f2/vector_symbols.inc diff --git a/support/ld/stm32/series/stm32f2/vector_symbols.inc b/support/ld/stm32/series/stm32f2/vector_symbols.inc new file mode 100644 index 0000000..d275ec3 --- /dev/null +++ b/support/ld/stm32/series/stm32f2/vector_symbols.inc @@ -0,0 +1,98 @@ +EXTERN(__msp_init) +EXTERN(__exc_reset) +EXTERN(__exc_nmi) +EXTERN(__exc_hardfault) +EXTERN(__exc_memmanage) +EXTERN(__exc_busfault) +EXTERN(__exc_usagefault) +EXTERN(__stm32reservedexception7) +EXTERN(__stm32reservedexception8) +EXTERN(__stm32reservedexception9) +EXTERN(__stm32reservedexception10) +EXTERN(__exc_svc) +EXTERN(__exc_debug_monitor) +EXTERN(__stm32reservedexception13) +EXTERN(__exc_pendsv) +EXTERN(__exc_systick) + +EXTERN(__irq_wwdg) +EXTERN(__irq_pvd) +EXTERN(__irq_tamp_stamp) +EXTERN(__irq_rtc_wkup) +EXTERN(__irq_flash) +EXTERN(__irq_rcc) +EXTERN(__irq_exti0) +EXTERN(__irq_exti1) +EXTERN(__irq_exti2) +EXTERN(__irq_exti3) +EXTERN(__irq_exti4) +EXTERN(__irq_dma1_stream0) +EXTERN(__irq_dma1_stream1) +EXTERN(__irq_dma1_stream2) +EXTERN(__irq_dma1_stream3) +EXTERN(__irq_dma1_stream4) +EXTERN(__irq_dma1_stream5) +EXTERN(__irq_dma1_stream6) +EXTERN(__irq_adc) +EXTERN(__irq_can1_tx) +EXTERN(__irq_can1_rx0) +EXTERN(__irq_can1_rx1) +EXTERN(__irq_can1_sce) +EXTERN(__irq_exti9_5) +EXTERN(__irq_tim1_brk_tim9) +EXTERN(__irq_tim1_up_tim10) +EXTERN(__irq_tim1_trg_com_tim11) +EXTERN(__irq_tim1_cc) +EXTERN(__irq_tim2) +EXTERN(__irq_tim3) +EXTERN(__irq_tim4) +EXTERN(__irq_i2c1_ev) +EXTERN(__irq_i2c1_er) +EXTERN(__irq_i2c2_ev) +EXTERN(__irq_i2c2_er) +EXTERN(__irq_spi1) +EXTERN(__irq_spi2) +EXTERN(__irq_usart1) +EXTERN(__irq_usart2) +EXTERN(__irq_usart3) +EXTERN(__irq_exti15_10) +EXTERN(__irq_rtc_alarm) +EXTERN(__irq_otg_fs_wkup) +EXTERN(__irq_tim8_brk_tim12) +EXTERN(__irq_tim8_up_tim13) +EXTERN(__irq_tim8_trg_com_tim14) +EXTERN(__irq_tim8_cc) +EXTERN(__irq_dma1_stream7) +EXTERN(__irq_fsmc) +EXTERN(__irq_sdio) +EXTERN(__irq_tim5) +EXTERN(__irq_spi3) +EXTERN(__irq_uart4) +EXTERN(__irq_uart5) +EXTERN(__irq_tim6_dac) +EXTERN(__irq_tim7) +EXTERN(__irq_dma2_stream0) +EXTERN(__irq_dma2_stream1) +EXTERN(__irq_dma2_stream2) +EXTERN(__irq_dma2_stream3) +EXTERN(__irq_dma2_stream4) +EXTERN(__irq_eth) +EXTERN(__irq_eth_wkup) +EXTERN(__irq_can2_tx) +EXTERN(__irq_can2_rx0) +EXTERN(__irq_can2_rx1) +EXTERN(__irq_can2_sce) +EXTERN(__irq_otg_fs) +EXTERN(__irq_dma2_stream5) +EXTERN(__irq_dma2_stream6) +EXTERN(__irq_dma2_stream7) +EXTERN(__irq_usart6) +EXTERN(__irq_i2c3_ev) +EXTERN(__irq_i2c3_er) +EXTERN(__irq_otg_hs_ep1_out) +EXTERN(__irq_otg_hs_ep1_in) +EXTERN(__irq_otg_hs_wkup) +EXTERN(__irq_otg_hs) +EXTERN(__irq_dcmi) +EXTERN(__irq_cryp) +EXTERN(__irq_hash_rng) -- cgit v1.2.3 From 3ff544c9e881186ae8d939233ef24ccb71d9e33e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 19:16:41 -0500 Subject: Add skeleton libmaple/stm32f2/rules.mk. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/rules.mk | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 libmaple/stm32f2/rules.mk diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk new file mode 100644 index 0000000..89b48ee --- /dev/null +++ b/libmaple/stm32f2/rules.mk @@ -0,0 +1,29 @@ +# Standard things +sp := $(sp).x +dirstack_$(sp) := $(d) +d := $(dir) +BUILDDIRS += $(BUILD_PATH)/$(d) + +# Local flags +CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -Werror + +# Local rules and targets +sSRCS_$(d) := +cSRCS_$(d) := + +sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) +cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) + +OBJS_$(d) := $(sFILES_$(d):%.S=$(BUILD_PATH)/%.o) \ + $(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) +DEPS_$(d) := $(OBJS_$(d):%.o=%.d) + +$(OBJS_$(d)): TGT_ASFLAGS := +$(OBJS_$(d)): TGT_CFLAGS := $(CFLAGS_$(d)) + +TGT_BIN += $(OBJS_$(d)) + +# Standard things +-include $(DEPS_$(d)) +d := $(dirstack_$(sp)) +sp := $(basename $(sp)) -- cgit v1.2.3 From a002eefe9ca71a2a942e16a01374c15ee12183d3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 19:40:41 -0500 Subject: STM32F2: Add vector table and weak ISR definitions. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/isrs.S | 322 ++++++++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 2 +- libmaple/stm32f2/vector_table.S | 135 +++++++++++++++++ 3 files changed, 458 insertions(+), 1 deletion(-) create mode 100644 libmaple/stm32f2/isrs.S create mode 100644 libmaple/stm32f2/vector_table.S diff --git a/libmaple/stm32f2/isrs.S b/libmaple/stm32f2/isrs.S new file mode 100644 index 0000000..5baaf8b --- /dev/null +++ b/libmaple/stm32f2/isrs.S @@ -0,0 +1,322 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F2 ISR weak declarations */ + + .thumb + +/* Default handler, as with STM32F1 */ + .globl __default_handler + .type __default_handler, %function + +__default_handler: + b . + + .weak __exc_nmi + .globl __exc_nmi + .set __exc_nmi, __default_handler + .weak __exc_hardfault + .globl __exc_hardfault + .set __exc_hardfault, __default_handler + .weak __exc_memmanage + .globl __exc_memmanage + .set __exc_memmanage, __default_handler + .weak __exc_busfault + .globl __exc_busfault + .set __exc_busfault, __default_handler + .weak __exc_usagefault + .globl __exc_usagefault + .set __exc_usagefault, __default_handler + .weak __stm32reservedexception7 + .globl __stm32reservedexception7 + .set __stm32reservedexception7, __default_handler + .weak __stm32reservedexception8 + .globl __stm32reservedexception8 + .set __stm32reservedexception8, __default_handler + .weak __stm32reservedexception9 + .globl __stm32reservedexception9 + .set __stm32reservedexception9, __default_handler + .weak __stm32reservedexception10 + .globl __stm32reservedexception10 + .set __stm32reservedexception10, __default_handler + .weak __exc_svc + .globl __exc_svc + .set __exc_svc, __default_handler + .weak __exc_debug_monitor + .globl __exc_debug_monitor + .set __exc_debug_monitor, __default_handler + .weak __stm32reservedexception13 + .globl __stm32reservedexception13 + .set __stm32reservedexception13, __default_handler + .weak __exc_pendsv + .globl __exc_pendsv + .set __exc_pendsv, __default_handler + .weak __exc_systick + .globl __exc_systick + .set __exc_systick, __default_handler + .weak __irq_wwdg + .globl __irq_wwdg + .set __irq_wwdg, __default_handler + .weak __irq_pvd + .globl __irq_pvd + .set __irq_pvd, __default_handler + .weak __irq_tamp_stamp + .globl __irq_tamp_stamp + .set __irq_tamp_stamp, __default_handler + .weak __irq_rtc_wkup + .globl __irq_rtc_wkup + .set __irq_rtc_wkup, __default_handler + .weak __irq_flash + .globl __irq_flash + .set __irq_flash, __default_handler + .weak __irq_rcc + .globl __irq_rcc + .set __irq_rcc, __default_handler + .weak __irq_exti0 + .globl __irq_exti0 + .set __irq_exti0, __default_handler + .weak __irq_exti1 + .globl __irq_exti1 + .set __irq_exti1, __default_handler + .weak __irq_exti2 + .globl __irq_exti2 + .set __irq_exti2, __default_handler + .weak __irq_exti3 + .globl __irq_exti3 + .set __irq_exti3, __default_handler + .weak __irq_exti4 + .globl __irq_exti4 + .set __irq_exti4, __default_handler + .weak __irq_dma1_stream0 + .globl __irq_dma1_stream0 + .set __irq_dma1_stream0, __default_handler + .weak __irq_dma1_stream1 + .globl __irq_dma1_stream1 + .set __irq_dma1_stream1, __default_handler + .weak __irq_dma1_stream2 + .globl __irq_dma1_stream2 + .set __irq_dma1_stream2, __default_handler + .weak __irq_dma1_stream3 + .globl __irq_dma1_stream3 + .set __irq_dma1_stream3, __default_handler + .weak __irq_dma1_stream4 + .globl __irq_dma1_stream4 + .set __irq_dma1_stream4, __default_handler + .weak __irq_dma1_stream5 + .globl __irq_dma1_stream5 + .set __irq_dma1_stream5, __default_handler + .weak __irq_dma1_stream6 + .globl __irq_dma1_stream6 + .set __irq_dma1_stream6, __default_handler + .weak __irq_adc + .globl __irq_adc + .set __irq_adc, __default_handler + .weak __irq_can1_tx + .globl __irq_can1_tx + .set __irq_can1_tx, __default_handler + .weak __irq_can1_rx0 + .globl __irq_can1_rx0 + .set __irq_can1_rx0, __default_handler + .weak __irq_can1_rx1 + .globl __irq_can1_rx1 + .set __irq_can1_rx1, __default_handler + .weak __irq_can1_sce + .globl __irq_can1_sce + .set __irq_can1_sce, __default_handler + .weak __irq_exti9_5 + .globl __irq_exti9_5 + .set __irq_exti9_5, __default_handler + .weak __irq_tim1_brk_tim9 + .globl __irq_tim1_brk_tim9 + .set __irq_tim1_brk_tim9, __default_handler + .weak __irq_tim1_up_tim10 + .globl __irq_tim1_up_tim10 + .set __irq_tim1_up_tim10, __default_handler + .weak __irq_tim1_trg_com_tim11 + .globl __irq_tim1_trg_com_tim11 + .set __irq_tim1_trg_com_tim11, __default_handler + .weak __irq_tim1_cc + .globl __irq_tim1_cc + .set __irq_tim1_cc, __default_handler + .weak __irq_tim2 + .globl __irq_tim2 + .set __irq_tim2, __default_handler + .weak __irq_tim3 + .globl __irq_tim3 + .set __irq_tim3, __default_handler + .weak __irq_tim4 + .globl __irq_tim4 + .set __irq_tim4, __default_handler + .weak __irq_i2c1_ev + .globl __irq_i2c1_ev + .set __irq_i2c1_ev, __default_handler + .weak __irq_i2c1_er + .globl __irq_i2c1_er + .set __irq_i2c1_er, __default_handler + .weak __irq_i2c2_ev + .globl __irq_i2c2_ev + .set __irq_i2c2_ev, __default_handler + .weak __irq_i2c2_er + .globl __irq_i2c2_er + .set __irq_i2c2_er, __default_handler + .weak __irq_spi1 + .globl __irq_spi1 + .set __irq_spi1, __default_handler + .weak __irq_spi2 + .globl __irq_spi2 + .set __irq_spi2, __default_handler + .weak __irq_usart1 + .globl __irq_usart1 + .set __irq_usart1, __default_handler + .weak __irq_usart2 + .globl __irq_usart2 + .set __irq_usart2, __default_handler + .weak __irq_usart3 + .globl __irq_usart3 + .set __irq_usart3, __default_handler + .weak __irq_exti15_10 + .globl __irq_exti15_10 + .set __irq_exti15_10, __default_handler + .weak __irq_rtc_alarm + .globl __irq_rtc_alarm + .set __irq_rtc_alarm, __default_handler + .weak __irq_otg_fs_wkup + .globl __irq_otg_fs_wkup + .set __irq_otg_fs_wkup, __default_handler + .weak __irq_tim8_brk_tim12 + .globl __irq_tim8_brk_tim12 + .set __irq_tim8_brk_tim12, __default_handler + .weak __irq_tim8_up_tim13 + .globl __irq_tim8_up_tim13 + .set __irq_tim8_up_tim13, __default_handler + .weak __irq_tim8_trg_com_tim14 + .globl __irq_tim8_trg_com_tim14 + .set __irq_tim8_trg_com_tim14, __default_handler + .weak __irq_tim8_cc + .globl __irq_tim8_cc + .set __irq_tim8_cc, __default_handler + .weak __irq_dma1_stream7 + .globl __irq_dma1_stream7 + .set __irq_dma1_stream7, __default_handler + .weak __irq_fsmc + .globl __irq_fsmc + .set __irq_fsmc, __default_handler + .weak __irq_sdio + .globl __irq_sdio + .set __irq_sdio, __default_handler + .weak __irq_tim5 + .globl __irq_tim5 + .set __irq_tim5, __default_handler + .weak __irq_spi3 + .globl __irq_spi3 + .set __irq_spi3, __default_handler + .weak __irq_uart4 + .globl __irq_uart4 + .set __irq_uart4, __default_handler + .weak __irq_uart5 + .globl __irq_uart5 + .set __irq_uart5, __default_handler + .weak __irq_tim6_dac + .globl __irq_tim6_dac + .set __irq_tim6_dac, __default_handler + .weak __irq_tim7 + .globl __irq_tim7 + .set __irq_tim7, __default_handler + .weak __irq_dma2_stream0 + .globl __irq_dma2_stream0 + .set __irq_dma2_stream0, __default_handler + .weak __irq_dma2_stream1 + .globl __irq_dma2_stream1 + .set __irq_dma2_stream1, __default_handler + .weak __irq_dma2_stream2 + .globl __irq_dma2_stream2 + .set __irq_dma2_stream2, __default_handler + .weak __irq_dma2_stream3 + .globl __irq_dma2_stream3 + .set __irq_dma2_stream3, __default_handler + .weak __irq_dma2_stream4 + .globl __irq_dma2_stream4 + .set __irq_dma2_stream4, __default_handler + .weak __irq_eth + .globl __irq_eth + .set __irq_eth, __default_handler + .weak __irq_eth_wkup + .globl __irq_eth_wkup + .set __irq_eth_wkup, __default_handler + .weak __irq_can2_tx + .globl __irq_can2_tx + .set __irq_can2_tx, __default_handler + .weak __irq_can2_rx0 + .globl __irq_can2_rx0 + .set __irq_can2_rx0, __default_handler + .weak __irq_can2_rx1 + .globl __irq_can2_rx1 + .set __irq_can2_rx1, __default_handler + .weak __irq_can2_sce + .globl __irq_can2_sce + .set __irq_can2_sce, __default_handler + .weak __irq_otg_fs + .globl __irq_otg_fs + .set __irq_otg_fs, __default_handler + .weak __irq_dma2_stream5 + .globl __irq_dma2_stream5 + .set __irq_dma2_stream5, __default_handler + .weak __irq_dma2_stream6 + .globl __irq_dma2_stream6 + .set __irq_dma2_stream6, __default_handler + .weak __irq_dma2_stream7 + .globl __irq_dma2_stream7 + .set __irq_dma2_stream7, __default_handler + .weak __irq_usart6 + .globl __irq_usart6 + .set __irq_usart6, __default_handler + .weak __irq_i2c3_ev + .globl __irq_i2c3_ev + .set __irq_i2c3_ev, __default_handler + .weak __irq_i2c3_er + .globl __irq_i2c3_er + .set __irq_i2c3_er, __default_handler + .weak __irq_otg_hs_ep1_out + .globl __irq_otg_hs_ep1_out + .set __irq_otg_hs_ep1_out, __default_handler + .weak __irq_otg_hs_ep1_in + .globl __irq_otg_hs_ep1_in + .set __irq_otg_hs_ep1_in, __default_handler + .weak __irq_otg_hs_wkup + .globl __irq_otg_hs_wkup + .set __irq_otg_hs_wkup, __default_handler + .weak __irq_otg_hs + .globl __irq_otg_hs + .set __irq_otg_hs, __default_handler + .weak __irq_dcmi + .globl __irq_dcmi + .set __irq_dcmi, __default_handler + .weak __irq_cryp + .globl __irq_cryp + .set __irq_cryp, __default_handler + .weak __irq_hash_rng + .globl __irq_hash_rng + .set __irq_hash_rng, __default_handler diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 89b48ee..afdcd4f 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -8,7 +8,7 @@ BUILDDIRS += $(BUILD_PATH)/$(d) CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -Werror # Local rules and targets -sSRCS_$(d) := +sSRCS_$(d) := isrs.S vector_table.S cSRCS_$(d) := sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f2/vector_table.S b/libmaple/stm32f2/vector_table.S new file mode 100644 index 0000000..147e516 --- /dev/null +++ b/libmaple/stm32f2/vector_table.S @@ -0,0 +1,135 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F2 vector table */ + + .section ".stm32.interrupt_vector" + + .globl __stm32_vector_table + .type __stm32_vector_table, %object + +__stm32_vector_table: +/* CM3 core interrupts */ + .long __msp_init + .long __exc_reset + .long __exc_nmi + .long __exc_hardfault + .long __exc_memmanage + .long __exc_busfault + .long __exc_usagefault + .long __stm32reservedexception7 + .long __stm32reservedexception8 + .long __stm32reservedexception9 + .long __stm32reservedexception10 + .long __exc_svc + .long __exc_debug_monitor + .long __stm32reservedexception13 + .long __exc_pendsv + .long __exc_systick +/* Peripheral interrupts */ + .long __irq_wwdg + .long __irq_pvd + .long __irq_tamp_stamp + .long __irq_rtc_wkup + .long __irq_flash + .long __irq_rcc + .long __irq_exti0 + .long __irq_exti1 + .long __irq_exti2 + .long __irq_exti3 + .long __irq_exti4 + .long __irq_dma1_stream0 + .long __irq_dma1_stream1 + .long __irq_dma1_stream2 + .long __irq_dma1_stream3 + .long __irq_dma1_stream4 + .long __irq_dma1_stream5 + .long __irq_dma1_stream6 + .long __irq_adc + .long __irq_can1_tx + .long __irq_can1_rx0 + .long __irq_can1_rx1 + .long __irq_can1_sce + .long __irq_exti9_5 + .long __irq_tim1_brk_tim9 + .long __irq_tim1_up_tim10 + .long __irq_tim1_trg_com_tim11 + .long __irq_tim1_cc + .long __irq_tim2 + .long __irq_tim3 + .long __irq_tim4 + .long __irq_i2c1_ev + .long __irq_i2c1_er + .long __irq_i2c2_ev + .long __irq_i2c2_er + .long __irq_spi1 + .long __irq_spi2 + .long __irq_usart1 + .long __irq_usart2 + .long __irq_usart3 + .long __irq_exti15_10 + .long __irq_rtc_alarm + .long __irq_otg_fs_wkup + .long __irq_tim8_brk_tim12 + .long __irq_tim8_up_tim13 + .long __irq_tim8_trg_com_tim14 + .long __irq_tim8_cc + .long __irq_dma1_stream7 + .long __irq_fsmc + .long __irq_sdio + .long __irq_tim5 + .long __irq_spi3 + .long __irq_uart4 + .long __irq_uart5 + .long __irq_tim6_dac + .long __irq_tim7 + .long __irq_dma2_stream0 + .long __irq_dma2_stream1 + .long __irq_dma2_stream2 + .long __irq_dma2_stream3 + .long __irq_dma2_stream4 + .long __irq_eth + .long __irq_eth_wkup + .long __irq_can2_tx + .long __irq_can2_rx0 + .long __irq_can2_rx1 + .long __irq_can2_sce + .long __irq_otg_fs + .long __irq_dma2_stream5 + .long __irq_dma2_stream6 + .long __irq_dma2_stream7 + .long __irq_usart6 + .long __irq_i2c3_ev + .long __irq_i2c3_er + .long __irq_otg_hs_ep1_out + .long __irq_otg_hs_ep1_in + .long __irq_otg_hs_wkup + .long __irq_otg_hs + .long __irq_dcmi + .long __irq_cryp + .long __irq_hash_rng + + .size __stm32_vector_table, . - __stm32_vector_table -- cgit v1.2.3 From f7c1bd5f584aed14361979d5a536365a5ad35f8f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 19 Nov 2011 16:22:28 -0500 Subject: STM32F2 NVIC support. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/nvic.h | 156 +++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 libmaple/stm32f2/include/series/nvic.h diff --git a/libmaple/stm32f2/include/series/nvic.h b/libmaple/stm32f2/include/series/nvic.h new file mode 100644 index 0000000..1daad60 --- /dev/null +++ b/libmaple/stm32f2/include/series/nvic.h @@ -0,0 +1,156 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/nvic.h + * @brief STM32F2 nested vectored interrupt controller (NVIC) header. + */ + +#ifndef _LIBMAPLE_STM32F2_NVIC_H_ +#define _LIBMAPLE_STM32F2_NVIC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Interrupt vector table interrupt numbers. + */ +typedef enum nvic_irq_num { + NVIC_NMI = -14, /**< Non-maskable interrupt */ + NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */ + NVIC_MEM_MANAGE = -12, /**< Memory management */ + NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory + access fault. */ + NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction + or illegal state. */ + NVIC_SVC = -5, /**< System service call via SWI + instruction */ + NVIC_DEBUG_MON = -4, /**< Debug monitor */ + NVIC_PEND_SVC = -2, /**< Pendable request for system + service */ + NVIC_SYSTICK = -1, /**< System tick timer */ + NVIC_WWDG = 0, /**< Window watchdog interrupt */ + NVIC_PVD = 1, /**< PVD through EXTI line detection */ + NVIC_TAMP_STAMP = 2, /**< Tamper and TimeStamp */ + NVIC_RTC_WKUP = 3, /**< Real-time clock wakeup */ + NVIC_FLASH = 4, /**< Flash */ + NVIC_RCC = 5, /**< Reset and clock control */ + NVIC_EXTI0 = 6, /**< EXTI line 0 */ + NVIC_EXTI1 = 7, /**< EXTI line 1 */ + NVIC_EXTI2 = 8, /**< EXTI line 2 */ + NVIC_EXTI3 = 9, /**< EXTI line 3 */ + NVIC_EXTI4 = 10, /**< EXTI line 4 */ + NVIC_DMA1_STREAM0 = 11, /**< DMA1 stream 0 */ + NVIC_DMA1_STREAM1 = 12, /**< DMA1 stream 1 */ + NVIC_DMA1_STREAM2 = 13, /**< DMA1 stream 2 */ + NVIC_DMA1_STREAM3 = 14, /**< DMA1 stream 3 */ + NVIC_DMA1_STREAM4 = 15, /**< DMA1 stream 4 */ + NVIC_DMA1_STREAM5 = 16, /**< DMA1 stream 5 */ + NVIC_DMA1_STREAM6 = 17, /**< DMA1 stream 6 */ + NVIC_ADC = 18, /**< ADC */ + NVIC_CAN1_TX = 19, /**< CAN1 TX */ + NVIC_CAN1_RX0 = 20, /**< CAN1 RX0 */ + NVIC_CAN1_RX1 = 21, /**< CAN1 RX1 */ + NVIC_CAN1_SCE = 22, /**< CAN1 SCE */ + NVIC_EXTI_9_5 = 23, /**< EXTI lines [9:5] */ + NVIC_TIMER1_BRK_TIMER9 = 24, /**< Timer 1 break and timer 9 */ + NVIC_TIMER1_UP_TIMER10 = 25, /**< Timer 1 update and timer 10 */ + NVIC_TIMER1_TRG_COM_TIMER11 = 26, /**< Timer 1 trigger and commutation and + timer 11.*/ + NVIC_TIMER1_CC = 27, /**< Timer 1 capture and compare */ + NVIC_TIMER2 = 28, /**< Timer 2 */ + NVIC_TIMER3 = 29, /**< Timer 3 */ + NVIC_TIMER4 = 30, /**< Timer 4 */ + NVIC_I2C1_EV = 31, /**< I2C1 event */ + NVIC_I2C1_ER = 32, /**< I2C2 error */ + NVIC_I2C2_EV = 33, /**< I2C2 event */ + NVIC_I2C2_ER = 34, /**< I2C2 error */ + NVIC_SPI1 = 35, /**< SPI1 */ + NVIC_SPI2 = 36, /**< SPI2 */ + NVIC_USART1 = 37, /**< USART1 */ + NVIC_USART2 = 38, /**< USART2 */ + NVIC_USART3 = 39, /**< USART3 */ + NVIC_EXTI_15_10 = 40, /**< EXTI lines [15:10] */ + NVIC_RTCALARM = 41, /**< RTC alarms A and B through EXTI */ + NVIC_OTG_FS_WKUP = 42, /**< USB on-the-go full-speed wakeup + through EXTI*/ + NVIC_TIMER8_BRK_TIMER12 = 43, /**< Timer 8 break and timer 12 */ + NVIC_TIMER8_UP_TIMER13 = 44, /**< Timer 8 update and timer 13 */ + NVIC_TIMER8_TRG_COM_TIMER14 = 45, /**< Timer 8 trigger and commutation and + timer 14 */ + NVIC_TIMER8_CC = 46, /**< Timer 8 capture and compare */ + NVIC_DMA1_STREAM7 = 47, /**< DMA1 stream 7 */ + NVIC_FSMC = 48, /**< FSMC */ + NVIC_SDIO = 49, /**< SDIO */ + NVIC_TIMER5 = 50, /**< Timer 5 */ + NVIC_SPI3 = 51, /**< SPI3 */ + NVIC_UART4 = 52, /**< UART4 */ + NVIC_UART5 = 53, /**< UART5 */ + NVIC_TIMER6_DAC = 54, /**< Timer 6 and DAC underrun */ + NVIC_TIMER7 = 55, /**< Timer 7 */ + NVIC_DMA2_STREAM0 = 56, /**< DMA2 stream 0 */ + NVIC_DMA2_STREAM1 = 57, /**< DMA2 stream 1 */ + NVIC_DMA2_STREAM2 = 58, /**< DMA2 stream 2 */ + NVIC_DMA2_STREAM3 = 59, /**< DMA2 stream 3 */ + NVIC_DMA2_STREAM4 = 60, /**< DMA2 stream 4 */ + NVIC_ETH = 61, /**< Ethernet */ + NVIC_ETH_WKUP = 62, /**< Ethernet wakeup through EXTI */ + NVIC_CAN2_TX = 63, /**< CAN2 TX */ + NVIC_CAN2_RX0 = 64, /**< CAN2 RX0 */ + NVIC_CAN2_RX1 = 65, /**< CAN2 RX1 */ + NVIC_CAN2_SCE = 66, /**< CAN2 SCE */ + NVIC_OTG_FS = 67, /**< USB on-the-go full-speed */ + NVIC_DMA2_STREAM5 = 68, /**< DMA2 stream 5 */ + NVIC_DMA2_STREAM6 = 69, /**< DMA2 stream 6 */ + NVIC_DMA2_STREAM7 = 70, /**< DMA2 stream 7 */ + NVIC_USART6 = 71, /**< USART6 */ + NVIC_I2C3_EV = 72, /**< I2C3 event */ + NVIC_I2C3_ER = 73, /**< I2C3 error */ + NVIC_OTG_HS_EP1_OUT = 74, /**< USB on-the-go high-speed + endpoint 1 OUT */ + NVIC_OTG_HS_EP1_IN = 75, /**< USB on-the-go high-speed + endpoint 1 IN */ + NVIC_OTG_HS_WKUP = 76, /**< USB on-the-go high-speed wakeup + through EXTI*/ + NVIC_OTG_HS = 77, /**< USB on-the-go high-speed */ + NVIC_DCMI = 78, /**< DCMI */ + NVIC_CRYP = 79, /**< Cryptographic processor */ + NVIC_HASH_RNG = 80, /**< Hash and random number + generation */ +} nvic_irq_num; + +static inline void nvic_irq_disable_all(void) { + NVIC_BASE->ICER[0] = 0xFFFFFFFF; + NVIC_BASE->ICER[1] = 0xFFFFFFFF; + NVIC_BASE->ICER[2] = 0xFFFFFFFF; +} + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.2.3 From 9cf4afdd74a280e5aaaa700ffdcbe587631c85ae Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 2 Feb 2012 02:27:14 -0500 Subject: libmaple_types.h: Add offsetof(). Rather than rely on newlib's stddef.h, define our own offsetof() in terms of GCC's __builtin_offsetof(). Don't override an existing offsetof() definition, in case the user already has one they prefer. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/libmaple_types.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h index ae01691..19a5101 100644 --- a/libmaple/include/libmaple/libmaple_types.h +++ b/libmaple/include/libmaple/libmaple_types.h @@ -27,7 +27,7 @@ /** * @file libmaple_types.h * - * @brief libmaple types + * @brief libmaple's types, and operations on types. */ #ifndef _LIBMAPLE_LIBMAPLE_TYPES_H_ @@ -57,6 +57,10 @@ typedef void (*voidFuncPtr)(void); #define NULL 0 #endif +#ifndef offsetof +#define offsetof(type, member) __builtin_offsetof(type, member) +#endif + #ifdef __cplusplus } #endif -- cgit v1.2.3 From 0b8706d8258c7e134e90f6ae3614e286b7fda581 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 18 Nov 2011 19:18:04 -0500 Subject: Initial STM32F2 RCC support. Largely untested. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 919 ++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rcc.c | 168 +++++++ libmaple/stm32f2/rules.mk | 2 +- 3 files changed, 1088 insertions(+), 1 deletion(-) create mode 100644 libmaple/stm32f2/include/series/rcc.h create mode 100644 libmaple/stm32f2/rcc.c diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h new file mode 100644 index 0000000..1557f2d --- /dev/null +++ b/libmaple/stm32f2/include/series/rcc.h @@ -0,0 +1,919 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/rcc.h + * @brief STM32F2 reset and clock control (RCC) header. + */ + +/* + * TODO: + * + * - Can prescaler enums be merged with F1's into + * (perhaps by adding more register bit definitions to F1 header)? + */ + +#ifndef _LIBMAPLE_STM32F2_RCC_H_ +#define _LIBMAPLE_STM32F2_RCC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register map + */ + +/** RCC register map type */ +typedef struct rcc_reg_map { + __io uint32 CR; /**< Clock control register */ + __io uint32 PLLCFGR; /**< PLL configuration register */ + __io uint32 CFGR; /**< Clock configuration register */ + __io uint32 CIR; /**< Clock interrupt register */ + __io uint32 AHB1RSTR; /**< AHB1 peripheral reset register */ + __io uint32 AHB2RSTR; /**< AHB2 peripheral reset register */ + __io uint32 AHB3RSTR; /**< AHB3 peripheral reset register */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 APB1RSTR; /**< APB1 peripheral reset register */ + __io uint32 APB2RSTR; /**< APB2 peripheral reset register */ + const uint32 RESERVED2; /**< Reserved */ + const uint32 RESERVED3; /**< Reserved */ + __io uint32 AHB1ENR; /**< AHB1 peripheral clock enable register */ + __io uint32 AHB2ENR; /**< AHB2 peripheral clock enable register */ + __io uint32 AHB3ENR; /**< AHB3 peripheral clock enable register */ + const uint32 RESERVED4; /**< Reserved */ + __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */ + __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */ + const uint32 RESERVED5; /**< Reserved */ + const uint32 RESERVED6; /**< Reserved */ + __io uint32 AHB1LPENR; /**< AHB1 peripheral clock enable in + low power mode register */ + __io uint32 AHB2LPENR; /**< AHB2 peripheral clock enable in + low power mode register */ + __io uint32 AHB3LPENR; /**< AHB3 peripheral clock enable in + low power mode register */ + const uint32 RESERVED7; /**< Reserved */ + __io uint32 APB1LPENR; /**< APB1 peripheral clock enable in + low power mode register */ + __io uint32 APB2LPENR; /**< APB2 peripheral clock enable in + low power mode register */ + const uint32 RESERVED8; /**< Reserved */ + const uint32 RESERVED9; /**< Reserved */ + __io uint32 BDCR; /**< Backup domain control register */ + __io uint32 CSR; /**< Clock control and status register */ + const uint32 RESERVED10; /**< Reserved */ + const uint32 RESERVED11; /**< Reserved */ + __io uint32 SSCGR; /**< Spread spectrum clock generation + register */ + __io uint32 PLLI2SCFGR; /**< PLLI2S configuration register */ +} rcc_reg_map; + +/* RCC register map base pointer */ +#define RCC_BASE ((struct rcc_reg_map*)0x40023800) + +/* + * Register bit definitions + */ + +/* Clock control register */ + +#define RCC_CR_PLLI2SRDY_BIT 27 +#define RCC_CR_PLLI2SON_BIT 26 +#define RCC_CR_PLLRDY_BIT 25 +#define RCC_CR_PLLON_BIT 24 +#define RCC_CR_CSSON_BIT 19 +#define RCC_CR_HSEBYP_BIT 18 +#define RCC_CR_HSERDY_BIT 17 +#define RCC_CR_HSEON_BIT 16 +#define RCC_CR_HSIRDY_BIT 1 +#define RCC_CR_HSION_BIT 0 + +#define RCC_CR_PLLI2SRDY BIT(RCC_CR_PLLI2SRDY_BIT) +#define RCC_CR_PLLI2SON BIT(RCC_CR_PLLI2SON_BIT) +#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) +#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) +#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) +#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) +#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) +#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) +#define RCC_CR_HSICAL (0xFF << 8) +#define RCC_CR_HSITRIM (0x1F << 3) +#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) +#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) + +/* PLL configuration register */ + +#define RCC_PLLCFGR_PLLSRC_BIT 22 + +#define RCC_PLLCFGR_PLLQ (0xF << 24) +#define RCC_PLLCFGR_PLLSRC BIT(RCC_PLLCFGR_PLLSRC_BIT) +#define RCC_PLLCFGR_PLLSRC_HSI (0x0 << RCC_PLLCFGR_PLLSRC_BIT) +#define RCC_PLLCFGR_PLLSRC_HSE (0x1 << RCC_PLLCFGR_PLLSRC_BIT) +#define RCC_PLLCFGR_PLLP (0x3 << 16) +#define RCC_PLLCFGR_PLLN (0x1FF << 6) +#define RCC_PLLCFGR_PLLM 0x1F + +/* Clock configuration register */ + +#define RCC_CFGR_I2SSRC_BIT 23 + +#define RCC_CFGR_MCO2 (0x3 << 30) +#define RCC_CFGR_MCO2_SYSCLK (0x0 << 30) +#define RCC_CFGR_MCO2_PLLI2S (0x1 << 30) +#define RCC_CFGR_MCO2_HSE (0x2 << 30) +#define RCC_CFGR_MCO2_PLL (0x3 << 30) + +#define RCC_CFGR_MCO2PRE (0x7 << 27) +#define RCC_CFGR_MCO2PRE_DIV_1 (0x0 << 27) +#define RCC_CFGR_MCO2PRE_DIV_2 (0x4 << 27) +#define RCC_CFGR_MCO2PRE_DIV_3 (0x5 << 27) +#define RCC_CFGR_MCO2PRE_DIV_4 (0x6 << 27) +#define RCC_CFGR_MCO2PRE_DIV_5 (0x7 << 27) + +#define RCC_CFGR_MCO1PRE (0x7 << 24) +#define RCC_CFGR_MCO1PRE_DIV_1 (0x0 << 24) +#define RCC_CFGR_MCO1PRE_DIV_2 (0x4 << 24) +#define RCC_CFGR_MCO1PRE_DIV_3 (0x5 << 24) +#define RCC_CFGR_MCO1PRE_DIV_4 (0x6 << 24) +#define RCC_CFGR_MCO1PRE_DIV_5 (0x7 << 24) + +#define RCC_CFGR_I2SSRC BIT(RCC_CFGR_I2SSRC_BIT) +#define RCC_CFGR_I2SSRC_PLLI2S (0 << RCC_CFGR_I2SSRC_BIT) +#define RCC_CFGR_I2SSRC_I2S_CKIN (1 << RCC_CFGR_I2SSRC_BIT) + +#define RCC_CFGR_MCO1 (0x3 << 21) +#define RCC_CFGR_MCO1_HSI (0x0 << 21) +#define RCC_CFGR_MCO1_LSE (0x1 << 21) +#define RCC_CFGR_MCO1_HSE (0x2 << 21) +#define RCC_CFGR_MCO1_PLL (0x3 << 21) + +#define RCC_CFGR_RTCPRE (0x1F << 16) + +/* Skipped: all the 0b0xx values meaning "not divided" */ +#define RCC_CFGR_PPRE2 (0x7 << 13) +#define RCC_CFGR_PPRE2_AHB_DIV_2 (0x4 << 13) +#define RCC_CFGR_PPRE2_AHB_DIV_4 (0x5 << 13) +#define RCC_CFGR_PPRE2_AHB_DIV_8 (0x6 << 13) +#define RCC_CFGR_PPRE2_AHB_DIV_16 (0x7 << 13) + +/* Skipped: all the 0b0xx values meaning "not divided" */ +#define RCC_CFGR_PPRE1 (0x7 << 10) +#define RCC_CFGR_PPRE1_AHB_DIV_2 (0x4 << 10) +#define RCC_CFGR_PPRE1_AHB_DIV_4 (0x5 << 10) +#define RCC_CFGR_PPRE1_AHB_DIV_8 (0x6 << 10) +#define RCC_CFGR_PPRE1_AHB_DIV_16 (0x7 << 10) + +/* Skipped: all the 0b0xxx values meaning "not divided" */ +#define RCC_CFGR_HPRE (0xF << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_2 (0x8 << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_4 (0x9 << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_8 (0xA << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_16 (0xB << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_64 (0xC << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_128 (0xD << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_256 (0xE << 4) +#define RCC_CFGR_HPRE_SYSCLK_DIV_512 (0xF << 4) + +#define RCC_CFGR_SWS (0x3 << 2) +#define RCC_CFGR_SWS_HSI (0x0 << 2) +#define RCC_CFGR_SWS_HSE (0x1 << 2) +#define RCC_CFGR_SWS_PLL (0x2 << 2) + +#define RCC_CFGR_SW 0x3 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* Clock interrupt register */ + +#define RCC_CIR_CSSC_BIT 23 + +#define RCC_CIR_PLLI2SRDYC_BIT 21 +#define RCC_CIR_PLLRDYC_BIT 20 +#define RCC_CIR_HSERDYC_BIT 19 +#define RCC_CIR_HSIRDYC_BIT 18 +#define RCC_CIR_LSERDYC_BIT 17 +#define RCC_CIR_LSIRDYC_BIT 16 + +#define RCC_CIR_PLLI2SRDYIE_BIT 13 +#define RCC_CIR_PLLRDYIE_BIT 12 +#define RCC_CIR_HSERDYIE_BIT 11 +#define RCC_CIR_HSIRDYIE_BIT 10 +#define RCC_CIR_LSERDYIE_BIT 9 +#define RCC_CIR_LSIRDYIE_BIT 8 + +#define RCC_CIR_CSSF_BIT 7 + +#define RCC_CIR_PLLI2SRDYF_BIT 5 +#define RCC_CIR_PLLRDYF_BIT 4 +#define RCC_CIR_HSERDYF_BIT 3 +#define RCC_CIR_HSIRDYF_BIT 2 +#define RCC_CIR_LSERDYF_BIT 1 +#define RCC_CIR_LSIRDYF_BIT 0 + +#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) + +#define RCC_CIR_PLLI2SRDYC BIT(RCC_CIR_PLLI2SRDYC_BIT) +#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) +#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) +#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) +#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) +#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) + +#define RCC_CIR_PLLI2SRDYIE BIT(RCC_CIR_PLLI2SRDYIE_BIT) +#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) +#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) +#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) +#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) +#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) + +#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) + +#define RCC_CIR_PLLI2SRDYF BIT(RCC_CIR_PLLI2SRDYF_BIT) +#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) +#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) +#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) +#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) +#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_OTGHSRST_BIT 29 +#define RCC_AHB1RSTR_ETHMACRST_BIT 25 +#define RCC_AHB1RSTR_DMA2RST_BIT 22 +#define RCC_AHB1RSTR_DMA1RST_BIT 21 +#define RCC_AHB1RSTR_CRCRST_BIT 12 +#define RCC_AHB1RSTR_GPIOIRST_BIT 8 +#define RCC_AHB1RSTR_GPIOHRST_BIT 7 +#define RCC_AHB1RSTR_GPIOGRST_BIT 6 +#define RCC_AHB1RSTR_GPIOFRST_BIT 5 +#define RCC_AHB1RSTR_GPIOERST_BIT 4 +#define RCC_AHB1RSTR_GPIODRST_BIT 3 +#define RCC_AHB1RSTR_GPIOCRST_BIT 2 +#define RCC_AHB1RSTR_GPIOBRST_BIT 1 +#define RCC_AHB1RSTR_GPIOARST_BIT 0 + +#define RCC_AHB1RSTR_OTGHSRST BIT(RCC_AHB1RSTR_OTGHSRST_BIT) +#define RCC_AHB1RSTR_ETHMACRST BIT(RCC_AHB1RSTR_ETHMACRST_BIT) +#define RCC_AHB1RSTR_DMA2RST BIT(RCC_AHB1RSTR_DMA2RST_BIT) +#define RCC_AHB1RSTR_DMA1RST BIT(RCC_AHB1RSTR_DMA1RST_BIT) +#define RCC_AHB1RSTR_CRCRST BIT(RCC_AHB1RSTR_CRCRST_BIT) +#define RCC_AHB1RSTR_GPIOIRST BIT(RCC_AHB1RSTR_GPIOIRST_BIT) +#define RCC_AHB1RSTR_GPIOHRST BIT(RCC_AHB1RSTR_GPIOHRST_BIT) +#define RCC_AHB1RSTR_GPIOGRST BIT(RCC_AHB1RSTR_GPIOGRST_BIT) +#define RCC_AHB1RSTR_GPIOFRST BIT(RCC_AHB1RSTR_GPIOFRST_BIT) +#define RCC_AHB1RSTR_GPIOERST BIT(RCC_AHB1RSTR_GPIOERST_BIT) +#define RCC_AHB1RSTR_GPIODRST BIT(RCC_AHB1RSTR_GPIODRST_BIT) +#define RCC_AHB1RSTR_GPIOCRST BIT(RCC_AHB1RSTR_GPIOCRST_BIT) +#define RCC_AHB1RSTR_GPIOBRST BIT(RCC_AHB1RSTR_GPIOBRST_BIT) +#define RCC_AHB1RSTR_GPIOARST BIT(RCC_AHB1RSTR_GPIOARST_BIT) + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_OTGFSRST_BIT 7 +#define RCC_AHB2RSTR_RNGRST_BIT 6 +#define RCC_AHB2RSTR_HASHRST_BIT 5 +#define RCC_AHB2RSTR_CRYPRST_BIT 4 +#define RCC_AHB2RSTR_DCMIRST_BIT 0 + +#define RCC_AHB2RSTR_OTGFSRST BIT(RCC_AHB2RSTR_OTGFSRST_BIT) +#define RCC_AHB2RSTR_RNGRST BIT(RCC_AHB2RSTR_RNGRST_BIT) +#define RCC_AHB2RSTR_HASHRST BIT(RCC_AHB2RSTR_HASHRST_BIT) +#define RCC_AHB2RSTR_CRYPRST BIT(RCC_AHB2RSTR_CRYPRST_BIT) +#define RCC_AHB2RSTR_DCMIRST BIT(RCC_AHB2RSTR_DCMIRST_BIT) + +/* AHB3 peripheral reset register */ + +#define RCC_AHB3RSTR_FSMCRST_BIT 0 + +#define RCC_AHB3RSTR_FSMCRST BIT(RCC_AHB3RSTR_FSMCRST_BIT) + +/* APB1 peripheral reset register */ + +#define RCC_APB1RSTR_DACRST_BIT 29 +#define RCC_APB1RSTR_PWRRST_BIT 28 +#define RCC_APB1RSTR_CAN2RST_BIT 26 +#define RCC_APB1RSTR_CAN1RST_BIT 25 +#define RCC_APB1RSTR_I2C3RST_BIT 23 +#define RCC_APB1RSTR_I2C2RST_BIT 22 +#define RCC_APB1RSTR_I2C1RST_BIT 21 +#define RCC_APB1RSTR_UART5RST_BIT 20 +#define RCC_APB1RSTR_UART4RST_BIT 19 +#define RCC_APB1RSTR_UART3RST_BIT 18 +#define RCC_APB1RSTR_UART2RST_BIT 17 +#define RCC_APB1RSTR_SPI3RST_BIT 15 +#define RCC_APB1RSTR_SPI2RST_BIT 14 +#define RCC_APB1RSTR_WWDGRST_BIT 11 +#define RCC_APB1RSTR_TIM14RST_BIT 8 +#define RCC_APB1RSTR_TIM13RST_BIT 7 +#define RCC_APB1RSTR_TIM12RST_BIT 6 +#define RCC_APB1RSTR_TIM7RST_BIT 5 +#define RCC_APB1RSTR_TIM6RST_BIT 4 +#define RCC_APB1RSTR_TIM5RST_BIT 3 +#define RCC_APB1RSTR_TIM4RST_BIT 2 +#define RCC_APB1RSTR_TIM3RST_BIT 1 +#define RCC_APB1RSTR_TIM2RST_BIT 0 + +#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) +#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) +#define RCC_APB1RSTR_CAN2RST BIT(RCC_APB1RSTR_CAN2RST_BIT) +#define RCC_APB1RSTR_CAN1RST BIT(RCC_APB1RSTR_CAN1RST_BIT) +#define RCC_APB1RSTR_I2C3RST BIT(RCC_APB1RSTR_I2C3RST_BIT) +#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) +#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) +#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) +#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) +#define RCC_APB1RSTR_UART3RST BIT(RCC_APB1RSTR_UART3RST_BIT) +#define RCC_APB1RSTR_UART2RST BIT(RCC_APB1RSTR_UART2RST_BIT) +#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) +#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) +#define RCC_APB1RSTR_WWDGRST BIT(RCC_APB1RSTR_WWDGRST_BIT) +#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) +#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) +#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) +#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) +#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) +#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) +#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) +#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) +#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM11RST_BIT 18 +#define RCC_APB2RSTR_TIM10RST_BIT 17 +#define RCC_APB2RSTR_TIM9RST_BIT 16 +#define RCC_APB2RSTR_SYSCFGRST_BIT 14 +#define RCC_APB2RSTR_SPI1RST_BIT 12 +#define RCC_APB2RSTR_SDIORST_BIT 11 +#define RCC_APB2RSTR_ADCRST_BIT 8 +#define RCC_APB2RSTR_USART6RST_BIT 5 +#define RCC_APB2RSTR_USART1RST_BIT 4 +#define RCC_APB2RSTR_TIM8RST_BIT 1 +#define RCC_APB2RSTR_TIM1RST_BIT 0 + +#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) +#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) +#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) +#define RCC_APB2RSTR_SYSCFGRST BIT(RCC_APB2RSTR_SYSCFGRST_BIT) +#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) +#define RCC_APB2RSTR_SDIORST BIT(RCC_APB2RSTR_SDIORST_BIT) +#define RCC_APB2RSTR_ADCRST BIT(RCC_APB2RSTR_ADCRST_BIT) +#define RCC_APB2RSTR_USART6RST BIT(RCC_APB2RSTR_USART6RST_BIT) +#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) +#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) +#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) + +/* AHB1 peripheral clock enable register */ + +#define RCC_AHB1ENR_OTGHSULPIEN_BIT 30 +#define RCC_AHB1ENR_OTGHSEN_BIT 29 +#define RCC_AHB1ENR_ETHMACPTPEN_BIT 28 +#define RCC_AHB1ENR_ETHMACRXEN_BIT 27 +#define RCC_AHB1ENR_ETHMACTXEN_BIT 26 +#define RCC_AHB1ENR_ETHMACEN_BIT 25 +#define RCC_AHB1ENR_DMA2EN_BIT 22 +#define RCC_AHB1ENR_DMA1EN_BIT 21 +#define RCC_AHB1ENR_BKPSRAMEN_BIT 18 +#define RCC_AHB1ENR_CRCEN_BIT 12 +#define RCC_AHB1ENR_GPIOIEN_BIT 8 +#define RCC_AHB1ENR_GPIOHEN_BIT 7 +#define RCC_AHB1ENR_GPIOGEN_BIT 6 +#define RCC_AHB1ENR_GPIOFEN_BIT 5 +#define RCC_AHB1ENR_GPIOEEN_BIT 4 +#define RCC_AHB1ENR_GPIODEN_BIT 3 +#define RCC_AHB1ENR_GPIOCEN_BIT 2 +#define RCC_AHB1ENR_GPIOBEN_BIT 1 +#define RCC_AHB1ENR_GPIOAEN_BIT 0 + +#define RCC_AHB1ENR_OTGHSULPIEN BIT(RCC_AHB1ENR_OTGHSULPIEN_BIT) +#define RCC_AHB1ENR_OTGHSEN BIT(RCC_AHB1ENR_OTGHSEN_BIT) +#define RCC_AHB1ENR_ETHMACPTPEN BIT(RCC_AHB1ENR_ETHMACPTPEN_BIT) +#define RCC_AHB1ENR_ETHMACRXEN BIT(RCC_AHB1ENR_ETHMACRXEN_BIT) +#define RCC_AHB1ENR_ETHMACTXEN BIT(RCC_AHB1ENR_ETHMACTXEN_BIT) +#define RCC_AHB1ENR_ETHMACEN BIT(RCC_AHB1ENR_ETHMACEN_BIT) +#define RCC_AHB1ENR_DMA2EN BIT(RCC_AHB1ENR_DMA2EN_BIT) +#define RCC_AHB1ENR_DMA1EN BIT(RCC_AHB1ENR_DMA1EN_BIT) +#define RCC_AHB1ENR_BKPSRAMEN BIT(RCC_AHB1ENR_BKPSRAMEN_BIT) +#define RCC_AHB1ENR_CRCEN BIT(RCC_AHB1ENR_CRCEN_BIT) +#define RCC_AHB1ENR_GPIOIEN BIT(RCC_AHB1ENR_GPIOIEN_BIT) +#define RCC_AHB1ENR_GPIOHEN BIT(RCC_AHB1ENR_GPIOHEN_BIT) +#define RCC_AHB1ENR_GPIOGEN BIT(RCC_AHB1ENR_GPIOGEN_BIT) +#define RCC_AHB1ENR_GPIOFEN BIT(RCC_AHB1ENR_GPIOFEN_BIT) +#define RCC_AHB1ENR_GPIOEEN BIT(RCC_AHB1ENR_GPIOEEN_BIT) +#define RCC_AHB1ENR_GPIODEN BIT(RCC_AHB1ENR_GPIODEN_BIT) +#define RCC_AHB1ENR_GPIOCEN BIT(RCC_AHB1ENR_GPIOCEN_BIT) +#define RCC_AHB1ENR_GPIOBEN BIT(RCC_AHB1ENR_GPIOBEN_BIT) +#define RCC_AHB1ENR_GPIOAEN BIT(RCC_AHB1ENR_GPIOAEN_BIT) + +/* AHB2 peripheral clock enable register */ + +#define RCC_AHB2ENR_OTGFSEN_BIT 7 +#define RCC_AHB2ENR_RNGEN_BIT 6 +#define RCC_AHB2ENR_HASHEN_BIT 5 +#define RCC_AHB2ENR_CRYPEN_BIT 4 +#define RCC_AHB2ENR_DCMIEN_BIT 0 + +#define RCC_AHB2ENR_OTGFSEN BIT(RCC_AHB2ENR_OTGFSEN_BIT) +#define RCC_AHB2ENR_RNGEN BIT(RCC_AHB2ENR_RNGEN_BIT) +#define RCC_AHB2ENR_HASHEN BIT(RCC_AHB2ENR_HASHEN_BIT) +#define RCC_AHB2ENR_CRYPEN BIT(RCC_AHB2ENR_CRYPEN_BIT) +#define RCC_AHB2ENR_DCMIEN BIT(RCC_AHB2ENR_DCMIEN_BIT) + +/* AHB3 peripheral clock enable register */ + +#define RCC_AHB3ENR_FSMCEN_BIT 0 + +#define RCC_AHB3ENR_FSMCEN BIT(RCC_AHB3ENR_FSMCEN_BIT) + +/* APB1 peripheral clock enable register */ + +#define RCC_APB1ENR_DACEN_BIT 29 +#define RCC_APB1ENR_PWREN_BIT 28 +#define RCC_APB1ENR_CAN2EN_BIT 26 +#define RCC_APB1ENR_CAN1EN_BIT 25 +#define RCC_APB1ENR_I2C3EN_BIT 23 +#define RCC_APB1ENR_I2C2EN_BIT 22 +#define RCC_APB1ENR_I2C1EN_BIT 21 +#define RCC_APB1ENR_UART5EN_BIT 20 +#define RCC_APB1ENR_UART4EN_BIT 19 +#define RCC_APB1ENR_USART3EN_BIT 18 +#define RCC_APB1ENR_USART2EN_BIT 17 +#define RCC_APB1ENR_SPI3EN_BIT 15 +#define RCC_APB1ENR_SPI2EN_BIT 14 +#define RCC_APB1ENR_WWDGEN_BIT 11 +#define RCC_APB1ENR_TIM14EN_BIT 8 +#define RCC_APB1ENR_TIM13EN_BIT 7 +#define RCC_APB1ENR_TIM12EN_BIT 6 +#define RCC_APB1ENR_TIM7EN_BIT 5 +#define RCC_APB1ENR_TIM6EN_BIT 4 +#define RCC_APB1ENR_TIM5EN_BIT 3 +#define RCC_APB1ENR_TIM4EN_BIT 2 +#define RCC_APB1ENR_TIM3EN_BIT 1 +#define RCC_APB1ENR_TIM2EN_BIT 0 + +#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) +#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) +#define RCC_APB1ENR_CAN2EN BIT(RCC_APB1ENR_CAN2EN_BIT) +#define RCC_APB1ENR_CAN1EN BIT(RCC_APB1ENR_CAN1EN_BIT) +#define RCC_APB1ENR_I2C3EN BIT(RCC_APB1ENR_I2C3EN_BIT) +#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) +#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) +#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) +#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) +#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) +#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) +#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) +#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) +#define RCC_APB1ENR_WWDGEN BIT(RCC_APB1ENR_WWDGEN_BIT) +#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) +#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) +#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) +#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) +#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) +#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) +#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) +#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) +#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) + +/* APB2 peripheral clock enable register */ + +#define RCC_APB2ENR_TIM11EN_BIT 18 +#define RCC_APB2ENR_TIM10EN_BIT 17 +#define RCC_APB2ENR_TIM9EN_BIT 16 +#define RCC_APB2ENR_SYSCFGEN_BIT 14 +#define RCC_APB2ENR_SPI1EN_BIT 12 +#define RCC_APB2ENR_SDIOEN_BIT 11 +#define RCC_APB2ENR_ADC3EN_BIT 10 +#define RCC_APB2ENR_ADC2EN_BIT 9 +#define RCC_APB2ENR_ADC1EN_BIT 8 +#define RCC_APB2ENR_USART6EN_BIT 5 +#define RCC_APB2ENR_USART1EN_BIT 4 +#define RCC_APB2ENR_TIM8EN_BIT 1 +#define RCC_APB2ENR_TIM1EN_BIT 0 + +#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) +#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) +#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) +#define RCC_APB2ENR_SYSCFGEN BIT(RCC_APB2ENR_SYSCFGEN_BIT) +#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) +#define RCC_APB2ENR_SDIOEN BIT(RCC_APB2ENR_SDIOEN_BIT) +#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) +#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) +#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) +#define RCC_APB2ENR_USART6EN BIT(RCC_APB2ENR_USART6EN_BIT) +#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) +#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) +#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) + +/* AHB1 peripheral clock enable in low power mode register */ + +#define RCC_AHB1LPENR_OTGHSULPILPEN_BIT 30 +#define RCC_AHB1LPENR_OTGHSLPEN_BIT 29 +#define RCC_AHB1LPENR_ETHMACPTPLPEN_BIT 28 +#define RCC_AHB1LPENR_ETHMACRXLPEN_BIT 27 +#define RCC_AHB1LPENR_ETHMACTXLPEN_BIT 26 +#define RCC_AHB1LPENR_ETHMACLPEN_BIT 25 +#define RCC_AHB1LPENR_DMA2LPEN_BIT 22 +#define RCC_AHB1LPENR_DMA1LPEN_BIT 21 +#define RCC_AHB1LPENR_BKPSRAMLPEN_BIT 18 +#define RCC_AHB1LPENR_SRAM2LPEN_BIT 17 +#define RCC_AHB1LPENR_SRAM1LPEN_BIT 16 +#define RCC_AHB1LPENR_FLITFLPEN_BIT 15 +#define RCC_AHB1LPENR_CRCLPEN_BIT 12 +#define RCC_AHB1LPENR_GPIOILPEN_BIT 8 +#define RCC_AHB1LPENR_GPIOGLPEN_BIT 6 +#define RCC_AHB1LPENR_GPIOFLPEN_BIT 5 +#define RCC_AHB1LPENR_GPIOELPEN_BIT 4 +#define RCC_AHB1LPENR_GPIODLPEN_BIT 3 +#define RCC_AHB1LPENR_GPIOCLPEN_BIT 2 +#define RCC_AHB1LPENR_GPIOBLPEN_BIT 1 +#define RCC_AHB1LPENR_GPIOALPEN_BIT 0 + +#define RCC_AHB1LPENR_OTGHSULPILPEN BIT(RCC_AHB1LPENR_OTGHSULPILPEN_BIT) +#define RCC_AHB1LPENR_OTGHSLPEN BIT(RCC_AHB1LPENR_OTGHSLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACPTPLPEN BIT(RCC_AHB1LPENR_ETHMACPTPLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACRXLPEN BIT(RCC_AHB1LPENR_ETHMACRXLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACTXLPEN BIT(RCC_AHB1LPENR_ETHMACTXLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACLPEN BIT(RCC_AHB1LPENR_ETHMACLPEN_BIT) +#define RCC_AHB1LPENR_DMA2LPEN BIT(RCC_AHB1LPENR_DMA2LPEN_BIT) +#define RCC_AHB1LPENR_DMA1LPEN BIT(RCC_AHB1LPENR_DMA1LPEN_BIT) +#define RCC_AHB1LPENR_BKPSRAMLPEN BIT(RCC_AHB1LPENR_BKPSRAMLPEN_BIT) +#define RCC_AHB1LPENR_SRAM2LPEN BIT(RCC_AHB1LPENR_SRAM2LPEN_BIT) +#define RCC_AHB1LPENR_SRAM1LPEN BIT(RCC_AHB1LPENR_SRAM1LPEN_BIT) +#define RCC_AHB1LPENR_FLITFLPEN BIT(RCC_AHB1LPENR_FLITFLPEN_BIT) +#define RCC_AHB1LPENR_CRCLPEN BIT(RCC_AHB1LPENR_CRCLPEN_BIT) +#define RCC_AHB1LPENR_GPIOILPEN BIT(RCC_AHB1LPENR_GPIOILPEN_BIT) +#define RCC_AHB1LPENR_GPIOGLPEN BIT(RCC_AHB1LPENR_GPIOGLPEN_BIT) +#define RCC_AHB1LPENR_GPIOFLPEN BIT(RCC_AHB1LPENR_GPIOFLPEN_BIT) +#define RCC_AHB1LPENR_GPIOELPEN BIT(RCC_AHB1LPENR_GPIOELPEN_BIT) +#define RCC_AHB1LPENR_GPIODLPEN BIT(RCC_AHB1LPENR_GPIODLPEN_BIT) +#define RCC_AHB1LPENR_GPIOCLPEN BIT(RCC_AHB1LPENR_GPIOCLPEN_BIT) +#define RCC_AHB1LPENR_GPIOBLPEN BIT(RCC_AHB1LPENR_GPIOBLPEN_BIT) +#define RCC_AHB1LPENR_GPIOALPEN BIT(RCC_AHB1LPENR_GPIOALPEN_BIT) + +/* AHB2 peripheral clock enable in low power mode register */ + +#define RCC_AHB2LPENR_OTGFSLPEN_BIT 7 +#define RCC_AHB2LPENR_RNGLPEN_BIT 6 +#define RCC_AHB2LPENR_HASHLPEN_BIT 5 +#define RCC_AHB2LPENR_CRYPLPEN_BIT 4 +#define RCC_AHB2LPENR_DCMILPEN_BIT 0 + +#define RCC_AHB2LPENR_OTGFSLPEN BIT(RCC_AHB2LPENR_OTGFSLPEN_BIT) +#define RCC_AHB2LPENR_RNGLPEN BIT(RCC_AHB2LPENR_RNGLPEN_BIT) +#define RCC_AHB2LPENR_HASHLPEN BIT(RCC_AHB2LPENR_HASHLPEN_BIT) +#define RCC_AHB2LPENR_CRYPLPEN BIT(RCC_AHB2LPENR_CRYPLPEN_BIT) +#define RCC_AHB2LPENR_DCMILPEN BIT(RCC_AHB2LPENR_DCMILPEN_BIT) + +/* AHB3 peripheral clock enable in low power mode register */ + +#define RCC_AHB3LPENR_FSMCLPEN_BIT 0 + +#define RCC_AHB3LPENR_FSMCLPEN BIT(RCC_AHB3LPENR_FSMCLPEN_BIT) + +/* APB1 peripheral clock enable in low power mode register */ + +#define RCC_APB1LPENR_DACLPEN_BIT 29 +#define RCC_APB1LPENR_PWRLPEN_BIT 28 +#define RCC_APB1LPENR_CAN2LPEN_BIT 26 +#define RCC_APB1LPENR_CAN1LPEN_BIT 25 +#define RCC_APB1LPENR_I2C3LPEN_BIT 23 +#define RCC_APB1LPENR_I2C2LPEN_BIT 22 +#define RCC_APB1LPENR_I2C1LPEN_BIT 21 +#define RCC_APB1LPENR_UART5LPEN_BIT 20 +#define RCC_APB1LPENR_UART4LPEN_BIT 19 +#define RCC_APB1LPENR_USART3LPEN_BIT 18 +#define RCC_APB1LPENR_USART2LPEN_BIT 17 +#define RCC_APB1LPENR_SPI3LPEN_BIT 15 +#define RCC_APB1LPENR_SPI2LPEN_BIT 14 +#define RCC_APB1LPENR_WWDGLPEN_BIT 11 +#define RCC_APB1LPENR_TIM14LPEN_BIT 8 +#define RCC_APB1LPENR_TIM13LPEN_BIT 7 +#define RCC_APB1LPENR_TIM12LPEN_BIT 6 +#define RCC_APB1LPENR_TIM7LPEN_BIT 5 +#define RCC_APB1LPENR_TIM6LPEN_BIT 4 +#define RCC_APB1LPENR_TIM5LPEN_BIT 3 +#define RCC_APB1LPENR_TIM4LPEN_BIT 2 +#define RCC_APB1LPENR_TIM3LPEN_BIT 1 +#define RCC_APB1LPENR_TIM2LPEN_BIT 0 + +#define RCC_APB1LPENR_DACLPEN BIT(RCC_APB1LPENR_DACLPEN_BIT) +#define RCC_APB1LPENR_PWRLPEN BIT(RCC_APB1LPENR_PWRLPEN_BIT) +#define RCC_APB1LPENR_CAN2LPEN BIT(RCC_APB1LPENR_CAN2LPEN_BIT) +#define RCC_APB1LPENR_CAN1LPEN BIT(RCC_APB1LPENR_CAN1LPEN_BIT) +#define RCC_APB1LPENR_I2C3LPEN BIT(RCC_APB1LPENR_I2C3LPEN_BIT) +#define RCC_APB1LPENR_I2C2LPEN BIT(RCC_APB1LPENR_I2C2LPEN_BIT) +#define RCC_APB1LPENR_I2C1LPEN BIT(RCC_APB1LPENR_I2C1LPEN_BIT) +#define RCC_APB1LPENR_UART5LPEN BIT(RCC_APB1LPENR_UART5LPEN_BIT) +#define RCC_APB1LPENR_UART4LPEN BIT(RCC_APB1LPENR_UART4LPEN_BIT) +#define RCC_APB1LPENR_USART3LPEN BIT(RCC_APB1LPENR_USART3LPEN_BIT) +#define RCC_APB1LPENR_USART2LPEN BIT(RCC_APB1LPENR_USART2LPEN_BIT) +#define RCC_APB1LPENR_SPI3LPEN BIT(RCC_APB1LPENR_SPI3LPEN_BIT) +#define RCC_APB1LPENR_SPI2LPEN BIT(RCC_APB1LPENR_SPI2LPEN_BIT) +#define RCC_APB1LPENR_WWDGLPEN BIT(RCC_APB1LPENR_WWDGLPEN_BIT) +#define RCC_APB1LPENR_TIM14LPEN BIT(RCC_APB1LPENR_TIM14LPEN_BIT) +#define RCC_APB1LPENR_TIM13LPEN BIT(RCC_APB1LPENR_TIM13LPEN_BIT) +#define RCC_APB1LPENR_TIM12LPEN BIT(RCC_APB1LPENR_TIM12LPEN_BIT) +#define RCC_APB1LPENR_TIM7LPEN BIT(RCC_APB1LPENR_TIM7LPEN_BIT) +#define RCC_APB1LPENR_TIM6LPEN BIT(RCC_APB1LPENR_TIM6LPEN_BIT) +#define RCC_APB1LPENR_TIM5LPEN BIT(RCC_APB1LPENR_TIM5LPEN_BIT) +#define RCC_APB1LPENR_TIM4LPEN BIT(RCC_APB1LPENR_TIM4LPEN_BIT) +#define RCC_APB1LPENR_TIM3LPEN BIT(RCC_APB1LPENR_TIM3LPEN_BIT) +#define RCC_APB1LPENR_TIM2LPEN BIT(RCC_APB1LPENR_TIM2LPEN_BIT) + +/* APB2 peripheral clock enable in low power mode register */ + +#define RCC_APB2LPENR_TIM11LPEN_BIT 18 +#define RCC_APB2LPENR_TIM10LPEN_BIT 17 +#define RCC_APB2LPENR_TIM9LPEN_BIT 16 +#define RCC_APB2LPENR_SYSCFGLPEN_BIT 14 +#define RCC_APB2LPENR_SPI1LPEN_BIT 12 +#define RCC_APB2LPENR_SDIOLPEN_BIT 11 +#define RCC_APB2LPENR_ADC3LPEN_BIT 10 +#define RCC_APB2LPENR_ADC2LPEN_BIT 9 +#define RCC_APB2LPENR_ADC1LPEN_BIT 8 +#define RCC_APB2LPENR_USART6LPEN_BIT 5 +#define RCC_APB2LPENR_USART1LPEN_BIT 4 +#define RCC_APB2LPENR_TIM8LPEN_BIT 1 +#define RCC_APB2LPENR_TIM1LPEN_BIT 0 + +#define RCC_APB2LPENR_TIM11LPEN BIT(RCC_APB2LPENR_TIM11LPEN_BIT) +#define RCC_APB2LPENR_TIM10LPEN BIT(RCC_APB2LPENR_TIM10LPEN_BIT) +#define RCC_APB2LPENR_TIM9LPEN BIT(RCC_APB2LPENR_TIM9LPEN_BIT) +#define RCC_APB2LPENR_SYSCFGLPEN BIT(RCC_APB2LPENR_SYSCFGLPEN_BIT) +#define RCC_APB2LPENR_SPI1LPEN BIT(RCC_APB2LPENR_SPI1LPEN_BIT) +#define RCC_APB2LPENR_SDIOLPEN BIT(RCC_APB2LPENR_SDIOLPEN_BIT) +#define RCC_APB2LPENR_ADC3LPEN BIT(RCC_APB2LPENR_ADC3LPEN_BIT) +#define RCC_APB2LPENR_ADC2LPEN BIT(RCC_APB2LPENR_ADC2LPEN_BIT) +#define RCC_APB2LPENR_ADC1LPEN BIT(RCC_APB2LPENR_ADC1LPEN_BIT) +#define RCC_APB2LPENR_USART6LPEN BIT(RCC_APB2LPENR_USART6LPEN_BIT) +#define RCC_APB2LPENR_USART1LPEN BIT(RCC_APB2LPENR_USART1LPEN_BIT) +#define RCC_APB2LPENR_TIM8LPEN BIT(RCC_APB2LPENR_TIM8LPEN_BIT) +#define RCC_APB2LPENR_TIM1LPEN BIT(RCC_APB2LPENR_TIM1LPEN_BIT) + +/* Backup domain control register */ + +#define RCC_BDCR_BDRST_BIT 16 +#define RCC_BDCR_RTCEN_BIT 15 +#define RCC_BDCR_LSEBYP_BIT 2 +#define RCC_BDCR_LSERDY_BIT 1 +#define RCC_BDCR_LSEON_BIT 0 + +#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) +#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTCEN_BIT) +#define RCC_BDCR_RTCSEL (0x3 << 8) +#define RCC_BDCR_RTCSEL_NOCLOCK (0x0 << 8) +#define RCC_BDCR_RTCSEL_LSE (0x1 << 8) +#define RCC_BDCR_RTCSEL_LSI (0x2 << 8) +#define RCC_BDCR_RTCSEL_HSE_DIV (0x3 << 8) +#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) +#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) +#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) + +/* Clock control and status register */ + +#define RCC_CSR_LPWRRSTF_BIT 31 +#define RCC_CSR_WWDGRSTF_BIT 30 +#define RCC_CSR_IWDGRSTF_BIT 29 +#define RCC_CSR_SFTRSTF_BIT 28 +#define RCC_CSR_PORRSTF_BIT 27 +#define RCC_CSR_PINRSTF_BIT 26 +#define RCC_CSR_BORRSTF_BIT 25 +#define RCC_CSR_RMVF_BIT 24 +#define RCC_CSR_LSIRDY_BIT 1 +#define RCC_CSR_LSION_BIT 0 + +#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) +#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) +#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) +#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) +#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) +#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) +#define RCC_CSR_BORRSTF BIT(RCC_CSR_BORRSTF_BIT) +#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) +#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) +#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) + +/* Spread spectrum clock generation register */ + + +#define RCC_SSCGR_SSCGEN_BIT 31 +#define RCC_SSCGR_SPREADSEL_BIT 30 + +#define RCC_SSCGR_SSCGEN BIT(RCC_SSCGR_SSCGEN_BIT) +#define RCC_SSCGR_SPREADSEL BIT(RCC_SSCGR_SPREADSEL_BIT) +#define RCC_SSCGR_SPREADSEL_CENTER (0x0 << RCC_SSCGR_SPREADSEL_BIT) +#define RCC_SSCGR_SPREADSEL_DOWN (0x1 << RCC_SSCGR_SPREADSEL_BIT) +#define RCC_SSCGR_INCSTEP (0xFFF << 16) +#define RCC_SSCGR_MODPER 0xFFFF + +/* PLLI2S configuration register */ + +#define RCC_PLLI2SCFGR_PLLI2SR (0x7 << 28) +#define RCC_PLLI2SCFGR_PLLI2SN (0x1FF << 6) + +/* + * Other types + */ + +/** + * @brief Identifies bus and clock line for a peripheral or peripheral + * clock. + */ +typedef enum rcc_clk_id { + RCC_OTGHSULPI, + RCC_OTGHS, + RCC_ETHMACPTP, + RCC_ETHMACRX, + RCC_ETHMACTX, + RCC_ETHMAC, + RCC_DMA2, + RCC_DMA1, + RCC_BKPSRAM, + RCC_CRC, + RCC_GPIOI, + RCC_GPIOH, + RCC_GPIOG, + RCC_GPIOF, + RCC_GPIOE, + RCC_GPIOD, + RCC_GPIOC, + RCC_GPIOB, + RCC_GPIOA, + RCC_OTGFS, + RCC_RNG, + RCC_HASH, + RCC_CRYP, + RCC_DCMI, + RCC_FSMC, + RCC_DAC, + RCC_PWR, + RCC_CAN2, + RCC_CAN1, + RCC_I2C3, + RCC_I2C2, + RCC_I2C1, + RCC_UART5, + RCC_UART4, + RCC_USART3, + RCC_USART2, + RCC_SPI3, + RCC_SPI2, + RCC_WWDG, + RCC_TIM14, + RCC_TIM13, + RCC_TIM12, + RCC_TIM7, + RCC_TIM6, + RCC_TIM5, + RCC_TIM4, + RCC_TIM3, + RCC_TIM2, + RCC_TIM11, + RCC_TIM10, + RCC_TIM9, + RCC_SYSCFG, + RCC_SPI1, + RCC_SDIO, + RCC_ADC3, + RCC_ADC2, + RCC_ADC1, + RCC_USART6, + RCC_USART1, + RCC_TIM8, + RCC_TIM1, +} rcc_clk_id; + +/** + * @brief PLL entry clock source + * @see rcc_clk_init() + */ +typedef enum rcc_pllsrc { + RCC_PLLSRC_HSI = 0, + RCC_PLLSRC_HSE = RCC_PLLCFGR_PLLSRC, +} rcc_pllsrc; + +typedef enum rcc_pll_multiplier { /* TODO -- does this make sense anymore? */ + RCC_PLLMUL_XXX, +} rcc_pll_multiplier; + +/** + * @brief Peripheral clock domains. + */ +typedef enum rcc_clk_domain { + RCC_APB1, + RCC_APB2, + RCC_AHB1, + RCC_AHB2, + RCC_AHB3, +} rcc_clk_domain; + +/** + * @brief Prescaler identifiers. + */ +typedef enum rcc_prescaler { + RCC_PRESCALER_MCO2, + RCC_PRESCALER_MCO1, + RCC_PRESCALER_RTC, + RCC_PRESCALER_APB2, + RCC_PRESCALER_APB1, + RCC_PRESCALER_AHB +} rcc_prescaler; + +/** + * @brief MCO2 prescaler dividers. + */ +typedef enum rcc_mco2_divider { + RCC_MCO2_DIV_1 = RCC_CFGR_MCO2PRE_DIV_1, + RCC_MCO2_DIV_2 = RCC_CFGR_MCO2PRE_DIV_2, + RCC_MCO2_DIV_3 = RCC_CFGR_MCO2PRE_DIV_3, + RCC_MCO2_DIV_4 = RCC_CFGR_MCO2PRE_DIV_4, + RCC_MCO2_DIV_5 = RCC_CFGR_MCO2PRE_DIV_5, +} rcc_mco2_divider; + +/** + * @brief MCO1 prescaler dividers. + */ +typedef enum rcc_mco1_divider { + RCC_MCO1_DIV_1 = RCC_CFGR_MCO1PRE_DIV_1, + RCC_MCO1_DIV_2 = RCC_CFGR_MCO1PRE_DIV_2, + RCC_MCO1_DIV_3 = RCC_CFGR_MCO1PRE_DIV_3, + RCC_MCO1_DIV_4 = RCC_CFGR_MCO1PRE_DIV_4, + RCC_MCO1_DIV_5 = RCC_CFGR_MCO1PRE_DIV_5, +} rcc_mco1_divider; + +/** + * @brief RTC prescaler dividers. + */ +typedef enum rcc_rtc_divider { /* TODO */ + RCC_RTC_DIV_TODO = 0xFFFFFFFF, +} rcc_rtc_divider; + +/** + * @brief AP2 prescaler dividers. + */ +typedef enum rcc_apb2_divider { + RCC_APB2_HCLK_DIV_1 = 0, + RCC_APB2_HCLK_DIV_2 = RCC_CFGR_PPRE2_AHB_DIV_2, + RCC_APB2_HCLK_DIV_4 = RCC_CFGR_PPRE2_AHB_DIV_4, + RCC_APB2_HCLK_DIV_8 = RCC_CFGR_PPRE2_AHB_DIV_8, + RCC_APB2_HCLK_DIV_16 = RCC_CFGR_PPRE2_AHB_DIV_16, +} rcc_apb2_divider; + +/** + * @brief AP1 prescaler dividers. + */ +typedef enum rcc_apb1_divider { + RCC_APB1_HCLK_DIV_1 = 0, + RCC_APB1_HCLK_DIV_2 = RCC_CFGR_PPRE1_AHB_DIV_2, + RCC_APB1_HCLK_DIV_4 = RCC_CFGR_PPRE1_AHB_DIV_4, + RCC_APB1_HCLK_DIV_8 = RCC_CFGR_PPRE1_AHB_DIV_8, + RCC_APB1_HCLK_DIV_16 = RCC_CFGR_PPRE1_AHB_DIV_16, +} rcc_apb1_divider; + +/** + * @brief AHB prescaler dividers. + */ +typedef enum rcc_ahb_divider { + RCC_AHB_SYSCLK_DIV_1 = 0, + RCC_AHB_SYSCLK_DIV_2 = RCC_CFGR_HPRE_SYSCLK_DIV_2, + RCC_AHB_SYSCLK_DIV_4 = RCC_CFGR_HPRE_SYSCLK_DIV_4, + RCC_AHB_SYSCLK_DIV_8 = RCC_CFGR_HPRE_SYSCLK_DIV_8, + RCC_AHB_SYSCLK_DIV_16 = RCC_CFGR_HPRE_SYSCLK_DIV_16, + RCC_AHB_SYSCLK_DIV_64 = RCC_CFGR_HPRE_SYSCLK_DIV_64, + RCC_AHB_SYSCLK_DIV_128 = RCC_CFGR_HPRE_SYSCLK_DIV_128, + RCC_AHB_SYSCLK_DIV_256 = RCC_CFGR_HPRE_SYSCLK_DIV_256, + RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512, +} rcc_ahb_divider; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c new file mode 100644 index 0000000..268a9b1 --- /dev/null +++ b/libmaple/stm32f2/rcc.c @@ -0,0 +1,168 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/rcc.c + * @brief STM32F2 RCC routines. + */ + +#include +#include + +#include "rcc_private.h" + +#define DEV_ENTRY(domain, dev) \ + {.clk_domain = RCC_##domain, .line_num = RCC_##domain##ENR_##dev##EN_BIT} + +const struct rcc_dev_info rcc_dev_table[] = { + /* AHB1 */ + [RCC_OTGHSULPI] = DEV_ENTRY(AHB1, OTGHSULPI), + [RCC_OTGHS] = DEV_ENTRY(AHB1, OTGHS), + [RCC_ETHMACPTP] = DEV_ENTRY(AHB1, ETHMACPTP), + [RCC_ETHMACRX] = DEV_ENTRY(AHB1, ETHMACRX), + [RCC_ETHMACTX] = DEV_ENTRY(AHB1, ETHMACTX), + [RCC_ETHMAC] = DEV_ENTRY(AHB1, ETHMAC), + [RCC_DMA2] = DEV_ENTRY(AHB1, DMA2), + [RCC_DMA1] = DEV_ENTRY(AHB1, DMA1), + [RCC_BKPSRAM] = DEV_ENTRY(AHB1, BKPSRAM), + [RCC_CRC] = DEV_ENTRY(AHB1, CRC), + [RCC_GPIOI] = DEV_ENTRY(AHB1, GPIOI), + [RCC_GPIOH] = DEV_ENTRY(AHB1, GPIOH), + [RCC_GPIOG] = DEV_ENTRY(AHB1, GPIOG), + [RCC_GPIOF] = DEV_ENTRY(AHB1, GPIOF), + [RCC_GPIOE] = DEV_ENTRY(AHB1, GPIOE), + [RCC_GPIOD] = DEV_ENTRY(AHB1, GPIOD), + [RCC_GPIOC] = DEV_ENTRY(AHB1, GPIOC), + [RCC_GPIOB] = DEV_ENTRY(AHB1, GPIOB), + [RCC_GPIOA] = DEV_ENTRY(AHB1, GPIOA), + + /* AHB2 */ + [RCC_OTGFS] = DEV_ENTRY(AHB2, OTGFS), + [RCC_RNG] = DEV_ENTRY(AHB2, RNG), + [RCC_HASH] = DEV_ENTRY(AHB2, HASH), + [RCC_CRYP] = DEV_ENTRY(AHB2, CRYP), + [RCC_DCMI] = DEV_ENTRY(AHB2, DCMI), + + /* AHB3 */ + [RCC_FSMC] = DEV_ENTRY(AHB3, FSMC), + + /* APB1 */ + [RCC_DAC] = DEV_ENTRY(APB1, DAC), + [RCC_PWR] = DEV_ENTRY(APB1, PWR), + [RCC_CAN2] = DEV_ENTRY(APB1, CAN2), + [RCC_CAN1] = DEV_ENTRY(APB1, CAN1), + [RCC_I2C3] = DEV_ENTRY(APB1, I2C3), + [RCC_I2C2] = DEV_ENTRY(APB1, I2C2), + [RCC_I2C1] = DEV_ENTRY(APB1, I2C1), + [RCC_UART5] = DEV_ENTRY(APB1, UART5), + [RCC_UART4] = DEV_ENTRY(APB1, UART4), + [RCC_USART3] = DEV_ENTRY(APB1, USART3), + [RCC_USART2] = DEV_ENTRY(APB1, USART2), + [RCC_SPI3] = DEV_ENTRY(APB1, SPI3), + [RCC_SPI2] = DEV_ENTRY(APB1, SPI2), + [RCC_WWDG] = DEV_ENTRY(APB1, WWDG), + [RCC_TIM14] = DEV_ENTRY(APB1, TIM14), + [RCC_TIM13] = DEV_ENTRY(APB1, TIM13), + [RCC_TIM12] = DEV_ENTRY(APB1, TIM12), + [RCC_TIM7] = DEV_ENTRY(APB1, TIM7), + [RCC_TIM6] = DEV_ENTRY(APB1, TIM6), + [RCC_TIM5] = DEV_ENTRY(APB1, TIM5), + [RCC_TIM4] = DEV_ENTRY(APB1, TIM4), + [RCC_TIM3] = DEV_ENTRY(APB1, TIM3), + [RCC_TIM2] = DEV_ENTRY(APB1, TIM2), + + /* APB2 */ + [RCC_TIM11] = DEV_ENTRY(APB2, TIM11), + [RCC_TIM10] = DEV_ENTRY(APB2, TIM10), + [RCC_TIM9] = DEV_ENTRY(APB2, TIM9), + [RCC_SYSCFG] = DEV_ENTRY(APB2, SYSCFG), + [RCC_SPI1] = DEV_ENTRY(APB2, SPI1), + [RCC_SDIO] = DEV_ENTRY(APB2, SDIO), + [RCC_ADC3] = DEV_ENTRY(APB2, ADC3), + [RCC_ADC2] = DEV_ENTRY(APB2, ADC2), + [RCC_ADC1] = DEV_ENTRY(APB2, ADC1), + [RCC_USART6] = DEV_ENTRY(APB2, USART6), + [RCC_USART1] = DEV_ENTRY(APB2, USART1), + [RCC_TIM8] = DEV_ENTRY(APB2, TIM8), + [RCC_TIM1] = DEV_ENTRY(APB2, TIM1), +}; + +void rcc_clk_init(rcc_sysclk_src sysclk_src, + rcc_pllsrc pll_src, + rcc_pll_multiplier pll_mul) { + ASSERT(0); /* FIXME */ +} + +/** + * @brief Turn on the clock line on a peripheral + * @param id Clock ID of the peripheral to turn on. + */ +void rcc_clk_enable(rcc_clk_id id) { + static __io uint32* enable_regs[] = { + [RCC_AHB1] = &RCC_BASE->AHB1ENR, + [RCC_AHB2] = &RCC_BASE->AHB2ENR, + [RCC_AHB3] = &RCC_BASE->AHB3ENR, + [RCC_APB1] = &RCC_BASE->APB1ENR, + [RCC_APB2] = &RCC_BASE->APB2ENR, + }; + rcc_do_clk_enable(enable_regs, id); +} + +/** + * @brief Reset a peripheral. + * + * Caution: not all rcc_clk_id values refer to a peripheral which can + * be reset. + * + * @param id Clock ID of the peripheral to reset. + */ +void rcc_reset_dev(rcc_clk_id id) { + static __io uint32* reset_regs[] = { + [RCC_AHB1] = &RCC_BASE->AHB1RSTR, + [RCC_AHB2] = &RCC_BASE->AHB2RSTR, + [RCC_AHB3] = &RCC_BASE->AHB3RSTR, + [RCC_APB1] = &RCC_BASE->AHB3RSTR, + [RCC_APB2] = &RCC_BASE->AHB3RSTR, + }; + rcc_do_reset_dev(reset_regs, id); +} + +/** + * @brief Set the divider on a peripheral prescaler + * @param prescaler prescaler to set + * @param divider prescaler divider + */ +void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { + static const uint32 masks[] = { + [RCC_PRESCALER_MCO2] = RCC_CFGR_MCO2PRE, + [RCC_PRESCALER_MCO1] = RCC_CFGR_MCO1PRE, + [RCC_PRESCALER_RTC] = RCC_CFGR_RTCPRE, + [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2, + [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1, + [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE, + }; + rcc_do_set_prescaler(masks, prescaler, divider); +} diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index afdcd4f..a865340 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -9,7 +9,7 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We # Local rules and targets sSRCS_$(d) := isrs.S vector_table.S -cSRCS_$(d) := +cSRCS_$(d) := rcc.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 17c4d2136f6efbac66600d54b05378529cc96718 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 20 Nov 2011 20:58:02 -0500 Subject: Initial STM32F2 GPIO support. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/gpio.c | 157 +++++++++++++++++++++++ libmaple/stm32f2/include/series/gpio.h | 222 +++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + 3 files changed, 380 insertions(+) create mode 100644 libmaple/stm32f2/gpio.c create mode 100644 libmaple/stm32f2/include/series/gpio.h diff --git a/libmaple/stm32f2/gpio.c b/libmaple/stm32f2/gpio.c new file mode 100644 index 0000000..61b71f7 --- /dev/null +++ b/libmaple/stm32f2/gpio.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/gpio.c + * @brief GPIO support for STM32F2 line. + */ + +#include +#include +#include + +/* + * GPIO devices + */ + +gpio_dev gpioa = { + .regs = GPIOA_BASE, + .clk_id = RCC_GPIOA, +}; +/** GPIO port A device. */ +gpio_dev* const GPIOA = &gpioa; + +gpio_dev gpiob = { + .regs = GPIOB_BASE, + .clk_id = RCC_GPIOB, +}; +/** GPIO port B device. */ +gpio_dev* const GPIOB = &gpiob; + +gpio_dev gpioc = { + .regs = GPIOC_BASE, + .clk_id = RCC_GPIOC, +}; +/** GPIO port C device. */ +gpio_dev* const GPIOC = &gpioc; + +gpio_dev gpiod = { + .regs = GPIOD_BASE, + .clk_id = RCC_GPIOD, +}; +/** GPIO port D device. */ +gpio_dev* const GPIOD = &gpiod; + +gpio_dev gpioe = { + .regs = GPIOE_BASE, + .clk_id = RCC_GPIOE, +}; +/** GPIO port E device. */ +gpio_dev* const GPIOE = &gpioe; + +gpio_dev gpiof = { + .regs = GPIOF_BASE, + .clk_id = RCC_GPIOF, +}; +/** GPIO port F device. */ +gpio_dev* const GPIOF = &gpiof; + +gpio_dev gpiog = { + .regs = GPIOG_BASE, + .clk_id = RCC_GPIOG, +}; +/** GPIO port G device. */ +gpio_dev* const GPIOG = &gpiog; + +gpio_dev gpioh = { + .regs = GPIOG_BASE, + .clk_id = RCC_GPIOH, +}; +/** GPIO port G device. */ +gpio_dev* const GPIOH = &gpioh; + +gpio_dev gpioi = { + .regs = GPIOI_BASE, + .clk_id = RCC_GPIOI, +}; +/** GPIO port G device. */ +gpio_dev* const GPIOI = &gpioi; + +/* + * GPIO routines + */ + +/** + * Initialize and reset all available GPIO devices. + */ +void gpio_init_all(void) { + gpio_init(GPIOA); + gpio_init(GPIOB); + gpio_init(GPIOC); + gpio_init(GPIOD); + gpio_init(GPIOE); + gpio_init(GPIOF); + gpio_init(GPIOG); + gpio_init(GPIOH); + gpio_init(GPIOI); +} + +/** + * @brief Set the mode of a GPIO pin. + * @param dev GPIO device. + * @param pin Pin on the device whose mode to set, 0--15. + * @param mode Mode to set the pin to. + * @param flags Flags to modify basic mode configuration + */ +void gpio_set_modef(gpio_dev *dev, + uint8 pin, + gpio_pin_mode mode, + unsigned flags) { + gpio_reg_map *regs = dev->regs; + unsigned shift = pin * 2; + uint32 tmp; + + /* Mode */ + tmp = regs->MODER; + tmp &= ~(0x3 << shift); + tmp |= mode << shift; + regs->MODER = tmp; + + /* Output type */ + bb_peri_set_bit(®s->OTYPER, pin, flags & 0x1); + + /* Speed */ + tmp = regs->OSPEEDR; + tmp &= ~(0x3 << shift); + tmp |= (flags >> 1) << shift; + regs->OSPEEDR = tmp; + + /* Pull-up/pull-down */ + tmp = regs->PUPDR; + tmp &= ~(0x3 << shift); + tmp |= (flags >> 2) << shift; + regs->PUPDR = tmp; +} diff --git a/libmaple/stm32f2/include/series/gpio.h b/libmaple/stm32f2/include/series/gpio.h new file mode 100644 index 0000000..86ee4aa --- /dev/null +++ b/libmaple/stm32f2/include/series/gpio.h @@ -0,0 +1,222 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +/** + * @file libmaple/stm32f2/gpio.h + * @brief STM32F2 General Purpose I/O (GPIO) header. + */ + +#ifndef _LIBMAPLE_STM32F2_GPIO_H_ +#define _LIBMAPLE_STM32F2_GPIO_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/* + * GPIO register maps and devices + */ + +/** GPIO register map type */ +typedef struct gpio_reg_map { + __io uint32 MODER; /**< Mode register */ + __io uint32 OTYPER; /**< Output type register */ + __io uint32 OSPEEDR; /**< Output speed register */ + __io uint32 PUPDR; /**< Pull-up/pull-down register */ + __io uint32 IDR; /**< Input data register */ + __io uint32 ODR; /**< Output data register */ + __io uint32 BSRR; /**< Bit set/reset register */ + __io uint32 LCKR; /**< Configuration lock register */ + __io uint32 AFRL; /**< Alternate function low register */ + __io uint32 AFRH; /**< Alternate function high register */ +} gpio_reg_map; + +/** GPIO port A register map base pointer */ +#define GPIOA_BASE ((struct gpio_reg_map*)0x40020000) +/** GPIO port B register map base pointer */ +#define GPIOB_BASE ((struct gpio_reg_map*)0x40020400) +/** GPIO port C register map base pointer */ +#define GPIOC_BASE ((struct gpio_reg_map*)0x40020800) +/** GPIO port D register map base pointer */ +#define GPIOD_BASE ((struct gpio_reg_map*)0x40020C00) +/** GPIO port E register map base pointer */ +#define GPIOE_BASE ((struct gpio_reg_map*)0x40021000) +/** GPIO port F register map base pointer */ +#define GPIOF_BASE ((struct gpio_reg_map*)0x40021400) +/** GPIO port G register map base pointer */ +#define GPIOG_BASE ((struct gpio_reg_map*)0x40021800) +/** GPIO port H register map base pointer */ +#define GPIOH_BASE ((struct gpio_reg_map*)0x40021C00) +/** GPIO port I register map base pointer */ +#define GPIOI_BASE ((struct gpio_reg_map*)0x40022000) + +/** GPIO device type */ +typedef struct gpio_dev { + gpio_reg_map *regs; + rcc_clk_id clk_id; +} gpio_dev; + +extern gpio_dev* const GPIOA; +extern gpio_dev gpioa; +extern gpio_dev* const GPIOB; +extern gpio_dev gpiob; +extern gpio_dev* const GPIOC; +extern gpio_dev gpioc; +extern gpio_dev* const GPIOD; +extern gpio_dev gpiod; +extern gpio_dev* const GPIOE; +extern gpio_dev gpioe; +extern gpio_dev* const GPIOF; +extern gpio_dev gpiof; +extern gpio_dev* const GPIOG; +extern gpio_dev gpiog; +extern gpio_dev* const GPIOH; +extern gpio_dev gpioh; +extern gpio_dev* const GPIOI; +extern gpio_dev gpioi; + +/* + * Register bit definitions + * + * Currently, we only provide masks to be used for shifting, rather + * than repeating the same values 16 times. + */ + +/* Mode register */ + +#define GPIO_MODER_INPUT 0x0 +#define GPIO_MODER_OUTPUT 0x1 +#define GPIO_MODER_AF 0x2 +#define GPIO_MODER_ANALOG 0x3 + +/* Output type register */ + +#define GPIO_OTYPER_PP 0x0 +#define GPIO_OTYPER_OD 0x1 + +/* Output speed register */ + +#define GPIO_OSPEEDR_LOW 0x0 +#define GPIO_OSPEEDR_MED 0x1 +#define GPIO_OSPEEDR_FAST 0x2 +#define GPIO_OSPEEDR_HIGH 0x3 + +/* Pull-up/pull-down register */ + +#define GPIO_PUPDR_NOPUPD 0x0 +#define GPIO_PUPDR_PU 0x1 +#define GPIO_PUPDR_PD 0x2 + +/* + * GPIO routines + */ + +/** + * @brief GPIO pin modes + */ +typedef enum gpio_pin_mode { + GPIO_MODE_INPUT = GPIO_MODER_INPUT, /**< Input mode */ + GPIO_MODE_OUTPUT = GPIO_MODER_OUTPUT, /**< Output mode */ + GPIO_MODE_AF = GPIO_MODER_AF, /**< Alternate function mode */ + GPIO_MODE_ANALOG = GPIO_MODER_ANALOG, /**< Analog mode */ +} gpio_pin_mode; + +/** + * @brief Additional flags to be used when setting a pin's mode. + * + * Beyond the basic modes (input, general purpose output, alternate + * function, and analog), there are three parameters that can affect a + * pin's mode: + * + * 1. Output type: push/pull or open-drain. This only has an effect + * for output modes. Choices are: GPIO_MODEF_TYPE_PP (the default) + * and GPIO_MODEF_TYPE_OD. + * + * 2. Output speed: specifies the frequency at which a pin changes + * state. This only has an effect for output modes. Choices are: + * GPIO_MODEF_SPEED_LOW (default), GPIO_MODEF_SPEED_MED, + * GPIO_MODEF_SPEED_FAST, and GPIO_MODEF_SPEED_HIGH. + * + * 3. Push/pull setting: All GPIO pins have weak pull-up and pull-down + * resistors that can be enabled when the pin's mode is + * set. Choices are: GPIO_MODEF_PUPD_NONE (default), + * GPIO_MODEF_PUPD_PU, and GPIO_MODEF_PUPD_PD. + */ +typedef enum gpio_mode_flags { + /* Output type in bit 0 */ + GPIO_MODEF_TYPE_PP = GPIO_OTYPER_PP, /**< Output push/pull (default). + Applies only when the mode + specifies output. */ + GPIO_MODEF_TYPE_OD = GPIO_OTYPER_OD, /**< Output open drain. + Applies only when the mode + specifies output. */ + + /* Speed in bits 2:1 */ + GPIO_MODEF_SPEED_LOW = GPIO_OSPEEDR_LOW << 1, /**< Low speed (default): + 2 MHz. */ + GPIO_MODEF_SPEED_MED = GPIO_OSPEEDR_MED << 1, /**< Medium speed: 25 MHz. */ + GPIO_MODEF_SPEED_FAST = GPIO_OSPEEDR_FAST << 1, /**< Fast speed: 50 MHz. */ + GPIO_MODEF_SPEED_HIGH = GPIO_OSPEEDR_HIGH << 1, /**< High speed: + 100 MHz on 30 pF, + 80 MHz on 15 pF. */ + + /* Pull-up/pull-down in bits 4:3 */ + GPIO_MODEF_PUPD_NONE = GPIO_PUPDR_NOPUPD << 3, /**< No pull-up/pull-down + (default). */ + GPIO_MODEF_PUPD_PU = GPIO_PUPDR_PU << 3, /**< Pull-up */ + GPIO_MODEF_PUPD_PD = GPIO_PUPDR_PD << 3, /**< Pull-down */ +} gpio_mode_flags; + +void gpio_set_modef(gpio_dev *dev, + uint8 pin, + gpio_pin_mode mode, + unsigned flags); + +/** + * @brief Set the mode of a GPIO pin. + * + * Calling this function is equivalent to calling gpio_set_modef(dev, + * pin, mode, GPIO_MODE_SPEED_HIGH). Note that this overrides the + * default speed. + * + * @param dev GPIO device. + * @param pin Pin on the device whose mode to set, 0--15. + * @param mode Mode to set the pin to. + */ +static inline void gpio_set_mode(gpio_dev *dev, + uint8 pin, + gpio_pin_mode mode) { + gpio_set_modef(dev, pin, mode, GPIO_MODEF_SPEED_HIGH); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index a865340..83ab043 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -10,6 +10,7 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We # Local rules and targets sSRCS_$(d) := isrs.S vector_table.S cSRCS_$(d) := rcc.c +cSRCS_$(d) += gpio.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 7902ca198e8eac83f0703bbe9d5e8f7830720bb5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 14:38:31 -0500 Subject: Initial STM32F2 series/stm32.h. This still has some FIXMEs, but it's enough to get going. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/stm32.h | 83 +++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 libmaple/stm32f2/include/series/stm32.h diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h new file mode 100644 index 0000000..8b14a7d --- /dev/null +++ b/libmaple/stm32f2/include/series/stm32.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/stm32.h + * @brief STM32F2 chip- and series-specific definitions. + */ + +#ifndef _LIBMAPLE_STM32F2_H_ +#define _LIBMAPLE_STM32F2_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Chip configuration + */ + +#ifndef STM32_PCLK1 +#define STM32_PCLK1 30000000U +#endif + +#ifndef STM32_PCLK2 +#define STM32_PCLK2 60000000U +#endif + +#ifndef STM32_DELAY_US_MULT +#define STM32_DELAY_US_MULT 20 /* FIXME: dummy value. */ +#endif + +#ifndef STM32_FLASH_WAIT_STATES +#define STM32_FLASH_WAIT_STATES 3 /* TODO: stop using magic number */ +#endif + +/* + * Interrupts + */ + +#define STM32_NR_INTERRUPTS 81 + +/* + * Series- and MCU-specific values + */ + +#define STM32_MCU_SERIES STM32_SERIES_F2 + +#if defined(MCU_STM32F207IC) +# define STM32_NR_GPIO_PORTS 9 +# define STM32_SRAM_END ((void*)0x20020000) + +#else +#error "Unrecognized STM32F2 MCU, or no MCU specified." +#endif + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.2.3 From 2ab2f4d3784692f8cd0e79d24638157926f894ca Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 21 Nov 2011 17:22:38 -0500 Subject: [UNDO] Rip out everything but libmaple and Wirish startup code. We'll need to bring all this functionality back online piecemeal as we add F2 support. Signed-off-by: Marti Bolivar --- Makefile | 8 ++++---- wirish/rules.mk | 38 +++++++++++++++++++------------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/Makefile b/Makefile index 9b37580..785b9a6 100644 --- a/Makefile +++ b/Makefile @@ -79,12 +79,12 @@ LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # USB FS device LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_SERIES) # STM32 series submodule in libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish # Official libraries: -LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo -LIBMAPLE_MODULES += $(SRCROOT)/libraries/LiquidCrystal -LIBMAPLE_MODULES += $(SRCROOT)/libraries/Wire +# LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo +# LIBMAPLE_MODULES += $(SRCROOT)/libraries/LiquidCrystal +# LIBMAPLE_MODULES += $(SRCROOT)/libraries/Wire # Experimental libraries: -LIBMAPLE_MODULES += $(SRCROOT)/libraries/FreeRTOS +# LIBMAPLE_MODULES += $(SRCROOT)/libraries/FreeRTOS # Call each module's rules.mk: $(foreach m,$(LIBMAPLE_MODULES),$(eval $(call LIBMAPLE_MODULE_template,$(m)))) diff --git a/wirish/rules.mk b/wirish/rules.mk index 6fa3a28..c72e60f 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -5,33 +5,33 @@ d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) # Board config -- TODO allow user override -WIRISH_BOARD_PATH := boards/$(BOARD) -BUILDDIRS += $(BUILD_PATH)/$(d)/$(WIRISH_BOARD_PATH) +# WIRISH_BOARD_PATH := boards/$(BOARD) +# BUILDDIRS += $(BUILD_PATH)/$(d)/$(WIRISH_BOARD_PATH) -WIRISH_INCLUDES := -I$(d)/include -I$(d)/$(WIRISH_BOARD_PATH)/include +# WIRISH_INCLUDES := -I$(d)/include -I$(d)/$(WIRISH_BOARD_PATH)/include # Local flags -CFLAGS_$(d) := $(WIRISH_INCLUDES) $(LIBMAPLE_INCLUDES) +CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) # Local rules and targets sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c -cppSRCS_$(d) := wirish_math.cpp \ - Print.cpp \ - boards.cpp \ - HardwareSerial.cpp \ - HardwareSPI.cpp \ - HardwareTimer.cpp \ - usb_serial.cpp \ - cxxabi-compat.cpp \ - wirish_shift.cpp \ - wirish_analog.cpp \ - wirish_time.cpp \ - pwm.cpp \ - ext_interrupts.cpp \ - wirish_digital.cpp -cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp +# cppSRCS_$(d) := wirish_math.cpp \ +# Print.cpp \ +# boards.cpp \ +# HardwareSerial.cpp \ +# HardwareSPI.cpp \ +# HardwareTimer.cpp \ +# usb_serial.cpp \ +# cxxabi-compat.cpp \ +# wirish_shift.cpp \ +# wirish_analog.cpp \ +# wirish_time.cpp \ +# pwm.cpp \ +# ext_interrupts.cpp \ +# wirish_digital.cpp +# cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 1ffbef80396cdb13a7976de0eefdc3017ca4499c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 29 Nov 2011 16:16:05 -0500 Subject: [UNDO] Rip out a bunch of F1-only bits from libmaple proper We'll need to bring this functionality back online piecemeal as we add F2 support. Signed-off-by: Marti Bolivar --- Makefile | 2 +- libmaple/rules.mk | 13 +----------- libmaple/util.c | 62 ++++++++++++++++++++++++++++--------------------------- 3 files changed, 34 insertions(+), 43 deletions(-) diff --git a/Makefile b/Makefile index 785b9a6..0784644 100644 --- a/Makefile +++ b/Makefile @@ -75,7 +75,7 @@ ifeq ($(LIBMAPLE_MODULES),) else LIBMAPLE_MODULES += $(SRCROOT)/libmaple endif -LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # USB FS device +# LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # USB FS device LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_SERIES) # STM32 series submodule in libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish # Official libraries: diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 61d4edd..8802161 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -11,23 +11,12 @@ LIBMAPLE_PRIVATE_INCLUDES := -I$(LIBMAPLE_PATH) CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets -cSRCS_$(d) := adc.c \ - dac.c \ - dma.c \ - exti.c \ - flash.c \ - fsmc.c \ +cSRCS_$(d) := flash.c \ gpio.c \ - iwdg.c \ nvic.c \ - pwr.c \ - i2c.c \ rcc.c \ - spi.c \ syscalls.c \ systick.c \ - timer.c \ - usart.c \ util.c sSRCS_$(d) := exc.S diff --git a/libmaple/util.c b/libmaple/util.c index 07e9572..96050a1 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -62,18 +62,18 @@ void __error(void) { /* Turn off peripheral interrupts */ nvic_irq_disable_all(); - /* Turn off timers */ - timer_disable_all(); + /* /\* Turn off timers *\/ */ + /* timer_disable_all(); */ - /* Turn off ADC */ - adc_disable_all(); + /* /\* Turn off ADC *\/ */ + /* adc_disable_all(); */ - /* Turn off all USARTs */ - usart_disable_all(); + /* /\* Turn off all USARTs *\/ */ + /* usart_disable_all(); */ - /* Turn the USB interrupt back on so the bootloader keeps on functioning */ - nvic_irq_enable(NVIC_USB_HP_CAN_TX); - nvic_irq_enable(NVIC_USB_LP_CAN_RX0); + /* /\* Turn the USB interrupt back on so the bootloader keeps on functioning *\/ */ + /* nvic_irq_enable(NVIC_USB_HP_CAN_TX); */ + /* nvic_irq_enable(NVIC_USB_LP_CAN_RX0); */ /* Reenable global interrupts */ nvic_globalirq_enable(); @@ -85,9 +85,9 @@ void __error(void) { * @sideeffect Configures ERROR_USART appropriately for writing. */ void _enable_error_usart() { - gpio_set_mode(ERROR_TX_PORT, ERROR_TX_PIN, GPIO_AF_OUTPUT_PP); - usart_init(ERROR_USART); - usart_set_baud_rate(ERROR_USART, ERROR_USART_CLK_SPEED, ERROR_USART_BAUD); + /* gpio_set_mode(ERROR_TX_PORT, ERROR_TX_PIN, GPIO_AF_OUTPUT_PP); */ + /* usart_init(ERROR_USART); */ + /* usart_set_baud_rate(ERROR_USART, ERROR_USART_CLK_SPEED, ERROR_USART_BAUD); */ } /** @@ -100,17 +100,17 @@ void _enable_error_usart() { */ void _fail(const char* file, int line, const char* exp) { /* Initialize the error USART */ - _enable_error_usart(); - - /* Print failed assert message */ - usart_putstr(ERROR_USART, "ERROR: FAILED ASSERT("); - usart_putstr(ERROR_USART, exp); - usart_putstr(ERROR_USART, "): "); - usart_putstr(ERROR_USART, file); - usart_putstr(ERROR_USART, ": "); - usart_putudec(ERROR_USART, line); - usart_putc(ERROR_USART, '\n'); - usart_putc(ERROR_USART, '\r'); + /* _enable_error_usart(); */ + + /* /\* Print failed assert message *\/ */ + /* usart_putstr(ERROR_USART, "ERROR: FAILED ASSERT("); */ + /* usart_putstr(ERROR_USART, exp); */ + /* usart_putstr(ERROR_USART, "): "); */ + /* usart_putstr(ERROR_USART, file); */ + /* usart_putstr(ERROR_USART, ": "); */ + /* usart_putudec(ERROR_USART, line); */ + /* usart_putc(ERROR_USART, '\n'); */ + /* usart_putc(ERROR_USART, '\r'); */ /* Shutdown and error fade */ __error(); @@ -130,14 +130,16 @@ void __assert_func(const char* file, int line, const char* method, * error state with the throbbing LED indicator. */ void abort() { - /* Initialize the error USART */ - _enable_error_usart(); + /* /\* Initialize the error USART *\/ */ + /* _enable_error_usart(); */ - /* Print abort message. */ - usart_putstr(ERROR_USART, "ERROR: PROGRAM ABORTED VIA abort()\n\r"); + /* /\* Print abort message. *\/ */ + /* usart_putstr(ERROR_USART, "ERROR: PROGRAM ABORTED VIA abort()\n\r"); */ - /* Shutdown and error fade */ - __error(); + /* /\* Shutdown and error fade *\/ */ + /* __error(); */ + while (1) + ; } /** @@ -145,7 +147,7 @@ void abort() { * @sideeffect Sets output push-pull on ERROR_LED_PIN. */ void throb(void) { -#ifdef HAVE_ERROR_LED +#if 0 int32 slope = 1; uint32 CC = 0x0000; uint32 TOP_CNT = 0x0200; -- cgit v1.2.3 From 59e02b35a7714a6d10afbf33dd4ea933cfaebab4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Jan 2012 13:51:07 -0500 Subject: ld/make: Add support for STM3220G-EVAL board. Signed-off-by: Marti Bolivar --- support/ld/st_stm3220g_eval/jtag.ld | 17 +++++++++++++++++ support/make/board-includes/st_stm3220g_eval.mk | 4 ++++ 2 files changed, 21 insertions(+) create mode 100644 support/ld/st_stm3220g_eval/jtag.ld create mode 100644 support/make/board-includes/st_stm3220g_eval.mk diff --git a/support/ld/st_stm3220g_eval/jtag.ld b/support/ld/st_stm3220g_eval/jtag.ld new file mode 100644 index 0000000..4193f5b --- /dev/null +++ b/support/ld/st_stm3220g_eval/jtag.ld @@ -0,0 +1,17 @@ +/* + * STM3220G-EVAL (STM32F207IGH6) linker script for JTAG (bare metal, + * no bootloader) builds. + */ + +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", rom); + +INCLUDE common.inc diff --git a/support/make/board-includes/st_stm3220g_eval.mk b/support/make/board-includes/st_stm3220g_eval.mk new file mode 100644 index 0000000..f8073ea --- /dev/null +++ b/support/make/board-includes/st_stm3220g_eval.mk @@ -0,0 +1,4 @@ +MCU := STM32F207IG +ERROR_LED_PORT := GPIOG +ERROR_LED_PIN := 6 +MCU_SERIES := stm32f2 -- cgit v1.2.3 From 0ac67559bb4d69557c866bd6bdde4a9402bc2ff0 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Jan 2012 13:51:48 -0500 Subject: stm32f2/stm32.h: Add support for STM32F207IG. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 27 ++++++++++++++++++--------- libmaple/stm32f2/include/series/stm32.h | 2 +- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 4c0898b..3f86faa 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -36,15 +36,20 @@ extern "C" { #endif -/** - * @brief STM32 series identifiers. +/* + * STM32 series identifiers. + * + * Don't make these into an enum; the preprocessor needs them. */ -typedef enum stm32_series { - STM32_SERIES_F1, /**< F1 series */ - STM32_SERIES_F2, /**< F2 series */ - STM32_SERIES_L1, /**< L1 series */ - STM32_SERIES_F4, /**< F4 series */ -} stm32_series; + +/** STM32F1 series. */ +#define STM32_SERIES_F1 0 +/** STM32F2 series. */ +#define STM32_SERIES_F2 1 +/** STM32L1 series. */ +#define STM32_SERIES_L1 2 +/** STM32F4 series. */ +#define STM32_SERIES_F4 3 /* The series header is responsible for defining: * @@ -83,7 +88,11 @@ typedef enum stm32_series { */ /** - * @brief enum stm32_series value for the MCU being targeted. + * @brief STM32 series value for the MCU being targeted. + * + * At time of writing, allowed values are: STM32_SERIES_F1, + * STM32_SERIES_F2. This set of values will expand as libmaple adds + * support for more STM32 series MCUs. */ #define STM32_MCU_SERIES diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 8b14a7d..7ae53b2 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -68,7 +68,7 @@ extern "C" { #define STM32_MCU_SERIES STM32_SERIES_F2 -#if defined(MCU_STM32F207IC) +#if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG) # define STM32_NR_GPIO_PORTS 9 # define STM32_SRAM_END ((void*)0x20020000) -- cgit v1.2.3 From e6a595b6e51e82388b323dbd4f96aad023ddd978 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Jan 2012 13:52:44 -0500 Subject: [WIP] boards: Add st_stm3220g_eval. This supports ST's STM3220G-EVAL, the standard "kitchen-sink" evaluation board for the STM32F2 series. Signed-off-by: Marti Bolivar --- wirish/boards/st_stm3220g_eval/board.cpp | 60 ++++++++++++++++++++++ .../boards/st_stm3220g_eval/include/board/board.h | 49 ++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 wirish/boards/st_stm3220g_eval/board.cpp create mode 100644 wirish/boards/st_stm3220g_eval/include/board/board.h diff --git a/wirish/boards/st_stm3220g_eval/board.cpp b/wirish/boards/st_stm3220g_eval/board.cpp new file mode 100644 index 0000000..674fc67 --- /dev/null +++ b/wirish/boards/st_stm3220g_eval/board.cpp @@ -0,0 +1,60 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/st_stm3220g_eval/board.cpp + * @author Marti Bolivar + * @brief STM3220G-EVAL board file. + */ + +#include + +#include +#include +#include + +/* Board initialization. Unused. */ +void boardInit(void) { +} + +/* Pin map. Current restrictions: + * - LEDs and user button only + * - GPIO devices only (no timers etc. yet) + */ +#define pmap_row(dev, bit) {dev, NULL, NULL, bit, 0, ADCx} +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + pmap_row(GPIOG, 6), /* D0/PG6 (LED1) */ + pmap_row(GPIOG, 8), /* D1/PG8 (LED2) */ + pmap_row(GPIOI, 9), /* D2/PI9 (LED3) */ + pmap_row(GPIOC, 7), /* D4/PC7 (LED4) */ + pmap_row(GPIOG, 15), /* D5/PG15 (BUT) */ +}; +#undef pmap_row + +/* Special pin arrays. Unused. */ +extern const uint8 boardPWMPins[] __FLASH__ = {}; +extern const uint8 boardADCPins[] __FLASH__ = {}; +extern const uint8 boardUsedPins[] __FLASH__ = {}; diff --git a/wirish/boards/st_stm3220g_eval/include/board/board.h b/wirish/boards/st_stm3220g_eval/include/board/board.h new file mode 100644 index 0000000..08b935e --- /dev/null +++ b/wirish/boards/st_stm3220g_eval/include/board/board.h @@ -0,0 +1,49 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/st_stm3220g_eval/include/board/board.h + * @author Marti Bolivar + * @brief STM3220G-EVAL board header. + */ + +#ifndef _BOARD_ST_STM3220G_EVAL_H_ +#define _BOARD_ST_STM3220G_EVAL_H_ + +#define CYCLES_PER_MICROSECOND 120 +#define SYSTICK_RELOAD_VAL 119999 /* takes a cycle to reload */ + +#define BOARD_BUTTON_PIN 5 +#define BOARD_LED_PIN 0 + +#define BOARD_NR_USARTS 0 +#define BOARD_NR_SPI 0 +#define BOARD_NR_GPIO_PINS 6 +#define BOARD_NR_PWM_PINS 0 +#define BOARD_NR_ADC_PINS 0 +#define BOARD_NR_USED_PINS 6 + +#endif -- cgit v1.2.3 From 511a553334f36112bc2fd85f7c991840df727b60 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Jan 2012 13:53:18 -0500 Subject: STM32F2 Flash support. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/flash.c | 39 +++++++ libmaple/stm32f2/include/series/flash.h | 196 ++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + 3 files changed, 236 insertions(+) create mode 100644 libmaple/stm32f2/flash.c create mode 100644 libmaple/stm32f2/include/series/flash.h diff --git a/libmaple/stm32f2/flash.c b/libmaple/stm32f2/flash.c new file mode 100644 index 0000000..d239940 --- /dev/null +++ b/libmaple/stm32f2/flash.c @@ -0,0 +1,39 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/flash.c + * @brief Flash management functions + */ + +#include + +/** + * @brief Turn on the instruction prefetcher. + */ +void flash_enable_prefetch(void) { + FLASH_BASE->ACR |= FLASH_ACR_PRFTEN; +} diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h new file mode 100644 index 0000000..73cbe14 --- /dev/null +++ b/libmaple/stm32f2/include/series/flash.h @@ -0,0 +1,196 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/flash.h + * @brief STM32F2 Flash header. + * + * Provides register map, base pointer, and register bit definitions + * for the Flash controller on the STM32F2 series, along with + * series-specific configuration values. + */ + +#ifndef _LIBMAPLE_STM32F2_FLASH_H_ +#define _LIBMAPLE_STM32F2_FLASH_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register map + */ + +/** Flash register map type */ +typedef struct flash_reg_map { + __io uint32 ACR; /**< Access control register */ + __io uint32 KEYR; /**< Key register */ + __io uint32 OPTKEYR; /**< Option key register */ + __io uint32 SR; /**< Status register */ + __io uint32 CR; /**< Control register */ + __io uint32 OPTCR; /**< Option control register */ +} flash_reg_map; + +/** Flash register map base pointer */ +#define FLASH_BASE ((struct flash_reg_map*)0x40023C00) + +/* + * Register bit definitions + */ + +/* Access control register */ + +#define FLASH_ACR_DCRST_BIT 12 +#define FLASH_ACR_ICRST_BIT 11 +#define FLASH_ACR_DCEN_BIT 10 +#define FLASH_ACR_ICEN_BIT 9 +#define FLASH_ACR_PRFTEN_BIT 8 + +#define FLASH_ACR_DCRST BIT(FLASH_ACR_DCRST_BIT) +#define FLASH_ACR_ICRST BIT(FLASH_ACR_ICRST_BIT) +#define FLASH_ACR_DCEN BIT(FLASH_ACR_DCEN_BIT) +#define FLASH_ACR_ICEN BIT(FLASH_ACR_ICEN_BIT) +#define FLASH_ACR_PRFTEN BIT(FLASH_ACR_PRFTEN_BIT) +#define FLASH_ACR_LATENCY 0x7 +#define FLASH_ACR_LATENCY_0WS 0x0 +#define FLASH_ACR_LATENCY_1WS 0x1 +#define FLASH_ACR_LATENCY_2WS 0x2 +#define FLASH_ACR_LATENCY_3WS 0x3 +#define FLASH_ACR_LATENCY_4WS 0x4 +#define FLASH_ACR_LATENCY_5WS 0x5 +#define FLASH_ACR_LATENCY_6WS 0x6 +#define FLASH_ACR_LATENCY_7WS 0x7 + +/* Key register */ + +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB + +/* Option key register */ + +#define FLASH_OPTKEYR_OPTKEY1 0x08192A3B +#define FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F + +/* Status register */ + +#define FLASH_SR_BSY_BIT 16 +#define FLASH_SR_PGSERR_BIT 7 +#define FLASH_SR_PGPERR_BIT 6 +#define FLASH_SR_PGAERR_BIT 5 +#define FLASH_SR_WRPERR_BIT 4 +#define FLASH_SR_OPERR_BIT 1 +#define FLASH_SR_EOP_BIT 0 + +#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) +#define FLASH_SR_PGSERR BIT(FLASH_SR_PGSERR_BIT) +#define FLASH_SR_PGPERR BIT(FLASH_SR_PGPERR_BIT) +#define FLASH_SR_PGAERR BIT(FLASH_SR_PGAERR_BIT) +#define FLASH_SR_WRPERR BIT(FLASH_SR_WRPERR_BIT) +#define FLASH_SR_OPERR BIT(FLASH_SR_OPERR_BIT) +#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) + +/* Control register */ + +#define FLASH_CR_LOCK_BIT 31 +#define FLASH_CR_ERRIE_BIT 25 +#define FLASH_CR_EOPIE_BIT 24 +#define FLASH_CR_STRT_BIT 16 +#define FLASH_CR_MER_BIT 2 +#define FLASH_CR_SER_BIT 1 +#define FLASH_CR_PG_BIT 0 + +#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) +#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) +#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) +#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) + +#define FLASH_CR_PSIZE (0x3 << 8) +#define FLASH_CR_PSIZE_MUL8 (0x0 << 8) +#define FLASH_CR_PSIZE_MUL16 (0x1 << 8) +#define FLASH_CR_PSIZE_MUL32 (0x2 << 8) +#define FLASH_CR_PSIZE_MUL64 (0x3 << 8) + +#define FLASH_CR_SNB (0xF << 3) +#define FLASH_CR_SNB_0 (0x0 << 3) +#define FLASH_CR_SNB_1 (0x1 << 3) +#define FLASH_CR_SNB_2 (0x2 << 3) +#define FLASH_CR_SNB_3 (0x3 << 3) +#define FLASH_CR_SNB_4 (0x4 << 3) +#define FLASH_CR_SNB_5 (0x5 << 3) +#define FLASH_CR_SNB_6 (0x6 << 3) +#define FLASH_CR_SNB_7 (0x7 << 3) +#define FLASH_CR_SNB_8 (0x8 << 3) +#define FLASH_CR_SNB_9 (0x9 << 3) +#define FLASH_CR_SNB_10 (0xA << 3) +#define FLASH_CR_SNB_11 (0xB << 3) + +#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) +#define FLASH_CR_SER BIT(FLASH_CR_SER_BIT) +#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) + +/* Option control register */ + +#define FLASH_OPTCR_NRST_STDBY_BIT 7 +#define FLASH_OPTCR_NRST_STOP_BIT 6 +#define FLASH_OPTCR_WDG_SW_BIT 5 +#define FLASH_OPTCR_OPTSTRT_BIT 1 +#define FLASH_OPTCR_OPTLOCK_BIT 0 + +#define FLASH_OPTCR_NWRP (0x3FF << 16) + +/* Excluded: The many level 1 values */ +#define FLASH_OPTCR_RDP (0xFF << 8) +#define FLASH_OPTCR_RDP_LEVEL0 (0xAA << 8) +#define FLASH_OPTCR_RDP_LEVEL2 (0xCC << 8) + +#define FLASH_OPTCR_USER (0x7 << 5) +#define FLASH_OPTCR_nRST_STDBY BIT(FLASH_OPTCR_nRST_STDBY_BIT) +#define FLASH_OPTCR_nRST_STOP BIT(FLASH_OPTCR_nRST_STOP_BIT) +#define FLASH_OPTCR_WDG_SW BIT(FLASH_OPTCR_WDG_SW_BIT) + +#define FLASH_OPTCR_BOR_LEV (0x3 << 2) +#define FLASH_OPTCR_BOR_LEVEL3 (0x0 << 2) +#define FLASH_OPTCR_BOR_LEVEL2 (0x1 << 2) +#define FLASH_OPTCR_BOR_LEVEL1 (0x2 << 2) +#define FLASH_OPTCR_BOR_OFF (0x3 << 2) + +#define FLASH_OPTCR_OPTSTRT BIT(FLASH_OPTCR_OPTSTRT_BIT) +#define FLASH_OPTCR_OPTLOCK BIT(FLASH_OPTCR_OPTLOCK_BIT) + +/* + * Series-specific configuration values + */ + +/* Note that this value depends on a 2.7V--3.6V supply voltage */ +#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_3 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 83ab043..0743f4f 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -11,6 +11,7 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We sSRCS_$(d) := isrs.S vector_table.S cSRCS_$(d) := rcc.c cSRCS_$(d) += gpio.c +cSRCS_$(d) += flash.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From b5a8e0386d5134839bf23e82110d2f1926201202 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 27 Jan 2012 21:01:59 -0500 Subject: Clean up Flash interface; add flash_enable_features(). Make a single function, flash_enable_features(), to control the access characteristics of Flash memory (i.e. to write to the non-latency bits of ACR). In so doing, make everybody pretend to allow instruction and data caching. On STM32F1, trying to turn these on simply has no effect. This allows unconditionally trying to turn them on, which will simplify users' lives. This has the ancillary benefit of making the stm32f2- and stm32f1-specific flash.c files unnecessary; delete these. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 32 +++++++++++++++++++++---- libmaple/stm32f1/flash.c | 41 --------------------------------- libmaple/stm32f1/include/series/flash.h | 8 +++++++ libmaple/stm32f1/rules.mk | 1 - libmaple/stm32f2/flash.c | 39 ------------------------------- libmaple/stm32f2/include/series/flash.h | 7 ++++++ libmaple/stm32f2/rules.mk | 1 - 7 files changed, 42 insertions(+), 87 deletions(-) delete mode 100644 libmaple/stm32f1/flash.c delete mode 100644 libmaple/stm32f2/flash.c diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index 97bfa26..bacbbda 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -47,18 +47,40 @@ extern "C"{ #define FLASH_WAIT_STATE_6 0x6 #define FLASH_WAIT_STATE_7 0x7 -/* The series header must define FLASH_SAFE_WAIT_STATES, the smallest - * number of wait states that it is safe to use when the MCU clock is - * at its fastest rate (not considering overclocking). */ +/* The series header must define: + * + * - FLASH_SAFE_WAIT_STATES, the smallest number of wait states that + * it is safe to use when SYSCLK is at its fastest documented rate + * and the MCU is powered at 3.3V (i.e. this doesn't consider + * overclocking or low voltage operation). + * + * - The following bit flags, for flash_enable_features(): + * + * -- FLASH_PREFETCH: prefetcher + * -- FLASH_ICACHE: instruction cache + * -- FLASH_DCACHE: data cache + * + * If the target doesn't provide a feature (e.g. instruction and + * data caches on the STM32F1), the flag should be set to some no-op + * value. This allows using these flags unconditionally, with the + * desired effect taking place on series that support them. + */ #include /* - * Setup routines + * Flash routines */ -void flash_enable_prefetch(void); void flash_set_latency(uint32 wait_states); +static inline void flash_enable_features(uint32 feature_flags) { + FLASH_BASE->ACR |= feature_flags; +} + +static inline void flash_enable_prefetch(void) { + flash_enable_features(FLASH_PREFETCH); +} + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/flash.c b/libmaple/stm32f1/flash.c deleted file mode 100644 index 73fc93f..0000000 --- a/libmaple/stm32f1/flash.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f1/flash.c - * @brief Flash management functions - */ - -#include -#include - -/** - * @brief Turn on the hardware prefetcher. - */ -void flash_enable_prefetch(void) { - *bb_perip(&FLASH_BASE->ACR, FLASH_ACR_PRFTBE_BIT) = 1; -} diff --git a/libmaple/stm32f1/include/series/flash.h b/libmaple/stm32f1/include/series/flash.h index efa608c..5603176 100644 --- a/libmaple/stm32f1/include/series/flash.h +++ b/libmaple/stm32f1/include/series/flash.h @@ -135,6 +135,14 @@ typedef struct flash_reg_map { #define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_2 +/* Flash memory features available via ACR */ +enum { + FLASH_PREFETCH = 0x10, + FLASH_HALF_CYCLE = 0x8, + FLASH_ICACHE = 0x0, /* Not available on STM32F1 */ + FLASH_DCACHE = 0x0, /* Not available on STM32F1 */ +}; + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 32b3a2c..4c7db60 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -12,7 +12,6 @@ sSRCS_$(d) := isrs_performance.S \ vector_table_performance.S cSRCS_$(d) := rcc.c -cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c cSRCS_$(d) += bkp.c diff --git a/libmaple/stm32f2/flash.c b/libmaple/stm32f2/flash.c deleted file mode 100644 index d239940..0000000 --- a/libmaple/stm32f2/flash.c +++ /dev/null @@ -1,39 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/stm32f2/flash.c - * @brief Flash management functions - */ - -#include - -/** - * @brief Turn on the instruction prefetcher. - */ -void flash_enable_prefetch(void) { - FLASH_BASE->ACR |= FLASH_ACR_PRFTEN; -} diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h index 73cbe14..f48eea3 100644 --- a/libmaple/stm32f2/include/series/flash.h +++ b/libmaple/stm32f2/include/series/flash.h @@ -189,6 +189,13 @@ typedef struct flash_reg_map { /* Note that this value depends on a 2.7V--3.6V supply voltage */ #define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_3 +/* Flash memory features available via ACR. */ +enum { + FLASH_PREFETCH = 0x100, + FLASH_ICACHE = 0x200, + FLASH_DCACHE = 0x400, +}; + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 0743f4f..83ab043 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -11,7 +11,6 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We sSRCS_$(d) := isrs.S vector_table.S cSRCS_$(d) := rcc.c cSRCS_$(d) += gpio.c -cSRCS_$(d) += flash.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 4dc4d99fdddffdeb3e14e722e935c76c74ff9a15 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 27 Jan 2012 21:31:30 -0500 Subject: RCC: Clean up and sanitize interfaces across F1, F2 series. Additions: - rcc_switch_sysclk(): For changing the clock used as SYSCLK's source. - enum rcc_clk: One for each system and secondary clock source (e.g. HSE, LSE). These are defined on a per-series basis in each of the . - rcc_turn_on_clk(), rcc_turn_off_clk(), rcc_is_clk_ready(): For turning on system and secondary clock sources, and checking whether or not they're ready. Uses enum rcc_clk. Removals: - rcc_clk_init(): There's no way to port this to F2. Move it to the F1 header. This also means we can remove the empty implementation and enum rcc_pll_multiplier from the F2 RCC header, where it doesn't make any sense. Also fix up some includes, and rewrite rcc_clk_init() in terms of the new clock source management functions. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 59 +++++++++++------ libmaple/rcc.c | 116 ++++++++++++++++++++++++++++++++++ libmaple/stm32f1/include/series/rcc.h | 31 ++++++++- libmaple/stm32f1/rcc.c | 26 +++----- libmaple/stm32f2/include/series/rcc.h | 35 ++++++++-- libmaple/stm32f2/rcc.c | 6 -- 6 files changed, 224 insertions(+), 49 deletions(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 08f7c7e..842800b 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -37,42 +37,63 @@ extern "C"{ #endif #include + +/* Put the SYSCLK sources before the series header is included, as it + * might need them. */ +/** + * @brief SYSCLK sources + * @see rcc_clk_init() + */ +typedef enum rcc_sysclk_src { + RCC_CLKSRC_HSI = 0x0, + RCC_CLKSRC_HSE = 0x1, + RCC_CLKSRC_PLL = 0x2, +} rcc_sysclk_src; + #include /* Note: Beyond the usual (registers, etc.), it's up to the series * header to define the following types: * - * - rcc_pllsrc: For each PLL source (passed to rcc_clk_init()). + * - enum rcc_clk: Available system and secondary clock sources, + * e.g. RCC_CLK_HSE, RCC_CLK_PLL, RCC_CLK_LSE. + * + * Note that the inclusion of secondary clock sources (like LSI and + * LSE) makes enum rcc_clk different from the SYSCLK sources, which + * are defined in this header as enum rcc_sysclk_src. * - * - rcc_pll_multiplier: If appropriate (TODO verify this makes sense). + * IMPORTANT NOTE TO IMPLEMENTORS: If you are adding support for a + * new STM32 series, see the comment near rcc_clk_reg() in + * libmaple/rcc.c for information on how to choose these values so + * that rcc_turn_on_clk() etc. will work on your series. * - * - rcc_clk_id: For each available peripheral. These are widely used + * - enum rcc_clk_id: For each available peripheral. These are widely used * as unique IDs (TODO extricate from RCC?). Peripherals which are - * common across families should use the same token for their + * common across STM32 series should use the same token for their * rcc_clk_id in each series header. * - * - rcc_clk_domain: For each clock domain (returned by rcc_dev_clk()). + * - enum rcc_clk_domain: For each clock domain. This is returned by + * rcc_dev_clk(). For instance, each AHB and APB is a clock domain. * - * - rcc_prescaler (and a suitable set of dividers): for rcc_set_prescaler(). + * - enum rcc_prescaler: And a suitable set of dividers for + * rcc_set_prescaler(). */ -/** - * SYSCLK sources - * @see rcc_clk_init() - */ -typedef enum rcc_sysclk_src { - RCC_CLKSRC_HSI = 0x0, - RCC_CLKSRC_HSE = 0x1, - RCC_CLKSRC_PLL = 0x2, -} rcc_sysclk_src; +/* Clock prescaler management. */ +void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); + +/* SYSCLK. */ +void rcc_switch_sysclk(rcc_sysclk_src sysclk_src); -void rcc_clk_init(rcc_sysclk_src sysclk_src, - rcc_pllsrc pll_src, - rcc_pll_multiplier pll_mul); +/* System and secondary clock sources. */ +void rcc_turn_on_clk(rcc_clk clock); +void rcc_turn_off_clk(rcc_clk clock); +int rcc_is_clk_ready(rcc_clk clock); + +/* Peripheral clock lines and clock domains. */ void rcc_clk_enable(rcc_clk_id device); void rcc_reset_dev(rcc_clk_id device); rcc_clk_domain rcc_dev_clk(rcc_clk_id device); -void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); #ifdef __cplusplus } // extern "C" diff --git a/libmaple/rcc.c b/libmaple/rcc.c index d6ed2d6..d42bbf1 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -42,3 +42,119 @@ rcc_clk_domain rcc_dev_clk(rcc_clk_id id) { return rcc_dev_table[id].clk_domain; } + +/** + * @brief Switch the clock used as the source of the system clock. + * + * After switching the source, this function blocks until the new + * clock source is in use. + * + * @param sysclk_src New system clock source. + * @see rcc_sysclk_src + */ +void rcc_switch_sysclk(rcc_sysclk_src sysclk_src) { + uint32 cfgr = RCC_BASE->CFGR; + cfgr &= ~RCC_CFGR_SW; + cfgr |= sysclk_src; + + /* Switch SYSCLK source. */ + RCC_BASE->CFGR = cfgr; + + /* Wait for new source to come into use. */ + while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != (sysclk_src << 2)) + ; +} + +/* + * Turning clocks off and on, querying their status. + */ + +/* IMPORTANT NOTE FOR IMPLEMENTORS: + * + * libmaple assumes that enum rcc_clk enumerators are two-byte + * values, stored in a uint16, in the following way: + * + * - The high-order byte is the byte offset (from RCC_BASE) of the register + * to touch when turning on or off the given clock. + * + * - The low-order byte is the bit in that register that turns the + * clock on or off. + * + * Example for STM32F1: Turning on the high-speed external clock (HSE) + * involves setting HSEON, bit 16, of RCC_CR. The high-order byte is + * then offsetof(struct rcc_reg_map, CR) = 0, and the low-order byte + * is 16. + * + * The corresponding value of RCC_CLK_HSE is thus (0 << 8) | 16 = 16. + * + * On all known STM32 series, this encoding has the property that + * adding one to the low byte also gives the bit to check to determine + * if the clock is ready. For example, on STM32F1, RCC_CR_HSERDY is + * bit 17. If that's not the case on your ser ies, rcc_is_clk_ready() + * won't work for you. */ + +/* Returns the RCC register which controls the clock source. */ +static inline __io uint32* rcc_clk_reg(rcc_clk clock) { + return (__io uint32*)((__io uint8*)RCC_BASE + (clock >> 8)); +} + +/* Returns a mask in rcc_clk_reg(clock) to be used for turning the + * clock on and off */ +static inline uint32 rcc_clk_on_mask(rcc_clk clock) { + return 1 << (clock & 0xFF); +} + +/* Returns a mask in rcc_clk_reg(clock) to be used when checking the + * readiness of the clock. */ +static inline uint32 rcc_clk_ready_mask(rcc_clk clock) { + return rcc_clk_on_mask(clock) << 1; +} + +/** + * @brief Turn on a clock source. + * + * After this routine exists, callers should ensure that the clock + * source is ready by waiting until rcc_is_clk_ready(clock) returns + * true. + * + * @param clock Clock to turn on. + * @see rcc_turn_off_clk() + * @see rcc_is_clk_ready() + */ +void rcc_turn_on_clk(rcc_clk clock) { + *rcc_clk_reg(clock) |= rcc_clk_on_mask(clock); +} + +/** + * @brief Turn off a clock source. + * + * In certain configurations, certain clock sources cannot be safely + * turned off. (For example, the main PLL on STM32F1 devices cannot be + * turned off if it has been selected as the SYSCLK source). Consult + * the reference material for your MCU to ensure it is safe to call + * this function. + * + * @param clock Clock to turn off. + * @see rcc_turn_on_clk() + * @see rcc_is_clk_ready() + */ +void rcc_turn_off_clk(rcc_clk clock) { + *rcc_clk_reg(clock) &= ~rcc_clk_on_mask(clock); +} + +/** + * @brief Check if a clock source is ready. + * + * In general, it is not safe to rely on a clock source unless this + * function returns nonzero. Also note that this function may return + * nonzero for a short period of time after a clock has been turned + * off. Consult the reference material for your MCU for more details. + * + * @param clock Clock whose readiness to check for. + * @return Nonzero if the clock is ready, zero otherwise. + * @see rcc_turn_on_clk() + * @see rcc_turn_off_clk() + */ +int rcc_is_clk_ready(rcc_clk clock) { + return (int)(*rcc_clk_reg(clock) & rcc_clk_ready_mask(clock)); +} diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index 261dc5d..474aaf7 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -37,6 +37,8 @@ extern "C"{ #endif +#include + /* * Register map */ @@ -383,7 +385,7 @@ typedef struct rcc_reg_map { #define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) /* - * Other types + * libmaple-mandated enumeration types. */ /** @@ -546,6 +548,33 @@ typedef enum rcc_ahb_divider { RCC_AHB_SYSCLK_DIV_512 = 0xF << 4, } rcc_ahb_divider; +/** + * @brief Available clock sources. + */ +typedef enum rcc_clk { + RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLON_BIT), /**< Main PLL, clocked by + HSI or HSE. */ + RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSEON_BIT), /**< High speed external. */ + RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSION_BIT), /**< High speed internal. */ + RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) | + RCC_BDCR_LSEON_BIT), /**< Low-speed external + * (32.768 KHz). */ + RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) | + RCC_CSR_LSION_BIT), /**< Low-speed internal + * (approximately 32 KHz). */ +} rcc_clk; + +/* + * Series-specific functionality. + */ + +void rcc_clk_init(rcc_sysclk_src sysclk_src, + rcc_pllsrc pll_src, + rcc_pll_multiplier pll_mul); + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index 2b78e89..2d31482 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -105,9 +105,6 @@ const struct rcc_dev_info rcc_dev_table[] = { void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul) { - uint32 cfgr = 0; - uint32 cr; - /* Assume that we're going to clock the chip off the PLL, fed by * the HSE */ ASSERT(sysclk_src == RCC_CLKSRC_PLL && @@ -115,25 +112,18 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src, RCC_BASE->CFGR = pll_src | pll_mul; - /* Turn on the HSE */ - cr = RCC_BASE->CR; - cr |= RCC_CR_HSEON; - RCC_BASE->CR = cr; - while (!(RCC_BASE->CR & RCC_CR_HSERDY)) + /* Turn on, and wait for, HSE. */ + rcc_turn_on_clk(RCC_CLK_HSE); + while (!rcc_is_clk_ready(RCC_CLK_HSE)) ; - /* Now the PLL */ - cr |= RCC_CR_PLLON; - RCC_BASE->CR = cr; - while (!(RCC_BASE->CR & RCC_CR_PLLRDY)) + /* Do the same for the main PLL. */ + rcc_turn_on_clk(RCC_CLK_PLL); + while(!rcc_is_clk_ready(RCC_CLK_PLL)) ; - /* Finally, let's switch over to the PLL */ - cfgr &= ~RCC_CFGR_SW; - cfgr |= RCC_CFGR_SW_PLL; - RCC_BASE->CFGR = cfgr; - while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) - ; + /* Finally, switch over to the PLL. */ + rcc_switch_sysclk(RCC_CLKSRC_PLL); } /** diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 1557f2d..89fed1d 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -722,7 +722,6 @@ typedef struct rcc_reg_map { /* Spread spectrum clock generation register */ - #define RCC_SSCGR_SSCGEN_BIT 31 #define RCC_SSCGR_SPREADSEL_BIT 30 @@ -742,6 +741,10 @@ typedef struct rcc_reg_map { * Other types */ +/* + * Clock sources, domains, and peripheral clock IDs. + */ + /** * @brief Identifies bus and clock line for a peripheral or peripheral * clock. @@ -819,10 +822,6 @@ typedef enum rcc_pllsrc { RCC_PLLSRC_HSE = RCC_PLLCFGR_PLLSRC, } rcc_pllsrc; -typedef enum rcc_pll_multiplier { /* TODO -- does this make sense anymore? */ - RCC_PLLMUL_XXX, -} rcc_pll_multiplier; - /** * @brief Peripheral clock domains. */ @@ -834,6 +833,10 @@ typedef enum rcc_clk_domain { RCC_AHB3, } rcc_clk_domain; +/* + * Prescalers and dividers. + */ + /** * @brief Prescaler identifiers. */ @@ -912,6 +915,28 @@ typedef enum rcc_ahb_divider { RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512, } rcc_ahb_divider; +/** + * @brief Available clock sources. + */ +typedef enum rcc_clk { + RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL + for I2S. */ + RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLON_BIT), /**< Main PLL, clocked by + HSI or HSE. */ + RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSEON_BIT), /**< High speed external. */ + RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSION_BIT), /**< High speed internal. */ + RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) | + RCC_BDCR_LSEON_BIT), /**< Low-speed external + * (32.768 KHz). */ + RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) | + RCC_CSR_LSION_BIT), /**< Low-speed internal + * (approximately 32 KHz). */ +} rcc_clk; + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c index 268a9b1..7bc220d 100644 --- a/libmaple/stm32f2/rcc.c +++ b/libmaple/stm32f2/rcc.c @@ -110,12 +110,6 @@ const struct rcc_dev_info rcc_dev_table[] = { [RCC_TIM1] = DEV_ENTRY(APB2, TIM1), }; -void rcc_clk_init(rcc_sysclk_src sysclk_src, - rcc_pllsrc pll_src, - rcc_pll_multiplier pll_mul) { - ASSERT(0); /* FIXME */ -} - /** * @brief Turn on the clock line on a peripheral * @param id Clock ID of the peripheral to turn on. -- cgit v1.2.3 From 1251c6e396dffd218d85db13be211ff34365279e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 2 Feb 2012 06:53:07 -0500 Subject: libmaple_types.h: Add __deprecated. This is a define for __attribute__((deprecated)). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/libmaple_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h index 19a5101..25ad222 100644 --- a/libmaple/include/libmaple/libmaple_types.h +++ b/libmaple/include/libmaple/libmaple_types.h @@ -52,6 +52,7 @@ typedef void (*voidFuncPtr)(void); #define __io volatile #define __attr_flash __attribute__((section (".USER_FLASH"))) #define __packed __attribute__((__packed__)) +#define __deprecated __attribute__((__deprecated__)) #ifndef NULL #define NULL 0 -- cgit v1.2.3 From 63d6d83c24bddc451a8c7f2ecc44d33c63553652 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 2 Feb 2012 06:53:44 -0500 Subject: libmaple/rcc.h: Add rcc_enable_css(), rcc_disable_css(). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 842800b..4a22b5e 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -91,10 +91,27 @@ void rcc_turn_off_clk(rcc_clk clock); int rcc_is_clk_ready(rcc_clk clock); /* Peripheral clock lines and clock domains. */ + void rcc_clk_enable(rcc_clk_id device); void rcc_reset_dev(rcc_clk_id device); rcc_clk_domain rcc_dev_clk(rcc_clk_id device); +/* Clock security system */ + +/** + * @brief Enable the clock security system (CSS). + */ +static inline void rcc_enable_css() { + RCC_BASE->CR |= RCC_CR_CSSON; +} + +/** + * @brief Disable the clock security system (CSS). + */ +static inline void rcc_disable_css() { + RCC_BASE->CR &= ~RCC_CR_CSSON; +} + #ifdef __cplusplus } // extern "C" #endif -- cgit v1.2.3 From fd03ab16e37437d99c76b0335305e0205fa5efbb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 2 Feb 2012 06:54:39 -0500 Subject: stm32f1/rcc.h: Deprecate rcc_clk_init(). We're going to replace this with a more portable mechanism. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/rcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index 474aaf7..68a79d4 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -571,6 +571,7 @@ typedef enum rcc_clk { * Series-specific functionality. */ +__deprecated void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul); -- cgit v1.2.3 From c122d16c71d2aa04baa8b4b5a5df7faed93240fb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 2 Feb 2012 07:01:41 -0500 Subject: RCC: Add new mechanism for configuring the main PLL. The new style for configuring the PLL is to initialize a (series-specific) struct rcc_pll_cfg, and pass a pointer to it to rcc_configure_pll(). After that's done, you can use rcc_turn_on_clk(RCC_CLK_PLL) to turn on the main PLL, and busy-wait until rcc_is_clk_ready(RCC_CLK_PLL) is true to make sure the new configuration took effect. - libmaple/rcc.h: -- Add struct rcc_pll_cfg, which specifies a PLL configuration. This specifies a PLL source and a void pointer to series-specific PLL configuration data. -- Add rcc_configure_pll(), which takes a pointer to struct rcc_pll_cfg, and configures the main PLL. It's up to each series to define this function. - stm32f1/rcc.h: Add struct stm32f1_rcc_pll_data, to store F1-specific PLL configuration state. - stm32f1/rcc.c: Add an implementation for rcc_configure_pll(). - stm32f2/rcc.h: Add struct stm32f2_rcc_pll_data, to store F2-specific PLL configuration data. - stm32f2/rcc.c: Add an implementation for rcc_configure_pll(). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 18 ++++++++++ libmaple/stm32f1/include/series/rcc.h | 11 ++++++ libmaple/stm32f1/rcc.c | 19 ++++++++++ libmaple/stm32f2/include/series/rcc.h | 66 +++++++++++++++++++++++------------ libmaple/stm32f2/rcc.c | 34 ++++++++++++++++++ 5 files changed, 126 insertions(+), 22 deletions(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 4a22b5e..2c8776b 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -80,12 +80,30 @@ typedef enum rcc_sysclk_src { */ /* Clock prescaler management. */ + void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); /* SYSCLK. */ + void rcc_switch_sysclk(rcc_sysclk_src sysclk_src); +/* PLL configuration */ + +/** + * @brief Specifies a configuration for the main PLL. + */ +typedef struct rcc_pll_cfg { + rcc_pllsrc pllsrc; /**< PLL source */ + void *data; /**< Series-specific configuration + * data. See the for your + * MCU for more information on what to put + * here. */ +} rcc_pll_cfg; + +void rcc_configure_pll(rcc_pll_cfg *pll_cfg); + /* System and secondary clock sources. */ + void rcc_turn_on_clk(rcc_clk clock); void rcc_turn_off_clk(rcc_clk clock); int rcc_is_clk_ready(rcc_clk clock); diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index 68a79d4..b72c5cf 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -576,6 +576,17 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul); +/** + * @brief STM32F1-specific PLL configuration values. + * + * Use this as the "data" field in a struct rcc_pll_cfg. + * + * @see struct rcc_pll_cfg. + */ +typedef struct stm32f1_rcc_pll_data { + rcc_pll_multiplier pll_mul; /**< PLL multiplication factor. */ +} stm32f1_rcc_pll_data; + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index 2d31482..a9c9c3a 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -126,6 +126,25 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_switch_sysclk(RCC_CLKSRC_PLL); } +/** + * @brief Configure the main PLL. + * + * You may only call this function while the PLL is disabled. + * + * @param pll_cfg Desired PLL configuration. The data field must point + * to a valid struct stm32f1_rcc_pll_data. + */ +void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { + stm32f1_rcc_pll_data *data = pll_cfg->data; + rcc_pll_multiplier pll_mul = data->pll_mul; + uint32 cfgr; + + cfgr = RCC_BASE->CFGR; + cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL); + cfgr |= pll_cfg->pllsrc | pll_mul; + RCC_BASE->CFGR = cfgr; +} + /** * @brief Turn on the clock line on a peripheral * @param id Clock ID of the peripheral to turn on. diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 89fed1d..019bb3e 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -738,12 +738,30 @@ typedef struct rcc_reg_map { #define RCC_PLLI2SCFGR_PLLI2SN (0x1FF << 6) /* - * Other types + * Clock sources, domains, and peripheral clock IDs. */ -/* - * Clock sources, domains, and peripheral clock IDs. +/** + * @brief Available clock sources. */ +typedef enum rcc_clk { + RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL + for I2S. */ + RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_PLLON_BIT), /**< Main PLL, clocked by + HSI or HSE. */ + RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSEON_BIT), /**< High speed external. */ + RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | + RCC_CR_HSION_BIT), /**< High speed internal. */ + RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) | + RCC_BDCR_LSEON_BIT), /**< Low-speed external + * (32.768 KHz). */ + RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) | + RCC_CSR_LSION_BIT), /**< Low-speed internal + * (approximately 32 KHz). */ +} rcc_clk; /** * @brief Identifies bus and clock line for a peripheral or peripheral @@ -915,27 +933,31 @@ typedef enum rcc_ahb_divider { RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512, } rcc_ahb_divider; +/* + * Series-specific PLL configuration. + */ + /** - * @brief Available clock sources. + * @brief STM32F2-specific PLL configuration values. + * + * Use this as the "data" field in a struct rcc_pll_cfg. + * + * @see struct rcc_pll_cfg. */ -typedef enum rcc_clk { - RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL - for I2S. */ - RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_PLLON_BIT), /**< Main PLL, clocked by - HSI or HSE. */ - RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_HSEON_BIT), /**< High speed external. */ - RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | - RCC_CR_HSION_BIT), /**< High speed internal. */ - RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) | - RCC_BDCR_LSEON_BIT), /**< Low-speed external - * (32.768 KHz). */ - RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) | - RCC_CSR_LSION_BIT), /**< Low-speed internal - * (approximately 32 KHz). */ -} rcc_clk; +typedef struct stm32f2_rcc_pll_data { + uint8 pllq; /**< + * @brief PLLQ value. + * Allowed values: 4, 5, ..., 15. */ + uint8 pllp; /**< + * @brief PLLP value. + * Allowed values: 2, 4, 6, 8. */ + uint16 plln; /**< + * @brief PLLN value. + * Allowed values: 192, 193, ..., 432. */ + uint8 pllm; /**< + * @brief PLLM value. + * Allowed values: 2, 3, ..., 63. */ +} stm32f2_rcc_pll_data; #ifdef __cplusplus } diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c index 7bc220d..b94f2e6 100644 --- a/libmaple/stm32f2/rcc.c +++ b/libmaple/stm32f2/rcc.c @@ -160,3 +160,37 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { }; rcc_do_set_prescaler(masks, prescaler, divider); } + +/** + * @brief Configure the main PLL. + * + * You may only call this function while the PLL is disabled. + * + * @param pll_cfg Desired PLL configuration. The data field must point + * to a valid struct stm32f2_rcc_pll_data. + */ +void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { + stm32f2_rcc_pll_data *data = pll_cfg->data; + uint32 pllcfgr; + + /* Sanity-check all the parameters */ + ASSERT_FAULT((data->pllq >= 4) && (data->pllq <= 15)); + ASSERT_FAULT((data->pllp >= 2) && (data->pllp <= 8)); + ASSERT_FAULT(!(data->pllp & 1)); + ASSERT_FAULT((data->plln >= 192) && (data->plln <= 432)); + ASSERT_FAULT((data->pllm >= 2) && (data->pllm <= 63)); + + /* Update RCC_PLLCFGR to reflect new values. */ + pllcfgr = RCC_BASE->PLLCFGR; + pllcfgr &= ~(RCC_PLLCFGR_PLLQ | + RCC_PLLCFGR_PLLP | + RCC_PLLCFGR_PLLN | + RCC_PLLCFGR_PLLM | + RCC_PLLCFGR_PLLSRC); + pllcfgr |= (pll_cfg->pllsrc | + (data->pllq << 24) | + (((data->pllp >> 1) - 1) << 16) | + (data->plln << 6) | + data->pllm); + RCC_BASE->PLLCFGR = pllcfgr; +} -- cgit v1.2.3 From 21468a69ca2e7ff9a5c7ffc03c608a24f1412d64 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 20 Mar 2012 17:44:34 -0400 Subject: [FIXME] Resurrect boards.cpp for F2 and F1. FIXME: - F1 support currently appears to be failing in start_c.c, for some unknown reason. This will need to get sorted out later. Add a new wirish namespace, and a sub-namespace wirish::priv::. Put a bunch of board setup routines in this namespace, and declare them in new wirish/boards_private.h. boards.cpp uses this to perform initialization tasks in a portable way, with two new boards_setup.cpp files under wirish/stm32f1 and wirish/stm32f2 handling the series-specific details. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 167 ++++++++++++++++++---------------------- wirish/boards_private.h | 59 ++++++++++++++ wirish/include/wirish/boards.h | 5 -- wirish/rules.mk | 22 ++++-- wirish/stm32f1/boards_setup.cpp | 141 +++++++++++++++++++++++++++++++++ wirish/stm32f2/boards_setup.cpp | 75 ++++++++++++++++++ 6 files changed, 363 insertions(+), 106 deletions(-) create mode 100644 wirish/boards_private.h create mode 100644 wirish/stm32f1/boards_setup.cpp create mode 100644 wirish/stm32f2/boards_setup.cpp diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 5d5ecb5..7d783db 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -25,49 +25,55 @@ *****************************************************************************/ /** - * @brief Generic board initialization routines. + * @file boards.cpp + * @brief Generic board routines. * * This file is mostly interesting for the init() function, which * configures Flash, the core sytem clocks, and a variety of other * available peripherals on the board so the rest of Wirish doesn't * have to turn things on before using them. * - * Prior to returning, init() calls boardInit(), which allows boards - * to perform any initialization they need to. + * How init() does this is chip-specific. See the chip-specific pieces + * of Wirish (under e.g. wirish/stm32f1/, wirish/stmf32f2) for + * details. * - * Specifically how init() works varies across boards and MCUs. + * Finally, prior to returning, init() calls boardInit(), which allows + * boards to perform any initialization they need to. This file + * includes a weak no-op definition of boardInit(), so boards that + * don't need any special initialization don't have to define their + * own. */ #include - #include -#include #include #include -#include -#include -#include -#include +#include "boards_private.h" + +static void setup_flash(void); +static void setup_clocks(void); +static void setup_nvic(void); -static void setupFlash(void); -static void setupClocks(void); -static void setupNVIC(void); -static void setupADC(void); -static void setupTimers(void); +/* + * Exported functions + */ void init(void) { - setupFlash(); - setupClocks(); - setupNVIC(); + setup_flash(); + setup_clocks(); + setup_nvic(); systick_init(SYSTICK_RELOAD_VAL); - gpio_init_all(); - afio_init(); - setupADC(); - setupTimers(); - usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); + wirish::priv::board_setup_gpio(); + wirish::priv::board_setup_adc(); + wirish::priv::board_setup_timers(); + wirish::priv::board_setup_usb(); boardInit(); } +/* Provide a default boardInit(). */ +__attribute__((weak)) void boardInit(void) { +} + /* You could farm this out to the files in boards/ if e.g. it takes * too long to test on Maple Native (all those FSMC pins...). */ bool boardUsesPin(uint8 pin) { @@ -79,24 +85,56 @@ bool boardUsesPin(uint8 pin) { return false; } -static void setupFlash(void) { - flash_enable_prefetch(); +/* + * Auxiliary routines + */ + +static void setup_flash(void) { + // Turn on as many Flash "go faster" features as + // possible. flash_enable_features() just ignores any flags it + // can't support. + flash_enable_features(FLASH_PREFETCH | FLASH_ICACHE | FLASH_DCACHE); + // Configure the wait states, assuming we're operating at "close + // enough" to 3.3V. flash_set_latency(FLASH_SAFE_WAIT_STATES); } -/* - * Clock setup. Note that some of this only takes effect if we're - * running bare metal and the bootloader hasn't done it for us - * already. - */ -static void setupClocks() { - rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); - rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); - rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); - rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); +static void setup_clocks(void) { + // Turn on HSI. We'll switch to and run off of this while we're + // setting up the main PLL. + rcc_turn_on_clk(RCC_CLK_HSI); + + // Turn off and reset the clock subsystems we'll be using, as well + // as the clock security subsystem (CSS). Note that resetting CFGR + // to its default value of 0 implies a switch to HSI for SYSCLK. + RCC_BASE->CFGR = 0x00000000; + rcc_disable_css(); + rcc_turn_off_clk(RCC_CLK_PLL); + rcc_turn_off_clk(RCC_CLK_HSE); + wirish::priv::board_reset_pll(); + // Clear clock readiness interrupt flags and turn off clock + // readiness interrupts. + RCC_BASE->CIR = 0x00000000; + + // Enable HSE, and wait until it's ready. + rcc_turn_on_clk(RCC_CLK_HSE); + while (!rcc_is_clk_ready(RCC_CLK_HSE)) + ; + + // Configure AHBx, APBx, etc. prescalers and the main PLL. + wirish::priv::board_setup_clock_prescalers(); + rcc_configure_pll(&wirish::priv::board_pll_cfg); + + // Enable the PLL, and wait until it's ready. + rcc_turn_on_clk(RCC_CLK_PLL); + while(!rcc_is_clk_ready(RCC_CLK_PLL)) + ; + + // Finally, switch to the now-ready PLL as the main clock source. + rcc_switch_sysclk(RCC_CLKSRC_PLL); } -static void setupNVIC() { +static void setup_nvic(void) { #ifdef VECT_TAB_FLASH nvic_init(USER_ADDR_ROM, 0); #elif defined VECT_TAB_RAM @@ -107,60 +145,3 @@ static void setupNVIC() { #error "You must select a base address for the vector table." #endif } - -static void adcDefaultConfig(const adc_dev* dev); - -static void setupADC() { - rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); - adc_foreach(adcDefaultConfig); -} - -static void timerDefaultConfig(timer_dev*); - -static void setupTimers() { - timer_foreach(timerDefaultConfig); -} - -static void adcDefaultConfig(const adc_dev *dev) { - adc_init(dev); - - adc_set_extsel(dev, ADC_SWSTART); - adc_set_exttrig(dev, true); - - adc_enable(dev); - adc_calibrate(dev); - adc_set_sample_rate(dev, ADC_SMPR_55_5); -} - -static void timerDefaultConfig(timer_dev *dev) { - timer_adv_reg_map *regs = (dev->regs).adv; - const uint16 full_overflow = 0xFFFF; - const uint16 half_duty = 0x8FFF; - - timer_init(dev); - timer_pause(dev); - - regs->CR1 = TIMER_CR1_ARPE; - regs->PSC = 1; - regs->SR = 0; - regs->DIER = 0; - regs->EGR = TIMER_EGR_UG; - - switch (dev->type) { - case TIMER_ADVANCED: - regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; - // fall-through - case TIMER_GENERAL: - timer_set_reload(dev, full_overflow); - - for (int channel = 1; channel <= 4; channel++) { - timer_set_compare(dev, channel, half_duty); - timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); - } - // fall-through - case TIMER_BASIC: - break; - } - - timer_resume(dev); -} diff --git a/wirish/boards_private.h b/wirish/boards_private.h new file mode 100644 index 0000000..a4101c9 --- /dev/null +++ b/wirish/boards_private.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards_private.h + * @author Marti Bolivar + * @brief Private board support header. + */ + +#ifndef _WIRISH_BOARDS_PRIVATE_H_ +#define _WIRISH_BOARDS_PRIVATE_H_ + +namespace wirish { + namespace priv { + + /* + * Chip-specific initialization data + */ + + extern rcc_pll_cfg board_pll_cfg; + + /* + * Chip-specific initialization routines and helper functions. + */ + + void board_reset_pll(void); + void board_setup_clock_prescalers(void); + void board_setup_gpio(void); + void board_setup_adc(void); + void board_setup_timers(void); + void board_setup_usb(void); + + } +} + +#endif diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index e708f79..c762542 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -29,11 +29,6 @@ * @author Bryan Newbold , * Marti Bolivar * @brief Board-specific pin information. - * - * To add a new board type, add a new pair of files to - * /wirish/boards/, update the section below with a new "BOARD" type, - * and update /wirish/rules.mk to include your boards/your_board.cpp - * file in the top-level Makefile build. */ #ifndef _WIRISH_BOARDS_H_ diff --git a/wirish/rules.mk b/wirish/rules.mk index c72e60f..17c4d05 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -4,22 +4,26 @@ dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) -# Board config -- TODO allow user override -# WIRISH_BOARD_PATH := boards/$(BOARD) -# BUILDDIRS += $(BUILD_PATH)/$(d)/$(WIRISH_BOARD_PATH) +# Add board directory and MCU-specific directory to BUILDDIRS. These +# are in subdirectories, but they're logically part of the Wirish +# submodule. +WIRISH_BOARD_PATH := boards/$(BOARD) +BUILDDIRS += $(BUILD_PATH)/$(d)/$(WIRISH_BOARD_PATH) +BUILDDIRS += $(BUILD_PATH)/$(d)/$(MCU_SERIES) -# WIRISH_INCLUDES := -I$(d)/include -I$(d)/$(WIRISH_BOARD_PATH)/include +# Safe includes for Wirish. +WIRISH_INCLUDES := -I$(d)/include -I$(d)/$(WIRISH_BOARD_PATH)/include -# Local flags -CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) +# Local flags. Add -I$(d) to allow for private includes. +CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) $(WIRISH_INCLUDES) -I$(d) # Local rules and targets - sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c +cppSRCS_$(d) := boards.cpp +# TODO: test these on F2 and put them back in: # cppSRCS_$(d) := wirish_math.cpp \ # Print.cpp \ -# boards.cpp \ # HardwareSerial.cpp \ # HardwareSPI.cpp \ # HardwareTimer.cpp \ @@ -31,7 +35,9 @@ cSRCS_$(d) := start_c.c # pwm.cpp \ # ext_interrupts.cpp \ # wirish_digital.cpp +# TODO: Put this back in once we've got the necessary libmaple support back. # cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp +cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp new file mode 100644 index 0000000..4ee292a --- /dev/null +++ b/wirish/stm32f1/boards_setup.cpp @@ -0,0 +1,141 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +/** + * @file wirish/stm32f1/boards_setup.cpp + * @author Marti Bolivar + * @brief STM32F1 chip setup. + */ + +#include +#include +#include +#include +#include + +#include + +/* FIXME: Reintroduce all "#if 0"'ed blocks once libmaple provides + * these definitions again. */ + +namespace wirish { + namespace priv { + + static stm32f1_rcc_pll_data pll_data = {RCC_PLLMUL_9}; + rcc_pll_cfg board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + +#if 0 + static void config_adc(const adc_dev* dev); + static void config_timer(timer_dev*); +#endif + + void board_reset_pll(void) { + // TODO + } + + void board_setup_clock_prescalers(void) { + rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); + rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); + rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); + } + + void board_setup_gpio(void) { + gpio_init_all(); + // Initialize AFIO here, too, so peripheral remaps and external + // interrupts work out of the box. + afio_init(); + } + + void board_setup_adc(void) { +#if 0 + rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); + adc_foreach(config_adc); +#endif + } + + void board_setup_timers(void) { +#if 0 + timer_foreach(config_timer); +#endif + } + + void board_setup_usb(void) { +#if 0 + usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); +#endif + } + + /* + * Auxiliary routines + */ + +#if 0 + static void config_adc(const adc_dev *dev) { + adc_init(dev); + + adc_set_extsel(dev, ADC_SWSTART); + adc_set_exttrig(dev, true); + + adc_enable(dev); + adc_calibrate(dev); + adc_set_sample_rate(dev, ADC_SMPR_55_5); + } + + static void config_timer(timer_dev *dev) { + timer_adv_reg_map *regs = (dev->regs).adv; + const uint16 full_overflow = 0xFFFF; + const uint16 half_duty = 0x8FFF; + + timer_init(dev); + timer_pause(dev); + + regs->CR1 = TIMER_CR1_ARPE; + regs->PSC = 1; + regs->SR = 0; + regs->DIER = 0; + regs->EGR = TIMER_EGR_UG; + + switch (dev->type) { + case TIMER_ADVANCED: + regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; + // fall-through + case TIMER_GENERAL: + timer_set_reload(dev, full_overflow); + + for (int channel = 1; channel <= 4; channel++) { + timer_set_compare(dev, channel, half_duty); + timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); + } + // fall-through + case TIMER_BASIC: + break; + } + + timer_resume(dev); + } +#endif + } +} diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp new file mode 100644 index 0000000..b3c690c --- /dev/null +++ b/wirish/stm32f2/boards_setup.cpp @@ -0,0 +1,75 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/stm32f2/boards_setup.cpp + * @author Marti Bolivar + * @brief STM32F2 chip setup. + */ + +#include +#include + +#define PLL_Q 5 +#define PLL_P 2 +#define PLL_N 240 +#define PLL_M 25 +static stm32f2_rcc_pll_data pll_data = {PLL_Q, PLL_P, PLL_N, PLL_M}; + +namespace wirish { + namespace priv { + rcc_pll_cfg board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + + void board_reset_pll(void) { + // Set PLLCFGR to its reset value. + RCC_BASE->PLLCFGR = 0x24003010; // FIXME lose the magic number. + } + + void board_setup_clock_prescalers(void) { + rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); + rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_4); + rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_2); + } + + void board_setup_gpio(void) { + gpio_init_all(); + } + + void board_setup_adc(void) { + // TODO + } + + void board_setup_timers(void) { + // TODO + } + + void board_setup_usb(void) { + // TODO + } + + } +} + -- cgit v1.2.3 From 6b2dfa0f90b3422e4cbfa6f51770acde50b19cfa Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 20 Mar 2012 17:46:05 -0400 Subject: Add __weak to . This is just an alias for __attribute__((weak)). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/libmaple_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h index 25ad222..b2c424a 100644 --- a/libmaple/include/libmaple/libmaple_types.h +++ b/libmaple/include/libmaple/libmaple_types.h @@ -53,6 +53,7 @@ typedef void (*voidFuncPtr)(void); #define __attr_flash __attribute__((section (".USER_FLASH"))) #define __packed __attribute__((__packed__)) #define __deprecated __attribute__((__deprecated__)) +#define __weak __attribute__((weak)) #ifndef NULL #define NULL 0 -- cgit v1.2.3 From e486ef1d6d682f2fd4d3605ed873de030d10ae2a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 20 Mar 2012 17:46:41 -0400 Subject: wirish/boards.cpp: Use __weak instead of GCC attribute. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 7d783db..04b359f 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -45,6 +45,7 @@ */ #include +#include #include #include #include @@ -71,7 +72,7 @@ void init(void) { } /* Provide a default boardInit(). */ -__attribute__((weak)) void boardInit(void) { +__weak void boardInit(void) { } /* You could farm this out to the files in boards/ if e.g. it takes -- cgit v1.2.3 From 44c3367a09f2057614392fe779129831618d795c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 13:09:08 -0400 Subject: stm32.h: Cleanups. Fix include guard name. Remove unused STM32_FLASH_WAIT_STATES (which was superseded by FLASH_SAFE_WAIT_STATES). Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/stm32.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 7ae53b2..29e789f 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -29,8 +29,8 @@ * @brief STM32F2 chip- and series-specific definitions. */ -#ifndef _LIBMAPLE_STM32F2_H_ -#define _LIBMAPLE_STM32F2_H_ +#ifndef _LIBMAPLE_STM32F2_STM32_H_ +#define _LIBMAPLE_STM32F2_STM32_H_ #ifdef __cplusplus extern "C" { @@ -52,10 +52,6 @@ extern "C" { #define STM32_DELAY_US_MULT 20 /* FIXME: dummy value. */ #endif -#ifndef STM32_FLASH_WAIT_STATES -#define STM32_FLASH_WAIT_STATES 3 /* TODO: stop using magic number */ -#endif - /* * Interrupts */ -- cgit v1.2.3 From 117a6f118adb4540866beb5aba8afd8f98da139e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 22 Mar 2012 16:01:51 -0400 Subject: Style change to libmaple/rules.mk. New style makes for cleaner diffs. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 8802161..abb6ab2 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -11,13 +11,13 @@ LIBMAPLE_PRIVATE_INCLUDES := -I$(LIBMAPLE_PATH) CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets -cSRCS_$(d) := flash.c \ - gpio.c \ - nvic.c \ - rcc.c \ - syscalls.c \ - systick.c \ - util.c +cSRCS_$(d) := flash.c +cSRCS_$(d) += gpio.c +cSRCS_$(d) += nvic.c +cSRCS_$(d) += rcc.c +cSRCS_$(d) += syscalls.c +cSRCS_$(d) += systick.c +cSRCS_$(d) += util.c sSRCS_$(d) := exc.S -- cgit v1.2.3 From 382da37cda44204331d57939c596d768cbd0e188 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 15:19:53 -0400 Subject: RCC: Add rcc_is_clk_on(). This is a convenience function for checking if a clock line is on. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 1 + libmaple/rcc.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 2c8776b..9042391 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -106,6 +106,7 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg); void rcc_turn_on_clk(rcc_clk clock); void rcc_turn_off_clk(rcc_clk clock); +int rcc_is_clk_on(rcc_clk clock); int rcc_is_clk_ready(rcc_clk clock); /* Peripheral clock lines and clock domains. */ diff --git a/libmaple/rcc.c b/libmaple/rcc.c index d42bbf1..91ce8e7 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -142,6 +142,15 @@ void rcc_turn_off_clk(rcc_clk clock) { *rcc_clk_reg(clock) &= ~rcc_clk_on_mask(clock); } +/** + * @brief Check if a clock is on. + * @param clock Clock to check. + * @return 1 if the clock is on, 0 if the clock is off. + */ +int rcc_is_clk_on(rcc_clk clock) { + return !!(*rcc_clk_reg(clock) & rcc_clk_on_mask(clock)); +} + /** * @brief Check if a clock source is ready. * -- cgit v1.2.3 From 6632789976b804889494dc1e7aea51181d4ca754 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 15:21:25 -0400 Subject: rcc_reconfigure_pll(): Assert that the PLL is disabled. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/rcc.c | 3 +++ libmaple/stm32f2/rcc.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index a9c9c3a..0752b82 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -139,6 +139,9 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { rcc_pll_multiplier pll_mul = data->pll_mul; uint32 cfgr; + /* Check that the PLL is disabled. */ + ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL)); + cfgr = RCC_BASE->CFGR; cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL); cfgr |= pll_cfg->pllsrc | pll_mul; diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c index b94f2e6..46e6565 100644 --- a/libmaple/stm32f2/rcc.c +++ b/libmaple/stm32f2/rcc.c @@ -173,6 +173,9 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { stm32f2_rcc_pll_data *data = pll_cfg->data; uint32 pllcfgr; + /* Check that the PLL is disabled. */ + ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL)); + /* Sanity-check all the parameters */ ASSERT_FAULT((data->pllq >= 4) && (data->pllq <= 15)); ASSERT_FAULT((data->pllp >= 2) && (data->pllp <= 8)); -- cgit v1.2.3 From 45763badb4ff7cee56a38b72d7546eae4205630b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 15:38:08 -0400 Subject: stm32f2: Improve GPIO alternate function support. Add GPIO_AFRL and GPIO_AFRH bit definitions; these seem to have been overlooked. Add enum gpio_af to give labels to the various functions. Add gpio_set_af() convenience routine for configuring a GPIO's alternate function. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/gpio.c | 36 ++++++++++++++++++--- libmaple/stm32f2/include/series/gpio.h | 58 +++++++++++++++++++++++++++++++--- 2 files changed, 85 insertions(+), 9 deletions(-) diff --git a/libmaple/stm32f2/gpio.c b/libmaple/stm32f2/gpio.c index 61b71f7..e441fbc 100644 --- a/libmaple/stm32f2/gpio.c +++ b/libmaple/stm32f2/gpio.c @@ -122,16 +122,16 @@ void gpio_init_all(void) { /** * @brief Set the mode of a GPIO pin. * @param dev GPIO device. - * @param pin Pin on the device whose mode to set, 0--15. + * @param bit Bit on dev whose mode to set, 0--15. * @param mode Mode to set the pin to. * @param flags Flags to modify basic mode configuration */ void gpio_set_modef(gpio_dev *dev, - uint8 pin, + uint8 bit, gpio_pin_mode mode, unsigned flags) { gpio_reg_map *regs = dev->regs; - unsigned shift = pin * 2; + unsigned shift = bit * 2; uint32 tmp; /* Mode */ @@ -141,7 +141,7 @@ void gpio_set_modef(gpio_dev *dev, regs->MODER = tmp; /* Output type */ - bb_peri_set_bit(®s->OTYPER, pin, flags & 0x1); + bb_peri_set_bit(®s->OTYPER, bit, flags & 0x1); /* Speed */ tmp = regs->OSPEEDR; @@ -155,3 +155,31 @@ void gpio_set_modef(gpio_dev *dev, tmp |= (flags >> 2) << shift; regs->PUPDR = tmp; } + +/** + * @brief Set a pin's alternate function. + * + * The pin must have its mode set to GPIO_MODE_AF for this to take + * effect. + * + * @param dev Device whose pin to configure. + * @param bit Pin whose alternate function to set. + * @param af Alternate function to use for pin. + * @see gpio_set_modef() + */ +void gpio_set_af(gpio_dev *dev, uint8 bit, gpio_af af) { + __io uint32 *afr; + unsigned shift; + uint32 tmp; + if (bit >= 8) { + afr = &dev->regs->AFRH; + shift = 4 * (bit - 8); + } else{ + afr = &dev->regs->AFRL; + shift = 4 * bit; + } + tmp = *afr; + tmp &= ~(0xF << shift); + tmp |= (af << shift); + *afr = tmp; +} diff --git a/libmaple/stm32f2/include/series/gpio.h b/libmaple/stm32f2/include/series/gpio.h index 86ee4aa..b6a7599 100644 --- a/libmaple/stm32f2/include/series/gpio.h +++ b/libmaple/stm32f2/include/series/gpio.h @@ -104,8 +104,8 @@ extern gpio_dev gpioi; /* * Register bit definitions * - * Currently, we only provide masks to be used for shifting, rather - * than repeating the same values 16 times. + * Currently, we only provide masks to be used for shifting for some + * registers, rather than repeating the same values 16 times. */ /* Mode register */ @@ -133,6 +133,28 @@ extern gpio_dev gpioi; #define GPIO_PUPDR_PU 0x1 #define GPIO_PUPDR_PD 0x2 +/* Alternate function register low */ + +#define GPIO_AFRL_AF0 (0xFU << 0) +#define GPIO_AFRL_AF1 (0xFU << 4) +#define GPIO_AFRL_AF2 (0xFU << 8) +#define GPIO_AFRL_AF3 (0xFU << 12) +#define GPIO_AFRL_AF4 (0xFU << 16) +#define GPIO_AFRL_AF5 (0xFU << 20) +#define GPIO_AFRL_AF6 (0xFU << 24) +#define GPIO_AFRL_AF7 (0xFU << 28) + +/* Alternate function register high */ + +#define GPIO_AFRH_AF8 (0xFU << 0) +#define GPIO_AFRH_AF9 (0xFU << 4) +#define GPIO_AFRH_AF10 (0xFU << 8) +#define GPIO_AFRH_AF11 (0xFU << 12) +#define GPIO_AFRH_AF12 (0xFU << 16) +#define GPIO_AFRH_AF13 (0xFU << 20) +#define GPIO_AFRH_AF14 (0xFU << 24) +#define GPIO_AFRH_AF15 (0xFU << 28) + /* * GPIO routines */ @@ -194,7 +216,7 @@ typedef enum gpio_mode_flags { } gpio_mode_flags; void gpio_set_modef(gpio_dev *dev, - uint8 pin, + uint8 bit, gpio_pin_mode mode, unsigned flags); @@ -210,11 +232,37 @@ void gpio_set_modef(gpio_dev *dev, * @param mode Mode to set the pin to. */ static inline void gpio_set_mode(gpio_dev *dev, - uint8 pin, + uint8 bit, gpio_pin_mode mode) { - gpio_set_modef(dev, pin, mode, GPIO_MODEF_SPEED_HIGH); + gpio_set_modef(dev, bit, mode, GPIO_MODEF_SPEED_HIGH); } +/** + * @brief GPIO alternate functions. + * Use these to select an alternate function for a pin. + * @see gpio_set_af() + */ +typedef enum gpio_af { + GPIO_AF_SYS = 0, /**< System. */ + GPIO_AF_TIM_1_2 = 1, /**< Timers 1 and 2. */ + GPIO_AF_TIM_3_4_5 = 2, /**< Timers 3, 4, and 5. */ + GPIO_AF_TIM_8_9_10_11 = 3, /**< Timers 8 through 11. */ + GPIO_AF_I2C = 4, /**< I2C 1, 2, and 3. */ + GPIO_AF_SPI_1_2 = 5, /**< SPI1, SPI2/I2S2. */ + GPIO_AF_SPI3 = 6, /**< SPI3/I2S3. */ + GPIO_AF_USART_1_2_3 = 7, /**< USART 1, 2, and 3. */ + GPIO_AF_USART_4_5_6 = 8, /**< UART 4 and 5, USART 6. */ + GPIO_AF_CAN_1_2_TIM_12_13_14 = 9, /**< + * CAN 1 and 2, timers 12, 13, and 14. */ + GPIO_AF_USB_OTG_FS_HS = 10, /**< USB OTG HS and FS. */ + GPIO_AF_ETH = 11, /**< Ethernet MII and RMII. */ + GPIO_AF_FSMC_SDIO_OTG_FS = 12, /**< FSMC, SDIO, and USB OTG FS. */ + GPIO_AF_DCMI = 13, /**< DCMI. */ + GPIO_AF_EVENTOUT = 15, /**< EVENTOUT. */ +} gpio_af; + +void gpio_set_af(gpio_dev *dev, uint8 bit, gpio_af af); + #ifdef __cplusplus } #endif -- cgit v1.2.3 From eee763308a497105a1aa1aefd3c4b3124e8362b3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 15:42:25 -0400 Subject: [FIXME] Resurrected, shinier USART support. FIXME: - Test F1 support - Solve problem of duplicated bytes being TXed unless delay is inserted after configuration but before first bytes are TXed. Rip out nonportable bits from top-level interfaces. The USART register maps are basically the same between F1 and F2, so leave these, but add register bit definitions which had name changes to the libmaple header to avoid needless repetition. There are also a few new bits in the F2 USART registers; add definitions for these in the F2 USART header. Add Doxygen comments for all USART bit definitions. Deprecate struct usart_dev's max_baud field. This is just bloat that doesn't bring us much real benefit. Add new series-specific USART files for F1 and F2: - libmaple/stm32f[1,2]/usart.c - libmaple/stm32f[1,2]/include/series/usart.h These are standard series-specific files, providing register map base pointers, defining devices, implementing nonportable routines, etc. We need a portable way to configure the USART GPIOs. To this end, add usart_async_gpio_cfg() to the top-level USART interface. This function is implemented in new F1 and F2 USART backends to take the appropriate action to configure the RX and TX pins for asynchronous full duplex mode. USART baud rate calculation is done differently on the different series. Keep the usart_set_baud_rate() declaration in the top-level USART header, but move the implementations into the series-specific usart.c files. In usart_set_baud_rate(), allow for deriving clock_speed automatically by letting user tell us to figure out the peripheral clock speed by mapping the device's rcc_clk_id onto an STM32_PCLK[1,2] value. This preserves flexibility for users with non-default clock configurations, but makes things easier on everyone else. Add private USART files for portable private USART routines: - libmaple/usart_private.h - libmaple/usart_private.c Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/usart.h | 229 ++++++++++++++++++++++++++------ libmaple/rules.mk | 2 + libmaple/stm32f1/include/series/usart.h | 76 +++++++++++ libmaple/stm32f1/rules.mk | 1 + libmaple/stm32f1/usart.c | 170 ++++++++++++++++++++++++ libmaple/stm32f2/include/series/usart.h | 103 ++++++++++++++ libmaple/stm32f2/rules.mk | 1 + libmaple/stm32f2/usart.c | 198 +++++++++++++++++++++++++++ libmaple/usart.c | 138 +------------------ libmaple/usart_private.c | 40 ++++++ libmaple/usart_private.h | 53 ++++++++ 11 files changed, 836 insertions(+), 175 deletions(-) create mode 100644 libmaple/stm32f1/include/series/usart.h create mode 100644 libmaple/stm32f1/usart.c create mode 100644 libmaple/stm32f2/include/series/usart.h create mode 100644 libmaple/stm32f2/usart.c create mode 100644 libmaple/usart_private.c create mode 100644 libmaple/usart_private.h diff --git a/libmaple/include/libmaple/usart.h b/libmaple/include/libmaple/usart.h index f9bdb8b..42f9576 100644 --- a/libmaple/include/libmaple/usart.h +++ b/libmaple/include/libmaple/usart.h @@ -43,9 +43,10 @@ extern "C"{ #include #include #include +#include /* - * Register maps and devices + * Register map (common across supported STM32 series). */ /** USART register map type */ @@ -59,169 +60,315 @@ typedef struct usart_reg_map { __io uint32 GTPR; /**< Guard time and prescaler register */ } usart_reg_map; -/** USART1 register map base pointer */ -#define USART1_BASE ((struct usart_reg_map*)0x40013800) -/** USART2 register map base pointer */ -#define USART2_BASE ((struct usart_reg_map*)0x40004400) -/** USART3 register map base pointer */ -#define USART3_BASE ((struct usart_reg_map*)0x40004800) -#ifdef STM32_HIGH_DENSITY -/** UART4 register map base pointer */ -#define UART4_BASE ((struct usart_reg_map*)0x40004C00) -/** UART5 register map base pointer */ -#define UART5_BASE ((struct usart_reg_map*)0x40005000) -#endif - /* * Register bit definitions */ /* Status register */ +/** Clear to send bit */ #define USART_SR_CTS_BIT 9 +/** Line break detection bit */ #define USART_SR_LBD_BIT 8 +/** Transmit data register empty bit */ #define USART_SR_TXE_BIT 7 +/** Transmission complete bit */ #define USART_SR_TC_BIT 6 +/** Read data register not empty bit */ #define USART_SR_RXNE_BIT 5 +/** IDLE line detected bit */ #define USART_SR_IDLE_BIT 4 +/** Overrun error bit */ #define USART_SR_ORE_BIT 3 +/** Noise error bit */ #define USART_SR_NE_BIT 2 +/** + * @brief Synonym for USART_SR_NE_BIT. + * + * Some series (e.g. STM32F2) use "NF" for "noise flag" instead of the + * original "NE" for "noise error". The meaning of the bit is + * unchanged, but the NF flag can be disabled when the line is + * noise-free. + * + * @see USART_SR_NE_BIT + */ +#define USART_SR_NF_BIT USART_SR_NE_BIT +/** Framing error bit */ #define USART_SR_FE_BIT 1 +/** Parity error bit */ #define USART_SR_PE_BIT 0 +/** Clear to send mask */ #define USART_SR_CTS BIT(USART_SR_CTS_BIT) +/** Line break detected mask */ #define USART_SR_LBD BIT(USART_SR_LBD_BIT) +/** Transmit data register empty mask */ #define USART_SR_TXE BIT(USART_SR_TXE_BIT) +/** Transmission complete mask */ #define USART_SR_TC BIT(USART_SR_TC_BIT) +/** Read data register not empty mask */ #define USART_SR_RXNE BIT(USART_SR_RXNE_BIT) +/** IDLE line detected mask */ #define USART_SR_IDLE BIT(USART_SR_IDLE_BIT) +/** Overrun error mask */ #define USART_SR_ORE BIT(USART_SR_ORE_BIT) +/** Noise error mask */ #define USART_SR_NE BIT(USART_SR_NE_BIT) +/** + * @brief Synonym for USART_SR_NE. + * @see USART_SR_NF_BIT + */ +#define USART_SR_NF USART_SR_NE +/** Framing error mask */ #define USART_SR_FE BIT(USART_SR_FE_BIT) +/** Parity error mask */ #define USART_SR_PE BIT(USART_SR_PE_BIT) /* Data register */ +/** Data register data value mask */ #define USART_DR_DR 0xFF /* Baud rate register */ +/** Mantissa of USARTDIV mask */ #define USART_BRR_DIV_MANTISSA (0xFFF << 4) +/** Fraction of USARTDIV mask */ #define USART_BRR_DIV_FRACTION 0xF /* Control register 1 */ +/** USART enable bit */ #define USART_CR1_UE_BIT 13 +/** Word length bit */ #define USART_CR1_M_BIT 12 +/** Wakeup method bit */ #define USART_CR1_WAKE_BIT 11 +/** Parity control enable bit */ #define USART_CR1_PCE_BIT 10 +/** Parity selection bit */ #define USART_CR1_PS_BIT 9 +/** Parity error interrupt enable bit */ #define USART_CR1_PEIE_BIT 8 +/** Transmit data regsiter not empty interrupt enable bit */ #define USART_CR1_TXEIE_BIT 7 +/** Transmission complete interrupt enable bit */ #define USART_CR1_TCIE_BIT 6 +/** RXNE interrupt enable bit */ #define USART_CR1_RXNEIE_BIT 5 +/** IDLE interrupt enable bit */ #define USART_CR1_IDLEIE_BIT 4 +/** Transmitter enable bit */ #define USART_CR1_TE_BIT 3 +/** Receiver enable bit */ #define USART_CR1_RE_BIT 2 +/** Receiver wakeup bit */ #define USART_CR1_RWU_BIT 1 +/** Send break bit */ #define USART_CR1_SBK_BIT 0 +/** USART enable mask */ #define USART_CR1_UE BIT(USART_CR1_UE_BIT) +/** Word length mask */ #define USART_CR1_M BIT(USART_CR1_M_BIT) +/** Word length: 1 start bit, 8 data bits, n stop bit */ +#define USART_CR1_M_8N1 (0 << USART_CR1_M_BIT) +/** Word length: 1 start bit, 9 data bits, n stop bit */ +#define USART_CR1_M_9N1 (1 << USART_CR1_M_BIT) +/** Wakeup method mask */ #define USART_CR1_WAKE BIT(USART_CR1_WAKE_BIT) +/** Wakeup on idle line */ #define USART_CR1_WAKE_IDLE (0 << USART_CR1_WAKE_BIT) +/** Wakeup on address mark */ #define USART_CR1_WAKE_ADDR (1 << USART_CR1_WAKE_BIT) +/** Parity control enable mask */ #define USART_CR1_PCE BIT(USART_CR1_PCE_BIT) +/** Parity selection mask */ #define USART_CR1_PS BIT(USART_CR1_PS_BIT) +/** Parity selection: even parity */ #define USART_CR1_PS_EVEN (0 << USART_CR1_PS_BIT) +/** Parity selection: odd parity */ #define USART_CR1_PS_ODD (1 << USART_CR1_PS_BIT) +/** Parity error interrupt enable mask */ #define USART_CR1_PEIE BIT(USART_CR1_PEIE_BIT) +/** Transmit data register empty interrupt enable mask */ #define USART_CR1_TXEIE BIT(USART_CR1_TXEIE_BIT) +/** Transmission complete interrupt enable mask */ #define USART_CR1_TCIE BIT(USART_CR1_TCIE_BIT) +/** RXNE interrupt enable mask */ #define USART_CR1_RXNEIE BIT(USART_CR1_RXNEIE_BIT) +/** IDLE line interrupt enable mask */ #define USART_CR1_IDLEIE BIT(USART_CR1_IDLEIE_BIT) +/** Transmitter enable mask */ #define USART_CR1_TE BIT(USART_CR1_TE_BIT) +/** Receiver enable mask */ #define USART_CR1_RE BIT(USART_CR1_RE_BIT) +/** Receiver wakeup mask */ #define USART_CR1_RWU BIT(USART_CR1_RWU_BIT) +/** Receiver wakeup: receiver in active mode */ #define USART_CR1_RWU_ACTIVE (0 << USART_CR1_RWU_BIT) +/** Receiver wakeup: receiver in mute mode */ #define USART_CR1_RWU_MUTE (1 << USART_CR1_RWU_BIT) +/** Send break */ #define USART_CR1_SBK BIT(USART_CR1_SBK_BIT) /* Control register 2 */ +/** LIN mode enable bit */ #define USART_CR2_LINEN_BIT 14 +/** Clock enable bit */ #define USART_CR2_CLKEN_BIT 11 +/** Clock polarity bit */ #define USART_CR2_CPOL_BIT 10 +/** Clock phase bit */ #define USART_CR2_CPHA_BIT 9 +/** Last bit clock pulse bit */ #define USART_CR2_LBCL_BIT 8 +/** LIN break detection interrupt enable bit */ #define USART_CR2_LBDIE_BIT 6 +/** LIN break detection length bit */ #define USART_CR2_LBDL_BIT 5 +/** LIN mode enable mask */ #define USART_CR2_LINEN BIT(USART_CR2_LINEN_BIT) +/** STOP bits mask */ #define USART_CR2_STOP (0x3 << 12) +/** STOP bits: 1 stop bit */ #define USART_CR2_STOP_BITS_1 (0x0 << 12) -/* Not on UART4, UART5 */ +/** + * @brief STOP bits: 0.5 stop bits + * Not available on UART4, UART5. */ #define USART_CR2_STOP_BITS_POINT_5 (0x1 << 12) -/* Not on UART4, UART5 */ -#define USART_CR2_STOP_BITS_1_POINT_5 (0x3 << 12) +/** STOP bits: 2 stop bits */ #define USART_CR2_STOP_BITS_2 (0x2 << 12) +/** + * @brief STOP bits: 1.5 stop bits + * Not available on UART4, UART5. */ +#define USART_CR2_STOP_BITS_1_POINT_5 (0x3 << 12) +/** + * @brief Clock enable. + * Not available on UART4, UART5 */ #define USART_CR2_CLKEN BIT(USART_CR2_CLKEN_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Clock polarity mask. + * Not available on UART4, UART5 */ #define USART_CR2_CPOL BIT(USART_CR2_CPOL_BIT) +/** Clock polarity: low */ #define USART_CR2_CPOL_LOW (0x0 << USART_CR2_CLKEN_BIT) +/** Clock polarity: high */ #define USART_CR2_CPOL_HIGH (0x1 << USART_CR2_CLKEN_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Clock phase mask. + * Not available on UART4, UART5 */ #define USART_CR2_CPHA BIT(USART_CR2_CPHA_BIT) +/** + * @brief Clock phase: first + * First clock transition is the first data capture edge. */ #define USART_CR2_CPHA_FIRST (0x0 << USART_CR2_CPHA_BIT) +/** + * @brief Clock phase: second + * Second clock transition is the first data capture edge. */ #define USART_CR2_CPHA_SECOND (0x1 << USART_CR2_CPHA_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Last bit clock pulse mask. + * + * When set, the last bit transmitted causes a clock pulse in + * synchronous mode. + * + * Not available on UART4, UART5 */ #define USART_CR2_LBCL BIT(USART_CR2_LBCL_BIT) +/** LIN break detection interrupt enable mask. */ #define USART_CR2_LBDIE BIT(USART_CR2_LBDIE_BIT) +/** LIN break detection length. */ #define USART_CR2_LBDL BIT(USART_CR2_LBDL_BIT) +/** LIN break detection length: 10 bits */ #define USART_CR2_LBDL_10_BIT (0 << USART_CR2_LBDL_BIT) +/** LIN break detection length: 11 bits */ #define USART_CR2_LBDL_11_BIT (1 << USART_CR2_LBDL_BIT) +/** + * @brief Address of the USART node + * This is useful during multiprocessor communication. */ #define USART_CR2_ADD 0xF /* Control register 3 */ +/** Clear to send interrupt enable bit */ #define USART_CR3_CTSIE_BIT 10 +/** Clear to send enable bit */ #define USART_CR3_CTSE_BIT 9 +/** Ready to send enable bit */ #define USART_CR3_RTSE_BIT 8 +/** DMA enable transmitter bit */ #define USART_CR3_DMAT_BIT 7 +/** DMA enable receiver bit */ #define USART_CR3_DMAR_BIT 6 +/** Smartcard mode enable bit */ #define USART_CR3_SCEN_BIT 5 +/** Smartcard NACK enable bit */ #define USART_CR3_NACK_BIT 4 +/** Half-duplex selection bit */ #define USART_CR3_HDSEL_BIT 3 +/** IrDA low power bit */ #define USART_CR3_IRLP_BIT 2 +/** IrDA mode enable bit */ #define USART_CR3_IREN_BIT 1 +/** Error interrupt enable bit */ #define USART_CR3_EIE_BIT 0 -/* Not on UART4, UART5 */ +/** + * @brief Clear to send interrupt enable + * Not available on UART4, UART5. */ #define USART_CR3_CTSIE BIT(USART_CR3_CTSIE_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Clear to send enable + * Not available on UART4, UART5. */ #define USART_CR3_CTSE BIT(USART_CR3_CTSE_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Ready to send enable + * Not available on UART4, UART5. */ #define USART_CR3_RTSE BIT(USART_CR3_RTSE_BIT) -/* Not on UART5 */ +/** + * @brief DMA enable transmitter + * Not available on UART5. */ #define USART_CR3_DMAT BIT(USART_CR3_DMAT_BIT) -/* Not on UART5 */ +/** + * @brief DMA enable receiver + * Not available on UART5. */ #define USART_CR3_DMAR BIT(USART_CR3_DMAR_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Smartcard mode enable + * Not available on UART4, UART5. */ #define USART_CR3_SCEN BIT(USART_CR3_SCEN_BIT) -/* Not on UART4, UART5 */ +/** + * @brief Smartcard NACK enable + * Not available on UART4, UART5. */ #define USART_CR3_NACK BIT(USART_CR3_NACK_BIT) +/** + * @brief Half-duplex selection + * When set, single-wire half duplex mode is selected. + */ #define USART_CR3_HDSEL BIT(USART_CR3_HDSEL_BIT) +/** IrDA low power mode */ #define USART_CR3_IRLP BIT(USART_CR3_IRLP_BIT) -#define USART_CR3_IRLP_NORMAL (0 << USART_CR3_IRLP_BIT) -#define USART_CR3_IRLP_LOW_POWER (1 << USART_CR3_IRLP_BIT) +/** IrDA mode: normal */ +#define USART_CR3_IRLP_NORMAL (0U << USART_CR3_IRLP_BIT) +/** IrDA mode: low power */ +#define USART_CR3_IRLP_LOW_POWER (1U << USART_CR3_IRLP_BIT) +/** IrDA mode enable */ #define USART_CR3_IREN BIT(USART_CR3_IREN_BIT) +/** Error interrupt enable */ #define USART_CR3_EIE BIT(USART_CR3_EIE_BIT) /* Guard time and prescaler register */ -/* Not on UART4, UART5 */ +/** + * @brief Guard time value mask + * Used in Smartcard mode. Not available on UART4, UART5. */ #define USART_GTPR_GT (0xFF << 8) -/* Not on UART4, UART5 */ +/** + * @brief Prescaler value mask + * Restrictions on this value apply, depending on the USART mode. Not + * available on UART4, UART5. */ #define USART_GTPR_PSC 0xFF /* @@ -236,7 +383,8 @@ typedef struct usart_reg_map { typedef struct usart_dev { usart_reg_map *regs; /**< Register map */ ring_buffer *rb; /**< RX ring buffer */ - uint32 max_baud; /**< Maximum baud */ + uint32 max_baud; /**< @brief Deprecated. + * Maximum baud rate. */ uint8 rx_buf[USART_RX_BUF_SIZE]; /**< @brief Deprecated. * Actual RX buffer used by rb. * This field will be removed in @@ -245,16 +393,17 @@ typedef struct usart_dev { nvic_irq_num irq_num; /**< USART NVIC interrupt */ } usart_dev; -extern usart_dev *USART1; -extern usart_dev *USART2; -extern usart_dev *USART3; -#ifdef STM32_HIGH_DENSITY -extern usart_dev *UART4; -extern usart_dev *UART5; -#endif - void usart_init(usart_dev *dev); + +struct gpio_dev; /* forward declaration */ +void usart_async_gpio_cfg(usart_dev *udev, + struct gpio_dev *rx_dev, uint8 rx, + struct gpio_dev *tx_dev, uint8 tx, + unsigned flags); + +#define USART_USE_PCLK 0 void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud); + void usart_enable(usart_dev *dev); void usart_disable(usart_dev *dev); void usart_foreach(void (*fn)(usart_dev *dev)); diff --git a/libmaple/rules.mk b/libmaple/rules.mk index abb6ab2..5675c1c 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -18,6 +18,8 @@ cSRCS_$(d) += rcc.c cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c cSRCS_$(d) += util.c +cSRCS_$(d) += usart.c +cSRCS_$(d) += usart_private.c sSRCS_$(d) := exc.S diff --git a/libmaple/stm32f1/include/series/usart.h b/libmaple/stm32f1/include/series/usart.h new file mode 100644 index 0000000..93a7728 --- /dev/null +++ b/libmaple/stm32f1/include/series/usart.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/usart.h + * @author Marti Bolivar + * @brief STM32F1 USART header. + */ + +#ifndef _LIBMAPLE_STM32F1_USART_H_ +#define _LIBMAPLE_STM32F1_USART_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Register map base pointers + */ + +struct usart_reg_map; + +/** USART1 register map base pointer */ +#define USART1_BASE ((struct usart_reg_map*)0x40013800) +/** USART2 register map base pointer */ +#define USART2_BASE ((struct usart_reg_map*)0x40004400) +/** USART3 register map base pointer */ +#define USART3_BASE ((struct usart_reg_map*)0x40004800) +#ifdef STM32_HIGH_DENSITY +/** UART4 register map base pointer */ +#define UART4_BASE ((struct usart_reg_map*)0x40004C00) +/** UART5 register map base pointer */ +#define UART5_BASE ((struct usart_reg_map*)0x40005000) +#endif + +/* + * Devices + */ + +struct usart_dev; +extern struct usart_dev *USART1; +extern struct usart_dev *USART2; +extern struct usart_dev *USART3; +#ifdef STM32_HIGH_DENSITY +extern struct usart_dev *UART4; +extern struct usart_dev *UART5; +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 4c7db60..3d34797 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -14,6 +14,7 @@ sSRCS_$(d) := isrs_performance.S \ cSRCS_$(d) := rcc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += bkp.c +cSRCS_$(d) += usart.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f1/usart.c b/libmaple/stm32f1/usart.c new file mode 100644 index 0000000..ee68082 --- /dev/null +++ b/libmaple/stm32f1/usart.c @@ -0,0 +1,170 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/usart.c + * @author Marti Bolivar , + * Perry Hung + * @brief STM32F1 USART support. + */ + +#include +#include +#include "usart_private.h" + +/* + * Devices + */ + +static ring_buffer usart1_rb; +static usart_dev usart1 = { + .regs = USART1_BASE, + .rb = &usart1_rb, + .max_baud = 4500000UL, + .clk_id = RCC_USART1, + .irq_num = NVIC_USART1, +}; +/** USART1 device */ +usart_dev *USART1 = &usart1; + +static ring_buffer usart2_rb; +static usart_dev usart2 = { + .regs = USART2_BASE, + .rb = &usart2_rb, + .max_baud = 2250000UL, + .clk_id = RCC_USART2, + .irq_num = NVIC_USART2, +}; +/** USART2 device */ +usart_dev *USART2 = &usart2; + +static ring_buffer usart3_rb; +static usart_dev usart3 = { + .regs = USART3_BASE, + .rb = &usart3_rb, + .max_baud = 2250000UL, + .clk_id = RCC_USART3, + .irq_num = NVIC_USART3, +}; +/** USART3 device */ +usart_dev *USART3 = &usart3; + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +static ring_buffer uart4_rb; +static usart_dev uart4 = { + .regs = UART4_BASE, + .rb = &uart4_rb, + .max_baud = 2250000UL, + .clk_id = RCC_UART4, + .irq_num = NVIC_UART4, +}; +/** UART4 device */ +usart_dev *UART4 = &uart4; + +static ring_buffer uart5_rb; +static usart_dev uart5 = { + .regs = UART5_BASE, + .rb = &uart5_rb, + .max_baud = 2250000UL, + .clk_id = RCC_UART5, + .irq_num = NVIC_UART5, +}; +/** UART5 device */ +usart_dev *UART5 = &uart5; +#endif + +/* + * Routines + */ + +void usart_async_gpio_cfg(usart_dev *udev, + gpio_dev *rx_dev, uint8 rx, + gpio_dev *tx_dev, uint8 tx, + unsigned flags) { + gpio_set_mode(rx_dev, rx, GPIO_INPUT_FLOATING); + gpio_set_mode(tx_dev, tx, GPIO_AF_OUTPUT_PP); +} + +void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud) { + uint32 integer_part; + uint32 fractional_part; + uint32 tmp; + + /* Figure out the clock speed, if the user doesn't give one. */ + if (clock_speed == 0) { + clock_speed = _usart_clock_freq(dev); + } + ASSERT(clock_speed); + + /* Convert desired baud rate to baud rate register setting. */ + integer_part = (25 * clock_speed) / (4 * baud); + tmp = (integer_part / 100) << 4; + fractional_part = integer_part - (100 * (tmp >> 4)); + tmp |= (((fractional_part * 16) + 50) / 100) & ((uint8)0x0F); + + dev->regs->BRR = (uint16)tmp; +} + +/** + * @brief Call a function on each USART. + * @param fn Function to call. + */ +void usart_foreach(void (*fn)(usart_dev*)) { + fn(USART1); + fn(USART2); + fn(USART3); +#ifdef STM32_HIGH_DENSITY + fn(UART4); + fn(UART5); +#endif +} + +/* + * Interrupt handlers. + */ + +void __irq_usart1(void) { + usart_irq(&usart1_rb, USART1_BASE); +} + +void __irq_usart2(void) { + usart_irq(&usart2_rb, USART2_BASE); +} + +void __irq_usart3(void) { + usart_irq(&usart3_rb, USART3_BASE); +} + +#ifdef STM32_HIGH_DENSITY +void __irq_uart4(void) { + usart_irq(&uart4_rb, UART4_BASE); +} + +void __irq_uart5(void) { + usart_irq(&uart5_rb, UART5_BASE); +} +#endif diff --git a/libmaple/stm32f2/include/series/usart.h b/libmaple/stm32f2/include/series/usart.h new file mode 100644 index 0000000..9b18b9c --- /dev/null +++ b/libmaple/stm32f2/include/series/usart.h @@ -0,0 +1,103 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/usart.h + * @author Marti Bolivar + * @brief STM32F2 USART header. + */ + +#ifndef _LIBMAPLE_STM32F2_USART_H_ +#define _LIBMAPLE_STM32F2_USART_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Register map base pointers. + */ + +struct usart_reg_map; + +/** USART1 register map base pointer */ +#define USART1_BASE ((struct usart_reg_map*)0x40011000) +/** USART2 register map base pointer */ +#define USART2_BASE ((struct usart_reg_map*)0x40004400) +/** USART3 register map base pointer */ +#define USART3_BASE ((struct usart_reg_map*)0x40004800) +/** UART4 register map base pointer */ +#define UART4_BASE ((struct usart_reg_map*)0x40004C00) +/** UART5 register map base pointer */ +#define UART5_BASE ((struct usart_reg_map*)0x40005000) +/** USART6 register map base pointer */ +#define USART6_BASE ((struct usart_reg_map*)0x40011400) + +/* + * F2-only register bit definitions. + */ + +/* Control register 1 */ + +/** + * @brief Oversampling mode bit. + * Availability: STM32F2. */ +#define USART_CR1_OVER8_BIT 15 + +/** + * @brief Oversampling mode. + * Availability: STM32F2. */ +#define USART_CR1_OVER8 (1U << USART_CR1_OVER8_BIT) + +/* Control register 3 */ + +/** One sample bit method enable bit. */ +#define USART_CR3_ONEBIT_BIT 11 + +/** One bit sample method enable. */ +#define USART_CR3_ONEBIT (1 << USART_CR3_ONEBIT_BIT) +/** Sample method: Three sample bit method. */ +#define USART_CR3_ONEBIT_3SAMPLE (0 << USART_CR3_ONEBIT_BIT) +/** Sample method: One sample bit method. */ +#define USART_CR3_ONEBIT_1SAMPLE (1 << USART_CR3_ONEBIT_BIT) + +/* + * Devices + */ + +struct usart_dev; +extern struct usart_dev *USART1; +extern struct usart_dev *USART2; +extern struct usart_dev *USART3; +extern struct usart_dev *UART4; +extern struct usart_dev *UART5; +extern struct usart_dev *USART6; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 83ab043..54fa068 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -11,6 +11,7 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We sSRCS_$(d) := isrs.S vector_table.S cSRCS_$(d) := rcc.c cSRCS_$(d) += gpio.c +cSRCS_$(d) += usart.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f2/usart.c b/libmaple/stm32f2/usart.c new file mode 100644 index 0000000..364558c --- /dev/null +++ b/libmaple/stm32f2/usart.c @@ -0,0 +1,198 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/usart.c + * @author Marti Bolivar + * @brief STM32F2 USART support. + */ + +#include +#include +#include "usart_private.h" + +/* + * Devices + */ + +static ring_buffer usart1_rb; +static usart_dev usart1 = { + .regs = USART1_BASE, + .rb = &usart1_rb, + .max_baud = 4500000UL, /* FIXME */ + .clk_id = RCC_USART1, + .irq_num = NVIC_USART1, +}; +/** USART1 device */ +usart_dev *USART1 = &usart1; + +static ring_buffer usart2_rb; +static usart_dev usart2 = { + .regs = USART2_BASE, + .rb = &usart2_rb, + .max_baud = 2250000UL, /* FIXME */ + .clk_id = RCC_USART2, + .irq_num = NVIC_USART2, +}; +/** USART2 device */ +usart_dev *USART2 = &usart2; + +static ring_buffer usart3_rb; +static usart_dev usart3 = { + .regs = USART3_BASE, + .rb = &usart3_rb, + .max_baud = 2250000UL, /* FIXME */ + .clk_id = RCC_USART3, + .irq_num = NVIC_USART3, +}; +/** USART3 device */ +usart_dev *USART3 = &usart3; + +static ring_buffer uart4_rb; +static usart_dev uart4 = { + .regs = UART4_BASE, + .rb = &uart4_rb, + .max_baud = 2250000UL, /* FIXME */ + .clk_id = RCC_UART4, + .irq_num = NVIC_UART4, +}; +/** UART4 device */ +usart_dev *UART4 = &uart4; + +static ring_buffer uart5_rb; +static usart_dev uart5 = { + .regs = UART5_BASE, + .rb = &uart5_rb, + .max_baud = 2250000UL, /* FIXME */ + .clk_id = RCC_UART5, + .irq_num = NVIC_UART5, +}; +/** UART5 device */ +usart_dev *UART5 = &uart5; + +static ring_buffer usart6_rb; +static usart_dev usart6 = { + .regs = USART6_BASE, + .rb = &usart6_rb, + .max_baud = 4500000UL, /* FIXME */ + .clk_id = RCC_USART6, + .irq_num = NVIC_USART6, +}; +usart_dev *USART6 = &usart6; + +/* + * Routines + */ + +void usart_async_gpio_cfg(usart_dev *udev, + gpio_dev *rx_dev, uint8 rx, + gpio_dev *tx_dev, uint8 tx, + unsigned flags) { + gpio_af af; + switch (udev->clk_id) { + case RCC_USART1: + case RCC_USART2: + case RCC_USART3: + af = GPIO_AF_USART_1_2_3; + break; + case RCC_UART4: + case RCC_UART5: + case RCC_USART6: + af = GPIO_AF_USART_4_5_6; + break; + default: + ASSERT(0); + return; + } + gpio_set_modef(rx_dev, rx, GPIO_MODE_AF, 0); + gpio_set_modef(tx_dev, tx, GPIO_MODE_AF, 0); + gpio_set_af(rx_dev, rx, af); + gpio_set_af(tx_dev, tx, af); +} + +void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud) { + uint32 integer_part; + uint32 fractional_part; + uint32 tmp; + uint32 over8 = !!(dev->regs->CR1 & USART_CR1_OVER8); + + ASSERT(!over8); /* OVER8 is currently unsupported. */ + + /* Figure out the clock speed, if the user doesn't give one. */ + if (clock_speed == 0) { + clock_speed = _usart_clock_freq(dev); + } + ASSERT(clock_speed); + + /* Convert desired baud rate to baud rate register setting. */ + integer_part = (25 * clock_speed) / (2 * (2 - over8) * baud); + tmp = (integer_part / 100) << 4; + fractional_part = integer_part - (100 * (tmp >> 4)); + tmp |= ((fractional_part * 16 + 50) / 100) & (uint8)0x0F; + + dev->regs->BRR = tmp; +} + +/** + * @brief Call a function on each USART. + * @param fn Function to call. + */ +void usart_foreach(void (*fn)(usart_dev*)) { + fn(USART1); + fn(USART2); + fn(USART3); + fn(UART4); + fn(UART5); + fn(USART6); +} + +/* + * Interrupt handlers. + */ + +void __irq_usart1(void) { + usart_irq(&usart1_rb, USART1_BASE); +} + +void __irq_usart2(void) { + usart_irq(&usart2_rb, USART2_BASE); +} + +void __irq_usart3(void) { + usart_irq(&usart3_rb, USART3_BASE); +} + +void __irq_uart4(void) { + usart_irq(&uart4_rb, UART4_BASE); +} + +void __irq_uart5(void) { + usart_irq(&uart5_rb, UART5_BASE); +} + +void __irq_usart6(void) { + usart_irq(&usart6_rb, USART6_BASE); +} diff --git a/libmaple/usart.c b/libmaple/usart.c index ba63b79..1070aa2 100644 --- a/libmaple/usart.c +++ b/libmaple/usart.c @@ -33,67 +33,6 @@ #include -/* - * Devices - */ - -static ring_buffer usart1_rb; -static usart_dev usart1 = { - .regs = USART1_BASE, - .rb = &usart1_rb, - .max_baud = 4500000UL, - .clk_id = RCC_USART1, - .irq_num = NVIC_USART1 -}; -/** USART1 device */ -usart_dev *USART1 = &usart1; - -static ring_buffer usart2_rb; -static usart_dev usart2 = { - .regs = USART2_BASE, - .rb = &usart2_rb, - .max_baud = 2250000UL, - .clk_id = RCC_USART2, - .irq_num = NVIC_USART2 -}; -/** USART2 device */ -usart_dev *USART2 = &usart2; - -static ring_buffer usart3_rb; -static usart_dev usart3 = { - .regs = USART3_BASE, - .rb = &usart3_rb, - .max_baud = 2250000UL, - .clk_id = RCC_USART3, - .irq_num = NVIC_USART3 -}; -/** USART3 device */ -usart_dev *USART3 = &usart3; - -#ifdef STM32_HIGH_DENSITY -static ring_buffer uart4_rb; -static usart_dev uart4 = { - .regs = UART4_BASE, - .rb = &uart4_rb, - .max_baud = 2250000UL, - .clk_id = RCC_UART4, - .irq_num = NVIC_UART4 -}; -/** UART4 device */ -usart_dev *UART4 = &uart4; - -static ring_buffer uart5_rb; -static usart_dev uart5 = { - .regs = UART5_BASE, - .rb = &uart5_rb, - .max_baud = 2250000UL, - .clk_id = RCC_UART5, - .irq_num = NVIC_UART5 -}; -/** UART5 device */ -usart_dev *UART5 = &uart5; -#endif - /** * @brief Initialize a serial port. * @param dev Serial port to be initialized @@ -104,27 +43,6 @@ void usart_init(usart_dev *dev) { nvic_irq_enable(dev->irq_num); } -/** - * @brief Configure a serial port's baud rate. - * - * @param dev Serial port to be configured - * @param clock_speed Clock speed, in megahertz. - * @param baud Baud rate for transmit/receive. - */ -void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud) { - uint32 integer_part; - uint32 fractional_part; - uint32 tmp; - - /* See ST RM0008 for the details on configuring the baud rate register */ - integer_part = (25 * clock_speed) / (4 * baud); - tmp = (integer_part / 100) << 4; - fractional_part = integer_part - (100 * (tmp >> 4)); - tmp |= (((fractional_part * 16) + 50) / 100) & ((uint8)0x0F); - - dev->regs->BRR = (uint16)tmp; -} - /** * @brief Enable a serial port. * @@ -138,7 +56,8 @@ void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud) { */ void usart_enable(usart_dev *dev) { usart_reg_map *regs = dev->regs; - regs->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; + regs->CR1 = (USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE | + USART_CR1_M_8N1); regs->CR1 |= USART_CR1_UE; } @@ -147,7 +66,7 @@ void usart_enable(usart_dev *dev) { * @param dev Serial port to be disabled */ void usart_disable(usart_dev *dev) { - /* FIXME this misbehaves if you try to use PWM on TX afterwards */ + /* FIXME this misbehaves (on F1) if you try to use PWM on TX afterwards */ usart_reg_map *regs = dev->regs; /* TC bit must be high before disabling the USART */ @@ -161,20 +80,6 @@ void usart_disable(usart_dev *dev) { usart_reset_rx(dev); } -/** - * @brief Call a function on each USART. - * @param fn Function to call. - */ -void usart_foreach(void (*fn)(usart_dev*)) { - fn(USART1); - fn(USART2); - fn(USART3); -#ifdef STM32_HIGH_DENSITY - fn(UART4); - fn(UART5); -#endif -} - /** * @brief Nonblocking USART transmit * @param dev Serial port to transmit over @@ -230,40 +135,3 @@ void usart_putudec(usart_dev *dev, uint32 val) { usart_putc(dev, digits[i]); } } - -/* - * Interrupt handlers. - */ - -static inline void usart_irq(usart_dev *dev) { -#ifdef USART_SAFE_INSERT - /* If the buffer is full and the user defines USART_SAFE_INSERT, - * ignore new bytes. */ - rb_safe_insert(dev->rb, (uint8)dev->regs->DR); -#else - /* By default, push bytes around in the ring buffer. */ - rb_push_insert(dev->rb, (uint8)dev->regs->DR); -#endif -} - -void __irq_usart1(void) { - usart_irq(USART1); -} - -void __irq_usart2(void) { - usart_irq(USART2); -} - -void __irq_usart3(void) { - usart_irq(USART3); -} - -#ifdef STM32_HIGH_DENSITY -void __irq_uart4(void) { - usart_irq(UART4); -} - -void __irq_uart5(void) { - usart_irq(UART5); -} -#endif diff --git a/libmaple/usart_private.c b/libmaple/usart_private.c new file mode 100644 index 0000000..d79387a --- /dev/null +++ b/libmaple/usart_private.c @@ -0,0 +1,40 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/usart_private.c + * @author Marti Bolivar + * @brief Private USART routines. + */ + +#include "usart_private.h" +#include + +uint32 _usart_clock_freq(usart_dev *dev) { + rcc_clk_domain domain = rcc_dev_clk(dev->clk_id); + return (domain == RCC_APB1 ? STM32_PCLK1 : + (domain == RCC_APB2 ? STM32_PCLK2 : 0)); +} diff --git a/libmaple/usart_private.h b/libmaple/usart_private.h new file mode 100644 index 0000000..a5cec83 --- /dev/null +++ b/libmaple/usart_private.h @@ -0,0 +1,53 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/usart_private.h + * @author Marti Bolivar + * @brief Private USART header. + */ + +#ifndef _LIBMAPLE_USART_PRIVATE_H_ +#define _LIBMAPLE_USART_PRIVATE_H_ + +#include +#include + +static inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) { +#ifdef USART_SAFE_INSERT + /* If the buffer is full and the user defines USART_SAFE_INSERT, + * ignore new bytes. */ + rb_safe_insert(rb, (uint8)regs->DR); +#else + /* By default, push bytes around in the ring buffer. */ + rb_push_insert(rb, (uint8)regs->DR); +#endif +} + +uint32 _usart_clock_freq(usart_dev *dev); + +#endif -- cgit v1.2.3 From c997dcd4f4d4c1a2cba55dc4bb5998e3ec3e03da Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 17:04:06 -0400 Subject: stm32.h: Add STM32_HAVE_FSMC. This is a feature test macro for the flexible static memory controller (FSMC) peripheral. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 3 +++ libmaple/stm32f1/include/series/stm32.h | 2 ++ libmaple/stm32f2/include/series/stm32.h | 9 ++------- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 3f86faa..d6f3304 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -55,6 +55,9 @@ extern "C" { * * - Everything enclosed in the following __DOXYGEN_PREDEFINED_HACK * conditional block. + * + * - STM32_HAVE_FSMC: 1 if the MCU has the FSMC peripheral, and 0 + * otherwise. */ #include diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 86f0294..26c45a2 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -58,8 +58,10 @@ extern "C" { #ifdef STM32_MEDIUM_DENSITY # define STM32_NR_INTERRUPTS 43 +# define STM32_HAVE_FSMC 0 #elif defined(STM32_HIGH_DENSITY) # define STM32_NR_INTERRUPTS 60 +# define STM32_HAVE_FSMC 1 #else #error "Unsupported STM32F1 density, or no density specified. Add something " \ "like -DSTM32_MEDIUM_DENSITY to your compiler arguments." diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 29e789f..222608d 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -52,22 +52,17 @@ extern "C" { #define STM32_DELAY_US_MULT 20 /* FIXME: dummy value. */ #endif -/* - * Interrupts - */ - -#define STM32_NR_INTERRUPTS 81 - /* * Series- and MCU-specific values */ #define STM32_MCU_SERIES STM32_SERIES_F2 +#define STM32_NR_INTERRUPTS 81 +#define STM32_HAVE_FSMC 1 #if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG) # define STM32_NR_GPIO_PORTS 9 # define STM32_SRAM_END ((void*)0x20020000) - #else #error "Unrecognized STM32F2 MCU, or no MCU specified." #endif -- cgit v1.2.3 From 9762659a16011a2e78665dffd11e5ef6ac928d8f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 17:06:21 -0400 Subject: fsmc.h: Use STM32_HAVE_FSMC feature-test macro. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/fsmc.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/fsmc.h b/libmaple/include/libmaple/fsmc.h index 95b0d3a..a83f7ab 100644 --- a/libmaple/include/libmaple/fsmc.h +++ b/libmaple/include/libmaple/fsmc.h @@ -41,8 +41,11 @@ extern "C"{ #endif #include +#include -#ifdef STM32_HIGH_DENSITY +#if !STM32_HAVE_FSMC +#error "FSMC is unavailable on your MCU" +#endif /* * Register maps and devices @@ -307,8 +310,6 @@ static inline void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map *regs, regs->BTR |= addset & 0xF; } -#endif /* STM32_HIGH_DENSITY */ - #ifdef __cplusplus } /* extern "C" */ #endif -- cgit v1.2.3 From 66f75ca74ea11d0c242bd3773a7b31f07030c8e7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 17:38:32 -0400 Subject: [UNTESTED] Resurrect FSMC support. fsmc_sram_init_gpios() is now series-specific, so move its existing implementation to the F1 backend, and add libmaple/stm32f2/fsmc.c for the F2 backend. Delete libmaple/fsmc.c; it is now empty. Signed-off-by: Marti Bolivar --- libmaple/fsmc.c | 93 --------------------------------------- libmaple/include/libmaple/fsmc.h | 3 ++ libmaple/stm32f1/fsmc.c | 95 ++++++++++++++++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 1 + libmaple/stm32f2/fsmc.c | 90 +++++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 2 + 6 files changed, 191 insertions(+), 93 deletions(-) delete mode 100644 libmaple/fsmc.c create mode 100644 libmaple/stm32f1/fsmc.c create mode 100644 libmaple/stm32f2/fsmc.c diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c deleted file mode 100644 index bf4611d..0000000 --- a/libmaple/fsmc.c +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Bryan Newbold. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file fsmc.c - * @brief Flexible static memory controller support. - */ - -#include -#include - -#ifdef STM32_HIGH_DENSITY - -/** - * Configure FSMC GPIOs for use with SRAM. - */ -void fsmc_sram_init_gpios(void) { - /* Data lines... */ - gpio_set_mode(GPIOD, 0, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 8, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 9, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 7, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 8, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 9, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP); - - /* Address lines... */ - gpio_set_mode(GPIOD, 11, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 12, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOD, 13, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 0, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 1, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 2, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 3, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 4, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 5, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 12, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 13, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 14, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOF, 15, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOG, 0, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOG, 1, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOG, 2, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOG, 3, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOG, 4, GPIO_AF_OUTPUT_PP); - gpio_set_mode(GPIOG, 5, GPIO_AF_OUTPUT_PP); - - /* And control lines... */ - gpio_set_mode(GPIOD, 4, GPIO_AF_OUTPUT_PP); // NOE - gpio_set_mode(GPIOD, 5, GPIO_AF_OUTPUT_PP); // NWE - - gpio_set_mode(GPIOD, 7, GPIO_AF_OUTPUT_PP); // NE1 - gpio_set_mode(GPIOG, 9, GPIO_AF_OUTPUT_PP); // NE2 - gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP); // NE3 - gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP); // NE4 - - gpio_set_mode(GPIOE, 0, GPIO_AF_OUTPUT_PP); // NBL0 - gpio_set_mode(GPIOE, 1, GPIO_AF_OUTPUT_PP); // NBL1 -} - -#endif /* STM32_HIGH_DENSITY */ diff --git a/libmaple/include/libmaple/fsmc.h b/libmaple/include/libmaple/fsmc.h index a83f7ab..df211b2 100644 --- a/libmaple/include/libmaple/fsmc.h +++ b/libmaple/include/libmaple/fsmc.h @@ -280,6 +280,9 @@ typedef struct fsmc_nor_psram_reg_map { * SRAM/NOR Flash routines */ +/** + * @brief Configure FSMC GPIOs for use with SRAM. + */ void fsmc_sram_init_gpios(void); /** diff --git a/libmaple/stm32f1/fsmc.c b/libmaple/stm32f1/fsmc.c new file mode 100644 index 0000000..8e01b5e --- /dev/null +++ b/libmaple/stm32f1/fsmc.c @@ -0,0 +1,95 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * Copyright (c) 2010 Bryan Newbold. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f1/fsmc.c + * @author Marti Bolivar , + * Bryan Newbold + * @brief STM32F1 FSMC support. + */ + +#include + +#if STM32_HAVE_FSMC /* Don't try building the rest for MCUs without FSMC */ + +#include +#include + +void fsmc_sram_init_gpios(void) { + /* Data lines... */ + gpio_set_mode(GPIOD, 0, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 8, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 9, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 7, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 8, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 9, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP); + + /* Address lines... */ + gpio_set_mode(GPIOD, 11, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 12, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOD, 13, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 0, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 1, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 2, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 3, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 4, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 5, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 12, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 13, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 14, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOF, 15, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOG, 0, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOG, 1, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOG, 2, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOG, 3, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOG, 4, GPIO_AF_OUTPUT_PP); + gpio_set_mode(GPIOG, 5, GPIO_AF_OUTPUT_PP); + + /* And control lines... */ + gpio_set_mode(GPIOD, 4, GPIO_AF_OUTPUT_PP); // NOE + gpio_set_mode(GPIOD, 5, GPIO_AF_OUTPUT_PP); // NWE + + gpio_set_mode(GPIOD, 7, GPIO_AF_OUTPUT_PP); // NE1 + gpio_set_mode(GPIOG, 9, GPIO_AF_OUTPUT_PP); // NE2 + gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP); // NE3 + gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP); // NE4 + + gpio_set_mode(GPIOE, 0, GPIO_AF_OUTPUT_PP); // NBL0 + gpio_set_mode(GPIOE, 1, GPIO_AF_OUTPUT_PP); // NBL1 +} + +#endif /* STM32_HAVE_FSMC */ diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 3d34797..b961d77 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -12,6 +12,7 @@ sSRCS_$(d) := isrs_performance.S \ vector_table_performance.S cSRCS_$(d) := rcc.c +cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += bkp.c cSRCS_$(d) += usart.c diff --git a/libmaple/stm32f2/fsmc.c b/libmaple/stm32f2/fsmc.c new file mode 100644 index 0000000..9b23eea --- /dev/null +++ b/libmaple/stm32f2/fsmc.c @@ -0,0 +1,90 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f2/fsmc.c + * @author Marti Bolivar , + * @brief STM32F2 FSMC support. + */ + +#include +#include + +#define CONFIG_GPIO(dev, bit) \ + do { \ + gpio_set_modef(dev, bit, GPIO_MODE_AF, GPIO_MODEF_SPEED_HIGH); \ + gpio_set_af(dev, bit, GPIO_AF_FSMC_SDIO_OTG_FS); \ + } while (0) +void fsmc_sram_init_gpios(void) { + /* Data lines... */ + CONFIG_GPIO(GPIOD, 0); + CONFIG_GPIO(GPIOD, 1); + CONFIG_GPIO(GPIOD, 8); + CONFIG_GPIO(GPIOD, 9); + CONFIG_GPIO(GPIOD, 10); + CONFIG_GPIO(GPIOD, 14); + CONFIG_GPIO(GPIOD, 15); + CONFIG_GPIO(GPIOE, 7); + CONFIG_GPIO(GPIOE, 8); + CONFIG_GPIO(GPIOE, 9); + CONFIG_GPIO(GPIOE, 10); + CONFIG_GPIO(GPIOE, 11); + CONFIG_GPIO(GPIOE, 12); + CONFIG_GPIO(GPIOE, 13); + CONFIG_GPIO(GPIOE, 14); + CONFIG_GPIO(GPIOE, 15); + + /* Address lines... */ + CONFIG_GPIO(GPIOD, 11); + CONFIG_GPIO(GPIOD, 12); + CONFIG_GPIO(GPIOD, 13); + CONFIG_GPIO(GPIOF, 0); + CONFIG_GPIO(GPIOF, 1); + CONFIG_GPIO(GPIOF, 2); + CONFIG_GPIO(GPIOF, 3); + CONFIG_GPIO(GPIOF, 4); + CONFIG_GPIO(GPIOF, 5); + CONFIG_GPIO(GPIOF, 12); + CONFIG_GPIO(GPIOF, 13); + CONFIG_GPIO(GPIOF, 14); + CONFIG_GPIO(GPIOF, 15); + CONFIG_GPIO(GPIOG, 0); + CONFIG_GPIO(GPIOG, 1); + CONFIG_GPIO(GPIOG, 2); + CONFIG_GPIO(GPIOG, 3); + CONFIG_GPIO(GPIOG, 4); + CONFIG_GPIO(GPIOG, 5); + + /* And control lines... */ + CONFIG_GPIO(GPIOD, 4); + CONFIG_GPIO(GPIOD, 5); + CONFIG_GPIO(GPIOD, 7); + CONFIG_GPIO(GPIOG, 9); + CONFIG_GPIO(GPIOG, 10); + CONFIG_GPIO(GPIOG, 12); + CONFIG_GPIO(GPIOE, 0); + CONFIG_GPIO(GPIOE, 1); +} diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 54fa068..8711090 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -9,7 +9,9 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We # Local rules and targets sSRCS_$(d) := isrs.S vector_table.S + cSRCS_$(d) := rcc.c +cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += usart.c -- cgit v1.2.3 From b70544a1fd713db6c9fb2cef773da2029cdc8c70 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 19:27:37 -0400 Subject: libmaple/pwr.h: Fix register bits (breaking change). This is a backwards-incompatible change. It is necessary to fix an error. The register bit definitions are given as if they were masks, but they're actually bit numbers. E.g., PWR_CR_DBP, which should be the mask for DBP in the power control register PWR_CR, is actually the number of the bit that should be masked. Fix this by adding _BIT to the definitions and adding proper masks. Also add a mask for the PVD level selection bits in PWR_CSR. Don't add any mask values for particular voltages selected as these are not portable. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/pwr.h | 44 +++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/libmaple/include/libmaple/pwr.h b/libmaple/include/libmaple/pwr.h index 6836e7f..8841518 100644 --- a/libmaple/include/libmaple/pwr.h +++ b/libmaple/include/libmaple/pwr.h @@ -54,28 +54,52 @@ typedef struct pwr_reg_map { /* Control register */ /** Disable backup domain write protection bit */ -#define PWR_CR_DBP 8 +#define PWR_CR_DBP_BIT 8 /** Power voltage detector enable bit */ -#define PWR_CR_PVDE 4 +#define PWR_CR_PVDE_BIT 4 /** Clear standby flag bit */ -#define PWR_CR_CSBF 3 +#define PWR_CR_CSBF_BIT 3 /** Clear wakeup flag bit */ -#define PWR_CR_CWUF 2 +#define PWR_CR_CWUF_BIT 2 /** Power down deepsleep bit */ -#define PWR_CR_PDDS 1 +#define PWR_CR_PDDS_BIT 1 /** Low-power deepsleep bit */ -#define PWR_CR_LPDS 0 +#define PWR_CR_LPDS_BIT 0 + +/** Disable backup domain write protection */ +#define PWR_CR_DBP (1U << PWR_CR_DBP_BIT) +/** Power voltage detector (PVD) level selection */ +#define PWR_CR_PLS (0x7 << 5) +/** Power voltage detector enable */ +#define PWR_CR_PVDE (1U << PWR_CR_PVDE_BIT) +/** Clear standby flag */ +#define PWR_CR_CSBF (1U << PWR_CR_CSBF_BIT) +/** Clear wakeup flag */ +#define PWR_CR_CWUF (1U << PWR_CR_CWUF_BIT) +/** Power down deepsleep */ +#define PWR_CR_PDDS (1U << PWR_CR_PDDS_BIT) +/** Low-power deepsleep */ +#define PWR_CR_LPDS (1U << PWR_CR_LPDS_BIT) /* Control and status register */ /** Enable wakeup pin bit */ -#define PWR_CSR_EWUP 8 +#define PWR_CSR_EWUP_BIT 8 /** PVD output bit */ -#define PWR_CSR_PVDO 2 +#define PWR_CSR_PVDO_BIT 2 /** Standby flag bit */ -#define PWR_CSR_SBF 1 +#define PWR_CSR_SBF_BIT 1 /** Wakeup flag bit */ -#define PWR_CSR_WUF 0 +#define PWR_CSR_WUF_BIT 0 + +/** Enable wakeup pin */ +#define PWR_CSR_EWUP (1U << PWR_CSR_EWUP_BIT) +/** PVD output */ +#define PWR_CSR_PVDO (1U << PWR_CSR_PVDO_BIT) +/** Standby flag */ +#define PWR_CSR_SBF (1U << PWR_CSR_SBF_BIT) +/** Wakeup flag */ +#define PWR_CSR_WUF (1U << PWR_CSR_WUF_BIT) /* * Convenience functions -- cgit v1.2.3 From 6dd3c2e202e46c843e00498f5d9a675cfa83522d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 19:34:04 -0400 Subject: Clean up rules.mk files. Alphabetize targets and remove continuation lines. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 2 +- libmaple/stm32f1/rules.mk | 8 ++++---- libmaple/stm32f2/rules.mk | 5 +++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 5675c1c..4c2a40f 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -17,9 +17,9 @@ cSRCS_$(d) += nvic.c cSRCS_$(d) += rcc.c cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c -cSRCS_$(d) += util.c cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c +cSRCS_$(d) += util.c sSRCS_$(d) := exc.S diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index b961d77..bdff00e 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -8,13 +8,13 @@ BUILDDIRS += $(BUILD_PATH)/$(d) CFLAGS_$(d) = -I$(d) $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets -sSRCS_$(d) := isrs_performance.S \ - vector_table_performance.S +sSRCS_$(d) := isrs_performance.S +sSRCS_$(d) += vector_table_performance.S -cSRCS_$(d) := rcc.c +cSRCS_$(d) := bkp.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c -cSRCS_$(d) += bkp.c +cSRCS_$(d) += rcc.c cSRCS_$(d) += usart.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 8711090..a46f8d1 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -8,11 +8,12 @@ BUILDDIRS += $(BUILD_PATH)/$(d) CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -Werror # Local rules and targets -sSRCS_$(d) := isrs.S vector_table.S +sSRCS_$(d) := isrs.S +sSRCS_$(d) += vector_table.S -cSRCS_$(d) := rcc.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c +cSRCS_$(d) += rcc.c cSRCS_$(d) += usart.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From bf0f839fb1d7d8075b148e2e6788479a36f56b7e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 19:39:49 -0400 Subject: Resurrect PWR support for F1 and F2. Just add the missing register bit definitions in new series headers. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/pwr.h | 1 + libmaple/rules.mk | 1 + libmaple/stm32f1/include/series/pwr.h | 52 +++++++++++++++++++++++++ libmaple/stm32f2/include/series/pwr.h | 73 +++++++++++++++++++++++++++++++++++ 4 files changed, 127 insertions(+) create mode 100644 libmaple/stm32f1/include/series/pwr.h create mode 100644 libmaple/stm32f2/include/series/pwr.h diff --git a/libmaple/include/libmaple/pwr.h b/libmaple/include/libmaple/pwr.h index 8841518..2611587 100644 --- a/libmaple/include/libmaple/pwr.h +++ b/libmaple/include/libmaple/pwr.h @@ -37,6 +37,7 @@ extern "C" { #endif #include +#include /** Power interface register map. */ typedef struct pwr_reg_map { diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 4c2a40f..b12e3ff 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -14,6 +14,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror cSRCS_$(d) := flash.c cSRCS_$(d) += gpio.c cSRCS_$(d) += nvic.c +cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c diff --git a/libmaple/stm32f1/include/series/pwr.h b/libmaple/stm32f1/include/series/pwr.h new file mode 100644 index 0000000..d13ffa7 --- /dev/null +++ b/libmaple/stm32f1/include/series/pwr.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f1/pwr.h + * @author Marti Bolivar + * @brief STM32F1 Power control (PWR) support. + */ + +#ifndef _LIBMAPLE_STM32F1_PWR_H_ +#define _LIBMAPLE_STM32F1_PWR_H_ + +/* + * Register bit definitions + */ + +/* Control register */ + +/* PVD level selection */ +#define PWR_CR_PLS_2_2V (0x0 << 5) +#define PWR_CR_PLS_2_3V (0x1 << 5) +#define PWR_CR_PLS_2_4V (0x2 << 5) +#define PWR_CR_PLS_2_5V (0x3 << 5) +#define PWR_CR_PLS_2_6V (0x4 << 5) +#define PWR_CR_PLS_2_7V (0x5 << 5) +#define PWR_CR_PLS_2_8V (0x6 << 5) +#define PWR_CR_PLS_2_9V (0x7 << 5) + +#endif diff --git a/libmaple/stm32f2/include/series/pwr.h b/libmaple/stm32f2/include/series/pwr.h new file mode 100644 index 0000000..dec2d76 --- /dev/null +++ b/libmaple/stm32f2/include/series/pwr.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f2/pwr.h + * @author Marti Bolivar + * @brief STM32F2 Power control (PWR) support. + */ + +#ifndef _LIBMAPLE_STM32F2_PWR_H_ +#define _LIBMAPLE_STM32F2_PWR_H_ + +/* + * Additional register bits + */ + +/* Control register */ + +/** + * @brief Flash power down in stop mode bit. + * Availability: STM32F2 */ +#define PWR_CR_FPDS_BIT 9 +/** + * @brief Flash power down in stop mode. + * Availability: STM32F2 */ +#define PWR_CR_FPDS (1U << PWR_CR_FPDS_BIT) + +/* PVD level selection */ +#define PWR_CR_PLS_2_0V (0x0 << 5) +#define PWR_CR_PLS_2_1V (0x1 << 5) +#define PWR_CR_PLS_2_3V (0x2 << 5) +#define PWR_CR_PLS_2_5V (0x3 << 5) +#define PWR_CR_PLS_2_6V (0x4 << 5) +#define PWR_CR_PLS_2_7V (0x5 << 5) +#define PWR_CR_PLS_2_8V (0x6 << 5) +#define PWR_CR_PLS_2_9V (0x7 << 5) + +/* Control/Status register */ + +/** Backup regulator enable bit. */ +#define PWR_CSR_BRE_BIT 9 +/** Backup regulator ready bit. */ +#define PWR_CSR_BRR_BIT 3 + +/** Backup regulator enable. */ +#define PWR_CSR_BRE (1U << PWR_CSR_BRE_BIT) +/** Backup regulator ready. */ +#define PWR_CSR_BRR (1U << PWR_CSR_BRR_BIT) + +#endif -- cgit v1.2.3 From 658068615dda2088c4198b3f1b4e2e8e8719c2a8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 19:51:39 -0400 Subject: Resurrect IWDG support. This peripheral is identical on F1 and F2. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/iwdg.h | 2 +- libmaple/rules.mk | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/iwdg.h b/libmaple/include/libmaple/iwdg.h index baddf4f..80202d2 100644 --- a/libmaple/include/libmaple/iwdg.h +++ b/libmaple/include/libmaple/iwdg.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file iwdg.h + * @file libmaple/iwdg.h * @author Michael Hope, Marti Bolivar * @brief Independent watchdog support. * diff --git a/libmaple/rules.mk b/libmaple/rules.mk index b12e3ff..24b3c0e 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -13,6 +13,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := flash.c cSRCS_$(d) += gpio.c +cSRCS_$(d) += iwdg.c cSRCS_$(d) += nvic.c cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c -- cgit v1.2.3 From d969ea5467101a8c03de9171a6444ce859c8da61 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 19:58:46 -0400 Subject: libmaple/rules.mk: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 24b3c0e..cc562ea 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -22,6 +22,14 @@ cSRCS_$(d) += systick.c cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c +# These still need to be ported to F2: +# cSRCS_$(d) += adc.c +# cSRCS_$(d) += dac.c +# cSRCS_$(d) += dma.c +# cSRCS_$(d) += exti.c +# cSRCS_$(d) += i2c.c +# cSRCS_$(d) += spi.c +# cSRCS_$(d) += timer.c sSRCS_$(d) := exc.S -- cgit v1.2.3 From 7a400b065167beda0a1a9c642954e08581bc0c29 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 4 Apr 2012 16:57:45 -0400 Subject: Add notes/stm32.txt. Some general notes on the various STM32 series. Signed-off-by: Marti Bolivar --- notes/stm32.txt | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 notes/stm32.txt diff --git a/notes/stm32.txt b/notes/stm32.txt new file mode 100644 index 0000000..106b369 --- /dev/null +++ b/notes/stm32.txt @@ -0,0 +1,63 @@ +STM32 platform notes. + +Most of this information comes from ST AN3427 (Migrating a +microcontroller application from STM32F1 to STM32F2 series) and ST +AN3364 (How to migrate across STM32 series). + +The STM32 series of MCUs is divided into series. At time of writing, +the available series are: + +- F1 series (STM32F1) +- L1 series (STM32L1) +- F2 series (STM32F2) +- F4 series (STM32F4) + +Some notes on the characteristics of, and differences between, the +series follow. + +F1 Series +--------- + +The STM32F1 series is further subdivided into a variety of somewhat +compatible "lines". Performance, value, and connectivity line MCUs are +available. (There's also an access line, which is ignored in these +notes). + +At time of writing, libmaple supports medium- and high-density +performance line MCUs. work to port it to other series is ongoing. + +Performance line MCU part numbers begin with STM32F101 or +STM32F103. The performance line is further subdivided into +"densities": low, medium, high, and XL. + +Value line MCU part numbers begin with STM32F100. Similarly to the +performance line, the value line is subdivided into medium and high +densities. + +Connectivity line MCU part numbers begin with STM32F105 or +STM32F107. Mercifully, these are not further subdivided by density. + +F2 Series +--------- + +A revamp of the F1 series, The F2 series address a number of the +STM32F1's deficiencies (both silicon bugs and unfortunate design +decisions), while maintaining a fair amount of software and pin +compatibility. + +The F2 series is most similar to the F1 connectivity line. Like the +connectivity line, STM32F2s come with a USB on-the-go full speed +peripheral (like the connectivity line), instead of USB full speed +device (like the performance line). + +F4 Series +--------- + +The F4 series MCUs are essentially equivalent to those in the F2 +series, except they have an ARM Cortex M4 core, an FPU, and support a +higher clock frequencies (168 MHz instead of 120 MHz). + +L1 Series +--------- + +This series is intended for low-power applications. -- cgit v1.2.3 From 28825b6a2f66b0329229185eb9cbd9004fae4b1b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 26 Mar 2012 22:17:47 -0400 Subject: Resurrect ADC support. Standard refactoring: add series headers for F1 and F2, along with series adc.c files. There are some issues relating to adc_extsel_event to hammer out later, but this will do for now. We also add some new portability interfaces to libmaple/adc.h in order for Wirish to use the same code to initialize the ADCs at init() time. As usual, F1 is untested. Signed-off-by: Marti Bolivar --- libmaple/adc.c | 74 +------- libmaple/include/libmaple/adc.h | 175 +++++++----------- libmaple/rules.mk | 4 +- libmaple/stm32f1/adc.c | 110 +++++++++++ libmaple/stm32f1/include/series/adc.h | 254 ++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 3 +- libmaple/stm32f2/adc.c | 84 +++++++++ libmaple/stm32f2/include/series/adc.h | 331 ++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + wirish/boards.cpp | 15 +- wirish/boards_private.h | 12 +- wirish/stm32f1/boards_setup.cpp | 39 ++-- wirish/stm32f2/boards_setup.cpp | 32 +++- 13 files changed, 920 insertions(+), 214 deletions(-) create mode 100644 libmaple/stm32f1/adc.c create mode 100644 libmaple/stm32f1/include/series/adc.h create mode 100644 libmaple/stm32f2/adc.c create mode 100644 libmaple/stm32f2/include/series/adc.h diff --git a/libmaple/adc.c b/libmaple/adc.c index 40369e9..acce923 100644 --- a/libmaple/adc.c +++ b/libmaple/adc.c @@ -25,44 +25,15 @@ *****************************************************************************/ /** - * @file adc.c - * + * @file libmaple/adc.c + * @author Marti Bolivar , + * Perry Hung * @brief Analog to digital converter routines - * - * IMPORTANT: maximum external impedance must be below 0.4kOhms for 1.5 - * sample conversion time. - * - * At 55.5 cycles/sample, the external input impedance < 50kOhms. - * - * See STM32 manual RM0008 for how to calculate this. */ +#include #include #include -#include - -static adc_dev adc1 = { - .regs = ADC1_BASE, - .clk_id = RCC_ADC1 -}; -/** ADC1 device. */ -const adc_dev *ADC1 = &adc1; - -static adc_dev adc2 = { - .regs = ADC2_BASE, - .clk_id = RCC_ADC2 -}; -/** ADC2 device. */ -const adc_dev *ADC2 = &adc2; - -#ifdef STM32_HIGH_DENSITY -adc_dev adc3 = { - .regs = ADC3_BASE, - .clk_id = RCC_ADC3 -}; -/** ADC3 device. */ -const adc_dev *ADC3 = &adc3; -#endif /** * @brief Initialize an ADC peripheral. @@ -91,20 +62,10 @@ void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) { } /** - * @brief Call a function on all ADC devices. - * @param fn Function to call on each ADC device. - */ -void adc_foreach(void (*fn)(const adc_dev*)) { - fn(ADC1); - fn(ADC2); -#ifdef STM32_HIGH_DENSITY - fn(ADC3); -#endif -} - -/** - * @brief Turn the given sample rate into values for ADC_SMPRx. Don't - * call this during conversion. + * @brief Set the sample rate for all channels on an ADC device. + * + * Don't call this during conversion. + * * @param dev adc device * @param smp_rate sample rate to set * @see adc_smp_rate @@ -126,26 +87,9 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) { dev->regs->SMPR2 = adc_smpr2_val; } -/** - * @brief Calibrate an ADC peripheral - * @param dev adc device - */ -void adc_calibrate(const adc_dev *dev) { - __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3); - __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2); - - *rstcal_bit = 1; - while (*rstcal_bit) - ; - - *cal_bit = 1; - while (*cal_bit) - ; -} - /** * @brief Perform a single synchronous software triggered conversion on a - * channel. + * channel. * @param dev ADC device to use for reading. * @param channel channel to convert * @return conversion result diff --git a/libmaple/include/libmaple/adc.h b/libmaple/include/libmaple/adc.h index d531d00..be29676 100644 --- a/libmaple/include/libmaple/adc.h +++ b/libmaple/include/libmaple/adc.h @@ -1,6 +1,7 @@ /****************************************************************************** * The MIT License * + * Copyright (c) 2012 LeafLabs, LLC. * Copyright (c) 2010 Perry Hung. * * Permission is hereby granted, free of charge, to any person @@ -25,9 +26,10 @@ *****************************************************************************/ /** - * @file adc.h - * - * @brief Analog-to-Digital Conversion (ADC) header. + * @file libmaple/adc.h + * @author Marti Bolivar , + * Perry Hung + * @brief Analog-to-Digital Conversion (ADC) header. */ #ifndef _LIBMAPLE_ADC_H_ @@ -40,6 +42,12 @@ extern "C"{ #include #include #include +/* We include the series header below, after defining the register map + * and device structs. */ + +/* + * Register map + */ /** ADC register map type. */ typedef struct adc_reg_map { @@ -71,24 +79,30 @@ typedef struct adc_dev { rcc_clk_id clk_id; /**< RCC clock information */ } adc_dev; -extern const adc_dev *ADC1; -extern const adc_dev *ADC2; -#ifdef STM32_HIGH_DENSITY -extern const adc_dev *ADC3; -#endif - -/* - * Register map base pointers +/* Pull in the series header (which may need the above struct + * definitions). + * + * IMPORTANT: The series header must define the following: + * + * - enum adc_extsel_event (and typedef to adc_extsel_event): One per + * external event used to trigger start of conversion of a regular + * group. If two different series support the same event as a + * trigger, they must use the same token for the enumerator for that + * event. (The value of the enumerator is of course allowed to be + * different). + * + * - enum adc_smp_rate (and typedef to adc_smp_rate): One per + * available sampling time. These must be in the form ADC_SMPR_X_Y + * for X.Y cycles (e.g. ADC_SMPR_1_5 means 1.5 cycles), or + * ADC_SMPR_X for X cycles (e.g. ADC_SMPR_3 means 3 cycles). + * + * - enum adc_prescaler (and typedef): One per available prescaler, + * suitable for adc_set_prescaler. Series which have the same + * prescaler dividers (e.g. STM32F1 and STM32F2 both divide PCLK2 by + * 2, 4, 6, or 8) must provide the same tokens as enumerators, for + * portability. */ - -/** ADC1 register map base pointer. */ -#define ADC1_BASE ((struct adc_reg_map*)0x40012400) -/** ADC2 register map base pointer. */ -#define ADC2_BASE ((struct adc_reg_map*)0x40012800) -#ifdef STM32_HIGH_DENSITY -/** ADC3 register map base pointer. */ -#define ADC3_BASE ((struct adc_reg_map*)0x40013C00) -#endif +#include /* * Register bit definitions @@ -136,31 +150,9 @@ extern const adc_dev *ADC3; /* Control register 2 */ -#define ADC_CR2_ADON_BIT 0 -#define ADC_CR2_CONT_BIT 1 -#define ADC_CR2_CAL_BIT 2 -#define ADC_CR2_RSTCAL_BIT 3 -#define ADC_CR2_DMA_BIT 8 -#define ADC_CR2_ALIGN_BIT 11 -#define ADC_CR2_JEXTTRIG_BIT 15 -#define ADC_CR2_EXTTRIG_BIT 20 -#define ADC_CR2_JSWSTART_BIT 21 -#define ADC_CR2_SWSTART_BIT 22 -#define ADC_CR2_TSEREFE_BIT 23 - -#define ADC_CR2_ADON BIT(ADC_CR2_ADON_BIT) -#define ADC_CR2_CONT BIT(ADC_CR2_CONT_BIT) -#define ADC_CR2_CAL BIT(ADC_CR2_CAL_BIT) -#define ADC_CR2_RSTCAL BIT(ADC_CR2_RSTCAL_BIT) -#define ADC_CR2_DMA BIT(ADC_CR2_DMA_BIT) -#define ADC_CR2_ALIGN BIT(ADC_CR2_ALIGN_BIT) -#define ADC_CR2_JEXTSEL (0x7000) -#define ADC_CR2_JEXTTRIG BIT(ADC_CR2_JEXTTRIG_BIT) -#define ADC_CR2_EXTSEL (0xE0000) -#define ADC_CR2_EXTTRIG BIT(ADC_CR2_EXTTRIG_BIT) -#define ADC_CR2_JSWSTART BIT(ADC_CR2_JSWSTART_BIT) -#define ADC_CR2_SWSTART BIT(ADC_CR2_SWSTART_BIT) -#define ADC_CR2_TSEREFE BIT(ADC_CR2_TSEREFE_BIT) +/* Because this register varies significantly by series (e.g. some + * bits moved and others disappeared in the F1->F2 transition), its + * definitions are in the series headers. */ /* Sample time register 1 */ @@ -245,68 +237,47 @@ extern const adc_dev *ADC3; #define ADC_DR_ADC2DATA (0xFFFF << 16) #define ADC_DR_DATA 0xFFFF -void adc_init(const adc_dev *dev); +/* + * Routines + */ /** - * @brief External event selector for regular group conversion. - * @see adc_set_extsel + * @brief Set the ADC prescaler. + * + * This determines the ADC clock for all devices. */ -typedef enum adc_extsel_event { - ADC_ADC12_TIM1_CC1 = (0 << 17), /**< ADC1 and ADC2: Timer 1 CC1 event */ - ADC_ADC12_TIM1_CC2 = (1 << 17), /**< ADC1 and ADC2: Timer 1 CC2 event */ - ADC_ADC12_TIM1_CC3 = (2 << 17), /**< ADC1 and ADC2: Timer 1 CC3 event */ - ADC_ADC12_TIM2_CC2 = (3 << 17), /**< ADC1 and ADC2: Timer 2 CC2 event */ - ADC_ADC12_TIM3_TRGO = (4 << 17), /**< ADC1 and ADC2: Timer 3 TRGO event */ - ADC_ADC12_TIM4_CC4 = (5 << 17), /**< ADC1 and ADC2: Timer 4 CC4 event */ - ADC_ADC12_EXTI11 = (6 << 17), /**< ADC1 and ADC2: EXTI11 event */ -#ifdef STM32_HIGH_DENSITY - ADC_ADC12_TIM8_TRGO = (6 << 17), /**< ADC1 and ADC2: Timer 8 TRGO - event (high density only) */ -#endif - ADC_ADC12_SWSTART = (7 << 17), /**< ADC1 and ADC2: Software start */ -#ifdef STM32_HIGH_DENSITY - ADC_ADC3_TIM3_CC1 = (0 << 17), /**< ADC3: Timer 3 CC1 event - (high density only) */ - ADC_ADC3_TIM2_CC3 = (1 << 17), /**< ADC3: Timer 2 CC3 event - (high density only) */ - ADC_ADC3_TIM1_CC3 = (2 << 17), /**< ADC3: Timer 1 CC3 event - (high density only) */ - ADC_ADC3_TIM8_CC1 = (3 << 17), /**< ADC3: Timer 8 CC1 event - (high density only) */ - ADC_ADC3_TIM8_TRGO = (4 << 17), /**< ADC3: Timer 8 TRGO event - (high density only) */ - ADC_ADC3_TIM5_CC1 = (5 << 17), /**< ADC3: Timer 5 CC1 event - (high density only) */ - ADC_ADC3_TIM5_CC3 = (6 << 17), /**< ADC3: Timer 5 CC3 event - (high density only) */ - ADC_ADC3_SWSTART = (7 << 17), /**< ADC3: Software start (high - density only) */ -#endif - ADC_SWSTART = (7 << 17) /**< ADC1, ADC2, ADC3: Software start */ -} adc_extsel_event; +void adc_set_prescaler(adc_prescaler pre); +void adc_init(const adc_dev *dev); void adc_set_extsel(const adc_dev *dev, adc_extsel_event event); +void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); +uint16 adc_read(const adc_dev *dev, uint8 channel); + +/** + * @brief Call a function on all ADC devices. + * @param fn Function to call on each ADC device. + */ void adc_foreach(void (*fn)(const adc_dev*)); /** - * @brief ADC sample times, in ADC clock cycles - * - * These control the amount of time spent sampling the input voltage. + * @brief Configure a GPIO pin for ADC conversion. + * @param gdev GPIO device to configure. + * @param bit Bit on gdev to configure for ADC conversion. */ -typedef enum { - ADC_SMPR_1_5, /**< 1.5 ADC cycles */ - ADC_SMPR_7_5, /**< 7.5 ADC cycles */ - ADC_SMPR_13_5, /**< 13.5 ADC cycles */ - ADC_SMPR_28_5, /**< 28.5 ADC cycles */ - ADC_SMPR_41_5, /**< 41.5 ADC cycles */ - ADC_SMPR_55_5, /**< 55.5 ADC cycles */ - ADC_SMPR_71_5, /**< 71.5 ADC cycles */ - ADC_SMPR_239_5 /**< 239.5 ADC cycles */ -} adc_smp_rate; +struct gpio_dev; +void adc_gpio_cfg(struct gpio_dev *gdev, uint8 bit); -void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); -void adc_calibrate(const adc_dev *dev); -uint16 adc_read(const adc_dev *dev, uint8 channel); +/** + * @brief Enable an ADC and configure it for single conversion mode. + * + * This function performs any initialization necessary to allow the + * ADC device to perform a single synchronous regular software + * triggered conversion, using adc_read(). + * + * @param dev Device to enable. + * @see adc_read() + */ +void adc_enable_single_swstart(const adc_dev* dev); /** * @brief Set the regular channel sequence length. @@ -324,16 +295,6 @@ static inline void adc_set_reg_seqlen(const adc_dev *dev, uint8 length) { dev->regs->SQR1 = tmp; } -/** - * @brief Set external trigger conversion mode event for regular channels - * @param dev ADC device - * @param enable If 1, conversion on external events is enabled; if 0, - * disabled. - */ -static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) { - *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable; -} - /** * @brief Enable an adc peripheral * @param dev ADC device to enable diff --git a/libmaple/rules.mk b/libmaple/rules.mk index cc562ea..d118b16 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -11,7 +11,8 @@ LIBMAPLE_PRIVATE_INCLUDES := -I$(LIBMAPLE_PATH) CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets -cSRCS_$(d) := flash.c +cSRCS_$(d) := adc.c +cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c cSRCS_$(d) += iwdg.c cSRCS_$(d) += nvic.c @@ -23,7 +24,6 @@ cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c # These still need to be ported to F2: -# cSRCS_$(d) += adc.c # cSRCS_$(d) += dac.c # cSRCS_$(d) += dma.c # cSRCS_$(d) += exti.c diff --git a/libmaple/stm32f1/adc.c b/libmaple/stm32f1/adc.c new file mode 100644 index 0000000..8242520 --- /dev/null +++ b/libmaple/stm32f1/adc.c @@ -0,0 +1,110 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/include/series/adc.c + * @brief STM32F1 ADC header. + */ + +#include +#include + +/* + * Devices + */ + +static adc_dev adc1 = { + .regs = ADC1_BASE, + .clk_id = RCC_ADC1 +}; +/** ADC1 device. */ +const adc_dev *ADC1 = &adc1; + +static adc_dev adc2 = { + .regs = ADC2_BASE, + .clk_id = RCC_ADC2 +}; +/** ADC2 device. */ +const adc_dev *ADC2 = &adc2; + +#ifdef STM32_HIGH_DENSITY +adc_dev adc3 = { + .regs = ADC3_BASE, + .clk_id = RCC_ADC3 +}; +/** ADC3 device. */ +const adc_dev *ADC3 = &adc3; +#endif + +/* + * STM32F1 routines + */ + +/** + * @brief Calibrate an ADC peripheral + * @param dev adc device + */ +void adc_calibrate(const adc_dev *dev) { + __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3); + __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2); + + *rstcal_bit = 1; + while (*rstcal_bit) + ; + + *cal_bit = 1; + while (*cal_bit) + ; +} + +/* + * Common routines + */ + +void adc_set_prescaler(adc_prescaler pre) { + rcc_set_prescaler(RCC_PRESCALER_ADC, (uint32)pre); +} + +void adc_foreach(void (*fn)(const adc_dev*)) { + fn(ADC1); + fn(ADC2); +#ifdef STM32_HIGH_DENSITY + fn(ADC3); +#endif +} + +void adc_gpio_cfg(gpio_dev *gdev, uint8 bit) { + gpio_set_mode(gdev, bit, GPIO_INPUT_ANALOG); +} + +void adc_enable_single_swstart(const adc_dev *dev) { + adc_init(dev); + adc_set_extsel(dev, ADC_SWSTART); + adc_set_exttrig(dev, 1); + adc_enable(dev); + adc_calibrate(dev); +} diff --git a/libmaple/stm32f1/include/series/adc.h b/libmaple/stm32f1/include/series/adc.h new file mode 100644 index 0000000..1798e55 --- /dev/null +++ b/libmaple/stm32f1/include/series/adc.h @@ -0,0 +1,254 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f1/include/series/adc.h + * @author Marti Bolivar , + * Perry Hung + * @brief STM32F1 ADC header. + */ + +#ifndef _LIBMAPLE_STM32F1_ADC_H_ +#define _LIBMAPLE_STM32F1_ADC_H_ + +#include /* For the prescalers */ + +/* + * Devices + */ + +extern const struct adc_dev *ADC1; +extern const struct adc_dev *ADC2; +#ifdef STM32_HIGH_DENSITY +extern const struct adc_dev *ADC3; +#endif + +/* + * Register map base pointers + */ + +/** ADC1 register map base pointer. */ +#define ADC1_BASE ((struct adc_reg_map*)0x40012400) +/** ADC2 register map base pointer. */ +#define ADC2_BASE ((struct adc_reg_map*)0x40012800) +#ifdef STM32_HIGH_DENSITY +/** ADC3 register map base pointer. */ +#define ADC3_BASE ((struct adc_reg_map*)0x40013C00) +#endif + +/* + * Register bit definitions + */ + +/* Control register 2 */ + +#define ADC_CR2_ADON_BIT 0 +#define ADC_CR2_CONT_BIT 1 +#define ADC_CR2_CAL_BIT 2 +#define ADC_CR2_RSTCAL_BIT 3 +#define ADC_CR2_DMA_BIT 8 +#define ADC_CR2_ALIGN_BIT 11 +#define ADC_CR2_JEXTTRIG_BIT 15 +#define ADC_CR2_EXTTRIG_BIT 20 +#define ADC_CR2_JSWSTART_BIT 21 +#define ADC_CR2_SWSTART_BIT 22 +#define ADC_CR2_TSEREFE_BIT 23 + +#define ADC_CR2_ADON (1U << ADC_CR2_ADON_BIT) +#define ADC_CR2_CONT (1U << ADC_CR2_CONT_BIT) +#define ADC_CR2_CAL (1U << ADC_CR2_CAL_BIT) +#define ADC_CR2_RSTCAL (1U << ADC_CR2_RSTCAL_BIT) +#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT) +#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT) +#define ADC_CR2_JEXTSEL 0x7000 +#define ADC_CR2_JEXTTRIG (1U << ADC_CR2_JEXTTRIG_BIT) +#define ADC_CR2_EXTSEL 0xE0000 +#define ADC_CR2_EXTTRIG (1U << ADC_CR2_EXTTRIG_BIT) +#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT) +#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT) +#define ADC_CR2_TSEREFE (1U << ADC_CR2_TSEREFE_BIT) + +/* + * Other types + */ + +/** + * @brief STM32F1 external event selectors for regular group + * conversion. + * + * Some external events are only available on ADCs 1 and 2, others + * only on ADC3, while others are available on all three ADCs. + * Additionally, some events are only available on high- and + * XL-density STM32F1 MCUs, as they use peripherals only available on + * those MCU densities. + * + * For ease of use, each event selector is given along with the ADCs + * it's available on, along with any other availability restrictions. + * + * @see adc_set_extsel() + */ +typedef enum adc_extsel_event { + /* TODO: Smarten this up a bit, as follows. + * + * The EXTSEL bits on F1 are a little brain-damaged in that the + * TIM8 TRGO event has different bits depending on whether you're + * using ADC1/2 or ADC3. We route around this by declaring two + * enumerators, ADC_EXT_EV_ADC12_TIM8_TRGO and + * ADC_EXT_EV_ADC3_TIM8_TRGO. + * + * The right thing to do is to provide a single + * ADC_EXT_EV_TIM8_TRGO enumerator and override adc_set_extsel on + * STM32F1 to handle this situation correctly. We can do that + * later, though, and change the per-ADC enumerator values to + * ADC_EXT_EV_TIM8_TRGO to preserve compatibility. */ + + /* ADC1 and ADC2 only: */ + ADC_EXT_EV_TIM1_CC1 = 0x00000, /**< ADC1, ADC2: Timer 1 CC1 event */ + ADC_EXT_EV_TIM1_CC2 = 0x20000, /**< ADC1, ADC2: Timer 1 CC2 event */ + ADC_EXT_EV_TIM2_CC2 = 0x60000, /**< ADC1, ADC2: Timer 2 CC2 event */ + ADC_EXT_EV_TIM3_TRGO = 0x80000, /**< ADC1, ADC2: Timer 3 TRGO event */ + ADC_EXT_EV_TIM4_CC4 = 0xA0000, /**< ADC1, ADC2: Timer 4 CC4 event */ + ADC_EXT_EV_EXTI11 = 0xC0000, /**< ADC1, ADC2: EXTI11 event */ + + /* Common: */ + ADC_EXT_EV_TIM1_CC3 = 0x40000, /**< ADC1, ADC2, ADC3: Timer 1 CC3 event */ + ADC_EXT_EV_SWSTART = 0xE0000, /**< ADC1, ADC2, ADC3: Software start */ + + /* HD only: */ + ADC_EXT_EV_TIM3_CC1 = 0x00000, /**< + * ADC3: Timer 3 CC1 event + * Availability: high- and XL-density. */ + ADC_EXT_EV_TIM2_CC3 = 0x20000, /**< + * ADC3: Timer 2 CC3 event + * Availability: high- and XL-density. */ + ADC_EXT_EV_TIM8_CC1 = 0x60000, /**< + * ADC3: Timer 8 CC1 event + * Availability: high- and XL-density. */ + ADC_EXT_EV_ADC3_TIM8_TRGO = 0x80000, /**< + * ADC3: Timer 8 TRGO event + * Availability: high- and XL-density. */ + ADC_EXT_EV_TIM5_CC1 = 0xA0000, /**< + * ADC3: Timer 5 CC1 event + * Availability: high- and XL-density. */ + ADC_EXT_EV_ADC12_TIM8_TRGO = 0xC0000, /**< + * ADC1, ADC2: Timer 8 TRGO event + * Availability: high- and XL-density. */ + ADC_EXT_EV_TIM5_CC3 = 0xC0000, /**< + * ADC3: Timer 5 CC3 event + * Availability: high- and XL-density. */ +} adc_extsel_event; + +/* We'll keep these old adc_extsel_event enumerators around for a + * while, for backwards compatibility: */ +/** Deprecated. Use ADC_EXT_EV_TIM1_CC1 instead. */ +#define ADC_ADC12_TIM1_CC1 ADC_EXT_EV_TIM1_CC1 +/** Deprecated. Use ADC_EXT_EV_TIM1_CC2 instead. */ +#define ADC_ADC12_TIM1_CC2 ADC_EXT_EV_TIM1_CC2 +/** Deprecated. Use ADC_EXT_EV_TIM1_CC3 instead. */ +#define ADC_ADC12_TIM1_CC3 ADC_EXT_EV_TIM1_CC3 +/** Deprecated. Use ADC_EXT_EV_TIM2_CC2 instead. */ +#define ADC_ADC12_TIM2_CC2 ADC_EXT_EV_TIM2_CC2 +/** Deprecated. Use ADC_EXT_EV_TIM3_TRGO instead. */ +#define ADC_ADC12_TIM3_TRGO ADC_EXT_EV_TIM3_TRGO +/** Deprecated. Use ADC_EXT_EV_TIM4_CC4 instead. */ +#define ADC_ADC12_TIM4_CC4 ADC_EXT_EV_TIM4_CC4 +/** Deprecated. Use ADC_EXT_EV_EXTI11 instead. */ +#define ADC_ADC12_EXTI11 ADC_EXT_EV_EXTI11 +/** Deprecated. Use ADC_EXT_EV_ADC12_TIM8_TRGO instead. */ +#define ADC_ADC12_TIM8_TRGO ADC_EXT_EV_ADC12_TIM8_TRGO +/** Deprecated. Use ADC_EXT_EV_SWSTART instead. */ +#define ADC_ADC12_SWSTART ADC_EXT_EV_SWSTART +/** Deprecated. Use ADC_EXT_EV_TIM1_CC1 instead. */ +#define ADC_ADC3_TIM3_CC1 ADC_EXT_EV_TIM1_CC1 +/** Deprecated. Use ADC_EXT_EV_TIM1_CC2 instead. */ +#define ADC_ADC3_TIM2_CC3 ADC_EXT_EV_TIM1_CC2 +/** Deprecated. Use ADC_EXT_EV_TIM1_CC3 instead. */ +#define ADC_ADC3_TIM1_CC3 ADC_EXT_EV_TIM1_CC3 +/** Deprecated. Use ADC_EXT_EV_TIM2_CC2 instead. */ +#define ADC_ADC3_TIM8_CC1 ADC_EXT_EV_TIM2_CC2 +/** Deprecated. Use ADC_EXT_EV_TIM3_TRGO instead. */ +#define ADC_ADC3_TIM8_TRGO ADC_EXT_EV_TIM3_TRGO +/** Deprecated. Use ADC_EXT_EV_TIM4_CC4 instead. */ +#define ADC_ADC3_TIM5_CC1 ADC_EXT_EV_TIM4_CC4 +/** Deprecated. Use ADC_EXT_EV_EXTI11 instead. */ +#define ADC_ADC3_TIM5_CC3 ADC_EXT_EV_EXTI11 +/** Deprecated. Use ADC_EXT_EV_TIM8_TRGO instead. */ +#define ADC_ADC3_SWSTART ADC_EXT_EV_TIM8_TRGO +/** Deprecated. Use ADC_EXT_EV_SWSTART instead. */ +#define ADC_SWSTART ADC_EXT_EV_SWSTART + +/** + * @brief STM32F1 sample times, in ADC clock cycles. + * + * These control the amount of time spent sampling the input voltage. + * + * IMPORTANT: maximum external impedance must be below 0.4kOhms for + * 1.5 cycle sampling time. At 55.5 cycles/sample, the external input + * impedance must be at most 50kOhms. See your device's datasheet for + * more information. + */ +typedef enum adc_smp_rate { + ADC_SMPR_1_5, /**< 1.5 ADC cycles */ + ADC_SMPR_7_5, /**< 7.5 ADC cycles */ + ADC_SMPR_13_5, /**< 13.5 ADC cycles */ + ADC_SMPR_28_5, /**< 28.5 ADC cycles */ + ADC_SMPR_41_5, /**< 41.5 ADC cycles */ + ADC_SMPR_55_5, /**< 55.5 ADC cycles */ + ADC_SMPR_71_5, /**< 71.5 ADC cycles */ + ADC_SMPR_239_5, /**< 239.5 ADC cycles */ +} adc_smp_rate; + +/** + * @brief STM32F1 ADC prescalers, as divisors of PCLK2. + */ +typedef enum adc_prescaler { + ADC_PRE_PCLK2_DIV_2 = RCC_ADCPRE_PCLK_DIV_2, /** PCLK2 divided by 2 */ + ADC_PRE_PCLK2_DIV_4 = RCC_ADCPRE_PCLK_DIV_4, /** PCLK2 divided by 4 */ + ADC_PRE_PCLK2_DIV_6 = RCC_ADCPRE_PCLK_DIV_6, /** PCLK2 divided by 6 */ + ADC_PRE_PCLK2_DIV_8 = RCC_ADCPRE_PCLK_DIV_8, /** PCLK2 divided by 8 */ +} adc_prescaler; + +/* + * Routines + */ + +void adc_calibrate(const adc_dev *dev); + +/** + * @brief Set external trigger conversion mode event for regular channels + * + * Availability: STM32F1. + * + * @param dev ADC device + * @param enable If 1, conversion on external events is enabled; if 0, + * disabled. + */ +static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) { + *bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable; +} + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index bdff00e..c0d6344 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -11,7 +11,8 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -We sSRCS_$(d) := isrs_performance.S sSRCS_$(d) += vector_table_performance.S -cSRCS_$(d) := bkp.c +cSRCS_$(d) := adc.c +cSRCS_$(d) += bkp.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c diff --git a/libmaple/stm32f2/adc.c b/libmaple/stm32f2/adc.c new file mode 100644 index 0000000..fbe1618 --- /dev/null +++ b/libmaple/stm32f2/adc.c @@ -0,0 +1,84 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/include/series/adc.c + * @brief STM32F2 ADC header. + */ + +#include +#include + +/* + * Devices + */ + +static adc_dev adc1 = { + .regs = ADC1_BASE, + .clk_id = RCC_ADC1, +}; +/** ADC1 device. */ +const adc_dev *ADC1 = &adc1; + +static adc_dev adc2 = { + .regs = ADC2_BASE, + .clk_id = RCC_ADC2, +}; +/** ADC2 device. */ +const adc_dev *ADC2 = &adc2; + +adc_dev adc3 = { + .regs = ADC3_BASE, + .clk_id = RCC_ADC3, +}; +/** ADC3 device. */ +const adc_dev *ADC3 = &adc3; + +/* + * Common routines + */ + +void adc_set_prescaler(adc_prescaler pre) { + uint32 ccr = ADC_COMMON_BASE->CCR; + ccr &= ~ADC_CCR_ADCPRE; + ccr |= (uint32)pre; + ADC_COMMON_BASE->CCR = ccr; +} + +void adc_foreach(void (*fn)(const adc_dev*)) { + fn(ADC1); + fn(ADC2); + fn(ADC3); +} + +void adc_gpio_cfg(gpio_dev *gdev, uint8 bit) { + gpio_set_modef(gdev, bit, GPIO_MODE_ANALOG, GPIO_MODEF_PUPD_NONE); +} + +void adc_enable_single_swstart(const adc_dev *dev) { + adc_init(dev); + adc_enable(dev); +} diff --git a/libmaple/stm32f2/include/series/adc.h b/libmaple/stm32f2/include/series/adc.h new file mode 100644 index 0000000..4f0cd6b --- /dev/null +++ b/libmaple/stm32f2/include/series/adc.h @@ -0,0 +1,331 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f2/include/series/adc.h + * @author Marti Bolivar , + * @brief STM32F2 ADC header. + */ + +#ifndef _LIBMAPLE_STM32F2_ADC_H_ +#define _LIBMAPLE_STM32F2_ADC_H_ + +#include + +/* + * Devices + */ + +extern const struct adc_dev *ADC1; +extern const struct adc_dev *ADC2; +extern const struct adc_dev *ADC3; + +/* + * Common register map + */ + +/** ADC common register map type */ +typedef struct adc_common_reg_map { + __io uint32 CSR; /**< Common status register */ + __io uint32 CCR; /**< Common control register */ + __io uint32 CDR; /**< + * @brief Common regular data register + * for dual and triple modes */ +} adc_common_reg_map; + +/* + * Register map base pointers + */ + +/** ADC1 register map base pointer. */ +#define ADC1_BASE ((struct adc_reg_map*)0x40012000) +/** ADC2 register map base pointer. */ +#define ADC2_BASE ((struct adc_reg_map*)0x40012100) +/** ADC3 register map base pointer. */ +#define ADC3_BASE ((struct adc_reg_map*)0x40012200) +/** ADC common register map base pointer. */ +#define ADC_COMMON_BASE ((struct adc_common_reg_map*)0x40012300) + +/* + * Register bit definitions + */ + +/* Status register */ + +/** Overrun bit. */ +#define ADC_SR_OVR_BIT 5 +/** Overrun. */ +#define ADC_SR_OVR (1U << ADC_SR_OVR_BIT) + +/* Control register 1 */ + +/** Overrun interrupt enable bit. */ +#define ADC_CR1_OVRIE_BIT 26 + +/** Overrun interrupt error enable. */ +#define ADC_CR1_OVRIE (1U << ADC_CR1_OVRIE_BIT) +/** Conversion resolution. */ +#define ADC_CR1_RES (0x3U << 24) +/** Conversion resolution: 12 bit (at least 15 ADCCLK cycles). */ +#define ADC_CR1_RES_12BIT (0x0U << 24) +/** Conversion resolution: 10 bit (at least 13 ADCCLK cycles). */ +#define ADC_CR1_RES_10BIT (0x1U << 24) +/** Conversion resolution: 8 bit (at least 11 ADCCLK cycles). */ +#define ADC_CR1_RES_8BIT (0x2U << 24) +/** Conversion resolution: 6 bit (at least 9 ADCCLK cycles). */ +#define ADC_CR1_RES_6BIT (0x3U << 24) + +/* Control register 2 */ + +#define ADC_CR2_SWSTART_BIT 30 +#define ADC_CR2_JSWSTART_BIT 22 +#define ADC_CR2_ALIGN_BIT 11 +#define ADC_CR2_EOCS_BIT 10 +#define ADC_CR2_DDS_BIT 9 +#define ADC_CR2_DMA_BIT 8 +#define ADC_CR2_CONT_BIT 1 +#define ADC_CR2_ADON_BIT 0 + +#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT) +#define ADC_CR2_EXTEN (0x3 << 28) +#define ADC_CR2_EXTEN_DISABLED (0x0 << 28) +#define ADC_CR2_EXTEN_RISE (0x1 << 28) +#define ADC_CR2_EXTEN_FALL (0x2 << 28) +#define ADC_CR2_EXTEN_RISE_FALL (0x3 << 28) +#define ADC_CR2_EXTSEL (0xF << 24) +#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) +#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) +#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) +#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) +#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) +#define ADC_CR2_EXTSEL_TIM1_TRGO (0x6 << 24) +#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) +#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) +#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) +#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) +#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) +#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) +#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) +#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) +#define ADC_CR2_EXTSEL_TIM1_EXTI11 (0xF << 24) +#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT) +#define ADC_CR2_JEXTEN (0x3 << 20) +#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) +#define ADC_CR2_JEXTEN_RISE (0x1 << 20) +#define ADC_CR2_JEXTEN_FALL (0x2 << 20) +#define ADC_CR2_JEXTEN_RISE_FALL (0x3 << 20) +#define ADC_CR2_JEXTSEL (0xF << 16) +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) +#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) +#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) +#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) +#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) +#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) +#define ADC_CR2_JEXTSEL_TIM1_EXTI15 (0xF << 16) +#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT) +#define ADC_CR2_ALIGN_RIGHT (0U << ADC_CR2_ALIGN_BIT) +#define ADC_CR2_ALIGN_LEFT (1U << ADC_CR2_ALIGN_BIT) +#define ADC_CR2_EOCS (1U << ADC_CR2_EOCS_BIT) +#define ADC_CR2_EOCS_SEQUENCE (0U << ADC_CR2_EOCS_BIT) +#define ADC_CR2_EOCS_CONVERSION (1U << ADC_CR2_EOCS_BIT) +#define ADC_CR2_DDS (1U << ADC_CR2_DDS_BIT) +#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT) +#define ADC_CR2_CONT (1U << ADC_CR2_CONT_BIT) +#define ADC_CR2_ADON (1U << ADC_CR2_ADON_BIT) + +/* Common status register */ + +#define ADC_CSR_OVR3_BIT 21 +#define ADC_CSR_STRT3_BIT 20 +#define ADC_CSR_JSTRT3_BIT 19 +#define ADC_CSR_JEOC3_BIT 18 +#define ADC_CSR_EOC3_BIT 17 +#define ADC_CSR_AWD3_BIT 16 +#define ADC_CSR_OVR2_BIT 13 +#define ADC_CSR_STRT2_BIT 12 +#define ADC_CSR_JSTRT2_BIT 11 +#define ADC_CSR_JEOC2_BIT 10 +#define ADC_CSR_EOC2_BIT 9 +#define ADC_CSR_AWD2_BIT 8 +#define ADC_CSR_OVR1_BIT 5 +#define ADC_CSR_STRT1_BIT 4 +#define ADC_CSR_JSTRT1_BIT 3 +#define ADC_CSR_JEOC1_BIT 2 +#define ADC_CSR_EOC1_BIT 1 +#define ADC_CSR_AWD1_BIT 0 + +#define ADC_CSR_OVR3 (1U << ADC_CSR_OVR3_BIT) +#define ADC_CSR_STRT3 (1U << ADC_CSR_STRT3_BIT) +#define ADC_CSR_JSTRT3 (1U << ADC_CSR_JSTRT3_BIT) +#define ADC_CSR_JEOC3 (1U << ADC_CSR_JEOC3_BIT) +#define ADC_CSR_EOC3 (1U << ADC_CSR_EOC3_BIT) +#define ADC_CSR_AWD3 (1U << ADC_CSR_AWD3_BIT) +#define ADC_CSR_OVR2 (1U << ADC_CSR_OVR2_BIT) +#define ADC_CSR_STRT2 (1U << ADC_CSR_STRT2_BIT) +#define ADC_CSR_JSTRT2 (1U << ADC_CSR_JSTRT2_BIT) +#define ADC_CSR_JEOC2 (1U << ADC_CSR_JEOC2_BIT) +#define ADC_CSR_EOC2 (1U << ADC_CSR_EOC2_BIT) +#define ADC_CSR_AWD2 (1U << ADC_CSR_AWD2_BIT) +#define ADC_CSR_OVR1 (1U << ADC_CSR_OVR1_BIT) +#define ADC_CSR_STRT1 (1U << ADC_CSR_STRT1_BIT) +#define ADC_CSR_JSTRT1 (1U << ADC_CSR_JSTRT1_BIT) +#define ADC_CSR_JEOC1 (1U << ADC_CSR_JEOC1_BIT) +#define ADC_CSR_EOC1 (1U << ADC_CSR_EOC1_BIT) +#define ADC_CSR_AWD1 (1U << ADC_CSR_AWD1_BIT) + +/* Common control register */ + +#define ADC_CCR_TSVREFE_BIT 23 +#define ADC_CCR_VBATE_BIT 22 +#define ADC_CCR_DDS_BIT 13 + +#define ADC_CCR_TSVREFE (1U << ADC_CCR_TSVREFE_BIT) +#define ADC_CCR_VBATE (1U << ADC_CCR_VBATE_BIT) +#define ADC_CCR_ADCPRE (0x3 << 16) +#define ADC_CCR_ADCPRE_PCLK2_DIV_2 (0x0 << 16) +#define ADC_CCR_ADCPRE_PCLK2_DIV_4 (0x1 << 16) +#define ADC_CCR_ADCPRE_PCLK2_DIV_6 (0x2 << 16) +#define ADC_CCR_ADCPRE_PCLK2_DIV_8 (0x3 << 16) +#define ADC_CCR_DMA (0x3 << 14) +#define ADC_CCR_DMA_DIS (0x0 << 14) +#define ADC_CCR_DMA_MODE_1 (0x1 << 14) +#define ADC_CCR_DMA_MODE_2 (0x2 << 14) +#define ADC_CCR_DMA_MODE_3 (0x3 << 14) +#define ADC_CCR_DDS (1U << ADC_CCR_DDS_BIT) +#define ADC_CCR_DELAY (0xF << 8) +#define ADC_CCR_DELAY_5 (0x0 << 8) +#define ADC_CCR_DELAY_6 (0x1 << 8) +#define ADC_CCR_DELAY_7 (0x2 << 8) +#define ADC_CCR_DELAY_8 (0x3 << 8) +#define ADC_CCR_DELAY_9 (0x4 << 8) +#define ADC_CCR_DELAY_10 (0x5 << 8) +#define ADC_CCR_DELAY_11 (0x6 << 8) +#define ADC_CCR_DELAY_12 (0x7 << 8) +#define ADC_CCR_DELAY_13 (0x8 << 8) +#define ADC_CCR_DELAY_14 (0x9 << 8) +#define ADC_CCR_DELAY_15 (0xA << 8) +#define ADC_CCR_DELAY_16 (0xB << 8) +#define ADC_CCR_DELAY_17 (0xC << 8) +#define ADC_CCR_DELAY_18 (0xD << 8) +#define ADC_CCR_DELAY_19 (0xE << 8) +#define ADC_CCR_DELAY_20 (0xF << 8) +/** Multi ADC mode selection. */ +#define ADC_CCR_MULTI 0x1F +/** All ADCs independent. */ +#define ADC_CCR_MULTI_INDEPENDENT 0x0 +/** Dual mode: combined regular simultaneous/injected simultaneous. */ +#define ADC_CCR_MULTI_DUAL_REG_SIM_INJ_SIM 0x1 +/** Dual mode: combined regular simultaneous/alternate trigger. */ +#define ADC_CCR_MULTI_DUAL_REG_SIM_ALT_TRIG 0x2 +/** Dual mode: injected simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_INJ_SIM 0x5 +/** Dual mode: regular simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_REG_SIM 0x6 +/** Dual mode: interleaved mode only. */ +#define ADC_CCR_MULTI_DUAL_INTER 0x7 +/** Dual mode: alternate trigger mode only. */ +#define ADC_CCR_MULTI_DUAL_ALT_TRIG 0x9 +/** Triple mode: combined regular simultaneous/injected simultaneous. */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIM_INJ_SIM 0x10 +/** Triple mode: combined regular simultaneous/alternate trigger. */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIM_ALT_TRIG 0x11 +/** Triple mode: injected simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INJ_SIM 0x12 +/** Triple mode: regular simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIM 0x15 +/** Triple mode: interleaved mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INTER 0x17 +/** Triple mode: alternate trigger mode only. */ +#define ADC_CCR_MULTI_TRIPLE_ALT_TRIG 0x19 + +/* Common regular data register for dual and triple modes */ + +#define ADC_CDR_DATA2 0xFFFF0000 +#define ADC_CDR_DATA1 0xFFFF + +/* + * Other types + */ + +/** + * @brief STM32F2 external event selectors for regular group + * conversion. + * @see adc_set_extsel() + */ +typedef enum adc_extsel_event { + ADC_EXT_EV_TIM1_CC1 = ADC_CR2_EXTSEL_TIM1_CC1, + ADC_EXT_EV_TIM1_CC2 = ADC_CR2_EXTSEL_TIM1_CC2, + ADC_EXT_EV_TIM1_CC3 = ADC_CR2_EXTSEL_TIM1_CC3, + ADC_EXT_EV_TIM2_CC2 = ADC_CR2_EXTSEL_TIM2_CC2, + ADC_EXT_EV_TIM2_CC3 = ADC_CR2_EXTSEL_TIM2_CC3, + ADC_EXT_EV_TIM2_CC4 = ADC_CR2_EXTSEL_TIM2_CC4, + ADC_EXT_EV_TIM1_TRGO = ADC_CR2_EXTSEL_TIM1_TRGO, + ADC_EXT_EV_TIM3_CC1 = ADC_CR2_EXTSEL_TIM3_CC1, + ADC_EXT_EV_TIM3_TRGO = ADC_CR2_EXTSEL_TIM3_TRGO, + ADC_EXT_EV_TIM4_CC4 = ADC_CR2_EXTSEL_TIM4_CC4, + ADC_EXT_EV_TIM5_CC1 = ADC_CR2_EXTSEL_TIM5_CC1, + ADC_EXT_EV_TIM5_CC2 = ADC_CR2_EXTSEL_TIM5_CC2, + ADC_EXT_EV_TIM5_CC3 = ADC_CR2_EXTSEL_TIM5_CC3, + ADC_EXT_EV_TIM8_CC1 = ADC_CR2_EXTSEL_TIM8_CC1, + ADC_EXT_EV_TIM8_TRGO = ADC_CR2_EXTSEL_TIM8_TRGO, + ADC_EXT_EV_TIM1_EXTI11 = ADC_CR2_EXTSEL_TIM1_EXTI11, +} adc_extsel_event; + +/** + * @brief STM32F2 sample times, in ADC clock cycles. + */ +typedef enum adc_smp_rate { + ADC_SMPR_3, /**< 3 ADC cycles */ + ADC_SMPR_15, /**< 15 ADC cycles */ + ADC_SMPR_28, /**< 28 ADC cycles */ + ADC_SMPR_56, /**< 56 ADC cycles */ + ADC_SMPR_84, /**< 84 ADC cycles */ + ADC_SMPR_112, /**< 112 ADC cycles */ + ADC_SMPR_144, /**< 144 ADC cycles */ + ADC_SMPR_480, /**< 480 ADC cycles */ +} adc_smp_rate; + +/** + * @brief STM32F2 ADC prescalers, as divisors of PCLK2. + */ +typedef enum adc_prescaler { + ADC_PRE_PCLK2_DIV_2 = ADC_CCR_ADCPRE_PCLK2_DIV_2, /** PCLK2 divided by 2 */ + ADC_PRE_PCLK2_DIV_4 = ADC_CCR_ADCPRE_PCLK2_DIV_4, /** PCLK2 divided by 4 */ + ADC_PRE_PCLK2_DIV_6 = ADC_CCR_ADCPRE_PCLK2_DIV_6, /** PCLK2 divided by 6 */ + ADC_PRE_PCLK2_DIV_8 = ADC_CCR_ADCPRE_PCLK2_DIV_8, /** PCLK2 divided by 8 */ +} adc_prescaler; + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index a46f8d1..5951b94 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -11,6 +11,7 @@ CFLAGS_$(d) = -I$(d) $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall -We sSRCS_$(d) := isrs.S sSRCS_$(d) += vector_table.S +cSRCS_$(d) := adc.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 04b359f..54807d3 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -54,6 +54,7 @@ static void setup_flash(void); static void setup_clocks(void); static void setup_nvic(void); +static void setup_adcs(void); /* * Exported functions @@ -65,7 +66,7 @@ void init(void) { setup_nvic(); systick_init(SYSTICK_RELOAD_VAL); wirish::priv::board_setup_gpio(); - wirish::priv::board_setup_adc(); + setup_adcs(); wirish::priv::board_setup_timers(); wirish::priv::board_setup_usb(); boardInit(); @@ -124,7 +125,7 @@ static void setup_clocks(void) { // Configure AHBx, APBx, etc. prescalers and the main PLL. wirish::priv::board_setup_clock_prescalers(); - rcc_configure_pll(&wirish::priv::board_pll_cfg); + rcc_configure_pll(&wirish::priv::w_board_pll_cfg); // Enable the PLL, and wait until it's ready. rcc_turn_on_clk(RCC_CLK_PLL); @@ -146,3 +147,13 @@ static void setup_nvic(void) { #error "You must select a base address for the vector table." #endif } + +static void adc_default_config(const adc_dev *dev) { + adc_enable_single_swstart(dev); + adc_set_sample_rate(dev, wirish::priv::w_adc_smp); +} + +static void setup_adcs(void) { + adc_set_prescaler(wirish::priv::w_adc_pre); + adc_foreach(adc_default_config); +} diff --git a/wirish/boards_private.h b/wirish/boards_private.h index a4101c9..e32f298 100644 --- a/wirish/boards_private.h +++ b/wirish/boards_private.h @@ -28,11 +28,18 @@ * @file wirish/boards_private.h * @author Marti Bolivar * @brief Private board support header. + * + * This file declares chip-specific variables and functions which + * determine how init() behaves. It is not part of the public Wirish + * API, and can change without notice. */ #ifndef _WIRISH_BOARDS_PRIVATE_H_ #define _WIRISH_BOARDS_PRIVATE_H_ +#include +#include + namespace wirish { namespace priv { @@ -40,7 +47,9 @@ namespace wirish { * Chip-specific initialization data */ - extern rcc_pll_cfg board_pll_cfg; + extern rcc_pll_cfg w_board_pll_cfg; + extern adc_prescaler w_adc_pre; + extern adc_smp_rate w_adc_smp; /* * Chip-specific initialization routines and helper functions. @@ -49,7 +58,6 @@ namespace wirish { void board_reset_pll(void); void board_setup_clock_prescalers(void); void board_setup_gpio(void); - void board_setup_adc(void); void board_setup_timers(void); void board_setup_usb(void); diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index 4ee292a..8e16009 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -28,11 +28,15 @@ * @file wirish/stm32f1/boards_setup.cpp * @author Marti Bolivar * @brief STM32F1 chip setup. + * + * This file controls how init() behaves on the STM32F1. Be very + * careful when changing anything here. Many of these values depend + * upon each other. */ -#include +#include "boards_private.h" + #include -#include #include #include @@ -45,12 +49,11 @@ namespace wirish { namespace priv { static stm32f1_rcc_pll_data pll_data = {RCC_PLLMUL_9}; - rcc_pll_cfg board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6; + adc_smp_rate w_adc_smp = ADC_SMPR_55_5; -#if 0 - static void config_adc(const adc_dev* dev); static void config_timer(timer_dev*); -#endif void board_reset_pll(void) { // TODO @@ -69,17 +72,8 @@ namespace wirish { afio_init(); } - void board_setup_adc(void) { -#if 0 - rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); - adc_foreach(config_adc); -#endif - } - void board_setup_timers(void) { -#if 0 timer_foreach(config_timer); -#endif } void board_setup_usb(void) { @@ -92,19 +86,8 @@ namespace wirish { * Auxiliary routines */ -#if 0 - static void config_adc(const adc_dev *dev) { - adc_init(dev); - - adc_set_extsel(dev, ADC_SWSTART); - adc_set_exttrig(dev, true); - - adc_enable(dev); - adc_calibrate(dev); - adc_set_sample_rate(dev, ADC_SMPR_55_5); - } - static void config_timer(timer_dev *dev) { +#if 0 timer_adv_reg_map *regs = (dev->regs).adv; const uint16 full_overflow = 0xFFFF; const uint16 half_duty = 0x8FFF; @@ -135,7 +118,7 @@ namespace wirish { } timer_resume(dev); - } #endif + } } } diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index b3c690c..e1bf1fd 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -28,11 +28,18 @@ * @file wirish/stm32f2/boards_setup.cpp * @author Marti Bolivar * @brief STM32F2 chip setup. + * + * This file controls how init() behaves on the STM32F2. Be very + * careful when changing anything here. Many of these values depend + * upon each other. */ -#include +#include "boards_private.h" + #include +#include +// PLL configuration for 25 MHz external oscillator --> 120 MHz SYSCLK. #define PLL_Q 5 #define PLL_P 2 #define PLL_N 240 @@ -41,7 +48,18 @@ static stm32f2_rcc_pll_data pll_data = {PLL_Q, PLL_P, PLL_N, PLL_M}; namespace wirish { namespace priv { - rcc_pll_cfg board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + // PLL clocked off of HSE, with above configuration data. + rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + // As f_APB2 = 60 MHz (see board_setup_clock_prescalers), + // we need f_ADC = f_PCLK2 / 2 to get the (maximum) + // f_ADC = 30 MHz. + adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_2; + // With clocks as specified here (i.e. f_ADC = 30 MHz), this + // ADC sample rate allows for error less than 1/4 LSB with a + // 50 KOhm input impedance, assuming an internal sample and + // hold capacitance C_ADC at most 8.8 pF. See Equation 1 and + // Table 61 in the F2 datasheet for more details. + adc_smp_rate w_adc_smp = ADC_SMPR_144; void board_reset_pll(void) { // Set PLLCFGR to its reset value. @@ -49,8 +67,13 @@ namespace wirish { } void board_setup_clock_prescalers(void) { + // With f_SYSCLK = 120 MHz (as determined by board_pll_cfg), + // + // f_AHB = f_SYSCLK / 1 = 120 MHz rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); + // f_APB1 = f_AHB / 4 = 30 MHz rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_4); + // f_APB2 = f_AHB / 2 = 60 MHz rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_2); } @@ -58,10 +81,6 @@ namespace wirish { gpio_init_all(); } - void board_setup_adc(void) { - // TODO - } - void board_setup_timers(void) { // TODO } @@ -72,4 +91,3 @@ namespace wirish { } } - -- cgit v1.2.3 From 5295f92b19e7ca63e5d0c0f3bb15b926e79ceea4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 5 Apr 2012 12:07:12 -0400 Subject: Deprecate rcc_clk_init(). This function has been with us from the earliest days of libmaple. It's showing its age, as the API it presents is tied to the STM32F1. Deprecate it, and provide instructions for how to use newer, more portable APIs. The new way is more verbose, but we can always add a portable "just set up the PLL, dammit" convenience function later (a nice candidate is to extract an interface from setup_clocks() in boards.cpp). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 2 +- libmaple/stm32f1/include/series/rcc.h | 7 +++---- libmaple/stm32f1/rcc.c | 19 +++++++++++++++++-- libmaple/stm32f2/include/series/rcc.h | 2 +- 4 files changed, 22 insertions(+), 8 deletions(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 9042391..4693606 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -42,7 +42,7 @@ extern "C"{ * might need them. */ /** * @brief SYSCLK sources - * @see rcc_clk_init() + * @see rcc_switch_sysclk() */ typedef enum rcc_sysclk_src { RCC_CLKSRC_HSI = 0x0, diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index b72c5cf..1eb913a 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -448,8 +448,7 @@ typedef enum rcc_clk_id { } rcc_clk_id; /** - * PLL multipliers - * @see rcc_clk_init() + * @brief Deprecated PLL multipliers, for rcc_clk_init(). */ typedef enum rcc_pll_multiplier { RCC_PLLMUL_2 = (0x0 << 18), @@ -470,8 +469,8 @@ typedef enum rcc_pll_multiplier { } rcc_pll_multiplier; /** - * PLL entry clock source - * @see rcc_clk_init() + * @brief PLL clock sources. + * @see rcc_configure_pll() */ typedef enum rcc_pllsrc { RCC_PLLSRC_HSE = (0x1 << 16), diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index 0752b82..aeedf66 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -96,8 +96,23 @@ const struct rcc_dev_info rcc_dev_table[] = { }; /** - * @brief Initialize the clock control system. Initializes the system - * clock source to use the PLL driven by an external oscillator + * @brief Deprecated. + * + * Initialize the clock control system. Initializes the system + * clock source to use the PLL driven by an external oscillator. + * + * This function is limited and nonportable. Instead of using it, + * follow this (portable) procedure: + * + * 1. Switch to HSI by calling rcc_switch_sysclk(RCC_CLKSRC_HSI). + * 2. Turn off HSE by calling rcc_turn_off_clk(RCC_CLK_HSE). + * 3. Turn off the PLL by calling rcc_turn_off_clk(RCC_CLK_HSE). + * 4. Reconfigure the PLL using rcc_configure_pll(). + * 5. Turn on RCC_CLK_HSE using rcc_turn_on_clk() and wait for it to + * become ready by busy-waiting on rcc_is_clk_ready(). + * 6. Turn on RCC_CLK_PLL using the same methods. + * 7. Switch to the PLL with rcc_switch_sysclk(RCC_CLKSRC_PLL). + * * @param sysclk_src system clock source, must be PLL * @param pll_src pll clock source, must be HSE * @param pll_mul pll multiplier diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 019bb3e..79bdf73 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -833,7 +833,7 @@ typedef enum rcc_clk_id { /** * @brief PLL entry clock source - * @see rcc_clk_init() + * @see rcc_configure_pll() */ typedef enum rcc_pllsrc { RCC_PLLSRC_HSI = 0, -- cgit v1.2.3 From a0da4bb4ded385385eb1b8f9752f800f9cebf15b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 5 Apr 2012 14:23:48 -0400 Subject: libmaple/dac.h: Fixups. Assert LeafLabs copyright; fix Doxygen @file, and add missing include. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/dac.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/dac.h b/libmaple/include/libmaple/dac.h index 738bede..9bd74b4 100644 --- a/libmaple/include/libmaple/dac.h +++ b/libmaple/include/libmaple/dac.h @@ -1,6 +1,7 @@ /****************************************************************************** * The MIT License * + * Copyright (c) 2011 LeafLabs, LLC. * Copyright (c) 2010 Bryan Newbold. * * Permission is hereby granted, free of charge, to any person @@ -25,7 +26,7 @@ *****************************************************************************/ /** - * @file dac.h + * @file libmaple/dac.h * @brief Digital to analog converter support. */ @@ -38,6 +39,7 @@ extern "C"{ #endif +#include #include /* -- cgit v1.2.3 From cd4613ca787ba0d36dd201ced3aa843f0af7a31a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 5 Apr 2012 14:25:46 -0400 Subject: libmaple/timer.h: Fixups. Fix include guard define name, update copyright, fix Doxygen @file. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index 9e4e20c..fef34fc 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -1,7 +1,7 @@ /****************************************************************************** * The MIT License * - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -25,13 +25,13 @@ *****************************************************************************/ /** - * @file timer.h + * @file libmaple/timer.h * @author Marti Bolivar * @brief Timer interface. */ -#ifndef _LIBMAPLE_TIMERS_H_ -#define _LIBMAPLE_TIMERS_H_ +#ifndef _LIBMAPLE_TIMER_H_ +#define _LIBMAPLE_TIMER_H_ #ifdef __cplusplus extern "C"{ -- cgit v1.2.3 From 342c8de23e22b0b91daafb412f47b13deddf2128 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 5 Apr 2012 16:32:53 -0400 Subject: libmaple/libmaple_types.h: Add __always_inline. We need this to ensure inlining when compiled with -Os. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/libmaple_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h index b2c424a..0a83795 100644 --- a/libmaple/include/libmaple/libmaple_types.h +++ b/libmaple/include/libmaple/libmaple_types.h @@ -54,6 +54,7 @@ typedef void (*voidFuncPtr)(void); #define __packed __attribute__((__packed__)) #define __deprecated __attribute__((__deprecated__)) #define __weak __attribute__((weak)) +#define __always_inline inline __attribute__((always_inline)) #ifndef NULL #define NULL 0 -- cgit v1.2.3 From fb061ae2e50a81904797146c3b5de8156dfd3f91 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 5 Apr 2012 16:44:11 -0400 Subject: Don't conditionally compile rcc_clk_id or nvic_irq_num enumerators. Whether or not a given peripheral is present on an F1 series MCU doesn't matter. It doesn't take up any extra space to include these enumerators, and it's convenient to have them defined so portable libmaple routines can safely refer to them. This can prevent the need for special series-specific versions of some functions. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/nvic.h | 2 -- libmaple/stm32f1/include/series/rcc.h | 4 ---- 2 files changed, 6 deletions(-) diff --git a/libmaple/stm32f1/include/series/nvic.h b/libmaple/stm32f1/include/series/nvic.h index 69fd945..33783f3 100644 --- a/libmaple/stm32f1/include/series/nvic.h +++ b/libmaple/stm32f1/include/series/nvic.h @@ -102,7 +102,6 @@ typedef enum nvic_irq_num { NVIC_TIMER8_UP = 44, /**< Timer 8 update */ NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ -#ifdef STM32_HIGH_DENSITY NVIC_ADC3 = 47, /**< ADC3 */ NVIC_FSMC = 48, /**< FSMC */ NVIC_SDIO = 49, /**< SDIO */ @@ -116,7 +115,6 @@ typedef enum nvic_irq_num { NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ -#endif } nvic_irq_num; static inline void nvic_irq_disable_all(void) { diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index 1eb913a..f60b07b 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -421,7 +421,6 @@ typedef enum rcc_clk_id { RCC_FLITF, RCC_SRAM, RCC_USB, -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) RCC_GPIOE, RCC_GPIOF, RCC_GPIOG, @@ -436,15 +435,12 @@ typedef enum rcc_clk_id { RCC_DMA2, RCC_SDIO, RCC_SPI3, -#endif -#ifdef STM32_XL_DENSITY RCC_TIMER9, RCC_TIMER10, RCC_TIMER11, RCC_TIMER12, RCC_TIMER13, RCC_TIMER14, -#endif } rcc_clk_id; /** -- cgit v1.2.3 From 9cefeca5c1927c34d64e592bb4ad7ffe7c44822c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 5 Apr 2012 17:10:33 -0400 Subject: timer: Fixes, rip out nonportable bits. Fix copy-paste errors in, and add missing, register bit definitions. For copy-paste errors that would result in source incompatibilities with past releases, add some legacy defines. Add series header and C file for STM32F1 which fills in the missing API. Much of the F1 timer.c would be repeated on F2, so also add timer_private.h to hold these. Support for timers 9 through 14 is still missing. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 233 ++++++++++++++++----------- libmaple/rules.mk | 2 +- libmaple/stm32f1/include/series/timer.h | 97 +++++++++++ libmaple/stm32f1/rules.mk | 1 + libmaple/stm32f1/timer.c | 152 ++++++++++++++++++ libmaple/timer.c | 275 +------------------------------- libmaple/timer_private.h | 168 +++++++++++++++++++ 7 files changed, 568 insertions(+), 360 deletions(-) create mode 100644 libmaple/stm32f1/include/series/timer.h create mode 100644 libmaple/stm32f1/timer.c create mode 100644 libmaple/timer_private.h diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index fef34fc..0a046c9 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -42,8 +42,15 @@ extern "C"{ #include #include +struct timer_adv_reg_map; +struct timer_gen_reg_map; +struct timer_bas_reg_map; +struct timer_dev; +/* Include the series header here, as it may need the above */ +#include + /* - * Register maps and devices + * Register maps */ /** Advanced control timer register map type */ @@ -70,29 +77,10 @@ typedef struct timer_adv_reg_map { __io uint32 DMAR; /**< DMA address for full transfer */ } timer_adv_reg_map; -/** General purpose timer register map type */ -typedef struct timer_gen_reg_map { - __io uint32 CR1; /**< Control register 1 */ - __io uint32 CR2; /**< Control register 2 */ - __io uint32 SMCR; /**< Slave mode control register */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ - __io uint32 SR; /**< Status register */ - __io uint32 EGR; /**< Event generation register */ - __io uint32 CCMR1; /**< Capture/compare mode register 1 */ - __io uint32 CCMR2; /**< Capture/compare mode register 2 */ - __io uint32 CCER; /**< Capture/compare enable register */ - __io uint32 CNT; /**< Counter */ - __io uint32 PSC; /**< Prescaler */ - __io uint32 ARR; /**< Auto-reload register */ - const uint32 RESERVED1; /**< Reserved */ - __io uint32 CCR1; /**< Capture/compare register 1 */ - __io uint32 CCR2; /**< Capture/compare register 2 */ - __io uint32 CCR3; /**< Capture/compare register 3 */ - __io uint32 CCR4; /**< Capture/compare register 4 */ - const uint32 RESERVED2; /**< Reserved */ - __io uint32 DCR; /**< DMA control register */ - __io uint32 DMAR; /**< DMA address for full transfer */ -} timer_gen_reg_map; +/* timer_gen_reg_map: intentionally omitted. + * + * General purpose timers differ slightly across series, so leave it + * up to the series header to define struct timer_gen_reg_map. */ /** Basic timer register map type */ typedef struct timer_bas_reg_map { @@ -110,25 +98,6 @@ typedef struct timer_bas_reg_map { __io uint32 ARR; /**< Auto-reload register */ } timer_bas_reg_map; -/** Timer 1 register map base pointer */ -#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) -/** Timer 2 register map base pointer */ -#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) -/** Timer 3 register map base pointer */ -#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) -/** Timer 4 register map base pointer */ -#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) -#ifdef STM32_HIGH_DENSITY -/** Timer 5 register map base pointer */ -#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) -/** Timer 6 register map base pointer */ -#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) -/** Timer 7 register map base pointer */ -#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) -/** Timer 8 register map base pointer */ -#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) -#endif - /* * Timer devices */ @@ -163,19 +132,14 @@ typedef struct timer_dev { timer_reg_map regs; /**< Register map */ rcc_clk_id clk_id; /**< RCC clock information */ timer_type type; /**< Timer's type */ - voidFuncPtr handlers[]; /**< User IRQ handlers */ + voidFuncPtr handlers[]; /**< + * @brief User IRQ handlers + * It's not a good idea to touch these + * directly. + * @see timer_attach_interrupt() + * @see timer_detach_interrupt() */ } timer_dev; -extern timer_dev *TIMER1; -extern timer_dev *TIMER2; -extern timer_dev *TIMER3; -extern timer_dev *TIMER4; -#ifdef STM32_HIGH_DENSITY -extern timer_dev *TIMER5; -extern timer_dev *TIMER6; -extern timer_dev *TIMER7; -extern timer_dev *TIMER8; -#endif /* * Register bit definitions @@ -278,12 +242,15 @@ extern timer_dev *TIMER8; /* DMA/Interrupt enable register (DIER) */ #define TIMER_DIER_TDE_BIT 14 +#define TIMER_DIER_COMDE_BIT 13 #define TIMER_DIER_CC4DE_BIT 12 #define TIMER_DIER_CC3DE_BIT 11 #define TIMER_DIER_CC2DE_BIT 10 #define TIMER_DIER_CC1DE_BIT 9 #define TIMER_DIER_UDE_BIT 8 +#define TIMER_DIER_BIE_BIT 7 #define TIMER_DIER_TIE_BIT 6 +#define TIMER_DIER_COMIE_BIT 5 #define TIMER_DIER_CC4IE_BIT 4 #define TIMER_DIER_CC3IE_BIT 3 #define TIMER_DIER_CC2IE_BIT 2 @@ -291,12 +258,15 @@ extern timer_dev *TIMER8; #define TIMER_DIER_UIE_BIT 0 #define TIMER_DIER_TDE BIT(TIMER_DIER_TDE_BIT) +#define TIMER_DIER_COMDE BIT(TIMER_DIER_COMDE_BIT) #define TIMER_DIER_CC4DE BIT(TIMER_DIER_CC4DE_BIT) #define TIMER_DIER_CC3DE BIT(TIMER_DIER_CC3DE_BIT) #define TIMER_DIER_CC2DE BIT(TIMER_DIER_CC2DE_BIT) #define TIMER_DIER_CC1DE BIT(TIMER_DIER_CC1DE_BIT) #define TIMER_DIER_UDE BIT(TIMER_DIER_UDE_BIT) +#define TIMER_DIER_BIE BIT(TIMER_DIER_BIE_BIT) #define TIMER_DIER_TIE BIT(TIMER_DIER_TIE_BIT) +#define TIMER_DIER_COMIE BIT(TIMER_DIER_COMIE_BIT) #define TIMER_DIER_CC4IE BIT(TIMER_DIER_CC4IE_BIT) #define TIMER_DIER_CC3IE BIT(TIMER_DIER_CC3IE_BIT) #define TIMER_DIER_CC2IE BIT(TIMER_DIER_CC2IE_BIT) @@ -333,14 +303,18 @@ extern timer_dev *TIMER8; /* Event generation register (EGR) */ +#define TIMER_EGR_BG_BIT 7 #define TIMER_EGR_TG_BIT 6 +#define TIMER_EGR_COMG_BIT 5 #define TIMER_EGR_CC4G_BIT 4 #define TIMER_EGR_CC3G_BIT 3 #define TIMER_EGR_CC2G_BIT 2 #define TIMER_EGR_CC1G_BIT 1 #define TIMER_EGR_UG_BIT 0 +#define TIMER_EGR_BG BIT(TIMER_EGR_BG_BIT) #define TIMER_EGR_TG BIT(TIMER_EGR_TG_BIT) +#define TIMER_EGR_COMG BIT(TIMER_EGR_COMG_BIT) #define TIMER_EGR_CC4G BIT(TIMER_EGR_CC4G_BIT) #define TIMER_EGR_CC3G BIT(TIMER_EGR_CC3G_BIT) #define TIMER_EGR_CC2G BIT(TIMER_EGR_CC2G_BIT) @@ -397,44 +371,83 @@ extern timer_dev *TIMER8; #define TIMER_CCMR2_OC4CE BIT(TIMER_CCMR2_OC4CE_BIT) #define TIMER_CCMR2_OC4M (0x3 << 12) -#define TIMER_CCMR2_IC2F (0xF << 12) +#define TIMER_CCMR2_IC4F (0xF << 12) #define TIMER_CCMR2_OC4PE BIT(TIMER_CCMR2_OC4PE_BIT) #define TIMER_CCMR2_OC4FE BIT(TIMER_CCMR2_OC4FE_BIT) -#define TIMER_CCMR2_IC2PSC (0x3 << 10) +#define TIMER_CCMR2_IC4PSC (0x3 << 10) #define TIMER_CCMR2_CC4S (0x3 << 8) -#define TIMER_CCMR1_CC4S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) -#define TIMER_CCMR1_CC4S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) -#define TIMER_CCMR1_CC4S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) -#define TIMER_CCMR1_CC4S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) +#define TIMER_CCMR2_CC4S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) +#define TIMER_CCMR2_CC4S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) +#define TIMER_CCMR2_CC4S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR2_CC4S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) #define TIMER_CCMR2_OC3CE BIT(TIMER_CCMR2_OC3CE_BIT) #define TIMER_CCMR2_OC3M (0x3 << 4) -#define TIMER_CCMR2_IC1F (0xF << 4) +#define TIMER_CCMR2_IC3F (0xF << 4) #define TIMER_CCMR2_OC3PE BIT(TIMER_CCMR2_OC3PE_BIT) #define TIMER_CCMR2_OC3FE BIT(TIMER_CCMR2_OC3FE_BIT) -#define TIMER_CCMR2_IC1PSC (0x3 << 2) +#define TIMER_CCMR2_IC3PSC (0x3 << 2) #define TIMER_CCMR2_CC3S 0x3 -#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR_CCS_OUTPUT -#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 -#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 -#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC +#define TIMER_CCMR2_CC3S_OUTPUT TIMER_CCMR_CCS_OUTPUT +#define TIMER_CCMR2_CC3S_INPUT_TI1 TIMER_CCMR_CCS_INPUT_TI1 +#define TIMER_CCMR2_CC3S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 +#define TIMER_CCMR2_CC3S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC + +/* Old, copy-paste error CCMR2 bit definitions from previous releases, + * kept for backwards compatibility: */ +/** Deprecated. Use TIMER_CCMR1_CC4S_OUTPUT instead. */ +#define TIMER_CCMR1_CC4S_OUTPUT TIMER_CCMR2_CC4S_OUTPUT +/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI1 instead. */ +#define TIMER_CCMR1_CC4S_INPUT_TI1 TIMER_CCMR2_CC4S_INPUT_TI1 +/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI2 instead. */ +#define TIMER_CCMR1_CC4S_INPUT_TI2 TIMER_CCMR2_CC4S_INPUT_TI2 +/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TRC instead. */ +#define TIMER_CCMR1_CC4S_INPUT_TRC TIMER_CCMR2_CC4S_INPUT_TRC +/** Deprecated. Use TIMER_CCMR2_IC4F instead. */ +#define TIMER_CCMR2_IC2F TIMER_CCMR2_IC4F +/** Deprecated. Use TIMER_CCMR2_IC4PSC instead. */ +#define TIMER_CCMR2_IC2PSC TIMER_CCMR2_IC4PSC +/** Deprecated. Use TIMER_CCMR2_IC3F instead. */ +#define TIMER_CCMR2_IC1F TIMER_CCMR2_IC3F +/** Deprecated. Use TIMER_CCMR2_IC3PSC instead. */ +#define TIMER_CCMR2_IC1PSC TIMER_CCMR2_IC3PSC +/** Deprecated. Use TIMER_CCMR1_CC3S_OUTPUT instead. */ +#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR2_CC3S_OUTPUT +/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI1 instead. */ +#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR2_CC3S_INPUT_TI1 +/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI2 instead. */ +#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR2_CC3S_INPUT_TI2 +/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TRC instead. */ +#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR2_CC3S_INPUT_TRC /* Capture/compare enable register (CCER) */ #define TIMER_CCER_CC4P_BIT 13 #define TIMER_CCER_CC4E_BIT 12 +#define TIMER_CCER_CC3NP_BIT 11 +#define TIMER_CCER_CC3NE_BIT 10 #define TIMER_CCER_CC3P_BIT 9 #define TIMER_CCER_CC3E_BIT 8 +#define TIMER_CCER_CC2NP_BIT 7 +#define TIMER_CCER_CC2NE_BIT 6 #define TIMER_CCER_CC2P_BIT 5 #define TIMER_CCER_CC2E_BIT 4 +#define TIMER_CCER_CC1NP_BIT 3 +#define TIMER_CCER_CC1NE_BIT 2 #define TIMER_CCER_CC1P_BIT 1 #define TIMER_CCER_CC1E_BIT 0 #define TIMER_CCER_CC4P BIT(TIMER_CCER_CC4P_BIT) #define TIMER_CCER_CC4E BIT(TIMER_CCER_CC4E_BIT) +#define TIMER_CCER_CC3NP BIT(TIMER_CCER_CC3NP_BIT) +#define TIMER_CCER_CC3NE BIT(TIMER_CCER_CC3NE_BIT) #define TIMER_CCER_CC3P BIT(TIMER_CCER_CC3P_BIT) #define TIMER_CCER_CC3E BIT(TIMER_CCER_CC3E_BIT) +#define TIMER_CCER_CC2NP BIT(TIMER_CCER_CC2NP_BIT) +#define TIMER_CCER_CC2NE BIT(TIMER_CCER_CC2NE_BIT) #define TIMER_CCER_CC2P BIT(TIMER_CCER_CC2P_BIT) #define TIMER_CCER_CC2E BIT(TIMER_CCER_CC2E_BIT) +#define TIMER_CCER_CC1NP BIT(TIMER_CCER_CC1NP_BIT) +#define TIMER_CCER_CC1NE BIT(TIMER_CCER_CC1NE_BIT) #define TIMER_CCER_CC1P BIT(TIMER_CCER_CC1P_BIT) #define TIMER_CCER_CC1E BIT(TIMER_CCER_CC1E_BIT) @@ -463,24 +476,24 @@ extern timer_dev *TIMER8; /* DMA control register (DCR) */ #define TIMER_DCR_DBL (0x1F << 8) -#define TIMER_DCR_DBL_1BYTE (0x0 << 8) -#define TIMER_DCR_DBL_2BYTE (0x1 << 8) -#define TIMER_DCR_DBL_3BYTE (0x2 << 8) -#define TIMER_DCR_DBL_4BYTE (0x3 << 8) -#define TIMER_DCR_DBL_5BYTE (0x4 << 8) -#define TIMER_DCR_DBL_6BYTE (0x5 << 8) -#define TIMER_DCR_DBL_7BYTE (0x6 << 8) -#define TIMER_DCR_DBL_8BYTE (0x7 << 8) -#define TIMER_DCR_DBL_9BYTE (0x8 << 8) -#define TIMER_DCR_DBL_10BYTE (0x9 << 8) -#define TIMER_DCR_DBL_11BYTE (0xA << 8) -#define TIMER_DCR_DBL_12BYTE (0xB << 8) -#define TIMER_DCR_DBL_13BYTE (0xC << 8) -#define TIMER_DCR_DBL_14BYTE (0xD << 8) -#define TIMER_DCR_DBL_15BYTE (0xE << 8) -#define TIMER_DCR_DBL_16BYTE (0xF << 8) -#define TIMER_DCR_DBL_17BYTE (0x10 << 8) -#define TIMER_DCR_DBL_18BYTE (0x11 << 8) +#define TIMER_DCR_DBL_1_XFER (0x0 << 8) +#define TIMER_DCR_DBL_2_XFER (0x1 << 8) +#define TIMER_DCR_DBL_3_XFER (0x2 << 8) +#define TIMER_DCR_DBL_4_XFER (0x3 << 8) +#define TIMER_DCR_DBL_5_XFER (0x4 << 8) +#define TIMER_DCR_DBL_6_XFER (0x5 << 8) +#define TIMER_DCR_DBL_7_XFER (0x6 << 8) +#define TIMER_DCR_DBL_8_XFER (0x7 << 8) +#define TIMER_DCR_DBL_9_XFER (0x8 << 8) +#define TIMER_DCR_DBL_10_XFER (0x9 << 8) +#define TIMER_DCR_DBL_11_XFER (0xA << 8) +#define TIMER_DCR_DBL_12_XFER (0xB << 8) +#define TIMER_DCR_DBL_13_XFER (0xC << 8) +#define TIMER_DCR_DBL_14_XFER (0xD << 8) +#define TIMER_DCR_DBL_15_XFER (0xE << 8) +#define TIMER_DCR_DBL_16_XFER (0xF << 8) +#define TIMER_DCR_DBL_17_XFER (0x10 << 8) +#define TIMER_DCR_DBL_18_XFER (0x11 << 8) #define TIMER_DCR_DBA 0x1F #define TIMER_DCR_DBA_CR1 0x0 #define TIMER_DCR_DBA_CR2 0x1 @@ -503,6 +516,45 @@ extern timer_dev *TIMER8; #define TIMER_DCR_DBA_DCR 0x12 #define TIMER_DCR_DBA_DMAR 0x13 +/* Old, erroneous bit definitions from previous releases, kept for + * backwards compatibility: */ +/** Deprecated. Use TIMER_DCR_DBL_1_XFER instead. */ +#define TIMER_DCR_DBL_1BYTE TIMER_DCR_DBL_1_XFER +/** Deprecated. Use TIMER_DCR_DBL_2_XFER instead. */ +#define TIMER_DCR_DBL_2BYTE TIMER_DCR_DBL_2_XFER +/** Deprecated. Use TIMER_DCR_DBL_3_XFER instead. */ +#define TIMER_DCR_DBL_3BYTE TIMER_DCR_DBL_3_XFER +/** Deprecated. Use TIMER_DCR_DBL_4_XFER instead. */ +#define TIMER_DCR_DBL_4BYTE TIMER_DCR_DBL_4_XFER +/** Deprecated. Use TIMER_DCR_DBL_5_XFER instead. */ +#define TIMER_DCR_DBL_5BYTE TIMER_DCR_DBL_5_XFER +/** Deprecated. Use TIMER_DCR_DBL_6_XFER instead. */ +#define TIMER_DCR_DBL_6BYTE TIMER_DCR_DBL_6_XFER +/** Deprecated. Use TIMER_DCR_DBL_7_XFER instead. */ +#define TIMER_DCR_DBL_7BYTE TIMER_DCR_DBL_7_XFER +/** Deprecated. Use TIMER_DCR_DBL_8_XFER instead. */ +#define TIMER_DCR_DBL_8BYTE TIMER_DCR_DBL_8_XFER +/** Deprecated. Use TIMER_DCR_DBL_9_XFER instead. */ +#define TIMER_DCR_DBL_9BYTE TIMER_DCR_DBL_9_XFER +/** Deprecated. Use TIMER_DCR_DBL_10_XFER instead. */ +#define TIMER_DCR_DBL_10BYTE TIMER_DCR_DBL_10_XFER +/** Deprecated. Use TIMER_DCR_DBL_11_XFER instead. */ +#define TIMER_DCR_DBL_11BYTE TIMER_DCR_DBL_11_XFER +/** Deprecated. Use TIMER_DCR_DBL_12_XFER instead. */ +#define TIMER_DCR_DBL_12BYTE TIMER_DCR_DBL_12_XFER +/** Deprecated. Use TIMER_DCR_DBL_13_XFER instead. */ +#define TIMER_DCR_DBL_13BYTE TIMER_DCR_DBL_13_XFER +/** Deprecated. Use TIMER_DCR_DBL_14_XFER instead. */ +#define TIMER_DCR_DBL_14BYTE TIMER_DCR_DBL_14_XFER +/** Deprecated. Use TIMER_DCR_DBL_15_XFER instead. */ +#define TIMER_DCR_DBL_15BYTE TIMER_DCR_DBL_15_XFER +/** Deprecated. Use TIMER_DCR_DBL_16_XFER instead. */ +#define TIMER_DCR_DBL_16BYTE TIMER_DCR_DBL_16_XFER +/** Deprecated. Use TIMER_DCR_DBL_17_XFER instead. */ +#define TIMER_DCR_DBL_17BYTE TIMER_DCR_DBL_17_XFER +/** Deprecated. Use TIMER_DCR_DBL_18_XFER instead. */ +#define TIMER_DCR_DBL_18BYTE TIMER_DCR_DBL_18_XFER + /* * Convenience routines */ @@ -841,18 +893,19 @@ static inline void timer_cc_set_pol(timer_dev *dev, uint8 channel, uint8 pol) { /** * @brief Get a timer's DMA burst length. * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @return Number of bytes to be transferred per DMA request, from 1 to 18. + * @return Number of transfers per read or write to timer DMA register, + * from 1 to 18. */ static inline uint8 timer_dma_get_burst_len(timer_dev *dev) { uint32 dbl = ((dev->regs).gen->DCR & TIMER_DCR_DBL) >> 8; - return dbl + 1; /* 0 means 1 byte, etc. */ + return dbl + 1; /* 0 means 1 transfer, etc. */ } /** * @brief Set a timer's DMA burst length. * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. - * @param length DMA burst length; i.e., number of bytes to transfer - * per DMA request, from 1 to 18. + * @param length DMA burst length; i.e., number of DMA transfers per + * read/write to timer DMA register, from 1 to 18. */ static inline void timer_dma_set_burst_len(timer_dev *dev, uint8 length) { uint32 tmp = (dev->regs).gen->DCR; @@ -907,7 +960,7 @@ typedef enum timer_dma_base_addr { /** * @brief Get the timer's DMA base address. * - * Some restrictions apply; see ST RM0008. + * Some restrictions apply; see the reference manual for your chip. * * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. * @return DMA base address @@ -920,7 +973,7 @@ static inline timer_dma_base_addr timer_dma_get_base_addr(timer_dev *dev) { /** * @brief Set the timer's DMA base address. * - * Some restrictions apply; see ST RM0008. + * Some restrictions apply; see the reference manual for your chip. * * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. * @param dma_base DMA base address. diff --git a/libmaple/rules.mk b/libmaple/rules.mk index d118b16..2f5e066 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -20,6 +20,7 @@ cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c +cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c @@ -29,7 +30,6 @@ cSRCS_$(d) += util.c # cSRCS_$(d) += exti.c # cSRCS_$(d) += i2c.c # cSRCS_$(d) += spi.c -# cSRCS_$(d) += timer.c sSRCS_$(d) := exc.S diff --git a/libmaple/stm32f1/include/series/timer.h b/libmaple/stm32f1/include/series/timer.h new file mode 100644 index 0000000..3e2ab0f --- /dev/null +++ b/libmaple/stm32f1/include/series/timer.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f1/include/series/timer.h + * @author Marti Bolivar + * @brief STM32F1 timer sub-header. + */ + +#ifndef _LIBMAPLE_STM32F1_TIMER_H_ +#define _LIBMAPLE_STM32F1_TIMER_H_ + +#include +#include + +/* + * Register maps and devices + */ + +/** STM32F1 general purpose timer register map type */ +typedef struct timer_gen_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SMCR; /**< Slave mode control register */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + __io uint32 CCMR1; /**< Capture/compare mode register 1 */ + __io uint32 CCMR2; /**< Capture/compare mode register 2 */ + __io uint32 CCER; /**< Capture/compare enable register */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 CCR1; /**< Capture/compare register 1 */ + __io uint32 CCR2; /**< Capture/compare register 2 */ + __io uint32 CCR3; /**< Capture/compare register 3 */ + __io uint32 CCR4; /**< Capture/compare register 4 */ + const uint32 RESERVED2; /**< Reserved */ + __io uint32 DCR; /**< DMA control register */ + __io uint32 DMAR; /**< DMA address for full transfer */ +} timer_gen_reg_map; + +/** Timer 1 register map base pointer */ +#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) +/** Timer 2 register map base pointer */ +#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) +/** Timer 3 register map base pointer */ +#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) +/** Timer 4 register map base pointer */ +#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +/** Timer 5 register map base pointer */ +#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) +/** Timer 6 register map base pointer */ +#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) +/** Timer 7 register map base pointer */ +#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) +/** Timer 8 register map base pointer */ +#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) +#endif + +extern struct timer_dev *TIMER1; +extern struct timer_dev *TIMER2; +extern struct timer_dev *TIMER3; +extern struct timer_dev *TIMER4; +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +extern struct timer_dev *TIMER5; +extern struct timer_dev *TIMER6; +extern struct timer_dev *TIMER7; +extern struct timer_dev *TIMER8; +#endif + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index c0d6344..03fddb3 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -16,6 +16,7 @@ cSRCS_$(d) += bkp.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c +cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f1/timer.c b/libmaple/stm32f1/timer.c new file mode 100644 index 0000000..7506cb6 --- /dev/null +++ b/libmaple/stm32f1/timer.c @@ -0,0 +1,152 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011, 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/timer.c + * @author Marti Bolivar + * @brief STM32F1 timer support. + */ + +#include +#include "timer_private.h" + +/* + * Devices + */ + +/* Use timer_private macros to save typing. */ +static DECLARE_ADVANCED_TIMER(timer1, 1); +static DECLARE_GENERAL_TIMER(timer2, 2); +static DECLARE_GENERAL_TIMER(timer3, 3); +static DECLARE_GENERAL_TIMER(timer4, 4); + +/** Timer 1 device (advanced) */ +timer_dev *TIMER1 = &timer1; +/** Timer 2 device (general-purpose) */ +timer_dev *TIMER2 = &timer2; +/** Timer 3 device (general-purpose) */ +timer_dev *TIMER3 = &timer3; +/** Timer 4 device (general-purpose) */ +timer_dev *TIMER4 = &timer4; + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +static DECLARE_GENERAL_TIMER(timer5, 5); +static DECLARE_BASIC_TIMER(timer6, 6); +static DECLARE_BASIC_TIMER(timer7, 7); +static DECLARE_ADVANCED_TIMER(timer8, 8); + +/** Timer 5 device (general-purpose) */ +timer_dev *TIMER5 = &timer5; +/** Timer 6 device (basic) */ +timer_dev *TIMER6 = &timer6; +/** Timer 7 device (basic) */ +timer_dev *TIMER7 = &timer7; +/** Timer 8 device (advanced) */ +timer_dev *TIMER8 = &timer8; +#endif + +/* + * Routines + */ + +/** + * @brief Call a function on timer devices. + * @param fn Function to call on each timer device. + */ +void timer_foreach(void (*fn)(timer_dev*)) { + fn(TIMER1); + fn(TIMER2); + fn(TIMER3); + fn(TIMER4); +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + fn(TIMER5); + fn(TIMER6); + fn(TIMER7); + fn(TIMER8); +#endif +} + +/* + * IRQ handlers + */ + +void __irq_tim1_brk(void) { + dispatch_adv_brk(TIMER1); +} + +void __irq_tim1_up(void) { + dispatch_adv_up(TIMER1); +} + +void __irq_tim1_trg_com(void) { + dispatch_adv_trg_com(TIMER1); +} + +void __irq_tim1_cc(void) { + dispatch_adv_cc(TIMER1); +} + +void __irq_tim2(void) { + dispatch_general(TIMER2); +} + +void __irq_tim3(void) { + dispatch_general(TIMER3); +} + +void __irq_tim4(void) { + dispatch_general(TIMER4); +} + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +void __irq_tim5(void) { + dispatch_general(TIMER5); +} + +void __irq_tim6(void) { + dispatch_basic(TIMER6); +} + +void __irq_tim7(void) { + dispatch_basic(TIMER7); +} + +void __irq_tim8_brk(void) { + dispatch_adv_brk(TIMER8); +} + +void __irq_tim8_up(void) { + dispatch_adv_up(TIMER8); +} + +void __irq_tim8_trg_com(void) { + dispatch_adv_trg_com(TIMER8); +} + +void __irq_tim8_cc(void) { + dispatch_adv_cc(TIMER8); +} +#endif diff --git a/libmaple/timer.c b/libmaple/timer.c index 90995e2..d64e3e9 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -25,103 +25,13 @@ *****************************************************************************/ /** - * @file timer.c + * @file libmaple/timer.c * @author Marti Bolivar - * @brief New-style timer interface + * @brief Portable timer routines. */ #include -/* Just like the corresponding DIER bits: - * [0] = Update handler; - * [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively; - * [5] = COM; - * [6] = TRG; - * [7] = BRK. */ -#define NR_ADV_HANDLERS 8 -/* Update, capture/compare 1,2,3,4; ; trigger. */ -#define NR_GEN_HANDLERS 7 -/* Update only. */ -#define NR_BAS_HANDLERS 1 - -static timer_dev timer1 = { - .regs = { .adv = TIMER1_BASE }, - .clk_id = RCC_TIMER1, - .type = TIMER_ADVANCED, - .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, -}; -/** Timer 1 device (advanced) */ -timer_dev *TIMER1 = &timer1; - -static timer_dev timer2 = { - .regs = { .gen = TIMER2_BASE }, - .clk_id = RCC_TIMER2, - .type = TIMER_GENERAL, - .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, -}; -/** Timer 2 device (general-purpose) */ -timer_dev *TIMER2 = &timer2; - -static timer_dev timer3 = { - .regs = { .gen = TIMER3_BASE }, - .clk_id = RCC_TIMER3, - .type = TIMER_GENERAL, - .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, -}; -/** Timer 3 device (general-purpose) */ -timer_dev *TIMER3 = &timer3; - -static timer_dev timer4 = { - .regs = { .gen = TIMER4_BASE }, - .clk_id = RCC_TIMER4, - .type = TIMER_GENERAL, - .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, -}; -/** Timer 4 device (general-purpose) */ -timer_dev *TIMER4 = &timer4; - -#ifdef STM32_HIGH_DENSITY -static timer_dev timer5 = { - .regs = { .gen = TIMER5_BASE }, - .clk_id = RCC_TIMER5, - .type = TIMER_GENERAL, - .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, -}; -/** Timer 5 device (general-purpose) */ -timer_dev *TIMER5 = &timer5; - -static timer_dev timer6 = { - .regs = { .bas = TIMER6_BASE }, - .clk_id = RCC_TIMER6, - .type = TIMER_BASIC, - .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, -}; -/** Timer 6 device (basic) */ -timer_dev *TIMER6 = &timer6; - -static timer_dev timer7 = { - .regs = { .bas = TIMER7_BASE }, - .clk_id = RCC_TIMER7, - .type = TIMER_BASIC, - .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, -}; -/** Timer 7 device (basic) */ -timer_dev *TIMER7 = &timer7; - -static timer_dev timer8 = { - .regs = { .adv = TIMER8_BASE }, - .clk_id = RCC_TIMER8, - .type = TIMER_ADVANCED, - .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, -}; -/** Timer 8 device (advanced) */ -timer_dev *TIMER8 = &timer8; -#endif - -/* - * Convenience routines - */ - static void disable_channel(timer_dev *dev, uint8 channel); static void pwm_mode(timer_dev *dev, uint8 channel); static void output_compare_mode(timer_dev *dev, uint8 channel); @@ -190,23 +100,6 @@ void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) { } } -/** - * @brief Call a function on timer devices. - * @param fn Function to call on each timer device. - */ -void timer_foreach(void (*fn)(timer_dev*)) { - fn(TIMER1); - fn(TIMER2); - fn(TIMER3); - fn(TIMER4); -#ifdef STM32_HIGH_DENSITY - fn(TIMER5); - fn(TIMER6); - fn(TIMER7); - fn(TIMER8); -#endif -} - /** * @brief Attach a timer interrupt. * @param dev Timer device @@ -239,164 +132,6 @@ void timer_detach_interrupt(timer_dev *dev, uint8 interrupt) { dev->handlers[interrupt] = NULL; } -/* - * IRQ handlers - */ - -static inline void dispatch_adv_brk(timer_dev *dev); -static inline void dispatch_adv_up(timer_dev *dev); -static inline void dispatch_adv_trg_com(timer_dev *dev); -static inline void dispatch_adv_cc(timer_dev *dev); -static inline void dispatch_general(timer_dev *dev); -static inline void dispatch_basic(timer_dev *dev); - -void __irq_tim1_brk(void) { - dispatch_adv_brk(TIMER1); -} - -void __irq_tim1_up(void) { - dispatch_adv_up(TIMER1); -} - -void __irq_tim1_trg_com(void) { - dispatch_adv_trg_com(TIMER1); -} - -void __irq_tim1_cc(void) { - dispatch_adv_cc(TIMER1); -} - -void __irq_tim2(void) { - dispatch_general(TIMER2); -} - -void __irq_tim3(void) { - dispatch_general(TIMER3); -} - -void __irq_tim4(void) { - dispatch_general(TIMER4); -} - -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) - -void __irq_tim5(void) { - dispatch_general(TIMER5); -} - -void __irq_tim6(void) { - dispatch_basic(TIMER6); -} - -void __irq_tim7(void) { - dispatch_basic(TIMER7); -} - -void __irq_tim8_brk(void) { - dispatch_adv_brk(TIMER8); -} - -void __irq_tim8_up(void) { - dispatch_adv_up(TIMER8); -} - -void __irq_tim8_trg_com(void) { - dispatch_adv_trg_com(TIMER8); -} - -void __irq_tim8_cc(void) { - dispatch_adv_cc(TIMER8); -} -#endif - -/* Note: the following dispatch routines make use of the fact that - * DIER interrupt enable bits and SR interrupt flags have common bit - * positions. Thus, ANDing DIER and SR lets us check if an interrupt - * is enabled and if it has occurred simultaneously. - */ - -/* A special-case dispatch routine for single-interrupt NVIC lines. - * This function assumes that the interrupt corresponding to `iid' has - * in fact occurred (i.e., it doesn't check DIER & SR). */ -static inline void dispatch_single_irq(timer_dev *dev, - timer_interrupt_id iid, - uint32 irq_mask) { - timer_bas_reg_map *regs = (dev->regs).bas; - void (*handler)(void) = dev->handlers[iid]; - if (handler) { - handler(); - regs->SR &= ~irq_mask; - } -} - -/* For dispatch routines which service multiple interrupts. */ -#define handle_irq(dier_sr, irq_mask, handlers, iid, handled_irq) do { \ - if ((dier_sr) & (irq_mask)) { \ - void (*__handler)(void) = (handlers)[iid]; \ - if (__handler) { \ - __handler(); \ - handled_irq |= (irq_mask); \ - } \ - } \ - } while (0) - -static inline void dispatch_adv_brk(timer_dev *dev) { - dispatch_single_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF); -} - -static inline void dispatch_adv_up(timer_dev *dev) { - dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); -} - -static inline void dispatch_adv_trg_com(timer_dev *dev) { - timer_adv_reg_map *regs = (dev->regs).adv; - uint32 dsr = regs->DIER & regs->SR; - void (**hs)(void) = dev->handlers; - uint32 handled = 0; /* Logical OR of SR interrupt flags we end up - * handling. We clear these. User handlers - * must clear overcapture flags, to avoid - * wasting time in output mode. */ - - handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_COMIF, hs, TIMER_COM_INTERRUPT, handled); - - regs->SR &= ~handled; -} - -static inline void dispatch_adv_cc(timer_dev *dev) { - timer_adv_reg_map *regs = (dev->regs).adv; - uint32 dsr = regs->DIER & regs->SR; - void (**hs)(void) = dev->handlers; - uint32 handled = 0; - - handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC3IF, hs, TIMER_CC3_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled); - - regs->SR &= ~handled; -} - -static inline void dispatch_general(timer_dev *dev) { - timer_gen_reg_map *regs = (dev->regs).gen; - uint32 dsr = regs->DIER & regs->SR; - void (**hs)(void) = dev->handlers; - uint32 handled = 0; - - handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC3IF, hs, TIMER_CC3_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled); - handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled); - - regs->SR &= ~handled; -} - -static inline void dispatch_basic(timer_dev *dev) { - dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); -} - /* * Utilities */ @@ -417,6 +152,10 @@ static void output_compare_mode(timer_dev *dev, uint8 channel) { timer_cc_enable(dev, channel); } +/* FIXME: These IRQ enable routines fail for timers 9 through 14. + * We don't support those timers yet, so it's OK for now, but this + * really needs to get fixed. */ + static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id); static void enable_nonmuxed_irq(timer_dev *dev); @@ -462,7 +201,6 @@ static void enable_nonmuxed_irq(timer_dev *dev) { case RCC_TIMER4: nvic_irq_enable(NVIC_TIMER4); break; -#ifdef STM32_HIGH_DENSITY case RCC_TIMER5: nvic_irq_enable(NVIC_TIMER5); break; @@ -472,7 +210,6 @@ static void enable_nonmuxed_irq(timer_dev *dev) { case RCC_TIMER7: nvic_irq_enable(NVIC_TIMER7); break; -#endif default: ASSERT_FAULT(0); break; diff --git a/libmaple/timer_private.h b/libmaple/timer_private.h new file mode 100644 index 0000000..f882f51 --- /dev/null +++ b/libmaple/timer_private.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011, 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/timer_private.h + * @author Marti Bolivar + * @brief Private, internal timer APIs. + */ + +#ifndef _LIBMAPLE_TIMER_PRIVATE_H_ +#define _LIBMAPLE_TIMER_PRIVATE_H_ + +/* + * Devices + */ + +/* Just like the corresponding DIER bits: + * [0] = Update handler; + * [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively; + * [5] = COM; + * [6] = TRG; + * [7] = BRK. */ +#define NR_ADV_HANDLERS 8 +/* Update, capture/compare 1,2,3,4; ; trigger. */ +#define NR_GEN_HANDLERS 7 +/* Update only. */ +#define NR_BAS_HANDLERS 1 + +#define DECLARE_ADVANCED_TIMER(name, num) \ + timer_dev name = { \ + .regs = { .adv = TIMER##num##_BASE }, \ + .clk_id = RCC_TIMER##num, \ + .type = TIMER_ADVANCED, \ + .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, \ + } + +#define DECLARE_GENERAL_TIMER(name, num) \ + timer_dev name = { \ + .regs = { .gen = TIMER##num##_BASE }, \ + .clk_id = RCC_TIMER##num, \ + .type = TIMER_GENERAL, \ + .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, \ + } + +#define DECLARE_BASIC_TIMER(name, num) \ + timer_dev name = { \ + .regs = { .bas = TIMER##num##_BASE }, \ + .clk_id = RCC_TIMER##num, \ + .type = TIMER_BASIC, \ + .handlers = { [NR_BAS_HANDLERS - 1] = 0 }, \ + } + +/* + * IRQ handlers + */ + +/* Note: the following dispatch routines make use of the fact that + * DIER interrupt enable bits and SR interrupt flags have common bit + * positions. Thus, ANDing DIER and SR lets us check if an interrupt + * is enabled and if it has occurred simultaneously. + */ + +/* A special-case dispatch routine for single-interrupt NVIC lines. + * This function assumes that the interrupt corresponding to `iid' has + * in fact occurred (i.e., it doesn't check DIER & SR). */ +static __always_inline void dispatch_single_irq(timer_dev *dev, + timer_interrupt_id iid, + uint32 irq_mask) { + timer_bas_reg_map *regs = (dev->regs).bas; + void (*handler)(void) = dev->handlers[iid]; + if (handler) { + handler(); + regs->SR &= ~irq_mask; + } +} + +/* For dispatch routines which service multiple interrupts. */ +#define handle_irq(dier_sr, irq_mask, handlers, iid, handled_irq) do { \ + if ((dier_sr) & (irq_mask)) { \ + void (*__handler)(void) = (handlers)[iid]; \ + if (__handler) { \ + __handler(); \ + handled_irq |= (irq_mask); \ + } \ + } \ + } while (0) + +static __always_inline void dispatch_adv_brk(timer_dev *dev) { + dispatch_single_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF); +} + +static __always_inline void dispatch_adv_up(timer_dev *dev) { + dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); +} + +static __always_inline void dispatch_adv_trg_com(timer_dev *dev) { + timer_adv_reg_map *regs = (dev->regs).adv; + uint32 dsr = regs->DIER & regs->SR; + void (**hs)(void) = dev->handlers; + uint32 handled = 0; /* Logical OR of SR interrupt flags we end up + * handling. We clear these. User handlers + * must clear overcapture flags, to avoid + * wasting time in output mode. */ + + handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_COMIF, hs, TIMER_COM_INTERRUPT, handled); + + regs->SR &= ~handled; +} + +static __always_inline void dispatch_adv_cc(timer_dev *dev) { + timer_adv_reg_map *regs = (dev->regs).adv; + uint32 dsr = regs->DIER & regs->SR; + void (**hs)(void) = dev->handlers; + uint32 handled = 0; + + handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC3IF, hs, TIMER_CC3_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled); + + regs->SR &= ~handled; +} + +static __always_inline void dispatch_general(timer_dev *dev) { + timer_gen_reg_map *regs = (dev->regs).gen; + uint32 dsr = regs->DIER & regs->SR; + void (**hs)(void) = dev->handlers; + uint32 handled = 0; + + handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC3IF, hs, TIMER_CC3_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled); + + regs->SR &= ~handled; +} + +static __always_inline void dispatch_basic(timer_dev *dev) { + dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); +} + +#endif -- cgit v1.2.3 From d79ea860968318292922509b9e7d0b7c5976713d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 6 Apr 2012 14:54:47 -0400 Subject: libmaple/timer.h: Minor tweaks. Comments etc. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index 0a046c9..e98759a 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -77,7 +77,7 @@ typedef struct timer_adv_reg_map { __io uint32 DMAR; /**< DMA address for full transfer */ } timer_adv_reg_map; -/* timer_gen_reg_map: intentionally omitted. +/* General purpose timer register map type: intentionally omitted. * * General purpose timers differ slightly across series, so leave it * up to the series header to define struct timer_gen_reg_map. */ @@ -124,7 +124,7 @@ typedef union timer_reg_map { typedef enum timer_type { TIMER_ADVANCED, /**< Advanced type */ TIMER_GENERAL, /**< General purpose type */ - TIMER_BASIC /**< Basic type */ + TIMER_BASIC, /**< Basic type */ } timer_type; /** Timer device type */ @@ -609,8 +609,8 @@ void timer_foreach(void (*fn)(timer_dev*)); /** * @brief Timer interrupt number. * - * Not all timers support all of these values; see the descriptions - * for each value. + * Not all timers support all of these values. General purpose timers + * can be a special nuisance in this regard. */ typedef enum timer_interrupt_id { TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */ -- cgit v1.2.3 From fbd55a2647f4412ba51f1a54c1af49508f863cba Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 6 Apr 2012 14:55:15 -0400 Subject: stm32f1/timer.h: Whitespace tweaks. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/timer.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/libmaple/stm32f1/include/series/timer.h b/libmaple/stm32f1/include/series/timer.h index 3e2ab0f..9bd273e 100644 --- a/libmaple/stm32f1/include/series/timer.h +++ b/libmaple/stm32f1/include/series/timer.h @@ -65,22 +65,22 @@ typedef struct timer_gen_reg_map { } timer_gen_reg_map; /** Timer 1 register map base pointer */ -#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) +#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) /** Timer 2 register map base pointer */ -#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) +#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) /** Timer 3 register map base pointer */ -#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) +#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) /** Timer 4 register map base pointer */ -#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) +#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) /** Timer 5 register map base pointer */ -#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) +#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) /** Timer 6 register map base pointer */ -#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) +#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) /** Timer 7 register map base pointer */ -#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) +#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) /** Timer 8 register map base pointer */ -#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) +#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) #endif extern struct timer_dev *TIMER1; -- cgit v1.2.3 From 702d6495985451c7d37a7a46c639e694887a84c1 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 9 Apr 2012 13:56:03 -0400 Subject: stm32f2/rcc: Fix timer rcc_clk_id enumerators. The timer enumerators are different tokens on F2 than they are on F1. This is wrong (breaks portability), so fix it, and update the F2 rcc_dev_info table to match. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 28 +++++++------- libmaple/stm32f2/rcc.c | 72 +++++++++++++++++------------------ 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 79bdf73..540eb66 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -807,18 +807,18 @@ typedef enum rcc_clk_id { RCC_SPI3, RCC_SPI2, RCC_WWDG, - RCC_TIM14, - RCC_TIM13, - RCC_TIM12, - RCC_TIM7, - RCC_TIM6, - RCC_TIM5, - RCC_TIM4, - RCC_TIM3, - RCC_TIM2, - RCC_TIM11, - RCC_TIM10, - RCC_TIM9, + RCC_TIMER14, + RCC_TIMER13, + RCC_TIMER12, + RCC_TIMER7, + RCC_TIMER6, + RCC_TIMER5, + RCC_TIMER4, + RCC_TIMER3, + RCC_TIMER2, + RCC_TIMER11, + RCC_TIMER10, + RCC_TIMER9, RCC_SYSCFG, RCC_SPI1, RCC_SDIO, @@ -827,8 +827,8 @@ typedef enum rcc_clk_id { RCC_ADC1, RCC_USART6, RCC_USART1, - RCC_TIM8, - RCC_TIM1, + RCC_TIMER8, + RCC_TIMER1, } rcc_clk_id; /** diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c index 46e6565..8a91f30 100644 --- a/libmaple/stm32f2/rcc.c +++ b/libmaple/stm32f2/rcc.c @@ -70,44 +70,44 @@ const struct rcc_dev_info rcc_dev_table[] = { [RCC_FSMC] = DEV_ENTRY(AHB3, FSMC), /* APB1 */ - [RCC_DAC] = DEV_ENTRY(APB1, DAC), - [RCC_PWR] = DEV_ENTRY(APB1, PWR), - [RCC_CAN2] = DEV_ENTRY(APB1, CAN2), - [RCC_CAN1] = DEV_ENTRY(APB1, CAN1), - [RCC_I2C3] = DEV_ENTRY(APB1, I2C3), - [RCC_I2C2] = DEV_ENTRY(APB1, I2C2), - [RCC_I2C1] = DEV_ENTRY(APB1, I2C1), - [RCC_UART5] = DEV_ENTRY(APB1, UART5), - [RCC_UART4] = DEV_ENTRY(APB1, UART4), - [RCC_USART3] = DEV_ENTRY(APB1, USART3), - [RCC_USART2] = DEV_ENTRY(APB1, USART2), - [RCC_SPI3] = DEV_ENTRY(APB1, SPI3), - [RCC_SPI2] = DEV_ENTRY(APB1, SPI2), - [RCC_WWDG] = DEV_ENTRY(APB1, WWDG), - [RCC_TIM14] = DEV_ENTRY(APB1, TIM14), - [RCC_TIM13] = DEV_ENTRY(APB1, TIM13), - [RCC_TIM12] = DEV_ENTRY(APB1, TIM12), - [RCC_TIM7] = DEV_ENTRY(APB1, TIM7), - [RCC_TIM6] = DEV_ENTRY(APB1, TIM6), - [RCC_TIM5] = DEV_ENTRY(APB1, TIM5), - [RCC_TIM4] = DEV_ENTRY(APB1, TIM4), - [RCC_TIM3] = DEV_ENTRY(APB1, TIM3), - [RCC_TIM2] = DEV_ENTRY(APB1, TIM2), + [RCC_DAC] = DEV_ENTRY(APB1, DAC), + [RCC_PWR] = DEV_ENTRY(APB1, PWR), + [RCC_CAN2] = DEV_ENTRY(APB1, CAN2), + [RCC_CAN1] = DEV_ENTRY(APB1, CAN1), + [RCC_I2C3] = DEV_ENTRY(APB1, I2C3), + [RCC_I2C2] = DEV_ENTRY(APB1, I2C2), + [RCC_I2C1] = DEV_ENTRY(APB1, I2C1), + [RCC_UART5] = DEV_ENTRY(APB1, UART5), + [RCC_UART4] = DEV_ENTRY(APB1, UART4), + [RCC_USART3] = DEV_ENTRY(APB1, USART3), + [RCC_USART2] = DEV_ENTRY(APB1, USART2), + [RCC_SPI3] = DEV_ENTRY(APB1, SPI3), + [RCC_SPI2] = DEV_ENTRY(APB1, SPI2), + [RCC_WWDG] = DEV_ENTRY(APB1, WWDG), + [RCC_TIMER14] = DEV_ENTRY(APB1, TIM14), + [RCC_TIMER13] = DEV_ENTRY(APB1, TIM13), + [RCC_TIMER12] = DEV_ENTRY(APB1, TIM12), + [RCC_TIMER7] = DEV_ENTRY(APB1, TIM7), + [RCC_TIMER6] = DEV_ENTRY(APB1, TIM6), + [RCC_TIMER5] = DEV_ENTRY(APB1, TIM5), + [RCC_TIMER4] = DEV_ENTRY(APB1, TIM4), + [RCC_TIMER3] = DEV_ENTRY(APB1, TIM3), + [RCC_TIMER2] = DEV_ENTRY(APB1, TIM2), /* APB2 */ - [RCC_TIM11] = DEV_ENTRY(APB2, TIM11), - [RCC_TIM10] = DEV_ENTRY(APB2, TIM10), - [RCC_TIM9] = DEV_ENTRY(APB2, TIM9), - [RCC_SYSCFG] = DEV_ENTRY(APB2, SYSCFG), - [RCC_SPI1] = DEV_ENTRY(APB2, SPI1), - [RCC_SDIO] = DEV_ENTRY(APB2, SDIO), - [RCC_ADC3] = DEV_ENTRY(APB2, ADC3), - [RCC_ADC2] = DEV_ENTRY(APB2, ADC2), - [RCC_ADC1] = DEV_ENTRY(APB2, ADC1), - [RCC_USART6] = DEV_ENTRY(APB2, USART6), - [RCC_USART1] = DEV_ENTRY(APB2, USART1), - [RCC_TIM8] = DEV_ENTRY(APB2, TIM8), - [RCC_TIM1] = DEV_ENTRY(APB2, TIM1), + [RCC_TIMER11] = DEV_ENTRY(APB2, TIM11), + [RCC_TIMER10] = DEV_ENTRY(APB2, TIM10), + [RCC_TIMER9] = DEV_ENTRY(APB2, TIM9), + [RCC_SYSCFG] = DEV_ENTRY(APB2, SYSCFG), + [RCC_SPI1] = DEV_ENTRY(APB2, SPI1), + [RCC_SDIO] = DEV_ENTRY(APB2, SDIO), + [RCC_ADC3] = DEV_ENTRY(APB2, ADC3), + [RCC_ADC2] = DEV_ENTRY(APB2, ADC2), + [RCC_ADC1] = DEV_ENTRY(APB2, ADC1), + [RCC_USART6] = DEV_ENTRY(APB2, USART6), + [RCC_USART1] = DEV_ENTRY(APB2, USART1), + [RCC_TIMER8] = DEV_ENTRY(APB2, TIM8), + [RCC_TIMER1] = DEV_ENTRY(APB2, TIM1), }; /** -- cgit v1.2.3 From f4583644e18bc0b3229c3c7dfb2500004e1a4340 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 9 Apr 2012 13:56:47 -0400 Subject: stm32f2/nvic.h: Fix Doxygen @file directive. This lets Doxygen pick it up. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/nvic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/stm32f2/include/series/nvic.h b/libmaple/stm32f2/include/series/nvic.h index 1daad60..129e3bc 100644 --- a/libmaple/stm32f2/include/series/nvic.h +++ b/libmaple/stm32f2/include/series/nvic.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/nvic.h + * @file libmaple/stm32f2/include/series/nvic.h * @brief STM32F2 nested vectored interrupt controller (NVIC) header. */ -- cgit v1.2.3 From 68800148b998488f09fb36fde53970900c199c0a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 9 Apr 2012 14:03:30 -0400 Subject: stm32f1/nvic.h: Add nvic_irq_num's for XL-density timers; Doxygen fixup. This is a backwards-compatible change, but it deprecates some existing functionality. XL density STM32F1 devices have additional timers 9 through 14. These share NVIC lines with timers 1 and 8. This scheme is also used on e.g. STM32F2, so the corresponding nvic_irq_num enumerators on that series have names like "NVIC_TIMER1_BRK_TIMER9" instead of "NVIC_TIMER1_BRK". For portability (and XL-density support), it makes sense to add these enumerators to the F1 version of nvic_irq_num, which we do here. For backwards compatibility, we keep the old enumerators (like NVIC_TIMER1_BRK) around as aliases to the new ones (like NVIC_TIMER1_BRK_TIMER9). These old enumerators are now deprecated. Also fix up the Doxygen @file header. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/nvic.h | 52 +++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 7 deletions(-) diff --git a/libmaple/stm32f1/include/series/nvic.h b/libmaple/stm32f1/include/series/nvic.h index 33783f3..42c0b37 100644 --- a/libmaple/stm32f1/include/series/nvic.h +++ b/libmaple/stm32f1/include/series/nvic.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/nvic.h + * @file libmaple/stm32f1/include/series/nvic.h * @brief STM32F1 Nested Vectored Interrupt Controller (NVIC) support. */ @@ -78,9 +78,11 @@ typedef enum nvic_irq_num { NVIC_CAN_RX1 = 21, /**< CAN RX1 */ NVIC_CAN_SCE = 22, /**< CAN SCE */ NVIC_EXTI_9_5 = 23, /**< EXTI line [9:5] */ - NVIC_TIMER1_BRK = 24, /**< Timer 1 break */ - NVIC_TIMER1_UP = 25, /**< Timer 1 update */ - NVIC_TIMER1_TRG_COM = 26, /**< Timer 1 trigger and commutation */ + NVIC_TIMER1_BRK_TIMER9 = 24, /**< Timer 1 break, Timer 9. */ + NVIC_TIMER1_UP_TIMER10 = 25, /**< Timer 1 update, Timer 10. */ + NVIC_TIMER1_TRG_COM_TIMER11 = 26, /**< + * Timer 1 trigger and commutation, + * Timer 11. */ NVIC_TIMER1_CC = 27, /**< Timer 1 capture/compare */ NVIC_TIMER2 = 28, /**< Timer 2 */ NVIC_TIMER3 = 29, /**< Timer 3 */ @@ -98,9 +100,11 @@ typedef enum nvic_irq_num { NVIC_RTCALARM = 41, /**< RTC alarm through EXTI line */ NVIC_USBWAKEUP = 42, /**< USB wakeup from suspend through EXTI line */ - NVIC_TIMER8_BRK = 43, /**< Timer 8 break */ - NVIC_TIMER8_UP = 44, /**< Timer 8 update */ - NVIC_TIMER8_TRG_COM = 45, /**< Timer 8 trigger and commutation */ + NVIC_TIMER8_BRK_TIMER12 = 43, /**< Timer 8 break, timer 12 */ + NVIC_TIMER8_UP_TIMER13 = 44, /**< Timer 8 update, timer 13 */ + NVIC_TIMER8_TRG_COM_TIMER14 = 45, /**< + * Timer 8 trigger and commutation, + * Timer 14. */ NVIC_TIMER8_CC = 46, /**< Timer 8 capture/compare */ NVIC_ADC3 = 47, /**< ADC3 */ NVIC_FSMC = 48, /**< FSMC */ @@ -115,6 +119,40 @@ typedef enum nvic_irq_num { NVIC_DMA2_CH2 = 57, /**< DMA2 channel 2 */ NVIC_DMA2_CH3 = 58, /**< DMA2 channel 3 */ NVIC_DMA2_CH_4_5 = 59, /**< DMA2 channels 4 and 5 */ + + /* Old enumerators kept around for backwards compatibility: */ + NVIC_TIMER1_BRK = + NVIC_TIMER1_BRK_TIMER9, /**< @brief (Deprecated) Timer 1 break + * + * For backwards compatibility only. + * Use NVIC_TIMER1_BRK_TIMER9 instead. */ + NVIC_TIMER1_UP = + NVIC_TIMER1_UP_TIMER10, /**< @brief (Deprecated) Timer 1 update. + * + * For backwards compatibility only. + * Use NVIC_TIMER1_UP_TIMER10 instead. */ + NVIC_TIMER1_TRG_COM = + NVIC_TIMER1_TRG_COM_TIMER11, /**< @brief (deprecated) Timer 1 trigger + * and commutation. + * + * For backwards compatibility only. + * Use NVIC_TIMER1_TRG_COM_TIMER11 + * instead. */ + NVIC_TIMER8_BRK = + NVIC_TIMER8_BRK_TIMER12, /**< @brief (deprecated) Timer 8 break + * + * For backwards compatibility only. + * Use NVIC_TIMER8_BRK_TIMER12 instead. */ + NVIC_TIMER8_UP = + NVIC_TIMER8_UP_TIMER13, /**< @brief (deprecated) Timer 8 update + * For backwards compatibility only. + * Use NVIC_TIMER8_UP_TIMER13 instead. */ + NVIC_TIMER8_TRG_COM = + NVIC_TIMER8_TRG_COM_TIMER14, /**< @brief (deprecated) Timer 8 trigger + * and commutation. + * For backwards compatibility only. + * Use NVIC_TIMER8_TRG_COM_TIMER14 + * instead. */ } nvic_irq_num; static inline void nvic_irq_disable_all(void) { -- cgit v1.2.3 From 42059788b4fff74fddfc7d391e82c316b6901211 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 9 Apr 2012 15:14:01 -0400 Subject: libmaple/timer_private.h: Add more explanatory comments. Hopefully these will be helpful when adding timer support for additional series in the future. Signed-off-by: Marti Bolivar --- libmaple/timer_private.h | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/libmaple/timer_private.h b/libmaple/timer_private.h index f882f51..54e3ea1 100644 --- a/libmaple/timer_private.h +++ b/libmaple/timer_private.h @@ -34,21 +34,30 @@ #define _LIBMAPLE_TIMER_PRIVATE_H_ /* - * Devices + * Helper macros for declaring timer_devs of various timer_types */ -/* Just like the corresponding DIER bits: +/* The indexes of user handlers in a timer_dev.handlers are just like + * the corresponding DIER bits, as follows: */ + +/* Advanced timers: * [0] = Update handler; * [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively; * [5] = COM; * [6] = TRG; * [7] = BRK. */ #define NR_ADV_HANDLERS 8 -/* Update, capture/compare 1,2,3,4; ; trigger. */ +/* General purpose timers: + * [0] = update; + * [1,2,3,4] = capture/compare 1,2,3,4; + * [5] = ; + * [6] = trigger. */ #define NR_GEN_HANDLERS 7 -/* Update only. */ +/* Basic timers: + * [0] = update. */ #define NR_BAS_HANDLERS 1 +/* For declaring advanced timers. */ #define DECLARE_ADVANCED_TIMER(name, num) \ timer_dev name = { \ .regs = { .adv = TIMER##num##_BASE }, \ @@ -57,6 +66,7 @@ .handlers = { [NR_ADV_HANDLERS - 1] = 0 }, \ } +/* For declaring full-featured general purpose timers. */ #define DECLARE_GENERAL_TIMER(name, num) \ timer_dev name = { \ .regs = { .gen = TIMER##num##_BASE }, \ @@ -65,6 +75,7 @@ .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, \ } +/* For declaring basic timers (e.g. TIM6 and TIM7). */ #define DECLARE_BASIC_TIMER(name, num) \ timer_dev name = { \ .regs = { .bas = TIMER##num##_BASE }, \ @@ -75,13 +86,21 @@ /* * IRQ handlers - */ - -/* Note: the following dispatch routines make use of the fact that - * DIER interrupt enable bits and SR interrupt flags have common bit - * positions. Thus, ANDing DIER and SR lets us check if an interrupt - * is enabled and if it has occurred simultaneously. - */ + * + * These decode TIMx_DIER and TIMx_SR, then dispatch to the user-level + * IRQ handlers. They also clean up TIMx_SR afterwards, so the user + * doesn't have to deal with register details. + * + * Notes: + * + * - These dispatch routines make use of the fact that DIER interrupt + * enable bits and SR interrupt flags have common bit positions. + * Thus, ANDing DIER and SR lets us check if an interrupt is enabled + * and if it has occurred simultaneously. + * + * - We force these routines to inline to avoid call overhead, but + * there aren't any measurements to prove that this is actually a + * good idea. Profile-directed optimizations are definitely wanted. */ /* A special-case dispatch routine for single-interrupt NVIC lines. * This function assumes that the interrupt corresponding to `iid' has @@ -97,7 +116,7 @@ static __always_inline void dispatch_single_irq(timer_dev *dev, } } -/* For dispatch routines which service multiple interrupts. */ +/* Helper macro for dispatch routines which service multiple interrupts. */ #define handle_irq(dier_sr, irq_mask, handlers, iid, handled_irq) do { \ if ((dier_sr) & (irq_mask)) { \ void (*__handler)(void) = (handlers)[iid]; \ -- cgit v1.2.3 From 378a766ec86694a6be0f8e38976473646c82702c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 9 Apr 2012 16:05:50 -0400 Subject: libmaple/timer_private.h: Update to support TIM9-TIM14. Add DECLARE_RESTRICTED_GENERAL_TIMER(), for declaring general-purpose timers with limited interrupt support -- that is, for declaring timers 9 through 14. This helps avoid wasting space on pointers to user handlers for interrupts that don't exist. Add dispatch_tim_9_12() and dispatch_tim_10_11_13_14(), which are special purpose dispatch routines for these "restricted" general purpose timers, which only try to dispatch interrupts supported by these timers. Change dispatch_single_irq() to check the logical and of the DIER and SR registers for the timer whose interrupt it's dispatching. This is necessary due to increased muxing on the timer IRQ lines caused by the new timers. See the comment in the patch for more details. This does add overhead on medium- and high-density STM32F1s, where the extra check is unnecessary, but it doesn't change dispatch_single_irq()'s semantics, and keeps the implementation simple, so we'll live with it. These changes will also work on F2 (and F4 AFAIK), which is why they're part of the global private timer API, as opposed to libmaple/stm32f1/timer.c. Signed-off-by: Marti Bolivar --- libmaple/timer_private.h | 62 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/libmaple/timer_private.h b/libmaple/timer_private.h index 54e3ea1..0eb569d 100644 --- a/libmaple/timer_private.h +++ b/libmaple/timer_private.h @@ -75,6 +75,17 @@ .handlers = { [NR_GEN_HANDLERS - 1] = 0 }, \ } +/* For declaring general purpose timers with limited interrupt + * capability (e.g. timers 9 through 14 on STM32F2 and XL-density + * STM32F1). */ +#define DECLARE_RESTRICTED_GENERAL_TIMER(name, num, max_dier_bit) \ + timer_dev name = { \ + .regs = { .gen = TIMER##num##_BASE }, \ + .clk_id = RCC_TIMER##num, \ + .type = TIMER_GENERAL, \ + .handlers = { [max_dier_bit] = 0 }, \ + } + /* For declaring basic timers (e.g. TIM6 and TIM7). */ #define DECLARE_BASIC_TIMER(name, num) \ timer_dev name = { \ @@ -102,17 +113,24 @@ * there aren't any measurements to prove that this is actually a * good idea. Profile-directed optimizations are definitely wanted. */ -/* A special-case dispatch routine for single-interrupt NVIC lines. - * This function assumes that the interrupt corresponding to `iid' has - * in fact occurred (i.e., it doesn't check DIER & SR). */ +/* A special-case dispatch routine for timers which only serve a + * single interrupt on a given IRQ line. + * + * This function still checks DIER & SR, as in some cases, a timer may + * only serve a single interrupt on a particular NVIC line, but that + * line may be shared with another timer. For example, the timer 1 + * update interrupt shares an IRQ line with the timer 10 interrupt on + * STM32F1 (XL-density), STM32F2, and STM32F4. */ static __always_inline void dispatch_single_irq(timer_dev *dev, timer_interrupt_id iid, uint32 irq_mask) { timer_bas_reg_map *regs = (dev->regs).bas; - void (*handler)(void) = dev->handlers[iid]; - if (handler) { - handler(); - regs->SR &= ~irq_mask; + if (regs->DIER & regs->SR & irq_mask) { + void (*handler)(void) = dev->handlers[iid]; + if (handler) { + handler(); + regs->SR &= ~irq_mask; + } } } @@ -180,6 +198,36 @@ static __always_inline void dispatch_general(timer_dev *dev) { regs->SR &= ~handled; } +/* On F1 (XL-density), F2, and F4, TIM9 and TIM12 are restricted + * general-purpose timers with update, CC1, CC2, and TRG interrupts. */ +static __always_inline void dispatch_tim_9_12(timer_dev *dev) { + timer_gen_reg_map *regs = (dev->regs).gen; + uint32 dsr = regs->DIER & regs->SR; + void (**hs)(void) = dev->handlers; + uint32 handled = 0; + + handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled); + + regs->SR &= ~handled; +} + +/* On F1 (XL-density), F2, and F4, timers 10, 11, 13, and 14 are + * restricted general-purpose timers with update and CC1 interrupts. */ +static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) { + timer_gen_reg_map *regs = (dev->regs).gen; + uint32 dsr = regs->DIER & regs->SR; + void (**hs)(void) = dev->handlers; + uint32 handled = 0; + + handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled); + handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled); + + regs->SR &= ~handled; +} + static __always_inline void dispatch_basic(timer_dev *dev) { dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); } -- cgit v1.2.3 From 08c56bb56a5ba4028ad761a8ff05ead0f54a549c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 9 Apr 2012 16:38:01 -0400 Subject: STM32F1: Add support for timers 9 through 14. This applies to XL-density STM32F1 devices. In stm32f1/timer.c, add timer_dev's for the new timers, using the timer_private API. These definitions are conditionally compiled based on the target density to avoid wasting space on smaller MCUs. Also add calls to the appropriate timer_private.h dispatch routines within the IRQ handlers for these timers. We need to change the IRQ handler names to reflect this eventually, but put that off for now, as it could break backwards compatibility in some exotic situations where the user refers to the libmaple IRQ handlers directly. In stm32f1/timer.h, add register map base pointers and device declarations for the new timers. timer_dev* declarations are compiled in only when the target MCU supports them, in keeping with the above stm32f1/timer.c changes. In libmaple/timer.c, update the (static) IRQ enable routines to account for the additional timers. This adds some code that's unnecessary on smaller STM32F1s, but it's minimal (40 extra bytes on my machine), so portability and readability win out. Size change, using GCC version "(Sourcery G++ Lite 2011.03-42) 4.5.2": Before: text data bss dec hex filename 615 0 0 615 267 build/home/mbolivar/leaf/libmaple/libmaple/timer.o After: text data bss dec hex filename 655 0 0 655 28f build/home/mbolivar/leaf/libmaple/libmaple/timer.o Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 8 +-- libmaple/stm32f1/include/series/timer.h | 42 ++++++++++++++-- libmaple/stm32f1/timer.c | 83 ++++++++++++++++++++++++++++-- libmaple/timer.c | 89 +++++++++++++++++++++++---------- 4 files changed, 180 insertions(+), 42 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index e98759a..0a34066 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -37,18 +37,12 @@ extern "C"{ #endif +#include #include #include #include #include -struct timer_adv_reg_map; -struct timer_gen_reg_map; -struct timer_bas_reg_map; -struct timer_dev; -/* Include the series header here, as it may need the above */ -#include - /* * Register maps */ diff --git a/libmaple/stm32f1/include/series/timer.h b/libmaple/stm32f1/include/series/timer.h index 9bd273e..2551f70 100644 --- a/libmaple/stm32f1/include/series/timer.h +++ b/libmaple/stm32f1/include/series/timer.h @@ -33,11 +33,10 @@ #ifndef _LIBMAPLE_STM32F1_TIMER_H_ #define _LIBMAPLE_STM32F1_TIMER_H_ -#include -#include +#include /* - * Register maps and devices + * Register maps and base pointers */ /** STM32F1 general purpose timer register map type */ @@ -64,6 +63,10 @@ typedef struct timer_gen_reg_map { __io uint32 DMAR; /**< DMA address for full transfer */ } timer_gen_reg_map; +struct timer_adv_reg_map; +struct timer_gen_reg_map; +struct timer_bas_reg_map; + /** Timer 1 register map base pointer */ #define TIMER1_BASE ((struct timer_adv_reg_map*)0x40012C00) /** Timer 2 register map base pointer */ @@ -72,7 +75,6 @@ typedef struct timer_gen_reg_map { #define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) /** Timer 4 register map base pointer */ #define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) /** Timer 5 register map base pointer */ #define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) /** Timer 6 register map base pointer */ @@ -81,7 +83,29 @@ typedef struct timer_gen_reg_map { #define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) /** Timer 8 register map base pointer */ #define TIMER8_BASE ((struct timer_adv_reg_map*)0x40013400) -#endif +/** Timer 9 register map base pointer */ +#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40014C00) +/** Timer 10 register map base pointer */ +#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40015000) +/** Timer 11 register map base pointer */ +#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40015400) +/** Timer 12 register map base pointer */ +#define TIMER12_BASE ((struct timer_gen_reg_map*)0x40001800) +/** Timer 13 register map base pointer */ +#define TIMER13_BASE ((struct timer_gen_reg_map*)0x40001C00) +/** Timer 14 register map base pointer */ +#define TIMER14_BASE ((struct timer_gen_reg_map*)0x40002000) + +/* + * Device pointers + * + * We only declare device pointers to timers which actually exist on + * the target MCU. This helps when porting programs to STM32F1 (or + * within F1 to a lower density MCU), as attempts to use nonexistent + * timers cause build errors instead of undefined behavior. + */ + +struct timer_dev; extern struct timer_dev *TIMER1; extern struct timer_dev *TIMER2; @@ -93,5 +117,13 @@ extern struct timer_dev *TIMER6; extern struct timer_dev *TIMER7; extern struct timer_dev *TIMER8; #endif +#ifdef STM32_XL_DENSITY +extern struct timer_dev *TIMER9; +extern struct timer_dev *TIMER10; +extern struct timer_dev *TIMER11; +extern struct timer_dev *TIMER12; +extern struct timer_dev *TIMER13; +extern struct timer_dev *TIMER14; +#endif #endif diff --git a/libmaple/stm32f1/timer.c b/libmaple/stm32f1/timer.c index 7506cb6..899abbc 100644 --- a/libmaple/stm32f1/timer.c +++ b/libmaple/stm32f1/timer.c @@ -30,14 +30,30 @@ * @brief STM32F1 timer support. */ +/* Notes: + * + * - We use STM32F1 density test macros throughout to avoid defining + * symbols or linking in code that would use timers that are + * unavailable in a given density. For example, TIM5 doesn't exist + * on medium-density, and TIM9 doesn't exist on high-density, so we + * don't define or use TIM5 when being compiled for medium-density, + * and similarly for TIM9 and high-density. + * + * This makes a mess, but helps avoid bloat and ensures backwards + * compatibility. Since the mess is manageable and there don't seem + * to be any plans on ST's part to add new STM32F1 lines or + * densities, we'll live with it. + */ + #include #include "timer_private.h" /* * Devices + * + * Defer to the timer_private API. */ -/* Use timer_private macros to save typing. */ static DECLARE_ADVANCED_TIMER(timer1, 1); static DECLARE_GENERAL_TIMER(timer2, 2); static DECLARE_GENERAL_TIMER(timer3, 3); @@ -66,7 +82,35 @@ timer_dev *TIMER6 = &timer6; timer_dev *TIMER7 = &timer7; /** Timer 8 device (advanced) */ timer_dev *TIMER8 = &timer8; -#endif +#endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */ + +#ifdef STM32_XL_DENSITY +/* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer9, 9, TIMER_DIER_TIE_BIT); +/* TIM10 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer10, 10, TIMER_DIER_CC1IE_BIT); +/* TIM11 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer11, 11, TIMER_DIER_CC1IE_BIT); +/* TIM12 has UIE, CC1IE, CC2IE, TIE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer12, 12, TIMER_DIER_TIE_BIT); +/* TIM13 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer13, 13, TIMER_DIER_CC1IE_BIT); +/* TIM14 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer14, 14, TIMER_DIER_CC1IE_BIT); + +/** Timer 9 device (general-purpose) */ +timer_dev *TIMER9 = &timer9; +/** Timer 10 device (general-purpose) */ +timer_dev *TIMER10 = &timer10; +/** Timer 11 device (general-purpose) */ +timer_dev *TIMER11 = &timer11; +/** Timer 12 device (general-purpose) */ +timer_dev *TIMER12 = &timer12; +/** Timer 13 device (general-purpose) */ +timer_dev *TIMER13 = &timer13; +/** Timer 14 device (general-purpose) */ +timer_dev *TIMER14 = &timer14; +#endif /* STM32_XL_DENSITY */ /* * Routines @@ -87,22 +131,46 @@ void timer_foreach(void (*fn)(timer_dev*)) { fn(TIMER7); fn(TIMER8); #endif +#ifdef STM32_XL_DENSITY + fn(TIMER9); + fn(TIMER10); + fn(TIMER11); + fn(TIMER12); + fn(TIMER13); + fn(TIMER14); +#endif } /* * IRQ handlers + * + * Defer to the timer_private dispatch API. + * + * FIXME: The names of these handlers are inaccurate since XL-density + * devices came out. Update these to match the STM32F2 names, maybe + * using some weak symbol magic to preserve backwards compatibility if + * possible. */ void __irq_tim1_brk(void) { dispatch_adv_brk(TIMER1); +#ifdef STM32_XL_DENSITY + dispatch_tim_9_12(TIMER9); +#endif } void __irq_tim1_up(void) { dispatch_adv_up(TIMER1); +#ifdef STM32_XL_DENSITY + dispatch_tim_10_11_13_14(TIMER10); +#endif } void __irq_tim1_trg_com(void) { dispatch_adv_trg_com(TIMER1); +#ifdef STM32_XL_DENSITY + dispatch_tim_10_11_13_14(TIMER11); +#endif } void __irq_tim1_cc(void) { @@ -136,17 +204,26 @@ void __irq_tim7(void) { void __irq_tim8_brk(void) { dispatch_adv_brk(TIMER8); +#ifdef STM32_XL_DENSITY + dispatch_tim_9_12(TIMER12); +#endif } void __irq_tim8_up(void) { dispatch_adv_up(TIMER8); +#ifdef STM32_XL_DENSITY + dispatch_tim_10_11_13_14(TIMER13); +#endif } void __irq_tim8_trg_com(void) { dispatch_adv_trg_com(TIMER8); +#ifdef STM32_XL_DENSITY + dispatch_tim_10_11_13_14(TIMER14); +#endif } void __irq_tim8_cc(void) { dispatch_adv_cc(TIMER8); } -#endif +#endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */ diff --git a/libmaple/timer.c b/libmaple/timer.c index d64e3e9..d204fef 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -152,66 +152,101 @@ static void output_compare_mode(timer_dev *dev, uint8 channel) { timer_cc_enable(dev, channel); } -/* FIXME: These IRQ enable routines fail for timers 9 through 14. - * We don't support those timers yet, so it's OK for now, but this - * really needs to get fixed. */ - -static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id); -static void enable_nonmuxed_irq(timer_dev *dev); +static void enable_adv_irq(timer_dev *dev, timer_interrupt_id id); +static void enable_bas_gen_irq(timer_dev *dev); static inline void enable_irq(timer_dev *dev, timer_interrupt_id iid) { if (dev->type == TIMER_ADVANCED) { - enable_advanced_irq(dev, iid); + enable_adv_irq(dev, iid); } else { - enable_nonmuxed_irq(dev); + enable_bas_gen_irq(dev); } } -static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id) { - uint8 is_timer1 = dev->clk_id == RCC_TIMER1; - +/* Advanced control timers have several IRQ lines corresponding to + * different timer interrupts. + * + * Note: This function assumes that the only advanced timers are TIM1 + * and TIM8, and needs the obvious changes if that assumption is + * violated by a later STM32 series. */ +static void enable_adv_irq(timer_dev *dev, timer_interrupt_id id) { + uint8 is_tim1 = dev->clk_id == RCC_TIMER1; + nvic_irq_num irq_num; switch (id) { case TIMER_UPDATE_INTERRUPT: - nvic_irq_enable(is_timer1 ? NVIC_TIMER1_UP : NVIC_TIMER8_UP); + irq_num = (is_tim1 ? + NVIC_TIMER1_UP_TIMER10 : + NVIC_TIMER8_UP_TIMER13); break; - case TIMER_CC1_INTERRUPT: - case TIMER_CC2_INTERRUPT: - case TIMER_CC3_INTERRUPT: + case TIMER_CC1_INTERRUPT: /* Fall through */ + case TIMER_CC2_INTERRUPT: /* ... */ + case TIMER_CC3_INTERRUPT: /* ... */ case TIMER_CC4_INTERRUPT: - nvic_irq_enable(is_timer1 ? NVIC_TIMER1_CC : NVIC_TIMER8_CC); + irq_num = is_tim1 ? NVIC_TIMER1_CC : NVIC_TIMER8_CC; break; - case TIMER_COM_INTERRUPT: + case TIMER_COM_INTERRUPT: /* Fall through */ case TIMER_TRG_INTERRUPT: - nvic_irq_enable(is_timer1 ? NVIC_TIMER1_TRG_COM : NVIC_TIMER8_TRG_COM); + irq_num = (is_tim1 ? + NVIC_TIMER1_TRG_COM_TIMER11 : + NVIC_TIMER8_TRG_COM_TIMER14); break; case TIMER_BREAK_INTERRUPT: - nvic_irq_enable(is_timer1 ? NVIC_TIMER1_BRK : NVIC_TIMER8_BRK); + irq_num = (is_tim1 ? + NVIC_TIMER1_BRK_TIMER9 : + NVIC_TIMER8_BRK_TIMER12); break; + default: + /* Can't happen, but placate the compiler */ + ASSERT(0); + return; } + nvic_irq_enable(irq_num); } -static void enable_nonmuxed_irq(timer_dev *dev) { +/* Basic and general purpose timers have a single IRQ line, which is + * shared by all interrupts supported by a particular timer. */ +static void enable_bas_gen_irq(timer_dev *dev) { + nvic_irq_num irq_num; switch (dev->clk_id) { case RCC_TIMER2: - nvic_irq_enable(NVIC_TIMER2); + irq_num = NVIC_TIMER2; break; case RCC_TIMER3: - nvic_irq_enable(NVIC_TIMER3); + irq_num = NVIC_TIMER3; break; case RCC_TIMER4: - nvic_irq_enable(NVIC_TIMER4); + irq_num = NVIC_TIMER4; break; case RCC_TIMER5: - nvic_irq_enable(NVIC_TIMER5); + irq_num = NVIC_TIMER5; break; case RCC_TIMER6: - nvic_irq_enable(NVIC_TIMER6); + irq_num = NVIC_TIMER6; break; case RCC_TIMER7: - nvic_irq_enable(NVIC_TIMER7); + irq_num = NVIC_TIMER7; + break; + case RCC_TIMER9: + irq_num = NVIC_TIMER1_BRK_TIMER9; + break; + case RCC_TIMER10: + irq_num = NVIC_TIMER1_UP_TIMER10; + break; + case RCC_TIMER11: + irq_num = NVIC_TIMER1_TRG_COM_TIMER11; + break; + case RCC_TIMER12: + irq_num = NVIC_TIMER8_BRK_TIMER12; + break; + case RCC_TIMER13: + irq_num = NVIC_TIMER8_UP_TIMER13; + break; + case RCC_TIMER14: + irq_num = NVIC_TIMER8_TRG_COM_TIMER14; break; default: ASSERT_FAULT(0); - break; + return; } + nvic_irq_enable(irq_num); } -- cgit v1.2.3 From 5a2df8d18f1b0f6c7aa9ec0a4a1413a49929d4e6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 15:00:47 -0400 Subject: stm32f2/rcc.h: Fix Doxygen file header. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 540eb66..d797ba9 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/rcc.h + * @file libmaple/stm32f2/include/series/rcc.h * @brief STM32F2 reset and clock control (RCC) header. */ -- cgit v1.2.3 From 8ca93860929f99807190bf43049dce750cff4b2c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 15:00:57 -0400 Subject: libmaple/rcc.h: Fix Doxygen file header. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 4693606..b04f016 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file rcc.h + * @file libmaple/rcc.h * @brief Reset and Clock Control (RCC) interface. */ -- cgit v1.2.3 From 3300145b6c7cb9cc1d57c47f0ed85bd16e57c615 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 15:22:21 -0400 Subject: stm32f2/nvic.h: Add fake NVIC_TIMER6 irq number. This is necessary to make some timer code portable, but I'm not sure it's a good idea. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/nvic.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libmaple/stm32f2/include/series/nvic.h b/libmaple/stm32f2/include/series/nvic.h index 129e3bc..c433068 100644 --- a/libmaple/stm32f2/include/series/nvic.h +++ b/libmaple/stm32f2/include/series/nvic.h @@ -141,6 +141,10 @@ typedef enum nvic_irq_num { NVIC_CRYP = 79, /**< Cryptographic processor */ NVIC_HASH_RNG = 80, /**< Hash and random number generation */ + + /* Fake enumerator values, for compatiblity with F1. + * TODO decide if this is actually a good idea. */ + NVIC_TIMER6 = NVIC_TIMER6_DAC, /**< For compatibility with STM32F1. */ } nvic_irq_num; static inline void nvic_irq_disable_all(void) { -- cgit v1.2.3 From 31fbdb5994338592c1b122b52c04bffaaddb3be8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 15:23:38 -0400 Subject: STM32F2: Add timer support. Standard series peripheral support patch, containing STM32F2 series timer.h and timer.c. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/timer.h | 170 +++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + libmaple/stm32f2/timer.c | 185 ++++++++++++++++++++++++++++++++ 3 files changed, 356 insertions(+) create mode 100644 libmaple/stm32f2/include/series/timer.h create mode 100644 libmaple/stm32f2/timer.c diff --git a/libmaple/stm32f2/include/series/timer.h b/libmaple/stm32f2/include/series/timer.h new file mode 100644 index 0000000..cf7cc15 --- /dev/null +++ b/libmaple/stm32f2/include/series/timer.h @@ -0,0 +1,170 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011,2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file stm32f2/include/series/timer.h + * @author Marti Bolivar + * @brief STM32F2 timer sub-header. + */ + +#ifndef _LIBMAPLE_STM32F2_TIMER_H_ +#define _LIBMAPLE_STM32F2_TIMER_H_ + +#include + +/* + * Register maps and base pointers + */ + +/** + * @brief STM32F2 general purpose timer register map type + * + * Note that not all general purpose timers have all of these + * registers. Consult your chip's reference manual for the details. + */ +typedef struct timer_gen_reg_map { + __io uint32 CR1; /**< Control register 1 */ + __io uint32 CR2; /**< Control register 2 */ + __io uint32 SMCR; /**< Slave mode control register */ + __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 SR; /**< Status register */ + __io uint32 EGR; /**< Event generation register */ + __io uint32 CCMR1; /**< Capture/compare mode register 1 */ + __io uint32 CCMR2; /**< Capture/compare mode register 2 */ + __io uint32 CCER; /**< Capture/compare enable register */ + __io uint32 CNT; /**< Counter */ + __io uint32 PSC; /**< Prescaler */ + __io uint32 ARR; /**< Auto-reload register */ + const uint32 RESERVED1; /**< Reserved */ + __io uint32 CCR1; /**< Capture/compare register 1 */ + __io uint32 CCR2; /**< Capture/compare register 2 */ + __io uint32 CCR3; /**< Capture/compare register 3 */ + __io uint32 CCR4; /**< Capture/compare register 4 */ + const uint32 RESERVED2; /**< Reserved */ + __io uint32 DCR; /**< DMA control register */ + __io uint32 DMAR; /**< DMA address for full transfer */ + __io uint32 OR; /**< Option register. */ +} timer_gen_reg_map; + +struct timer_adv_reg_map; +struct timer_gen_reg_map; +struct timer_bas_reg_map; + +/** Timer 1 register map base pointer */ +#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40010000) +/** Timer 2 register map base pointer */ +#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000) +/** Timer 3 register map base pointer */ +#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400) +/** Timer 4 register map base pointer */ +#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800) +/** Timer 5 register map base pointer */ +#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00) +/** Timer 6 register map base pointer */ +#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000) +/** Timer 7 register map base pointer */ +#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400) +/** Timer 8 register map base pointer */ +#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40010400) +/** Timer 9 register map base pointer */ +#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40014000) +/** Timer 10 register map base pointer */ +#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40014400) +/** Timer 11 register map base pointer */ +#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40014800) +/** Timer 12 register map base pointer */ +#define TIMER12_BASE ((struct timer_gen_reg_map*)0x40001800) +/** Timer 13 register map base pointer */ +#define TIMER13_BASE ((struct timer_gen_reg_map*)0x40001C00) +/** Timer 14 register map base pointer */ +#define TIMER14_BASE ((struct timer_gen_reg_map*)0x40002000) + +/* + * Register bit definitions + */ + +/* TIM2 option register */ + +/** Timer 2 option register internal trigger 1 remap */ +#define TIMER2_OR_ITR1_RMP (0x3 << 10) +/** Timer 2 OR internal trigger 1: TIM8_TRGOUT */ +#define TIMER2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10) +/** Timer 2 OR internal trigger 1: Ethernet PTP trigger output */ +#define TIMER2_OR_ITR1_RMP_PTP_TRGOUT (0x1 << 10) +/** Timer 2 OR internal trigger 1: USB OTG full speed start of frame */ +#define TIMER2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) +/** Timer 2 OR internal trigger 1: USB OTG high speed start of frame */ +#define TIMER2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) + +/* TIM5 option register */ + +/** + * Timer 5 option register input 4 remap. + * + * These bits control whether TIM5_CH4 is connected to a GPIO or a + * clock. Connecting to a GPIO is the normal mode, useful for e.g. PWM + * generation or input pulse duration measurement. Connecting to a + * clock is useful for calibrating that clock. + */ +#define TIMER5_OR_TI4_RMP (0x3 << 6) +/** + * Timer 5 OR input 4: Timer 5 channel 4 connected to GPIO. */ +#define TIMER5_OR_TI4_RMP_GPIO (0x0 << 6) +/** + * Timer 5 OR input 4: low speed internal clock (LSI) is connected to + * TIM5_CH4. */ +#define TIMER5_OR_TI4_RMP_LSI (0x1 << 6) +/** + * Timer 5 OR input 4: low speed external clock (LSE) is connected to + * TIM5_CH4. */ +#define TIMER5_OR_TI4_RMP_LSE (0x2 << 6) +/** + * Timer 5 OR input 4: real time clock (RTC) output is connected to + * TIM5_CH4. */ +#define TIMER5_OR_TI4_RMP_RTC (0x3 << 6) + +/* + * Device pointers + */ + +struct timer_dev; + +extern struct timer_dev *TIMER1; +extern struct timer_dev *TIMER2; +extern struct timer_dev *TIMER3; +extern struct timer_dev *TIMER4; +extern struct timer_dev *TIMER5; +extern struct timer_dev *TIMER6; +extern struct timer_dev *TIMER7; +extern struct timer_dev *TIMER8; +extern struct timer_dev *TIMER9; +extern struct timer_dev *TIMER10; +extern struct timer_dev *TIMER11; +extern struct timer_dev *TIMER12; +extern struct timer_dev *TIMER13; +extern struct timer_dev *TIMER14; + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 5951b94..c98f5b9 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -15,6 +15,7 @@ cSRCS_$(d) := adc.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c +cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f2/timer.c b/libmaple/stm32f2/timer.c new file mode 100644 index 0000000..eed7810 --- /dev/null +++ b/libmaple/stm32f2/timer.c @@ -0,0 +1,185 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/timer.c + * @author Marti Bolivar + * @brief STM32F2 timer support. + */ + +#include +#include "timer_private.h" + +/* + * Devices + * + * Defer to the timer_private API for declaring these. + */ + +static DECLARE_ADVANCED_TIMER(timer1, 1); +static DECLARE_GENERAL_TIMER(timer2, 2); +static DECLARE_GENERAL_TIMER(timer3, 3); +static DECLARE_GENERAL_TIMER(timer4, 4); +static DECLARE_GENERAL_TIMER(timer5, 5); +static DECLARE_BASIC_TIMER(timer6, 6); +static DECLARE_BASIC_TIMER(timer7, 7); +static DECLARE_ADVANCED_TIMER(timer8, 8); +/* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer9, 9, TIMER_DIER_TIE_BIT); +/* TIM10 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer10, 10, TIMER_DIER_CC1IE_BIT); +/* TIM11 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer11, 11, TIMER_DIER_CC1IE_BIT); +/* TIM12 has UIE, CC1IE, CC2IE, TIE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer12, 12, TIMER_DIER_TIE_BIT); +/* TIM13 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer13, 13, TIMER_DIER_CC1IE_BIT); +/* TIM14 has UIE, CC1IE. */ +static DECLARE_RESTRICTED_GENERAL_TIMER(timer14, 14, TIMER_DIER_CC1IE_BIT); + +/** Timer 1 device (advanced) */ +timer_dev *TIMER1 = &timer1; +/** Timer 2 device (general-purpose) */ +timer_dev *TIMER2 = &timer2; +/** Timer 3 device (general-purpose) */ +timer_dev *TIMER3 = &timer3; +/** Timer 4 device (general-purpose) */ +timer_dev *TIMER4 = &timer4; +/** Timer 5 device (general-purpose) */ +timer_dev *TIMER5 = &timer5; +/** Timer 6 device (basic) */ +timer_dev *TIMER6 = &timer6; +/** Timer 7 device (basic) */ +timer_dev *TIMER7 = &timer7; +/** Timer 8 device (advanced) */ +timer_dev *TIMER8 = &timer8; +/** Timer 9 device (general-purpose) */ +timer_dev *TIMER9 = &timer9; +/** Timer 10 device (general-purpose) */ +timer_dev *TIMER10 = &timer10; +/** Timer 11 device (general-purpose) */ +timer_dev *TIMER11 = &timer11; +/** Timer 12 device (general-purpose) */ +timer_dev *TIMER12 = &timer12; +/** Timer 13 device (general-purpose) */ +timer_dev *TIMER13 = &timer13; +/** Timer 14 device (general-purpose) */ +timer_dev *TIMER14 = &timer14; + +/* + * Routines + */ + +/** + * @brief Call a function on timer devices. + * @param fn Function to call on each timer device. + */ +void timer_foreach(void (*fn)(timer_dev*)) { + fn(TIMER1); + fn(TIMER2); + fn(TIMER3); + fn(TIMER4); + fn(TIMER5); + fn(TIMER6); + fn(TIMER7); + fn(TIMER8); + fn(TIMER9); + fn(TIMER10); + fn(TIMER11); + fn(TIMER12); + fn(TIMER13); + fn(TIMER14); +} + +/* + * IRQ handlers + * + * Defer to the timer_private dispatch API. + */ + +void __irq_tim1_brk_tim9(void) { + dispatch_adv_brk(TIMER1); + dispatch_tim_9_12(TIMER9); +} + +void __irq_tim1_up_tim10(void) { + dispatch_adv_up(TIMER1); + dispatch_tim_10_11_13_14(TIMER10); +} + +void __irq_tim1_trg_com_tim11(void) { + dispatch_adv_trg_com(TIMER1); + dispatch_tim_10_11_13_14(TIMER11); +} + +void __irq_tim1_cc(void) { + dispatch_adv_cc(TIMER1); +} + +void __irq_tim2(void) { + dispatch_general(TIMER2); +} + +void __irq_tim3(void) { + dispatch_general(TIMER3); +} + +void __irq_tim4(void) { + dispatch_general(TIMER4); +} + +void __irq_tim5(void) { + dispatch_general(TIMER5); +} + +/* FIXME: this is also the DAC DMA underrun interrupt, so it needs a + * different name (and to be supported?). */ +void __irq_tim6(void) { + dispatch_basic(TIMER6); +} + +void __irq_tim7(void) { + dispatch_basic(TIMER7); +} + +void __irq_tim8_brk_tim12(void) { + dispatch_adv_brk(TIMER8); + dispatch_tim_9_12(TIMER12); +} + +void __irq_tim8_up_tim13(void) { + dispatch_adv_up(TIMER8); + dispatch_tim_10_11_13_14(TIMER13); +} + +void __irq_tim8_trg_com_tim14(void) { + dispatch_adv_trg_com(TIMER8); + dispatch_tim_10_11_13_14(TIMER14); +} + +void __irq_tim8_cc(void) { + dispatch_adv_cc(TIMER8); +} -- cgit v1.2.3 From 44d1b1c763291283da8e346849ffc2a187032884 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 15:24:01 -0400 Subject: Update examples/test.timers.cpp. Currently passing on STM32F2. Signed-off-by: Marti Bolivar --- examples/test-timers.cpp | 708 +++++++++++++++++++++++++++++++---------------- 1 file changed, 474 insertions(+), 234 deletions(-) diff --git a/examples/test-timers.cpp b/examples/test-timers.cpp index 2a8223c..1f376b7 100644 --- a/examples/test-timers.cpp +++ b/examples/test-timers.cpp @@ -1,288 +1,528 @@ -// Program to test the timer.h implementation's essential functionality. - -#include +// +// This is a mostly Wirish-free timer test. Wirish usage is minimized +// because this is a test of the C timer interface in +// , so it's good if it can be made to work even +// when most or all of Wirish is missing. Because of that, you may +// need to customize the following output configuration: +// +// Output is printed: +// - on COMM_USART, +// - via TX pin on port COMM_USART_PORT, bit COMM_USART_TX_BIT +// - via RX pin on port COMM_USART_PORT, bit COMM_USART_RX_BIT +// - at COMM_USART_BAUD baud. +#define COMM_USART USART6 +#define COMM_USART_BAUD 115200 +#define COMM_USART_PORT GPIOG +#define COMM_USART_TX_BIT 14 +#define COMM_USART_RX_BIT 9 +// Other optional configuration below. + +#include +#include +#include +#include #include - -void handler1(void); -void handler2(void); -void handler3(void); -void handler4(void); - -void handler3b(void); -void handler4b(void); - -int t; - -int count1 = 0; -int count2 = 0; -int count3 = 0; -int count4 = 0; -uint16 rate1 = 1000; -uint16 rate2 = 2000; -uint16 rate3 = 4000; -uint16 rate4 = 8000; -uint16 val1 = 10000; -uint16 val2 = 10000; -uint16 val3 = 10000; -uint16 val4 = 10000; - -// FIXME [0.1.0] high density timer test (especially basic timers + DAC) -timer_dev *timers[] = {TIMER1, TIMER2, TIMER3, TIMER4}; -voidFuncPtr handlers[] = {handler1, handler2, handler3, handler4}; - -void initTimer(timer_dev *dev); -void setTimerPeriod(timer_dev *dev, uint32 period_us); -void testSetTimerPeriod(uint32 period); -void testTimerChannels(timer_dev *dev); -int timerNumber(timer_dev *dev); +#include + +// +// Configuration +// + +// More output if true +static bool verbose = true; + +// Timers to test +// FIXME use feature test macros for smaller MCUs +static timer_dev *timers[] = { + // Available on all currently supported MCUs + TIMER1, TIMER2, TIMER3, TIMER4, + // Available on F1 (HD and up), F2 + TIMER5, TIMER6, TIMER7, TIMER8, + // Available on F1 (XL), F2 + TIMER9, TIMER10, TIMER11, TIMER12, TIMER13, TIMER14, +}; + +// +// Test routines +// + +typedef void (*timer_test_t)(timer_dev *); + +static void runTest(const char description[], timer_test_t test); +static void runTests(void); + +static void testGetAndSetCount(timer_dev*); +static void testPauseAndResume(timer_dev*); +static void testTimerChannels(timer_dev*); + +// +// Helpers +// + +static void initTimer(timer_dev *dev); +static int timerNumber(timer_dev *dev); +// Hack: a systick-based delay, useful until delay_us() is fixed +static void _delay(uint32 msec); +// Wirish-less USART initialization routine +static void init_usart(usart_dev *dev, gpio_dev *gdev, uint8 tx, uint8 rx); +// Return whether or not the timer has capture/compare channel `ch'. +// TODO: does something like this belong in the standard timer library? +static bool timer_has_cc_ch(timer_dev *dev, int ch); + +// Printing routines and variants for verbose mode +static void putstr(const char str[]); +static void println(void); +static void putstrln(const char str[]); +static void putudec(uint32 val); +static void puttimn(timer_dev *dev); +static void v_putstr(const char str[]); +static void v_println(); +static void v_putstrln(const char str[]); +static void v_putudec(uint32 val); +static void v_puttimn(timer_dev *dev); +// Used to visually separate output from different tests +static void printBanner(void); + +// +// Handler state +// + +static int count1 = 0; +static int count2 = 0; +static int count3 = 0; +static int count4 = 0; +static int timer_num; // Current timer we're considering + +// +// Timer capture/compare interrupt handlers +// +// These are shared between timers. The global variable timer_num +// controls which timer they affect. +// + +static void handler1(void); +static void handler2(void); +static void handler3(void); +static void handler4(void); +static voidFuncPtr handlers[] = {handler1, handler2, handler3, handler4}; + +// +// setup() and loop() +// void setup() { - // Set up the LED to blink - pinMode(BOARD_LED_PIN, OUTPUT); - - // Setup the button as input - pinMode(BOARD_BUTTON_PIN, INPUT); - - // Send a message out Serial2 - Serial2.begin(115200); - Serial2.println("*** Initializing timers..."); + init_usart(COMM_USART, COMM_USART_PORT, + COMM_USART_TX_BIT, COMM_USART_RX_BIT); + _delay(5); + println(); + printBanner(); + putstr("Initializing timers...\r\n"); timer_foreach(initTimer); - Serial2.println("*** Done. Beginning timer test."); + putstr("Done. Running tests.\r\n"); + runTests(); + printBanner(); + putstr("Done testing timers.\r\n"); } void loop() { - Serial2.println("-----------------------------------------------------"); - - Serial2.println("Testing timer_get_count()/timer_set_count()"); - Serial2.print("TIMER1 count = "); - Serial2.println(timer_get_count(TIMER1)); - Serial2.println("timer_set_count(TIMER1, 1234)"); - timer_set_count(TIMER1, 1234); - Serial2.print("timer_get_count(TIMER1) = "); - Serial2.println(timer_get_count(TIMER1)); - - Serial2.println("-----------------------------------------------------"); - Serial2.println("Testing pause/resume; button roughly controls TIMER4"); - // when BUT is held down, TIMER4 is in the "pause" state and the - // timer doesn't increment, so the final counts should reflect the - // ratio of time that BUT was held down. - count3 = 0; - count4 = 0; - timer_set_mode(TIMER3, TIMER_CH1, TIMER_OUTPUT_COMPARE); - timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE); - timer_pause(TIMER3); - timer_pause(TIMER4); - timer_set_count(TIMER3, 0); - timer_set_count(TIMER4, 0); - timer_set_reload(TIMER3, 30000); - timer_set_reload(TIMER4, 30000); - timer_set_compare(TIMER3, 1, 1000); - timer_set_compare(TIMER4, 1, 1000); - timer_attach_interrupt(TIMER3, TIMER_CC1_INTERRUPT, handler3b); - timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b); - timer_resume(TIMER3); - timer_resume(TIMER4); - - Serial2.println("Testing for ~4 seconds..."); - for(int i = 0; i < 4000; i++) { - if (isButtonPressed()) { - timer_pause(TIMER4); - } else { - timer_resume(TIMER4); - } - delay(1); - } +} + +// +// Test routine implementations +// - timer_set_mode(TIMER3, TIMER_CH1, TIMER_DISABLED); - timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED); - - Serial2.print("TIMER3 count: "); - Serial2.println(timer_get_count(TIMER3)); - Serial2.print("TIMER4 count: "); - Serial2.println(timer_get_count(TIMER4)); - - Serial2.println("-----------------------------------------------------"); - Serial2.println("Testing setTimerPeriod()"); - testSetTimerPeriod(10); - testSetTimerPeriod(30000); - testSetTimerPeriod(300000); - testSetTimerPeriod(30000); - - Serial2.println("Sanity check (with hand-coded reload and prescaler for " - "72 MHz timers):"); - timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE); - timer_set_prescaler(TIMER4, 33); - timer_set_reload(TIMER4, 65454); - timer_pause(TIMER4); - timer_set_count(TIMER4, 0); - timer_set_compare(TIMER4, TIMER_CH1, 1); - timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b); - Serial2.println("Period 30000ms, wait 2 seconds..."); - count4 = 0; - timer_resume(TIMER4); - delay(2000); - timer_pause(TIMER4); - timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED); - Serial2.print("TIMER4 count: "); - Serial2.println(count4); - Serial2.println(" (Should be around 2sec/30000ms ~ 67)"); - - // Test all the individual timer channels - timer_foreach(testTimerChannels); +static void runTests(void) { + runTest("timer_get_count()/timer_set_count()", testGetAndSetCount); + runTest("timer_pause()/timer_resume()", testPauseAndResume); + runTest("capture/compare channels and interrupts", + testTimerChannels); } -void initTimer(timer_dev *dev) { - switch (dev->type) { - case TIMER_ADVANCED: - case TIMER_GENERAL: - Serial2.print("Initializing timer "); - Serial2.println(timerNumber(dev)); - for (int c = 1; c <= 4; c++) { - timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE); - } - Serial2.println("Done."); - break; - case TIMER_BASIC: - break; +static void runTest(const char description[], timer_test_t test) { + printBanner(); + putstr("Testing "); + putstr(description); + putstrln("."); + timer_foreach(test); +} + +static void testGetAndSetCount(timer_dev *dev) { + unsigned before, after; + unsigned val_to_set = 1234; + + timer_pause(dev); + before = timer_get_count(dev); + timer_set_count(dev, val_to_set); + after = timer_get_count(dev); + timer_resume(dev); + + if (after != val_to_set) { + puttimn(dev); + putstr(": "); + putstr("*** FAIL: get/set count for "); + puttimn(dev); + putstr("."); + putstr("Start count = "); + putudec(before); + putstr(". Count set to "); + putudec(val_to_set); + putstr(", and now count is = "); + putudec(after); + println(); + } else if (verbose) { + puttimn(dev); + putstr(": "); + putstrln("[ok]"); } } -void testSetTimerPeriod(uint32 period) { - timer_set_mode(TIMER4, TIMER_CH1, TIMER_OUTPUT_COMPARE); - timer_set_compare(TIMER4, TIMER_CH1, 1); - setTimerPeriod(TIMER4, period); - timer_pause(TIMER4); - timer_set_count(TIMER4, 0); - timer_attach_interrupt(TIMER4, TIMER_CC1_INTERRUPT, handler4b); - Serial2.println("Period "); - Serial2.print(period); - Serial2.print(" ms. Waiting 2 seconds..."); - count4 = 0; - timer_resume(TIMER4); - delay(2000); - timer_pause(TIMER4); - timer_set_mode(TIMER4, TIMER_CH1, TIMER_DISABLED); - Serial2.print("TIMER4 count: "); - Serial2.println(timer_get_count(TIMER4)); - Serial2.print(" (Should be around 2 sec / "); - Serial2.print(period); - Serial2.print(" ms = "); - Serial2.print(double(2) / period * 1000); - Serial2.println(", modulo delays due to interrupts)"); +// This hack works on all currently supported STM32 series, but you +// may need to do something smarter in the future. The assertions +// ensure that our assumptions hold for your target. +static timer_dev *getDifferentTimerOnSameBusAs(timer_dev *dev) { + rcc_clk_domain dev_domain = rcc_dev_clk(dev->clk_id); + ASSERT(RCC_APB1 == dev_domain || RCC_APB2 == dev_domain); + ASSERT(rcc_dev_clk(TIMER1->clk_id) == RCC_APB2); + ASSERT(rcc_dev_clk(TIMER2->clk_id) == RCC_APB1); + ASSERT(rcc_dev_clk(TIMER8->clk_id) == RCC_APB2); + ASSERT(rcc_dev_clk(TIMER3->clk_id) == RCC_APB1); + + if (dev->clk_id == RCC_TIMER1) { + return TIMER8; + } + if (dev->clk_id == RCC_TIMER2) { + return TIMER3; + } + return dev_domain == RCC_APB2 ? TIMER1 : TIMER2; } -int timerNumber(timer_dev *dev) { - switch (dev->clk_id) { - case RCC_TIMER1: - return 1; - case RCC_TIMER2: - return 2; - case RCC_TIMER3: - return 3; - case RCC_TIMER4: - return 4; -#ifdef STM32_HIGH_DENSITY - case RCC_TIMER5: - return 5; - case RCC_TIMER6: - return 6; - case RCC_TIMER7: - return 7; - case RCC_TIMER8: - return 8; -#endif - default: - ASSERT(0); - return 0; +// Rough test of pause and resume. +// +// Approximately half the time, dev is in the "pause" state and the +// timer doesn't increment, while another timer (`base_dev') on the +// same bus continues. dev and base_dev have identical start counts +// and prescalers. +// +// Since dev and base_dev share a bus (and thus a base clock), and we +// configure them to have the same prescaler and start count, the +// ratio of their end counts should be approximately 1 : 2. We check +// to make sure this is true, up to tolerance `epsilon'. +static void testPauseAndResume(timer_dev *dev) { + timer_dev *base_dev = getDifferentTimerOnSameBusAs(dev); + unsigned start_count = 0, reload = 65535; + // This prescaler should be enough to ensure that we don't + // overflow, while still giving us a reasonably large number of + // timer ticks. + uint16 prescaler = CYCLES_PER_MICROSECOND * 50; + double epsilon = .02; + + if (rcc_dev_clk(base_dev->clk_id) != rcc_dev_clk(dev->clk_id)) { + putstrln("*** ERROR: cannot run test. Bus info is messed up."); + return; + } + + // Pause and set up timers + timer_pause(base_dev); + timer_pause(dev); + timer_set_count(base_dev, start_count); + timer_set_count(dev, start_count); + timer_set_reload(base_dev, reload); + timer_set_reload(dev, reload); + timer_set_prescaler(base_dev, prescaler); + timer_set_prescaler(dev, prescaler); + timer_generate_update(base_dev); + timer_generate_update(dev); + + // Resume the timers and run the test + ASSERT(timer_get_count(base_dev) == start_count); + ASSERT(timer_get_count(dev) == start_count); + timer_resume(base_dev); + timer_resume(dev); + _delay(1000); + timer_pause(dev); + _delay(1000); + timer_pause(base_dev); + + // Check the results + unsigned dev_count = timer_get_count(dev); + unsigned base_count = timer_get_count(base_dev); + double count_ratio = ((double)dev_count / base_count); + bool fail = false; + if (count_ratio > 0.5 + epsilon || count_ratio < 0.5 - epsilon) { + fail = true; + } + if (fail || verbose) { + puttimn(dev); + putstr(" vs. "); + puttimn(base_dev); + putstr(": "); + if (fail) putstr("*** FAIL: "); + else putstr("[ok] "); + putstr("(dev = "); + putudec(dev_count); + putstr(") / (base = "); + putudec(base_count); + putstr(") = "); + // hack hack hack + putudec((int)count_ratio); + count_ratio -= (int)count_ratio; + putstr("."); + int cr_x_100 = (int)(count_ratio * 100); + int hundredths = cr_x_100 % 10; + cr_x_100 /= 10; + int tenths = cr_x_100 % 10; + putudec(tenths); + putudec(hundredths); + println(); } } -/* This function touches every channel of a given timer. The output - * ratios should reflect the ratios of the rate variables. It - * demonstrates that, over time, the actual timing rates get blown - * away by other system interrupts. */ -void testTimerChannels(timer_dev *dev) { - t = timerNumber(dev); - toggleLED(); - delay(100); - Serial2.println("-----------------------------------------------------"); +// This function touches every capture/compare channel of a given +// timer. The channel counts should be equal within a timer +// regardless of other interrupts on the system (note that this +// doesn't really test timers with only a single capture/compare +// channel; for that, you'll want to do visual inspection of timers +// that share a bus, in verbose mode). +static void testTimerChannels(timer_dev *dev) { switch (dev->type) { case TIMER_BASIC: - Serial2.print("NOT testing channels for basic timer "); - Serial2.println(t); - break; + v_putstr("Skipping basic timer "); + v_puttimn(dev); + v_println(); + return; case TIMER_ADVANCED: case TIMER_GENERAL: - Serial2.print("Testing channels for timer "); - Serial2.println(t); + // Set up + v_puttimn(dev); + v_println(); + v_putstr("\tchannels: "); + + timer_num = timerNumber(dev); timer_pause(dev); - count1 = count2 = count3 = count4 = 0; + count1 = 0; + count2 = 0; + count3 = 0; + count4 = 0; timer_set_reload(dev, 0xFFFF); timer_set_prescaler(dev, 1); for (int c = 1; c <= 4; c++) { - timer_set_compare(dev, c, 65535); - timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE); - timer_attach_interrupt(dev, c, handlers[c - 1]); + if (timer_has_cc_ch(dev, c)) { + v_putudec(c); + v_putstr("\t"); + timer_set_compare(dev, c, 0xFFFF); + timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE); + timer_attach_interrupt(dev, c, handlers[c - 1]); + } } + v_println(); + + // Run test + timer_generate_update(dev); timer_resume(dev); - delay(3000); + _delay(250); + timer_pause(dev); + + // Print results + v_putstr("\tcounts: "); + bool fail = false; + bool mismatched[4] = {false, false, false, false}; + int counts[4]; + counts[0] = count1; + counts[1] = count2; + counts[2] = count3; + counts[3] = count4; + bool first = true; + int first_count = -1; for (int c = 1; c <= 4; c++) { - timer_set_mode(dev, c, TIMER_DISABLED); + if (timer_has_cc_ch(dev, c)) { + if (first) { + first_count = counts[c - 1]; + first = false; + } + if (!first && (counts[c - 1] != first_count)) { + mismatched[c - 1] = true; + fail = true; + } + v_putudec(counts[c - 1]); + v_putstr("\t"); + } + } + v_println(); + if (fail) { + for (int i = 0; i < 4; i++) { + if (mismatched[i]) { + putstr("*** FAIL: mismatch on "); + puttimn(dev); + putstr(", channel "); + putudec(i + 1); + putstr(": expected "); + putudec(first_count); + putstr(", got "); + putudec(counts[i]); + println(); + } + } + } else { + puttimn(dev); + putstrln(" [ok]"); + } + v_println(); + + // Clean up + for (int c = 1; c <= 4; c++) { + if (timer_has_cc_ch(dev, c)) { + timer_set_mode(dev, c, TIMER_DISABLED); + } } - Serial2.print("Channel 1 count: "); Serial2.println(count1); - Serial2.print("Channel 2 count: "); Serial2.println(count2); - Serial2.print("Channel 3 count: "); Serial2.println(count3); - Serial2.print("Channel 4 count: "); Serial2.println(count4); break; } } -// FIXME [0.1.0] move some incarnation of this into timer.h -void setTimerPeriod(timer_dev *dev, uint32 period_us) { - if (!period_us) { - // FIXME handle this case - ASSERT(0); - return; - } +// +// Helper implementations +// - uint32 cycles = period_us * CYCLES_PER_MICROSECOND; - uint16 pre = (uint16)((cycles >> 16) + 1); - timer_set_prescaler(dev, pre); - timer_set_reload(dev, cycles / pre - 1); +static void _delay(uint32 msec) { + uint32 end = systick_uptime() + msec; + while (systick_uptime() < end) + ; } -void handler1(void) { - val1 += rate1; - timer_set_compare(timers[t], TIMER_CH1, val1); - count1++; +static void init_usart(usart_dev *dev, gpio_dev *gdev, uint8 tx, uint8 rx) { + usart_async_gpio_cfg(dev, gdev, rx, gdev, tx, 0); + usart_init(dev); + usart_set_baud_rate(dev, USART_USE_PCLK, COMM_USART_BAUD); + usart_enable(dev); } -void handler2(void) { - val2 += rate2; - timer_set_compare(timers[t], TIMER_CH2, val2); - count2++; +static bool timer_has_cc_ch(timer_dev *dev, int ch) { + ASSERT(1 <= ch && ch <= 4); + if (dev->type == TIMER_BASIC) + return false; + int tn = timerNumber(dev); + return (// TIM1-5 and 8 have all four channels + (tn <= 5 || tn == 8) || + // TIM9 and 12 only have channels 1 and 2 + ((tn == 9 || tn == 12) && ch <= 2) || + // All other general purpose timers only have channel 1 + (ch == 1)); } -void handler3(void) { - val3 += rate3; - timer_set_compare(timers[t], TIMER_CH3, val3); - count3++; +static void putstr(const char str[]) { + usart_putstr(COMM_USART, str); } -void handler4(void) { - val4 += rate4; - timer_set_compare(timers[t], TIMER_CH4, val4); - count4++; +static void println(void) { + putstr("\r\n"); +} + +static void putstrln(const char str[]) { + putstr(str); + println(); +} + +static void putudec(uint32 val) { + usart_putudec(COMM_USART, val); +} + +static void puttimn(timer_dev *dev) { + putstr("TIM"); + putudec(timerNumber(dev)); +} + +static void v_putstr(const char str[]) { + if (verbose) putstr(str); } -void handler3b(void) { +static void v_println() { + if (verbose) println(); +} + +__attribute__((unused)) /* (shut up, gcc) */ +static void v_putstrln(const char str[]) { + if (verbose) putstrln(str); +} + +static void v_putudec(uint32 val) { + if (verbose) putudec(val); +} + +static void v_puttimn(timer_dev *dev) { + if (verbose) puttimn(dev); +} + +// Used to visually separate output from different tests +static void printBanner(void) { + putstrln("-----------------------------------------------------"); +} + +static void initTimer(timer_dev *dev) { + v_puttimn(dev); + timer_init(dev); + switch (dev->type) { + case TIMER_ADVANCED: + case TIMER_GENERAL: + v_putstr(" channels "); + for (int c = 1; c <= 4; c++) { + if (timer_has_cc_ch(dev, c)) { + v_putudec(c); + v_putstr(" "); + timer_set_mode(dev, c, TIMER_OUTPUT_COMPARE); + } + } + break; + case TIMER_BASIC: + break; + } + v_println(); +} + +static int timerNumber(timer_dev *dev) { + switch (dev->clk_id) { + case RCC_TIMER1: return 1; + case RCC_TIMER2: return 2; + case RCC_TIMER3: return 3; + case RCC_TIMER4: return 4; + case RCC_TIMER5: return 5; + case RCC_TIMER6: return 6; + case RCC_TIMER7: return 7; + case RCC_TIMER8: return 8; + case RCC_TIMER9: return 9; + case RCC_TIMER10: return 10; + case RCC_TIMER11: return 11; + case RCC_TIMER12: return 12; + case RCC_TIMER13: return 13; + case RCC_TIMER14: return 14; + default: + ASSERT(0); + return 0; + } +} + +// +// IRQ Handlers +// + +static void handler1(void) { + count1++; +} + +static void handler2(void) { + count2++; +} + +static void handler3(void) { count3++; } -void handler4b(void) { +static void handler4(void) { count4++; } +// +// init() and main() +// + __attribute__((constructor)) void premain() { init(); } -- cgit v1.2.3 From c114022b2599fc7024c771d13b24a2119bee2208 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 15:35:50 -0400 Subject: libmaple/spi: Fix boilerplate. Update Doxygen file headers and license copyright dates. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/spi.h | 3 ++- libmaple/spi.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h index 6f509c2..7a665db 100644 --- a/libmaple/include/libmaple/spi.h +++ b/libmaple/include/libmaple/spi.h @@ -1,6 +1,7 @@ /****************************************************************************** * The MIT License * + * Copyright (c) 2011, 2012 LeafLabs, LLC. * Copyright (c) 2010 Perry Hung. * * Permission is hereby granted, free of charge, to any person @@ -25,7 +26,7 @@ *****************************************************************************/ /** - * @file spi.h + * @file libmaple/spi.h * @author Marti Bolivar * @brief Serial Peripheral Interface (SPI) and Integrated * Interchip Sound (I2S) peripheral support. diff --git a/libmaple/spi.c b/libmaple/spi.c index d0aaaf0..00b7ce2 100644 --- a/libmaple/spi.c +++ b/libmaple/spi.c @@ -1,6 +1,7 @@ /****************************************************************************** * The MIT License * + * Copyright (c) 2011, 2012 LeafLabs, LLC. * Copyright (c) 2010 Perry Hung. * * Permission is hereby granted, free of charge, to any person @@ -25,7 +26,7 @@ *****************************************************************************/ /** - * @file spi.c + * @file libmaple/spi.c * @author Marti Bolivar * @brief Serial Peripheral Interface (SPI) support. * Currently, there is no Integrated Interchip Sound (I2S) support. -- cgit v1.2.3 From 301fe2c02ef0ca779d11dcedc2a081436360fbe3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 16:05:42 -0400 Subject: libmaple/spi: Fixups, move nonportable bits into libmaple/stm32f1. Standard family support refactoring: add STM32F1 series spi.h, spi.c, and move anything that won't port to STM32F2 there. As part of a general effort to be cleaner, remove the dependency on libmaple/util.h from libmaple/spi.h by not using BIT(). Also forward declare struct gpio_dev for spi_gpio_cfg() to remove that include. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/spi.h | 118 ++++++++++++++++++---------------- libmaple/rules.mk | 2 +- libmaple/spi.c | 77 ---------------------- libmaple/stm32f1/include/series/spi.h | 70 ++++++++++++++++++++ libmaple/stm32f1/rules.mk | 1 + libmaple/stm32f1/spi.c | 97 ++++++++++++++++++++++++++++ 6 files changed, 231 insertions(+), 134 deletions(-) create mode 100644 libmaple/stm32f1/include/series/spi.h create mode 100644 libmaple/stm32f1/spi.c diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h index 7a665db..5b045a9 100644 --- a/libmaple/include/libmaple/spi.h +++ b/libmaple/include/libmaple/spi.h @@ -44,8 +44,7 @@ extern "C" { #include #include #include -#include -#include +#include /* * Register maps @@ -64,13 +63,6 @@ typedef struct spi_reg_map { __io uint32 I2SPR; /**< I2S prescaler register */ } spi_reg_map; -/** SPI1 register map base pointer */ -#define SPI1_BASE ((struct spi_reg_map*)0x40013000) -/** SPI2 register map base pointer */ -#define SPI2_BASE ((struct spi_reg_map*)0x40003800) -/** SPI3 register map base pointer */ -#define SPI3_BASE ((struct spi_reg_map*)0x40003C00) - /* * Register bit definitions */ @@ -91,20 +83,20 @@ typedef struct spi_reg_map { #define SPI_CR1_CPOL_BIT 1 #define SPI_CR1_CPHA_BIT 0 -#define SPI_CR1_BIDIMODE BIT(SPI_CR1_BIDIMODE_BIT) +#define SPI_CR1_BIDIMODE (1U << SPI_CR1_BIDIMODE_BIT) #define SPI_CR1_BIDIMODE_2_LINE (0x0 << SPI_CR1_BIDIMODE_BIT) #define SPI_CR1_BIDIMODE_1_LINE (0x1 << SPI_CR1_BIDIMODE_BIT) -#define SPI_CR1_BIDIOE BIT(SPI_CR1_BIDIOE_BIT) -#define SPI_CR1_CRCEN BIT(SPI_CR1_CRCEN_BIT) -#define SPI_CR1_CRCNEXT BIT(SPI_CR1_CRCNEXT_BIT) -#define SPI_CR1_DFF BIT(SPI_CR1_DFF_BIT) +#define SPI_CR1_BIDIOE (1U << SPI_CR1_BIDIOE_BIT) +#define SPI_CR1_CRCEN (1U << SPI_CR1_CRCEN_BIT) +#define SPI_CR1_CRCNEXT (1U << SPI_CR1_CRCNEXT_BIT) +#define SPI_CR1_DFF (1U << SPI_CR1_DFF_BIT) #define SPI_CR1_DFF_8_BIT (0x0 << SPI_CR1_DFF_BIT) #define SPI_CR1_DFF_16_BIT (0x1 << SPI_CR1_DFF_BIT) -#define SPI_CR1_RXONLY BIT(SPI_CR1_RXONLY_BIT) -#define SPI_CR1_SSM BIT(SPI_CR1_SSM_BIT) -#define SPI_CR1_SSI BIT(SPI_CR1_SSI_BIT) -#define SPI_CR1_LSBFIRST BIT(SPI_CR1_LSBFIRST_BIT) -#define SPI_CR1_SPE BIT(SPI_CR1_SPE_BIT) +#define SPI_CR1_RXONLY (1U << SPI_CR1_RXONLY_BIT) +#define SPI_CR1_SSM (1U << SPI_CR1_SSM_BIT) +#define SPI_CR1_SSI (1U << SPI_CR1_SSI_BIT) +#define SPI_CR1_LSBFIRST (1U << SPI_CR1_LSBFIRST_BIT) +#define SPI_CR1_SPE (1U << SPI_CR1_SPE_BIT) #define SPI_CR1_BR (0x7 << 3) #define SPI_CR1_BR_PCLK_DIV_2 (0x0 << 3) #define SPI_CR1_BR_PCLK_DIV_4 (0x1 << 3) @@ -114,17 +106,14 @@ typedef struct spi_reg_map { #define SPI_CR1_BR_PCLK_DIV_64 (0x5 << 3) #define SPI_CR1_BR_PCLK_DIV_128 (0x6 << 3) #define SPI_CR1_BR_PCLK_DIV_256 (0x7 << 3) -#define SPI_CR1_MSTR BIT(SPI_CR1_MSTR_BIT) -#define SPI_CR1_CPOL BIT(SPI_CR1_CPOL_BIT) +#define SPI_CR1_MSTR (1U << SPI_CR1_MSTR_BIT) +#define SPI_CR1_CPOL (1U << SPI_CR1_CPOL_BIT) #define SPI_CR1_CPOL_LOW (0x0 << SPI_CR1_CPOL_BIT) #define SPI_CR1_CPOL_HIGH (0x1 << SPI_CR1_CPOL_BIT) -#define SPI_CR1_CPHA BIT(SPI_CR1_CPHA_BIT) +#define SPI_CR1_CPHA (1U << SPI_CR1_CPHA_BIT) /* Control register 2 */ -/* RM0008-ism: SPI CR2 has "TXDMAEN" and "RXDMAEN" bits, while the - * USARTs have CR3 "DMAR" and "DMAT" bits. */ - #define SPI_CR2_TXEIE_BIT 7 #define SPI_CR2_RXNEIE_BIT 6 #define SPI_CR2_ERRIE_BIT 5 @@ -132,12 +121,12 @@ typedef struct spi_reg_map { #define SPI_CR2_TXDMAEN_BIT 1 #define SPI_CR2_RXDMAEN_BIT 0 -#define SPI_CR2_TXEIE BIT(SPI_CR2_TXEIE_BIT) -#define SPI_CR2_RXNEIE BIT(SPI_CR2_RXNEIE_BIT) -#define SPI_CR2_ERRIE BIT(SPI_CR2_ERRIE_BIT) -#define SPI_CR2_SSOE BIT(SPI_CR2_SSOE_BIT) -#define SPI_CR2_TXDMAEN BIT(SPI_CR2_TXDMAEN_BIT) -#define SPI_CR2_RXDMAEN BIT(SPI_CR2_RXDMAEN_BIT) +#define SPI_CR2_TXEIE (1U << SPI_CR2_TXEIE_BIT) +#define SPI_CR2_RXNEIE (1U << SPI_CR2_RXNEIE_BIT) +#define SPI_CR2_ERRIE (1U << SPI_CR2_ERRIE_BIT) +#define SPI_CR2_SSOE (1U << SPI_CR2_SSOE_BIT) +#define SPI_CR2_TXDMAEN (1U << SPI_CR2_TXDMAEN_BIT) +#define SPI_CR2_RXDMAEN (1U << SPI_CR2_RXDMAEN_BIT) /* Status register */ @@ -150,37 +139,35 @@ typedef struct spi_reg_map { #define SPI_SR_TXE_BIT 1 #define SPI_SR_RXNE_BIT 0 -#define SPI_SR_BSY BIT(SPI_SR_BSY_BIT) -#define SPI_SR_OVR BIT(SPI_SR_OVR_BIT) -#define SPI_SR_MODF BIT(SPI_SR_MODF_BIT) -#define SPI_SR_CRCERR BIT(SPI_SR_CRCERR_BIT) -#define SPI_SR_UDR BIT(SPI_SR_UDR_BIT) -#define SPI_SR_CHSIDE BIT(SPI_SR_CHSIDE_BIT) +#define SPI_SR_BSY (1U << SPI_SR_BSY_BIT) +#define SPI_SR_OVR (1U << SPI_SR_OVR_BIT) +#define SPI_SR_MODF (1U << SPI_SR_MODF_BIT) +#define SPI_SR_CRCERR (1U << SPI_SR_CRCERR_BIT) +#define SPI_SR_UDR (1U << SPI_SR_UDR_BIT) +#define SPI_SR_CHSIDE (1U << SPI_SR_CHSIDE_BIT) #define SPI_SR_CHSIDE_LEFT (0x0 << SPI_SR_CHSIDE_BIT) #define SPI_SR_CHSIDE_RIGHT (0x1 << SPI_SR_CHSIDE_BIT) -#define SPI_SR_TXE BIT(SPI_SR_TXE_BIT) -#define SPI_SR_RXNE BIT(SPI_SR_RXNE_BIT) +#define SPI_SR_TXE (1U << SPI_SR_TXE_BIT) +#define SPI_SR_RXNE (1U << SPI_SR_RXNE_BIT) /* I2S configuration register */ -/* RM0008-ism: CR1 has "CPOL", I2SCFGR has "CKPOL". */ - #define SPI_I2SCFGR_I2SMOD_BIT 11 #define SPI_I2SCFGR_I2SE_BIT 10 #define SPI_I2SCFGR_PCMSYNC_BIT 7 #define SPI_I2SCFGR_CKPOL_BIT 3 #define SPI_I2SCFGR_CHLEN_BIT 0 -#define SPI_I2SCFGR_I2SMOD BIT(SPI_I2SCFGR_I2SMOD_BIT) +#define SPI_I2SCFGR_I2SMOD (1U << SPI_I2SCFGR_I2SMOD_BIT) #define SPI_I2SCFGR_I2SMOD_SPI (0x0 << SPI_I2SCFGR_I2SMOD_BIT) #define SPI_I2SCFGR_I2SMOD_I2S (0x1 << SPI_I2SCFGR_I2SMOD_BIT) -#define SPI_I2SCFGR_I2SE BIT(SPI_I2SCFGR_I2SE_BIT) +#define SPI_I2SCFGR_I2SE (1U << SPI_I2SCFGR_I2SE_BIT) #define SPI_I2SCFGR_I2SCFG (0x3 << 8) #define SPI_I2SCFGR_I2SCFG_SLAVE_TX (0x0 << 8) #define SPI_I2SCFGR_I2SCFG_SLAVE_RX (0x1 << 8) #define SPI_I2SCFGR_I2SCFG_MASTER_TX (0x2 << 8) #define SPI_I2SCFGR_I2SCFG_MASTER_RX (0x3 << 8) -#define SPI_I2SCFGR_PCMSYNC BIT(SPI_I2SCFGR_PCMSYNC_BIT) +#define SPI_I2SCFGR_PCMSYNC (1U << SPI_I2SCFGR_PCMSYNC_BIT) #define SPI_I2SCFGR_PCMSYNC_SHORT (0x0 << SPI_I2SCFGR_PCMSYNC_BIT) #define SPI_I2SCFGR_PCMSYNC_LONG (0x1 << SPI_I2SCFGR_PCMSYNC_BIT) #define SPI_I2SCFGR_I2SSTD (0x3 << 4) @@ -188,17 +175,26 @@ typedef struct spi_reg_map { #define SPI_I2SCFGR_I2SSTD_MSB (0x1 << 4) #define SPI_I2SCFGR_I2SSTD_LSB (0x2 << 4) #define SPI_I2SCFGR_I2SSTD_PCM (0x3 << 4) -#define SPI_I2SCFGR_CKPOL BIT(SPI_I2SCFGR_CKPOL_BIT) +#define SPI_I2SCFGR_CKPOL (1U << SPI_I2SCFGR_CKPOL_BIT) #define SPI_I2SCFGR_CKPOL_LOW (0x0 << SPI_I2SCFGR_CKPOL_BIT) #define SPI_I2SCFGR_CKPOL_HIGH (0x1 << SPI_I2SCFGR_CKPOL_BIT) #define SPI_I2SCFGR_DATLEN (0x3 << 1) #define SPI_I2SCFGR_DATLEN_16_BIT (0x0 << 1) #define SPI_I2SCFGR_DATLEN_24_BIT (0x1 << 1) #define SPI_I2SCFGR_DATLEN_32_BIT (0x2 << 1) -#define SPI_I2SCFGR_CHLEN BIT(SPI_I2SCFGR_CHLEN_BIT) +#define SPI_I2SCFGR_CHLEN (1U << SPI_I2SCFGR_CHLEN_BIT) #define SPI_I2SCFGR_CHLEN_16_BIT (0x0 << SPI_I2SCFGR_CHLEN_BIT) #define SPI_I2SCFGR_CHLEN_32_BIT (0x1 << SPI_I2SCFGR_CHLEN_BIT) +/* I2S prescaler register */ + +#define SPI_I2SPR_MCKOE_BIT 9 +#define SPI_I2SPR_ODD_BIT 8 + +#define SPI_I2SPR_MCKOE (1U << SPI_I2SPR_MCKOE_BIT) +#define SPI_I2SPR_ODD (1U << SPI_I2SPR_ODD_BIT) +#define SPI_I2SPR_I2SDIV 0xFF + /* * Devices */ @@ -210,22 +206,28 @@ typedef struct spi_dev { nvic_irq_num irq_num; /**< NVIC interrupt number */ } spi_dev; -extern spi_dev *SPI1; -extern spi_dev *SPI2; -#ifdef STM32_HIGH_DENSITY -extern spi_dev *SPI3; -#endif - /* * SPI Convenience functions */ void spi_init(spi_dev *dev); +struct gpio_dev; +/** + * @brief Configure GPIO bit modes for use as a SPI port's pins. + * @param as_master If true, configure bits for use as a bus master. + * Otherwise, configure bits for use as slave. + * @param nss_dev NSS pin's GPIO device + * @param comm_dev SCK, MISO, MOSI pins' GPIO device + * @param nss_bit NSS pin's GPIO bit on nss_dev + * @param sck_bit SCK pin's GPIO bit on comm_dev + * @param miso_bit MISO pin's GPIO bit on comm_dev + * @param mosi_bit MOSI pin's GPIO bit on comm_dev + */ void spi_gpio_cfg(uint8 as_master, - gpio_dev *nss_dev, + struct gpio_dev *nss_dev, uint8 nss_bit, - gpio_dev *comm_dev, + struct gpio_dev *comm_dev, uint8 sck_bit, uint8 miso_bit, uint8 mosi_bit); @@ -244,7 +246,7 @@ typedef enum spi_mode { clock transition */ SPI_MODE_2, /**< Clock line idles high (1), data capture on first clock transition. */ - SPI_MODE_3 /**< Clock line idles high (1), data capture on + SPI_MODE_3, /**< Clock line idles high (1), data capture on second clock transition. */ } spi_mode; @@ -300,7 +302,11 @@ void spi_slave_enable(spi_dev *dev, uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len); -void spi_foreach(void (*fn)(spi_dev (*dev))); +/** + * @brief Call a function on each SPI port + * @param fn Function to call. + */ +void spi_foreach(void (*fn)(spi_dev*)); void spi_peripheral_enable(spi_dev *dev); void spi_peripheral_disable(spi_dev *dev); diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 2f5e066..93716d2 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -18,6 +18,7 @@ cSRCS_$(d) += iwdg.c cSRCS_$(d) += nvic.c cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c +cSRCS_$(d) += spi.c cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c cSRCS_$(d) += timer.c @@ -29,7 +30,6 @@ cSRCS_$(d) += util.c # cSRCS_$(d) += dma.c # cSRCS_$(d) += exti.c # cSRCS_$(d) += i2c.c -# cSRCS_$(d) += spi.c sSRCS_$(d) := exc.S diff --git a/libmaple/spi.c b/libmaple/spi.c index 00b7ce2..194a82e 100644 --- a/libmaple/spi.c +++ b/libmaple/spi.c @@ -37,36 +37,6 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config); -/* - * SPI devices - */ - -static spi_dev spi1 = { - .regs = SPI1_BASE, - .clk_id = RCC_SPI1, - .irq_num = NVIC_SPI1, -}; -/** SPI device 1 */ -spi_dev *SPI1 = &spi1; - -static spi_dev spi2 = { - .regs = SPI2_BASE, - .clk_id = RCC_SPI2, - .irq_num = NVIC_SPI2, -}; -/** SPI device 2 */ -spi_dev *SPI2 = &spi2; - -#ifdef STM32_HIGH_DENSITY -static spi_dev spi3 = { - .regs = SPI3_BASE, - .clk_id = RCC_SPI3, - .irq_num = NVIC_SPI3, -}; -/** SPI device 3 */ -spi_dev *SPI3 = &spi3; -#endif - /* * SPI convenience routines */ @@ -80,37 +50,6 @@ void spi_init(spi_dev *dev) { rcc_reset_dev(dev->clk_id); } -/** - * @brief Configure GPIO bit modes for use as a SPI port's pins. - * @param as_master If true, configure bits for use as a bus master. - * Otherwise, configure bits for use as slave. - * @param nss_dev NSS pin's GPIO device - * @param comm_dev SCK, MISO, MOSI pins' GPIO device - * @param nss_bit NSS pin's GPIO bit on nss_dev - * @param sck_bit SCK pin's GPIO bit on comm_dev - * @param miso_bit MISO pin's GPIO bit on comm_dev - * @param mosi_bit MOSI pin's GPIO bit on comm_dev - */ -void spi_gpio_cfg(uint8 as_master, - gpio_dev *nss_dev, - uint8 nss_bit, - gpio_dev *comm_dev, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit) { - if (as_master) { - gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING); - gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP); - } else { - gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING); - gpio_set_mode(comm_dev, sck_bit, GPIO_INPUT_FLOATING); - gpio_set_mode(comm_dev, miso_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(comm_dev, mosi_bit, GPIO_INPUT_FLOATING); - } -} - /** * @brief Configure and enable a SPI device as bus master. * @@ -165,18 +104,6 @@ uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) { return txed; } -/** - * @brief Call a function on each SPI port - * @param fn Function to call. - */ -void spi_foreach(void (*fn)(spi_dev*)) { - fn(SPI1); - fn(SPI2); -#ifdef STM32_HIGH_DENSITY - fn(SPI3); -#endif -} - /** * @brief Enable a SPI peripheral * @param dev Device to enable @@ -235,7 +162,3 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) { dev->regs->CR1 = cr1_config; spi_peripheral_enable(dev); } - -/* - * IRQ handlers (TODO) - */ diff --git a/libmaple/stm32f1/include/series/spi.h b/libmaple/stm32f1/include/series/spi.h new file mode 100644 index 0000000..167df0c --- /dev/null +++ b/libmaple/stm32f1/include/series/spi.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011, 2012 LeafLabs, LLC. + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/include/series/spi.h + * @author Marti Bolivar + * @brief STM32F1 SPI/I2S series header. + */ + +#ifndef _LIBMAPLE_STM32F1_SPI_H_ +#define _LIBMAPLE_STM32F1_SPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Register map base pointers + */ + +struct spi_reg_map; + +/** SPI1 register map base pointer */ +#define SPI1_BASE ((struct spi_reg_map*)0x40013000) +/** SPI2 register map base pointer */ +#define SPI2_BASE ((struct spi_reg_map*)0x40003800) +/** SPI3 register map base pointer */ +#define SPI3_BASE ((struct spi_reg_map*)0x40003C00) + +/* + * Device pointers + */ + +struct spi_dev; + +extern struct spi_dev *SPI1; +extern struct spi_dev *SPI2; +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +extern struct spi_dev *SPI3; +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 03fddb3..52ceea6 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -16,6 +16,7 @@ cSRCS_$(d) += bkp.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c +cSRCS_$(d) += spi.c cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c diff --git a/libmaple/stm32f1/spi.c b/libmaple/stm32f1/spi.c new file mode 100644 index 0000000..b860918 --- /dev/null +++ b/libmaple/stm32f1/spi.c @@ -0,0 +1,97 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011, 2012 LeafLabs, LLC. + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/spi.c + * @author Marti Bolivar + * @brief STM32F1 SPI/I2S support. + */ + +#include +#include + +/* + * Devices + */ + +static spi_dev spi1 = { + .regs = SPI1_BASE, + .clk_id = RCC_SPI1, + .irq_num = NVIC_SPI1, +}; +/** SPI device 1 */ +spi_dev *SPI1 = &spi1; + +static spi_dev spi2 = { + .regs = SPI2_BASE, + .clk_id = RCC_SPI2, + .irq_num = NVIC_SPI2, +}; +/** SPI device 2 */ +spi_dev *SPI2 = &spi2; + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +static spi_dev spi3 = { + .regs = SPI3_BASE, + .clk_id = RCC_SPI3, + .irq_num = NVIC_SPI3, +}; +/** SPI device 3 */ +spi_dev *SPI3 = &spi3; +#endif + +/* + * Routines + */ + +void spi_gpio_cfg(uint8 as_master, + gpio_dev *nss_dev, + uint8 nss_bit, + gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit) { + if (as_master) { + gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP); + } else { + gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(comm_dev, sck_bit, GPIO_INPUT_FLOATING); + gpio_set_mode(comm_dev, miso_bit, GPIO_AF_OUTPUT_PP); + gpio_set_mode(comm_dev, mosi_bit, GPIO_INPUT_FLOATING); + } +} + +void spi_foreach(void (*fn)(spi_dev*)) { + fn(SPI1); + fn(SPI2); +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) + fn(SPI3); +#endif +} -- cgit v1.2.3 From f49487116d9ddf7b2da64674d91b14ed34db8289 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 16:13:00 -0400 Subject: libmaple/stm32f1/spi.c: cosmetics. Fix whitespace, move some definitions around. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/spi.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/libmaple/stm32f1/spi.c b/libmaple/stm32f1/spi.c index b860918..45ff354 100644 --- a/libmaple/stm32f1/spi.c +++ b/libmaple/stm32f1/spi.c @@ -39,27 +39,28 @@ */ static spi_dev spi1 = { - .regs = SPI1_BASE, - .clk_id = RCC_SPI1, - .irq_num = NVIC_SPI1, + .regs = SPI1_BASE, + .clk_id = RCC_SPI1, + .irq_num = NVIC_SPI1, }; -/** SPI device 1 */ -spi_dev *SPI1 = &spi1; - static spi_dev spi2 = { - .regs = SPI2_BASE, - .clk_id = RCC_SPI2, - .irq_num = NVIC_SPI2, + .regs = SPI2_BASE, + .clk_id = RCC_SPI2, + .irq_num = NVIC_SPI2, }; -/** SPI device 2 */ -spi_dev *SPI2 = &spi2; - #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) static spi_dev spi3 = { - .regs = SPI3_BASE, - .clk_id = RCC_SPI3, - .irq_num = NVIC_SPI3, + .regs = SPI3_BASE, + .clk_id = RCC_SPI3, + .irq_num = NVIC_SPI3, }; +#endif + +/** SPI device 1 */ +spi_dev *SPI1 = &spi1; +/** SPI device 2 */ +spi_dev *SPI2 = &spi2; +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) /** SPI device 3 */ spi_dev *SPI3 = &spi3; #endif -- cgit v1.2.3 From 913a76148bf28b780f5179e690b77e3177dbddc6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 16:20:13 -0400 Subject: stm32f2/gpio.h: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/stm32f2/include/series/gpio.h b/libmaple/stm32f2/include/series/gpio.h index b6a7599..40c7292 100644 --- a/libmaple/stm32f2/include/series/gpio.h +++ b/libmaple/stm32f2/include/series/gpio.h @@ -163,9 +163,9 @@ extern gpio_dev gpioi; * @brief GPIO pin modes */ typedef enum gpio_pin_mode { - GPIO_MODE_INPUT = GPIO_MODER_INPUT, /**< Input mode */ + GPIO_MODE_INPUT = GPIO_MODER_INPUT, /**< Input mode */ GPIO_MODE_OUTPUT = GPIO_MODER_OUTPUT, /**< Output mode */ - GPIO_MODE_AF = GPIO_MODER_AF, /**< Alternate function mode */ + GPIO_MODE_AF = GPIO_MODER_AF, /**< Alternate function mode */ GPIO_MODE_ANALOG = GPIO_MODER_ANALOG, /**< Analog mode */ } gpio_pin_mode; -- cgit v1.2.3 From 5fa30279b80cd9ae401f61a127a33034b241a2e8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 10 Apr 2012 17:11:55 -0400 Subject: libmaple/i2c.h: Rearrange i2c_dev members to improve packing. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 35c4628..8a1485e 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -82,17 +82,17 @@ typedef struct i2c_msg { */ typedef struct i2c_dev { i2c_reg_map *regs; /**< Register map */ - gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ + i2c_msg *msg; /**< Messages */ + uint32 error_flags; /**< Error flags, set on I2C error condition */ + volatile uint32 timestamp; /**< For internal use */ + struct gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ + uint16 msgs_left; /**< Messages left */ uint8 sda_pin; /**< SDA bit on gpio_port */ uint8 scl_pin; /**< SCL bit on gpio_port */ rcc_clk_id clk_id; /**< RCC clock information */ nvic_irq_num ev_nvic_line; /**< Event IRQ number */ nvic_irq_num er_nvic_line; /**< Error IRQ number */ volatile i2c_state state; /**< Device state */ - uint16 msgs_left; /**< Messages left */ - i2c_msg *msg; /**< Messages */ - volatile uint32 timestamp; /**< For internal use */ - uint32 error_flags; /**< Error flags, set on I2C error condition */ } i2c_dev; /* -- cgit v1.2.3 From c213a1af51dff8655d23c1b66d19533ec35b5265 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 23 Apr 2012 13:30:00 -0400 Subject: stm32f1: stm32.h: Put MCU section first, allow overrides. Put the section defining MCU-specific values before the other sections. Surround the density-specific defines with #ifndef/#endif pairs. This allows any of the settings in the STM32F1 stm32.h to be overridden on a per-MCU basis. That's hopefully useful to e.g. people porting libmaple to STM32F100 MCUs, which have slower clocks. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 77 ++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 30 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 26c45a2..ed51ae5 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -36,6 +36,41 @@ extern "C" { #endif +#define STM32_MCU_SERIES STM32_SERIES_F1 + +/* + * MCU-specific values. + * + * You can use this section to override any of the below settings on a + * per-MCU basis. For example, if your MCU has different STM32_PCLK1 + * or STM32_PCLK2 values, you can set them here and the values for + * STM32F103 microcontrollers set below won't take effect. + */ + +#if defined(MCU_STM32F103RB) +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20005000) + +#elif defined(MCU_STM32F103ZE) +# define STM32_NR_GPIO_PORTS 7 +# define STM32_SRAM_END ((void*)0x20010000) + +#elif defined(MCU_STM32F103CB) + /* This STM32_NR_GPIO_PORTS is not stricly true, but only pins 0 + * and exist, and they're used for OSC (e.g. on e.g. LeafLabs + * Maple Mini), so we'll live with this for now. */ +# define STM32_NR_GPIO_PORTS 3 +# define STM32_SRAM_END ((void*)0x20005000) + +#elif defined(MCU_STM32F103RE) +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20010000) + +#else +#error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ + "-DMCU_STM32F103RB to your compiler arguments." +#endif + /* * Clock configuration. */ @@ -57,46 +92,28 @@ extern "C" { */ #ifdef STM32_MEDIUM_DENSITY +# ifndef STM32_NR_INTERRUPTS # define STM32_NR_INTERRUPTS 43 +# endif + +# ifndef STM32_HAVE_FSMC # define STM32_HAVE_FSMC 0 +# endif + #elif defined(STM32_HIGH_DENSITY) +# ifndef STM32_NR_INTERRUPTS # define STM32_NR_INTERRUPTS 60 +# endif + +# ifndef STM32_HAVE_FSMC # define STM32_HAVE_FSMC 1 +# endif + #else #error "Unsupported STM32F1 density, or no density specified. Add something " \ "like -DSTM32_MEDIUM_DENSITY to your compiler arguments." #endif -/* - * Series- and MCU-specific values. - */ - -#define STM32_MCU_SERIES STM32_SERIES_F1 - -#if defined(MCU_STM32F103RB) -# define STM32_NR_GPIO_PORTS 4 -# define STM32_SRAM_END ((void*)0x20005000) - -#elif defined(MCU_STM32F103ZE) -# define STM32_NR_GPIO_PORTS 7 -# define STM32_SRAM_END ((void*)0x20010000) - -#elif defined(MCU_STM32F103CB) - /* This STM32_NR_GPIO_PORTS is not stricly true, but only pins 0 - * and exist, and they're used for OSC (e.g. on e.g. LeafLabs - * Maple Mini), so we'll live with this for now. */ -# define STM32_NR_GPIO_PORTS 3 -# define STM32_SRAM_END ((void*)0x20005000) - -#elif defined(MCU_STM32F103RE) -# define STM32_NR_GPIO_PORTS 4 -# define STM32_SRAM_END ((void*)0x20010000) - -#else -#error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ - "-DMCU_STM32F103RB to your compiler arguments." -#endif - #ifdef __cplusplus } #endif -- cgit v1.2.3 From f3e5111cff8d9f91dd5279df5165c386d77fed2e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 23 Apr 2012 13:45:15 -0400 Subject: stm32f1 boards_setup.cpp: Allow overriding the PLL multiplier. Allow to override the PLL multiplier by defining BOARD_RCC_PLLMUL. This should be useful for e.g. value line MCUs, which have slower clocks. It's also probably useful for people who have external oscillators different from the 8 MHz ones we use on all of our boards. Signed-off-by: Marti Bolivar --- wirish/stm32f1/boards_setup.cpp | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index 8e16009..74c0e79 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -42,13 +42,22 @@ #include +// Allow boards to provide a PLL multiplier. This is useful for +// e.g. STM32F100 value line MCUs, which use slower multipliers. +// (We're leaving the default to RCC_PLLMUL_9 for now, since that +// works for F103 performance line MCUs, which is all that LeafLabs +// currently officially supports). +#ifndef BOARD_RCC_PLLMUL +#define BOARD_RCC_PLLMUL RCC_PLLMUL_9 +#endif + /* FIXME: Reintroduce all "#if 0"'ed blocks once libmaple provides * these definitions again. */ namespace wirish { namespace priv { - static stm32f1_rcc_pll_data pll_data = {RCC_PLLMUL_9}; + static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL}; rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6; adc_smp_rate w_adc_smp = ADC_SMPR_55_5; -- cgit v1.2.3 From 83f361c4bb9bed827b02df7aeae5f2cf9a14707a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 24 Apr 2012 03:20:18 -0400 Subject: stm32f1: stm32.h: Fix comment typo. --- libmaple/stm32f1/include/series/stm32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index ed51ae5..c122df0 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -56,7 +56,7 @@ extern "C" { # define STM32_SRAM_END ((void*)0x20010000) #elif defined(MCU_STM32F103CB) - /* This STM32_NR_GPIO_PORTS is not stricly true, but only pins 0 + /* This STM32_NR_GPIO_PORTS is not strictly true, but only pins 0 * and exist, and they're used for OSC (e.g. on e.g. LeafLabs * Maple Mini), so we'll live with this for now. */ # define STM32_NR_GPIO_PORTS 3 -- cgit v1.2.3 From 9c8b3225efd5ee816ad840ea97ba7bb92ff17941 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 24 Apr 2012 05:01:28 -0400 Subject: stm32.h: Various updates, mostly to help STM32F1 line support. Add STM32_HAVE_USB feature test macro requirement for . This will let us test if we've got a USB peripheral. wirish/stm32f1/boards_setup.cpp is set up to use this when turning on USB CDC ACM support at init() time. Rework the STM32F1 to make it easier to support the various lines that subdivide that series. We don't really support anything besides performance line yet, but there's been enough enthusiasm for value and connectivity line support in the past that these hooks seem worth adding. This means adding an STM32_F1_LINE macro and STM32_F1_LINE_[PERFORMANCE,VALUE,ACCESS,CONNECTIVITY] macros for values that STM32_F1_LINE can take, and generalizing the rest of the file to begin taking this into account. Some TODOs remain, but filling these in is the responsibility of future libmaple porting efforts. One pleasant consequence of the F1 stm32.h rework is that the build system no longer has to tell us what density of F103 we're building for, so remove that from the relevant support/make/board-includes/ files. Add some tweaks to and the STM32F2 stm32.h header to make sure this went through properly, and continues to go through properly in the future. --- libmaple/include/libmaple/stm32.h | 12 +++ libmaple/stm32f1/include/series/stm32.h | 100 ++++++++++++++++------- libmaple/stm32f2/include/series/stm32.h | 1 + support/make/board-includes/maple.mk | 2 - support/make/board-includes/maple_RET6.mk | 2 - support/make/board-includes/maple_mini.mk | 2 - support/make/board-includes/maple_native.mk | 2 - support/make/board-includes/olimex_stm32_h103.mk | 2 - wirish/stm32f1/boards_setup.cpp | 2 + 9 files changed, 84 insertions(+), 41 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index d6f3304..d53af3a 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -58,9 +58,21 @@ extern "C" { * * - STM32_HAVE_FSMC: 1 if the MCU has the FSMC peripheral, and 0 * otherwise. + * + * - STM32_HAVE_USB: 1 if the MCU has a USB peripheral, and 0 + * otherwise. */ #include +/* Ensure the series header isn't broken. */ +#if (!defined(STM32_PCLK1) || !defined(STM32_PCLK2) || \ + !defined(STM32_MCU_SERIES) || !defined(STM32_NR_INTERRUPTS) || \ + !defined(STM32_NR_GPIO_PORTS) || !defined(STM32_DELAY_US_MULT) || \ + !defined(STM32_SRAM_END) || !defined(STM32_HAVE_FSMC) || \ + !defined(STM32_HAVE_USB)) +#error "Bad STM32F1 configuration. Check header for your MCU." +#endif + #ifdef __DOXYGEN_PREDEFINED_HACK /* diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index c122df0..eaf9287 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -38,6 +38,17 @@ extern "C" { #define STM32_MCU_SERIES STM32_SERIES_F1 +/* The STM32F1 series is subdivided into "lines". libmaple currently + * officially supports STM32F103 performance line MCUs (see the + * MCU-specific value section below). + * + * You can use these F1 line defines if porting libmaple to support + * MCUs on other lines. */ +#define STM32_F1_LINE_PERFORMANCE 0 +#define STM32_F1_LINE_VALUE 1 +#define STM32_F1_LINE_ACCESS 2 +#define STM32_F1_LINE_CONNECTIVITY 3 + /* * MCU-specific values. * @@ -48,23 +59,31 @@ extern "C" { */ #if defined(MCU_STM32F103RB) +# define STM32_F1_LINE STM32_F1_LINE_PERFORMANCE # define STM32_NR_GPIO_PORTS 4 # define STM32_SRAM_END ((void*)0x20005000) +# define STM32_MEDIUM_DENSITY #elif defined(MCU_STM32F103ZE) +# define STM32_F1_LINE STM32_F1_LINE_PERFORMANCE # define STM32_NR_GPIO_PORTS 7 # define STM32_SRAM_END ((void*)0x20010000) +# define STM32_HIGH_DENSITY #elif defined(MCU_STM32F103CB) +# define STM32_F1_LINE STM32_F1_LINE_PERFORMANCE /* This STM32_NR_GPIO_PORTS is not strictly true, but only pins 0 * and exist, and they're used for OSC (e.g. on e.g. LeafLabs * Maple Mini), so we'll live with this for now. */ # define STM32_NR_GPIO_PORTS 3 # define STM32_SRAM_END ((void*)0x20005000) +# define STM32_MEDIUM_DENSITY #elif defined(MCU_STM32F103RE) +# define STM32_F1_LINE STM32_F1_LINE_PERFORMANCE # define STM32_NR_GPIO_PORTS 4 # define STM32_SRAM_END ((void*)0x20010000) +# define STM32_HIGH_DENSITY #else #error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ @@ -72,46 +91,65 @@ extern "C" { #endif /* - * Clock configuration. + * Derived values. */ -#ifndef STM32_PCLK1 -#define STM32_PCLK1 36000000U -#endif +#if STM32_F1_LINE == STM32_F1_LINE_PERFORMANCE + /* All supported performance line MCUs have a USB peripheral */ +# define STM32_HAVE_USB 1 + +# ifdef STM32_MEDIUM_DENSITY +# define STM32_NR_INTERRUPTS 43 +# define STM32_HAVE_FSMC 0 +# elif defined(STM32_HIGH_DENSITY) +# define STM32_NR_INTERRUPTS 60 +# define STM32_HAVE_FSMC 1 +# endif + +#elif STM32_F1_LINE == STM32_F1_LINE_VALUE + /* Value line MCUs don't have USB peripherals. */ +# define STM32_HAVE_USB 0 + +# ifdef STM32_MEDIUM_DENSITY +# define STM32_NR_INTERRUPTS 56 +# define STM32_HAVE_FSMC 0 +# elif defined(STM32_HIGH_DENSITY) + /* 61 interrupts here counts the possibility for a remapped + * DMA2 channel 5 IRQ occurring at NVIC index 60. */ +# define STM32_NR_INTERRUPTS 61 +# define STM32_HAVE_FSMC 1 +# endif -#ifndef STM32_PCLK2 -#define STM32_PCLK2 72000000U -#endif - -#ifndef STM32_DELAY_US_MULT -#define STM32_DELAY_US_MULT 12 /* FIXME: value is incorrect. */ #endif /* - * Density-specific values. + * Clock configuration. + * + * We've currently got values for F103 MCUs operating at the fastest + * possible speeds. + * + * You can patch these for your line, MCU, clock configuration, + * etc. here or by setting cflags when compiling libmaple. */ -#ifdef STM32_MEDIUM_DENSITY -# ifndef STM32_NR_INTERRUPTS -# define STM32_NR_INTERRUPTS 43 -# endif - -# ifndef STM32_HAVE_FSMC -# define STM32_HAVE_FSMC 0 -# endif - -#elif defined(STM32_HIGH_DENSITY) -# ifndef STM32_NR_INTERRUPTS -# define STM32_NR_INTERRUPTS 60 -# endif - -# ifndef STM32_HAVE_FSMC -# define STM32_HAVE_FSMC 1 -# endif +#if STM32_F1_LINE == STM32_F1_LINE_PERFORMANCE +# ifndef STM32_PCLK1 +# define STM32_PCLK1 36000000U +# endif +# ifndef STM32_PCLK2 +# define STM32_PCLK2 72000000U +# endif +# ifndef STM32_DELAY_US_MULT +# define STM32_DELAY_US_MULT 12 /* FIXME: value is incorrect. */ +# endif +#elif STM32_F1_LINE == STM32_F1_LINE_VALUE /* TODO */ +#elif STM32_F1_LINE == STM32_F1_LINE_ACCESS /* TODO */ +#elif STM32_F1_LINE == STM32_F1_LINE_CONNECTIVITY /* TODO */ +#endif -#else -#error "Unsupported STM32F1 density, or no density specified. Add something " \ - "like -DSTM32_MEDIUM_DENSITY to your compiler arguments." +/* Make sure we have the F1-specific defines we need. */ +#if !defined(STM32_F1_LINE) +#error "Bad STM32F1 configuration. Check STM32F1 header." #endif #ifdef __cplusplus diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 222608d..5ab4c56 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -59,6 +59,7 @@ extern "C" { #define STM32_MCU_SERIES STM32_SERIES_F2 #define STM32_NR_INTERRUPTS 81 #define STM32_HAVE_FSMC 1 +#define STM32_HAVE_USB 1 #if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG) # define STM32_NR_GPIO_PORTS 9 diff --git a/support/make/board-includes/maple.mk b/support/make/board-includes/maple.mk index a84f0ac..d31ad83 100644 --- a/support/make/board-includes/maple.mk +++ b/support/make/board-includes/maple.mk @@ -2,6 +2,4 @@ MCU := STM32F103RB PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 -DENSITY := STM32_MEDIUM_DENSITY -TARGET_FLAGS += -D$(DENSITY) MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/maple_RET6.mk b/support/make/board-includes/maple_RET6.mk index 8bd9b90..d06f068 100644 --- a/support/make/board-includes/maple_RET6.mk +++ b/support/make/board-includes/maple_RET6.mk @@ -2,6 +2,4 @@ MCU := STM32F103RE PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 -DENSITY := STM32_HIGH_DENSITY -TARGET_FLAGS += -D$(DENSITY) MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/maple_mini.mk b/support/make/board-includes/maple_mini.mk index 4a3e2ab..835adc3 100644 --- a/support/make/board-includes/maple_mini.mk +++ b/support/make/board-includes/maple_mini.mk @@ -2,6 +2,4 @@ MCU := STM32F103CB PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOB ERROR_LED_PIN := 1 -DENSITY := STM32_MEDIUM_DENSITY -TARGET_FLAGS += -D$(DENSITY) MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/maple_native.mk b/support/make/board-includes/maple_native.mk index cd07c21..3e88e7b 100644 --- a/support/make/board-includes/maple_native.mk +++ b/support/make/board-includes/maple_native.mk @@ -2,6 +2,4 @@ MCU := STM32F103ZE PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 15 -DENSITY := STM32_HIGH_DENSITY -TARGET_FLAGS += -D$(DENSITY) MCU_SERIES := stm32f1 diff --git a/support/make/board-includes/olimex_stm32_h103.mk b/support/make/board-includes/olimex_stm32_h103.mk index 1d84cc2..96d6976 100644 --- a/support/make/board-includes/olimex_stm32_h103.mk +++ b/support/make/board-includes/olimex_stm32_h103.mk @@ -2,6 +2,4 @@ MCU := STM32F103RB PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 12 -DENSITY := STM32_MEDIUM_DENSITY -TARGET_FLAGS += -D$(DENSITY) MCU_SERIES := stm32f1 diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index 74c0e79..a71661d 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -87,7 +87,9 @@ namespace wirish { void board_setup_usb(void) { #if 0 +# if STM32_HAVE_USB usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); +# endif #endif } -- cgit v1.2.3 From daf62cd246a4c747f9f7505afb9615924bc8ebff Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 23 Apr 2012 14:33:06 -0400 Subject: libmaple/dma.h: Fix Doxygen @file. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/dma.h b/libmaple/include/libmaple/dma.h index da2bd4f..32e915c 100644 --- a/libmaple/include/libmaple/dma.h +++ b/libmaple/include/libmaple/dma.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file dma.h + * @file libmaple/include/libmaple/dma.h * * @author Marti Bolivar ; * Original implementation by Michael Hope -- cgit v1.2.3 From ae98df23f2f940faa9197d3efa8bfd8cf8c6df96 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 23 Apr 2012 14:36:07 -0400 Subject: Move notes/dma.txt to notes/dma-stm32f1.txt. This information is all STM32F1 only. Signed-off-by: Marti Bolivar --- notes/dma-stm32f1.txt | 99 +++++++++++++++++++++++++++++++++++++++++++++++++++ notes/dma.txt | 99 --------------------------------------------------- 2 files changed, 99 insertions(+), 99 deletions(-) create mode 100644 notes/dma-stm32f1.txt delete mode 100644 notes/dma.txt diff --git a/notes/dma-stm32f1.txt b/notes/dma-stm32f1.txt new file mode 100644 index 0000000..97b23a0 --- /dev/null +++ b/notes/dma-stm32f1.txt @@ -0,0 +1,99 @@ +DMA Notes +========= + +Medium-density devices have one DMA controller, DMA1. High-density +devices and up also have DMA2. DMA1 has 7 channels; DMA2 has 5. Each +channel multiplexes DMA requests from various peripherals, like so: + +Channel Capabilities +-------------------- + +DMA1: + + * Channel 1: ADC1, TIM2_CH3, TIM4_CH1 + * Channel 2: USART3_TX, TIM1_CH1, TIM2_UP, TIM3_CH3, SPI1_RX + * Channel 3: USART3_RX, TIM1_CH2, TIM3_CH4, TIM3_UP, SPI1_TX + * Channel 4: USART1_TX, TIM1_CH4, TIM1_TRIG, TIM1_COM, TIM4_CH2, + SPI2/I2S2_RX, I2C2_TX + * Channel 5: USART1_RX, TIM1_UP, TIM2_CH1, TIM4_CH3, + SPI2/I2S2_TX, I2C2_RX + * Channel 6: USART2_RX, TIM1_CH3, TIM3_CH1, TIM3_TRIG, I2C1_TX + * Channel 7: USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX + +DMA2: + + * Channel 1: TIM5_CH4, TIM5_TRIG, TIM8_CH3, TIM8_UP, SPI/I2S3_RX + * Channel 2: TIM8_CH4, TIM8_TRIG, TIM8_COM, TIM5_CH3, TIM5_UP, SPI/I2S3_TX + * Channel 3: TIM8_CH1, UART4_RX, TIM6_UP/DAC_CH1 + * Channel 4: TIM5_CH2, SDIO, TIM7_UP/DAC_CH2 + * Channel 5: ADC3, TIM8_CH2, TIM5_CH1, UART4_TX + +An example usage: via DMA1, channel 1, you can have ADC1 periodically +dump converted data into an array in memory. The DMA controller can +then interrupt you when the array is half-full and full, and if any +error occurred. + +Since channels are multiplexed in hardware, you can't simultaneously +use the same DMA channel to serve requests from two of its peripherals +at the same time. For example, if you are using DMA 1 channel 1 to +serve DMA requests from ADC1, you can't also serve requests from Timer +2 channel 3. + +Channel Priority +---------------- + +An arbiter prioritizes simultaneous channel DMA requests. Channel +priority levels are configurable (4 levels of priority). Ties within +a DMA controller are broken by choosing the lower channel number; +between the controllers, DMA1 has higher priority than DMA2. + +Interrupts +---------- + +You can cause an interrupt to fire once half the transfers are +complete, when all the transfers are complete, if an error occurs +during transfer, or any combination of the three. + +If an error occurs, the transfer is automatically disabled. + +Configuration +------------- + +In order to configure a DMA transfer for DMA controller n, channel x, +ST RM0008 says you should do the following: + + A. Set the peripheral register address in DMAn_BASE->CPARx. + B. Set the memory address in DMAn_BASE->CMARx. + C. Set the number of data to be transferred in DMAn_BASE->CNDTRx. + D. Set the channel priority via the PL bits in DMAn_BASE->CCRx. + E. Configure various other things (e.g. data transfer sizes, what + events cause channel interrupts) in DMAn_BASE->CCRx as desired. + F. Activate the channel by setting ENABLE bit in DMAn_BASE->CCRx. + +The channel will start serving DMA requests as soon as it's activated. + +The DMA library lets you accomplish these tasks as follows: + + **Setup transfer** + + Do (A), (B), and (E) using dma_setup_transfer(). + + This also does (D), but chooses the lowest priority by default. + + **Perform any other desired configuration** + + You can do (C) using dma_set_num_transfers(). + + You can do (D) using dma_set_priority(). + + You can attach interrupt handlers with dma_attach_interrupt(). + + **Activate the channel** + + Do (F) with dma_enable(). + +Once you're all done, you can dma_disable() the channel. If you +dma_detach_interrupt() an interrupt handler, the channel interrupts +will stop firing, but the transfer itself won't stop until it's done +(which never happens if you set the DMA_CIRC_MODE flag when you called +dma_setup_transfer()). diff --git a/notes/dma.txt b/notes/dma.txt deleted file mode 100644 index 97b23a0..0000000 --- a/notes/dma.txt +++ /dev/null @@ -1,99 +0,0 @@ -DMA Notes -========= - -Medium-density devices have one DMA controller, DMA1. High-density -devices and up also have DMA2. DMA1 has 7 channels; DMA2 has 5. Each -channel multiplexes DMA requests from various peripherals, like so: - -Channel Capabilities --------------------- - -DMA1: - - * Channel 1: ADC1, TIM2_CH3, TIM4_CH1 - * Channel 2: USART3_TX, TIM1_CH1, TIM2_UP, TIM3_CH3, SPI1_RX - * Channel 3: USART3_RX, TIM1_CH2, TIM3_CH4, TIM3_UP, SPI1_TX - * Channel 4: USART1_TX, TIM1_CH4, TIM1_TRIG, TIM1_COM, TIM4_CH2, - SPI2/I2S2_RX, I2C2_TX - * Channel 5: USART1_RX, TIM1_UP, TIM2_CH1, TIM4_CH3, - SPI2/I2S2_TX, I2C2_RX - * Channel 6: USART2_RX, TIM1_CH3, TIM3_CH1, TIM3_TRIG, I2C1_TX - * Channel 7: USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX - -DMA2: - - * Channel 1: TIM5_CH4, TIM5_TRIG, TIM8_CH3, TIM8_UP, SPI/I2S3_RX - * Channel 2: TIM8_CH4, TIM8_TRIG, TIM8_COM, TIM5_CH3, TIM5_UP, SPI/I2S3_TX - * Channel 3: TIM8_CH1, UART4_RX, TIM6_UP/DAC_CH1 - * Channel 4: TIM5_CH2, SDIO, TIM7_UP/DAC_CH2 - * Channel 5: ADC3, TIM8_CH2, TIM5_CH1, UART4_TX - -An example usage: via DMA1, channel 1, you can have ADC1 periodically -dump converted data into an array in memory. The DMA controller can -then interrupt you when the array is half-full and full, and if any -error occurred. - -Since channels are multiplexed in hardware, you can't simultaneously -use the same DMA channel to serve requests from two of its peripherals -at the same time. For example, if you are using DMA 1 channel 1 to -serve DMA requests from ADC1, you can't also serve requests from Timer -2 channel 3. - -Channel Priority ----------------- - -An arbiter prioritizes simultaneous channel DMA requests. Channel -priority levels are configurable (4 levels of priority). Ties within -a DMA controller are broken by choosing the lower channel number; -between the controllers, DMA1 has higher priority than DMA2. - -Interrupts ----------- - -You can cause an interrupt to fire once half the transfers are -complete, when all the transfers are complete, if an error occurs -during transfer, or any combination of the three. - -If an error occurs, the transfer is automatically disabled. - -Configuration -------------- - -In order to configure a DMA transfer for DMA controller n, channel x, -ST RM0008 says you should do the following: - - A. Set the peripheral register address in DMAn_BASE->CPARx. - B. Set the memory address in DMAn_BASE->CMARx. - C. Set the number of data to be transferred in DMAn_BASE->CNDTRx. - D. Set the channel priority via the PL bits in DMAn_BASE->CCRx. - E. Configure various other things (e.g. data transfer sizes, what - events cause channel interrupts) in DMAn_BASE->CCRx as desired. - F. Activate the channel by setting ENABLE bit in DMAn_BASE->CCRx. - -The channel will start serving DMA requests as soon as it's activated. - -The DMA library lets you accomplish these tasks as follows: - - **Setup transfer** - - Do (A), (B), and (E) using dma_setup_transfer(). - - This also does (D), but chooses the lowest priority by default. - - **Perform any other desired configuration** - - You can do (C) using dma_set_num_transfers(). - - You can do (D) using dma_set_priority(). - - You can attach interrupt handlers with dma_attach_interrupt(). - - **Activate the channel** - - Do (F) with dma_enable(). - -Once you're all done, you can dma_disable() the channel. If you -dma_detach_interrupt() an interrupt handler, the channel interrupts -will stop firing, but the transfer itself won't stop until it's done -(which never happens if you set the DMA_CIRC_MODE flag when you called -dma_setup_transfer()). -- cgit v1.2.3 From a58ab72172936a224fb220122e703ea9a21cf9b8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 14:03:31 -0400 Subject: libmaple/stm32.h: Copyrights and cosmetics. Fix copyright. Fix Doxygen @file. Update file-level documentation, given this file's increased importance as an abstraction for porting between series. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index d53af3a..80d0777 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -1,7 +1,7 @@ /****************************************************************************** * The MIT License * - * Copyright (c) 2010 LeafLabs, LLC. + * Copyright (c) 2010, 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -25,8 +25,14 @@ *****************************************************************************/ /** - * @file stm32.h - * @brief STM32 chip-specific definitions + * @file libmaple/include/libmaple/stm32.h + * @brief STM32 chip header + * + * This header supplies various chip-specific values for the current + * build target. It's useful both to abstract away hardware details + * (e.g. through use of STM32_NR_INTERRUPTS) and to decide what to do + * when you want something nonportable (e.g. by checking + * STM32_MCU_SERIES). */ #ifndef _LIBMAPLE_STM32_H_ -- cgit v1.2.3 From 6ae19973da18ae67db0f0495c6b3cdf44797e2c8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 14:04:36 -0400 Subject: Doxyfile: Allow group documentation. This change allows us to document several members of a group with one Doxygen comment. It's not clear how well this will work out in practice. Signed-off-by: Marti Bolivar --- support/doxygen/Doxyfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/support/doxygen/Doxyfile b/support/doxygen/Doxyfile index 67b7692..35e6bd6 100644 --- a/support/doxygen/Doxyfile +++ b/support/doxygen/Doxyfile @@ -263,7 +263,7 @@ IDL_PROPERTY_SUPPORT = YES # member in the group (if any) for the other members of the group. By default # all members of a group must be documented explicitly. -DISTRIBUTE_GROUP_DOC = NO +DISTRIBUTE_GROUP_DOC = YES # Set the SUBGROUPING tag to YES (the default) to allow class member groups of # the same type (for instance a group of public functions) to be put as a -- cgit v1.2.3 From a81a02257d69454412d4ef062b56a3cc5c758815 Mon Sep 17 00:00:00 2001 From: Anton Eltchaninov Date: Thu, 26 Apr 2012 11:17:40 +0700 Subject: STM32VLDiscovery support files Signed-off-by: Anton Eltchaninov Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 15 ++++ support/ld/VLDiscovery/flash.ld | 24 ++++++ support/ld/VLDiscovery/jtag.ld | 24 ++++++ support/ld/VLDiscovery/ram.ld | 22 +++++ support/make/board-includes/VLDiscovery.mk | 5 ++ wirish/boards/VLDiscovery/board.cpp | 104 ++++++++++++++++++++++++ wirish/boards/VLDiscovery/include/board/board.h | 91 +++++++++++++++++++++ 7 files changed, 285 insertions(+) create mode 100644 support/ld/VLDiscovery/flash.ld create mode 100644 support/ld/VLDiscovery/jtag.ld create mode 100644 support/ld/VLDiscovery/ram.ld create mode 100644 support/make/board-includes/VLDiscovery.mk create mode 100644 wirish/boards/VLDiscovery/board.cpp create mode 100644 wirish/boards/VLDiscovery/include/board/board.h diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index eaf9287..76143a0 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -85,6 +85,12 @@ extern "C" { # define STM32_SRAM_END ((void*)0x20010000) # define STM32_HIGH_DENSITY +#elif defined(MCU_STM32F100RB) +# define STM32_F1_LINE STM32_F1_LINE_VALUE +# define STM32_NR_GPIO_PORTS 4 +# define STM32_SRAM_END ((void*)0x20002000) +# define STM32_MEDIUM_DENSITY + #else #error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ "-DMCU_STM32F103RB to your compiler arguments." @@ -143,6 +149,15 @@ extern "C" { # define STM32_DELAY_US_MULT 12 /* FIXME: value is incorrect. */ # endif #elif STM32_F1_LINE == STM32_F1_LINE_VALUE /* TODO */ +# ifndef STM32_PCLK1 +# define STM32_PCLK1 12000000U +# endif +# ifndef STM32_PCLK2 +# define STM32_PCLK2 24000000U +# endif +# ifndef STM32_DELAY_US_MULT +# define STM32_DELAY_US_MULT 8 /* FIXME: value is incorrect. */ +# endif #elif STM32_F1_LINE == STM32_F1_LINE_ACCESS /* TODO */ #elif STM32_F1_LINE == STM32_F1_LINE_CONNECTIVITY /* TODO */ #endif diff --git a/support/ld/VLDiscovery/flash.ld b/support/ld/VLDiscovery/flash.ld new file mode 100644 index 0000000..44ff8a1 --- /dev/null +++ b/support/ld/VLDiscovery/flash.ld @@ -0,0 +1,24 @@ +/* + * VLDiscovery (STM32F100RBT6, medium density) linker script for Flash builds. + */ + +/* + * Define memory spaces. + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K +} + +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", rom); + +/* + * Define the rest of the sections + */ +_FLASH_BUILD = 1; + +INCLUDE common.inc diff --git a/support/ld/VLDiscovery/jtag.ld b/support/ld/VLDiscovery/jtag.ld new file mode 100644 index 0000000..b952572 --- /dev/null +++ b/support/ld/VLDiscovery/jtag.ld @@ -0,0 +1,24 @@ +/* + * VLDiscovery (STM32F100RBT6, medium density) linker script for JTAG (bare + * metal, no bootloader) builds. + */ + +/* + * Define memory spaces. + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K +} + +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", rom); + +/* + * Define the rest of the sections + */ +_FLASH_BUILD = 1; +INCLUDE common.inc diff --git a/support/ld/VLDiscovery/ram.ld b/support/ld/VLDiscovery/ram.ld new file mode 100644 index 0000000..d659cd6 --- /dev/null +++ b/support/ld/VLDiscovery/ram.ld @@ -0,0 +1,22 @@ +/* + * VLDiscovery (STM32F100RBT6, medium density) linker script for RAM builds. + */ + +/* + * Define memory spaces. + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 0K +} + +REGION_ALIAS("REGION_TEXT", ram); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", ram); + +/* + * Define the rest of the sections + */ +INCLUDE common.inc diff --git a/support/make/board-includes/VLDiscovery.mk b/support/make/board-includes/VLDiscovery.mk new file mode 100644 index 0000000..82d1b23 --- /dev/null +++ b/support/make/board-includes/VLDiscovery.mk @@ -0,0 +1,5 @@ +MCU := STM32F100RB +PRODUCT_ID := 0003 +ERROR_LED_PORT := GPIOC +ERROR_LED_PIN := 9 +MCU_SERIES := stm32f1 diff --git a/wirish/boards/VLDiscovery/board.cpp b/wirish/boards/VLDiscovery/board.cpp new file mode 100644 index 0000000..c86204d --- /dev/null +++ b/wirish/boards/VLDiscovery/board.cpp @@ -0,0 +1,104 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/VLDiscovery/board.cpp + * @author Anton Eltchaninov + * @brief VLDiscovery board file. + */ + +#include + +#include +#include +#include + +void boardInit(void) { + afio_cfg_debug_ports(AFIO_DEBUG_SW_ONLY); +} + +extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { + + {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ + {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ + {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 (BUT) */ + {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ + {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ + {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ + {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ + {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ + {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ + {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ + {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ + {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ + {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ + {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 */ + {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ + {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ + {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ + {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ + {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ + {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ + {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ + {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ + {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ + {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ + {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ + {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ + {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ + {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ + {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ + {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ + {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ + {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ + {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ + {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ + {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ + {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D35/PC6 */ + {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D36/PC7 */ + {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D37/PC8 (Blue led) */ + {GPIOC, NULL, NULL, 9, 0, ADCx}, /* D38/PC9 (Green led) */ + {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D39/PA11 */ + {GPIOA, NULL, NULL, 12, 0, ADCx}, /* D40/PA12 */ + {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D41/PA15 */ + {GPIOB, NULL, NULL, 2, 0, ADCx}, /* D42/PB2 */ + {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D43/PB3 */ + {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D44/PB4 */ + {GPIOC, NULL, NULL, 11, 0, ADCx}, /* D45/PC11 */ + {GPIOC, NULL, NULL, 12, 0, ADCx} /* D46/PC12 */ +}; + +extern const uint8 boardPWMPins[] __FLASH__ = { + 0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 27, 28 +}; + +extern const uint8 boardADCPins[] __FLASH__ = { + 0, 1, 2, 3, 10, 11, 12, 15, 16, 17, 18, 19, 20, 27, 28 +}; + +extern const uint8 boardUsedPins[] __FLASH__ = { + BOARD_BLUE_LED_PIN, BOARD_GREEN_LED_PIN, BOARD_BUTTON_PIN +}; diff --git a/wirish/boards/VLDiscovery/include/board/board.h b/wirish/boards/VLDiscovery/include/board/board.h new file mode 100644 index 0000000..04d21c7 --- /dev/null +++ b/wirish/boards/VLDiscovery/include/board/board.h @@ -0,0 +1,91 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/boards/VLDiscovery/include/board/board.h + * @author Anton Eltchaninov + * @brief VLDiscovery board header. + */ + +#ifndef _BOARD_VLDISCOVERY_H_ +#define _BOARD_VLDISCOVERY_H_ + +#define BOARD_RCC_PLLMUL RCC_PLLMUL_3 + +#define CYCLES_PER_MICROSECOND 24 +#define SYSTICK_RELOAD_VAL 23999 /* takes a cycle to reload */ + +#define BOARD_BUTTON_PIN 2 /* PA0 USER */ +#define BOARD_BLUE_LED_PIN 37 /* blue led LD4 */ +#define BOARD_GREEN_LED_PIN 38 /* green led LD3 */ +#define BOARD_LED_PIN BOARD_BLUE_LED_PIN + +/* Number of USARTs/UARTs whose pins are broken out to headers */ +#define BOARD_NR_USARTS 3 + +/* Default USART pin numbers (not considering AFIO remap) */ +#define BOARD_USART1_TX_PIN 7 +#define BOARD_USART1_RX_PIN 8 +#define BOARD_USART2_TX_PIN 1 +#define BOARD_USART2_RX_PIN 0 +#define BOARD_USART3_TX_PIN 29 +#define BOARD_USART3_RX_PIN 30 + +/* Number of SPI ports */ +#define BOARD_NR_SPI 2 + +/* Default SPI pin numbers (not considering AFIO remap) */ +#define BOARD_SPI1_NSS_PIN 10 +#define BOARD_SPI1_MOSI_PIN 11 +#define BOARD_SPI1_MISO_PIN 12 +#define BOARD_SPI1_SCK_PIN 13 +#define BOARD_SPI2_NSS_PIN 31 +#define BOARD_SPI2_MOSI_PIN 34 +#define BOARD_SPI2_MISO_PIN 33 +#define BOARD_SPI2_SCK_PIN 32 + +/* Total number of GPIO pins that are broken out to headers and + * intended for general use. */ +#define BOARD_NR_GPIO_PINS 47 + +/* Number of pins capable of PWM output */ +#define BOARD_NR_PWM_PINS 15 + +/* Number of pins capable of ADC conversion */ +#define BOARD_NR_ADC_PINS 15 + +/* Number of pins already connected to external hardware. */ +#define BOARD_NR_USED_PINS 3 + +/* Save Maple pin order and define aliases */ +enum { +PA3, PA2, PA0, PA1, PB5, PB6, PA8, PA9, PA10, PB7, PA4, PA7, PA6, PA5, +PB8, PC0, PC1, PC2, PC3, PC4, PC5, PC13, PC14, PC15, PB9, PD2, PC10, +PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PC6, PC7, PC8, PC9, +PA11, PA12, PA15, PB2, PB3, PB4, PC11, PC12 }; + + +#endif -- cgit v1.2.3 From 1f67ed8f23048c45b0a3deec232b19047966bce7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 26 Apr 2012 17:33:56 -0400 Subject: stm32f1: Resurrect DMA support. (sets up breaking change) Breaking change set up: struct dma_handler_config is no longer part of the public API in . User code which was touching these was always mistaken; it should be using dma_attach_interrupt() or dma_detach_interrupt() instead. Other than that, just move the nonportable bits in and libmaple/dma.c to the appropriate places under libmaple/stm32f1/. (Ouch. This is almost everything.) Patch the (new) STM32F1 here and there to make everything compile; this is mostly limited to forward-declaring struct dma_dev and providing a hack _dma_dev_regs() declaration so inline functions in the series header can still access a device's registers. Signed-off-by: Marti Bolivar --- libmaple/dma.c | 338 +------------------------- libmaple/include/libmaple/dma.h | 404 ++----------------------------- libmaple/rules.mk | 2 +- libmaple/stm32f1/dma.c | 371 ++++++++++++++++++++++++++++ libmaple/stm32f1/include/series/dma.h | 438 ++++++++++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 1 + 6 files changed, 836 insertions(+), 718 deletions(-) create mode 100644 libmaple/stm32f1/dma.c create mode 100644 libmaple/stm32f1/include/series/dma.h diff --git a/libmaple/dma.c b/libmaple/dma.c index f20613b..6442e4d 100644 --- a/libmaple/dma.c +++ b/libmaple/dma.c @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Michael Hope. + * Copyright (c) 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -25,47 +26,13 @@ *****************************************************************************/ /** - * @file dma.c + * @file libmaple/dma.c * @author Marti Bolivar ; * Original implementation by Michael Hope - * @brief Direct Memory Access peripheral support + * @brief Portable DMA routines. */ #include -#include -#include - -/* - * Devices - */ - -static dma_dev dma1 = { - .regs = DMA1_BASE, - .clk_id = RCC_DMA1, - .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH2 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH3 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH4 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH5 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH6 }, - { .handler = NULL, .irq_line = NVIC_DMA_CH7 }} -}; -/** DMA1 device */ -dma_dev *DMA1 = &dma1; - -#ifdef STM32_HIGH_DENSITY -static dma_dev dma2 = { - .regs = DMA2_BASE, - .clk_id = RCC_DMA2, - .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1 }, - { .handler = NULL, .irq_line = NVIC_DMA2_CH2 }, - { .handler = NULL, .irq_line = NVIC_DMA2_CH3 }, - { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }, - { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }} /* !@#$ */ -}; -/** DMA2 device */ -dma_dev *DMA2 = &dma2; -#endif /* * Convenience routines @@ -78,302 +45,3 @@ dma_dev *DMA2 = &dma2; void dma_init(dma_dev *dev) { rcc_clk_enable(dev->clk_id); } - -/** - * @brief Set up a DMA transfer. - * - * The channel will be disabled before being reconfigured. The - * transfer will have low priority by default. You may choose another - * priority before the transfer begins using dma_set_priority(), as - * well as performing any other configuration you desire. When the - * channel is configured to your liking, enable it using dma_enable(). - * - * @param dev DMA device. - * @param channel DMA channel. - * @param peripheral_address Base address of peripheral data register - * involved in the transfer. - * @param peripheral_size Peripheral data transfer size. - * @param memory_address Base memory address involved in the transfer. - * @param memory_size Memory data transfer size. - * @param mode Logical OR of dma_mode_flags - * @sideeffect Disables the given DMA channel. - * @see dma_xfer_size - * @see dma_mode_flags - * @see dma_set_num_transfers() - * @see dma_set_priority() - * @see dma_attach_interrupt() - * @see dma_enable() - */ -void dma_setup_transfer(dma_dev *dev, - dma_channel channel, - __io void *peripheral_address, - dma_xfer_size peripheral_size, - __io void *memory_address, - dma_xfer_size memory_size, - uint32 mode) { - dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel); - - dma_disable(dev, channel); /* can't write to CMAR/CPAR otherwise */ - channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode; - channel_regs->CMAR = (uint32)memory_address; - channel_regs->CPAR = (uint32)peripheral_address; -} - -/** - * @brief Set the number of data to be transferred on a DMA channel. - * - * You may not call this function while the channel is enabled. - * - * @param dev DMA device - * @param channel Channel through which the transfer occurs. - * @param num_transfers - */ -void dma_set_num_transfers(dma_dev *dev, - dma_channel channel, - uint16 num_transfers) { - dma_channel_reg_map *channel_regs; - - ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); - - channel_regs = dma_channel_regs(dev, channel); - channel_regs->CNDTR = num_transfers; -} - -/** - * @brief Set the priority of a DMA transfer. - * - * You may not call this function while the channel is enabled. - * - * @param dev DMA device - * @param channel DMA channel - * @param priority priority to set. - */ -void dma_set_priority(dma_dev *dev, - dma_channel channel, - dma_priority priority) { - dma_channel_reg_map *channel_regs; - uint32 ccr; - - ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); - - channel_regs = dma_channel_regs(dev, channel); - ccr = channel_regs->CCR; - ccr &= ~DMA_CCR_PL; - ccr |= priority; - channel_regs->CCR = ccr; -} - -/** - * @brief Attach an interrupt to a DMA transfer. - * - * Interrupts are enabled using appropriate mode flags in - * dma_setup_transfer(). - * - * @param dev DMA device - * @param channel Channel to attach handler to - * @param handler Interrupt handler to call when channel interrupt fires. - * @see dma_setup_transfer() - * @see dma_get_irq_cause() - * @see dma_detach_interrupt() - */ -void dma_attach_interrupt(dma_dev *dev, - dma_channel channel, - void (*handler)(void)) { - dev->handlers[channel - 1].handler = handler; - nvic_irq_enable(dev->handlers[channel - 1].irq_line); -} - -/** - * @brief Detach a DMA transfer interrupt handler. - * - * After calling this function, the given channel's interrupts will be - * disabled. - * - * @param dev DMA device - * @param channel Channel whose handler to detach - * @sideeffect Clears interrupt enable bits in the channel's CCR register. - * @see dma_attach_interrupt() - */ -void dma_detach_interrupt(dma_dev *dev, dma_channel channel) { - /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */ - dma_channel_regs(dev, channel)->CCR &= ~0xF; - dev->handlers[channel - 1].handler = NULL; -} - -/** - * @brief Discover the reason why a DMA interrupt was called. - * - * You may only call this function within an attached interrupt - * handler for the given channel. - * - * This function resets the internal DMA register state which encodes - * the cause of the interrupt; consequently, it can only be called - * once per interrupt handler invocation. - * - * @param dev DMA device - * @param channel Channel whose interrupt is being handled. - * @return Reason why the interrupt fired. - * @sideeffect Clears channel status flags in dev->regs->ISR. - * @see dma_attach_interrupt() - * @see dma_irq_cause - */ -dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) { - uint8 status_bits = dma_get_isr_bits(dev, channel); - - /* If the channel global interrupt flag is cleared, then - * something's very wrong. */ - ASSERT(status_bits & BIT(0)); - - dma_clear_isr_bits(dev, channel); - - /* ISR flags get set even if the corresponding interrupt enable - * bits in the channel's configuration register are cleared, so we - * can't use a switch here. - * - * Don't change the order of these if statements. */ - if (status_bits & BIT(3)) { - return DMA_TRANSFER_ERROR; - } else if (status_bits & BIT(1)) { - return DMA_TRANSFER_COMPLETE; - } else if (status_bits & BIT(2)) { - return DMA_TRANSFER_HALF_COMPLETE; - } else if (status_bits & BIT(0)) { - /* Shouldn't happen (unless someone messed up an IFCR write). */ - throb(); - } -#if DEBUG_LEVEL < DEBUG_ALL - else { - /* We shouldn't have been called, but the debug level is too - * low for the above ASSERT() to have had any effect. In - * order to fail fast, mimic the DMA controller's behavior - * when an error occurs. */ - dma_disable(dev, channel); - } -#endif - return DMA_TRANSFER_ERROR; -} - -/** - * @brief Enable a DMA channel. - * @param dev DMA device - * @param channel Channel to enable - */ -void dma_enable(dma_dev *dev, dma_channel channel) { - dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); - bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1); -} - -/** - * @brief Disable a DMA channel. - * @param dev DMA device - * @param channel Channel to disable - */ -void dma_disable(dma_dev *dev, dma_channel channel) { - dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); - bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0); -} - -/** - * @brief Set the base memory address where data will be read from or - * written to. - * - * You must not call this function while the channel is enabled. - * - * If the DMA memory size is 16 bits, the address is automatically - * aligned to a half-word. If the DMA memory size is 32 bits, the - * address is aligned to a word. - * - * @param dev DMA Device - * @param channel Channel whose base memory address to set. - * @param addr Memory base address to use. - */ -void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) { - dma_channel_reg_map *chan_regs; - - ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); - - chan_regs = dma_channel_regs(dev, channel); - chan_regs->CMAR = (uint32)addr; -} - -/** - * @brief Set the base peripheral address where data will be read from - * or written to. - * - * You must not call this function while the channel is enabled. - * - * If the DMA peripheral size is 16 bits, the address is automatically - * aligned to a half-word. If the DMA peripheral size is 32 bits, the - * address is aligned to a word. - * - * @param dev DMA Device - * @param channel Channel whose peripheral data register base address to set. - * @param addr Peripheral memory base address to use. - */ -void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) { - dma_channel_reg_map *chan_regs; - - ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); - - chan_regs = dma_channel_regs(dev, channel); - chan_regs->CPAR = (uint32)addr; -} - -/* - * IRQ handlers - */ - -static inline void dispatch_handler(dma_dev *dev, dma_channel channel) { - void (*handler)(void) = dev->handlers[channel - 1].handler; - if (handler) { - handler(); - dma_clear_isr_bits(dev, channel); /* in case handler doesn't */ - } -} - -void __irq_dma1_channel1(void) { - dispatch_handler(DMA1, DMA_CH1); -} - -void __irq_dma1_channel2(void) { - dispatch_handler(DMA1, DMA_CH2); -} - -void __irq_dma1_channel3(void) { - dispatch_handler(DMA1, DMA_CH3); -} - -void __irq_dma1_channel4(void) { - dispatch_handler(DMA1, DMA_CH4); -} - -void __irq_dma1_channel5(void) { - dispatch_handler(DMA1, DMA_CH5); -} - -void __irq_dma1_channel6(void) { - dispatch_handler(DMA1, DMA_CH6); -} - -void __irq_dma1_channel7(void) { - dispatch_handler(DMA1, DMA_CH7); -} - -#ifdef STM32_HIGH_DENSITY -void __irq_dma2_channel1(void) { - dispatch_handler(DMA2, DMA_CH1); -} - -void __irq_dma2_channel2(void) { - dispatch_handler(DMA2, DMA_CH2); -} - -void __irq_dma2_channel3(void) { - dispatch_handler(DMA2, DMA_CH3); -} - -void __irq_dma2_channel4_5(void) { - dispatch_handler(DMA2, DMA_CH4); - dispatch_handler(DMA2, DMA_CH5); -} -#endif diff --git a/libmaple/include/libmaple/dma.h b/libmaple/include/libmaple/dma.h index 32e915c..0aed572 100644 --- a/libmaple/include/libmaple/dma.h +++ b/libmaple/include/libmaple/dma.h @@ -33,10 +33,6 @@ * @brief Direct Memory Access peripheral support */ -/* - * See /notes/dma.txt for more information. - */ - #ifndef _LIBMAPLE_DMA_H_ #define _LIBMAPLE_DMA_H_ @@ -44,406 +40,50 @@ extern "C"{ #endif -#include -#include -#include - -/* - * Register maps - */ - -/** - * @brief DMA register map type. +/* provides: * - * Note that DMA controller 2 (register map base pointer DMA2_BASE) - * only supports channels 1--5. + * - Normal stuff: dma_reg_map and base pointers, register bit + * definitions, dma_dev pointer declarations, and any other + * convenience functions useful for that series. */ -typedef struct dma_reg_map { - __io uint32 ISR; /**< Interrupt status register */ - __io uint32 IFCR; /**< Interrupt flag clear register */ - __io uint32 CCR1; /**< Channel 1 configuration register */ - __io uint32 CNDTR1; /**< Channel 1 number of data register */ - __io uint32 CPAR1; /**< Channel 1 peripheral address register */ - __io uint32 CMAR1; /**< Channel 1 memory address register */ - const uint32 RESERVED1; /**< Reserved. */ - __io uint32 CCR2; /**< Channel 2 configuration register */ - __io uint32 CNDTR2; /**< Channel 2 number of data register */ - __io uint32 CPAR2; /**< Channel 2 peripheral address register */ - __io uint32 CMAR2; /**< Channel 2 memory address register */ - const uint32 RESERVED2; /**< Reserved. */ - __io uint32 CCR3; /**< Channel 3 configuration register */ - __io uint32 CNDTR3; /**< Channel 3 number of data register */ - __io uint32 CPAR3; /**< Channel 3 peripheral address register */ - __io uint32 CMAR3; /**< Channel 3 memory address register */ - const uint32 RESERVED3; /**< Reserved. */ - __io uint32 CCR4; /**< Channel 4 configuration register */ - __io uint32 CNDTR4; /**< Channel 4 number of data register */ - __io uint32 CPAR4; /**< Channel 4 peripheral address register */ - __io uint32 CMAR4; /**< Channel 4 memory address register */ - const uint32 RESERVED4; /**< Reserved. */ - __io uint32 CCR5; /**< Channel 5 configuration register */ - __io uint32 CNDTR5; /**< Channel 5 number of data register */ - __io uint32 CPAR5; /**< Channel 5 peripheral address register */ - __io uint32 CMAR5; /**< Channel 5 memory address register */ - const uint32 RESERVED5; /**< Reserved. */ - __io uint32 CCR6; /**< Channel 6 configuration register */ - __io uint32 CNDTR6; /**< Channel 6 number of data register */ - __io uint32 CPAR6; /**< Channel 6 peripheral address register */ - __io uint32 CMAR6; /**< Channel 6 memory address register */ - const uint32 RESERVED6; /**< Reserved. */ - __io uint32 CCR7; /**< Channel 7 configuration register */ - __io uint32 CNDTR7; /**< Channel 7 number of data register */ - __io uint32 CPAR7; /**< Channel 7 peripheral address register */ - __io uint32 CMAR7; /**< Channel 7 memory address register */ - const uint32 RESERVED7; /**< Reserved. */ -} dma_reg_map; - -/** DMA controller 1 register map base pointer */ -#define DMA1_BASE ((struct dma_reg_map*)0x40020000) - -#ifdef STM32_HIGH_DENSITY -/** DMA controller 2 register map base pointer */ -#define DMA2_BASE ((struct dma_reg_map*)0x40020400) -#endif - -/* - * Register bit definitions - */ - -/* Interrupt status register */ +#include -#define DMA_ISR_TEIF7_BIT 27 -#define DMA_ISR_HTIF7_BIT 26 -#define DMA_ISR_TCIF7_BIT 25 -#define DMA_ISR_GIF7_BIT 24 -#define DMA_ISR_TEIF6_BIT 23 -#define DMA_ISR_HTIF6_BIT 22 -#define DMA_ISR_TCIF6_BIT 21 -#define DMA_ISR_GIF6_BIT 20 -#define DMA_ISR_TEIF5_BIT 19 -#define DMA_ISR_HTIF5_BIT 18 -#define DMA_ISR_TCIF5_BIT 17 -#define DMA_ISR_GIF5_BIT 16 -#define DMA_ISR_TEIF4_BIT 15 -#define DMA_ISR_HTIF4_BIT 14 -#define DMA_ISR_TCIF4_BIT 13 -#define DMA_ISR_GIF4_BIT 12 -#define DMA_ISR_TEIF3_BIT 11 -#define DMA_ISR_HTIF3_BIT 10 -#define DMA_ISR_TCIF3_BIT 9 -#define DMA_ISR_GIF3_BIT 8 -#define DMA_ISR_TEIF2_BIT 7 -#define DMA_ISR_HTIF2_BIT 6 -#define DMA_ISR_TCIF2_BIT 5 -#define DMA_ISR_GIF2_BIT 4 -#define DMA_ISR_TEIF1_BIT 3 -#define DMA_ISR_HTIF1_BIT 2 -#define DMA_ISR_TCIF1_BIT 1 -#define DMA_ISR_GIF1_BIT 0 - -#define DMA_ISR_TEIF7 BIT(DMA_ISR_TEIF7_BIT) -#define DMA_ISR_HTIF7 BIT(DMA_ISR_HTIF7_BIT) -#define DMA_ISR_TCIF7 BIT(DMA_ISR_TCIF7_BIT) -#define DMA_ISR_GIF7 BIT(DMA_ISR_GIF7_BIT) -#define DMA_ISR_TEIF6 BIT(DMA_ISR_TEIF6_BIT) -#define DMA_ISR_HTIF6 BIT(DMA_ISR_HTIF6_BIT) -#define DMA_ISR_TCIF6 BIT(DMA_ISR_TCIF6_BIT) -#define DMA_ISR_GIF6 BIT(DMA_ISR_GIF6_BIT) -#define DMA_ISR_TEIF5 BIT(DMA_ISR_TEIF5_BIT) -#define DMA_ISR_HTIF5 BIT(DMA_ISR_HTIF5_BIT) -#define DMA_ISR_TCIF5 BIT(DMA_ISR_TCIF5_BIT) -#define DMA_ISR_GIF5 BIT(DMA_ISR_GIF5_BIT) -#define DMA_ISR_TEIF4 BIT(DMA_ISR_TEIF4_BIT) -#define DMA_ISR_HTIF4 BIT(DMA_ISR_HTIF4_BIT) -#define DMA_ISR_TCIF4 BIT(DMA_ISR_TCIF4_BIT) -#define DMA_ISR_GIF4 BIT(DMA_ISR_GIF4_BIT) -#define DMA_ISR_TEIF3 BIT(DMA_ISR_TEIF3_BIT) -#define DMA_ISR_HTIF3 BIT(DMA_ISR_HTIF3_BIT) -#define DMA_ISR_TCIF3 BIT(DMA_ISR_TCIF3_BIT) -#define DMA_ISR_GIF3 BIT(DMA_ISR_GIF3_BIT) -#define DMA_ISR_TEIF2 BIT(DMA_ISR_TEIF2_BIT) -#define DMA_ISR_HTIF2 BIT(DMA_ISR_HTIF2_BIT) -#define DMA_ISR_TCIF2 BIT(DMA_ISR_TCIF2_BIT) -#define DMA_ISR_GIF2 BIT(DMA_ISR_GIF2_BIT) -#define DMA_ISR_TEIF1 BIT(DMA_ISR_TEIF1_BIT) -#define DMA_ISR_HTIF1 BIT(DMA_ISR_HTIF1_BIT) -#define DMA_ISR_TCIF1 BIT(DMA_ISR_TCIF1_BIT) -#define DMA_ISR_GIF1 BIT(DMA_ISR_GIF1_BIT) - -/* Interrupt flag clear register */ - -#define DMA_IFCR_CTEIF7_BIT 27 -#define DMA_IFCR_CHTIF7_BIT 26 -#define DMA_IFCR_CTCIF7_BIT 25 -#define DMA_IFCR_CGIF7_BIT 24 -#define DMA_IFCR_CTEIF6_BIT 23 -#define DMA_IFCR_CHTIF6_BIT 22 -#define DMA_IFCR_CTCIF6_BIT 21 -#define DMA_IFCR_CGIF6_BIT 20 -#define DMA_IFCR_CTEIF5_BIT 19 -#define DMA_IFCR_CHTIF5_BIT 18 -#define DMA_IFCR_CTCIF5_BIT 17 -#define DMA_IFCR_CGIF5_BIT 16 -#define DMA_IFCR_CTEIF4_BIT 15 -#define DMA_IFCR_CHTIF4_BIT 14 -#define DMA_IFCR_CTCIF4_BIT 13 -#define DMA_IFCR_CGIF4_BIT 12 -#define DMA_IFCR_CTEIF3_BIT 11 -#define DMA_IFCR_CHTIF3_BIT 10 -#define DMA_IFCR_CTCIF3_BIT 9 -#define DMA_IFCR_CGIF3_BIT 8 -#define DMA_IFCR_CTEIF2_BIT 7 -#define DMA_IFCR_CHTIF2_BIT 6 -#define DMA_IFCR_CTCIF2_BIT 5 -#define DMA_IFCR_CGIF2_BIT 4 -#define DMA_IFCR_CTEIF1_BIT 3 -#define DMA_IFCR_CHTIF1_BIT 2 -#define DMA_IFCR_CTCIF1_BIT 1 -#define DMA_IFCR_CGIF1_BIT 0 - -#define DMA_IFCR_CTEIF7 BIT(DMA_IFCR_CTEIF7_BIT) -#define DMA_IFCR_CHTIF7 BIT(DMA_IFCR_CHTIF7_BIT) -#define DMA_IFCR_CTCIF7 BIT(DMA_IFCR_CTCIF7_BIT) -#define DMA_IFCR_CGIF7 BIT(DMA_IFCR_CGIF7_BIT) -#define DMA_IFCR_CTEIF6 BIT(DMA_IFCR_CTEIF6_BIT) -#define DMA_IFCR_CHTIF6 BIT(DMA_IFCR_CHTIF6_BIT) -#define DMA_IFCR_CTCIF6 BIT(DMA_IFCR_CTCIF6_BIT) -#define DMA_IFCR_CGIF6 BIT(DMA_IFCR_CGIF6_BIT) -#define DMA_IFCR_CTEIF5 BIT(DMA_IFCR_CTEIF5_BIT) -#define DMA_IFCR_CHTIF5 BIT(DMA_IFCR_CHTIF5_BIT) -#define DMA_IFCR_CTCIF5 BIT(DMA_IFCR_CTCIF5_BIT) -#define DMA_IFCR_CGIF5 BIT(DMA_IFCR_CGIF5_BIT) -#define DMA_IFCR_CTEIF4 BIT(DMA_IFCR_CTEIF4_BIT) -#define DMA_IFCR_CHTIF4 BIT(DMA_IFCR_CHTIF4_BIT) -#define DMA_IFCR_CTCIF4 BIT(DMA_IFCR_CTCIF4_BIT) -#define DMA_IFCR_CGIF4 BIT(DMA_IFCR_CGIF4_BIT) -#define DMA_IFCR_CTEIF3 BIT(DMA_IFCR_CTEIF3_BIT) -#define DMA_IFCR_CHTIF3 BIT(DMA_IFCR_CHTIF3_BIT) -#define DMA_IFCR_CTCIF3 BIT(DMA_IFCR_CTCIF3_BIT) -#define DMA_IFCR_CGIF3 BIT(DMA_IFCR_CGIF3_BIT) -#define DMA_IFCR_CTEIF2 BIT(DMA_IFCR_CTEIF2_BIT) -#define DMA_IFCR_CHTIF2 BIT(DMA_IFCR_CHTIF2_BIT) -#define DMA_IFCR_CTCIF2 BIT(DMA_IFCR_CTCIF2_BIT) -#define DMA_IFCR_CGIF2 BIT(DMA_IFCR_CGIF2_BIT) -#define DMA_IFCR_CTEIF1 BIT(DMA_IFCR_CTEIF1_BIT) -#define DMA_IFCR_CHTIF1 BIT(DMA_IFCR_CHTIF1_BIT) -#define DMA_IFCR_CTCIF1 BIT(DMA_IFCR_CTCIF1_BIT) -#define DMA_IFCR_CGIF1 BIT(DMA_IFCR_CGIF1_BIT) - -/* Channel configuration register */ - -#define DMA_CCR_MEM2MEM_BIT 14 -#define DMA_CCR_MINC_BIT 7 -#define DMA_CCR_PINC_BIT 6 -#define DMA_CCR_CIRC_BIT 5 -#define DMA_CCR_DIR_BIT 4 -#define DMA_CCR_TEIE_BIT 3 -#define DMA_CCR_HTIE_BIT 2 -#define DMA_CCR_TCIE_BIT 1 -#define DMA_CCR_EN_BIT 0 - -#define DMA_CCR_MEM2MEM BIT(DMA_CCR_MEM2MEM_BIT) -#define DMA_CCR_PL (0x3 << 12) -#define DMA_CCR_PL_LOW (0x0 << 12) -#define DMA_CCR_PL_MEDIUM (0x1 << 12) -#define DMA_CCR_PL_HIGH (0x2 << 12) -#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) -#define DMA_CCR_MSIZE (0x3 << 10) -#define DMA_CCR_MSIZE_8BITS (0x0 << 10) -#define DMA_CCR_MSIZE_16BITS (0x1 << 10) -#define DMA_CCR_MSIZE_32BITS (0x2 << 10) -#define DMA_CCR_PSIZE (0x3 << 8) -#define DMA_CCR_PSIZE_8BITS (0x0 << 8) -#define DMA_CCR_PSIZE_16BITS (0x1 << 8) -#define DMA_CCR_PSIZE_32BITS (0x2 << 8) -#define DMA_CCR_MINC BIT(DMA_CCR_MINC_BIT) -#define DMA_CCR_PINC BIT(DMA_CCR_PINC_BIT) -#define DMA_CCR_CIRC BIT(DMA_CCR_CIRC_BIT) -#define DMA_CCR_DIR BIT(DMA_CCR_DIR_BIT) -#define DMA_CCR_TEIE BIT(DMA_CCR_TEIE_BIT) -#define DMA_CCR_HTIE BIT(DMA_CCR_HTIE_BIT) -#define DMA_CCR_TCIE BIT(DMA_CCR_TCIE_BIT) -#define DMA_CCR_EN BIT(DMA_CCR_EN_BIT) +#include +#include +#include /* * Devices */ -/** Encapsulates state related to a DMA channel interrupt. */ +/* Encapsulates state related to user interrupt handlers. You + * shouldn't touch these directly; use dma_attach_interrupt() and + * dma_detach_interupt() instead. */ typedef struct dma_handler_config { - void (*handler)(void); /**< User-specified channel interrupt - handler */ - nvic_irq_num irq_line; /**< Channel's NVIC interrupt number */ + void (*handler)(void); /* User handler */ + nvic_irq_num irq_line; /* IRQ line for interrupt */ } dma_handler_config; /** DMA device type */ typedef struct dma_dev { - dma_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< Clock ID */ - dma_handler_config handlers[]; /**< - * @brief IRQ handlers and NVIC numbers. - * - * @see dma_attach_interrupt() - * @see dma_detach_interrupt() - */ + dma_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< Clock ID */ + struct dma_handler_config handlers[]; /**< For internal use */ } dma_dev; -extern dma_dev *DMA1; -#ifdef STM32_HIGH_DENSITY -extern dma_dev *DMA2; -#endif - /* * Convenience functions */ void dma_init(dma_dev *dev); -/** Flags for DMA transfer configuration. */ -typedef enum dma_mode_flags { - DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ - DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ - DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ - DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ - DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ - DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ - DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ - DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ -} dma_mode_flags; - -/** Source and destination transfer sizes. */ -typedef enum dma_xfer_size { - DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ - DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ - DMA_SIZE_32BITS = 2 /**< 32-bit transfers */ -} dma_xfer_size; - -/** DMA channel */ -typedef enum dma_channel { - DMA_CH1 = 1, /**< Channel 1 */ - DMA_CH2 = 2, /**< Channel 2 */ - DMA_CH3 = 3, /**< Channel 3 */ - DMA_CH4 = 4, /**< Channel 4 */ - DMA_CH5 = 5, /**< Channel 5 */ - DMA_CH6 = 6, /**< Channel 6 */ - DMA_CH7 = 7, /**< Channel 7 */ -} dma_channel; - -void dma_setup_transfer(dma_dev *dev, - dma_channel channel, - __io void *peripheral_address, - dma_xfer_size peripheral_size, - __io void *memory_address, - dma_xfer_size memory_size, - uint32 mode); - -void dma_set_num_transfers(dma_dev *dev, - dma_channel channel, - uint16 num_transfers); - -/** DMA transfer priority. */ -typedef enum dma_priority { - DMA_PRIORITY_LOW = DMA_CCR_PL_LOW, /**< Low priority */ - DMA_PRIORITY_MEDIUM = DMA_CCR_PL_MEDIUM, /**< Medium priority */ - DMA_PRIORITY_HIGH = DMA_CCR_PL_HIGH, /**< High priority */ - DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */ -} dma_priority; - -void dma_set_priority(dma_dev *dev, - dma_channel channel, - dma_priority priority); - -void dma_attach_interrupt(dma_dev *dev, - dma_channel channel, - void (*handler)(void)); -void dma_detach_interrupt(dma_dev *dev, dma_channel channel); - -/** - * Encodes the reason why a DMA interrupt was called. - * @see dma_get_irq_cause() - */ -typedef enum dma_irq_cause { - DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ - DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ - DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ -} dma_irq_cause; - -dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel); - -void dma_enable(dma_dev *dev, dma_channel channel); -void dma_disable(dma_dev *dev, dma_channel channel); - -void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address); -void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address); - -/** - * @brief DMA channel register map type. - * - * Provides access to an individual channel's registers. - */ -typedef struct dma_channel_reg_map { - __io uint32 CCR; /**< Channel configuration register */ - __io uint32 CNDTR; /**< Channel number of data register */ - __io uint32 CPAR; /**< Channel peripheral address register */ - __io uint32 CMAR; /**< Channel memory address register */ -} dma_channel_reg_map; - -#define DMA_CHANNEL_NREGS 5 - -/** - * @brief Obtain a pointer to an individual DMA channel's registers. - * - * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. - * - * @param dev DMA device - * @param channel DMA channel whose channel register map to obtain. - */ -static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev, - dma_channel channel) { - __io uint32 *ccr1 = &dev->regs->CCR1; - return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1)); -} - -/** - * @brief Check if a DMA channel is enabled - * @param dev DMA device - * @param channel Channel whose enabled bit to check. - */ -static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) { - return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN); -} - -/** - * @brief Get the ISR status bits for a DMA channel. - * - * The bits are returned right-aligned, in the following order: - * transfer error flag, half-transfer flag, transfer complete flag, - * global interrupt flag. - * - * If you're attempting to figure out why a DMA interrupt fired; you - * may find dma_get_irq_cause() more convenient. - * - * @param dev DMA device - * @param channel Channel whose ISR bits to return. - * @see dma_get_irq_cause(). - */ -static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) { - uint8 shift = (channel - 1) * 4; - return (dev->regs->ISR >> shift) & 0xF; -} - -/** - * @brief Clear the ISR status bits for a given DMA channel. - * - * If you're attempting to clean up after yourself in a DMA interrupt, - * you may find dma_get_irq_cause() more convenient. - * - * @param dev DMA device - * @param channel Channel whose ISR bits to clear. - * @see dma_get_irq_cause() +/* + * Hack: This is here so the series header can declare it and access + * dma_dev->regs without knowing the structure of dma_dev. Don't use + * it outside of a series header. */ -static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) { - dev->regs->IFCR = BIT(4 * (channel - 1)); +static __always_inline dma_reg_map* _dma_dev_regs(dma_dev *dev) { + return dev->regs; } #ifdef __cplusplus diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 93716d2..d6efb1f 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -12,6 +12,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c +cSRCS_$(d) += dma.c cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c cSRCS_$(d) += iwdg.c @@ -27,7 +28,6 @@ cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c # These still need to be ported to F2: # cSRCS_$(d) += dac.c -# cSRCS_$(d) += dma.c # cSRCS_$(d) += exti.c # cSRCS_$(d) += i2c.c diff --git a/libmaple/stm32f1/dma.c b/libmaple/stm32f1/dma.c new file mode 100644 index 0000000..14ac645 --- /dev/null +++ b/libmaple/stm32f1/dma.c @@ -0,0 +1,371 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Michael Hope. + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/dma.c + * @author Marti Bolivar ; + * Original implementation by Michael Hope + * @brief STM32F1 DMA support. + */ + +#include +#include + +/* + * Devices + */ + +static dma_dev dma1 = { + .regs = DMA1_BASE, + .clk_id = RCC_DMA1, + .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH2 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH3 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH4 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH5 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH6 }, + { .handler = NULL, .irq_line = NVIC_DMA_CH7 }}, +}; +/** DMA1 device */ +dma_dev *DMA1 = &dma1; + +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +static dma_dev dma2 = { + .regs = DMA2_BASE, + .clk_id = RCC_DMA2, + .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH2 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH3 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }, + { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }}, /* !@#$ */ +}; +/** DMA2 device */ +dma_dev *DMA2 = &dma2; +#endif + +/* + * Routines + */ + +/** + * @brief Set up a DMA transfer. + * + * The channel will be disabled before being reconfigured. The + * transfer will have low priority by default. You may choose another + * priority before the transfer begins using dma_set_priority(), as + * well as performing any other configuration you desire. When the + * channel is configured to your liking, enable it using dma_enable(). + * + * @param dev DMA device. + * @param channel DMA channel. + * @param peripheral_address Base address of peripheral data register + * involved in the transfer. + * @param peripheral_size Peripheral data transfer size. + * @param memory_address Base memory address involved in the transfer. + * @param memory_size Memory data transfer size. + * @param mode Logical OR of dma_mode_flags + * @sideeffect Disables the given DMA channel. + * @see dma_xfer_size + * @see dma_mode_flags + * @see dma_set_num_transfers() + * @see dma_set_priority() + * @see dma_attach_interrupt() + * @see dma_enable() + */ +void dma_setup_transfer(dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode) { + dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel); + + dma_disable(dev, channel); /* can't write to CMAR/CPAR otherwise */ + channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode; + channel_regs->CMAR = (uint32)memory_address; + channel_regs->CPAR = (uint32)peripheral_address; +} + +/** + * @brief Set the number of data to be transferred on a DMA channel. + * + * You may not call this function while the channel is enabled. + * + * @param dev DMA device + * @param channel Channel through which the transfer occurs. + * @param num_transfers + */ +void dma_set_num_transfers(dma_dev *dev, + dma_channel channel, + uint16 num_transfers) { + dma_channel_reg_map *channel_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + channel_regs = dma_channel_regs(dev, channel); + channel_regs->CNDTR = num_transfers; +} + +/** + * @brief Set the priority of a DMA transfer. + * + * You may not call this function while the channel is enabled. + * + * @param dev DMA device + * @param channel DMA channel + * @param priority priority to set. + */ +void dma_set_priority(dma_dev *dev, + dma_channel channel, + dma_priority priority) { + dma_channel_reg_map *channel_regs; + uint32 ccr; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + channel_regs = dma_channel_regs(dev, channel); + ccr = channel_regs->CCR; + ccr &= ~DMA_CCR_PL; + ccr |= priority; + channel_regs->CCR = ccr; +} + +/** + * @brief Attach an interrupt to a DMA transfer. + * + * Interrupts are enabled using appropriate mode flags in + * dma_setup_transfer(). + * + * @param dev DMA device + * @param channel Channel to attach handler to + * @param handler Interrupt handler to call when channel interrupt fires. + * @see dma_setup_transfer() + * @see dma_get_irq_cause() + * @see dma_detach_interrupt() + */ +void dma_attach_interrupt(dma_dev *dev, + dma_channel channel, + void (*handler)(void)) { + dev->handlers[channel - 1].handler = handler; + nvic_irq_enable(dev->handlers[channel - 1].irq_line); +} + +/** + * @brief Detach a DMA transfer interrupt handler. + * + * After calling this function, the given channel's interrupts will be + * disabled. + * + * @param dev DMA device + * @param channel Channel whose handler to detach + * @sideeffect Clears interrupt enable bits in the channel's CCR register. + * @see dma_attach_interrupt() + */ +void dma_detach_interrupt(dma_dev *dev, dma_channel channel) { + /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */ + dma_channel_regs(dev, channel)->CCR &= ~0xF; + dev->handlers[channel - 1].handler = NULL; +} + +/** + * @brief Discover the reason why a DMA interrupt was called. + * + * You may only call this function within an attached interrupt + * handler for the given channel. + * + * This function resets the internal DMA register state which encodes + * the cause of the interrupt; consequently, it can only be called + * once per interrupt handler invocation. + * + * @param dev DMA device + * @param channel Channel whose interrupt is being handled. + * @return Reason why the interrupt fired. + * @sideeffect Clears channel status flags in dev->regs->ISR. + * @see dma_attach_interrupt() + * @see dma_irq_cause + */ +dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) { + uint8 status_bits = dma_get_isr_bits(dev, channel); + + /* If the channel global interrupt flag is cleared, then + * something's very wrong. */ + ASSERT(status_bits & BIT(0)); + + dma_clear_isr_bits(dev, channel); + + /* ISR flags get set even if the corresponding interrupt enable + * bits in the channel's configuration register are cleared, so we + * can't use a switch here. + * + * Don't change the order of these if statements. */ + if (status_bits & BIT(3)) { + return DMA_TRANSFER_ERROR; + } else if (status_bits & BIT(1)) { + return DMA_TRANSFER_COMPLETE; + } else if (status_bits & BIT(2)) { + return DMA_TRANSFER_HALF_COMPLETE; + } else if (status_bits & BIT(0)) { + /* Shouldn't happen (unless someone messed up an IFCR write). */ + throb(); + } +#if DEBUG_LEVEL < DEBUG_ALL + else { + /* We shouldn't have been called, but the debug level is too + * low for the above ASSERT() to have had any effect. In + * order to fail fast, mimic the DMA controller's behavior + * when an error occurs. */ + dma_disable(dev, channel); + } +#endif + return DMA_TRANSFER_ERROR; +} + +/** + * @brief Enable a DMA channel. + * @param dev DMA device + * @param channel Channel to enable + */ +void dma_enable(dma_dev *dev, dma_channel channel) { + dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); + bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1); +} + +/** + * @brief Disable a DMA channel. + * @param dev DMA device + * @param channel Channel to disable + */ +void dma_disable(dma_dev *dev, dma_channel channel) { + dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); + bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0); +} + +/** + * @brief Set the base memory address where data will be read from or + * written to. + * + * You must not call this function while the channel is enabled. + * + * If the DMA memory size is 16 bits, the address is automatically + * aligned to a half-word. If the DMA memory size is 32 bits, the + * address is aligned to a word. + * + * @param dev DMA Device + * @param channel Channel whose base memory address to set. + * @param addr Memory base address to use. + */ +void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) { + dma_channel_reg_map *chan_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + chan_regs = dma_channel_regs(dev, channel); + chan_regs->CMAR = (uint32)addr; +} + +/** + * @brief Set the base peripheral address where data will be read from + * or written to. + * + * You must not call this function while the channel is enabled. + * + * If the DMA peripheral size is 16 bits, the address is automatically + * aligned to a half-word. If the DMA peripheral size is 32 bits, the + * address is aligned to a word. + * + * @param dev DMA Device + * @param channel Channel whose peripheral data register base address to set. + * @param addr Peripheral memory base address to use. + */ +void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) { + dma_channel_reg_map *chan_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + chan_regs = dma_channel_regs(dev, channel); + chan_regs->CPAR = (uint32)addr; +} + +/* + * IRQ handlers + */ + +static __always_inline void dispatch_handler(dma_dev *dev, int channel) { + void (*handler)(void) = dev->handlers[channel - 1].handler; + if (handler) { + handler(); + dma_clear_isr_bits(dev, channel); /* in case handler doesn't */ + } +} + +void __irq_dma1_channel1(void) { + dispatch_handler(DMA1, DMA_CH1); +} + +void __irq_dma1_channel2(void) { + dispatch_handler(DMA1, DMA_CH2); +} + +void __irq_dma1_channel3(void) { + dispatch_handler(DMA1, DMA_CH3); +} + +void __irq_dma1_channel4(void) { + dispatch_handler(DMA1, DMA_CH4); +} + +void __irq_dma1_channel5(void) { + dispatch_handler(DMA1, DMA_CH5); +} + +void __irq_dma1_channel6(void) { + dispatch_handler(DMA1, DMA_CH6); +} + +void __irq_dma1_channel7(void) { + dispatch_handler(DMA1, DMA_CH7); +} + +#ifdef STM32_HIGH_DENSITY +void __irq_dma2_channel1(void) { + dispatch_handler(DMA2, DMA_CH1); +} + +void __irq_dma2_channel2(void) { + dispatch_handler(DMA2, DMA_CH2); +} + +void __irq_dma2_channel3(void) { + dispatch_handler(DMA2, DMA_CH3); +} + +void __irq_dma2_channel4_5(void) { + dispatch_handler(DMA2, DMA_CH4); + dispatch_handler(DMA2, DMA_CH5); +} +#endif diff --git a/libmaple/stm32f1/include/series/dma.h b/libmaple/stm32f1/include/series/dma.h new file mode 100644 index 0000000..60582ea --- /dev/null +++ b/libmaple/stm32f1/include/series/dma.h @@ -0,0 +1,438 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Michael Hope. + * Copyright (c) 2012 LeafLabs, LLC + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/include/series/dma.h + * @author Marti Bolivar ; + * Original implementation by Michael Hope + * @brief STM32F1 Direct Memory Access header + */ + +/* + * See /notes/dma-stm32f1.txt for more information. + */ + +#ifndef _LIBMAPLE_STM32F1_DMA_H_ +#define _LIBMAPLE_STM32F1_DMA_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register map and base pointers + */ + +/** + * @brief DMA register map type. + * + * Note that DMA controller 2 (register map base pointer DMA2_BASE) + * only supports channels 1--5. + */ +typedef struct dma_reg_map { + __io uint32 ISR; /**< Interrupt status register */ + __io uint32 IFCR; /**< Interrupt flag clear register */ + __io uint32 CCR1; /**< Channel 1 configuration register */ + __io uint32 CNDTR1; /**< Channel 1 number of data register */ + __io uint32 CPAR1; /**< Channel 1 peripheral address register */ + __io uint32 CMAR1; /**< Channel 1 memory address register */ + const uint32 RESERVED1; /**< Reserved. */ + __io uint32 CCR2; /**< Channel 2 configuration register */ + __io uint32 CNDTR2; /**< Channel 2 number of data register */ + __io uint32 CPAR2; /**< Channel 2 peripheral address register */ + __io uint32 CMAR2; /**< Channel 2 memory address register */ + const uint32 RESERVED2; /**< Reserved. */ + __io uint32 CCR3; /**< Channel 3 configuration register */ + __io uint32 CNDTR3; /**< Channel 3 number of data register */ + __io uint32 CPAR3; /**< Channel 3 peripheral address register */ + __io uint32 CMAR3; /**< Channel 3 memory address register */ + const uint32 RESERVED3; /**< Reserved. */ + __io uint32 CCR4; /**< Channel 4 configuration register */ + __io uint32 CNDTR4; /**< Channel 4 number of data register */ + __io uint32 CPAR4; /**< Channel 4 peripheral address register */ + __io uint32 CMAR4; /**< Channel 4 memory address register */ + const uint32 RESERVED4; /**< Reserved. */ + __io uint32 CCR5; /**< Channel 5 configuration register */ + __io uint32 CNDTR5; /**< Channel 5 number of data register */ + __io uint32 CPAR5; /**< Channel 5 peripheral address register */ + __io uint32 CMAR5; /**< Channel 5 memory address register */ + const uint32 RESERVED5; /**< Reserved. */ + __io uint32 CCR6; /**< Channel 6 configuration register */ + __io uint32 CNDTR6; /**< Channel 6 number of data register */ + __io uint32 CPAR6; /**< Channel 6 peripheral address register */ + __io uint32 CMAR6; /**< Channel 6 memory address register */ + const uint32 RESERVED6; /**< Reserved. */ + __io uint32 CCR7; /**< Channel 7 configuration register */ + __io uint32 CNDTR7; /**< Channel 7 number of data register */ + __io uint32 CPAR7; /**< Channel 7 peripheral address register */ + __io uint32 CMAR7; /**< Channel 7 memory address register */ + const uint32 RESERVED7; /**< Reserved. */ +} dma_reg_map; + +/** DMA controller 1 register map base pointer */ +#define DMA1_BASE ((struct dma_reg_map*)0x40020000) +/** DMA controller 2 register map base pointer */ +#define DMA2_BASE ((struct dma_reg_map*)0x40020400) + +/* + * Register bit definitions + */ + +/* Interrupt status register */ + +#define DMA_ISR_TEIF7_BIT 27 +#define DMA_ISR_HTIF7_BIT 26 +#define DMA_ISR_TCIF7_BIT 25 +#define DMA_ISR_GIF7_BIT 24 +#define DMA_ISR_TEIF6_BIT 23 +#define DMA_ISR_HTIF6_BIT 22 +#define DMA_ISR_TCIF6_BIT 21 +#define DMA_ISR_GIF6_BIT 20 +#define DMA_ISR_TEIF5_BIT 19 +#define DMA_ISR_HTIF5_BIT 18 +#define DMA_ISR_TCIF5_BIT 17 +#define DMA_ISR_GIF5_BIT 16 +#define DMA_ISR_TEIF4_BIT 15 +#define DMA_ISR_HTIF4_BIT 14 +#define DMA_ISR_TCIF4_BIT 13 +#define DMA_ISR_GIF4_BIT 12 +#define DMA_ISR_TEIF3_BIT 11 +#define DMA_ISR_HTIF3_BIT 10 +#define DMA_ISR_TCIF3_BIT 9 +#define DMA_ISR_GIF3_BIT 8 +#define DMA_ISR_TEIF2_BIT 7 +#define DMA_ISR_HTIF2_BIT 6 +#define DMA_ISR_TCIF2_BIT 5 +#define DMA_ISR_GIF2_BIT 4 +#define DMA_ISR_TEIF1_BIT 3 +#define DMA_ISR_HTIF1_BIT 2 +#define DMA_ISR_TCIF1_BIT 1 +#define DMA_ISR_GIF1_BIT 0 + +#define DMA_ISR_TEIF7 (1U << DMA_ISR_TEIF7_BIT) +#define DMA_ISR_HTIF7 (1U << DMA_ISR_HTIF7_BIT) +#define DMA_ISR_TCIF7 (1U << DMA_ISR_TCIF7_BIT) +#define DMA_ISR_GIF7 (1U << DMA_ISR_GIF7_BIT) +#define DMA_ISR_TEIF6 (1U << DMA_ISR_TEIF6_BIT) +#define DMA_ISR_HTIF6 (1U << DMA_ISR_HTIF6_BIT) +#define DMA_ISR_TCIF6 (1U << DMA_ISR_TCIF6_BIT) +#define DMA_ISR_GIF6 (1U << DMA_ISR_GIF6_BIT) +#define DMA_ISR_TEIF5 (1U << DMA_ISR_TEIF5_BIT) +#define DMA_ISR_HTIF5 (1U << DMA_ISR_HTIF5_BIT) +#define DMA_ISR_TCIF5 (1U << DMA_ISR_TCIF5_BIT) +#define DMA_ISR_GIF5 (1U << DMA_ISR_GIF5_BIT) +#define DMA_ISR_TEIF4 (1U << DMA_ISR_TEIF4_BIT) +#define DMA_ISR_HTIF4 (1U << DMA_ISR_HTIF4_BIT) +#define DMA_ISR_TCIF4 (1U << DMA_ISR_TCIF4_BIT) +#define DMA_ISR_GIF4 (1U << DMA_ISR_GIF4_BIT) +#define DMA_ISR_TEIF3 (1U << DMA_ISR_TEIF3_BIT) +#define DMA_ISR_HTIF3 (1U << DMA_ISR_HTIF3_BIT) +#define DMA_ISR_TCIF3 (1U << DMA_ISR_TCIF3_BIT) +#define DMA_ISR_GIF3 (1U << DMA_ISR_GIF3_BIT) +#define DMA_ISR_TEIF2 (1U << DMA_ISR_TEIF2_BIT) +#define DMA_ISR_HTIF2 (1U << DMA_ISR_HTIF2_BIT) +#define DMA_ISR_TCIF2 (1U << DMA_ISR_TCIF2_BIT) +#define DMA_ISR_GIF2 (1U << DMA_ISR_GIF2_BIT) +#define DMA_ISR_TEIF1 (1U << DMA_ISR_TEIF1_BIT) +#define DMA_ISR_HTIF1 (1U << DMA_ISR_HTIF1_BIT) +#define DMA_ISR_TCIF1 (1U << DMA_ISR_TCIF1_BIT) +#define DMA_ISR_GIF1 (1U << DMA_ISR_GIF1_BIT) + +/* Interrupt flag clear register */ + +#define DMA_IFCR_CTEIF7_BIT 27 +#define DMA_IFCR_CHTIF7_BIT 26 +#define DMA_IFCR_CTCIF7_BIT 25 +#define DMA_IFCR_CGIF7_BIT 24 +#define DMA_IFCR_CTEIF6_BIT 23 +#define DMA_IFCR_CHTIF6_BIT 22 +#define DMA_IFCR_CTCIF6_BIT 21 +#define DMA_IFCR_CGIF6_BIT 20 +#define DMA_IFCR_CTEIF5_BIT 19 +#define DMA_IFCR_CHTIF5_BIT 18 +#define DMA_IFCR_CTCIF5_BIT 17 +#define DMA_IFCR_CGIF5_BIT 16 +#define DMA_IFCR_CTEIF4_BIT 15 +#define DMA_IFCR_CHTIF4_BIT 14 +#define DMA_IFCR_CTCIF4_BIT 13 +#define DMA_IFCR_CGIF4_BIT 12 +#define DMA_IFCR_CTEIF3_BIT 11 +#define DMA_IFCR_CHTIF3_BIT 10 +#define DMA_IFCR_CTCIF3_BIT 9 +#define DMA_IFCR_CGIF3_BIT 8 +#define DMA_IFCR_CTEIF2_BIT 7 +#define DMA_IFCR_CHTIF2_BIT 6 +#define DMA_IFCR_CTCIF2_BIT 5 +#define DMA_IFCR_CGIF2_BIT 4 +#define DMA_IFCR_CTEIF1_BIT 3 +#define DMA_IFCR_CHTIF1_BIT 2 +#define DMA_IFCR_CTCIF1_BIT 1 +#define DMA_IFCR_CGIF1_BIT 0 + +#define DMA_IFCR_CTEIF7 (1U << DMA_IFCR_CTEIF7_BIT) +#define DMA_IFCR_CHTIF7 (1U << DMA_IFCR_CHTIF7_BIT) +#define DMA_IFCR_CTCIF7 (1U << DMA_IFCR_CTCIF7_BIT) +#define DMA_IFCR_CGIF7 (1U << DMA_IFCR_CGIF7_BIT) +#define DMA_IFCR_CTEIF6 (1U << DMA_IFCR_CTEIF6_BIT) +#define DMA_IFCR_CHTIF6 (1U << DMA_IFCR_CHTIF6_BIT) +#define DMA_IFCR_CTCIF6 (1U << DMA_IFCR_CTCIF6_BIT) +#define DMA_IFCR_CGIF6 (1U << DMA_IFCR_CGIF6_BIT) +#define DMA_IFCR_CTEIF5 (1U << DMA_IFCR_CTEIF5_BIT) +#define DMA_IFCR_CHTIF5 (1U << DMA_IFCR_CHTIF5_BIT) +#define DMA_IFCR_CTCIF5 (1U << DMA_IFCR_CTCIF5_BIT) +#define DMA_IFCR_CGIF5 (1U << DMA_IFCR_CGIF5_BIT) +#define DMA_IFCR_CTEIF4 (1U << DMA_IFCR_CTEIF4_BIT) +#define DMA_IFCR_CHTIF4 (1U << DMA_IFCR_CHTIF4_BIT) +#define DMA_IFCR_CTCIF4 (1U << DMA_IFCR_CTCIF4_BIT) +#define DMA_IFCR_CGIF4 (1U << DMA_IFCR_CGIF4_BIT) +#define DMA_IFCR_CTEIF3 (1U << DMA_IFCR_CTEIF3_BIT) +#define DMA_IFCR_CHTIF3 (1U << DMA_IFCR_CHTIF3_BIT) +#define DMA_IFCR_CTCIF3 (1U << DMA_IFCR_CTCIF3_BIT) +#define DMA_IFCR_CGIF3 (1U << DMA_IFCR_CGIF3_BIT) +#define DMA_IFCR_CTEIF2 (1U << DMA_IFCR_CTEIF2_BIT) +#define DMA_IFCR_CHTIF2 (1U << DMA_IFCR_CHTIF2_BIT) +#define DMA_IFCR_CTCIF2 (1U << DMA_IFCR_CTCIF2_BIT) +#define DMA_IFCR_CGIF2 (1U << DMA_IFCR_CGIF2_BIT) +#define DMA_IFCR_CTEIF1 (1U << DMA_IFCR_CTEIF1_BIT) +#define DMA_IFCR_CHTIF1 (1U << DMA_IFCR_CHTIF1_BIT) +#define DMA_IFCR_CTCIF1 (1U << DMA_IFCR_CTCIF1_BIT) +#define DMA_IFCR_CGIF1 (1U << DMA_IFCR_CGIF1_BIT) + +/* Channel configuration register */ + +#define DMA_CCR_MEM2MEM_BIT 14 +#define DMA_CCR_MINC_BIT 7 +#define DMA_CCR_PINC_BIT 6 +#define DMA_CCR_CIRC_BIT 5 +#define DMA_CCR_DIR_BIT 4 +#define DMA_CCR_TEIE_BIT 3 +#define DMA_CCR_HTIE_BIT 2 +#define DMA_CCR_TCIE_BIT 1 +#define DMA_CCR_EN_BIT 0 + +#define DMA_CCR_MEM2MEM (1U << DMA_CCR_MEM2MEM_BIT) +#define DMA_CCR_PL (0x3 << 12) +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +#define DMA_CCR_MSIZE (0x3 << 10) +#define DMA_CCR_MSIZE_8BITS (0x0 << 10) +#define DMA_CCR_MSIZE_16BITS (0x1 << 10) +#define DMA_CCR_MSIZE_32BITS (0x2 << 10) +#define DMA_CCR_PSIZE (0x3 << 8) +#define DMA_CCR_PSIZE_8BITS (0x0 << 8) +#define DMA_CCR_PSIZE_16BITS (0x1 << 8) +#define DMA_CCR_PSIZE_32BITS (0x2 << 8) +#define DMA_CCR_MINC (1U << DMA_CCR_MINC_BIT) +#define DMA_CCR_PINC (1U << DMA_CCR_PINC_BIT) +#define DMA_CCR_CIRC (1U << DMA_CCR_CIRC_BIT) +#define DMA_CCR_DIR (1U << DMA_CCR_DIR_BIT) +#define DMA_CCR_TEIE (1U << DMA_CCR_TEIE_BIT) +#define DMA_CCR_HTIE (1U << DMA_CCR_HTIE_BIT) +#define DMA_CCR_TCIE (1U << DMA_CCR_TCIE_BIT) +#define DMA_CCR_EN (1U << DMA_CCR_EN_BIT) + +/* + * Devices + */ + +struct dma_dev; +extern struct dma_dev *DMA1; +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) +extern struct dma_dev *DMA2; +#endif + +/* + * Convenience routines. + */ + +/* This hack is due to a circular dependency between us and + * . */ +static __always_inline dma_reg_map* _dma_dev_regs(struct dma_dev*); + +/** Flags for DMA transfer configuration. */ +typedef enum dma_mode_flags { + DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ + DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ + DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ + DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ + DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ + DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ + DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ + DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ +} dma_mode_flags; + +/** Source and destination transfer sizes. */ +typedef enum dma_xfer_size { + DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ + DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ + DMA_SIZE_32BITS = 2 /**< 32-bit transfers */ +} dma_xfer_size; + +/** DMA channel */ +typedef enum dma_channel { + DMA_CH1 = 1, /**< Channel 1 */ + DMA_CH2 = 2, /**< Channel 2 */ + DMA_CH3 = 3, /**< Channel 3 */ + DMA_CH4 = 4, /**< Channel 4 */ + DMA_CH5 = 5, /**< Channel 5 */ + DMA_CH6 = 6, /**< Channel 6 */ + DMA_CH7 = 7, /**< Channel 7 */ +} dma_channel; + +void dma_setup_transfer(struct dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode); + +void dma_set_num_transfers(struct dma_dev *dev, + dma_channel channel, + uint16 num_transfers); + +/** DMA transfer priority. */ +typedef enum dma_priority { + DMA_PRIORITY_LOW = DMA_CCR_PL_LOW, /**< Low priority */ + DMA_PRIORITY_MEDIUM = DMA_CCR_PL_MEDIUM, /**< Medium priority */ + DMA_PRIORITY_HIGH = DMA_CCR_PL_HIGH, /**< High priority */ + DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */ +} dma_priority; + +void dma_set_priority(struct dma_dev *dev, + dma_channel channel, + dma_priority priority); + +void dma_attach_interrupt(struct dma_dev *dev, + dma_channel channel, + void (*handler)(void)); +void dma_detach_interrupt(struct dma_dev *dev, dma_channel channel); + +/** + * Encodes the reason why a DMA interrupt was called. + * @see dma_get_irq_cause() + */ +typedef enum dma_irq_cause { + DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ + DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ + DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ +} dma_irq_cause; + +dma_irq_cause dma_get_irq_cause(struct dma_dev *dev, dma_channel channel); + +void dma_enable(struct dma_dev *dev, dma_channel channel); +void dma_disable(struct dma_dev *dev, dma_channel channel); + +void dma_set_mem_addr(struct dma_dev *dev, + dma_channel channel, + __io void *address); +void dma_set_per_addr(struct dma_dev *dev, + dma_channel channel, + __io void *address); + +/** + * @brief DMA channel register map type. + * + * Provides access to an individual channel's registers. + */ +typedef struct dma_channel_reg_map { + __io uint32 CCR; /**< Channel configuration register */ + __io uint32 CNDTR; /**< Channel number of data register */ + __io uint32 CPAR; /**< Channel peripheral address register */ + __io uint32 CMAR; /**< Channel memory address register */ +} dma_channel_reg_map; + +#define DMA_CHANNEL_NREGS 5 + +/** + * @brief Obtain a pointer to an individual DMA channel's registers. + * + * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. + * + * @param dev DMA device + * @param channel DMA channel whose channel register map to obtain. + */ +static inline dma_channel_reg_map* dma_channel_regs(struct dma_dev *dev, + dma_channel channel) { + __io uint32 *ccr1 = &_dma_dev_regs(dev)->CCR1; + return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1)); +} + +/** + * @brief Check if a DMA channel is enabled + * @param dev DMA device + * @param channel Channel whose enabled bit to check. + */ +static inline uint8 dma_is_channel_enabled(struct dma_dev *dev, + dma_channel channel) { + return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN); +} + +/** + * @brief Get the ISR status bits for a DMA channel. + * + * The bits are returned right-aligned, in the following order: + * transfer error flag, half-transfer flag, transfer complete flag, + * global interrupt flag. + * + * If you're attempting to figure out why a DMA interrupt fired; you + * may find dma_get_irq_cause() more convenient. + * + * @param dev DMA device + * @param channel Channel whose ISR bits to return. + * @see dma_get_irq_cause(). + */ +static inline uint8 dma_get_isr_bits(struct dma_dev *dev, + dma_channel channel) { + uint8 shift = (channel - 1) * 4; + return (_dma_dev_regs(dev)->ISR >> shift) & 0xF; +} + +/** + * @brief Clear the ISR status bits for a given DMA channel. + * + * If you're attempting to clean up after yourself in a DMA interrupt, + * you may find dma_get_irq_cause() more convenient. + * + * @param dev DMA device + * @param channel Channel whose ISR bits to clear. + * @see dma_get_irq_cause() + */ +static inline void dma_clear_isr_bits(struct dma_dev *dev, + dma_channel channel) { + _dma_dev_regs(dev)->IFCR = (1U << (4 * (channel - 1))); +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 52ceea6..b67f446 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -13,6 +13,7 @@ sSRCS_$(d) += vector_table_performance.S cSRCS_$(d) := adc.c cSRCS_$(d) += bkp.c +cSRCS_$(d) += dma.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c -- cgit v1.2.3 From b600996c6a075ea7f7dca4f952a302d73329c94a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 15:19:13 -0400 Subject: STM32F1: adc: Tweaks for XL-density MCUs. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/adc.c | 4 ++-- libmaple/stm32f1/include/series/adc.h | 4 +--- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/libmaple/stm32f1/adc.c b/libmaple/stm32f1/adc.c index 8242520..bb6f8ca 100644 --- a/libmaple/stm32f1/adc.c +++ b/libmaple/stm32f1/adc.c @@ -51,7 +51,7 @@ static adc_dev adc2 = { /** ADC2 device. */ const adc_dev *ADC2 = &adc2; -#ifdef STM32_HIGH_DENSITY +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) adc_dev adc3 = { .regs = ADC3_BASE, .clk_id = RCC_ADC3 @@ -92,7 +92,7 @@ void adc_set_prescaler(adc_prescaler pre) { void adc_foreach(void (*fn)(const adc_dev*)) { fn(ADC1); fn(ADC2); -#ifdef STM32_HIGH_DENSITY +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) fn(ADC3); #endif } diff --git a/libmaple/stm32f1/include/series/adc.h b/libmaple/stm32f1/include/series/adc.h index 1798e55..45a5e9d 100644 --- a/libmaple/stm32f1/include/series/adc.h +++ b/libmaple/stm32f1/include/series/adc.h @@ -43,7 +43,7 @@ extern const struct adc_dev *ADC1; extern const struct adc_dev *ADC2; -#ifdef STM32_HIGH_DENSITY +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) extern const struct adc_dev *ADC3; #endif @@ -55,10 +55,8 @@ extern const struct adc_dev *ADC3; #define ADC1_BASE ((struct adc_reg_map*)0x40012400) /** ADC2 register map base pointer. */ #define ADC2_BASE ((struct adc_reg_map*)0x40012800) -#ifdef STM32_HIGH_DENSITY /** ADC3 register map base pointer. */ #define ADC3_BASE ((struct adc_reg_map*)0x40013C00) -#endif /* * Register bit definitions -- cgit v1.2.3 From 11ff6dcb5cec9db63db90257222cbc34276f8c3a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 15:20:02 -0400 Subject: stm32f1/adc.c: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/adc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/libmaple/stm32f1/adc.c b/libmaple/stm32f1/adc.c index bb6f8ca..06c2d30 100644 --- a/libmaple/stm32f1/adc.c +++ b/libmaple/stm32f1/adc.c @@ -27,7 +27,9 @@ /** * @file libmaple/stm32f1/include/series/adc.c - * @brief STM32F1 ADC header. + * @author Marti Bolivar , + * Perry Hung + * @brief STM32F1-specific ADC support. */ #include @@ -39,14 +41,14 @@ static adc_dev adc1 = { .regs = ADC1_BASE, - .clk_id = RCC_ADC1 + .clk_id = RCC_ADC1, }; /** ADC1 device. */ const adc_dev *ADC1 = &adc1; static adc_dev adc2 = { .regs = ADC2_BASE, - .clk_id = RCC_ADC2 + .clk_id = RCC_ADC2, }; /** ADC2 device. */ const adc_dev *ADC2 = &adc2; @@ -54,7 +56,7 @@ const adc_dev *ADC2 = &adc2; #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) adc_dev adc3 = { .regs = ADC3_BASE, - .clk_id = RCC_ADC3 + .clk_id = RCC_ADC3, }; /** ADC3 device. */ const adc_dev *ADC3 = &adc3; -- cgit v1.2.3 From 376ea4797ad88378dfae607beb7bba88634561f6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 15:21:57 -0400 Subject: stm32f1/adc.h: Add missing includes. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/adc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libmaple/stm32f1/include/series/adc.h b/libmaple/stm32f1/include/series/adc.h index 45a5e9d..007641a 100644 --- a/libmaple/stm32f1/include/series/adc.h +++ b/libmaple/stm32f1/include/series/adc.h @@ -35,6 +35,8 @@ #ifndef _LIBMAPLE_STM32F1_ADC_H_ #define _LIBMAPLE_STM32F1_ADC_H_ +#include +#include #include /* For the prescalers */ /* -- cgit v1.2.3 From 2e8c42e85f0966b9be28490be80fa1266ef109bc Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 15:32:46 -0400 Subject: libmaple/adc.h: Cosmetics. Add "extern" to mark portable interface routines that are implemented individually by each series. Move some code around. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/adc.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/libmaple/include/libmaple/adc.h b/libmaple/include/libmaple/adc.h index be29676..3cd3eb2 100644 --- a/libmaple/include/libmaple/adc.h +++ b/libmaple/include/libmaple/adc.h @@ -241,23 +241,23 @@ typedef struct adc_dev { * Routines */ +void adc_init(const adc_dev *dev); +void adc_set_extsel(const adc_dev *dev, adc_extsel_event event); +void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); +uint16 adc_read(const adc_dev *dev, uint8 channel); + /** * @brief Set the ADC prescaler. * * This determines the ADC clock for all devices. */ -void adc_set_prescaler(adc_prescaler pre); - -void adc_init(const adc_dev *dev); -void adc_set_extsel(const adc_dev *dev, adc_extsel_event event); -void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate); -uint16 adc_read(const adc_dev *dev, uint8 channel); +extern void adc_set_prescaler(adc_prescaler pre); /** * @brief Call a function on all ADC devices. * @param fn Function to call on each ADC device. */ -void adc_foreach(void (*fn)(const adc_dev*)); +extern void adc_foreach(void (*fn)(const adc_dev*)); /** * @brief Configure a GPIO pin for ADC conversion. @@ -265,7 +265,7 @@ void adc_foreach(void (*fn)(const adc_dev*)); * @param bit Bit on gdev to configure for ADC conversion. */ struct gpio_dev; -void adc_gpio_cfg(struct gpio_dev *gdev, uint8 bit); +extern void adc_gpio_cfg(struct gpio_dev *gdev, uint8 bit); /** * @brief Enable an ADC and configure it for single conversion mode. @@ -277,7 +277,7 @@ void adc_gpio_cfg(struct gpio_dev *gdev, uint8 bit); * @param dev Device to enable. * @see adc_read() */ -void adc_enable_single_swstart(const adc_dev* dev); +extern void adc_enable_single_swstart(const adc_dev* dev); /** * @brief Set the regular channel sequence length. -- cgit v1.2.3 From 12dbd700d2a2172c40909b6302caf0aa83135478 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 3 May 2012 21:47:48 -0400 Subject: Fix wrong comment in libmaple/rules.mk. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index d6efb1f..834c7a3 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -26,7 +26,7 @@ cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c -# These still need to be ported to F2: +# These still need to be brought back for F1: # cSRCS_$(d) += dac.c # cSRCS_$(d) += exti.c # cSRCS_$(d) += i2c.c -- cgit v1.2.3 From 9f41111904f8dd6691c4d3c880572b369b5fed43 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 6 May 2012 21:26:18 -0400 Subject: adc: Add missing "static" on adc_dev adc3. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/adc.c | 2 +- libmaple/stm32f2/adc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/stm32f1/adc.c b/libmaple/stm32f1/adc.c index 06c2d30..794c5c8 100644 --- a/libmaple/stm32f1/adc.c +++ b/libmaple/stm32f1/adc.c @@ -54,7 +54,7 @@ static adc_dev adc2 = { const adc_dev *ADC2 = &adc2; #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -adc_dev adc3 = { +static adc_dev adc3 = { .regs = ADC3_BASE, .clk_id = RCC_ADC3, }; diff --git a/libmaple/stm32f2/adc.c b/libmaple/stm32f2/adc.c index fbe1618..a4c227e 100644 --- a/libmaple/stm32f2/adc.c +++ b/libmaple/stm32f2/adc.c @@ -50,7 +50,7 @@ static adc_dev adc2 = { /** ADC2 device. */ const adc_dev *ADC2 = &adc2; -adc_dev adc3 = { +static adc_dev adc3 = { .regs = ADC3_BASE, .clk_id = RCC_ADC3, }; -- cgit v1.2.3 From d6ab9e92a6b9cbf077f1ce38e0ef1d3190877563 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 7 May 2012 01:53:34 -0400 Subject: libmaple/bkp.h: Tweak for STM32F1 XL-density. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/bkp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/bkp.h b/libmaple/include/libmaple/bkp.h index 7f90c0c..edc1013 100644 --- a/libmaple/include/libmaple/bkp.h +++ b/libmaple/include/libmaple/bkp.h @@ -60,7 +60,7 @@ typedef struct bkp_reg_map { __io uint32 RTCCR; ///< RTC control register __io uint32 CR; ///< Control register __io uint32 CSR; ///< Control and status register -#ifdef STM32_HIGH_DENSITY +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) const uint32 RESERVED2; ///< Reserved const uint32 RESERVED3; ///< Reserved __io uint32 DR11; ///< Data register 11 -- cgit v1.2.3 From 1cd49bc226d21cda977f81b25e507b3421a3f9dc Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:31:37 -0400 Subject: stm32f1: stm32.h: Fix wrong comment. We've got some value line values now. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 76143a0..2460b95 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -131,9 +131,6 @@ extern "C" { /* * Clock configuration. * - * We've currently got values for F103 MCUs operating at the fastest - * possible speeds. - * * You can patch these for your line, MCU, clock configuration, * etc. here or by setting cflags when compiling libmaple. */ -- cgit v1.2.3 From 4469a1380cffd8fa8a20ad1d4bbbb13cedde6941 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:39:10 -0400 Subject: stm32f1: stm32.h: Add hooks for USB access line. There are five F1 lines in total. The necessary infrastructure for USB access line (STM32F102 MCUs) support is missing, so add it. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 2460b95..bcc938b 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -47,7 +47,8 @@ extern "C" { #define STM32_F1_LINE_PERFORMANCE 0 #define STM32_F1_LINE_VALUE 1 #define STM32_F1_LINE_ACCESS 2 -#define STM32_F1_LINE_CONNECTIVITY 3 +#define STM32_F1_LINE_USB_ACCESS 3 +#define STM32_F1_LINE_CONNECTIVITY 4 /* * MCU-specific values. @@ -156,6 +157,7 @@ extern "C" { # define STM32_DELAY_US_MULT 8 /* FIXME: value is incorrect. */ # endif #elif STM32_F1_LINE == STM32_F1_LINE_ACCESS /* TODO */ +#elif STM32_F1_LINE == STM32_F1_LINE_USB_ACCESS /* TODO */ #elif STM32_F1_LINE == STM32_F1_LINE_CONNECTIVITY /* TODO */ #endif -- cgit v1.2.3 From 7ed7ff2280bd0d2a73ca2577a6da212b510c7694 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:39:47 -0400 Subject: stm32f1: stm32.h: Add Doxygen comments. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index bcc938b..d7ec2ea 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -44,10 +44,15 @@ extern "C" { * * You can use these F1 line defines if porting libmaple to support * MCUs on other lines. */ +/** STM32F1 performance line. */ #define STM32_F1_LINE_PERFORMANCE 0 +/** STM32F1 value line. */ #define STM32_F1_LINE_VALUE 1 +/** STM32F1 access line. */ #define STM32_F1_LINE_ACCESS 2 +/** STM32F1 USB access line. */ #define STM32_F1_LINE_USB_ACCESS 3 +/** STM32F1 connectivity line. */ #define STM32_F1_LINE_CONNECTIVITY 4 /* @@ -166,6 +171,23 @@ extern "C" { #error "Bad STM32F1 configuration. Check STM32F1 header." #endif +/* + * Doxygen + */ + +#ifdef __DOXYGEN_PREDEFINED_HACK + +/** + * @brief STM32 line value for the STM32F1 MCU being targeted. + * + * At time of writing, allowed values are: STM32_F1_LINE_PERFORMANCE, + * STM32_F1_LINE_VALUE. This set of values may expand as libmaple adds + * support for more STM32F1 lines. + */ +#define STM32_F1_LINE + +#endif /* __DOXYGEN_PREDEFINED_HACK */ + #ifdef __cplusplus } #endif -- cgit v1.2.3 From d03ab7f8cfbf02ba68cfe1e3c28cfa6b37c3a8c6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:40:46 -0400 Subject: stm32f1: stm32.h: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index d7ec2ea..60af6b5 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -78,9 +78,9 @@ extern "C" { #elif defined(MCU_STM32F103CB) # define STM32_F1_LINE STM32_F1_LINE_PERFORMANCE - /* This STM32_NR_GPIO_PORTS is not strictly true, but only pins 0 - * and exist, and they're used for OSC (e.g. on e.g. LeafLabs - * Maple Mini), so we'll live with this for now. */ + /* This STM32_NR_GPIO_PORTS is not true, but only pins 0 and + * exist, and they're used for OSC (e.g. on LeafLabs' Maple Mini), + * so we'll live with this for now. */ # define STM32_NR_GPIO_PORTS 3 # define STM32_SRAM_END ((void*)0x20005000) # define STM32_MEDIUM_DENSITY @@ -166,7 +166,13 @@ extern "C" { #elif STM32_F1_LINE == STM32_F1_LINE_CONNECTIVITY /* TODO */ #endif -/* Make sure we have the F1-specific defines we need. */ +/* + * Sanity checks. + * + * Make sure we have the F1-specific defines we need. + * will check that we've defined everything it needs. + */ + #if !defined(STM32_F1_LINE) #error "Bad STM32F1 configuration. Check STM32F1 header." #endif -- cgit v1.2.3 From 786138dc6f95db06baa56b97333264435c8f47db Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:41:03 -0400 Subject: libmaple/stm32.h: Doxygen. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 80d0777..6b8e905 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -145,6 +145,23 @@ extern "C" { */ #define STM32_SRAM_END +/** + * @brief 1 if the target MCU has the FSMC peripheral, and 0 otherwise. + * + * Note that the feature set of the FSMC peripheral is restricted on + * some MCUs. + */ +#define STM32_HAVE_FSMC + +/** + * @brief 1 if the target MCU has a USB peripheral, and 0 otherwise. + * + * Note that a variety of USB peripherals are available across the + * different series, with widely varying feature sets and programming + * interfaces. This macro will be 1 if any such peripheral is present. + */ +#define STM32_HAVE_USB + #endif /* __DOXYGEN_PREDEFINED_HACK */ /* -- cgit v1.2.3 From edf892e454c644b258cb14ad8a0d3a52f00a4505 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:44:55 -0400 Subject: stm32f1: stm32.h: Doxygen. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 60af6b5..6bf836c 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -44,15 +44,15 @@ extern "C" { * * You can use these F1 line defines if porting libmaple to support * MCUs on other lines. */ -/** STM32F1 performance line. */ +/** STM32F1 performance line (STM32F103 MCUs). */ #define STM32_F1_LINE_PERFORMANCE 0 -/** STM32F1 value line. */ +/** STM32F1 value line (STM32F100 MCUs). */ #define STM32_F1_LINE_VALUE 1 -/** STM32F1 access line. */ +/** STM32F1 access line (STM32F101 MCUs). */ #define STM32_F1_LINE_ACCESS 2 -/** STM32F1 USB access line. */ +/** STM32F1 USB access line (STM32F102 MCUs). */ #define STM32_F1_LINE_USB_ACCESS 3 -/** STM32F1 connectivity line. */ +/** STM32F1 connectivity line (STM32F105/F107 MCUs). */ #define STM32_F1_LINE_CONNECTIVITY 4 /* -- cgit v1.2.3 From 9d27584cb1bd59fa1063651d413feefdcc22d661 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 11:47:50 -0400 Subject: stm32f1: stm32.h: Tweak STM32_F1_LINE_xxx for mnemonic value. Change the values of the STM32_F1_LINE_xxx macros to match the part number better (so performance line, or F103s, now have STM32_F1_LINE_PERFORMANCE==3, F100s have STM32_F1_LINE_VALUE==0, etc.). This will hopefully make debugging or error checking easier for someone at some point. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 6bf836c..999abab 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -44,16 +44,16 @@ extern "C" { * * You can use these F1 line defines if porting libmaple to support * MCUs on other lines. */ -/** STM32F1 performance line (STM32F103 MCUs). */ -#define STM32_F1_LINE_PERFORMANCE 0 /** STM32F1 value line (STM32F100 MCUs). */ -#define STM32_F1_LINE_VALUE 1 +#define STM32_F1_LINE_VALUE 0 /** STM32F1 access line (STM32F101 MCUs). */ -#define STM32_F1_LINE_ACCESS 2 +#define STM32_F1_LINE_ACCESS 1 /** STM32F1 USB access line (STM32F102 MCUs). */ -#define STM32_F1_LINE_USB_ACCESS 3 +#define STM32_F1_LINE_USB_ACCESS 2 +/** STM32F1 performance line (STM32F103 MCUs). */ +#define STM32_F1_LINE_PERFORMANCE 3 /** STM32F1 connectivity line (STM32F105/F107 MCUs). */ -#define STM32_F1_LINE_CONNECTIVITY 4 +#define STM32_F1_LINE_CONNECTIVITY 5 /* * MCU-specific values. -- cgit v1.2.3 From 84c4bc02c57f40996f4000b3b87ee47179759ca5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 13:10:00 -0400 Subject: ring_buffer.h: Fix Doxygen @file. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/ring_buffer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/ring_buffer.h b/libmaple/include/libmaple/ring_buffer.h index 7169e7e..e02e6e7 100644 --- a/libmaple/include/libmaple/ring_buffer.h +++ b/libmaple/include/libmaple/ring_buffer.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file ring_buffer.h + * @file libmaple/include/libmaple/ring_buffer.h * @brief Simple circular buffer * * This implementation is not thread-safe. In particular, none of -- cgit v1.2.3 From f1be82306a02df38992817e0a57609df7171e4c5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 14:19:01 -0400 Subject: libmaple/util.h: Doxygen fixups. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/util.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/util.h b/libmaple/include/libmaple/util.h index d0b7b0b..78bc03d 100644 --- a/libmaple/include/libmaple/util.h +++ b/libmaple/include/libmaple/util.h @@ -42,13 +42,13 @@ extern "C"{ * Bit manipulation */ -/** 1 << the bit number */ +/** 1UL << (shift) */ #define BIT(shift) (1UL << (shift)) -/** Mask shifted left by 'shift' */ +/** 'Mask' shifted left by 'shift' */ #define BIT_MASK_SHIFT(mask, shift) ((mask) << (shift)) /** Bits m to n of x */ #define GET_BITS(x, m, n) ((((uint32)x) << (31 - (n))) >> ((31 - (n)) + (m))) -/** True if v is a power of two (1, 2, 4, 8, ...) */ +/** True iff v is a power of two (1, 2, 4, 8, ...) */ #define IS_POWER_OF_TWO(v) ((v) && !((v) & ((v) - 1))) /* -- cgit v1.2.3 From 4af77d8a765061c23ff517a807852060892838ab Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 15:04:53 -0400 Subject: libmaple/flash.h: Fix Doxygen @file Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index bacbbda..d3810a7 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/flash.h + * @file libmaple/include/libmaple/flash.h * @brief Flash support. */ -- cgit v1.2.3 From b5c11895b59fbfdc6dda9d26e02df053f8035ff2 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:22:41 -0400 Subject: Fix a bunch of Doxygen file-level comments. Fix @file in many places. Also fix up the descriptions where it's appropriate. This standardizes the @file formatting across the library to explicitly include any parent directories up to the repository root. Besides being nice, this will hopefully let us manage Doxygen's XML output so as to make extracting series-specific pieces via Breathe in the leaflabs-docs repo possible. Signed-off-by: Marti Bolivar --- examples/test-usart-dma.cpp | 2 +- libmaple/dac.c | 2 +- libmaple/exti.c | 2 +- libmaple/gpio.c | 2 +- libmaple/i2c.c | 2 +- libmaple/include/libmaple/adc.h | 2 +- libmaple/include/libmaple/bitband.h | 2 +- libmaple/include/libmaple/bkp.h | 2 +- libmaple/include/libmaple/dac.h | 2 +- libmaple/include/libmaple/delay.h | 2 +- libmaple/include/libmaple/exti.h | 2 +- libmaple/include/libmaple/fsmc.h | 2 +- libmaple/include/libmaple/gpio.h | 2 +- libmaple/include/libmaple/i2c.h | 2 +- libmaple/include/libmaple/iwdg.h | 2 +- libmaple/include/libmaple/libmaple.h | 2 +- libmaple/include/libmaple/libmaple_types.h | 2 +- libmaple/include/libmaple/nvic.h | 2 +- libmaple/include/libmaple/pwr.h | 4 ++-- libmaple/include/libmaple/rcc.h | 2 +- libmaple/include/libmaple/scb.h | 2 +- libmaple/include/libmaple/spi.h | 2 +- libmaple/include/libmaple/systick.h | 3 +-- libmaple/include/libmaple/timer.h | 2 +- libmaple/include/libmaple/usart.h | 2 +- libmaple/include/libmaple/usb_cdcacm.h | 2 +- libmaple/include/libmaple/util.h | 2 +- libmaple/iwdg.c | 2 +- libmaple/nvic.c | 2 +- libmaple/pwr.c | 2 +- libmaple/stm32f1/adc.c | 4 ++-- libmaple/stm32f1/bkp.c | 4 ++-- libmaple/stm32f1/fsmc.c | 2 +- libmaple/stm32f1/gpio.c | 2 +- libmaple/stm32f1/include/series/adc.h | 2 +- libmaple/stm32f1/include/series/flash.h | 2 +- libmaple/stm32f1/include/series/gpio.h | 8 +++++--- libmaple/stm32f1/include/series/pwr.h | 2 +- libmaple/stm32f1/include/series/rcc.h | 4 ++-- libmaple/stm32f1/include/series/stm32.h | 2 +- libmaple/stm32f1/include/series/timer.h | 4 ++-- libmaple/stm32f1/include/series/usart.h | 4 ++-- libmaple/stm32f1/rcc.c | 2 +- libmaple/stm32f1/spi.c | 2 +- libmaple/stm32f1/timer.c | 2 +- libmaple/stm32f1/usart.c | 2 +- libmaple/stm32f2/adc.c | 4 ++-- libmaple/stm32f2/fsmc.c | 2 +- libmaple/stm32f2/gpio.c | 2 +- libmaple/stm32f2/include/series/adc.h | 4 ++-- libmaple/stm32f2/include/series/flash.h | 2 +- libmaple/stm32f2/include/series/gpio.h | 4 ++-- libmaple/stm32f2/include/series/pwr.h | 2 +- libmaple/stm32f2/include/series/rcc.h | 2 +- libmaple/stm32f2/include/series/stm32.h | 2 +- libmaple/stm32f2/include/series/timer.h | 4 ++-- libmaple/stm32f2/include/series/usart.h | 4 ++-- libmaple/stm32f2/rcc.c | 2 +- libmaple/stm32f2/timer.c | 2 +- libmaple/stm32f2/usart.c | 2 +- libmaple/syscalls.c | 8 +++++--- libmaple/systick.c | 4 ++-- libmaple/usart.c | 4 ++-- libmaple/usb/usb.c | 4 +++- libmaple/usb/usb_cdcacm.c | 8 +++++--- libmaple/util.c | 2 +- wirish/HardwareSerial.cpp | 2 +- wirish/boards.cpp | 2 +- wirish/ext_interrupts.cpp | 5 ++--- wirish/include/wirish/HardwareSPI.h | 2 +- wirish/include/wirish/HardwareSerial.h | 2 +- wirish/include/wirish/boards.h | 4 ++-- wirish/include/wirish/ext_interrupts.h | 5 ++--- wirish/include/wirish/io.h | 5 ++--- wirish/include/wirish/pwm.h | 5 ++--- wirish/include/wirish/wirish_debug.h | 2 +- wirish/include/wirish/wirish_math.h | 4 ++-- wirish/include/wirish/wirish_time.h | 2 +- wirish/include/wirish/wirish_types.h | 2 +- 79 files changed, 112 insertions(+), 109 deletions(-) diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index 8fbcccb..10ebe8b 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -1,5 +1,5 @@ /** - * @file test-usart-dma.cpp + * @file examples/test-usart-dma.cpp * @author Marti Bolivar * * Simple test of DMA used with a USART receiver. diff --git a/libmaple/dac.c b/libmaple/dac.c index efcba15..f630ac0 100644 --- a/libmaple/dac.c +++ b/libmaple/dac.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file dac.c + * @file libmaple/dac.c * @brief Digital to analog converter support. */ diff --git a/libmaple/exti.c b/libmaple/exti.c index 00e0df2..248c4b6 100644 --- a/libmaple/exti.c +++ b/libmaple/exti.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file exti.c + * @file libmaple/exti.c * @brief External interrupt control routines */ diff --git a/libmaple/gpio.c b/libmaple/gpio.c index 64b2d54..898007a 100644 --- a/libmaple/gpio.c +++ b/libmaple/gpio.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file gpio.c + * @file libmaple/gpio.c * @brief Generic STM32 GPIO support. */ diff --git a/libmaple/i2c.c b/libmaple/i2c.c index ae44532..3eca22a 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file i2c.c + * @file libmaple/i2c.c * @brief Inter-Integrated Circuit (I2C) support. * * Currently, only master mode is supported. diff --git a/libmaple/include/libmaple/adc.h b/libmaple/include/libmaple/adc.h index 3cd3eb2..8d2f398 100644 --- a/libmaple/include/libmaple/adc.h +++ b/libmaple/include/libmaple/adc.h @@ -26,7 +26,7 @@ *****************************************************************************/ /** - * @file libmaple/adc.h + * @file libmaple/include/libmaple/adc.h * @author Marti Bolivar , * Perry Hung * @brief Analog-to-Digital Conversion (ADC) header. diff --git a/libmaple/include/libmaple/bitband.h b/libmaple/include/libmaple/bitband.h index 607e4eb..0980311 100644 --- a/libmaple/include/libmaple/bitband.h +++ b/libmaple/include/libmaple/bitband.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file bitband.h + * @file libmaple/include/libmaple/bitband.h * * @brief Bit-banding utility functions */ diff --git a/libmaple/include/libmaple/bkp.h b/libmaple/include/libmaple/bkp.h index edc1013..bb63a2f 100644 --- a/libmaple/include/libmaple/bkp.h +++ b/libmaple/include/libmaple/bkp.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file bkp.h + * @file libmaple/include/libmaple/bkp.h * @brief Backup register support (STM32F1 only). */ diff --git a/libmaple/include/libmaple/dac.h b/libmaple/include/libmaple/dac.h index 9bd74b4..047f874 100644 --- a/libmaple/include/libmaple/dac.h +++ b/libmaple/include/libmaple/dac.h @@ -26,7 +26,7 @@ *****************************************************************************/ /** - * @file libmaple/dac.h + * @file libmaple/include/libmaple/dac.h * @brief Digital to analog converter support. */ diff --git a/libmaple/include/libmaple/delay.h b/libmaple/include/libmaple/delay.h index f79655d..472a208 100644 --- a/libmaple/include/libmaple/delay.h +++ b/libmaple/include/libmaple/delay.h @@ -26,7 +26,7 @@ *****************************************************************************/ /** - * @file delay.h + * @file libmaple/include/libmaple/delay.h * @brief Delay implementation */ diff --git a/libmaple/include/libmaple/exti.h b/libmaple/include/libmaple/exti.h index 0a763d7..d7bfe51 100644 --- a/libmaple/include/libmaple/exti.h +++ b/libmaple/include/libmaple/exti.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file exti.h + * @file libmaple/include/libmaple/exti.h * @brief External interrupt control prototypes and defines */ diff --git a/libmaple/include/libmaple/fsmc.h b/libmaple/include/libmaple/fsmc.h index df211b2..01a6a3b 100644 --- a/libmaple/include/libmaple/fsmc.h +++ b/libmaple/include/libmaple/fsmc.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file fsmc.h + * @file libmaple/include/libmaple/fsmc.h * @brief Flexible static memory controller support. */ diff --git a/libmaple/include/libmaple/gpio.h b/libmaple/include/libmaple/gpio.h index 609320f..f7773c0 100644 --- a/libmaple/include/libmaple/gpio.h +++ b/libmaple/include/libmaple/gpio.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file gpio.h + * @file libmaple/include/libmaple/gpio.h * @brief General Purpose I/O (GPIO) interace. */ diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 8a1485e..ffd0cfb 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file i2c.h + * @file libmaple/include/libmaple/i2c.h * @brief Inter-Integrated Circuit (I2C) peripheral support */ diff --git a/libmaple/include/libmaple/iwdg.h b/libmaple/include/libmaple/iwdg.h index 80202d2..0aef8fd 100644 --- a/libmaple/include/libmaple/iwdg.h +++ b/libmaple/include/libmaple/iwdg.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/iwdg.h + * @file libmaple/include/libmaple/iwdg.h * @author Michael Hope, Marti Bolivar * @brief Independent watchdog support. * diff --git a/libmaple/include/libmaple/libmaple.h b/libmaple/include/libmaple/libmaple.h index 60b23ed..f1a595e 100644 --- a/libmaple/include/libmaple/libmaple.h +++ b/libmaple/include/libmaple/libmaple.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple.h + * @file libmaple/include/libmaple/libmaple.h * @brief General include file for libmaple */ diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h index 0a83795..0c22792 100644 --- a/libmaple/include/libmaple/libmaple_types.h +++ b/libmaple/include/libmaple/libmaple_types.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple_types.h + * @file libmaple/include/libmaple/libmaple_types.h * * @brief libmaple's types, and operations on types. */ diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h index 1a1a4ed..86ac1cb 100644 --- a/libmaple/include/libmaple/nvic.h +++ b/libmaple/include/libmaple/nvic.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file nvic.h + * @file libmaple/include/libmaple/nvic.h * @brief Nested vectored interrupt controller support. * * Basic usage: diff --git a/libmaple/include/libmaple/pwr.h b/libmaple/include/libmaple/pwr.h index 2611587..e4b5b0d 100644 --- a/libmaple/include/libmaple/pwr.h +++ b/libmaple/include/libmaple/pwr.h @@ -25,8 +25,8 @@ *****************************************************************************/ /** - * @file pwr.h - * @brief Power control (PWR) defines. + * @file libmaple/include/libmaple/pwr.h + * @brief Power control (PWR). */ #ifndef _LIBMAPLE_PWR_H_ diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index b04f016..7c23f1b 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/rcc.h + * @file libmaple/include/libmaple/rcc.h * @brief Reset and Clock Control (RCC) interface. */ diff --git a/libmaple/include/libmaple/scb.h b/libmaple/include/libmaple/scb.h index 9c4ee15..1c7c5d7 100644 --- a/libmaple/include/libmaple/scb.h +++ b/libmaple/include/libmaple/scb.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file scb.h + * @file libmaple/include/libmaple/scb.h * @brief System control block header */ diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h index 5b045a9..3805b2e 100644 --- a/libmaple/include/libmaple/spi.h +++ b/libmaple/include/libmaple/spi.h @@ -26,7 +26,7 @@ *****************************************************************************/ /** - * @file libmaple/spi.h + * @file libmaple/include/libmaple/spi.h * @author Marti Bolivar * @brief Serial Peripheral Interface (SPI) and Integrated * Interchip Sound (I2S) peripheral support. diff --git a/libmaple/include/libmaple/systick.h b/libmaple/include/libmaple/systick.h index 1731c85..551f800 100644 --- a/libmaple/include/libmaple/systick.h +++ b/libmaple/include/libmaple/systick.h @@ -25,8 +25,7 @@ *****************************************************************************/ /** - * @file systick.h - * + * @file libmaple/include/libmaple/systick.h * @brief System timer definitions */ diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index 0a34066..887b7eb 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/timer.h + * @file libmaple/include/libmaple/timer.h * @author Marti Bolivar * @brief Timer interface. */ diff --git a/libmaple/include/libmaple/usart.h b/libmaple/include/libmaple/usart.h index 42f9576..ad7eb51 100644 --- a/libmaple/include/libmaple/usart.h +++ b/libmaple/include/libmaple/usart.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file usart.h + * @file libmaple/include/libmaple/usart.h * @author Marti Bolivar , * Perry Hung * @brief USART definitions and prototypes diff --git a/libmaple/include/libmaple/usb_cdcacm.h b/libmaple/include/libmaple/usb_cdcacm.h index 2dbcbea..9d70758 100644 --- a/libmaple/include/libmaple/usb_cdcacm.h +++ b/libmaple/include/libmaple/usb_cdcacm.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file usb_cdcacm.h + * @file libmaple/include/libmaple/usb_cdcacm.h * @brief USB CDC ACM (virtual serial terminal) support */ diff --git a/libmaple/include/libmaple/util.h b/libmaple/include/libmaple/util.h index 78bc03d..60ca0d3 100644 --- a/libmaple/include/libmaple/util.h +++ b/libmaple/include/libmaple/util.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file util.h + * @file libmaple/include/libmaple/util.h * @brief Miscellaneous utility macros and procedures. */ diff --git a/libmaple/iwdg.c b/libmaple/iwdg.c index 6dd77fc..2456235 100644 --- a/libmaple/iwdg.c +++ b/libmaple/iwdg.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file iwdg.c + * @file libmaple/iwdg.c * @brief Independent watchdog (IWDG) support */ diff --git a/libmaple/nvic.c b/libmaple/nvic.c index e3f79a3..fe7c7bc 100644 --- a/libmaple/nvic.c +++ b/libmaple/nvic.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file nvic.c + * @file libmaple/nvic.c * @brief Nested vector interrupt controller support. */ diff --git a/libmaple/pwr.c b/libmaple/pwr.c index f934269..3cf170f 100644 --- a/libmaple/pwr.c +++ b/libmaple/pwr.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file pwr.c + * @file libmaple/pwr.c * @brief Power control (PWR) support. */ diff --git a/libmaple/stm32f1/adc.c b/libmaple/stm32f1/adc.c index 794c5c8..facc6bd 100644 --- a/libmaple/stm32f1/adc.c +++ b/libmaple/stm32f1/adc.c @@ -26,10 +26,10 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/include/series/adc.c + * @file libmaple/stm32f1/adc.c * @author Marti Bolivar , * Perry Hung - * @brief STM32F1-specific ADC support. + * @brief STM32F1 ADC support. */ #include diff --git a/libmaple/stm32f1/bkp.c b/libmaple/stm32f1/bkp.c index 62783e7..f435ff1 100644 --- a/libmaple/stm32f1/bkp.c +++ b/libmaple/stm32f1/bkp.c @@ -25,8 +25,8 @@ *****************************************************************************/ /** - * @file bkp.c - * @brief Backup register support. + * @file libmaple/stm32f1/bkp.c + * @brief STM32F1 Backup register support. */ #include diff --git a/libmaple/stm32f1/fsmc.c b/libmaple/stm32f1/fsmc.c index 8e01b5e..210f0be 100644 --- a/libmaple/stm32f1/fsmc.c +++ b/libmaple/stm32f1/fsmc.c @@ -26,7 +26,7 @@ *****************************************************************************/ /** - * @file stm32f1/fsmc.c + * @file libmaple/stm32f1/fsmc.c * @author Marti Bolivar , * Bryan Newbold * @brief STM32F1 FSMC support. diff --git a/libmaple/stm32f1/gpio.c b/libmaple/stm32f1/gpio.c index 01a4028..2cbe299 100644 --- a/libmaple/stm32f1/gpio.c +++ b/libmaple/stm32f1/gpio.c @@ -26,7 +26,7 @@ /** * @file libmaple/stm32f1/gpio.c - * @brief GPIO support for STM32F1 line. + * @brief STM32F1 GPIO support. */ #include diff --git a/libmaple/stm32f1/include/series/adc.h b/libmaple/stm32f1/include/series/adc.h index 007641a..774c97c 100644 --- a/libmaple/stm32f1/include/series/adc.h +++ b/libmaple/stm32f1/include/series/adc.h @@ -26,7 +26,7 @@ *****************************************************************************/ /** - * @file stm32f1/include/series/adc.h + * @file libmaple/stm32f1/include/series/adc.h * @author Marti Bolivar , * Perry Hung * @brief STM32F1 ADC header. diff --git a/libmaple/stm32f1/include/series/flash.h b/libmaple/stm32f1/include/series/flash.h index 5603176..0c70986 100644 --- a/libmaple/stm32f1/include/series/flash.h +++ b/libmaple/stm32f1/include/series/flash.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/flash.h + * @file libmaple/stm32f1/include/series/flash.h * @brief STM32F1 Flash header. * * Provides register map, base pointer, and register bit definitions diff --git a/libmaple/stm32f1/include/series/gpio.h b/libmaple/stm32f1/include/series/gpio.h index c10244d..1f209fe 100644 --- a/libmaple/stm32f1/include/series/gpio.h +++ b/libmaple/stm32f1/include/series/gpio.h @@ -26,9 +26,11 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/gpio.h - * @brief General purpose I/O (GPIO) and Alternate Function I/O - * (AFIO) prototypes, defines, and inlined access functions. + * @file libmaple/stm32f1/include/series/gpio.h + * @brief STM32F1 GPIO support. + * + * General purpose I/O (GPIO) and Alternate Function I/O (AFIO) + * prototypes, defines, and support functions. */ #ifndef _LIBMAPLE_STM32F1_GPIO_H_ diff --git a/libmaple/stm32f1/include/series/pwr.h b/libmaple/stm32f1/include/series/pwr.h index d13ffa7..e143a8c 100644 --- a/libmaple/stm32f1/include/series/pwr.h +++ b/libmaple/stm32f1/include/series/pwr.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file stm32f1/pwr.h + * @file libmaple/stm32f1/include/series/pwr.h * @author Marti Bolivar * @brief STM32F1 Power control (PWR) support. */ diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index f60b07b..3e7f7c6 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -26,8 +26,8 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/rcc.h - * @brief STM32F1 reset and clock control (RCC) header. + * @file libmaple/stm32f1/include/series/rcc.h + * @brief STM32F1 reset and clock control (RCC) support. */ #ifndef _LIBMAPLE_STM32F1_RCC_H_ diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 999abab..e6d3b19 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/stm32.h + * @file libmaple/stm32f1/include/series/stm32.h * @brief STM32F1 chip- and series-specific definitions. */ diff --git a/libmaple/stm32f1/include/series/timer.h b/libmaple/stm32f1/include/series/timer.h index 2551f70..8a64ffa 100644 --- a/libmaple/stm32f1/include/series/timer.h +++ b/libmaple/stm32f1/include/series/timer.h @@ -25,9 +25,9 @@ *****************************************************************************/ /** - * @file stm32f1/include/series/timer.h + * @file libmaple/stm32f1/include/series/timer.h * @author Marti Bolivar - * @brief STM32F1 timer sub-header. + * @brief STM32F1 timer support. */ #ifndef _LIBMAPLE_STM32F1_TIMER_H_ diff --git a/libmaple/stm32f1/include/series/usart.h b/libmaple/stm32f1/include/series/usart.h index 93a7728..d12a3e2 100644 --- a/libmaple/stm32f1/include/series/usart.h +++ b/libmaple/stm32f1/include/series/usart.h @@ -25,9 +25,9 @@ *****************************************************************************/ /** - * @file libmaple/stm32f1/usart.h + * @file libmaple/stm32f1/include/series/usart.h * @author Marti Bolivar - * @brief STM32F1 USART header. + * @brief STM32F1 USART support. */ #ifndef _LIBMAPLE_STM32F1_USART_H_ diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index aeedf66..ca81755 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -27,7 +27,7 @@ /** * @file libmaple/stm32f1/rcc.c - * @brief STM32F1 RCC routines. + * @brief STM32F1 RCC. */ #include diff --git a/libmaple/stm32f1/spi.c b/libmaple/stm32f1/spi.c index 45ff354..8b6e495 100644 --- a/libmaple/stm32f1/spi.c +++ b/libmaple/stm32f1/spi.c @@ -28,7 +28,7 @@ /** * @file libmaple/stm32f1/spi.c * @author Marti Bolivar - * @brief STM32F1 SPI/I2S support. + * @brief STM32F1 SPI/I2S. */ #include diff --git a/libmaple/stm32f1/timer.c b/libmaple/stm32f1/timer.c index 899abbc..002b9d6 100644 --- a/libmaple/stm32f1/timer.c +++ b/libmaple/stm32f1/timer.c @@ -27,7 +27,7 @@ /** * @file libmaple/stm32f1/timer.c * @author Marti Bolivar - * @brief STM32F1 timer support. + * @brief STM32F1 timer. */ /* Notes: diff --git a/libmaple/stm32f1/usart.c b/libmaple/stm32f1/usart.c index ee68082..eed420e 100644 --- a/libmaple/stm32f1/usart.c +++ b/libmaple/stm32f1/usart.c @@ -29,7 +29,7 @@ * @file libmaple/stm32f1/usart.c * @author Marti Bolivar , * Perry Hung - * @brief STM32F1 USART support. + * @brief STM32F1 USART. */ #include diff --git a/libmaple/stm32f2/adc.c b/libmaple/stm32f2/adc.c index a4c227e..0380736 100644 --- a/libmaple/stm32f2/adc.c +++ b/libmaple/stm32f2/adc.c @@ -25,8 +25,8 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/include/series/adc.c - * @brief STM32F2 ADC header. + * @file libmaple/stm32f2/adc.c + * @brief STM32F2 ADC. */ #include diff --git a/libmaple/stm32f2/fsmc.c b/libmaple/stm32f2/fsmc.c index 9b23eea..7f49cd8 100644 --- a/libmaple/stm32f2/fsmc.c +++ b/libmaple/stm32f2/fsmc.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file stm32f2/fsmc.c + * @file libmaple/stm32f2/fsmc.c * @author Marti Bolivar , * @brief STM32F2 FSMC support. */ diff --git a/libmaple/stm32f2/gpio.c b/libmaple/stm32f2/gpio.c index e441fbc..7479922 100644 --- a/libmaple/stm32f2/gpio.c +++ b/libmaple/stm32f2/gpio.c @@ -26,7 +26,7 @@ /** * @file libmaple/stm32f2/gpio.c - * @brief GPIO support for STM32F2 line. + * @brief STM32F2 GPIO. */ #include diff --git a/libmaple/stm32f2/include/series/adc.h b/libmaple/stm32f2/include/series/adc.h index 4f0cd6b..714179c 100644 --- a/libmaple/stm32f2/include/series/adc.h +++ b/libmaple/stm32f2/include/series/adc.h @@ -25,9 +25,9 @@ *****************************************************************************/ /** - * @file stm32f2/include/series/adc.h + * @file libmaple/stm32f2/include/series/adc.h * @author Marti Bolivar , - * @brief STM32F2 ADC header. + * @brief STM32F2 ADC support. */ #ifndef _LIBMAPLE_STM32F2_ADC_H_ diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h index f48eea3..cfc6e6b 100644 --- a/libmaple/stm32f2/include/series/flash.h +++ b/libmaple/stm32f2/include/series/flash.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/flash.h + * @file libmaple/stm32f2/include/series/flash.h * @brief STM32F2 Flash header. * * Provides register map, base pointer, and register bit definitions diff --git a/libmaple/stm32f2/include/series/gpio.h b/libmaple/stm32f2/include/series/gpio.h index 40c7292..9687247 100644 --- a/libmaple/stm32f2/include/series/gpio.h +++ b/libmaple/stm32f2/include/series/gpio.h @@ -25,8 +25,8 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/gpio.h - * @brief STM32F2 General Purpose I/O (GPIO) header. + * @file libmaple/stm32f2/include/series/gpio.h + * @brief STM32F2 GPIO support. */ #ifndef _LIBMAPLE_STM32F2_GPIO_H_ diff --git a/libmaple/stm32f2/include/series/pwr.h b/libmaple/stm32f2/include/series/pwr.h index dec2d76..96353a4 100644 --- a/libmaple/stm32f2/include/series/pwr.h +++ b/libmaple/stm32f2/include/series/pwr.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file stm32f2/pwr.h + * @file libmaple/stm32f2/include/series/pwr.h * @author Marti Bolivar * @brief STM32F2 Power control (PWR) support. */ diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index d797ba9..9c3fdd5 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -26,7 +26,7 @@ /** * @file libmaple/stm32f2/include/series/rcc.h - * @brief STM32F2 reset and clock control (RCC) header. + * @brief STM32F2 reset and clock control (RCC) support. */ /* diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 5ab4c56..9e88a70 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/stm32.h + * @file libmaple/stm32f2/include/series/stm32.h * @brief STM32F2 chip- and series-specific definitions. */ diff --git a/libmaple/stm32f2/include/series/timer.h b/libmaple/stm32f2/include/series/timer.h index cf7cc15..0d959d0 100644 --- a/libmaple/stm32f2/include/series/timer.h +++ b/libmaple/stm32f2/include/series/timer.h @@ -25,9 +25,9 @@ *****************************************************************************/ /** - * @file stm32f2/include/series/timer.h + * @file libmaple/stm32f2/include/series/timer.h * @author Marti Bolivar - * @brief STM32F2 timer sub-header. + * @brief STM32F2 timer support. */ #ifndef _LIBMAPLE_STM32F2_TIMER_H_ diff --git a/libmaple/stm32f2/include/series/usart.h b/libmaple/stm32f2/include/series/usart.h index 9b18b9c..805a2b2 100644 --- a/libmaple/stm32f2/include/series/usart.h +++ b/libmaple/stm32f2/include/series/usart.h @@ -25,9 +25,9 @@ *****************************************************************************/ /** - * @file libmaple/stm32f2/usart.h + * @file libmaple/stm32f2/include/series/usart.h * @author Marti Bolivar - * @brief STM32F2 USART header. + * @brief STM32F2 USART support. */ #ifndef _LIBMAPLE_STM32F2_USART_H_ diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c index 8a91f30..a13e56d 100644 --- a/libmaple/stm32f2/rcc.c +++ b/libmaple/stm32f2/rcc.c @@ -26,7 +26,7 @@ /** * @file libmaple/stm32f2/rcc.c - * @brief STM32F2 RCC routines. + * @brief STM32F2 RCC. */ #include diff --git a/libmaple/stm32f2/timer.c b/libmaple/stm32f2/timer.c index eed7810..3f9a8d2 100644 --- a/libmaple/stm32f2/timer.c +++ b/libmaple/stm32f2/timer.c @@ -27,7 +27,7 @@ /** * @file libmaple/stm32f2/timer.c * @author Marti Bolivar - * @brief STM32F2 timer support. + * @brief STM32F2 timers. */ #include diff --git a/libmaple/stm32f2/usart.c b/libmaple/stm32f2/usart.c index 364558c..e4fc9b1 100644 --- a/libmaple/stm32f2/usart.c +++ b/libmaple/stm32f2/usart.c @@ -27,7 +27,7 @@ /** * @file libmaple/stm32f2/usart.c * @author Marti Bolivar - * @brief STM32F2 USART support. + * @brief STM32F2 USART. */ #include diff --git a/libmaple/syscalls.c b/libmaple/syscalls.c index 86fd8e6..30a63bf 100644 --- a/libmaple/syscalls.c +++ b/libmaple/syscalls.c @@ -25,9 +25,11 @@ *****************************************************************************/ /** - * @file syscalls.c - * @brief Low level system routines used by Newlib for basic I/O and - * memory allocation. + * @file libmaple/syscalls.c + * @brief newlib stubs + * + * Low level system routines used by Newlib for basic I/O and memory + * allocation. */ #include diff --git a/libmaple/systick.c b/libmaple/systick.c index c6e3cbd..80c0c47 100644 --- a/libmaple/systick.c +++ b/libmaple/systick.c @@ -25,8 +25,8 @@ *****************************************************************************/ /** - * @file systick.c - * @brief System timer interrupt handler and initialization routines + * @file libmaple/systick.c + * @brief System timer (SysTick). */ #include diff --git a/libmaple/usart.c b/libmaple/usart.c index 1070aa2..253cf9f 100644 --- a/libmaple/usart.c +++ b/libmaple/usart.c @@ -25,10 +25,10 @@ *****************************************************************************/ /** - * @file usart.c + * @file libmaple/usart.c * @author Marti Bolivar , * Perry Hung - * @brief USART control routines + * @brief Portable USART routines */ #include diff --git a/libmaple/usb/usb.c b/libmaple/usb/usb.c index 6f23848..0130bab 100644 --- a/libmaple/usb/usb.c +++ b/libmaple/usb/usb.c @@ -25,8 +25,10 @@ *****************************************************************************/ /** - * @file usb.c + * @file libmaple/usb/usb.c * @brief USB support. + * + * This is a mess. What we need almost amounts to a ground-up rewrite. */ #include diff --git a/libmaple/usb/usb_cdcacm.c b/libmaple/usb/usb_cdcacm.c index 07d2bc8..6ef4806 100644 --- a/libmaple/usb/usb_cdcacm.c +++ b/libmaple/usb/usb_cdcacm.c @@ -25,10 +25,12 @@ *****************************************************************************/ /** - * @file usb_cdcacm.c + * @file libmaple/usb/usb_cdcacm.c + * @brief USB CDC ACM (a.k.a. virtual serial terminal, VCOM). * - * @brief USB CDC ACM (a.k.a. virtual serial terminal, VCOM) state and - * routines. + * FIXME: this works on the STM32F1 USB peripherals, and probably no + * place else. Nonportable bits really need to be factored out, and + * the result made cleaner. */ #include diff --git a/libmaple/util.c b/libmaple/util.c index 96050a1..ff100fe 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file util.c + * @file libmaple/util.c * @brief Utility procedures for debugging, mostly an error LED fade * and messages dumped over a UART for failed asserts. */ diff --git a/wirish/HardwareSerial.cpp b/wirish/HardwareSerial.cpp index a9eb763..0f12e72 100644 --- a/wirish/HardwareSerial.cpp +++ b/wirish/HardwareSerial.cpp @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file HardwareSerial.cpp + * @file wirish/HardwareSerial.cpp * @brief Wirish serial port implementation. */ diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 54807d3..51ff50e 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file boards.cpp + * @file wirish/boards.cpp * @brief Generic board routines. * * This file is mostly interesting for the init() function, which diff --git a/wirish/ext_interrupts.cpp b/wirish/ext_interrupts.cpp index 8f8c768..a4a27c2 100644 --- a/wirish/ext_interrupts.cpp +++ b/wirish/ext_interrupts.cpp @@ -25,9 +25,8 @@ *****************************************************************************/ /** - * @file ext_interrupts.c - * - * @brief Wiring-like interface for external interrupts + * @file wirish/ext_interrupts.c + * @brief Wiring-like interface for external interrupts */ #include diff --git a/wirish/include/wirish/HardwareSPI.h b/wirish/include/wirish/HardwareSPI.h index ad95191..89cf166 100644 --- a/wirish/include/wirish/HardwareSPI.h +++ b/wirish/include/wirish/HardwareSPI.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file HardwareSPI.h + * @file wirish/include/wirish/HardwareSPI.h * @brief High-level SPI interface * * This is a "bare essentials" polling driver for now. diff --git a/wirish/include/wirish/HardwareSerial.h b/wirish/include/wirish/HardwareSerial.h index c25fd6e..1eaacb6 100644 --- a/wirish/include/wirish/HardwareSerial.h +++ b/wirish/include/wirish/HardwareSerial.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file HardwareSerial.h + * @file wirish/include/wirish/HardwareSerial.h * @brief Wirish serial port interface. */ diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index c762542..3c2740a 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -25,10 +25,10 @@ *****************************************************************************/ /** - * @file boards.h + * @file wirish/include/wirish/boards.h * @author Bryan Newbold , * Marti Bolivar - * @brief Board-specific pin information. + * @brief init() and board-specific pin information. */ #ifndef _WIRISH_BOARDS_H_ diff --git a/wirish/include/wirish/ext_interrupts.h b/wirish/include/wirish/ext_interrupts.h index 617e43d..03b8e97 100644 --- a/wirish/include/wirish/ext_interrupts.h +++ b/wirish/include/wirish/ext_interrupts.h @@ -25,9 +25,8 @@ *****************************************************************************/ /** - * @file ext_interrupts.h - * - * @brief Wiring-like external interrupt prototypes and types. + * @file wirish/include/wirish/ext_interrupts.h + * @brief Wiring-like external interrupt prototypes and types. */ #ifndef _WIRISH_EXT_INTERRUPTS_H_ diff --git a/wirish/include/wirish/io.h b/wirish/include/wirish/io.h index de56a49..b5fe3a8 100644 --- a/wirish/include/wirish/io.h +++ b/wirish/include/wirish/io.h @@ -25,9 +25,8 @@ *****************************************************************************/ /** - * @file io.h - * - * @brief Arduino-compatible digital pin I/O interface. + * @file wirish/include/wirish/io.h + * @brief Wiring-style pin I/O interface. */ #ifndef _WIRISH_IO_H_ diff --git a/wirish/include/wirish/pwm.h b/wirish/include/wirish/pwm.h index e7130fb..6631d42 100644 --- a/wirish/include/wirish/pwm.h +++ b/wirish/include/wirish/pwm.h @@ -25,9 +25,8 @@ *****************************************************************************/ /** - * @file pwm.h - * - * @brief Arduino-compatible PWM interface. + * @file wirish/include/wirish/pwm.h + * @brief Wiring-style PWM interface. */ #ifndef _WIRISH_PWM_H_ diff --git a/wirish/include/wirish/wirish_debug.h b/wirish/include/wirish/wirish_debug.h index c8bc077..cb1be3d 100644 --- a/wirish/include/wirish/wirish_debug.h +++ b/wirish/include/wirish/wirish_debug.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file wirish_debug.h + * @file wirish/include/wirish/wirish_debug.h * @brief High level debug port configuration */ diff --git a/wirish/include/wirish/wirish_math.h b/wirish/include/wirish/wirish_math.h index 3820cab..39f16a0 100644 --- a/wirish/include/wirish/wirish_math.h +++ b/wirish/include/wirish/wirish_math.h @@ -25,8 +25,8 @@ *****************************************************************************/ /** - * @file wirish_math.h - * @brief Includes ; provides Arduino-compatible math routines. + * @file wirish/include/wirish/wirish_math.h + * @brief Includes ; provides Wiring-compatible math routines. */ #ifndef _WIRISH_WIRISH_MATH_H_ diff --git a/wirish/include/wirish/wirish_time.h b/wirish/include/wirish/wirish_time.h index a81075c..1520b1e 100644 --- a/wirish/include/wirish/wirish_time.h +++ b/wirish/include/wirish/wirish_time.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file wirish_time.h + * @file wirish/include/wirish/wirish_time.h * @brief Timing and delay functions. */ diff --git a/wirish/include/wirish/wirish_types.h b/wirish/include/wirish/wirish_types.h index d70b26f..fce895e 100644 --- a/wirish/include/wirish/wirish_types.h +++ b/wirish/include/wirish/wirish_types.h @@ -25,7 +25,7 @@ *****************************************************************************/ /** - * @file wirish_types.h + * @file wirish/include/wirish/wirish_types.h * @author Marti Bolivar * @brief Wirish library type definitions. */ -- cgit v1.2.3 From 173c7e1a7a7ce6a36801a96a235ae74d3ce062ed Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:23:45 -0400 Subject: libmaple/flash.c: Update Doxygen for flash_set_latency(). Update for STM32F2 support. Signed-off-by: Marti Bolivar --- libmaple/flash.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/libmaple/flash.c b/libmaple/flash.c index 0ade4cb..0cdff59 100644 --- a/libmaple/flash.c +++ b/libmaple/flash.c @@ -35,12 +35,14 @@ /** * @brief Set flash wait states * - * See ST PM0042, section 3.1 for restrictions on the acceptable value - * of wait_states for a given SYSCLK configuration. + * Note that not all wait states are available on every MCU. See the + * Flash programming manual for your MCU for restrictions on the + * allowed value of wait_states for a given system clock (SYSCLK) + * frequency. * * @param wait_states number of wait states (one of * FLASH_WAIT_STATE_0, FLASH_WAIT_STATE_1, - * FLASH_WAIT_STATE_2). + * ..., FLASH_WAIT_STATE_7). */ void flash_set_latency(uint32 wait_states) { uint32 val = FLASH_BASE->ACR; -- cgit v1.2.3 From 99ca63216d9dd4985e0892dad6b3ddfe216c6b8c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:24:16 -0400 Subject: libmaple/flash.h: Deprecate flash_enable_prefetch(). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index d3810a7..4ecfb77 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -77,6 +77,9 @@ static inline void flash_enable_features(uint32 feature_flags) { FLASH_BASE->ACR |= feature_flags; } +/** + * @brief Deprecated. Use flash_enable_features(FLASH_PREFETCH) instead. + */ static inline void flash_enable_prefetch(void) { flash_enable_features(FLASH_PREFETCH); } -- cgit v1.2.3 From d7f698eef315fa5edc009ec6335fc41ad62dfc05 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:24:42 -0400 Subject: libmaple/flash.h: Doxygen for flash_enable_features(). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index 4ecfb77..d84ded1 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -60,10 +60,7 @@ extern "C"{ * -- FLASH_ICACHE: instruction cache * -- FLASH_DCACHE: data cache * - * If the target doesn't provide a feature (e.g. instruction and - * data caches on the STM32F1), the flag should be set to some no-op - * value. This allows using these flags unconditionally, with the - * desired effect taking place on series that support them. + * See that function's Doxygen for more restrictions. */ #include @@ -73,6 +70,19 @@ extern "C"{ void flash_set_latency(uint32 wait_states); +/** + * @brief Enable Flash memory features + * + * If the target MCU doesn't provide a feature (e.g. instruction and + * data caches on the STM32F1), the flag will be ignored. This allows + * using these flags unconditionally, with the desired effect taking + * place on targets that support them. + * + * @param feature_flags Bitwise OR of the following: + * FLASH_PREFETCH (turns on prefetcher), + * FLASH_ICACHE (turns on instruction cache), + * FLASH_DCACHE (turns on data cache). + */ static inline void flash_enable_features(uint32 feature_flags) { FLASH_BASE->ACR |= feature_flags; } -- cgit v1.2.3 From 32fcf1c726e7a4641c42608a64161045982ea960 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:25:32 -0400 Subject: libmaple/util.h: Doxygen cosmetics. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/util.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/util.h b/libmaple/include/libmaple/util.h index 60ca0d3..5a70348 100644 --- a/libmaple/include/libmaple/util.h +++ b/libmaple/include/libmaple/util.h @@ -42,7 +42,7 @@ extern "C"{ * Bit manipulation */ -/** 1UL << (shift) */ +/** 1UL shifted left by 'shift' */ #define BIT(shift) (1UL << (shift)) /** 'Mask' shifted left by 'shift' */ #define BIT_MASK_SHIFT(mask, shift) ((mask) << (shift)) -- cgit v1.2.3 From 780552d65b4ab0a6a70eed3c2074547e3b1dc255 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:26:39 -0400 Subject: Mark Doxygen for Flash register maps as series-specific. This will let help us verify that we got the right thing when we pull it out of of Doxygen XML for the official HTML documentation. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/flash.h | 2 +- libmaple/stm32f2/include/series/flash.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/stm32f1/include/series/flash.h b/libmaple/stm32f1/include/series/flash.h index 0c70986..bb335e7 100644 --- a/libmaple/stm32f1/include/series/flash.h +++ b/libmaple/stm32f1/include/series/flash.h @@ -46,7 +46,7 @@ extern "C"{ * Register map */ -/** Flash register map type */ +/** @brief STM32F1 Flash register map type */ typedef struct flash_reg_map { __io uint32 ACR; /**< Access control register */ __io uint32 KEYR; /**< Key register */ diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h index cfc6e6b..10b8717 100644 --- a/libmaple/stm32f2/include/series/flash.h +++ b/libmaple/stm32f2/include/series/flash.h @@ -46,7 +46,7 @@ extern "C"{ * Register map */ -/** Flash register map type */ +/** @brief STM32F2 Flash register map type */ typedef struct flash_reg_map { __io uint32 ACR; /**< Access control register */ __io uint32 KEYR; /**< Key register */ -- cgit v1.2.3 From 68f29ea554603ee0a39dbe1a15c4fbcdb0736ccb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 8 May 2012 16:28:05 -0400 Subject: Make usart_irq() __always_inline. Compiling with -Os can prevent this from inlining, and it's an IRQ handler, so the space is worth spending. Signed-off-by: Marti Bolivar --- libmaple/usart_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/usart_private.h b/libmaple/usart_private.h index a5cec83..8e8e11b 100644 --- a/libmaple/usart_private.h +++ b/libmaple/usart_private.h @@ -37,7 +37,7 @@ #include #include -static inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) { +static __always_inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) { #ifdef USART_SAFE_INSERT /* If the buffer is full and the user defines USART_SAFE_INSERT, * ignore new bytes. */ -- cgit v1.2.3 From 392d791b26de9f77170332abab57c6542a4ced79 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 9 May 2012 15:00:45 -0400 Subject: Shut up, doxygen. Signed-off-by: Marti Bolivar --- support/doxygen/Doxyfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/support/doxygen/Doxyfile b/support/doxygen/Doxyfile index 35e6bd6..5a5d7ed 100644 --- a/support/doxygen/Doxyfile +++ b/support/doxygen/Doxyfile @@ -537,7 +537,7 @@ LAYOUT_FILE = # The QUIET tag can be used to turn on/off the messages that are generated # by doxygen. Possible values are YES and NO. If left blank NO is used. -QUIET = NO +QUIET = YES # The WARNINGS tag can be used to turn on/off the warning messages that are # generated by doxygen. Possible values are YES and NO. If left blank @@ -549,7 +549,7 @@ WARNINGS = YES # for undocumented members. If EXTRACT_ALL is set to YES then this flag will # automatically be disabled. -WARN_IF_UNDOCUMENTED = YES +WARN_IF_UNDOCUMENTED = NO # If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for # potential errors in the documentation, such as not documenting some -- cgit v1.2.3 From 94d95639c124ebff02a9944237ca9c1764c9cca9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 9 May 2012 15:09:52 -0400 Subject: Change __DOXYGEN_PREDEFINED_HACK to __DOXYGEN__. avr-gcc does it this way. Seems ok to me. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 7 +++---- libmaple/stm32f1/include/series/stm32.h | 4 ++-- support/doxygen/Doxyfile | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 6b8e905..097a016 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -59,8 +59,7 @@ extern "C" { /* The series header is responsible for defining: * - * - Everything enclosed in the following __DOXYGEN_PREDEFINED_HACK - * conditional block. + * - Everything in the following __DOXYGEN__ conditional block. * * - STM32_HAVE_FSMC: 1 if the MCU has the FSMC peripheral, and 0 * otherwise. @@ -79,7 +78,7 @@ extern "C" { #error "Bad STM32F1 configuration. Check header for your MCU." #endif -#ifdef __DOXYGEN_PREDEFINED_HACK +#ifdef __DOXYGEN__ /* * Clock configuration. @@ -162,7 +161,7 @@ extern "C" { */ #define STM32_HAVE_USB -#endif /* __DOXYGEN_PREDEFINED_HACK */ +#endif /* __DOXYGEN__ */ /* * The following are for backwards compatibility only. diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index e6d3b19..e01c494 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -181,7 +181,7 @@ extern "C" { * Doxygen */ -#ifdef __DOXYGEN_PREDEFINED_HACK +#ifdef __DOXYGEN__ /** * @brief STM32 line value for the STM32F1 MCU being targeted. @@ -192,7 +192,7 @@ extern "C" { */ #define STM32_F1_LINE -#endif /* __DOXYGEN_PREDEFINED_HACK */ +#endif /* __DOXYGEN__ */ #ifdef __cplusplus } diff --git a/support/doxygen/Doxyfile b/support/doxygen/Doxyfile index 5a5d7ed..a267c36 100644 --- a/support/doxygen/Doxyfile +++ b/support/doxygen/Doxyfile @@ -1377,7 +1377,7 @@ PREDEFINED = __attribute__()= \ STM32_MEDIUM_DENSITY \ STM32_HIGH_DENSITY \ STM32_XL_DENSITY \ - __DOXYGEN_PREDEFINED_HACK + __DOXYGEN__ # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then # this tag can be used to specify a list of macro names that should be expanded. -- cgit v1.2.3 From ca34bcaa8cf5ac129694cbe11e9b0b2fa16e6d9d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 9 May 2012 17:53:04 -0400 Subject: flash.h: Doxygen. Document FLASH_BASE once. This is due to restrictions in the documentation build system. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/flash.h | 5 +++++ libmaple/stm32f1/include/series/flash.h | 1 - libmaple/stm32f2/include/series/flash.h | 1 - 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/libmaple/include/libmaple/flash.h b/libmaple/include/libmaple/flash.h index d84ded1..943e466 100644 --- a/libmaple/include/libmaple/flash.h +++ b/libmaple/include/libmaple/flash.h @@ -64,6 +64,11 @@ extern "C"{ */ #include +#ifdef __DOXYGEN__ +/** Flash register map base pointer. */ +#define FLASH_BASE +#endif + /* * Flash routines */ diff --git a/libmaple/stm32f1/include/series/flash.h b/libmaple/stm32f1/include/series/flash.h index bb335e7..729cf9a 100644 --- a/libmaple/stm32f1/include/series/flash.h +++ b/libmaple/stm32f1/include/series/flash.h @@ -58,7 +58,6 @@ typedef struct flash_reg_map { __io uint32 WRPR; /**< Write protection register */ } flash_reg_map; -/** Flash register map base pointer */ #define FLASH_BASE ((struct flash_reg_map*)0x40022000) /* diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h index 10b8717..f3c650b 100644 --- a/libmaple/stm32f2/include/series/flash.h +++ b/libmaple/stm32f2/include/series/flash.h @@ -56,7 +56,6 @@ typedef struct flash_reg_map { __io uint32 OPTCR; /**< Option control register */ } flash_reg_map; -/** Flash register map base pointer */ #define FLASH_BASE ((struct flash_reg_map*)0x40023C00) /* -- cgit v1.2.3 From 38636eb015cb8f6789ffe376d8ba0b8b2bb52912 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 9 May 2012 17:56:35 -0400 Subject: Lose dependency in series/flash.h headers. Switch from BIT(...) to (1U << ...). Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/flash.h | 46 +++++++++++++++--------------- libmaple/stm32f2/include/series/flash.h | 50 ++++++++++++++++----------------- 2 files changed, 48 insertions(+), 48 deletions(-) diff --git a/libmaple/stm32f1/include/series/flash.h b/libmaple/stm32f1/include/series/flash.h index 729cf9a..24efb0b 100644 --- a/libmaple/stm32f1/include/series/flash.h +++ b/libmaple/stm32f1/include/series/flash.h @@ -40,7 +40,7 @@ extern "C"{ #endif -#include +#include /* * Register map @@ -70,9 +70,9 @@ typedef struct flash_reg_map { #define FLASH_ACR_PRFTBE_BIT 4 #define FLASH_ACR_HLFCYA_BIT 3 -#define FLASH_ACR_PRFTBS BIT(FLASH_ACR_PRFTBS_BIT) -#define FLASH_ACR_PRFTBE BIT(FLASH_ACR_PRFTBE_BIT) -#define FLASH_ACR_HLFCYA BIT(FLASH_ACR_HLFCYA_BIT) +#define FLASH_ACR_PRFTBS (1U << FLASH_ACR_PRFTBS_BIT) +#define FLASH_ACR_PRFTBE (1U << FLASH_ACR_PRFTBE_BIT) +#define FLASH_ACR_HLFCYA (1U << FLASH_ACR_HLFCYA_BIT) #define FLASH_ACR_LATENCY 0x7 /* Status register */ @@ -82,10 +82,10 @@ typedef struct flash_reg_map { #define FLASH_SR_PGERR_BIT 2 #define FLASH_SR_BSY_BIT 0 -#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) -#define FLASH_SR_WRPRTERR BIT(FLASH_SR_WRPRTERR_BIT) -#define FLASH_SR_PGERR BIT(FLASH_SR_PGERR_BIT) -#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) +#define FLASH_SR_EOP (1U << FLASH_SR_EOP_BIT) +#define FLASH_SR_WRPRTERR (1U << FLASH_SR_WRPRTERR_BIT) +#define FLASH_SR_PGERR (1U << FLASH_SR_PGERR_BIT) +#define FLASH_SR_BSY (1U << FLASH_SR_BSY_BIT) /* Control register */ @@ -100,16 +100,16 @@ typedef struct flash_reg_map { #define FLASH_CR_PER_BIT 1 #define FLASH_CR_PG_BIT 0 -#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) -#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) -#define FLASH_CR_OPTWRE BIT(FLASH_CR_OPTWRE_BIT) -#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) -#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) -#define FLASH_CR_OPTER BIT(FLASH_CR_OPTER_BIT) -#define FLASH_CR_OPTPG BIT(FLASH_CR_OPTPG_BIT) -#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) -#define FLASH_CR_PER BIT(FLASH_CR_PER_BIT) -#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) +#define FLASH_CR_EOPIE (1U << FLASH_CR_EOPIE_BIT) +#define FLASH_CR_ERRIE (1U << FLASH_CR_ERRIE_BIT) +#define FLASH_CR_OPTWRE (1U << FLASH_CR_OPTWRE_BIT) +#define FLASH_CR_LOCK (1U << FLASH_CR_LOCK_BIT) +#define FLASH_CR_STRT (1U << FLASH_CR_STRT_BIT) +#define FLASH_CR_OPTER (1U << FLASH_CR_OPTER_BIT) +#define FLASH_CR_OPTPG (1U << FLASH_CR_OPTPG_BIT) +#define FLASH_CR_MER (1U << FLASH_CR_MER_BIT) +#define FLASH_CR_PER (1U << FLASH_CR_PER_BIT) +#define FLASH_CR_PG (1U << FLASH_CR_PG_BIT) /* Option byte register */ @@ -122,11 +122,11 @@ typedef struct flash_reg_map { #define FLASH_OBR_DATA1 (0xFF << 18) #define FLASH_OBR_DATA0 (0xFF << 10) #define FLASH_OBR_USER 0x3FF -#define FLASH_OBR_nRST_STDBY BIT(FLASH_OBR_nRST_STDBY_BIT) -#define FLASH_OBR_nRST_STOP BIT(FLASH_OBR_nRST_STOP_BIT) -#define FLASH_OBR_WDG_SW BIT(FLASH_OBR_WDG_SW_BIT) -#define FLASH_OBR_RDPRT BIT(FLASH_OBR_RDPRT_BIT) -#define FLASH_OBR_OPTERR BIT(FLASH_OBR_OPTERR_BIT) +#define FLASH_OBR_nRST_STDBY (1U << FLASH_OBR_nRST_STDBY_BIT) +#define FLASH_OBR_nRST_STOP (1U << FLASH_OBR_nRST_STOP_BIT) +#define FLASH_OBR_WDG_SW (1U << FLASH_OBR_WDG_SW_BIT) +#define FLASH_OBR_RDPRT (1U << FLASH_OBR_RDPRT_BIT) +#define FLASH_OBR_OPTERR (1U << FLASH_OBR_OPTERR_BIT) /* * Series-specific configuration values. diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h index f3c650b..a3c3933 100644 --- a/libmaple/stm32f2/include/series/flash.h +++ b/libmaple/stm32f2/include/series/flash.h @@ -40,7 +40,7 @@ extern "C"{ #endif -#include +#include /* * Register map @@ -70,11 +70,11 @@ typedef struct flash_reg_map { #define FLASH_ACR_ICEN_BIT 9 #define FLASH_ACR_PRFTEN_BIT 8 -#define FLASH_ACR_DCRST BIT(FLASH_ACR_DCRST_BIT) -#define FLASH_ACR_ICRST BIT(FLASH_ACR_ICRST_BIT) -#define FLASH_ACR_DCEN BIT(FLASH_ACR_DCEN_BIT) -#define FLASH_ACR_ICEN BIT(FLASH_ACR_ICEN_BIT) -#define FLASH_ACR_PRFTEN BIT(FLASH_ACR_PRFTEN_BIT) +#define FLASH_ACR_DCRST (1U << FLASH_ACR_DCRST_BIT) +#define FLASH_ACR_ICRST (1U << FLASH_ACR_ICRST_BIT) +#define FLASH_ACR_DCEN (1U << FLASH_ACR_DCEN_BIT) +#define FLASH_ACR_ICEN (1U << FLASH_ACR_ICEN_BIT) +#define FLASH_ACR_PRFTEN (1U << FLASH_ACR_PRFTEN_BIT) #define FLASH_ACR_LATENCY 0x7 #define FLASH_ACR_LATENCY_0WS 0x0 #define FLASH_ACR_LATENCY_1WS 0x1 @@ -105,13 +105,13 @@ typedef struct flash_reg_map { #define FLASH_SR_OPERR_BIT 1 #define FLASH_SR_EOP_BIT 0 -#define FLASH_SR_BSY BIT(FLASH_SR_BSY_BIT) -#define FLASH_SR_PGSERR BIT(FLASH_SR_PGSERR_BIT) -#define FLASH_SR_PGPERR BIT(FLASH_SR_PGPERR_BIT) -#define FLASH_SR_PGAERR BIT(FLASH_SR_PGAERR_BIT) -#define FLASH_SR_WRPERR BIT(FLASH_SR_WRPERR_BIT) -#define FLASH_SR_OPERR BIT(FLASH_SR_OPERR_BIT) -#define FLASH_SR_EOP BIT(FLASH_SR_EOP_BIT) +#define FLASH_SR_BSY (1U << FLASH_SR_BSY_BIT) +#define FLASH_SR_PGSERR (1U << FLASH_SR_PGSERR_BIT) +#define FLASH_SR_PGPERR (1U << FLASH_SR_PGPERR_BIT) +#define FLASH_SR_PGAERR (1U << FLASH_SR_PGAERR_BIT) +#define FLASH_SR_WRPERR (1U << FLASH_SR_WRPERR_BIT) +#define FLASH_SR_OPERR (1U << FLASH_SR_OPERR_BIT) +#define FLASH_SR_EOP (1U << FLASH_SR_EOP_BIT) /* Control register */ @@ -123,10 +123,10 @@ typedef struct flash_reg_map { #define FLASH_CR_SER_BIT 1 #define FLASH_CR_PG_BIT 0 -#define FLASH_CR_LOCK BIT(FLASH_CR_LOCK_BIT) -#define FLASH_CR_ERRIE BIT(FLASH_CR_ERRIE_BIT) -#define FLASH_CR_EOPIE BIT(FLASH_CR_EOPIE_BIT) -#define FLASH_CR_STRT BIT(FLASH_CR_STRT_BIT) +#define FLASH_CR_LOCK (1U << FLASH_CR_LOCK_BIT) +#define FLASH_CR_ERRIE (1U << FLASH_CR_ERRIE_BIT) +#define FLASH_CR_EOPIE (1U << FLASH_CR_EOPIE_BIT) +#define FLASH_CR_STRT (1U << FLASH_CR_STRT_BIT) #define FLASH_CR_PSIZE (0x3 << 8) #define FLASH_CR_PSIZE_MUL8 (0x0 << 8) @@ -148,9 +148,9 @@ typedef struct flash_reg_map { #define FLASH_CR_SNB_10 (0xA << 3) #define FLASH_CR_SNB_11 (0xB << 3) -#define FLASH_CR_MER BIT(FLASH_CR_MER_BIT) -#define FLASH_CR_SER BIT(FLASH_CR_SER_BIT) -#define FLASH_CR_PG BIT(FLASH_CR_PG_BIT) +#define FLASH_CR_MER (1U << FLASH_CR_MER_BIT) +#define FLASH_CR_SER (1U << FLASH_CR_SER_BIT) +#define FLASH_CR_PG (1U << FLASH_CR_PG_BIT) /* Option control register */ @@ -168,9 +168,9 @@ typedef struct flash_reg_map { #define FLASH_OPTCR_RDP_LEVEL2 (0xCC << 8) #define FLASH_OPTCR_USER (0x7 << 5) -#define FLASH_OPTCR_nRST_STDBY BIT(FLASH_OPTCR_nRST_STDBY_BIT) -#define FLASH_OPTCR_nRST_STOP BIT(FLASH_OPTCR_nRST_STOP_BIT) -#define FLASH_OPTCR_WDG_SW BIT(FLASH_OPTCR_WDG_SW_BIT) +#define FLASH_OPTCR_nRST_STDBY (1U << FLASH_OPTCR_nRST_STDBY_BIT) +#define FLASH_OPTCR_nRST_STOP (1U << FLASH_OPTCR_nRST_STOP_BIT) +#define FLASH_OPTCR_WDG_SW (1U << FLASH_OPTCR_WDG_SW_BIT) #define FLASH_OPTCR_BOR_LEV (0x3 << 2) #define FLASH_OPTCR_BOR_LEVEL3 (0x0 << 2) @@ -178,8 +178,8 @@ typedef struct flash_reg_map { #define FLASH_OPTCR_BOR_LEVEL1 (0x2 << 2) #define FLASH_OPTCR_BOR_OFF (0x3 << 2) -#define FLASH_OPTCR_OPTSTRT BIT(FLASH_OPTCR_OPTSTRT_BIT) -#define FLASH_OPTCR_OPTLOCK BIT(FLASH_OPTCR_OPTLOCK_BIT) +#define FLASH_OPTCR_OPTSTRT (1U << FLASH_OPTCR_OPTSTRT_BIT) +#define FLASH_OPTCR_OPTLOCK (1U << FLASH_OPTCR_OPTLOCK_BIT) /* * Series-specific configuration values -- cgit v1.2.3 From 8bed1f3e3a5db4268c4f9f49319d993c922fe496 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 13:20:03 -0400 Subject: Doxyfile: Disable TYPEDEF_HIDES_STRUCT to work around Breathe issues. This works around a problem we're having getting the XML for the series headers into a form that we can work with in leaflabs-docs. Signed-off-by: Marti Bolivar --- support/doxygen/Doxyfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/support/doxygen/Doxyfile b/support/doxygen/Doxyfile index a267c36..6dbce7d 100644 --- a/support/doxygen/Doxyfile +++ b/support/doxygen/Doxyfile @@ -281,7 +281,7 @@ SUBGROUPING = YES # be useful for C code in case the coding convention dictates that all compound # types are typedef'ed and only the typedef is referenced, never the tag name. -TYPEDEF_HIDES_STRUCT = YES +TYPEDEF_HIDES_STRUCT = NO # The SYMBOL_CACHE_SIZE determines the size of the internal cache use to # determine which symbols to keep in memory and which to flush to disk. -- cgit v1.2.3 From 9ebe3545cb63a0afec3958b1ddda582d32106a4a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 15:26:06 -0400 Subject: Fix .gitignore so it doesn't filter out support/doxygen/. Signed-off-by: Marti Bolivar --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 33e77e7..f394b3c 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ build/ -doxygen/ +doxygen/xml/ +doxygen/html/ main.cpp libmaple.layout tags -- cgit v1.2.3 From 6ecabd970516bb374000f9074b5a4323da2482d5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 15:47:56 -0400 Subject: Doxygen: add the Evil Mangler. Whenever Doxygen is running on a series header, make it run an awk script, the Evil Mangler, that pretends the file is enclosed in an appropriate namespace declaration for the series target. Doxygen chokes if two structs have the same name. This is a problem for the series headers, which commonly have data structures with the same name. However, if those structs are in different namespaces, Doxygen has no problems. We obviously can't use namespaces in C headers, so use FILTER_PATTERNS to trick Doxygen into thinking they're there. Ugly, but I can't think of a better way to handle this. Signed-off-by: Marti Bolivar --- support/doxygen/Doxyfile | 4 +++- support/doxygen/evil_mangler.awk | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) create mode 100755 support/doxygen/evil_mangler.awk diff --git a/support/doxygen/Doxyfile b/support/doxygen/Doxyfile index 6dbce7d..1074403 100644 --- a/support/doxygen/Doxyfile +++ b/support/doxygen/Doxyfile @@ -690,7 +690,9 @@ INPUT_FILTER = # info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER # is applied to all files. -FILTER_PATTERNS = +# Trick Doxygen into thinking series headers are in separate +# namespaces; see the Evil Mangler source for more information. +FILTER_PATTERNS = */libmaple/stm32*/include/series/*.h=./support/doxygen/evil_mangler.awk # If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using # INPUT_FILTER) will be used to filter the input files when producing source diff --git a/support/doxygen/evil_mangler.awk b/support/doxygen/evil_mangler.awk new file mode 100755 index 0000000..b07da72 --- /dev/null +++ b/support/doxygen/evil_mangler.awk @@ -0,0 +1,38 @@ +#!/usr/bin/awk -f + +# libmaple's own Evil Mangler +# +# Input filter hack to trick Doxygen into thinking that a series +# header is in a separate namespace. This is necessary because Doxygen +# doesn't know how to cope with two data structures with the same name +# in different places in the project. (We do that all the time, +# e.g. for foo_reg_map structs.) +# +# E.g., an STM32F1 header gets transformed into: +# +# namespace stm32f1 { +# +# } + +BEGIN { + # For extracting series component from header FILENAME. + series_regex = "/stm32[flw][0-9]*/"; + # Holds header FILENAME. Cargo-culted; not sure why it's necessary. + f = ""; + # Holds series component. + series = ""; +} +{ + if (f != FILENAME) { + f = FILENAME; + match(f, series_regex); + series = substr(f, RSTART + 1, RLENGTH - 2); + printf("namespace %s {\n", series); + } + print; +} +END { + if (series != "") { + print "}" + } +} -- cgit v1.2.3 From e34923631052c41349e660628fab310835ca5a5e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 16:02:00 -0400 Subject: Don't try to build some libmaple files. We can't do these on F2 right now. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 834c7a3..5c63522 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -12,14 +12,14 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c -cSRCS_$(d) += dma.c +# cSRCS_$(d) += dma.c cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c cSRCS_$(d) += iwdg.c cSRCS_$(d) += nvic.c cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c -cSRCS_$(d) += spi.c +# cSRCS_$(d) += spi.c cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c cSRCS_$(d) += timer.c -- cgit v1.2.3 From a00bf9944d419432c633dcdfd27dba06b0f71842 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 16:04:09 -0400 Subject: libmaple/iwdg.h: Remove BIT() usages. This cleans up another unnecessary dependency. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/iwdg.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/iwdg.h b/libmaple/include/libmaple/iwdg.h index 0aef8fd..3a16c55 100644 --- a/libmaple/include/libmaple/iwdg.h +++ b/libmaple/include/libmaple/iwdg.h @@ -46,7 +46,6 @@ extern "C"{ #endif #include -#include /* * Register map @@ -88,8 +87,8 @@ typedef struct iwdg_reg_map { #define IWDG_SR_RVU_BIT 1 #define IWDG_SR_PVU_BIT 0 -#define IWDG_SR_RVU BIT(IWDG_SR_RVU_BIT) -#define IWDG_SR_PVU BIT(IWDG_SR_PVU_BIT) +#define IWDG_SR_RVU (1U << IWDG_SR_RVU_BIT) +#define IWDG_SR_PVU (1U << IWDG_SR_PVU_BIT) /** * @brief Independent watchdog prescalers. -- cgit v1.2.3 From f5c3c93e18f552b8e25a9a201a34daa9f625b4d0 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 16:58:36 -0400 Subject: stm32f2/fsmc.c: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/fsmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/stm32f2/fsmc.c b/libmaple/stm32f2/fsmc.c index 7f49cd8..ec41720 100644 --- a/libmaple/stm32f2/fsmc.c +++ b/libmaple/stm32f2/fsmc.c @@ -26,7 +26,7 @@ /** * @file libmaple/stm32f2/fsmc.c - * @author Marti Bolivar , + * @author Marti Bolivar * @brief STM32F2 FSMC support. */ -- cgit v1.2.3 From 23598a3b21bc355f4a72cfd51686dad2edd97ffb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 17:31:00 -0400 Subject: libmaple/fsmc.h: Don't use BIT(). As fsmc.h doesn't include util.h or libmaple.h, these usages are actually in error. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/fsmc.h | 46 ++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/libmaple/include/libmaple/fsmc.h b/libmaple/include/libmaple/fsmc.h index 01a6a3b..ddfedee 100644 --- a/libmaple/include/libmaple/fsmc.h +++ b/libmaple/include/libmaple/fsmc.h @@ -135,16 +135,16 @@ typedef struct fsmc_nor_psram_reg_map { #define FSMC_BCR_MUXEN_BIT 1 #define FSMC_BCR_MBKEN_BIT 0 -#define FSMC_BCR_CBURSTRW BIT(FSMC_BCR_CBURSTRW_BIT) -#define FSMC_BCR_ASYNCWAIT BIT(FSMC_BCR_ASYNCWAIT_BIT) -#define FSMC_BCR_EXTMOD BIT(FSMC_BCR_EXTMOD_BIT) -#define FSMC_BCR_WAITEN BIT(FSMC_BCR_WAITEN_BIT) -#define FSMC_BCR_WREN BIT(FSMC_BCR_WREN_BIT) -#define FSMC_BCR_WAITCFG BIT(FSMC_BCR_WAITCFG_BIT) -#define FSMC_BCR_WRAPMOD BIT(FSMC_BCR_WRAPMOD_BIT) -#define FSMC_BCR_WAITPOL BIT(FSMC_BCR_WAITPOL_BIT) -#define FSMC_BCR_BURSTEN BIT(FSMC_BCR_BURSTEN_BIT) -#define FSMC_BCR_FACCEN BIT(FSMC_BCR_FACCEN_BIT) +#define FSMC_BCR_CBURSTRW (1U << FSMC_BCR_CBURSTRW_BIT) +#define FSMC_BCR_ASYNCWAIT (1U << FSMC_BCR_ASYNCWAIT_BIT) +#define FSMC_BCR_EXTMOD (1U << FSMC_BCR_EXTMOD_BIT) +#define FSMC_BCR_WAITEN (1U << FSMC_BCR_WAITEN_BIT) +#define FSMC_BCR_WREN (1U << FSMC_BCR_WREN_BIT) +#define FSMC_BCR_WAITCFG (1U << FSMC_BCR_WAITCFG_BIT) +#define FSMC_BCR_WRAPMOD (1U << FSMC_BCR_WRAPMOD_BIT) +#define FSMC_BCR_WAITPOL (1U << FSMC_BCR_WAITPOL_BIT) +#define FSMC_BCR_BURSTEN (1U << FSMC_BCR_BURSTEN_BIT) +#define FSMC_BCR_FACCEN (1U << FSMC_BCR_FACCEN_BIT) #define FSMC_BCR_MWID (0x3 << 4) #define FSMC_BCR_MWID_8BITS (0x0 << 4) #define FSMC_BCR_MWID_16BITS (0x1 << 4) @@ -152,8 +152,8 @@ typedef struct fsmc_nor_psram_reg_map { #define FSMC_BCR_MTYP_SRAM (0x0 << 2) #define FSMC_BCR_MTYP_PSRAM (0x1 << 2) #define FSMC_BCR_MTYP_NOR_FLASH (0x2 << 2) -#define FSMC_BCR_MUXEN BIT(FSMC_BCR_MUXEN_BIT) -#define FSMC_BCR_MBKEN BIT(FSMC_BCR_MBKEN_BIT) +#define FSMC_BCR_MUXEN (1U << FSMC_BCR_MUXEN_BIT) +#define FSMC_BCR_MBKEN (1U << FSMC_BCR_MBKEN_BIT) /* SRAM/NOR-Flash chip-select timing registers */ @@ -198,15 +198,15 @@ typedef struct fsmc_nor_psram_reg_map { #define FSMC_PCR_ECCPS_8192B (0x5 << 17) #define FSMC_PCR_TAR (0xF << 13) #define FSMC_PCR_TCLR (0xF << 9) -#define FSMC_PCR_ECCEN BIT(FSMC_PCR_ECCEN_BIT) +#define FSMC_PCR_ECCEN (1U << FSMC_PCR_ECCEN_BIT) #define FSMC_PCR_PWID (0x3 << 4) #define FSMC_PCR_PWID_8BITS (0x0 << 4) #define FSMC_PCR_PWID_16BITS (0x1 << 4) -#define FSMC_PCR_PTYP BIT(FSMC_PCR_PTYP_BIT) +#define FSMC_PCR_PTYP (1U << FSMC_PCR_PTYP_BIT) #define FSMC_PCR_PTYP_PC_CF_PCMCIA (0x0 << FSMC_PCR_PTYP_BIT) #define FSMC_PCR_PTYP_NAND (0x1 << FSMC_PCR_PTYP_BIT) -#define FSMC_PCR_PBKEN BIT(FSMC_PCR_PBKEN_BIT) -#define FSMC_PCR_PWAITEN BIT(FSMC_PCR_PWAITEN_BIT) +#define FSMC_PCR_PBKEN (1U << FSMC_PCR_PBKEN_BIT) +#define FSMC_PCR_PWAITEN (1U << FSMC_PCR_PWAITEN_BIT) /* FIFO status and interrupt registers */ @@ -218,13 +218,13 @@ typedef struct fsmc_nor_psram_reg_map { #define FSMC_SR_ILS_BIT 1 #define FSMC_SR_IRS_BIT 0 -#define FSMC_SR_FEMPT BIT(FSMC_SR_FEMPT_BIT) -#define FSMC_SR_IFEN BIT(FSMC_SR_IFEN_BIT) -#define FSMC_SR_ILEN BIT(FSMC_SR_ILEN_BIT) -#define FSMC_SR_IREN BIT(FSMC_SR_IREN_BIT) -#define FSMC_SR_IFS BIT(FSMC_SR_IFS_BIT) -#define FSMC_SR_ILS BIT(FSMC_SR_ILS_BIT) -#define FSMC_SR_IRS BIT(FSMC_SR_IRS_BIT) +#define FSMC_SR_FEMPT (1U << FSMC_SR_FEMPT_BIT) +#define FSMC_SR_IFEN (1U << FSMC_SR_IFEN_BIT) +#define FSMC_SR_ILEN (1U << FSMC_SR_ILEN_BIT) +#define FSMC_SR_IREN (1U << FSMC_SR_IREN_BIT) +#define FSMC_SR_IFS (1U << FSMC_SR_IFS_BIT) +#define FSMC_SR_ILS (1U << FSMC_SR_ILS_BIT) +#define FSMC_SR_IRS (1U << FSMC_SR_IRS_BIT) /* Common memory space timing registers */ -- cgit v1.2.3 From 56deba11cb967c8f9cc61ae17e20c69268ecb5e4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 10 May 2012 17:31:24 -0400 Subject: libmaple/fsmc.h: Better Doxygen for memory bank bases. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/fsmc.h | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/libmaple/include/libmaple/fsmc.h b/libmaple/include/libmaple/fsmc.h index ddfedee..6225fee 100644 --- a/libmaple/include/libmaple/fsmc.h +++ b/libmaple/include/libmaple/fsmc.h @@ -251,29 +251,49 @@ typedef struct fsmc_nor_psram_reg_map { * Memory bank boundary addresses */ -/** Pointer to base address of FSMC memory bank 1 (split into 4 - * regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip) */ +/** + * @brief Void pointer to base address of FSMC memory bank 1 (NOR/PSRAM). + * + * This bank is split into 4 regions. Each region supports interfacing + * with 1 NOR Flash, SRAM, or PSRAM chip. The base addresses of these + * regions are FSMC_NOR_PSRAM_REGIONx, for x = 1, 2, 3, 4. + */ #define FSMC_BANK1 ((void*)0x60000000) -/** Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM) */ +/** + * @brief Void pointer to base address of FSMC memory bank 1, region 1 + * (NOR/PSRAM). + */ #define FSMC_NOR_PSRAM_REGION1 FSMC_BANK1 -/** Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM) */ +/** + * @brief Void pointer to base address of FSMC memory bank 1, region 2 + * (NOR/PSRAM). + */ #define FSMC_NOR_PSRAM_REGION2 ((void*)0x64000000) -/** Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM) */ +/** + * @brief Void pointer to base address of FSMC memory bank 1, region 3 + * (NOR/PSRAM). + */ #define FSMC_NOR_PSRAM_REGION3 ((void*)0x68000000) -/** Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM) */ +/** + * @brief Void pointer to base address of FSMC memory bank 1, region 4 + * (NOR/PSRAM). + */ #define FSMC_NOR_PSRAM_REGION4 ((void*)0x6C000000) -/** Pointer to base address of FSMC memory bank 2 (for NAND Flash) */ +/** Void pointer to base address of FSMC memory bank 2 (NAND Flash). */ #define FSMC_BANK2 ((void*)0x70000000) -/** Pointer to base address of FSMC memory bank 3 (for NAND Flash) */ +/** Void pointer to base address of FSMC memory bank 3 (NAND Flash). */ #define FSMC_BANK3 ((void*)0x80000000) -/** Pointer to base address of FSMC memory bank 4 (for PC card devices */ +/** + * @brief Void pointer to base address of FSMC memory bank 4 (PC card + * devices). + */ #define FSMC_BANK4 ((void*)0x90000000) /* -- cgit v1.2.3 From bc3090f787cd7d8bb052a79632275211b57fc23b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 12:11:56 -0400 Subject: libmaple/rcc.h: Doxygen workarounds. We need the arguments to be the same name everywhere, or Breathe/Doxygen get confused. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 7c23f1b..9ed12bc 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -111,9 +111,9 @@ int rcc_is_clk_ready(rcc_clk clock); /* Peripheral clock lines and clock domains. */ -void rcc_clk_enable(rcc_clk_id device); -void rcc_reset_dev(rcc_clk_id device); -rcc_clk_domain rcc_dev_clk(rcc_clk_id device); +void rcc_clk_enable(rcc_clk_id id); +void rcc_reset_dev(rcc_clk_id id); +rcc_clk_domain rcc_dev_clk(rcc_clk_id id); /* Clock security system */ -- cgit v1.2.3 From cfdc0986c8c6617dd0762d72514d1c8f56329f59 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 12:12:56 -0400 Subject: rcc.c: Fix typo. Signed-off-by: Marti Bolivar --- libmaple/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/rcc.c b/libmaple/rcc.c index 91ce8e7..7b7be0d 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -90,7 +90,7 @@ void rcc_switch_sysclk(rcc_sysclk_src sysclk_src) { * On all known STM32 series, this encoding has the property that * adding one to the low byte also gives the bit to check to determine * if the clock is ready. For example, on STM32F1, RCC_CR_HSERDY is - * bit 17. If that's not the case on your ser ies, rcc_is_clk_ready() + * bit 17. If that's not the case on your series, rcc_is_clk_ready() * won't work for you. */ /* Returns the RCC register which controls the clock source. */ -- cgit v1.2.3 From e4a64648af9923e408be49ac3cb7083215d83efd Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:18:30 -0400 Subject: RCC: Doxygen Various changes to Doxygen structure, to help leaflabs-docs make sense of everything. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 53 +++++++++++++++++---- libmaple/stm32f1/include/series/rcc.h | 88 +++++++++++++++++------------------ libmaple/stm32f1/rcc.c | 40 +--------------- libmaple/stm32f2/include/series/rcc.h | 36 ++++++-------- libmaple/stm32f2/rcc.c | 26 +---------- 5 files changed, 105 insertions(+), 138 deletions(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 9ed12bc..3055bb4 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -77,11 +77,26 @@ typedef enum rcc_sysclk_src { * * - enum rcc_prescaler: And a suitable set of dividers for * rcc_set_prescaler(). + * + * - enum rcc_pllsrc: For each PLL source. Same source, same token. + * + * - A target-dependent type to be pointed to by the data field in a + * struct rcc_pll_cfg. */ +#ifdef __DOXYGEN__ +/* RCC register map base pointer */ +#define RCC_BASE +#endif + /* Clock prescaler management. */ -void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); +/** + * @brief Set the divider on a peripheral prescaler + * @param prescaler prescaler to set + * @param divider prescaler divider + */ +extern void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider); /* SYSCLK. */ @@ -94,13 +109,20 @@ void rcc_switch_sysclk(rcc_sysclk_src sysclk_src); */ typedef struct rcc_pll_cfg { rcc_pllsrc pllsrc; /**< PLL source */ - void *data; /**< Series-specific configuration - * data. See the for your - * MCU for more information on what to put - * here. */ + + /** Series-specific configuration data. */ + void *data; } rcc_pll_cfg; -void rcc_configure_pll(rcc_pll_cfg *pll_cfg); +/** + * @brief Configure the main PLL. + * + * You may only call this function while the PLL is disabled. + * + * @param pll_cfg Desired PLL configuration. The contents of this + * struct depend entirely on the target. + */ +extern void rcc_configure_pll(rcc_pll_cfg *pll_cfg); /* System and secondary clock sources. */ @@ -111,8 +133,23 @@ int rcc_is_clk_ready(rcc_clk clock); /* Peripheral clock lines and clock domains. */ -void rcc_clk_enable(rcc_clk_id id); -void rcc_reset_dev(rcc_clk_id id); +/** + * @brief Turn on the clock line on a peripheral + * @param id Clock ID of the peripheral to turn on. + */ +extern void rcc_clk_enable(rcc_clk_id id); + +/** + * @brief Reset a peripheral. + * + * Caution: not all rcc_clk_id values refer to a peripheral which can + * be reset. (Only rcc_clk_ids for peripherals with bits in an RCC + * reset register can be used here.) + * + * @param id Clock ID of the peripheral to reset. + */ +extern void rcc_reset_dev(rcc_clk_id id); + rcc_clk_domain rcc_dev_clk(rcc_clk_id id); /* Clock security system */ diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index 3e7f7c6..c20d5d6 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -43,7 +43,7 @@ extern "C"{ * Register map */ -/** RCC register map type */ +/** STM32F1 RCC register map type */ typedef struct rcc_reg_map { __io uint32 CR; /**< Clock control register */ __io uint32 CFGR; /**< Clock configuration register */ @@ -57,7 +57,6 @@ typedef struct rcc_reg_map { __io uint32 CSR; /**< Control/status register */ } rcc_reg_map; -/** RCC register map base pointer */ #define RCC_BASE ((struct rcc_reg_map*)0x40021000) /* @@ -389,10 +388,7 @@ typedef struct rcc_reg_map { */ /** - * @brief Identifies bus and clock line for a peripheral. - * - * Also generally useful as a unique identifier for that peripheral - * (or its corresponding device struct). + * @brief STM32F1 rcc_clk_id. */ typedef enum rcc_clk_id { RCC_GPIOA, @@ -444,28 +440,7 @@ typedef enum rcc_clk_id { } rcc_clk_id; /** - * @brief Deprecated PLL multipliers, for rcc_clk_init(). - */ -typedef enum rcc_pll_multiplier { - RCC_PLLMUL_2 = (0x0 << 18), - RCC_PLLMUL_3 = (0x1 << 18), - RCC_PLLMUL_4 = (0x2 << 18), - RCC_PLLMUL_5 = (0x3 << 18), - RCC_PLLMUL_6 = (0x4 << 18), - RCC_PLLMUL_7 = (0x5 << 18), - RCC_PLLMUL_8 = (0x6 << 18), - RCC_PLLMUL_9 = (0x7 << 18), - RCC_PLLMUL_10 = (0x8 << 18), - RCC_PLLMUL_11 = (0x9 << 18), - RCC_PLLMUL_12 = (0xA << 18), - RCC_PLLMUL_13 = (0xB << 18), - RCC_PLLMUL_14 = (0xC << 18), - RCC_PLLMUL_15 = (0xD << 18), - RCC_PLLMUL_16 = (0xE << 18), -} rcc_pll_multiplier; - -/** - * @brief PLL clock sources. + * @brief STM32F1 PLL clock sources. * @see rcc_configure_pll() */ typedef enum rcc_pllsrc { @@ -473,6 +448,10 @@ typedef enum rcc_pllsrc { RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16) } rcc_pllsrc; +/** + * @brief STM32F1 clock domains. + * @see rcc_dev_clk() + */ typedef enum rcc_clk_domain { RCC_APB1, RCC_APB2, @@ -480,7 +459,7 @@ typedef enum rcc_clk_domain { } rcc_clk_domain; /** - * Prescaler identifiers + * @brief STM32F1 Prescaler identifiers * @see rcc_set_prescaler() */ typedef enum rcc_prescaler { @@ -492,7 +471,7 @@ typedef enum rcc_prescaler { } rcc_prescaler; /** - * ADC prescaler dividers + * @brief STM32F1 ADC prescaler dividers * @see rcc_set_prescaler() */ typedef enum rcc_adc_divider { @@ -503,7 +482,7 @@ typedef enum rcc_adc_divider { } rcc_adc_divider; /** - * APB1 prescaler dividers + * @brief STM32F1 APB1 prescaler dividers * @see rcc_set_prescaler() */ typedef enum rcc_apb1_divider { @@ -515,7 +494,7 @@ typedef enum rcc_apb1_divider { } rcc_apb1_divider; /** - * APB2 prescaler dividers + * @brief STM32F1 APB2 prescaler dividers * @see rcc_set_prescaler() */ typedef enum rcc_apb2_divider { @@ -527,7 +506,7 @@ typedef enum rcc_apb2_divider { } rcc_apb2_divider; /** - * AHB prescaler dividers + * @brief STM32F1 AHB prescaler dividers * @see rcc_set_prescaler() */ typedef enum rcc_ahb_divider { @@ -544,7 +523,7 @@ typedef enum rcc_ahb_divider { } rcc_ahb_divider; /** - * @brief Available clock sources. + * @brief STM32F1 clock sources. */ typedef enum rcc_clk { RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | @@ -562,26 +541,45 @@ typedef enum rcc_clk { * (approximately 32 KHz). */ } rcc_clk; -/* - * Series-specific functionality. +/** + * @brief STM32F1 PLL multipliers. */ - -__deprecated -void rcc_clk_init(rcc_sysclk_src sysclk_src, - rcc_pllsrc pll_src, - rcc_pll_multiplier pll_mul); +typedef enum rcc_pll_multiplier { + RCC_PLLMUL_2 = (0x0 << 18), + RCC_PLLMUL_3 = (0x1 << 18), + RCC_PLLMUL_4 = (0x2 << 18), + RCC_PLLMUL_5 = (0x3 << 18), + RCC_PLLMUL_6 = (0x4 << 18), + RCC_PLLMUL_7 = (0x5 << 18), + RCC_PLLMUL_8 = (0x6 << 18), + RCC_PLLMUL_9 = (0x7 << 18), + RCC_PLLMUL_10 = (0x8 << 18), + RCC_PLLMUL_11 = (0x9 << 18), + RCC_PLLMUL_12 = (0xA << 18), + RCC_PLLMUL_13 = (0xB << 18), + RCC_PLLMUL_14 = (0xC << 18), + RCC_PLLMUL_15 = (0xD << 18), + RCC_PLLMUL_16 = (0xE << 18), +} rcc_pll_multiplier; /** - * @brief STM32F1-specific PLL configuration values. - * - * Use this as the "data" field in a struct rcc_pll_cfg. - * + * @brief STM32F1 PLL configuration values. + * Point to one of these with the "data" field in a struct rcc_pll_cfg. * @see struct rcc_pll_cfg. */ typedef struct stm32f1_rcc_pll_data { rcc_pll_multiplier pll_mul; /**< PLL multiplication factor. */ } stm32f1_rcc_pll_data; +/* + * Deprecated bits. + */ + +__deprecated +void rcc_clk_init(rcc_sysclk_src sysclk_src, + rcc_pllsrc pll_src, + rcc_pll_multiplier pll_mul); + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index ca81755..a83bea3 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -96,23 +96,11 @@ const struct rcc_dev_info rcc_dev_table[] = { }; /** - * @brief Deprecated. + * @brief Deprecated; STM32F1 only. * * Initialize the clock control system. Initializes the system * clock source to use the PLL driven by an external oscillator. * - * This function is limited and nonportable. Instead of using it, - * follow this (portable) procedure: - * - * 1. Switch to HSI by calling rcc_switch_sysclk(RCC_CLKSRC_HSI). - * 2. Turn off HSE by calling rcc_turn_off_clk(RCC_CLK_HSE). - * 3. Turn off the PLL by calling rcc_turn_off_clk(RCC_CLK_HSE). - * 4. Reconfigure the PLL using rcc_configure_pll(). - * 5. Turn on RCC_CLK_HSE using rcc_turn_on_clk() and wait for it to - * become ready by busy-waiting on rcc_is_clk_ready(). - * 6. Turn on RCC_CLK_PLL using the same methods. - * 7. Switch to the PLL with rcc_switch_sysclk(RCC_CLKSRC_PLL). - * * @param sysclk_src system clock source, must be PLL * @param pll_src pll clock source, must be HSE * @param pll_mul pll multiplier @@ -141,14 +129,7 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_switch_sysclk(RCC_CLKSRC_PLL); } -/** - * @brief Configure the main PLL. - * - * You may only call this function while the PLL is disabled. - * - * @param pll_cfg Desired PLL configuration. The data field must point - * to a valid struct stm32f1_rcc_pll_data. - */ +/* pll_cfg->data must point to a valid struct stm32f1_rcc_pll_data. */ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { stm32f1_rcc_pll_data *data = pll_cfg->data; rcc_pll_multiplier pll_mul = data->pll_mul; @@ -163,10 +144,6 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { RCC_BASE->CFGR = cfgr; } -/** - * @brief Turn on the clock line on a peripheral - * @param id Clock ID of the peripheral to turn on. - */ void rcc_clk_enable(rcc_clk_id id) { static __io uint32* enable_regs[] = { [APB1] = &RCC_BASE->APB1ENR, @@ -176,14 +153,6 @@ void rcc_clk_enable(rcc_clk_id id) { rcc_do_clk_enable(enable_regs, id); } -/** - * @brief Reset a peripheral. - * - * Caution: not all rcc_clk_id values refer to a peripheral which can - * be reset. - * - * @param id Clock ID of the peripheral to reset. - */ void rcc_reset_dev(rcc_clk_id id) { static __io uint32* reset_regs[] = { [APB1] = &RCC_BASE->APB1RSTR, @@ -192,11 +161,6 @@ void rcc_reset_dev(rcc_clk_id id) { rcc_do_reset_dev(reset_regs, id); } -/** - * @brief Set the divider on a peripheral prescaler - * @param prescaler prescaler to set - * @param divider prescaler divider - */ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { static const uint32 masks[] = { [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE, diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 9c3fdd5..52f6b4a 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -49,7 +49,7 @@ extern "C"{ * Register map */ -/** RCC register map type */ +/** STM32F1 RCC register map type */ typedef struct rcc_reg_map { __io uint32 CR; /**< Clock control register */ __io uint32 PLLCFGR; /**< PLL configuration register */ @@ -93,7 +93,6 @@ typedef struct rcc_reg_map { __io uint32 PLLI2SCFGR; /**< PLLI2S configuration register */ } rcc_reg_map; -/* RCC register map base pointer */ #define RCC_BASE ((struct rcc_reg_map*)0x40023800) /* @@ -742,7 +741,7 @@ typedef struct rcc_reg_map { */ /** - * @brief Available clock sources. + * @brief STM32F2 clock sources. */ typedef enum rcc_clk { RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) | @@ -764,8 +763,7 @@ typedef enum rcc_clk { } rcc_clk; /** - * @brief Identifies bus and clock line for a peripheral or peripheral - * clock. + * @brief STM32F2 rcc_clk_id. */ typedef enum rcc_clk_id { RCC_OTGHSULPI, @@ -832,7 +830,7 @@ typedef enum rcc_clk_id { } rcc_clk_id; /** - * @brief PLL entry clock source + * @brief STM32F2 PLL entry clock source * @see rcc_configure_pll() */ typedef enum rcc_pllsrc { @@ -841,7 +839,7 @@ typedef enum rcc_pllsrc { } rcc_pllsrc; /** - * @brief Peripheral clock domains. + * @brief STM32F2 Peripheral clock domains. */ typedef enum rcc_clk_domain { RCC_APB1, @@ -856,7 +854,7 @@ typedef enum rcc_clk_domain { */ /** - * @brief Prescaler identifiers. + * @brief STM32F2 Prescaler identifiers. */ typedef enum rcc_prescaler { RCC_PRESCALER_MCO2, @@ -868,7 +866,7 @@ typedef enum rcc_prescaler { } rcc_prescaler; /** - * @brief MCO2 prescaler dividers. + * @brief STM32F2 MCO2 prescaler dividers. */ typedef enum rcc_mco2_divider { RCC_MCO2_DIV_1 = RCC_CFGR_MCO2PRE_DIV_1, @@ -879,7 +877,7 @@ typedef enum rcc_mco2_divider { } rcc_mco2_divider; /** - * @brief MCO1 prescaler dividers. + * @brief STM32F2 MCO1 prescaler dividers. */ typedef enum rcc_mco1_divider { RCC_MCO1_DIV_1 = RCC_CFGR_MCO1PRE_DIV_1, @@ -890,14 +888,14 @@ typedef enum rcc_mco1_divider { } rcc_mco1_divider; /** - * @brief RTC prescaler dividers. + * @brief STM32F2 RTC prescaler dividers. */ typedef enum rcc_rtc_divider { /* TODO */ RCC_RTC_DIV_TODO = 0xFFFFFFFF, } rcc_rtc_divider; /** - * @brief AP2 prescaler dividers. + * @brief STM32F2 AP2 prescaler dividers. */ typedef enum rcc_apb2_divider { RCC_APB2_HCLK_DIV_1 = 0, @@ -908,7 +906,7 @@ typedef enum rcc_apb2_divider { } rcc_apb2_divider; /** - * @brief AP1 prescaler dividers. + * @brief STM32F2 APB1 prescaler dividers. */ typedef enum rcc_apb1_divider { RCC_APB1_HCLK_DIV_1 = 0, @@ -919,7 +917,7 @@ typedef enum rcc_apb1_divider { } rcc_apb1_divider; /** - * @brief AHB prescaler dividers. + * @brief STM32F2 AHB prescaler dividers. */ typedef enum rcc_ahb_divider { RCC_AHB_SYSCLK_DIV_1 = 0, @@ -933,15 +931,9 @@ typedef enum rcc_ahb_divider { RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512, } rcc_ahb_divider; -/* - * Series-specific PLL configuration. - */ - /** - * @brief STM32F2-specific PLL configuration values. - * - * Use this as the "data" field in a struct rcc_pll_cfg. - * + * @brief STM32F2 PLL configuration values. + * Point to one of these with the "data" field in a struct rcc_pll_cfg. * @see struct rcc_pll_cfg. */ typedef struct stm32f2_rcc_pll_data { diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c index a13e56d..7fc7eb0 100644 --- a/libmaple/stm32f2/rcc.c +++ b/libmaple/stm32f2/rcc.c @@ -110,10 +110,6 @@ const struct rcc_dev_info rcc_dev_table[] = { [RCC_TIMER1] = DEV_ENTRY(APB2, TIM1), }; -/** - * @brief Turn on the clock line on a peripheral - * @param id Clock ID of the peripheral to turn on. - */ void rcc_clk_enable(rcc_clk_id id) { static __io uint32* enable_regs[] = { [RCC_AHB1] = &RCC_BASE->AHB1ENR, @@ -125,14 +121,6 @@ void rcc_clk_enable(rcc_clk_id id) { rcc_do_clk_enable(enable_regs, id); } -/** - * @brief Reset a peripheral. - * - * Caution: not all rcc_clk_id values refer to a peripheral which can - * be reset. - * - * @param id Clock ID of the peripheral to reset. - */ void rcc_reset_dev(rcc_clk_id id) { static __io uint32* reset_regs[] = { [RCC_AHB1] = &RCC_BASE->AHB1RSTR, @@ -144,11 +132,6 @@ void rcc_reset_dev(rcc_clk_id id) { rcc_do_reset_dev(reset_regs, id); } -/** - * @brief Set the divider on a peripheral prescaler - * @param prescaler prescaler to set - * @param divider prescaler divider - */ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { static const uint32 masks[] = { [RCC_PRESCALER_MCO2] = RCC_CFGR_MCO2PRE, @@ -161,14 +144,7 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) { rcc_do_set_prescaler(masks, prescaler, divider); } -/** - * @brief Configure the main PLL. - * - * You may only call this function while the PLL is disabled. - * - * @param pll_cfg Desired PLL configuration. The data field must point - * to a valid struct stm32f2_rcc_pll_data. - */ +/* pll_cfg->data must point to a struct stm32f2_rcc_pll_data. */ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) { stm32f2_rcc_pll_data *data = pll_cfg->data; uint32 pllcfgr; -- cgit v1.2.3 From f6e0a0e8e63e576d7f6c0194d13ec24c5a907363 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:18:48 -0400 Subject: stm32f1/rcc.h: Add a FIXME. Having a separate struct is stupid. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/rcc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index c20d5d6..4df88ea 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -562,6 +562,8 @@ typedef enum rcc_pll_multiplier { RCC_PLLMUL_16 = (0xE << 18), } rcc_pll_multiplier; +/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */ + /** * @brief STM32F1 PLL configuration values. * Point to one of these with the "data" field in a struct rcc_pll_cfg. -- cgit v1.2.3 From 5eda0127524f60d4e09dc8213e042915e22351f7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:49:17 -0400 Subject: Doxyfile: Add to PREDEFINED to cover libmaple_types.h. Signed-off-by: Marti Bolivar --- support/doxygen/Doxyfile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/support/doxygen/Doxyfile b/support/doxygen/Doxyfile index 1074403..daeaf38 100644 --- a/support/doxygen/Doxyfile +++ b/support/doxygen/Doxyfile @@ -1375,6 +1375,10 @@ INCLUDE_FILE_PATTERNS = # instead of the = operator. PREDEFINED = __attribute__()= \ + __deprecated= \ + __always_inline= \ + __packed = \ + __weak = \ __cplusplus \ STM32_MEDIUM_DENSITY \ STM32_HIGH_DENSITY \ -- cgit v1.2.3 From 0128564f414ce05b37bd3f68d5d981a46e70a069 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:49:35 -0400 Subject: stm32f2/rcc.h: Fix typo. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 52f6b4a..7d02d0d 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -49,7 +49,7 @@ extern "C"{ * Register map */ -/** STM32F1 RCC register map type */ +/** STM32F2 RCC register map type */ typedef struct rcc_reg_map { __io uint32 CR; /**< Clock control register */ __io uint32 PLLCFGR; /**< PLL configuration register */ -- cgit v1.2.3 From 6873ac2ce3b912c83922d91438c8f467a32b392a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:50:05 -0400 Subject: stm32f2/rcc.h: Add FIXME for rcc_rtc_divider. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 7d02d0d..d2fd54d 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -890,7 +890,7 @@ typedef enum rcc_mco1_divider { /** * @brief STM32F2 RTC prescaler dividers. */ -typedef enum rcc_rtc_divider { /* TODO */ +typedef enum rcc_rtc_divider { /* FIXME [0.0.13] TODO */ RCC_RTC_DIV_TODO = 0xFFFFFFFF, } rcc_rtc_divider; -- cgit v1.2.3 From 1995b6555b1f801ff37e541f9484490eda85046b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:50:18 -0400 Subject: stm32f2/rcc.h: Remove a TODO. That never worked out. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/rcc.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index d2fd54d..e5a6e3e 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -29,13 +29,6 @@ * @brief STM32F2 reset and clock control (RCC) support. */ -/* - * TODO: - * - * - Can prescaler enums be merged with F1's into - * (perhaps by adding more register bit definitions to F1 header)? - */ - #ifndef _LIBMAPLE_STM32F2_RCC_H_ #define _LIBMAPLE_STM32F2_RCC_H_ -- cgit v1.2.3 From 86a85bc5f1091a8c0ec59d4598a983410bd5cf33 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:50:27 -0400 Subject: libmaple/rcc.h: Doxygen. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/rcc.h b/libmaple/include/libmaple/rcc.h index 3055bb4..ea16803 100644 --- a/libmaple/include/libmaple/rcc.h +++ b/libmaple/include/libmaple/rcc.h @@ -85,7 +85,7 @@ typedef enum rcc_sysclk_src { */ #ifdef __DOXYGEN__ -/* RCC register map base pointer */ +/** RCC register map base pointer */ #define RCC_BASE #endif -- cgit v1.2.3 From b8334558def9b7efd3cd35fe125ac046b1772a5b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 14:50:36 -0400 Subject: libmaple/rcc.c: Fix typo. Signed-off-by: Marti Bolivar --- libmaple/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/rcc.c b/libmaple/rcc.c index 7b7be0d..8e7d1ea 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -113,7 +113,7 @@ static inline uint32 rcc_clk_ready_mask(rcc_clk clock) { /** * @brief Turn on a clock source. * - * After this routine exists, callers should ensure that the clock + * After this routine exits, callers should ensure that the clock * source is ready by waiting until rcc_is_clk_ready(clock) returns * true. * -- cgit v1.2.3 From 2c685cef97ed6eeabf793abc55d1d18e194d8e80 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 16:43:25 -0400 Subject: series/rcc.h: Lose BIT(). Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/rcc.h | 274 ++++++++++---------- libmaple/stm32f2/include/series/rcc.h | 456 +++++++++++++++++----------------- 2 files changed, 370 insertions(+), 360 deletions(-) diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index 4df88ea..e6afe0e 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -37,7 +37,7 @@ extern "C"{ #endif -#include +#include /* * Register map @@ -74,16 +74,16 @@ typedef struct rcc_reg_map { #define RCC_CR_HSIRDY_BIT 1 #define RCC_CR_HSION_BIT 0 -#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) -#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) -#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) -#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) -#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) -#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) +#define RCC_CR_PLLRDY (1U << RCC_CR_PLLRDY_BIT) +#define RCC_CR_PLLON (1U << RCC_CR_PLLON_BIT) +#define RCC_CR_CSSON (1U << RCC_CR_CSSON_BIT) +#define RCC_CR_HSEBYP (1U << RCC_CR_HSEBYP_BIT) +#define RCC_CR_HSERDY (1U << RCC_CR_HSERDY_BIT) +#define RCC_CR_HSEON (1U << RCC_CR_HSEON_BIT) #define RCC_CR_HSICAL (0xFF << 8) #define RCC_CR_HSITRIM (0x1F << 3) -#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) -#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) +#define RCC_CR_HSIRDY (1U << RCC_CR_HSIRDY_BIT) +#define RCC_CR_HSION (1U << RCC_CR_HSION_BIT) /* Clock configuration register */ @@ -92,10 +92,10 @@ typedef struct rcc_reg_map { #define RCC_CFGR_PLLSRC_BIT 16 #define RCC_CFGR_MCO (0x3 << 24) -#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT) +#define RCC_CFGR_USBPRE (1U << RCC_CFGR_USBPRE_BIT) #define RCC_CFGR_PLLMUL (0xF << 18) -#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT) -#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT) +#define RCC_CFGR_PLLXTPRE (1U << RCC_CFGR_PLLXTPRE_BIT) +#define RCC_CFGR_PLLSRC (1U << RCC_CFGR_PLLSRC_BIT) #define RCC_CFGR_ADCPRE (0x3 << 14) #define RCC_CFGR_PPRE2 (0x7 << 11) #define RCC_CFGR_PPRE1 (0x7 << 8) @@ -127,23 +127,23 @@ typedef struct rcc_reg_map { #define RCC_CIR_LSERDYF_BIT 1 #define RCC_CIR_LSIRDYF_BIT 0 -#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) -#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) -#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) -#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) -#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) -#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) -#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) -#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) -#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) -#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) -#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) -#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) -#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) -#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) -#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) -#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) -#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) +#define RCC_CIR_CSSC (1U << RCC_CIR_CSSC_BIT) +#define RCC_CIR_PLLRDYC (1U << RCC_CIR_PLLRDYC_BIT) +#define RCC_CIR_HSERDYC (1U << RCC_CIR_HSERDYC_BIT) +#define RCC_CIR_HSIRDYC (1U << RCC_CIR_HSIRDYC_BIT) +#define RCC_CIR_LSERDYC (1U << RCC_CIR_LSERDYC_BIT) +#define RCC_CIR_LSIRDYC (1U << RCC_CIR_LSIRDYC_BIT) +#define RCC_CIR_PLLRDYIE (1U << RCC_CIR_PLLRDYIE_BIT) +#define RCC_CIR_HSERDYIE (1U << RCC_CIR_HSERDYIE_BIT) +#define RCC_CIR_HSIRDYIE (1U << RCC_CIR_HSIRDYIE_BIT) +#define RCC_CIR_LSERDYIE (1U << RCC_CIR_LSERDYIE_BIT) +#define RCC_CIR_LSIRDYIE (1U << RCC_CIR_LSIRDYIE_BIT) +#define RCC_CIR_CSSF (1U << RCC_CIR_CSSF_BIT) +#define RCC_CIR_PLLRDYF (1U << RCC_CIR_PLLRDYF_BIT) +#define RCC_CIR_HSERDYF (1U << RCC_CIR_HSERDYF_BIT) +#define RCC_CIR_HSIRDYF (1U << RCC_CIR_HSIRDYF_BIT) +#define RCC_CIR_LSERDYF (1U << RCC_CIR_LSERDYF_BIT) +#define RCC_CIR_LSIRDYF (1U << RCC_CIR_LSIRDYF_BIT) /* APB2 peripheral reset register */ @@ -166,24 +166,24 @@ typedef struct rcc_reg_map { #define RCC_APB2RSTR_IOPARST_BIT 2 #define RCC_APB2RSTR_AFIORST_BIT 0 -#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) -#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) -#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) -#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT) -#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) -#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) -#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) -#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) -#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT) -#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT) -#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT) -#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT) -#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT) -#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT) -#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT) -#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT) -#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT) -#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT) +#define RCC_APB2RSTR_TIM11RST (1U << RCC_APB2RSTR_TIM11RST_BIT) +#define RCC_APB2RSTR_TIM10RST (1U << RCC_APB2RSTR_TIM10RST_BIT) +#define RCC_APB2RSTR_TIM9RST (1U << RCC_APB2RSTR_TIM9RST_BIT) +#define RCC_APB2RSTR_ADC3RST (1U << RCC_APB2RSTR_ADC3RST_BIT) +#define RCC_APB2RSTR_USART1RST (1U << RCC_APB2RSTR_USART1RST_BIT) +#define RCC_APB2RSTR_TIM8RST (1U << RCC_APB2RSTR_TIM8RST_BIT) +#define RCC_APB2RSTR_SPI1RST (1U << RCC_APB2RSTR_SPI1RST_BIT) +#define RCC_APB2RSTR_TIM1RST (1U << RCC_APB2RSTR_TIM1RST_BIT) +#define RCC_APB2RSTR_ADC2RST (1U << RCC_APB2RSTR_ADC2RST_BIT) +#define RCC_APB2RSTR_ADC1RST (1U << RCC_APB2RSTR_ADC1RST_BIT) +#define RCC_APB2RSTR_IOPGRST (1U << RCC_APB2RSTR_IOPGRST_BIT) +#define RCC_APB2RSTR_IOPFRST (1U << RCC_APB2RSTR_IOPFRST_BIT) +#define RCC_APB2RSTR_IOPERST (1U << RCC_APB2RSTR_IOPERST_BIT) +#define RCC_APB2RSTR_IOPDRST (1U << RCC_APB2RSTR_IOPDRST_BIT) +#define RCC_APB2RSTR_IOPCRST (1U << RCC_APB2RSTR_IOPCRST_BIT) +#define RCC_APB2RSTR_IOPBRST (1U << RCC_APB2RSTR_IOPBRST_BIT) +#define RCC_APB2RSTR_IOPARST (1U << RCC_APB2RSTR_IOPARST_BIT) +#define RCC_APB2RSTR_AFIORST (1U << RCC_APB2RSTR_AFIORST_BIT) /* APB1 peripheral reset register */ @@ -211,29 +211,29 @@ typedef struct rcc_reg_map { #define RCC_APB1RSTR_TIM3RST_BIT 1 #define RCC_APB1RSTR_TIM2RST_BIT 0 -#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) -#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) -#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT) -#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT) -#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT) -#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) -#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) -#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) -#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) -#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT) -#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT) -#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) -#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) -#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT) -#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) -#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) -#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) -#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) -#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) -#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) -#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) -#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) -#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) +#define RCC_APB1RSTR_DACRST (1U << RCC_APB1RSTR_DACRST_BIT) +#define RCC_APB1RSTR_PWRRST (1U << RCC_APB1RSTR_PWRRST_BIT) +#define RCC_APB1RSTR_BKPRST (1U << RCC_APB1RSTR_BKPRST_BIT) +#define RCC_APB1RSTR_CANRST (1U << RCC_APB1RSTR_CANRST_BIT) +#define RCC_APB1RSTR_USBRST (1U << RCC_APB1RSTR_USBRST_BIT) +#define RCC_APB1RSTR_I2C2RST (1U << RCC_APB1RSTR_I2C2RST_BIT) +#define RCC_APB1RSTR_I2C1RST (1U << RCC_APB1RSTR_I2C1RST_BIT) +#define RCC_APB1RSTR_UART5RST (1U << RCC_APB1RSTR_UART5RST_BIT) +#define RCC_APB1RSTR_UART4RST (1U << RCC_APB1RSTR_UART4RST_BIT) +#define RCC_APB1RSTR_USART3RST (1U << RCC_APB1RSTR_USART3RST_BIT) +#define RCC_APB1RSTR_USART2RST (1U << RCC_APB1RSTR_USART2RST_BIT) +#define RCC_APB1RSTR_SPI3RST (1U << RCC_APB1RSTR_SPI3RST_BIT) +#define RCC_APB1RSTR_SPI2RST (1U << RCC_APB1RSTR_SPI2RST_BIT) +#define RCC_APB1RSTR_WWDRST (1U << RCC_APB1RSTR_WWDRST_BIT) +#define RCC_APB1RSTR_TIM14RST (1U << RCC_APB1RSTR_TIM14RST_BIT) +#define RCC_APB1RSTR_TIM13RST (1U << RCC_APB1RSTR_TIM13RST_BIT) +#define RCC_APB1RSTR_TIM12RST (1U << RCC_APB1RSTR_TIM12RST_BIT) +#define RCC_APB1RSTR_TIM7RST (1U << RCC_APB1RSTR_TIM7RST_BIT) +#define RCC_APB1RSTR_TIM6RST (1U << RCC_APB1RSTR_TIM6RST_BIT) +#define RCC_APB1RSTR_TIM5RST (1U << RCC_APB1RSTR_TIM5RST_BIT) +#define RCC_APB1RSTR_TIM4RST (1U << RCC_APB1RSTR_TIM4RST_BIT) +#define RCC_APB1RSTR_TIM3RST (1U << RCC_APB1RSTR_TIM3RST_BIT) +#define RCC_APB1RSTR_TIM2RST (1U << RCC_APB1RSTR_TIM2RST_BIT) /* AHB peripheral clock enable register */ @@ -245,13 +245,13 @@ typedef struct rcc_reg_map { #define RCC_AHBENR_DMA2EN_BIT 1 #define RCC_AHBENR_DMA1EN_BIT 0 -#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT) -#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT) -#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT) -#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT) -#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT) -#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT) -#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT) +#define RCC_AHBENR_SDIOEN (1U << RCC_AHBENR_SDIOEN_BIT) +#define RCC_AHBENR_FSMCEN (1U << RCC_AHBENR_FSMCEN_BIT) +#define RCC_AHBENR_CRCEN (1U << RCC_AHBENR_CRCEN_BIT) +#define RCC_AHBENR_FLITFEN (1U << RCC_AHBENR_FLITFEN_BIT) +#define RCC_AHBENR_SRAMEN (1U << RCC_AHBENR_SRAMEN_BIT) +#define RCC_AHBENR_DMA2EN (1U << RCC_AHBENR_DMA2EN_BIT) +#define RCC_AHBENR_DMA1EN (1U << RCC_AHBENR_DMA1EN_BIT) /* APB2 peripheral clock enable register */ @@ -274,24 +274,24 @@ typedef struct rcc_reg_map { #define RCC_APB2ENR_IOPAEN_BIT 2 #define RCC_APB2ENR_AFIOEN_BIT 0 -#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) -#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) -#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) -#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) -#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) -#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) -#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) -#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) -#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) -#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) -#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT) -#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT) -#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT) -#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT) -#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT) -#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT) -#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT) -#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT) +#define RCC_APB2ENR_TIM11EN (1U << RCC_APB2ENR_TIM11EN_BIT) +#define RCC_APB2ENR_TIM10EN (1U << RCC_APB2ENR_TIM10EN_BIT) +#define RCC_APB2ENR_TIM9EN (1U << RCC_APB2ENR_TIM9EN_BIT) +#define RCC_APB2ENR_ADC3EN (1U << RCC_APB2ENR_ADC3EN_BIT) +#define RCC_APB2ENR_USART1EN (1U << RCC_APB2ENR_USART1EN_BIT) +#define RCC_APB2ENR_TIM8EN (1U << RCC_APB2ENR_TIM8EN_BIT) +#define RCC_APB2ENR_SPI1EN (1U << RCC_APB2ENR_SPI1EN_BIT) +#define RCC_APB2ENR_TIM1EN (1U << RCC_APB2ENR_TIM1EN_BIT) +#define RCC_APB2ENR_ADC2EN (1U << RCC_APB2ENR_ADC2EN_BIT) +#define RCC_APB2ENR_ADC1EN (1U << RCC_APB2ENR_ADC1EN_BIT) +#define RCC_APB2ENR_IOPGEN (1U << RCC_APB2ENR_IOPGEN_BIT) +#define RCC_APB2ENR_IOPFEN (1U << RCC_APB2ENR_IOPFEN_BIT) +#define RCC_APB2ENR_IOPEEN (1U << RCC_APB2ENR_IOPEEN_BIT) +#define RCC_APB2ENR_IOPDEN (1U << RCC_APB2ENR_IOPDEN_BIT) +#define RCC_APB2ENR_IOPCEN (1U << RCC_APB2ENR_IOPCEN_BIT) +#define RCC_APB2ENR_IOPBEN (1U << RCC_APB2ENR_IOPBEN_BIT) +#define RCC_APB2ENR_IOPAEN (1U << RCC_APB2ENR_IOPAEN_BIT) +#define RCC_APB2ENR_AFIOEN (1U << RCC_APB2ENR_AFIOEN_BIT) /* APB1 peripheral clock enable register */ @@ -319,29 +319,29 @@ typedef struct rcc_reg_map { #define RCC_APB1ENR_TIM3EN_BIT 1 #define RCC_APB1ENR_TIM2EN_BIT 0 -#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) -#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) -#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT) -#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT) -#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT) -#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) -#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) -#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) -#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) -#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) -#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) -#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) -#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) -#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT) -#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) -#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) -#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) -#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) -#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) -#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) -#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) -#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) -#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) +#define RCC_APB1ENR_DACEN (1U << RCC_APB1ENR_DACEN_BIT) +#define RCC_APB1ENR_PWREN (1U << RCC_APB1ENR_PWREN_BIT) +#define RCC_APB1ENR_BKPEN (1U << RCC_APB1ENR_BKPEN_BIT) +#define RCC_APB1ENR_CANEN (1U << RCC_APB1ENR_CANEN_BIT) +#define RCC_APB1ENR_USBEN (1U << RCC_APB1ENR_USBEN_BIT) +#define RCC_APB1ENR_I2C2EN (1U << RCC_APB1ENR_I2C2EN_BIT) +#define RCC_APB1ENR_I2C1EN (1U << RCC_APB1ENR_I2C1EN_BIT) +#define RCC_APB1ENR_UART5EN (1U << RCC_APB1ENR_UART5EN_BIT) +#define RCC_APB1ENR_UART4EN (1U << RCC_APB1ENR_UART4EN_BIT) +#define RCC_APB1ENR_USART3EN (1U << RCC_APB1ENR_USART3EN_BIT) +#define RCC_APB1ENR_USART2EN (1U << RCC_APB1ENR_USART2EN_BIT) +#define RCC_APB1ENR_SPI3EN (1U << RCC_APB1ENR_SPI3EN_BIT) +#define RCC_APB1ENR_SPI2EN (1U << RCC_APB1ENR_SPI2EN_BIT) +#define RCC_APB1ENR_WWDEN (1U << RCC_APB1ENR_WWDEN_BIT) +#define RCC_APB1ENR_TIM14EN (1U << RCC_APB1ENR_TIM14EN_BIT) +#define RCC_APB1ENR_TIM13EN (1U << RCC_APB1ENR_TIM13EN_BIT) +#define RCC_APB1ENR_TIM12EN (1U << RCC_APB1ENR_TIM12EN_BIT) +#define RCC_APB1ENR_TIM7EN (1U << RCC_APB1ENR_TIM7EN_BIT) +#define RCC_APB1ENR_TIM6EN (1U << RCC_APB1ENR_TIM6EN_BIT) +#define RCC_APB1ENR_TIM5EN (1U << RCC_APB1ENR_TIM5EN_BIT) +#define RCC_APB1ENR_TIM4EN (1U << RCC_APB1ENR_TIM4EN_BIT) +#define RCC_APB1ENR_TIM3EN (1U << RCC_APB1ENR_TIM3EN_BIT) +#define RCC_APB1ENR_TIM2EN (1U << RCC_APB1ENR_TIM2EN_BIT) /* Backup domain control register */ @@ -351,15 +351,15 @@ typedef struct rcc_reg_map { #define RCC_BDCR_LSERDY_BIT 1 #define RCC_BDCR_LSEON_BIT 0 -#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) -#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTC_BIT) +#define RCC_BDCR_BDRST (1U << RCC_BDCR_BDRST_BIT) +#define RCC_BDCR_RTCEN (1U << RCC_BDCR_RTC_BIT) #define RCC_BDCR_RTCSEL (0x3 << 8) #define RCC_BDCR_RTCSEL_NONE (0x0 << 8) #define RCC_BDCR_RTCSEL_LSE (0x1 << 8) #define RCC_BDCR_RTCSEL_HSE (0x3 << 8) -#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) -#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) -#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) +#define RCC_BDCR_LSEBYP (1U << RCC_BDCR_LSEBYP_BIT) +#define RCC_BDCR_LSERDY (1U << RCC_BDCR_LSERDY_BIT) +#define RCC_BDCR_LSEON (1U << RCC_BDCR_LSEON_BIT) /* Control/status register */ @@ -373,15 +373,15 @@ typedef struct rcc_reg_map { #define RCC_CSR_LSIRDY_BIT 1 #define RCC_CSR_LSION_BIT 0 -#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) -#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) -#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) -#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) -#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) -#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) -#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) -#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) -#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) +#define RCC_CSR_LPWRRSTF (1U << RCC_CSR_LPWRRSTF_BIT) +#define RCC_CSR_WWDGRSTF (1U << RCC_CSR_WWDGRSTF_BIT) +#define RCC_CSR_IWDGRSTF (1U << RCC_CSR_IWDGRSTF_BIT) +#define RCC_CSR_SFTRSTF (1U << RCC_CSR_SFTRSTF_BIT) +#define RCC_CSR_PORRSTF (1U << RCC_CSR_PORRSTF_BIT) +#define RCC_CSR_PINRSTF (1U << RCC_CSR_PINRSTF_BIT) +#define RCC_CSR_RMVF (1U << RCC_CSR_RMVF_BIT) +#define RCC_CSR_LSIRDY (1U << RCC_CSR_LSIRDY_BIT) +#define RCC_CSR_LSION (1U << RCC_CSR_LSION_BIT) /* * libmaple-mandated enumeration types. @@ -577,6 +577,16 @@ typedef struct stm32f1_rcc_pll_data { * Deprecated bits. */ +/** + * @brief Deprecated; STM32F1 only. + * + * Initialize the clock control system. Initializes the system + * clock source to use the PLL driven by an external oscillator. + * + * @param sysclk_src system clock source, must be PLL + * @param pll_src pll clock source, must be HSE + * @param pll_mul pll multiplier + */ __deprecated void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index e5a6e3e..1d9de85 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -36,7 +36,7 @@ extern "C"{ #endif -#include +#include /* * Register map @@ -105,25 +105,25 @@ typedef struct rcc_reg_map { #define RCC_CR_HSIRDY_BIT 1 #define RCC_CR_HSION_BIT 0 -#define RCC_CR_PLLI2SRDY BIT(RCC_CR_PLLI2SRDY_BIT) -#define RCC_CR_PLLI2SON BIT(RCC_CR_PLLI2SON_BIT) -#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT) -#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT) -#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT) -#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT) -#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT) -#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT) +#define RCC_CR_PLLI2SRDY (1U << RCC_CR_PLLI2SRDY_BIT) +#define RCC_CR_PLLI2SON (1U << RCC_CR_PLLI2SON_BIT) +#define RCC_CR_PLLRDY (1U << RCC_CR_PLLRDY_BIT) +#define RCC_CR_PLLON (1U << RCC_CR_PLLON_BIT) +#define RCC_CR_CSSON (1U << RCC_CR_CSSON_BIT) +#define RCC_CR_HSEBYP (1U << RCC_CR_HSEBYP_BIT) +#define RCC_CR_HSERDY (1U << RCC_CR_HSERDY_BIT) +#define RCC_CR_HSEON (1U << RCC_CR_HSEON_BIT) #define RCC_CR_HSICAL (0xFF << 8) #define RCC_CR_HSITRIM (0x1F << 3) -#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT) -#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT) +#define RCC_CR_HSIRDY (1U << RCC_CR_HSIRDY_BIT) +#define RCC_CR_HSION (1U << RCC_CR_HSION_BIT) /* PLL configuration register */ #define RCC_PLLCFGR_PLLSRC_BIT 22 #define RCC_PLLCFGR_PLLQ (0xF << 24) -#define RCC_PLLCFGR_PLLSRC BIT(RCC_PLLCFGR_PLLSRC_BIT) +#define RCC_PLLCFGR_PLLSRC (1U << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSI (0x0 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLSRC_HSE (0x1 << RCC_PLLCFGR_PLLSRC_BIT) #define RCC_PLLCFGR_PLLP (0x3 << 16) @@ -154,7 +154,7 @@ typedef struct rcc_reg_map { #define RCC_CFGR_MCO1PRE_DIV_4 (0x6 << 24) #define RCC_CFGR_MCO1PRE_DIV_5 (0x7 << 24) -#define RCC_CFGR_I2SSRC BIT(RCC_CFGR_I2SSRC_BIT) +#define RCC_CFGR_I2SSRC (1U << RCC_CFGR_I2SSRC_BIT) #define RCC_CFGR_I2SSRC_PLLI2S (0 << RCC_CFGR_I2SSRC_BIT) #define RCC_CFGR_I2SSRC_I2S_CKIN (1 << RCC_CFGR_I2SSRC_BIT) @@ -228,30 +228,30 @@ typedef struct rcc_reg_map { #define RCC_CIR_LSERDYF_BIT 1 #define RCC_CIR_LSIRDYF_BIT 0 -#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT) +#define RCC_CIR_CSSC (1U << RCC_CIR_CSSC_BIT) -#define RCC_CIR_PLLI2SRDYC BIT(RCC_CIR_PLLI2SRDYC_BIT) -#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT) -#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT) -#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT) -#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT) -#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT) +#define RCC_CIR_PLLI2SRDYC (1U << RCC_CIR_PLLI2SRDYC_BIT) +#define RCC_CIR_PLLRDYC (1U << RCC_CIR_PLLRDYC_BIT) +#define RCC_CIR_HSERDYC (1U << RCC_CIR_HSERDYC_BIT) +#define RCC_CIR_HSIRDYC (1U << RCC_CIR_HSIRDYC_BIT) +#define RCC_CIR_LSERDYC (1U << RCC_CIR_LSERDYC_BIT) +#define RCC_CIR_LSIRDYC (1U << RCC_CIR_LSIRDYC_BIT) -#define RCC_CIR_PLLI2SRDYIE BIT(RCC_CIR_PLLI2SRDYIE_BIT) -#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT) -#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT) -#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT) -#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT) -#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT) +#define RCC_CIR_PLLI2SRDYIE (1U << RCC_CIR_PLLI2SRDYIE_BIT) +#define RCC_CIR_PLLRDYIE (1U << RCC_CIR_PLLRDYIE_BIT) +#define RCC_CIR_HSERDYIE (1U << RCC_CIR_HSERDYIE_BIT) +#define RCC_CIR_HSIRDYIE (1U << RCC_CIR_HSIRDYIE_BIT) +#define RCC_CIR_LSERDYIE (1U << RCC_CIR_LSERDYIE_BIT) +#define RCC_CIR_LSIRDYIE (1U << RCC_CIR_LSIRDYIE_BIT) -#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT) +#define RCC_CIR_CSSF (1U << RCC_CIR_CSSF_BIT) -#define RCC_CIR_PLLI2SRDYF BIT(RCC_CIR_PLLI2SRDYF_BIT) -#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT) -#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT) -#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT) -#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT) -#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT) +#define RCC_CIR_PLLI2SRDYF (1U << RCC_CIR_PLLI2SRDYF_BIT) +#define RCC_CIR_PLLRDYF (1U << RCC_CIR_PLLRDYF_BIT) +#define RCC_CIR_HSERDYF (1U << RCC_CIR_HSERDYF_BIT) +#define RCC_CIR_HSIRDYF (1U << RCC_CIR_HSIRDYF_BIT) +#define RCC_CIR_LSERDYF (1U << RCC_CIR_LSERDYF_BIT) +#define RCC_CIR_LSIRDYF (1U << RCC_CIR_LSIRDYF_BIT) /* AHB1 peripheral reset register */ @@ -270,20 +270,20 @@ typedef struct rcc_reg_map { #define RCC_AHB1RSTR_GPIOBRST_BIT 1 #define RCC_AHB1RSTR_GPIOARST_BIT 0 -#define RCC_AHB1RSTR_OTGHSRST BIT(RCC_AHB1RSTR_OTGHSRST_BIT) -#define RCC_AHB1RSTR_ETHMACRST BIT(RCC_AHB1RSTR_ETHMACRST_BIT) -#define RCC_AHB1RSTR_DMA2RST BIT(RCC_AHB1RSTR_DMA2RST_BIT) -#define RCC_AHB1RSTR_DMA1RST BIT(RCC_AHB1RSTR_DMA1RST_BIT) -#define RCC_AHB1RSTR_CRCRST BIT(RCC_AHB1RSTR_CRCRST_BIT) -#define RCC_AHB1RSTR_GPIOIRST BIT(RCC_AHB1RSTR_GPIOIRST_BIT) -#define RCC_AHB1RSTR_GPIOHRST BIT(RCC_AHB1RSTR_GPIOHRST_BIT) -#define RCC_AHB1RSTR_GPIOGRST BIT(RCC_AHB1RSTR_GPIOGRST_BIT) -#define RCC_AHB1RSTR_GPIOFRST BIT(RCC_AHB1RSTR_GPIOFRST_BIT) -#define RCC_AHB1RSTR_GPIOERST BIT(RCC_AHB1RSTR_GPIOERST_BIT) -#define RCC_AHB1RSTR_GPIODRST BIT(RCC_AHB1RSTR_GPIODRST_BIT) -#define RCC_AHB1RSTR_GPIOCRST BIT(RCC_AHB1RSTR_GPIOCRST_BIT) -#define RCC_AHB1RSTR_GPIOBRST BIT(RCC_AHB1RSTR_GPIOBRST_BIT) -#define RCC_AHB1RSTR_GPIOARST BIT(RCC_AHB1RSTR_GPIOARST_BIT) +#define RCC_AHB1RSTR_OTGHSRST (1U << RCC_AHB1RSTR_OTGHSRST_BIT) +#define RCC_AHB1RSTR_ETHMACRST (1U << RCC_AHB1RSTR_ETHMACRST_BIT) +#define RCC_AHB1RSTR_DMA2RST (1U << RCC_AHB1RSTR_DMA2RST_BIT) +#define RCC_AHB1RSTR_DMA1RST (1U << RCC_AHB1RSTR_DMA1RST_BIT) +#define RCC_AHB1RSTR_CRCRST (1U << RCC_AHB1RSTR_CRCRST_BIT) +#define RCC_AHB1RSTR_GPIOIRST (1U << RCC_AHB1RSTR_GPIOIRST_BIT) +#define RCC_AHB1RSTR_GPIOHRST (1U << RCC_AHB1RSTR_GPIOHRST_BIT) +#define RCC_AHB1RSTR_GPIOGRST (1U << RCC_AHB1RSTR_GPIOGRST_BIT) +#define RCC_AHB1RSTR_GPIOFRST (1U << RCC_AHB1RSTR_GPIOFRST_BIT) +#define RCC_AHB1RSTR_GPIOERST (1U << RCC_AHB1RSTR_GPIOERST_BIT) +#define RCC_AHB1RSTR_GPIODRST (1U << RCC_AHB1RSTR_GPIODRST_BIT) +#define RCC_AHB1RSTR_GPIOCRST (1U << RCC_AHB1RSTR_GPIOCRST_BIT) +#define RCC_AHB1RSTR_GPIOBRST (1U << RCC_AHB1RSTR_GPIOBRST_BIT) +#define RCC_AHB1RSTR_GPIOARST (1U << RCC_AHB1RSTR_GPIOARST_BIT) /* AHB2 peripheral reset register */ @@ -293,17 +293,17 @@ typedef struct rcc_reg_map { #define RCC_AHB2RSTR_CRYPRST_BIT 4 #define RCC_AHB2RSTR_DCMIRST_BIT 0 -#define RCC_AHB2RSTR_OTGFSRST BIT(RCC_AHB2RSTR_OTGFSRST_BIT) -#define RCC_AHB2RSTR_RNGRST BIT(RCC_AHB2RSTR_RNGRST_BIT) -#define RCC_AHB2RSTR_HASHRST BIT(RCC_AHB2RSTR_HASHRST_BIT) -#define RCC_AHB2RSTR_CRYPRST BIT(RCC_AHB2RSTR_CRYPRST_BIT) -#define RCC_AHB2RSTR_DCMIRST BIT(RCC_AHB2RSTR_DCMIRST_BIT) +#define RCC_AHB2RSTR_OTGFSRST (1U << RCC_AHB2RSTR_OTGFSRST_BIT) +#define RCC_AHB2RSTR_RNGRST (1U << RCC_AHB2RSTR_RNGRST_BIT) +#define RCC_AHB2RSTR_HASHRST (1U << RCC_AHB2RSTR_HASHRST_BIT) +#define RCC_AHB2RSTR_CRYPRST (1U << RCC_AHB2RSTR_CRYPRST_BIT) +#define RCC_AHB2RSTR_DCMIRST (1U << RCC_AHB2RSTR_DCMIRST_BIT) /* AHB3 peripheral reset register */ #define RCC_AHB3RSTR_FSMCRST_BIT 0 -#define RCC_AHB3RSTR_FSMCRST BIT(RCC_AHB3RSTR_FSMCRST_BIT) +#define RCC_AHB3RSTR_FSMCRST (1U << RCC_AHB3RSTR_FSMCRST_BIT) /* APB1 peripheral reset register */ @@ -331,29 +331,29 @@ typedef struct rcc_reg_map { #define RCC_APB1RSTR_TIM3RST_BIT 1 #define RCC_APB1RSTR_TIM2RST_BIT 0 -#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT) -#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT) -#define RCC_APB1RSTR_CAN2RST BIT(RCC_APB1RSTR_CAN2RST_BIT) -#define RCC_APB1RSTR_CAN1RST BIT(RCC_APB1RSTR_CAN1RST_BIT) -#define RCC_APB1RSTR_I2C3RST BIT(RCC_APB1RSTR_I2C3RST_BIT) -#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT) -#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT) -#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT) -#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT) -#define RCC_APB1RSTR_UART3RST BIT(RCC_APB1RSTR_UART3RST_BIT) -#define RCC_APB1RSTR_UART2RST BIT(RCC_APB1RSTR_UART2RST_BIT) -#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT) -#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT) -#define RCC_APB1RSTR_WWDGRST BIT(RCC_APB1RSTR_WWDGRST_BIT) -#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT) -#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT) -#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT) -#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT) -#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT) -#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT) -#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT) -#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT) -#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT) +#define RCC_APB1RSTR_DACRST (1U << RCC_APB1RSTR_DACRST_BIT) +#define RCC_APB1RSTR_PWRRST (1U << RCC_APB1RSTR_PWRRST_BIT) +#define RCC_APB1RSTR_CAN2RST (1U << RCC_APB1RSTR_CAN2RST_BIT) +#define RCC_APB1RSTR_CAN1RST (1U << RCC_APB1RSTR_CAN1RST_BIT) +#define RCC_APB1RSTR_I2C3RST (1U << RCC_APB1RSTR_I2C3RST_BIT) +#define RCC_APB1RSTR_I2C2RST (1U << RCC_APB1RSTR_I2C2RST_BIT) +#define RCC_APB1RSTR_I2C1RST (1U << RCC_APB1RSTR_I2C1RST_BIT) +#define RCC_APB1RSTR_UART5RST (1U << RCC_APB1RSTR_UART5RST_BIT) +#define RCC_APB1RSTR_UART4RST (1U << RCC_APB1RSTR_UART4RST_BIT) +#define RCC_APB1RSTR_UART3RST (1U << RCC_APB1RSTR_UART3RST_BIT) +#define RCC_APB1RSTR_UART2RST (1U << RCC_APB1RSTR_UART2RST_BIT) +#define RCC_APB1RSTR_SPI3RST (1U << RCC_APB1RSTR_SPI3RST_BIT) +#define RCC_APB1RSTR_SPI2RST (1U << RCC_APB1RSTR_SPI2RST_BIT) +#define RCC_APB1RSTR_WWDGRST (1U << RCC_APB1RSTR_WWDGRST_BIT) +#define RCC_APB1RSTR_TIM14RST (1U << RCC_APB1RSTR_TIM14RST_BIT) +#define RCC_APB1RSTR_TIM13RST (1U << RCC_APB1RSTR_TIM13RST_BIT) +#define RCC_APB1RSTR_TIM12RST (1U << RCC_APB1RSTR_TIM12RST_BIT) +#define RCC_APB1RSTR_TIM7RST (1U << RCC_APB1RSTR_TIM7RST_BIT) +#define RCC_APB1RSTR_TIM6RST (1U << RCC_APB1RSTR_TIM6RST_BIT) +#define RCC_APB1RSTR_TIM5RST (1U << RCC_APB1RSTR_TIM5RST_BIT) +#define RCC_APB1RSTR_TIM4RST (1U << RCC_APB1RSTR_TIM4RST_BIT) +#define RCC_APB1RSTR_TIM3RST (1U << RCC_APB1RSTR_TIM3RST_BIT) +#define RCC_APB1RSTR_TIM2RST (1U << RCC_APB1RSTR_TIM2RST_BIT) /* APB2 peripheral reset register */ @@ -369,17 +369,17 @@ typedef struct rcc_reg_map { #define RCC_APB2RSTR_TIM8RST_BIT 1 #define RCC_APB2RSTR_TIM1RST_BIT 0 -#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT) -#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT) -#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT) -#define RCC_APB2RSTR_SYSCFGRST BIT(RCC_APB2RSTR_SYSCFGRST_BIT) -#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT) -#define RCC_APB2RSTR_SDIORST BIT(RCC_APB2RSTR_SDIORST_BIT) -#define RCC_APB2RSTR_ADCRST BIT(RCC_APB2RSTR_ADCRST_BIT) -#define RCC_APB2RSTR_USART6RST BIT(RCC_APB2RSTR_USART6RST_BIT) -#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT) -#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT) -#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT) +#define RCC_APB2RSTR_TIM11RST (1U << RCC_APB2RSTR_TIM11RST_BIT) +#define RCC_APB2RSTR_TIM10RST (1U << RCC_APB2RSTR_TIM10RST_BIT) +#define RCC_APB2RSTR_TIM9RST (1U << RCC_APB2RSTR_TIM9RST_BIT) +#define RCC_APB2RSTR_SYSCFGRST (1U << RCC_APB2RSTR_SYSCFGRST_BIT) +#define RCC_APB2RSTR_SPI1RST (1U << RCC_APB2RSTR_SPI1RST_BIT) +#define RCC_APB2RSTR_SDIORST (1U << RCC_APB2RSTR_SDIORST_BIT) +#define RCC_APB2RSTR_ADCRST (1U << RCC_APB2RSTR_ADCRST_BIT) +#define RCC_APB2RSTR_USART6RST (1U << RCC_APB2RSTR_USART6RST_BIT) +#define RCC_APB2RSTR_USART1RST (1U << RCC_APB2RSTR_USART1RST_BIT) +#define RCC_APB2RSTR_TIM8RST (1U << RCC_APB2RSTR_TIM8RST_BIT) +#define RCC_APB2RSTR_TIM1RST (1U << RCC_APB2RSTR_TIM1RST_BIT) /* AHB1 peripheral clock enable register */ @@ -403,25 +403,25 @@ typedef struct rcc_reg_map { #define RCC_AHB1ENR_GPIOBEN_BIT 1 #define RCC_AHB1ENR_GPIOAEN_BIT 0 -#define RCC_AHB1ENR_OTGHSULPIEN BIT(RCC_AHB1ENR_OTGHSULPIEN_BIT) -#define RCC_AHB1ENR_OTGHSEN BIT(RCC_AHB1ENR_OTGHSEN_BIT) -#define RCC_AHB1ENR_ETHMACPTPEN BIT(RCC_AHB1ENR_ETHMACPTPEN_BIT) -#define RCC_AHB1ENR_ETHMACRXEN BIT(RCC_AHB1ENR_ETHMACRXEN_BIT) -#define RCC_AHB1ENR_ETHMACTXEN BIT(RCC_AHB1ENR_ETHMACTXEN_BIT) -#define RCC_AHB1ENR_ETHMACEN BIT(RCC_AHB1ENR_ETHMACEN_BIT) -#define RCC_AHB1ENR_DMA2EN BIT(RCC_AHB1ENR_DMA2EN_BIT) -#define RCC_AHB1ENR_DMA1EN BIT(RCC_AHB1ENR_DMA1EN_BIT) -#define RCC_AHB1ENR_BKPSRAMEN BIT(RCC_AHB1ENR_BKPSRAMEN_BIT) -#define RCC_AHB1ENR_CRCEN BIT(RCC_AHB1ENR_CRCEN_BIT) -#define RCC_AHB1ENR_GPIOIEN BIT(RCC_AHB1ENR_GPIOIEN_BIT) -#define RCC_AHB1ENR_GPIOHEN BIT(RCC_AHB1ENR_GPIOHEN_BIT) -#define RCC_AHB1ENR_GPIOGEN BIT(RCC_AHB1ENR_GPIOGEN_BIT) -#define RCC_AHB1ENR_GPIOFEN BIT(RCC_AHB1ENR_GPIOFEN_BIT) -#define RCC_AHB1ENR_GPIOEEN BIT(RCC_AHB1ENR_GPIOEEN_BIT) -#define RCC_AHB1ENR_GPIODEN BIT(RCC_AHB1ENR_GPIODEN_BIT) -#define RCC_AHB1ENR_GPIOCEN BIT(RCC_AHB1ENR_GPIOCEN_BIT) -#define RCC_AHB1ENR_GPIOBEN BIT(RCC_AHB1ENR_GPIOBEN_BIT) -#define RCC_AHB1ENR_GPIOAEN BIT(RCC_AHB1ENR_GPIOAEN_BIT) +#define RCC_AHB1ENR_OTGHSULPIEN (1U << RCC_AHB1ENR_OTGHSULPIEN_BIT) +#define RCC_AHB1ENR_OTGHSEN (1U << RCC_AHB1ENR_OTGHSEN_BIT) +#define RCC_AHB1ENR_ETHMACPTPEN (1U << RCC_AHB1ENR_ETHMACPTPEN_BIT) +#define RCC_AHB1ENR_ETHMACRXEN (1U << RCC_AHB1ENR_ETHMACRXEN_BIT) +#define RCC_AHB1ENR_ETHMACTXEN (1U << RCC_AHB1ENR_ETHMACTXEN_BIT) +#define RCC_AHB1ENR_ETHMACEN (1U << RCC_AHB1ENR_ETHMACEN_BIT) +#define RCC_AHB1ENR_DMA2EN (1U << RCC_AHB1ENR_DMA2EN_BIT) +#define RCC_AHB1ENR_DMA1EN (1U << RCC_AHB1ENR_DMA1EN_BIT) +#define RCC_AHB1ENR_BKPSRAMEN (1U << RCC_AHB1ENR_BKPSRAMEN_BIT) +#define RCC_AHB1ENR_CRCEN (1U << RCC_AHB1ENR_CRCEN_BIT) +#define RCC_AHB1ENR_GPIOIEN (1U << RCC_AHB1ENR_GPIOIEN_BIT) +#define RCC_AHB1ENR_GPIOHEN (1U << RCC_AHB1ENR_GPIOHEN_BIT) +#define RCC_AHB1ENR_GPIOGEN (1U << RCC_AHB1ENR_GPIOGEN_BIT) +#define RCC_AHB1ENR_GPIOFEN (1U << RCC_AHB1ENR_GPIOFEN_BIT) +#define RCC_AHB1ENR_GPIOEEN (1U << RCC_AHB1ENR_GPIOEEN_BIT) +#define RCC_AHB1ENR_GPIODEN (1U << RCC_AHB1ENR_GPIODEN_BIT) +#define RCC_AHB1ENR_GPIOCEN (1U << RCC_AHB1ENR_GPIOCEN_BIT) +#define RCC_AHB1ENR_GPIOBEN (1U << RCC_AHB1ENR_GPIOBEN_BIT) +#define RCC_AHB1ENR_GPIOAEN (1U << RCC_AHB1ENR_GPIOAEN_BIT) /* AHB2 peripheral clock enable register */ @@ -431,17 +431,17 @@ typedef struct rcc_reg_map { #define RCC_AHB2ENR_CRYPEN_BIT 4 #define RCC_AHB2ENR_DCMIEN_BIT 0 -#define RCC_AHB2ENR_OTGFSEN BIT(RCC_AHB2ENR_OTGFSEN_BIT) -#define RCC_AHB2ENR_RNGEN BIT(RCC_AHB2ENR_RNGEN_BIT) -#define RCC_AHB2ENR_HASHEN BIT(RCC_AHB2ENR_HASHEN_BIT) -#define RCC_AHB2ENR_CRYPEN BIT(RCC_AHB2ENR_CRYPEN_BIT) -#define RCC_AHB2ENR_DCMIEN BIT(RCC_AHB2ENR_DCMIEN_BIT) +#define RCC_AHB2ENR_OTGFSEN (1U << RCC_AHB2ENR_OTGFSEN_BIT) +#define RCC_AHB2ENR_RNGEN (1U << RCC_AHB2ENR_RNGEN_BIT) +#define RCC_AHB2ENR_HASHEN (1U << RCC_AHB2ENR_HASHEN_BIT) +#define RCC_AHB2ENR_CRYPEN (1U << RCC_AHB2ENR_CRYPEN_BIT) +#define RCC_AHB2ENR_DCMIEN (1U << RCC_AHB2ENR_DCMIEN_BIT) /* AHB3 peripheral clock enable register */ #define RCC_AHB3ENR_FSMCEN_BIT 0 -#define RCC_AHB3ENR_FSMCEN BIT(RCC_AHB3ENR_FSMCEN_BIT) +#define RCC_AHB3ENR_FSMCEN (1U << RCC_AHB3ENR_FSMCEN_BIT) /* APB1 peripheral clock enable register */ @@ -469,29 +469,29 @@ typedef struct rcc_reg_map { #define RCC_APB1ENR_TIM3EN_BIT 1 #define RCC_APB1ENR_TIM2EN_BIT 0 -#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT) -#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT) -#define RCC_APB1ENR_CAN2EN BIT(RCC_APB1ENR_CAN2EN_BIT) -#define RCC_APB1ENR_CAN1EN BIT(RCC_APB1ENR_CAN1EN_BIT) -#define RCC_APB1ENR_I2C3EN BIT(RCC_APB1ENR_I2C3EN_BIT) -#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT) -#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT) -#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT) -#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT) -#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT) -#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT) -#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT) -#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT) -#define RCC_APB1ENR_WWDGEN BIT(RCC_APB1ENR_WWDGEN_BIT) -#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT) -#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT) -#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT) -#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT) -#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT) -#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT) -#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT) -#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT) -#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT) +#define RCC_APB1ENR_DACEN (1U << RCC_APB1ENR_DACEN_BIT) +#define RCC_APB1ENR_PWREN (1U << RCC_APB1ENR_PWREN_BIT) +#define RCC_APB1ENR_CAN2EN (1U << RCC_APB1ENR_CAN2EN_BIT) +#define RCC_APB1ENR_CAN1EN (1U << RCC_APB1ENR_CAN1EN_BIT) +#define RCC_APB1ENR_I2C3EN (1U << RCC_APB1ENR_I2C3EN_BIT) +#define RCC_APB1ENR_I2C2EN (1U << RCC_APB1ENR_I2C2EN_BIT) +#define RCC_APB1ENR_I2C1EN (1U << RCC_APB1ENR_I2C1EN_BIT) +#define RCC_APB1ENR_UART5EN (1U << RCC_APB1ENR_UART5EN_BIT) +#define RCC_APB1ENR_UART4EN (1U << RCC_APB1ENR_UART4EN_BIT) +#define RCC_APB1ENR_USART3EN (1U << RCC_APB1ENR_USART3EN_BIT) +#define RCC_APB1ENR_USART2EN (1U << RCC_APB1ENR_USART2EN_BIT) +#define RCC_APB1ENR_SPI3EN (1U << RCC_APB1ENR_SPI3EN_BIT) +#define RCC_APB1ENR_SPI2EN (1U << RCC_APB1ENR_SPI2EN_BIT) +#define RCC_APB1ENR_WWDGEN (1U << RCC_APB1ENR_WWDGEN_BIT) +#define RCC_APB1ENR_TIM14EN (1U << RCC_APB1ENR_TIM14EN_BIT) +#define RCC_APB1ENR_TIM13EN (1U << RCC_APB1ENR_TIM13EN_BIT) +#define RCC_APB1ENR_TIM12EN (1U << RCC_APB1ENR_TIM12EN_BIT) +#define RCC_APB1ENR_TIM7EN (1U << RCC_APB1ENR_TIM7EN_BIT) +#define RCC_APB1ENR_TIM6EN (1U << RCC_APB1ENR_TIM6EN_BIT) +#define RCC_APB1ENR_TIM5EN (1U << RCC_APB1ENR_TIM5EN_BIT) +#define RCC_APB1ENR_TIM4EN (1U << RCC_APB1ENR_TIM4EN_BIT) +#define RCC_APB1ENR_TIM3EN (1U << RCC_APB1ENR_TIM3EN_BIT) +#define RCC_APB1ENR_TIM2EN (1U << RCC_APB1ENR_TIM2EN_BIT) /* APB2 peripheral clock enable register */ @@ -509,19 +509,19 @@ typedef struct rcc_reg_map { #define RCC_APB2ENR_TIM8EN_BIT 1 #define RCC_APB2ENR_TIM1EN_BIT 0 -#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT) -#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT) -#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT) -#define RCC_APB2ENR_SYSCFGEN BIT(RCC_APB2ENR_SYSCFGEN_BIT) -#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT) -#define RCC_APB2ENR_SDIOEN BIT(RCC_APB2ENR_SDIOEN_BIT) -#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT) -#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT) -#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT) -#define RCC_APB2ENR_USART6EN BIT(RCC_APB2ENR_USART6EN_BIT) -#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT) -#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT) -#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT) +#define RCC_APB2ENR_TIM11EN (1U << RCC_APB2ENR_TIM11EN_BIT) +#define RCC_APB2ENR_TIM10EN (1U << RCC_APB2ENR_TIM10EN_BIT) +#define RCC_APB2ENR_TIM9EN (1U << RCC_APB2ENR_TIM9EN_BIT) +#define RCC_APB2ENR_SYSCFGEN (1U << RCC_APB2ENR_SYSCFGEN_BIT) +#define RCC_APB2ENR_SPI1EN (1U << RCC_APB2ENR_SPI1EN_BIT) +#define RCC_APB2ENR_SDIOEN (1U << RCC_APB2ENR_SDIOEN_BIT) +#define RCC_APB2ENR_ADC3EN (1U << RCC_APB2ENR_ADC3EN_BIT) +#define RCC_APB2ENR_ADC2EN (1U << RCC_APB2ENR_ADC2EN_BIT) +#define RCC_APB2ENR_ADC1EN (1U << RCC_APB2ENR_ADC1EN_BIT) +#define RCC_APB2ENR_USART6EN (1U << RCC_APB2ENR_USART6EN_BIT) +#define RCC_APB2ENR_USART1EN (1U << RCC_APB2ENR_USART1EN_BIT) +#define RCC_APB2ENR_TIM8EN (1U << RCC_APB2ENR_TIM8EN_BIT) +#define RCC_APB2ENR_TIM1EN (1U << RCC_APB2ENR_TIM1EN_BIT) /* AHB1 peripheral clock enable in low power mode register */ @@ -547,27 +547,27 @@ typedef struct rcc_reg_map { #define RCC_AHB1LPENR_GPIOBLPEN_BIT 1 #define RCC_AHB1LPENR_GPIOALPEN_BIT 0 -#define RCC_AHB1LPENR_OTGHSULPILPEN BIT(RCC_AHB1LPENR_OTGHSULPILPEN_BIT) -#define RCC_AHB1LPENR_OTGHSLPEN BIT(RCC_AHB1LPENR_OTGHSLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACPTPLPEN BIT(RCC_AHB1LPENR_ETHMACPTPLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACRXLPEN BIT(RCC_AHB1LPENR_ETHMACRXLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACTXLPEN BIT(RCC_AHB1LPENR_ETHMACTXLPEN_BIT) -#define RCC_AHB1LPENR_ETHMACLPEN BIT(RCC_AHB1LPENR_ETHMACLPEN_BIT) -#define RCC_AHB1LPENR_DMA2LPEN BIT(RCC_AHB1LPENR_DMA2LPEN_BIT) -#define RCC_AHB1LPENR_DMA1LPEN BIT(RCC_AHB1LPENR_DMA1LPEN_BIT) -#define RCC_AHB1LPENR_BKPSRAMLPEN BIT(RCC_AHB1LPENR_BKPSRAMLPEN_BIT) -#define RCC_AHB1LPENR_SRAM2LPEN BIT(RCC_AHB1LPENR_SRAM2LPEN_BIT) -#define RCC_AHB1LPENR_SRAM1LPEN BIT(RCC_AHB1LPENR_SRAM1LPEN_BIT) -#define RCC_AHB1LPENR_FLITFLPEN BIT(RCC_AHB1LPENR_FLITFLPEN_BIT) -#define RCC_AHB1LPENR_CRCLPEN BIT(RCC_AHB1LPENR_CRCLPEN_BIT) -#define RCC_AHB1LPENR_GPIOILPEN BIT(RCC_AHB1LPENR_GPIOILPEN_BIT) -#define RCC_AHB1LPENR_GPIOGLPEN BIT(RCC_AHB1LPENR_GPIOGLPEN_BIT) -#define RCC_AHB1LPENR_GPIOFLPEN BIT(RCC_AHB1LPENR_GPIOFLPEN_BIT) -#define RCC_AHB1LPENR_GPIOELPEN BIT(RCC_AHB1LPENR_GPIOELPEN_BIT) -#define RCC_AHB1LPENR_GPIODLPEN BIT(RCC_AHB1LPENR_GPIODLPEN_BIT) -#define RCC_AHB1LPENR_GPIOCLPEN BIT(RCC_AHB1LPENR_GPIOCLPEN_BIT) -#define RCC_AHB1LPENR_GPIOBLPEN BIT(RCC_AHB1LPENR_GPIOBLPEN_BIT) -#define RCC_AHB1LPENR_GPIOALPEN BIT(RCC_AHB1LPENR_GPIOALPEN_BIT) +#define RCC_AHB1LPENR_OTGHSULPILPEN (1U << RCC_AHB1LPENR_OTGHSULPILPEN_BIT) +#define RCC_AHB1LPENR_OTGHSLPEN (1U << RCC_AHB1LPENR_OTGHSLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACPTPLPEN (1U << RCC_AHB1LPENR_ETHMACPTPLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACRXLPEN (1U << RCC_AHB1LPENR_ETHMACRXLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACTXLPEN (1U << RCC_AHB1LPENR_ETHMACTXLPEN_BIT) +#define RCC_AHB1LPENR_ETHMACLPEN (1U << RCC_AHB1LPENR_ETHMACLPEN_BIT) +#define RCC_AHB1LPENR_DMA2LPEN (1U << RCC_AHB1LPENR_DMA2LPEN_BIT) +#define RCC_AHB1LPENR_DMA1LPEN (1U << RCC_AHB1LPENR_DMA1LPEN_BIT) +#define RCC_AHB1LPENR_BKPSRAMLPEN (1U << RCC_AHB1LPENR_BKPSRAMLPEN_BIT) +#define RCC_AHB1LPENR_SRAM2LPEN (1U << RCC_AHB1LPENR_SRAM2LPEN_BIT) +#define RCC_AHB1LPENR_SRAM1LPEN (1U << RCC_AHB1LPENR_SRAM1LPEN_BIT) +#define RCC_AHB1LPENR_FLITFLPEN (1U << RCC_AHB1LPENR_FLITFLPEN_BIT) +#define RCC_AHB1LPENR_CRCLPEN (1U << RCC_AHB1LPENR_CRCLPEN_BIT) +#define RCC_AHB1LPENR_GPIOILPEN (1U << RCC_AHB1LPENR_GPIOILPEN_BIT) +#define RCC_AHB1LPENR_GPIOGLPEN (1U << RCC_AHB1LPENR_GPIOGLPEN_BIT) +#define RCC_AHB1LPENR_GPIOFLPEN (1U << RCC_AHB1LPENR_GPIOFLPEN_BIT) +#define RCC_AHB1LPENR_GPIOELPEN (1U << RCC_AHB1LPENR_GPIOELPEN_BIT) +#define RCC_AHB1LPENR_GPIODLPEN (1U << RCC_AHB1LPENR_GPIODLPEN_BIT) +#define RCC_AHB1LPENR_GPIOCLPEN (1U << RCC_AHB1LPENR_GPIOCLPEN_BIT) +#define RCC_AHB1LPENR_GPIOBLPEN (1U << RCC_AHB1LPENR_GPIOBLPEN_BIT) +#define RCC_AHB1LPENR_GPIOALPEN (1U << RCC_AHB1LPENR_GPIOALPEN_BIT) /* AHB2 peripheral clock enable in low power mode register */ @@ -577,17 +577,17 @@ typedef struct rcc_reg_map { #define RCC_AHB2LPENR_CRYPLPEN_BIT 4 #define RCC_AHB2LPENR_DCMILPEN_BIT 0 -#define RCC_AHB2LPENR_OTGFSLPEN BIT(RCC_AHB2LPENR_OTGFSLPEN_BIT) -#define RCC_AHB2LPENR_RNGLPEN BIT(RCC_AHB2LPENR_RNGLPEN_BIT) -#define RCC_AHB2LPENR_HASHLPEN BIT(RCC_AHB2LPENR_HASHLPEN_BIT) -#define RCC_AHB2LPENR_CRYPLPEN BIT(RCC_AHB2LPENR_CRYPLPEN_BIT) -#define RCC_AHB2LPENR_DCMILPEN BIT(RCC_AHB2LPENR_DCMILPEN_BIT) +#define RCC_AHB2LPENR_OTGFSLPEN (1U << RCC_AHB2LPENR_OTGFSLPEN_BIT) +#define RCC_AHB2LPENR_RNGLPEN (1U << RCC_AHB2LPENR_RNGLPEN_BIT) +#define RCC_AHB2LPENR_HASHLPEN (1U << RCC_AHB2LPENR_HASHLPEN_BIT) +#define RCC_AHB2LPENR_CRYPLPEN (1U << RCC_AHB2LPENR_CRYPLPEN_BIT) +#define RCC_AHB2LPENR_DCMILPEN (1U << RCC_AHB2LPENR_DCMILPEN_BIT) /* AHB3 peripheral clock enable in low power mode register */ #define RCC_AHB3LPENR_FSMCLPEN_BIT 0 -#define RCC_AHB3LPENR_FSMCLPEN BIT(RCC_AHB3LPENR_FSMCLPEN_BIT) +#define RCC_AHB3LPENR_FSMCLPEN (1U << RCC_AHB3LPENR_FSMCLPEN_BIT) /* APB1 peripheral clock enable in low power mode register */ @@ -615,29 +615,29 @@ typedef struct rcc_reg_map { #define RCC_APB1LPENR_TIM3LPEN_BIT 1 #define RCC_APB1LPENR_TIM2LPEN_BIT 0 -#define RCC_APB1LPENR_DACLPEN BIT(RCC_APB1LPENR_DACLPEN_BIT) -#define RCC_APB1LPENR_PWRLPEN BIT(RCC_APB1LPENR_PWRLPEN_BIT) -#define RCC_APB1LPENR_CAN2LPEN BIT(RCC_APB1LPENR_CAN2LPEN_BIT) -#define RCC_APB1LPENR_CAN1LPEN BIT(RCC_APB1LPENR_CAN1LPEN_BIT) -#define RCC_APB1LPENR_I2C3LPEN BIT(RCC_APB1LPENR_I2C3LPEN_BIT) -#define RCC_APB1LPENR_I2C2LPEN BIT(RCC_APB1LPENR_I2C2LPEN_BIT) -#define RCC_APB1LPENR_I2C1LPEN BIT(RCC_APB1LPENR_I2C1LPEN_BIT) -#define RCC_APB1LPENR_UART5LPEN BIT(RCC_APB1LPENR_UART5LPEN_BIT) -#define RCC_APB1LPENR_UART4LPEN BIT(RCC_APB1LPENR_UART4LPEN_BIT) -#define RCC_APB1LPENR_USART3LPEN BIT(RCC_APB1LPENR_USART3LPEN_BIT) -#define RCC_APB1LPENR_USART2LPEN BIT(RCC_APB1LPENR_USART2LPEN_BIT) -#define RCC_APB1LPENR_SPI3LPEN BIT(RCC_APB1LPENR_SPI3LPEN_BIT) -#define RCC_APB1LPENR_SPI2LPEN BIT(RCC_APB1LPENR_SPI2LPEN_BIT) -#define RCC_APB1LPENR_WWDGLPEN BIT(RCC_APB1LPENR_WWDGLPEN_BIT) -#define RCC_APB1LPENR_TIM14LPEN BIT(RCC_APB1LPENR_TIM14LPEN_BIT) -#define RCC_APB1LPENR_TIM13LPEN BIT(RCC_APB1LPENR_TIM13LPEN_BIT) -#define RCC_APB1LPENR_TIM12LPEN BIT(RCC_APB1LPENR_TIM12LPEN_BIT) -#define RCC_APB1LPENR_TIM7LPEN BIT(RCC_APB1LPENR_TIM7LPEN_BIT) -#define RCC_APB1LPENR_TIM6LPEN BIT(RCC_APB1LPENR_TIM6LPEN_BIT) -#define RCC_APB1LPENR_TIM5LPEN BIT(RCC_APB1LPENR_TIM5LPEN_BIT) -#define RCC_APB1LPENR_TIM4LPEN BIT(RCC_APB1LPENR_TIM4LPEN_BIT) -#define RCC_APB1LPENR_TIM3LPEN BIT(RCC_APB1LPENR_TIM3LPEN_BIT) -#define RCC_APB1LPENR_TIM2LPEN BIT(RCC_APB1LPENR_TIM2LPEN_BIT) +#define RCC_APB1LPENR_DACLPEN (1U << RCC_APB1LPENR_DACLPEN_BIT) +#define RCC_APB1LPENR_PWRLPEN (1U << RCC_APB1LPENR_PWRLPEN_BIT) +#define RCC_APB1LPENR_CAN2LPEN (1U << RCC_APB1LPENR_CAN2LPEN_BIT) +#define RCC_APB1LPENR_CAN1LPEN (1U << RCC_APB1LPENR_CAN1LPEN_BIT) +#define RCC_APB1LPENR_I2C3LPEN (1U << RCC_APB1LPENR_I2C3LPEN_BIT) +#define RCC_APB1LPENR_I2C2LPEN (1U << RCC_APB1LPENR_I2C2LPEN_BIT) +#define RCC_APB1LPENR_I2C1LPEN (1U << RCC_APB1LPENR_I2C1LPEN_BIT) +#define RCC_APB1LPENR_UART5LPEN (1U << RCC_APB1LPENR_UART5LPEN_BIT) +#define RCC_APB1LPENR_UART4LPEN (1U << RCC_APB1LPENR_UART4LPEN_BIT) +#define RCC_APB1LPENR_USART3LPEN (1U << RCC_APB1LPENR_USART3LPEN_BIT) +#define RCC_APB1LPENR_USART2LPEN (1U << RCC_APB1LPENR_USART2LPEN_BIT) +#define RCC_APB1LPENR_SPI3LPEN (1U << RCC_APB1LPENR_SPI3LPEN_BIT) +#define RCC_APB1LPENR_SPI2LPEN (1U << RCC_APB1LPENR_SPI2LPEN_BIT) +#define RCC_APB1LPENR_WWDGLPEN (1U << RCC_APB1LPENR_WWDGLPEN_BIT) +#define RCC_APB1LPENR_TIM14LPEN (1U << RCC_APB1LPENR_TIM14LPEN_BIT) +#define RCC_APB1LPENR_TIM13LPEN (1U << RCC_APB1LPENR_TIM13LPEN_BIT) +#define RCC_APB1LPENR_TIM12LPEN (1U << RCC_APB1LPENR_TIM12LPEN_BIT) +#define RCC_APB1LPENR_TIM7LPEN (1U << RCC_APB1LPENR_TIM7LPEN_BIT) +#define RCC_APB1LPENR_TIM6LPEN (1U << RCC_APB1LPENR_TIM6LPEN_BIT) +#define RCC_APB1LPENR_TIM5LPEN (1U << RCC_APB1LPENR_TIM5LPEN_BIT) +#define RCC_APB1LPENR_TIM4LPEN (1U << RCC_APB1LPENR_TIM4LPEN_BIT) +#define RCC_APB1LPENR_TIM3LPEN (1U << RCC_APB1LPENR_TIM3LPEN_BIT) +#define RCC_APB1LPENR_TIM2LPEN (1U << RCC_APB1LPENR_TIM2LPEN_BIT) /* APB2 peripheral clock enable in low power mode register */ @@ -655,19 +655,19 @@ typedef struct rcc_reg_map { #define RCC_APB2LPENR_TIM8LPEN_BIT 1 #define RCC_APB2LPENR_TIM1LPEN_BIT 0 -#define RCC_APB2LPENR_TIM11LPEN BIT(RCC_APB2LPENR_TIM11LPEN_BIT) -#define RCC_APB2LPENR_TIM10LPEN BIT(RCC_APB2LPENR_TIM10LPEN_BIT) -#define RCC_APB2LPENR_TIM9LPEN BIT(RCC_APB2LPENR_TIM9LPEN_BIT) -#define RCC_APB2LPENR_SYSCFGLPEN BIT(RCC_APB2LPENR_SYSCFGLPEN_BIT) -#define RCC_APB2LPENR_SPI1LPEN BIT(RCC_APB2LPENR_SPI1LPEN_BIT) -#define RCC_APB2LPENR_SDIOLPEN BIT(RCC_APB2LPENR_SDIOLPEN_BIT) -#define RCC_APB2LPENR_ADC3LPEN BIT(RCC_APB2LPENR_ADC3LPEN_BIT) -#define RCC_APB2LPENR_ADC2LPEN BIT(RCC_APB2LPENR_ADC2LPEN_BIT) -#define RCC_APB2LPENR_ADC1LPEN BIT(RCC_APB2LPENR_ADC1LPEN_BIT) -#define RCC_APB2LPENR_USART6LPEN BIT(RCC_APB2LPENR_USART6LPEN_BIT) -#define RCC_APB2LPENR_USART1LPEN BIT(RCC_APB2LPENR_USART1LPEN_BIT) -#define RCC_APB2LPENR_TIM8LPEN BIT(RCC_APB2LPENR_TIM8LPEN_BIT) -#define RCC_APB2LPENR_TIM1LPEN BIT(RCC_APB2LPENR_TIM1LPEN_BIT) +#define RCC_APB2LPENR_TIM11LPEN (1U << RCC_APB2LPENR_TIM11LPEN_BIT) +#define RCC_APB2LPENR_TIM10LPEN (1U << RCC_APB2LPENR_TIM10LPEN_BIT) +#define RCC_APB2LPENR_TIM9LPEN (1U << RCC_APB2LPENR_TIM9LPEN_BIT) +#define RCC_APB2LPENR_SYSCFGLPEN (1U << RCC_APB2LPENR_SYSCFGLPEN_BIT) +#define RCC_APB2LPENR_SPI1LPEN (1U << RCC_APB2LPENR_SPI1LPEN_BIT) +#define RCC_APB2LPENR_SDIOLPEN (1U << RCC_APB2LPENR_SDIOLPEN_BIT) +#define RCC_APB2LPENR_ADC3LPEN (1U << RCC_APB2LPENR_ADC3LPEN_BIT) +#define RCC_APB2LPENR_ADC2LPEN (1U << RCC_APB2LPENR_ADC2LPEN_BIT) +#define RCC_APB2LPENR_ADC1LPEN (1U << RCC_APB2LPENR_ADC1LPEN_BIT) +#define RCC_APB2LPENR_USART6LPEN (1U << RCC_APB2LPENR_USART6LPEN_BIT) +#define RCC_APB2LPENR_USART1LPEN (1U << RCC_APB2LPENR_USART1LPEN_BIT) +#define RCC_APB2LPENR_TIM8LPEN (1U << RCC_APB2LPENR_TIM8LPEN_BIT) +#define RCC_APB2LPENR_TIM1LPEN (1U << RCC_APB2LPENR_TIM1LPEN_BIT) /* Backup domain control register */ @@ -677,16 +677,16 @@ typedef struct rcc_reg_map { #define RCC_BDCR_LSERDY_BIT 1 #define RCC_BDCR_LSEON_BIT 0 -#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT) -#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTCEN_BIT) +#define RCC_BDCR_BDRST (1U << RCC_BDCR_BDRST_BIT) +#define RCC_BDCR_RTCEN (1U << RCC_BDCR_RTCEN_BIT) #define RCC_BDCR_RTCSEL (0x3 << 8) #define RCC_BDCR_RTCSEL_NOCLOCK (0x0 << 8) #define RCC_BDCR_RTCSEL_LSE (0x1 << 8) #define RCC_BDCR_RTCSEL_LSI (0x2 << 8) #define RCC_BDCR_RTCSEL_HSE_DIV (0x3 << 8) -#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT) -#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT) -#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT) +#define RCC_BDCR_LSEBYP (1U << RCC_BDCR_LSEBYP_BIT) +#define RCC_BDCR_LSERDY (1U << RCC_BDCR_LSERDY_BIT) +#define RCC_BDCR_LSEON (1U << RCC_BDCR_LSEON_BIT) /* Clock control and status register */ @@ -701,24 +701,24 @@ typedef struct rcc_reg_map { #define RCC_CSR_LSIRDY_BIT 1 #define RCC_CSR_LSION_BIT 0 -#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT) -#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT) -#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT) -#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT) -#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT) -#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT) -#define RCC_CSR_BORRSTF BIT(RCC_CSR_BORRSTF_BIT) -#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT) -#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT) -#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT) +#define RCC_CSR_LPWRRSTF (1U << RCC_CSR_LPWRRSTF_BIT) +#define RCC_CSR_WWDGRSTF (1U << RCC_CSR_WWDGRSTF_BIT) +#define RCC_CSR_IWDGRSTF (1U << RCC_CSR_IWDGRSTF_BIT) +#define RCC_CSR_SFTRSTF (1U << RCC_CSR_SFTRSTF_BIT) +#define RCC_CSR_PORRSTF (1U << RCC_CSR_PORRSTF_BIT) +#define RCC_CSR_PINRSTF (1U << RCC_CSR_PINRSTF_BIT) +#define RCC_CSR_BORRSTF (1U << RCC_CSR_BORRSTF_BIT) +#define RCC_CSR_RMVF (1U << RCC_CSR_RMVF_BIT) +#define RCC_CSR_LSIRDY (1U << RCC_CSR_LSIRDY_BIT) +#define RCC_CSR_LSION (1U << RCC_CSR_LSION_BIT) /* Spread spectrum clock generation register */ #define RCC_SSCGR_SSCGEN_BIT 31 #define RCC_SSCGR_SPREADSEL_BIT 30 -#define RCC_SSCGR_SSCGEN BIT(RCC_SSCGR_SSCGEN_BIT) -#define RCC_SSCGR_SPREADSEL BIT(RCC_SSCGR_SPREADSEL_BIT) +#define RCC_SSCGR_SSCGEN (1U << RCC_SSCGR_SSCGEN_BIT) +#define RCC_SSCGR_SPREADSEL (1U << RCC_SSCGR_SPREADSEL_BIT) #define RCC_SSCGR_SPREADSEL_CENTER (0x0 << RCC_SSCGR_SPREADSEL_BIT) #define RCC_SSCGR_SPREADSEL_DOWN (0x1 << RCC_SSCGR_SPREADSEL_BIT) #define RCC_SSCGR_INCSTEP (0xFFF << 16) -- cgit v1.2.3 From 18c4bc628070518902261e5fb9d1abfc68c4c073 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 16:43:46 -0400 Subject: stm32f1/rcc.c: Move Doyxgen. This is a workaround for Breathe. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/rcc.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c index a83bea3..8d71a41 100644 --- a/libmaple/stm32f1/rcc.c +++ b/libmaple/stm32f1/rcc.c @@ -95,16 +95,7 @@ const struct rcc_dev_info rcc_dev_table[] = { #endif }; -/** - * @brief Deprecated; STM32F1 only. - * - * Initialize the clock control system. Initializes the system - * clock source to use the PLL driven by an external oscillator. - * - * @param sysclk_src system clock source, must be PLL - * @param pll_src pll clock source, must be HSE - * @param pll_mul pll multiplier - */ +__deprecated void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul) { -- cgit v1.2.3 From 493a58d80ca8a606fab6fdc20eff688acf3fd5b9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 16:44:24 -0400 Subject: libmaple/nvic.h: Fix typo. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/nvic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h index 86ac1cb..dfdd901 100644 --- a/libmaple/include/libmaple/nvic.h +++ b/libmaple/include/libmaple/nvic.h @@ -58,7 +58,7 @@ typedef struct nvic_reg_map { __io uint32 ISER[8]; /**< Interrupt Set Enable Registers */ uint32 RESERVED0[24]; /**< Reserved */ __io uint32 ICER[8]; /**< Interrupt Clear Enable Registers */ - uint32 RSERVED1[24]; /**< Reserved */ + uint32 RESERVED1[24]; /**< Reserved */ __io uint32 ISPR[8]; /**< Interrupt Set Pending Registers */ uint32 RESERVED2[24]; /**< Reserved */ __io uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */ -- cgit v1.2.3 From c2eb6f652367dc5b6f39062a9ec5af1e506fe172 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 11 May 2012 16:45:38 -0400 Subject: libmaple/nvic.h: Doxygen tweak.s Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/nvic.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/libmaple/include/libmaple/nvic.h b/libmaple/include/libmaple/nvic.h index dfdd901..ac102d9 100644 --- a/libmaple/include/libmaple/nvic.h +++ b/libmaple/include/libmaple/nvic.h @@ -56,17 +56,29 @@ extern "C"{ /** NVIC register map type. */ typedef struct nvic_reg_map { __io uint32 ISER[8]; /**< Interrupt Set Enable Registers */ - uint32 RESERVED0[24]; /**< Reserved */ + /** Reserved */ + uint32 RESERVED0[24]; + __io uint32 ICER[8]; /**< Interrupt Clear Enable Registers */ - uint32 RESERVED1[24]; /**< Reserved */ + /** Reserved */ + uint32 RESERVED1[24]; + __io uint32 ISPR[8]; /**< Interrupt Set Pending Registers */ - uint32 RESERVED2[24]; /**< Reserved */ + /** Reserved */ + uint32 RESERVED2[24]; + __io uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */ - uint32 RESERVED3[24]; /**< Reserved */ + /** Reserved */ + uint32 RESERVED3[24]; + __io uint32 IABR[8]; /**< Interrupt Active bit Registers */ - uint32 RESERVED4[56]; /**< Reserved */ + /** Reserved */ + uint32 RESERVED4[56]; + __io uint8 IP[240]; /**< Interrupt Priority Registers */ - uint32 RESERVED5[644]; /**< Reserved */ + /** Reserved */ + uint32 RESERVED5[644]; + __io uint32 STIR; /**< Software Trigger Interrupt Registers */ } nvic_reg_map; -- cgit v1.2.3 From ef9ff361423d9788614607864a01bbb708b32664 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 14 May 2012 12:11:17 -0400 Subject: nvic.h: Doxygen: nvic_irq_num is target dependent. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/nvic.h | 2 +- libmaple/stm32f2/include/series/nvic.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/stm32f1/include/series/nvic.h b/libmaple/stm32f1/include/series/nvic.h index 42c0b37..acabd93 100644 --- a/libmaple/stm32f1/include/series/nvic.h +++ b/libmaple/stm32f1/include/series/nvic.h @@ -39,7 +39,7 @@ extern "C"{ #include /** - * @brief Interrupt vector table interrupt numbers. + * @brief STM32F1 interrupt vector table interrupt numbers. * @see */ typedef enum nvic_irq_num { diff --git a/libmaple/stm32f2/include/series/nvic.h b/libmaple/stm32f2/include/series/nvic.h index c433068..dc03806 100644 --- a/libmaple/stm32f2/include/series/nvic.h +++ b/libmaple/stm32f2/include/series/nvic.h @@ -37,7 +37,7 @@ extern "C"{ #endif /** - * @brief Interrupt vector table interrupt numbers. + * @brief STM32F2 interrupt vector table interrupt numbers. */ typedef enum nvic_irq_num { NVIC_NMI = -14, /**< Non-maskable interrupt */ -- cgit v1.2.3 From 7d1fc98ab041c646767295088952bdabbf941756 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 14 May 2012 12:20:28 -0400 Subject: STM32F1: Fix nvic_irq_disable_all() on some MCUs. The current implementation only disables the first 64 IRQ lines. This covers all the chips we currently support, but it'll be a nasty surprise if anyone decides to add e.g. connectivity line MCUs (which have more IRQs) in the future. We already have the infrastructure to fix it in a clean way, so we might as well do it now. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/nvic.h | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/libmaple/stm32f1/include/series/nvic.h b/libmaple/stm32f1/include/series/nvic.h index acabd93..cdac737 100644 --- a/libmaple/stm32f1/include/series/nvic.h +++ b/libmaple/stm32f1/include/series/nvic.h @@ -37,6 +37,7 @@ extern "C"{ #endif #include +#include /** * @brief STM32F1 interrupt vector table interrupt numbers. @@ -156,16 +157,13 @@ typedef enum nvic_irq_num { } nvic_irq_num; static inline void nvic_irq_disable_all(void) { - /* Note: This only works up to XL density. The fix for - * connectivity line is: - * - * NVIC_BASE->ICER[2] = 0xF; - * - * We don't support connectivity line devices (yet), so leave it - * alone for now. - */ + /* Even low-density devices have over 32 interrupt lines. */ NVIC_BASE->ICER[0] = 0xFFFFFFFF; NVIC_BASE->ICER[1] = 0xFFFFFFFF; +#if STM32_NR_INTERRUPTS > 64 + /* Only some have over 64; e.g. connectivity line MCUs. */ + NVIC_BASE->ICER[2] = 0xFFFFFFFF; +#endif } #ifdef __cplusplus -- cgit v1.2.3 From 0e83157fcbed12cdae1b596820ad54ddc77a2608 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 16:02:37 -0400 Subject: wirish: Build board.cpp. There's enough infrastructure for a basic board.cpp on STM32F2, so we might as well bring this back. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index 17c4d05..afd78e2 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -36,7 +36,7 @@ cppSRCS_$(d) := boards.cpp # ext_interrupts.cpp \ # wirish_digital.cpp # TODO: Put this back in once we've got the necessary libmaple support back. -# cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp +cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From e63048b9a4eb678fdfaa8d733bed6a9f20b36969 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 16:03:11 -0400 Subject: : Don't include some files. These don't work on F2, so leave them out for now. Signed-off-by: Marti Bolivar --- wirish/include/wirish/wirish.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wirish/include/wirish/wirish.h b/wirish/include/wirish/wirish.h index 4097ce1..6810e4f 100644 --- a/wirish/include/wirish/wirish.h +++ b/wirish/include/wirish/wirish.h @@ -39,10 +39,10 @@ #include #include #include -#include +/* FIXME put this back when you can #include */ #include #include -#include +/* FIXME put this back when you can #include */ #include #include #include -- cgit v1.2.3 From 40c13f67e21215639b5de3bcf58955abb8f0c6ce Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 16:03:26 -0400 Subject: libmaple/usart_private.c: Add missing include. Signed-off-by: Marti Bolivar --- libmaple/usart_private.c | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/usart_private.c b/libmaple/usart_private.c index d79387a..0eaacdf 100644 --- a/libmaple/usart_private.c +++ b/libmaple/usart_private.c @@ -32,6 +32,7 @@ #include "usart_private.h" #include +#include uint32 _usart_clock_freq(usart_dev *dev) { rcc_clk_domain domain = rcc_dev_clk(dev->clk_id); -- cgit v1.2.3 From 014f9a0545556f2e0d4fb3faba5607e59e1e97ad Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 17:17:06 -0400 Subject: examples/blinky.cpp works on F2. Only OUTPUT mode is tested; any other modes might work, but no guarantees. Bring back: - wirish/wirish_digital.cpp - wirish/cxxabi-compat.cpp - wirish/wirish_time.cpp Add new: - wirish/stm32f1/wirish_digital.cpp - wirish/stm32f2/wirish_digital.cpp Move pinMode() from wirish/wirish_digital.cpp into the file by the same basename in wirish/stm32f1. This implementation is tied to F1. Add an F2 implementation in wirish/stm32f2/wirish_digital.cpp. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 14 ++-- wirish/stm32f1/wirish_digital.cpp | 89 ++++++++++++++++++++++++++ wirish/stm32f2/wirish_digital.cpp | 130 ++++++++++++++++++++++++++++++++++++++ wirish/wirish_digital.cpp | 54 +--------------- 4 files changed, 227 insertions(+), 60 deletions(-) create mode 100644 wirish/stm32f1/wirish_digital.cpp create mode 100644 wirish/stm32f2/wirish_digital.cpp diff --git a/wirish/rules.mk b/wirish/rules.mk index afd78e2..5e00a5f 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -21,6 +21,12 @@ CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) $(WIRISH_INCLUDES) -I$(d) sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c cppSRCS_$(d) := boards.cpp +cppSRCS_$(d) += cxxabi-compat.cpp +cppSRCS_$(d) += wirish_digital.cpp +cppSRCS_$(d) += wirish_time.cpp +cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp +cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp +cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: test these on F2 and put them back in: # cppSRCS_$(d) := wirish_math.cpp \ # Print.cpp \ @@ -28,16 +34,10 @@ cppSRCS_$(d) := boards.cpp # HardwareSPI.cpp \ # HardwareTimer.cpp \ # usb_serial.cpp \ -# cxxabi-compat.cpp \ # wirish_shift.cpp \ # wirish_analog.cpp \ -# wirish_time.cpp \ # pwm.cpp \ -# ext_interrupts.cpp \ -# wirish_digital.cpp -# TODO: Put this back in once we've got the necessary libmaple support back. -cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp -cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp +# ext_interrupts.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) diff --git a/wirish/stm32f1/wirish_digital.cpp b/wirish/stm32f1/wirish_digital.cpp new file mode 100644 index 0000000..8371b0e --- /dev/null +++ b/wirish/stm32f1/wirish_digital.cpp @@ -0,0 +1,89 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* + * STM32F1 implementations for basic GPIO functionality. + */ + +#include + +#include +#include + +#include + +void pinMode(uint8 pin, WiringPinMode mode) { + gpio_pin_mode outputMode; + bool pwm = false; + + if (pin >= BOARD_NR_GPIO_PINS) { + return; + } + + switch(mode) { + case OUTPUT: + outputMode = GPIO_OUTPUT_PP; + break; + case OUTPUT_OPEN_DRAIN: + outputMode = GPIO_OUTPUT_OD; + break; + case INPUT: + case INPUT_FLOATING: + outputMode = GPIO_INPUT_FLOATING; + break; + case INPUT_ANALOG: + outputMode = GPIO_INPUT_ANALOG; + break; + case INPUT_PULLUP: + outputMode = GPIO_INPUT_PU; + break; + case INPUT_PULLDOWN: + outputMode = GPIO_INPUT_PD; + break; + case PWM: + outputMode = GPIO_AF_OUTPUT_PP; + pwm = true; + break; + case PWM_OPEN_DRAIN: + outputMode = GPIO_AF_OUTPUT_OD; + pwm = true; + break; + default: + ASSERT(0); + return; + } + + gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode); + + if (PIN_MAP[pin].timer_device != NULL) { + /* Enable/disable timer channels if we're switching into or + * out of PWM. */ + timer_set_mode(PIN_MAP[pin].timer_device, + PIN_MAP[pin].timer_channel, + pwm ? TIMER_PWM : TIMER_DISABLED); + } +} diff --git a/wirish/stm32f2/wirish_digital.cpp b/wirish/stm32f2/wirish_digital.cpp new file mode 100644 index 0000000..a67111d --- /dev/null +++ b/wirish/stm32f2/wirish_digital.cpp @@ -0,0 +1,130 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* + * STM32F2 implementations for basic GPIO functionality. + */ + +#include + +#include +#include + +#include + +void pinMode(uint8 pin, WiringPinMode w_mode) { + if (pin >= BOARD_NR_GPIO_PINS) { + return; + } + + gpio_pin_mode mode; + // People always do the silly pin-toggle speed benchmark, so let's + // accomodate them: + unsigned flags = GPIO_MODEF_SPEED_HIGH; + bool pwm = false; + switch(w_mode) { + case OUTPUT: + mode = GPIO_MODE_OUTPUT; + break; + case OUTPUT_OPEN_DRAIN: + mode = GPIO_MODE_OUTPUT; + flags |= GPIO_MODEF_TYPE_OD; + break; + case INPUT: + case INPUT_FLOATING: + mode = GPIO_MODE_INPUT; + break; + case INPUT_ANALOG: + mode = GPIO_MODE_ANALOG; + break; + case INPUT_PULLUP: + mode = GPIO_MODE_INPUT; + flags |= GPIO_MODEF_PUPD_PU; + break; + case INPUT_PULLDOWN: + mode = GPIO_MODE_INPUT; + flags |= GPIO_MODEF_PUPD_PD; + break; + case PWM: + mode = GPIO_MODE_AF; + pwm = true; + break; + case PWM_OPEN_DRAIN: + mode = GPIO_MODE_AF; + flags |= GPIO_MODEF_TYPE_OD; + pwm = true; + break; + default: + ASSERT(0); // Can't happen + return; + } + + const stm32_pin_info *info = &PIN_MAP[pin]; + + if (pwm) { + /* If enabling PWM, tell the timer to do PWM, and tell the pin + * to listen to the right timer. */ + ASSERT(info->timer_device != NULL); + if (info->timer_device == NULL) { + return; + } + gpio_af timer_af; + /* TODO make this code a convenience + * routine for series that support GPIO alternate + * functions. */ + switch(info->timer_device->clk_id) { + case RCC_TIMER1: // fall-through + case RCC_TIMER2: + timer_af = GPIO_AF_TIM_1_2; + break; + case RCC_TIMER3: // fall-through + case RCC_TIMER4: // ... + case RCC_TIMER5: + timer_af = GPIO_AF_TIM_3_4_5; + break; + /* Timers 6 and 7 don't have any capture/compare, so they + * can't do PWM (and in fact have no AF values). */ + case RCC_TIMER8: // fall-through + case RCC_TIMER9: // ... + case RCC_TIMER10: // ... + case RCC_TIMER11: + timer_af = GPIO_AF_TIM_8_9_10_11; + break; + case RCC_TIMER12: // fall-through + case RCC_TIMER13: // ... + case RCC_TIMER14: + timer_af = GPIO_AF_CAN_1_2_TIM_12_13_14; + break; + default: + ASSERT(0); // Can't happen + return; + } + timer_set_mode(info->timer_device, info->timer_channel, TIMER_PWM); + gpio_set_af(info->gpio_device, info->gpio_bit, timer_af); + } else { + gpio_set_modef(info->gpio_device, info->gpio_bit, mode, flags); + } +} diff --git a/wirish/wirish_digital.cpp b/wirish/wirish_digital.cpp index 6be1a29..a7f10cd 100644 --- a/wirish/wirish_digital.cpp +++ b/wirish/wirish_digital.cpp @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -36,59 +37,6 @@ #include #include -void pinMode(uint8 pin, WiringPinMode mode) { - gpio_pin_mode outputMode; - bool pwm = false; - - if (pin >= BOARD_NR_GPIO_PINS) { - return; - } - - switch(mode) { - case OUTPUT: - outputMode = GPIO_OUTPUT_PP; - break; - case OUTPUT_OPEN_DRAIN: - outputMode = GPIO_OUTPUT_OD; - break; - case INPUT: - case INPUT_FLOATING: - outputMode = GPIO_INPUT_FLOATING; - break; - case INPUT_ANALOG: - outputMode = GPIO_INPUT_ANALOG; - break; - case INPUT_PULLUP: - outputMode = GPIO_INPUT_PU; - break; - case INPUT_PULLDOWN: - outputMode = GPIO_INPUT_PD; - break; - case PWM: - outputMode = GPIO_AF_OUTPUT_PP; - pwm = true; - break; - case PWM_OPEN_DRAIN: - outputMode = GPIO_AF_OUTPUT_OD; - pwm = true; - break; - default: - ASSERT(0); - return; - } - - gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode); - - if (PIN_MAP[pin].timer_device != NULL) { - /* Enable/disable timer channels if we're switching into or - * out of PWM. */ - timer_set_mode(PIN_MAP[pin].timer_device, - PIN_MAP[pin].timer_channel, - pwm ? TIMER_PWM : TIMER_DISABLED); - } -} - - uint32 digitalRead(uint8 pin) { if (pin >= BOARD_NR_GPIO_PINS) { return 0; -- cgit v1.2.3 From 1ed01dad43f95be2af258d44d03fcafde5714942 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 18:43:18 -0400 Subject: : Fix gpio_write_bit(). It's exactly wrong -- val=0 makes the pin high, and val=1 makes it low. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/gpio.h b/libmaple/include/libmaple/gpio.h index f7773c0..ca7b2bf 100644 --- a/libmaple/include/libmaple/gpio.h +++ b/libmaple/include/libmaple/gpio.h @@ -63,7 +63,7 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode); * @param val If true, set the pin. If false, reset the pin. */ static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) { - val = !!val; + val = !val; /* "set" bits are lower than "reset" bits */ dev->regs->BSRR = BIT(pin) << (16 * val); } -- cgit v1.2.3 From 322a324963d8210dbbe529357b41e7c9ff8f8db6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 18:44:26 -0400 Subject: stm32f2/gpio.c: Fix some bugs. Make gpioh.regs actually point to GPIOH_BASE. Properly AND out flag bits in gpio_set_modef(). Signed-off-by: Marti Bolivar --- libmaple/stm32f2/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libmaple/stm32f2/gpio.c b/libmaple/stm32f2/gpio.c index 7479922..f2cd776 100644 --- a/libmaple/stm32f2/gpio.c +++ b/libmaple/stm32f2/gpio.c @@ -87,7 +87,7 @@ gpio_dev gpiog = { gpio_dev* const GPIOG = &gpiog; gpio_dev gpioh = { - .regs = GPIOG_BASE, + .regs = GPIOH_BASE, .clk_id = RCC_GPIOH, }; /** GPIO port G device. */ @@ -146,13 +146,13 @@ void gpio_set_modef(gpio_dev *dev, /* Speed */ tmp = regs->OSPEEDR; tmp &= ~(0x3 << shift); - tmp |= (flags >> 1) << shift; + tmp |= ((flags >> 1) & 0x3) << shift; regs->OSPEEDR = tmp; /* Pull-up/pull-down */ tmp = regs->PUPDR; tmp &= ~(0x3 << shift); - tmp |= (flags >> 2) << shift; + tmp |= ((flags >> 3) & 0x3) << shift; regs->PUPDR = tmp; } -- cgit v1.2.3 From 77abda29002216bd8186b430f484c98666a52339 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 18:47:39 -0400 Subject: Replace shiftOut(), also fixing a possible bug. The current shiftOut() is borrowed from Arduino, and is in an LGPL file. Replace that file with a new MIT-licensed version containing a new implementation. The new version brings the clock line LOW before starting, to make sure that the first pulse is detected if the clock line was previously HIGH. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 2 +- wirish/wirish_shift.cpp | 59 +++++++++++++++++++++++-------------------------- 2 files changed, 29 insertions(+), 32 deletions(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index 5e00a5f..0b0b82c 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -24,6 +24,7 @@ cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += wirish_digital.cpp cppSRCS_$(d) += wirish_time.cpp +cppSRCS_$(d) += wirish_shift.cpp cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp @@ -34,7 +35,6 @@ cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # HardwareSPI.cpp \ # HardwareTimer.cpp \ # usb_serial.cpp \ -# wirish_shift.cpp \ # wirish_analog.cpp \ # pwm.cpp \ # ext_interrupts.cpp diff --git a/wirish/wirish_shift.cpp b/wirish/wirish_shift.cpp index 0f24f59..a032d50 100644 --- a/wirish/wirish_shift.cpp +++ b/wirish/wirish_shift.cpp @@ -1,40 +1,37 @@ -/* - * wiring_shift.c - shiftOut() function - * Part of Arduino - http://www.arduino.cc/ +/****************************************************************************** + * The MIT License * - * Copyright (c) 2005-2006 David A. Mellis + * Copyright (c) 2012 LeafLabs, LLC. * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: * - * This library is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - * - * $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ - */ + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ #include -void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 val) { - int i; - - for (i = 0; i < 8; i++) { - if (bitOrder == LSBFIRST) { - digitalWrite(dataPin, !!(val & (1 << i))); - } else { - digitalWrite(dataPin, !!(val & (1 << (7 - i)))); - } - - digitalWrite(clockPin, HIGH); - digitalWrite(clockPin, LOW); +void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value) { + digitalWrite(clockPin, LOW); + for (int i = 0; i < 8; i++) { + int bit = bitOrder == LSBFIRST ? i : (7 - i); + digitalWrite(dataPin, (value >> bit) & 0x1); + togglePin(clockPin); + togglePin(clockPin); } } -- cgit v1.2.3 From e630db87d2d30341e7b1b3db30c3a0c768adae5f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 18:55:44 -0400 Subject: Assert LeafLabs copyright in wirish/Print.cpp. This should get replaced with a clean-room MIT licensed version, but pieces of it are ours (notably the bugfixes to the floating point printing routines), so might as well do the copyright thing. Signed-off-by: Marti Bolivar --- wirish/Print.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/wirish/Print.cpp b/wirish/Print.cpp index 1a2bddb..f6bc0c6 100644 --- a/wirish/Print.cpp +++ b/wirish/Print.cpp @@ -1,6 +1,7 @@ /* * Print.cpp - Base class that provides print() and println() * Copyright (c) 2008 David A. Mellis. All right reserved. + * Copyright (c) 2011 LeafLabs, LLC. * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public License -- cgit v1.2.3 From bf47524bc9956030ff03ec776660994d71224ddb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 18:57:41 -0400 Subject: Bring back wirish/Print.cpp. The only nonportable parts of this file are based on the assumption that we're on ILP32. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index 0b0b82c..b795f60 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -22,6 +22,7 @@ sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp +cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += wirish_digital.cpp cppSRCS_$(d) += wirish_time.cpp cppSRCS_$(d) += wirish_shift.cpp @@ -30,7 +31,6 @@ cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: test these on F2 and put them back in: # cppSRCS_$(d) := wirish_math.cpp \ -# Print.cpp \ # HardwareSerial.cpp \ # HardwareSPI.cpp \ # HardwareTimer.cpp \ -- cgit v1.2.3 From bb3fa82563a121e76680f3d4b38fe4ecdf809dde Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 19:15:43 -0400 Subject: wirish/rules.mk: Cosmetics. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index b795f60..0e99e2c 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -24,20 +24,20 @@ cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += wirish_digital.cpp -cppSRCS_$(d) += wirish_time.cpp cppSRCS_$(d) += wirish_shift.cpp +cppSRCS_$(d) += wirish_time.cpp cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp -# TODO: test these on F2 and put them back in: -# cppSRCS_$(d) := wirish_math.cpp \ -# HardwareSerial.cpp \ -# HardwareSPI.cpp \ -# HardwareTimer.cpp \ -# usb_serial.cpp \ -# wirish_analog.cpp \ -# pwm.cpp \ -# ext_interrupts.cpp +# TODO: revise these appropriately F2 and put them back in: +# wirish_math.cpp +# HardwareSerial.cpp +# HardwareSPI.cpp +# HardwareTimer.cpp +# usb_serial.cpp +# wirish_analog.cpp +# pwm.cpp +# ext_interrupts.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From b1e06d3acaa72976042314c1debec008c5ac54d7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 31 May 2012 19:20:01 -0400 Subject: Bring back wirish/wirish_math.cpp. This is portable. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index 0e99e2c..903c817 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -24,13 +24,13 @@ cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += wirish_digital.cpp +cppSRCS_$(d) += wirish_math.cpp cppSRCS_$(d) += wirish_shift.cpp cppSRCS_$(d) += wirish_time.cpp cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately F2 and put them back in: -# wirish_math.cpp # HardwareSerial.cpp # HardwareSPI.cpp # HardwareTimer.cpp -- cgit v1.2.3 From d483f8fa0c7c1f65c926b24d6c66275953d03c4f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 01:10:47 -0400 Subject: Bring back HardwareSerial. To make this happen, we need to have tell us whether or not it's got each of the USARTs. Do that with BOARD_HAVE_USARTn, for n = 1,...,6. This lets us define HardwareSerial instances only when appropriate, and gets rid of some board-specific hacks we'd accumulated. The new now has a convenience function for determining the bus rate by using the appropriate STM32_PCLKx macro, so we can shave a uint32 per instance, which is nice given that they're all going to be in memory. This changes the constructor arguments, but the API only specifies the semantics of the predefined instances, so this is still backwards-compatible. (We should look into storing the instances in Flash -- they don't change, after all.) We don't actually need struct usart_dev's definition in HardwareSerial.h, so replace it with a forward declaration and include it in HardwareSerial.cpp instead. Assert some copyrights. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/usart.h | 1 + wirish/HardwareSerial.cpp | 98 ++++++++++++---------- wirish/boards/VLDiscovery/include/board/board.h | 6 ++ wirish/boards/maple/include/board/board.h | 9 +- wirish/boards/maple_RET6/include/board/board.h | 11 ++- wirish/boards/maple_mini/include/board/board.h | 6 ++ wirish/boards/maple_native/include/board/board.h | 6 ++ .../boards/olimex_stm32_h103/include/board/board.h | 6 ++ .../boards/st_stm3220g_eval/include/board/board.h | 12 ++- wirish/include/wirish/HardwareSerial.h | 26 ++++-- wirish/rules.mk | 2 +- 11 files changed, 127 insertions(+), 56 deletions(-) diff --git a/libmaple/include/libmaple/usart.h b/libmaple/include/libmaple/usart.h index ad7eb51..293d59e 100644 --- a/libmaple/include/libmaple/usart.h +++ b/libmaple/include/libmaple/usart.h @@ -395,6 +395,7 @@ typedef struct usart_dev { void usart_init(usart_dev *dev); +/* FIXME document this function */ struct gpio_dev; /* forward declaration */ void usart_async_gpio_cfg(usart_dev *udev, struct gpio_dev *rx_dev, uint8 rx, diff --git a/wirish/HardwareSerial.cpp b/wirish/HardwareSerial.cpp index 0f12e72..3f418e2 100644 --- a/wirish/HardwareSerial.cpp +++ b/wirish/HardwareSerial.cpp @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -34,36 +35,36 @@ #include #include #include +#include -#include - -#define TX1 BOARD_USART1_TX_PIN -#define RX1 BOARD_USART1_RX_PIN -#define TX2 BOARD_USART2_TX_PIN -#define RX2 BOARD_USART2_RX_PIN -#define TX3 BOARD_USART3_TX_PIN -#define RX3 BOARD_USART3_RX_PIN -#if defined STM32_HIGH_DENSITY && !defined(BOARD_maple_RET6) -#define TX4 BOARD_UART4_TX_PIN -#define RX4 BOARD_UART4_RX_PIN -#define TX5 BOARD_UART5_TX_PIN -#define RX5 BOARD_UART5_RX_PIN -#endif +#define DEFINE_HWSERIAL(name, n) \ + HardwareSerial name(USART##n, \ + BOARD_USART##n##_TX_PIN, \ + BOARD_USART##n##_RX_PIN) -HardwareSerial Serial1(USART1, TX1, RX1, STM32_PCLK2); -HardwareSerial Serial2(USART2, TX2, RX2, STM32_PCLK1); -HardwareSerial Serial3(USART3, TX3, RX3, STM32_PCLK1); -#if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6) -HardwareSerial Serial4(UART4, TX4, RX4, STM32_PCLK1); -HardwareSerial Serial5(UART5, TX5, RX5, STM32_PCLK1); +#if BOARD_HAVE_USART1 +DEFINE_HWSERIAL(Serial1, 1); +#endif +#if BOARD_HAVE_USART2 +DEFINE_HWSERIAL(Serial2, 2); +#endif +#if BOARD_HAVE_USART3 +DEFINE_HWSERIAL(Serial3, 3); +#endif +#if BOARD_HAVE_UART4 +DEFINE_HWSERIAL(Serial4, 4); +#endif +#if BOARD_HAVE_UART5 +DEFINE_HWSERIAL(Serial5, 5); +#endif +#if BOARD_HAVE_USART6 +DEFINE_HWSERIAL(Serial6, 6); #endif HardwareSerial::HardwareSerial(usart_dev *usart_device, uint8 tx_pin, - uint8 rx_pin, - uint32 clock_speed) { + uint8 rx_pin) { this->usart_device = usart_device; - this->clock_speed = clock_speed; this->tx_pin = tx_pin; this->rx_pin = rx_pin; } @@ -72,31 +73,44 @@ HardwareSerial::HardwareSerial(usart_dev *usart_device, * Set up/tear down */ +#if STM32_MCU_SERIES == STM32_SERIES_F1 +/* F1 MCUs have no GPIO_AFR[HL], so turn off PWM if there's a conflict + * on this GPIO bit. */ +static void disable_timer_if_necessary(timer_dev *dev, uint8 ch) { + if (txi->timer_device != NULL) { + timer_set_mode(txi->timer_device, txi->timer_channel, TIMER_DISABLED); + } +} +#elif (STM32_MCU_SERIES == STM32_SERIES_F2) || \ + (STM32_MCU_SERIES == STM32_SERIES_F4) +#define disable_timer_if_necessary(dev, ch) ((void)0) +#else +#warn "Unsupported STM32 series; timer conflicts are possible" +#endif + void HardwareSerial::begin(uint32 baud) { - ASSERT(baud <= usart_device->max_baud); + ASSERT(baud <= this->usart_device->max_baud); - if (baud > usart_device->max_baud) { + if (baud > this->usart_device->max_baud) { return; } - const stm32_pin_info *txi = &PIN_MAP[tx_pin]; - const stm32_pin_info *rxi = &PIN_MAP[rx_pin]; + const stm32_pin_info *txi = &PIN_MAP[this->tx_pin]; + const stm32_pin_info *rxi = &PIN_MAP[this->rx_pin]; - gpio_set_mode(txi->gpio_device, txi->gpio_bit, GPIO_AF_OUTPUT_PP); - gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, GPIO_INPUT_FLOATING); - - if (txi->timer_device != NULL) { - /* Turn off any PWM if there's a conflict on this GPIO bit. */ - timer_set_mode(txi->timer_device, txi->timer_channel, TIMER_DISABLED); - } + disable_timer_if_necessary(txi->timer_device, txi->timer_channel); - usart_init(usart_device); - usart_set_baud_rate(usart_device, clock_speed, baud); - usart_enable(usart_device); + usart_async_gpio_cfg(this->usart_device, + rxi->gpio_device, rxi->gpio_bit, + txi->gpio_device, txi->gpio_bit, + 0); + usart_init(this->usart_device); + usart_set_baud_rate(this->usart_device, USART_USE_PCLK, baud); + usart_enable(this->usart_device); } void HardwareSerial::end(void) { - usart_disable(usart_device); + usart_disable(this->usart_device); } /* @@ -104,17 +118,17 @@ void HardwareSerial::end(void) { */ uint8 HardwareSerial::read(void) { - return usart_getc(usart_device); + return usart_getc(this->usart_device); } uint32 HardwareSerial::available(void) { - return usart_data_available(usart_device); + return usart_data_available(this->usart_device); } void HardwareSerial::write(unsigned char ch) { - usart_putc(usart_device, ch); + usart_putc(this->usart_device, ch); } void HardwareSerial::flush(void) { - usart_reset_rx(usart_device); + usart_reset_rx(this->usart_device); } diff --git a/wirish/boards/VLDiscovery/include/board/board.h b/wirish/boards/VLDiscovery/include/board/board.h index 04d21c7..c54abc1 100644 --- a/wirish/boards/VLDiscovery/include/board/board.h +++ b/wirish/boards/VLDiscovery/include/board/board.h @@ -45,6 +45,12 @@ /* Number of USARTs/UARTs whose pins are broken out to headers */ #define BOARD_NR_USARTS 3 +#define BOARD_HAVE_USART1 1 +#define BOARD_HAVE_USART2 1 +#define BOARD_HAVE_USART3 1 +#define BOARD_HAVE_UART4 0 +#define BOARD_HAVE_UART5 0 +#define BOARD_HAVE_USART6 0 /* Default USART pin numbers (not considering AFIO remap) */ #define BOARD_USART1_TX_PIN 7 diff --git a/wirish/boards/maple/include/board/board.h b/wirish/boards/maple/include/board/board.h index 49f5b9a..ed89fee 100644 --- a/wirish/boards/maple/include/board/board.h +++ b/wirish/boards/maple/include/board/board.h @@ -39,8 +39,15 @@ #define BOARD_BUTTON_PIN 38 #define BOARD_LED_PIN 13 -/* Number of USARTs/UARTs whose pins are broken out to headers */ +/* Number of USARTs/UARTs whose pins are broken out to headers, and + * macros saying which ones they are. */ #define BOARD_NR_USARTS 3 +#define BOARD_HAVE_USART1 1 +#define BOARD_HAVE_USART2 1 +#define BOARD_HAVE_USART3 1 +#define BOARD_HAVE_UART4 0 +#define BOARD_HAVE_UART5 0 +#define BOARD_HAVE_USART6 0 /* Default USART pin numbers (not considering AFIO remap) */ #define BOARD_USART1_TX_PIN 7 diff --git a/wirish/boards/maple_RET6/include/board/board.h b/wirish/boards/maple_RET6/include/board/board.h index 1a0365a..3291498 100644 --- a/wirish/boards/maple_RET6/include/board/board.h +++ b/wirish/boards/maple_RET6/include/board/board.h @@ -36,17 +36,20 @@ #ifndef _BOARDS_MAPLE_RET6_H_ #define _BOARDS_MAPLE_RET6_H_ -/* A few of these values will seem strange given that it's a - * high-density board. */ - #define CYCLES_PER_MICROSECOND 72 #define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ #define BOARD_BUTTON_PIN 38 #define BOARD_LED_PIN 13 -/* Note: UART4 and UART5 have pins which aren't broken out :( */ +/* UART4 and UART5 have pins which aren't broken out :( */ #define BOARD_NR_USARTS 3 +#define BOARD_HAVE_USART1 1 +#define BOARD_HAVE_USART2 1 +#define BOARD_HAVE_USART3 1 +#define BOARD_HAVE_UART4 0 +#define BOARD_HAVE_UART5 0 +#define BOARD_HAVE_USART6 0 #define BOARD_USART1_TX_PIN 7 #define BOARD_USART1_RX_PIN 8 #define BOARD_USART2_TX_PIN 1 diff --git a/wirish/boards/maple_mini/include/board/board.h b/wirish/boards/maple_mini/include/board/board.h index bfba46d..8ba91ce 100644 --- a/wirish/boards/maple_mini/include/board/board.h +++ b/wirish/boards/maple_mini/include/board/board.h @@ -43,6 +43,12 @@ #define BOARD_LED_PIN 33 #define BOARD_NR_USARTS 3 +#define BOARD_HAVE_USART1 1 +#define BOARD_HAVE_USART2 1 +#define BOARD_HAVE_USART3 1 +#define BOARD_HAVE_UART4 0 +#define BOARD_HAVE_UART5 0 +#define BOARD_HAVE_USART6 0 #define BOARD_USART1_TX_PIN 26 #define BOARD_USART1_RX_PIN 25 #define BOARD_USART2_TX_PIN 9 diff --git a/wirish/boards/maple_native/include/board/board.h b/wirish/boards/maple_native/include/board/board.h index 397afaf..a4f8896 100644 --- a/wirish/boards/maple_native/include/board/board.h +++ b/wirish/boards/maple_native/include/board/board.h @@ -43,6 +43,12 @@ #define BOARD_BUTTON_PIN 6 #define BOARD_NR_USARTS 5 +#define BOARD_HAVE_USART1 1 +#define BOARD_HAVE_USART2 1 +#define BOARD_HAVE_USART3 1 +#define BOARD_HAVE_UART4 1 +#define BOARD_HAVE_UART5 1 +#define BOARD_HAVE_USART6 0 #define BOARD_USART1_TX_PIN 24 #define BOARD_USART1_RX_PIN 25 #define BOARD_USART2_TX_PIN 50 diff --git a/wirish/boards/olimex_stm32_h103/include/board/board.h b/wirish/boards/olimex_stm32_h103/include/board/board.h index b312e26..46367ac 100644 --- a/wirish/boards/olimex_stm32_h103/include/board/board.h +++ b/wirish/boards/olimex_stm32_h103/include/board/board.h @@ -42,6 +42,12 @@ /* Number of USARTs/UARTs whose pins are broken out to headers */ #define BOARD_NR_USARTS 3 +#define BOARD_HAVE_USART1 1 +#define BOARD_HAVE_USART2 1 +#define BOARD_HAVE_USART3 1 +#define BOARD_HAVE_UART4 0 +#define BOARD_HAVE_UART5 0 +#define BOARD_HAVE_USART6 0 /* Default USART pin numbers (not considering AFIO remap) */ #define BOARD_USART1_TX_PIN 3 diff --git a/wirish/boards/st_stm3220g_eval/include/board/board.h b/wirish/boards/st_stm3220g_eval/include/board/board.h index 08b935e..f99a585 100644 --- a/wirish/boards/st_stm3220g_eval/include/board/board.h +++ b/wirish/boards/st_stm3220g_eval/include/board/board.h @@ -27,7 +27,11 @@ /** * @file wirish/boards/st_stm3220g_eval/include/board/board.h * @author Marti Bolivar - * @brief STM3220G-EVAL board header. + * @brief STM3220G-EVAL board stub header. + * + * This (and the corresponding board.cpp) needs to be fixed and + * fleshed out. Do it later? Maybe someone who wants support for this + * board will do it. */ #ifndef _BOARD_ST_STM3220G_EVAL_H_ @@ -40,6 +44,12 @@ #define BOARD_LED_PIN 0 #define BOARD_NR_USARTS 0 +#define BOARD_HAVE_USART1 0 +#define BOARD_HAVE_USART2 0 +#define BOARD_HAVE_USART3 0 +#define BOARD_HAVE_UART4 0 +#define BOARD_HAVE_UART5 0 +#define BOARD_HAVE_USART6 0 #define BOARD_NR_SPI 0 #define BOARD_NR_GPIO_PINS 6 #define BOARD_NR_PWM_PINS 0 diff --git a/wirish/include/wirish/HardwareSerial.h b/wirish/include/wirish/HardwareSerial.h index 1eaacb6..2b1e747 100644 --- a/wirish/include/wirish/HardwareSerial.h +++ b/wirish/include/wirish/HardwareSerial.h @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -33,9 +34,9 @@ #define _WIRISH_HARDWARESERIAL_H_ #include -#include #include +#include /* * IMPORTANT: @@ -47,12 +48,13 @@ * the documentation accordingly. */ +struct usart_dev; + class HardwareSerial : public Print { public: - HardwareSerial(usart_dev *usart_device, + HardwareSerial(struct usart_dev *usart_device, uint8 tx_pin, - uint8 rx_pin, - uint32 clock_speed); + uint8 rx_pin); /* Set up/tear down */ void begin(uint32 baud); @@ -69,18 +71,28 @@ public: int txPin(void) { return this->tx_pin; } int rxPin(void) { return this->rx_pin; } private: - usart_dev *usart_device; + struct usart_dev *usart_device; uint8 tx_pin; uint8 rx_pin; - uint32 clock_speed; }; +#if BOARD_HAVE_USART1 extern HardwareSerial Serial1; +#endif +#if BOARD_HAVE_USART2 extern HardwareSerial Serial2; +#endif +#if BOARD_HAVE_USART3 extern HardwareSerial Serial3; -#if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6) +#endif +#if BOARD_HAVE_UART4 extern HardwareSerial Serial4; +#endif +#if BOARD_HAVE_UART5 extern HardwareSerial Serial5; #endif +#if BOARD_HAVE_USART6 +extern HardwareSerial Serial6; +#endif #endif diff --git a/wirish/rules.mk b/wirish/rules.mk index 903c817..4084448 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -22,6 +22,7 @@ sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp +cppSRCS_$(d) += HardwareSerial.cpp cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += wirish_digital.cpp cppSRCS_$(d) += wirish_math.cpp @@ -31,7 +32,6 @@ cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately F2 and put them back in: -# HardwareSerial.cpp # HardwareSPI.cpp # HardwareTimer.cpp # usb_serial.cpp -- cgit v1.2.3 From 51e0ae832fdf909cea09f72dd9f7d36edf274780 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 01:29:23 -0400 Subject: Add examples/serial-echo.cpp. Serial1 writes back what it receives. Signed-off-by: Marti Bolivar --- examples/serial-echo.cpp | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 examples/serial-echo.cpp diff --git a/examples/serial-echo.cpp b/examples/serial-echo.cpp new file mode 100644 index 0000000..204f011 --- /dev/null +++ b/examples/serial-echo.cpp @@ -0,0 +1,30 @@ +// Simple serial port "echo". Send back any received data. + +#include + +// Note: you can change "Serial1" to any other serial port you have on +// your board. + +void setup() { + Serial1.begin(115200); +} + +void loop() { + while (Serial1.available()) { + Serial1.write(Serial1.read()); + } +} + +// Force init() to be called before anything else. +__attribute__((constructor)) void premain() { + init(); +} + +int main(void) { + setup(); + + while (true) { + loop(); + } + return 0; +} -- cgit v1.2.3 From cc8a5cbaad299c0cfbf730042014cf12bc0cb975 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 01:29:54 -0400 Subject: stm32f2/usart.c: Change some FIXMEs to TODOs. I think these are probably unchanged, but we need to make sure. Signed-off-by: Marti Bolivar --- libmaple/stm32f2/usart.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/libmaple/stm32f2/usart.c b/libmaple/stm32f2/usart.c index e4fc9b1..2dd3afc 100644 --- a/libmaple/stm32f2/usart.c +++ b/libmaple/stm32f2/usart.c @@ -42,7 +42,7 @@ static ring_buffer usart1_rb; static usart_dev usart1 = { .regs = USART1_BASE, .rb = &usart1_rb, - .max_baud = 4500000UL, /* FIXME */ + .max_baud = 4500000UL, /* TODO: are these correct? */ .clk_id = RCC_USART1, .irq_num = NVIC_USART1, }; @@ -53,7 +53,7 @@ static ring_buffer usart2_rb; static usart_dev usart2 = { .regs = USART2_BASE, .rb = &usart2_rb, - .max_baud = 2250000UL, /* FIXME */ + .max_baud = 2250000UL, /* TODO: are these correct? */ .clk_id = RCC_USART2, .irq_num = NVIC_USART2, }; @@ -64,7 +64,7 @@ static ring_buffer usart3_rb; static usart_dev usart3 = { .regs = USART3_BASE, .rb = &usart3_rb, - .max_baud = 2250000UL, /* FIXME */ + .max_baud = 2250000UL, /* TODO: are these correct? */ .clk_id = RCC_USART3, .irq_num = NVIC_USART3, }; @@ -75,7 +75,7 @@ static ring_buffer uart4_rb; static usart_dev uart4 = { .regs = UART4_BASE, .rb = &uart4_rb, - .max_baud = 2250000UL, /* FIXME */ + .max_baud = 2250000UL, /* TODO: are these correct? */ .clk_id = RCC_UART4, .irq_num = NVIC_UART4, }; @@ -86,7 +86,7 @@ static ring_buffer uart5_rb; static usart_dev uart5 = { .regs = UART5_BASE, .rb = &uart5_rb, - .max_baud = 2250000UL, /* FIXME */ + .max_baud = 2250000UL, /* TODO: are these correct? */ .clk_id = RCC_UART5, .irq_num = NVIC_UART5, }; @@ -97,7 +97,7 @@ static ring_buffer usart6_rb; static usart_dev usart6 = { .regs = USART6_BASE, .rb = &usart6_rb, - .max_baud = 4500000UL, /* FIXME */ + .max_baud = 4500000UL, /* TODO: are these correct? */ .clk_id = RCC_USART6, .irq_num = NVIC_USART6, }; @@ -112,6 +112,7 @@ void usart_async_gpio_cfg(usart_dev *udev, gpio_dev *tx_dev, uint8 tx, unsigned flags) { gpio_af af; + /* TODO: break this out into a user-facing function. */ switch (udev->clk_id) { case RCC_USART1: case RCC_USART2: -- cgit v1.2.3 From c134c8b1e1df0b06d21aa98e385e0255107319a0 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 01:30:06 -0400 Subject: examples/debug-dtrrts.cpp: Cosmetics. Signed-off-by: Marti Bolivar --- examples/debug-dtrrts.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/examples/debug-dtrrts.cpp b/examples/debug-dtrrts.cpp index 0286212..75eceef 100644 --- a/examples/debug-dtrrts.cpp +++ b/examples/debug-dtrrts.cpp @@ -31,9 +31,8 @@ __attribute__((constructor)) void premain() { int main(void) { setup(); - while (1) { + while (true) { loop(); } return 0; } - -- cgit v1.2.3 From 33a2fff2fc60ea0e6938d72c81812b2afb3bfb0e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 02:04:59 -0400 Subject: Bring back analogRead(). Yay, it just worked! Still, while we're here, touch up the make-up on wirish_analog.cpp. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 2 +- wirish/wirish_analog.cpp | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index 4084448..deb3906 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -24,6 +24,7 @@ cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += HardwareSerial.cpp cppSRCS_$(d) += Print.cpp +cppSRCS_$(d) += wirish_analog.cpp cppSRCS_$(d) += wirish_digital.cpp cppSRCS_$(d) += wirish_math.cpp cppSRCS_$(d) += wirish_shift.cpp @@ -35,7 +36,6 @@ cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # HardwareSPI.cpp # HardwareTimer.cpp # usb_serial.cpp -# wirish_analog.cpp # pwm.cpp # ext_interrupts.cpp diff --git a/wirish/wirish_analog.cpp b/wirish/wirish_analog.cpp index 7a12156..91ca0e2 100644 --- a/wirish/wirish_analog.cpp +++ b/wirish/wirish_analog.cpp @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -25,17 +26,17 @@ *****************************************************************************/ /** - * @brief Arduino-compatible ADC implementation. + * @file wirish/wirish_analog.cpp + * @brief Wiring-style analogRead() implementation. */ #include - #include - #include -/* Assumes that the ADC has been initialized and that the pin is set - * to INPUT_ANALOG */ +/* Unlike Wiring and Arduino, this assumes that the pin's mode is set + * to INPUT_ANALOG. That's faster, but it does require some extra work + * on the user's part. Not too much, we think ;). */ uint16 analogRead(uint8 pin) { const adc_dev *dev = PIN_MAP[pin].adc_device; if (dev == NULL) { -- cgit v1.2.3 From 5befb0826a1ff77994c55f42cd73ccf0905a5ce0 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 03:05:56 -0400 Subject: libmaple/stm32.h: Add STM32_TIMER_MASK, STM32_HAVE_TIMER. Feature-test macros for dealing with the fact that timer support has holes. STM32_TIMER_MASK is a bitmask where bit n is set when TIMERn is present. STM32_HAVE_TIMER(n) just tests whether bit n is set in STM32_TIMER_MASK. This is necessary because e.g. the STM32F100RB has timers 1-4, 6, 7, and 15-17. Because of this, the usual STM32_NR_whatever won't work, and we use a bitmask instead. For F1 performance line (F103s), STM32_TIMER_MASK can be derived from the density. For F1 value line, I'm not as sure, so just add it for the single MCU we support (the STM32F100RB). Same story for F2: add it for the STM32F207IC. We can fix this up later if necessary. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 43 ++++++++++++++++++++++++++++++--- libmaple/stm32f1/include/series/stm32.h | 8 ++++++ libmaple/stm32f2/include/series/stm32.h | 1 + 3 files changed, 48 insertions(+), 4 deletions(-) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 097a016..94fb689 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -70,14 +70,36 @@ extern "C" { #include /* Ensure the series header isn't broken. */ -#if (!defined(STM32_PCLK1) || !defined(STM32_PCLK2) || \ - !defined(STM32_MCU_SERIES) || !defined(STM32_NR_INTERRUPTS) || \ - !defined(STM32_NR_GPIO_PORTS) || !defined(STM32_DELAY_US_MULT) || \ - !defined(STM32_SRAM_END) || !defined(STM32_HAVE_FSMC) || \ +#if (!defined(STM32_PCLK1) || \ + !defined(STM32_PCLK2) || \ + !defined(STM32_MCU_SERIES) || \ + !defined(STM32_NR_INTERRUPTS) || \ + !defined(STM32_NR_GPIO_PORTS) || \ + !defined(STM32_TIMER_MASK) || \ + !defined(STM32_DELAY_US_MULT) || \ + !defined(STM32_SRAM_END) || \ + !defined(STM32_HAVE_FSMC) || \ !defined(STM32_HAVE_USB)) #error "Bad STM32F1 configuration. Check header for your MCU." #endif +/* + * Derived macros + */ + +/* FIXME [0.0.13] add this to ReST API page */ +/** + * @brief Statically determine whether a timer is present. + * + * Given a constant timer number n (starting from 1), this macro has a + * nonzero value exactly when TIMERn is available. + */ +#define STM32_HAVE_TIMER(n) (STM32_TIMER_MASK & (1 << (n))) + +/* + * Doxygen for functionality provided by series header. + */ + #ifdef __DOXYGEN__ /* @@ -128,6 +150,19 @@ extern "C" { */ #define STM32_NR_GPIO_PORTS +/* FIXME [0.0.13] add this to ReST API page */ +/** + * @brief Bitmask of timers available on the MCU. + * + * That is, if TIMERn is available, then STM32_TIMER_MASK & (1 << n) + * will be nonzero. For example, a nonzero value of "STM32_TIMER_MASK + * & 0x2" means TIMER1 is available. + * + * A bitmask is necessary as some STM32 MCUs have "holes" in the range + * of available timers. + */ +#define STM32_TIMER_MASK + /** * @brief Multiplier to convert microseconds into loop iterations * in delay_us(). diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index e01c494..59205c3 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -94,6 +94,7 @@ extern "C" { #elif defined(MCU_STM32F100RB) # define STM32_F1_LINE STM32_F1_LINE_VALUE # define STM32_NR_GPIO_PORTS 4 +# define STM32_TIMER_MASK 0x380DE /* Timers: 1-4, 6, 7, 15-17. */ # define STM32_SRAM_END ((void*)0x20002000) # define STM32_MEDIUM_DENSITY @@ -112,9 +113,16 @@ extern "C" { # ifdef STM32_MEDIUM_DENSITY # define STM32_NR_INTERRUPTS 43 +# define STM32_TIMER_MASK 0x1E /* TIMER1--TIMER4 */ # define STM32_HAVE_FSMC 0 # elif defined(STM32_HIGH_DENSITY) # define STM32_NR_INTERRUPTS 60 +# define STM32_TIMER_MASK 0x1FE /* TIMER1--TIMER8 */ +# define STM32_HAVE_FSMC 1 +# endif +# elif defined(STM32_XL_DENSITY) +# define STM32_NR_INTERRUPTS 60 +# define STM32_TIMER_MASK 0x7FFE /* TIMER1--TIMER14 */ # define STM32_HAVE_FSMC 1 # endif diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 9e88a70..b53b7b6 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -63,6 +63,7 @@ extern "C" { #if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG) # define STM32_NR_GPIO_PORTS 9 +# define STM32_TIMER_MASK 0x7FFE /* TIMER1-TIMER14. */ # define STM32_SRAM_END ((void*)0x20020000) #else #error "Unrecognized STM32F2 MCU, or no MCU specified." -- cgit v1.2.3 From 73f2cefbdf6d8f255bc5284c64d315f38ee45616 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 03:26:19 -0400 Subject: Bring back HardwareTimer. Untested, but the timers work on F2 (see exampes/test-timers.cpp), so I'm hoping this is mostly OK. Note that there's an issue with TIMER2 and TIMER5 on F2: these timers have 32-bit counters, and the HardwareTimer methods are all based on uint16 (like on F1). I'm sorely tempted to keep this as-is; exposing the extra bits is just extra documentation, and the HardwareTimer interface is already way too complicated. The interface should still _work_; it just hides the fact that you're missing out on the extra bits for some of the timers. Signed-off-by: Marti Bolivar --- wirish/HardwareTimer.cpp | 123 ++++++++++++++++++++++++++++------ wirish/include/wirish/HardwareTimer.h | 2 +- wirish/rules.mk | 2 +- 3 files changed, 104 insertions(+), 23 deletions(-) diff --git a/wirish/HardwareTimer.cpp b/wirish/HardwareTimer.cpp index 52257bf..ca8ea63 100644 --- a/wirish/HardwareTimer.cpp +++ b/wirish/HardwareTimer.cpp @@ -30,33 +30,114 @@ // TODO [0.1.0] Remove deprecated pieces -#ifdef STM32_MEDIUM_DENSITY -#define NR_TIMERS 4 -#elif defined(STM32_HIGH_DENSITY) -#define NR_TIMERS 8 +#define MAX_RELOAD ((1 << 16) - 1) + +/* + * Big ugly table of timers available on the MCU. Needed by the + * HardwareTimer constructor. Sigh; maybe predefined instances weren't + * such a bad idea. Oh well, at least the HardwareTimer interface is + * officially unstable since v0.0.12; we can always get rid of this + * later. + */ + +#define MAX_NR_TIMERS 17 // No STM32 I've ever heard of has higher than TIMER17 + +static timer_dev *devs[MAX_NR_TIMERS] = { +#if STM32_HAVE_TIMER(1) + TIMER1, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(2) + TIMER2, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(3) + TIMER3, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(4) + TIMER4, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(5) + TIMER5, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(6) + TIMER6, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(7) + TIMER7, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(8) + TIMER8, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(9) + TIMER9, #else -#error "Unsupported density" + NULL, #endif +#if STM32_HAVE_TIMER(10) + TIMER10, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(11) + TIMER11, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(12) + TIMER12, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(13) + TIMER13, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(14) + TIMER14, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(15) + TIMER15, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(16) + TIMER16, +#else + NULL, +#endif +#if STM32_HAVE_TIMER(17) + TIMER17, +#else + NULL, +#endif +}; -#define MAX_RELOAD ((1 << 16) - 1) +/* + * HardwareTimer routines + */ HardwareTimer::HardwareTimer(uint8 timerNum) { - if (timerNum > NR_TIMERS) { - ASSERT(0); - } - timer_dev *devs[] = { - TIMER1, - TIMER2, - TIMER3, - TIMER4, -#ifdef STM32_HIGH_DENSITY - TIMER5, - TIMER6, - TIMER7, - TIMER8, -#endif - }; + ASSERT(timerNum <= MAX_NR_TIMERS); this->dev = devs[timerNum - 1]; + ASSERT(this->dev != NULL); } void HardwareTimer::pause(void) { diff --git a/wirish/include/wirish/HardwareTimer.h b/wirish/include/wirish/HardwareTimer.h index bdcca5d..d322033 100644 --- a/wirish/include/wirish/HardwareTimer.h +++ b/wirish/include/wirish/HardwareTimer.h @@ -313,7 +313,7 @@ extern HardwareTimer Timer3; * Pre-instantiated timer. */ extern HardwareTimer Timer4; -#ifdef STM32_HIGH_DENSITY +#if (STM32_MCU_SERIES == STM32_SERIES_F1) && defined(STM32_HIGH_DENSITY) /** * @brief Deprecated. * diff --git a/wirish/rules.mk b/wirish/rules.mk index deb3906..54c9180 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -23,6 +23,7 @@ cSRCS_$(d) := start_c.c cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += HardwareSerial.cpp +cppSRCS_$(d) += HardwareTimer.cpp cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += wirish_analog.cpp cppSRCS_$(d) += wirish_digital.cpp @@ -34,7 +35,6 @@ cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately F2 and put them back in: # HardwareSPI.cpp -# HardwareTimer.cpp # usb_serial.cpp # pwm.cpp # ext_interrupts.cpp -- cgit v1.2.3 From 13d3b358627363682aba12e90cabb003b8ea6bc3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 03:27:23 -0400 Subject: cosmetics. Signed-off-by: Marti Bolivar --- wirish/include/wirish/HardwareTimer.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/wirish/include/wirish/HardwareTimer.h b/wirish/include/wirish/HardwareTimer.h index d322033..4e140ca 100644 --- a/wirish/include/wirish/HardwareTimer.h +++ b/wirish/include/wirish/HardwareTimer.h @@ -38,9 +38,6 @@ /** Timer mode. */ typedef timer_mode TimerMode; -/** @brief Deprecated; use TIMER_OUTPUT_COMPARE instead. */ -#define TIMER_OUTPUTCOMPARE TIMER_OUTPUT_COMPARE - /** * @brief Interface to one of the 16-bit timer peripherals. */ @@ -208,7 +205,7 @@ public: */ void refresh(void); - /* -- Deprecated methods ----------------------------------------------- */ +/* -- The rest of this file is deprecated. --------------------------------- */ /** @brief Deprecated; use setMode(channel, mode) instead. */ void setChannelMode(int channel, timer_mode mode) { @@ -287,7 +284,8 @@ public: void generateUpdate(void) { refresh(); } }; -/* -- The rest of this file is deprecated. --------------------------------- */ +/** @brief Deprecated; use TIMER_OUTPUT_COMPARE instead. */ +#define TIMER_OUTPUTCOMPARE TIMER_OUTPUT_COMPARE /** * @brief Deprecated. -- cgit v1.2.3 From d4d924ccda26083f4495661ee1fd1b6e549626d7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 16:36:20 -0400 Subject: libmaple/adc.h: Fixup for Doxygen. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/adc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/adc.h b/libmaple/include/libmaple/adc.h index 8d2f398..ff9a5e4 100644 --- a/libmaple/include/libmaple/adc.h +++ b/libmaple/include/libmaple/adc.h @@ -259,12 +259,12 @@ extern void adc_set_prescaler(adc_prescaler pre); */ extern void adc_foreach(void (*fn)(const adc_dev*)); +struct gpio_dev; /** * @brief Configure a GPIO pin for ADC conversion. * @param gdev GPIO device to configure. * @param bit Bit on gdev to configure for ADC conversion. */ -struct gpio_dev; extern void adc_gpio_cfg(struct gpio_dev *gdev, uint8 bit); /** -- cgit v1.2.3 From 66876d1883055bccae9ae5e73fb3c5d29cb2b453 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 1 Jun 2012 17:26:03 -0400 Subject: Preprocessor-fu to derive BOARD_HAVE_USARTn from . Signed-off-by: Marti Bolivar --- wirish/boards/VLDiscovery/include/board/board.h | 6 ------ wirish/boards/maple/include/board/board.h | 9 +-------- wirish/boards/maple_RET6/include/board/board.h | 6 ------ wirish/boards/maple_mini/include/board/board.h | 6 ------ wirish/boards/maple_native/include/board/board.h | 6 ------ .../boards/olimex_stm32_h103/include/board/board.h | 6 ------ .../boards/st_stm3220g_eval/include/board/board.h | 6 ------ wirish/include/wirish/boards.h | 21 +++++++++++++++++++++ 8 files changed, 22 insertions(+), 44 deletions(-) diff --git a/wirish/boards/VLDiscovery/include/board/board.h b/wirish/boards/VLDiscovery/include/board/board.h index c54abc1..04d21c7 100644 --- a/wirish/boards/VLDiscovery/include/board/board.h +++ b/wirish/boards/VLDiscovery/include/board/board.h @@ -45,12 +45,6 @@ /* Number of USARTs/UARTs whose pins are broken out to headers */ #define BOARD_NR_USARTS 3 -#define BOARD_HAVE_USART1 1 -#define BOARD_HAVE_USART2 1 -#define BOARD_HAVE_USART3 1 -#define BOARD_HAVE_UART4 0 -#define BOARD_HAVE_UART5 0 -#define BOARD_HAVE_USART6 0 /* Default USART pin numbers (not considering AFIO remap) */ #define BOARD_USART1_TX_PIN 7 diff --git a/wirish/boards/maple/include/board/board.h b/wirish/boards/maple/include/board/board.h index ed89fee..9319989 100644 --- a/wirish/boards/maple/include/board/board.h +++ b/wirish/boards/maple/include/board/board.h @@ -39,15 +39,8 @@ #define BOARD_BUTTON_PIN 38 #define BOARD_LED_PIN 13 -/* Number of USARTs/UARTs whose pins are broken out to headers, and - * macros saying which ones they are. */ +/* Number of USARTs/UARTs whose pins are broken out to headers. */ #define BOARD_NR_USARTS 3 -#define BOARD_HAVE_USART1 1 -#define BOARD_HAVE_USART2 1 -#define BOARD_HAVE_USART3 1 -#define BOARD_HAVE_UART4 0 -#define BOARD_HAVE_UART5 0 -#define BOARD_HAVE_USART6 0 /* Default USART pin numbers (not considering AFIO remap) */ #define BOARD_USART1_TX_PIN 7 diff --git a/wirish/boards/maple_RET6/include/board/board.h b/wirish/boards/maple_RET6/include/board/board.h index 3291498..05b9031 100644 --- a/wirish/boards/maple_RET6/include/board/board.h +++ b/wirish/boards/maple_RET6/include/board/board.h @@ -44,12 +44,6 @@ /* UART4 and UART5 have pins which aren't broken out :( */ #define BOARD_NR_USARTS 3 -#define BOARD_HAVE_USART1 1 -#define BOARD_HAVE_USART2 1 -#define BOARD_HAVE_USART3 1 -#define BOARD_HAVE_UART4 0 -#define BOARD_HAVE_UART5 0 -#define BOARD_HAVE_USART6 0 #define BOARD_USART1_TX_PIN 7 #define BOARD_USART1_RX_PIN 8 #define BOARD_USART2_TX_PIN 1 diff --git a/wirish/boards/maple_mini/include/board/board.h b/wirish/boards/maple_mini/include/board/board.h index 8ba91ce..bfba46d 100644 --- a/wirish/boards/maple_mini/include/board/board.h +++ b/wirish/boards/maple_mini/include/board/board.h @@ -43,12 +43,6 @@ #define BOARD_LED_PIN 33 #define BOARD_NR_USARTS 3 -#define BOARD_HAVE_USART1 1 -#define BOARD_HAVE_USART2 1 -#define BOARD_HAVE_USART3 1 -#define BOARD_HAVE_UART4 0 -#define BOARD_HAVE_UART5 0 -#define BOARD_HAVE_USART6 0 #define BOARD_USART1_TX_PIN 26 #define BOARD_USART1_RX_PIN 25 #define BOARD_USART2_TX_PIN 9 diff --git a/wirish/boards/maple_native/include/board/board.h b/wirish/boards/maple_native/include/board/board.h index a4f8896..397afaf 100644 --- a/wirish/boards/maple_native/include/board/board.h +++ b/wirish/boards/maple_native/include/board/board.h @@ -43,12 +43,6 @@ #define BOARD_BUTTON_PIN 6 #define BOARD_NR_USARTS 5 -#define BOARD_HAVE_USART1 1 -#define BOARD_HAVE_USART2 1 -#define BOARD_HAVE_USART3 1 -#define BOARD_HAVE_UART4 1 -#define BOARD_HAVE_UART5 1 -#define BOARD_HAVE_USART6 0 #define BOARD_USART1_TX_PIN 24 #define BOARD_USART1_RX_PIN 25 #define BOARD_USART2_TX_PIN 50 diff --git a/wirish/boards/olimex_stm32_h103/include/board/board.h b/wirish/boards/olimex_stm32_h103/include/board/board.h index 46367ac..b312e26 100644 --- a/wirish/boards/olimex_stm32_h103/include/board/board.h +++ b/wirish/boards/olimex_stm32_h103/include/board/board.h @@ -42,12 +42,6 @@ /* Number of USARTs/UARTs whose pins are broken out to headers */ #define BOARD_NR_USARTS 3 -#define BOARD_HAVE_USART1 1 -#define BOARD_HAVE_USART2 1 -#define BOARD_HAVE_USART3 1 -#define BOARD_HAVE_UART4 0 -#define BOARD_HAVE_UART5 0 -#define BOARD_HAVE_USART6 0 /* Default USART pin numbers (not considering AFIO remap) */ #define BOARD_USART1_TX_PIN 3 diff --git a/wirish/boards/st_stm3220g_eval/include/board/board.h b/wirish/boards/st_stm3220g_eval/include/board/board.h index f99a585..fe9658a 100644 --- a/wirish/boards/st_stm3220g_eval/include/board/board.h +++ b/wirish/boards/st_stm3220g_eval/include/board/board.h @@ -44,12 +44,6 @@ #define BOARD_LED_PIN 0 #define BOARD_NR_USARTS 0 -#define BOARD_HAVE_USART1 0 -#define BOARD_HAVE_USART2 0 -#define BOARD_HAVE_USART3 0 -#define BOARD_HAVE_UART4 0 -#define BOARD_HAVE_UART5 0 -#define BOARD_HAVE_USART6 0 #define BOARD_NR_SPI 0 #define BOARD_NR_GPIO_PINS 6 #define BOARD_NR_PWM_PINS 0 diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index 3c2740a..2da252d 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -114,4 +114,25 @@ bool boardUsesPin(uint8 pin); #define CLOCK_SPEED_MHZ CYCLES_PER_MICROSECOND #define CLOCK_SPEED_HZ (CLOCK_SPEED_MHZ * 1000000UL) +/** + * @brief Does the board break out a USART/UART's RX and TX pins? + * + * BOARD_HAVE_USART(n) is nonzero iff USARTn is available. Also see + * BOARD_HAVE_USART1, ..., BOARD_HAVE_UART4 (sic), etc. + */ +#define BOARD_HAVE_USART(n) (defined(BOARD_USART##n##_TX_PIN) && \ + defined(BOARD_USART##n##_RX_PIN)) +/** Feature test: nonzero iff the board has USART1. */ +#define BOARD_HAVE_USART1 BOARD_HAVE_USART(1) +/** Feature test: nonzero iff the board has USART2, 0 otherwise. */ +#define BOARD_HAVE_USART2 BOARD_HAVE_USART(2) +/** Feature test: nonzero iff the board has USART3, 0 otherwise. */ +#define BOARD_HAVE_USART3 BOARD_HAVE_USART(3) +/** Feature test: nonzero iff the board has UART4, 0 otherwise. */ +#define BOARD_HAVE_UART4 BOARD_HAVE_USART(4) +/** Feature test: nonzero iff the board has UART5, 0 otherwise. */ +#define BOARD_HAVE_UART5 BOARD_HAVE_USART(5) +/** Feature test: nonzero iff the board has USART6, 0 otherwise. */ +#define BOARD_HAVE_USART6 BOARD_HAVE_USART(6) + #endif -- cgit v1.2.3 From 33b972e7e214e291bd62f83a0621fb87c267a9de Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 19:39:47 -0400 Subject: Oops; don't break the build on F1. That was dumb. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 1 - wirish/HardwareSerial.cpp | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 59205c3..23c0591 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -119,7 +119,6 @@ extern "C" { # define STM32_NR_INTERRUPTS 60 # define STM32_TIMER_MASK 0x1FE /* TIMER1--TIMER8 */ # define STM32_HAVE_FSMC 1 -# endif # elif defined(STM32_XL_DENSITY) # define STM32_NR_INTERRUPTS 60 # define STM32_TIMER_MASK 0x7FFE /* TIMER1--TIMER14 */ diff --git a/wirish/HardwareSerial.cpp b/wirish/HardwareSerial.cpp index 3f418e2..75f5bbb 100644 --- a/wirish/HardwareSerial.cpp +++ b/wirish/HardwareSerial.cpp @@ -77,8 +77,8 @@ HardwareSerial::HardwareSerial(usart_dev *usart_device, /* F1 MCUs have no GPIO_AFR[HL], so turn off PWM if there's a conflict * on this GPIO bit. */ static void disable_timer_if_necessary(timer_dev *dev, uint8 ch) { - if (txi->timer_device != NULL) { - timer_set_mode(txi->timer_device, txi->timer_channel, TIMER_DISABLED); + if (dev != NULL) { + timer_set_mode(dev, ch, TIMER_DISABLED); } } #elif (STM32_MCU_SERIES == STM32_SERIES_F2) || \ -- cgit v1.2.3 From ff6a1e449f6e722ca33c8a0d4131574b6efc02f9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 20:26:10 -0400 Subject: Sort the rcc_clk_id enumerators semi-alphabetically. Only semi-alphabetically because peripherals are kept together (so the UARTs sort as if they were USARTs). Advantages: - It lets us play numeric comparison and lookup-table hacks, as we now have the property that the rcc_clk_ids for a given peripheral are a contiguous range of integers. - It will hopefully let the compiler emit faster/smaller code for switches over a dev->clk_id. - It's better intuitively. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/rcc.h | 54 +++++++++--------- libmaple/stm32f2/include/series/rcc.h | 100 +++++++++++++++++----------------- 2 files changed, 77 insertions(+), 77 deletions(-) diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h index e6afe0e..225ca49 100644 --- a/libmaple/stm32f1/include/series/rcc.h +++ b/libmaple/stm32f1/include/series/rcc.h @@ -391,52 +391,52 @@ typedef struct rcc_reg_map { * @brief STM32F1 rcc_clk_id. */ typedef enum rcc_clk_id { - RCC_GPIOA, - RCC_GPIOB, - RCC_GPIOC, - RCC_GPIOD, - RCC_AFIO, RCC_ADC1, RCC_ADC2, RCC_ADC3, - RCC_USART1, - RCC_USART2, - RCC_USART3, - RCC_TIMER1, - RCC_TIMER2, - RCC_TIMER3, - RCC_TIMER4, - RCC_SPI1, - RCC_SPI2, - RCC_DMA1, - RCC_PWR, + RCC_AFIO, RCC_BKP, - RCC_I2C1, - RCC_I2C2, RCC_CRC, + RCC_DAC, + RCC_DMA1, + RCC_DMA2, RCC_FLITF, - RCC_SRAM, - RCC_USB, + RCC_FSMC, + RCC_GPIOA, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, RCC_GPIOE, RCC_GPIOF, RCC_GPIOG, - RCC_UART4, - RCC_UART5, + RCC_I2C1, + RCC_I2C2, + RCC_PWR, + RCC_SDIO, + RCC_SPI1, + RCC_SPI2, + RCC_SPI3, + RCC_SRAM, + RCC_TIMER1, + RCC_TIMER2, + RCC_TIMER3, + RCC_TIMER4, RCC_TIMER5, RCC_TIMER6, RCC_TIMER7, RCC_TIMER8, - RCC_FSMC, - RCC_DAC, - RCC_DMA2, - RCC_SDIO, - RCC_SPI3, RCC_TIMER9, RCC_TIMER10, RCC_TIMER11, RCC_TIMER12, RCC_TIMER13, RCC_TIMER14, + RCC_USART1, + RCC_USART2, + RCC_USART3, + RCC_UART4, + RCC_UART5, + RCC_USB, } rcc_clk_id; /** diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h index 1d9de85..441a5a8 100644 --- a/libmaple/stm32f2/include/series/rcc.h +++ b/libmaple/stm32f2/include/series/rcc.h @@ -759,67 +759,67 @@ typedef enum rcc_clk { * @brief STM32F2 rcc_clk_id. */ typedef enum rcc_clk_id { - RCC_OTGHSULPI, - RCC_OTGHS, - RCC_ETHMACPTP, - RCC_ETHMACRX, - RCC_ETHMACTX, - RCC_ETHMAC, - RCC_DMA2, - RCC_DMA1, + RCC_ADC1, + RCC_ADC2, + RCC_ADC3, RCC_BKPSRAM, + RCC_CAN1, + RCC_CAN2, RCC_CRC, - RCC_GPIOI, - RCC_GPIOH, - RCC_GPIOG, - RCC_GPIOF, - RCC_GPIOE, - RCC_GPIOD, - RCC_GPIOC, - RCC_GPIOB, - RCC_GPIOA, - RCC_OTGFS, - RCC_RNG, - RCC_HASH, RCC_CRYP, + RCC_DAC, RCC_DCMI, + RCC_DMA1, + RCC_DMA2, + RCC_ETHMAC, + RCC_ETHMACPTP, + RCC_ETHMACRX, + RCC_ETHMACTX, RCC_FSMC, - RCC_DAC, - RCC_PWR, - RCC_CAN2, - RCC_CAN1, - RCC_I2C3, - RCC_I2C2, + RCC_GPIOA, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, + RCC_GPIOE, + RCC_GPIOF, + RCC_GPIOG, + RCC_GPIOH, + RCC_GPIOI, + RCC_HASH, RCC_I2C1, - RCC_UART5, - RCC_UART4, - RCC_USART3, - RCC_USART2, - RCC_SPI3, + RCC_I2C2, + RCC_I2C3, + RCC_OTGFS, + RCC_OTGHS, + RCC_OTGHSULPI, + RCC_PWR, + RCC_RNG, + RCC_SDIO, + RCC_SPI1, RCC_SPI2, - RCC_WWDG, - RCC_TIMER14, - RCC_TIMER13, + RCC_SPI3, + RCC_SYSCFG, + RCC_TIMER1, + RCC_TIMER10, + RCC_TIMER11, RCC_TIMER12, - RCC_TIMER7, - RCC_TIMER6, - RCC_TIMER5, - RCC_TIMER4, - RCC_TIMER3, + RCC_TIMER13, + RCC_TIMER14, RCC_TIMER2, - RCC_TIMER11, - RCC_TIMER10, + RCC_TIMER3, + RCC_TIMER4, + RCC_TIMER5, + RCC_TIMER6, + RCC_TIMER7, + RCC_TIMER8, RCC_TIMER9, - RCC_SYSCFG, - RCC_SPI1, - RCC_SDIO, - RCC_ADC3, - RCC_ADC2, - RCC_ADC1, - RCC_USART6, RCC_USART1, - RCC_TIMER8, - RCC_TIMER1, + RCC_USART2, + RCC_USART3, + RCC_UART4, + RCC_UART5, + RCC_USART6, + RCC_WWDG, } rcc_clk_id; /** -- cgit v1.2.3 From daa792f486ea7ce848c37eee636c73824efec396 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 20:36:36 -0400 Subject: Add timer_has_cc_channel(). This is a convenience function for deciding whether a timer supports a particular capture/compare channel. It's necessary because of those nuisance "general purpose" timers that only have a subset of the channels. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 1 + libmaple/timer.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index 887b7eb..5d9650c 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -599,6 +599,7 @@ void timer_init(timer_dev *dev); void timer_disable(timer_dev *dev); void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode); void timer_foreach(void (*fn)(timer_dev*)); +int timer_has_cc_channel(timer_dev *dev, uint8 channel); /** * @brief Timer interrupt number. diff --git a/libmaple/timer.c b/libmaple/timer.c index d204fef..cd9448a 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -100,6 +100,34 @@ void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) { } } +/** + * @brief Determine whether a timer has a particular capture/compare channel. + * + * Different timers have different numbers of capture/compare channels + * (and some have none at all). Use this function to test whether a + * given timer/channel combination will work. + * + * @param dev Timer device + * @param channel Capture/compare channel, from 1 to 4 + * @return Nonzero if dev has channel, zero otherwise. + */ +int timer_has_cc_channel(timer_dev *dev, uint8 channel) { + /* On all currently supported series: advanced and "full-featured" + * general purpose timers have all four channels. Of the + * restricted general timers, timers 9 and 12 have channels 1 and + * 2; the others have channel 1 only. Basic timers have none. */ + rcc_clk_id id = dev->clk_id; + ASSERT((1 <= channel) && (channel <= 4)); + if (id <= RCC_TIMER5 || id == RCC_TIMER8) { + return 1; /* 1 and 8 are advanced, 2-5 are "full" general */ + } else if (id <= RCC_TIMER7) { + return 0; /* 6 and 7 are basic */ + } + /* The rest are restricted general. */ + return (((id == RCC_TIMER9 || id == RCC_TIMER12) && channel <= 2) || + channel == 1); +} + /** * @brief Attach a timer interrupt. * @param dev Timer device -- cgit v1.2.3 From 1637300f8f751ccc17ff1a2f383c7fca902c0f8f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 21:02:34 -0400 Subject: Bring timer initialization back to init(). Turns out the F1 code was pretty portable after all, so take it from the F1 boards_setup.cpp and stick it back into boards.cpp. The only change needed was to add a call to the newly-minted timer_has_cc_channel() (and this is necessary on F103 XL-density, anyway). Also assert LeafLabs copyright in boards.cpp. We really need to do this throughout the library; it's basically been rewritten since Perry. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 43 ++++++++++++++++++++++++++++++++++++++- wirish/boards_private.h | 1 - wirish/stm32f1/boards_setup.cpp | 45 ----------------------------------------- wirish/stm32f2/boards_setup.cpp | 6 +----- 4 files changed, 43 insertions(+), 52 deletions(-) diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 51ff50e..0faabfd 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -55,6 +56,7 @@ static void setup_flash(void); static void setup_clocks(void); static void setup_nvic(void); static void setup_adcs(void); +static void setup_timers(void); /* * Exported functions @@ -67,7 +69,7 @@ void init(void) { systick_init(SYSTICK_RELOAD_VAL); wirish::priv::board_setup_gpio(); setup_adcs(); - wirish::priv::board_setup_timers(); + setup_timers(); wirish::priv::board_setup_usb(); boardInit(); } @@ -157,3 +159,42 @@ static void setup_adcs(void) { adc_set_prescaler(wirish::priv::w_adc_pre); adc_foreach(adc_default_config); } + +static void timer_default_config(timer_dev *dev) { + timer_adv_reg_map *regs = (dev->regs).adv; + const uint16 full_overflow = 0xFFFF; + const uint16 half_duty = 0x8FFF; + + timer_init(dev); + timer_pause(dev); + + regs->CR1 = TIMER_CR1_ARPE; + regs->PSC = 1; + regs->SR = 0; + regs->DIER = 0; + regs->EGR = TIMER_EGR_UG; + switch (dev->type) { + case TIMER_ADVANCED: + regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; + // fall-through + case TIMER_GENERAL: + timer_set_reload(dev, full_overflow); + for (uint8 channel = 1; channel <= 4; channel++) { + if (timer_has_cc_channel(dev, channel)) { + timer_set_compare(dev, channel, half_duty); + timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, + TIMER_OC_PE); + } + } + // fall-through + case TIMER_BASIC: + break; + } + + timer_generate_update(dev); + timer_resume(dev); +} + +static void setup_timers(void) { + timer_foreach(timer_default_config); +} diff --git a/wirish/boards_private.h b/wirish/boards_private.h index e32f298..cdac844 100644 --- a/wirish/boards_private.h +++ b/wirish/boards_private.h @@ -58,7 +58,6 @@ namespace wirish { void board_reset_pll(void); void board_setup_clock_prescalers(void); void board_setup_gpio(void); - void board_setup_timers(void); void board_setup_usb(void); } diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index a71661d..423e5ec 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -62,8 +62,6 @@ namespace wirish { adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6; adc_smp_rate w_adc_smp = ADC_SMPR_55_5; - static void config_timer(timer_dev*); - void board_reset_pll(void) { // TODO } @@ -81,54 +79,11 @@ namespace wirish { afio_init(); } - void board_setup_timers(void) { - timer_foreach(config_timer); - } - void board_setup_usb(void) { #if 0 # if STM32_HAVE_USB usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); # endif -#endif - } - - /* - * Auxiliary routines - */ - - static void config_timer(timer_dev *dev) { -#if 0 - timer_adv_reg_map *regs = (dev->regs).adv; - const uint16 full_overflow = 0xFFFF; - const uint16 half_duty = 0x8FFF; - - timer_init(dev); - timer_pause(dev); - - regs->CR1 = TIMER_CR1_ARPE; - regs->PSC = 1; - regs->SR = 0; - regs->DIER = 0; - regs->EGR = TIMER_EGR_UG; - - switch (dev->type) { - case TIMER_ADVANCED: - regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF; - // fall-through - case TIMER_GENERAL: - timer_set_reload(dev, full_overflow); - - for (int channel = 1; channel <= 4; channel++) { - timer_set_compare(dev, channel, half_duty); - timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE); - } - // fall-through - case TIMER_BASIC: - break; - } - - timer_resume(dev); #endif } } diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index e1bf1fd..9832bb7 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -81,12 +81,8 @@ namespace wirish { gpio_init_all(); } - void board_setup_timers(void) { - // TODO - } - void board_setup_usb(void) { - // TODO + // Nothing to do. } } -- cgit v1.2.3 From 54e139760a22040535b879ce6537af49ea9b31a5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 21:13:52 -0400 Subject: boards.cpp: Improve the comments. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 0faabfd..7616245 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -27,22 +27,22 @@ /** * @file wirish/boards.cpp - * @brief Generic board routines. + * @brief init() and board routines. * * This file is mostly interesting for the init() function, which - * configures Flash, the core sytem clocks, and a variety of other - * available peripherals on the board so the rest of Wirish doesn't - * have to turn things on before using them. + * configures Flash, the core clocks, and a variety of other available + * peripherals on the board so the rest of Wirish doesn't have to turn + * things on before using them. * - * How init() does this is chip-specific. See the chip-specific pieces - * of Wirish (under e.g. wirish/stm32f1/, wirish/stmf32f2) for - * details. + * Prior to returning, init() calls boardInit(), which allows boards + * to perform any initialization they need to. This file includes a + * weak no-op definition of boardInit(), so boards that don't need any + * special initialization don't have to define their own. * - * Finally, prior to returning, init() calls boardInit(), which allows - * boards to perform any initialization they need to. This file - * includes a weak no-op definition of boardInit(), so boards that - * don't need any special initialization don't have to define their - * own. + * How init() works is chip-specific. See the boards_setup.cpp files + * under e.g. wirish/stm32f1/, wirish/stmf32f2 for the details, but be + * advised: their contents are unstable, and can/will change without + * notice. */ #include @@ -79,7 +79,7 @@ __weak void boardInit(void) { } /* You could farm this out to the files in boards/ if e.g. it takes - * too long to test on Maple Native (all those FSMC pins...). */ + * too long to test on boards with lots of pins. */ bool boardUsesPin(uint8 pin) { for (int i = 0; i < BOARD_NR_USED_PINS; i++) { if (pin == boardUsedPins[i]) { -- cgit v1.2.3 From 7943836c4a967e70ced14a2f4accf21a0469b238 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 21:15:17 -0400 Subject: Bring back/tweak pwmWrite(). Works on F1, doesn't on F2. Will figure that out next. Signed-off-by: Marti Bolivar --- wirish/pwm.cpp | 13 ++++++++----- wirish/rules.mk | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/wirish/pwm.cpp b/wirish/pwm.cpp index a55f245..44884cd 100644 --- a/wirish/pwm.cpp +++ b/wirish/pwm.cpp @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -25,7 +26,8 @@ *****************************************************************************/ /** - * @brief Arduino-style PWM implementation. + * @file wirish/pwm.cpp + * @brief Wiring-style pwmWrite(). */ #include @@ -36,10 +38,11 @@ #include void pwmWrite(uint8 pin, uint16 duty_cycle) { - timer_dev *dev = PIN_MAP[pin].timer_device; - if (pin >= BOARD_NR_GPIO_PINS || dev == NULL || dev->type == TIMER_BASIC) { + if (pin >= BOARD_NR_GPIO_PINS) { return; } - - timer_set_compare(dev, PIN_MAP[pin].timer_channel, duty_cycle); + timer_dev *dev = PIN_MAP[pin].timer_device; + uint8 cc_channel = PIN_MAP[pin].timer_channel; + ASSERT(dev && cc_channel); + timer_set_compare(dev, cc_channel, duty_cycle); } diff --git a/wirish/rules.mk b/wirish/rules.mk index 54c9180..176ba6a 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -25,6 +25,7 @@ cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += HardwareSerial.cpp cppSRCS_$(d) += HardwareTimer.cpp cppSRCS_$(d) += Print.cpp +cppSRCS_$(d) += pwm.cpp cppSRCS_$(d) += wirish_analog.cpp cppSRCS_$(d) += wirish_digital.cpp cppSRCS_$(d) += wirish_math.cpp @@ -36,7 +37,6 @@ cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately F2 and put them back in: # HardwareSPI.cpp # usb_serial.cpp -# pwm.cpp # ext_interrupts.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From 98cc4bfcace01da7b467280f586bb6844916dea7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 21:55:10 -0400 Subject: HardwareTimer.cpp: save some space with an rcc_clk_id hack. Since rcc_clk_ids for a peripheral now form a contiguous range by peripheral number, we can infer the rcc_clk_id for a timer given its number (e.g., can calculate RCC_TIMER2 given timerNum == 2). This lets us use timer_foreach() to avoid keeping a table of available timers in HardwareTimer.cpp. The implementation is hackish, but can be fixed up later if need be. Signed-off-by: Marti Bolivar --- wirish/HardwareTimer.cpp | 123 ++++++++++------------------------------------- 1 file changed, 26 insertions(+), 97 deletions(-) diff --git a/wirish/HardwareTimer.cpp b/wirish/HardwareTimer.cpp index ca8ea63..c35804c 100644 --- a/wirish/HardwareTimer.cpp +++ b/wirish/HardwareTimer.cpp @@ -25,7 +25,10 @@ *****************************************************************************/ #include -#include // for CYCLES_PER_MICROSECOND + +#include // for rcc_clk_id +#include // for CYCLES_PER_MICROSECOND +#include // for noInterrupts(), interrupts() #include // TODO [0.1.0] Remove deprecated pieces @@ -33,110 +36,36 @@ #define MAX_RELOAD ((1 << 16) - 1) /* - * Big ugly table of timers available on the MCU. Needed by the - * HardwareTimer constructor. Sigh; maybe predefined instances weren't - * such a bad idea. Oh well, at least the HardwareTimer interface is - * officially unstable since v0.0.12; we can always get rid of this - * later. + * Evil hack to infer this->dev from timerNum in the HardwareTimer + * constructor. See: + * + * http://www.parashift.com/c++-faq-lite/pointers-to-members.html#faq-33.2 + * http://yosefk.com/c++fqa/function.html#fqa-33.2 */ -#define MAX_NR_TIMERS 17 // No STM32 I've ever heard of has higher than TIMER17 - -static timer_dev *devs[MAX_NR_TIMERS] = { -#if STM32_HAVE_TIMER(1) - TIMER1, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(2) - TIMER2, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(3) - TIMER3, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(4) - TIMER4, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(5) - TIMER5, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(6) - TIMER6, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(7) - TIMER7, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(8) - TIMER8, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(9) - TIMER9, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(10) - TIMER10, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(11) - TIMER11, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(12) - TIMER12, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(13) - TIMER13, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(14) - TIMER14, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(15) - TIMER15, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(16) - TIMER16, -#else - NULL, -#endif -#if STM32_HAVE_TIMER(17) - TIMER17, -#else - NULL, -#endif -}; +extern "C" { + static timer_dev **this_devp; + static rcc_clk_id this_id; + static void set_this_dev(timer_dev *dev) { + if (dev->clk_id == this_id) { + *this_devp = dev; + } + } +} /* * HardwareTimer routines */ HardwareTimer::HardwareTimer(uint8 timerNum) { - ASSERT(timerNum <= MAX_NR_TIMERS); - this->dev = devs[timerNum - 1]; + rcc_clk_id timerID = (rcc_clk_id)(RCC_TIMER1 + (timerNum - 1)); + this->dev = NULL; + noInterrupts(); // Hack to ensure we're the only ones using + // set_this_dev() and friends. TODO: use a lock. + this_id = timerID; + this_devp = &this->dev; + timer_foreach(set_this_dev); + interrupts(); ASSERT(this->dev != NULL); } -- cgit v1.2.3 From c274dfafc202134e791de1468ba2cf0c9137621e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 22:01:29 -0400 Subject: HardwareTimer::setPeriod(): Don't use floating point. I can't believe we've been shipping this for so long. Signed-off-by: Marti Bolivar --- wirish/HardwareTimer.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/wirish/HardwareTimer.cpp b/wirish/HardwareTimer.cpp index c35804c..ef720ce 100644 --- a/wirish/HardwareTimer.cpp +++ b/wirish/HardwareTimer.cpp @@ -26,10 +26,10 @@ #include -#include // for rcc_clk_id -#include // for CYCLES_PER_MICROSECOND +#include #include // for noInterrupts(), interrupts() #include +#include // for CYCLES_PER_MICROSECOND // TODO [0.1.0] Remove deprecated pieces @@ -112,7 +112,7 @@ uint16 HardwareTimer::setPeriod(uint32 microseconds) { uint32 period_cyc = microseconds * CYCLES_PER_MICROSECOND; uint16 prescaler = (uint16)(period_cyc / MAX_RELOAD + 1); - uint16 overflow = (uint16)round(period_cyc / prescaler); + uint16 overflow = (uint16)((period_cyc + (prescaler / 2)) / prescaler); this->setPrescaleFactor(prescaler); this->setOverflow(overflow); return overflow; -- cgit v1.2.3 From 058c2d284a7f0da96a30b17764676a940e102d93 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 22:06:33 -0400 Subject: HardwareTimer.cpp: cosmetics. Signed-off-by: Marti Bolivar --- wirish/HardwareTimer.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/wirish/HardwareTimer.cpp b/wirish/HardwareTimer.cpp index ef720ce..4f68ad7 100644 --- a/wirish/HardwareTimer.cpp +++ b/wirish/HardwareTimer.cpp @@ -33,8 +33,6 @@ // TODO [0.1.0] Remove deprecated pieces -#define MAX_RELOAD ((1 << 16) - 1) - /* * Evil hack to infer this->dev from timerNum in the HardwareTimer * constructor. See: @@ -102,6 +100,7 @@ void HardwareTimer::setCount(uint16 val) { timer_set_count(this->dev, min(val, ovf)); } +#define MAX_RELOAD ((1 << 16) - 1) uint16 HardwareTimer::setPeriod(uint32 microseconds) { // Not the best way to handle this edge case? if (!microseconds) { -- cgit v1.2.3 From cc40b48edacdee58e56e443993aa3c1f22c9374e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sat, 2 Jun 2012 23:57:52 -0400 Subject: STM32F2: fix pinMode() for PWM, PWM_OPEN_DRAIN. Make it so the call to gpio_set_modef() actually happens. Signed-off-by: Marti Bolivar --- wirish/stm32f2/wirish_digital.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/wirish/stm32f2/wirish_digital.cpp b/wirish/stm32f2/wirish_digital.cpp index a67111d..bf9dcf5 100644 --- a/wirish/stm32f2/wirish_digital.cpp +++ b/wirish/stm32f2/wirish_digital.cpp @@ -124,7 +124,6 @@ void pinMode(uint8 pin, WiringPinMode w_mode) { } timer_set_mode(info->timer_device, info->timer_channel, TIMER_PWM); gpio_set_af(info->gpio_device, info->gpio_bit, timer_af); - } else { - gpio_set_modef(info->gpio_device, info->gpio_bit, mode, flags); } + gpio_set_modef(info->gpio_device, info->gpio_bit, mode, flags); } -- cgit v1.2.3 From ff56b76d41a390ed193da180316690f6e2dcbb75 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 00:02:10 -0400 Subject: STM32F2: Add timer_get_af(). Pull some code out of the F2 pinMode() into a utility function. This feels generally useful enough to be exposed to the users (it will, for example, make it easier to implement input capture in a clean way). Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/timer.h | 7 +++++ libmaple/stm32f2/timer.c | 45 +++++++++++++++++++++++++++++++++ wirish/stm32f2/wirish_digital.cpp | 32 +---------------------- 3 files changed, 53 insertions(+), 31 deletions(-) diff --git a/libmaple/stm32f2/include/series/timer.h b/libmaple/stm32f2/include/series/timer.h index 0d959d0..ed473b4 100644 --- a/libmaple/stm32f2/include/series/timer.h +++ b/libmaple/stm32f2/include/series/timer.h @@ -34,6 +34,7 @@ #define _LIBMAPLE_STM32F2_TIMER_H_ #include +#include /* for gpio_af */ /* * Register maps and base pointers @@ -167,4 +168,10 @@ extern struct timer_dev *TIMER12; extern struct timer_dev *TIMER13; extern struct timer_dev *TIMER14; +/* + * Routines + */ + +gpio_af timer_get_af(struct timer_dev *dev); + #endif diff --git a/libmaple/stm32f2/timer.c b/libmaple/stm32f2/timer.c index 3f9a8d2..f644b16 100644 --- a/libmaple/stm32f2/timer.c +++ b/libmaple/stm32f2/timer.c @@ -114,6 +114,51 @@ void timer_foreach(void (*fn)(timer_dev*)) { fn(TIMER14); } +/** + * @brief Get the GPIO alternate function corresponding to a timer. + * + * For example, if dev is TIMER1, this function returns + * GPIO_AF_TIM_1_2. This is useful for e.g. using gpio_set_af() to set + * a pin's alternate function to a timer. + * + * Note that the timer gpio_afs are shared with other timers (and + * sometimes with CAN). For example, timers 1 and 2 both use + * GPIO_AF_TIM_1_2. Because of that, it can pay to e.g not point two + * timers at the same pin. + * + * @param dev Timer device, must not be TIMER6 or TIMER7. + * @return gpio_af corresponding to dev + * @see gpio_set_af + * @see gpio_af + */ +gpio_af timer_get_af(timer_dev *dev) { + rcc_clk_id clk_id = dev->clk_id; + /* Timers 6 and 7 don't have any capture/compare, so they can't do + * PWM (and in fact have no AF values). */ + ASSERT(clk_id != RCC_TIMER6 && clk_id != RCC_TIMER7); + switch(dev->clk_id) { + case RCC_TIMER1: // fall-through + case RCC_TIMER2: + return GPIO_AF_TIM_1_2; + case RCC_TIMER3: // fall-through + case RCC_TIMER4: // ... + case RCC_TIMER5: + return GPIO_AF_TIM_3_4_5; + case RCC_TIMER8: // fall-through + case RCC_TIMER9: // ... + case RCC_TIMER10: // ... + case RCC_TIMER11: + return GPIO_AF_TIM_8_9_10_11; + case RCC_TIMER12: // fall-through + case RCC_TIMER13: // ... + case RCC_TIMER14: + return GPIO_AF_CAN_1_2_TIM_12_13_14; + default: + ASSERT(0); // Can't happen + return (gpio_af)-1; + } +} + /* * IRQ handlers * diff --git a/wirish/stm32f2/wirish_digital.cpp b/wirish/stm32f2/wirish_digital.cpp index bf9dcf5..4d46f1c 100644 --- a/wirish/stm32f2/wirish_digital.cpp +++ b/wirish/stm32f2/wirish_digital.cpp @@ -91,37 +91,7 @@ void pinMode(uint8 pin, WiringPinMode w_mode) { if (info->timer_device == NULL) { return; } - gpio_af timer_af; - /* TODO make this code a convenience - * routine for series that support GPIO alternate - * functions. */ - switch(info->timer_device->clk_id) { - case RCC_TIMER1: // fall-through - case RCC_TIMER2: - timer_af = GPIO_AF_TIM_1_2; - break; - case RCC_TIMER3: // fall-through - case RCC_TIMER4: // ... - case RCC_TIMER5: - timer_af = GPIO_AF_TIM_3_4_5; - break; - /* Timers 6 and 7 don't have any capture/compare, so they - * can't do PWM (and in fact have no AF values). */ - case RCC_TIMER8: // fall-through - case RCC_TIMER9: // ... - case RCC_TIMER10: // ... - case RCC_TIMER11: - timer_af = GPIO_AF_TIM_8_9_10_11; - break; - case RCC_TIMER12: // fall-through - case RCC_TIMER13: // ... - case RCC_TIMER14: - timer_af = GPIO_AF_CAN_1_2_TIM_12_13_14; - break; - default: - ASSERT(0); // Can't happen - return; - } + gpio_af timer_af = timer_get_af(info->timer_device); timer_set_mode(info->timer_device, info->timer_channel, TIMER_PWM); gpio_set_af(info->gpio_device, info->gpio_bit, timer_af); } -- cgit v1.2.3 From f5c37f28fd9be3bd8e2c7159a09891d5e571bc43 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 02:11:07 -0400 Subject: Globally switch style for GPIO config routines. Stupidly, spi_gpio_cfg() didn't take a spi_dev* argument on F1, because it doesn't matter there. On F2, where we need to set an alternate function when configuring GPIOs for SPI, we need to know the dev. We can't add break backwards compatibility, so we need a new function. However, we've since added a bunch of foo_gpio_cfg() routines, and we don't want confusing asymmetry in the names. So a global style change is needed. (Fortunately, the new functions weren't part of a release, so it's no problem to change their names). Change all foo_gpio_cfg() routines to foo_config_gpios() (or foo_config_gpio(), if there's only one GPIO to configure). For backwards compatibility, make spi_gpio_cfg() on F1 an __always_inline call to spi_config_gpios(). Signed-off-by: Marti Bolivar --- examples/test-timers.cpp | 2 +- libmaple/include/libmaple/adc.h | 6 +++++- libmaple/include/libmaple/spi.h | 15 ++++++++------- libmaple/include/libmaple/usart.h | 19 ++++++++++++++----- libmaple/stm32f1/adc.c | 2 +- libmaple/stm32f1/include/series/spi.h | 32 ++++++++++++++++++++++++++++++++ libmaple/stm32f1/spi.c | 15 ++++++++------- libmaple/stm32f1/usart.c | 8 ++++---- libmaple/stm32f2/adc.c | 2 +- libmaple/stm32f2/usart.c | 8 ++++---- wirish/HardwareSPI.cpp | 10 +++------- wirish/HardwareSerial.cpp | 8 ++++---- 12 files changed, 85 insertions(+), 42 deletions(-) diff --git a/examples/test-timers.cpp b/examples/test-timers.cpp index 1f376b7..e646916 100644 --- a/examples/test-timers.cpp +++ b/examples/test-timers.cpp @@ -389,7 +389,7 @@ static void _delay(uint32 msec) { } static void init_usart(usart_dev *dev, gpio_dev *gdev, uint8 tx, uint8 rx) { - usart_async_gpio_cfg(dev, gdev, rx, gdev, tx, 0); + usart_config_gpios_async(dev, gdev, rx, gdev, tx, 0); usart_init(dev); usart_set_baud_rate(dev, USART_USE_PCLK, COMM_USART_BAUD); usart_enable(dev); diff --git a/libmaple/include/libmaple/adc.h b/libmaple/include/libmaple/adc.h index ff9a5e4..a500af7 100644 --- a/libmaple/include/libmaple/adc.h +++ b/libmaple/include/libmaple/adc.h @@ -262,10 +262,14 @@ extern void adc_foreach(void (*fn)(const adc_dev*)); struct gpio_dev; /** * @brief Configure a GPIO pin for ADC conversion. + * @param dev ADC device to use for conversion (currently ignored on + * all targets). * @param gdev GPIO device to configure. * @param bit Bit on gdev to configure for ADC conversion. */ -extern void adc_gpio_cfg(struct gpio_dev *gdev, uint8 bit); +extern void adc_config_gpio(const struct adc_dev *dev, + struct gpio_dev *gdev, + uint8 bit); /** * @brief Enable an ADC and configure it for single conversion mode. diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h index 3805b2e..90e2036 100644 --- a/libmaple/include/libmaple/spi.h +++ b/libmaple/include/libmaple/spi.h @@ -224,13 +224,14 @@ struct gpio_dev; * @param miso_bit MISO pin's GPIO bit on comm_dev * @param mosi_bit MOSI pin's GPIO bit on comm_dev */ -void spi_gpio_cfg(uint8 as_master, - struct gpio_dev *nss_dev, - uint8 nss_bit, - struct gpio_dev *comm_dev, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit); +extern void spi_config_gpios(spi_dev *dev, + uint8 as_master, + struct gpio_dev *nss_dev, + uint8 nss_bit, + struct gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit); /** * @brief SPI mode configuration. diff --git a/libmaple/include/libmaple/usart.h b/libmaple/include/libmaple/usart.h index 293d59e..26a64d3 100644 --- a/libmaple/include/libmaple/usart.h +++ b/libmaple/include/libmaple/usart.h @@ -395,12 +395,21 @@ typedef struct usart_dev { void usart_init(usart_dev *dev); -/* FIXME document this function */ struct gpio_dev; /* forward declaration */ -void usart_async_gpio_cfg(usart_dev *udev, - struct gpio_dev *rx_dev, uint8 rx, - struct gpio_dev *tx_dev, uint8 tx, - unsigned flags); +/* FIXME [PRE 0.0.13] decide if flags are necessary */ +/** + * @brief Configure GPIOs for use as USART TX/RX. + * @param udev USART device to use + * @param rx_dev RX pin gpio_dev + * @param rx RX pin bit on rx_dev + * @param tx_dev TX pin gpio_dev + * @param tx TX pin bit on tx_dev + * @param flags Currently ignored + */ +extern void usart_config_gpios_async(usart_dev *udev, + struct gpio_dev *rx_dev, uint8 rx, + struct gpio_dev *tx_dev, uint8 tx, + unsigned flags); #define USART_USE_PCLK 0 void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud); diff --git a/libmaple/stm32f1/adc.c b/libmaple/stm32f1/adc.c index facc6bd..ecfbc1c 100644 --- a/libmaple/stm32f1/adc.c +++ b/libmaple/stm32f1/adc.c @@ -99,7 +99,7 @@ void adc_foreach(void (*fn)(const adc_dev*)) { #endif } -void adc_gpio_cfg(gpio_dev *gdev, uint8 bit) { +void adc_config_gpio(const adc_dev *ignored, gpio_dev *gdev, uint8 bit) { gpio_set_mode(gdev, bit, GPIO_INPUT_ANALOG); } diff --git a/libmaple/stm32f1/include/series/spi.h b/libmaple/stm32f1/include/series/spi.h index 167df0c..8cc4c4d 100644 --- a/libmaple/stm32f1/include/series/spi.h +++ b/libmaple/stm32f1/include/series/spi.h @@ -34,6 +34,8 @@ #ifndef _LIBMAPLE_STM32F1_SPI_H_ #define _LIBMAPLE_STM32F1_SPI_H_ +#include + #ifdef __cplusplus extern "C" { #endif @@ -63,6 +65,36 @@ extern struct spi_dev *SPI2; extern struct spi_dev *SPI3; #endif +/* + * Routines + */ + +/* spi_gpio_cfg(): Backwards compatibility shim to spi_config_gpios() */ +struct gpio_dev; +extern void spi_config_gpios(struct spi_dev*, uint8, + struct gpio_dev*, uint8, + struct gpio_dev*, uint8, uint8, uint8); +/** + * @brief Deprecated. Use spi_config_gpios() instead. + * @see spi_config_gpios() + */ +static __always_inline void spi_gpio_cfg(uint8 as_master, + struct gpio_dev *nss_dev, + uint8 nss_bit, + struct gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit) { + /* We switched style globally to foo_config_gpios() and always + * taking a foo_dev* argument (that last bit is the important + * part) after this function was written. + * + * However, spi_config_gpios() just ignores the spi_dev* on F1, so + * we can still keep this around for older code. */ + spi_config_gpios(NULL, as_master, nss_dev, nss_bit, + comm_dev, sck_bit, miso_bit, mosi_bit); +} + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/spi.c b/libmaple/stm32f1/spi.c index 8b6e495..72f2ef4 100644 --- a/libmaple/stm32f1/spi.c +++ b/libmaple/stm32f1/spi.c @@ -69,13 +69,14 @@ spi_dev *SPI3 = &spi3; * Routines */ -void spi_gpio_cfg(uint8 as_master, - gpio_dev *nss_dev, - uint8 nss_bit, - gpio_dev *comm_dev, - uint8 sck_bit, - uint8 miso_bit, - uint8 mosi_bit) { +void spi_config_gpios(spi_dev *ignored, + uint8 as_master, + gpio_dev *nss_dev, + uint8 nss_bit, + gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit) { if (as_master) { gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP); gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP); diff --git a/libmaple/stm32f1/usart.c b/libmaple/stm32f1/usart.c index eed420e..b3b849f 100644 --- a/libmaple/stm32f1/usart.c +++ b/libmaple/stm32f1/usart.c @@ -101,10 +101,10 @@ usart_dev *UART5 = &uart5; * Routines */ -void usart_async_gpio_cfg(usart_dev *udev, - gpio_dev *rx_dev, uint8 rx, - gpio_dev *tx_dev, uint8 tx, - unsigned flags) { +void usart_config_gpios_async(usart_dev *udev, + gpio_dev *rx_dev, uint8 rx, + gpio_dev *tx_dev, uint8 tx, + unsigned flags) { gpio_set_mode(rx_dev, rx, GPIO_INPUT_FLOATING); gpio_set_mode(tx_dev, tx, GPIO_AF_OUTPUT_PP); } diff --git a/libmaple/stm32f2/adc.c b/libmaple/stm32f2/adc.c index 0380736..a400d7b 100644 --- a/libmaple/stm32f2/adc.c +++ b/libmaple/stm32f2/adc.c @@ -74,7 +74,7 @@ void adc_foreach(void (*fn)(const adc_dev*)) { fn(ADC3); } -void adc_gpio_cfg(gpio_dev *gdev, uint8 bit) { +void adc_config_gpio(const adc_dev *ignored, gpio_dev *gdev, uint8 bit) { gpio_set_modef(gdev, bit, GPIO_MODE_ANALOG, GPIO_MODEF_PUPD_NONE); } diff --git a/libmaple/stm32f2/usart.c b/libmaple/stm32f2/usart.c index 2dd3afc..9a1acf3 100644 --- a/libmaple/stm32f2/usart.c +++ b/libmaple/stm32f2/usart.c @@ -107,10 +107,10 @@ usart_dev *USART6 = &usart6; * Routines */ -void usart_async_gpio_cfg(usart_dev *udev, - gpio_dev *rx_dev, uint8 rx, - gpio_dev *tx_dev, uint8 tx, - unsigned flags) { +void usart_config_gpios_async(usart_dev *udev, + gpio_dev *rx_dev, uint8 rx, + gpio_dev *tx_dev, uint8 tx, + unsigned flags) { gpio_af af; /* TODO: break this out into a user-facing function. */ switch (udev->clk_id) { diff --git a/wirish/HardwareSPI.cpp b/wirish/HardwareSPI.cpp index e1f186e..120cd67 100644 --- a/wirish/HardwareSPI.cpp +++ b/wirish/HardwareSPI.cpp @@ -283,13 +283,9 @@ static void configure_gpios(spi_dev *dev, bool as_master) { disable_pwm(misoi); disable_pwm(mosii); - spi_gpio_cfg(as_master, - nssi->gpio_device, - nssi->gpio_bit, - scki->gpio_device, - scki->gpio_bit, - misoi->gpio_bit, - mosii->gpio_bit); + spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit, + scki->gpio_device, scki->gpio_bit, misoi->gpio_bit, + mosii->gpio_bit); } static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = { diff --git a/wirish/HardwareSerial.cpp b/wirish/HardwareSerial.cpp index 75f5bbb..7dccccf 100644 --- a/wirish/HardwareSerial.cpp +++ b/wirish/HardwareSerial.cpp @@ -100,10 +100,10 @@ void HardwareSerial::begin(uint32 baud) { disable_timer_if_necessary(txi->timer_device, txi->timer_channel); - usart_async_gpio_cfg(this->usart_device, - rxi->gpio_device, rxi->gpio_bit, - txi->gpio_device, txi->gpio_bit, - 0); + usart_config_gpios_async(this->usart_device, + rxi->gpio_device, rxi->gpio_bit, + txi->gpio_device, txi->gpio_bit, + 0); usart_init(this->usart_device); usart_set_baud_rate(this->usart_device, USART_USE_PCLK, baud); usart_enable(this->usart_device); -- cgit v1.2.3 From 4723f6525215ee5bce550ceb615326f05f8fbc3f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 02:15:57 -0400 Subject: Typo fix. Signed-off-by: Marti Bolivar --- wirish/rules.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/rules.mk b/wirish/rules.mk index 176ba6a..147857a 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -34,7 +34,7 @@ cppSRCS_$(d) += wirish_time.cpp cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp -# TODO: revise these appropriately F2 and put them back in: +# TODO: revise these appropriately for F2 and put them back in: # HardwareSPI.cpp # usb_serial.cpp # ext_interrupts.cpp -- cgit v1.2.3 From 7277d15c68641b4f840240aa4f0557b5f69d727d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 02:23:27 -0400 Subject: F2: Add usart_get_af(). Signed-off-by: Marti Bolivar --- libmaple/stm32f2/include/series/usart.h | 8 +++++++ libmaple/stm32f2/usart.c | 39 +++++++++++++++++++-------------- 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/libmaple/stm32f2/include/series/usart.h b/libmaple/stm32f2/include/series/usart.h index 805a2b2..8936efa 100644 --- a/libmaple/stm32f2/include/series/usart.h +++ b/libmaple/stm32f2/include/series/usart.h @@ -37,6 +37,8 @@ extern "C"{ #endif +#include /* for gpio_af */ + /* * Register map base pointers. */ @@ -96,6 +98,12 @@ extern struct usart_dev *UART4; extern struct usart_dev *UART5; extern struct usart_dev *USART6; +/* + * Routines + */ + +gpio_af usart_get_af(struct usart_dev *dev); + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f2/usart.c b/libmaple/stm32f2/usart.c index 9a1acf3..1472d13 100644 --- a/libmaple/stm32f2/usart.c +++ b/libmaple/stm32f2/usart.c @@ -111,23 +111,7 @@ void usart_config_gpios_async(usart_dev *udev, gpio_dev *rx_dev, uint8 rx, gpio_dev *tx_dev, uint8 tx, unsigned flags) { - gpio_af af; - /* TODO: break this out into a user-facing function. */ - switch (udev->clk_id) { - case RCC_USART1: - case RCC_USART2: - case RCC_USART3: - af = GPIO_AF_USART_1_2_3; - break; - case RCC_UART4: - case RCC_UART5: - case RCC_USART6: - af = GPIO_AF_USART_4_5_6; - break; - default: - ASSERT(0); - return; - } + gpio_af af = usart_get_af(udev); gpio_set_modef(rx_dev, rx, GPIO_MODE_AF, 0); gpio_set_modef(tx_dev, tx, GPIO_MODE_AF, 0); gpio_set_af(rx_dev, rx, af); @@ -170,6 +154,27 @@ void usart_foreach(void (*fn)(usart_dev*)) { fn(USART6); } +/** + * @brief Get GPIO alternate function mode for a USART. + * @param dev USART whose gpio_af to get. + * @return gpio_af corresponding to dev. + */ +gpio_af usart_get_af(usart_dev *dev) { + switch (dev->clk_id) { + case RCC_USART1: + case RCC_USART2: + case RCC_USART3: + return GPIO_AF_USART_1_2_3; + case RCC_UART4: + case RCC_UART5: + case RCC_USART6: + return GPIO_AF_USART_4_5_6; + default: + ASSERT(0); /* Can't happen */ + return (gpio_af)-1; + } +} + /* * Interrupt handlers. */ -- cgit v1.2.3 From ccd1ca1403490db05cf02696e1b5430147fc2805 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 02:48:32 -0400 Subject: libmaple_types.h: Add __unused. We'll need this soon. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/libmaple_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/include/libmaple/libmaple_types.h b/libmaple/include/libmaple/libmaple_types.h index 0c22792..9e1fbb3 100644 --- a/libmaple/include/libmaple/libmaple_types.h +++ b/libmaple/include/libmaple/libmaple_types.h @@ -55,6 +55,7 @@ typedef void (*voidFuncPtr)(void); #define __deprecated __attribute__((__deprecated__)) #define __weak __attribute__((weak)) #define __always_inline inline __attribute__((always_inline)) +#define __unused __attribute__((unused)) #ifndef NULL #define NULL 0 -- cgit v1.2.3 From 4a53794f1afbb9951bd87f413c64614d1006294c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 02:48:57 -0400 Subject: : Add feature test macros for SPI. Signed-off-by: Marti Bolivar --- wirish/include/wirish/boards.h | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index 2da252d..69e8882 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -117,8 +117,9 @@ bool boardUsesPin(uint8 pin); /** * @brief Does the board break out a USART/UART's RX and TX pins? * - * BOARD_HAVE_USART(n) is nonzero iff USARTn is available. Also see - * BOARD_HAVE_USART1, ..., BOARD_HAVE_UART4 (sic), etc. + * BOARD_HAVE_USART(n) is nonzero iff USARTn is available (n must be + * an integer literal, 1 through 6). Also see BOARD_HAVE_USART1, ..., + * BOARD_HAVE_UART4 (sic), etc. */ #define BOARD_HAVE_USART(n) (defined(BOARD_USART##n##_TX_PIN) && \ defined(BOARD_USART##n##_RX_PIN)) @@ -135,4 +136,21 @@ bool boardUsesPin(uint8 pin); /** Feature test: nonzero iff the board has USART6, 0 otherwise. */ #define BOARD_HAVE_USART6 BOARD_HAVE_USART(6) +/** + * @brief Does the board break out a SPI peripheral's pins? + * + * BOARD_HAVE_SPI(n) is nonzero iff SPIn is available (n must be an + * integer literal: 1, 2, or 3). Also see BOARD_HAVE_SPI1, + * BOARD_HAVE_SPI2, BOARD_HAVE_SPI3. */ +#define BOARD_HAVE_SPI(n) (defined(BOARD_SPI##n##_NSS_PIN) && \ + defined(BOARD_SPI##n##_SCK_PIN) && \ + defined(BOARD_SPI##n##_MISO_PIN) && \ + defined(BOARD_SPI##n##_MOSI_PIN)) +/** Feature test: nonzero iff the board has SPI1. */ +#define BOARD_HAVE_SPI1 BOARD_HAVE_SPI(1) +/** Feature test: nonzero iff the board has SPI2. */ +#define BOARD_HAVE_SPI2 BOARD_HAVE_SPI(2) +/** Feature test: nonzero iff the board has SPI3. */ +#define BOARD_HAVE_SPI3 BOARD_HAVE_SPI(3) + #endif -- cgit v1.2.3 From b522a442b805507e7a8fc93ba8011068b8b57d96 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 04:21:20 -0400 Subject: Add BOARD_HAVE_SERIALUSB. Feature-test for SerialUSB support. Signed-off-by: Marti Bolivar --- wirish/include/wirish/boards.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index 69e8882..1375512 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -153,4 +153,10 @@ bool boardUsesPin(uint8 pin); /** Feature test: nonzero iff the board has SPI3. */ #define BOARD_HAVE_SPI3 BOARD_HAVE_SPI(3) +/** + * @brief Feature test: nonzero iff the board has SerialUSB. + */ +#define BOARD_HAVE_SERIALUSB (defined(BOARD_USB_DISC_DEV) && \ + defined(BOARD_USB_DISC_BIT)) + #endif -- cgit v1.2.3 From 378c3a70f81ddfbbddf3656977f81b7dfd8f96cd Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 06:00:41 -0400 Subject: Slightly improve and generify the USB infrastructure. The good news is that and did turn out generic enough in what they specify to go on unchanged. However, we can't just go on assuming that there's USB just because we're on an F1. Now that there's value line in the tree, we need to be more careful (value line F1s don't have USB peripherals). To that end, make all the F1 board-includes/*.mk files specify what line their MCU is with an MCU_F1_LINE variable. Use that to hack libmaple/usb/rules.mk so we only try to build the USB module under appropriate circumstances. While we're at it, add a vector_symbols.inc for value line MCUs under support/ld/. We need this to get the target-config.mk modifications implied by the addition of MCU_F1_LINE. We'll fix up some other performance-line-isms under libmaple/stm32f1 in a separate commit. Also in libmaple/usb/: - Move everything into a new stm32f1 directory. Due to aforementioned rules.mk hacks, there is no immediate need for an stm32f2 directory (USB support doesn't exist there). - Update the README for style and content. Signed-off-by: Marti Bolivar --- Makefile | 2 +- libmaple/include/libmaple/usb.h | 2 +- libmaple/usb/README | 69 +- libmaple/usb/rules.mk | 27 +- libmaple/usb/stm32f1/usb.c | 381 +++++++++++ libmaple/usb/stm32f1/usb_cdcacm.c | 762 +++++++++++++++++++++ libmaple/usb/stm32f1/usb_descriptors.h | 148 ++++ libmaple/usb/stm32f1/usb_lib_globals.h | 55 ++ libmaple/usb/stm32f1/usb_reg_map.c | 79 +++ libmaple/usb/stm32f1/usb_reg_map.h | 433 ++++++++++++ libmaple/usb/usb.c | 381 ----------- libmaple/usb/usb_cdcacm.c | 762 --------------------- libmaple/usb/usb_descriptors.h | 148 ---- libmaple/usb/usb_lib_globals.h | 55 -- libmaple/usb/usb_reg_map.c | 79 --- libmaple/usb/usb_reg_map.h | 433 ------------ .../stm32/series/stm32f1/value/vector_symbols.inc | 78 +++ support/make/board-includes/VLDiscovery.mk | 1 + support/make/board-includes/maple.mk | 1 + support/make/board-includes/maple_RET6.mk | 1 + support/make/board-includes/maple_mini.mk | 1 + support/make/board-includes/maple_native.mk | 1 + support/make/board-includes/olimex_stm32_h103.mk | 1 + support/make/target-config.mk | 6 +- wirish/include/wirish/usb_serial.h | 5 +- wirish/rules.mk | 4 +- wirish/stm32f1/boards_setup.cpp | 10 +- wirish/usb_serial.cpp | 9 + 28 files changed, 2015 insertions(+), 1919 deletions(-) create mode 100644 libmaple/usb/stm32f1/usb.c create mode 100644 libmaple/usb/stm32f1/usb_cdcacm.c create mode 100644 libmaple/usb/stm32f1/usb_descriptors.h create mode 100644 libmaple/usb/stm32f1/usb_lib_globals.h create mode 100644 libmaple/usb/stm32f1/usb_reg_map.c create mode 100644 libmaple/usb/stm32f1/usb_reg_map.h delete mode 100644 libmaple/usb/usb.c delete mode 100644 libmaple/usb/usb_cdcacm.c delete mode 100644 libmaple/usb/usb_descriptors.h delete mode 100644 libmaple/usb/usb_lib_globals.h delete mode 100644 libmaple/usb/usb_reg_map.c delete mode 100644 libmaple/usb/usb_reg_map.h create mode 100644 support/ld/stm32/series/stm32f1/value/vector_symbols.inc diff --git a/Makefile b/Makefile index 0784644..e3a1e4f 100644 --- a/Makefile +++ b/Makefile @@ -75,7 +75,7 @@ ifeq ($(LIBMAPLE_MODULES),) else LIBMAPLE_MODULES += $(SRCROOT)/libmaple endif -# LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # USB FS device +LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # The USB module is kept separate LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_SERIES) # STM32 series submodule in libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish # Official libraries: diff --git a/libmaple/include/libmaple/usb.h b/libmaple/include/libmaple/usb.h index 82bace9..8555aca 100644 --- a/libmaple/include/libmaple/usb.h +++ b/libmaple/include/libmaple/usb.h @@ -1,7 +1,7 @@ /****************************************************************************** * The MIT License * - * Copyright (c) 2010 LeafLabs LLC. + * Copyright (c) 2010, 2011 LeafLabs LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation diff --git a/libmaple/usb/README b/libmaple/usb/README index 2c55364..d0fca8d 100644 --- a/libmaple/usb/README +++ b/libmaple/usb/README @@ -1,35 +1,24 @@ -The USB submodule of libmaple is responsible for: - - Initializing the USB peripheral, scaling the peripheral clocks - appropriately, enabling the interrupt channels to USB, defining - the USB IRQ, resetting the USB DISC pin (used to tell the host - were alive). Additionally, the USB submodule defines the virtual - COM port interface that is exposed to user sketches via SerialUSB. - -To use it: - - SerialUSB.print/ln, available(), read(), write() implement the same - interface as Serial1/2/3. +The USB submodule of libmaple is a separate piece of the codebase for +reasons that are largely historical. Current Status: - Currently, the USB submodule relies on the low level core library - provided by ST to implement the USB transfer protocol for control - endpoint transfers. The high level virtual com port application - is unfortunately hard to untangle from this low level dependence, - and when a new USB core library is written (to nix ST dependence) - changes will likely have to be made to virtual com application - code. Ideally, the new core library should mimic the form of MyUSB - (LUFA), since this library (USB for AVR) is growing in popularity - and in example applications. + There's only support for the USB device peripheral found on + STM32F103s. - The virtual com port serves two important purposes. + We rely on the low level core library provided by ST to implement + the USB transfer protocol for control endpoint transfers. - 1) It allows serial data transfers between user sketches an a - host computer. + The virtual com port (which is exposed via + ) serves two important purposes. - 2) It allows the host machine to issue a system reset by - asserting the DTR signal. + 1) It allows serial data transfers between user sketches an a + host computer. + + 2) It allows the host PC to issue a system reset into the DFU + bootloader with the DTR + RTS + "1EAF" sequence (see + leaflabs.com/docs/bootloader.html for more information on + this). After reset, Maple will run the DFU bootloader for a few seconds, during which the user can begin a DFU upload operation (uploads @@ -38,11 +27,11 @@ Current Status: the chip in order to enable the bootloader. If you would like to develop your own USB application for whatever - reason (uses faster isochronous enpoints for streaming audio, or - implements the USB HID or Mass Storage specs for examples) then + reason (e.g. to use faster isochronous enpoints for streaming + audio, or implement the USB HID or Mass Storage specs), then ensure that you leave some hook for resetting Maple remotely in - order to spin up the DFU bootloader. Please make sure to give - yourself a unique vendor/product ID pair in your application, as + order to spin up the DFU bootloader. Please make sure to get + yourself a unique vendor/product ID pair for your application, as some operating systems will assign a host-side driver based on these tags. @@ -52,21 +41,23 @@ Current Status: be a burden from the host driver side, as Windows and *nix handle compound USB devices quite differently. - Be mindful that enabling the USB peripheral isnt "free." The + Be mindful that enabling the USB peripheral isn't "free." The device must respond to periodic bus activity (every few milliseconds) by servicing an ISR. Therefore, the USB application - should be disabled inside of timing critical applications. In - order to disconnect the device from the host, the USB_DISC pin can - be asserted (on Maple this is GPIO C12). Alternatively, the NVIC + should be disabled inside of timing critical applications. + + In order to disconnect the device from the host, a USB_DISC pin is + asserted (e.g. on Maple, this is PC12). Alternatively, the NVIC can be directly configured to disable the USB LP/HP IRQ's. The files inside of usb_lib were provided by ST and are subject to their own license, all other files were written by the LeafLabs team and fall under the MIT license. -Todo: +TODO: - - write custom low level USB stack to strip out any remaining - dependence on ST code - - add a high level USB application library that would allow users - to make their own HID/Mass Storage/Audio/Video devices. + - Generic USB driver core with series-provided backends, like + libopencm3 has. + - Strip out ST code. + - Integration with a high level USB library (like LUFA/MyUSB) to + allow users to write custom USB applications. diff --git a/libmaple/usb/rules.mk b/libmaple/usb/rules.mk index 816fad6..e8ccc15 100644 --- a/libmaple/usb/rules.mk +++ b/libmaple/usb/rules.mk @@ -3,20 +3,29 @@ sp := $(sp).x dirstack_$(sp) := $(d) d := $(dir) BUILDDIRS += $(BUILD_PATH)/$(d) -BUILDDIRS += $(BUILD_PATH)/$(d)/usb_lib # Local flags -CFLAGS_$(d) = -I$(d) -I$(d)/usb_lib $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall +CFLAGS_$(d) = -I$(d) -I$(d)/$(MCU_SERIES) -I$(d)/usb_lib $(LIBMAPLE_INCLUDES) $(LIBMAPLE_PRIVATE_INCLUDES) -Wall + +# Add usblib and series subdirectory to BUILDDIRS. +BUILDDIRS += $(BUILD_PATH)/$(d)/$(MCU_SERIES) +BUILDDIRS += $(BUILD_PATH)/$(d)/usb_lib # Local rules and targets sSRCS_$(d) := -cSRCS_$(d) := usb.c \ - usb_reg_map.c \ - usb_cdcacm.c \ - usb_lib/usb_core.c \ - usb_lib/usb_init.c \ - usb_lib/usb_mem.c \ - usb_lib/usb_regs.c +cSRCS_$(d) := +# We currently only have F1 performance line support. Sigh. +ifeq ($(MCU_SERIES), stm32f1) +ifeq ($(MCU_F1_LINE), performance) +cSRCS_$(d) += $(MCU_SERIES)/usb.c +cSRCS_$(d) += $(MCU_SERIES)/usb_reg_map.c +cSRCS_$(d) += $(MCU_SERIES)/usb_cdcacm.c +cSRCS_$(d) += usb_lib/usb_core.c +cSRCS_$(d) += usb_lib/usb_init.c +cSRCS_$(d) += usb_lib/usb_mem.c +cSRCS_$(d) += usb_lib/usb_regs.c +endif +endif sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) diff --git a/libmaple/usb/stm32f1/usb.c b/libmaple/usb/stm32f1/usb.c new file mode 100644 index 0000000..0130bab --- /dev/null +++ b/libmaple/usb/stm32f1/usb.c @@ -0,0 +1,381 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/usb/usb.c + * @brief USB support. + * + * This is a mess. What we need almost amounts to a ground-up rewrite. + */ + +#include + +#include +#include + +/* Private headers */ +#include "usb_reg_map.h" +#include "usb_lib_globals.h" + +/* usb_lib headers */ +#include "usb_type.h" +#include "usb_core.h" + +static void dispatch_ctr_lp(void); + +/* + * usb_lib/ globals + */ + +uint16 SaveTState; /* caches TX status for later use */ +uint16 SaveRState; /* caches RX status for later use */ + +/* + * Other state + */ + +typedef enum { + RESUME_EXTERNAL, + RESUME_INTERNAL, + RESUME_LATER, + RESUME_WAIT, + RESUME_START, + RESUME_ON, + RESUME_OFF, + RESUME_ESOF +} RESUME_STATE; + +struct { + volatile RESUME_STATE eState; + volatile uint8 bESOFcnt; +} ResumeS; + +static usblib_dev usblib = { + .irq_mask = USB_ISR_MSK, + .state = USB_UNCONNECTED, + .clk_id = RCC_USB, +}; +usblib_dev *USBLIB = &usblib; + +/* + * Routines + */ + +void usb_init_usblib(usblib_dev *dev, + void (**ep_int_in)(void), + void (**ep_int_out)(void)) { + rcc_clk_enable(dev->clk_id); + + dev->ep_int_in = ep_int_in; + dev->ep_int_out = ep_int_out; + + /* usb_lib/ declares both and then assumes that pFoo points to Foo + * (even though the names don't always match), which is stupid for + * all of the obvious reasons, but whatever. Here we are. */ + pInformation = &Device_Info; + pProperty = &Device_Property; + pUser_Standard_Requests = &User_Standard_Requests; + + pInformation->ControlState = 2; /* FIXME [0.0.12] use + CONTROL_STATE enumerator */ + pProperty->Init(); +} + +static void usb_suspend(void) { + uint16 cntr; + + /* TODO decide if read/modify/write is really what we want + * (e.g. usb_resume_init() reconfigures CNTR). */ + cntr = USB_BASE->CNTR; + cntr |= USB_CNTR_FSUSP; + USB_BASE->CNTR = cntr; + cntr |= USB_CNTR_LP_MODE; + USB_BASE->CNTR = cntr; + + USBLIB->state = USB_SUSPENDED; +} + +static void usb_resume_init(void) { + uint16 cntr; + + cntr = USB_BASE->CNTR; + cntr &= ~USB_CNTR_LP_MODE; + USB_BASE->CNTR = cntr; + + /* Enable interrupt lines */ + USB_BASE->CNTR = USB_ISR_MSK; +} + +static void usb_resume(RESUME_STATE eResumeSetVal) { + uint16 cntr; + + if (eResumeSetVal != RESUME_ESOF) + ResumeS.eState = eResumeSetVal; + + switch (ResumeS.eState) + { + case RESUME_EXTERNAL: + usb_resume_init(); + ResumeS.eState = RESUME_OFF; + break; + case RESUME_INTERNAL: + usb_resume_init(); + ResumeS.eState = RESUME_START; + break; + case RESUME_LATER: + ResumeS.bESOFcnt = 2; + ResumeS.eState = RESUME_WAIT; + break; + case RESUME_WAIT: + ResumeS.bESOFcnt--; + if (ResumeS.bESOFcnt == 0) + ResumeS.eState = RESUME_START; + break; + case RESUME_START: + cntr = USB_BASE->CNTR; + cntr |= USB_CNTR_RESUME; + USB_BASE->CNTR = cntr; + ResumeS.eState = RESUME_ON; + ResumeS.bESOFcnt = 10; + break; + case RESUME_ON: + ResumeS.bESOFcnt--; + if (ResumeS.bESOFcnt == 0) { + cntr = USB_BASE->CNTR; + cntr &= ~USB_CNTR_RESUME; + USB_BASE->CNTR = cntr; + ResumeS.eState = RESUME_OFF; + } + break; + case RESUME_OFF: + case RESUME_ESOF: + default: + ResumeS.eState = RESUME_OFF; + break; + } +} + +#define SUSPEND_ENABLED 1 +void __irq_usb_lp_can_rx0(void) { + uint16 istr = USB_BASE->ISTR; + + /* Use USB_ISR_MSK to only include code for bits we care about. */ + +#if (USB_ISR_MSK & USB_ISTR_RESET) + if (istr & USB_ISTR_RESET & USBLIB->irq_mask) { + USB_BASE->ISTR = ~USB_ISTR_RESET; + pProperty->Reset(); + } +#endif + +#if (USB_ISR_MSK & USB_ISTR_PMAOVR) + if (istr & ISTR_PMAOVR & USBLIB->irq_mask) { + USB_BASE->ISTR = ~USB_ISTR_PMAOVR; + } +#endif + +#if (USB_ISR_MSK & USB_ISTR_ERR) + if (istr & USB_ISTR_ERR & USBLIB->irq_mask) { + USB_BASE->ISTR = ~USB_ISTR_ERR; + } +#endif + +#if (USB_ISR_MSK & USB_ISTR_WKUP) + if (istr & USB_ISTR_WKUP & USBLIB->irq_mask) { + USB_BASE->ISTR = ~USB_ISTR_WKUP; + usb_resume(RESUME_EXTERNAL); + } +#endif + +#if (USB_ISR_MSK & USB_ISTR_SUSP) + if (istr & USB_ISTR_SUSP & USBLIB->irq_mask) { + /* check if SUSPEND is possible */ + if (SUSPEND_ENABLED) { + usb_suspend(); + } else { + /* if not possible then resume after xx ms */ + usb_resume(RESUME_LATER); + } + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + USB_BASE->ISTR = ~USB_ISTR_SUSP; +} +#endif + +#if (USB_ISR_MSK & USB_ISTR_SOF) + if (istr & USB_ISTR_SOF & USBLIB->irq_mask) { + USB_BASE->ISTR = ~USB_ISTR_SOF; + } +#endif + +#if (USB_ISR_MSK & USB_ISTR_ESOF) + if (istr & USB_ISTR_ESOF & USBLIB->irq_mask) { + USB_BASE->ISTR = ~USB_ISTR_ESOF; + /* resume handling timing is made with ESOFs */ + usb_resume(RESUME_ESOF); /* request without change of the machine state */ + } +#endif + + /* + * Service the correct transfer interrupt. + */ + +#if (USB_ISR_MSK & USB_ISTR_CTR) + if (istr & USB_ISTR_CTR & USBLIB->irq_mask) { + dispatch_ctr_lp(); + } +#endif +} + +/* + * Auxiliary routines + */ + +static inline uint8 dispatch_endpt_zero(uint16 istr_dir); +static inline void dispatch_endpt(uint8 ep); +static inline void set_rx_tx_status0(uint16 rx, uint16 tx); + +static void handle_setup0(void); +static void handle_in0(void); +static void handle_out0(void); + +static void dispatch_ctr_lp() { + uint16 istr; + while (((istr = USB_BASE->ISTR) & USB_ISTR_CTR) != 0) { + /* TODO WTF, figure this out: RM0008 says CTR is read-only, + * but ST's firmware claims it's clear-only, and emphasizes + * the importance of clearing it in more than one place. */ + USB_BASE->ISTR = ~USB_ISTR_CTR; + uint8 ep_id = istr & USB_ISTR_EP_ID; + if (ep_id == 0) { + /* TODO figure out why it's OK to break out of the loop + * once we're done serving endpoint zero, but not okay if + * there are multiple nonzero endpoint transfers to + * handle. */ + if (dispatch_endpt_zero(istr & USB_ISTR_DIR)) + return; + } else { + dispatch_endpt(ep_id); + } + } +} + +/* FIXME Dataflow on endpoint 0 RX/TX status is based off of ST's + * code, and is ugly/confusing in its use of SaveRState/SaveTState. + * Fixing this requires filling in handle_in0(), handle_setup0(), + * handle_out0(). */ +static inline uint8 dispatch_endpt_zero(uint16 istr_dir) { + uint32 epr = (uint16)USB_BASE->EP[0]; + + if (!(epr & (USB_EP_CTR_TX | USB_EP_SETUP | USB_EP_CTR_RX))) { + return 0; + } + + /* Cache RX/TX statuses in SaveRState/SaveTState, respectively. + * The various handle_foo0() may clobber these values + * before we reset them at the end of this routine. */ + SaveRState = epr & USB_EP_STAT_RX; + SaveTState = epr & USB_EP_STAT_TX; + + /* Set actual RX/TX statuses to NAK while we're thinking */ + set_rx_tx_status0(USB_EP_STAT_RX_NAK, USB_EP_STAT_TX_NAK); + + if (istr_dir == 0) { + /* ST RM0008: "If DIR bit=0, CTR_TX bit is set in the USB_EPnR + * register related to the interrupting endpoint. The + * interrupting transaction is of IN type (data transmitted by + * the USB peripheral to the host PC)." */ + ASSERT_FAULT(epr & USB_EP_CTR_TX); + usb_clear_ctr_tx(USB_EP0); + handle_in0(); + } else { + /* RM0008: "If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX + * are set in the USB_EPnR register related to the + * interrupting endpoint. The interrupting transaction is of + * OUT type (data received by the USB peripheral from the host + * PC) or two pending transactions are waiting to be + * processed." + * + * [mbolivar] Note how the following control flow (which + * replicates ST's) doesn't seem to actually handle both + * interrupts that are ostensibly pending when both CTR_RX and + * CTR_TX are set. + * + * TODO sort this mess out. + */ + if (epr & USB_EP_CTR_TX) { + usb_clear_ctr_tx(USB_EP0); + handle_in0(); + } else { /* SETUP or CTR_RX */ + /* SETUP is held constant while CTR_RX is set, so clear it + * either way */ + usb_clear_ctr_rx(USB_EP0); + if (epr & USB_EP_SETUP) { + handle_setup0(); + } else { /* CTR_RX */ + handle_out0(); + } + } + } + + set_rx_tx_status0(SaveRState, SaveTState); + return 1; +} + +static inline void dispatch_endpt(uint8 ep) { + uint32 epr = USB_BASE->EP[ep]; + /* If ISTR_CTR is set and the ISTR gave us this EP_ID to handle, + * then presumably at least one of CTR_RX and CTR_TX is set, but + * again, ST's control flow allows for the possibility of neither. + * + * TODO try to find out if neither being set is possible. */ + if (epr & USB_EP_CTR_RX) { + usb_clear_ctr_rx(ep); + (USBLIB->ep_int_out[ep - 1])(); + } + if (epr & USB_EP_CTR_TX) { + usb_clear_ctr_tx(ep); + (USBLIB->ep_int_in[ep - 1])(); + } +} + +static inline void set_rx_tx_status0(uint16 rx, uint16 tx) { + usb_set_ep_rx_stat(USB_EP0, rx); + usb_set_ep_tx_stat(USB_EP0, tx); +} + +/* TODO Rip out usb_lib/ dependency from the following functions: */ + +static void handle_setup0(void) { + Setup0_Process(); +} + +static void handle_in0(void) { + In0_Process(); +} + +static void handle_out0(void) { + Out0_Process(); +} diff --git a/libmaple/usb/stm32f1/usb_cdcacm.c b/libmaple/usb/stm32f1/usb_cdcacm.c new file mode 100644 index 0000000..6ef4806 --- /dev/null +++ b/libmaple/usb/stm32f1/usb_cdcacm.c @@ -0,0 +1,762 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/usb/usb_cdcacm.c + * @brief USB CDC ACM (a.k.a. virtual serial terminal, VCOM). + * + * FIXME: this works on the STM32F1 USB peripherals, and probably no + * place else. Nonportable bits really need to be factored out, and + * the result made cleaner. + */ + +#include + +#include +#include +#include + +/* Private headers */ +#include "usb_descriptors.h" +#include "usb_lib_globals.h" +#include "usb_reg_map.h" + +/* usb_lib headers */ +#include "usb_type.h" +#include "usb_core.h" +#include "usb_def.h" + +/****************************************************************************** + ****************************************************************************** + *** + *** HACK ALERT! FIXME FIXME FIXME FIXME! + *** + *** A bunch of LeafLabs-specific configuration lives in here for + *** now. This mess REALLY needs to get teased apart, with + *** appropriate pieces moved into Wirish. + *** + ****************************************************************************** + *****************************************************************************/ + +#if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) || \ + defined(BOARD_maple_mini) || defined(BOARD_maple_native)) +#warning USB CDC ACM relies on LeafLabs board-specific configuration.\ + You may have problems on non-LeafLabs boards. +#endif + +static void vcomDataTxCb(void); +static void vcomDataRxCb(void); +static uint8* vcomGetSetLineCoding(uint16); + +static void usbInit(void); +static void usbReset(void); +static RESULT usbDataSetup(uint8 request); +static RESULT usbNoDataSetup(uint8 request); +static RESULT usbGetInterfaceSetting(uint8 interface, uint8 alt_setting); +static uint8* usbGetDeviceDescriptor(uint16 length); +static uint8* usbGetConfigDescriptor(uint16 length); +static uint8* usbGetStringDescriptor(uint16 length); +static void usbSetConfiguration(void); +static void usbSetDeviceAddress(void); + +static void wait_reset(void); + +/* + * VCOM config + */ + +#define VCOM_CTRL_EPNUM 0x00 +#define VCOM_CTRL_RX_ADDR 0x40 +#define VCOM_CTRL_TX_ADDR 0x80 +#define VCOM_CTRL_EPSIZE 0x40 + +#define VCOM_TX_ENDP 1 +#define VCOM_TX_EPNUM 0x01 +#define VCOM_TX_ADDR 0xC0 +#define VCOM_TX_EPSIZE 0x40 + +#define VCOM_NOTIFICATION_ENDP 2 +#define VCOM_NOTIFICATION_EPNUM 0x02 +#define VCOM_NOTIFICATION_ADDR 0x100 +#define VCOM_NOTIFICATION_EPSIZE 0x40 + +#define VCOM_RX_ENDP 3 +#define VCOM_RX_EPNUM 0x03 +#define VCOM_RX_ADDR 0x110 +#define VCOM_RX_EPSIZE 0x40 +#define VCOM_RX_BUFLEN (VCOM_RX_EPSIZE*3) + +/* + * CDC ACM Requests + */ + +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_COMM_FEATURE 0x02 +#define SET_CONTROL_LINE_STATE 0x22 +#define CONTROL_LINE_DTR (0x01) +#define CONTROL_LINE_RTS (0x02) + +/* + * Descriptors + */ + +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_SUBCLASS_CDC 0x00 +#define LEAFLABS_ID_VENDOR 0x1EAF +#define MAPLE_ID_PRODUCT 0x0004 +const USB_Descriptor_Device usbVcomDescriptor_Device = { + .bLength = sizeof(USB_Descriptor_Device), + .bDescriptorType = USB_DESCRIPTOR_TYPE_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = USB_DEVICE_CLASS_CDC, + .bDeviceSubClass = USB_DEVICE_SUBCLASS_CDC, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = 0x40, + .idVendor = LEAFLABS_ID_VENDOR, + .idProduct = MAPLE_ID_PRODUCT, + .bcdDevice = 0x0200, + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x00, + .bNumConfigurations = 0x01, +}; + +#define MAX_POWER (100 >> 1) +const USB_Descriptor_Config usbVcomDescriptor_Config = { + .Config_Header = { + .bLength = sizeof(USB_Descriptor_Config_Header), + .bDescriptorType = USB_DESCRIPTOR_TYPE_CONFIGURATION, + .wTotalLength = sizeof(USB_Descriptor_Config), + .bNumInterfaces = 0x02, + .bConfigurationValue = 0x01, + .iConfiguration = 0x00, + .bmAttributes = (USB_CONFIG_ATTR_BUSPOWERED | + USB_CONFIG_ATTR_SELF_POWERED), + .bMaxPower = MAX_POWER, + }, + + .CCI_Interface = { + .bLength = sizeof(USB_Descriptor_Interface), + .bDescriptorType = USB_DESCRIPTOR_TYPE_INTERFACE, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x01, + .bInterfaceClass = USB_INTERFACE_CLASS_CDC, + .bInterfaceSubClass = USB_INTERFACE_SUBCLASS_CDC_ACM, + .bInterfaceProtocol = 0x01, /* Common AT Commands */ + .iInterface = 0x00, + }, + + .CDC_Functional_IntHeader = { + .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(2), + .bDescriptorType = 0x24, + .SubType = 0x00, + .Data = {0x01, 0x10}, + }, + + .CDC_Functional_CallManagement = { + .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(2), + .bDescriptorType = 0x24, + .SubType = 0x01, + .Data = {0x03, 0x01}, + }, + + .CDC_Functional_ACM = { + .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(1), + .bDescriptorType = 0x24, + .SubType = 0x02, + .Data = {0x06}, + }, + + .CDC_Functional_Union = { + .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(2), + .bDescriptorType = 0x24, + .SubType = 0x06, + .Data = {0x00, 0x01}, + }, + + .ManagementEndpoint = { + .bLength = sizeof(USB_Descriptor_Endpoint), + .bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT, + .bEndpointAddress = (USB_DESCRIPTOR_ENDPOINT_IN | + VCOM_NOTIFICATION_EPNUM), + .bmAttributes = EP_TYPE_INTERRUPT, + .wMaxPacketSize = VCOM_NOTIFICATION_EPSIZE, + .bInterval = 0xFF, + }, + + .DCI_Interface = { + .bLength = sizeof(USB_Descriptor_Interface), + .bDescriptorType = USB_DESCRIPTOR_TYPE_INTERFACE, + .bInterfaceNumber = 0x01, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = USB_INTERFACE_CLASS_DIC, + .bInterfaceSubClass = 0x00, /* None */ + .bInterfaceProtocol = 0x00, /* None */ + .iInterface = 0x00, + }, + + .DataOutEndpoint = { + .bLength = sizeof(USB_Descriptor_Endpoint), + .bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT, + .bEndpointAddress = (USB_DESCRIPTOR_ENDPOINT_OUT | VCOM_RX_EPNUM), + .bmAttributes = EP_TYPE_BULK, + .wMaxPacketSize = VCOM_RX_EPSIZE, + .bInterval = 0x00, + }, + + .DataInEndpoint = { + .bLength = sizeof(USB_Descriptor_Endpoint), + .bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT, + .bEndpointAddress = (USB_DESCRIPTOR_ENDPOINT_IN | VCOM_TX_EPNUM), + .bmAttributes = EP_TYPE_BULK, + .wMaxPacketSize = VCOM_TX_EPSIZE, + .bInterval = 0x00, + }, +}; + +/* + String Identifiers: + + we may choose to specify any or none of the following string + identifiers: + + iManufacturer: LeafLabs + iProduct: Maple + iSerialNumber: NONE + iConfiguration: NONE + iInterface(CCI): NONE + iInterface(DCI): NONE + + additionally we must provide the unicode language identifier, + which is 0x0409 for US English +*/ + +const uint8 usbVcomDescriptor_LangID[USB_DESCRIPTOR_STRING_LEN(1)] = { + USB_DESCRIPTOR_STRING_LEN(1), + USB_DESCRIPTOR_TYPE_STRING, + 0x09, + 0x04, +}; + +const uint8 usbVcomDescriptor_iManufacturer[USB_DESCRIPTOR_STRING_LEN(8)] = { + USB_DESCRIPTOR_STRING_LEN(8), + USB_DESCRIPTOR_TYPE_STRING, + 'L', 0, 'e', 0, 'a', 0, 'f', 0, + 'L', 0, 'a', 0, 'b', 0, 's', 0, +}; + +const uint8 usbVcomDescriptor_iProduct[USB_DESCRIPTOR_STRING_LEN(8)] = { + USB_DESCRIPTOR_STRING_LEN(8), + USB_DESCRIPTOR_TYPE_STRING, + 'M', 0, 'a', 0, 'p', 0, 'l', 0, + 'e', 0, ' ', 0, ' ', 0, ' ', 0 +}; + +ONE_DESCRIPTOR Device_Descriptor = { + (uint8*)&usbVcomDescriptor_Device, + sizeof(USB_Descriptor_Device) +}; + +ONE_DESCRIPTOR Config_Descriptor = { + (uint8*)&usbVcomDescriptor_Config, + sizeof(USB_Descriptor_Config) +}; + +ONE_DESCRIPTOR String_Descriptor[3] = { + {(uint8*)&usbVcomDescriptor_LangID, USB_DESCRIPTOR_STRING_LEN(1)}, + {(uint8*)&usbVcomDescriptor_iManufacturer,USB_DESCRIPTOR_STRING_LEN(8)}, + {(uint8*)&usbVcomDescriptor_iProduct, USB_DESCRIPTOR_STRING_LEN(8)} +}; + +/* + * Etc. + */ + +typedef enum { + DTR_UNSET, + DTR_HIGH, + DTR_NEGEDGE, + DTR_LOW +} RESET_STATE; + +typedef struct { + uint32 bitrate; + uint8 format; + uint8 paritytype; + uint8 datatype; +} USB_Line_Coding; + +uint8 last_request = 0; +USB_Line_Coding line_coding = { + .bitrate = 115200, + .format = 0x00, /* stop bits-1 */ + .paritytype = 0x00, + .datatype = 0x08 +}; +uint8 vcomBufferRx[VCOM_RX_BUFLEN]; +volatile uint32 countTx = 0; +volatile uint32 recvBufIn = 0; +volatile uint32 recvBufOut = 0; +volatile uint32 maxNewBytes = VCOM_RX_BUFLEN; +volatile uint32 newBytes = 0; +RESET_STATE reset_state = DTR_UNSET; +uint8 line_dtr_rts = 0; + +/* + * Endpoint callbacks + */ + +static void (*ep_int_in[7])(void) = + {vcomDataTxCb, + NOP_Process, + NOP_Process, + NOP_Process, + NOP_Process, + NOP_Process, + NOP_Process}; + +static void (*ep_int_out[7])(void) = + {NOP_Process, + NOP_Process, + vcomDataRxCb, + NOP_Process, + NOP_Process, + NOP_Process, + NOP_Process}; + +/* + * Globals required by usb_lib/ + */ + +#define NUM_ENDPTS 0x04 +DEVICE Device_Table = { + .Total_Endpoint = NUM_ENDPTS, + .Total_Configuration = 1 +}; + +#define MAX_PACKET_SIZE 0x40 /* 64B, maximum for USB FS Devices */ +DEVICE_PROP Device_Property = { + .Init = usbInit, + .Reset = usbReset, + .Process_Status_IN = NOP_Process, + .Process_Status_OUT = NOP_Process, + .Class_Data_Setup = usbDataSetup, + .Class_NoData_Setup = usbNoDataSetup, + .Class_Get_Interface_Setting = usbGetInterfaceSetting, + .GetDeviceDescriptor = usbGetDeviceDescriptor, + .GetConfigDescriptor = usbGetConfigDescriptor, + .GetStringDescriptor = usbGetStringDescriptor, + .RxEP_buffer = NULL, + .MaxPacketSize = MAX_PACKET_SIZE +}; + +USER_STANDARD_REQUESTS User_Standard_Requests = { + .User_GetConfiguration = NOP_Process, + .User_SetConfiguration = usbSetConfiguration, + .User_GetInterface = NOP_Process, + .User_SetInterface = NOP_Process, + .User_GetStatus = NOP_Process, + .User_ClearFeature = NOP_Process, + .User_SetEndPointFeature = NOP_Process, + .User_SetDeviceFeature = NOP_Process, + .User_SetDeviceAddress = usbSetDeviceAddress +}; + +/* + * CDC ACM interface + */ + +void usb_cdcacm_enable(gpio_dev *disc_dev, uint8 disc_bit) { + /* Present ourselves to the host */ + gpio_set_mode(disc_dev, disc_bit, GPIO_OUTPUT_PP); + gpio_write_bit(disc_dev, disc_bit, 0); // presents us to the host + + /* initialize USB peripheral */ + usb_init_usblib(USBLIB, ep_int_in, ep_int_out); +} + +void usb_cdcacm_disable(gpio_dev *disc_dev, uint8 disc_bit) { + // These are just guesses about how to do this, but it seems to work. + // TODO: verify this with USB spec + nvic_irq_disable(NVIC_USB_LP_CAN_RX0); + gpio_write_bit(disc_dev, disc_bit, 1); +} + +void usb_cdcacm_putc(char ch) { + while (!usb_cdcacm_tx((uint8*)&ch, 1)) + ; +} + +/* This function is non-blocking. + * + * It copies data from a usercode buffer into the USB peripheral TX + * buffer and return the number placed in that buffer. + */ +uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) { + /* Last transmission hasn't finished, abort */ + if (countTx) { + return 0; + } + + // We can only put VCOM_TX_EPSIZE bytes in the buffer + /* FIXME then why are we only copying half as many? */ + if (len > VCOM_TX_EPSIZE / 2) { + len = VCOM_TX_EPSIZE / 2; + } + + // Try to load some bytes if we can + if (len) { + usb_copy_to_pma(buf, len, VCOM_TX_ADDR); + usb_set_ep_tx_count(VCOM_TX_ENDP, len); + countTx += len; + usb_set_ep_tx_stat(VCOM_TX_ENDP, USB_EP_STAT_TX_VALID); + } + + return len; +} + +/* returns the number of available bytes are in the recv FIFO */ +uint32 usb_cdcacm_data_available(void) { + return newBytes; +} + +uint16 usb_cdcacm_get_pending() { + return countTx; +} + +/* Nonblocking byte receive. + * + * Copies up to len bytes from our private data buffer (*NOT* the PMA) + * into buf and deq's the FIFO. */ +uint32 usb_cdcacm_rx(uint8* buf, uint32 len) { + static int offset = 0; + int i; + + if (len > newBytes) { + len = newBytes; + } + + for (i = 0; i < len; i++) { + buf[i] = vcomBufferRx[i + offset]; + } + + newBytes -= len; + offset += len; + + /* Re-enable the RX endpoint, which we had set to receive 0 bytes */ + if (newBytes == 0) { + usb_set_ep_rx_count(VCOM_RX_ENDP, VCOM_RX_EPSIZE); + usb_set_ep_rx_stat(VCOM_RX_ENDP, USB_EP_STAT_RX_VALID); + offset = 0; + } + + return len; +} + +uint8 usb_cdcacm_get_dtr() { + return ((line_dtr_rts & CONTROL_LINE_DTR) != 0); +} + +uint8 usb_cdcacm_get_rts() { + return ((line_dtr_rts & CONTROL_LINE_RTS) != 0); +} + +/* + * Callbacks + */ + +static void vcomDataTxCb(void) { + /* assumes tx transactions are atomic 64 bytes (nearly certain they are) */ + countTx = 0; +} + +#define EXC_RETURN 0xFFFFFFF9 +#define DEFAULT_CPSR 0x61000000 +static void vcomDataRxCb(void) { + /* FIXME this is mad buggy */ + + /* setEPRxCount on the previous cycle should garuntee + we havnt received more bytes than we can fit */ + newBytes = usb_get_ep_rx_count(VCOM_RX_ENDP); + usb_set_ep_rx_stat(VCOM_RX_ENDP, USB_EP_STAT_RX_NAK); + + /* magic number, {0x31, 0x45, 0x41, 0x46} is "1EAF" */ + uint8 chkBuf[4]; + uint8 cmpBuf[4] = {0x31, 0x45, 0x41, 0x46}; + if (reset_state == DTR_NEGEDGE) { + reset_state = DTR_LOW; + + if (newBytes >= 4) { + unsigned int target = (unsigned int)wait_reset | 0x1; + + usb_copy_from_pma(chkBuf, 4, VCOM_RX_ADDR); + + int i; + USB_Bool cmpMatch = TRUE; + for (i = 0; i < 4; i++) { + if (chkBuf[i] != cmpBuf[i]) { + cmpMatch = FALSE; + } + } + + if (cmpMatch) { + asm volatile("mov r0, %[stack_top] \n\t" // Reset stack + "mov sp, r0 \n\t" + "mov r0, #1 \n\t" + "mov r1, %[target_addr] \n\t" + "mov r2, %[cpsr] \n\t" + "push {r2} \n\t" // Fake xPSR + "push {r1} \n\t" // PC target addr + "push {r0} \n\t" // Fake LR + "push {r0} \n\t" // Fake R12 + "push {r0} \n\t" // Fake R3 + "push {r0} \n\t" // Fake R2 + "push {r0} \n\t" // Fake R1 + "push {r0} \n\t" // Fake R0 + "mov lr, %[exc_return] \n\t" + "bx lr" + : + : [stack_top] "r" (STACK_TOP), + [target_addr] "r" (target), + [exc_return] "r" (EXC_RETURN), + [cpsr] "r" (DEFAULT_CPSR) + : "r0", "r1", "r2"); + /* should never get here */ + } + } + } + + usb_copy_from_pma(vcomBufferRx, newBytes, VCOM_RX_ADDR); +} + +static uint8* vcomGetSetLineCoding(uint16 length) { + if (length == 0) { + pInformation->Ctrl_Info.Usb_wLength = sizeof(USB_Line_Coding); + } + return (uint8*)&line_coding; +} + +static void usbInit(void) { + pInformation->Current_Configuration = 0; + + USB_BASE->CNTR = USB_CNTR_FRES; + + USBLIB->irq_mask = 0; + USB_BASE->CNTR = USBLIB->irq_mask; + USB_BASE->ISTR = 0; + USBLIB->irq_mask = USB_CNTR_RESETM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; + USB_BASE->CNTR = USBLIB->irq_mask; + + USB_BASE->ISTR = 0; + USBLIB->irq_mask = USB_ISR_MSK; + USB_BASE->CNTR = USBLIB->irq_mask; + + nvic_irq_enable(NVIC_USB_LP_CAN_RX0); + USBLIB->state = USB_UNCONNECTED; +} + +/* choose addresses to give endpoints the max 64 byte buffers */ +#define BTABLE_ADDRESS 0x00 +static void usbReset(void) { + pInformation->Current_Configuration = 0; + + /* current feature is current bmAttributes */ + pInformation->Current_Feature = (USB_CONFIG_ATTR_BUSPOWERED | + USB_CONFIG_ATTR_SELF_POWERED); + + USB_BASE->BTABLE = BTABLE_ADDRESS; + + /* setup control endpoint 0 */ + usb_set_ep_type(USB_EP0, USB_EP_EP_TYPE_CONTROL); + usb_set_ep_tx_stat(USB_EP0, USB_EP_STAT_TX_STALL); + usb_set_ep_rx_addr(USB_EP0, VCOM_CTRL_RX_ADDR); + usb_set_ep_tx_addr(USB_EP0, VCOM_CTRL_TX_ADDR); + usb_clear_status_out(USB_EP0); + + usb_set_ep_rx_count(USB_EP0, pProperty->MaxPacketSize); + usb_set_ep_rx_stat(USB_EP0, USB_EP_STAT_RX_VALID); + + /* setup management endpoint 1 */ + usb_set_ep_type(VCOM_NOTIFICATION_ENDP, USB_EP_EP_TYPE_INTERRUPT); + usb_set_ep_tx_addr(VCOM_NOTIFICATION_ENDP, VCOM_NOTIFICATION_ADDR); + usb_set_ep_tx_stat(VCOM_NOTIFICATION_ENDP, USB_EP_STAT_TX_NAK); + usb_set_ep_rx_stat(VCOM_NOTIFICATION_ENDP, USB_EP_STAT_RX_DISABLED); + + /* TODO figure out differences in style between RX/TX EP setup */ + + /* set up data endpoint OUT (RX) */ + usb_set_ep_type(VCOM_RX_ENDP, USB_EP_EP_TYPE_BULK); + usb_set_ep_rx_addr(VCOM_RX_ENDP, 0x110); + usb_set_ep_rx_count(VCOM_RX_ENDP, 64); + usb_set_ep_rx_stat(VCOM_RX_ENDP, USB_EP_STAT_RX_VALID); + + /* set up data endpoint IN (TX) */ + usb_set_ep_type(VCOM_TX_ENDP, USB_EP_EP_TYPE_BULK); + usb_set_ep_tx_addr(VCOM_TX_ENDP, VCOM_TX_ADDR); + usb_set_ep_tx_stat(VCOM_TX_ENDP, USB_EP_STAT_TX_NAK); + usb_set_ep_rx_stat(VCOM_TX_ENDP, USB_EP_STAT_RX_DISABLED); + + USBLIB->state = USB_ATTACHED; + SetDeviceAddress(0); + + /* reset the rx fifo */ + recvBufIn = 0; + recvBufOut = 0; + maxNewBytes = VCOM_RX_EPSIZE; + countTx = 0; +} + +static RESULT usbDataSetup(uint8 request) { + uint8 *(*CopyRoutine)(uint16); + CopyRoutine = NULL; + + if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT)) { + switch (request) { + case (GET_LINE_CODING): + CopyRoutine = vcomGetSetLineCoding; + last_request = GET_LINE_CODING; + break; + case (SET_LINE_CODING): + CopyRoutine = vcomGetSetLineCoding; + last_request = SET_LINE_CODING; + break; + default: + break; + } + } + + if (CopyRoutine == NULL) { + return USB_UNSUPPORT; + } + + pInformation->Ctrl_Info.CopyData = CopyRoutine; + pInformation->Ctrl_Info.Usb_wOffset = 0; + (*CopyRoutine)(0); + return USB_SUCCESS; +} + +static RESULT usbNoDataSetup(uint8 request) { + uint8 new_signal; + + /* we support set com feature but dont handle it */ + if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT)) { + + switch (request) { + case (SET_COMM_FEATURE): + return USB_SUCCESS; + case (SET_CONTROL_LINE_STATE): + /* to reset the board, pull both dtr and rts low + then pulse dtr by itself */ + new_signal = (pInformation->USBwValues.bw.bb0 & + (CONTROL_LINE_DTR | CONTROL_LINE_RTS)); + line_dtr_rts = new_signal & 0x03; + + switch (reset_state) { + /* no default, covered enum */ + case DTR_UNSET: + if ((new_signal & CONTROL_LINE_DTR) == 0 ) { + reset_state = DTR_LOW; + } else { + reset_state = DTR_HIGH; + } + break; + + case DTR_HIGH: + if ((new_signal & CONTROL_LINE_DTR) == 0 ) { + reset_state = DTR_NEGEDGE; + } else { + reset_state = DTR_HIGH; + } + break; + + case DTR_NEGEDGE: + if ((new_signal & CONTROL_LINE_DTR) == 0 ) { + reset_state = DTR_LOW; + } else { + reset_state = DTR_HIGH; + } + break; + + case DTR_LOW: + if ((new_signal & CONTROL_LINE_DTR) == 0 ) { + reset_state = DTR_LOW; + } else { + reset_state = DTR_HIGH; + } + break; + } + + return USB_SUCCESS; + } + } + return USB_UNSUPPORT; +} + +static RESULT usbGetInterfaceSetting(uint8 interface, uint8 alt_setting) { + if (alt_setting > 0) { + return USB_UNSUPPORT; + } else if (interface > 1) { + return USB_UNSUPPORT; + } + + return USB_SUCCESS; +} + +static uint8* usbGetDeviceDescriptor(uint16 length) { + return Standard_GetDescriptorData(length, &Device_Descriptor); +} + +static uint8* usbGetConfigDescriptor(uint16 length) { + return Standard_GetDescriptorData(length, &Config_Descriptor); +} + +static uint8* usbGetStringDescriptor(uint16 length) { + uint8 wValue0 = pInformation->USBwValue0; + + if (wValue0 > 2) { + return NULL; + } + return Standard_GetDescriptorData(length, &String_Descriptor[wValue0]); +} + +static void usbSetConfiguration(void) { + if (pInformation->Current_Configuration != 0) { + USBLIB->state = USB_CONFIGURED; + } +} + +static void usbSetDeviceAddress(void) { + USBLIB->state = USB_ADDRESSED; +} + +#define RESET_DELAY 100000 +static void wait_reset(void) { + delay_us(RESET_DELAY); + nvic_sys_reset(); +} diff --git a/libmaple/usb/stm32f1/usb_descriptors.h b/libmaple/usb/stm32f1/usb_descriptors.h new file mode 100644 index 0000000..9bcb2b6 --- /dev/null +++ b/libmaple/usb/stm32f1/usb_descriptors.h @@ -0,0 +1,148 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#ifndef _USB_DESCRIPTORS_H_ +#define _USB_DESCRIPTORS_H_ + +#include + +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB_DESCRIPTOR_TYPE_STRING 0x03 +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05 + +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_SUBCLASS_CDC 0x00 +#define USB_INTERFACE_CLASS_CDC 0x02 +/* CDC Abstract Control Model */ +#define USB_INTERFACE_SUBCLASS_CDC_ACM 0x02 +#define USB_INTERFACE_CLASS_DIC 0x0A + +#define USB_CONFIG_ATTR_BUSPOWERED 0b10000000 +#define USB_CONFIG_ATTR_SELF_POWERED 0b11000000 + +#define EP_TYPE_INTERRUPT 0x03 +#define EP_TYPE_BULK 0x02 + +#define USB_DESCRIPTOR_ENDPOINT_IN 0x80 +#define USB_DESCRIPTOR_ENDPOINT_OUT 0x00 + +#define USB_DESCRIPTOR_STRING_LEN(x) (2 + (x << 1)) + +#if defined(__cplusplus) +extern "C" { +#endif + +#define USB_DESCRIPTOR_STRING(len) \ + struct { \ + uint8 bLength; \ + uint8 bDescriptorType; \ + uint16 bString[len]; \ + } __packed + +#define CDC_FUNCTIONAL_DESCRIPTOR_SIZE(DataSize) (3 + DataSize) +#define CDC_FUNCTIONAL_DESCRIPTOR(DataSize) \ + struct { \ + uint8 bLength; \ + uint8 bDescriptorType; \ + uint8 SubType; \ + uint8 Data[DataSize]; \ + } __packed + +typedef struct { + uint8 bLength; + uint8 bDescriptorType; + uint16 bcdUSB; + uint8 bDeviceClass; + uint8 bDeviceSubClass; + uint8 bDeviceProtocol; + uint8 bMaxPacketSize0; + uint16 idVendor; + uint16 idProduct; + uint16 bcdDevice; + uint8 iManufacturer; + uint8 iProduct; + uint8 iSerialNumber; + uint8 bNumConfigurations; +} __packed USB_Descriptor_Device; + +typedef struct { + uint8 bLength; + uint8 bDescriptorType; + uint16 wTotalLength; + uint8 bNumInterfaces; + uint8 bConfigurationValue; + uint8 iConfiguration; + uint8 bmAttributes; + uint8 bMaxPower; +} __packed USB_Descriptor_Config_Header; + +typedef struct { + uint8 bLength; + uint8 bDescriptorType; + uint8 bInterfaceNumber; + uint8 bAlternateSetting; + uint8 bNumEndpoints; + uint8 bInterfaceClass; + uint8 bInterfaceSubClass; + uint8 bInterfaceProtocol; + uint8 iInterface; +} __packed USB_Descriptor_Interface; + +typedef struct { + uint8 bLength; + uint8 bDescriptorType; + uint8 bEndpointAddress; + uint8 bmAttributes; + uint16 wMaxPacketSize; + uint8 bInterval; +} __packed USB_Descriptor_Endpoint; + +typedef struct { + USB_Descriptor_Config_Header Config_Header; + USB_Descriptor_Interface CCI_Interface; + CDC_FUNCTIONAL_DESCRIPTOR(2) CDC_Functional_IntHeader; + CDC_FUNCTIONAL_DESCRIPTOR(2) CDC_Functional_CallManagement; + CDC_FUNCTIONAL_DESCRIPTOR(1) CDC_Functional_ACM; + CDC_FUNCTIONAL_DESCRIPTOR(2) CDC_Functional_Union; + USB_Descriptor_Endpoint ManagementEndpoint; + USB_Descriptor_Interface DCI_Interface; + USB_Descriptor_Endpoint DataOutEndpoint; + USB_Descriptor_Endpoint DataInEndpoint; +} __packed USB_Descriptor_Config; + +typedef struct { + uint8 bLength; + uint8 bDescriptorType; + uint16 bString[]; +} USB_Descriptor_String; + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/libmaple/usb/stm32f1/usb_lib_globals.h b/libmaple/usb/stm32f1/usb_lib_globals.h new file mode 100644 index 0000000..1cd2754 --- /dev/null +++ b/libmaple/usb/stm32f1/usb_lib_globals.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#ifndef _USB_LIB_GLOBALS_H_ +#define _USB_LIB_GLOBALS_H_ + +/* usb_lib headers */ +#include "usb_type.h" +#include "usb_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern USER_STANDARD_REQUESTS User_Standard_Requests; +extern USER_STANDARD_REQUESTS *pUser_Standard_Requests; + +extern DEVICE_PROP Device_Property; +extern DEVICE_PROP *pProperty; + +extern DEVICE_INFO Device_Info; +extern DEVICE_INFO *pInformation; + +extern DEVICE Device_Table; +extern u16 SaveRState; +extern u16 SaveTState; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/usb/stm32f1/usb_reg_map.c b/libmaple/usb/stm32f1/usb_reg_map.c new file mode 100644 index 0000000..75562e1 --- /dev/null +++ b/libmaple/usb/stm32f1/usb_reg_map.c @@ -0,0 +1,79 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#include "usb_reg_map.h" + +/* TODO these could use some improvement; they're fairly + * straightforward ports of the analogous ST code. The PMA blit + * routines in particular are obvious targets for performance + * measurement and tuning. */ + +void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset) { + uint16 *dst = (uint16*)usb_pma_ptr(pma_offset); + uint16 n = len >> 1; + uint16 i; + for (i = 0; i < n; i++) { + *dst = (uint16)(*buf) | *(buf + 1) << 8; + buf += 2; + dst += 2; + } + if (len & 1) { + *dst = *buf; + } +} + +void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset) { + uint32 *src = (uint32*)usb_pma_ptr(pma_offset); + uint16 *dst = (uint16*)buf; + uint16 n = len >> 1; + uint16 i; + for (i = 0; i < n; i++) { + *dst++ = *src++; + } + if (len & 1) { + *dst = *src & 0xFF; + } +} + +void usb_set_ep_rx_count(uint8 ep, uint16 count) { + uint32 *rxc = usb_ep_rx_count_ptr(ep); + uint16 nblocks; + if (count > 62) { + /* use 32-byte memory block size */ + nblocks = count >> 5; + if ((count & 0x1F) == 0) { + nblocks--; + } + *rxc = (nblocks << 10) | 0x8000; + } else { + /* use 2-byte memory block size */ + nblocks = count >> 1; + if ((count & 0x1) != 0) { + nblocks++; + } + *rxc = nblocks << 10; + } +} diff --git a/libmaple/usb/stm32f1/usb_reg_map.h b/libmaple/usb/stm32f1/usb_reg_map.h new file mode 100644 index 0000000..ce80842 --- /dev/null +++ b/libmaple/usb/stm32f1/usb_reg_map.h @@ -0,0 +1,433 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#include +#include + +#ifndef _USB_REG_MAP_H_ +#define _USB_REG_MAP_H_ + +/* TODO: + * - Pick one of "endp", "ep" "endpt" + */ + +/* + * Register map and base pointer + */ + +#define USB_NR_EP_REGS 8 + +/** USB register map type */ +typedef struct usb_reg_map { + __io uint32 EP[USB_NR_EP_REGS]; /**< Endpoint registers */ + const uint32 RESERVED[8]; /**< Reserved */ + __io uint32 CNTR; /**< Control register */ + __io uint32 ISTR; /**< Interrupt status register */ + __io uint32 FNR; /**< Frame number register */ + __io uint32 DADDR; /**< Device address */ + __io uint32 BTABLE; /**< @brief Buffer table address + * + * Address offset within the USB + * packet memory area which points + * to the base of the buffer + * descriptor table. Must be + * aligned to an 8 byte boundary. + */ +} usb_reg_map; + +/** USB register map base pointer */ +#define USB_BASE ((struct usb_reg_map*)0x40005C00) + +/* + * Register bit definitions + */ + +/* Endpoint registers (USB_EPnR) */ + +#define USB_EP_CTR_RX_BIT 15 +#define USB_EP_DTOG_RX_BIT 14 +#define USB_EP_SETUP_BIT 11 +#define USB_EP_EP_KIND_BIT 8 +#define USB_EP_CTR_TX_BIT 7 +#define USB_EP_DTOG_TX_BIT 6 + +#define USB_EP_CTR_RX BIT(USB_EP_CTR_RX_BIT) +#define USB_EP_DTOG_RX BIT(USB_EP_DTOG_RX_BIT) +#define USB_EP_STAT_RX (0x3 << 12) +#define USB_EP_STAT_RX_DISABLED (0x0 << 12) +#define USB_EP_STAT_RX_STALL (0x1 << 12) +#define USB_EP_STAT_RX_NAK (0x2 << 12) +#define USB_EP_STAT_RX_VALID (0x3 << 12) +#define USB_EP_SETUP BIT(USB_EP_SETUP_BIT) +#define USB_EP_EP_TYPE (0x3 << 9) +#define USB_EP_EP_TYPE_BULK (0x0 << 9) +#define USB_EP_EP_TYPE_CONTROL (0x1 << 9) +#define USB_EP_EP_TYPE_ISO (0x2 << 9) +#define USB_EP_EP_TYPE_INTERRUPT (0x3 << 9) +#define USB_EP_EP_KIND BIT(USB_EP_EP_KIND_BIT) +#define USB_EP_CTR_TX BIT(USB_EP_CTR_TX_BIT) +#define USB_EP_DTOG_TX BIT(USB_EP_DTOG_TX_BIT) +#define USB_EP_STAT_TX (0x3 << 4) +#define USB_EP_STAT_TX_DISABLED (0x0 << 4) +#define USB_EP_STAT_TX_STALL (0x1 << 4) +#define USB_EP_STAT_TX_NAK (0x2 << 4) +#define USB_EP_STAT_TX_VALID (0x3 << 4) +#define USB_EP_EA 0xF + +/* Control register (USB_CNTR) */ + +#define USB_CNTR_CTRM_BIT 15 +#define USB_CNTR_PMAOVERM_BIT 14 +#define USB_CNTR_ERRM_BIT 13 +#define USB_CNTR_WKUPM_BIT 12 +#define USB_CNTR_SUSPM_BIT 11 +#define USB_CNTR_RESETM_BIT 10 +#define USB_CNTR_SOFM_BIT 9 +#define USB_CNTR_ESOFM_BIT 8 +#define USB_CNTR_RESUME_BIT 4 +#define USB_CNTR_FSUSP_BIT 3 +#define USB_CNTR_LP_MODE_BIT 2 +#define USB_CNTR_PDWN_BIT 1 +#define USB_CNTR_FRES_BIT 0 + +#define USB_CNTR_CTRM BIT(USB_CNTR_CTRM_BIT) +#define USB_CNTR_PMAOVERM BIT(USB_CNTR_PMAOVERM_BIT) +#define USB_CNTR_ERRM BIT(USB_CNTR_ERRM_BIT) +#define USB_CNTR_WKUPM BIT(USB_CNTR_WKUPM_BIT) +#define USB_CNTR_SUSPM BIT(USB_CNTR_SUSPM_BIT) +#define USB_CNTR_RESETM BIT(USB_CNTR_RESETM_BIT) +#define USB_CNTR_SOFM BIT(USB_CNTR_SOFM_BIT) +#define USB_CNTR_ESOFM BIT(USB_CNTR_ESOFM_BIT) +#define USB_CNTR_RESUME BIT(USB_CNTR_RESUME_BIT) +#define USB_CNTR_FSUSP BIT(USB_CNTR_FSUSP_BIT) +#define USB_CNTR_LP_MODE BIT(USB_CNTR_LP_MODE_BIT) +#define USB_CNTR_PDWN BIT(USB_CNTR_PDWN_BIT) +#define USB_CNTR_FRES BIT(USB_CNTR_FRES_BIT) + +/* Interrupt status register (USB_ISTR) */ + +#define USB_ISTR_CTR_BIT 15 +#define USB_ISTR_PMAOVR_BIT 14 +#define USB_ISTR_ERR_BIT 13 +#define USB_ISTR_WKUP_BIT 12 +#define USB_ISTR_SUSP_BIT 11 +#define USB_ISTR_RESET_BIT 10 +#define USB_ISTR_SOF_BIT 9 +#define USB_ISTR_ESOF_BIT 8 +#define USB_ISTR_DIR_BIT 4 + +#define USB_ISTR_CTR BIT(USB_ISTR_CTR_BIT) +#define USB_ISTR_PMAOVR BIT(USB_ISTR_PMAOVR_BIT) +#define USB_ISTR_ERR BIT(USB_ISTR_ERR_BIT) +#define USB_ISTR_WKUP BIT(USB_ISTR_WKUP_BIT) +#define USB_ISTR_SUSP BIT(USB_ISTR_SUSP_BIT) +#define USB_ISTR_RESET BIT(USB_ISTR_RESET_BIT) +#define USB_ISTR_SOF BIT(USB_ISTR_SOF_BIT) +#define USB_ISTR_ESOF BIT(USB_ISTR_ESOF_BIT) +#define USB_ISTR_DIR BIT(USB_ISTR_DIR_BIT) +#define USB_ISTR_EP_ID 0xF + +/* Frame number register (USB_FNR) */ + +#define USB_FNR_RXDP_BIT 15 +#define USB_FNR_RXDM_BIT 14 +#define USB_FNR_LCK_BIT 13 + +#define USB_FNR_RXDP BIT(USB_FNR_RXDP_BIT) +#define USB_FNR_RXDM BIT(USB_FNR_RXDM_BIT) +#define USB_FNR_LCK BIT(USB_FNR_LCK_BIT) +#define USB_FNR_LSOF (0x3 << 11) +#define USB_FNR_FN 0x7FF + +/* Device address (USB_DADDR) */ + +#define USB_DADDR_EF_BIT 7 +#define USB_DADDR_ADD6_BIT 6 +#define USB_DADDR_ADD5_BIT 5 +#define USB_DADDR_ADD4_BIT 4 +#define USB_DADDR_ADD3_BIT 3 +#define USB_DADDR_ADD2_BIT 2 +#define USB_DADDR_ADD1_BIT 1 +#define USB_DADDR_ADD0_BIT 0 + +#define USB_DADDR_EF BIT(USB_DADDR_EF_BIT) +#define USB_DADDR_ADD6 BIT(USB_DADDR_ADD6_BIT) +#define USB_DADDR_ADD5 BIT(USB_DADDR_ADD5_BIT) +#define USB_DADDR_ADD4 BIT(USB_DADDR_ADD4_BIT) +#define USB_DADDR_ADD3 BIT(USB_DADDR_ADD3_BIT) +#define USB_DADDR_ADD2 BIT(USB_DADDR_ADD2_BIT) +#define USB_DADDR_ADD1 BIT(USB_DADDR_ADD1_BIT) +#define USB_DADDR_ADD0 BIT(USB_DADDR_ADD0_BIT) + +/* Buffer table address (USB_BTABLE) */ + +#define USB_BTABLE_BTABLE (0x1FFF << 3) + +/* + * Register convenience routines + */ + +#define __EP_CTR_NOP (USB_EP_CTR_RX | USB_EP_CTR_TX) +#define __EP_NONTOGGLE (USB_EP_CTR_RX | USB_EP_SETUP | \ + USB_EP_EP_TYPE | USB_EP_EP_KIND | \ + USB_EP_CTR_TX | USB_EP_EA) + +static inline void usb_clear_ctr_rx(uint8 ep) { + uint32 epr = USB_BASE->EP[ep]; + USB_BASE->EP[ep] = epr & ~USB_EP_CTR_RX & __EP_NONTOGGLE; +} + +static inline void usb_clear_ctr_tx(uint8 ep) { + uint32 epr = USB_BASE->EP[ep]; + USB_BASE->EP[ep] = epr & ~USB_EP_CTR_TX & __EP_NONTOGGLE; +} + +static inline void usb_set_ep_rx_stat(uint8 ep, uint32 status) { + uint32 epr = USB_BASE->EP[ep]; + epr &= ~(USB_EP_STAT_TX | USB_EP_DTOG_RX | USB_EP_DTOG_TX); + epr |= __EP_CTR_NOP; + epr ^= status; + USB_BASE->EP[ep] = epr; +} + +static inline void usb_set_ep_tx_stat(uint8 ep, uint32 status) { + uint32 epr = USB_BASE->EP[ep]; + epr &= ~(USB_EP_STAT_RX | USB_EP_DTOG_RX | USB_EP_DTOG_TX); + epr |= __EP_CTR_NOP; + epr ^= status; + USB_BASE->EP[ep] = epr; +} + +static inline void usb_set_ep_type(uint8 ep, uint32 type) { + uint32 epr = USB_BASE->EP[ep]; + epr &= ~USB_EP_EP_TYPE & __EP_NONTOGGLE; + epr |= type; + USB_BASE->EP[ep] = epr; +} + +static inline void usb_set_ep_kind(uint8 ep, uint32 kind) { + uint32 epr = USB_BASE->EP[ep]; + epr &= ~USB_EP_EP_KIND & __EP_NONTOGGLE; + epr |= kind; + USB_BASE->EP[ep] = epr; +} + +static inline void usb_clear_status_out(uint8 ep) { + usb_set_ep_kind(ep, 0); +} + +/* + * Packet memory area (PMA) base pointer + */ + +/** + * @brief USB packet memory area (PMA) base pointer. + * + * The USB PMA is SRAM shared between USB and CAN. The USB peripheral + * accesses this memory directly via the packet buffer interface. */ +#define USB_PMA_BASE ((__io void*)0x40006000) + +/* + * PMA conveniences + */ + +void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset); +void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset); + +static inline void* usb_pma_ptr(uint32 offset) { + return (void*)(USB_PMA_BASE + 2 * offset); +} + +/* + * BTABLE + */ + +/* (Forward-declared) BTABLE entry. + * + * The BTABLE can be viewed as an array of usb_btable_ent values; + * these vary in structure according to the configuration of the + * endpoint. + */ +union usb_btable_ent; + +/* Bidirectional endpoint BTABLE entry */ +typedef struct usb_btable_bidi { + __io uint16 addr_tx; const uint16 PAD1; + __io uint16 count_tx; const uint16 PAD2; + __io uint16 addr_rx; const uint16 PAD3; + __io uint16 count_rx; const uint16 PAD4; +} usb_btable_bidi; + +/* Unidirectional receive-only endpoint BTABLE entry */ +typedef struct usb_btable_uni_rx { + __io uint16 empty1; const uint16 PAD1; + __io uint16 empty2; const uint16 PAD2; + __io uint16 addr_rx; const uint16 PAD3; + __io uint16 count_rx; const uint16 PAD4; +} usb_btable_uni_rx; + +/* Unidirectional transmit-only endpoint BTABLE entry */ +typedef struct usb_btable_uni_tx { + __io uint16 addr_tx; const uint16 PAD1; + __io uint16 count_tx; const uint16 PAD2; + __io uint16 empty1; const uint16 PAD3; + __io uint16 empty2; const uint16 PAD4; +} usb_btable_uni_tx; + +/* Double-buffered transmission endpoint BTABLE entry */ +typedef struct usb_btable_dbl_tx { + __io uint16 addr_tx0; const uint16 PAD1; + __io uint16 count_tx0; const uint16 PAD2; + __io uint16 addr_tx1; const uint16 PAD3; + __io uint16 count_tx1; const uint16 PAD4; +} usb_btable_dbl_tx; + +/* Double-buffered reception endpoint BTABLE entry */ +typedef struct usb_btable_dbl_rx { + __io uint16 addr_rx0; const uint16 PAD1; + __io uint16 count_rx0; const uint16 PAD2; + __io uint16 addr_rx1; const uint16 PAD3; + __io uint16 count_rx1; const uint16 PAD4; +} usb_btable_dbl_rx; + +/* TODO isochronous endpoint entries */ + +/* Definition for above forward-declared BTABLE entry. */ +typedef union usb_btable_ent { + usb_btable_bidi bidi; + usb_btable_uni_rx u_rx; + usb_btable_uni_tx u_tx; + usb_btable_dbl_tx d_tx; + usb_btable_dbl_rx d_rx; +} usb_btable_ent; + +/* + * BTABLE conveniences + */ + +/* TODO (?) Convert usages of the many (and lengthily-named) + * accessors/mutators below to just manipulating usb_btable_entry + * values. */ + +static inline uint32* usb_btable_ptr(uint32 offset) { + return (uint32*)usb_pma_ptr(USB_BASE->BTABLE + offset); +} + +static inline usb_btable_ent *usb_btable(void) { + return (usb_btable_ent*)usb_btable_ptr(0); +} + +/* TX address */ + +static inline uint32* usb_ep_tx_addr_ptr(uint8 ep) { + return usb_btable_ptr(ep * 8); +} + +static inline uint16 usb_get_ep_tx_addr(uint8 ep) { + return (uint16)*usb_ep_tx_addr_ptr(ep); +} + +static inline void usb_set_ep_tx_addr(uint8 ep, uint16 addr) { + uint32 *tx_addr = usb_ep_tx_addr_ptr(ep); + *tx_addr = addr & ~0x1; +} + +/* RX address */ + +static inline uint32* usb_ep_rx_addr_ptr(uint8 ep) { + return usb_btable_ptr(ep * 8 + 4); +} + +static inline uint16 usb_get_ep_rx_addr(uint8 ep) { + return (uint16)*usb_ep_rx_addr_ptr(ep); +} + +static inline void usb_set_ep_rx_addr(uint8 ep, uint16 addr) { + uint32 *rx_addr = usb_ep_rx_addr_ptr(ep); + *rx_addr = addr & ~0x1; +} + +/* TX count (doesn't cover double-buffered and isochronous in) */ + +static inline uint32* usb_ep_tx_count_ptr(uint8 ep) { + return usb_btable_ptr(ep * 8 + 2); +} + +static inline uint16 usb_get_ep_tx_count(uint8 ep) { + return (uint16)*usb_ep_tx_count_ptr(ep); +} + +static inline void usb_set_ep_tx_count(uint8 ep, uint16 count) { + uint32 *txc = usb_ep_tx_count_ptr(ep); + *txc = count; +} + +/* RX count */ + +static inline uint32* usb_ep_rx_count_ptr(uint8 ep) { + return usb_btable_ptr(ep * 8 + 6); +} + +static inline uint16 usb_get_ep_rx_count(uint8 ep) { + return (uint16)*usb_ep_rx_count_ptr(ep) & 0x3FF; +} + +void usb_set_ep_rx_count(uint8 ep, uint16 count); + +/* + * Misc. types + */ + +typedef enum usb_ep { + USB_EP0, + USB_EP1, + USB_EP2, + USB_EP3, + USB_EP4, + USB_EP5, + USB_EP6, + USB_EP7, +} usb_ep; + +typedef enum usb_ep_type { + USB_EP_T_CTL = USB_EP_EP_TYPE_CONTROL, + USB_EP_T_BULK = USB_EP_EP_TYPE_BULK, + USB_EP_T_INT = USB_EP_EP_TYPE_INTERRUPT, + USB_EP_T_ISO = USB_EP_EP_TYPE_ISO +} usb_ep_type; + +typedef enum usb_ep_stat { + USB_EP_ST_RX_DIS = USB_EP_STAT_RX_DISABLED, + USB_EP_ST_RX_STL = USB_EP_STAT_RX_STALL, + USB_EP_ST_RX_NAK = USB_EP_STAT_RX_NAK, + USB_EP_ST_RX_VAL = USB_EP_STAT_RX_VALID, + USB_EP_ST_TX_DIS = USB_EP_STAT_TX_DISABLED, + USB_EP_ST_TX_STL = USB_EP_STAT_TX_STALL, + USB_EP_ST_TX_NAK = USB_EP_STAT_TX_NAK, + USB_EP_ST_TX_VAL = USB_EP_STAT_TX_VALID +} usb_ep_stat; + +#endif diff --git a/libmaple/usb/usb.c b/libmaple/usb/usb.c deleted file mode 100644 index 0130bab..0000000 --- a/libmaple/usb/usb.c +++ /dev/null @@ -1,381 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/usb/usb.c - * @brief USB support. - * - * This is a mess. What we need almost amounts to a ground-up rewrite. - */ - -#include - -#include -#include - -/* Private headers */ -#include "usb_reg_map.h" -#include "usb_lib_globals.h" - -/* usb_lib headers */ -#include "usb_type.h" -#include "usb_core.h" - -static void dispatch_ctr_lp(void); - -/* - * usb_lib/ globals - */ - -uint16 SaveTState; /* caches TX status for later use */ -uint16 SaveRState; /* caches RX status for later use */ - -/* - * Other state - */ - -typedef enum { - RESUME_EXTERNAL, - RESUME_INTERNAL, - RESUME_LATER, - RESUME_WAIT, - RESUME_START, - RESUME_ON, - RESUME_OFF, - RESUME_ESOF -} RESUME_STATE; - -struct { - volatile RESUME_STATE eState; - volatile uint8 bESOFcnt; -} ResumeS; - -static usblib_dev usblib = { - .irq_mask = USB_ISR_MSK, - .state = USB_UNCONNECTED, - .clk_id = RCC_USB, -}; -usblib_dev *USBLIB = &usblib; - -/* - * Routines - */ - -void usb_init_usblib(usblib_dev *dev, - void (**ep_int_in)(void), - void (**ep_int_out)(void)) { - rcc_clk_enable(dev->clk_id); - - dev->ep_int_in = ep_int_in; - dev->ep_int_out = ep_int_out; - - /* usb_lib/ declares both and then assumes that pFoo points to Foo - * (even though the names don't always match), which is stupid for - * all of the obvious reasons, but whatever. Here we are. */ - pInformation = &Device_Info; - pProperty = &Device_Property; - pUser_Standard_Requests = &User_Standard_Requests; - - pInformation->ControlState = 2; /* FIXME [0.0.12] use - CONTROL_STATE enumerator */ - pProperty->Init(); -} - -static void usb_suspend(void) { - uint16 cntr; - - /* TODO decide if read/modify/write is really what we want - * (e.g. usb_resume_init() reconfigures CNTR). */ - cntr = USB_BASE->CNTR; - cntr |= USB_CNTR_FSUSP; - USB_BASE->CNTR = cntr; - cntr |= USB_CNTR_LP_MODE; - USB_BASE->CNTR = cntr; - - USBLIB->state = USB_SUSPENDED; -} - -static void usb_resume_init(void) { - uint16 cntr; - - cntr = USB_BASE->CNTR; - cntr &= ~USB_CNTR_LP_MODE; - USB_BASE->CNTR = cntr; - - /* Enable interrupt lines */ - USB_BASE->CNTR = USB_ISR_MSK; -} - -static void usb_resume(RESUME_STATE eResumeSetVal) { - uint16 cntr; - - if (eResumeSetVal != RESUME_ESOF) - ResumeS.eState = eResumeSetVal; - - switch (ResumeS.eState) - { - case RESUME_EXTERNAL: - usb_resume_init(); - ResumeS.eState = RESUME_OFF; - break; - case RESUME_INTERNAL: - usb_resume_init(); - ResumeS.eState = RESUME_START; - break; - case RESUME_LATER: - ResumeS.bESOFcnt = 2; - ResumeS.eState = RESUME_WAIT; - break; - case RESUME_WAIT: - ResumeS.bESOFcnt--; - if (ResumeS.bESOFcnt == 0) - ResumeS.eState = RESUME_START; - break; - case RESUME_START: - cntr = USB_BASE->CNTR; - cntr |= USB_CNTR_RESUME; - USB_BASE->CNTR = cntr; - ResumeS.eState = RESUME_ON; - ResumeS.bESOFcnt = 10; - break; - case RESUME_ON: - ResumeS.bESOFcnt--; - if (ResumeS.bESOFcnt == 0) { - cntr = USB_BASE->CNTR; - cntr &= ~USB_CNTR_RESUME; - USB_BASE->CNTR = cntr; - ResumeS.eState = RESUME_OFF; - } - break; - case RESUME_OFF: - case RESUME_ESOF: - default: - ResumeS.eState = RESUME_OFF; - break; - } -} - -#define SUSPEND_ENABLED 1 -void __irq_usb_lp_can_rx0(void) { - uint16 istr = USB_BASE->ISTR; - - /* Use USB_ISR_MSK to only include code for bits we care about. */ - -#if (USB_ISR_MSK & USB_ISTR_RESET) - if (istr & USB_ISTR_RESET & USBLIB->irq_mask) { - USB_BASE->ISTR = ~USB_ISTR_RESET; - pProperty->Reset(); - } -#endif - -#if (USB_ISR_MSK & USB_ISTR_PMAOVR) - if (istr & ISTR_PMAOVR & USBLIB->irq_mask) { - USB_BASE->ISTR = ~USB_ISTR_PMAOVR; - } -#endif - -#if (USB_ISR_MSK & USB_ISTR_ERR) - if (istr & USB_ISTR_ERR & USBLIB->irq_mask) { - USB_BASE->ISTR = ~USB_ISTR_ERR; - } -#endif - -#if (USB_ISR_MSK & USB_ISTR_WKUP) - if (istr & USB_ISTR_WKUP & USBLIB->irq_mask) { - USB_BASE->ISTR = ~USB_ISTR_WKUP; - usb_resume(RESUME_EXTERNAL); - } -#endif - -#if (USB_ISR_MSK & USB_ISTR_SUSP) - if (istr & USB_ISTR_SUSP & USBLIB->irq_mask) { - /* check if SUSPEND is possible */ - if (SUSPEND_ENABLED) { - usb_suspend(); - } else { - /* if not possible then resume after xx ms */ - usb_resume(RESUME_LATER); - } - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - USB_BASE->ISTR = ~USB_ISTR_SUSP; -} -#endif - -#if (USB_ISR_MSK & USB_ISTR_SOF) - if (istr & USB_ISTR_SOF & USBLIB->irq_mask) { - USB_BASE->ISTR = ~USB_ISTR_SOF; - } -#endif - -#if (USB_ISR_MSK & USB_ISTR_ESOF) - if (istr & USB_ISTR_ESOF & USBLIB->irq_mask) { - USB_BASE->ISTR = ~USB_ISTR_ESOF; - /* resume handling timing is made with ESOFs */ - usb_resume(RESUME_ESOF); /* request without change of the machine state */ - } -#endif - - /* - * Service the correct transfer interrupt. - */ - -#if (USB_ISR_MSK & USB_ISTR_CTR) - if (istr & USB_ISTR_CTR & USBLIB->irq_mask) { - dispatch_ctr_lp(); - } -#endif -} - -/* - * Auxiliary routines - */ - -static inline uint8 dispatch_endpt_zero(uint16 istr_dir); -static inline void dispatch_endpt(uint8 ep); -static inline void set_rx_tx_status0(uint16 rx, uint16 tx); - -static void handle_setup0(void); -static void handle_in0(void); -static void handle_out0(void); - -static void dispatch_ctr_lp() { - uint16 istr; - while (((istr = USB_BASE->ISTR) & USB_ISTR_CTR) != 0) { - /* TODO WTF, figure this out: RM0008 says CTR is read-only, - * but ST's firmware claims it's clear-only, and emphasizes - * the importance of clearing it in more than one place. */ - USB_BASE->ISTR = ~USB_ISTR_CTR; - uint8 ep_id = istr & USB_ISTR_EP_ID; - if (ep_id == 0) { - /* TODO figure out why it's OK to break out of the loop - * once we're done serving endpoint zero, but not okay if - * there are multiple nonzero endpoint transfers to - * handle. */ - if (dispatch_endpt_zero(istr & USB_ISTR_DIR)) - return; - } else { - dispatch_endpt(ep_id); - } - } -} - -/* FIXME Dataflow on endpoint 0 RX/TX status is based off of ST's - * code, and is ugly/confusing in its use of SaveRState/SaveTState. - * Fixing this requires filling in handle_in0(), handle_setup0(), - * handle_out0(). */ -static inline uint8 dispatch_endpt_zero(uint16 istr_dir) { - uint32 epr = (uint16)USB_BASE->EP[0]; - - if (!(epr & (USB_EP_CTR_TX | USB_EP_SETUP | USB_EP_CTR_RX))) { - return 0; - } - - /* Cache RX/TX statuses in SaveRState/SaveTState, respectively. - * The various handle_foo0() may clobber these values - * before we reset them at the end of this routine. */ - SaveRState = epr & USB_EP_STAT_RX; - SaveTState = epr & USB_EP_STAT_TX; - - /* Set actual RX/TX statuses to NAK while we're thinking */ - set_rx_tx_status0(USB_EP_STAT_RX_NAK, USB_EP_STAT_TX_NAK); - - if (istr_dir == 0) { - /* ST RM0008: "If DIR bit=0, CTR_TX bit is set in the USB_EPnR - * register related to the interrupting endpoint. The - * interrupting transaction is of IN type (data transmitted by - * the USB peripheral to the host PC)." */ - ASSERT_FAULT(epr & USB_EP_CTR_TX); - usb_clear_ctr_tx(USB_EP0); - handle_in0(); - } else { - /* RM0008: "If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX - * are set in the USB_EPnR register related to the - * interrupting endpoint. The interrupting transaction is of - * OUT type (data received by the USB peripheral from the host - * PC) or two pending transactions are waiting to be - * processed." - * - * [mbolivar] Note how the following control flow (which - * replicates ST's) doesn't seem to actually handle both - * interrupts that are ostensibly pending when both CTR_RX and - * CTR_TX are set. - * - * TODO sort this mess out. - */ - if (epr & USB_EP_CTR_TX) { - usb_clear_ctr_tx(USB_EP0); - handle_in0(); - } else { /* SETUP or CTR_RX */ - /* SETUP is held constant while CTR_RX is set, so clear it - * either way */ - usb_clear_ctr_rx(USB_EP0); - if (epr & USB_EP_SETUP) { - handle_setup0(); - } else { /* CTR_RX */ - handle_out0(); - } - } - } - - set_rx_tx_status0(SaveRState, SaveTState); - return 1; -} - -static inline void dispatch_endpt(uint8 ep) { - uint32 epr = USB_BASE->EP[ep]; - /* If ISTR_CTR is set and the ISTR gave us this EP_ID to handle, - * then presumably at least one of CTR_RX and CTR_TX is set, but - * again, ST's control flow allows for the possibility of neither. - * - * TODO try to find out if neither being set is possible. */ - if (epr & USB_EP_CTR_RX) { - usb_clear_ctr_rx(ep); - (USBLIB->ep_int_out[ep - 1])(); - } - if (epr & USB_EP_CTR_TX) { - usb_clear_ctr_tx(ep); - (USBLIB->ep_int_in[ep - 1])(); - } -} - -static inline void set_rx_tx_status0(uint16 rx, uint16 tx) { - usb_set_ep_rx_stat(USB_EP0, rx); - usb_set_ep_tx_stat(USB_EP0, tx); -} - -/* TODO Rip out usb_lib/ dependency from the following functions: */ - -static void handle_setup0(void) { - Setup0_Process(); -} - -static void handle_in0(void) { - In0_Process(); -} - -static void handle_out0(void) { - Out0_Process(); -} diff --git a/libmaple/usb/usb_cdcacm.c b/libmaple/usb/usb_cdcacm.c deleted file mode 100644 index 6ef4806..0000000 --- a/libmaple/usb/usb_cdcacm.c +++ /dev/null @@ -1,762 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/usb/usb_cdcacm.c - * @brief USB CDC ACM (a.k.a. virtual serial terminal, VCOM). - * - * FIXME: this works on the STM32F1 USB peripherals, and probably no - * place else. Nonportable bits really need to be factored out, and - * the result made cleaner. - */ - -#include - -#include -#include -#include - -/* Private headers */ -#include "usb_descriptors.h" -#include "usb_lib_globals.h" -#include "usb_reg_map.h" - -/* usb_lib headers */ -#include "usb_type.h" -#include "usb_core.h" -#include "usb_def.h" - -/****************************************************************************** - ****************************************************************************** - *** - *** HACK ALERT! FIXME FIXME FIXME FIXME! - *** - *** A bunch of LeafLabs-specific configuration lives in here for - *** now. This mess REALLY needs to get teased apart, with - *** appropriate pieces moved into Wirish. - *** - ****************************************************************************** - *****************************************************************************/ - -#if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) || \ - defined(BOARD_maple_mini) || defined(BOARD_maple_native)) -#warning USB CDC ACM relies on LeafLabs board-specific configuration.\ - You may have problems on non-LeafLabs boards. -#endif - -static void vcomDataTxCb(void); -static void vcomDataRxCb(void); -static uint8* vcomGetSetLineCoding(uint16); - -static void usbInit(void); -static void usbReset(void); -static RESULT usbDataSetup(uint8 request); -static RESULT usbNoDataSetup(uint8 request); -static RESULT usbGetInterfaceSetting(uint8 interface, uint8 alt_setting); -static uint8* usbGetDeviceDescriptor(uint16 length); -static uint8* usbGetConfigDescriptor(uint16 length); -static uint8* usbGetStringDescriptor(uint16 length); -static void usbSetConfiguration(void); -static void usbSetDeviceAddress(void); - -static void wait_reset(void); - -/* - * VCOM config - */ - -#define VCOM_CTRL_EPNUM 0x00 -#define VCOM_CTRL_RX_ADDR 0x40 -#define VCOM_CTRL_TX_ADDR 0x80 -#define VCOM_CTRL_EPSIZE 0x40 - -#define VCOM_TX_ENDP 1 -#define VCOM_TX_EPNUM 0x01 -#define VCOM_TX_ADDR 0xC0 -#define VCOM_TX_EPSIZE 0x40 - -#define VCOM_NOTIFICATION_ENDP 2 -#define VCOM_NOTIFICATION_EPNUM 0x02 -#define VCOM_NOTIFICATION_ADDR 0x100 -#define VCOM_NOTIFICATION_EPSIZE 0x40 - -#define VCOM_RX_ENDP 3 -#define VCOM_RX_EPNUM 0x03 -#define VCOM_RX_ADDR 0x110 -#define VCOM_RX_EPSIZE 0x40 -#define VCOM_RX_BUFLEN (VCOM_RX_EPSIZE*3) - -/* - * CDC ACM Requests - */ - -#define SET_LINE_CODING 0x20 -#define GET_LINE_CODING 0x21 -#define SET_COMM_FEATURE 0x02 -#define SET_CONTROL_LINE_STATE 0x22 -#define CONTROL_LINE_DTR (0x01) -#define CONTROL_LINE_RTS (0x02) - -/* - * Descriptors - */ - -#define USB_DEVICE_CLASS_CDC 0x02 -#define USB_DEVICE_SUBCLASS_CDC 0x00 -#define LEAFLABS_ID_VENDOR 0x1EAF -#define MAPLE_ID_PRODUCT 0x0004 -const USB_Descriptor_Device usbVcomDescriptor_Device = { - .bLength = sizeof(USB_Descriptor_Device), - .bDescriptorType = USB_DESCRIPTOR_TYPE_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = USB_DEVICE_CLASS_CDC, - .bDeviceSubClass = USB_DEVICE_SUBCLASS_CDC, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = 0x40, - .idVendor = LEAFLABS_ID_VENDOR, - .idProduct = MAPLE_ID_PRODUCT, - .bcdDevice = 0x0200, - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x00, - .bNumConfigurations = 0x01, -}; - -#define MAX_POWER (100 >> 1) -const USB_Descriptor_Config usbVcomDescriptor_Config = { - .Config_Header = { - .bLength = sizeof(USB_Descriptor_Config_Header), - .bDescriptorType = USB_DESCRIPTOR_TYPE_CONFIGURATION, - .wTotalLength = sizeof(USB_Descriptor_Config), - .bNumInterfaces = 0x02, - .bConfigurationValue = 0x01, - .iConfiguration = 0x00, - .bmAttributes = (USB_CONFIG_ATTR_BUSPOWERED | - USB_CONFIG_ATTR_SELF_POWERED), - .bMaxPower = MAX_POWER, - }, - - .CCI_Interface = { - .bLength = sizeof(USB_Descriptor_Interface), - .bDescriptorType = USB_DESCRIPTOR_TYPE_INTERFACE, - .bInterfaceNumber = 0x00, - .bAlternateSetting = 0x00, - .bNumEndpoints = 0x01, - .bInterfaceClass = USB_INTERFACE_CLASS_CDC, - .bInterfaceSubClass = USB_INTERFACE_SUBCLASS_CDC_ACM, - .bInterfaceProtocol = 0x01, /* Common AT Commands */ - .iInterface = 0x00, - }, - - .CDC_Functional_IntHeader = { - .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(2), - .bDescriptorType = 0x24, - .SubType = 0x00, - .Data = {0x01, 0x10}, - }, - - .CDC_Functional_CallManagement = { - .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(2), - .bDescriptorType = 0x24, - .SubType = 0x01, - .Data = {0x03, 0x01}, - }, - - .CDC_Functional_ACM = { - .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(1), - .bDescriptorType = 0x24, - .SubType = 0x02, - .Data = {0x06}, - }, - - .CDC_Functional_Union = { - .bLength = CDC_FUNCTIONAL_DESCRIPTOR_SIZE(2), - .bDescriptorType = 0x24, - .SubType = 0x06, - .Data = {0x00, 0x01}, - }, - - .ManagementEndpoint = { - .bLength = sizeof(USB_Descriptor_Endpoint), - .bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT, - .bEndpointAddress = (USB_DESCRIPTOR_ENDPOINT_IN | - VCOM_NOTIFICATION_EPNUM), - .bmAttributes = EP_TYPE_INTERRUPT, - .wMaxPacketSize = VCOM_NOTIFICATION_EPSIZE, - .bInterval = 0xFF, - }, - - .DCI_Interface = { - .bLength = sizeof(USB_Descriptor_Interface), - .bDescriptorType = USB_DESCRIPTOR_TYPE_INTERFACE, - .bInterfaceNumber = 0x01, - .bAlternateSetting = 0x00, - .bNumEndpoints = 0x02, - .bInterfaceClass = USB_INTERFACE_CLASS_DIC, - .bInterfaceSubClass = 0x00, /* None */ - .bInterfaceProtocol = 0x00, /* None */ - .iInterface = 0x00, - }, - - .DataOutEndpoint = { - .bLength = sizeof(USB_Descriptor_Endpoint), - .bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT, - .bEndpointAddress = (USB_DESCRIPTOR_ENDPOINT_OUT | VCOM_RX_EPNUM), - .bmAttributes = EP_TYPE_BULK, - .wMaxPacketSize = VCOM_RX_EPSIZE, - .bInterval = 0x00, - }, - - .DataInEndpoint = { - .bLength = sizeof(USB_Descriptor_Endpoint), - .bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT, - .bEndpointAddress = (USB_DESCRIPTOR_ENDPOINT_IN | VCOM_TX_EPNUM), - .bmAttributes = EP_TYPE_BULK, - .wMaxPacketSize = VCOM_TX_EPSIZE, - .bInterval = 0x00, - }, -}; - -/* - String Identifiers: - - we may choose to specify any or none of the following string - identifiers: - - iManufacturer: LeafLabs - iProduct: Maple - iSerialNumber: NONE - iConfiguration: NONE - iInterface(CCI): NONE - iInterface(DCI): NONE - - additionally we must provide the unicode language identifier, - which is 0x0409 for US English -*/ - -const uint8 usbVcomDescriptor_LangID[USB_DESCRIPTOR_STRING_LEN(1)] = { - USB_DESCRIPTOR_STRING_LEN(1), - USB_DESCRIPTOR_TYPE_STRING, - 0x09, - 0x04, -}; - -const uint8 usbVcomDescriptor_iManufacturer[USB_DESCRIPTOR_STRING_LEN(8)] = { - USB_DESCRIPTOR_STRING_LEN(8), - USB_DESCRIPTOR_TYPE_STRING, - 'L', 0, 'e', 0, 'a', 0, 'f', 0, - 'L', 0, 'a', 0, 'b', 0, 's', 0, -}; - -const uint8 usbVcomDescriptor_iProduct[USB_DESCRIPTOR_STRING_LEN(8)] = { - USB_DESCRIPTOR_STRING_LEN(8), - USB_DESCRIPTOR_TYPE_STRING, - 'M', 0, 'a', 0, 'p', 0, 'l', 0, - 'e', 0, ' ', 0, ' ', 0, ' ', 0 -}; - -ONE_DESCRIPTOR Device_Descriptor = { - (uint8*)&usbVcomDescriptor_Device, - sizeof(USB_Descriptor_Device) -}; - -ONE_DESCRIPTOR Config_Descriptor = { - (uint8*)&usbVcomDescriptor_Config, - sizeof(USB_Descriptor_Config) -}; - -ONE_DESCRIPTOR String_Descriptor[3] = { - {(uint8*)&usbVcomDescriptor_LangID, USB_DESCRIPTOR_STRING_LEN(1)}, - {(uint8*)&usbVcomDescriptor_iManufacturer,USB_DESCRIPTOR_STRING_LEN(8)}, - {(uint8*)&usbVcomDescriptor_iProduct, USB_DESCRIPTOR_STRING_LEN(8)} -}; - -/* - * Etc. - */ - -typedef enum { - DTR_UNSET, - DTR_HIGH, - DTR_NEGEDGE, - DTR_LOW -} RESET_STATE; - -typedef struct { - uint32 bitrate; - uint8 format; - uint8 paritytype; - uint8 datatype; -} USB_Line_Coding; - -uint8 last_request = 0; -USB_Line_Coding line_coding = { - .bitrate = 115200, - .format = 0x00, /* stop bits-1 */ - .paritytype = 0x00, - .datatype = 0x08 -}; -uint8 vcomBufferRx[VCOM_RX_BUFLEN]; -volatile uint32 countTx = 0; -volatile uint32 recvBufIn = 0; -volatile uint32 recvBufOut = 0; -volatile uint32 maxNewBytes = VCOM_RX_BUFLEN; -volatile uint32 newBytes = 0; -RESET_STATE reset_state = DTR_UNSET; -uint8 line_dtr_rts = 0; - -/* - * Endpoint callbacks - */ - -static void (*ep_int_in[7])(void) = - {vcomDataTxCb, - NOP_Process, - NOP_Process, - NOP_Process, - NOP_Process, - NOP_Process, - NOP_Process}; - -static void (*ep_int_out[7])(void) = - {NOP_Process, - NOP_Process, - vcomDataRxCb, - NOP_Process, - NOP_Process, - NOP_Process, - NOP_Process}; - -/* - * Globals required by usb_lib/ - */ - -#define NUM_ENDPTS 0x04 -DEVICE Device_Table = { - .Total_Endpoint = NUM_ENDPTS, - .Total_Configuration = 1 -}; - -#define MAX_PACKET_SIZE 0x40 /* 64B, maximum for USB FS Devices */ -DEVICE_PROP Device_Property = { - .Init = usbInit, - .Reset = usbReset, - .Process_Status_IN = NOP_Process, - .Process_Status_OUT = NOP_Process, - .Class_Data_Setup = usbDataSetup, - .Class_NoData_Setup = usbNoDataSetup, - .Class_Get_Interface_Setting = usbGetInterfaceSetting, - .GetDeviceDescriptor = usbGetDeviceDescriptor, - .GetConfigDescriptor = usbGetConfigDescriptor, - .GetStringDescriptor = usbGetStringDescriptor, - .RxEP_buffer = NULL, - .MaxPacketSize = MAX_PACKET_SIZE -}; - -USER_STANDARD_REQUESTS User_Standard_Requests = { - .User_GetConfiguration = NOP_Process, - .User_SetConfiguration = usbSetConfiguration, - .User_GetInterface = NOP_Process, - .User_SetInterface = NOP_Process, - .User_GetStatus = NOP_Process, - .User_ClearFeature = NOP_Process, - .User_SetEndPointFeature = NOP_Process, - .User_SetDeviceFeature = NOP_Process, - .User_SetDeviceAddress = usbSetDeviceAddress -}; - -/* - * CDC ACM interface - */ - -void usb_cdcacm_enable(gpio_dev *disc_dev, uint8 disc_bit) { - /* Present ourselves to the host */ - gpio_set_mode(disc_dev, disc_bit, GPIO_OUTPUT_PP); - gpio_write_bit(disc_dev, disc_bit, 0); // presents us to the host - - /* initialize USB peripheral */ - usb_init_usblib(USBLIB, ep_int_in, ep_int_out); -} - -void usb_cdcacm_disable(gpio_dev *disc_dev, uint8 disc_bit) { - // These are just guesses about how to do this, but it seems to work. - // TODO: verify this with USB spec - nvic_irq_disable(NVIC_USB_LP_CAN_RX0); - gpio_write_bit(disc_dev, disc_bit, 1); -} - -void usb_cdcacm_putc(char ch) { - while (!usb_cdcacm_tx((uint8*)&ch, 1)) - ; -} - -/* This function is non-blocking. - * - * It copies data from a usercode buffer into the USB peripheral TX - * buffer and return the number placed in that buffer. - */ -uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) { - /* Last transmission hasn't finished, abort */ - if (countTx) { - return 0; - } - - // We can only put VCOM_TX_EPSIZE bytes in the buffer - /* FIXME then why are we only copying half as many? */ - if (len > VCOM_TX_EPSIZE / 2) { - len = VCOM_TX_EPSIZE / 2; - } - - // Try to load some bytes if we can - if (len) { - usb_copy_to_pma(buf, len, VCOM_TX_ADDR); - usb_set_ep_tx_count(VCOM_TX_ENDP, len); - countTx += len; - usb_set_ep_tx_stat(VCOM_TX_ENDP, USB_EP_STAT_TX_VALID); - } - - return len; -} - -/* returns the number of available bytes are in the recv FIFO */ -uint32 usb_cdcacm_data_available(void) { - return newBytes; -} - -uint16 usb_cdcacm_get_pending() { - return countTx; -} - -/* Nonblocking byte receive. - * - * Copies up to len bytes from our private data buffer (*NOT* the PMA) - * into buf and deq's the FIFO. */ -uint32 usb_cdcacm_rx(uint8* buf, uint32 len) { - static int offset = 0; - int i; - - if (len > newBytes) { - len = newBytes; - } - - for (i = 0; i < len; i++) { - buf[i] = vcomBufferRx[i + offset]; - } - - newBytes -= len; - offset += len; - - /* Re-enable the RX endpoint, which we had set to receive 0 bytes */ - if (newBytes == 0) { - usb_set_ep_rx_count(VCOM_RX_ENDP, VCOM_RX_EPSIZE); - usb_set_ep_rx_stat(VCOM_RX_ENDP, USB_EP_STAT_RX_VALID); - offset = 0; - } - - return len; -} - -uint8 usb_cdcacm_get_dtr() { - return ((line_dtr_rts & CONTROL_LINE_DTR) != 0); -} - -uint8 usb_cdcacm_get_rts() { - return ((line_dtr_rts & CONTROL_LINE_RTS) != 0); -} - -/* - * Callbacks - */ - -static void vcomDataTxCb(void) { - /* assumes tx transactions are atomic 64 bytes (nearly certain they are) */ - countTx = 0; -} - -#define EXC_RETURN 0xFFFFFFF9 -#define DEFAULT_CPSR 0x61000000 -static void vcomDataRxCb(void) { - /* FIXME this is mad buggy */ - - /* setEPRxCount on the previous cycle should garuntee - we havnt received more bytes than we can fit */ - newBytes = usb_get_ep_rx_count(VCOM_RX_ENDP); - usb_set_ep_rx_stat(VCOM_RX_ENDP, USB_EP_STAT_RX_NAK); - - /* magic number, {0x31, 0x45, 0x41, 0x46} is "1EAF" */ - uint8 chkBuf[4]; - uint8 cmpBuf[4] = {0x31, 0x45, 0x41, 0x46}; - if (reset_state == DTR_NEGEDGE) { - reset_state = DTR_LOW; - - if (newBytes >= 4) { - unsigned int target = (unsigned int)wait_reset | 0x1; - - usb_copy_from_pma(chkBuf, 4, VCOM_RX_ADDR); - - int i; - USB_Bool cmpMatch = TRUE; - for (i = 0; i < 4; i++) { - if (chkBuf[i] != cmpBuf[i]) { - cmpMatch = FALSE; - } - } - - if (cmpMatch) { - asm volatile("mov r0, %[stack_top] \n\t" // Reset stack - "mov sp, r0 \n\t" - "mov r0, #1 \n\t" - "mov r1, %[target_addr] \n\t" - "mov r2, %[cpsr] \n\t" - "push {r2} \n\t" // Fake xPSR - "push {r1} \n\t" // PC target addr - "push {r0} \n\t" // Fake LR - "push {r0} \n\t" // Fake R12 - "push {r0} \n\t" // Fake R3 - "push {r0} \n\t" // Fake R2 - "push {r0} \n\t" // Fake R1 - "push {r0} \n\t" // Fake R0 - "mov lr, %[exc_return] \n\t" - "bx lr" - : - : [stack_top] "r" (STACK_TOP), - [target_addr] "r" (target), - [exc_return] "r" (EXC_RETURN), - [cpsr] "r" (DEFAULT_CPSR) - : "r0", "r1", "r2"); - /* should never get here */ - } - } - } - - usb_copy_from_pma(vcomBufferRx, newBytes, VCOM_RX_ADDR); -} - -static uint8* vcomGetSetLineCoding(uint16 length) { - if (length == 0) { - pInformation->Ctrl_Info.Usb_wLength = sizeof(USB_Line_Coding); - } - return (uint8*)&line_coding; -} - -static void usbInit(void) { - pInformation->Current_Configuration = 0; - - USB_BASE->CNTR = USB_CNTR_FRES; - - USBLIB->irq_mask = 0; - USB_BASE->CNTR = USBLIB->irq_mask; - USB_BASE->ISTR = 0; - USBLIB->irq_mask = USB_CNTR_RESETM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; - USB_BASE->CNTR = USBLIB->irq_mask; - - USB_BASE->ISTR = 0; - USBLIB->irq_mask = USB_ISR_MSK; - USB_BASE->CNTR = USBLIB->irq_mask; - - nvic_irq_enable(NVIC_USB_LP_CAN_RX0); - USBLIB->state = USB_UNCONNECTED; -} - -/* choose addresses to give endpoints the max 64 byte buffers */ -#define BTABLE_ADDRESS 0x00 -static void usbReset(void) { - pInformation->Current_Configuration = 0; - - /* current feature is current bmAttributes */ - pInformation->Current_Feature = (USB_CONFIG_ATTR_BUSPOWERED | - USB_CONFIG_ATTR_SELF_POWERED); - - USB_BASE->BTABLE = BTABLE_ADDRESS; - - /* setup control endpoint 0 */ - usb_set_ep_type(USB_EP0, USB_EP_EP_TYPE_CONTROL); - usb_set_ep_tx_stat(USB_EP0, USB_EP_STAT_TX_STALL); - usb_set_ep_rx_addr(USB_EP0, VCOM_CTRL_RX_ADDR); - usb_set_ep_tx_addr(USB_EP0, VCOM_CTRL_TX_ADDR); - usb_clear_status_out(USB_EP0); - - usb_set_ep_rx_count(USB_EP0, pProperty->MaxPacketSize); - usb_set_ep_rx_stat(USB_EP0, USB_EP_STAT_RX_VALID); - - /* setup management endpoint 1 */ - usb_set_ep_type(VCOM_NOTIFICATION_ENDP, USB_EP_EP_TYPE_INTERRUPT); - usb_set_ep_tx_addr(VCOM_NOTIFICATION_ENDP, VCOM_NOTIFICATION_ADDR); - usb_set_ep_tx_stat(VCOM_NOTIFICATION_ENDP, USB_EP_STAT_TX_NAK); - usb_set_ep_rx_stat(VCOM_NOTIFICATION_ENDP, USB_EP_STAT_RX_DISABLED); - - /* TODO figure out differences in style between RX/TX EP setup */ - - /* set up data endpoint OUT (RX) */ - usb_set_ep_type(VCOM_RX_ENDP, USB_EP_EP_TYPE_BULK); - usb_set_ep_rx_addr(VCOM_RX_ENDP, 0x110); - usb_set_ep_rx_count(VCOM_RX_ENDP, 64); - usb_set_ep_rx_stat(VCOM_RX_ENDP, USB_EP_STAT_RX_VALID); - - /* set up data endpoint IN (TX) */ - usb_set_ep_type(VCOM_TX_ENDP, USB_EP_EP_TYPE_BULK); - usb_set_ep_tx_addr(VCOM_TX_ENDP, VCOM_TX_ADDR); - usb_set_ep_tx_stat(VCOM_TX_ENDP, USB_EP_STAT_TX_NAK); - usb_set_ep_rx_stat(VCOM_TX_ENDP, USB_EP_STAT_RX_DISABLED); - - USBLIB->state = USB_ATTACHED; - SetDeviceAddress(0); - - /* reset the rx fifo */ - recvBufIn = 0; - recvBufOut = 0; - maxNewBytes = VCOM_RX_EPSIZE; - countTx = 0; -} - -static RESULT usbDataSetup(uint8 request) { - uint8 *(*CopyRoutine)(uint16); - CopyRoutine = NULL; - - if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT)) { - switch (request) { - case (GET_LINE_CODING): - CopyRoutine = vcomGetSetLineCoding; - last_request = GET_LINE_CODING; - break; - case (SET_LINE_CODING): - CopyRoutine = vcomGetSetLineCoding; - last_request = SET_LINE_CODING; - break; - default: - break; - } - } - - if (CopyRoutine == NULL) { - return USB_UNSUPPORT; - } - - pInformation->Ctrl_Info.CopyData = CopyRoutine; - pInformation->Ctrl_Info.Usb_wOffset = 0; - (*CopyRoutine)(0); - return USB_SUCCESS; -} - -static RESULT usbNoDataSetup(uint8 request) { - uint8 new_signal; - - /* we support set com feature but dont handle it */ - if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT)) { - - switch (request) { - case (SET_COMM_FEATURE): - return USB_SUCCESS; - case (SET_CONTROL_LINE_STATE): - /* to reset the board, pull both dtr and rts low - then pulse dtr by itself */ - new_signal = (pInformation->USBwValues.bw.bb0 & - (CONTROL_LINE_DTR | CONTROL_LINE_RTS)); - line_dtr_rts = new_signal & 0x03; - - switch (reset_state) { - /* no default, covered enum */ - case DTR_UNSET: - if ((new_signal & CONTROL_LINE_DTR) == 0 ) { - reset_state = DTR_LOW; - } else { - reset_state = DTR_HIGH; - } - break; - - case DTR_HIGH: - if ((new_signal & CONTROL_LINE_DTR) == 0 ) { - reset_state = DTR_NEGEDGE; - } else { - reset_state = DTR_HIGH; - } - break; - - case DTR_NEGEDGE: - if ((new_signal & CONTROL_LINE_DTR) == 0 ) { - reset_state = DTR_LOW; - } else { - reset_state = DTR_HIGH; - } - break; - - case DTR_LOW: - if ((new_signal & CONTROL_LINE_DTR) == 0 ) { - reset_state = DTR_LOW; - } else { - reset_state = DTR_HIGH; - } - break; - } - - return USB_SUCCESS; - } - } - return USB_UNSUPPORT; -} - -static RESULT usbGetInterfaceSetting(uint8 interface, uint8 alt_setting) { - if (alt_setting > 0) { - return USB_UNSUPPORT; - } else if (interface > 1) { - return USB_UNSUPPORT; - } - - return USB_SUCCESS; -} - -static uint8* usbGetDeviceDescriptor(uint16 length) { - return Standard_GetDescriptorData(length, &Device_Descriptor); -} - -static uint8* usbGetConfigDescriptor(uint16 length) { - return Standard_GetDescriptorData(length, &Config_Descriptor); -} - -static uint8* usbGetStringDescriptor(uint16 length) { - uint8 wValue0 = pInformation->USBwValue0; - - if (wValue0 > 2) { - return NULL; - } - return Standard_GetDescriptorData(length, &String_Descriptor[wValue0]); -} - -static void usbSetConfiguration(void) { - if (pInformation->Current_Configuration != 0) { - USBLIB->state = USB_CONFIGURED; - } -} - -static void usbSetDeviceAddress(void) { - USBLIB->state = USB_ADDRESSED; -} - -#define RESET_DELAY 100000 -static void wait_reset(void) { - delay_us(RESET_DELAY); - nvic_sys_reset(); -} diff --git a/libmaple/usb/usb_descriptors.h b/libmaple/usb/usb_descriptors.h deleted file mode 100644 index 9bcb2b6..0000000 --- a/libmaple/usb/usb_descriptors.h +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -#ifndef _USB_DESCRIPTORS_H_ -#define _USB_DESCRIPTORS_H_ - -#include - -#define USB_DESCRIPTOR_TYPE_DEVICE 0x01 -#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02 -#define USB_DESCRIPTOR_TYPE_STRING 0x03 -#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04 -#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05 - -#define USB_DEVICE_CLASS_CDC 0x02 -#define USB_DEVICE_SUBCLASS_CDC 0x00 -#define USB_INTERFACE_CLASS_CDC 0x02 -/* CDC Abstract Control Model */ -#define USB_INTERFACE_SUBCLASS_CDC_ACM 0x02 -#define USB_INTERFACE_CLASS_DIC 0x0A - -#define USB_CONFIG_ATTR_BUSPOWERED 0b10000000 -#define USB_CONFIG_ATTR_SELF_POWERED 0b11000000 - -#define EP_TYPE_INTERRUPT 0x03 -#define EP_TYPE_BULK 0x02 - -#define USB_DESCRIPTOR_ENDPOINT_IN 0x80 -#define USB_DESCRIPTOR_ENDPOINT_OUT 0x00 - -#define USB_DESCRIPTOR_STRING_LEN(x) (2 + (x << 1)) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define USB_DESCRIPTOR_STRING(len) \ - struct { \ - uint8 bLength; \ - uint8 bDescriptorType; \ - uint16 bString[len]; \ - } __packed - -#define CDC_FUNCTIONAL_DESCRIPTOR_SIZE(DataSize) (3 + DataSize) -#define CDC_FUNCTIONAL_DESCRIPTOR(DataSize) \ - struct { \ - uint8 bLength; \ - uint8 bDescriptorType; \ - uint8 SubType; \ - uint8 Data[DataSize]; \ - } __packed - -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint16 bcdUSB; - uint8 bDeviceClass; - uint8 bDeviceSubClass; - uint8 bDeviceProtocol; - uint8 bMaxPacketSize0; - uint16 idVendor; - uint16 idProduct; - uint16 bcdDevice; - uint8 iManufacturer; - uint8 iProduct; - uint8 iSerialNumber; - uint8 bNumConfigurations; -} __packed USB_Descriptor_Device; - -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint16 wTotalLength; - uint8 bNumInterfaces; - uint8 bConfigurationValue; - uint8 iConfiguration; - uint8 bmAttributes; - uint8 bMaxPower; -} __packed USB_Descriptor_Config_Header; - -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 bInterfaceNumber; - uint8 bAlternateSetting; - uint8 bNumEndpoints; - uint8 bInterfaceClass; - uint8 bInterfaceSubClass; - uint8 bInterfaceProtocol; - uint8 iInterface; -} __packed USB_Descriptor_Interface; - -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 bEndpointAddress; - uint8 bmAttributes; - uint16 wMaxPacketSize; - uint8 bInterval; -} __packed USB_Descriptor_Endpoint; - -typedef struct { - USB_Descriptor_Config_Header Config_Header; - USB_Descriptor_Interface CCI_Interface; - CDC_FUNCTIONAL_DESCRIPTOR(2) CDC_Functional_IntHeader; - CDC_FUNCTIONAL_DESCRIPTOR(2) CDC_Functional_CallManagement; - CDC_FUNCTIONAL_DESCRIPTOR(1) CDC_Functional_ACM; - CDC_FUNCTIONAL_DESCRIPTOR(2) CDC_Functional_Union; - USB_Descriptor_Endpoint ManagementEndpoint; - USB_Descriptor_Interface DCI_Interface; - USB_Descriptor_Endpoint DataOutEndpoint; - USB_Descriptor_Endpoint DataInEndpoint; -} __packed USB_Descriptor_Config; - -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint16 bString[]; -} USB_Descriptor_String; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/libmaple/usb/usb_lib_globals.h b/libmaple/usb/usb_lib_globals.h deleted file mode 100644 index 1cd2754..0000000 --- a/libmaple/usb/usb_lib_globals.h +++ /dev/null @@ -1,55 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -#ifndef _USB_LIB_GLOBALS_H_ -#define _USB_LIB_GLOBALS_H_ - -/* usb_lib headers */ -#include "usb_type.h" -#include "usb_core.h" - -#ifdef __cplusplus -extern "C" { -#endif - -extern USER_STANDARD_REQUESTS User_Standard_Requests; -extern USER_STANDARD_REQUESTS *pUser_Standard_Requests; - -extern DEVICE_PROP Device_Property; -extern DEVICE_PROP *pProperty; - -extern DEVICE_INFO Device_Info; -extern DEVICE_INFO *pInformation; - -extern DEVICE Device_Table; -extern u16 SaveRState; -extern u16 SaveTState; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libmaple/usb/usb_reg_map.c b/libmaple/usb/usb_reg_map.c deleted file mode 100644 index 75562e1..0000000 --- a/libmaple/usb/usb_reg_map.c +++ /dev/null @@ -1,79 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -#include "usb_reg_map.h" - -/* TODO these could use some improvement; they're fairly - * straightforward ports of the analogous ST code. The PMA blit - * routines in particular are obvious targets for performance - * measurement and tuning. */ - -void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset) { - uint16 *dst = (uint16*)usb_pma_ptr(pma_offset); - uint16 n = len >> 1; - uint16 i; - for (i = 0; i < n; i++) { - *dst = (uint16)(*buf) | *(buf + 1) << 8; - buf += 2; - dst += 2; - } - if (len & 1) { - *dst = *buf; - } -} - -void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset) { - uint32 *src = (uint32*)usb_pma_ptr(pma_offset); - uint16 *dst = (uint16*)buf; - uint16 n = len >> 1; - uint16 i; - for (i = 0; i < n; i++) { - *dst++ = *src++; - } - if (len & 1) { - *dst = *src & 0xFF; - } -} - -void usb_set_ep_rx_count(uint8 ep, uint16 count) { - uint32 *rxc = usb_ep_rx_count_ptr(ep); - uint16 nblocks; - if (count > 62) { - /* use 32-byte memory block size */ - nblocks = count >> 5; - if ((count & 0x1F) == 0) { - nblocks--; - } - *rxc = (nblocks << 10) | 0x8000; - } else { - /* use 2-byte memory block size */ - nblocks = count >> 1; - if ((count & 0x1) != 0) { - nblocks++; - } - *rxc = nblocks << 10; - } -} diff --git a/libmaple/usb/usb_reg_map.h b/libmaple/usb/usb_reg_map.h deleted file mode 100644 index ce80842..0000000 --- a/libmaple/usb/usb_reg_map.h +++ /dev/null @@ -1,433 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 LeafLabs, LLC. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -#include -#include - -#ifndef _USB_REG_MAP_H_ -#define _USB_REG_MAP_H_ - -/* TODO: - * - Pick one of "endp", "ep" "endpt" - */ - -/* - * Register map and base pointer - */ - -#define USB_NR_EP_REGS 8 - -/** USB register map type */ -typedef struct usb_reg_map { - __io uint32 EP[USB_NR_EP_REGS]; /**< Endpoint registers */ - const uint32 RESERVED[8]; /**< Reserved */ - __io uint32 CNTR; /**< Control register */ - __io uint32 ISTR; /**< Interrupt status register */ - __io uint32 FNR; /**< Frame number register */ - __io uint32 DADDR; /**< Device address */ - __io uint32 BTABLE; /**< @brief Buffer table address - * - * Address offset within the USB - * packet memory area which points - * to the base of the buffer - * descriptor table. Must be - * aligned to an 8 byte boundary. - */ -} usb_reg_map; - -/** USB register map base pointer */ -#define USB_BASE ((struct usb_reg_map*)0x40005C00) - -/* - * Register bit definitions - */ - -/* Endpoint registers (USB_EPnR) */ - -#define USB_EP_CTR_RX_BIT 15 -#define USB_EP_DTOG_RX_BIT 14 -#define USB_EP_SETUP_BIT 11 -#define USB_EP_EP_KIND_BIT 8 -#define USB_EP_CTR_TX_BIT 7 -#define USB_EP_DTOG_TX_BIT 6 - -#define USB_EP_CTR_RX BIT(USB_EP_CTR_RX_BIT) -#define USB_EP_DTOG_RX BIT(USB_EP_DTOG_RX_BIT) -#define USB_EP_STAT_RX (0x3 << 12) -#define USB_EP_STAT_RX_DISABLED (0x0 << 12) -#define USB_EP_STAT_RX_STALL (0x1 << 12) -#define USB_EP_STAT_RX_NAK (0x2 << 12) -#define USB_EP_STAT_RX_VALID (0x3 << 12) -#define USB_EP_SETUP BIT(USB_EP_SETUP_BIT) -#define USB_EP_EP_TYPE (0x3 << 9) -#define USB_EP_EP_TYPE_BULK (0x0 << 9) -#define USB_EP_EP_TYPE_CONTROL (0x1 << 9) -#define USB_EP_EP_TYPE_ISO (0x2 << 9) -#define USB_EP_EP_TYPE_INTERRUPT (0x3 << 9) -#define USB_EP_EP_KIND BIT(USB_EP_EP_KIND_BIT) -#define USB_EP_CTR_TX BIT(USB_EP_CTR_TX_BIT) -#define USB_EP_DTOG_TX BIT(USB_EP_DTOG_TX_BIT) -#define USB_EP_STAT_TX (0x3 << 4) -#define USB_EP_STAT_TX_DISABLED (0x0 << 4) -#define USB_EP_STAT_TX_STALL (0x1 << 4) -#define USB_EP_STAT_TX_NAK (0x2 << 4) -#define USB_EP_STAT_TX_VALID (0x3 << 4) -#define USB_EP_EA 0xF - -/* Control register (USB_CNTR) */ - -#define USB_CNTR_CTRM_BIT 15 -#define USB_CNTR_PMAOVERM_BIT 14 -#define USB_CNTR_ERRM_BIT 13 -#define USB_CNTR_WKUPM_BIT 12 -#define USB_CNTR_SUSPM_BIT 11 -#define USB_CNTR_RESETM_BIT 10 -#define USB_CNTR_SOFM_BIT 9 -#define USB_CNTR_ESOFM_BIT 8 -#define USB_CNTR_RESUME_BIT 4 -#define USB_CNTR_FSUSP_BIT 3 -#define USB_CNTR_LP_MODE_BIT 2 -#define USB_CNTR_PDWN_BIT 1 -#define USB_CNTR_FRES_BIT 0 - -#define USB_CNTR_CTRM BIT(USB_CNTR_CTRM_BIT) -#define USB_CNTR_PMAOVERM BIT(USB_CNTR_PMAOVERM_BIT) -#define USB_CNTR_ERRM BIT(USB_CNTR_ERRM_BIT) -#define USB_CNTR_WKUPM BIT(USB_CNTR_WKUPM_BIT) -#define USB_CNTR_SUSPM BIT(USB_CNTR_SUSPM_BIT) -#define USB_CNTR_RESETM BIT(USB_CNTR_RESETM_BIT) -#define USB_CNTR_SOFM BIT(USB_CNTR_SOFM_BIT) -#define USB_CNTR_ESOFM BIT(USB_CNTR_ESOFM_BIT) -#define USB_CNTR_RESUME BIT(USB_CNTR_RESUME_BIT) -#define USB_CNTR_FSUSP BIT(USB_CNTR_FSUSP_BIT) -#define USB_CNTR_LP_MODE BIT(USB_CNTR_LP_MODE_BIT) -#define USB_CNTR_PDWN BIT(USB_CNTR_PDWN_BIT) -#define USB_CNTR_FRES BIT(USB_CNTR_FRES_BIT) - -/* Interrupt status register (USB_ISTR) */ - -#define USB_ISTR_CTR_BIT 15 -#define USB_ISTR_PMAOVR_BIT 14 -#define USB_ISTR_ERR_BIT 13 -#define USB_ISTR_WKUP_BIT 12 -#define USB_ISTR_SUSP_BIT 11 -#define USB_ISTR_RESET_BIT 10 -#define USB_ISTR_SOF_BIT 9 -#define USB_ISTR_ESOF_BIT 8 -#define USB_ISTR_DIR_BIT 4 - -#define USB_ISTR_CTR BIT(USB_ISTR_CTR_BIT) -#define USB_ISTR_PMAOVR BIT(USB_ISTR_PMAOVR_BIT) -#define USB_ISTR_ERR BIT(USB_ISTR_ERR_BIT) -#define USB_ISTR_WKUP BIT(USB_ISTR_WKUP_BIT) -#define USB_ISTR_SUSP BIT(USB_ISTR_SUSP_BIT) -#define USB_ISTR_RESET BIT(USB_ISTR_RESET_BIT) -#define USB_ISTR_SOF BIT(USB_ISTR_SOF_BIT) -#define USB_ISTR_ESOF BIT(USB_ISTR_ESOF_BIT) -#define USB_ISTR_DIR BIT(USB_ISTR_DIR_BIT) -#define USB_ISTR_EP_ID 0xF - -/* Frame number register (USB_FNR) */ - -#define USB_FNR_RXDP_BIT 15 -#define USB_FNR_RXDM_BIT 14 -#define USB_FNR_LCK_BIT 13 - -#define USB_FNR_RXDP BIT(USB_FNR_RXDP_BIT) -#define USB_FNR_RXDM BIT(USB_FNR_RXDM_BIT) -#define USB_FNR_LCK BIT(USB_FNR_LCK_BIT) -#define USB_FNR_LSOF (0x3 << 11) -#define USB_FNR_FN 0x7FF - -/* Device address (USB_DADDR) */ - -#define USB_DADDR_EF_BIT 7 -#define USB_DADDR_ADD6_BIT 6 -#define USB_DADDR_ADD5_BIT 5 -#define USB_DADDR_ADD4_BIT 4 -#define USB_DADDR_ADD3_BIT 3 -#define USB_DADDR_ADD2_BIT 2 -#define USB_DADDR_ADD1_BIT 1 -#define USB_DADDR_ADD0_BIT 0 - -#define USB_DADDR_EF BIT(USB_DADDR_EF_BIT) -#define USB_DADDR_ADD6 BIT(USB_DADDR_ADD6_BIT) -#define USB_DADDR_ADD5 BIT(USB_DADDR_ADD5_BIT) -#define USB_DADDR_ADD4 BIT(USB_DADDR_ADD4_BIT) -#define USB_DADDR_ADD3 BIT(USB_DADDR_ADD3_BIT) -#define USB_DADDR_ADD2 BIT(USB_DADDR_ADD2_BIT) -#define USB_DADDR_ADD1 BIT(USB_DADDR_ADD1_BIT) -#define USB_DADDR_ADD0 BIT(USB_DADDR_ADD0_BIT) - -/* Buffer table address (USB_BTABLE) */ - -#define USB_BTABLE_BTABLE (0x1FFF << 3) - -/* - * Register convenience routines - */ - -#define __EP_CTR_NOP (USB_EP_CTR_RX | USB_EP_CTR_TX) -#define __EP_NONTOGGLE (USB_EP_CTR_RX | USB_EP_SETUP | \ - USB_EP_EP_TYPE | USB_EP_EP_KIND | \ - USB_EP_CTR_TX | USB_EP_EA) - -static inline void usb_clear_ctr_rx(uint8 ep) { - uint32 epr = USB_BASE->EP[ep]; - USB_BASE->EP[ep] = epr & ~USB_EP_CTR_RX & __EP_NONTOGGLE; -} - -static inline void usb_clear_ctr_tx(uint8 ep) { - uint32 epr = USB_BASE->EP[ep]; - USB_BASE->EP[ep] = epr & ~USB_EP_CTR_TX & __EP_NONTOGGLE; -} - -static inline void usb_set_ep_rx_stat(uint8 ep, uint32 status) { - uint32 epr = USB_BASE->EP[ep]; - epr &= ~(USB_EP_STAT_TX | USB_EP_DTOG_RX | USB_EP_DTOG_TX); - epr |= __EP_CTR_NOP; - epr ^= status; - USB_BASE->EP[ep] = epr; -} - -static inline void usb_set_ep_tx_stat(uint8 ep, uint32 status) { - uint32 epr = USB_BASE->EP[ep]; - epr &= ~(USB_EP_STAT_RX | USB_EP_DTOG_RX | USB_EP_DTOG_TX); - epr |= __EP_CTR_NOP; - epr ^= status; - USB_BASE->EP[ep] = epr; -} - -static inline void usb_set_ep_type(uint8 ep, uint32 type) { - uint32 epr = USB_BASE->EP[ep]; - epr &= ~USB_EP_EP_TYPE & __EP_NONTOGGLE; - epr |= type; - USB_BASE->EP[ep] = epr; -} - -static inline void usb_set_ep_kind(uint8 ep, uint32 kind) { - uint32 epr = USB_BASE->EP[ep]; - epr &= ~USB_EP_EP_KIND & __EP_NONTOGGLE; - epr |= kind; - USB_BASE->EP[ep] = epr; -} - -static inline void usb_clear_status_out(uint8 ep) { - usb_set_ep_kind(ep, 0); -} - -/* - * Packet memory area (PMA) base pointer - */ - -/** - * @brief USB packet memory area (PMA) base pointer. - * - * The USB PMA is SRAM shared between USB and CAN. The USB peripheral - * accesses this memory directly via the packet buffer interface. */ -#define USB_PMA_BASE ((__io void*)0x40006000) - -/* - * PMA conveniences - */ - -void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset); -void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset); - -static inline void* usb_pma_ptr(uint32 offset) { - return (void*)(USB_PMA_BASE + 2 * offset); -} - -/* - * BTABLE - */ - -/* (Forward-declared) BTABLE entry. - * - * The BTABLE can be viewed as an array of usb_btable_ent values; - * these vary in structure according to the configuration of the - * endpoint. - */ -union usb_btable_ent; - -/* Bidirectional endpoint BTABLE entry */ -typedef struct usb_btable_bidi { - __io uint16 addr_tx; const uint16 PAD1; - __io uint16 count_tx; const uint16 PAD2; - __io uint16 addr_rx; const uint16 PAD3; - __io uint16 count_rx; const uint16 PAD4; -} usb_btable_bidi; - -/* Unidirectional receive-only endpoint BTABLE entry */ -typedef struct usb_btable_uni_rx { - __io uint16 empty1; const uint16 PAD1; - __io uint16 empty2; const uint16 PAD2; - __io uint16 addr_rx; const uint16 PAD3; - __io uint16 count_rx; const uint16 PAD4; -} usb_btable_uni_rx; - -/* Unidirectional transmit-only endpoint BTABLE entry */ -typedef struct usb_btable_uni_tx { - __io uint16 addr_tx; const uint16 PAD1; - __io uint16 count_tx; const uint16 PAD2; - __io uint16 empty1; const uint16 PAD3; - __io uint16 empty2; const uint16 PAD4; -} usb_btable_uni_tx; - -/* Double-buffered transmission endpoint BTABLE entry */ -typedef struct usb_btable_dbl_tx { - __io uint16 addr_tx0; const uint16 PAD1; - __io uint16 count_tx0; const uint16 PAD2; - __io uint16 addr_tx1; const uint16 PAD3; - __io uint16 count_tx1; const uint16 PAD4; -} usb_btable_dbl_tx; - -/* Double-buffered reception endpoint BTABLE entry */ -typedef struct usb_btable_dbl_rx { - __io uint16 addr_rx0; const uint16 PAD1; - __io uint16 count_rx0; const uint16 PAD2; - __io uint16 addr_rx1; const uint16 PAD3; - __io uint16 count_rx1; const uint16 PAD4; -} usb_btable_dbl_rx; - -/* TODO isochronous endpoint entries */ - -/* Definition for above forward-declared BTABLE entry. */ -typedef union usb_btable_ent { - usb_btable_bidi bidi; - usb_btable_uni_rx u_rx; - usb_btable_uni_tx u_tx; - usb_btable_dbl_tx d_tx; - usb_btable_dbl_rx d_rx; -} usb_btable_ent; - -/* - * BTABLE conveniences - */ - -/* TODO (?) Convert usages of the many (and lengthily-named) - * accessors/mutators below to just manipulating usb_btable_entry - * values. */ - -static inline uint32* usb_btable_ptr(uint32 offset) { - return (uint32*)usb_pma_ptr(USB_BASE->BTABLE + offset); -} - -static inline usb_btable_ent *usb_btable(void) { - return (usb_btable_ent*)usb_btable_ptr(0); -} - -/* TX address */ - -static inline uint32* usb_ep_tx_addr_ptr(uint8 ep) { - return usb_btable_ptr(ep * 8); -} - -static inline uint16 usb_get_ep_tx_addr(uint8 ep) { - return (uint16)*usb_ep_tx_addr_ptr(ep); -} - -static inline void usb_set_ep_tx_addr(uint8 ep, uint16 addr) { - uint32 *tx_addr = usb_ep_tx_addr_ptr(ep); - *tx_addr = addr & ~0x1; -} - -/* RX address */ - -static inline uint32* usb_ep_rx_addr_ptr(uint8 ep) { - return usb_btable_ptr(ep * 8 + 4); -} - -static inline uint16 usb_get_ep_rx_addr(uint8 ep) { - return (uint16)*usb_ep_rx_addr_ptr(ep); -} - -static inline void usb_set_ep_rx_addr(uint8 ep, uint16 addr) { - uint32 *rx_addr = usb_ep_rx_addr_ptr(ep); - *rx_addr = addr & ~0x1; -} - -/* TX count (doesn't cover double-buffered and isochronous in) */ - -static inline uint32* usb_ep_tx_count_ptr(uint8 ep) { - return usb_btable_ptr(ep * 8 + 2); -} - -static inline uint16 usb_get_ep_tx_count(uint8 ep) { - return (uint16)*usb_ep_tx_count_ptr(ep); -} - -static inline void usb_set_ep_tx_count(uint8 ep, uint16 count) { - uint32 *txc = usb_ep_tx_count_ptr(ep); - *txc = count; -} - -/* RX count */ - -static inline uint32* usb_ep_rx_count_ptr(uint8 ep) { - return usb_btable_ptr(ep * 8 + 6); -} - -static inline uint16 usb_get_ep_rx_count(uint8 ep) { - return (uint16)*usb_ep_rx_count_ptr(ep) & 0x3FF; -} - -void usb_set_ep_rx_count(uint8 ep, uint16 count); - -/* - * Misc. types - */ - -typedef enum usb_ep { - USB_EP0, - USB_EP1, - USB_EP2, - USB_EP3, - USB_EP4, - USB_EP5, - USB_EP6, - USB_EP7, -} usb_ep; - -typedef enum usb_ep_type { - USB_EP_T_CTL = USB_EP_EP_TYPE_CONTROL, - USB_EP_T_BULK = USB_EP_EP_TYPE_BULK, - USB_EP_T_INT = USB_EP_EP_TYPE_INTERRUPT, - USB_EP_T_ISO = USB_EP_EP_TYPE_ISO -} usb_ep_type; - -typedef enum usb_ep_stat { - USB_EP_ST_RX_DIS = USB_EP_STAT_RX_DISABLED, - USB_EP_ST_RX_STL = USB_EP_STAT_RX_STALL, - USB_EP_ST_RX_NAK = USB_EP_STAT_RX_NAK, - USB_EP_ST_RX_VAL = USB_EP_STAT_RX_VALID, - USB_EP_ST_TX_DIS = USB_EP_STAT_TX_DISABLED, - USB_EP_ST_TX_STL = USB_EP_STAT_TX_STALL, - USB_EP_ST_TX_NAK = USB_EP_STAT_TX_NAK, - USB_EP_ST_TX_VAL = USB_EP_STAT_TX_VALID -} usb_ep_stat; - -#endif diff --git a/support/ld/stm32/series/stm32f1/value/vector_symbols.inc b/support/ld/stm32/series/stm32f1/value/vector_symbols.inc new file mode 100644 index 0000000..f8726f9 --- /dev/null +++ b/support/ld/stm32/series/stm32f1/value/vector_symbols.inc @@ -0,0 +1,78 @@ +EXTERN(__msp_init) +EXTERN(__exc_reset) +EXTERN(__exc_nmi) +EXTERN(__exc_hardfault) +EXTERN(__exc_memmanage) +EXTERN(__exc_busfault) +EXTERN(__exc_usagefault) +EXTERN(__stm32reservedexception7) +EXTERN(__stm32reservedexception8) +EXTERN(__stm32reservedexception9) +EXTERN(__stm32reservedexception10) +EXTERN(__exc_svc) +EXTERN(__exc_debug_monitor) +EXTERN(__stm32reservedexception13) +EXTERN(__exc_pendsv) +EXTERN(__exc_systick) + +EXTERN(__irq_wwdg) +EXTERN(__irq_pvd) +EXTERN(__irq_tamper) +EXTERN(__irq_rtc) +EXTERN(__irq_flash) +EXTERN(__irq_rcc) +EXTERN(__irq_exti0) +EXTERN(__irq_exti1) +EXTERN(__irq_exti2) +EXTERN(__irq_exti3) +EXTERN(__irq_exti4) +EXTERN(__irq_dma1_channel1) +EXTERN(__irq_dma1_channel2) +EXTERN(__irq_dma1_channel3) +EXTERN(__irq_dma1_channel4) +EXTERN(__irq_dma1_channel5) +EXTERN(__irq_dma1_channel6) +EXTERN(__irq_dma1_channel7) +EXTERN(__irq_adc1) +EXTERN(__stm32reservedexception14) +EXTERN(__stm32reservedexception15) +EXTERN(__stm32reservedexception16) +EXTERN(__stm32reservedexception17) +EXTERN(__irq_exti9_5) +EXTERN(__irq_tim1_brk) +EXTERN(__irq_tim1_up) +EXTERN(__irq_tim1_trg_com) +EXTERN(__irq_tim1_cc) +EXTERN(__irq_tim2) +EXTERN(__irq_tim3) +EXTERN(__irq_tim4) +EXTERN(__irq_i2c1_ev) +EXTERN(__irq_i2c1_er) +EXTERN(__irq_i2c2_ev) +EXTERN(__irq_i2c2_er) +EXTERN(__irq_spi1) +EXTERN(__irq_spi2) +EXTERN(__irq_usart1) +EXTERN(__irq_usart2) +EXTERN(__irq_usart3) +EXTERN(__irq_exti15_10) +EXTERN(__irq_rtcalarm) +EXTERN(__irq_cec) +EXTERN(__irq_tim12) +EXTERN(__irq_tim13) +EXTERN(__irq_tim14) +EXTERN(__stm32reservedexception18) +EXTERN(__stm32reservedexception19) +EXTERN(__irq_fsmc) +EXTERN(__stm32reservedexception20) +EXTERN(__irq_tim5) +EXTERN(__irq_spi3) +EXTERN(__irq_uart4) +EXTERN(__irq_uart5) +EXTERN(__irq_tim6) +EXTERN(__irq_tim7) +EXTERN(__irq_dma2_channel1) +EXTERN(__irq_dma2_channel2) +EXTERN(__irq_dma2_channel3) +EXTERN(__irq_dma2_channel4_5) +EXTERN(__irq_dma2_channel5) /* on remap only */ diff --git a/support/make/board-includes/VLDiscovery.mk b/support/make/board-includes/VLDiscovery.mk index 82d1b23..441f078 100644 --- a/support/make/board-includes/VLDiscovery.mk +++ b/support/make/board-includes/VLDiscovery.mk @@ -3,3 +3,4 @@ PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 9 MCU_SERIES := stm32f1 +MCU_F1_LINE := value diff --git a/support/make/board-includes/maple.mk b/support/make/board-includes/maple.mk index d31ad83..4de4bab 100644 --- a/support/make/board-includes/maple.mk +++ b/support/make/board-includes/maple.mk @@ -3,3 +3,4 @@ PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 MCU_SERIES := stm32f1 +MCU_F1_LINE := performance diff --git a/support/make/board-includes/maple_RET6.mk b/support/make/board-includes/maple_RET6.mk index d06f068..104ae08 100644 --- a/support/make/board-includes/maple_RET6.mk +++ b/support/make/board-includes/maple_RET6.mk @@ -3,3 +3,4 @@ PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 MCU_SERIES := stm32f1 +MCU_F1_LINE := performance diff --git a/support/make/board-includes/maple_mini.mk b/support/make/board-includes/maple_mini.mk index 835adc3..70ef506 100644 --- a/support/make/board-includes/maple_mini.mk +++ b/support/make/board-includes/maple_mini.mk @@ -3,3 +3,4 @@ PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOB ERROR_LED_PIN := 1 MCU_SERIES := stm32f1 +MCU_F1_LINE := performance diff --git a/support/make/board-includes/maple_native.mk b/support/make/board-includes/maple_native.mk index 3e88e7b..86746a6 100644 --- a/support/make/board-includes/maple_native.mk +++ b/support/make/board-includes/maple_native.mk @@ -3,3 +3,4 @@ PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 15 MCU_SERIES := stm32f1 +MCU_F1_LINE := performance diff --git a/support/make/board-includes/olimex_stm32_h103.mk b/support/make/board-includes/olimex_stm32_h103.mk index 96d6976..31f2c04 100644 --- a/support/make/board-includes/olimex_stm32_h103.mk +++ b/support/make/board-includes/olimex_stm32_h103.mk @@ -3,3 +3,4 @@ PRODUCT_ID := 0003 ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 12 MCU_SERIES := stm32f1 +MCU_F1_LINE := performance diff --git a/support/make/target-config.mk b/support/make/target-config.mk index 48a33de..e13504d 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -15,9 +15,9 @@ TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ LD_SERIES_PATH := $(LDDIR)/stm32/series/$(MCU_SERIES) ifeq ($(MCU_SERIES), stm32f1) - # Hack: force F1 to performance line; this will need to change if - # you add connectivity etc. line support. - LD_SERIES_PATH := $(LD_SERIES_PATH)/performance +# Due to the Balkanization on F1, we need to specify the line when +# making linker decisions. +LD_SERIES_PATH := $(LD_SERIES_PATH)/$(MCU_F1_LINE) endif LIBMAPLE_MODULE_SERIES := $(LIBMAPLE_PATH)/$(MCU_SERIES) diff --git a/wirish/include/wirish/usb_serial.h b/wirish/include/wirish/usb_serial.h index 81e9e97..f36671b 100644 --- a/wirish/include/wirish/usb_serial.h +++ b/wirish/include/wirish/usb_serial.h @@ -25,13 +25,14 @@ *****************************************************************************/ /** - * @brief Wirish virtual serial port + * @brief Wirish USB virtual serial port (SerialUSB). */ #ifndef _WIRISH_USB_SERIAL_H_ #define _WIRISH_USB_SERIAL_H_ #include +#include /** * @brief Virtual serial terminal. @@ -58,7 +59,9 @@ public: uint8 pending(); }; +#if BOARD_HAVE_SERIALUSB extern USBSerial SerialUSB; +#endif #endif diff --git a/wirish/rules.mk b/wirish/rules.mk index 147857a..6d96cbe 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -26,6 +26,9 @@ cppSRCS_$(d) += HardwareSerial.cpp cppSRCS_$(d) += HardwareTimer.cpp cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += pwm.cpp +ifeq ($(MCU_SERIES), stm32f1) +cppSRCS_$(d) += usb_serial.cpp # HACK: this is currently STM32F1 only. +endif cppSRCS_$(d) += wirish_analog.cpp cppSRCS_$(d) += wirish_digital.cpp cppSRCS_$(d) += wirish_math.cpp @@ -36,7 +39,6 @@ cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately for F2 and put them back in: # HardwareSPI.cpp -# usb_serial.cpp # ext_interrupts.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index 423e5ec..1dec579 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -38,9 +38,9 @@ #include #include -#include -#include +#include +#include // Allow boards to provide a PLL multiplier. This is useful for // e.g. STM32F100 value line MCUs, which use slower multipliers. @@ -80,10 +80,8 @@ namespace wirish { } void board_setup_usb(void) { -#if 0 -# if STM32_HAVE_USB - usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); -# endif +#if BOARD_HAVE_SERIALUSB + SerialUSB.begin(); #endif } } diff --git a/wirish/usb_serial.cpp b/wirish/usb_serial.cpp index 388c739..a01900f 100644 --- a/wirish/usb_serial.cpp +++ b/wirish/usb_serial.cpp @@ -40,14 +40,21 @@ #define USB_TIMEOUT 50 USBSerial::USBSerial(void) { +#if !BOARD_HAVE_SERIALUSB + ASSERT(0); +#endif } void USBSerial::begin(void) { +#if BOARD_HAVE_SERIALUSB usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); +#endif } void USBSerial::end(void) { +#if BOARD_HAVE_SERIALUSB usb_cdcacm_disable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT); +#endif } void USBSerial::write(uint8 ch) { @@ -117,4 +124,6 @@ uint8 USBSerial::getRTS(void) { return usb_cdcacm_get_rts(); } +#if BOARD_HAVE_SERIALUSB USBSerial SerialUSB; +#endif -- cgit v1.2.3 From 9cb33ac2d3829715e352e4550493f414b2b4c003 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 06:19:00 -0400 Subject: Add ISRs and vector table for F1 value line. Now libmaple/stm32f1/rules.mk tries to pull in ISRs and a vector table on a per-line basis. Move isrs_performance.S and vector_table_performance.S to (new) libmaple/stm32f1/performance, and rename them. Add corresponding files for value line under (new) libmaple/stm32f1/value. This helps clean up some performance-line-isms, and allows implementing e.g. the CEC interrupt, which is used by something else on performance line. Untested (I don't have access to a value line MCU); hopefully this works. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/isrs_performance.S | 261 --------------------------- libmaple/stm32f1/performance/isrs.S | 261 +++++++++++++++++++++++++++ libmaple/stm32f1/performance/vector_table.S | 116 ++++++++++++ libmaple/stm32f1/rules.mk | 7 +- libmaple/stm32f1/value/isrs.S | 270 ++++++++++++++++++++++++++++ libmaple/stm32f1/value/vector_table.S | 116 ++++++++++++ libmaple/stm32f1/vector_table_performance.S | 116 ------------ 7 files changed, 768 insertions(+), 379 deletions(-) delete mode 100644 libmaple/stm32f1/isrs_performance.S create mode 100644 libmaple/stm32f1/performance/isrs.S create mode 100644 libmaple/stm32f1/performance/vector_table.S create mode 100644 libmaple/stm32f1/value/isrs.S create mode 100644 libmaple/stm32f1/value/vector_table.S delete mode 100644 libmaple/stm32f1/vector_table_performance.S diff --git a/libmaple/stm32f1/isrs_performance.S b/libmaple/stm32f1/isrs_performance.S deleted file mode 100644 index af39198..0000000 --- a/libmaple/stm32f1/isrs_performance.S +++ /dev/null @@ -1,261 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/* STM32F1 ISR weak declarations */ - - .thumb - -/* Default handler for all non-overridden interrupts and exceptions */ - .globl __default_handler - .type __default_handler, %function - -__default_handler: - b . - - .weak __exc_nmi - .globl __exc_nmi - .set __exc_nmi, __default_handler - .weak __exc_hardfault - .globl __exc_hardfault - .set __exc_hardfault, __default_handler - .weak __exc_memmanage - .globl __exc_memmanage - .set __exc_memmanage, __default_handler - .weak __exc_busfault - .globl __exc_busfault - .set __exc_busfault, __default_handler - .weak __exc_usagefault - .globl __exc_usagefault - .set __exc_usagefault, __default_handler - .weak __stm32reservedexception7 - .globl __stm32reservedexception7 - .set __stm32reservedexception7, __default_handler - .weak __stm32reservedexception8 - .globl __stm32reservedexception8 - .set __stm32reservedexception8, __default_handler - .weak __stm32reservedexception9 - .globl __stm32reservedexception9 - .set __stm32reservedexception9, __default_handler - .weak __stm32reservedexception10 - .globl __stm32reservedexception10 - .set __stm32reservedexception10, __default_handler - .weak __exc_svc - .globl __exc_svc - .set __exc_svc, __default_handler - .weak __exc_debug_monitor - .globl __exc_debug_monitor - .set __exc_debug_monitor, __default_handler - .weak __stm32reservedexception13 - .globl __stm32reservedexception13 - .set __stm32reservedexception13, __default_handler - .weak __exc_pendsv - .globl __exc_pendsv - .set __exc_pendsv, __default_handler - .weak __exc_systick - .globl __exc_systick - .set __exc_systick, __default_handler - .weak __irq_wwdg - .globl __irq_wwdg - .set __irq_wwdg, __default_handler - .weak __irq_pvd - .globl __irq_pvd - .set __irq_pvd, __default_handler - .weak __irq_tamper - .globl __irq_tamper - .set __irq_tamper, __default_handler - .weak __irq_rtc - .globl __irq_rtc - .set __irq_rtc, __default_handler - .weak __irq_flash - .globl __irq_flash - .set __irq_flash, __default_handler - .weak __irq_rcc - .globl __irq_rcc - .set __irq_rcc, __default_handler - .weak __irq_exti0 - .globl __irq_exti0 - .set __irq_exti0, __default_handler - .weak __irq_exti1 - .globl __irq_exti1 - .set __irq_exti1, __default_handler - .weak __irq_exti2 - .globl __irq_exti2 - .set __irq_exti2, __default_handler - .weak __irq_exti3 - .globl __irq_exti3 - .set __irq_exti3, __default_handler - .weak __irq_exti4 - .globl __irq_exti4 - .set __irq_exti4, __default_handler - .weak __irq_dma1_channel1 - .globl __irq_dma1_channel1 - .set __irq_dma1_channel1, __default_handler - .weak __irq_dma1_channel2 - .globl __irq_dma1_channel2 - .set __irq_dma1_channel2, __default_handler - .weak __irq_dma1_channel3 - .globl __irq_dma1_channel3 - .set __irq_dma1_channel3, __default_handler - .weak __irq_dma1_channel4 - .globl __irq_dma1_channel4 - .set __irq_dma1_channel4, __default_handler - .weak __irq_dma1_channel5 - .globl __irq_dma1_channel5 - .set __irq_dma1_channel5, __default_handler - .weak __irq_dma1_channel6 - .globl __irq_dma1_channel6 - .set __irq_dma1_channel6, __default_handler - .weak __irq_dma1_channel7 - .globl __irq_dma1_channel7 - .set __irq_dma1_channel7, __default_handler - .weak __irq_adc - .globl __irq_adc - .set __irq_adc, __default_handler - .weak __irq_usb_hp_can_tx - .globl __irq_usb_hp_can_tx - .set __irq_usb_hp_can_tx, __default_handler - .weak __irq_usb_lp_can_rx0 - .globl __irq_usb_lp_can_rx0 - .set __irq_usb_lp_can_rx0, __default_handler - .weak __irq_can_rx1 - .globl __irq_can_rx1 - .set __irq_can_rx1, __default_handler - .weak __irq_can_sce - .globl __irq_can_sce - .set __irq_can_sce, __default_handler - .weak __irq_exti9_5 - .globl __irq_exti9_5 - .set __irq_exti9_5, __default_handler - .weak __irq_tim1_brk - .globl __irq_tim1_brk - .set __irq_tim1_brk, __default_handler - .weak __irq_tim1_up - .globl __irq_tim1_up - .set __irq_tim1_up, __default_handler - .weak __irq_tim1_trg_com - .globl __irq_tim1_trg_com - .set __irq_tim1_trg_com, __default_handler - .weak __irq_tim1_cc - .globl __irq_tim1_cc - .set __irq_tim1_cc, __default_handler - .weak __irq_tim2 - .globl __irq_tim2 - .set __irq_tim2, __default_handler - .weak __irq_tim3 - .globl __irq_tim3 - .set __irq_tim3, __default_handler - .weak __irq_tim4 - .globl __irq_tim4 - .set __irq_tim4, __default_handler - .weak __irq_i2c1_ev - .globl __irq_i2c1_ev - .set __irq_i2c1_ev, __default_handler - .weak __irq_i2c1_er - .globl __irq_i2c1_er - .set __irq_i2c1_er, __default_handler - .weak __irq_i2c2_ev - .globl __irq_i2c2_ev - .set __irq_i2c2_ev, __default_handler - .weak __irq_i2c2_er - .globl __irq_i2c2_er - .set __irq_i2c2_er, __default_handler - .weak __irq_spi1 - .globl __irq_spi1 - .set __irq_spi1, __default_handler - .weak __irq_spi2 - .globl __irq_spi2 - .set __irq_spi2, __default_handler - .weak __irq_usart1 - .globl __irq_usart1 - .set __irq_usart1, __default_handler - .weak __irq_usart2 - .globl __irq_usart2 - .set __irq_usart2, __default_handler - .weak __irq_usart3 - .globl __irq_usart3 - .set __irq_usart3, __default_handler - .weak __irq_exti15_10 - .globl __irq_exti15_10 - .set __irq_exti15_10, __default_handler - .weak __irq_rtcalarm - .globl __irq_rtcalarm - .set __irq_rtcalarm, __default_handler - .weak __irq_usbwakeup - .globl __irq_usbwakeup - .set __irq_usbwakeup, __default_handler -#if defined (STM32_HIGH_DENSITY) - .weak __irq_tim8_brk - .globl __irq_tim8_brk - .set __irq_tim8_brk, __default_handler - .weak __irq_tim8_up - .globl __irq_tim8_up - .set __irq_tim8_up, __default_handler - .weak __irq_tim8_trg_com - .globl __irq_tim8_trg_com - .set __irq_tim8_trg_com, __default_handler - .weak __irq_tim8_cc - .globl __irq_tim8_cc - .set __irq_tim8_cc, __default_handler - .weak __irq_adc3 - .globl __irq_adc3 - .set __irq_adc3, __default_handler - .weak __irq_fsmc - .globl __irq_fsmc - .set __irq_fsmc, __default_handler - .weak __irq_sdio - .globl __irq_sdio - .set __irq_sdio, __default_handler - .weak __irq_tim5 - .globl __irq_tim5 - .set __irq_tim5, __default_handler - .weak __irq_spi3 - .globl __irq_spi3 - .set __irq_spi3, __default_handler - .weak __irq_uart4 - .globl __irq_uart4 - .set __irq_uart4, __default_handler - .weak __irq_uart5 - .globl __irq_uart5 - .set __irq_uart5, __default_handler - .weak __irq_tim6 - .globl __irq_tim6 - .set __irq_tim6, __default_handler - .weak __irq_tim7 - .globl __irq_tim7 - .set __irq_tim7, __default_handler - .weak __irq_dma2_channel1 - .globl __irq_dma2_channel1 - .set __irq_dma2_channel1, __default_handler - .weak __irq_dma2_channel2 - .globl __irq_dma2_channel2 - .set __irq_dma2_channel2, __default_handler - .weak __irq_dma2_channel3 - .globl __irq_dma2_channel3 - .set __irq_dma2_channel3, __default_handler - .weak __irq_dma2_channel4_5 - .globl __irq_dma2_channel4_5 - .set __irq_dma2_channel4_5, __default_handler -#endif /* STM32_HIGH_DENSITY */ diff --git a/libmaple/stm32f1/performance/isrs.S b/libmaple/stm32f1/performance/isrs.S new file mode 100644 index 0000000..a8f0709 --- /dev/null +++ b/libmaple/stm32f1/performance/isrs.S @@ -0,0 +1,261 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F1 performance line ISR weak declarations */ + + .thumb + +/* Default handler for all non-overridden interrupts and exceptions */ + .globl __default_handler + .type __default_handler, %function + +__default_handler: + b . + + .weak __exc_nmi + .globl __exc_nmi + .set __exc_nmi, __default_handler + .weak __exc_hardfault + .globl __exc_hardfault + .set __exc_hardfault, __default_handler + .weak __exc_memmanage + .globl __exc_memmanage + .set __exc_memmanage, __default_handler + .weak __exc_busfault + .globl __exc_busfault + .set __exc_busfault, __default_handler + .weak __exc_usagefault + .globl __exc_usagefault + .set __exc_usagefault, __default_handler + .weak __stm32reservedexception7 + .globl __stm32reservedexception7 + .set __stm32reservedexception7, __default_handler + .weak __stm32reservedexception8 + .globl __stm32reservedexception8 + .set __stm32reservedexception8, __default_handler + .weak __stm32reservedexception9 + .globl __stm32reservedexception9 + .set __stm32reservedexception9, __default_handler + .weak __stm32reservedexception10 + .globl __stm32reservedexception10 + .set __stm32reservedexception10, __default_handler + .weak __exc_svc + .globl __exc_svc + .set __exc_svc, __default_handler + .weak __exc_debug_monitor + .globl __exc_debug_monitor + .set __exc_debug_monitor, __default_handler + .weak __stm32reservedexception13 + .globl __stm32reservedexception13 + .set __stm32reservedexception13, __default_handler + .weak __exc_pendsv + .globl __exc_pendsv + .set __exc_pendsv, __default_handler + .weak __exc_systick + .globl __exc_systick + .set __exc_systick, __default_handler + .weak __irq_wwdg + .globl __irq_wwdg + .set __irq_wwdg, __default_handler + .weak __irq_pvd + .globl __irq_pvd + .set __irq_pvd, __default_handler + .weak __irq_tamper + .globl __irq_tamper + .set __irq_tamper, __default_handler + .weak __irq_rtc + .globl __irq_rtc + .set __irq_rtc, __default_handler + .weak __irq_flash + .globl __irq_flash + .set __irq_flash, __default_handler + .weak __irq_rcc + .globl __irq_rcc + .set __irq_rcc, __default_handler + .weak __irq_exti0 + .globl __irq_exti0 + .set __irq_exti0, __default_handler + .weak __irq_exti1 + .globl __irq_exti1 + .set __irq_exti1, __default_handler + .weak __irq_exti2 + .globl __irq_exti2 + .set __irq_exti2, __default_handler + .weak __irq_exti3 + .globl __irq_exti3 + .set __irq_exti3, __default_handler + .weak __irq_exti4 + .globl __irq_exti4 + .set __irq_exti4, __default_handler + .weak __irq_dma1_channel1 + .globl __irq_dma1_channel1 + .set __irq_dma1_channel1, __default_handler + .weak __irq_dma1_channel2 + .globl __irq_dma1_channel2 + .set __irq_dma1_channel2, __default_handler + .weak __irq_dma1_channel3 + .globl __irq_dma1_channel3 + .set __irq_dma1_channel3, __default_handler + .weak __irq_dma1_channel4 + .globl __irq_dma1_channel4 + .set __irq_dma1_channel4, __default_handler + .weak __irq_dma1_channel5 + .globl __irq_dma1_channel5 + .set __irq_dma1_channel5, __default_handler + .weak __irq_dma1_channel6 + .globl __irq_dma1_channel6 + .set __irq_dma1_channel6, __default_handler + .weak __irq_dma1_channel7 + .globl __irq_dma1_channel7 + .set __irq_dma1_channel7, __default_handler + .weak __irq_adc + .globl __irq_adc + .set __irq_adc, __default_handler + .weak __irq_usb_hp_can_tx + .globl __irq_usb_hp_can_tx + .set __irq_usb_hp_can_tx, __default_handler + .weak __irq_usb_lp_can_rx0 + .globl __irq_usb_lp_can_rx0 + .set __irq_usb_lp_can_rx0, __default_handler + .weak __irq_can_rx1 + .globl __irq_can_rx1 + .set __irq_can_rx1, __default_handler + .weak __irq_can_sce + .globl __irq_can_sce + .set __irq_can_sce, __default_handler + .weak __irq_exti9_5 + .globl __irq_exti9_5 + .set __irq_exti9_5, __default_handler + .weak __irq_tim1_brk + .globl __irq_tim1_brk + .set __irq_tim1_brk, __default_handler + .weak __irq_tim1_up + .globl __irq_tim1_up + .set __irq_tim1_up, __default_handler + .weak __irq_tim1_trg_com + .globl __irq_tim1_trg_com + .set __irq_tim1_trg_com, __default_handler + .weak __irq_tim1_cc + .globl __irq_tim1_cc + .set __irq_tim1_cc, __default_handler + .weak __irq_tim2 + .globl __irq_tim2 + .set __irq_tim2, __default_handler + .weak __irq_tim3 + .globl __irq_tim3 + .set __irq_tim3, __default_handler + .weak __irq_tim4 + .globl __irq_tim4 + .set __irq_tim4, __default_handler + .weak __irq_i2c1_ev + .globl __irq_i2c1_ev + .set __irq_i2c1_ev, __default_handler + .weak __irq_i2c1_er + .globl __irq_i2c1_er + .set __irq_i2c1_er, __default_handler + .weak __irq_i2c2_ev + .globl __irq_i2c2_ev + .set __irq_i2c2_ev, __default_handler + .weak __irq_i2c2_er + .globl __irq_i2c2_er + .set __irq_i2c2_er, __default_handler + .weak __irq_spi1 + .globl __irq_spi1 + .set __irq_spi1, __default_handler + .weak __irq_spi2 + .globl __irq_spi2 + .set __irq_spi2, __default_handler + .weak __irq_usart1 + .globl __irq_usart1 + .set __irq_usart1, __default_handler + .weak __irq_usart2 + .globl __irq_usart2 + .set __irq_usart2, __default_handler + .weak __irq_usart3 + .globl __irq_usart3 + .set __irq_usart3, __default_handler + .weak __irq_exti15_10 + .globl __irq_exti15_10 + .set __irq_exti15_10, __default_handler + .weak __irq_rtcalarm + .globl __irq_rtcalarm + .set __irq_rtcalarm, __default_handler + .weak __irq_usbwakeup + .globl __irq_usbwakeup + .set __irq_usbwakeup, __default_handler +#if defined (STM32_HIGH_DENSITY) + .weak __irq_tim8_brk + .globl __irq_tim8_brk + .set __irq_tim8_brk, __default_handler + .weak __irq_tim8_up + .globl __irq_tim8_up + .set __irq_tim8_up, __default_handler + .weak __irq_tim8_trg_com + .globl __irq_tim8_trg_com + .set __irq_tim8_trg_com, __default_handler + .weak __irq_tim8_cc + .globl __irq_tim8_cc + .set __irq_tim8_cc, __default_handler + .weak __irq_adc3 + .globl __irq_adc3 + .set __irq_adc3, __default_handler + .weak __irq_fsmc + .globl __irq_fsmc + .set __irq_fsmc, __default_handler + .weak __irq_sdio + .globl __irq_sdio + .set __irq_sdio, __default_handler + .weak __irq_tim5 + .globl __irq_tim5 + .set __irq_tim5, __default_handler + .weak __irq_spi3 + .globl __irq_spi3 + .set __irq_spi3, __default_handler + .weak __irq_uart4 + .globl __irq_uart4 + .set __irq_uart4, __default_handler + .weak __irq_uart5 + .globl __irq_uart5 + .set __irq_uart5, __default_handler + .weak __irq_tim6 + .globl __irq_tim6 + .set __irq_tim6, __default_handler + .weak __irq_tim7 + .globl __irq_tim7 + .set __irq_tim7, __default_handler + .weak __irq_dma2_channel1 + .globl __irq_dma2_channel1 + .set __irq_dma2_channel1, __default_handler + .weak __irq_dma2_channel2 + .globl __irq_dma2_channel2 + .set __irq_dma2_channel2, __default_handler + .weak __irq_dma2_channel3 + .globl __irq_dma2_channel3 + .set __irq_dma2_channel3, __default_handler + .weak __irq_dma2_channel4_5 + .globl __irq_dma2_channel4_5 + .set __irq_dma2_channel4_5, __default_handler +#endif /* STM32_HIGH_DENSITY */ diff --git a/libmaple/stm32f1/performance/vector_table.S b/libmaple/stm32f1/performance/vector_table.S new file mode 100644 index 0000000..b489b94 --- /dev/null +++ b/libmaple/stm32f1/performance/vector_table.S @@ -0,0 +1,116 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F1 performance line vector table */ + + .section ".stm32.interrupt_vector" + + .globl __stm32_vector_table + .type __stm32_vector_table, %object + +__stm32_vector_table: +/* CM3 core interrupts */ + .long __msp_init + .long __exc_reset + .long __exc_nmi + .long __exc_hardfault + .long __exc_memmanage + .long __exc_busfault + .long __exc_usagefault + .long __stm32reservedexception7 + .long __stm32reservedexception8 + .long __stm32reservedexception9 + .long __stm32reservedexception10 + .long __exc_svc + .long __exc_debug_monitor + .long __stm32reservedexception13 + .long __exc_pendsv + .long __exc_systick +/* Peripheral interrupts */ + .long __irq_wwdg + .long __irq_pvd + .long __irq_tamper + .long __irq_rtc + .long __irq_flash + .long __irq_rcc + .long __irq_exti0 + .long __irq_exti1 + .long __irq_exti2 + .long __irq_exti3 + .long __irq_exti4 + .long __irq_dma1_channel1 + .long __irq_dma1_channel2 + .long __irq_dma1_channel3 + .long __irq_dma1_channel4 + .long __irq_dma1_channel5 + .long __irq_dma1_channel6 + .long __irq_dma1_channel7 + .long __irq_adc + .long __irq_usb_hp_can_tx + .long __irq_usb_lp_can_rx0 + .long __irq_can_rx1 + .long __irq_can_sce + .long __irq_exti9_5 + .long __irq_tim1_brk + .long __irq_tim1_up + .long __irq_tim1_trg_com + .long __irq_tim1_cc + .long __irq_tim2 + .long __irq_tim3 + .long __irq_tim4 + .long __irq_i2c1_ev + .long __irq_i2c1_er + .long __irq_i2c2_ev + .long __irq_i2c2_er + .long __irq_spi1 + .long __irq_spi2 + .long __irq_usart1 + .long __irq_usart2 + .long __irq_usart3 + .long __irq_exti15_10 + .long __irq_rtcalarm + .long __irq_usbwakeup +#if defined (STM32_HIGH_DENSITY) + .long __irq_tim8_brk + .long __irq_tim8_up + .long __irq_tim8_trg_com + .long __irq_tim8_cc + .long __irq_adc3 + .long __irq_fsmc + .long __irq_sdio + .long __irq_tim5 + .long __irq_spi3 + .long __irq_uart4 + .long __irq_uart5 + .long __irq_tim6 + .long __irq_tim7 + .long __irq_dma2_channel1 + .long __irq_dma2_channel2 + .long __irq_dma2_channel3 + .long __irq_dma2_channel4_5 +#endif /* STM32_HIGH_DENSITY */ + + .size __stm32_vector_table, . - __stm32_vector_table diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index b67f446..0effea3 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -7,9 +7,12 @@ BUILDDIRS += $(BUILD_PATH)/$(d) # Local flags CFLAGS_$(d) = -I$(d) $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror +# Extra BUILDDIRS +BUILDDIRS += $(BUILD_PATH)/$(d)/$(MCU_F1_LINE) + # Local rules and targets -sSRCS_$(d) := isrs_performance.S -sSRCS_$(d) += vector_table_performance.S +sSRCS_$(d) := $(MCU_F1_LINE)/isrs.S +sSRCS_$(d) += $(MCU_F1_LINE)/vector_table.S cSRCS_$(d) := adc.c cSRCS_$(d) += bkp.c diff --git a/libmaple/stm32f1/value/isrs.S b/libmaple/stm32f1/value/isrs.S new file mode 100644 index 0000000..858016b --- /dev/null +++ b/libmaple/stm32f1/value/isrs.S @@ -0,0 +1,270 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 Perry Hung. + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F1 value line ISR weak declarations */ + + .thumb + +/* Default handler for all non-overridden interrupts and exceptions */ + .globl __default_handler + .type __default_handler, %function + +__default_handler: + b . + + .weak __msp_init + .globl __msp_init + .set __msp_init, __default_handler + .weak __exc_reset + .globl __exc_reset + .set __exc_reset, __default_handler + .weak __exc_nmi + .globl __exc_nmi + .set __exc_nmi, __default_handler + .weak __exc_hardfault + .globl __exc_hardfault + .set __exc_hardfault, __default_handler + .weak __exc_memmanage + .globl __exc_memmanage + .set __exc_memmanage, __default_handler + .weak __exc_busfault + .globl __exc_busfault + .set __exc_busfault, __default_handler + .weak __exc_usagefault + .globl __exc_usagefault + .set __exc_usagefault, __default_handler + .weak __stm32reservedexception7 + .globl __stm32reservedexception7 + .set __stm32reservedexception7, __default_handler + .weak __stm32reservedexception8 + .globl __stm32reservedexception8 + .set __stm32reservedexception8, __default_handler + .weak __stm32reservedexception9 + .globl __stm32reservedexception9 + .set __stm32reservedexception9, __default_handler + .weak __stm32reservedexception10 + .globl __stm32reservedexception10 + .set __stm32reservedexception10, __default_handler + .weak __exc_svc + .globl __exc_svc + .set __exc_svc, __default_handler + .weak __exc_debug_monitor + .globl __exc_debug_monitor + .set __exc_debug_monitor, __default_handler + .weak __stm32reservedexception13 + .globl __stm32reservedexception13 + .set __stm32reservedexception13, __default_handler + .weak __exc_pendsv + .globl __exc_pendsv + .set __exc_pendsv, __default_handler + .weak __exc_systick + .globl __exc_systick + .set __exc_systick, __default_handler + + .weak __irq_wwdg + .globl __irq_wwdg + .set __irq_wwdg, __default_handler + .weak __irq_pvd + .globl __irq_pvd + .set __irq_pvd, __default_handler + .weak __irq_tamper + .globl __irq_tamper + .set __irq_tamper, __default_handler + .weak __irq_rtc + .globl __irq_rtc + .set __irq_rtc, __default_handler + .weak __irq_flash + .globl __irq_flash + .set __irq_flash, __default_handler + .weak __irq_rcc + .globl __irq_rcc + .set __irq_rcc, __default_handler + .weak __irq_exti0 + .globl __irq_exti0 + .set __irq_exti0, __default_handler + .weak __irq_exti1 + .globl __irq_exti1 + .set __irq_exti1, __default_handler + .weak __irq_exti2 + .globl __irq_exti2 + .set __irq_exti2, __default_handler + .weak __irq_exti3 + .globl __irq_exti3 + .set __irq_exti3, __default_handler + .weak __irq_exti4 + .globl __irq_exti4 + .set __irq_exti4, __default_handler + .weak __irq_dma1_channel1 + .globl __irq_dma1_channel1 + .set __irq_dma1_channel1, __default_handler + .weak __irq_dma1_channel2 + .globl __irq_dma1_channel2 + .set __irq_dma1_channel2, __default_handler + .weak __irq_dma1_channel3 + .globl __irq_dma1_channel3 + .set __irq_dma1_channel3, __default_handler + .weak __irq_dma1_channel4 + .globl __irq_dma1_channel4 + .set __irq_dma1_channel4, __default_handler + .weak __irq_dma1_channel5 + .globl __irq_dma1_channel5 + .set __irq_dma1_channel5, __default_handler + .weak __irq_dma1_channel6 + .globl __irq_dma1_channel6 + .set __irq_dma1_channel6, __default_handler + .weak __irq_dma1_channel7 + .globl __irq_dma1_channel7 + .set __irq_dma1_channel7, __default_handler + .weak __irq_adc1 + .globl __irq_adc1 + .set __irq_adc1, __default_handler + .weak __stm32reservedexception14 + .globl __stm32reservedexception14 + .set __stm32reservedexception14, __default_handler + .weak __stm32reservedexception15 + .globl __stm32reservedexception15 + .set __stm32reservedexception15, __default_handler + .weak __stm32reservedexception16 + .globl __stm32reservedexception16 + .set __stm32reservedexception16, __default_handler + .weak __stm32reservedexception17 + .globl __stm32reservedexception17 + .set __stm32reservedexception17, __default_handler + .weak __irq_exti9_5 + .globl __irq_exti9_5 + .set __irq_exti9_5, __default_handler + .weak __irq_tim1_brk + .globl __irq_tim1_brk + .set __irq_tim1_brk, __default_handler + .weak __irq_tim1_up + .globl __irq_tim1_up + .set __irq_tim1_up, __default_handler + .weak __irq_tim1_trg_com + .globl __irq_tim1_trg_com + .set __irq_tim1_trg_com, __default_handler + .weak __irq_tim1_cc + .globl __irq_tim1_cc + .set __irq_tim1_cc, __default_handler + .weak __irq_tim2 + .globl __irq_tim2 + .set __irq_tim2, __default_handler + .weak __irq_tim3 + .globl __irq_tim3 + .set __irq_tim3, __default_handler + .weak __irq_tim4 + .globl __irq_tim4 + .set __irq_tim4, __default_handler + .weak __irq_i2c1_ev + .globl __irq_i2c1_ev + .set __irq_i2c1_ev, __default_handler + .weak __irq_i2c1_er + .globl __irq_i2c1_er + .set __irq_i2c1_er, __default_handler + .weak __irq_i2c2_ev + .globl __irq_i2c2_ev + .set __irq_i2c2_ev, __default_handler + .weak __irq_i2c2_er + .globl __irq_i2c2_er + .set __irq_i2c2_er, __default_handler + .weak __irq_spi1 + .globl __irq_spi1 + .set __irq_spi1, __default_handler + .weak __irq_spi2 + .globl __irq_spi2 + .set __irq_spi2, __default_handler + .weak __irq_usart1 + .globl __irq_usart1 + .set __irq_usart1, __default_handler + .weak __irq_usart2 + .globl __irq_usart2 + .set __irq_usart2, __default_handler + .weak __irq_usart3 + .globl __irq_usart3 + .set __irq_usart3, __default_handler + .weak __irq_exti15_10 + .globl __irq_exti15_10 + .set __irq_exti15_10, __default_handler + .weak __irq_rtcalarm + .globl __irq_rtcalarm + .set __irq_rtcalarm, __default_handler + .weak __irq_cec + .globl __irq_cec + .set __irq_cec, __default_handler + .weak __irq_tim12 + .globl __irq_tim12 + .set __irq_tim12, __default_handler + .weak __irq_tim13 + .globl __irq_tim13 + .set __irq_tim13, __default_handler + .weak __irq_tim14 + .globl __irq_tim14 + .set __irq_tim14, __default_handler + .weak __stm32reservedexception18 + .globl __stm32reservedexception18 + .set __stm32reservedexception18, __default_handler + .weak __stm32reservedexception19 + .globl __stm32reservedexception19 + .set __stm32reservedexception19, __default_handler + .weak __irq_fsmc + .globl __irq_fsmc + .set __irq_fsmc, __default_handler + .weak __stm32reservedexception20 + .globl __stm32reservedexception20 + .set __stm32reservedexception20, __default_handler + .weak __irq_tim5 + .globl __irq_tim5 + .set __irq_tim5, __default_handler + .weak __irq_spi3 + .globl __irq_spi3 + .set __irq_spi3, __default_handler + .weak __irq_uart4 + .globl __irq_uart4 + .set __irq_uart4, __default_handler + .weak __irq_uart5 + .globl __irq_uart5 + .set __irq_uart5, __default_handler + .weak __irq_tim6 + .globl __irq_tim6 + .set __irq_tim6, __default_handler + .weak __irq_tim7 + .globl __irq_tim7 + .set __irq_tim7, __default_handler + .weak __irq_dma2_channel1 + .globl __irq_dma2_channel1 + .set __irq_dma2_channel1, __default_handler + .weak __irq_dma2_channel2 + .globl __irq_dma2_channel2 + .set __irq_dma2_channel2, __default_handler + .weak __irq_dma2_channel3 + .globl __irq_dma2_channel3 + .set __irq_dma2_channel3, __default_handler + .weak __irq_dma2_channel4_5 + .globl __irq_dma2_channel4_5 + .set __irq_dma2_channel4_5, __default_handler + .weak __irq_dma2_channel5 /* on remap only */ + .globl __irq_dma2_channel5 + .set __irq_dma2_channel5, __default_handler diff --git a/libmaple/stm32f1/value/vector_table.S b/libmaple/stm32f1/value/vector_table.S new file mode 100644 index 0000000..76a2a6e --- /dev/null +++ b/libmaple/stm32f1/value/vector_table.S @@ -0,0 +1,116 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011 Perry Hung. + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* STM32F1 value line vector table */ + + .section ".stm32.interrupt_vector" + + .globl __stm32_vector_table + .type __stm32_vector_table, %object + +__stm32_vector_table: +/* CM3 core interrupts */ + .long __msp_init + .long __exc_reset + .long __exc_nmi + .long __exc_hardfault + .long __exc_memmanage + .long __exc_busfault + .long __exc_usagefault + .long __stm32reservedexception7 + .long __stm32reservedexception8 + .long __stm32reservedexception9 + .long __stm32reservedexception10 + .long __exc_svc + .long __exc_debug_monitor + .long __stm32reservedexception13 + .long __exc_pendsv + .long __exc_systick +/* Peripheral interrupts */ + .long __irq_wwdg + .long __irq_pvd + .long __irq_tamper + .long __irq_rtc + .long __irq_flash + .long __irq_rcc + .long __irq_exti0 + .long __irq_exti1 + .long __irq_exti2 + .long __irq_exti3 + .long __irq_exti4 + .long __irq_dma1_channel1 + .long __irq_dma1_channel2 + .long __irq_dma1_channel3 + .long __irq_dma1_channel4 + .long __irq_dma1_channel5 + .long __irq_dma1_channel6 + .long __irq_dma1_channel7 + .long __irq_adc1 + .long __stm32reservedexception14 + .long __stm32reservedexception15 + .long __stm32reservedexception16 + .long __stm32reservedexception17 + .long __irq_exti9_5 + .long __irq_tim1_brk + .long __irq_tim1_up + .long __irq_tim1_trg_com + .long __irq_tim1_cc + .long __irq_tim2 + .long __irq_tim3 + .long __irq_tim4 + .long __irq_i2c1_ev + .long __irq_i2c1_er + .long __irq_i2c2_ev + .long __irq_i2c2_er + .long __irq_spi1 + .long __irq_spi2 + .long __irq_usart1 + .long __irq_usart2 + .long __irq_usart3 + .long __irq_exti15_10 + .long __irq_rtcalarm + .long __irq_cec + .long __irq_tim12 + .long __irq_tim13 + .long __irq_tim14 + .long __stm32reservedexception18 + .long __stm32reservedexception19 + .long __irq_fsmc + .long __stm32reservedexception20 + .long __irq_tim5 + .long __irq_spi3 + .long __irq_uart4 + .long __irq_uart5 + .long __irq_tim6 + .long __irq_tim7 + .long __irq_dma2_channel1 + .long __irq_dma2_channel2 + .long __irq_dma2_channel3 + .long __irq_dma2_channel4_5 + .long __irq_dma2_channel5 /* on remap only */ + + .size __stm32_vector_table, . - __stm32_vector_table diff --git a/libmaple/stm32f1/vector_table_performance.S b/libmaple/stm32f1/vector_table_performance.S deleted file mode 100644 index 55cf44f..0000000 --- a/libmaple/stm32f1/vector_table_performance.S +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2011 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/* STM32F1 vector table */ - - .section ".stm32.interrupt_vector" - - .globl __stm32_vector_table - .type __stm32_vector_table, %object - -__stm32_vector_table: -/* CM3 core interrupts */ - .long __msp_init - .long __exc_reset - .long __exc_nmi - .long __exc_hardfault - .long __exc_memmanage - .long __exc_busfault - .long __exc_usagefault - .long __stm32reservedexception7 - .long __stm32reservedexception8 - .long __stm32reservedexception9 - .long __stm32reservedexception10 - .long __exc_svc - .long __exc_debug_monitor - .long __stm32reservedexception13 - .long __exc_pendsv - .long __exc_systick -/* Peripheral interrupts */ - .long __irq_wwdg - .long __irq_pvd - .long __irq_tamper - .long __irq_rtc - .long __irq_flash - .long __irq_rcc - .long __irq_exti0 - .long __irq_exti1 - .long __irq_exti2 - .long __irq_exti3 - .long __irq_exti4 - .long __irq_dma1_channel1 - .long __irq_dma1_channel2 - .long __irq_dma1_channel3 - .long __irq_dma1_channel4 - .long __irq_dma1_channel5 - .long __irq_dma1_channel6 - .long __irq_dma1_channel7 - .long __irq_adc - .long __irq_usb_hp_can_tx - .long __irq_usb_lp_can_rx0 - .long __irq_can_rx1 - .long __irq_can_sce - .long __irq_exti9_5 - .long __irq_tim1_brk - .long __irq_tim1_up - .long __irq_tim1_trg_com - .long __irq_tim1_cc - .long __irq_tim2 - .long __irq_tim3 - .long __irq_tim4 - .long __irq_i2c1_ev - .long __irq_i2c1_er - .long __irq_i2c2_ev - .long __irq_i2c2_er - .long __irq_spi1 - .long __irq_spi2 - .long __irq_usart1 - .long __irq_usart2 - .long __irq_usart3 - .long __irq_exti15_10 - .long __irq_rtcalarm - .long __irq_usbwakeup -#if defined (STM32_HIGH_DENSITY) - .long __irq_tim8_brk - .long __irq_tim8_up - .long __irq_tim8_trg_com - .long __irq_tim8_cc - .long __irq_adc3 - .long __irq_fsmc - .long __irq_sdio - .long __irq_tim5 - .long __irq_spi3 - .long __irq_uart4 - .long __irq_uart5 - .long __irq_tim6 - .long __irq_tim7 - .long __irq_dma2_channel1 - .long __irq_dma2_channel2 - .long __irq_dma2_channel3 - .long __irq_dma2_channel4_5 -#endif /* STM32_HIGH_DENSITY */ - - .size __stm32_vector_table, . - __stm32_vector_table -- cgit v1.2.3 From 94cdc275384674362f93017ef6cbc2117027e5b4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 17:18:57 -0400 Subject: wirish/ext_interrupts.cpp: Doxygen, copyright. Signed-off-by: Marti Bolivar --- wirish/ext_interrupts.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/wirish/ext_interrupts.cpp b/wirish/ext_interrupts.cpp index a4a27c2..90c7e60 100644 --- a/wirish/ext_interrupts.cpp +++ b/wirish/ext_interrupts.cpp @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -25,7 +26,7 @@ *****************************************************************************/ /** - * @file wirish/ext_interrupts.c + * @file wirish/ext_interrupts.cpp * @brief Wiring-like interface for external interrupts */ -- cgit v1.2.3 From d992ac7ae79b889fd5680a7e15a18301bd9dc778 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 17:19:31 -0400 Subject: libmaple/dac.c: Generalize comment about PA4/PA5. Seems like this is true on F2 as well! Signed-off-by: Marti Bolivar --- libmaple/dac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/dac.c b/libmaple/dac.c index f630ac0..83eb4bd 100644 --- a/libmaple/dac.c +++ b/libmaple/dac.c @@ -92,8 +92,8 @@ void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val) { */ void dac_enable_channel(const dac_dev *dev, uint8 channel) { /* - * Setup ANALOG mode on PA4 and PA5. This mapping is consistent across - * all STM32 chips with a DAC. See RM0008 12.2. + * Setup ANALOG mode on PA4 and PA5. This mapping is consistent + * across all supported STM32s with a DAC. */ switch (channel) { case 1: -- cgit v1.2.3 From 12b626f0b5802b5cc8a4ea98e9cec2aa849ae2d7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 17:20:40 -0400 Subject: libmaple/dac.c: Copyright. Signed-off-by: Marti Bolivar --- libmaple/dac.c | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/dac.c b/libmaple/dac.c index 83eb4bd..5a00590 100644 --- a/libmaple/dac.c +++ b/libmaple/dac.c @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Bryan Newbold. + * Copyright (c) 2011 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation -- cgit v1.2.3 From 41c909dd2a9f6311d443550cb7c2ca3337fe3a20 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 17:25:22 -0400 Subject: : Doxygen Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/bitband.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/include/libmaple/bitband.h b/libmaple/include/libmaple/bitband.h index 0980311..6e77991 100644 --- a/libmaple/include/libmaple/bitband.h +++ b/libmaple/include/libmaple/bitband.h @@ -51,7 +51,7 @@ static inline volatile uint32* __bb_addr(volatile void*, /** * @brief Obtain a pointer to the bit-band address corresponding to a - * bit in a volatile SRAM address. + * bit in a volatile SRAM address. * @param address Address in the bit-banded SRAM region * @param bit Bit in address to bit-band */ @@ -83,7 +83,7 @@ static inline void bb_sram_set_bit(volatile void *address, /** * @brief Obtain a pointer to the bit-band address corresponding to a - * bit in a peripheral address. + * bit in a peripheral address. * @param address Address in the bit-banded peripheral region * @param bit Bit in address to bit-band */ -- cgit v1.2.3 From a5b5d4f27f94befaf5577563a0319e8194377118 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 20:30:13 -0400 Subject: Bring back EXTI on F1, with deprecations for gpio.h on F1. Tested on Maple Mini with examples/mini-exti-test. Changes to Wirish are minor: use the new EXTI types exti_num and exti_cfg (see below) in place of now-deprecated variants in ext_interrupts.cpp. The way I originally did libmaple/exti.h was stupid, and fixing it turned out to be a little disruptive. libmaple/exti.h depends on libmaple/gpio.h (for AFIO), but that's a classic case of exposed implementation detail. So invert the dependency: make gpio.h depend on exti.h. Do this by adding exti_num and exti_cfg to exti.h; these respectively replace afio_exti_num and afio_exti_port. The afio_* variants are now deprecated. (Throw in a typedef and some macros at the bottom of the F1 series/gpio.h for backwards compatibility). Make exti_attach_interrupt() and exti_detach_interrupt() take exti_num/exti_cfg arguments instead of the afio_* variants. Make the EXTI dispatch routines __always_inline to defeat GCC -Os. Many renames throughout libmaple/stm32f1/ to stop using the deprecated names. Also move the previously F1-only gpio_exti_port() function into the public libmaple header. Reimplementing it in terms of rcc_clk_ids lets us deprecate the gpio_dev->exti_port field, which will save space in the future. While we're there, I notice that struct gpio_dev is defined once per series. That's dumb, as it misses the entire point of having device structs: they contain what's portable. So put the F1 version (which has the extra EXTI port field) into libmaple/gpio.h, and add the necessary exti_ports to libmaple/stm32f2/gpio.c. Sigh. We'll get rid of it eventually, at least. Clean up some other mistakes in gpio.h files as well (mostly removing util.h dependency). Sorry for the messy commit. For portability, add a new series-specific exti function, exti_select(). The F1 version in (new) libmaple/stm32f1/exti.c uses AFIO and some new private functionality in libmaple/exti.c and (new) libmaple/exti_private.h to make this convenient. We'll be able to do the SYSCFG equivalent on F2 without any trouble. Signed-off-by: Marti Bolivar --- libmaple/exti.c | 58 ++++++--- libmaple/exti_private.h | 34 ++++++ libmaple/include/libmaple/exti.h | 78 +++++++++++- libmaple/include/libmaple/gpio.h | 41 +++++-- libmaple/rules.mk | 2 +- libmaple/stm32f1/exti.c | 32 +++++ libmaple/stm32f1/gpio.c | 36 ++---- libmaple/stm32f1/include/series/gpio.h | 215 ++++++++++++++++++--------------- libmaple/stm32f1/rules.mk | 1 + libmaple/stm32f2/gpio.c | 9 ++ libmaple/stm32f2/include/series/gpio.h | 54 ++++----- wirish/ext_interrupts.cpp | 4 +- wirish/rules.mk | 2 +- 13 files changed, 375 insertions(+), 191 deletions(-) create mode 100644 libmaple/exti_private.h create mode 100644 libmaple/stm32f1/exti.c diff --git a/libmaple/exti.c b/libmaple/exti.c index 248c4b6..d84b789 100644 --- a/libmaple/exti.c +++ b/libmaple/exti.c @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -66,7 +67,7 @@ static exti_channel exti_channels[] = { }; /* - * Convenience routines + * Portable routines */ /** @@ -80,13 +81,13 @@ static exti_channel exti_channels[] = { * @param handler Function handler to execute when interrupt is triggered. * @param mode Type of transition to trigger on, one of: * EXTI_RISING, EXTI_FALLING, EXTI_RISING_FALLING. - * @see afio_exti_num - * @see afio_exti_port + * @see exti_num + * @see exti_cfg * @see voidFuncPtr * @see exti_trigger_mode */ -void exti_attach_interrupt(afio_exti_num num, - afio_exti_port port, +void exti_attach_interrupt(exti_num num, + exti_cfg port, voidFuncPtr handler, exti_trigger_mode mode) { ASSERT(handler); @@ -108,8 +109,8 @@ void exti_attach_interrupt(afio_exti_num num, break; } - /* Map num to port */ - afio_exti_select(num, port); + /* Use the chip-specific exti_select() to map num to port */ + exti_select(num, port); /* Unmask external interrupt request */ bb_peri_set_bit(&EXTI_BASE->IMR, num, 1); @@ -120,10 +121,10 @@ void exti_attach_interrupt(afio_exti_num num, /** * @brief Unregister an external interrupt handler - * @param num Number of the external interrupt line to disable. - * @see afio_exti_num + * @param num External interrupt line to disable. + * @see exti_num */ -void exti_detach_interrupt(afio_exti_num num) { +void exti_detach_interrupt(exti_num num) { /* First, mask the interrupt request */ bb_peri_set_bit(&EXTI_BASE->IMR, num, 0); @@ -135,28 +136,45 @@ void exti_detach_interrupt(afio_exti_num num) { exti_channels[num].handler = NULL; } +/* Weak default exti_select(), until we get F2 support */ +__weak void exti_select(exti_num num, exti_cfg port) { + ASSERT(0); +} + +/* + * Private routines + */ + +void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port) { + uint32 shift = 4 * (num % 4); + uint32 cr = *exti_cr; + cr &= ~(0xF << shift); + cr |= port << shift; + *exti_cr = cr; +} + /* * Interrupt handlers */ void __irq_exti0(void) { - dispatch_single_exti(AFIO_EXTI_0); + dispatch_single_exti(EXTI0); } void __irq_exti1(void) { - dispatch_single_exti(AFIO_EXTI_1); + dispatch_single_exti(EXTI1); } void __irq_exti2(void) { - dispatch_single_exti(AFIO_EXTI_2); + dispatch_single_exti(EXTI2); } void __irq_exti3(void) { - dispatch_single_exti(AFIO_EXTI_3); + dispatch_single_exti(EXTI3); } void __irq_exti4(void) { - dispatch_single_exti(AFIO_EXTI_4); + dispatch_single_exti(EXTI4); } void __irq_exti9_5(void) { @@ -177,7 +195,7 @@ void __irq_exti15_10(void) { * won't actually be cleared in time and the ISR will fire again. To * compensate, this function NOPs for 2 cycles after clearing the * pending bits to ensure it takes effect. */ -static inline void clear_pending_msk(uint32 exti_msk) { +static __always_inline void clear_pending_msk(uint32 exti_msk) { EXTI_BASE->PR = exti_msk; asm volatile("nop"); asm volatile("nop"); @@ -185,7 +203,7 @@ static inline void clear_pending_msk(uint32 exti_msk) { /* This dispatch routine is for non-multiplexed EXTI lines only; i.e., * it doesn't check EXTI_PR. */ -static inline void dispatch_single_exti(uint32 exti) { +static __always_inline void dispatch_single_exti(uint32 exti) { voidFuncPtr handler = exti_channels[exti].handler; if (!handler) { @@ -193,18 +211,18 @@ static inline void dispatch_single_exti(uint32 exti) { } handler(); - clear_pending_msk(BIT(exti)); + clear_pending_msk(1U << exti); } /* Dispatch routine for EXTIs which share an IRQ. */ -static inline void dispatch_extis(uint32 start, uint32 stop) { +static __always_inline void dispatch_extis(uint32 start, uint32 stop) { uint32 pr = EXTI_BASE->PR; uint32 handled_msk = 0; uint32 exti; /* Dispatch user handlers for pending EXTIs. */ for (exti = start; exti <= stop; exti++) { - uint32 eb = BIT(exti); + uint32 eb = (1U << exti); if (pr & eb) { voidFuncPtr handler = exti_channels[exti].handler; if (handler) { diff --git a/libmaple/exti_private.h b/libmaple/exti_private.h new file mode 100644 index 0000000..4f0a4cf --- /dev/null +++ b/libmaple/exti_private.h @@ -0,0 +1,34 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +#ifndef _LIBMAPLE_EXTI_PRIVATE_H_ +#define _LIBMAPLE_EXTI_PRIVATE_H_ + +#include + +void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port); + +#endif diff --git a/libmaple/include/libmaple/exti.h b/libmaple/include/libmaple/exti.h index d7bfe51..5259a44 100644 --- a/libmaple/include/libmaple/exti.h +++ b/libmaple/include/libmaple/exti.h @@ -26,7 +26,7 @@ /** * @file libmaple/include/libmaple/exti.h - * @brief External interrupt control prototypes and defines + * @brief External interrupt control */ /* See notes/exti.txt for more info */ @@ -38,8 +38,11 @@ extern "C"{ #endif -#include -#include +#include + +/* + * Register map and base pointer. + */ /** EXTI register map type */ typedef struct exti_reg_map { @@ -54,6 +57,51 @@ typedef struct exti_reg_map { /** EXTI register map base pointer */ #define EXTI_BASE ((struct exti_reg_map*)0x40010400) +/* + * Types: exti_num, exti_cfg, exti_trigger_mode. + * + * A combination of these three specifies an external interrupt + * configuration (see exti_attach_interrupt()). + */ + +/** EXTI line. */ +typedef enum exti_num { + EXTI0, /**< EXTI line 0 */ + EXTI1, /**< EXTI line 1 */ + EXTI2, /**< EXTI line 2 */ + EXTI3, /**< EXTI line 3 */ + EXTI4, /**< EXTI line 4 */ + EXTI5, /**< EXTI line 5 */ + EXTI6, /**< EXTI line 6 */ + EXTI7, /**< EXTI line 7 */ + EXTI8, /**< EXTI line 8 */ + EXTI9, /**< EXTI line 9 */ + EXTI10, /**< EXTI line 10 */ + EXTI11, /**< EXTI line 11 */ + EXTI12, /**< EXTI line 12 */ + EXTI13, /**< EXTI line 13 */ + EXTI14, /**< EXTI line 14 */ + EXTI15, /**< EXTI line 15 */ +} exti_num; + +/** + * @brief EXTI port configuration + * + * These specify which GPIO port an external interrupt line should be + * connected to. + */ +typedef enum exti_cfg { + EXTI_PA, /**< Use PAx pin */ + EXTI_PB, /**< Use PBx pin */ + EXTI_PC, /**< Use PCx pin */ + EXTI_PD, /**< Use PDx pin */ + EXTI_PE, /**< Use PEx pin */ + EXTI_PF, /**< Use PFx pin */ + EXTI_PG, /**< Use PGx pin */ + EXTI_PH, /**< Use PHx pin */ + EXTI_PI, /**< Use PIx pin */ +} exti_cfg; + /** External interrupt trigger mode */ typedef enum exti_trigger_mode { EXTI_RISING, /**< Trigger on the rising edge */ @@ -61,11 +109,29 @@ typedef enum exti_trigger_mode { EXTI_RISING_FALLING /**< Trigger on both the rising and falling edges */ } exti_trigger_mode; -void exti_attach_interrupt(afio_exti_num num, - afio_exti_port port, +/* + * Routines + */ + +void exti_attach_interrupt(exti_num num, + exti_cfg port, voidFuncPtr handler, exti_trigger_mode mode); -void exti_detach_interrupt(afio_exti_num num); +void exti_detach_interrupt(exti_num num); + +/** + * @brief Set the GPIO port for an EXTI line. + * + * This is a low-level routine that most users will not + * need. exti_attach_interrupt() handles calling this function + * appropriately. + * + * @param num EXTI line + * @param port EXTI configuration for GPIO port to connect to num. + * @see exti_num + * @see exti_cfg + */ +extern void exti_select(exti_num num, exti_cfg port); #ifdef __cplusplus } // extern "C" diff --git a/libmaple/include/libmaple/gpio.h b/libmaple/include/libmaple/gpio.h index ca7b2bf..0cc3746 100644 --- a/libmaple/include/libmaple/gpio.h +++ b/libmaple/include/libmaple/gpio.h @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -38,21 +39,45 @@ extern "C"{ /* * Note: Series header must define: - * - struct gpio_dev (and declare extern pointers to series-provided ones) - * - enum gpio_pin_mode (TODO think hard on this) + * - enum gpio_pin_mode (TODO think harder about portability here) */ #include -#include +#include +#include +#include /* - * GPIO Convenience routines + * Device type + */ + +/** GPIO device type */ +typedef struct gpio_dev { + gpio_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< RCC clock information */ + /** + * @brief (Deprecated) External interrupt port. + * Instead of dev->exti_port, use gpio_exti_port(dev). + */ + exti_cfg exti_port; +} gpio_dev; + +/* + * Portable routines */ void gpio_init(gpio_dev *dev); void gpio_init_all(void); -/* TODO deprecate this? We should probably take a flags argument. */ +/* TODO flags argument version? */ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode); +/** + * @brief Get a GPIO port's corresponding EXTI port configuration. + * @param dev GPIO port whose exti_cfg to return. + */ +static inline exti_cfg gpio_exti_port(gpio_dev *dev) { + return (exti_cfg)(EXTI_PA + (dev->clk_id - RCC_GPIOA)); +} + /** * Set or reset a GPIO pin. * @@ -64,7 +89,7 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode); */ static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) { val = !val; /* "set" bits are lower than "reset" bits */ - dev->regs->BSRR = BIT(pin) << (16 * val); + dev->regs->BSRR = (1U << pin) << (16 * val); } /** @@ -77,7 +102,7 @@ static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) { * @return True if the pin is set, false otherwise. */ static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) { - return dev->regs->IDR & BIT(pin); + return dev->regs->IDR & (1U << pin); } /** @@ -86,7 +111,7 @@ static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) { * @param pin Pin on dev to toggle. */ static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) { - dev->regs->ODR = dev->regs->ODR ^ BIT(pin); + dev->regs->ODR = dev->regs->ODR ^ (1U << pin); } #ifdef __cplusplus diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 5c63522..b39c318 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -13,6 +13,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c # cSRCS_$(d) += dma.c +cSRCS_$(d) += exti.c cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c cSRCS_$(d) += iwdg.c @@ -28,7 +29,6 @@ cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c # These still need to be brought back for F1: # cSRCS_$(d) += dac.c -# cSRCS_$(d) += exti.c # cSRCS_$(d) += i2c.c sSRCS_$(d) := exc.S diff --git a/libmaple/stm32f1/exti.c b/libmaple/stm32f1/exti.c new file mode 100644 index 0000000..b9ff401 --- /dev/null +++ b/libmaple/stm32f1/exti.c @@ -0,0 +1,32 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +#include +#include "exti_private.h" + +void exti_select(exti_num num, exti_cfg port) { + exti_do_select(&AFIO_BASE->EXTICR1 + num / 4, num, port); +} diff --git a/libmaple/stm32f1/gpio.c b/libmaple/stm32f1/gpio.c index 2cbe299..4b596e9 100644 --- a/libmaple/stm32f1/gpio.c +++ b/libmaple/stm32f1/gpio.c @@ -39,7 +39,7 @@ gpio_dev gpioa = { .regs = GPIOA_BASE, .clk_id = RCC_GPIOA, - .exti_port = AFIO_EXTI_PA, + .exti_port = EXTI_PA, }; /** GPIO port A device. */ gpio_dev* const GPIOA = &gpioa; @@ -47,7 +47,7 @@ gpio_dev* const GPIOA = &gpioa; gpio_dev gpiob = { .regs = GPIOB_BASE, .clk_id = RCC_GPIOB, - .exti_port = AFIO_EXTI_PB, + .exti_port = EXTI_PB, }; /** GPIO port B device. */ gpio_dev* const GPIOB = &gpiob; @@ -55,7 +55,7 @@ gpio_dev* const GPIOB = &gpiob; gpio_dev gpioc = { .regs = GPIOC_BASE, .clk_id = RCC_GPIOC, - .exti_port = AFIO_EXTI_PC, + .exti_port = EXTI_PC, }; /** GPIO port C device. */ gpio_dev* const GPIOC = &gpioc; @@ -63,7 +63,7 @@ gpio_dev* const GPIOC = &gpioc; gpio_dev gpiod = { .regs = GPIOD_BASE, .clk_id = RCC_GPIOD, - .exti_port = AFIO_EXTI_PD, + .exti_port = EXTI_PD, }; /** GPIO port D device. */ gpio_dev* const GPIOD = &gpiod; @@ -72,7 +72,7 @@ gpio_dev* const GPIOD = &gpiod; gpio_dev gpioe = { .regs = GPIOE_BASE, .clk_id = RCC_GPIOE, - .exti_port = AFIO_EXTI_PE, + .exti_port = EXTI_PE, }; /** GPIO port E device. */ gpio_dev* const GPIOE = &gpioe; @@ -80,7 +80,7 @@ gpio_dev* const GPIOE = &gpioe; gpio_dev gpiof = { .regs = GPIOF_BASE, .clk_id = RCC_GPIOF, - .exti_port = AFIO_EXTI_PF, + .exti_port = EXTI_PF, }; /** GPIO port F device. */ gpio_dev* const GPIOF = &gpiof; @@ -88,7 +88,7 @@ gpio_dev* const GPIOF = &gpiof; gpio_dev gpiog = { .regs = GPIOG_BASE, .clk_id = RCC_GPIOG, - .exti_port = AFIO_EXTI_PG, + .exti_port = EXTI_PG, }; /** GPIO port G device. */ gpio_dev* const GPIOG = &gpiog; @@ -132,9 +132,9 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) { *cr = tmp; if (mode == GPIO_INPUT_PD) { - regs->ODR &= ~BIT(pin); + regs->ODR &= ~(1U << pin); } else if (mode == GPIO_INPUT_PU) { - regs->ODR |= BIT(pin); + regs->ODR |= (1U << pin); } } @@ -152,24 +152,6 @@ void afio_init(void) { #define AFIO_EXTI_SEL_MASK 0xF -/** - * @brief Select a source input for an external interrupt. - * - * @param exti External interrupt. - * @param gpio_port Port which contains pin to use as source input. - * @see afio_exti_num - * @see afio_exti_port - */ -void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) { - __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4; - uint32 shift = 4 * (exti % 4); - uint32 cr = *exti_cr; - - cr &= ~(AFIO_EXTI_SEL_MASK << shift); - cr |= gpio_port << shift; - *exti_cr = cr; -} - /** * @brief Perform an alternate function remap. * @param remapping Remapping to perform. diff --git a/libmaple/stm32f1/include/series/gpio.h b/libmaple/stm32f1/include/series/gpio.h index 1f209fe..0ca6d56 100644 --- a/libmaple/stm32f1/include/series/gpio.h +++ b/libmaple/stm32f1/include/series/gpio.h @@ -2,7 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -27,7 +27,7 @@ /** * @file libmaple/stm32f1/include/series/gpio.h - * @brief STM32F1 GPIO support. + * @brief STM32F1 GPIO and AFIO support. * * General purpose I/O (GPIO) and Alternate Function I/O (AFIO) * prototypes, defines, and support functions. @@ -40,8 +40,9 @@ extern "C"{ #endif -#include -#include +#include +#include +#include /* * GPIO register maps and devices @@ -58,46 +59,22 @@ typedef struct gpio_reg_map { __io uint32 LCKR; /**< Port configuration lock register */ } gpio_reg_map; -/** - * @brief External interrupt line port selector. - * - * Used to determine which GPIO port to map an external interrupt line - * onto. */ -/* (See AFIO sections, below) */ -typedef enum afio_exti_port { - AFIO_EXTI_PA, /**< Use port A (PAx) pin. */ - AFIO_EXTI_PB, /**< Use port B (PBx) pin. */ - AFIO_EXTI_PC, /**< Use port C (PCx) pin. */ - AFIO_EXTI_PD, /**< Use port D (PDx) pin. */ -#ifdef STM32_HIGH_DENSITY - AFIO_EXTI_PE, /**< Use port E (PEx) pin. */ - AFIO_EXTI_PF, /**< Use port F (PFx) pin. */ - AFIO_EXTI_PG, /**< Use port G (PGx) pin. */ -#endif -} afio_exti_port; - -/** GPIO device type */ -typedef struct gpio_dev { - gpio_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< RCC clock information */ - afio_exti_port exti_port; /**< AFIO external interrupt port value */ -} gpio_dev; - -extern gpio_dev gpioa; -extern gpio_dev* const GPIOA; -extern gpio_dev gpiob; -extern gpio_dev* const GPIOB; -extern gpio_dev gpioc; -extern gpio_dev* const GPIOC; -extern gpio_dev gpiod; -extern gpio_dev* const GPIOD; +struct gpio_dev; +extern struct gpio_dev gpioa; +extern struct gpio_dev* const GPIOA; +extern struct gpio_dev gpiob; +extern struct gpio_dev* const GPIOB; +extern struct gpio_dev gpioc; +extern struct gpio_dev* const GPIOC; +extern struct gpio_dev gpiod; +extern struct gpio_dev* const GPIOD; #ifdef STM32_HIGH_DENSITY -extern gpio_dev gpioe; -extern gpio_dev* const GPIOE; -extern gpio_dev gpiof; -extern gpio_dev* const GPIOF; -extern gpio_dev gpiog; -extern gpio_dev* const GPIOG; +extern struct gpio_dev gpioe; +extern struct gpio_dev* const GPIOE; +extern struct gpio_dev gpiof; +extern struct gpio_dev* const GPIOF; +extern struct gpio_dev gpiog; +extern struct gpio_dev* const GPIOG; #endif /** GPIO port A register map base pointer */ @@ -108,14 +85,12 @@ extern gpio_dev* const GPIOG; #define GPIOC_BASE ((struct gpio_reg_map*)0x40011000) /** GPIO port D register map base pointer */ #define GPIOD_BASE ((struct gpio_reg_map*)0x40011400) -#ifdef STM32_HIGH_DENSITY /** GPIO port E register map base pointer */ #define GPIOE_BASE ((struct gpio_reg_map*)0x40011800) /** GPIO port F register map base pointer */ #define GPIOF_BASE ((struct gpio_reg_map*)0x40011C00) /** GPIO port G register map base pointer */ #define GPIOG_BASE ((struct gpio_reg_map*)0x40012000) -#endif /* * GPIO register bit definitions @@ -138,7 +113,7 @@ extern gpio_dev* const GPIOG; #define GPIO_CR_MODE_OUTPUT_50MHZ 0x3 /** - * @brief GPIO Pin modes. + * @brief GPIO pin modes. * * These only allow for 50MHZ max output speeds; if you want slower, * use direct register access. @@ -164,14 +139,6 @@ typedef enum gpio_pin_mode { /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ } gpio_pin_mode; -/** - * @brief Get a GPIO port's corresponding afio_exti_port. - * @param dev GPIO device whose afio_exti_port to return. - */ -static inline afio_exti_port gpio_exti_port(gpio_dev *dev) { - return dev->exti_port; -} - /* * AFIO register map */ @@ -232,17 +199,17 @@ typedef struct afio_reg_map { #define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24) #define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24) #define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24) -#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20) -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19) -#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18) -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17) -#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16) -#define AFIO_MAPR_PD01_REMAP BIT(15) +#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1U << 20) +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1U << 19) +#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1U << 18) +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1U << 17) +#define AFIO_MAPR_TIM5CH4_IREMAP (1U << 16) +#define AFIO_MAPR_PD01_REMAP (1U << 15) #define AFIO_MAPR_CAN_REMAP (0x3 << 13) #define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13) #define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13) #define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13) -#define AFIO_MAPR_TIM4_REMAP BIT(12) +#define AFIO_MAPR_TIM4_REMAP (1U << 12) #define AFIO_MAPR_TIM3_REMAP (0x3 << 10) #define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10) #define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10) @@ -260,10 +227,10 @@ typedef struct afio_reg_map { #define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4) #define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4) #define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4) -#define AFIO_MAPR_USART2_REMAP BIT(3) -#define AFIO_MAPR_USART1_REMAP BIT(2) -#define AFIO_MAPR_I2C1_REMAP BIT(1) -#define AFIO_MAPR_SPI1_REMAP BIT(0) +#define AFIO_MAPR_USART2_REMAP (1U << 3) +#define AFIO_MAPR_USART1_REMAP (1U << 2) +#define AFIO_MAPR_I2C1_REMAP (1U << 1) +#define AFIO_MAPR_SPI1_REMAP (1U << 0) /* External interrupt configuration register 1 */ @@ -337,12 +304,12 @@ typedef struct afio_reg_map { /* AF remap and debug I/O configuration register 2 */ -#define AFIO_MAPR2_FSMC_NADV BIT(10) -#define AFIO_MAPR2_TIM14_REMAP BIT(9) -#define AFIO_MAPR2_TIM13_REMAP BIT(8) -#define AFIO_MAPR2_TIM11_REMAP BIT(7) -#define AFIO_MAPR2_TIM10_REMAP BIT(6) -#define AFIO_MAPR2_TIM9_REMAP BIT(5) +#define AFIO_MAPR2_FSMC_NADV (1U << 10) +#define AFIO_MAPR2_TIM14_REMAP (1U << 9) +#define AFIO_MAPR2_TIM13_REMAP (1U << 8) +#define AFIO_MAPR2_TIM11_REMAP (1U << 7) +#define AFIO_MAPR2_TIM10_REMAP (1U << 6) +#define AFIO_MAPR2_TIM9_REMAP (1U << 5) /* * AFIO convenience routines @@ -350,33 +317,9 @@ typedef struct afio_reg_map { void afio_init(void); -/** - * External interrupt line numbers. - */ -typedef enum afio_exti_num { - AFIO_EXTI_0, /**< External interrupt line 0. */ - AFIO_EXTI_1, /**< External interrupt line 1. */ - AFIO_EXTI_2, /**< External interrupt line 2. */ - AFIO_EXTI_3, /**< External interrupt line 3. */ - AFIO_EXTI_4, /**< External interrupt line 4. */ - AFIO_EXTI_5, /**< External interrupt line 5. */ - AFIO_EXTI_6, /**< External interrupt line 6. */ - AFIO_EXTI_7, /**< External interrupt line 7. */ - AFIO_EXTI_8, /**< External interrupt line 8. */ - AFIO_EXTI_9, /**< External interrupt line 9. */ - AFIO_EXTI_10, /**< External interrupt line 10. */ - AFIO_EXTI_11, /**< External interrupt line 11. */ - AFIO_EXTI_12, /**< External interrupt line 12. */ - AFIO_EXTI_13, /**< External interrupt line 13. */ - AFIO_EXTI_14, /**< External interrupt line 14. */ - AFIO_EXTI_15, /**< External interrupt line 15. */ -} afio_exti_num; - -void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port); - /* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and * not used in either MAPR or MAPR2 */ -#define AFIO_REMAP_USE_MAPR2 (1 << 31) +#define AFIO_REMAP_USE_MAPR2 (1U << 31) /** * @brief Available peripheral remaps. @@ -474,6 +417,86 @@ static inline void afio_cfg_debug_ports(afio_debug_cfg config) { *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config; } +/* + * Deprecated bits + */ + +/** + * @brief Deprecated. Use exti_cfg instead. + * + * In previous versions of libmaple, exti_attach_interrupt() took an + * afio_exti_port argument; afio_exti_port was also a member of struct + * gpio_dev. This isn't portable, so we now use exti_cfg + * instead. This typedef (and the macros AFIO_EXTI_PA, ..., + * AFIO_EXTI_PG) exist to preserve backwards compatibility. + */ +typedef exti_cfg afio_exti_port; + +/** Deprecated. Use EXTI_PA instead. */ +#define AFIO_EXTI_PA EXTI_PA +/** Deprecated. Use EXTI_PB instead. */ +#define AFIO_EXTI_PB EXTI_PB +/** Deprecated. Use EXTI_PC instead. */ +#define AFIO_EXTI_PC EXTI_PC +/** Deprecated. Use EXTI_PD instead. */ +#define AFIO_EXTI_PD EXTI_PD +/** Deprecated. Use EXTI_PE instead. */ +#define AFIO_EXTI_PE EXTI_PE +/** Deprecated. Use EXTI_PF instead. */ +#define AFIO_EXTI_PF EXTI_PF +/** Deprecated. Use EXTI_PG instead. */ +#define AFIO_EXTI_PG EXTI_PG + +/** + * @brief Deprecated. Use exti_num instead. + * + * In previous versions of libmaple, exti_attach_interrupt() took an + * afio_exti_num argument. This isn't portable, so we use exti_num + * instead. This typedef (and the macros AFIO_EXTI_0, ..., + * AFIO_EXTI_15) exist to preserve backwards compatibility. + */ +typedef exti_num afio_exti_num; + +/** Deprecated. Use EXTI0 instead. */ +#define AFIO_EXTI_0 EXTI0 +/** Deprecated. Use EXTI1 instead. */ +#define AFIO_EXTI_1 EXTI1 +/** Deprecated. Use EXTI2 instead. */ +#define AFIO_EXTI_2 EXTI2 +/** Deprecated. Use EXTI3 instead. */ +#define AFIO_EXTI_3 EXTI3 +/** Deprecated. Use EXTI4 instead. */ +#define AFIO_EXTI_4 EXTI4 +/** Deprecated. Use EXTI5 instead. */ +#define AFIO_EXTI_5 EXTI5 +/** Deprecated. Use EXTI6 instead. */ +#define AFIO_EXTI_6 EXTI6 +/** Deprecated. Use EXTI7 instead. */ +#define AFIO_EXTI_7 EXTI7 +/** Deprecated. Use EXTI8 instead. */ +#define AFIO_EXTI_8 EXTI8 +/** Deprecated. Use EXTI9 instead. */ +#define AFIO_EXTI_9 EXTI9 +/** Deprecated. Use EXTI10 instead. */ +#define AFIO_EXTI_10 EXTI10 +/** Deprecated. Use EXTI11 instead. */ +#define AFIO_EXTI_11 EXTI11 +/** Deprecated. Use EXTI12 instead. */ +#define AFIO_EXTI_12 EXTI12 +/** Deprecated. Use EXTI13 instead. */ +#define AFIO_EXTI_13 EXTI13 +/** Deprecated. Use EXTI14 instead. */ +#define AFIO_EXTI_14 EXTI14 +/** Deprecated. Use EXTI15 instead. */ +#define AFIO_EXTI_15 EXTI15 + +/** + * @brief Deprecated. Use exti_select(exti, port) instead. + */ +static __always_inline void afio_exti_select(exti_num exti, exti_cfg port) { + exti_select(exti, port); +} + #ifdef __cplusplus } #endif diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 0effea3..15f6fdb 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -17,6 +17,7 @@ sSRCS_$(d) += $(MCU_F1_LINE)/vector_table.S cSRCS_$(d) := adc.c cSRCS_$(d) += bkp.c cSRCS_$(d) += dma.c +cSRCS_$(d) += exti.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c diff --git a/libmaple/stm32f2/gpio.c b/libmaple/stm32f2/gpio.c index f2cd776..a26edaa 100644 --- a/libmaple/stm32f2/gpio.c +++ b/libmaple/stm32f2/gpio.c @@ -40,6 +40,7 @@ gpio_dev gpioa = { .regs = GPIOA_BASE, .clk_id = RCC_GPIOA, + .exti_port = EXTI_PA, }; /** GPIO port A device. */ gpio_dev* const GPIOA = &gpioa; @@ -47,6 +48,7 @@ gpio_dev* const GPIOA = &gpioa; gpio_dev gpiob = { .regs = GPIOB_BASE, .clk_id = RCC_GPIOB, + .exti_port = EXTI_PB, }; /** GPIO port B device. */ gpio_dev* const GPIOB = &gpiob; @@ -54,6 +56,7 @@ gpio_dev* const GPIOB = &gpiob; gpio_dev gpioc = { .regs = GPIOC_BASE, .clk_id = RCC_GPIOC, + .exti_port = EXTI_PC, }; /** GPIO port C device. */ gpio_dev* const GPIOC = &gpioc; @@ -61,6 +64,7 @@ gpio_dev* const GPIOC = &gpioc; gpio_dev gpiod = { .regs = GPIOD_BASE, .clk_id = RCC_GPIOD, + .exti_port = EXTI_PD, }; /** GPIO port D device. */ gpio_dev* const GPIOD = &gpiod; @@ -68,6 +72,7 @@ gpio_dev* const GPIOD = &gpiod; gpio_dev gpioe = { .regs = GPIOE_BASE, .clk_id = RCC_GPIOE, + .exti_port = EXTI_PE, }; /** GPIO port E device. */ gpio_dev* const GPIOE = &gpioe; @@ -75,6 +80,7 @@ gpio_dev* const GPIOE = &gpioe; gpio_dev gpiof = { .regs = GPIOF_BASE, .clk_id = RCC_GPIOF, + .exti_port = EXTI_PF, }; /** GPIO port F device. */ gpio_dev* const GPIOF = &gpiof; @@ -82,6 +88,7 @@ gpio_dev* const GPIOF = &gpiof; gpio_dev gpiog = { .regs = GPIOG_BASE, .clk_id = RCC_GPIOG, + .exti_port = EXTI_PG, }; /** GPIO port G device. */ gpio_dev* const GPIOG = &gpiog; @@ -89,6 +96,7 @@ gpio_dev* const GPIOG = &gpiog; gpio_dev gpioh = { .regs = GPIOH_BASE, .clk_id = RCC_GPIOH, + .exti_port = EXTI_PH, }; /** GPIO port G device. */ gpio_dev* const GPIOH = &gpioh; @@ -96,6 +104,7 @@ gpio_dev* const GPIOH = &gpioh; gpio_dev gpioi = { .regs = GPIOI_BASE, .clk_id = RCC_GPIOI, + .exti_port = EXTI_PI, }; /** GPIO port G device. */ gpio_dev* const GPIOI = &gpioi; diff --git a/libmaple/stm32f2/include/series/gpio.h b/libmaple/stm32f2/include/series/gpio.h index 9687247..1496e8e 100644 --- a/libmaple/stm32f2/include/series/gpio.h +++ b/libmaple/stm32f2/include/series/gpio.h @@ -1,7 +1,7 @@ /****************************************************************************** * The MIT License * - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -36,8 +36,7 @@ extern "C"{ #endif -#include -#include +#include /* * GPIO register maps and devices @@ -76,30 +75,25 @@ typedef struct gpio_reg_map { /** GPIO port I register map base pointer */ #define GPIOI_BASE ((struct gpio_reg_map*)0x40022000) -/** GPIO device type */ -typedef struct gpio_dev { - gpio_reg_map *regs; - rcc_clk_id clk_id; -} gpio_dev; - -extern gpio_dev* const GPIOA; -extern gpio_dev gpioa; -extern gpio_dev* const GPIOB; -extern gpio_dev gpiob; -extern gpio_dev* const GPIOC; -extern gpio_dev gpioc; -extern gpio_dev* const GPIOD; -extern gpio_dev gpiod; -extern gpio_dev* const GPIOE; -extern gpio_dev gpioe; -extern gpio_dev* const GPIOF; -extern gpio_dev gpiof; -extern gpio_dev* const GPIOG; -extern gpio_dev gpiog; -extern gpio_dev* const GPIOH; -extern gpio_dev gpioh; -extern gpio_dev* const GPIOI; -extern gpio_dev gpioi; +struct gpio_dev; +extern struct gpio_dev* const GPIOA; +extern struct gpio_dev gpioa; +extern struct gpio_dev* const GPIOB; +extern struct gpio_dev gpiob; +extern struct gpio_dev* const GPIOC; +extern struct gpio_dev gpioc; +extern struct gpio_dev* const GPIOD; +extern struct gpio_dev gpiod; +extern struct gpio_dev* const GPIOE; +extern struct gpio_dev gpioe; +extern struct gpio_dev* const GPIOF; +extern struct gpio_dev gpiof; +extern struct gpio_dev* const GPIOG; +extern struct gpio_dev gpiog; +extern struct gpio_dev* const GPIOH; +extern struct gpio_dev gpioh; +extern struct gpio_dev* const GPIOI; +extern struct gpio_dev gpioi; /* * Register bit definitions @@ -215,7 +209,7 @@ typedef enum gpio_mode_flags { GPIO_MODEF_PUPD_PD = GPIO_PUPDR_PD << 3, /**< Pull-down */ } gpio_mode_flags; -void gpio_set_modef(gpio_dev *dev, +void gpio_set_modef(struct gpio_dev *dev, uint8 bit, gpio_pin_mode mode, unsigned flags); @@ -231,7 +225,7 @@ void gpio_set_modef(gpio_dev *dev, * @param pin Pin on the device whose mode to set, 0--15. * @param mode Mode to set the pin to. */ -static inline void gpio_set_mode(gpio_dev *dev, +static inline void gpio_set_mode(struct gpio_dev *dev, uint8 bit, gpio_pin_mode mode) { gpio_set_modef(dev, bit, mode, GPIO_MODEF_SPEED_HIGH); @@ -261,7 +255,7 @@ typedef enum gpio_af { GPIO_AF_EVENTOUT = 15, /**< EVENTOUT. */ } gpio_af; -void gpio_set_af(gpio_dev *dev, uint8 bit, gpio_af af); +void gpio_set_af(struct gpio_dev *dev, uint8 bit, gpio_af af); #ifdef __cplusplus } diff --git a/wirish/ext_interrupts.cpp b/wirish/ext_interrupts.cpp index 90c7e60..fab7343 100644 --- a/wirish/ext_interrupts.cpp +++ b/wirish/ext_interrupts.cpp @@ -53,7 +53,7 @@ void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) { exti_trigger_mode outMode = exti_out_mode(mode); - exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit), + exti_attach_interrupt((exti_num)(PIN_MAP[pin].gpio_bit), gpio_exti_port(PIN_MAP[pin].gpio_device), handler, outMode); @@ -68,7 +68,7 @@ void detachInterrupt(uint8 pin) { return; } - exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit)); + exti_detach_interrupt((exti_num)(PIN_MAP[pin].gpio_bit)); } static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) { diff --git a/wirish/rules.mk b/wirish/rules.mk index 6d96cbe..a198c2d 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -22,6 +22,7 @@ sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp +cppSRCS_$(d) += ext_interrupts.cpp cppSRCS_$(d) += HardwareSerial.cpp cppSRCS_$(d) += HardwareTimer.cpp cppSRCS_$(d) += Print.cpp @@ -39,7 +40,6 @@ cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately for F2 and put them back in: # HardwareSPI.cpp -# ext_interrupts.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3 From eaf34012efe105c5c7e9654c5cc0e988e4bbd719 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 20:58:16 -0400 Subject: STM32F1: gpio.h: Cosmetics. Those ugly Doxygen comments have been bothering me since forever. Fix them up and throw some M-x align around. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/gpio.h | 185 +++++++++++++++------------------ 1 file changed, 85 insertions(+), 100 deletions(-) diff --git a/libmaple/stm32f1/include/series/gpio.h b/libmaple/stm32f1/include/series/gpio.h index 0ca6d56..ec4a39c 100644 --- a/libmaple/stm32f1/include/series/gpio.h +++ b/libmaple/stm32f1/include/series/gpio.h @@ -28,9 +28,7 @@ /** * @file libmaple/stm32f1/include/series/gpio.h * @brief STM32F1 GPIO and AFIO support. - * - * General purpose I/O (GPIO) and Alternate Function I/O (AFIO) - * prototypes, defines, and support functions. + * General purpose I/O (GPIO) and Alternate Function I/O (AFIO). */ #ifndef _LIBMAPLE_STM32F1_GPIO_H_ @@ -119,24 +117,22 @@ extern struct gpio_dev* const GPIOG; * use direct register access. */ typedef enum gpio_pin_mode { - GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */ - GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */ - GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output push-pull. */ - GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD | - GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function - output open drain. */ - GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG | - GPIO_CR_MODE_INPUT), /**< Analog input. */ - GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING | - GPIO_CR_MODE_INPUT), /**< Input floating. */ - GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD | - GPIO_CR_MODE_INPUT), /**< Input pull-down. */ - GPIO_INPUT_PU /**< Input pull-up. */ - /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */ + /** Output push-pull. */ + GPIO_OUTPUT_PP = GPIO_CR_CNF_OUTPUT_PP | GPIO_CR_MODE_OUTPUT_50MHZ, + /** Output open-drain. */ + GPIO_OUTPUT_OD = GPIO_CR_CNF_OUTPUT_OD | GPIO_CR_MODE_OUTPUT_50MHZ, + /** Alternate function output push-pull. */ + GPIO_AF_OUTPUT_PP = GPIO_CR_CNF_AF_OUTPUT_PP | GPIO_CR_MODE_OUTPUT_50MHZ, + /** Alternate function output open drain. */ + GPIO_AF_OUTPUT_OD = GPIO_CR_CNF_AF_OUTPUT_OD | GPIO_CR_MODE_OUTPUT_50MHZ, + /** Analog input. */ + GPIO_INPUT_ANALOG = GPIO_CR_CNF_INPUT_ANALOG | GPIO_CR_MODE_INPUT, + /** Input floating. */ + GPIO_INPUT_FLOATING = GPIO_CR_CNF_INPUT_FLOATING | GPIO_CR_MODE_INPUT, + /** Input pull-down. */ + GPIO_INPUT_PD = GPIO_CR_CNF_INPUT_PU_PD | GPIO_CR_MODE_INPUT, + /** Input pull-up. */ + GPIO_INPUT_PU, /* (treated a special case, for ODR twiddling) */ } gpio_pin_mode; /* @@ -145,19 +141,14 @@ typedef enum gpio_pin_mode { /** AFIO register map */ typedef struct afio_reg_map { - __io uint32 EVCR; /**< Event control register. */ - __io uint32 MAPR; /**< AF remap and debug I/O configuration - register. */ - __io uint32 EXTICR1; /**< External interrupt configuration - register 1. */ - __io uint32 EXTICR2; /**< External interrupt configuration - register 2. */ - __io uint32 EXTICR3; /**< External interrupt configuration - register 3. */ - __io uint32 EXTICR4; /**< External interrupt configuration - register 4. */ - __io uint32 MAPR2; /**< AF remap and debug I/O configuration - register 2. */ + __io uint32 EVCR; /**< Event control register. */ + __io uint32 MAPR; /**< AF remap and debug I/O configuration register. */ + __io uint32 EXTICR1; /**< External interrupt configuration register 1. */ + __io uint32 EXTICR2; /**< External interrupt configuration register 2. */ + __io uint32 EXTICR3; /**< External interrupt configuration register 3. */ + __io uint32 EXTICR4; /**< External interrupt configuration register 4. */ + __io uint32 MAPR2; /**< + * AF remap and debug I/O configuration register 2. */ } afio_reg_map; /** AFIO register map base pointer. */ @@ -326,62 +317,58 @@ void afio_init(void); * @see afio_remap() */ typedef enum afio_remap_peripheral { - AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**< - ADC 2 external trigger regular conversion remapping */ - AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**< - ADC 2 external trigger injected conversion remapping */ - AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**< - ADC 1 external trigger regular conversion remapping */ - AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**< - ADC 1 external trigger injected conversion remapping */ - AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**< - Timer 5 channel 4 internal remapping */ - AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**< - Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**< - CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ - AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**< - CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ - AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**< - Timer 4 remapping */ - AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**< - Timer 3 partial remapping */ - AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**< - Timer 3 full remapping */ - AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**< - Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 - on PA2, CH4 on PA3) */ - AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**< - Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 - on PB10, CH4 on PB11) */ - AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**< - Timer 2 full remapping */ - AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**< - USART 2 remapping */ - AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**< - USART 1 remapping */ - AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**< - I2C 1 remapping */ - AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**< - SPI 1 remapping */ - AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV | - AFIO_REMAP_USE_MAPR2), /**< - NADV signal not connected */ - AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 14 remapping */ - AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 13 remapping */ - AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 11 remapping */ - AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP | - AFIO_REMAP_USE_MAPR2), /**< - Timer 10 remapping */ - AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP | - AFIO_REMAP_USE_MAPR2) /**< - Timer 9 */ + /** ADC 2 external trigger regular conversion remapping */ + AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, + /** ADC 2 external trigger injected conversion remapping */ + AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, + /** ADC 1 external trigger regular conversion remapping */ + AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, + /** ADC 1 external trigger injected conversion remapping */ + AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, + /** Timer 5 channel 4 internal remapping */ + AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, + /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, + /** CAN alternate function remapping 1 (RX on PB8, TX on PB9) */ + AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, + /** CAN alternate function remapping 2 (RX on PD0, TX on PD1) */ + AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, + /** Timer 4 remapping */ + AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, + /** Timer 3 partial remapping */ + AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, + /** Timer 3 full remapping */ + AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, + /** + * Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, + * CH3 on PA2, CH4 on PA3) */ + AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, + /** + * Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, + * CH3 on PB10, CH4 on PB11) */ + AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, + /** Timer 2 full remapping */ + AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, + /** USART 2 remapping */ + AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, + /** USART 1 remapping */ + AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, + /** I2C 1 remapping */ + AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, + /** SPI 1 remapping */ + AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, + /** NADV signal not connected */ + AFIO_REMAP_FSMC_NADV = AFIO_MAPR2_FSMC_NADV | AFIO_REMAP_USE_MAPR2, + /** Timer 14 remapping */ + AFIO_REMAP_TIM14 = AFIO_MAPR2_TIM14_REMAP | AFIO_REMAP_USE_MAPR2, + /** Timer 13 remapping */ + AFIO_REMAP_TIM13 = AFIO_MAPR2_TIM13_REMAP | AFIO_REMAP_USE_MAPR2, + /** Timer 11 remapping */ + AFIO_REMAP_TIM11 = AFIO_MAPR2_TIM11_REMAP | AFIO_REMAP_USE_MAPR2, + /** Timer 10 remapping */ + AFIO_REMAP_TIM10 = AFIO_MAPR2_TIM10_REMAP | AFIO_REMAP_USE_MAPR2, + /** Timer 9 remapping */ + AFIO_REMAP_TIM9 = AFIO_MAPR2_TIM9_REMAP | AFIO_REMAP_USE_MAPR2, } afio_remap_peripheral; void afio_remap(afio_remap_peripheral p); @@ -395,16 +382,14 @@ void afio_remap(afio_remap_peripheral p); * @see afio_cfg_debug_ports() */ typedef enum afio_debug_cfg { - AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**< - Full Serial Wire and JTAG debug */ - AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**< - Full Serial Wire and JTAG, but no NJTRST. */ - AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**< - Serial Wire debug only (JTAG-DP disabled, - SW-DP enabled) */ - AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**< - No debug; all JTAG and SW pins are free - for use as GPIOs. */ + /** Full Serial Wire and JTAG debug */ + AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, + /** Full Serial Wire and JTAG, but no NJTRST. */ + AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, + /** Serial Wire debug only (JTAG-DP disabled, SW-DP enabled) */ + AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, + /** No debug; all JTAG and SW pins are free for use as GPIOs. */ + AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW, } afio_debug_cfg; /** -- cgit v1.2.3 From b52f574dd6ec75157aebc48f1504832c0dd1c281 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 21:00:14 -0400 Subject: STM32F2: Add SYSCFG support. Turn it on at init() time on F2. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/syscfg.h | 151 +++++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + libmaple/stm32f2/syscfg.c | 78 +++++++++++++++++++ wirish/boards.cpp | 10 ++- wirish/boards_private.h | 1 + wirish/stm32f2/boards_setup.cpp | 6 ++ 6 files changed, 246 insertions(+), 1 deletion(-) create mode 100644 libmaple/include/libmaple/syscfg.h create mode 100644 libmaple/stm32f2/syscfg.c diff --git a/libmaple/include/libmaple/syscfg.h b/libmaple/include/libmaple/syscfg.h new file mode 100644 index 0000000..6b375d3 --- /dev/null +++ b/libmaple/include/libmaple/syscfg.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/include/libmaple/syscfg.h + * @brief System configuration controller (SYSCFG) + * + * Availability: STM32F2, STM32F4. + */ + +#ifndef _LIBMAPLE_SYSCFG_H_ +#define _LIBMAPLE_SYSCFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * Register map and base pointer + */ + +/** + * @brief SYSCFG register map type. + */ +typedef struct syscfg_reg_map { + __io uint32 MEMRMP; /**< Memory remap register */ + __io uint32 PMC; /**< Peripheral mode configuration */ + __io uint32 EXTICR[4]; /**< External interrupt configuration registers */ + const uint32 RESERVED1; + const uint32 RESERVED2; + __io uint32 CMPCR; /**< Compensation cell control register */ +} syscfg_reg_map; + +/** SYSCFG register map base pointer */ +#define SYSCFG_BASE ((struct syscfg_reg_map*)0x40013800) + +/* + * Register bit definitions + */ + +/* Memory remap register */ + +#define SYSCFG_MEMRMP_MEM_MODE 0x3 +#define SYSCFG_MEMRMP_MEM_MODE_FLASH 0x0 +#define SYSCFG_MEMRMP_MEM_MODE_SYS_FLASH 0x1 +#define SYSCFG_MEMRMP_MEM_MODE_FSMC_1 0x2 +#define SYSCFG_MEMRMP_MEM_MODE_EMB_SRAM 0x3 + +/* Peripheral mode configuration register */ + +#define SYSCFG_PMC_MII_RMII_SEL_BIT 23 + +#define SYSCFG_PMC_MII_RMII_SEL (1U << SYSCFG_PMC_MII_RMII_SEL_BIT) +#define SYSCFG_PMC_MII_RMII_SEL_MII (0U << SYSCFG_PMC_MII_RMII_SEL_BIT) +#define SYSCFG_PMC_MII_RMII_SEL_RMII (1U << SYSCFG_PMC_MII_RMII_SEL_BIT) + +/* External interrupt configuration register 1 */ + +#define SYSCFG_EXTICR1_EXTI0 0xF +#define SYSCFG_EXTICR1_EXTI1 0xF0 +#define SYSCFG_EXTICR1_EXTI2 0xF00 +#define SYSCFG_EXTICR1_EXTI3 0xF000 + +/* External interrupt configuration register 2 */ + +#define SYSCFG_EXTICR2_EXTI4 0xF +#define SYSCFG_EXTICR2_EXTI5 0xF0 +#define SYSCFG_EXTICR2_EXTI6 0xF00 +#define SYSCFG_EXTICR2_EXTI7 0xF000 + +/* External interrupt configuration register 3 */ + +#define SYSCFG_EXTICR3_EXTI8 0xF +#define SYSCFG_EXTICR3_EXTI9 0xF0 +#define SYSCFG_EXTICR3_EXTI10 0xF00 +#define SYSCFG_EXTICR3_EXTI11 0xF000 + +/* External interrupt configuration register 4 */ + +#define SYSCFG_EXTICR4_EXTI12 0xF +#define SYSCFG_EXTICR4_EXTI13 0xF0 +#define SYSCFG_EXTICR4_EXTI14 0xF00 +#define SYSCFG_EXTICR4_EXTI15 0xF000 + +/* Compensation cell control register */ + +#define SYSCFG_CMPCR_READY_BIT 8 +#define SYSCFG_CMPCR_CMP_PD_BIT 0 + +#define SYSCFG_CMPCR_READY (1U << SYSCFG_CMPCR_READY_BIT) +#define SYSCFG_CMPCR_CMP_PD (1U << SYSCFG_CMPCR_CMP_PD_BIT) +#define SYSCFG_CMPCR_CMP_PD_PDWN (0U << SYSCFG_CMPCR_CMP_PD_BIT) +#define SYSCFG_CMPCR_CMP_PD_ENABLE (1U << SYSCFG_CMPCR_CMP_PD_BIT) + +/* + * Routines + */ + +void syscfg_init(void); + +void syscfg_enable_io_compensation(void); +void syscfg_disable_io_compensation(void); + +/** + * @brief System memory mode + * These values specify what memory to map to address 0x00000000. + * @see syscfg_set_mem_mode + */ +typedef enum syscfg_mem_mode { + /** Main flash memory is mapped at 0x0. */ + SYCFG_MEM_MODE_FLASH = SYSCFG_MEMRMP_MEM_MODE_FLASH, + /** System flash (i.e. ST's baked-in bootloader) is mapped at 0x0. */ + SYCFG_MEM_MODE_SYSTEM_FLASH = SYSCFG_MEMRMP_MEM_MODE_SYS_FLASH, + /** FSMC bank 1 (NOR/PSRAM 1 and 2) is mapped at 0x0. */ + SYCFG_MEM_MODE_FSMC_BANK_1 = SYSCFG_MEMRMP_MEM_MODE_FSMC_1, + /** Embedded SRAM (i.e., not backup SRAM) is mapped at 0x0. */ + SYCFG_MEM_MODE_SRAM = SYSCFG_MEMRMP_MEM_MODE_EMB_SRAM, +} syscfg_mem_mode; + +void syscfg_set_mem_mode(syscfg_mem_mode); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index c98f5b9..a5be551 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -15,6 +15,7 @@ cSRCS_$(d) := adc.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c +cSRCS_$(d) += syscfg.c cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c diff --git a/libmaple/stm32f2/syscfg.c b/libmaple/stm32f2/syscfg.c new file mode 100644 index 0000000..19e932e --- /dev/null +++ b/libmaple/stm32f2/syscfg.c @@ -0,0 +1,78 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/syscfg.c + * @brief SYSCFG routines. + */ + +#include +#include +#include + +/** + * @brief Initialize the SYSCFG peripheral. + */ +void syscfg_init(void) { + rcc_clk_enable(RCC_SYSCFG); + rcc_reset_dev(RCC_SYSCFG); +} + +/** + * @brief Turn on the I/O compensation cell. + * + * It's only safe to do this when the supply voltage is between 2.4 V + * and 3.6 V. + */ +void syscfg_enable_io_compensation(void) { + bb_peri_set_bit(&SYSCFG_BASE->CMPCR, SYSCFG_CMPCR_CMP_PD_BIT, 1); + while (!(SYSCFG_BASE->CMPCR & SYSCFG_CMPCR_READY)) + ; +} + +/** + * @brief Turn off the I/O compensation cell. + */ +void syscfg_disable_io_compensation(void) { + bb_peri_set_bit(&SYSCFG_BASE->CMPCR, SYSCFG_CMPCR_CMP_PD_BIT, 0); +} + +/** + * @brief Set the memory to be mapped at address 0x00000000. + * + * This function can be used to override the BOOT pin + * configuration. Some restrictions apply; see your chip's reference + * manual for the details. + * + * @param mode Mode to set + * @see syscfg_mem_mode + */ +void syscfg_set_mem_mode(syscfg_mem_mode mode) { + uint32 memrmp = SYSCFG_BASE->MEMRMP; + memrmp &= ~SYSCFG_MEMRMP_MEM_MODE; + memrmp |= (uint32)mode; + SYSCFG_BASE->MEMRMP = memrmp; +} diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 7616245..471325f 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -71,10 +71,18 @@ void init(void) { setup_adcs(); setup_timers(); wirish::priv::board_setup_usb(); + wirish::priv::series_init(); boardInit(); } -/* Provide a default boardInit(). */ +/* Provide a default no-op series_init() */ +namespace wirish { + namespace priv { + __weak void series_init(void) {} + } +} + +/* Provide a default no-op boardInit(). */ __weak void boardInit(void) { } diff --git a/wirish/boards_private.h b/wirish/boards_private.h index cdac844..4607913 100644 --- a/wirish/boards_private.h +++ b/wirish/boards_private.h @@ -59,6 +59,7 @@ namespace wirish { void board_setup_clock_prescalers(void); void board_setup_gpio(void); void board_setup_usb(void); + void series_init(void); } } diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index 9832bb7..d1ceac0 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -37,6 +37,7 @@ #include "boards_private.h" #include +#include #include // PLL configuration for 25 MHz external oscillator --> 120 MHz SYSCLK. @@ -85,5 +86,10 @@ namespace wirish { // Nothing to do. } + void series_init(void) { + // We need SYSCFG for external interrupts + syscfg_init(); + } + } } -- cgit v1.2.3 From 2bdf250ecdd0a30aae6f582aa92e5b3e53835a67 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 22:31:34 -0400 Subject: STM32F2: Turn on SYSCFG I/O compensation during init(). Signed-off-by: Marti Bolivar --- wirish/stm32f2/boards_setup.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index d1ceac0..952e84d 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -89,6 +89,9 @@ namespace wirish { void series_init(void) { // We need SYSCFG for external interrupts syscfg_init(); + // Turn on the I/O compensation cell, since we drive the + // GPIOs quickly be default. + syscfg_enable_io_compensation(); } } -- cgit v1.2.3 From d036d2f4e2d4475037294304e7c04a6db6b3167d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 21:01:18 -0400 Subject: STM32F2: Add EXTI support. Add series headers to keep the base pointers, and (on F2) use SYSCFG to tell exti_do_select() where the EXTI control registers are. No surprises. Signed-off-by: Marti Bolivar --- libmaple/exti.c | 5 ---- libmaple/include/libmaple/exti.h | 4 +-- libmaple/stm32f1/include/series/exti.h | 46 ++++++++++++++++++++++++++++++++++ libmaple/stm32f2/exti.c | 33 ++++++++++++++++++++++++ libmaple/stm32f2/include/series/exti.h | 46 ++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + wirish/ext_interrupts.cpp | 2 +- 7 files changed, 128 insertions(+), 9 deletions(-) create mode 100644 libmaple/stm32f1/include/series/exti.h create mode 100644 libmaple/stm32f2/exti.c create mode 100644 libmaple/stm32f2/include/series/exti.h diff --git a/libmaple/exti.c b/libmaple/exti.c index d84b789..9023782 100644 --- a/libmaple/exti.c +++ b/libmaple/exti.c @@ -136,11 +136,6 @@ void exti_detach_interrupt(exti_num num) { exti_channels[num].handler = NULL; } -/* Weak default exti_select(), until we get F2 support */ -__weak void exti_select(exti_num num, exti_cfg port) { - ASSERT(0); -} - /* * Private routines */ diff --git a/libmaple/include/libmaple/exti.h b/libmaple/include/libmaple/exti.h index 5259a44..3800b4a 100644 --- a/libmaple/include/libmaple/exti.h +++ b/libmaple/include/libmaple/exti.h @@ -38,6 +38,7 @@ extern "C"{ #endif +#include /* provides EXTI_BASE */ #include /* @@ -54,9 +55,6 @@ typedef struct exti_reg_map { __io uint32 PR; /**< Pending register */ } exti_reg_map; -/** EXTI register map base pointer */ -#define EXTI_BASE ((struct exti_reg_map*)0x40010400) - /* * Types: exti_num, exti_cfg, exti_trigger_mode. * diff --git a/libmaple/stm32f1/include/series/exti.h b/libmaple/stm32f1/include/series/exti.h new file mode 100644 index 0000000..1ece664 --- /dev/null +++ b/libmaple/stm32f1/include/series/exti.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/include/series/exti.h + * @brief STM32F1 external interrupts + */ + +#ifndef _LIBMAPLE_STM32F1_EXTI_H_ +#define _LIBMAPLE_STM32F1_EXTI_H_ + +#ifdef __cpluspus +extern "C" { +#endif + +struct exti_reg_map; +#define EXTI_BASE ((struct exti_reg_map*)0x40010400) + +#ifdef __cpluspus +} +#endif + +#endif diff --git a/libmaple/stm32f2/exti.c b/libmaple/stm32f2/exti.c new file mode 100644 index 0000000..208415f --- /dev/null +++ b/libmaple/stm32f2/exti.c @@ -0,0 +1,33 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +#include +#include +#include "exti_private.h" + +void exti_select(exti_num num, exti_cfg cfg) { + exti_do_select(&SYSCFG_BASE->EXTICR[num / 4], num, cfg); +} diff --git a/libmaple/stm32f2/include/series/exti.h b/libmaple/stm32f2/include/series/exti.h new file mode 100644 index 0000000..4643fcf --- /dev/null +++ b/libmaple/stm32f2/include/series/exti.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/include/series/exti.h + * @brief STM32F2 external interrupts + */ + +#ifndef _LIBMAPLE_STM32F2_EXTI_H_ +#define _LIBMAPLE_STM32F2_EXTI_H_ + +#ifdef __cpluspus +extern "C" { +#endif + +struct exti_reg_map; +#define EXTI_BASE ((struct exti_reg_map*)0x40013C00) + +#ifdef __cpluspus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index a5be551..fd6b933 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -12,6 +12,7 @@ sSRCS_$(d) := isrs.S sSRCS_$(d) += vector_table.S cSRCS_$(d) := adc.c +cSRCS_$(d) += exti.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c diff --git a/wirish/ext_interrupts.cpp b/wirish/ext_interrupts.cpp index fab7343..a3e61fd 100644 --- a/wirish/ext_interrupts.cpp +++ b/wirish/ext_interrupts.cpp @@ -2,7 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation -- cgit v1.2.3 From 0873e4fc167f08fbac4b188a755a61f5afb03d20 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 4 Jun 2012 00:15:40 -0400 Subject: STM32F1: gpio.h: Add hack mode macro, for F2 compatibility. I'm sure we can work the compatible subset of F1/F2 GPIO functionality into the F1 gpio.h interface in a clean way. This is not that clean way, but I'm short on time. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/gpio.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libmaple/stm32f1/include/series/gpio.h b/libmaple/stm32f1/include/series/gpio.h index ec4a39c..2f96a08 100644 --- a/libmaple/stm32f1/include/series/gpio.h +++ b/libmaple/stm32f1/include/series/gpio.h @@ -135,6 +135,9 @@ typedef enum gpio_pin_mode { GPIO_INPUT_PU, /* (treated a special case, for ODR twiddling) */ } gpio_pin_mode; +/* Hacks for F2: */ +#define GPIO_MODE_ANALOG GPIO_INPUT_ANALOG + /* * AFIO register map */ -- cgit v1.2.3 From 6ad1757e62dcfe112a473ef6474b9f4c1317cf9e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Sun, 3 Jun 2012 23:09:37 -0400 Subject: stm32.h: Add STM32_HAVE_DAC feature-test. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/stm32.h | 6 ++++++ libmaple/stm32f1/include/series/stm32.h | 5 +++++ libmaple/stm32f2/include/series/stm32.h | 1 + 3 files changed, 12 insertions(+) diff --git a/libmaple/include/libmaple/stm32.h b/libmaple/include/libmaple/stm32.h index 94fb689..3845cab 100644 --- a/libmaple/include/libmaple/stm32.h +++ b/libmaple/include/libmaple/stm32.h @@ -78,6 +78,7 @@ extern "C" { !defined(STM32_TIMER_MASK) || \ !defined(STM32_DELAY_US_MULT) || \ !defined(STM32_SRAM_END) || \ + !defined(STM32_HAVE_DAC) || \ !defined(STM32_HAVE_FSMC) || \ !defined(STM32_HAVE_USB)) #error "Bad STM32F1 configuration. Check header for your MCU." @@ -179,6 +180,11 @@ extern "C" { */ #define STM32_SRAM_END +/** + * @brief 1 if the target MCU has a DAC, and 0 otherwise. + */ +#define STM32_HAVE_DAC + /** * @brief 1 if the target MCU has the FSMC peripheral, and 0 otherwise. * diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index 23c0591..e793a10 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -115,14 +115,17 @@ extern "C" { # define STM32_NR_INTERRUPTS 43 # define STM32_TIMER_MASK 0x1E /* TIMER1--TIMER4 */ # define STM32_HAVE_FSMC 0 +# define STM32_HAVE_DAC 0 # elif defined(STM32_HIGH_DENSITY) # define STM32_NR_INTERRUPTS 60 # define STM32_TIMER_MASK 0x1FE /* TIMER1--TIMER8 */ # define STM32_HAVE_FSMC 1 +# define STM32_HAVE_DAC 1 # elif defined(STM32_XL_DENSITY) # define STM32_NR_INTERRUPTS 60 # define STM32_TIMER_MASK 0x7FFE /* TIMER1--TIMER14 */ # define STM32_HAVE_FSMC 1 +# define STM32_HAVE_DAC 1 # endif #elif STM32_F1_LINE == STM32_F1_LINE_VALUE @@ -132,11 +135,13 @@ extern "C" { # ifdef STM32_MEDIUM_DENSITY # define STM32_NR_INTERRUPTS 56 # define STM32_HAVE_FSMC 0 +# define STM32_HAVE_DAC 1 # elif defined(STM32_HIGH_DENSITY) /* 61 interrupts here counts the possibility for a remapped * DMA2 channel 5 IRQ occurring at NVIC index 60. */ # define STM32_NR_INTERRUPTS 61 # define STM32_HAVE_FSMC 1 +# define STM32_HAVE_DAC 1 # endif #endif diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index b53b7b6..2c389ab 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -60,6 +60,7 @@ extern "C" { #define STM32_NR_INTERRUPTS 81 #define STM32_HAVE_FSMC 1 #define STM32_HAVE_USB 1 +#define STM32_HAVE_DAC 1 #if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG) # define STM32_NR_GPIO_PORTS 9 -- cgit v1.2.3 From 23d81a1044ac3c3694d58d7659be8476ebe9ee15 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 4 Jun 2012 00:06:43 -0400 Subject: Bring back libmaple/dac.h. Minor variations on F2: DMA underrun interrupts, and a status register to hold the notification bits. Signed-off-by: Marti Bolivar --- libmaple/dac.c | 19 ++---- libmaple/include/libmaple/dac.h | 124 +++++++++++++++------------------- libmaple/rules.mk | 2 +- libmaple/stm32f1/include/series/dac.h | 71 +++++++++++++++++++ libmaple/stm32f2/include/series/dac.h | 94 ++++++++++++++++++++++++++ 5 files changed, 228 insertions(+), 82 deletions(-) create mode 100644 libmaple/stm32f1/include/series/dac.h create mode 100644 libmaple/stm32f2/include/series/dac.h diff --git a/libmaple/dac.c b/libmaple/dac.c index 5a00590..d802d2b 100644 --- a/libmaple/dac.c +++ b/libmaple/dac.c @@ -2,7 +2,7 @@ * The MIT License * * Copyright (c) 2010 Bryan Newbold. - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -30,21 +30,16 @@ * @brief Digital to analog converter support. */ +#include #include #include -#include - -#ifdef STM32_HIGH_DENSITY - -/** - * @brief DAC peripheral routines. - */ +#if STM32_HAVE_DAC dac_dev dac = { .regs = DAC_BASE, }; -/** DAC device. */ const dac_dev *DAC = &dac; +#endif /** * @brief Initialize the digital to analog converter @@ -98,11 +93,11 @@ void dac_enable_channel(const dac_dev *dev, uint8 channel) { */ switch (channel) { case 1: - gpio_set_mode(GPIOA, 4, GPIO_INPUT_ANALOG); + gpio_set_mode(GPIOA, 4, GPIO_MODE_ANALOG); dev->regs->CR |= DAC_CR_EN1; break; case 2: - gpio_set_mode(GPIOA, 5, GPIO_INPUT_ANALOG); + gpio_set_mode(GPIOA, 5, GPIO_MODE_ANALOG); dev->regs->CR |= DAC_CR_EN2; break; } @@ -123,5 +118,3 @@ void dac_disable_channel(const dac_dev *dev, uint8 channel) { break; } } - -#endif /* STM32_HIGH_DENSITY */ diff --git a/libmaple/include/libmaple/dac.h b/libmaple/include/libmaple/dac.h index 047f874..56bfdc4 100644 --- a/libmaple/include/libmaple/dac.h +++ b/libmaple/include/libmaple/dac.h @@ -1,7 +1,7 @@ /****************************************************************************** * The MIT License * - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * Copyright (c) 2010 Bryan Newbold. * * Permission is hereby granted, free of charge, to any person @@ -39,124 +39,112 @@ extern "C"{ #endif +#include #include #include +#include /* - * Register maps + * Register map base and device pointers. + * + * The DACs are the same on all supported targets, so it's not worth + * repeating these in the series headers. */ -/** DAC register map. */ -typedef struct dac_reg_map { - __io uint32 CR; /**< Control register */ - __io uint32 SWTRIGR; /**< Software trigger register */ - __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data - holding register */ - __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data - holding register */ - __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data - holding register */ - __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data - holding register */ - __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data - holding register */ - __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data - holding register */ - __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data - holding register */ - __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data - holding register */ - __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding - register */ - __io uint32 DOR1; /**< Channel 1 data output register */ - __io uint32 DOR2; /**< Channel 2 data output register */ -} dac_reg_map; - -/** DAC register map base address */ #define DAC_BASE ((struct dac_reg_map*)0x40007400) -/* - * Devices - */ - /** DAC device type. */ typedef struct dac_dev { dac_reg_map *regs; /**< Register map */ } dac_dev; +#if STM32_HAVE_DAC extern const dac_dev *DAC; +#endif /* * Register bit definitions */ /* Control register */ + /* Channel 1 control */ -#define DAC_CR_EN1 BIT(0) /* Enable */ -#define DAC_CR_BOFF1 BIT(1) /* Output buffer disable */ -#define DAC_CR_TEN1 BIT(2) /* Trigger enable */ -#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */ -#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave enable */ -#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */ -#define DAC_CR_DMAEN1 BIT(12) /* DMA enable */ +#define DAC_CR_EN1 (1U << 0) /* Enable */ +#define DAC_CR_BOFF1 (1U << 1) /* Output buffer disable */ +#define DAC_CR_TEN1 (1U << 2) /* Trigger enable */ +#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */ +#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave */ +#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */ +#define DAC_CR_DMAEN1 (1U << 12) /* DMA enable */ /* Channel 2 control */ -#define DAC_CR_EN2 BIT(16) /* Enable */ -#define DAC_CR_BOFF2 BIT(17) /* Output buffer disable */ -#define DAC_CR_TEN2 BIT(18) /* Trigger enable */ -#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */ -#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave generation*/ -#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */ -#define DAC_CR_DMAEN2 BIT(28) /* DMA enable */ +#define DAC_CR_EN2 (1U << 16) /* Enable */ +#define DAC_CR_BOFF2 (1U << 17) /* Output buffer disable */ +#define DAC_CR_TEN2 (1U << 18) /* Trigger enable */ +#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */ +#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave */ +#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */ +#define DAC_CR_DMAEN2 (1U << 28) /* DMA enable */ /* Software trigger register */ -#define DAC_SWTRIGR_SWTRIG1 BIT(0) /* Channel 1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 BIT(1) /* Channel 2 software trigger */ + +#define DAC_SWTRIGR_SWTRIG1 (1U << 0) /* Channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1U << 1) /* Channel 2 software trigger */ /* Channel 1 12-bit right-aligned data holding register */ -#define DAC_DHR12R1_DACC1DHR 0x00000FFF + +#define DAC_DHR12R1_DACC1DHR 0x00000FFF /* Channel 1 12-bit left-aligned data holding register */ -#define DAC_DHR12L1_DACC1DHR 0x0000FFF0 + +#define DAC_DHR12L1_DACC1DHR 0x0000FFF0 /* Channel 1 8-bit left-aligned data holding register */ -#define DAC_DHR8R1_DACC1DHR 0x000000FF + +#define DAC_DHR8R1_DACC1DHR 0x000000FF /* Channel 2 12-bit right-aligned data holding register */ -#define DAC_DHR12R2_DACC2DHR 0x00000FFF + +#define DAC_DHR12R2_DACC2DHR 0x00000FFF /* Channel 2 12-bit left-aligned data holding register */ -#define DAC_DHR12L2_DACC2DHR 0x0000FFF0 + +#define DAC_DHR12L2_DACC2DHR 0x0000FFF0 /* Channel 2 8-bit left-aligned data holding register */ -#define DAC_DHR8R2_DACC2DHR 0x000000FF + +#define DAC_DHR8R2_DACC2DHR 0x000000FF /* Dual DAC 12-bit right-aligned data holding register */ -#define DAC_DHR12RD_DACC1DHR 0x00000FFF -#define DAC_DHR12RD_DACC2DHR 0x0FFF0000 + +#define DAC_DHR12RD_DACC1DHR 0x00000FFF +#define DAC_DHR12RD_DACC2DHR 0x0FFF0000 /* Dual DAC 12-bit left-aligned data holding register */ -#define DAC_DHR12LD_DACC1DHR 0x0000FFF0 -#define DAC_DHR12LD_DACC2DHR 0xFFF00000 + +#define DAC_DHR12LD_DACC1DHR 0x0000FFF0 +#define DAC_DHR12LD_DACC2DHR 0xFFF00000 /* Dual DAC 8-bit left-aligned data holding register */ -#define DAC_DHR8RD_DACC1DHR 0x000000FF -#define DAC_DHR8RD_DACC2DHR 0x0000FF00 + +#define DAC_DHR8RD_DACC1DHR 0x000000FF +#define DAC_DHR8RD_DACC2DHR 0x0000FF00 /* Channel 1 data output register */ -#define DAC_DOR1_DACC1DOR 0x00000FFF + +#define DAC_DOR1_DACC1DOR 0x00000FFF /* Channel 1 data output register */ -#define DAC_DOR2_DACC2DOR 0x00000FFF + +#define DAC_DOR2_DACC2DOR 0x00000FFF /* - * Convenience functions + * Routines */ -/* We take the dev argument in these convenience functions for - * future-proofing */ +/* We take the dev argument in these for future-proofing */ -#define DAC_CH1 0x1 -#define DAC_CH2 0x2 +#define DAC_CH1 0x1 +#define DAC_CH2 0x2 void dac_init(const dac_dev *dev, uint32 flags); void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val); diff --git a/libmaple/rules.mk b/libmaple/rules.mk index b39c318..08c4c02 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -12,6 +12,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c +cSRCS_$(d) += dac.c # cSRCS_$(d) += dma.c cSRCS_$(d) += exti.c cSRCS_$(d) += flash.c @@ -28,7 +29,6 @@ cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c # These still need to be brought back for F1: -# cSRCS_$(d) += dac.c # cSRCS_$(d) += i2c.c sSRCS_$(d) := exc.S diff --git a/libmaple/stm32f1/include/series/dac.h b/libmaple/stm32f1/include/series/dac.h new file mode 100644 index 0000000..c0d026b --- /dev/null +++ b/libmaple/stm32f1/include/series/dac.h @@ -0,0 +1,71 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f1/include/series/dac.h + * @brief STM32F1 DAC support + */ + +#ifndef _LIBMAPLE_STM32F1_DAC_H_ +#define _LIBMAPLE_STM32F1_DAC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** STM32F1 DAC register map type. */ +typedef struct dac_reg_map { + __io uint32 CR; /**< Control register */ + __io uint32 SWTRIGR; /**< Software trigger register */ + __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data + holding register */ + __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data + holding register */ + __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data + holding register */ + __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data + holding register */ + __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data + holding register */ + __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data + holding register */ + __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data + holding register */ + __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data + holding register */ + __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding + register */ + __io uint32 DOR1; /**< Channel 1 data output register */ + __io uint32 DOR2; /**< Channel 2 data output register */ +} dac_reg_map; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/include/series/dac.h b/libmaple/stm32f2/include/series/dac.h new file mode 100644 index 0000000..0a578ca --- /dev/null +++ b/libmaple/stm32f2/include/series/dac.h @@ -0,0 +1,94 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/include/series/dac.h + * @brief STM32F2 DAC support + */ + +#ifndef _LIBMAPLE_STM32F2_DAC_H_ +#define _LIBMAPLE_STM32F2_DAC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/* + * Register map type + */ + +/** STM32F2 DAC register map type. */ +typedef struct dac_reg_map { + __io uint32 CR; /**< Control register */ + __io uint32 SWTRIGR; /**< Software trigger register */ + __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data + holding register */ + __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data + holding register */ + __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data + holding register */ + __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data + holding register */ + __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data + holding register */ + __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data + holding register */ + __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data + holding register */ + __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data + holding register */ + __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding + register */ + __io uint32 DOR1; /**< Channel 1 data output register */ + __io uint32 DOR2; /**< Channel 2 data output register */ + __io uint32 SR; /**< Status register */ +} dac_reg_map; + +/* + * Register bit definitions + */ + +/* Control register */ + +#define DAC_CR_DMAUDRIE1 (1U << 13) /* Channel 1 DMA underrun + * interrupt enable */ +#define DAC_CR_DMAUDRIE2 (1U << 29) /* Channel 2 DMA underrun + * interrupt enable */ + +/* Status register */ + +#define DAC_SR_DMAUDR1 (1U << 13) /* Channel 1 DMA underrun + * occurred */ +#define DAC_SR_DMAUDR2 (1U << 29) /* Channel 2 DMA underrun + * ocurred */ + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.2.3 From e6ba29161ee79ad8500b4d74ff11d123b9f6a17f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 14:38:39 -0400 Subject: Remove a completed FIXME comment. Signed-off-by: Marti Bolivar --- wirish/stm32f1/boards_setup.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index 1dec579..da45730 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -51,9 +51,6 @@ #define BOARD_RCC_PLLMUL RCC_PLLMUL_9 #endif -/* FIXME: Reintroduce all "#if 0"'ed blocks once libmaple provides - * these definitions again. */ - namespace wirish { namespace priv { -- cgit v1.2.3 From 90769437c91dd523e13e1437c4117dd40c76f372 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 15:04:06 -0400 Subject: Provide wirish::priv::series_init() on F1. This lets us remove the weak definition in boards.cpp. Signed-off-by: Marti Bolivar --- wirish/boards.cpp | 7 ------- wirish/stm32f1/boards_setup.cpp | 10 +++++++--- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/wirish/boards.cpp b/wirish/boards.cpp index 471325f..5771df5 100644 --- a/wirish/boards.cpp +++ b/wirish/boards.cpp @@ -75,13 +75,6 @@ void init(void) { boardInit(); } -/* Provide a default no-op series_init() */ -namespace wirish { - namespace priv { - __weak void series_init(void) {} - } -} - /* Provide a default no-op boardInit(). */ __weak void boardInit(void) { } diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index da45730..d224ef2 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -71,9 +71,6 @@ namespace wirish { void board_setup_gpio(void) { gpio_init_all(); - // Initialize AFIO here, too, so peripheral remaps and external - // interrupts work out of the box. - afio_init(); } void board_setup_usb(void) { @@ -81,5 +78,12 @@ namespace wirish { SerialUSB.begin(); #endif } + + void series_init(void) { + // Initialize AFIO here, too, so peripheral remaps and external + // interrupts work out of the box. + afio_init(); + } + } } -- cgit v1.2.3 From b12b8e7c24487c183d73fed4d7848a4bd0e8304a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 15:07:01 -0400 Subject: wirish: Weaken boards_private.h definitions. This lets users override them conveniently if our decisions don't suit. Signed-off-by: Marti Bolivar --- wirish/stm32f1/boards_setup.cpp | 16 +++++++------- wirish/stm32f2/boards_setup.cpp | 48 ++++++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 28 deletions(-) diff --git a/wirish/stm32f1/boards_setup.cpp b/wirish/stm32f1/boards_setup.cpp index d224ef2..11872d5 100644 --- a/wirish/stm32f1/boards_setup.cpp +++ b/wirish/stm32f1/boards_setup.cpp @@ -55,31 +55,31 @@ namespace wirish { namespace priv { static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL}; - rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; - adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6; - adc_smp_rate w_adc_smp = ADC_SMPR_55_5; + __weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; + __weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6; + __weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5; - void board_reset_pll(void) { + __weak void board_reset_pll(void) { // TODO } - void board_setup_clock_prescalers(void) { + __weak void board_setup_clock_prescalers(void) { rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); } - void board_setup_gpio(void) { + __weak void board_setup_gpio(void) { gpio_init_all(); } - void board_setup_usb(void) { + __weak void board_setup_usb(void) { #if BOARD_HAVE_SERIALUSB SerialUSB.begin(); #endif } - void series_init(void) { + __weak void series_init(void) { // Initialize AFIO here, too, so peripheral remaps and external // interrupts work out of the box. afio_init(); diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index 952e84d..876a65b 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -38,6 +38,7 @@ #include #include +#include #include // PLL configuration for 25 MHz external oscillator --> 120 MHz SYSCLK. @@ -50,43 +51,50 @@ static stm32f2_rcc_pll_data pll_data = {PLL_Q, PLL_P, PLL_N, PLL_M}; namespace wirish { namespace priv { // PLL clocked off of HSE, with above configuration data. - rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; - // As f_APB2 = 60 MHz (see board_setup_clock_prescalers), - // we need f_ADC = f_PCLK2 / 2 to get the (maximum) - // f_ADC = 30 MHz. - adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_2; - // With clocks as specified here (i.e. f_ADC = 30 MHz), this - // ADC sample rate allows for error less than 1/4 LSB with a - // 50 KOhm input impedance, assuming an internal sample and - // hold capacitance C_ADC at most 8.8 pF. See Equation 1 and - // Table 61 in the F2 datasheet for more details. - adc_smp_rate w_adc_smp = ADC_SMPR_144; + __weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data}; - void board_reset_pll(void) { + // Global ADC prescaler + // + // On F2, with f_APB2 = 60 MHz, we need f_ADC = f_PCLK2 / 2 to + // get the (maximum) f_ADC = 30 MHz. + __weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_2; + + // Conservative ADC sample rate. Goal is error less than 1/4 + // LSB with 50 KOhm input impedance. + // + // On F2, with f_ADC = 30 MHz, error is acceptable assuming an + // internal sample and hold capacitance C_ADC at most 8.8 pF + // (ST doesn't specify the maximum C_ADC, so we had to take a + // guess). See Equation 1 and Table 61 in the F2 datasheet for + // more details. + __weak adc_smp_rate w_adc_smp = ADC_SMPR_144; + + __weak void board_reset_pll(void) { // Set PLLCFGR to its reset value. RCC_BASE->PLLCFGR = 0x24003010; // FIXME lose the magic number. } - void board_setup_clock_prescalers(void) { - // With f_SYSCLK = 120 MHz (as determined by board_pll_cfg), + __weak void board_setup_clock_prescalers(void) { + // On F2, with f_SYSCLK = 120 MHz (as determined by + // board_pll_cfg), // - // f_AHB = f_SYSCLK / 1 = 120 MHz + // f_AHB = f_SYSCLK / 1 = 120 MHz + // f_APB1 = f_AHB / 4 = 30 MHz + // f_APB2 = f_AHB / 2 = 60 MHz rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); - // f_APB1 = f_AHB / 4 = 30 MHz rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_4); - // f_APB2 = f_AHB / 2 = 60 MHz rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_2); } - void board_setup_gpio(void) { + __weak void board_setup_gpio(void) { gpio_init_all(); } - void board_setup_usb(void) { + __weak void board_setup_usb(void) { // Nothing to do. } - void series_init(void) { + __weak void series_init(void) { // We need SYSCFG for external interrupts syscfg_init(); // Turn on the I/O compensation cell, since we drive the -- cgit v1.2.3 From 89f375949b3df609b489d14b961940e4fed31038 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 15:08:35 -0400 Subject: HardwareSerial.cpp: Fix "#warn" -> "#warning". Signed-off-by: Marti Bolivar --- wirish/HardwareSerial.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/HardwareSerial.cpp b/wirish/HardwareSerial.cpp index 7dccccf..e78156d 100644 --- a/wirish/HardwareSerial.cpp +++ b/wirish/HardwareSerial.cpp @@ -85,7 +85,7 @@ static void disable_timer_if_necessary(timer_dev *dev, uint8 ch) { (STM32_MCU_SERIES == STM32_SERIES_F4) #define disable_timer_if_necessary(dev, ch) ((void)0) #else -#warn "Unsupported STM32 series; timer conflicts are possible" +#warning "Unsupported STM32 series; timer conflicts are possible" #endif void HardwareSerial::begin(uint32 baud) { -- cgit v1.2.3 From bc6d7181b8fe73fb4f7343a6eeec3da9342bc1fc Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 15:23:51 -0400 Subject: stm32.h: Soften "missing MCU" errors into warnings. It's not important whether the MCU is specified. What's important is that gets everything it needs -- which it now ensures that it does. Requiring people to do things on a per-MCU basis hurts hackability and is just asking for trouble. On the other hand, it's nice to provide a clue as to why might be giving #errors, so do leave the warnings. People can always hack the header to shut them up if they want. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/stm32.h | 3 +-- libmaple/stm32f2/include/series/stm32.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index e793a10..f6e96f8 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -99,8 +99,7 @@ extern "C" { # define STM32_MEDIUM_DENSITY #else -#error "Unrecognized STM32F1 MCU, or no MCU specified. Add something like " \ - "-DMCU_STM32F103RB to your compiler arguments." +#warning "Unsupported or unspecified STM32F1 MCU." #endif /* diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h index 2c389ab..180ab30 100644 --- a/libmaple/stm32f2/include/series/stm32.h +++ b/libmaple/stm32f2/include/series/stm32.h @@ -67,7 +67,7 @@ extern "C" { # define STM32_TIMER_MASK 0x7FFE /* TIMER1-TIMER14. */ # define STM32_SRAM_END ((void*)0x20020000) #else -#error "Unrecognized STM32F2 MCU, or no MCU specified." +#warning "Unsupported or unspecified STM32F2 MCU." #endif #ifdef __cplusplus -- cgit v1.2.3 From 221a3eb9aa5bb8318c4c2cafabd4cb4a9db2eea2 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 15:38:22 -0400 Subject: Makefile: move the fake VID/PID, to hide our shame. Signed-off-by: Marti Bolivar --- Makefile | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index e3a1e4f..56a8f50 100644 --- a/Makefile +++ b/Makefile @@ -20,10 +20,6 @@ LDDIR := $(SUPPORT_PATH)/ld # Support files for this Makefile MAKEDIR := $(SUPPORT_PATH)/make -# USB ID for DFU upload -VENDOR_ID := 1EAF -PRODUCT_ID := 0003 - ## ## Target-specific configuration. This determines some compiler and ## linker options/flags. @@ -99,12 +95,15 @@ include $(SRCROOT)/build-targets.mk .PHONY: install sketch clean help debug cscope tags ctags ram flash jtag doxygen mrproper # Target upload commands +# USB ID for DFU upload -- FIXME: do something smarter with this +BOARD_USB_VENDOR_ID := 1EAF +BOARD_USB_PRODUCT_ID := 0003 UPLOAD_ram := $(SUPPORT_PATH)/scripts/reset.py && \ sleep 1 && \ - $(DFU) -a0 -d $(VENDOR_ID):$(PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R + $(DFU) -a0 -d $(BOARD_USB_VENDOR_ID):$(BOARD_USB_PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R UPLOAD_flash := $(SUPPORT_PATH)/scripts/reset.py && \ sleep 1 && \ - $(DFU) -a1 -d $(VENDOR_ID):$(PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R + $(DFU) -a1 -d $(BOARD_USB_VENDOR_ID):$(BOARD_USB_PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R UPLOAD_jtag := $(OPENOCD_WRAPPER) flash # Conditionally upload to whatever the last build was -- cgit v1.2.3 From adbbbc19369f64d64f72d9417a0bf0272d1ba497 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 17:50:18 -0400 Subject: STM32F2: Allow boards to override PLL configuration. Signed-off-by: Marti Bolivar --- wirish/stm32f2/boards_setup.cpp | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index 876a65b..dd872d3 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -40,13 +40,27 @@ #include #include #include +#include -// PLL configuration for 25 MHz external oscillator --> 120 MHz SYSCLK. -#define PLL_Q 5 -#define PLL_P 2 -#define PLL_N 240 -#define PLL_M 25 -static stm32f2_rcc_pll_data pll_data = {PLL_Q, PLL_P, PLL_N, PLL_M}; +// PLL config for 25 MHz external crystal --> 120 MHz SYSCLK, with +// 48 MHz PLL48CK. +#ifndef BOARD_PLL_Q +#define BOARD_PLL_Q 5 +#endif +#ifndef BOARD_PLL_P +#define BOARD_PLL_P 2 +#endif +#ifndef BOARD_PLL_N +#define BOARD_PLL_N 240 +#endif +#ifndef BOARD_PLL_M +#define BOARD_PLL_M 25 +#endif + +static stm32f2_rcc_pll_data pll_data = {BOARD_PLL_Q, + BOARD_PLL_P, + BOARD_PLL_N, + BOARD_PLL_M}; namespace wirish { namespace priv { -- cgit v1.2.3 From ab6814b687a670475fcf9be2be2af30f72904320 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 17:59:14 -0400 Subject: wirish/boards.h: Optionally derive SYSTICK_RELOAD_VAL. It's stupid to make everyone keep this around. Signed-off-by: Marti Bolivar --- wirish/include/wirish/boards.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index 1375512..73d5509 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -113,6 +113,9 @@ bool boardUsesPin(uint8 pin); /* Set derived definitions */ #define CLOCK_SPEED_MHZ CYCLES_PER_MICROSECOND #define CLOCK_SPEED_HZ (CLOCK_SPEED_MHZ * 1000000UL) +#ifndef SYSTICK_RELOAD_VAL +#define SYSTICK_RELOAD_VAL (1000 * CYCLES_PER_MICROSECOND - 1) +#endif /** * @brief Does the board break out a USART/UART's RX and TX pins? -- cgit v1.2.3 From 66167fcf43fabbf33a1ea357954a433cee4a76ff Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 18:11:29 -0400 Subject: : Add BOARD_BUTTON_PRESSED_LEVEL. This allows boards to override the logic level of a pressed button. All Maple boards have a pressed button read HIGH, but if the opposite convention is used, isButtonPressed() will infinite loop. Make isButtonPressed() respect this setting. Signed-off-by: Marti Bolivar --- wirish/include/wirish/boards.h | 10 +++++++++- wirish/wirish_digital.cpp | 4 ++-- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/wirish/include/wirish/boards.h b/wirish/include/wirish/boards.h index 73d5509..6676a02 100644 --- a/wirish/include/wirish/boards.h +++ b/wirish/include/wirish/boards.h @@ -110,13 +110,21 @@ extern void boardInit(void); */ bool boardUsesPin(uint8 pin); -/* Set derived definitions */ +/* + * Derived and default board definitions + */ + #define CLOCK_SPEED_MHZ CYCLES_PER_MICROSECOND #define CLOCK_SPEED_HZ (CLOCK_SPEED_MHZ * 1000000UL) + #ifndef SYSTICK_RELOAD_VAL #define SYSTICK_RELOAD_VAL (1000 * CYCLES_PER_MICROSECOND - 1) #endif +#ifndef BOARD_BUTTON_PRESSED_LEVEL +#define BOARD_BUTTON_PRESSED_LEVEL HIGH +#endif + /** * @brief Does the board break out a USART/UART's RX and TX pins? * diff --git a/wirish/wirish_digital.cpp b/wirish/wirish_digital.cpp index a7f10cd..05ce756 100644 --- a/wirish/wirish_digital.cpp +++ b/wirish/wirish_digital.cpp @@ -65,9 +65,9 @@ void togglePin(uint8 pin) { #define BUTTON_DEBOUNCE_DELAY 1 uint8 isButtonPressed() { - if (digitalRead(BOARD_BUTTON_PIN)) { + if (digitalRead(BOARD_BUTTON_PIN) == BOARD_BUTTON_PRESSED_LEVEL) { delay(BUTTON_DEBOUNCE_DELAY); - while (digitalRead(BOARD_BUTTON_PIN)) + while (digitalRead(BOARD_BUTTON_PIN) == BOARD_BUTTON_PRESSED_LEVEL) ; return true; } -- cgit v1.2.3 From 947caf8be9d94713d012443f950e148f8fa6e7c8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 18:13:20 -0400 Subject: isButtonPressed(): Take a pin and pressedLevel argument. This allows dealing with push-buttons on pins other than BOARD_BUTTON_PIN. Signed-off-by: Marti Bolivar --- wirish/include/wirish/io.h | 3 ++- wirish/wirish_digital.cpp | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/wirish/include/wirish/io.h b/wirish/include/wirish/io.h index b5fe3a8..08bbc06 100644 --- a/wirish/include/wirish/io.h +++ b/wirish/include/wirish/io.h @@ -181,7 +181,8 @@ static inline void toggleLED() { * * @see pinMode() */ -uint8 isButtonPressed(); +uint8 isButtonPressed(uint8 pin=BOARD_BUTTON_PIN, + uint32 pressedLevel=BOARD_BUTTON_PRESSED_LEVEL); /** * Wait until the button is pressed and released, timing out if no diff --git a/wirish/wirish_digital.cpp b/wirish/wirish_digital.cpp index 05ce756..2711a33 100644 --- a/wirish/wirish_digital.cpp +++ b/wirish/wirish_digital.cpp @@ -64,10 +64,10 @@ void togglePin(uint8 pin) { #define BUTTON_DEBOUNCE_DELAY 1 -uint8 isButtonPressed() { - if (digitalRead(BOARD_BUTTON_PIN) == BOARD_BUTTON_PRESSED_LEVEL) { +uint8 isButtonPressed(uint8 pin, uint32 pressedLevel) { + if (digitalRead(pin) == pressedLevel) { delay(BUTTON_DEBOUNCE_DELAY); - while (digitalRead(BOARD_BUTTON_PIN) == BOARD_BUTTON_PRESSED_LEVEL) + while (digitalRead(pin) == pressedLevel) ; return true; } -- cgit v1.2.3 From da4403052cf884c501f27f3b7be0252fa89d5d7a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 18:41:10 -0400 Subject: maple/board.cpp: Add more explanatory comments. Signed-off-by: Marti Bolivar --- wirish/boards/maple/board.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/wirish/boards/maple/board.cpp b/wirish/boards/maple/board.cpp index 256bb90..26c47b7 100644 --- a/wirish/boards/maple/board.cpp +++ b/wirish/boards/maple/board.cpp @@ -36,9 +36,19 @@ #include #include +// boardInit(): nothing special to do for Maple. +// +// When defining your own board.cpp, you can put extra code in this +// function if you have anything you want done on reset, before main() +// or setup() are called. void boardInit(void) { } +// Pin map: this lets the basic I/O functions (digitalWrite(), +// analogRead(), pwmWrite()) translate from pin numbers to STM32 +// peripherals. +// +// See for what goes in an stm32_pin_info. extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { /* Top header */ @@ -98,14 +108,20 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D43/PB4 */ }; +// Array of pins you can use for pwmWrite(). Keep it in Flash because +// it doesn't change, and so we don't waste RAM. extern const uint8 boardPWMPins[] __FLASH__ = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 27, 28 }; +// Array of pins you can use for analogRead(). extern const uint8 boardADCPins[] __FLASH__ = { 0, 1, 2, 3, 10, 11, 12, 15, 16, 17, 18, 19, 20, 27, 28 }; +// Array of pins that the board uses for something special. Other than +// the button and the LED, it's usually best to leave these pins alone +// unless you know what you're doing. extern const uint8 boardUsedPins[] __FLASH__ = { BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN -- cgit v1.2.3 From 645f2217d5a318312132655324ddfc3464bf4d0f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 18:44:58 -0400 Subject: board_private.h: Add PMAP_ROW() convenience macro. Signed-off-by: Marti Bolivar --- wirish/boards_private.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/wirish/boards_private.h b/wirish/boards_private.h index 4607913..49867ca 100644 --- a/wirish/boards_private.h +++ b/wirish/boards_private.h @@ -40,6 +40,10 @@ #include #include +/* Makes the PIN_MAP rows more human-readable. */ +#define PMAP_ROW(gpio_dev, gpio_bit, timer_dev, timer_ch, adc_dev, adc_ch) \ + { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch } + namespace wirish { namespace priv { -- cgit v1.2.3 From 03722806311d8646cbce46ca6bb2543c56cab56e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 18:51:01 -0400 Subject: maple/board.cpp: Use PMAP_ROW(). Signed-off-by: Marti Bolivar --- wirish/boards/maple/board.cpp | 100 +++++++++++++++++++++++------------------- 1 file changed, 55 insertions(+), 45 deletions(-) diff --git a/wirish/boards/maple/board.cpp b/wirish/boards/maple/board.cpp index 26c47b7..1f0e141 100644 --- a/wirish/boards/maple/board.cpp +++ b/wirish/boards/maple/board.cpp @@ -36,6 +36,8 @@ #include #include +#include "boards_private.h" // for PMAP_ROW() + // boardInit(): nothing special to do for Maple. // // When defining your own board.cpp, you can put extra code in this @@ -48,64 +50,72 @@ void boardInit(void) { // analogRead(), pwmWrite()) translate from pin numbers to STM32 // peripherals. // -// See for what goes in an stm32_pin_info. +// PMAP_ROW() lets us specify a row (really a struct stm32_pin_info) +// in the pin map. Its arguments are: +// +// - GPIO device for the pin (GPIOA, etc.) +// - GPIO bit for the pin (0 through 15) +// - Timer device, or NULL if none +// - Timer channel (1 to 4, for PWM), or 0 if none +// - ADC device, or NULL if none +// - ADC channel, or ADCx if none extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { /* Top header */ - {GPIOA, TIMER2, ADC1, 3, 4, 3}, /* D0/PA3 */ - {GPIOA, TIMER2, ADC1, 2, 3, 2}, /* D1/PA2 */ - {GPIOA, TIMER2, ADC1, 0, 1, 0}, /* D2/PA0 */ - {GPIOA, TIMER2, ADC1, 1, 2, 1}, /* D3/PA1 */ - {GPIOB, NULL, NULL, 5, 0, ADCx}, /* D4/PB5 */ - {GPIOB, TIMER4, NULL, 6, 1, ADCx}, /* D5/PB6 */ - {GPIOA, TIMER1, NULL, 8, 1, ADCx}, /* D6/PA8 */ - {GPIOA, TIMER1, NULL, 9, 2, ADCx}, /* D7/PA9 */ - {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D8/PA10 */ - {GPIOB, TIMER4, NULL, 7, 2, ADCx}, /* D9/PB7 */ - {GPIOA, NULL, ADC1, 4, 0, 4}, /* D10/PA4 */ - {GPIOA, TIMER3, ADC1, 7, 2, 7}, /* D11/PA7 */ - {GPIOA, TIMER3, ADC1, 6, 1, 6}, /* D12/PA6 */ - {GPIOA, NULL, ADC1, 5, 0, 5}, /* D13/PA5 (LED) */ - {GPIOB, TIMER4, NULL, 8, 3, ADCx}, /* D14/PB8 */ + PMAP_ROW(GPIOA, 3, TIMER2, 4, ADC1, 3), /* D0/PA3 */ + PMAP_ROW(GPIOA, 2, TIMER2, 3, ADC1, 2), /* D1/PA2 */ + PMAP_ROW(GPIOA, 0, TIMER2, 1, ADC1, 0), /* D2/PA0 */ + PMAP_ROW(GPIOA, 1, TIMER2, 2, ADC1, 1), /* D3/PA1 */ + PMAP_ROW(GPIOB, 5, NULL, 0, NULL, ADCx), /* D4/PB5 */ + PMAP_ROW(GPIOB, 6, TIMER4, 1, NULL, ADCx), /* D5/PB6 */ + PMAP_ROW(GPIOA, 8, TIMER1, 1, NULL, ADCx), /* D6/PA8 */ + PMAP_ROW(GPIOA, 9, TIMER1, 2, NULL, ADCx), /* D7/PA9 */ + PMAP_ROW(GPIOA, 10, TIMER1, 3, NULL, ADCx), /* D8/PA10 */ + PMAP_ROW(GPIOB, 7, TIMER4, 2, NULL, ADCx), /* D9/PB7 */ + PMAP_ROW(GPIOA, 4, NULL, 0, ADC1, 4), /* D10/PA4 */ + PMAP_ROW(GPIOA, 7, TIMER3, 2, ADC1, 7), /* D11/PA7 */ + PMAP_ROW(GPIOA, 6, TIMER3, 1, ADC1, 6), /* D12/PA6 */ + PMAP_ROW(GPIOA, 5, NULL, 0, ADC1, 5), /* D13/PA5 (LED) */ + PMAP_ROW(GPIOB, 8, TIMER4, 3, NULL, ADCx), /* D14/PB8 */ /* Little header */ - {GPIOC, NULL, ADC1, 0, 0, 10}, /* D15/PC0 */ - {GPIOC, NULL, ADC1, 1, 0, 11}, /* D16/PC1 */ - {GPIOC, NULL, ADC1, 2, 0, 12}, /* D17/PC2 */ - {GPIOC, NULL, ADC1, 3, 0, 13}, /* D18/PC3 */ - {GPIOC, NULL, ADC1, 4, 0, 14}, /* D19/PC4 */ - {GPIOC, NULL, ADC1, 5, 0, 15}, /* D20/PC5 */ + PMAP_ROW(GPIOC, 0, NULL, 0, ADC1, 10), /* D15/PC0 */ + PMAP_ROW(GPIOC, 1, NULL, 0, ADC1, 11), /* D16/PC1 */ + PMAP_ROW(GPIOC, 2, NULL, 0, ADC1, 12), /* D17/PC2 */ + PMAP_ROW(GPIOC, 3, NULL, 0, ADC1, 13), /* D18/PC3 */ + PMAP_ROW(GPIOC, 4, NULL, 0, ADC1, 14), /* D19/PC4 */ + PMAP_ROW(GPIOC, 5, NULL, 0, ADC1, 15), /* D20/PC5 */ /* External header */ - {GPIOC, NULL, NULL, 13, 0, ADCx}, /* D21/PC13 */ - {GPIOC, NULL, NULL, 14, 0, ADCx}, /* D22/PC14 */ - {GPIOC, NULL, NULL, 15, 0, ADCx}, /* D23/PC15 */ - {GPIOB, TIMER4, NULL, 9, 4, ADCx}, /* D24/PB9 */ - {GPIOD, NULL, NULL, 2, 0, ADCx}, /* D25/PD2 */ - {GPIOC, NULL, NULL, 10, 0, ADCx}, /* D26/PC10 */ - {GPIOB, TIMER3, ADC1, 0, 3, 8}, /* D27/PB0 */ - {GPIOB, TIMER3, ADC1, 1, 4, 9}, /* D28/PB1 */ - {GPIOB, NULL, NULL, 10, 0, ADCx}, /* D29/PB10 */ - {GPIOB, NULL, NULL, 11, 0, ADCx}, /* D30/PB11 */ - {GPIOB, NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */ - {GPIOB, NULL, NULL, 13, 0, ADCx}, /* D32/PB13 */ - {GPIOB, NULL, NULL, 14, 0, ADCx}, /* D33/PB14 */ - {GPIOB, NULL, NULL, 15, 0, ADCx}, /* D34/PB15 */ - {GPIOC, NULL, NULL, 6, 0, ADCx}, /* D35/PC6 */ - {GPIOC, NULL, NULL, 7, 0, ADCx}, /* D36/PC7 */ - {GPIOC, NULL, NULL, 8, 0, ADCx}, /* D37/PC8 */ - {GPIOC, NULL, NULL, 9, 0, ADCx}, /* D38/PC9 (BUT) */ + PMAP_ROW(GPIOC, 13, NULL, 0, NULL, ADCx), /* D21/PC13 */ + PMAP_ROW(GPIOC, 14, NULL, 0, NULL, ADCx), /* D22/PC14 */ + PMAP_ROW(GPIOC, 15, NULL, 0, NULL, ADCx), /* D23/PC15 */ + PMAP_ROW(GPIOB, 9, TIMER4, 4, NULL, ADCx), /* D24/PB9 */ + PMAP_ROW(GPIOD, 2, NULL, 0, NULL, ADCx), /* D25/PD2 */ + PMAP_ROW(GPIOC, 10, NULL, 0, NULL, ADCx), /* D26/PC10 */ + PMAP_ROW(GPIOB, 0, TIMER3, 3, ADC1, 8), /* D27/PB0 */ + PMAP_ROW(GPIOB, 1, TIMER3, 4, ADC1, 9), /* D28/PB1 */ + PMAP_ROW(GPIOB, 10, NULL, 0, NULL, ADCx), /* D29/PB10 */ + PMAP_ROW(GPIOB, 11, NULL, 0, NULL, ADCx), /* D30/PB11 */ + PMAP_ROW(GPIOB, 12, NULL, 0, NULL, ADCx), /* D31/PB12 */ + PMAP_ROW(GPIOB, 13, NULL, 0, NULL, ADCx), /* D32/PB13 */ + PMAP_ROW(GPIOB, 14, NULL, 0, NULL, ADCx), /* D33/PB14 */ + PMAP_ROW(GPIOB, 15, NULL, 0, NULL, ADCx), /* D34/PB15 */ + PMAP_ROW(GPIOC, 6, NULL, 0, NULL, ADCx), /* D35/PC6 */ + PMAP_ROW(GPIOC, 7, NULL, 0, NULL, ADCx), /* D36/PC7 */ + PMAP_ROW(GPIOC, 8, NULL, 0, NULL, ADCx), /* D37/PC8 */ + PMAP_ROW(GPIOC, 9, NULL, 0, NULL, ADCx), /* D38/PC9 (BUT) */ /* JTAG header */ - {GPIOA, NULL, NULL, 13, 0, ADCx}, /* D39/PA13 */ - {GPIOA, NULL, NULL, 14, 0, ADCx}, /* D40/PA14 */ - {GPIOA, NULL, NULL, 15, 0, ADCx}, /* D41/PA15 */ - {GPIOB, NULL, NULL, 3, 0, ADCx}, /* D42/PB3 */ - {GPIOB, NULL, NULL, 4, 0, ADCx}, /* D43/PB4 */ + PMAP_ROW(GPIOA, 13, NULL, 0, NULL, ADCx), /* D39/PA13 */ + PMAP_ROW(GPIOA, 14, NULL, 0, NULL, ADCx), /* D40/PA14 */ + PMAP_ROW(GPIOA, 15, NULL, 0, NULL, ADCx), /* D41/PA15 */ + PMAP_ROW(GPIOB, 3, NULL, 0, NULL, ADCx), /* D42/PB3 */ + PMAP_ROW(GPIOB, 4, NULL, 0, NULL, ADCx), /* D43/PB4 */ }; // Array of pins you can use for pwmWrite(). Keep it in Flash because -- cgit v1.2.3 From 9d5c8a6b9a880db7d41fdd0fcf29f7d0eac823fd Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 5 Jun 2012 18:52:33 -0400 Subject: maple/board.cpp: Demo weakness of boardInit(). This shows people what to do to write boardInit(), but also how to save work if they don't need it. Signed-off-by: Marti Bolivar --- wirish/boards/maple/board.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/wirish/boards/maple/board.cpp b/wirish/boards/maple/board.cpp index 1f0e141..42c847b 100644 --- a/wirish/boards/maple/board.cpp +++ b/wirish/boards/maple/board.cpp @@ -43,8 +43,13 @@ // When defining your own board.cpp, you can put extra code in this // function if you have anything you want done on reset, before main() // or setup() are called. +// +// If there's nothing special you need done, feel free to leave this +// function out, as we do here. +/* void boardInit(void) { } +*/ // Pin map: this lets the basic I/O functions (digitalWrite(), // analogRead(), pwmWrite()) translate from pin numbers to STM32 -- cgit v1.2.3 From 8652d6c517d18422a4e02fdc125c7b13787af709 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 01:18:01 -0400 Subject: Makefile: add list-boards target. As the number of boards increases, it's less practical to keep a list of them in the help target output (notice also that some have been forgotten). This target can't get out of date unless we change how the board-includes/ directory works. Signed-off-by: Marti Bolivar --- Makefile | 7 ++++++- support/make/target-config.mk | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 56a8f50..313cf94 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,7 @@ SUPPORT_PATH := $(SRCROOT)/support LDDIR := $(SUPPORT_PATH)/ld # Support files for this Makefile MAKEDIR := $(SUPPORT_PATH)/make +BOARD_INCLUDE_DIR := $(MAKEDIR)/board-includes ## ## Target-specific configuration. This determines some compiler and @@ -92,7 +93,7 @@ $(foreach m,$(LIBMAPLE_MODULES),$(eval $(call LIBMAPLE_MODULE_template,$(m)))) # main target include $(SRCROOT)/build-targets.mk -.PHONY: install sketch clean help debug cscope tags ctags ram flash jtag doxygen mrproper +.PHONY: install sketch clean help debug cscope tags ctags ram flash jtag doxygen mrproper list-boards # Target upload commands # USB ID for DFU upload -- FIXME: do something smarter with this @@ -182,3 +183,7 @@ jtag: doxygen: doxygen $(SUPPORT_PATH)/doxygen/Doxyfile + +# This output is kind of ugly, but I don't understand make very well. +list-boards: + @echo " $(addsuffix "\\n",$(basename $(notdir $(wildcard $(BOARD_INCLUDE_DIR)/*.mk))))" diff --git a/support/make/target-config.mk b/support/make/target-config.mk index e13504d..a04ca38 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -5,7 +5,7 @@ TARGET_FLAGS := # Board-specific configuration values. Punt these to board-specific # include files. -include $(MAKEDIR)/board-includes/$(BOARD).mk +include $(BOARD_INCLUDE_DIR)/$(BOARD).mk TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ -DERROR_LED_PORT=$(ERROR_LED_PORT) \ -- cgit v1.2.3 From 421e49046cddf786b20db35f76c2bf6edcd39ef3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 01:19:24 -0400 Subject: Makefile: make help target more helpful. Signed-off-by: Marti Bolivar --- Makefile | 52 ++++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/Makefile b/Makefile index 313cf94..833799b 100644 --- a/Makefile +++ b/Makefile @@ -130,32 +130,32 @@ mrproper: clean help: @echo "" - @echo " libmaple Makefile help" - @echo " ----------------------" - @echo " " - @echo " Programming targets:" - @echo " sketch: Compile for BOARD to MEMORY_TARGET (default)." - @echo " install: Compile and upload code over USB, using Maple bootloader" - @echo " " - @echo " You *must* set BOARD if not compiling for Maple (e.g." - @echo " use BOARD=maple_mini for mini, etc.), and MEMORY_TARGET" - @echo " if not compiling to Flash." - @echo " " - @echo " Valid BOARDs:" - @echo " maple, maple_mini, maple_RET6, maple_native" - @echo " " - @echo " Valid MEMORY_TARGETs (default=flash):" - @echo " ram: Compile sketch code to ram" - @echo " flash: Compile sketch code to flash" - @echo " jtag: Compile sketch code for jtag; overwrites bootloader" - @echo " " - @echo " Other targets:" - @echo " debug: Start OpenOCD gdb server on port 3333, telnet on port 4444" - @echo " clean: Remove all build and object files" - @echo " help: Show this message" - @echo " doxygen: Build Doxygen HTML and XML documentation" - @echo " mrproper: Remove all generated files" - @echo " " + @echo "Basic usage (BOARD defaults to maple):" + @echo " $$ cp your-main.cpp main.cpp" + @echo " $$ make BOARD=your_board" + @echo " $$ make BOARD=your_board install" + @echo "" + @echo "Important targets:" + @echo " sketch: Compile for BOARD to MEMORY_TARGET (default)." + @echo " install: Compile and upload over USB using Maple bootloader" + @echo "" + @echo "You *must* set BOARD if not compiling for Maple (e.g." + @echo "use BOARD=maple_mini for mini, etc.), and MEMORY_TARGET" + @echo "if not compiling to Flash. Run \`$$ make list-boards' for" + @echo "a list of all boards." + @echo "" + @echo "Valid MEMORY_TARGETs (default=flash):" + @echo " ram: Compile to RAM (doesn't touch Flash)" + @echo " flash: Compile to Flash (for Maple bootloader)" + @echo " jtag: Compile for JTAG/SWD upload (overwrites bootloader)" + @echo "" + @echo "Other targets:" + @echo " debug: Start OpenOCD gdb server on port 3333, telnet on port 4444" + @echo " clean: Remove all build and object files" + @echo " help: Show this message" + @echo " doxygen: Build Doxygen HTML and XML documentation" + @echo " mrproper: Remove all generated files" + @echo "" debug: $(OPENOCD_WRAPPER) debug -- cgit v1.2.3 From 42570013c5266449f7e8512a77fe66b8e852294d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 01:24:01 -0400 Subject: Move OpenOCD stuff into contrib/. This has gone unmaintained for long enough. Signed-off-by: Marti Bolivar --- Makefile | 7 +-- contrib/openocd/debug_0.3.cfg | 75 ++++++++++++++++++++++++++++++ contrib/openocd/debug_0.4.cfg | 75 ++++++++++++++++++++++++++++++ contrib/openocd/flash_0.3.cfg | 89 +++++++++++++++++++++++++++++++++++ contrib/openocd/flash_0.4.cfg | 95 ++++++++++++++++++++++++++++++++++++++ contrib/openocd/openocd-wrapper.sh | 16 +++++++ support/make/build-rules.mk | 1 - support/openocd/debug_0.3.cfg | 75 ------------------------------ support/openocd/debug_0.4.cfg | 75 ------------------------------ support/openocd/flash_0.3.cfg | 89 ----------------------------------- support/openocd/flash_0.4.cfg | 95 -------------------------------------- support/scripts/openocd-wrapper.sh | 16 ------- 12 files changed, 351 insertions(+), 357 deletions(-) create mode 100644 contrib/openocd/debug_0.3.cfg create mode 100644 contrib/openocd/debug_0.4.cfg create mode 100644 contrib/openocd/flash_0.3.cfg create mode 100644 contrib/openocd/flash_0.4.cfg create mode 100755 contrib/openocd/openocd-wrapper.sh delete mode 100644 support/openocd/debug_0.3.cfg delete mode 100644 support/openocd/debug_0.4.cfg delete mode 100644 support/openocd/flash_0.3.cfg delete mode 100644 support/openocd/flash_0.4.cfg delete mode 100755 support/scripts/openocd-wrapper.sh diff --git a/Makefile b/Makefile index 833799b..27e0ac8 100644 --- a/Makefile +++ b/Makefile @@ -93,7 +93,7 @@ $(foreach m,$(LIBMAPLE_MODULES),$(eval $(call LIBMAPLE_MODULE_template,$(m)))) # main target include $(SRCROOT)/build-targets.mk -.PHONY: install sketch clean help debug cscope tags ctags ram flash jtag doxygen mrproper list-boards +.PHONY: install sketch clean help cscope tags ctags ram flash jtag doxygen mrproper list-boards # Target upload commands # USB ID for DFU upload -- FIXME: do something smarter with this @@ -105,7 +105,6 @@ UPLOAD_ram := $(SUPPORT_PATH)/scripts/reset.py && \ UPLOAD_flash := $(SUPPORT_PATH)/scripts/reset.py && \ sleep 1 && \ $(DFU) -a1 -d $(BOARD_USB_VENDOR_ID):$(BOARD_USB_PRODUCT_ID) -D $(BUILD_PATH)/$(BOARD).bin -R -UPLOAD_jtag := $(OPENOCD_WRAPPER) flash # Conditionally upload to whatever the last build was install: INSTALL_TARGET = $(shell cat $(BUILD_PATH)/build-type 2>/dev/null) @@ -150,16 +149,12 @@ help: @echo " jtag: Compile for JTAG/SWD upload (overwrites bootloader)" @echo "" @echo "Other targets:" - @echo " debug: Start OpenOCD gdb server on port 3333, telnet on port 4444" @echo " clean: Remove all build and object files" @echo " help: Show this message" @echo " doxygen: Build Doxygen HTML and XML documentation" @echo " mrproper: Remove all generated files" @echo "" -debug: - $(OPENOCD_WRAPPER) debug - cscope: rm -rf *.cscope find . -name '*.[hcS]' -o -name '*.cpp' | xargs cscope -b diff --git a/contrib/openocd/debug_0.3.cfg b/contrib/openocd/debug_0.3.cfg new file mode 100644 index 0000000..87d33ae --- /dev/null +++ b/contrib/openocd/debug_0.3.cfg @@ -0,0 +1,75 @@ +# script for stm32 + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 30.6.3 + set _CPUTAPID 0x3ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + # High density devices, Rev A + set _BSTAPID4 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID5 0x06418041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 + + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 + +flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME + +proc nopforever {} { + puts "Resetting the chip..." + reset run +} + +init +nopforever diff --git a/contrib/openocd/debug_0.4.cfg b/contrib/openocd/debug_0.4.cfg new file mode 100644 index 0000000..7d6982a --- /dev/null +++ b/contrib/openocd/debug_0.4.cfg @@ -0,0 +1,75 @@ +# script for stm32 + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 30.6.3 + set _CPUTAPID 0x3ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + # High density devices, Rev A + set _BSTAPID4 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID5 0x06418041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 + + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 + +flash bank bank0 stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME + +proc nopforever {} { + puts "Resetting the chip... Halting for debugger." + reset halt +} + +init +nopforever diff --git a/contrib/openocd/flash_0.3.cfg b/contrib/openocd/flash_0.3.cfg new file mode 100644 index 0000000..41c6532 --- /dev/null +++ b/contrib/openocd/flash_0.3.cfg @@ -0,0 +1,89 @@ +# script for stm32 + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 30.6.3 + set _CPUTAPID 0x3ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + # High density devices, Rev A + set _BSTAPID4 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID5 0x06418041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 + + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 +# TODO: native +#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 + +flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME + +proc flash_chip {} { + echo "Halting..." + halt + echo "Erasing..." + flash erase_address 0x08000000 0x20000 + # TODO: native + #flash erase_address 0x08000000 0x80000 + echo "Flashing image..." + flash write_bank 0 build/maple.bin 0 + echo "Verifying image..." + verify_image build/maple.bin 0x08000000 bin + echo "Checksum verified, resetting chip" + reset run + echo "Daemon shutdown" + shutdown +} + +init +flash_chip diff --git a/contrib/openocd/flash_0.4.cfg b/contrib/openocd/flash_0.4.cfg new file mode 100644 index 0000000..32c06c6 --- /dev/null +++ b/contrib/openocd/flash_0.4.cfg @@ -0,0 +1,95 @@ +# script for stm32 + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 30.6.3 + set _CPUTAPID 0x3ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + # High density devices, Rev A + set _BSTAPID4 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID5 0x06418041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 + + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 +# TODO: native +#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 + +flash bank bank0 stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME + +proc flash_chip {} { + echo "Halting..." + reset halt + + echo "Unlocking flash..." + flash protect 0 0 last off + + echo "Erasing..." + flash erase_address 0x08000000 0x20000 + + echo "Flashing image..." + flash write_bank 0 build/maple.bin 0 + + echo "Verifying image..." + verify_image build/maple.bin 0x08000000 bin + + echo "Checksum verified, resetting chip" + reset run + + echo "Daemon shutdown" + shutdown +} + +init +flash_chip diff --git a/contrib/openocd/openocd-wrapper.sh b/contrib/openocd/openocd-wrapper.sh new file mode 100755 index 0000000..73be92e --- /dev/null +++ b/contrib/openocd/openocd-wrapper.sh @@ -0,0 +1,16 @@ +#!/usr/bin/env bash + +# Helper to decide which openocd script to use. We only support 0.3.x and 0.4.x. + +if [ $# -ne 1 ] +then + echo "Usage: `basename $0` {flash|debug}" + exit 1 +fi + +OPENOCD_VERSION=`openocd -v 2>&1 | head -n1 | \ + awk '{print $4}' | sed 's/\([0-9]*\.[0-9]*\)\.[0-9]*/\1/'` + +CFG_FILE=$1_${OPENOCD_VERSION}.cfg + +openocd -f support/openocd/$CFG_FILE diff --git a/support/make/build-rules.mk b/support/make/build-rules.mk index 330cdd8..3d541ba 100644 --- a/support/make/build-rules.mk +++ b/support/make/build-rules.mk @@ -9,7 +9,6 @@ DISAS := arm-none-eabi-objdump OBJDUMP := arm-none-eabi-objdump SIZE := arm-none-eabi-size DFU := dfu-util -OPENOCD_WRAPPER := support/scripts/openocd-wrapper.sh # Suppress annoying output unless V is set ifndef V diff --git a/support/openocd/debug_0.3.cfg b/support/openocd/debug_0.3.cfg deleted file mode 100644 index 87d33ae..0000000 --- a/support/openocd/debug_0.3.cfg +++ /dev/null @@ -1,75 +0,0 @@ -# script for stm32 - -interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG" -ft2232_layout olimex-jtag -ft2232_vid_pid 0x15ba 0x0003 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz -jtag_khz 1000 - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst - -#jtag scan chain -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0008 - # Section 30.6.3 - set _CPUTAPID 0x3ba00477 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID ] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0008 - # Section 29.6.2 - # Low density devices, Rev A - set _BSTAPID1 0x06412041 - # Medium density devices, Rev A - set _BSTAPID2 0x06410041 - # Medium density devices, Rev B and Rev Z - set _BSTAPID3 0x16410041 - # High density devices, Rev A - set _BSTAPID4 0x06414041 - # Connectivity line devices, Rev A and Rev Z - set _BSTAPID5 0x06418041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 - - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 - -flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME - -proc nopforever {} { - puts "Resetting the chip..." - reset run -} - -init -nopforever diff --git a/support/openocd/debug_0.4.cfg b/support/openocd/debug_0.4.cfg deleted file mode 100644 index 7d6982a..0000000 --- a/support/openocd/debug_0.4.cfg +++ /dev/null @@ -1,75 +0,0 @@ -# script for stm32 - -interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG" -ft2232_layout olimex-jtag -ft2232_vid_pid 0x15ba 0x0003 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz -jtag_khz 1000 - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only - -#jtag scan chain -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0008 - # Section 30.6.3 - set _CPUTAPID 0x3ba00477 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID ] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0008 - # Section 29.6.2 - # Low density devices, Rev A - set _BSTAPID1 0x06412041 - # Medium density devices, Rev A - set _BSTAPID2 0x06410041 - # Medium density devices, Rev B and Rev Z - set _BSTAPID3 0x16410041 - # High density devices, Rev A - set _BSTAPID4 0x06414041 - # Connectivity line devices, Rev A and Rev Z - set _BSTAPID5 0x06418041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 - - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 - -flash bank bank0 stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME - -proc nopforever {} { - puts "Resetting the chip... Halting for debugger." - reset halt -} - -init -nopforever diff --git a/support/openocd/flash_0.3.cfg b/support/openocd/flash_0.3.cfg deleted file mode 100644 index 41c6532..0000000 --- a/support/openocd/flash_0.3.cfg +++ /dev/null @@ -1,89 +0,0 @@ -# script for stm32 - -interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG" -ft2232_layout olimex-jtag -ft2232_vid_pid 0x15ba 0x0003 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz -jtag_khz 1000 - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst - -#jtag scan chain -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0008 - # Section 30.6.3 - set _CPUTAPID 0x3ba00477 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID ] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0008 - # Section 29.6.2 - # Low density devices, Rev A - set _BSTAPID1 0x06412041 - # Medium density devices, Rev A - set _BSTAPID2 0x06410041 - # Medium density devices, Rev B and Rev Z - set _BSTAPID3 0x16410041 - # High density devices, Rev A - set _BSTAPID4 0x06414041 - # Connectivity line devices, Rev A and Rev Z - set _BSTAPID5 0x06418041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 - - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 -# TODO: native -#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 - -flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME - -proc flash_chip {} { - echo "Halting..." - halt - echo "Erasing..." - flash erase_address 0x08000000 0x20000 - # TODO: native - #flash erase_address 0x08000000 0x80000 - echo "Flashing image..." - flash write_bank 0 build/maple.bin 0 - echo "Verifying image..." - verify_image build/maple.bin 0x08000000 bin - echo "Checksum verified, resetting chip" - reset run - echo "Daemon shutdown" - shutdown -} - -init -flash_chip diff --git a/support/openocd/flash_0.4.cfg b/support/openocd/flash_0.4.cfg deleted file mode 100644 index 32c06c6..0000000 --- a/support/openocd/flash_0.4.cfg +++ /dev/null @@ -1,95 +0,0 @@ -# script for stm32 - -interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG" -ft2232_layout olimex-jtag -ft2232_vid_pid 0x15ba 0x0003 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz -jtag_khz 1000 - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only - -#jtag scan chain -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0008 - # Section 30.6.3 - set _CPUTAPID 0x3ba00477 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID ] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0008 - # Section 29.6.2 - # Low density devices, Rev A - set _BSTAPID1 0x06412041 - # Medium density devices, Rev A - set _BSTAPID2 0x06410041 - # Medium density devices, Rev B and Rev Z - set _BSTAPID3 0x16410041 - # High density devices, Rev A - set _BSTAPID4 0x06414041 - # Connectivity line devices, Rev A and Rev Z - set _BSTAPID5 0x06418041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 - - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 -# TODO: native -#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 - -flash bank bank0 stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME - -proc flash_chip {} { - echo "Halting..." - reset halt - - echo "Unlocking flash..." - flash protect 0 0 last off - - echo "Erasing..." - flash erase_address 0x08000000 0x20000 - - echo "Flashing image..." - flash write_bank 0 build/maple.bin 0 - - echo "Verifying image..." - verify_image build/maple.bin 0x08000000 bin - - echo "Checksum verified, resetting chip" - reset run - - echo "Daemon shutdown" - shutdown -} - -init -flash_chip diff --git a/support/scripts/openocd-wrapper.sh b/support/scripts/openocd-wrapper.sh deleted file mode 100755 index 73be92e..0000000 --- a/support/scripts/openocd-wrapper.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env bash - -# Helper to decide which openocd script to use. We only support 0.3.x and 0.4.x. - -if [ $# -ne 1 ] -then - echo "Usage: `basename $0` {flash|debug}" - exit 1 -fi - -OPENOCD_VERSION=`openocd -v 2>&1 | head -n1 | \ - awk '{print $4}' | sed 's/\([0-9]*\.[0-9]*\)\.[0-9]*/\1/'` - -CFG_FILE=$1_${OPENOCD_VERSION}.cfg - -openocd -f support/openocd/$CFG_FILE -- cgit v1.2.3 From 5838b447f675444b154bacd205ebf9f47d003b2f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 6 Jun 2012 18:06:48 -0400 Subject: Rework linker scripts. Having separate linker scripts for all the boards is a bad idea. Most boards really only need to specify MEMORY and the appropriate REGION_ALIASES() so that support/ld/common.inc can do its work. Not having infrastructure for this leads to duplication -- viz. the Maple Mini linker scripts are identical to the Maple's, and the olimex_stm32_h103 linker directory is just a symlink to Maple's. Clearly, the current structure is wrong. To fix it, instead of having per-board subdirectories of support/ld/, add per-MEMORY subdirectories of (new) support/ld/stm32/mem/. The per-board .mk files under support/mk/board-includes/ now reference these directly, and target-config.mk and the Makefile handle this appropriately. We move some other stuff around in target-config.mk to make this all more convenient, and even allow more overriding of the libmaple defaults on a per-board basis. Custom board hacks will be easier now. Unfortunately, lots of duplication under support/ld/stm32/mem/ is necessary, as the LENGTH attribute in a MEMORY region specification doesn't support arithmetic expressions, and ld doesn't seem to have any way to specify MEMORY at the command line (why?!). If we find a better way than this, we should do it. If a board (e.g. Maple Native) _does_ really need special memory-related configuration, you can always put a per-board subdirectory of support/ld/stm32/mem. We do this here to configure the heap. Signed-off-by: Marti Bolivar --- Makefile | 3 +- support/ld/VLDiscovery/flash.ld | 24 ---------- support/ld/VLDiscovery/jtag.ld | 24 ---------- support/ld/VLDiscovery/ram.ld | 22 ---------- support/ld/flash.ld | 26 +++++++++++ support/ld/jtag.ld | 31 +++++++++++++ support/ld/maple/flash.ld | 24 ---------- support/ld/maple/jtag.ld | 24 ---------- support/ld/maple/ram.ld | 22 ---------- support/ld/maple_RET6/flash.ld | 18 -------- support/ld/maple_RET6/jtag.ld | 18 -------- support/ld/maple_RET6/ram.ld | 17 -------- support/ld/maple_mini/flash.ld | 23 ---------- support/ld/maple_mini/jtag.ld | 24 ---------- support/ld/maple_mini/ram.ld | 22 ---------- support/ld/maple_native/flash.ld | 22 ---------- support/ld/maple_native/jtag.ld | 22 ---------- support/ld/maple_native/ram.ld | 20 --------- support/ld/olimex_stm32_h103 | 1 - support/ld/ram.ld | 25 +++++++++++ support/ld/st_stm3220g_eval/jtag.ld | 17 -------- .../stm32/mem/maple_native/maple_native_heap.inc | 3 ++ support/ld/stm32/mem/maple_native/mem-flash.inc | 7 +++ support/ld/stm32/mem/maple_native/mem-jtag.inc | 7 +++ support/ld/stm32/mem/maple_native/mem-ram.inc | 7 +++ .../stm32/mem/sram_112k_flash_1024k/mem-jtag.inc | 5 +++ .../ld/stm32/mem/sram_112k_flash_1024k/mem-ram.inc | 5 +++ .../ld/stm32/mem/sram_20k_flash_128k/mem-flash.inc | 5 +++ .../ld/stm32/mem/sram_20k_flash_128k/mem-jtag.inc | 5 +++ .../ld/stm32/mem/sram_20k_flash_128k/mem-ram.inc | 5 +++ .../ld/stm32/mem/sram_64k_flash_512k/mem-flash.inc | 5 +++ .../ld/stm32/mem/sram_64k_flash_512k/mem-jtag.inc | 5 +++ .../ld/stm32/mem/sram_64k_flash_512k/mem-ram.inc | 5 +++ .../ld/stm32/mem/sram_8k_flash_128k/mem-flash.inc | 5 +++ .../ld/stm32/mem/sram_8k_flash_128k/mem-jtag.inc | 5 +++ .../ld/stm32/mem/sram_8k_flash_128k/mem-ram.inc | 5 +++ support/make/board-includes/VLDiscovery.mk | 1 + support/make/board-includes/maple.mk | 4 ++ support/make/board-includes/maple_RET6.mk | 1 + support/make/board-includes/maple_mini.mk | 1 + support/make/board-includes/maple_native.mk | 1 + support/make/board-includes/olimex_stm32_h103.mk | 1 + support/make/board-includes/st_stm3220g_eval.mk | 1 + support/make/target-config.mk | 51 ++++++++++++---------- 44 files changed, 199 insertions(+), 370 deletions(-) delete mode 100644 support/ld/VLDiscovery/flash.ld delete mode 100644 support/ld/VLDiscovery/jtag.ld delete mode 100644 support/ld/VLDiscovery/ram.ld create mode 100644 support/ld/flash.ld create mode 100644 support/ld/jtag.ld delete mode 100644 support/ld/maple/flash.ld delete mode 100644 support/ld/maple/jtag.ld delete mode 100644 support/ld/maple/ram.ld delete mode 100644 support/ld/maple_RET6/flash.ld delete mode 100644 support/ld/maple_RET6/jtag.ld delete mode 100644 support/ld/maple_RET6/ram.ld delete mode 100644 support/ld/maple_mini/flash.ld delete mode 100644 support/ld/maple_mini/jtag.ld delete mode 100644 support/ld/maple_mini/ram.ld delete mode 100644 support/ld/maple_native/flash.ld delete mode 100644 support/ld/maple_native/jtag.ld delete mode 100644 support/ld/maple_native/ram.ld delete mode 120000 support/ld/olimex_stm32_h103 create mode 100644 support/ld/ram.ld delete mode 100644 support/ld/st_stm3220g_eval/jtag.ld create mode 100644 support/ld/stm32/mem/maple_native/maple_native_heap.inc create mode 100644 support/ld/stm32/mem/maple_native/mem-flash.inc create mode 100644 support/ld/stm32/mem/maple_native/mem-jtag.inc create mode 100644 support/ld/stm32/mem/maple_native/mem-ram.inc create mode 100644 support/ld/stm32/mem/sram_112k_flash_1024k/mem-jtag.inc create mode 100644 support/ld/stm32/mem/sram_112k_flash_1024k/mem-ram.inc create mode 100644 support/ld/stm32/mem/sram_20k_flash_128k/mem-flash.inc create mode 100644 support/ld/stm32/mem/sram_20k_flash_128k/mem-jtag.inc create mode 100644 support/ld/stm32/mem/sram_20k_flash_128k/mem-ram.inc create mode 100644 support/ld/stm32/mem/sram_64k_flash_512k/mem-flash.inc create mode 100644 support/ld/stm32/mem/sram_64k_flash_512k/mem-jtag.inc create mode 100644 support/ld/stm32/mem/sram_64k_flash_512k/mem-ram.inc create mode 100644 support/ld/stm32/mem/sram_8k_flash_128k/mem-flash.inc create mode 100644 support/ld/stm32/mem/sram_8k_flash_128k/mem-jtag.inc create mode 100644 support/ld/stm32/mem/sram_8k_flash_128k/mem-ram.inc diff --git a/Makefile b/Makefile index 27e0ac8..97d65bb 100644 --- a/Makefile +++ b/Makefile @@ -51,8 +51,7 @@ GLOBAL_CFLAGS := -Os -g3 -gdwarf-2 -mcpu=cortex-m3 -mthumb -march=armv7-m \ GLOBAL_CXXFLAGS := -fno-rtti -fno-exceptions -Wall $(TARGET_FLAGS) GLOBAL_ASFLAGS := -mcpu=cortex-m3 -march=armv7-m -mthumb \ -x assembler-with-cpp $(TARGET_FLAGS) -LDFLAGS = -T$(LDDIR)/$(LDSCRIPT) -L$(LDDIR) \ - -mcpu=cortex-m3 -mthumb -Xlinker -L $(LD_SERIES_PATH) \ +LDFLAGS = $(TARGET_LDFLAGS) -mcpu=cortex-m3 -mthumb -Xlinker \ --gc-sections --print-gc-sections --march=armv7-m -Wall ## diff --git a/support/ld/VLDiscovery/flash.ld b/support/ld/VLDiscovery/flash.ld deleted file mode 100644 index 44ff8a1..0000000 --- a/support/ld/VLDiscovery/flash.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* - * VLDiscovery (STM32F100RBT6, medium density) linker script for Flash builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* - * Define the rest of the sections - */ -_FLASH_BUILD = 1; - -INCLUDE common.inc diff --git a/support/ld/VLDiscovery/jtag.ld b/support/ld/VLDiscovery/jtag.ld deleted file mode 100644 index b952572..0000000 --- a/support/ld/VLDiscovery/jtag.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* - * VLDiscovery (STM32F100RBT6, medium density) linker script for JTAG (bare - * metal, no bootloader) builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* - * Define the rest of the sections - */ -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/VLDiscovery/ram.ld b/support/ld/VLDiscovery/ram.ld deleted file mode 100644 index d659cd6..0000000 --- a/support/ld/VLDiscovery/ram.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * VLDiscovery (STM32F100RBT6, medium density) linker script for RAM builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 0K -} - -REGION_ALIAS("REGION_TEXT", ram); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", ram); - -/* - * Define the rest of the sections - */ -INCLUDE common.inc diff --git a/support/ld/flash.ld b/support/ld/flash.ld new file mode 100644 index 0000000..9e250cd --- /dev/null +++ b/support/ld/flash.ld @@ -0,0 +1,26 @@ +/* + * libmaple linker script for "Flash" builds. + * + * A Flash build puts .text (and .rodata) in Flash, and + * .data/.bss/heap (of course) in SRAM, but offsets the sections by + * enough space to store the Maple bootloader, which lives in low + * Flash and uses low memory. + */ + +/* + * This pulls in the appropriate MEMORY declaration from the right + * subdirectory of stm32/mem/ (the environment must call ld with the + * right include directory flags to make this happen). Boards can also + * use this file to use any of libmaple's memory-related hooks (like + * where the heap should live). + */ +INCLUDE mem-flash.inc + +/* Provide memory region aliases for common.inc */ +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", rom); + +/* Let common.inc handle the real work. */ +INCLUDE common.inc diff --git a/support/ld/jtag.ld b/support/ld/jtag.ld new file mode 100644 index 0000000..0612f95 --- /dev/null +++ b/support/ld/jtag.ld @@ -0,0 +1,31 @@ +/* + * libmaple linker script for "JTAG" builds. + * + * A "JTAG" build puts .text (and .rodata) in Flash, and + * .data/.bss/heap (of course) in SRAM, but links starting at the + * Flash and SRAM starting addresses (0x08000000 and 0x20000000 + * respectively). This will wipe out a Maple bootloader if there's one + * on the board, so only use this if you know what you're doing. + * + * Of course, a "JTAG" build is perfectly usable for upload over SWD, + * the system memory bootloader, etc. The name is just a historical + * artifact. + */ + +/* + * This pulls in the appropriate MEMORY declaration from the right + * subdirectory of stm32/mem/ (the environment must call ld with the + * right include directory flags to make this happen). Boards can also + * use this file to use any of libmaple's memory-related hooks (like + * where the heap should live). + */ +INCLUDE mem-jtag.inc + +/* Provide memory region aliases for common.inc */ +REGION_ALIAS("REGION_TEXT", rom); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", rom); + +/* Let common.inc handle the real work. */ +INCLUDE common.inc diff --git a/support/ld/maple/flash.ld b/support/ld/maple/flash.ld deleted file mode 100644 index 190c187..0000000 --- a/support/ld/maple/flash.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Maple (STM32F103RBT6, medium density) linker script for Flash builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* - * Define the rest of the sections - */ -_FLASH_BUILD = 1; - -INCLUDE common.inc diff --git a/support/ld/maple/jtag.ld b/support/ld/maple/jtag.ld deleted file mode 100644 index c090988..0000000 --- a/support/ld/maple/jtag.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Maple (STM32F103RBT6, medium density) linker script for JTAG (bare - * metal, no bootloader) builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* - * Define the rest of the sections - */ -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/maple/ram.ld b/support/ld/maple/ram.ld deleted file mode 100644 index a5ef621..0000000 --- a/support/ld/maple/ram.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Maple (STM32F103RBT6, medium density) linker script for RAM builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K -} - -REGION_ALIAS("REGION_TEXT", ram); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", ram); - -/* - * Define the rest of the sections - */ -INCLUDE common.inc diff --git a/support/ld/maple_RET6/flash.ld b/support/ld/maple_RET6/flash.ld deleted file mode 100644 index 8b529f8..0000000 --- a/support/ld/maple_RET6/flash.ld +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Maple RET6 Edition (STM32F103RET6, high density) linker script for - * Flash builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 492K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/maple_RET6/jtag.ld b/support/ld/maple_RET6/jtag.ld deleted file mode 100644 index 4ac9d76..0000000 --- a/support/ld/maple_RET6/jtag.ld +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Maple RET6 Edition (STM32F103RET6, high density) linker script for - * JTAG (bare metal, no bootloader) builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/maple_RET6/ram.ld b/support/ld/maple_RET6/ram.ld deleted file mode 100644 index 65c3a2c..0000000 --- a/support/ld/maple_RET6/ram.ld +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Maple RET6 Edition (STM32F103RET6, high density) linker script for - * RAM builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K -} - -REGION_ALIAS("REGION_TEXT", ram); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", ram); - -INCLUDE common.inc diff --git a/support/ld/maple_mini/flash.ld b/support/ld/maple_mini/flash.ld deleted file mode 100644 index 52d01dc..0000000 --- a/support/ld/maple_mini/flash.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Maple Mini (STM32F103CBT6, medium density) linker script for Flash builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* - * Define the rest of the sections - */ -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/maple_mini/jtag.ld b/support/ld/maple_mini/jtag.ld deleted file mode 100644 index 28e204f..0000000 --- a/support/ld/maple_mini/jtag.ld +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Maple Mini (STM32F103CBT6, medium density) linker script for JTAG - * (bare metal, no bootloader) builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* - * Define the rest of the sections - */ -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/maple_mini/ram.ld b/support/ld/maple_mini/ram.ld deleted file mode 100644 index 5b0111b..0000000 --- a/support/ld/maple_mini/ram.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Maple Mini (STM32F103CBT6, medium density) linker script for RAM builds. - */ - -/* - * Define memory spaces. - */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K -} - -REGION_ALIAS("REGION_TEXT", ram); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", ram); - -/* - * Define the rest of the sections - */ -INCLUDE common.inc diff --git a/support/ld/maple_native/flash.ld b/support/ld/maple_native/flash.ld deleted file mode 100644 index aac5325..0000000 --- a/support/ld/maple_native/flash.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Maple Native (STM32F103ZET6, high density) linker script for Flash builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 492K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* Specify heap boundary addresses on the external SRAM chip */ -_lm_heap_start = 0x60000000; -_lm_heap_end = 0x60100000; - -_FLASH_BUILD = 1; -INCLUDE common.inc - diff --git a/support/ld/maple_native/jtag.ld b/support/ld/maple_native/jtag.ld deleted file mode 100644 index 412348e..0000000 --- a/support/ld/maple_native/jtag.ld +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Maple Native (STM32F103ZET6, high density) linker script for JTAG - * (bare metal, no bootloader) builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -/* Specify heap boundary addresses on the external SRAM chip */ -_lm_heap_start = 0x60000000; -_lm_heap_end = 0x60100000; - -_FLASH_BUILD = 1; -INCLUDE common.inc diff --git a/support/ld/maple_native/ram.ld b/support/ld/maple_native/ram.ld deleted file mode 100644 index eeec761..0000000 --- a/support/ld/maple_native/ram.ld +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Maple Native (STM32F103ZET6, high density) linker script for RAM builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K - rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K -} - -REGION_ALIAS("REGION_TEXT", ram); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", ram); - -/* Specify heap boundary addresses on the external SRAM chip */ -_lm_heap_start = 0x60000000; -_lm_heap_end = 0x60100000; - -INCLUDE common.inc diff --git a/support/ld/olimex_stm32_h103 b/support/ld/olimex_stm32_h103 deleted file mode 120000 index 2d8bbed..0000000 --- a/support/ld/olimex_stm32_h103 +++ /dev/null @@ -1 +0,0 @@ -maple \ No newline at end of file diff --git a/support/ld/ram.ld b/support/ld/ram.ld new file mode 100644 index 0000000..34b468e --- /dev/null +++ b/support/ld/ram.ld @@ -0,0 +1,25 @@ +/* + * libmaple linker script for RAM builds. + * + * A Flash build puts .text, .rodata, and .data/.bss/heap (of course) + * in SRAM, but offsets the sections by enough space to store the + * Maple bootloader, which uses low memory. + */ + +/* + * This pulls in the appropriate MEMORY declaration from the right + * subdirectory of stm32/mem/ (the environment must call ld with the + * right include directory flags to make this happen). Boards can also + * use this file to use any of libmaple's memory-related hooks (like + * where the heap should live). + */ +INCLUDE mem-ram.inc + +/* Provide memory region aliases for common.inc */ +REGION_ALIAS("REGION_TEXT", ram); +REGION_ALIAS("REGION_DATA", ram); +REGION_ALIAS("REGION_BSS", ram); +REGION_ALIAS("REGION_RODATA", ram); + +/* Let common.inc handle the real work. */ +INCLUDE common.inc diff --git a/support/ld/st_stm3220g_eval/jtag.ld b/support/ld/st_stm3220g_eval/jtag.ld deleted file mode 100644 index 4193f5b..0000000 --- a/support/ld/st_stm3220g_eval/jtag.ld +++ /dev/null @@ -1,17 +0,0 @@ -/* - * STM3220G-EVAL (STM32F207IGH6) linker script for JTAG (bare metal, - * no bootloader) builds. - */ - -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K - rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K -} - -REGION_ALIAS("REGION_TEXT", rom); -REGION_ALIAS("REGION_DATA", ram); -REGION_ALIAS("REGION_BSS", ram); -REGION_ALIAS("REGION_RODATA", rom); - -INCLUDE common.inc diff --git a/support/ld/stm32/mem/maple_native/maple_native_heap.inc b/support/ld/stm32/mem/maple_native/maple_native_heap.inc new file mode 100644 index 0000000..34b5a2d --- /dev/null +++ b/support/ld/stm32/mem/maple_native/maple_native_heap.inc @@ -0,0 +1,3 @@ +/* Specify heap boundary addresses on the external SRAM chip */ +_lm_heap_start = 0x60000000; +_lm_heap_end = 0x60100000; diff --git a/support/ld/stm32/mem/maple_native/mem-flash.inc b/support/ld/stm32/mem/maple_native/mem-flash.inc new file mode 100644 index 0000000..bae4f39 --- /dev/null +++ b/support/ld/stm32/mem/maple_native/mem-flash.inc @@ -0,0 +1,7 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 492K +} + +INCLUDE maple_native_heap.inc diff --git a/support/ld/stm32/mem/maple_native/mem-jtag.inc b/support/ld/stm32/mem/maple_native/mem-jtag.inc new file mode 100644 index 0000000..508ed44 --- /dev/null +++ b/support/ld/stm32/mem/maple_native/mem-jtag.inc @@ -0,0 +1,7 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K +} + +INCLUDE maple_native_heap.inc diff --git a/support/ld/stm32/mem/maple_native/mem-ram.inc b/support/ld/stm32/mem/maple_native/mem-ram.inc new file mode 100644 index 0000000..6ae11ef --- /dev/null +++ b/support/ld/stm32/mem/maple_native/mem-ram.inc @@ -0,0 +1,7 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K +} + +INCLUDE maple_native_heap.inc diff --git a/support/ld/stm32/mem/sram_112k_flash_1024k/mem-jtag.inc b/support/ld/stm32/mem/sram_112k_flash_1024k/mem-jtag.inc new file mode 100644 index 0000000..e0d2da1 --- /dev/null +++ b/support/ld/stm32/mem/sram_112k_flash_1024k/mem-jtag.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} diff --git a/support/ld/stm32/mem/sram_112k_flash_1024k/mem-ram.inc b/support/ld/stm32/mem/sram_112k_flash_1024k/mem-ram.inc new file mode 100644 index 0000000..d21f17c --- /dev/null +++ b/support/ld/stm32/mem/sram_112k_flash_1024k/mem-ram.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 0K +} diff --git a/support/ld/stm32/mem/sram_20k_flash_128k/mem-flash.inc b/support/ld/stm32/mem/sram_20k_flash_128k/mem-flash.inc new file mode 100644 index 0000000..a9091ca --- /dev/null +++ b/support/ld/stm32/mem/sram_20k_flash_128k/mem-flash.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K +} diff --git a/support/ld/stm32/mem/sram_20k_flash_128k/mem-jtag.inc b/support/ld/stm32/mem/sram_20k_flash_128k/mem-jtag.inc new file mode 100644 index 0000000..20fbec0 --- /dev/null +++ b/support/ld/stm32/mem/sram_20k_flash_128k/mem-jtag.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K +} diff --git a/support/ld/stm32/mem/sram_20k_flash_128k/mem-ram.inc b/support/ld/stm32/mem/sram_20k_flash_128k/mem-ram.inc new file mode 100644 index 0000000..f02453b --- /dev/null +++ b/support/ld/stm32/mem/sram_20k_flash_128k/mem-ram.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K +} diff --git a/support/ld/stm32/mem/sram_64k_flash_512k/mem-flash.inc b/support/ld/stm32/mem/sram_64k_flash_512k/mem-flash.inc new file mode 100644 index 0000000..ddb8876 --- /dev/null +++ b/support/ld/stm32/mem/sram_64k_flash_512k/mem-flash.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 492K +} diff --git a/support/ld/stm32/mem/sram_64k_flash_512k/mem-jtag.inc b/support/ld/stm32/mem/sram_64k_flash_512k/mem-jtag.inc new file mode 100644 index 0000000..d3ed992 --- /dev/null +++ b/support/ld/stm32/mem/sram_64k_flash_512k/mem-jtag.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K +} diff --git a/support/ld/stm32/mem/sram_64k_flash_512k/mem-ram.inc b/support/ld/stm32/mem/sram_64k_flash_512k/mem-ram.inc new file mode 100644 index 0000000..360beaf --- /dev/null +++ b/support/ld/stm32/mem/sram_64k_flash_512k/mem-ram.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K + rom (rx) : ORIGIN = 0x08005000, LENGTH = 0K +} diff --git a/support/ld/stm32/mem/sram_8k_flash_128k/mem-flash.inc b/support/ld/stm32/mem/sram_8k_flash_128k/mem-flash.inc new file mode 100644 index 0000000..19372b7 --- /dev/null +++ b/support/ld/stm32/mem/sram_8k_flash_128k/mem-flash.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K +} diff --git a/support/ld/stm32/mem/sram_8k_flash_128k/mem-jtag.inc b/support/ld/stm32/mem/sram_8k_flash_128k/mem-jtag.inc new file mode 100644 index 0000000..19372b7 --- /dev/null +++ b/support/ld/stm32/mem/sram_8k_flash_128k/mem-jtag.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K +} diff --git a/support/ld/stm32/mem/sram_8k_flash_128k/mem-ram.inc b/support/ld/stm32/mem/sram_8k_flash_128k/mem-ram.inc new file mode 100644 index 0000000..4063ab4 --- /dev/null +++ b/support/ld/stm32/mem/sram_8k_flash_128k/mem-ram.inc @@ -0,0 +1,5 @@ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 0K +} diff --git a/support/make/board-includes/VLDiscovery.mk b/support/make/board-includes/VLDiscovery.mk index 441f078..76cd85a 100644 --- a/support/make/board-includes/VLDiscovery.mk +++ b/support/make/board-includes/VLDiscovery.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 9 MCU_SERIES := stm32f1 MCU_F1_LINE := value +LD_MEM_DIR := sram_8k_flash_128k diff --git a/support/make/board-includes/maple.mk b/support/make/board-includes/maple.mk index 4de4bab..a2943ce 100644 --- a/support/make/board-includes/maple.mk +++ b/support/make/board-includes/maple.mk @@ -4,3 +4,7 @@ ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 MCU_SERIES := stm32f1 MCU_F1_LINE := performance +# This crap is due to ld-script limitations. If you know of a better +# way to go about this (like some magic ld switches to specify MEMORY +# at the command line), please tell us! +LD_MEM_DIR := sram_20k_flash_128k diff --git a/support/make/board-includes/maple_RET6.mk b/support/make/board-includes/maple_RET6.mk index 104ae08..138722f 100644 --- a/support/make/board-includes/maple_RET6.mk +++ b/support/make/board-includes/maple_RET6.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOA ERROR_LED_PIN := 5 MCU_SERIES := stm32f1 MCU_F1_LINE := performance +LD_MEM_DIR := sram_64k_flash_512k diff --git a/support/make/board-includes/maple_mini.mk b/support/make/board-includes/maple_mini.mk index 70ef506..b022537 100644 --- a/support/make/board-includes/maple_mini.mk +++ b/support/make/board-includes/maple_mini.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOB ERROR_LED_PIN := 1 MCU_SERIES := stm32f1 MCU_F1_LINE := performance +LD_MEM_DIR := sram_20k_flash_128k diff --git a/support/make/board-includes/maple_native.mk b/support/make/board-includes/maple_native.mk index 86746a6..87e58e3 100644 --- a/support/make/board-includes/maple_native.mk +++ b/support/make/board-includes/maple_native.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 15 MCU_SERIES := stm32f1 MCU_F1_LINE := performance +LD_MEM_DIR := maple_native # The SRAM chip makes this board special diff --git a/support/make/board-includes/olimex_stm32_h103.mk b/support/make/board-includes/olimex_stm32_h103.mk index 31f2c04..a3304a1 100644 --- a/support/make/board-includes/olimex_stm32_h103.mk +++ b/support/make/board-includes/olimex_stm32_h103.mk @@ -4,3 +4,4 @@ ERROR_LED_PORT := GPIOC ERROR_LED_PIN := 12 MCU_SERIES := stm32f1 MCU_F1_LINE := performance +LD_MEM_DIR := sram_20k_flash_128k diff --git a/support/make/board-includes/st_stm3220g_eval.mk b/support/make/board-includes/st_stm3220g_eval.mk index f8073ea..8aaefc9 100644 --- a/support/make/board-includes/st_stm3220g_eval.mk +++ b/support/make/board-includes/st_stm3220g_eval.mk @@ -2,3 +2,4 @@ MCU := STM32F207IG ERROR_LED_PORT := GPIOG ERROR_LED_PIN := 6 MCU_SERIES := stm32f2 +LD_MEM_DIR := sram_112k_flash_1024k diff --git a/support/make/target-config.mk b/support/make/target-config.mk index a04ca38..ea5dfd9 100644 --- a/support/make/target-config.mk +++ b/support/make/target-config.mk @@ -1,39 +1,42 @@ # TARGET_FLAGS are to be passed while compiling, assembling, linking. - TARGET_FLAGS := +# TARGET_LDFLAGS go to the linker +TARGET_LDFLAGS := -# Board-specific configuration values. Punt these to board-specific -# include files. +# Configuration derived from $(MEMORY_TARGET) -include $(BOARD_INCLUDE_DIR)/$(BOARD).mk +LD_SCRIPT_PATH := $(LDDIR)/$(MEMORY_TARGET).ld -TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ - -DERROR_LED_PORT=$(ERROR_LED_PORT) \ - -DERROR_LED_PIN=$(ERROR_LED_PIN) +ifeq ($(MEMORY_TARGET), ram) +VECT_BASE_ADDR := VECT_TAB_RAM +endif +ifeq ($(MEMORY_TARGET), flash) +VECT_BASE_ADDR := VECT_TAB_FLASH +endif +ifeq ($(MEMORY_TARGET), jtag) +VECT_BASE_ADDR := VECT_TAB_BASE +endif + +# Pull in the board configuration file here, so it can override the +# above. + +include $(BOARD_INCLUDE_DIR)/$(BOARD).mk -# STM32 series-specific configuration values. +# Configuration derived from $(BOARD).mk LD_SERIES_PATH := $(LDDIR)/stm32/series/$(MCU_SERIES) +LD_MEM_PATH := $(LDDIR)/stm32/mem/$(LD_MEM_DIR) ifeq ($(MCU_SERIES), stm32f1) # Due to the Balkanization on F1, we need to specify the line when # making linker decisions. LD_SERIES_PATH := $(LD_SERIES_PATH)/$(MCU_F1_LINE) endif -LIBMAPLE_MODULE_SERIES := $(LIBMAPLE_PATH)/$(MCU_SERIES) - -# Memory target-specific configuration values -ifeq ($(MEMORY_TARGET), ram) - LDSCRIPT := $(BOARD)/ram.ld - VECT_BASE_ADDR := VECT_TAB_RAM -endif -ifeq ($(MEMORY_TARGET), flash) - LDSCRIPT := $(BOARD)/flash.ld - VECT_BASE_ADDR := VECT_TAB_FLASH -endif -ifeq ($(MEMORY_TARGET), jtag) - LDSCRIPT := $(BOARD)/jtag.ld - VECT_BASE_ADDR := VECT_TAB_BASE -endif +TARGET_LDFLAGS += -T$(LD_SCRIPT_PATH) -L $(LD_SERIES_PATH) \ + -L $(LD_MEM_PATH) -L$(LDDIR) +TARGET_FLAGS += -DBOARD_$(BOARD) -DMCU_$(MCU) \ + -DERROR_LED_PORT=$(ERROR_LED_PORT) \ + -DERROR_LED_PIN=$(ERROR_LED_PIN) \ + -D$(VECT_BASE_ADDR) -TARGET_FLAGS += -D$(VECT_BASE_ADDR) +LIBMAPLE_MODULE_SERIES := $(LIBMAPLE_PATH)/$(MCU_SERIES) -- cgit v1.2.3 From 9231544e6a2796df2552873755b1a2fc205a941e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 03:55:25 -0400 Subject: README: remove mention of support/openocd/. This is now in contrib/. Signed-off-by: Marti Bolivar --- README | 1 - 1 file changed, 1 deletion(-) diff --git a/README b/README index f66ad03..cbc4ada 100644 --- a/README +++ b/README @@ -122,7 +122,6 @@ Repository Layout gdb/ GDB scripts. ld/ Linker scripts. make/ Additional scripts used by the top-level Makefile. - openocd/ OpenOCD scripts for JTAG debugging. scripts/ Miscellany. doxygen/ Doxygen configuration. stm32loader.py Script for uploading via the built-in USART bootloader. -- cgit v1.2.3 From 193687bc43b245ef8b09fb3abacd29ca0c540432 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 04:15:06 -0400 Subject: Makefile: help target pointers for multiple source files. Signed-off-by: Marti Bolivar --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 97d65bb..d958a53 100644 --- a/Makefile +++ b/Makefile @@ -133,6 +133,9 @@ help: @echo " $$ make BOARD=your_board" @echo " $$ make BOARD=your_board install" @echo "" + @echo "(Multiple source files? Link with libmaple.a (\`$$ make library')" + @echo "or hack build-targets.mk appropriately.)" + @echo "" @echo "Important targets:" @echo " sketch: Compile for BOARD to MEMORY_TARGET (default)." @echo " install: Compile and upload over USB using Maple bootloader" -- cgit v1.2.3 From cb15495943b560cb0ca45e652bbcf7e14df2eadc Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 04:29:15 -0400 Subject: series/timer.h: Remove silly duplicate declarations. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/timer.h | 1 - libmaple/stm32f2/include/series/timer.h | 1 - 2 files changed, 2 deletions(-) diff --git a/libmaple/stm32f1/include/series/timer.h b/libmaple/stm32f1/include/series/timer.h index 8a64ffa..cfeb770 100644 --- a/libmaple/stm32f1/include/series/timer.h +++ b/libmaple/stm32f1/include/series/timer.h @@ -64,7 +64,6 @@ typedef struct timer_gen_reg_map { } timer_gen_reg_map; struct timer_adv_reg_map; -struct timer_gen_reg_map; struct timer_bas_reg_map; /** Timer 1 register map base pointer */ diff --git a/libmaple/stm32f2/include/series/timer.h b/libmaple/stm32f2/include/series/timer.h index ed473b4..a7ac276 100644 --- a/libmaple/stm32f2/include/series/timer.h +++ b/libmaple/stm32f2/include/series/timer.h @@ -71,7 +71,6 @@ typedef struct timer_gen_reg_map { } timer_gen_reg_map; struct timer_adv_reg_map; -struct timer_gen_reg_map; struct timer_bas_reg_map; /** Timer 1 register map base pointer */ -- cgit v1.2.3 From 0acbcb9c50d6eeb41d6036b2706a7b3d2b5e4b3c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 04:39:22 -0400 Subject: Tweak some timer_private APIs. The current versions of DELARE_*_TIMER() don't play well with cscope, which is a bad sign. Fix that. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/timer.c | 28 ++++++++++++++-------------- libmaple/stm32f2/timer.c | 33 ++++++++++++++------------------- libmaple/timer_private.h | 16 ++++++++-------- 3 files changed, 36 insertions(+), 41 deletions(-) diff --git a/libmaple/stm32f1/timer.c b/libmaple/stm32f1/timer.c index 002b9d6..8671695 100644 --- a/libmaple/stm32f1/timer.c +++ b/libmaple/stm32f1/timer.c @@ -54,10 +54,10 @@ * Defer to the timer_private API. */ -static DECLARE_ADVANCED_TIMER(timer1, 1); -static DECLARE_GENERAL_TIMER(timer2, 2); -static DECLARE_GENERAL_TIMER(timer3, 3); -static DECLARE_GENERAL_TIMER(timer4, 4); +static timer_dev timer1 = ADVANCED_TIMER(1); +static timer_dev timer2 = GENERAL_TIMER(2); +static timer_dev timer3 = GENERAL_TIMER(3); +static timer_dev timer4 = GENERAL_TIMER(4); /** Timer 1 device (advanced) */ timer_dev *TIMER1 = &timer1; @@ -69,10 +69,10 @@ timer_dev *TIMER3 = &timer3; timer_dev *TIMER4 = &timer4; #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -static DECLARE_GENERAL_TIMER(timer5, 5); -static DECLARE_BASIC_TIMER(timer6, 6); -static DECLARE_BASIC_TIMER(timer7, 7); -static DECLARE_ADVANCED_TIMER(timer8, 8); +static timer_dev timer5 = GENERAL_TIMER(5); +static timer_dev timer6 = BASIC_TIMER(6); +static timer_dev timer7 = BASIC_TIMER(7); +static timer_dev timer8 = ADVANCED_TIMER(8); /** Timer 5 device (general-purpose) */ timer_dev *TIMER5 = &timer5; @@ -86,17 +86,17 @@ timer_dev *TIMER8 = &timer8; #ifdef STM32_XL_DENSITY /* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer9, 9, TIMER_DIER_TIE_BIT); +static timer_dev timer9 = RESTRICTED_GENERAL_TIMER(9, TIMER_DIER_TIE_BIT); /* TIM10 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer10, 10, TIMER_DIER_CC1IE_BIT); +static timer_dev timer10 = RESTRICTED_GENERAL_TIMER(10, TIMER_DIER_CC1IE_BIT); /* TIM11 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer11, 11, TIMER_DIER_CC1IE_BIT); +static timer_dev timer11 = RESTRICTED_GENERAL_TIMER(11, TIMER_DIER_CC1IE_BIT); /* TIM12 has UIE, CC1IE, CC2IE, TIE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer12, 12, TIMER_DIER_TIE_BIT); +static timer_dev timer12 = RESTRICTED_GENERAL_TIMER(12, TIMER_DIER_TIE_BIT); /* TIM13 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer13, 13, TIMER_DIER_CC1IE_BIT); +static timer_dev timer13 = RESTRICTED_GENERAL_TIMER(13, TIMER_DIER_CC1IE_BIT); /* TIM14 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer14, 14, TIMER_DIER_CC1IE_BIT); +static timer_dev timer14 = RESTRICTED_GENERAL_TIMER(14, TIMER_DIER_CC1IE_BIT); /** Timer 9 device (general-purpose) */ timer_dev *TIMER9 = &timer9; diff --git a/libmaple/stm32f2/timer.c b/libmaple/stm32f2/timer.c index f644b16..99dbf48 100644 --- a/libmaple/stm32f2/timer.c +++ b/libmaple/stm32f2/timer.c @@ -39,26 +39,26 @@ * Defer to the timer_private API for declaring these. */ -static DECLARE_ADVANCED_TIMER(timer1, 1); -static DECLARE_GENERAL_TIMER(timer2, 2); -static DECLARE_GENERAL_TIMER(timer3, 3); -static DECLARE_GENERAL_TIMER(timer4, 4); -static DECLARE_GENERAL_TIMER(timer5, 5); -static DECLARE_BASIC_TIMER(timer6, 6); -static DECLARE_BASIC_TIMER(timer7, 7); -static DECLARE_ADVANCED_TIMER(timer8, 8); +static timer_dev timer1 = ADVANCED_TIMER(1); +static timer_dev timer2 = GENERAL_TIMER(2); +static timer_dev timer3 = GENERAL_TIMER(3); +static timer_dev timer4 = GENERAL_TIMER(4); +static timer_dev timer5 = GENERAL_TIMER(5); +static timer_dev timer6 = BASIC_TIMER(6); +static timer_dev timer7 = BASIC_TIMER(7); +static timer_dev timer8 = ADVANCED_TIMER(8); /* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer9, 9, TIMER_DIER_TIE_BIT); +static timer_dev timer9 = RESTRICTED_GENERAL_TIMER(9, TIMER_DIER_TIE_BIT); /* TIM10 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer10, 10, TIMER_DIER_CC1IE_BIT); +static timer_dev timer10 = RESTRICTED_GENERAL_TIMER(10, TIMER_DIER_CC1IE_BIT); /* TIM11 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer11, 11, TIMER_DIER_CC1IE_BIT); +static timer_dev timer11 = RESTRICTED_GENERAL_TIMER(11, TIMER_DIER_CC1IE_BIT); /* TIM12 has UIE, CC1IE, CC2IE, TIE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer12, 12, TIMER_DIER_TIE_BIT); +static timer_dev timer12 = RESTRICTED_GENERAL_TIMER(12, TIMER_DIER_TIE_BIT); /* TIM13 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer13, 13, TIMER_DIER_CC1IE_BIT); +static timer_dev timer13 = RESTRICTED_GENERAL_TIMER(13, TIMER_DIER_CC1IE_BIT); /* TIM14 has UIE, CC1IE. */ -static DECLARE_RESTRICTED_GENERAL_TIMER(timer14, 14, TIMER_DIER_CC1IE_BIT); +static timer_dev timer14 = RESTRICTED_GENERAL_TIMER(14, TIMER_DIER_CC1IE_BIT); /** Timer 1 device (advanced) */ timer_dev *TIMER1 = &timer1; @@ -121,11 +121,6 @@ void timer_foreach(void (*fn)(timer_dev*)) { * GPIO_AF_TIM_1_2. This is useful for e.g. using gpio_set_af() to set * a pin's alternate function to a timer. * - * Note that the timer gpio_afs are shared with other timers (and - * sometimes with CAN). For example, timers 1 and 2 both use - * GPIO_AF_TIM_1_2. Because of that, it can pay to e.g not point two - * timers at the same pin. - * * @param dev Timer device, must not be TIMER6 or TIMER7. * @return gpio_af corresponding to dev * @see gpio_set_af diff --git a/libmaple/timer_private.h b/libmaple/timer_private.h index 0eb569d..320c636 100644 --- a/libmaple/timer_private.h +++ b/libmaple/timer_private.h @@ -58,8 +58,8 @@ #define NR_BAS_HANDLERS 1 /* For declaring advanced timers. */ -#define DECLARE_ADVANCED_TIMER(name, num) \ - timer_dev name = { \ +#define ADVANCED_TIMER(num) \ + { \ .regs = { .adv = TIMER##num##_BASE }, \ .clk_id = RCC_TIMER##num, \ .type = TIMER_ADVANCED, \ @@ -67,8 +67,8 @@ } /* For declaring full-featured general purpose timers. */ -#define DECLARE_GENERAL_TIMER(name, num) \ - timer_dev name = { \ +#define GENERAL_TIMER(num) \ + { \ .regs = { .gen = TIMER##num##_BASE }, \ .clk_id = RCC_TIMER##num, \ .type = TIMER_GENERAL, \ @@ -78,8 +78,8 @@ /* For declaring general purpose timers with limited interrupt * capability (e.g. timers 9 through 14 on STM32F2 and XL-density * STM32F1). */ -#define DECLARE_RESTRICTED_GENERAL_TIMER(name, num, max_dier_bit) \ - timer_dev name = { \ +#define RESTRICTED_GENERAL_TIMER(num, max_dier_bit) \ + { \ .regs = { .gen = TIMER##num##_BASE }, \ .clk_id = RCC_TIMER##num, \ .type = TIMER_GENERAL, \ @@ -87,8 +87,8 @@ } /* For declaring basic timers (e.g. TIM6 and TIM7). */ -#define DECLARE_BASIC_TIMER(name, num) \ - timer_dev name = { \ +#define BASIC_TIMER(num) \ + { \ .regs = { .bas = TIMER##num##_BASE }, \ .clk_id = RCC_TIMER##num, \ .type = TIMER_BASIC, \ -- cgit v1.2.3 From 9e18f9577b4a838e98311afc59a34df4fc050075 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 04:56:30 -0400 Subject: Move timer_dev definitions into libmaple/timer.c. The addition of STM32_HAVE_TIMER() allows us to avoid some repetition. There's still an issue with names on F1 preventing us from moving the IRQ handlers to libmaple/timer.c, but once that's resolved, we'll be able to remove even more. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 42 ++++++++++++ libmaple/stm32f1/timer.c | 125 +++--------------------------------- libmaple/stm32f2/timer.c | 77 ---------------------- libmaple/timer.c | 132 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 184 insertions(+), 192 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index 5d9650c..3563749 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -134,6 +134,48 @@ typedef struct timer_dev { * @see timer_detach_interrupt() */ } timer_dev; +#if STM32_HAVE_TIMER(1) +extern timer_dev *TIMER1; +#endif +#if STM32_HAVE_TIMER(2) +extern timer_dev *TIMER2; +#endif +#if STM32_HAVE_TIMER(3) +extern timer_dev *TIMER3; +#endif +#if STM32_HAVE_TIMER(4) +extern timer_dev *TIMER4; +#endif +#if STM32_HAVE_TIMER(5) +extern timer_dev *TIMER5; +#endif +#if STM32_HAVE_TIMER(6) +extern timer_dev *TIMER6; +#endif +#if STM32_HAVE_TIMER(7) +extern timer_dev *TIMER7; +#endif +#if STM32_HAVE_TIMER(8) +extern timer_dev *TIMER8; +#endif +#if STM32_HAVE_TIMER(9) +extern timer_dev *TIMER9; +#endif +#if STM32_HAVE_TIMER(10) +extern timer_dev *TIMER10; +#endif +#if STM32_HAVE_TIMER(11) +extern timer_dev *TIMER11; +#endif +#if STM32_HAVE_TIMER(12) +extern timer_dev *TIMER12; +#endif +#if STM32_HAVE_TIMER(13) +extern timer_dev *TIMER13; +#endif +#if STM32_HAVE_TIMER(14) +extern timer_dev *TIMER14; +#endif /* * Register bit definitions diff --git a/libmaple/stm32f1/timer.c b/libmaple/stm32f1/timer.c index 8671695..8b9e976 100644 --- a/libmaple/stm32f1/timer.c +++ b/libmaple/stm32f1/timer.c @@ -30,117 +30,10 @@ * @brief STM32F1 timer. */ -/* Notes: - * - * - We use STM32F1 density test macros throughout to avoid defining - * symbols or linking in code that would use timers that are - * unavailable in a given density. For example, TIM5 doesn't exist - * on medium-density, and TIM9 doesn't exist on high-density, so we - * don't define or use TIM5 when being compiled for medium-density, - * and similarly for TIM9 and high-density. - * - * This makes a mess, but helps avoid bloat and ensures backwards - * compatibility. Since the mess is manageable and there don't seem - * to be any plans on ST's part to add new STM32F1 lines or - * densities, we'll live with it. - */ - #include +#include #include "timer_private.h" -/* - * Devices - * - * Defer to the timer_private API. - */ - -static timer_dev timer1 = ADVANCED_TIMER(1); -static timer_dev timer2 = GENERAL_TIMER(2); -static timer_dev timer3 = GENERAL_TIMER(3); -static timer_dev timer4 = GENERAL_TIMER(4); - -/** Timer 1 device (advanced) */ -timer_dev *TIMER1 = &timer1; -/** Timer 2 device (general-purpose) */ -timer_dev *TIMER2 = &timer2; -/** Timer 3 device (general-purpose) */ -timer_dev *TIMER3 = &timer3; -/** Timer 4 device (general-purpose) */ -timer_dev *TIMER4 = &timer4; - -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -static timer_dev timer5 = GENERAL_TIMER(5); -static timer_dev timer6 = BASIC_TIMER(6); -static timer_dev timer7 = BASIC_TIMER(7); -static timer_dev timer8 = ADVANCED_TIMER(8); - -/** Timer 5 device (general-purpose) */ -timer_dev *TIMER5 = &timer5; -/** Timer 6 device (basic) */ -timer_dev *TIMER6 = &timer6; -/** Timer 7 device (basic) */ -timer_dev *TIMER7 = &timer7; -/** Timer 8 device (advanced) */ -timer_dev *TIMER8 = &timer8; -#endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */ - -#ifdef STM32_XL_DENSITY -/* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */ -static timer_dev timer9 = RESTRICTED_GENERAL_TIMER(9, TIMER_DIER_TIE_BIT); -/* TIM10 has UIE, CC1IE. */ -static timer_dev timer10 = RESTRICTED_GENERAL_TIMER(10, TIMER_DIER_CC1IE_BIT); -/* TIM11 has UIE, CC1IE. */ -static timer_dev timer11 = RESTRICTED_GENERAL_TIMER(11, TIMER_DIER_CC1IE_BIT); -/* TIM12 has UIE, CC1IE, CC2IE, TIE. */ -static timer_dev timer12 = RESTRICTED_GENERAL_TIMER(12, TIMER_DIER_TIE_BIT); -/* TIM13 has UIE, CC1IE. */ -static timer_dev timer13 = RESTRICTED_GENERAL_TIMER(13, TIMER_DIER_CC1IE_BIT); -/* TIM14 has UIE, CC1IE. */ -static timer_dev timer14 = RESTRICTED_GENERAL_TIMER(14, TIMER_DIER_CC1IE_BIT); - -/** Timer 9 device (general-purpose) */ -timer_dev *TIMER9 = &timer9; -/** Timer 10 device (general-purpose) */ -timer_dev *TIMER10 = &timer10; -/** Timer 11 device (general-purpose) */ -timer_dev *TIMER11 = &timer11; -/** Timer 12 device (general-purpose) */ -timer_dev *TIMER12 = &timer12; -/** Timer 13 device (general-purpose) */ -timer_dev *TIMER13 = &timer13; -/** Timer 14 device (general-purpose) */ -timer_dev *TIMER14 = &timer14; -#endif /* STM32_XL_DENSITY */ - -/* - * Routines - */ - -/** - * @brief Call a function on timer devices. - * @param fn Function to call on each timer device. - */ -void timer_foreach(void (*fn)(timer_dev*)) { - fn(TIMER1); - fn(TIMER2); - fn(TIMER3); - fn(TIMER4); -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) - fn(TIMER5); - fn(TIMER6); - fn(TIMER7); - fn(TIMER8); -#endif -#ifdef STM32_XL_DENSITY - fn(TIMER9); - fn(TIMER10); - fn(TIMER11); - fn(TIMER12); - fn(TIMER13); - fn(TIMER14); -#endif -} - /* * IRQ handlers * @@ -149,26 +42,28 @@ void timer_foreach(void (*fn)(timer_dev*)) { * FIXME: The names of these handlers are inaccurate since XL-density * devices came out. Update these to match the STM32F2 names, maybe * using some weak symbol magic to preserve backwards compatibility if - * possible. + * possible. Once that's done, we can just move the IRQ handlers into + * the top-level libmaple/timer.c, and there will be no need for this + * file. */ void __irq_tim1_brk(void) { dispatch_adv_brk(TIMER1); -#ifdef STM32_XL_DENSITY +#if STM32_HAVE_TIMER(9) dispatch_tim_9_12(TIMER9); #endif } void __irq_tim1_up(void) { dispatch_adv_up(TIMER1); -#ifdef STM32_XL_DENSITY +#if STM32_HAVE_TIMER(10) dispatch_tim_10_11_13_14(TIMER10); #endif } void __irq_tim1_trg_com(void) { dispatch_adv_trg_com(TIMER1); -#ifdef STM32_XL_DENSITY +#if STM32_HAVE_TIMER(11) dispatch_tim_10_11_13_14(TIMER11); #endif } @@ -204,21 +99,21 @@ void __irq_tim7(void) { void __irq_tim8_brk(void) { dispatch_adv_brk(TIMER8); -#ifdef STM32_XL_DENSITY +#if STM32_HAVE_TIMER(12) dispatch_tim_9_12(TIMER12); #endif } void __irq_tim8_up(void) { dispatch_adv_up(TIMER8); -#ifdef STM32_XL_DENSITY +#if STM32_HAVE_TIMER(13) dispatch_tim_10_11_13_14(TIMER13); #endif } void __irq_tim8_trg_com(void) { dispatch_adv_trg_com(TIMER8); -#ifdef STM32_XL_DENSITY +#if STM32_HAVE_TIMER(14) dispatch_tim_10_11_13_14(TIMER14); #endif } diff --git a/libmaple/stm32f2/timer.c b/libmaple/stm32f2/timer.c index 99dbf48..a85bea0 100644 --- a/libmaple/stm32f2/timer.c +++ b/libmaple/stm32f2/timer.c @@ -33,87 +33,10 @@ #include #include "timer_private.h" -/* - * Devices - * - * Defer to the timer_private API for declaring these. - */ - -static timer_dev timer1 = ADVANCED_TIMER(1); -static timer_dev timer2 = GENERAL_TIMER(2); -static timer_dev timer3 = GENERAL_TIMER(3); -static timer_dev timer4 = GENERAL_TIMER(4); -static timer_dev timer5 = GENERAL_TIMER(5); -static timer_dev timer6 = BASIC_TIMER(6); -static timer_dev timer7 = BASIC_TIMER(7); -static timer_dev timer8 = ADVANCED_TIMER(8); -/* TIM9 has UIE, CC1IE, CC2IE, TIE bits in DIER. */ -static timer_dev timer9 = RESTRICTED_GENERAL_TIMER(9, TIMER_DIER_TIE_BIT); -/* TIM10 has UIE, CC1IE. */ -static timer_dev timer10 = RESTRICTED_GENERAL_TIMER(10, TIMER_DIER_CC1IE_BIT); -/* TIM11 has UIE, CC1IE. */ -static timer_dev timer11 = RESTRICTED_GENERAL_TIMER(11, TIMER_DIER_CC1IE_BIT); -/* TIM12 has UIE, CC1IE, CC2IE, TIE. */ -static timer_dev timer12 = RESTRICTED_GENERAL_TIMER(12, TIMER_DIER_TIE_BIT); -/* TIM13 has UIE, CC1IE. */ -static timer_dev timer13 = RESTRICTED_GENERAL_TIMER(13, TIMER_DIER_CC1IE_BIT); -/* TIM14 has UIE, CC1IE. */ -static timer_dev timer14 = RESTRICTED_GENERAL_TIMER(14, TIMER_DIER_CC1IE_BIT); - -/** Timer 1 device (advanced) */ -timer_dev *TIMER1 = &timer1; -/** Timer 2 device (general-purpose) */ -timer_dev *TIMER2 = &timer2; -/** Timer 3 device (general-purpose) */ -timer_dev *TIMER3 = &timer3; -/** Timer 4 device (general-purpose) */ -timer_dev *TIMER4 = &timer4; -/** Timer 5 device (general-purpose) */ -timer_dev *TIMER5 = &timer5; -/** Timer 6 device (basic) */ -timer_dev *TIMER6 = &timer6; -/** Timer 7 device (basic) */ -timer_dev *TIMER7 = &timer7; -/** Timer 8 device (advanced) */ -timer_dev *TIMER8 = &timer8; -/** Timer 9 device (general-purpose) */ -timer_dev *TIMER9 = &timer9; -/** Timer 10 device (general-purpose) */ -timer_dev *TIMER10 = &timer10; -/** Timer 11 device (general-purpose) */ -timer_dev *TIMER11 = &timer11; -/** Timer 12 device (general-purpose) */ -timer_dev *TIMER12 = &timer12; -/** Timer 13 device (general-purpose) */ -timer_dev *TIMER13 = &timer13; -/** Timer 14 device (general-purpose) */ -timer_dev *TIMER14 = &timer14; - /* * Routines */ -/** - * @brief Call a function on timer devices. - * @param fn Function to call on each timer device. - */ -void timer_foreach(void (*fn)(timer_dev*)) { - fn(TIMER1); - fn(TIMER2); - fn(TIMER3); - fn(TIMER4); - fn(TIMER5); - fn(TIMER6); - fn(TIMER7); - fn(TIMER8); - fn(TIMER9); - fn(TIMER10); - fn(TIMER11); - fn(TIMER12); - fn(TIMER13); - fn(TIMER14); -} - /** * @brief Get the GPIO alternate function corresponding to a timer. * diff --git a/libmaple/timer.c b/libmaple/timer.c index cd9448a..24ae7fa 100644 --- a/libmaple/timer.c +++ b/libmaple/timer.c @@ -31,6 +31,8 @@ */ #include +#include +#include "timer_private.h" static void disable_channel(timer_dev *dev, uint8 channel); static void pwm_mode(timer_dev *dev, uint8 channel); @@ -38,6 +40,136 @@ static void output_compare_mode(timer_dev *dev, uint8 channel); static inline void enable_irq(timer_dev *dev, uint8 interrupt); +/* + * Devices + * + * Defer to the timer_private API for declaring these. + */ + +#if STM32_HAVE_TIMER(1) +static timer_dev timer1 = ADVANCED_TIMER(1); +/** Timer 1 device (advanced) */ +timer_dev *TIMER1 = &timer1; +#endif +#if STM32_HAVE_TIMER(2) +static timer_dev timer2 = GENERAL_TIMER(2); +/** Timer 2 device (general-purpose) */ +timer_dev *TIMER2 = &timer2; +#endif +#if STM32_HAVE_TIMER(3) +static timer_dev timer3 = GENERAL_TIMER(3); +/** Timer 3 device (general-purpose) */ +timer_dev *TIMER3 = &timer3; +#endif +#if STM32_HAVE_TIMER(4) +static timer_dev timer4 = GENERAL_TIMER(4); +/** Timer 4 device (general-purpose) */ +timer_dev *TIMER4 = &timer4; +#endif +#if STM32_HAVE_TIMER(5) +static timer_dev timer5 = GENERAL_TIMER(5); +/** Timer 5 device (general-purpose) */ +timer_dev *TIMER5 = &timer5; +#endif +#if STM32_HAVE_TIMER(6) +static timer_dev timer6 = BASIC_TIMER(6); +/** Timer 6 device (basic) */ +timer_dev *TIMER6 = &timer6; +#endif +#if STM32_HAVE_TIMER(7) +static timer_dev timer7 = BASIC_TIMER(7); +/** Timer 7 device (basic) */ +timer_dev *TIMER7 = &timer7; +#endif +#if STM32_HAVE_TIMER(8) +static timer_dev timer8 = ADVANCED_TIMER(8); +/** Timer 8 device (advanced) */ +timer_dev *TIMER8 = &timer8; +#endif +#if STM32_HAVE_TIMER(9) +static timer_dev timer9 = RESTRICTED_GENERAL_TIMER(9, TIMER_DIER_TIE_BIT); +/** Timer 9 device (general-purpose) */ +timer_dev *TIMER9 = &timer9; +#endif +#if STM32_HAVE_TIMER(10) +static timer_dev timer10 = RESTRICTED_GENERAL_TIMER(10, TIMER_DIER_CC1IE_BIT); +/** Timer 10 device (general-purpose) */ +timer_dev *TIMER10 = &timer10; +#endif +#if STM32_HAVE_TIMER(11) +static timer_dev timer11 = RESTRICTED_GENERAL_TIMER(11, TIMER_DIER_CC1IE_BIT); +/** Timer 11 device (general-purpose) */ +timer_dev *TIMER11 = &timer11; +#endif +#if STM32_HAVE_TIMER(12) +static timer_dev timer12 = RESTRICTED_GENERAL_TIMER(12, TIMER_DIER_TIE_BIT); +/** Timer 12 device (general-purpose) */ +timer_dev *TIMER12 = &timer12; +#endif +#if STM32_HAVE_TIMER(13) +static timer_dev timer13 = RESTRICTED_GENERAL_TIMER(13, TIMER_DIER_CC1IE_BIT); +/** Timer 13 device (general-purpose) */ +timer_dev *TIMER13 = &timer13; +#endif +#if STM32_HAVE_TIMER(14) +static timer_dev timer14 = RESTRICTED_GENERAL_TIMER(14, TIMER_DIER_CC1IE_BIT); +/** Timer 14 device (general-purpose) */ +timer_dev *TIMER14 = &timer14; +#endif + +/* + * Routines + */ + +/** + * @brief Call a function on timer devices. + * @param fn Function to call on each timer device. + */ +void timer_foreach(void (*fn)(timer_dev*)) { +#if STM32_HAVE_TIMER(1) + fn(TIMER1); +#endif +#if STM32_HAVE_TIMER(2) + fn(TIMER2); +#endif +#if STM32_HAVE_TIMER(3) + fn(TIMER3); +#endif +#if STM32_HAVE_TIMER(4) + fn(TIMER4); +#endif +#if STM32_HAVE_TIMER(5) + fn(TIMER5); +#endif +#if STM32_HAVE_TIMER(6) + fn(TIMER6); +#endif +#if STM32_HAVE_TIMER(7) + fn(TIMER7); +#endif +#if STM32_HAVE_TIMER(8) + fn(TIMER8); +#endif +#if STM32_HAVE_TIMER(9) + fn(TIMER9); +#endif +#if STM32_HAVE_TIMER(10) + fn(TIMER10); +#endif +#if STM32_HAVE_TIMER(11) + fn(TIMER11); +#endif +#if STM32_HAVE_TIMER(12) + fn(TIMER12); +#endif +#if STM32_HAVE_TIMER(13) + fn(TIMER13); +#endif +#if STM32_HAVE_TIMER(14) + fn(TIMER14); +#endif +} + /** * Initialize a timer, and reset its register map. * @param dev Timer to initialize -- cgit v1.2.3 From 59d7e5740de67b934171669092ce21a0640ff6f2 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 04:59:41 -0400 Subject: Makefile: fix cscope target. Signed-off-by: Marti Bolivar --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index d958a53..9e8c796 100644 --- a/Makefile +++ b/Makefile @@ -152,13 +152,13 @@ help: @echo "" @echo "Other targets:" @echo " clean: Remove all build and object files" - @echo " help: Show this message" @echo " doxygen: Build Doxygen HTML and XML documentation" + @echo " help: Show this message" @echo " mrproper: Remove all generated files" @echo "" cscope: - rm -rf *.cscope + rm -rf cscope.* find . -name '*.[hcS]' -o -name '*.cpp' | xargs cscope -b tags: -- cgit v1.2.3 From 3cc4517f4be4044b761d16f8293b0a8b979e8c89 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:20:35 -0400 Subject: libmaple/timer.h: Doxygen beautification and fixups Make the Doxygen comments nicer to look at. Some of the docstrings are out-of-date since F2 support was added, so update them. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 207 ++++++++++++++++++++------------------ 1 file changed, 109 insertions(+), 98 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index 3563749..f411f17 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -596,27 +596,32 @@ extern timer_dev *TIMER14; */ /** - * Used to configure the behavior of a timer channel. Note that not - * all timers can be configured in every mode. + * @brief Used to configure the behavior of a timer channel. + * + * Be careful: not all timers can be configured in every mode. */ -/* TODO TIMER_PWM_CENTER_ALIGNED, TIMER_INPUT_CAPTURE, TIMER_ONE_PULSE */ typedef enum timer_mode { - TIMER_DISABLED, /**< In this mode, the timer stops counting, - channel interrupts are detached, and no state - changes are output. */ - TIMER_PWM, /**< PWM output mode. This is the default mode for pins - after initialization. */ - /* TIMER_PWM_CENTER_ALIGNED, /\**< Center-aligned PWM output mode. *\/ */ - TIMER_OUTPUT_COMPARE, /**< In this mode, the timer counts from 0 - to its reload value repeatedly; every - time the counter value reaches one of - the channel compare values, the - corresponding interrupt is fired. */ - /* TIMER_INPUT_CAPTURE, /\**< In this mode, the timer can measure the */ - /* pulse lengths of input signals. *\/ */ - /* TIMER_ONE_PULSE /\**< In this mode, the timer can generate a single */ - /* pulse on a GPIO pin for a specified amount of */ - /* time. *\/ */ + /** + * The timer stops counting, channel interrupts are detached, and + * no state changes are output. */ + TIMER_DISABLED, + + /** PWM output. */ + TIMER_PWM, + + /* TIMER_PWM_CENTER_ALIGNED, TODO: Center-aligned PWM output mode. */ + + /** + * The timer counts from 0 to its reload value repeatedly; every + * time the counter value reaches one of the channel compare + * values, the corresponding interrupt is fired. */ + TIMER_OUTPUT_COMPARE, + + /* TIMER_INPUT_CAPTURE, TODO: In this mode, the timer can measure the + * pulse lengths of input signals */ + /* TIMER_ONE_PULSE, TODO: In this mode, the timer can generate a single + * pulse on a GPIO pin for a specified amount of + * time. */ } timer_mode; /** Timer channel numbers */ @@ -646,23 +651,21 @@ int timer_has_cc_channel(timer_dev *dev, uint8 channel); /** * @brief Timer interrupt number. * - * Not all timers support all of these values. General purpose timers - * can be a special nuisance in this regard. + * Not all timers support all of these values. All timers support + * TIMER_UPDATE_INTERRUPT. "General purpose" timers can be a special + * nuisance in this regard, as they individually support different + * subsets of the available interupts. Consult your target's reference + * manual for the details. */ typedef enum timer_interrupt_id { - TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */ - TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt, available - on general and advanced timers only. */ - TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt, general and - advanced timers only. */ - TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt, general and - advanced timers only. */ - TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt, general and - advanced timers only. */ - TIMER_COM_INTERRUPT, /**< COM interrupt, advanced timers only */ - TIMER_TRG_INTERRUPT, /**< Trigger interrupt, general and advanced - timers only */ - TIMER_BREAK_INTERRUPT /**< Break interrupt, advanced timers only. */ + TIMER_UPDATE_INTERRUPT, /**< Update interrupt. */ + TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt. */ + TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt. */ + TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt. */ + TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt. */ + TIMER_COM_INTERRUPT, /**< COM interrupt. */ + TIMER_TRG_INTERRUPT, /**< Trigger interrupt. */ + TIMER_BREAK_INTERRUPT, /**< Break interrupt. */ } timer_interrupt_id; void timer_attach_interrupt(timer_dev *dev, @@ -957,41 +960,46 @@ static inline void timer_dma_set_burst_len(timer_dev *dev, uint8 length) { * Defines the base address for DMA transfers. */ typedef enum timer_dma_base_addr { - TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, /**< Base is control register 1 */ - TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, /**< Base is control register 2 */ - TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, /**< Base is slave mode - control register */ - TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, /**< Base is DMA interrupt enable - register */ - TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, /**< Base is status register */ - TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, /**< Base is event generation - register */ - TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, /**< Base is capture/compare - mode register 1 */ - TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, /**< Base is capture/compare - mode register 2 */ - TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER, /**< Base is capture/compare - enable register */ - TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT, /**< Base is counter */ - TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC, /**< Base is prescaler */ - TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR, /**< Base is auto-reload - register */ - TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR, /**< Base is repetition - counter register */ - TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1, /**< Base is capture/compare - register 1 */ - TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2, /**< Base is capture/compare - register 2 */ - TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3, /**< Base is capture/compare - register 3 */ - TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4, /**< Base is capture/compare - register 4 */ - TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR, /**< Base is break and - dead-time register */ - TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR, /**< Base is DMA control - register */ - TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR /**< Base is DMA address for - full transfer */ + /** Base is control register 1 */ + TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, + /** Base is control register 2 */ + TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, + /** Base is slave mode control register */ + TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, + /** Base is DMA interrupt enable register */ + TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, + /** Base is status register */ + TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, + /** Base is event generation register */ + TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, + /** Base is capture/compare mode register 1 */ + TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, + /** Base is capture/compare mode register 2 */ + TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, + /** Base is capture/compare enable register */ + TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER, + /** Base is counter */ + TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT, + /** Base is prescaler */ + TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC, + /** Base is auto-reload register */ + TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR, + /** Base is repetition counter register */ + TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR, + /** Base is capture/compare register 1 */ + TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1, + /** Base is capture/compare register 2 */ + TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2, + /** Base is capture/compare register 3 */ + TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3, + /** Base is capture/compare register 4 */ + TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4, + /** Base is break and dead-time register */ + TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR, + /** Base is DMA control register */ + TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR, + /** Base is DMA address for full transfer */ + TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR, } timer_dma_base_addr; /** @@ -1027,35 +1035,38 @@ static inline void timer_dma_set_base_addr(timer_dev *dev, * Timer output compare modes. */ typedef enum timer_oc_mode { - TIMER_OC_MODE_FROZEN = 0 << 4, /**< Frozen: comparison between output - compare register and counter has no - effect on the outputs. */ - TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, /**< OCxREF signal is forced - high when the count matches - the channel capture/compare - register. */ - TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, /**< OCxREF signal is forced - low when the counter matches - the channel capture/compare - register. */ - TIMER_OC_MODE_TOGGLE = 3 << 4, /**< OCxREF toggles when counter - matches the cannel capture/compare - register. */ - TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, /**< OCxREF is forced low. */ - TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, /**< OCxREF is forced high. */ - TIMER_OC_MODE_PWM_1 = 6 << 4, /**< PWM mode 1. In upcounting, channel is - active as long as count is less than - channel capture/compare register, else - inactive. In downcounting, channel is - inactive as long as count exceeds - capture/compare register, else - active. */ - TIMER_OC_MODE_PWM_2 = 7 << 4 /**< PWM mode 2. In upcounting, channel is - inactive as long as count is less than - capture/compare register, else active. - In downcounting, channel is active as - long as count exceeds capture/compare - register, else inactive. */ + /** + * Frozen: comparison between output compare register and counter + * has no effect on the outputs. */ + TIMER_OC_MODE_FROZEN = 0 << 4, + /** + * OCxREF signal is forced high when the count matches the channel + * capture/compare register. */ + TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, + /** + * OCxREF signal is forced low when the counter matches the + * channel capture/compare register. */ + TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, + /** + * OCxREF toggles when counter matches the channel capture/compare + * register. */ + TIMER_OC_MODE_TOGGLE = 3 << 4, + /** OCxREF is forced low. */ + TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, + /** OCxREF is forced high. */ + TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, + /** + * PWM mode 1. In upcounting, channel is active as long as count + * is less than channel capture/compare register, else inactive. + * In downcounting, channel is inactive as long as count exceeds + * capture/compare register, else active. */ + TIMER_OC_MODE_PWM_1 = 6 << 4, + /** + * PWM mode 2. In upcounting, channel is inactive as long as count + * is less than capture/compare register, else active. In + * downcounting, channel is active as long as count exceeds + * capture/compare register, else inactive. */ + TIMER_OC_MODE_PWM_2 = 7 << 4, } timer_oc_mode; /** -- cgit v1.2.3 From f32c912c4037fda34c4e6a9905b28f2e7fbe1c6f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:20:42 -0400 Subject: libmaple/timer.h: Nuke useless comment. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index f411f17..e8f3708 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -215,7 +215,7 @@ extern timer_dev *TIMER14; #define TIMER_CR2_OIS2_BIT 10 #define TIMER_CR2_OIS1N_BIT 9 #define TIMER_CR2_OIS1_BIT 8 -#define TIMER_CR2_TI1S_BIT 7 /* tills? yikes */ +#define TIMER_CR2_TI1S_BIT 7 #define TIMER_CR2_CCDS_BIT 3 #define TIMER_CR2_CCUS_BIT 2 #define TIMER_CR2_CCPC_BIT 0 -- cgit v1.2.3 From 441abdc26d8e9fe78836f0a36f87c36a279527f0 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:21:37 -0400 Subject: struct timer_dev: Don't touch ->handlers! Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index e8f3708..c33e8a7 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -127,9 +127,7 @@ typedef struct timer_dev { rcc_clk_id clk_id; /**< RCC clock information */ timer_type type; /**< Timer's type */ voidFuncPtr handlers[]; /**< - * @brief User IRQ handlers - * It's not a good idea to touch these - * directly. + * Don't touch these. Use these instead: * @see timer_attach_interrupt() * @see timer_detach_interrupt() */ } timer_dev; -- cgit v1.2.3 From 856ad1e549deaac38795d60141467f9ed8a3830d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:25:43 -0400 Subject: libmaple/timer.h: Move deprecated bits to bottom. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 133 +++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 66 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index c33e8a7..d675897 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -426,33 +426,6 @@ extern timer_dev *TIMER14; #define TIMER_CCMR2_CC3S_INPUT_TI2 TIMER_CCMR_CCS_INPUT_TI2 #define TIMER_CCMR2_CC3S_INPUT_TRC TIMER_CCMR_CCS_INPUT_TRC -/* Old, copy-paste error CCMR2 bit definitions from previous releases, - * kept for backwards compatibility: */ -/** Deprecated. Use TIMER_CCMR1_CC4S_OUTPUT instead. */ -#define TIMER_CCMR1_CC4S_OUTPUT TIMER_CCMR2_CC4S_OUTPUT -/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI1 instead. */ -#define TIMER_CCMR1_CC4S_INPUT_TI1 TIMER_CCMR2_CC4S_INPUT_TI1 -/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI2 instead. */ -#define TIMER_CCMR1_CC4S_INPUT_TI2 TIMER_CCMR2_CC4S_INPUT_TI2 -/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TRC instead. */ -#define TIMER_CCMR1_CC4S_INPUT_TRC TIMER_CCMR2_CC4S_INPUT_TRC -/** Deprecated. Use TIMER_CCMR2_IC4F instead. */ -#define TIMER_CCMR2_IC2F TIMER_CCMR2_IC4F -/** Deprecated. Use TIMER_CCMR2_IC4PSC instead. */ -#define TIMER_CCMR2_IC2PSC TIMER_CCMR2_IC4PSC -/** Deprecated. Use TIMER_CCMR2_IC3F instead. */ -#define TIMER_CCMR2_IC1F TIMER_CCMR2_IC3F -/** Deprecated. Use TIMER_CCMR2_IC3PSC instead. */ -#define TIMER_CCMR2_IC1PSC TIMER_CCMR2_IC3PSC -/** Deprecated. Use TIMER_CCMR1_CC3S_OUTPUT instead. */ -#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR2_CC3S_OUTPUT -/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI1 instead. */ -#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR2_CC3S_INPUT_TI1 -/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI2 instead. */ -#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR2_CC3S_INPUT_TI2 -/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TRC instead. */ -#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR2_CC3S_INPUT_TRC - /* Capture/compare enable register (CCER) */ #define TIMER_CCER_CC4P_BIT 13 @@ -550,45 +523,6 @@ extern timer_dev *TIMER14; #define TIMER_DCR_DBA_DCR 0x12 #define TIMER_DCR_DBA_DMAR 0x13 -/* Old, erroneous bit definitions from previous releases, kept for - * backwards compatibility: */ -/** Deprecated. Use TIMER_DCR_DBL_1_XFER instead. */ -#define TIMER_DCR_DBL_1BYTE TIMER_DCR_DBL_1_XFER -/** Deprecated. Use TIMER_DCR_DBL_2_XFER instead. */ -#define TIMER_DCR_DBL_2BYTE TIMER_DCR_DBL_2_XFER -/** Deprecated. Use TIMER_DCR_DBL_3_XFER instead. */ -#define TIMER_DCR_DBL_3BYTE TIMER_DCR_DBL_3_XFER -/** Deprecated. Use TIMER_DCR_DBL_4_XFER instead. */ -#define TIMER_DCR_DBL_4BYTE TIMER_DCR_DBL_4_XFER -/** Deprecated. Use TIMER_DCR_DBL_5_XFER instead. */ -#define TIMER_DCR_DBL_5BYTE TIMER_DCR_DBL_5_XFER -/** Deprecated. Use TIMER_DCR_DBL_6_XFER instead. */ -#define TIMER_DCR_DBL_6BYTE TIMER_DCR_DBL_6_XFER -/** Deprecated. Use TIMER_DCR_DBL_7_XFER instead. */ -#define TIMER_DCR_DBL_7BYTE TIMER_DCR_DBL_7_XFER -/** Deprecated. Use TIMER_DCR_DBL_8_XFER instead. */ -#define TIMER_DCR_DBL_8BYTE TIMER_DCR_DBL_8_XFER -/** Deprecated. Use TIMER_DCR_DBL_9_XFER instead. */ -#define TIMER_DCR_DBL_9BYTE TIMER_DCR_DBL_9_XFER -/** Deprecated. Use TIMER_DCR_DBL_10_XFER instead. */ -#define TIMER_DCR_DBL_10BYTE TIMER_DCR_DBL_10_XFER -/** Deprecated. Use TIMER_DCR_DBL_11_XFER instead. */ -#define TIMER_DCR_DBL_11BYTE TIMER_DCR_DBL_11_XFER -/** Deprecated. Use TIMER_DCR_DBL_12_XFER instead. */ -#define TIMER_DCR_DBL_12BYTE TIMER_DCR_DBL_12_XFER -/** Deprecated. Use TIMER_DCR_DBL_13_XFER instead. */ -#define TIMER_DCR_DBL_13BYTE TIMER_DCR_DBL_13_XFER -/** Deprecated. Use TIMER_DCR_DBL_14_XFER instead. */ -#define TIMER_DCR_DBL_14BYTE TIMER_DCR_DBL_14_XFER -/** Deprecated. Use TIMER_DCR_DBL_15_XFER instead. */ -#define TIMER_DCR_DBL_15BYTE TIMER_DCR_DBL_15_XFER -/** Deprecated. Use TIMER_DCR_DBL_16_XFER instead. */ -#define TIMER_DCR_DBL_16BYTE TIMER_DCR_DBL_16_XFER -/** Deprecated. Use TIMER_DCR_DBL_17_XFER instead. */ -#define TIMER_DCR_DBL_17BYTE TIMER_DCR_DBL_17_XFER -/** Deprecated. Use TIMER_DCR_DBL_18_XFER instead. */ -#define TIMER_DCR_DBL_18BYTE TIMER_DCR_DBL_18_XFER - /* * Convenience routines */ @@ -1102,6 +1036,73 @@ static inline void timer_oc_set_mode(timer_dev *dev, *ccmr = tmp; } +/* + * Old, erroneous bit definitions from previous releases, kept for + * backwards compatibility: + */ + +/** Deprecated. Use TIMER_CCMR1_CC4S_OUTPUT instead. */ +#define TIMER_CCMR1_CC4S_OUTPUT TIMER_CCMR2_CC4S_OUTPUT +/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI1 instead. */ +#define TIMER_CCMR1_CC4S_INPUT_TI1 TIMER_CCMR2_CC4S_INPUT_TI1 +/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TI2 instead. */ +#define TIMER_CCMR1_CC4S_INPUT_TI2 TIMER_CCMR2_CC4S_INPUT_TI2 +/** Deprecated. Use TIMER_CCMR1_CC4S_INPUT_TRC instead. */ +#define TIMER_CCMR1_CC4S_INPUT_TRC TIMER_CCMR2_CC4S_INPUT_TRC +/** Deprecated. Use TIMER_CCMR2_IC4F instead. */ +#define TIMER_CCMR2_IC2F TIMER_CCMR2_IC4F +/** Deprecated. Use TIMER_CCMR2_IC4PSC instead. */ +#define TIMER_CCMR2_IC2PSC TIMER_CCMR2_IC4PSC +/** Deprecated. Use TIMER_CCMR2_IC3F instead. */ +#define TIMER_CCMR2_IC1F TIMER_CCMR2_IC3F +/** Deprecated. Use TIMER_CCMR2_IC3PSC instead. */ +#define TIMER_CCMR2_IC1PSC TIMER_CCMR2_IC3PSC +/** Deprecated. Use TIMER_CCMR1_CC3S_OUTPUT instead. */ +#define TIMER_CCMR1_CC3S_OUTPUT TIMER_CCMR2_CC3S_OUTPUT +/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI1 instead. */ +#define TIMER_CCMR1_CC3S_INPUT_TI1 TIMER_CCMR2_CC3S_INPUT_TI1 +/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TI2 instead. */ +#define TIMER_CCMR1_CC3S_INPUT_TI2 TIMER_CCMR2_CC3S_INPUT_TI2 +/** Deprecated. Use TIMER_CCMR1_CC3S_INPUT_TRC instead. */ +#define TIMER_CCMR1_CC3S_INPUT_TRC TIMER_CCMR2_CC3S_INPUT_TRC + +/** Deprecated. Use TIMER_DCR_DBL_1_XFER instead. */ +#define TIMER_DCR_DBL_1BYTE TIMER_DCR_DBL_1_XFER +/** Deprecated. Use TIMER_DCR_DBL_2_XFER instead. */ +#define TIMER_DCR_DBL_2BYTE TIMER_DCR_DBL_2_XFER +/** Deprecated. Use TIMER_DCR_DBL_3_XFER instead. */ +#define TIMER_DCR_DBL_3BYTE TIMER_DCR_DBL_3_XFER +/** Deprecated. Use TIMER_DCR_DBL_4_XFER instead. */ +#define TIMER_DCR_DBL_4BYTE TIMER_DCR_DBL_4_XFER +/** Deprecated. Use TIMER_DCR_DBL_5_XFER instead. */ +#define TIMER_DCR_DBL_5BYTE TIMER_DCR_DBL_5_XFER +/** Deprecated. Use TIMER_DCR_DBL_6_XFER instead. */ +#define TIMER_DCR_DBL_6BYTE TIMER_DCR_DBL_6_XFER +/** Deprecated. Use TIMER_DCR_DBL_7_XFER instead. */ +#define TIMER_DCR_DBL_7BYTE TIMER_DCR_DBL_7_XFER +/** Deprecated. Use TIMER_DCR_DBL_8_XFER instead. */ +#define TIMER_DCR_DBL_8BYTE TIMER_DCR_DBL_8_XFER +/** Deprecated. Use TIMER_DCR_DBL_9_XFER instead. */ +#define TIMER_DCR_DBL_9BYTE TIMER_DCR_DBL_9_XFER +/** Deprecated. Use TIMER_DCR_DBL_10_XFER instead. */ +#define TIMER_DCR_DBL_10BYTE TIMER_DCR_DBL_10_XFER +/** Deprecated. Use TIMER_DCR_DBL_11_XFER instead. */ +#define TIMER_DCR_DBL_11BYTE TIMER_DCR_DBL_11_XFER +/** Deprecated. Use TIMER_DCR_DBL_12_XFER instead. */ +#define TIMER_DCR_DBL_12BYTE TIMER_DCR_DBL_12_XFER +/** Deprecated. Use TIMER_DCR_DBL_13_XFER instead. */ +#define TIMER_DCR_DBL_13BYTE TIMER_DCR_DBL_13_XFER +/** Deprecated. Use TIMER_DCR_DBL_14_XFER instead. */ +#define TIMER_DCR_DBL_14BYTE TIMER_DCR_DBL_14_XFER +/** Deprecated. Use TIMER_DCR_DBL_15_XFER instead. */ +#define TIMER_DCR_DBL_15BYTE TIMER_DCR_DBL_15_XFER +/** Deprecated. Use TIMER_DCR_DBL_16_XFER instead. */ +#define TIMER_DCR_DBL_16BYTE TIMER_DCR_DBL_16_XFER +/** Deprecated. Use TIMER_DCR_DBL_17_XFER instead. */ +#define TIMER_DCR_DBL_17BYTE TIMER_DCR_DBL_17_XFER +/** Deprecated. Use TIMER_DCR_DBL_18_XFER instead. */ +#define TIMER_DCR_DBL_18BYTE TIMER_DCR_DBL_18_XFER + #ifdef __cplusplus } // extern "C" #endif -- cgit v1.2.3 From 5dba81cd6728a4a2c561e0fe0cac42c8b8a264e7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:28:08 -0400 Subject: libmaple/timer.h: Lose BIT(). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 180 +++++++++++++++++++------------------- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index d675897..a23b81b 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -192,17 +192,17 @@ extern timer_dev *TIMER14; #define TIMER_CR1_CKD_1TCKINT (0x0 << 8) #define TIMER_CR1_CKD_2TCKINT (0x1 << 8) #define TIMER_CR1_CKD_4TICKINT (0x2 << 8) -#define TIMER_CR1_ARPE BIT(TIMER_CR1_ARPE_BIT) +#define TIMER_CR1_ARPE (1U << TIMER_CR1_ARPE_BIT) #define TIMER_CR1_CKD_CMS (0x3 << 5) #define TIMER_CR1_CKD_CMS_EDGE (0x0 << 5) #define TIMER_CR1_CKD_CMS_CENTER1 (0x1 << 5) #define TIMER_CR1_CKD_CMS_CENTER2 (0x2 << 5) #define TIMER_CR1_CKD_CMS_CENTER3 (0x3 << 5) -#define TIMER_CR1_DIR BIT(TIMER_CR1_DIR_BIT) -#define TIMER_CR1_OPM BIT(TIMER_CR1_OPM_BIT) -#define TIMER_CR1_URS BIT(TIMER_CR1_URS_BIT) -#define TIMER_CR1_UDIS BIT(TIMER_CR1_UDIS_BIT) -#define TIMER_CR1_CEN BIT(TIMER_CR1_CEN_BIT) +#define TIMER_CR1_DIR (1U << TIMER_CR1_DIR_BIT) +#define TIMER_CR1_OPM (1U << TIMER_CR1_OPM_BIT) +#define TIMER_CR1_URS (1U << TIMER_CR1_URS_BIT) +#define TIMER_CR1_UDIS (1U << TIMER_CR1_UDIS_BIT) +#define TIMER_CR1_CEN (1U << TIMER_CR1_CEN_BIT) /* Control register 2 (CR2) */ @@ -218,14 +218,14 @@ extern timer_dev *TIMER14; #define TIMER_CR2_CCUS_BIT 2 #define TIMER_CR2_CCPC_BIT 0 -#define TIMER_CR2_OIS4 BIT(TIMER_CR2_OIS4_BIT) -#define TIMER_CR2_OIS3N BIT(TIMER_CR2_OIS3N_BIT) -#define TIMER_CR2_OIS3 BIT(TIMER_CR2_OIS3_BIT) -#define TIMER_CR2_OIS2N BIT(TIMER_CR2_OIS2N_BIT) -#define TIMER_CR2_OIS2 BIT(TIMER_CR2_OIS2_BIT) -#define TIMER_CR2_OIS1N BIT(TIMER_CR2_OIS1N_BIT) -#define TIMER_CR2_OIS1 BIT(TIMER_CR2_OIS1_BIT) -#define TIMER_CR2_TI1S BIT(TIMER_CR2_TI1S_BIT) +#define TIMER_CR2_OIS4 (1U << TIMER_CR2_OIS4_BIT) +#define TIMER_CR2_OIS3N (1U << TIMER_CR2_OIS3N_BIT) +#define TIMER_CR2_OIS3 (1U << TIMER_CR2_OIS3_BIT) +#define TIMER_CR2_OIS2N (1U << TIMER_CR2_OIS2N_BIT) +#define TIMER_CR2_OIS2 (1U << TIMER_CR2_OIS2_BIT) +#define TIMER_CR2_OIS1N (1U << TIMER_CR2_OIS1N_BIT) +#define TIMER_CR2_OIS1 (1U << TIMER_CR2_OIS1_BIT) +#define TIMER_CR2_TI1S (1U << TIMER_CR2_TI1S_BIT) #define TIMER_CR2_MMS (0x7 << 4) #define TIMER_CR2_MMS_RESET (0x0 << 4) #define TIMER_CR2_MMS_ENABLE (0x1 << 4) @@ -235,9 +235,9 @@ extern timer_dev *TIMER14; #define TIMER_CR2_MMS_COMPARE_OC2REF (0x5 << 4) #define TIMER_CR2_MMS_COMPARE_OC3REF (0x6 << 4) #define TIMER_CR2_MMS_COMPARE_OC4REF (0x7 << 4) -#define TIMER_CR2_CCDS BIT(TIMER_CR2_CCDS_BIT) -#define TIMER_CR2_CCUS BIT(TIMER_CR2_CCUS_BIT) -#define TIMER_CR2_CCPC BIT(TIMER_CR2_CCPC_BIT) +#define TIMER_CR2_CCDS (1U << TIMER_CR2_CCDS_BIT) +#define TIMER_CR2_CCUS (1U << TIMER_CR2_CCUS_BIT) +#define TIMER_CR2_CCPC (1U << TIMER_CR2_CCPC_BIT) /* Slave mode control register (SMCR) */ @@ -245,15 +245,15 @@ extern timer_dev *TIMER14; #define TIMER_SMCR_ECE_BIT 14 #define TIMER_SMCR_MSM_BIT 7 -#define TIMER_SMCR_ETP BIT(TIMER_SMCR_ETP_BIT) -#define TIMER_SMCR_ECE BIT(TIMER_SMCR_ECE_BIT) +#define TIMER_SMCR_ETP (1U << TIMER_SMCR_ETP_BIT) +#define TIMER_SMCR_ECE (1U << TIMER_SMCR_ECE_BIT) #define TIMER_SMCR_ETPS (0x3 << 12) #define TIMER_SMCR_ETPS_OFF (0x0 << 12) #define TIMER_SMCR_ETPS_DIV2 (0x1 << 12) #define TIMER_SMCR_ETPS_DIV4 (0x2 << 12) #define TIMER_SMCR_ETPS_DIV8 (0x3 << 12) #define TIMER_SMCR_ETF (0xF << 12) -#define TIMER_SMCR_MSM BIT(TIMER_SMCR_MSM_BIT) +#define TIMER_SMCR_MSM (1U << TIMER_SMCR_MSM_BIT) #define TIMER_SMCR_TS (0x3 << 4) #define TIMER_SMCR_TS_ITR0 (0x0 << 4) #define TIMER_SMCR_TS_ITR1 (0x1 << 4) @@ -291,21 +291,21 @@ extern timer_dev *TIMER14; #define TIMER_DIER_CC1IE_BIT 1 #define TIMER_DIER_UIE_BIT 0 -#define TIMER_DIER_TDE BIT(TIMER_DIER_TDE_BIT) -#define TIMER_DIER_COMDE BIT(TIMER_DIER_COMDE_BIT) -#define TIMER_DIER_CC4DE BIT(TIMER_DIER_CC4DE_BIT) -#define TIMER_DIER_CC3DE BIT(TIMER_DIER_CC3DE_BIT) -#define TIMER_DIER_CC2DE BIT(TIMER_DIER_CC2DE_BIT) -#define TIMER_DIER_CC1DE BIT(TIMER_DIER_CC1DE_BIT) -#define TIMER_DIER_UDE BIT(TIMER_DIER_UDE_BIT) -#define TIMER_DIER_BIE BIT(TIMER_DIER_BIE_BIT) -#define TIMER_DIER_TIE BIT(TIMER_DIER_TIE_BIT) -#define TIMER_DIER_COMIE BIT(TIMER_DIER_COMIE_BIT) -#define TIMER_DIER_CC4IE BIT(TIMER_DIER_CC4IE_BIT) -#define TIMER_DIER_CC3IE BIT(TIMER_DIER_CC3IE_BIT) -#define TIMER_DIER_CC2IE BIT(TIMER_DIER_CC2IE_BIT) -#define TIMER_DIER_CC1IE BIT(TIMER_DIER_CC1IE_BIT) -#define TIMER_DIER_UIE BIT(TIMER_DIER_UIE_BIT) +#define TIMER_DIER_TDE (1U << TIMER_DIER_TDE_BIT) +#define TIMER_DIER_COMDE (1U << TIMER_DIER_COMDE_BIT) +#define TIMER_DIER_CC4DE (1U << TIMER_DIER_CC4DE_BIT) +#define TIMER_DIER_CC3DE (1U << TIMER_DIER_CC3DE_BIT) +#define TIMER_DIER_CC2DE (1U << TIMER_DIER_CC2DE_BIT) +#define TIMER_DIER_CC1DE (1U << TIMER_DIER_CC1DE_BIT) +#define TIMER_DIER_UDE (1U << TIMER_DIER_UDE_BIT) +#define TIMER_DIER_BIE (1U << TIMER_DIER_BIE_BIT) +#define TIMER_DIER_TIE (1U << TIMER_DIER_TIE_BIT) +#define TIMER_DIER_COMIE (1U << TIMER_DIER_COMIE_BIT) +#define TIMER_DIER_CC4IE (1U << TIMER_DIER_CC4IE_BIT) +#define TIMER_DIER_CC3IE (1U << TIMER_DIER_CC3IE_BIT) +#define TIMER_DIER_CC2IE (1U << TIMER_DIER_CC2IE_BIT) +#define TIMER_DIER_CC1IE (1U << TIMER_DIER_CC1IE_BIT) +#define TIMER_DIER_UIE (1U << TIMER_DIER_UIE_BIT) /* Status register (SR) */ @@ -322,18 +322,18 @@ extern timer_dev *TIMER14; #define TIMER_SR_CC1IF_BIT 1 #define TIMER_SR_UIF_BIT 0 -#define TIMER_SR_CC4OF BIT(TIMER_SR_CC4OF_BIT) -#define TIMER_SR_CC3OF BIT(TIMER_SR_CC3OF_BIT) -#define TIMER_SR_CC2OF BIT(TIMER_SR_CC2OF_BIT) -#define TIMER_SR_CC1OF BIT(TIMER_SR_CC1OF_BIT) -#define TIMER_SR_BIF BIT(TIMER_SR_BIF_BIT) -#define TIMER_SR_TIF BIT(TIMER_SR_TIF_BIT) -#define TIMER_SR_COMIF BIT(TIMER_SR_COMIF_BIT) -#define TIMER_SR_CC4IF BIT(TIMER_SR_CC4IF_BIT) -#define TIMER_SR_CC3IF BIT(TIMER_SR_CC3IF_BIT) -#define TIMER_SR_CC2IF BIT(TIMER_SR_CC2IF_BIT) -#define TIMER_SR_CC1IF BIT(TIMER_SR_CC1IF_BIT) -#define TIMER_SR_UIF BIT(TIMER_SR_UIF_BIT) +#define TIMER_SR_CC4OF (1U << TIMER_SR_CC4OF_BIT) +#define TIMER_SR_CC3OF (1U << TIMER_SR_CC3OF_BIT) +#define TIMER_SR_CC2OF (1U << TIMER_SR_CC2OF_BIT) +#define TIMER_SR_CC1OF (1U << TIMER_SR_CC1OF_BIT) +#define TIMER_SR_BIF (1U << TIMER_SR_BIF_BIT) +#define TIMER_SR_TIF (1U << TIMER_SR_TIF_BIT) +#define TIMER_SR_COMIF (1U << TIMER_SR_COMIF_BIT) +#define TIMER_SR_CC4IF (1U << TIMER_SR_CC4IF_BIT) +#define TIMER_SR_CC3IF (1U << TIMER_SR_CC3IF_BIT) +#define TIMER_SR_CC2IF (1U << TIMER_SR_CC2IF_BIT) +#define TIMER_SR_CC1IF (1U << TIMER_SR_CC1IF_BIT) +#define TIMER_SR_UIF (1U << TIMER_SR_UIF_BIT) /* Event generation register (EGR) */ @@ -346,14 +346,14 @@ extern timer_dev *TIMER14; #define TIMER_EGR_CC1G_BIT 1 #define TIMER_EGR_UG_BIT 0 -#define TIMER_EGR_BG BIT(TIMER_EGR_BG_BIT) -#define TIMER_EGR_TG BIT(TIMER_EGR_TG_BIT) -#define TIMER_EGR_COMG BIT(TIMER_EGR_COMG_BIT) -#define TIMER_EGR_CC4G BIT(TIMER_EGR_CC4G_BIT) -#define TIMER_EGR_CC3G BIT(TIMER_EGR_CC3G_BIT) -#define TIMER_EGR_CC2G BIT(TIMER_EGR_CC2G_BIT) -#define TIMER_EGR_CC1G BIT(TIMER_EGR_CC1G_BIT) -#define TIMER_EGR_UG BIT(TIMER_EGR_UG_BIT) +#define TIMER_EGR_BG (1U << TIMER_EGR_BG_BIT) +#define TIMER_EGR_TG (1U << TIMER_EGR_TG_BIT) +#define TIMER_EGR_COMG (1U << TIMER_EGR_COMG_BIT) +#define TIMER_EGR_CC4G (1U << TIMER_EGR_CC4G_BIT) +#define TIMER_EGR_CC3G (1U << TIMER_EGR_CC3G_BIT) +#define TIMER_EGR_CC2G (1U << TIMER_EGR_CC2G_BIT) +#define TIMER_EGR_CC1G (1U << TIMER_EGR_CC1G_BIT) +#define TIMER_EGR_UG (1U << TIMER_EGR_UG_BIT) /* Capture/compare mode registers, common values */ @@ -371,22 +371,22 @@ extern timer_dev *TIMER14; #define TIMER_CCMR1_OC1PE_BIT 3 #define TIMER_CCMR1_OC1FE_BIT 2 -#define TIMER_CCMR1_OC2CE BIT(TIMER_CCMR1_OC2CE_BIT) +#define TIMER_CCMR1_OC2CE (1U << TIMER_CCMR1_OC2CE_BIT) #define TIMER_CCMR1_OC2M (0x3 << 12) #define TIMER_CCMR1_IC2F (0xF << 12) -#define TIMER_CCMR1_OC2PE BIT(TIMER_CCMR1_OC2PE_BIT) -#define TIMER_CCMR1_OC2FE BIT(TIMER_CCMR1_OC2FE_BIT) +#define TIMER_CCMR1_OC2PE (1U << TIMER_CCMR1_OC2PE_BIT) +#define TIMER_CCMR1_OC2FE (1U << TIMER_CCMR1_OC2FE_BIT) #define TIMER_CCMR1_IC2PSC (0x3 << 10) #define TIMER_CCMR1_CC2S (0x3 << 8) #define TIMER_CCMR1_CC2S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) #define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) #define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) #define TIMER_CCMR1_CC2S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) -#define TIMER_CCMR1_OC1CE BIT(TIMER_CCMR1_OC1CE_BIT) +#define TIMER_CCMR1_OC1CE (1U << TIMER_CCMR1_OC1CE_BIT) #define TIMER_CCMR1_OC1M (0x3 << 4) #define TIMER_CCMR1_IC1F (0xF << 4) -#define TIMER_CCMR1_OC1PE BIT(TIMER_CCMR1_OC1PE_BIT) -#define TIMER_CCMR1_OC1FE BIT(TIMER_CCMR1_OC1FE_BIT) +#define TIMER_CCMR1_OC1PE (1U << TIMER_CCMR1_OC1PE_BIT) +#define TIMER_CCMR1_OC1FE (1U << TIMER_CCMR1_OC1FE_BIT) #define TIMER_CCMR1_IC1PSC (0x3 << 2) #define TIMER_CCMR1_CC1S 0x3 #define TIMER_CCMR1_CC1S_OUTPUT TIMER_CCMR_CCS_OUTPUT @@ -403,22 +403,22 @@ extern timer_dev *TIMER14; #define TIMER_CCMR2_OC3PE_BIT 3 #define TIMER_CCMR2_OC3FE_BIT 2 -#define TIMER_CCMR2_OC4CE BIT(TIMER_CCMR2_OC4CE_BIT) +#define TIMER_CCMR2_OC4CE (1U << TIMER_CCMR2_OC4CE_BIT) #define TIMER_CCMR2_OC4M (0x3 << 12) #define TIMER_CCMR2_IC4F (0xF << 12) -#define TIMER_CCMR2_OC4PE BIT(TIMER_CCMR2_OC4PE_BIT) -#define TIMER_CCMR2_OC4FE BIT(TIMER_CCMR2_OC4FE_BIT) +#define TIMER_CCMR2_OC4PE (1U << TIMER_CCMR2_OC4PE_BIT) +#define TIMER_CCMR2_OC4FE (1U << TIMER_CCMR2_OC4FE_BIT) #define TIMER_CCMR2_IC4PSC (0x3 << 10) #define TIMER_CCMR2_CC4S (0x3 << 8) #define TIMER_CCMR2_CC4S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) #define TIMER_CCMR2_CC4S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) #define TIMER_CCMR2_CC4S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) #define TIMER_CCMR2_CC4S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) -#define TIMER_CCMR2_OC3CE BIT(TIMER_CCMR2_OC3CE_BIT) +#define TIMER_CCMR2_OC3CE (1U << TIMER_CCMR2_OC3CE_BIT) #define TIMER_CCMR2_OC3M (0x3 << 4) #define TIMER_CCMR2_IC3F (0xF << 4) -#define TIMER_CCMR2_OC3PE BIT(TIMER_CCMR2_OC3PE_BIT) -#define TIMER_CCMR2_OC3FE BIT(TIMER_CCMR2_OC3FE_BIT) +#define TIMER_CCMR2_OC3PE (1U << TIMER_CCMR2_OC3PE_BIT) +#define TIMER_CCMR2_OC3FE (1U << TIMER_CCMR2_OC3FE_BIT) #define TIMER_CCMR2_IC3PSC (0x3 << 2) #define TIMER_CCMR2_CC3S 0x3 #define TIMER_CCMR2_CC3S_OUTPUT TIMER_CCMR_CCS_OUTPUT @@ -443,20 +443,20 @@ extern timer_dev *TIMER14; #define TIMER_CCER_CC1P_BIT 1 #define TIMER_CCER_CC1E_BIT 0 -#define TIMER_CCER_CC4P BIT(TIMER_CCER_CC4P_BIT) -#define TIMER_CCER_CC4E BIT(TIMER_CCER_CC4E_BIT) -#define TIMER_CCER_CC3NP BIT(TIMER_CCER_CC3NP_BIT) -#define TIMER_CCER_CC3NE BIT(TIMER_CCER_CC3NE_BIT) -#define TIMER_CCER_CC3P BIT(TIMER_CCER_CC3P_BIT) -#define TIMER_CCER_CC3E BIT(TIMER_CCER_CC3E_BIT) -#define TIMER_CCER_CC2NP BIT(TIMER_CCER_CC2NP_BIT) -#define TIMER_CCER_CC2NE BIT(TIMER_CCER_CC2NE_BIT) -#define TIMER_CCER_CC2P BIT(TIMER_CCER_CC2P_BIT) -#define TIMER_CCER_CC2E BIT(TIMER_CCER_CC2E_BIT) -#define TIMER_CCER_CC1NP BIT(TIMER_CCER_CC1NP_BIT) -#define TIMER_CCER_CC1NE BIT(TIMER_CCER_CC1NE_BIT) -#define TIMER_CCER_CC1P BIT(TIMER_CCER_CC1P_BIT) -#define TIMER_CCER_CC1E BIT(TIMER_CCER_CC1E_BIT) +#define TIMER_CCER_CC4P (1U << TIMER_CCER_CC4P_BIT) +#define TIMER_CCER_CC4E (1U << TIMER_CCER_CC4E_BIT) +#define TIMER_CCER_CC3NP (1U << TIMER_CCER_CC3NP_BIT) +#define TIMER_CCER_CC3NE (1U << TIMER_CCER_CC3NE_BIT) +#define TIMER_CCER_CC3P (1U << TIMER_CCER_CC3P_BIT) +#define TIMER_CCER_CC3E (1U << TIMER_CCER_CC3E_BIT) +#define TIMER_CCER_CC2NP (1U << TIMER_CCER_CC2NP_BIT) +#define TIMER_CCER_CC2NE (1U << TIMER_CCER_CC2NE_BIT) +#define TIMER_CCER_CC2P (1U << TIMER_CCER_CC2P_BIT) +#define TIMER_CCER_CC2E (1U << TIMER_CCER_CC2E_BIT) +#define TIMER_CCER_CC1NP (1U << TIMER_CCER_CC1NP_BIT) +#define TIMER_CCER_CC1NE (1U << TIMER_CCER_CC1NE_BIT) +#define TIMER_CCER_CC1P (1U << TIMER_CCER_CC1P_BIT) +#define TIMER_CCER_CC1E (1U << TIMER_CCER_CC1E_BIT) /* Break and dead-time register (BDTR) */ @@ -467,12 +467,12 @@ extern timer_dev *TIMER14; #define TIMER_BDTR_OSSR_BIT 11 #define TIMER_BDTR_OSSI_BIT 10 -#define TIMER_BDTR_MOE BIT(TIMER_BDTR_MOE_BIT) -#define TIMER_BDTR_AOE BIT(TIMER_BDTR_AOE_BIT) -#define TIMER_BDTR_BKP BIT(TIMER_BDTR_BKP_BIT) -#define TIMER_BDTR_BKE BIT(TIMER_BDTR_BKE_BIT) -#define TIMER_BDTR_OSSR BIT(TIMER_BDTR_OSSR_BIT) -#define TIMER_BDTR_OSSI BIT(TIMER_BDTR_OSSI_BIT) +#define TIMER_BDTR_MOE (1U << TIMER_BDTR_MOE_BIT) +#define TIMER_BDTR_AOE (1U << TIMER_BDTR_AOE_BIT) +#define TIMER_BDTR_BKP (1U << TIMER_BDTR_BKP_BIT) +#define TIMER_BDTR_BKE (1U << TIMER_BDTR_BKE_BIT) +#define TIMER_BDTR_OSSR (1U << TIMER_BDTR_OSSR_BIT) +#define TIMER_BDTR_OSSI (1U << TIMER_BDTR_OSSI_BIT) #define TIMER_BDTR_LOCK (0x3 << 8) #define TIMER_BDTR_LOCK_OFF (0x0 << 8) #define TIMER_BDTR_LOCK_LEVEL1 (0x1 << 8) @@ -1006,9 +1006,9 @@ typedef enum timer_oc_mode { * @see timer_oc_set_mode() */ typedef enum timer_oc_mode_flags { - TIMER_OC_CE = BIT(7), /**< Output compare clear enable. */ - TIMER_OC_PE = BIT(3), /**< Output compare preload enable. */ - TIMER_OC_FE = BIT(2) /**< Output compare fast enable. */ + TIMER_OC_CE = 1U << 7, /**< Output compare clear enable. */ + TIMER_OC_PE = 1U << 3, /**< Output compare preload enable. */ + TIMER_OC_FE = 1U << 2, /**< Output compare fast enable. */ } timer_oc_mode_flags; /** -- cgit v1.2.3 From 3e177c9e1a82ddceee27be7ed81ea64ea68845f2 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:29:45 -0400 Subject: libmaple/timer.h: Capitalization fix Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/timer.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/include/libmaple/timer.h b/libmaple/include/libmaple/timer.h index a23b81b..995f868 100644 --- a/libmaple/include/libmaple/timer.h +++ b/libmaple/include/libmaple/timer.h @@ -52,7 +52,7 @@ typedef struct timer_adv_reg_map { __io uint32 CR1; /**< Control register 1 */ __io uint32 CR2; /**< Control register 2 */ __io uint32 SMCR; /**< Slave mode control register */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 DIER; /**< DMA/interrupt enable register */ __io uint32 SR; /**< Status register */ __io uint32 EGR; /**< Event generation register */ __io uint32 CCMR1; /**< Capture/compare mode register 1 */ @@ -81,7 +81,7 @@ typedef struct timer_bas_reg_map { __io uint32 CR1; /**< Control register 1 */ __io uint32 CR2; /**< Control register 2 */ const uint32 RESERVED1; /**< Reserved */ - __io uint32 DIER; /**< DMA/Interrupt enable register */ + __io uint32 DIER; /**< DMA/interrupt enable register */ __io uint32 SR; /**< Status register */ __io uint32 EGR; /**< Event generation register */ const uint32 RESERVED2; /**< Reserved */ -- cgit v1.2.3 From 50cf479bc593bfcf68debac2812bcf7ce2862c52 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:45:10 -0400 Subject: Move syscalls.c into Wirish. libmaple takes orders, it doesn't give them. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 1 - libmaple/syscalls.c | 169 ---------------------------------------------------- wirish/rules.mk | 1 + wirish/syscalls.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+), 170 deletions(-) delete mode 100644 libmaple/syscalls.c create mode 100644 wirish/syscalls.c diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 08c4c02..649e4c8 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -22,7 +22,6 @@ cSRCS_$(d) += nvic.c cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c # cSRCS_$(d) += spi.c -cSRCS_$(d) += syscalls.c cSRCS_$(d) += systick.c cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c diff --git a/libmaple/syscalls.c b/libmaple/syscalls.c deleted file mode 100644 index 30a63bf..0000000 --- a/libmaple/syscalls.c +++ /dev/null @@ -1,169 +0,0 @@ -/****************************************************************************** - * The MIT License - * - * Copyright (c) 2010 Perry Hung. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - *****************************************************************************/ - -/** - * @file libmaple/syscalls.c - * @brief newlib stubs - * - * Low level system routines used by Newlib for basic I/O and memory - * allocation. - */ - -#include - -#include -#include - -/* If CONFIG_HEAP_START (or CONFIG_HEAP_END) isn't defined, then - * assume _lm_heap_start (resp. _lm_heap_end) is appropriately set by - * the linker */ -#ifndef CONFIG_HEAP_START -extern char _lm_heap_start; -#define CONFIG_HEAP_START ((caddr_t)&_lm_heap_start) -#endif -#ifndef CONFIG_HEAP_END -extern char _lm_heap_end; -#define CONFIG_HEAP_END ((caddr_t)&_lm_heap_end) -#endif - -/* - * _sbrk -- Increment the program break. - * - * Get incr bytes more RAM (for use by the heap). malloc() and - * friends call this function behind the scenes. - */ -caddr_t _sbrk(int incr) { - static caddr_t pbreak = NULL; /* current program break */ - caddr_t ret; - - if (pbreak == NULL) { - pbreak = CONFIG_HEAP_START; - } - - if ((CONFIG_HEAP_END - pbreak < incr) || - (pbreak - CONFIG_HEAP_START < -incr)) { - errno = ENOMEM; - return (caddr_t)-1; - } - - ret = pbreak; - pbreak += incr; - return ret; -} - -int _open(const char *path, int flags, ...) { - return 1; -} - -int _close(int fd) { - return 0; -} - -int _fstat(int fd, struct stat *st) { - st->st_mode = S_IFCHR; - return 0; -} - -int _isatty(int fd) { - return 1; -} - -int isatty(int fd) { - return 1; -} - -int _lseek(int fd, off_t pos, int whence) { - return -1; -} - -unsigned char getch(void) { - return 0; -} - - -int _read(int fd, char *buf, size_t cnt) { - *buf = getch(); - - return 1; -} - -void putch(unsigned char c) { -} - -void cgets(char *s, int bufsize) { - char *p; - int c; - int i; - - for (i = 0; i < bufsize; i++) { - *(s+i) = 0; - } -// memset(s, 0, bufsize); - - p = s; - - for (p = s; p < s + bufsize-1;) { - c = getch(); - switch (c) { - case '\r' : - case '\n' : - putch('\r'); - putch('\n'); - *p = '\n'; - return; - - case '\b' : - if (p > s) { - *p-- = 0; - putch('\b'); - putch(' '); - putch('\b'); - } - break; - - default : - putch(c); - *p++ = c; - break; - } - } - return; -} - -int _write(int fd, const char *buf, size_t cnt) { - int i; - - for (i = 0; i < cnt; i++) - putch(buf[i]); - - return cnt; -} - -/* Override fgets() in newlib with a version that does line editing */ -char *fgets(char *s, int bufsize, void *f) { - cgets(s, bufsize); - return s; -} diff --git a/wirish/rules.mk b/wirish/rules.mk index a198c2d..acf4c46 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -20,6 +20,7 @@ CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) $(WIRISH_INCLUDES) -I$(d) # Local rules and targets sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c +cSRCS_$(d) += syscalls.c cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += ext_interrupts.cpp diff --git a/wirish/syscalls.c b/wirish/syscalls.c new file mode 100644 index 0000000..d365e15 --- /dev/null +++ b/wirish/syscalls.c @@ -0,0 +1,169 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/syscalls.c + * @brief newlib stubs + * + * Low level system routines used by newlib for basic I/O and memory + * allocation. You can override most of these. + */ + +#include + +#include +#include + +/* If CONFIG_HEAP_START (or CONFIG_HEAP_END) isn't defined, then + * assume _lm_heap_start (resp. _lm_heap_end) is appropriately set by + * the linker */ +#ifndef CONFIG_HEAP_START +extern char _lm_heap_start; +#define CONFIG_HEAP_START ((caddr_t)&_lm_heap_start) +#endif +#ifndef CONFIG_HEAP_END +extern char _lm_heap_end; +#define CONFIG_HEAP_END ((caddr_t)&_lm_heap_end) +#endif + +/* + * _sbrk -- Increment the program break. + * + * Get incr bytes more RAM (for use by the heap). malloc() and + * friends call this function behind the scenes. + */ +caddr_t _sbrk(int incr) { + static caddr_t pbreak = NULL; /* current program break */ + caddr_t ret; + + if (pbreak == NULL) { + pbreak = CONFIG_HEAP_START; + } + + if ((CONFIG_HEAP_END - pbreak < incr) || + (pbreak - CONFIG_HEAP_START < -incr)) { + errno = ENOMEM; + return (caddr_t)-1; + } + + ret = pbreak; + pbreak += incr; + return ret; +} + +int _open(const char *path, int flags, ...) { + return 1; +} + +int _close(int fd) { + return 0; +} + +int _fstat(int fd, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int fd) { + return 1; +} + +int isatty(int fd) { + return 1; +} + +int _lseek(int fd, off_t pos, int whence) { + return -1; +} + +unsigned char getch(void) { + return 0; +} + + +int _read(int fd, char *buf, size_t cnt) { + *buf = getch(); + + return 1; +} + +void putch(unsigned char c) { +} + +void cgets(char *s, int bufsize) { + char *p; + int c; + int i; + + for (i = 0; i < bufsize; i++) { + *(s+i) = 0; + } +// memset(s, 0, bufsize); + + p = s; + + for (p = s; p < s + bufsize-1;) { + c = getch(); + switch (c) { + case '\r' : + case '\n' : + putch('\r'); + putch('\n'); + *p = '\n'; + return; + + case '\b' : + if (p > s) { + *p-- = 0; + putch('\b'); + putch(' '); + putch('\b'); + } + break; + + default : + putch(c); + *p++ = c; + break; + } + } + return; +} + +int _write(int fd, const char *buf, size_t cnt) { + int i; + + for (i = 0; i < cnt; i++) + putch(buf[i]); + + return cnt; +} + +/* Override fgets() in newlib with a version that does line editing */ +char *fgets(char *s, int bufsize, void *f) { + cgets(s, bufsize); + return s; +} -- cgit v1.2.3 From 9b97be19ee67206ed22d89a4d32d5701e2005b32 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 05:52:51 -0400 Subject: wirish/syscalls.c: Weaken I/O related function defs. For overriding. Signed-off-by: Marti Bolivar --- wirish/syscalls.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/wirish/syscalls.c b/wirish/syscalls.c index d365e15..4c5ce8a 100644 --- a/wirish/syscalls.c +++ b/wirish/syscalls.c @@ -74,46 +74,46 @@ caddr_t _sbrk(int incr) { return ret; } -int _open(const char *path, int flags, ...) { +__weak int _open(const char *path, int flags, ...) { return 1; } -int _close(int fd) { +__weak int _close(int fd) { return 0; } -int _fstat(int fd, struct stat *st) { +__weak int _fstat(int fd, struct stat *st) { st->st_mode = S_IFCHR; return 0; } -int _isatty(int fd) { +__weak int _isatty(int fd) { return 1; } -int isatty(int fd) { +__weak int isatty(int fd) { return 1; } -int _lseek(int fd, off_t pos, int whence) { +__weak int _lseek(int fd, off_t pos, int whence) { return -1; } -unsigned char getch(void) { +__weak unsigned char getch(void) { return 0; } -int _read(int fd, char *buf, size_t cnt) { +__weak int _read(int fd, char *buf, size_t cnt) { *buf = getch(); return 1; } -void putch(unsigned char c) { +__weak void putch(unsigned char c) { } -void cgets(char *s, int bufsize) { +__weak void cgets(char *s, int bufsize) { char *p; int c; int i; @@ -153,7 +153,7 @@ void cgets(char *s, int bufsize) { return; } -int _write(int fd, const char *buf, size_t cnt) { +__weak int _write(int fd, const char *buf, size_t cnt) { int i; for (i = 0; i < cnt; i++) @@ -163,7 +163,7 @@ int _write(int fd, const char *buf, size_t cnt) { } /* Override fgets() in newlib with a version that does line editing */ -char *fgets(char *s, int bufsize, void *f) { +__weak char *fgets(char *s, int bufsize, void *f) { cgets(s, bufsize); return s; } -- cgit v1.2.3 From 2c66df2876479bc2f2a1b4b4b787957ec4973657 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 19:14:08 -0400 Subject: wirish/syscalls.c: Assert LeafLabs copyright. _sbrk() is new in 2011, and there've been changes in 2012. Signed-off-by: Marti Bolivar --- wirish/syscalls.c | 1 + 1 file changed, 1 insertion(+) diff --git a/wirish/syscalls.c b/wirish/syscalls.c index 4c5ce8a..1e62d51 100644 --- a/wirish/syscalls.c +++ b/wirish/syscalls.c @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2011, 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation -- cgit v1.2.3 From a52fe9205cbb8f8a2e458e300c2048d889b26b54 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 21:41:50 -0400 Subject: Bring back . Add a spi_private.h with a SPI_DEV(), for convenience. Use it in the F1 and F2 implementations. We could probably unify these with an STM32_HAVE_SPI(n) macro, but we'll leave that for the future. Most everything from F1 is portable; F2 has some additional bit definitions and a spi_get_af() routine, but that's about it. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/spi.h | 2 +- libmaple/rules.mk | 2 +- libmaple/spi_private.h | 37 +++++++++++++++ libmaple/stm32f1/include/series/spi.h | 3 -- libmaple/stm32f1/spi.c | 25 ++-------- libmaple/stm32f2/include/series/spi.h | 88 +++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + libmaple/stm32f2/spi.c | 88 +++++++++++++++++++++++++++++++++++ 8 files changed, 221 insertions(+), 25 deletions(-) create mode 100644 libmaple/spi_private.h create mode 100644 libmaple/stm32f2/include/series/spi.h create mode 100644 libmaple/stm32f2/spi.c diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h index 90e2036..45dc5a2 100644 --- a/libmaple/include/libmaple/spi.h +++ b/libmaple/include/libmaple/spi.h @@ -307,7 +307,7 @@ uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len); * @brief Call a function on each SPI port * @param fn Function to call. */ -void spi_foreach(void (*fn)(spi_dev*)); +extern void spi_foreach(void (*fn)(spi_dev*)); void spi_peripheral_enable(spi_dev *dev); void spi_peripheral_disable(spi_dev *dev); diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 649e4c8..be93d2e 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -21,7 +21,7 @@ cSRCS_$(d) += iwdg.c cSRCS_$(d) += nvic.c cSRCS_$(d) += pwr.c cSRCS_$(d) += rcc.c -# cSRCS_$(d) += spi.c +cSRCS_$(d) += spi.c cSRCS_$(d) += systick.c cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c diff --git a/libmaple/spi_private.h b/libmaple/spi_private.h new file mode 100644 index 0000000..f0e0bd1 --- /dev/null +++ b/libmaple/spi_private.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#ifndef _LIBMAPLE_SPI_PRIVATE_H_ +#define _LIBMAPLE_SPI_PRIVATE_H_ + +#define SPI_DEV(num) \ + { \ + .regs = SPI##num##_BASE, \ + .clk_id = RCC_SPI##num, \ + .irq_num = NVIC_SPI##num, \ + } + +#endif diff --git a/libmaple/stm32f1/include/series/spi.h b/libmaple/stm32f1/include/series/spi.h index 8cc4c4d..d288a0c 100644 --- a/libmaple/stm32f1/include/series/spi.h +++ b/libmaple/stm32f1/include/series/spi.h @@ -46,11 +46,8 @@ extern "C" { struct spi_reg_map; -/** SPI1 register map base pointer */ #define SPI1_BASE ((struct spi_reg_map*)0x40013000) -/** SPI2 register map base pointer */ #define SPI2_BASE ((struct spi_reg_map*)0x40003800) -/** SPI3 register map base pointer */ #define SPI3_BASE ((struct spi_reg_map*)0x40003C00) /* diff --git a/libmaple/stm32f1/spi.c b/libmaple/stm32f1/spi.c index 72f2ef4..1c78cc3 100644 --- a/libmaple/stm32f1/spi.c +++ b/libmaple/stm32f1/spi.c @@ -33,35 +33,20 @@ #include #include +#include "spi_private.h" /* * Devices */ -static spi_dev spi1 = { - .regs = SPI1_BASE, - .clk_id = RCC_SPI1, - .irq_num = NVIC_SPI1, -}; -static spi_dev spi2 = { - .regs = SPI2_BASE, - .clk_id = RCC_SPI2, - .irq_num = NVIC_SPI2, -}; -#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -static spi_dev spi3 = { - .regs = SPI3_BASE, - .clk_id = RCC_SPI3, - .irq_num = NVIC_SPI3, -}; -#endif +static spi_dev spi1 = SPI_DEV(1); +static spi_dev spi2 = SPI_DEV(2); -/** SPI device 1 */ spi_dev *SPI1 = &spi1; -/** SPI device 2 */ spi_dev *SPI2 = &spi2; + #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -/** SPI device 3 */ +static spi_dev spi3 = SPI_DEV(3); spi_dev *SPI3 = &spi3; #endif diff --git a/libmaple/stm32f2/include/series/spi.h b/libmaple/stm32f2/include/series/spi.h new file mode 100644 index 0000000..7b9f94a --- /dev/null +++ b/libmaple/stm32f2/include/series/spi.h @@ -0,0 +1,88 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/include/series/spi.h + * @author Marti Bolivar + * @brief STM32F2 SPI/I2S series header. + */ + +#ifndef _LIBMAPLE_STM32F2_SPI_H_ +#define _LIBMAPLE_STM32F2_SPI_H_ + +#include /* for gpio_af */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Register map base pointers + */ + +struct spi_reg_map; + +#define SPI1_BASE ((struct spi_reg_map*)0x40013000) +#define SPI2_BASE ((struct spi_reg_map*)0x40003800) +#define SPI3_BASE ((struct spi_reg_map*)0x40003C00) + +/* + * Register bit definitions + */ + +/* Control register 2 */ + +#define SPI_CR2_FRF_BIT 4 + +#define SPI_CR2_FRF (1U << SPI_CR2_FRF_BIT) + +/* Status register */ + +#define SPI_SR_TIFRFE_BIT 8 + +#define SPI_SR_TIFRFE (1U << SPI_SR_TIFRFE_BIT) + +/* + * Device pointers + */ + +struct spi_dev; + +extern struct spi_dev *SPI1; +extern struct spi_dev *SPI2; +extern struct spi_dev *SPI3; + +/* + * Routines + */ + +gpio_af spi_get_af(struct spi_dev *dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index fd6b933..759f905 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -16,6 +16,7 @@ cSRCS_$(d) += exti.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c cSRCS_$(d) += rcc.c +cSRCS_$(d) += spi.c cSRCS_$(d) += syscfg.c cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c diff --git a/libmaple/stm32f2/spi.c b/libmaple/stm32f2/spi.c new file mode 100644 index 0000000..cfd9995 --- /dev/null +++ b/libmaple/stm32f2/spi.c @@ -0,0 +1,88 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/spi.c + * @author Marti Bolivar + * @brief STM32F2 SPI/I2S. + */ + +#include +#include "spi_private.h" + +/* + * Devices + */ + +static spi_dev spi1 = SPI_DEV(1); +static spi_dev spi2 = SPI_DEV(2); +static spi_dev spi3 = SPI_DEV(3); + +spi_dev *SPI1 = &spi1; +spi_dev *SPI2 = &spi2; +spi_dev *SPI3 = &spi3; + +/* + * Routines + */ + +void spi_config_gpios(spi_dev *dev, + uint8 as_master, + gpio_dev *nss_dev, + uint8 nss_bit, + gpio_dev *comm_dev, + uint8 sck_bit, + uint8 miso_bit, + uint8 mosi_bit) { + gpio_af dev_af = spi_get_af(dev); + gpio_set_mode(nss_dev, nss_bit, GPIO_MODE_AF); + gpio_set_mode(comm_dev, sck_bit, GPIO_MODE_AF); + gpio_set_mode(comm_dev, miso_bit, GPIO_MODE_AF); + gpio_set_mode(comm_dev, mosi_bit, GPIO_MODE_AF); + gpio_set_af(nss_dev, nss_bit, dev_af); + gpio_set_af(comm_dev, sck_bit, dev_af); + gpio_set_af(comm_dev, miso_bit, dev_af); + gpio_set_af(comm_dev, mosi_bit, dev_af); +} + +void spi_foreach(void (*fn)(spi_dev*)) { + fn(SPI1); + fn(SPI2); + fn(SPI3); +} + +gpio_af spi_get_af(spi_dev *dev) { + switch (dev->clk_id) { + case RCC_SPI1: /* Fall through */ + case RCC_SPI2: + return GPIO_AF_SPI_1_2; + case RCC_SPI3: + return GPIO_AF_SPI3; + default: + ASSERT(0); /* Can't happen */ + return (gpio_af)-1; + } +} -- cgit v1.2.3 From cb1facd43e34920adadf5829751d779f92cf7681 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 21:47:46 -0400 Subject: enum spi_mode: Add more descriptive enumerators, documentation. Instead of requiring everyone to figure it out for themselves, add enumerators specifying the idle logic level and what clock edge triggers data capture. Yes, it's easy enough to figure it out. It's also convenient to have these. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/spi.h | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/libmaple/include/libmaple/spi.h b/libmaple/include/libmaple/spi.h index 45dc5a2..fab643f 100644 --- a/libmaple/include/libmaple/spi.h +++ b/libmaple/include/libmaple/spi.h @@ -236,19 +236,24 @@ extern void spi_config_gpios(spi_dev *dev, /** * @brief SPI mode configuration. * - * Determines a combination of clock polarity (CPOL), which determines - * idle state of the clock line, and clock phase (CPHA), which - * determines which clock edge triggers data capture. + * A SPI mode determines a combination of the idle state of the clock + * line (the clock polarity, or "CPOL"), and which clock edge triggers + * data capture (the clock phase, or "CPHA"). */ typedef enum spi_mode { - SPI_MODE_0, /**< Clock line idles low (0), data capture on first - clock transition. */ - SPI_MODE_1, /**< Clock line idles low (0), data capture on second - clock transition */ - SPI_MODE_2, /**< Clock line idles high (1), data capture on first - clock transition. */ - SPI_MODE_3, /**< Clock line idles high (1), data capture on - second clock transition. */ + /** Clock idles low, data captured on rising edge (first transition) */ + SPI_MODE_LOW_RISING = 0, + /** Clock idles low, data captured on falling edge (second transition) */ + SPI_MODE_LOW_FALLING = 1, + /** Clock idles high, data captured on falling edge (first transition) */ + SPI_MODE_HIGH_FALLING = 2, + /** Clock idles high, data captured on rising edge (second transition) */ + SPI_MODE_HIGH_RISING = 3, + + SPI_MODE_0 = SPI_MODE_LOW_RISING, /**< Same as SPI_MODE_LOW_RISING */ + SPI_MODE_1 = SPI_MODE_LOW_FALLING, /**< Same as SPI_MODE_LOW_FALLING */ + SPI_MODE_2 = SPI_MODE_HIGH_FALLING, /**< Same as SPI_MODE_HIGH_FALLING */ + SPI_MODE_3 = SPI_MODE_HIGH_RISING, /**< Same as SPI_MODE_HIGH_RISING */ } spi_mode; /** -- cgit v1.2.3 From fd8456c37c7db78e93913d9f12c9b1407d3e4680 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 8 Jun 2012 18:21:02 -0400 Subject: maple: board.h: More comments, remove SYSTICK_RELOAD_VAL. We derive SYSTICK_RELOAD_VAL from CYCLES_PER_MICROSECOND now, so let's hide it for expert use. Signed-off-by: Marti Bolivar --- wirish/boards/maple/include/board/board.h | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/wirish/boards/maple/include/board/board.h b/wirish/boards/maple/include/board/board.h index 9319989..72a4282 100644 --- a/wirish/boards/maple/include/board/board.h +++ b/wirish/boards/maple/include/board/board.h @@ -33,16 +33,19 @@ #ifndef _BOARD_MAPLE_H_ #define _BOARD_MAPLE_H_ +/* 72 MHz -> 72 cycles per microsecond. */ #define CYCLES_PER_MICROSECOND 72 -#define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */ +/* Pin number for the built-in button. */ #define BOARD_BUTTON_PIN 38 + +/* Pin number for the built-in LED. */ #define BOARD_LED_PIN 13 /* Number of USARTs/UARTs whose pins are broken out to headers. */ #define BOARD_NR_USARTS 3 -/* Default USART pin numbers (not considering AFIO remap) */ +/* USART pin numbers. */ #define BOARD_USART1_TX_PIN 7 #define BOARD_USART1_RX_PIN 8 #define BOARD_USART2_TX_PIN 1 @@ -50,10 +53,10 @@ #define BOARD_USART3_TX_PIN 29 #define BOARD_USART3_RX_PIN 30 -/* Number of SPI ports */ +/* Number of SPI ports broken out to headers. */ #define BOARD_NR_SPI 2 -/* Default SPI pin numbers (not considering AFIO remap) */ +/* SPI pin numbers. */ #define BOARD_SPI1_NSS_PIN 10 #define BOARD_SPI1_MOSI_PIN 11 #define BOARD_SPI1_MISO_PIN 12 @@ -64,20 +67,22 @@ #define BOARD_SPI2_SCK_PIN 32 /* Total number of GPIO pins that are broken out to headers and - * intended for general use. */ + * intended for use. This includes pins like the LED, button, and + * debug port (JTAG/SWD) pins. */ #define BOARD_NR_GPIO_PINS 44 -/* Number of pins capable of PWM output */ +/* Number of pins capable of PWM output. */ #define BOARD_NR_PWM_PINS 15 -/* Number of pins capable of ADC conversion */ +/* Number of pins capable of ADC conversion. */ #define BOARD_NR_ADC_PINS 15 /* Number of pins already connected to external hardware. For Maple, - * these are just BOARD_LED_PIN and BOARD_BUTTON_PIN. */ + * these are just BOARD_LED_PIN, BOARD_BUTTON_PIN, and the debug port + * pins (see below). */ #define BOARD_NR_USED_PINS 7 -/* Debug port pins */ +/* Debug port pins. */ #define BOARD_JTMS_SWDIO_PIN 39 #define BOARD_JTCK_SWCLK_PIN 40 #define BOARD_JTDI_PIN 41 -- cgit v1.2.3 From 3193ae1326c738b54067674a6073287f90ecaa85 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 8 Jun 2012 18:34:33 -0400 Subject: Bring back . Signed-off-by: Marti Bolivar --- wirish/include/wirish/wirish.h | 2 +- wirish/include/wirish/wirish_debug.h | 8 ++--- wirish/rules.mk | 1 + wirish/stm32f1/wirish_debug.cpp | 41 ++++++++++++++++++++++++ wirish/stm32f2/wirish_debug.cpp | 60 ++++++++++++++++++++++++++++++++++++ 5 files changed, 105 insertions(+), 7 deletions(-) create mode 100644 wirish/stm32f1/wirish_debug.cpp create mode 100644 wirish/stm32f2/wirish_debug.cpp diff --git a/wirish/include/wirish/wirish.h b/wirish/include/wirish/wirish.h index 6810e4f..360b502 100644 --- a/wirish/include/wirish/wirish.h +++ b/wirish/include/wirish/wirish.h @@ -39,7 +39,7 @@ #include #include #include -/* FIXME put this back when you can #include */ +#include #include #include /* FIXME put this back when you can #include */ diff --git a/wirish/include/wirish/wirish_debug.h b/wirish/include/wirish/wirish_debug.h index cb1be3d..4edfd27 100644 --- a/wirish/include/wirish/wirish_debug.h +++ b/wirish/include/wirish/wirish_debug.h @@ -42,9 +42,7 @@ * * @see enableDebugPorts() */ -static inline void disableDebugPorts(void) { - afio_cfg_debug_ports(AFIO_DEBUG_NONE); -} +void disableDebugPorts(void); /** * @brief Enable the JTAG and Serial Wire (SW) debug ports. @@ -54,8 +52,6 @@ static inline void disableDebugPorts(void) { * * @see disableDebugPorts() */ -static inline void enableDebugPorts(void) { - afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ); -} +void enableDebugPorts(void); #endif diff --git a/wirish/rules.mk b/wirish/rules.mk index acf4c46..5138c82 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -38,6 +38,7 @@ cppSRCS_$(d) += wirish_shift.cpp cppSRCS_$(d) += wirish_time.cpp cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp +cppSRCS_$(d) += $(MCU_SERIES)/wirish_debug.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp # TODO: revise these appropriately for F2 and put them back in: # HardwareSPI.cpp diff --git a/wirish/stm32f1/wirish_debug.cpp b/wirish/stm32f1/wirish_debug.cpp new file mode 100644 index 0000000..28de96d --- /dev/null +++ b/wirish/stm32f1/wirish_debug.cpp @@ -0,0 +1,41 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2011, 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/stm32f1/wirish_debug.cpp + * @brief High level debug port configuration + */ + +#include +#include + +void disableDebugPorts(void) { + afio_cfg_debug_ports(AFIO_DEBUG_NONE); +} + +void enableDebugPorts(void) { + afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ); +} diff --git a/wirish/stm32f2/wirish_debug.cpp b/wirish/stm32f2/wirish_debug.cpp new file mode 100644 index 0000000..af6c78b --- /dev/null +++ b/wirish/stm32f2/wirish_debug.cpp @@ -0,0 +1,60 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file wirish/stm32f2/wirish_debug.cpp + * @brief High level debug port configuration + */ + +#include +#include + +// TODO is it worth optimizing these into raw MODER and AFR[LH] writes? + +void disableDebugPorts(void) { + // PA13-PA15 and PB3-PB4 are in system alternate function mode on + // reset, to support JTAG. Just put them in input mode to release + // them. + gpio_set_mode(GPIOA, 13, GPIO_MODE_INPUT); + gpio_set_mode(GPIOA, 14, GPIO_MODE_INPUT); + gpio_set_mode(GPIOA, 15, GPIO_MODE_INPUT); + gpio_set_mode(GPIOB, 3, GPIO_MODE_INPUT); + gpio_set_mode(GPIOB, 4, GPIO_MODE_INPUT); +} + +void enableDebugPorts(void) { + // Put PA13-PA15 and PB3-PB4 back in system AF mode. + gpio_set_mode(GPIOA, 13, GPIO_MODE_AF); + gpio_set_mode(GPIOA, 14, GPIO_MODE_AF); + gpio_set_mode(GPIOA, 15, GPIO_MODE_AF); + gpio_set_mode(GPIOB, 3, GPIO_MODE_AF); + gpio_set_mode(GPIOB, 4, GPIO_MODE_AF); + gpio_set_af(GPIOA, 13, GPIO_AF_SYS); + gpio_set_af(GPIOA, 14, GPIO_AF_SYS); + gpio_set_af(GPIOA, 15, GPIO_AF_SYS); + gpio_set_af(GPIOB, 3, GPIO_AF_SYS); + gpio_set_af(GPIOB, 4, GPIO_AF_SYS); +} -- cgit v1.2.3 From 1d4c35901150ac7adab003a7fd4f432ec3250c91 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 8 Jun 2012 18:46:25 -0400 Subject: maple: board.cpp: More comments. Signed-off-by: Marti Bolivar --- wirish/boards/maple/board.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/wirish/boards/maple/board.cpp b/wirish/boards/maple/board.cpp index 42c847b..a585ea1 100644 --- a/wirish/boards/maple/board.cpp +++ b/wirish/boards/maple/board.cpp @@ -30,13 +30,13 @@ * @brief Maple board file. */ -#include +#include // For this board's header file -#include -#include -#include +#include // For stm32_pin_info and its contents + // (these go into PIN_MAP). -#include "boards_private.h" // for PMAP_ROW() +#include "boards_private.h" // For PMAP_ROW(), which makes + // PIN_MAP easier to read. // boardInit(): nothing special to do for Maple. // -- cgit v1.2.3 From ba1d9f5eb6539003515b958b4935a06868e27733 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 12 Jun 2012 16:01:12 -0400 Subject: Build libmaple/dma.c on STM32F1. F2 doesn't work yet. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libmaple/rules.mk b/libmaple/rules.mk index be93d2e..0c29ec7 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -13,7 +13,9 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c cSRCS_$(d) += dac.c -# cSRCS_$(d) += dma.c +ifeq ($(MCU_SERIES),stm32f1) # FIXME add F2 support +cSRCS_$(d) += dma.c +endif cSRCS_$(d) += exti.c cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c -- cgit v1.2.3 From 24c77dbcb09e20f9d4b0e4c7bfc7b8c27809f931 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 7 Jun 2012 22:47:49 -0400 Subject: Typo fix. Signed-off-by: Marti Bolivar --- wirish/stm32f2/boards_setup.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp index dd872d3..5764dd0 100644 --- a/wirish/stm32f2/boards_setup.cpp +++ b/wirish/stm32f2/boards_setup.cpp @@ -112,7 +112,7 @@ namespace wirish { // We need SYSCFG for external interrupts syscfg_init(); // Turn on the I/O compensation cell, since we drive the - // GPIOs quickly be default. + // GPIOs quickly by default. syscfg_enable_io_compensation(); } -- cgit v1.2.3 From b0b4b12bbe74d94137f871d8063bc55225fb2e85 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Mon, 11 Jun 2012 23:30:20 -0400 Subject: Add stm32_private.h. This will hold STM32-related things that I'm not sure are well-thought out enough to go into . Currently, it contains an accessor routine that tells you the purpose of the memory block containing an address. Signed-off-by: Marti Bolivar --- libmaple/stm32_private.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 libmaple/stm32_private.h diff --git a/libmaple/stm32_private.h b/libmaple/stm32_private.h new file mode 100644 index 0000000..427417a --- /dev/null +++ b/libmaple/stm32_private.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +#ifndef _LIBMAPLE_STM32_PRIVATE_H_ +#define _LIBMAPLE_STM32_PRIVATE_H_ + +typedef enum stm32_mem_block_purpose { + STM32_BLOCK_CODE, + STM32_BLOCK_SRAM, + STM32_BLOCK_PERIPH, + STM32_BLOCK_FSMC_1_2, + STM32_BLOCK_FSMC_3_4, + STM32_BLOCK_FSMC_REG, + STM32_BLOCK_UNUSED, + STM32_BLOCK_CORTEX_INTERNAL, +} stm32_mem_block_purpose; + +static inline stm32_mem_block_purpose stm32_block_purpose(void *addr) { + return (stm32_mem_block_purpose)((unsigned)addr >> 29); +} + +#endif -- cgit v1.2.3 From 0c9d46d11f77f4737a767b2f95a9b40725b2fd97 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 11:39:51 -0400 Subject: HardwareSerial: Add c_dev() accessor for instance's usart_dev*. This is analagous to std::string::c_str(). Signed-off-by: Marti Bolivar --- wirish/include/wirish/HardwareSerial.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/wirish/include/wirish/HardwareSerial.h b/wirish/include/wirish/HardwareSerial.h index 2b1e747..f25362b 100644 --- a/wirish/include/wirish/HardwareSerial.h +++ b/wirish/include/wirish/HardwareSerial.h @@ -70,6 +70,10 @@ public: /* Pin accessors */ int txPin(void) { return this->tx_pin; } int rxPin(void) { return this->rx_pin; } + + /* Escape hatch into libmaple */ + /* FIXME [0.0.13] documentation */ + struct usart_dev* c_dev(void) { return this->usart_device; } private: struct usart_dev *usart_device; uint8 tx_pin; -- cgit v1.2.3 From 457f448bf775202d18d3d52662401ca8237cf453 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 11:47:10 -0400 Subject: HardwareSPI: add a c_dev(). Signed-off-by: Marti Bolivar --- wirish/include/wirish/HardwareSPI.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/wirish/include/wirish/HardwareSPI.h b/wirish/include/wirish/HardwareSPI.h index 89cf166..a1a4a73 100644 --- a/wirish/include/wirish/HardwareSPI.h +++ b/wirish/include/wirish/HardwareSPI.h @@ -184,6 +184,14 @@ public: */ uint8 nssPin(void); + /* Escape hatch */ + + /** + * @brief Get a pointer to the underlying libmaple spi_dev for + * this HardwareSPI instance. + */ + spi_dev* c_dev(void) { return this->spi_d; } + /* -- The following methods are deprecated --------------------------- */ /** -- cgit v1.2.3 From 28180328ef57328a0352fb00e2fcd4253b3166a9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 11:53:36 -0400 Subject: HardwareTimer: add a c_dev(). Signed-off-by: Marti Bolivar --- wirish/include/wirish/HardwareTimer.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/wirish/include/wirish/HardwareTimer.h b/wirish/include/wirish/HardwareTimer.h index 4e140ca..22aa010 100644 --- a/wirish/include/wirish/HardwareTimer.h +++ b/wirish/include/wirish/HardwareTimer.h @@ -205,6 +205,14 @@ public: */ void refresh(void); + /* Escape hatch */ + + /** + * @brief Get a pointer to the underlying libmaple timer_dev for + * this HardwareTimer instance. + */ + timer_dev* c_dev(void) { return this->dev; } + /* -- The rest of this file is deprecated. --------------------------------- */ /** @brief Deprecated; use setMode(channel, mode) instead. */ -- cgit v1.2.3 From 3bbdc100fb7e84a51c63a6cbba7ad46a9a4ae197 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 11:57:16 -0400 Subject: examples/test-usart-dma.cpp: Cleanups and comments. Someone pointed to this example on the DMA page in the wiki, so it's probably worth making it more clear what's going on. Remove unused code, add comments, and move things around for better exposition. Signed-off-by: Marti Bolivar --- examples/test-usart-dma.cpp | 127 +++++++++++++++++++++++++++----------------- 1 file changed, 78 insertions(+), 49 deletions(-) diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index 10ebe8b..7dafc3a 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -12,9 +12,9 @@ * * This example isn't very robust; don't use it in production. In * particular, since the buffer keeps filling (DMA_CIRC_MODE is set), - * if you keep typing after filling the buffer, you'll overwrite - * earlier bytes; this may happen before those earlier bytes are done - * printing. + * if you keep sending characters after filling the buffer, you'll + * overwrite earlier bytes; this may happen before those earlier bytes + * are done printing. * * This code is released into the public domain. */ @@ -25,29 +25,65 @@ #include -#define BAUD 9600 +/* + * Configuration and state + */ +// USART and DMA configuration #define USART USART2 #define USART_HWSER Serial2 #define USART_DMA_DEV DMA1 #define USART_RX_DMA_CHANNEL DMA_CH6 -#define USART_TX BOARD_USART2_TX_PIN -#define USART_RX BOARD_USART2_RX_PIN - -#define BUF_SIZE 8 -uint8 rx_buf[BUF_SIZE]; +#define BAUD 9600 -dma_irq_cause irq_cause; +// This will store received USART characters. +#define BUF_SIZE 20 +char rx_buf[BUF_SIZE]; +// The interrupt handler, rx_dma_irq(), sets this to 1. volatile uint32 irq_fired = 0; +// Used to store the ISR bits inside rx_dma_irq(). This helps explain +// what's going on inside loop(); see comments below. +volatile uint32 isr = 0; + +/* + * Helper functions + */ + +// This is our DMA interrupt handler. +void rx_dma_irq(void) { + irq_fired = 1; + isr = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); +} + +// Configure the USART receiver for use with DMA: +// 1. Turn it on. +// 2. Set the "DMA request on RX" bit in USART_CR3 (USART_CR3_DMAR). +void init_usart(void) { + USART_HWSER.begin(BAUD); + USART->regs->CR3 = USART_CR3_DMAR; +} + +// Configure the DMA controller to serve DMA requests from the USART. +void init_dma_xfer(void) { + dma_init(USART_DMA_DEV); + dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL, + &USART->regs->DR, DMA_SIZE_8BITS, + rx_buf, DMA_SIZE_8BITS, + (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_TRNS_CMPLT)); + dma_set_num_transfers(USART_DMA_DEV, USART_RX_DMA_CHANNEL, + BUF_SIZE - 1); + dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_CHANNEL, rx_dma_irq); + dma_enable(USART_DMA_DEV, USART_RX_DMA_CHANNEL); +} -void init_usart(void); -void init_dma_xfer(void); -void rx_dma_irq(void); +/* + * setup() and loop() + */ void setup(void) { pinMode(BOARD_LED_PIN, OUTPUT); - + rx_buf[BUF_SIZE - 1] = '\0'; // null-terminate rx_buf so we can print it init_dma_xfer(); init_usart(); } @@ -56,56 +92,49 @@ void loop(void) { toggleLED(); delay(100); - dma_channel_reg_map *ch_regs = dma_channel_regs(USART_DMA_DEV, - USART_RX_DMA_CHANNEL); + // See if the interrupt handler got called since the last time we + // checked. if (irq_fired) { USART_HWSER.println("** IRQ **"); + // Notice how the ISR bits show transfer complete _and_ + // half-complete here, but the ISR bits we print next will be + // zero. That's because the variable "isr" gets set _inside_ + // rx_dma_irq(). After it exits, libmaple cleans up by + // clearing the ISR bits. (If it didn't, and we forgot to, the + // interrupt would repeatedly fire forever.) + USART_HWSER.print("ISR bits: 0x"); + USART_HWSER.println(isr, HEX); irq_fired = 0; } + + // Print the ISR (interrupt status register) bits. + // + // Notice that the "transfer half-complete" ISR flag gets set when + // we reach the rx_buf half-way point. This is true even though we + // don't tell the DMA controller to interrupt us on a + // half-complete transfer. That is, the ISR bits get set at the + // right times no matter what; we just don't get interrupted + // unless we asked. (If an error or other problem occurs, the + // relevant ISR bits will get set in the same way). USART_HWSER.print("["); USART_HWSER.print(millis()); USART_HWSER.print("]\tISR bits: 0x"); uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); USART_HWSER.print(isr_bits, HEX); - USART_HWSER.print("\tCCR: 0x"); - USART_HWSER.print(ch_regs->CCR, HEX); - USART_HWSER.print("\tCNDTR: 0x"); - USART_HWSER.print(ch_regs->CNDTR, HEX); - USART_HWSER.print("\tBuffer contents: "); - for (int i = 0; i < BUF_SIZE; i++) { - USART_HWSER.print('\''); - USART_HWSER.print(rx_buf[i]); - USART_HWSER.print('\''); - if (i < BUF_SIZE - 1) USART_HWSER.print(", "); - } - USART_HWSER.println(); + + // Print the contents of rx_buf. If you keep typing after it fills + // up, the new characters will overwrite the old ones, thanks to + // DMA_CIRC_MODE. + USART_HWSER.print("\tCharacter buffer contents: '"); + USART_HWSER.print(rx_buf); + USART_HWSER.println("'"); if (isr_bits == 0x7) { USART_HWSER.println("** Clearing ISR bits."); dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); } } -/* Configure USART receiver for use with DMA */ -void init_usart(void) { - USART_HWSER.begin(BAUD); - USART->regs->CR3 = USART_CR3_DMAR; -} - -/* Configure DMA transmission */ -void init_dma_xfer(void) { - dma_init(USART_DMA_DEV); - dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL, - &USART->regs->DR, DMA_SIZE_8BITS, - rx_buf, DMA_SIZE_8BITS, - (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_TRNS_CMPLT)); - dma_set_num_transfers(USART_DMA_DEV, USART_RX_DMA_CHANNEL, BUF_SIZE); - dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_CHANNEL, rx_dma_irq); - dma_enable(USART_DMA_DEV, USART_RX_DMA_CHANNEL); -} - -void rx_dma_irq(void) { - irq_fired = true; -} +// ------- init() and main() -------------------------------------------------- // Force init to be called *first*, i.e. before static object allocation. // Otherwise, statically allocated objects that need libmaple may fail. -- cgit v1.2.3 From c000038c8b16a9be40ac95231c309aad05a57158 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 11:57:56 -0400 Subject: examples/test-usart-dma.cpp: Use HardwareSerial::c_dev(). Signed-off-by: Marti Bolivar --- examples/test-usart-dma.cpp | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index 7dafc3a..b3c766e 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -29,9 +29,9 @@ * Configuration and state */ -// USART and DMA configuration -#define USART USART2 -#define USART_HWSER Serial2 +// USART and DMA configuration. You can change these to suit your +// purposes. +HardwareSerial *serial = &Serial2; #define USART_DMA_DEV DMA1 #define USART_RX_DMA_CHANNEL DMA_CH6 #define BAUD 9600 @@ -60,16 +60,17 @@ void rx_dma_irq(void) { // 1. Turn it on. // 2. Set the "DMA request on RX" bit in USART_CR3 (USART_CR3_DMAR). void init_usart(void) { - USART_HWSER.begin(BAUD); - USART->regs->CR3 = USART_CR3_DMAR; + serial->begin(BAUD); + usart_dev *serial_dev = serial->c_dev(); + serial_dev->regs->CR3 = USART_CR3_DMAR; } // Configure the DMA controller to serve DMA requests from the USART. void init_dma_xfer(void) { dma_init(USART_DMA_DEV); dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL, - &USART->regs->DR, DMA_SIZE_8BITS, - rx_buf, DMA_SIZE_8BITS, + &serial->c_dev()->regs->DR, DMA_SIZE_8BITS, + rx_buf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_TRNS_CMPLT)); dma_set_num_transfers(USART_DMA_DEV, USART_RX_DMA_CHANNEL, BUF_SIZE - 1); @@ -95,15 +96,15 @@ void loop(void) { // See if the interrupt handler got called since the last time we // checked. if (irq_fired) { - USART_HWSER.println("** IRQ **"); + serial->println("** IRQ **"); // Notice how the ISR bits show transfer complete _and_ // half-complete here, but the ISR bits we print next will be // zero. That's because the variable "isr" gets set _inside_ // rx_dma_irq(). After it exits, libmaple cleans up by // clearing the ISR bits. (If it didn't, and we forgot to, the // interrupt would repeatedly fire forever.) - USART_HWSER.print("ISR bits: 0x"); - USART_HWSER.println(isr, HEX); + serial->print("ISR bits: 0x"); + serial->println(isr, HEX); irq_fired = 0; } @@ -116,20 +117,20 @@ void loop(void) { // right times no matter what; we just don't get interrupted // unless we asked. (If an error or other problem occurs, the // relevant ISR bits will get set in the same way). - USART_HWSER.print("["); - USART_HWSER.print(millis()); - USART_HWSER.print("]\tISR bits: 0x"); + serial->print("["); + serial->print(millis()); + serial->print("]\tISR bits: 0x"); uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); - USART_HWSER.print(isr_bits, HEX); + serial->print(isr_bits, HEX); // Print the contents of rx_buf. If you keep typing after it fills // up, the new characters will overwrite the old ones, thanks to // DMA_CIRC_MODE. - USART_HWSER.print("\tCharacter buffer contents: '"); - USART_HWSER.print(rx_buf); - USART_HWSER.println("'"); + serial->print("\tCharacter buffer contents: '"); + serial->print(rx_buf); + serial->println("'"); if (isr_bits == 0x7) { - USART_HWSER.println("** Clearing ISR bits."); + serial->println("** Clearing ISR bits."); dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); } } -- cgit v1.2.3 From e935e86a6f6a10fae3b646fc6aadfaf89bd76496 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 13:31:12 -0400 Subject: test-usart-dma.cpp: tweaks. Touch up comments, change some function names, and don't set something to zero which already is. Signed-off-by: Marti Bolivar --- examples/test-usart-dma.cpp | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index b3c766e..4a63044 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -29,8 +29,8 @@ * Configuration and state */ -// USART and DMA configuration. You can change these to suit your -// purposes. +// Serial port and DMA configuration. You can change these to suit +// your purposes. HardwareSerial *serial = &Serial2; #define USART_DMA_DEV DMA1 #define USART_RX_DMA_CHANNEL DMA_CH6 @@ -42,8 +42,9 @@ char rx_buf[BUF_SIZE]; // The interrupt handler, rx_dma_irq(), sets this to 1. volatile uint32 irq_fired = 0; -// Used to store the ISR bits inside rx_dma_irq(). This helps explain -// what's going on inside loop(); see comments below. +// Used to store DMA interrupt status register (ISR) bits inside +// rx_dma_irq(). This helps explain what's going on inside loop(); see +// comments below. volatile uint32 isr = 0; /* @@ -59,14 +60,14 @@ void rx_dma_irq(void) { // Configure the USART receiver for use with DMA: // 1. Turn it on. // 2. Set the "DMA request on RX" bit in USART_CR3 (USART_CR3_DMAR). -void init_usart(void) { +void setup_usart(void) { serial->begin(BAUD); usart_dev *serial_dev = serial->c_dev(); serial_dev->regs->CR3 = USART_CR3_DMAR; } // Configure the DMA controller to serve DMA requests from the USART. -void init_dma_xfer(void) { +void setup_dma_xfer(void) { dma_init(USART_DMA_DEV); dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL, &serial->c_dev()->regs->DR, DMA_SIZE_8BITS, @@ -84,9 +85,8 @@ void init_dma_xfer(void) { void setup(void) { pinMode(BOARD_LED_PIN, OUTPUT); - rx_buf[BUF_SIZE - 1] = '\0'; // null-terminate rx_buf so we can print it - init_dma_xfer(); - init_usart(); + setup_dma_xfer(); + setup_usart(); } void loop(void) { @@ -97,18 +97,19 @@ void loop(void) { // checked. if (irq_fired) { serial->println("** IRQ **"); - // Notice how the ISR bits show transfer complete _and_ - // half-complete here, but the ISR bits we print next will be - // zero. That's because the variable "isr" gets set _inside_ - // rx_dma_irq(). After it exits, libmaple cleans up by - // clearing the ISR bits. (If it didn't, and we forgot to, the - // interrupt would repeatedly fire forever.) + // Notice how the interrupt status register (ISR) bits show + // transfer complete _and_ half-complete here, but the ISR + // bits we print next will be zero. That's because the + // variable "isr" gets set _inside_ rx_dma_irq(). After it + // exits, libmaple cleans up by clearing the tube's ISR + // bits. (If it didn't, and we forgot to, the interrupt would + // repeatedly fire forever.) serial->print("ISR bits: 0x"); serial->println(isr, HEX); irq_fired = 0; } - // Print the ISR (interrupt status register) bits. + // Print the ISR bits. // // Notice that the "transfer half-complete" ISR flag gets set when // we reach the rx_buf half-way point. This is true even though we -- cgit v1.2.3 From e51c60e03661cc924420eba757e15044016b7c1f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 12 Jun 2012 17:01:12 -0400 Subject: DMA: prep for F2 with new "tube" API. To prepare for STM32F2/F4 DMA support, introduce a new libmaple DMA API, and move some code around to make priority level and interrupt handling more generic. The new API is based on a new set of types (dma_tube, struct dma_tube_reg_map, enum dma_request_src, enum dma_cfg_flags, and struct dma_tube_config). The central abstraction is the dma_tube type. STM32F2/F4 use DMA streams to control dataflow, and STM32F1 uses channels. dma_tube stands for whichever is appropriate for the current target. Dealing with tubes allows for configuring and using DMA with opaque tube values in the same source, instead of (as with ST's firmware) requiring two separate codebases. The new API is also more user-friendly, as it doesn't require knowing which DMA address registers to set and which configuration register flags go along with them. It now suffices to specify the source and destination for the DMA transfer, along with their sizes. This avoids confusion (e.g. for memory-to-memory transfers, data flows from the peripheral address register to the memory register, which might be surprising on F2, which has two memory address registers). The old API (based on enum dma_mode_flags and dma_setup_transfer()) is still available on F1, but deprecate it. Signed-off-by: Marti Bolivar --- libmaple/dma.c | 35 +++ libmaple/dma_private.h | 61 +++++ libmaple/include/libmaple/dma.h | 402 +++++++++++++++++++++++++++++--- libmaple/include/libmaple/dma_common.h | 114 +++++++++ libmaple/stm32f1/dma.c | 381 +++++++++++++++--------------- libmaple/stm32f1/include/series/dma.h | 411 +++++++++++++++++++++------------ 6 files changed, 1038 insertions(+), 366 deletions(-) create mode 100644 libmaple/dma_private.h create mode 100644 libmaple/include/libmaple/dma_common.h diff --git a/libmaple/dma.c b/libmaple/dma.c index 6442e4d..d13de10 100644 --- a/libmaple/dma.c +++ b/libmaple/dma.c @@ -33,6 +33,8 @@ */ #include +#include "dma_private.h" +#include "stm32_private.h" /* * Convenience routines @@ -45,3 +47,36 @@ void dma_init(dma_dev *dev) { rcc_clk_enable(dev->clk_id); } + +/* + * Private API + */ + +enum dma_atype _dma_addr_type(__io void *addr) { + switch (stm32_block_purpose((void*)addr)) { + /* Notice we're treating the code block as memory here. That's + * correct for addresses in Flash and in [0x0, 0x7FFFFFF] + * (provided that those addresses are aliased to Flash, SRAM, or + * FSMC, depending on BOOT[01] and possibly SYSCFG_MEMRMP). It's + * not correct for other addresses in the code block, but those + * will (hopefully) just fail-fast with transfer or bus errors. If + * lots of people get confused, it might be worth being more + * careful here. */ + case STM32_BLOCK_CODE: /* Fall through */ + case STM32_BLOCK_SRAM: /* ... */ + case STM32_BLOCK_FSMC_1_2: /* ... */ + case STM32_BLOCK_FSMC_3_4: + return DMA_ATYPE_MEM; + case STM32_BLOCK_PERIPH: + return DMA_ATYPE_PER; + case STM32_BLOCK_FSMC_REG: /* Fall through */ + /* Is this right? I can't think of a reason to DMA into or out + * of the FSMC registers. [mbolivar] */ + case STM32_BLOCK_UNUSED: /* ... */ + case STM32_BLOCK_CORTEX_INTERNAL: /* ... */ + return DMA_ATYPE_OTHER; + default: + ASSERT(0); /* Can't happen */ + return DMA_ATYPE_OTHER; + } +} diff --git a/libmaple/dma_private.h b/libmaple/dma_private.h new file mode 100644 index 0000000..b25ded2 --- /dev/null +++ b/libmaple/dma_private.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. +*****************************************************************************/ + +#ifndef _LIBMAPLE_DMA_PRIVATE_H_ +#define _LIBMAPLE_DMA_PRIVATE_H_ + +#include +#include + +/* + * IRQ handling + */ + +/* Wrap this in an ifdef to shut up GCC. (We provide DMA_GET_HANDLER + * in the series support files, which need dma_irq_handler().) */ +#ifdef DMA_GET_HANDLER +static __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) { + void (*handler)(void) = DMA_GET_HANDLER(dev, tube); + if (handler) { + handler(); + dma_clear_isr_bits(dev, tube); /* in case handler doesn't */ + } +} +#endif + +/* + * Conveniences for dealing with tube sources/destinations + */ + +enum dma_atype { + DMA_ATYPE_MEM, + DMA_ATYPE_PER, + DMA_ATYPE_OTHER, +}; + +enum dma_atype _dma_addr_type(__io void *addr); + +#endif diff --git a/libmaple/include/libmaple/dma.h b/libmaple/include/libmaple/dma.h index 0aed572..0ef495a 100644 --- a/libmaple/include/libmaple/dma.h +++ b/libmaple/include/libmaple/dma.h @@ -41,50 +41,400 @@ extern "C"{ #endif /* provides: + * + * - An opaque dma_tube type, and predefined rvalues for each tube + * supported by the series. + * + * A "DMA tube" is a series-specific (hopefully integer) datatype + * that abstracts the conduit through which DMA-ed data flow. + * + * Examples: On STM32F1, dma_tube is just an alias for dma_channel, + * and the tube values are just DMA_CH1 (=1), DMA_CH2 (=2), etc. + * + * Note that a dma_tube doesn't have to be an enum, and its values + * don't have to be integral. They _do_ need to be cheap to pass as + * arguments, though. + * + * - struct dma_tube_reg_map (and typedef to dma_tube_reg_map). DMA + * register maps tend to be split into global registers and per-tube + * registers. It's convenient to pass around pointers to a tube's + * registers, since that makes it possible to configure or otherwise + * mess with a tube without knowing which one you're dealing with. + * + * - Base pointers to the various dma_tube_reg_maps. + * + * Examples: On STM32F1, these are DMAxCHy_BASE. You can access + * registers like DMAxCHy_BASE->CPAR, etc. + * + * - enum dma_request_src (and typedef to dma_request_src). This + * specifies the peripheral DMA request sources (e.g. USART TX DMA + * requests, etc.). + * + * - enum dma_mode_flags (and typedef to dma_mode_flags). Used in + * dma_tube_config. If two series both support the same mode flags, + * they must use the same enumerator names for those flags (the + * values of those enumerators are of course allowed to differ). * * - Normal stuff: dma_reg_map and base pointers, register bit * definitions, dma_dev pointer declarations, and any other - * convenience functions useful for that series. - */ + * convenience functions useful for the series. */ #include - +/* buys us dma_dev and other necessities. */ +#include #include -#include -#include /* - * Devices + * Declarations/documentation for some of the series-provided types. + */ + +/** + * @brief (Series-dependent) DMA request sources. + * + * These specify the various pieces of peripheral functionality which + * may make DMA requests. Use them to set up a DMA transfer (see + * struct dma_tube_config, dma_tube_cfg()). */ +enum dma_request_src; -/* Encapsulates state related to user interrupt handlers. You - * shouldn't touch these directly; use dma_attach_interrupt() and - * dma_detach_interupt() instead. */ -typedef struct dma_handler_config { - void (*handler)(void); /* User handler */ - nvic_irq_num irq_line; /* IRQ line for interrupt */ -} dma_handler_config; +/** + * @brief (Series-dependent) DMA tube configuration flags. + * These specify miscellaneous bits of configuration for a DMA tube. + * @see struct dma_mode_config + */ +enum dma_cfg_flags; -/** DMA device type */ -typedef struct dma_dev { - dma_reg_map *regs; /**< Register map */ - rcc_clk_id clk_id; /**< Clock ID */ - struct dma_handler_config handlers[]; /**< For internal use */ -} dma_dev; +/** + * @brief (Series-dependent) DMA tube register map type. + * This allows you to access a tube's registers as a group. + * @see dma_tube_regs() + */ +struct dma_tube_reg_map; /* * Convenience functions */ +/* Initialization */ + void dma_init(dma_dev *dev); -/* - * Hack: This is here so the series header can declare it and access - * dma_dev->regs without knowing the structure of dma_dev. Don't use - * it outside of a series header. +/* dma_tube configuration + * + * Use these types and functions to set up DMA transfers, handle + * interrupts, etc. The main function of interest is dma_tube_cfg(), + * which the various series implement separately. */ + +/** + * @brief Specifies a DMA tube configuration. + * + * Use one of these to set up a DMA transfer by passing it to + * dma_tube_cfg(). + * + * @see dma_tube_cfg() + * @see dma_xfer_size + */ +typedef struct dma_tube_config { + /** Source of data */ + __io void *tube_src; + /** Source transfer size */ + dma_xfer_size tube_src_size; + + /** Destination of data */ + __io void *tube_dst; + /** Destination transfer size */ + dma_xfer_size tube_dst_size; + + /** + * Number of data to transfer (0 to 65,535). + * + * Note that this is NOT measured in bytes; it's measured in + * number of data, which occur in multiples of tube_src_size. For + * example, if tube_src_size is DMA_SIZE_32BITS and tube_nr_xfers + * is 2, then 8 total bytes will be transferred. + */ + unsigned tube_nr_xfers; + + /** + * Target-specific configuration flags. + * + * These are an OR of series-specific enum dma_mode_flags values. + * Consult the documentation for your target for what flags you + * can use here. + * + * Typical flag examples: DMA_CFG_SRC_INC, DMA_CFG_DST_INC, + * DMA_CFG_CIRC, DMA_CFG_CMPLT_IE, etc. + */ + unsigned tube_flags; + + /** + * Currently unused. You must set this to 0 or something valid for + * your target. */ + void *target_data; + + /** + * Hardware DMA request source. + * + * This is ignored for memory-to-memory transfers. + */ + enum dma_request_src tube_req_src; +} dma_tube_config; + +#define DMA_TUBE_CFG_SUCCESS 0 +#define DMA_TUBE_CFG_EREQ 1 +#define DMA_TUBE_CFG_ENDATA 2 +#define DMA_TUBE_CFG_EDEV 3 +#define DMA_TUBE_CFG_ESRC 4 +#define DMA_TUBE_CFG_EDST 5 +#define DMA_TUBE_CFG_EDIR 6 +#define DMA_TUBE_CFG_ESIZE 7 +#define DMA_TUBE_CFG_ECFG 0xFF +/** + * @brief Configure a DMA tube. + * + * Use this function to set up a DMA transfer. The tube will be + * disabled before being reconfigured. The transfer will have low + * priority by default. You can choose another priority before the + * transfer begins using dma_set_priority(). You can manage your + * interrupt handlers for the tube using dma_attach_interrupt() and + * dma_detach_interrupt(). + * + * After calling dma_tube_cfg() and performing any other desired + * configuration, start the transfer using dma_enable(). + * + * @param dev DMA device. + * @param tube DMA tube to configure. + * @param cfg Configuration to apply to tube. + * + * @return DMA_TUBE_CFG_SUCCESS (0) on success, <0 on failure. On + * failure, returned value will be the opposite (-) of one of: + * + * - DMA_TUBE_CFG_EREQ: tube doesn't work with cfg->tube_req_src + * - DMA_TUBE_CFG_ENDATA: cfg->tube_[src,dst]_size are + * incompatible with cfg->tube_nr_xfers, or cfg->tube_nr_xfers + * is out of bounds. + * - DMA_TUBE_CFG_EDEV: dev does not support cfg + * - DMA_TUBE_CFG_ESRC: bad cfg->tube_src + * - DMA_TUBE_CFG_EDST: bad cfg->tube_dst + * - DMA_TUBE_CFG_EDIR: dev can't transfer from cfg->tube_src to + * cfg->tube_dst + * - DMA_TUBE_CFG_ESIZE: something ended up wrong due to MSIZE/PSIZE + * - DMA_TUBE_CFG_ECFG: generic "something's wrong" + * + * @sideeffect Disables tube. May alter tube's registers even when an + * error occurs. + * @see struct dma_tube_config + * @see dma_attach_interrupt() + * @see dma_detach_interrupt() + * @see dma_enable() + */ +extern int dma_tube_cfg(dma_dev *dev, dma_tube tube, dma_tube_config *cfg); + +/* Other tube configuration functions. You can use these if + * dma_tube_cfg() isn't enough, or to adjust parts of an existing tube + * configuration. */ + +/** DMA transfer priority. */ +typedef enum dma_priority { + DMA_PRIORITY_LOW = 0, /**< Low priority */ + DMA_PRIORITY_MEDIUM = 1, /**< Medium priority */ + DMA_PRIORITY_HIGH = 2, /**< High priority */ + DMA_PRIORITY_VERY_HIGH = 3, /**< Very high priority */ +} dma_priority; + +/** + * @brief Set the priority of a DMA transfer. + * + * You may not call this function while the tube is enabled. + * + * @param dev DMA device + * @param tube DMA tube + * @param priority priority to set. + */ +extern void dma_set_priority(dma_dev *dev, dma_tube tube, + dma_priority priority); + +/** + * @brief Set the number of data transfers on a DMA tube. + * + * You may not call this function while the tube is enabled. + * + * @param dev DMA device + * @param tube Tube through which the transfer will occur. + * @param num_transfers Number of DMA transactions to set. + */ +extern void dma_set_num_transfers(dma_dev *dev, dma_tube tube, + uint16 num_transfers); + +/** + * @brief Set the base memory address where data will be read from or + * written to. + * + * You must not call this function while the tube is enabled. + * + * If the DMA memory size is 16 bits, the address is automatically + * aligned to a half-word. If the DMA memory size is 32 bits, the + * address is aligned to a word. + * + * @param dev DMA Device + * @param tube Tube whose base memory address to set. + * @param address Memory base address to use. + */ +extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *address); + +/** + * @brief Set the base peripheral address where data will be read from + * or written to. + * + * You must not call this function while the channel is enabled. + * + * If the DMA peripheral size is 16 bits, the address is automatically + * aligned to a half-word. If the DMA peripheral size is 32 bits, the + * address is aligned to a word. + * + * @param dev DMA Device + * @param tube Tube whose peripheral data register base address to set. + * @param addr Peripheral memory base address to use. + */ +extern void dma_set_per_addr(dma_dev *dev, dma_tube tube, __io void *address); + +/* Interrupt handling */ + +/** + * @brief Attach an interrupt to a DMA transfer. + * + * Interrupts are enabled using series-specific mode flags in + * dma_tube_cfg(). + * + * @param dev DMA device + * @param tube Tube to attach handler to + * @param handler Interrupt handler to call when tube interrupt fires. + * @see dma_tube_cfg() + * @see dma_get_irq_cause() + * @see dma_detach_interrupt() + */ +extern void dma_attach_interrupt(dma_dev *dev, dma_tube tube, + void (*handler)(void)); + + +/** + * @brief Detach a DMA transfer interrupt handler. + * + * After calling this function, the given tube's interrupts will be + * disabled. + * + * @param dev DMA device + * @param tube Tube whose handler to detach + * @sideeffect Clears the tube's interrupt enable bits. + * @see dma_attach_interrupt() + */ +extern void dma_detach_interrupt(dma_dev *dev, dma_tube tube); + +/* Tube enable/disable */ + +/** + * @brief Enable a DMA tube. + * + * If the tube has been properly configured, calling this function + * allows it to start serving DMA requests. + * + * @param dev DMA device + * @param tube Tube to enable + * @see dma_tube_cfg() + */ +extern void dma_enable(dma_dev *dev, dma_tube tube); + +/** + * @brief Disable a DMA channel. + * + * Calling this function makes the tube stop serving DMA requests. + * + * @param dev DMA device + * @param tube Tube to disable + */ +extern void dma_disable(dma_dev *dev, dma_tube tube); + +/** + * @brief Check if a DMA tube is enabled. + * @param dev DMA device. + * @param tube Tube to check. + * @return 0 if the tube is disabled, >0 if it is enabled. + */ +static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube); + +/* Other conveniences */ + +/** + * @brief Obtain a pointer to an individual DMA tube's registers. + * + * Examples: + * + * - On STM32F1, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. + * + * @param dev DMA device. + * @param tube DMA tube whose register map to obtain. + * @return (Series-specific) tube register map. + */ +static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube); + +/** + * Encodes the reason why a DMA interrupt was called. + * @see dma_get_irq_cause() + */ +typedef enum dma_irq_cause { + DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ + DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ + DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ + DMA_TRANSFER_DME_ERROR, /**< + * @brief Direct mode error occurred during + * transfer. */ + DMA_TRANSFER_FIFO_ERROR, /**< FIFO error occurred during transfer. */ +} dma_irq_cause; + +/** + * @brief Discover the reason why a DMA interrupt was called. + * + * You may only call this function within an attached interrupt + * handler for the given channel. + * + * This function resets the internal DMA register state which encodes + * the cause of the interrupt; consequently, it can only be called + * once per interrupt handler invocation. + * + * @param dev DMA device + * @param tube Tube whose interrupt is being handled. + * @return Reason why the interrupt fired. + * @sideeffect Clears flags in dev's interrupt status registers. + * @see dma_attach_interrupt() + * @see dma_irq_cause + */ +extern dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_tube tube); + +/** + * @brief Get the ISR status bits for a DMA channel. + * + * The bits are returned right-aligned, in the order they appear in + * the corresponding ISR register. + * + * If you're trying to figure out why a DMA interrupt fired, you may + * find dma_get_irq_cause() more convenient. + * + * @param dev DMA device + * @param tube Tube whose ISR bits to return. + * @see dma_get_irq_cause(). + */ +static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube); + +/** + * @brief Clear the ISR status bits for a given DMA tube. + * + * If you're trying to clean up after yourself in a DMA interrupt, you + * may find dma_get_irq_cause() more convenient. + * + * @param dev DMA device + * @param tube Tube whose ISR bits to clear. + * @see dma_get_irq_cause() */ -static __always_inline dma_reg_map* _dma_dev_regs(dma_dev *dev) { - return dev->regs; -} +static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube); #ifdef __cplusplus } // extern "C" diff --git a/libmaple/include/libmaple/dma_common.h b/libmaple/include/libmaple/dma_common.h new file mode 100644 index 0000000..67475f7 --- /dev/null +++ b/libmaple/include/libmaple/dma_common.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/include/libmaple/dma_common.h + * @author Marti Bolivar + * @brief Common DMA sub-header for and . + * + * WARNING: CONTENTS UNSTABLE + * + * The existence of this file is an implementation detail. Its + * contents are not stable, so never include it directly. If you need + * something from here, #include instead. + */ + +/* + * There's a fair amount of common DMA functionality needed by each + * and . This header exists in order + * to provide it to both, avoiding some hacks and circular + * dependencies. + */ + +#ifndef _LIBMAPLE_DMA_COMMON_H_ +#define _LIBMAPLE_DMA_COMMON_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include + +/* + * Devices + */ + +struct dma_reg_map; + +/* Encapsulates state related to user interrupt handlers. You + * shouldn't touch these directly; use dma_attach_interrupt() and + * dma_detach_interupt() instead. */ +typedef struct dma_handler_config { + void (*handler)(void); /* User handler */ + nvic_irq_num irq_line; /* IRQ line for interrupt */ +} dma_handler_config; + +/** DMA device type */ +typedef struct dma_dev { + struct dma_reg_map *regs; /**< Register map */ + rcc_clk_id clk_id; /**< Clock ID */ + struct dma_handler_config handlers[]; /**< For internal use */ +} dma_dev; + +/** + * @brief DMA channels + * + * Notes: + * - This is also the dma_tube type for STM32F1. + * - Channel 0 is not available on all STM32 series. + * + * @see dma_tube + */ +typedef enum dma_channel { + DMA_CH0 = 0, /**< Channel 0 */ + DMA_CH1 = 1, /**< Channel 1 */ + DMA_CH2 = 2, /**< Channel 2 */ + DMA_CH3 = 3, /**< Channel 3 */ + DMA_CH4 = 4, /**< Channel 4 */ + DMA_CH5 = 5, /**< Channel 5 */ + DMA_CH6 = 6, /**< Channel 6 */ + DMA_CH7 = 7, /**< Channel 7 */ +} dma_channel; + +/** + * @brief Source and destination transfer sizes. + * Use these when initializing a struct dma_tube_config. + * @see struct dma_tube_config + * @see dma_tube_cfg + */ +typedef enum dma_xfer_size { + DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ + DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ + DMA_SIZE_32BITS = 2, /**< 32-bit transfers */ +} dma_xfer_size; + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/stm32f1/dma.c b/libmaple/stm32f1/dma.c index 14ac645..fc502a1 100644 --- a/libmaple/stm32f1/dma.c +++ b/libmaple/stm32f1/dma.c @@ -35,6 +35,10 @@ #include #include +/* Hack to ensure inlining in dma_irq_handler() */ +#define DMA_GET_HANDLER(dev, tube) (dev->handlers[tube - 1].handler) +#include "dma_private.h" + /* * Devices */ @@ -50,7 +54,7 @@ static dma_dev dma1 = { { .handler = NULL, .irq_line = NVIC_DMA_CH6 }, { .handler = NULL, .irq_line = NVIC_DMA_CH7 }}, }; -/** DMA1 device */ +/** STM32F1 DMA1 device */ dma_dev *DMA1 = &dma1; #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) @@ -63,83 +67,95 @@ static dma_dev dma2 = { { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }, { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }}, /* !@#$ */ }; -/** DMA2 device */ +/** STM32F1 DMA2 device */ dma_dev *DMA2 = &dma2; #endif /* - * Routines + * Auxiliary routines */ -/** - * @brief Set up a DMA transfer. - * - * The channel will be disabled before being reconfigured. The - * transfer will have low priority by default. You may choose another - * priority before the transfer begins using dma_set_priority(), as - * well as performing any other configuration you desire. When the - * channel is configured to your liking, enable it using dma_enable(). - * - * @param dev DMA device. - * @param channel DMA channel. - * @param peripheral_address Base address of peripheral data register - * involved in the transfer. - * @param peripheral_size Peripheral data transfer size. - * @param memory_address Base memory address involved in the transfer. - * @param memory_size Memory data transfer size. - * @param mode Logical OR of dma_mode_flags - * @sideeffect Disables the given DMA channel. - * @see dma_xfer_size - * @see dma_mode_flags - * @see dma_set_num_transfers() - * @see dma_set_priority() - * @see dma_attach_interrupt() - * @see dma_enable() - */ -void dma_setup_transfer(dma_dev *dev, - dma_channel channel, - __io void *peripheral_address, - dma_xfer_size peripheral_size, - __io void *memory_address, - dma_xfer_size memory_size, - uint32 mode) { - dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel); +/* Can channel serve cfg->tube_req_src? */ +static int cfg_req_ok(dma_channel channel, dma_tube_config *cfg) { + return (cfg->tube_req_src & 0x7) == channel; +} - dma_disable(dev, channel); /* can't write to CMAR/CPAR otherwise */ - channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode; - channel_regs->CMAR = (uint32)memory_address; - channel_regs->CPAR = (uint32)peripheral_address; +/* Can dev serve cfg->tube_req_src? */ +static int cfg_dev_ok(dma_dev *dev, dma_tube_config *cfg) { + return (rcc_clk_id)(cfg->tube_req_src >> 3) == dev->clk_id; } -/** - * @brief Set the number of data to be transferred on a DMA channel. - * - * You may not call this function while the channel is enabled. - * - * @param dev DMA device - * @param channel Channel through which the transfer occurs. - * @param num_transfers - */ -void dma_set_num_transfers(dma_dev *dev, - dma_channel channel, - uint16 num_transfers) { - dma_channel_reg_map *channel_regs; +/* Is addr acceptable for use as DMA src/dst? */ +static int cfg_mem_ok(__io void *addr) { + enum dma_atype atype = _dma_addr_type(addr); + return atype == DMA_ATYPE_MEM || atype == DMA_ATYPE_PER; +} - ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); +/* Is the direction implied by src->dst supported? */ +static int cfg_dir_ok(dma_tube_config *cfg) { + /* We can't do peripheral->peripheral transfers. */ + return ((_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM) || + (_dma_addr_type(cfg->tube_dst) == DMA_ATYPE_MEM)); +} - channel_regs = dma_channel_regs(dev, channel); - channel_regs->CNDTR = num_transfers; +static int preconfig_check(dma_dev *dev, dma_channel channel, + dma_tube_config *cfg) { + if (!cfg_req_ok(channel, cfg)) { + return -DMA_TUBE_CFG_EREQ; + } + if (cfg->tube_nr_xfers > 65535) { + return -DMA_TUBE_CFG_ENDATA; + } + if (!cfg_dev_ok(dev, cfg)) { + return -DMA_TUBE_CFG_EDEV; + } + if (!cfg_mem_ok(cfg->tube_src)) { + return -DMA_TUBE_CFG_ESRC; + } + if (!cfg_mem_ok(cfg->tube_dst)) { + return -DMA_TUBE_CFG_EDST; + } + if (!cfg_dir_ok(cfg)) { + return -DMA_TUBE_CFG_EDIR; + } + return DMA_TUBE_CFG_SUCCESS; } -/** - * @brief Set the priority of a DMA transfer. - * - * You may not call this function while the channel is enabled. - * - * @param dev DMA device - * @param channel DMA channel - * @param priority priority to set. +/* Configure chregs according to cfg, where cfg->tube_dst is peripheral. */ +static int config_to_per(dma_tube_reg_map *chregs, dma_tube_config *cfg) { + return -DMA_TUBE_CFG_ECFG; /* FIXME implement */ +} + +/* Configure chregs according to cfg, where cfg->tube_dst is memory. */ +static int config_to_mem(dma_tube_reg_map *chregs, dma_tube_config *cfg) { + return -DMA_TUBE_CFG_ECFG; /* FIXME implement */ +} + +/* + * Routines */ + +int dma_tube_cfg(dma_dev *dev, dma_channel channel, dma_tube_config *cfg) { + dma_tube_reg_map *chregs; + int ret = preconfig_check(dev, channel, cfg); + + if (ret < 0) { + return ret; + } + + chregs = dma_tube_regs(dev, channel); + switch (_dma_addr_type(cfg->tube_dst)) { + case DMA_ATYPE_PER: + return config_to_per(chregs, cfg); + case DMA_ATYPE_MEM: + return config_to_mem(chregs, cfg); + default: + /* Can't happen */ + ASSERT(0); + return -DMA_TUBE_CFG_ECFG; + } +} + void dma_set_priority(dma_dev *dev, dma_channel channel, dma_priority priority) { @@ -151,134 +167,77 @@ void dma_set_priority(dma_dev *dev, channel_regs = dma_channel_regs(dev, channel); ccr = channel_regs->CCR; ccr &= ~DMA_CCR_PL; - ccr |= priority; + ccr |= (priority << 12); channel_regs->CCR = ccr; } -/** - * @brief Attach an interrupt to a DMA transfer. - * - * Interrupts are enabled using appropriate mode flags in - * dma_setup_transfer(). - * - * @param dev DMA device - * @param channel Channel to attach handler to - * @param handler Interrupt handler to call when channel interrupt fires. - * @see dma_setup_transfer() - * @see dma_get_irq_cause() - * @see dma_detach_interrupt() - */ -void dma_attach_interrupt(dma_dev *dev, - dma_channel channel, +void dma_set_num_transfers(dma_dev *dev, + dma_channel channel, + uint16 num_transfers) { + dma_channel_reg_map *channel_regs; + + ASSERT_FAULT(!dma_is_channel_enabled(dev, channel)); + + channel_regs = dma_channel_regs(dev, channel); + channel_regs->CNDTR = num_transfers; +} + +void dma_attach_interrupt(dma_dev *dev, dma_channel channel, void (*handler)(void)) { - dev->handlers[channel - 1].handler = handler; + DMA_GET_HANDLER(dev, channel) = handler; nvic_irq_enable(dev->handlers[channel - 1].irq_line); } -/** - * @brief Detach a DMA transfer interrupt handler. - * - * After calling this function, the given channel's interrupts will be - * disabled. - * - * @param dev DMA device - * @param channel Channel whose handler to detach - * @sideeffect Clears interrupt enable bits in the channel's CCR register. - * @see dma_attach_interrupt() - */ void dma_detach_interrupt(dma_dev *dev, dma_channel channel) { /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */ dma_channel_regs(dev, channel)->CCR &= ~0xF; - dev->handlers[channel - 1].handler = NULL; + DMA_GET_HANDLER(dev, channel) = NULL; +} + +void dma_enable(dma_dev *dev, dma_channel channel) { + dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); + bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1); +} + +void dma_disable(dma_dev *dev, dma_channel channel) { + dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); + bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0); } -/** - * @brief Discover the reason why a DMA interrupt was called. - * - * You may only call this function within an attached interrupt - * handler for the given channel. - * - * This function resets the internal DMA register state which encodes - * the cause of the interrupt; consequently, it can only be called - * once per interrupt handler invocation. - * - * @param dev DMA device - * @param channel Channel whose interrupt is being handled. - * @return Reason why the interrupt fired. - * @sideeffect Clears channel status flags in dev->regs->ISR. - * @see dma_attach_interrupt() - * @see dma_irq_cause - */ dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) { + /* Grab and clear the ISR bits. */ uint8 status_bits = dma_get_isr_bits(dev, channel); + dma_clear_isr_bits(dev, channel); /* If the channel global interrupt flag is cleared, then * something's very wrong. */ - ASSERT(status_bits & BIT(0)); - - dma_clear_isr_bits(dev, channel); + ASSERT(status_bits & 0x1); + /* If GIF is set, then some other flag should be set, barring + * something unexpected (e.g. the user making an unforeseen IFCR + * write). */ + ASSERT(status_bits != 0x1); /* ISR flags get set even if the corresponding interrupt enable * bits in the channel's configuration register are cleared, so we * can't use a switch here. * * Don't change the order of these if statements. */ - if (status_bits & BIT(3)) { + if (status_bits & 0x8) { return DMA_TRANSFER_ERROR; - } else if (status_bits & BIT(1)) { + } else if (status_bits & 0x2) { return DMA_TRANSFER_COMPLETE; - } else if (status_bits & BIT(2)) { + } else if (status_bits & 0x4) { return DMA_TRANSFER_HALF_COMPLETE; - } else if (status_bits & BIT(0)) { - /* Shouldn't happen (unless someone messed up an IFCR write). */ - throb(); - } -#if DEBUG_LEVEL < DEBUG_ALL - else { - /* We shouldn't have been called, but the debug level is too - * low for the above ASSERT() to have had any effect. In - * order to fail fast, mimic the DMA controller's behavior - * when an error occurs. */ - dma_disable(dev, channel); } -#endif - return DMA_TRANSFER_ERROR; -} -/** - * @brief Enable a DMA channel. - * @param dev DMA device - * @param channel Channel to enable - */ -void dma_enable(dma_dev *dev, dma_channel channel) { - dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); - bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1); -} - -/** - * @brief Disable a DMA channel. - * @param dev DMA device - * @param channel Channel to disable - */ -void dma_disable(dma_dev *dev, dma_channel channel) { - dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel); - bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0); + /* If we get here, one of our assumptions has been violated, but + * the debug level is too low for the above ASSERTs() to have had + * any effect. In order to fail fast, mimic the DMA controller's + * behavior when an error occurs. */ + dma_disable(dev, channel); + return DMA_TRANSFER_ERROR; } -/** - * @brief Set the base memory address where data will be read from or - * written to. - * - * You must not call this function while the channel is enabled. - * - * If the DMA memory size is 16 bits, the address is automatically - * aligned to a half-word. If the DMA memory size is 32 bits, the - * address is aligned to a word. - * - * @param dev DMA Device - * @param channel Channel whose base memory address to set. - * @param addr Memory base address to use. - */ void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) { dma_channel_reg_map *chan_regs; @@ -288,20 +247,6 @@ void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) { chan_regs->CMAR = (uint32)addr; } -/** - * @brief Set the base peripheral address where data will be read from - * or written to. - * - * You must not call this function while the channel is enabled. - * - * If the DMA peripheral size is 16 bits, the address is automatically - * aligned to a half-word. If the DMA peripheral size is 32 bits, the - * address is aligned to a word. - * - * @param dev DMA Device - * @param channel Channel whose peripheral data register base address to set. - * @param addr Peripheral memory base address to use. - */ void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) { dma_channel_reg_map *chan_regs; @@ -311,61 +256,103 @@ void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) { chan_regs->CPAR = (uint32)addr; } -/* - * IRQ handlers +/** + * @brief Deprecated. Use dma_tube_cfg() instead. + * + * Set up a DMA transfer. + * + * The channel will be disabled before being reconfigured. The + * transfer will have low priority by default. You may choose another + * priority before the transfer begins using dma_set_priority(), as + * well as performing any other configuration you desire. When the + * channel is configured to your liking, enable it using dma_enable(). + * + * @param dev DMA device. + * @param channel DMA channel. + * @param peripheral_address Base address of peripheral data register + * involved in the transfer. + * @param peripheral_size Peripheral data transfer size. + * @param memory_address Base memory address involved in the transfer. + * @param memory_size Memory data transfer size. + * @param mode Logical OR of dma_mode_flags + * + * @see dma_tube_cfg() + * + * @sideeffect Disables the given DMA channel. + * @see dma_xfer_size + * @see dma_mode_flags + * @see dma_set_num_transfers() + * @see dma_set_priority() + * @see dma_attach_interrupt() + * @see dma_enable() */ +__deprecated +void dma_setup_transfer(dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode) { + dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel); -static __always_inline void dispatch_handler(dma_dev *dev, int channel) { - void (*handler)(void) = dev->handlers[channel - 1].handler; - if (handler) { - handler(); - dma_clear_isr_bits(dev, channel); /* in case handler doesn't */ - } + dma_disable(dev, channel); /* can't write to CMAR/CPAR otherwise */ + channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode; + channel_regs->CMAR = (uint32)memory_address; + channel_regs->CPAR = (uint32)peripheral_address; } +/* + * IRQ handlers + */ + void __irq_dma1_channel1(void) { - dispatch_handler(DMA1, DMA_CH1); + dma_irq_handler(DMA1, DMA_CH1); } void __irq_dma1_channel2(void) { - dispatch_handler(DMA1, DMA_CH2); + dma_irq_handler(DMA1, DMA_CH2); } void __irq_dma1_channel3(void) { - dispatch_handler(DMA1, DMA_CH3); + dma_irq_handler(DMA1, DMA_CH3); } void __irq_dma1_channel4(void) { - dispatch_handler(DMA1, DMA_CH4); + dma_irq_handler(DMA1, DMA_CH4); } void __irq_dma1_channel5(void) { - dispatch_handler(DMA1, DMA_CH5); + dma_irq_handler(DMA1, DMA_CH5); } void __irq_dma1_channel6(void) { - dispatch_handler(DMA1, DMA_CH6); + dma_irq_handler(DMA1, DMA_CH6); } void __irq_dma1_channel7(void) { - dispatch_handler(DMA1, DMA_CH7); + dma_irq_handler(DMA1, DMA_CH7); } -#ifdef STM32_HIGH_DENSITY +#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) void __irq_dma2_channel1(void) { - dispatch_handler(DMA2, DMA_CH1); + dma_irq_handler(DMA2, DMA_CH1); } void __irq_dma2_channel2(void) { - dispatch_handler(DMA2, DMA_CH2); + dma_irq_handler(DMA2, DMA_CH2); } void __irq_dma2_channel3(void) { - dispatch_handler(DMA2, DMA_CH3); + dma_irq_handler(DMA2, DMA_CH3); } void __irq_dma2_channel4_5(void) { - dispatch_handler(DMA2, DMA_CH4); - dispatch_handler(DMA2, DMA_CH5); + if ((DMA2_BASE->CCR4 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF4)) { + dma_irq_handler(DMA2, DMA_CH4); + } + if ((DMA2_BASE->CCR5 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF5)) { + dma_irq_handler(DMA2, DMA_CH5); + } } #endif diff --git a/libmaple/stm32f1/include/series/dma.h b/libmaple/stm32f1/include/series/dma.h index 60582ea..6da3246 100644 --- a/libmaple/stm32f1/include/series/dma.h +++ b/libmaple/stm32f1/include/series/dma.h @@ -29,7 +29,7 @@ * @file libmaple/stm32f1/include/series/dma.h * @author Marti Bolivar ; * Original implementation by Michael Hope - * @brief STM32F1 Direct Memory Access header + * @brief STM32F1 DMA series header. */ /* @@ -44,13 +44,14 @@ extern "C"{ #endif #include +#include /* - * Register map and base pointers + * Register maps and base pointers */ /** - * @brief DMA register map type. + * @brief STM32F1 DMA register map type. * * Note that DMA controller 2 (register map base pointer DMA2_BASE) * only supports channels 1--5. @@ -100,6 +101,44 @@ typedef struct dma_reg_map { /** DMA controller 2 register map base pointer */ #define DMA2_BASE ((struct dma_reg_map*)0x40020400) +/** + * @brief STM32F1 DMA channel (i.e. tube) register map type. + * Provides access to an individual channel's registers. + * @see dma_tube_regs() + */ +typedef struct dma_tube_reg_map { + __io uint32 CCR; /**< Channel configuration register */ + __io uint32 CNDTR; /**< Channel number of data register */ + __io uint32 CPAR; /**< Channel peripheral address register */ + __io uint32 CMAR; /**< Channel memory address register */ +} dma_tube_reg_map; + +/** DMA1 channel 1 register map base pointer */ +#define DMA1CH1_BASE ((struct dma_tube_reg_map*)0x40020008) +/** DMA1 channel 2 register map base pointer */ +#define DMA1CH2_BASE ((struct dma_tube_reg_map*)0x4002001C) +/** DMA1 channel 3 register map base pointer */ +#define DMA1CH3_BASE ((struct dma_tube_reg_map*)0x40020030) +/** DMA1 channel 4 register map base pointer */ +#define DMA1CH4_BASE ((struct dma_tube_reg_map*)0x40020044) +/** DMA1 channel 5 register map base pointer */ +#define DMA1CH5_BASE ((struct dma_tube_reg_map*)0x40020058) +/** DMA1 channel 6 register map base pointer */ +#define DMA1CH6_BASE ((struct dma_tube_reg_map*)0x4002006C) +/** DMA1 channel 7 register map base pointer */ +#define DMA1CH7_BASE ((struct dma_tube_reg_map*)0x40020080) + +/** DMA2 channel 1 register map base pointer */ +#define DMA2CH1_BASE ((struct dma_tube_reg_map*)0x40020408) +/** DMA2 channel 2 register map base pointer */ +#define DMA2CH2_BASE ((struct dma_tube_reg_map*)0x4002041C) +/** DMA2 channel 3 register map base pointer */ +#define DMA2CH3_BASE ((struct dma_tube_reg_map*)0x40020430) +/** DMA2 channel 4 register map base pointer */ +#define DMA2CH4_BASE ((struct dma_tube_reg_map*)0x40020444) +/** DMA2 channel 5 register map base pointer */ +#define DMA2CH5_BASE ((struct dma_tube_reg_map*)0x40020458) + /* * Register bit definitions */ @@ -263,173 +302,259 @@ typedef struct dma_reg_map { * Devices */ -struct dma_dev; -extern struct dma_dev *DMA1; +extern dma_dev *DMA1; #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -extern struct dma_dev *DMA2; +extern dma_dev *DMA2; #endif /* - * Convenience routines. + * Other types needed by, or useful for, . */ -/* This hack is due to a circular dependency between us and - * . */ -static __always_inline dma_reg_map* _dma_dev_regs(struct dma_dev*); - -/** Flags for DMA transfer configuration. */ -typedef enum dma_mode_flags { - DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ - DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ - DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ - DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ - DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ - DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ - DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ - DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ -} dma_mode_flags; - -/** Source and destination transfer sizes. */ -typedef enum dma_xfer_size { - DMA_SIZE_8BITS = 0, /**< 8-bit transfers */ - DMA_SIZE_16BITS = 1, /**< 16-bit transfers */ - DMA_SIZE_32BITS = 2 /**< 32-bit transfers */ -} dma_xfer_size; - -/** DMA channel */ -typedef enum dma_channel { - DMA_CH1 = 1, /**< Channel 1 */ - DMA_CH2 = 2, /**< Channel 2 */ - DMA_CH3 = 3, /**< Channel 3 */ - DMA_CH4 = 4, /**< Channel 4 */ - DMA_CH5 = 5, /**< Channel 5 */ - DMA_CH6 = 6, /**< Channel 6 */ - DMA_CH7 = 7, /**< Channel 7 */ -} dma_channel; - -void dma_setup_transfer(struct dma_dev *dev, - dma_channel channel, - __io void *peripheral_address, - dma_xfer_size peripheral_size, - __io void *memory_address, - dma_xfer_size memory_size, - uint32 mode); - -void dma_set_num_transfers(struct dma_dev *dev, - dma_channel channel, - uint16 num_transfers); - -/** DMA transfer priority. */ -typedef enum dma_priority { - DMA_PRIORITY_LOW = DMA_CCR_PL_LOW, /**< Low priority */ - DMA_PRIORITY_MEDIUM = DMA_CCR_PL_MEDIUM, /**< Medium priority */ - DMA_PRIORITY_HIGH = DMA_CCR_PL_HIGH, /**< High priority */ - DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */ -} dma_priority; - -void dma_set_priority(struct dma_dev *dev, - dma_channel channel, - dma_priority priority); - -void dma_attach_interrupt(struct dma_dev *dev, - dma_channel channel, - void (*handler)(void)); -void dma_detach_interrupt(struct dma_dev *dev, dma_channel channel); - /** - * Encodes the reason why a DMA interrupt was called. - * @see dma_get_irq_cause() + * @brief STM32F1 dma_tube. + * On STM32F1, DMA tubes are just channels. */ -typedef enum dma_irq_cause { - DMA_TRANSFER_COMPLETE, /**< Transfer is complete. */ - DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */ - DMA_TRANSFER_ERROR, /**< Error occurred during transfer. */ -} dma_irq_cause; - -dma_irq_cause dma_get_irq_cause(struct dma_dev *dev, dma_channel channel); +#define dma_tube dma_channel -void dma_enable(struct dma_dev *dev, dma_channel channel); -void dma_disable(struct dma_dev *dev, dma_channel channel); - -void dma_set_mem_addr(struct dma_dev *dev, - dma_channel channel, - __io void *address); -void dma_set_per_addr(struct dma_dev *dev, - dma_channel channel, - __io void *address); +/** + * @brief On STM32F1, dma_channel_reg_map is an alias for dma_tube_reg_map. + * This is for backwards compatibility. */ +#define dma_channel_reg_map dma_tube_reg_map /** - * @brief DMA channel register map type. - * - * Provides access to an individual channel's registers. + * @brief STM32F1 configuration flags for dma_tube_config + * @see struct dma_tube_config */ -typedef struct dma_channel_reg_map { - __io uint32 CCR; /**< Channel configuration register */ - __io uint32 CNDTR; /**< Channel number of data register */ - __io uint32 CPAR; /**< Channel peripheral address register */ - __io uint32 CMAR; /**< Channel memory address register */ -} dma_channel_reg_map; - -#define DMA_CHANNEL_NREGS 5 +typedef enum dma_cfg_flags { + /** + * Source address increment mode + * + * If this flag is set, the source address is incremented (by the + * source size) after each DMA transfer. + */ + DMA_CFG_SRC_INC = 1U << 31, + + /** + * Destination address increment mode + * + * If this flag is set, the destination address is incremented (by + * the destination size) after each DMA transfer. + */ + DMA_CFG_DST_INC = 1U << 30, + + /** + * Circular mode + * + * This mode is not available for memory-to-memory transfers. + */ + DMA_CFG_CIRC = DMA_CCR_CIRC, + + /** Transfer complete interrupt enable */ + DMA_CFG_CMPLT_IE = DMA_CCR_TCIE, + /** Transfer half-complete interrupt enable */ + DMA_CFG_HALF_CMPLT_IE = DMA_CCR_HTIE, + /** Transfer error interrupt enable */ + DMA_CFG_ERR_IE = DMA_CCR_TEIE, +} dma_cfg_flags; /** - * @brief Obtain a pointer to an individual DMA channel's registers. + * @brief STM32F1 DMA request sources. + * + * IMPORTANT: * - * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1. + * 1. On STM32F1, each dma_request_src can only be used by a + * particular tube on a particular DMA controller. For example, + * DMA_REQ_SRC_ADC1 belongs to DMA1, tube 1. DMA2 cannot serve + * requests from ADC1, nor can DMA1 tube 2, etc. If you try to use a + * request source with the wrong DMA controller or tube on STM32F1, + * dma_tube_cfg() will fail. * - * @param dev DMA device - * @param channel DMA channel whose channel register map to obtain. + * 2. In general, a DMA tube can only serve a single request source at + * a time, and on STM32F1, Terrible Super-Bad Things will happen if + * two request sources are active for a single tube. + * + * To make all this easier to sort out, these dma_request_src + * enumerators are grouped by DMA controller and tube. + * + * @see struct dma_tube_config + * @see dma_tube_cfg() + */ +typedef enum dma_request_src { + /* Each request source encodes the DMA controller and channel it + * belongs to, for error checking in dma_tube_cfg(). */ + + /* DMA1 request sources */ + + /**@{*/ + /** (DMA1, tube 1) */ + DMA_REQ_SRC_ADC1 = (RCC_DMA1 << 3) | 1, + DMA_REQ_SRC_TIM2_CH3 = (RCC_DMA1 << 3) | 1, + DMA_REQ_SRC_TIM4_CH1 = (RCC_DMA1 << 3) | 1, + /**@}*/ + + /**@{*/ + /** (DMA1, tube 2)*/ + DMA_REQ_SRC_SPI1_RX = (RCC_DMA1 << 3) | 2, + DMA_REQ_SRC_USART3_TX = (RCC_DMA1 << 3) | 2, + DMA_REQ_SRC_TIM1_CH1 = (RCC_DMA1 << 3) | 2, + DMA_REQ_SRC_TIM2_UP = (RCC_DMA1 << 3) | 2, + DMA_REQ_SRC_TIM3_CH3 = (RCC_DMA1 << 3) | 2, + /**@}*/ + + /**@{*/ + /** (DMA1, tube 3)*/ + DMA_REQ_SRC_SPI1_TX = (RCC_DMA1 << 3) | 3, + DMA_REQ_SRC_USART3_RX = (RCC_DMA1 << 3) | 3, + DMA_REQ_SRC_TIM1_CH2 = (RCC_DMA1 << 3) | 3, + DMA_REQ_SRC_TIM3_CH4 = (RCC_DMA1 << 3) | 3, + DMA_REQ_SRC_TIM3_UP = (RCC_DMA1 << 3) | 3, + /**@}*/ + + /**@{*/ + /** (DMA1, tube 4)*/ + DMA_REQ_SRC_SPI2_RX = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_I2S2_RX = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_USART1_TX = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_I2C2_TX = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_TIM1_CH4 = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_TIM1_TRIG = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_TIM1_COM = (RCC_DMA1 << 3) | 4, + DMA_REQ_SRC_TIM4_CH2 = (RCC_DMA1 << 3) | 4, + /**@}*/ + + /**@{*/ + /** (DMA1, tube 5)*/ + DMA_REQ_SRC_SPI2_TX = (RCC_DMA1 << 3) | 5, + DMA_REQ_SRC_I2S2_TX = (RCC_DMA1 << 3) | 5, + DMA_REQ_SRC_USART1_RX = (RCC_DMA1 << 3) | 5, + DMA_REQ_SRC_I2C2_RX = (RCC_DMA1 << 3) | 5, + DMA_REQ_SRC_TIM1_UP = (RCC_DMA1 << 3) | 5, + DMA_REQ_SRC_TIM2_CH1 = (RCC_DMA1 << 3) | 5, + DMA_REQ_SRC_TIM4_CH3 = (RCC_DMA1 << 3) | 5, + /**@}*/ + + /**@{*/ + /** (DMA1, tube 6)*/ + DMA_REQ_SRC_USART2_RX = (RCC_DMA1 << 3) | 6, + DMA_REQ_SRC_I2C1_TX = (RCC_DMA1 << 3) | 6, + DMA_REQ_SRC_TIM1_CH3 = (RCC_DMA1 << 3) | 6, + DMA_REQ_SRC_TIM3_CH1 = (RCC_DMA1 << 3) | 6, + DMA_REQ_SRC_TIM3_TRIG = (RCC_DMA1 << 3) | 6, + /**@}*/ + + /**@{*/ + /* Tube 7 */ + DMA_REQ_SRC_USART2_TX = (RCC_DMA1 << 3) | 7, + DMA_REQ_SRC_I2C1_RX = (RCC_DMA1 << 3) | 7, + DMA_REQ_SRC_TIM2_CH2 = (RCC_DMA1 << 3) | 7, + DMA_REQ_SRC_TIM2_CH4 = (RCC_DMA1 << 3) | 7, + DMA_REQ_SRC_TIM4_UP = (RCC_DMA1 << 3) | 7, + /**@}*/ + + /* DMA2 request sources */ + + /**@{*/ + /** (DMA2, tube 1)*/ + DMA_REQ_SRC_SPI3_RX = (RCC_DMA2 << 3) | 1, + DMA_REQ_SRC_I2S3_RX = (RCC_DMA2 << 3) | 1, + DMA_REQ_SRC_TIM5_CH4 = (RCC_DMA2 << 3) | 1, + DMA_REQ_SRC_TIM5_TRIG = (RCC_DMA2 << 3) | 1, + /**@}*/ + + /**@{*/ + /** (DMA2, tube 2)*/ + DMA_REQ_SRC_SPI3_TX = (RCC_DMA2 << 3) | 2, + DMA_REQ_SRC_I2S3_TX = (RCC_DMA2 << 3) | 2, + DMA_REQ_SRC_TIM5_CH3 = (RCC_DMA2 << 3) | 2, + DMA_REQ_SRC_TIM5_UP = (RCC_DMA2 << 3) | 2, + /**@}*/ + + /**@{*/ + /** (DMA2, tube 3)*/ + DMA_REQ_SRC_UART4_RX = (RCC_DMA2 << 3) | 3, + DMA_REQ_SRC_TIM6_UP = (RCC_DMA2 << 3) | 3, + DMA_REQ_SRC_DAC_CH1 = (RCC_DMA2 << 3) | 3, + /**@}*/ + + /**@{*/ + /** (DMA2, tube 4)*/ + DMA_REQ_SRC_SDIO = (RCC_DMA2 << 3) | 4, + DMA_REQ_SRC_TIM5_CH2 = (RCC_DMA2 << 3) | 4, + /**@}*/ + + /**@{*/ + /** (DMA2, tube 5)*/ + DMA_REQ_SRC_ADC3 = (RCC_DMA2 << 3) | 5, + DMA_REQ_SRC_UART4_TX = (RCC_DMA2 << 3) | 5, + DMA_REQ_SRC_TIM5_CH1 = (RCC_DMA2 << 3) | 5, + /**@}*/ +} dma_request_src; + +/* + * Convenience routines. */ -static inline dma_channel_reg_map* dma_channel_regs(struct dma_dev *dev, - dma_channel channel) { - __io uint32 *ccr1 = &_dma_dev_regs(dev)->CCR1; - return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1)); -} /** - * @brief Check if a DMA channel is enabled - * @param dev DMA device - * @param channel Channel whose enabled bit to check. + * @brief On STM32F1, dma_is_channel_enabled() is an alias for + * dma_is_enabled(). + * This is for backwards compatibility. */ -static inline uint8 dma_is_channel_enabled(struct dma_dev *dev, - dma_channel channel) { - return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN); +#define dma_is_channel_enabled dma_is_enabled + +#define DMA_CHANNEL_NREGS 5 /* accounts for reserved word */ +static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube) { + __io uint32 *ccr1 = &dev->regs->CCR1; + return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (tube - 1)); } /** - * @brief Get the ISR status bits for a DMA channel. - * - * The bits are returned right-aligned, in the following order: - * transfer error flag, half-transfer flag, transfer complete flag, - * global interrupt flag. - * - * If you're attempting to figure out why a DMA interrupt fired; you - * may find dma_get_irq_cause() more convenient. - * - * @param dev DMA device - * @param channel Channel whose ISR bits to return. - * @see dma_get_irq_cause(). - */ -static inline uint8 dma_get_isr_bits(struct dma_dev *dev, - dma_channel channel) { - uint8 shift = (channel - 1) * 4; - return (_dma_dev_regs(dev)->ISR >> shift) & 0xF; + * @brief On STM32F1, dma_channel_regs() is an alias for dma_tube_regs(). + * This is for backwards compatibility. */ +#define dma_channel_regs(dev, ch) dma_tube_regs(dev, ch) + +static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) { + return (uint8)(dma_tube_regs(dev, tube)->CCR & DMA_CCR_EN); +} + +static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) { + uint8 shift = (tube - 1) * 4; + return (dev->regs->ISR >> shift) & 0xF; +} + +static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) { + dev->regs->IFCR = (1U << (4 * (tube - 1))); } /** - * @brief Clear the ISR status bits for a given DMA channel. - * - * If you're attempting to clean up after yourself in a DMA interrupt, - * you may find dma_get_irq_cause() more convenient. - * - * @param dev DMA device - * @param channel Channel whose ISR bits to clear. - * @see dma_get_irq_cause() + * @brief Deprecated + * STM32F1 mode flags for dma_setup_xfer(). Use dma_tube_cfg() instead. + * @see dma_tube_cfg() */ -static inline void dma_clear_isr_bits(struct dma_dev *dev, - dma_channel channel) { - _dma_dev_regs(dev)->IFCR = (1U << (4 * (channel - 1))); -} +typedef enum dma_mode_flags { + DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */ + DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */ + DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */ + DMA_CIRC_MODE = 1 << 5, /**< Circular mode */ + DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */ + DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */ + DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */ + DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */ +} dma_mode_flags; + +/* Keep this around for backwards compatibility, but it's deprecated. + * New code should use dma_tube_cfg() instead. + * + * (It's not possible to fully configure a DMA stream on F2 with just + * this information, so this interface is too tied to the F1.) */ +__deprecated +void dma_setup_transfer(dma_dev *dev, + dma_channel channel, + __io void *peripheral_address, + dma_xfer_size peripheral_size, + __io void *memory_address, + dma_xfer_size memory_size, + uint32 mode); #ifdef __cplusplus } // extern "C" -- cgit v1.2.3 From 0da5a577296ff3388feddb12bc86c43b61f54066 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 12:52:16 -0400 Subject: Implement DMA tube API on STM32F1. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/dma.c | 62 ++++++++++++++++++++++++++++++++--- libmaple/stm32f1/include/series/dma.h | 2 ++ 2 files changed, 60 insertions(+), 4 deletions(-) diff --git a/libmaple/stm32f1/dma.c b/libmaple/stm32f1/dma.c index fc502a1..5364a04 100644 --- a/libmaple/stm32f1/dma.c +++ b/libmaple/stm32f1/dma.c @@ -121,14 +121,57 @@ static int preconfig_check(dma_dev *dev, dma_channel channel, return DMA_TUBE_CFG_SUCCESS; } +static inline void set_ccr(dma_tube_reg_map *chregs, + dma_xfer_size msize, int minc, + dma_xfer_size psize, int pinc, + uint32 other_flags) { + chregs->CCR = ((msize << 10) | (psize << 8) | + (minc ? DMA_CCR_MINC : 0) | (pinc ? DMA_CCR_PINC : 0) | + other_flags); +} + +static inline uint32 cfg_ccr_flags(unsigned tube_flags) { + /* DMA_CFG_SRC_INC and DMA_CFG_DST_INC are special */ + return tube_flags & ~(DMA_CFG_SRC_INC | DMA_CFG_DST_INC); +} + /* Configure chregs according to cfg, where cfg->tube_dst is peripheral. */ static int config_to_per(dma_tube_reg_map *chregs, dma_tube_config *cfg) { - return -DMA_TUBE_CFG_ECFG; /* FIXME implement */ + /* Check that ->tube_src is memory (if it's anything else, we + * shouldn't have been called). */ + ASSERT(_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM); + + set_ccr(chregs, + cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC, + cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC, + (cfg_ccr_flags(cfg->tube_flags) | DMA_CCR_DIR_FROM_MEM)); + chregs->CMAR = (uint32)cfg->tube_src; + chregs->CPAR = (uint32)cfg->tube_dst; + return DMA_TUBE_CFG_SUCCESS; } /* Configure chregs according to cfg, where cfg->tube_dst is memory. */ static int config_to_mem(dma_tube_reg_map *chregs, dma_tube_config *cfg) { - return -DMA_TUBE_CFG_ECFG; /* FIXME implement */ + uint32 mem2mem; + + if ((_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM) && + (cfg->tube_flags & DMA_CFG_CIRC)) { + /* Can't do mem-to-mem and circular mode */ + return -DMA_TUBE_CFG_ECFG; + } + + mem2mem = (_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM ? + DMA_CCR_MEM2MEM : 0); + set_ccr(chregs, + cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC, + cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC, + (cfg_ccr_flags(cfg->tube_flags) | + DMA_CCR_DIR_FROM_PER | + mem2mem)); + chregs->CNDTR = cfg->tube_nr_xfers; + chregs->CMAR = (uint32)cfg->tube_dst; + chregs->CPAR = (uint32)cfg->tube_src; + return DMA_TUBE_CFG_SUCCESS; } /* @@ -143,17 +186,28 @@ int dma_tube_cfg(dma_dev *dev, dma_channel channel, dma_tube_config *cfg) { return ret; } + dma_disable(dev, channel); /* Must disable before reconfiguring */ + dma_clear_isr_bits(dev, channel); /* For sanity and consistency + * with STM32F2. */ + chregs = dma_tube_regs(dev, channel); switch (_dma_addr_type(cfg->tube_dst)) { case DMA_ATYPE_PER: - return config_to_per(chregs, cfg); + ret = config_to_per(chregs, cfg); + break; case DMA_ATYPE_MEM: - return config_to_mem(chregs, cfg); + ret = config_to_mem(chregs, cfg); + break; default: /* Can't happen */ ASSERT(0); return -DMA_TUBE_CFG_ECFG; } + if (ret < 0) { + return ret; + } + chregs->CNDTR = cfg->tube_nr_xfers; + return DMA_TUBE_CFG_SUCCESS; } void dma_set_priority(dma_dev *dev, diff --git a/libmaple/stm32f1/include/series/dma.h b/libmaple/stm32f1/include/series/dma.h index 6da3246..3b19e2b 100644 --- a/libmaple/stm32f1/include/series/dma.h +++ b/libmaple/stm32f1/include/series/dma.h @@ -293,6 +293,8 @@ typedef struct dma_tube_reg_map { #define DMA_CCR_PINC (1U << DMA_CCR_PINC_BIT) #define DMA_CCR_CIRC (1U << DMA_CCR_CIRC_BIT) #define DMA_CCR_DIR (1U << DMA_CCR_DIR_BIT) +#define DMA_CCR_DIR_FROM_PER (0U << DMA_CCR_DIR_BIT) +#define DMA_CCR_DIR_FROM_MEM (1U << DMA_CCR_DIR_BIT) #define DMA_CCR_TEIE (1U << DMA_CCR_TEIE_BIT) #define DMA_CCR_HTIE (1U << DMA_CCR_HTIE_BIT) #define DMA_CCR_TCIE (1U << DMA_CCR_TCIE_BIT) -- cgit v1.2.3 From 59b81331e9e767a271b873dc4a594e7406fa36a3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 13 Jun 2012 13:53:00 -0400 Subject: Port test-usart-dma.cpp to use tube API. This is straightforward. Do it in a verbose style with lots of comments, so we can use this patch as an example for how to port existing DMA code. Signed-off-by: Marti Bolivar --- examples/test-usart-dma.cpp | 74 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 61 insertions(+), 13 deletions(-) diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index 4a63044..04117c3 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -14,7 +14,9 @@ * particular, since the buffer keeps filling (DMA_CIRC_MODE is set), * if you keep sending characters after filling the buffer, you'll * overwrite earlier bytes; this may happen before those earlier bytes - * are done printing. + * are done printing. (Typing quickly and seeing how it affects the + * output is a fun way to make sense of how the interrupts and the + * main thread of execution interleave.) * * This code is released into the public domain. */ @@ -33,9 +35,18 @@ // your purposes. HardwareSerial *serial = &Serial2; #define USART_DMA_DEV DMA1 -#define USART_RX_DMA_CHANNEL DMA_CH6 +// On STM32F1 microcontrollers (like what's on Maple and Maple Mini), +// dma tubes are channels. +#define USART_RX_DMA_TUBE DMA_CH6 +// The serial port will make a DMA request each time it receives data. +// This is the dma_request_src we use to tell the DMA tube to handle +// that DMA request. +#define USART_DMA_REQ_SRC DMA_REQ_SRC_USART2_RX #define BAUD 9600 +// This will store the DMA configuration for USART RX. +dma_tube_config tube_config; + // This will store received USART characters. #define BUF_SIZE 20 char rx_buf[BUF_SIZE]; @@ -54,7 +65,7 @@ volatile uint32 isr = 0; // This is our DMA interrupt handler. void rx_dma_irq(void) { irq_fired = 1; - isr = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); + isr = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_TUBE); } // Configure the USART receiver for use with DMA: @@ -66,17 +77,53 @@ void setup_usart(void) { serial_dev->regs->CR3 = USART_CR3_DMAR; } +// Set up our dma_tube_config structure. (We could have done this +// above, when we declared tube_config, but having this function makes +// it easier to explain what's going on). +void setup_tube_config(void) { + // We're receiving from the USART data register. serial->c_dev() + // returns a pointer to the libmaple usart_dev for that serial + // port, so this is a pointer to its data register. + tube_config.tube_src = &serial->c_dev()->regs->DR; + // We're only interested in the bottom 8 bits of that data register. + tube_config.tube_src_size = DMA_SIZE_8BITS; + // We're storing to rx_buf. + tube_config.tube_dst = rx_buf; + // rx_buf is a char array, and a "char" takes up 8 bits on STM32. + tube_config.tube_dst_size = DMA_SIZE_8BITS; + // Only fill BUF_SIZE - 1 characters, to leave a null byte at the end. + tube_config.tube_nr_xfers = BUF_SIZE - 1; + // Flags: + // - DMA_CFG_DST_INC so we start at the beginning of rx_buf and + // fill towards the end. + // - DMA_CFG_CIRC so we go back to the beginning and start over when + // rx_buf fills up. + // - DMA_CFG_CMPLT_IE to turn on interrupts on transfer completion. + tube_config.tube_flags = DMA_CFG_DST_INC | DMA_CFG_CIRC | DMA_CFG_CMPLT_IE; + // Target data: none. It's important to set this to NULL if you + // don't have any special (microcontroller-specific) configuration + // in mind, which we don't. + tube_config.target_data = NULL; + // DMA request source. + tube_config.tube_req_src = USART_DMA_REQ_SRC; +} + // Configure the DMA controller to serve DMA requests from the USART. void setup_dma_xfer(void) { + // First, turn it on. dma_init(USART_DMA_DEV); - dma_setup_transfer(USART_DMA_DEV, USART_RX_DMA_CHANNEL, - &serial->c_dev()->regs->DR, DMA_SIZE_8BITS, - rx_buf, DMA_SIZE_8BITS, - (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_TRNS_CMPLT)); - dma_set_num_transfers(USART_DMA_DEV, USART_RX_DMA_CHANNEL, - BUF_SIZE - 1); - dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_CHANNEL, rx_dma_irq); - dma_enable(USART_DMA_DEV, USART_RX_DMA_CHANNEL); + // Next, configure it by calling dma_tube_cfg(), and check to make + // sure it succeeded. DMA tubes have many restrictions on their + // configuration, and there are configurations which work on some + // types of STM32 but not others. libmaple tries hard to make + // things just work, but checking the return status is important! + int status = dma_tube_cfg(USART_DMA_DEV, USART_RX_DMA_TUBE, &tube_config); + ASSERT(status == DMA_TUBE_CFG_SUCCESS); + // Now we'll perform any other configuration we want. For this + // example, we attach an interrupt handler. + dma_attach_interrupt(USART_DMA_DEV, USART_RX_DMA_TUBE, rx_dma_irq); + // Turn on the DMA tube. It will now begin serving requests. + dma_enable(USART_DMA_DEV, USART_RX_DMA_TUBE); } /* @@ -85,6 +132,7 @@ void setup_dma_xfer(void) { void setup(void) { pinMode(BOARD_LED_PIN, OUTPUT); + setup_tube_config(); setup_dma_xfer(); setup_usart(); } @@ -121,7 +169,7 @@ void loop(void) { serial->print("["); serial->print(millis()); serial->print("]\tISR bits: 0x"); - uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); + uint8 isr_bits = dma_get_isr_bits(USART_DMA_DEV, USART_RX_DMA_TUBE); serial->print(isr_bits, HEX); // Print the contents of rx_buf. If you keep typing after it fills @@ -132,7 +180,7 @@ void loop(void) { serial->println("'"); if (isr_bits == 0x7) { serial->println("** Clearing ISR bits."); - dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_CHANNEL); + dma_clear_isr_bits(USART_DMA_DEV, USART_RX_DMA_TUBE); } } -- cgit v1.2.3 From e72e411c1f0e4f96326351264301c6e475206e30 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 14 Jun 2012 18:31:40 -0400 Subject: Implement DMA tube API on STM32F2. Signed-off-by: Marti Bolivar --- libmaple/rules.mk | 2 - libmaple/stm32f2/dma.c | 504 +++++++++++++++++++++ libmaple/stm32f2/include/series/dma.h | 810 ++++++++++++++++++++++++++++++++++ libmaple/stm32f2/rules.mk | 1 + 4 files changed, 1315 insertions(+), 2 deletions(-) create mode 100644 libmaple/stm32f2/dma.c create mode 100644 libmaple/stm32f2/include/series/dma.h diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 0c29ec7..41f5601 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -13,9 +13,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror # Local rules and targets cSRCS_$(d) := adc.c cSRCS_$(d) += dac.c -ifeq ($(MCU_SERIES),stm32f1) # FIXME add F2 support cSRCS_$(d) += dma.c -endif cSRCS_$(d) += exti.c cSRCS_$(d) += flash.c cSRCS_$(d) += gpio.c diff --git a/libmaple/stm32f2/dma.c b/libmaple/stm32f2/dma.c new file mode 100644 index 0000000..26e87b9 --- /dev/null +++ b/libmaple/stm32f2/dma.c @@ -0,0 +1,504 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/dma.c + * @author Marti Bolivar + * @brief STM32F2 DMA support. + */ + +#include +#include +#include + +/* Hack to ensure inlining in dma_irq_handler() */ +#define DMA_GET_HANDLER(dev, tube) (dev->handlers[tube].handler) +#include "dma_private.h" + +/* + * Devices + */ + +static dma_dev dma1 = { + .regs = DMA1_BASE, + .clk_id = RCC_DMA1, + .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA1_STREAM0 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM1 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM2 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM3 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM4 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM5 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM6 }, + { .handler = NULL, .irq_line = NVIC_DMA1_STREAM7 }}, +}; +dma_dev *DMA1 = &dma1; + +static dma_dev dma2 = { + .regs = DMA2_BASE, + .clk_id = RCC_DMA2, + .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_STREAM0 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM1 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM2 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM3 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM4 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM5 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM6 }, + { .handler = NULL, .irq_line = NVIC_DMA2_STREAM7 }}, +}; +dma_dev *DMA2 = &dma2; + +/* + * Helpers for dealing with dma_request_src's bit encoding (see the + * comments in the dma_request_src definition). + */ + +/* rcc_clk_id of dma_dev which supports src. */ +static __always_inline rcc_clk_id src_clk_id(dma_request_src src) { + return (rcc_clk_id)(((uint32)src >> 3) & 0x3F); +} + +/* Bit vector of streams supporting src (e.g., bit 0 set => DMA_S0 support). */ +static __always_inline uint32 src_stream_mask(dma_request_src src) { + return ((uint32)src >> 10) & 0xFF; +} + +/* Channel corresponding to src. */ +static __always_inline dma_channel src_channel(dma_request_src src) { + return (dma_channel)(src & 0x7); +} + +/* + * Routines + */ + +/* For convenience */ +#define ASSERT_NOT_ENABLED(dev, tube) ASSERT(!dma_is_enabled(dev, tube)) + +/* Helpers for dma_tube_cfg() */ +static int preconfig_check(dma_dev *dev, dma_tube tube, dma_tube_config *cfg); +static int postconfig_check(dma_tube_reg_map *dummy, dma_tube_config *cfg); +static int config_fifo(dma_tube_reg_map *dummy, dma_tube_config *cfg); +static int config_src_dst(dma_tube_reg_map *dummy, dma_tube_config *cfg); +static void copy_regs(dma_tube_reg_map *src, dma_tube_reg_map *dst); + +int dma_tube_cfg(dma_dev *dev, dma_tube tube, dma_tube_config *cfg) { + dma_tube_reg_map dummy_regs; + dma_tube_reg_map *tregs = dma_tube_regs(dev, tube); + int ret; + + /* Initial error checking. */ + ret = preconfig_check(dev, tube, cfg); + if (ret < 0) { + return ret; + } + + /* Disable `tube' as per RM0033. */ + dma_disable(dev, tube); + dma_clear_isr_bits(dev, tube); + + /* Don't write to tregs until we've decided `cfg' is really OK, + * so as not to make a half-formed mess if we have to error out. */ + copy_regs(tregs, &dummy_regs); + + /* Try to reconfigure `tube', bailing on error. */ + ret = config_fifo(&dummy_regs, cfg); + if (ret < 0) { + return ret; + } + ret = config_src_dst(&dummy_regs, cfg); + if (ret < 0) { + return ret; + } + dummy_regs.SNDTR = cfg->tube_nr_xfers; + ret = postconfig_check(&dummy_regs, cfg); + if (ret < 0) { + return ret; + } + + /* Ok, we're good. Commit to the new configuration. */ + copy_regs(&dummy_regs, tregs); + return ret; +} + +void dma_set_priority(dma_dev *dev, dma_stream stream, dma_priority priority) { + dma_tube_reg_map *tregs = dma_tube_regs(dev, stream); + uint32 scr; + ASSERT_NOT_ENABLED(dev, stream); + scr = tregs->SCR; + scr &= ~DMA_SCR_PL; + scr |= (priority << 16); + tregs->SCR = scr; +} + +void dma_set_num_transfers(dma_dev *dev, dma_tube tube, uint16 num_transfers) { + dma_tube_reg_map *tregs = dma_tube_regs(dev, tube); + ASSERT_NOT_ENABLED(dev, tube); + tregs->SNDTR = num_transfers; +} + +/** + * @brief Set memory 0 or memory 1 address. + * + * This is a general function for setting one of the two memory + * addresses available on the double-buffered STM32F2 DMA controllers. + * + * @param dev DMA device + * @param tube Tube on dev. + * @param n If 0, set memory 0 address. If 1, set memory 1 address. + * @param address Address to set + */ +void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n, + __io void *address) { + dma_tube_reg_map *tregs = dma_tube_regs(dev, tube); + uint32 addr = (uint32)address; + + ASSERT_NOT_ENABLED(dev, tube); + if (n) { + tregs->SM1AR = addr; + } else { + tregs->SM0AR = addr; + } +} + +void dma_set_per_addr(dma_dev *dev, dma_tube tube, __io void *address) { + dma_tube_reg_map *tregs = dma_tube_regs(dev, tube); + ASSERT_NOT_ENABLED(dev, tube); + tregs->SPAR = (uint32)address; +} + +/** + * @brief Enable a stream's FIFO. + * + * You may only call this function when the stream is disabled. + * + * @param dev DMA device + * @param tube Stream whose FIFO to enable. + */ +void dma_enable_fifo(dma_dev *dev, dma_tube tube) { + ASSERT_NOT_ENABLED(dev, tube); + bb_peri_set_bit(&(dma_tube_regs(dev, tube)->SFCR), DMA_SFCR_DMDIS_BIT, 1); +} + +/** + * @brief Disable a stream's FIFO. + * + * You may only call this function when the stream is disabled. + * + * @param dev DMA device + * @param tube Stream whose FIFO to disable. + */ +void dma_disable_fifo(dma_dev *dev, dma_tube tube) { + ASSERT_NOT_ENABLED(dev, tube); + bb_peri_set_bit(&(dma_tube_regs(dev, tube)->SFCR), DMA_SFCR_DMDIS_BIT, 0); +} + +void dma_attach_interrupt(dma_dev *dev, dma_tube tube, + void (*handler)(void)) { + dev->handlers[tube].handler = handler; + nvic_irq_enable(dev->handlers[tube].irq_line); +} + +void dma_detach_interrupt(dma_dev *dev, dma_tube tube) { + nvic_irq_disable(dev->handlers[tube].irq_line); + dev->handlers[tube].handler = NULL; +} + +void dma_enable(dma_dev *dev, dma_tube tube) { + dma_tube_reg_map *tregs = dma_tube_regs(dev, tube); + bb_peri_set_bit(&tregs->SCR, DMA_SCR_EN_BIT, 1); +} + +void dma_disable(dma_dev *dev, dma_tube tube) { + dma_tube_reg_map *tregs = dma_tube_regs(dev, tube); + bb_peri_set_bit(&tregs->SCR, DMA_SCR_EN_BIT, 0); + /* The stream might not get disabled immediately, so wait. */ + while (tregs->SCR & DMA_SCR_EN) + ; +} + +dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_tube tube) { + /* TODO: does it still make sense to have this function? We should + * probably just be returning the ISR bits, with some defines to + * pull the flags out. The lack of masked status bits is an + * annoyance that would require documentation to solve, though. */ + uint8 status_bits = dma_get_isr_bits(dev, tube); + dma_clear_isr_bits(dev, tube); + ASSERT(status_bits); /* Or something's very wrong */ + /* Don't change the order of these if statements. */ + if (status_bits & 0x0) { + return DMA_TRANSFER_FIFO_ERROR; + } else if (status_bits & 0x4) { + return DMA_TRANSFER_DME_ERROR; + } else if (status_bits & 0x8) { + return DMA_TRANSFER_ERROR; + } else if (status_bits & 0x20) { + return DMA_TRANSFER_COMPLETE; + } else if (status_bits & 0x10) { + return DMA_TRANSFER_HALF_COMPLETE; + } + + /* Something's wrong; one of those bits should have been set. Fail + * an assert, and mimic the error behavior in case of a high debug + * level. */ + ASSERT(0); + dma_disable(dev, tube); + return DMA_TRANSFER_ERROR; +} + +/* + * IRQ handlers + */ + +void __irq_dma1_stream0(void) { + dma_irq_handler(DMA1, DMA_S0); +} + +void __irq_dma1_stream1(void) { + dma_irq_handler(DMA1, DMA_S1); +} + +void __irq_dma1_stream2(void) { + dma_irq_handler(DMA1, DMA_S2); +} + +void __irq_dma1_stream3(void) { + dma_irq_handler(DMA1, DMA_S3); +} + +void __irq_dma1_stream4(void) { + dma_irq_handler(DMA1, DMA_S4); +} + +void __irq_dma1_stream5(void) { + dma_irq_handler(DMA1, DMA_S5); +} + +void __irq_dma1_stream6(void) { + dma_irq_handler(DMA1, DMA_S6); +} + +void __irq_dma1_stream7(void) { + dma_irq_handler(DMA1, DMA_S7); +} + +void __irq_dma2_stream0(void) { + dma_irq_handler(DMA2, DMA_S0); +} + +void __irq_dma2_stream1(void) { + dma_irq_handler(DMA2, DMA_S1); +} + +void __irq_dma2_stream2(void) { + dma_irq_handler(DMA2, DMA_S2); +} + +void __irq_dma2_stream3(void) { + dma_irq_handler(DMA2, DMA_S3); +} + +void __irq_dma2_stream4(void) { + dma_irq_handler(DMA2, DMA_S4); +} + +void __irq_dma2_stream5(void) { + dma_irq_handler(DMA2, DMA_S5); +} + +void __irq_dma2_stream6(void) { + dma_irq_handler(DMA2, DMA_S6); +} + +void __irq_dma2_stream7(void) { + dma_irq_handler(DMA2, DMA_S7); +} + +/* + * Auxiliary routines for dma_tube_cfg() + */ + +/* Is addr acceptable for use as DMA src/dst? */ +static int cfg_mem_ok(__io void *addr) { + enum dma_atype atype = _dma_addr_type(addr); + return atype == DMA_ATYPE_MEM || atype == DMA_ATYPE_PER; +} + +/* Is src -> dst a reasonable combination of [MEM,PER] -> [MEM,PER]? */ +static int cfg_dir_ok(dma_dev *dev, __io void *src, __io void *dst) { + switch (_dma_addr_type(dst)) { + case DMA_ATYPE_MEM: + /* Only DMA2 can do memory-to-memory */ + return ((_dma_addr_type(src) == DMA_ATYPE_PER) || + (dev->clk_id == RCC_DMA2)); + case DMA_ATYPE_PER: + /* Peripheral-to-peripheral is illegal */ + return _dma_addr_type(src) == DMA_ATYPE_PER; + default: /* Can't happen */ + ASSERT(0); + return 0; + } +} + +/* Initial sanity check for dma_tube_cfg() */ +static int preconfig_check(dma_dev *dev, dma_tube tube, + dma_tube_config *cfg) { + if (!(src_stream_mask(cfg->tube_req_src) & (1U << tube))) { + /* ->tube_req_src not supported by stream */ + return -DMA_TUBE_CFG_EREQ; + } + if (cfg->tube_nr_xfers > 65535) { + /* That's too many. */ + return -DMA_TUBE_CFG_ENDATA; + } + if (src_clk_id(cfg->tube_req_src) != dev->clk_id) { + /* ->tube_req_src not supported by dev */ + return -DMA_TUBE_CFG_EDEV; + } + if (!cfg_mem_ok(cfg->tube_src)) { + return -DMA_TUBE_CFG_ESRC; + } + if (!cfg_mem_ok(cfg->tube_dst)) { + return -DMA_TUBE_CFG_EDST; + } + if (!cfg_dir_ok(dev, cfg->tube_src, cfg->tube_dst)) { + return -DMA_TUBE_CFG_EDIR; + } + return DMA_TUBE_CFG_SUCCESS; +} + +static int config_fifo(dma_tube_reg_map *dummy, dma_tube_config *cfg) { + /* TODO: FIFO configuration based on cfg->target_data */ + uint32 sfcr = dummy->SFCR; + sfcr &= ~DMA_SFCR_FEIE; + sfcr |= (cfg->tube_flags & DMA_CFG_FIFO_ERR_IE) ? DMA_SFCR_FEIE : 0; + dummy->SFCR = sfcr; + return DMA_TUBE_CFG_SUCCESS; +} + +/* Helper for configuring (DMA_SxCR) */ +#define BITS_WE_CARE_ABOUT \ + (DMA_SCR_CHSEL | DMA_SCR_MBURST | DMA_SCR_PBURST | DMA_SCR_PINCOS | \ + DMA_SCR_MINC | DMA_SCR_PINC | DMA_SCR_CIRC | DMA_SCR_DIR | \ + DMA_SCR_PFCTRL | DMA_SCR_TCIE | DMA_SCR_HTIE | DMA_SCR_TEIE | \ + DMA_SCR_DMEIE) +static inline void config_scr(dma_tube_reg_map *dummy, dma_tube_config *cfg, + unsigned src_shift, uint32 src_inc, + unsigned dst_shift, uint32 dst_inc, + uint32 dir) { + /* These would go here if we supported them: MBURST, PBURST, + * PINCOS, PFCTRL. We explicitly choose low priority, and double + * buffering belongs elsewhere, I think. [mbolivar] */ + uint32 flags = cfg->tube_flags & BITS_WE_CARE_ABOUT; + uint32 scr = dummy->SCR; + scr &= ~(BITS_WE_CARE_ABOUT | DMA_SCR_PL); + scr |= (/* CHSEL */ + (src_channel(cfg->tube_req_src) << 25) | + /* MSIZE/PSIZE */ + (cfg->tube_src_size << src_shift) | + (cfg->tube_dst_size << dst_shift) | + /* MINC/PINC */ + ((cfg->tube_flags & DMA_CFG_SRC_INC) ? src_inc : 0) | + ((cfg->tube_flags & DMA_CFG_DST_INC) ? dst_inc : 0) | + /* DIR */ + dir | + /* Other flags carried by cfg->tube_flags */ + flags); + dummy->SCR = scr; +} +#undef BITS_WE_CARE_ABOUT + +/* Helper for when cfg->tube_dst is memory */ +static int config_to_mem(dma_tube_reg_map *dummy, dma_tube_config *cfg) { + uint32 dir = (_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM ? + DMA_SCR_DIR_MEM_TO_MEM : DMA_SCR_DIR_PER_TO_MEM); + + if ((dir == DMA_SCR_DIR_MEM_TO_MEM) && (cfg->tube_flags & DMA_CFG_CIRC)) { + return -DMA_TUBE_CFG_ECFG; /* Can't do DMA_CFG_CIRC and mem->mem. */ + } + + config_scr(dummy, cfg, 11, DMA_SCR_PINC, 13, DMA_SCR_MINC, dir); + dummy->SPAR = (uint32)cfg->tube_src; + dummy->SM0AR = (uint32)cfg->tube_dst; + return DMA_TUBE_CFG_SUCCESS; +} + +/* Helper for when cfg->tube_src is peripheral */ +static int config_to_per(dma_tube_reg_map *dummy, dma_tube_config *cfg) { + config_scr(dummy, cfg, 13, DMA_SCR_MINC, 11, DMA_SCR_PINC, + DMA_SCR_DIR_MEM_TO_PER); + dummy->SM0AR = (uint32)cfg->tube_src; + dummy->SPAR = (uint32)cfg->tube_dst; + return DMA_TUBE_CFG_SUCCESS; +} + +/* Configures SCR, SPAR, SM0AR, and checks that the result is OK. */ +static int config_src_dst(dma_tube_reg_map *dummy, dma_tube_config *cfg) { + switch (_dma_addr_type(cfg->tube_dst)) { + case DMA_ATYPE_MEM: + return config_to_mem(dummy, cfg); + case DMA_ATYPE_PER: + return config_to_per(dummy, cfg); + case DMA_ATYPE_OTHER: + default: /* shut up, GCC */ + /* Can't happen */ + ASSERT(0); + return -DMA_TUBE_CFG_ECFG; + } +} + +/* Final checks we can only perform when fully configured */ +static int postconfig_check(dma_tube_reg_map *dummy, dma_tube_config *cfg) { + /* TODO add dma_get_[mem,per]_size() and use them here */ + /* msize and psize are in bytes here: */ + uint32 scr = dummy->SCR; + uint32 msize = 1U << ((scr >> 13) & 0x3); + uint32 psize = 1U << ((scr >> 11) & 0x3); + + /* Ensure NDT will work with PSIZE/MSIZE. + * + * RM0033 specifies that PSIZE, MSIZE, and NDT must be such that + * the last transfer completes; i.e. that if PSIZE < MSIZE, then + * NDT is a multiple of MSIZE/PSIZE. See e.g. Table 27. */ + if ((psize < msize) && (cfg->tube_nr_xfers % (msize / psize))) { + return -DMA_TUBE_CFG_ENDATA; + } + + /* Direct mode is only possible if MSIZE == PSIZE. */ + if ((msize != psize) && !(dummy->SFCR & DMA_SFCR_DMDIS)) { + return -DMA_TUBE_CFG_ESIZE; + } + + return DMA_TUBE_CFG_SUCCESS; +} + +/* Convenience for dealing with dummy registers */ +static void copy_regs(dma_tube_reg_map *src, dma_tube_reg_map *dst) { + dst->SCR = src->SCR; + dst->SNDTR = src->SNDTR; + dst->SPAR = src->SPAR; + dst->SM0AR = src->SM0AR; + dst->SFCR = src->SFCR; +} diff --git a/libmaple/stm32f2/include/series/dma.h b/libmaple/stm32f2/include/series/dma.h new file mode 100644 index 0000000..43bd1a2 --- /dev/null +++ b/libmaple/stm32f2/include/series/dma.h @@ -0,0 +1,810 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/stm32f2/include/series/dma.h + * @author Marti Bolivar + * @brief STM32F2 DMA series header + */ + +#ifndef _LIBMAPLE_STM32F2_DMA_H_ +#define _LIBMAPLE_STM32F2_DMA_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include + +/* + * Register map and base pointers + */ + +/** + * @brief STM32F2 DMA register map type. + */ +typedef struct dma_reg_map { + /* Isn't it nice how on F1, it's CCR1, but on F2, it's S1CR? */ + + /* Global DMA registers */ + __io uint32 LISR; /**< Low interrupt status register */ + __io uint32 HISR; /**< High interrupt status register */ + __io uint32 LIFCR; /**< Low interrupt flag clear register */ + __io uint32 HIFCR; /**< High interrupt flag clear register */ + /* Stream 0 registers */ + __io uint32 S0CR; /**< Stream 0 control register */ + __io uint32 S0NDTR; /**< Stream 0 number of data register */ + __io uint32 S0PAR; /**< Stream 0 peripheral address register */ + __io uint32 S0M0AR; /**< Stream 0 memory 0 address register */ + __io uint32 S0M1AR; /**< Stream 0 memory 1 address register */ + __io uint32 S0FCR; /**< Stream 0 FIFO control register */ + /* Stream 1 registers */ + __io uint32 S1CR; /**< Stream 1 control register */ + __io uint32 S1NDTR; /**< Stream 1 number of data register */ + __io uint32 S1PAR; /**< Stream 1 peripheral address register */ + __io uint32 S1M0AR; /**< Stream 1 memory 0 address register */ + __io uint32 S1M1AR; /**< Stream 1 memory 1 address register */ + __io uint32 S1FCR; /**< Stream 1 FIFO control register */ + /* Stream 2 registers */ + __io uint32 S2CR; /**< Stream 2 control register */ + __io uint32 S2NDTR; /**< Stream 2 number of data register */ + __io uint32 S2PAR; /**< Stream 2 peripheral address register */ + __io uint32 S2M0AR; /**< Stream 2 memory 0 address register */ + __io uint32 S2M1AR; /**< Stream 2 memory 1 address register */ + __io uint32 S2FCR; /**< Stream 2 FIFO control register */ + /* Stream 3 registers */ + __io uint32 S3CR; /**< Stream 3 control register */ + __io uint32 S3NDTR; /**< Stream 3 number of data register */ + __io uint32 S3PAR; /**< Stream 3 peripheral address register */ + __io uint32 S3M0AR; /**< Stream 3 memory 0 address register */ + __io uint32 S3M1AR; /**< Stream 3 memory 1 address register */ + __io uint32 S3FCR; /**< Stream 3 FIFO control register */ + /* Stream 4 registers */ + __io uint32 S4CR; /**< Stream 4 control register */ + __io uint32 S4NDTR; /**< Stream 4 number of data register */ + __io uint32 S4PAR; /**< Stream 4 peripheral address register */ + __io uint32 S4M0AR; /**< Stream 4 memory 0 address register */ + __io uint32 S4M1AR; /**< Stream 4 memory 1 address register */ + __io uint32 S4FCR; /**< Stream 4 FIFO control register */ + /* Stream 5 registers */ + __io uint32 S5CR; /**< Stream 5 control register */ + __io uint32 S5NDTR; /**< Stream 5 number of data register */ + __io uint32 S5PAR; /**< Stream 5 peripheral address register */ + __io uint32 S5M0AR; /**< Stream 5 memory 0 address register */ + __io uint32 S5M1AR; /**< Stream 5 memory 1 address register */ + __io uint32 S5FCR; /**< Stream 5 FIFO control register */ + /* Stream 6 registers */ + __io uint32 S6CR; /**< Stream 6 control register */ + __io uint32 S6NDTR; /**< Stream 6 number of data register */ + __io uint32 S6PAR; /**< Stream 6 peripheral address register */ + __io uint32 S6M0AR; /**< Stream 6 memory 0 address register */ + __io uint32 S6M1AR; /**< Stream 6 memory 1 address register */ + __io uint32 S6FCR; /**< Stream 6 FIFO control register */ + /* Stream 7 registers */ + __io uint32 S7CR; /**< Stream 7 control register */ + __io uint32 S7NDTR; /**< Stream 7 number of data register */ + __io uint32 S7PAR; /**< Stream 7 peripheral address register */ + __io uint32 S7M0AR; /**< Stream 7 memory 0 address register */ + __io uint32 S7M1AR; /**< Stream 7 memory 1 address register */ + __io uint32 S7FCR; /**< Stream 7 FIFO control register */ +} dma_reg_map; + +/** DMA controller 1 register map base pointer */ +#define DMA1_BASE ((struct dma_reg_map*)0x40026000) +/** DMA controller 2 register map base pointer */ +#define DMA2_BASE ((struct dma_reg_map*)0x40026400) + +/** + * @brief STM32F2 DMA stream (i.e. tube) register map type. + * Provides access to an individual stream's registers. + * @see dma_tube_regs() + */ +typedef struct dma_tube_reg_map { + __io uint32 SCR; /**< Stream configuration register */ + __io uint32 SNDTR; /**< Stream number of data register */ + __io uint32 SPAR; /**< Stream peripheral address register */ + __io uint32 SM0AR; /**< Stream memory 0 address register */ + __io uint32 SM1AR; /**< Stream memory 1 address register */ + __io uint32 SFCR; /**< Stream FIFO control register */ +} dma_tube_reg_map; + +/** DMA1 stream 0 register map base pointer */ +#define DMA1S0_BASE ((struct dma_tube_reg_map*)0x40026010) +/** DMA1 stream 1 register map base pointer */ +#define DMA1S1_BASE ((struct dma_tube_reg_map*)0x40026028) +/** DMA1 stream 2 register map base pointer */ +#define DMA1S2_BASE ((struct dma_tube_reg_map*)0x40026040) +/** DMA1 stream 3 register map base pointer */ +#define DMA1S3_BASE ((struct dma_tube_reg_map*)0x40026058) +/** DMA1 stream 4 register map base pointer */ +#define DMA1S4_BASE ((struct dma_tube_reg_map*)0x40026070) +/** DMA1 stream 5 register map base pointer */ +#define DMA1S5_BASE ((struct dma_tube_reg_map*)0x40026088) +/** DMA1 stream 6 register map base pointer */ +#define DMA1S6_BASE ((struct dma_tube_reg_map*)0x400260A0) +/** DMA1 stream 7 register map base pointer */ +#define DMA1S7_BASE ((struct dma_tube_reg_map*)0x400260B8) + +/** DMA2 stream 0 register map base pointer */ +#define DMA2S0_BASE ((struct dma_tube_reg_map*)0x40026410) +/** DMA2 stream 1 register map base pointer */ +#define DMA2S1_BASE ((struct dma_tube_reg_map*)0x40026028) +/** DMA2 stream 2 register map base pointer */ +#define DMA2S2_BASE ((struct dma_tube_reg_map*)0x40026040) +/** DMA2 stream 3 register map base pointer */ +#define DMA2S3_BASE ((struct dma_tube_reg_map*)0x40026058) +/** DMA2 stream 4 register map base pointer */ +#define DMA2S4_BASE ((struct dma_tube_reg_map*)0x40026070) +/** DMA2 stream 5 register map base pointer */ +#define DMA2S5_BASE ((struct dma_tube_reg_map*)0x40026088) +/** DMA2 stream 6 register map base pointer */ +#define DMA2S6_BASE ((struct dma_tube_reg_map*)0x400260A0) +/** DMA2 stream 7 register map base pointer */ +#define DMA2S7_BASE ((struct dma_tube_reg_map*)0x400260B8) + +/* + * Register bit definitions + */ + +/* Low interrupt status register */ + +#define DMA_LISR_TCIF3_BIT 27 +#define DMA_LISR_HTIF3_BIT 26 +#define DMA_LISR_TEIF3_BIT 25 +#define DMA_LISR_DMEIF3_BIT 24 +#define DMA_LISR_FEIF3_BIT 22 +#define DMA_LISR_TCIF2_BIT 21 +#define DMA_LISR_HTIF2_BIT 20 +#define DMA_LISR_TEIF2_BIT 19 +#define DMA_LISR_DMEIF2_BIT 18 +#define DMA_LISR_FEIF2_BIT 16 +#define DMA_LISR_TCIF1_BIT 11 +#define DMA_LISR_HTIF1_BIT 10 +#define DMA_LISR_TEIF1_BIT 9 +#define DMA_LISR_DMEIF1_BIT 8 +#define DMA_LISR_FEIF1_BIT 6 +#define DMA_LISR_TCIF0_BIT 5 +#define DMA_LISR_HTIF0_BIT 4 +#define DMA_LISR_TEIF0_BIT 3 +#define DMA_LISR_DMEIF0_BIT 2 +#define DMA_LISR_FEIF0_BIT 0 + +#define DMA_LISR_TCIF3 (1U << DMA_LISR_TCIF3_BIT) +#define DMA_LISR_HTIF3 (1U << DMA_LISR_HTIF3_BIT) +#define DMA_LISR_TEIF3 (1U << DMA_LISR_TEIF3_BIT) +#define DMA_LISR_DMEIF3 (1U << DMA_LISR_DMEIF3_BIT) +#define DMA_LISR_FEIF3 (1U << DMA_LISR_FEIF3_BIT) +#define DMA_LISR_TCIF2 (1U << DMA_LISR_TCIF2_BIT) +#define DMA_LISR_HTIF2 (1U << DMA_LISR_HTIF2_BIT) +#define DMA_LISR_TEIF2 (1U << DMA_LISR_TEIF2_BIT) +#define DMA_LISR_DMEIF2 (1U << DMA_LISR_DMEIF2_BIT) +#define DMA_LISR_FEIF2 (1U << DMA_LISR_FEIF2_BIT) +#define DMA_LISR_TCIF1 (1U << DMA_LISR_TCIF1_BIT) +#define DMA_LISR_HTIF1 (1U << DMA_LISR_HTIF1_BIT) +#define DMA_LISR_TEIF1 (1U << DMA_LISR_TEIF1_BIT) +#define DMA_LISR_DMEIF1 (1U << DMA_LISR_DMEIF1_BIT) +#define DMA_LISR_FEIF1 (1U << DMA_LISR_FEIF1_BIT) +#define DMA_LISR_TCIF0 (1U << DMA_LISR_TCIF0_BIT) +#define DMA_LISR_HTIF0 (1U << DMA_LISR_HTIF0_BIT) +#define DMA_LISR_TEIF0 (1U << DMA_LISR_TEIF0_BIT) +#define DMA_LISR_DMEIF0 (1U << DMA_LISR_DMEIF0_BIT) +#define DMA_LISR_FEIF0 (1U << DMA_LISR_FEIF0_BIT) + +/* High interrupt status register */ + +#define DMA_HISR_TCIF7_BIT 27 +#define DMA_HISR_HTIF7_BIT 26 +#define DMA_HISR_TEIF7_BIT 25 +#define DMA_HISR_DMEIF7_BIT 24 +#define DMA_HISR_FEIF7_BIT 22 +#define DMA_HISR_TCIF6_BIT 21 +#define DMA_HISR_HTIF6_BIT 20 +#define DMA_HISR_TEIF6_BIT 19 +#define DMA_HISR_DMEIF6_BIT 18 +#define DMA_HISR_FEIF6_BIT 16 +#define DMA_HISR_TCIF5_BIT 11 +#define DMA_HISR_HTIF5_BIT 10 +#define DMA_HISR_TEIF5_BIT 9 +#define DMA_HISR_DMEIF5_BIT 8 +#define DMA_HISR_FEIF5_BIT 6 +#define DMA_HISR_TCIF4_BIT 5 +#define DMA_HISR_HTIF4_BIT 4 +#define DMA_HISR_TEIF4_BIT 3 +#define DMA_HISR_DMEIF4_BIT 2 +#define DMA_HISR_FEIF4_BIT 0 + +#define DMA_HISR_TCIF7 (1U << DMA_HISR_TCIF7_BIT) +#define DMA_HISR_HTIF7 (1U << DMA_HISR_HTIF7_BIT) +#define DMA_HISR_TEIF7 (1U << DMA_HISR_TEIF7_BIT) +#define DMA_HISR_DMEIF7 (1U << DMA_HISR_DMEIF7_BIT) +#define DMA_HISR_FEIF7 (1U << DMA_HISR_FEIF7_BIT) +#define DMA_HISR_TCIF6 (1U << DMA_HISR_TCIF6_BIT) +#define DMA_HISR_HTIF6 (1U << DMA_HISR_HTIF6_BIT) +#define DMA_HISR_TEIF6 (1U << DMA_HISR_TEIF6_BIT) +#define DMA_HISR_DMEIF6 (1U << DMA_HISR_DMEIF6_BIT) +#define DMA_HISR_FEIF6 (1U << DMA_HISR_FEIF6_BIT) +#define DMA_HISR_TCIF5 (1U << DMA_HISR_TCIF5_BIT) +#define DMA_HISR_HTIF5 (1U << DMA_HISR_HTIF5_BIT) +#define DMA_HISR_TEIF5 (1U << DMA_HISR_TEIF5_BIT) +#define DMA_HISR_DMEIF5 (1U << DMA_HISR_DMEIF5_BIT) +#define DMA_HISR_FEIF5 (1U << DMA_HISR_FEIF5_BIT) +#define DMA_HISR_TCIF4 (1U << DMA_HISR_TCIF4_BIT) +#define DMA_HISR_HTIF4 (1U << DMA_HISR_HTIF4_BIT) +#define DMA_HISR_TEIF4 (1U << DMA_HISR_TEIF4_BIT) +#define DMA_HISR_DMEIF4 (1U << DMA_HISR_DMEIF4_BIT) +#define DMA_HISR_FEIF4 (1U << DMA_HISR_FEIF4_BIT) + +/* Low interrupt flag clear register */ + +#define DMA_LIFCR_CTCIF3_BIT 27 +#define DMA_LIFCR_CHTIF3_BIT 26 +#define DMA_LIFCR_CTEIF3_BIT 25 +#define DMA_LIFCR_CDMEIF3_BIT 24 +#define DMA_LIFCR_CFEIF3_BIT 22 +#define DMA_LIFCR_CTCIF2_BIT 21 +#define DMA_LIFCR_CHTIF2_BIT 20 +#define DMA_LIFCR_CTEIF2_BIT 19 +#define DMA_LIFCR_CDMEIF2_BIT 18 +#define DMA_LIFCR_CFEIF2_BIT 16 +#define DMA_LIFCR_CTCIF1_BIT 11 +#define DMA_LIFCR_CHTIF1_BIT 10 +#define DMA_LIFCR_CTEIF1_BIT 9 +#define DMA_LIFCR_CDMEIF1_BIT 8 +#define DMA_LIFCR_CFEIF1_BIT 6 +#define DMA_LIFCR_CTCIF0_BIT 5 +#define DMA_LIFCR_CHTIF0_BIT 4 +#define DMA_LIFCR_CTEIF0_BIT 3 +#define DMA_LIFCR_CDMEIF0_BIT 2 +#define DMA_LIFCR_CFEIF0_BIT 0 + +#define DMA_LIFCR_CTCIF3 (1U << DMA_LIFCR_CTCIF3_BIT) +#define DMA_LIFCR_CHTIF3 (1U << DMA_LIFCR_CHTIF3_BIT) +#define DMA_LIFCR_CTEIF3 (1U << DMA_LIFCR_CTEIF3_BIT) +#define DMA_LIFCR_CDMEIF3 (1U << DMA_LIFCR_CDMEIF3_BIT) +#define DMA_LIFCR_CFEIF3 (1U << DMA_LIFCR_CFEIF3_BIT) +#define DMA_LIFCR_CTCIF2 (1U << DMA_LIFCR_CTCIF2_BIT) +#define DMA_LIFCR_CHTIF2 (1U << DMA_LIFCR_CHTIF2_BIT) +#define DMA_LIFCR_CTEIF2 (1U << DMA_LIFCR_CTEIF2_BIT) +#define DMA_LIFCR_CDMEIF2 (1U << DMA_LIFCR_CDMEIF2_BIT) +#define DMA_LIFCR_CFEIF2 (1U << DMA_LIFCR_CFEIF2_BIT) +#define DMA_LIFCR_CTCIF1 (1U << DMA_LIFCR_CTCIF1_BIT) +#define DMA_LIFCR_CHTIF1 (1U << DMA_LIFCR_CHTIF1_BIT) +#define DMA_LIFCR_CTEIF1 (1U << DMA_LIFCR_CTEIF1_BIT) +#define DMA_LIFCR_CDMEIF1 (1U << DMA_LIFCR_CDMEIF1_BIT) +#define DMA_LIFCR_CFEIF1 (1U << DMA_LIFCR_CFEIF1_BIT) +#define DMA_LIFCR_CTCIF0 (1U << DMA_LIFCR_CTCIF0_BIT) +#define DMA_LIFCR_CHTIF0 (1U << DMA_LIFCR_CHTIF0_BIT) +#define DMA_LIFCR_CTEIF0 (1U << DMA_LIFCR_CTEIF0_BIT) +#define DMA_LIFCR_CDMEIF0 (1U << DMA_LIFCR_CDMEIF0_BIT) +#define DMA_LIFCR_CFEIF0 (1U << DMA_LIFCR_CFEIF0_BIT) + +/* High interrupt flag clear regsister */ + +#define DMA_HIFCR_CTCIF7_BIT 27 +#define DMA_HIFCR_CHTIF7_BIT 26 +#define DMA_HIFCR_CTEIF7_BIT 25 +#define DMA_HIFCR_CDMEIF7_BIT 24 +#define DMA_HIFCR_CFEIF7_BIT 22 +#define DMA_HIFCR_CTCIF6_BIT 21 +#define DMA_HIFCR_CHTIF6_BIT 20 +#define DMA_HIFCR_CTEIF6_BIT 19 +#define DMA_HIFCR_CDMEIF6_BIT 18 +#define DMA_HIFCR_CFEIF6_BIT 16 +#define DMA_HIFCR_CTCIF5_BIT 11 +#define DMA_HIFCR_CHTIF5_BIT 10 +#define DMA_HIFCR_CTEIF5_BIT 9 +#define DMA_HIFCR_CDMEIF5_BIT 8 +#define DMA_HIFCR_CFEIF5_BIT 6 +#define DMA_HIFCR_CTCIF4_BIT 5 +#define DMA_HIFCR_CHTIF4_BIT 4 +#define DMA_HIFCR_CTEIF4_BIT 3 +#define DMA_HIFCR_CDMEIF4_BIT 2 +#define DMA_HIFCR_CFEIF4_BIT 0 + +#define DMA_HIFCR_CTCIF7 (1U << DMA_HIFCR_CTCIF7_BIT) +#define DMA_HIFCR_CHTIF7 (1U << DMA_HIFCR_CHTIF7_BIT) +#define DMA_HIFCR_CTEIF7 (1U << DMA_HIFCR_CTEIF7_BIT) +#define DMA_HIFCR_CDMEIF7 (1U << DMA_HIFCR_CDMEIF7_BIT) +#define DMA_HIFCR_CFEIF7 (1U << DMA_HIFCR_CFEIF7_BIT) +#define DMA_HIFCR_CTCIF6 (1U << DMA_HIFCR_CTCIF6_BIT) +#define DMA_HIFCR_CHTIF6 (1U << DMA_HIFCR_CHTIF6_BIT) +#define DMA_HIFCR_CTEIF6 (1U << DMA_HIFCR_CTEIF6_BIT) +#define DMA_HIFCR_CDMEIF6 (1U << DMA_HIFCR_CDMEIF6_BIT) +#define DMA_HIFCR_CFEIF6 (1U << DMA_HIFCR_CFEIF6_BIT) +#define DMA_HIFCR_CTCIF5 (1U << DMA_HIFCR_CTCIF5_BIT) +#define DMA_HIFCR_CHTIF5 (1U << DMA_HIFCR_CHTIF5_BIT) +#define DMA_HIFCR_CTEIF5 (1U << DMA_HIFCR_CTEIF5_BIT) +#define DMA_HIFCR_CDMEIF5 (1U << DMA_HIFCR_CDMEIF5_BIT) +#define DMA_HIFCR_CFEIF5 (1U << DMA_HIFCR_CFEIF5_BIT) +#define DMA_HIFCR_CTCIF4 (1U << DMA_HIFCR_CTCIF4_BIT) +#define DMA_HIFCR_CHTIF4 (1U << DMA_HIFCR_CHTIF4_BIT) +#define DMA_HIFCR_CTEIF4 (1U << DMA_HIFCR_CTEIF4_BIT) +#define DMA_HIFCR_CDMEIF4 (1U << DMA_HIFCR_CDMEIF4_BIT) +#define DMA_HIFCR_CFEIF4 (1U << DMA_HIFCR_CFEIF4_BIT) + +/* Stream configuration register */ + +#define DMA_SCR_CT_BIT 19 +#define DMA_SCR_DBM_BIT 18 +#define DMA_SCR_PINCOS_BIT 15 +#define DMA_SCR_MINC_BIT 10 +#define DMA_SCR_PINC_BIT 9 +#define DMA_SCR_CIRC_BIT 8 +#define DMA_SCR_PFCTRL_BIT 5 +#define DMA_SCR_TCIE_BIT 4 +#define DMA_SCR_HTIE_BIT 3 +#define DMA_SCR_TEIE_BIT 2 +#define DMA_SCR_DMEIE_BIT 1 +#define DMA_SCR_EN_BIT 0 + +#define DMA_SCR_CHSEL (0x7 << 25) +#define DMA_SCR_CHSEL_CH_0 (0x0 << 25) +#define DMA_SCR_CHSEL_CH_1 (0x1 << 25) +#define DMA_SCR_CHSEL_CH_2 (0x2 << 25) +#define DMA_SCR_CHSEL_CH_3 (0x3 << 25) +#define DMA_SCR_CHSEL_CH_4 (0x4 << 25) +#define DMA_SCR_CHSEL_CH_5 (0x5 << 25) +#define DMA_SCR_CHSEL_CH_6 (0x6 << 25) +#define DMA_SCR_CHSEL_CH_7 (0x7 << 25) +#define DMA_SCR_MBURST (0x3 << 23) +#define DMA_SCR_MBURST_SINGLE (0x0 << 23) +#define DMA_SCR_MBURST_INCR4 (0x1 << 23) +#define DMA_SCR_MBURST_INCR8 (0x2 << 23) +#define DMA_SCR_MBURST_INCR16 (0x3 << 23) +#define DMA_SCR_PBURST (0x3 << 21) +#define DMA_SCR_PBURST_SINGLE (0x0 << 21) +#define DMA_SCR_PBURST_INCR4 (0x1 << 21) +#define DMA_SCR_PBURST_INCR8 (0x2 << 21) +#define DMA_SCR_PBURST_INCR16 (0x3 << 21) +#define DMA_SCR_CT (1U << DMA_SCR_CT_BIT) +#define DMA_SCR_DBM (1U << DMA_SCR_DBM_BIT) +#define DMA_SCR_PL (0x3 << 16) +#define DMA_SCR_PL_LOW (0x0 << 16) +#define DMA_SCR_PL_MEDIUM (0x1 << 16) +#define DMA_SCR_PL_HIGH (0x2 << 16) +#define DMA_SCR_VERY_HIGH (0x3 << 16) +#define DMA_SCR_PINCOS (1U << DMA_SCR_PINCOS_BIT) +#define DMA_SCR_MSIZE (0x3 << 13) +#define DMA_SCR_MSIZE_8BITS (0x0 << 13) +#define DMA_SCR_MSIZE_16BITS (0x1 << 13) +#define DMA_SCR_MSIZE_32BITS (0x2 << 13) +#define DMA_SCR_PSIZE (0x3 << 11) +#define DMA_SCR_PSIZE_8BITS (0x0 << 11) +#define DMA_SCR_PSIZE_16BITS (0x1 << 11) +#define DMA_SCR_PSIZE_32BITS (0x2 << 11) +#define DMA_SCR_MINC (1U << DMA_SCR_MINC_BIT) +#define DMA_SCR_PINC (1U << DMA_SCR_PINC_BIT) +#define DMA_SCR_CIRC (1U << DMA_SCR_CIRC_BIT) +#define DMA_SCR_DIR (0x3 << 6) +#define DMA_SCR_DIR_PER_TO_MEM (0x0 << 6) +#define DMA_SCR_DIR_MEM_TO_PER (0x1 << 6) +#define DMA_SCR_DIR_MEM_TO_MEM (0x2 << 6) +#define DMA_SCR_PFCTRL (1U << DMA_SCR_PFCTRL_BIT) +#define DMA_SCR_TCIE (1U << DMA_SCR_TCIE_BIT) +#define DMA_SCR_HTIE (1U << DMA_SCR_HTIE_BIT) +#define DMA_SCR_TEIE (1U << DMA_SCR_TEIE_BIT) +#define DMA_SCR_DMEIE (1U << DMA_SCR_DMEIE_BIT) +#define DMA_SCR_EN (1U << DMA_SCR_EN_BIT) + +/* Stream FIFO control register */ + +#define DMA_SFCR_FEIE_BIT 7 +#define DMA_SFCR_DMDIS_BIT 2 + +#define DMA_SFCR_FEIE (1U << DMA_SFCR_FEIE_BIT) +#define DMA_SFCR_FS (0x7 << 3) +#define DMA_SFCR_FS_ZERO_TO_QUARTER (0x0 << 3) +#define DMA_SFCR_FS_QUARTER_TO_HALF (0x1 << 3) +#define DMA_SFCR_FS_HALF_TO_THREE_QUARTERS (0x2 << 3) +#define DMA_SFCR_FS_THREE_QUARTERS_TO_FULL (0x3 << 3) +#define DMA_SFCR_FS_EMPTY (0x4 << 3) +#define DMA_SFCR_FS_FULL (0x5 << 3) +#define DMA_SFCR_DMDIS (1U << DMA_SFCR_DMDIS_BIT) +#define DMA_SFCR_FTH (0x3 << 0) +#define DMA_SFCR_FTH_QUARTER_FULL (0x0 << 3) +#define DMA_SFCR_FTH_HALF_FULL (0x1 << 3) +#define DMA_SFCR_FTH_THREE_QUARTERS_FULL (0x2 << 3) +#define DMA_SFCR_FTH_FULL (0x3 << 3) + +/* + * Devices + */ + +extern dma_dev *DMA1; +extern dma_dev *DMA2; + +/* + * Other types needed by, or useful for, + */ + +/** + * @brief DMA streams + * This is also the dma_tube type for STM32F2. + * @see dma_tube + */ +typedef enum dma_stream { + DMA_S0 = 0, + DMA_S1 = 1, + DMA_S2 = 2, + DMA_S3 = 3, + DMA_S4 = 4, + DMA_S5 = 5, + DMA_S6 = 6, + DMA_S7 = 7, +} dma_stream; + +/** STM32F2 dma_tube (=dma_stream) */ +#define dma_tube dma_stream + +/** + * @brief STM32F2 configuration flags for dma_tube_config. + * @see struct dma_tube_config + */ +typedef enum dma_cfg_flags { + /* NB: flags that aren't SCR bits are treated specially. */ + + /** + * Source address increment mode + * + * If this flag is set, the source address is incremented (by the + * source size) after each DMA transfer. + */ + DMA_CFG_SRC_INC = 1U << 31, + + /** + * Destination address increment mode + * + * If this flag is set, the destination address is incremented (by + * the destination size) after each DMA transfer. + */ + DMA_CFG_DST_INC = 1U << 30, + + /** + * Circular mode + * + * This mode is not available for memory-to-memory transfers. + */ + DMA_CFG_CIRC = DMA_SCR_CIRC, + + /** Transfer complete interrupt enable */ + DMA_CFG_CMPLT_IE = DMA_SCR_TCIE, + /** Transfer half-complete interrupt enable */ + DMA_CFG_HALF_CMPLT_IE = DMA_SCR_HTIE, + /** Transfer error interrupt enable */ + DMA_CFG_ERR_IE = DMA_SCR_TEIE, + /** Direct mode error interrupt enable */ + DMA_CFG_DM_ERR_IE = DMA_SCR_DMEIE, + /** FIFO error interrupt enable */ + DMA_CFG_FIFO_ERR_IE = (1U << 29), +} dma_cfg_flags; + +/** + * @brief STM32F2 DMA request sources. + * + * IMPORTANT: + * + * 1. On STM32F2, a particular dma_request_src is always tied to a + * single DMA controller, but often can be supported by multiple + * streams. For example, DMA requests from ADC1 (DMA_REQ_SRC_ADC1) can + * only be handled by DMA2, but they can go to either stream 0 or + * stream 4 (though not any other stream). If you try to use a request + * source with the wrong DMA controller or the wrong stream on + * STM32F2, dma_tube_cfg() will fail. + * + * 2. A single stream can only handle a single request source at a + * time. If you change a stream's request source later, it will stop + * serving requests from the old source. However, for some streams, + * some sources conflict with one another (when they correspond to the + * same channel on that stream), and on STM32F2, Terrible Super-Bad + * Things will happen if two conflicting request sources are active at + * the same time. + * + * @see struct dma_tube_config + * @see dma_tube_cfg() + */ +typedef enum dma_request_src { + /* These are constructed like so (though this may change, so user + * code shouldn't depend on it): + * + * Bits 0--2: Channel associated with request source + * + * Bits 3--9: rcc_clk_id of DMA controller associated with request source + * + * Bits 10--17: Bit mask of streams which can handle that request + * source. (E.g., bit 10 set means stream 0 can + * handle the source, bit 11 set means stream 1 can, + * etc.) + * + * Among other things, this is used for error checking in + * dma_tube_cfg(). If you change this bit encoding, you need to + * update the helper functions in stm32f2/dma.c. + */ +#define _DMA_STM32F2_REQ_SRC(stream_mask, clk_id, channel) \ + (((stream_mask) << 10) | ((clk_id) << 3) | (channel)) +#define _DMA_S(n) (1U << (n)) + + /* DMA1 request sources */ +#define _DMA_1_REQ_SRC(stream_mask, channel) \ + _DMA_STM32F2_REQ_SRC(stream_mask, RCC_DMA1, channel) + + /* Channel 0 */ + DMA_REQ_SRC_SPI3_RX = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(2), 0), + DMA_REQ_SRC_SPI2_RX = _DMA_1_REQ_SRC(_DMA_S(3), 0), + DMA_REQ_SRC_SPI2_TX = _DMA_1_REQ_SRC(_DMA_S(4), 0), + DMA_REQ_SRC_SPI3_TX = _DMA_1_REQ_SRC(_DMA_S(5) | _DMA_S(7), 0), + + /* Channel 1 */ + DMA_REQ_SRC_I2C1_RX = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(5), 1), + DMA_REQ_SRC_TIM7_UP = _DMA_1_REQ_SRC(_DMA_S(2) | _DMA_S(4), 1), + DMA_REQ_SRC_I2C1_TX = _DMA_1_REQ_SRC(_DMA_S(6) | _DMA_S(7), 1), + + /* Channel 2 */ + DMA_REQ_SRC_TIM4_CH1 = _DMA_1_REQ_SRC(_DMA_S(0), 2), + DMA_REQ_SRC_TIM4_CH2 = _DMA_1_REQ_SRC(_DMA_S(3), 2), + DMA_REQ_SRC_TIM4_UP = _DMA_1_REQ_SRC(_DMA_S(6), 2), + DMA_REQ_SRC_TIM4_CH3 = _DMA_1_REQ_SRC(_DMA_S(7), 2), + + /* Channel 3 */ + DMA_REQ_SRC_TIM2_UP = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(7), 3), + DMA_REQ_SRC_TIM2_CH3 = _DMA_1_REQ_SRC(_DMA_S(1), 3), + DMA_REQ_SRC_I2C3_RX = _DMA_1_REQ_SRC(_DMA_S(2), 3), + DMA_REQ_SRC_I2C3_TX = _DMA_1_REQ_SRC(_DMA_S(4), 3), + DMA_REQ_SRC_TIM2_CH1 = _DMA_1_REQ_SRC(_DMA_S(5), 3), + DMA_REQ_SRC_TIM2_CH2 = _DMA_1_REQ_SRC(_DMA_S(6), 3), + DMA_REQ_SRC_TIM2_CH4 = _DMA_1_REQ_SRC(_DMA_S(6) | _DMA_S(7), 3), + + /* Channel 4 */ + DMA_REQ_SRC_UART5_RX = _DMA_1_REQ_SRC(_DMA_S(0), 4), + DMA_REQ_SRC_USART3_RX = _DMA_1_REQ_SRC(_DMA_S(1), 4), + DMA_REQ_SRC_UART4_RX = _DMA_1_REQ_SRC(_DMA_S(2), 4), + DMA_REQ_SRC_USART3_TX = _DMA_1_REQ_SRC(_DMA_S(3), 4), + DMA_REQ_SRC_UART4_TX = _DMA_1_REQ_SRC(_DMA_S(4), 4), + DMA_REQ_SRC_USART2_RX = _DMA_1_REQ_SRC(_DMA_S(5), 4), + DMA_REQ_SRC_USART2_TX = _DMA_1_REQ_SRC(_DMA_S(6), 4), + DMA_REQ_SRC_UART5_TX = _DMA_1_REQ_SRC(_DMA_S(7), 4), + + /* Channel 5 */ + DMA_REQ_SRC_TIM3_CH4 = _DMA_1_REQ_SRC(_DMA_S(2), 5), + DMA_REQ_SRC_TIM3_UP = _DMA_1_REQ_SRC(_DMA_S(2), 5), + DMA_REQ_SRC_TIM3_CH1 = _DMA_1_REQ_SRC(_DMA_S(4), 5), + DMA_REQ_SRC_TIM3_TRIG = _DMA_1_REQ_SRC(_DMA_S(4), 5), + DMA_REQ_SRC_TIM3_CH2 = _DMA_1_REQ_SRC(_DMA_S(5), 5), + DMA_REQ_SRC_TIM3_CH3 = _DMA_1_REQ_SRC(_DMA_S(7), 5), + + /* Channel 6 */ + DMA_REQ_SRC_TIM5_CH3 = _DMA_1_REQ_SRC(_DMA_S(0), 6), + DMA_REQ_SRC_TIM5_UP = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(6), 6), + DMA_REQ_SRC_TIM5_CH4 = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6), + DMA_REQ_SRC_TIM5_TRIG = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6), + DMA_REQ_SRC_TIM5_CH1 = _DMA_1_REQ_SRC(_DMA_S(2), 6), + DMA_REQ_SRC_TIM5_CH2 = _DMA_1_REQ_SRC(_DMA_S(4), 6), + + /* Channel 7 */ + DMA_REQ_SRC_TIM6_UP = _DMA_1_REQ_SRC(_DMA_S(1), 7), + DMA_REQ_SRC_I2C2_RX = _DMA_1_REQ_SRC(_DMA_S(2) | _DMA_S(3), 7), + DMA_REQ_SRC_USART3_TX_ALTERNATE = _DMA_1_REQ_SRC(_DMA_S(4), 7), + DMA_REQ_SRC_DAC1 = _DMA_1_REQ_SRC(_DMA_S(5), 7), + DMA_REQ_SRC_DAC2 = _DMA_1_REQ_SRC(_DMA_S(6), 7), + DMA_REQ_SRC_I2C2_TX = _DMA_1_REQ_SRC(_DMA_S(7), 7), +#undef _DMA_1_REQ_SRC + + /* DMA2 request sources */ +#define _DMA_2_REQ_SRC(stream_mask, channel) \ + _DMA_STM32F2_REQ_SRC(stream_mask, RCC_DMA2, channel) + + /* Channel 0 */ + DMA_REQ_SRC_ADC1 = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(4), 0), + /* You can use these "DMA_REQ_SRC_TIMx_CHx_ALTERNATE" if you know + * what you're doing, but the other ones (for channels 6 and 7), + * are better, in that they don't conflict with one another. */ + DMA_REQ_SRC_TIM8_CH1_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0), + DMA_REQ_SRC_TIM8_CH2_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0), + DMA_REQ_SRC_TIM8_CH3_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0), + DMA_REQ_SRC_TIM1_CH1_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(6), 0), + DMA_REQ_SRC_TIM1_CH2_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(6), 0), + DMA_REQ_SRC_TIM1_CH3_ALTENRATE = _DMA_2_REQ_SRC(_DMA_S(6), 0), + + /* Channel 1 */ + DMA_REQ_SRC_DCMI = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(7), 1), + DMA_REQ_SRC_ADC2 = _DMA_2_REQ_SRC(_DMA_S(2) | _DMA_S(3), 1), + + /* Channel 2 */ + DMA_REQ_SRC_ADC3 = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(1), 2), + DMA_REQ_SRC_CRYP_OUT = _DMA_2_REQ_SRC(_DMA_S(5), 2), + DMA_REQ_SRC_CRYP_IN = _DMA_2_REQ_SRC(_DMA_S(6), 2), + DMA_REQ_SRC_HASH_IN = _DMA_2_REQ_SRC(_DMA_S(7), 2), + + /* Channel 3 */ + DMA_REQ_SRC_SPI1_RX = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(2), 3), + DMA_REQ_SRC_SPI1_TX = _DMA_2_REQ_SRC(_DMA_S(3) | _DMA_S(5), 3), + + /* Channel 4 */ + DMA_REQ_SRC_USART1_RX = _DMA_2_REQ_SRC(_DMA_S(2) | _DMA_S(5), 4), + DMA_REQ_SRC_SDIO = _DMA_2_REQ_SRC(_DMA_S(3) | _DMA_S(6), 4), + DMA_REQ_SRC_USART1_TX = _DMA_2_REQ_SRC(_DMA_S(7), 4), + + /* Channel 5 */ + DMA_REQ_SRC_USART6_RX = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(2), 5), + DMA_REQ_SRC_USART6_TX = _DMA_2_REQ_SRC(_DMA_S(6) | _DMA_S(7), 5), + + /* Channel 6 */ + DMA_REQ_SRC_TIM1_TRIG = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(4), 6), + DMA_REQ_SRC_TIM1_CH1 = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6), + DMA_REQ_SRC_TIM1_CH2 = _DMA_2_REQ_SRC(_DMA_S(3), 6), + DMA_REQ_SRC_TIM1_CH4 = _DMA_2_REQ_SRC(_DMA_S(4), 6), + DMA_REQ_SRC_TIM1_COM = _DMA_2_REQ_SRC(_DMA_S(4), 6), + DMA_REQ_SRC_TIM1_UP = _DMA_2_REQ_SRC(_DMA_S(5), 6), + DMA_REQ_SRC_TIM1_CH3 = _DMA_2_REQ_SRC(_DMA_S(6), 6), + + /* Channel 7 */ + DMA_REQ_SRC_TIM8_UP = _DMA_2_REQ_SRC(_DMA_S(1), 7), + DMA_REQ_SRC_TIM8_CH1 = _DMA_2_REQ_SRC(_DMA_S(2), 7), + DMA_REQ_SRC_TIM8_CH2 = _DMA_2_REQ_SRC(_DMA_S(3), 7), + DMA_REQ_SRC_TIM8_CH3 = _DMA_2_REQ_SRC(_DMA_S(4), 7), + DMA_REQ_SRC_TIM8_CH4 = _DMA_2_REQ_SRC(_DMA_S(7), 7), + DMA_REQ_SRC_TIM8_TRIG = _DMA_2_REQ_SRC(_DMA_S(7), 7), + DMA_REQ_SRC_TIM8_COM = _DMA_2_REQ_SRC(_DMA_S(7), 7), +#undef _DMA_2_REQ_SRC +#undef _DMA_S +} dma_request_src; + +/* + * Tube conveniences + */ + +static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, + dma_tube tube) { + ASSERT(DMA_S0 <= tube && tube <= DMA_S7); + switch (dev->clk_id) { + case RCC_DMA1: + return DMA1S0_BASE + (int)tube; + case RCC_DMA2: + return DMA2S0_BASE + (int)tube; + default: + /* Can't happen */ + ASSERT(0); + return 0; + } +} + +static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) { + return dma_tube_regs(dev, tube)->SCR & DMA_SCR_EN; +} + +/* F2-only; available because of double-buffering. */ +void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n, + __io void *address); + +/** + * @brief Set memory 0 address. + * Availability: STM32F2. + * + * @param dev DMA device + * @param tube Tube whose memory 0 address to set + * @param addr Address to use as memory 0 + */ +static __always_inline void +dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) { + dma_set_mem_n_addr(dev, tube, 0, addr); +} + +/** + * @brief Set memory 1 address. + * Availability: STM32F2. + * + * @param dev DMA device + * @param tube Tube whose memory 1 address to set + * @param addr Address to use as memory 1 + */ +static __always_inline void +dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) { + dma_set_mem_n_addr(dev, tube, 1, addr); +} + +/* Assume the user means SM0AR in a non-double-buffered configuration. */ +static __always_inline void +dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) { + dma_set_mem0_addr(dev, tube, addr); +} + +/* SM0AR and SM1AR are treated as though they have the same size */ +static inline dma_xfer_size dma_get_mem_size(dma_dev *dev, dma_tube tube) { + return (dma_xfer_size)(dma_tube_regs(dev, tube)->SCR >> 13); +} + +static inline dma_xfer_size dma_get_per_size(dma_dev *dev, dma_tube tube) { + return (dma_xfer_size)(dma_tube_regs(dev, tube)->SCR >> 11); +} + +void dma_enable_fifo(dma_dev *dev, dma_tube tube); +void dma_disable_fifo(dma_dev *dev, dma_tube tube); + +static __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) { + return dma_tube_regs(dev, tube)->SFCR & DMA_SFCR_DMDIS; +} + +/* + * TODO: + * - Double-buffer configuration function + * - FIFO configuration function + * - MBURST/PBURST configuration function + */ + +/* + * ISR/IFCR conveniences. + */ + +/* (undocumented) helper for reading LISR/HISR and writing + * LIFCR/HIFCR. For these registers, + * + * S0, S4: bits start at bit 0 + * S1, S5: 6 + * S2, S6: 16 + * S3, S7: 22 + * + * I can't imagine why ST didn't just use a byte for each group. The + * bits fit, and it would have made functions like these simpler and + * faster. Oh well. */ +static __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) { + switch (tube) { + case DMA_S0: /* fall through */ + case DMA_S4: + return 0; + case DMA_S1: /* fall through */ + case DMA_S5: + return 6; + case DMA_S2: /* fall through */ + case DMA_S6: + return 16; + case DMA_S3: /* fall through */ + case DMA_S7: + return 22; + } + /* Can't happen */ + ASSERT(0); + return 0; +} + +static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) { + dma_reg_map *regs = dev->regs; + __io uint32 *isr = tube > DMA_S3 ? ®s->HISR : ®s->LISR; + return (*isr >> _dma_sr_fcr_shift(tube)) & 0x3D; +} + +static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) { + dma_reg_map *regs = dev->regs; + __io uint32 *ifcr = tube > DMA_S3 ? ®s->HIFCR : ®s->LIFCR; + *ifcr = (0x3D << _dma_sr_fcr_shift(tube)); +} + +#undef _DMA_IRQ_BIT_SHIFT + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/libmaple/stm32f2/rules.mk b/libmaple/stm32f2/rules.mk index 759f905..4c62cc2 100644 --- a/libmaple/stm32f2/rules.mk +++ b/libmaple/stm32f2/rules.mk @@ -12,6 +12,7 @@ sSRCS_$(d) := isrs.S sSRCS_$(d) += vector_table.S cSRCS_$(d) := adc.c +cSRCS_$(d) += dma.c cSRCS_$(d) += exti.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c -- cgit v1.2.3 From c5b954a8670abe277daa06f4eea2b48d761e3175 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 14 Jun 2012 18:32:01 -0400 Subject: Port test-usart-dma.cpp for STM32F2. Too ugly? Meh. Signed-off-by: Marti Bolivar --- examples/test-usart-dma.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/examples/test-usart-dma.cpp b/examples/test-usart-dma.cpp index 04117c3..d10dc68 100644 --- a/examples/test-usart-dma.cpp +++ b/examples/test-usart-dma.cpp @@ -35,9 +35,18 @@ // your purposes. HardwareSerial *serial = &Serial2; #define USART_DMA_DEV DMA1 +#if STM32_MCU_SERIES == STM32_SERIES_F1 // On STM32F1 microcontrollers (like what's on Maple and Maple Mini), // dma tubes are channels. #define USART_RX_DMA_TUBE DMA_CH6 +#elif (STM32_MCU_SERIES == STM32_SERIES_F2 || \ + STM32_MCU_SERIES == STM32_SERIES_F4) +// On STM32F2 and STM32F4 microcontrollers (Maple 2 will have an F4), +// dma tubes are streams. +#define USART_RX_DMA_TUBE DMA_S5 +#else +#error "unsupported stm32 series" +#endif // The serial port will make a DMA request each time it receives data. // This is the dma_request_src we use to tell the DMA tube to handle // that DMA request. -- cgit v1.2.3 From bd5719db16f05dcc41ca1e148b07ed4837525104 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 23:16:35 -0400 Subject: : Assert LeafLabs copyright. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/dma.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/include/libmaple/dma.h b/libmaple/include/libmaple/dma.h index 0ef495a..0b1ec4c 100644 --- a/libmaple/include/libmaple/dma.h +++ b/libmaple/include/libmaple/dma.h @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Michael Hope. + * Copyright (c) 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation -- cgit v1.2.3 From 1a4ac9190b22da2477b759a0a402dfed0811ca30 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 15:25:00 -0400 Subject: libmaple/i2c.h: Don't use BIT(). Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 80 ++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index ffd0cfb..c77bd32 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -117,56 +117,56 @@ extern i2c_dev* const I2C2; /* Control register 1 */ -#define I2C_CR1_SWRST BIT(15) // Software reset -#define I2C_CR1_ALERT BIT(13) // SMBus alert -#define I2C_CR1_PEC BIT(12) // Packet error checking -#define I2C_CR1_POS BIT(11) // Acknowledge/PEC position -#define I2C_CR1_ACK BIT(10) // Acknowledge enable -#define I2C_CR1_START BIT(8) // Start generation -#define I2C_CR1_STOP BIT(9) // Stop generation -#define I2C_CR1_PE BIT(0) // Peripheral Enable +#define I2C_CR1_SWRST (1U << 15) // Software reset +#define I2C_CR1_ALERT (1U << 13) // SMBus alert +#define I2C_CR1_PEC (1U << 12) // Packet error checking +#define I2C_CR1_POS (1U << 11) // Acknowledge/PEC position +#define I2C_CR1_ACK (1U << 10) // Acknowledge enable +#define I2C_CR1_START (1U << 8) // Start generation +#define I2C_CR1_STOP (1U << 9) // Stop generation +#define I2C_CR1_PE (1U << 0) // Peripheral Enable /* Control register 2 */ -#define I2C_CR2_LAST BIT(12) // DMA last transfer -#define I2C_CR2_DMAEN BIT(11) // DMA requests enable -#define I2C_CR2_ITBUFEN BIT(10) // Buffer interrupt enable -#define I2C_CR2_ITEVTEN BIT(9) // Event interupt enable -#define I2C_CR2_ITERREN BIT(8) // Error interupt enable +#define I2C_CR2_LAST (1U << 12) // DMA last transfer +#define I2C_CR2_DMAEN (1U << 11) // DMA requests enable +#define I2C_CR2_ITBUFEN (1U << 10) // Buffer interrupt enable +#define I2C_CR2_ITEVTEN (1U << 9) // Event interupt enable +#define I2C_CR2_ITERREN (1U << 8) // Error interupt enable #define I2C_CR2_FREQ 0xFFF // Peripheral input frequency /* Clock control register */ -#define I2C_CCR_FS BIT(15) // Fast mode selection -#define I2C_CCR_DUTY BIT(14) // 16/9 duty ratio +#define I2C_CCR_FS (1U << 15) // Fast mode selection +#define I2C_CCR_DUTY (1U << 14) // 16/9 duty ratio #define I2C_CCR_CCR 0xFFF // Clock control bits /* Status register 1 */ -#define I2C_SR1_SB BIT(0) // Start bit -#define I2C_SR1_ADDR BIT(1) // Address sent/matched -#define I2C_SR1_BTF BIT(2) // Byte transfer finished -#define I2C_SR1_ADD10 BIT(3) // 10-bit header sent -#define I2C_SR1_STOPF BIT(4) // Stop detection -#define I2C_SR1_RXNE BIT(6) // Data register not empty -#define I2C_SR1_TXE BIT(7) // Data register empty -#define I2C_SR1_BERR BIT(8) // Bus error -#define I2C_SR1_ARLO BIT(9) // Arbitration lost -#define I2C_SR1_AF BIT(10) // Acknowledge failure -#define I2C_SR1_OVR BIT(11) // Overrun/underrun -#define I2C_SR1_PECERR BIT(12) // PEC Error in reception -#define I2C_SR1_TIMEOUT BIT(14) // Timeout or Tlow error -#define I2C_SR1_SMBALERT BIT(15) // SMBus alert +#define I2C_SR1_SB (1U << 0) // Start bit +#define I2C_SR1_ADDR (1U << 1) // Address sent/matched +#define I2C_SR1_BTF (1U << 2) // Byte transfer finished +#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent +#define I2C_SR1_STOPF (1U << 4) // Stop detection +#define I2C_SR1_RXNE (1U << 6) // Data register not empty +#define I2C_SR1_TXE (1U << 7) // Data register empty +#define I2C_SR1_BERR (1U << 8) // Bus error +#define I2C_SR1_ARLO (1U << 9) // Arbitration lost +#define I2C_SR1_AF (1U << 10) // Acknowledge failure +#define I2C_SR1_OVR (1U << 11) // Overrun/underrun +#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception +#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error +#define I2C_SR1_SMBALERT (1U << 15) // SMBus alert /* Status register 2 */ -#define I2C_SR2_MSL BIT(0) // Master/slave -#define I2C_SR2_BUSY BIT(1) // Bus busy -#define I2C_SR2_TRA BIT(2) // Transmitter/receiver -#define I2C_SR2_GENCALL BIT(4) // General call address -#define I2C_SR2_SMBDEFAULT BIT(5) // SMBus device default address -#define I2C_SR2_SMBHOST BIT(6) // SMBus host header -#define I2C_SR2_DUALF BIT(7) // Dual flag +#define I2C_SR2_MSL (1U << 0) // Master/slave +#define I2C_SR2_BUSY (1U << 1) // Bus busy +#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver +#define I2C_SR2_GENCALL (1U << 4) // General call address +#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address +#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header +#define I2C_SR2_DUALF (1U << 7) // Dual flag #define I2C_SR2_PEC 0xFF00 // Packet error checking register /* @@ -176,10 +176,10 @@ extern i2c_dev* const I2C2; void i2c_init(i2c_dev *dev); /* I2C enable options */ -#define I2C_FAST_MODE BIT(0) // 400 khz -#define I2C_DUTY_16_9 BIT(1) // 16/9 duty ratio -#define I2C_REMAP BIT(2) // Use alternate pin mapping -#define I2C_BUS_RESET BIT(3) // Perform a bus reset +#define I2C_FAST_MODE 0x1 // 400 khz +#define I2C_DUTY_16_9 0x2 // 16/9 duty ratio +#define I2C_REMAP 0x4 // Use alternate pin mapping +#define I2C_BUS_RESET 0x8 // Perform a bus reset void i2c_master_enable(i2c_dev *dev, uint32 flags); #define I2C_ERROR_PROTOCOL (-1) -- cgit v1.2.3 From 411c66ef48cafab8458d158ae8da4192044e46e7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 15:29:59 -0400 Subject: libmaple/i2c.h: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index c77bd32..4603837 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -122,8 +122,8 @@ extern i2c_dev* const I2C2; #define I2C_CR1_PEC (1U << 12) // Packet error checking #define I2C_CR1_POS (1U << 11) // Acknowledge/PEC position #define I2C_CR1_ACK (1U << 10) // Acknowledge enable -#define I2C_CR1_START (1U << 8) // Start generation #define I2C_CR1_STOP (1U << 9) // Stop generation +#define I2C_CR1_START (1U << 8) // Start generation #define I2C_CR1_PE (1U << 0) // Peripheral Enable /* Control register 2 */ -- cgit v1.2.3 From 68f35527c43001ceff27b9ec6f35e3be339742ca Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 15:33:30 -0400 Subject: Fix I2C_CR2_FREQ bit definition. The existing value clobbers the entire register. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 4603837..8c5ab06 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -133,7 +133,7 @@ extern i2c_dev* const I2C2; #define I2C_CR2_ITBUFEN (1U << 10) // Buffer interrupt enable #define I2C_CR2_ITEVTEN (1U << 9) // Event interupt enable #define I2C_CR2_ITERREN (1U << 8) // Error interupt enable -#define I2C_CR2_FREQ 0xFFF // Peripheral input frequency +#define I2C_CR2_FREQ 0x3F // Peripheral input frequency /* Clock control register */ -- cgit v1.2.3 From 156b6f1d61ab3985ee8abd4c51aeca3caa4ecb35 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 15:34:18 -0400 Subject: libmaple/i2c.h: Assert LeafLabs copyright. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 8c5ab06..217bead 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation -- cgit v1.2.3 From fb683bcc19e48e33c9f9310d2debb8d9e51496db Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 17:26:52 -0400 Subject: : Add missing register bit defns. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 217bead..26a0b65 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -125,6 +125,16 @@ extern i2c_dev* const I2C2; #define I2C_CR1_ACK (1U << 10) // Acknowledge enable #define I2C_CR1_STOP (1U << 9) // Stop generation #define I2C_CR1_START (1U << 8) // Start generation +#define I2C_CR1_NOSTRETCH (1U << 7) // Clock stretching disable +#define I2C_CR1_ENGC (1U << 6) // General call enable +#define I2C_CR1_ENPEC (1U << 5) // PEC enable +#define I2C_CR1_ENARP (1U << 4) // ARP enable +#define I2C_CR1_SMBTYPE (1U << 3) // SMBus type +#define I2C_CR1_SMBTYPE_DEVICE (0U << 3) // SMBus type: device +#define I2C_CR1_SMBTYPE_HOST (1U << 3) // SMBus type: host +#define I2C_CR1_SMBUS (1U << 1) // SMBus mode +#define I2C_CR1_SMBUS_I2C (0U << 1) // SMBus mode: I2C +#define I2C_CR1_SMBUS_SMBUS (1U << 1) // SMBus mode: SMBus #define I2C_CR1_PE (1U << 0) // Peripheral Enable /* Control register 2 */ @@ -136,6 +146,18 @@ extern i2c_dev* const I2C2; #define I2C_CR2_ITERREN (1U << 8) // Error interupt enable #define I2C_CR2_FREQ 0x3F // Peripheral input frequency +/* Own address register 1 */ + +#define I2C_OAR1_ADDMODE (1U << 15) // Addressing mode +#define I2C_OAR1_ADDMODE_7_BIT (0U << 15) // Addressing mode: 7-bit +#define I2C_OAR1_ADDMODE_10_BIT (1U << 15) // Addressing mode: 10-bit +#define I2C_OAR1_ADD 0x3FF // Interface address + +/* Own address register 2 */ + +#define I2C_OAR2_ADD2 0xFE // Interface address +#define I2C_OAR2_ENDUAL 1U // Dual addressing mode enable + /* Clock control register */ #define I2C_CCR_FS (1U << 15) // Fast mode selection -- cgit v1.2.3 From e9574e9c9bc91a8213d1292c8fcab8a7a93aeb2b Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 17:29:10 -0400 Subject: : Cosmetics. Reorder register bit definitions by descending bit number, for consistency with the rest of the library. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 26a0b65..f27f8eb 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -166,31 +166,31 @@ extern i2c_dev* const I2C2; /* Status register 1 */ -#define I2C_SR1_SB (1U << 0) // Start bit -#define I2C_SR1_ADDR (1U << 1) // Address sent/matched -#define I2C_SR1_BTF (1U << 2) // Byte transfer finished -#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent -#define I2C_SR1_STOPF (1U << 4) // Stop detection -#define I2C_SR1_RXNE (1U << 6) // Data register not empty -#define I2C_SR1_TXE (1U << 7) // Data register empty -#define I2C_SR1_BERR (1U << 8) // Bus error -#define I2C_SR1_ARLO (1U << 9) // Arbitration lost -#define I2C_SR1_AF (1U << 10) // Acknowledge failure -#define I2C_SR1_OVR (1U << 11) // Overrun/underrun -#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception -#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error #define I2C_SR1_SMBALERT (1U << 15) // SMBus alert +#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error +#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception +#define I2C_SR1_OVR (1U << 11) // Overrun/underrun +#define I2C_SR1_AF (1U << 10) // Acknowledge failure +#define I2C_SR1_ARLO (1U << 9) // Arbitration lost +#define I2C_SR1_BERR (1U << 8) // Bus error +#define I2C_SR1_TXE (1U << 7) // Data register empty +#define I2C_SR1_RXNE (1U << 6) // Data register not empty +#define I2C_SR1_STOPF (1U << 4) // Stop detection +#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent +#define I2C_SR1_BTF (1U << 2) // Byte transfer finished +#define I2C_SR1_ADDR (1U << 1) // Address sent/matched +#define I2C_SR1_SB (1U << 0) // Start bit /* Status register 2 */ -#define I2C_SR2_MSL (1U << 0) // Master/slave -#define I2C_SR2_BUSY (1U << 1) // Bus busy -#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver -#define I2C_SR2_GENCALL (1U << 4) // General call address -#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address -#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header -#define I2C_SR2_DUALF (1U << 7) // Dual flag #define I2C_SR2_PEC 0xFF00 // Packet error checking register +#define I2C_SR2_DUALF (1U << 7) // Dual flag +#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header +#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address +#define I2C_SR2_GENCALL (1U << 4) // General call address +#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver +#define I2C_SR2_BUSY (1U << 1) // Bus busy +#define I2C_SR2_MSL (1U << 0) // Master/slave /* * Convenience routines -- cgit v1.2.3 From c0e99fcc4958f8ccc4f245a441b523e3e9c84ec3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 17:29:58 -0400 Subject: : Cosmetics. Put CCR definitions after SR2, to keep them in register map order. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index f27f8eb..7ee0b9a 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -158,12 +158,6 @@ extern i2c_dev* const I2C2; #define I2C_OAR2_ADD2 0xFE // Interface address #define I2C_OAR2_ENDUAL 1U // Dual addressing mode enable -/* Clock control register */ - -#define I2C_CCR_FS (1U << 15) // Fast mode selection -#define I2C_CCR_DUTY (1U << 14) // 16/9 duty ratio -#define I2C_CCR_CCR 0xFFF // Clock control bits - /* Status register 1 */ #define I2C_SR1_SMBALERT (1U << 15) // SMBus alert @@ -192,6 +186,12 @@ extern i2c_dev* const I2C2; #define I2C_SR2_BUSY (1U << 1) // Bus busy #define I2C_SR2_MSL (1U << 0) // Master/slave +/* Clock control register */ + +#define I2C_CCR_FS (1U << 15) // Fast mode selection +#define I2C_CCR_DUTY (1U << 14) // 16/9 duty ratio +#define I2C_CCR_CCR 0xFFF // Clock control bits + /* * Convenience routines */ -- cgit v1.2.3 From 041a1c28d3ec5e99793a7afab340ae53e68ea1cf Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 19 Jun 2012 17:55:33 -0400 Subject: libmaple/i2c.c: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 3eca22a..3db8516 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -488,7 +488,6 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) { dev->state = I2C_STATE_IDLE; } - /** * @brief Process an i2c transaction. * @@ -531,7 +530,6 @@ out: return rc; } - /** * @brief Wait for an I2C event, or time out in case of error. * @param dev I2C device -- cgit v1.2.3 From bcd28f11c2e7adfd488a10e59ed9dfad7877746d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 13:47:47 -0400 Subject: I2C: Restore on F1, refactoring prep for F2. Bring back support on STM32F1 with a view towards how it'll be implemented on STM32F2. There are still many F1-isms in libmaple/i2c.c and , to be dealt with subsequently. Move device declarations and base pointer definitions to a new F1 . The register maps and bit definitions themselves are identical on both series, so leave them in the libmaple header. Add i2c_private.h, which contains: - I2C_DEV(), a convenience macro for defining an i2c_dev, and - declarations for the event and error IRQ handlers. The IRQ handlers are large, and I2C is slow anyway, so I see no reason to make them inline in the private header (as we do for some other peripherals). We just expose the existing ones that were formerly static in libmaple/i2c.c, but prefix the names with underscore. Move the device declarations and IRQ handlers into new stm32f1/i2c.c. These use the i2c_private.h API. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 47 ++------------------------- libmaple/i2c_private.h | 46 +++++++++++++++++++++++++++ libmaple/include/libmaple/i2c.h | 17 +--------- libmaple/rules.mk | 7 ++-- libmaple/stm32f1/i2c.c | 60 +++++++++++++++++++++++++++++++++++ libmaple/stm32f1/include/series/i2c.h | 56 ++++++++++++++++++++++++++++++++ libmaple/stm32f1/rules.mk | 1 + 7 files changed, 171 insertions(+), 63 deletions(-) create mode 100644 libmaple/i2c_private.h create mode 100644 libmaple/stm32f1/i2c.c create mode 100644 libmaple/stm32f1/include/series/i2c.h diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 3db8516..5c0d5e4 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -2,6 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. + * Copyright (c) 2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -40,32 +41,6 @@ #include -static i2c_dev i2c_dev1 = { - .regs = I2C1_BASE, - .gpio_port = &gpiob, - .sda_pin = 7, - .scl_pin = 6, - .clk_id = RCC_I2C1, - .ev_nvic_line = NVIC_I2C1_EV, - .er_nvic_line = NVIC_I2C1_ER, - .state = I2C_STATE_DISABLED -}; -/** I2C1 device */ -i2c_dev* const I2C1 = &i2c_dev1; - -static i2c_dev i2c_dev2 = { - .regs = I2C2_BASE, - .gpio_port = &gpiob, - .sda_pin = 11, - .scl_pin = 10, - .clk_id = RCC_I2C2, - .ev_nvic_line = NVIC_I2C2_EV, - .er_nvic_line = NVIC_I2C2_ER, - .state = I2C_STATE_DISABLED -}; -/** I2C2 device */ -i2c_dev* const I2C2 = &i2c_dev2; - static inline int32 wait_for_state_change(i2c_dev *dev, i2c_state state, uint32 timeout); @@ -129,7 +104,7 @@ enum { * @brief IRQ handler for I2C master. Handles transmission/reception. * @param dev I2C device */ -static void i2c_irq_handler(i2c_dev *dev) { +void _i2c_irq_handler(i2c_dev *dev) { i2c_msg *msg = dev->msg; uint8 read = msg->flags & I2C_MSG_READ; @@ -289,20 +264,12 @@ static void i2c_irq_handler(i2c_dev *dev) { } } -void __irq_i2c1_ev(void) { - i2c_irq_handler(&i2c_dev1); -} - -void __irq_i2c2_ev(void) { - i2c_irq_handler(&i2c_dev2); -} - /** * @brief Interrupt handler for I2C error conditions * @param dev I2C device * @sideeffect Aborts any pending I2C transactions */ -static void i2c_irq_error_handler(i2c_dev *dev) { +void _i2c_irq_error_handler(i2c_dev *dev) { I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2); dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR | @@ -318,14 +285,6 @@ static void i2c_irq_error_handler(i2c_dev *dev) { dev->state = I2C_STATE_ERROR; } -void __irq_i2c1_er(void) { - i2c_irq_error_handler(&i2c_dev1); -} - -void __irq_i2c2_er(void) { - i2c_irq_error_handler(&i2c_dev2); -} - /** * @brief Reset an I2C bus. * diff --git a/libmaple/i2c_private.h b/libmaple/i2c_private.h new file mode 100644 index 0000000..4a0f01f --- /dev/null +++ b/libmaple/i2c_private.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#ifndef _LIBMAPLE_I2C_PRIVATE_H_ +#define _LIBMAPLE_I2C_PRIVATE_H_ + +#define I2C_DEV(num, port, sda, scl) \ + { \ + .regs = I2C##num##_BASE, \ + .gpio_port = port, \ + .sda_pin = sda, \ + .scl_pin = scl, \ + .clk_id = RCC_I2C##num, \ + .ev_nvic_line = NVIC_I2C##num##_EV, \ + .er_nvic_line = NVIC_I2C##num##_ER, \ + .state = I2C_STATE_DISABLED, \ + } + +struct i2c_dev; +void _i2c_irq_handler(struct i2c_dev *dev); +void _i2c_irq_error_handler(struct i2c_dev *dev); + +#endif /* _LIBMAPLE_I2C_PRIVATE_H_ */ diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 7ee0b9a..2b36404 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -37,6 +37,7 @@ extern "C" { #endif +#include #include #include #include @@ -96,22 +97,6 @@ typedef struct i2c_dev { volatile i2c_state state; /**< Device state */ } i2c_dev; -/* - * Devices - */ - -extern i2c_dev* const I2C1; -extern i2c_dev* const I2C2; - -/* - * Register map base pointers - */ - -/** I2C1 register map base pointer */ -#define I2C1_BASE ((struct i2c_reg_map*)0x40005400) -/** I2C2 register map base pointer */ -#define I2C2_BASE ((struct i2c_reg_map*)0x40005800) - /* * Register bit definitions */ diff --git a/libmaple/rules.mk b/libmaple/rules.mk index 41f5601..71979f0 100644 --- a/libmaple/rules.mk +++ b/libmaple/rules.mk @@ -27,10 +27,11 @@ cSRCS_$(d) += timer.c cSRCS_$(d) += usart.c cSRCS_$(d) += usart_private.c cSRCS_$(d) += util.c -# These still need to be brought back for F1: -# cSRCS_$(d) += i2c.c - sSRCS_$(d) := exc.S +# I2C support must be ported to F2: +ifeq ($(MCU_SERIES),stm32f1) +cSRCS_$(d) += i2c.c +endif cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c new file mode 100644 index 0000000..9ebcb40 --- /dev/null +++ b/libmaple/stm32f1/i2c.c @@ -0,0 +1,60 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +#include "i2c_private.h" +#include + +/* + * Devices + */ + +static i2c_dev i2c1 = I2C_DEV(1, &gpiob, 7, 6); +static i2c_dev i2c2 = I2C_DEV(2, &gpiob, 11, 10); + +/** STM32F1 I2C device 1 */ +i2c_dev* const I2C1 = &i2c1; +/** STM32F1 I2C device 2 */ +i2c_dev* const I2C2 = &i2c2; + +/* + * IRQ handlers + */ + +void __irq_i2c1_ev(void) { + _i2c_irq_handler(I2C1); +} + +void __irq_i2c2_ev(void) { + _i2c_irq_handler(I2C2); +} + +void __irq_i2c1_er(void) { + _i2c_irq_error_handler(I2C1); +} + +void __irq_i2c2_er(void) { + _i2c_irq_error_handler(I2C2); +} diff --git a/libmaple/stm32f1/include/series/i2c.h b/libmaple/stm32f1/include/series/i2c.h new file mode 100644 index 0000000..0e4b3ba --- /dev/null +++ b/libmaple/stm32f1/include/series/i2c.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung (from ). + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/include/stm32f1/include/series/i2c.h + * @brief STM32F1 I2C + */ + +#ifndef _LIBMAPLE_STM32F1_I2C_H_ +#define _LIBMAPLE_STM32F1_I2C_H_ + +/* + * Register maps + */ + +struct i2c_reg_map; + +/** STM32F1 I2C1 register map base pointer */ +#define I2C1_BASE ((struct i2c_reg_map*)0x40005400) +/** STM32F1 I2C2 register map base pointer */ +#define I2C2_BASE ((struct i2c_reg_map*)0x40005800) + +/* + * Devices + */ + +struct i2c_dev; + +extern struct i2c_dev* const I2C1; +extern struct i2c_dev* const I2C2; + +#endif /* _LIBMAPLE_STM32F1_I2C_H_ */ diff --git a/libmaple/stm32f1/rules.mk b/libmaple/stm32f1/rules.mk index 15f6fdb..3ca0813 100644 --- a/libmaple/stm32f1/rules.mk +++ b/libmaple/stm32f1/rules.mk @@ -20,6 +20,7 @@ cSRCS_$(d) += dma.c cSRCS_$(d) += exti.c cSRCS_$(d) += fsmc.c cSRCS_$(d) += gpio.c +cSRCS_$(d) += i2c.c cSRCS_$(d) += rcc.c cSRCS_$(d) += spi.c cSRCS_$(d) += timer.c -- cgit v1.2.3 From 3029415c3ecf62a2c9f7270d0ddc83247d831168 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 13:49:41 -0400 Subject: libmaple/i2c.h: Cosmetics. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 2b36404..db5e6c8 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -259,7 +259,6 @@ static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) { dev->regs->CCR = ccr; } - /** * @brief Set SCL rise time * @param dev I2C device @@ -270,6 +269,7 @@ static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) { dev->regs->TRISE = trise; } +/* Start/stop conditions */ /** * @brief Generate a start condition on the bus. @@ -305,6 +305,8 @@ static inline void i2c_stop_condition(i2c_dev *dev) { } +/* IRQ enable/disable */ + /** * @brief Enable one or more I2C interrupts * @param dev I2C device @@ -332,6 +334,7 @@ static inline void i2c_disable_irq(i2c_dev *dev, uint32 irqs) { dev->regs->CR2 &= ~irqs; } +/* ACK/NACK */ /** * @brief Enable I2C acknowledgment -- cgit v1.2.3 From 2fa8bdb7509e81789e76ca95e8b537272ce95ad5 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 14:05:34 -0400 Subject: Move i2c_dev and i2c_state into new i2c_common.h. This is necessary to add series-specific infrastructure to clean up some F1-isms in 's inline functions. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 29 +------------ libmaple/include/libmaple/i2c_common.h | 78 ++++++++++++++++++++++++++++++++++ libmaple/stm32f1/include/series/i2c.h | 8 ++-- 3 files changed, 84 insertions(+), 31 deletions(-) create mode 100644 libmaple/include/libmaple/i2c_common.h diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index db5e6c8..d327c72 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -38,6 +38,8 @@ extern "C" { #endif #include +#include + #include #include #include @@ -56,15 +58,6 @@ typedef struct i2c_reg_map { __io uint32 TRISE; /**< TRISE (rise time) register */ } i2c_reg_map; -/** I2C device states */ -typedef enum i2c_state { - I2C_STATE_DISABLED = 0, /**< Disabled */ - I2C_STATE_IDLE = 1, /**< Idle */ - I2C_STATE_XFER_DONE = 2, /**< Done with transfer */ - I2C_STATE_BUSY = 3, /**< Busy */ - I2C_STATE_ERROR = -1 /**< Error occurred */ -} i2c_state; - /** * @brief I2C message type */ @@ -79,24 +72,6 @@ typedef struct i2c_msg { uint8 *data; /**< Data */ } i2c_msg; -/** - * @brief I2C device type. - */ -typedef struct i2c_dev { - i2c_reg_map *regs; /**< Register map */ - i2c_msg *msg; /**< Messages */ - uint32 error_flags; /**< Error flags, set on I2C error condition */ - volatile uint32 timestamp; /**< For internal use */ - struct gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ - uint16 msgs_left; /**< Messages left */ - uint8 sda_pin; /**< SDA bit on gpio_port */ - uint8 scl_pin; /**< SCL bit on gpio_port */ - rcc_clk_id clk_id; /**< RCC clock information */ - nvic_irq_num ev_nvic_line; /**< Event IRQ number */ - nvic_irq_num er_nvic_line; /**< Error IRQ number */ - volatile i2c_state state; /**< Device state */ -} i2c_dev; - /* * Register bit definitions */ diff --git a/libmaple/include/libmaple/i2c_common.h b/libmaple/include/libmaple/i2c_common.h new file mode 100644 index 0000000..2f36f80 --- /dev/null +++ b/libmaple/include/libmaple/i2c_common.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung (from ). + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/** + * @file libmaple/include/libmaple/i2c_common.h + * @author Marti Bolivar + * @brief This file is an implementation detail + * + * WARNING: CONTENTS UNSTABLE + * + * The existence of this file is an implementation detail. Its + * contents are not stable, so never include it directly. If you need + * something from here, #include instead. + */ + +#ifndef _LIBMAPLE_I2C_COMMON_H_ +#define _LIBMAPLE_I2C_COMMON_H_ + +#include +#include +#include + +struct gpio_dev; +struct i2c_reg_map; +struct i2c_msg; + +/** I2C device states */ +typedef enum i2c_state { + I2C_STATE_DISABLED = 0, /**< Disabled */ + I2C_STATE_IDLE = 1, /**< Idle */ + I2C_STATE_XFER_DONE = 2, /**< Done with transfer */ + I2C_STATE_BUSY = 3, /**< Busy */ + I2C_STATE_ERROR = -1 /**< Error occurred */ +} i2c_state; + +/** + * @brief I2C device type. + */ +typedef struct i2c_dev { + struct i2c_reg_map *regs; /**< Register map */ + struct i2c_msg *msg; /**< Messages */ + uint32 error_flags; /**< Error flags, set on I2C error condition */ + volatile uint32 timestamp; /**< For internal use */ + struct gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ + uint16 msgs_left; /**< Messages left */ + uint8 sda_pin; /**< SDA bit on gpio_port */ + uint8 scl_pin; /**< SCL bit on gpio_port */ + rcc_clk_id clk_id; /**< RCC clock information */ + nvic_irq_num ev_nvic_line; /**< Event IRQ number */ + nvic_irq_num er_nvic_line; /**< Error IRQ number */ + volatile i2c_state state; /**< Device state */ +} i2c_dev; + +#endif diff --git a/libmaple/stm32f1/include/series/i2c.h b/libmaple/stm32f1/include/series/i2c.h index 0e4b3ba..f9f1e43 100644 --- a/libmaple/stm32f1/include/series/i2c.h +++ b/libmaple/stm32f1/include/series/i2c.h @@ -33,6 +33,8 @@ #ifndef _LIBMAPLE_STM32F1_I2C_H_ #define _LIBMAPLE_STM32F1_I2C_H_ +#include + /* * Register maps */ @@ -48,9 +50,7 @@ struct i2c_reg_map; * Devices */ -struct i2c_dev; - -extern struct i2c_dev* const I2C1; -extern struct i2c_dev* const I2C2; +extern i2c_dev* const I2C1; +extern i2c_dev* const I2C2; #endif /* _LIBMAPLE_STM32F1_I2C_H_ */ -- cgit v1.2.3 From c61a99d053d5ea230e41efe11772bac12ca2d51a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 14:28:32 -0400 Subject: i2c_set_input_clk(): fix an F1-ism. i2c_set_input_clk()'s documentation says that the maximum peripheral clock frequency is 36 MHz, but that's a hard-coded magic number. The actual limit is the device's APB frequency or 46 MHz, whichever is lower (F2 and F4 share the 46 MHz limit). Fix the documentation to reflect that fact, and add an internal series-provided function to get the maximum clock frequency for a device. To help users porting to F2, have i2c_set_input_clk() assert-check that the provided frequency is less than that maximum value and the hard 46 MHz limit. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 17 ++++++++++++++++- libmaple/stm32f1/include/series/i2c.h | 10 ++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index d327c72..6d1fadf 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -37,6 +37,15 @@ extern "C" { #endif +/* + * Series header must provide: + * + * - uint32 _i2c_bus_clk(i2c_dev*): Clock frequency of dev's bus, in + * MHz. (This is for internal use only). + * + * - Reg. map base pointers, device pointer declarations. + */ + #include #include @@ -212,13 +221,19 @@ static inline void i2c_write(i2c_dev *dev, uint8 byte) { /** * @brief Set input clock frequency, in MHz * @param dev I2C device - * @param freq Frequency in megahertz (2-36) + * @param freq Frequency, in MHz. This must be at least 2, and at most + * the APB frequency of dev's bus. (For example, if + * rcc_dev_clk(dev) == RCC_APB1, freq must be at most + * PCLK1, in MHz). There is an additional limit of 46 MHz. */ static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) { +#define I2C_MAX_FREQ_MHZ 46 + ASSERT(2 <= freq && freq <= _i2c_bus_clk(dev) && freq <= I2C_MAX_FREQ_MHZ); uint32 cr2 = dev->regs->CR2; cr2 &= ~I2C_CR2_FREQ; cr2 |= freq; dev->regs->CR2 = freq; +#undef I2C_MAX_FREQ_MHZ } /** diff --git a/libmaple/stm32f1/include/series/i2c.h b/libmaple/stm32f1/include/series/i2c.h index f9f1e43..0c89df4 100644 --- a/libmaple/stm32f1/include/series/i2c.h +++ b/libmaple/stm32f1/include/series/i2c.h @@ -34,6 +34,7 @@ #define _LIBMAPLE_STM32F1_I2C_H_ #include +#include /* * Register maps @@ -53,4 +54,13 @@ struct i2c_reg_map; extern i2c_dev* const I2C1; extern i2c_dev* const I2C2; +/* + * For internal use + */ + +static inline uint32 _i2c_bus_clk(i2c_dev *dev) { + /* Both I2C peripherals are on APB1 */ + return STM32_PCLK1 / (1000 * 1000); +} + #endif /* _LIBMAPLE_STM32F1_I2C_H_ */ -- cgit v1.2.3 From 336b45c9954c8821e73e8f0e4a9b5011a4af28b6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 15:14:56 -0400 Subject: I2C: Fix Doxygen F1-isms. I'm not sure these functions should even exist in their present form,, but I don't understand the code well enough to make a real fix. For now, just replace references to RM0008 with "chip reference manual". Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 6d1fadf..ccce139 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -237,7 +237,10 @@ static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) { } /** - * @brief Set I2C clock control register. See RM008 + * @brief Set I2C clock control register. + * + * See the chip reference manual for the details. + * * @param dev I2C device * @param val Value to use for clock control register (in * Fast/Standard mode) @@ -252,8 +255,8 @@ static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) { /** * @brief Set SCL rise time * @param dev I2C device - * @param trise Maximum rise time in fast/standard mode (see RM0008 - * for relevant formula). + * @param trise Maximum rise time in fast/standard mode (see chip + * reference manual for the relevant formulas). */ static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) { dev->regs->TRISE = trise; -- cgit v1.2.3 From 9e08625d03acdef8dd2007cdb9fc203a074240b2 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 15:18:17 -0400 Subject: : Move low-level routines to end of file. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 144 ++++++++++++++++++++-------------------- 1 file changed, 73 insertions(+), 71 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index ccce139..8ea77d7 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -165,8 +165,6 @@ typedef struct i2c_msg { * Convenience routines */ -void i2c_init(i2c_dev *dev); - /* I2C enable options */ #define I2C_FAST_MODE 0x1 // 400 khz #define I2C_DUTY_16_9 0x2 // 16/9 duty ratio @@ -193,75 +191,6 @@ static inline void i2c_disable(i2c_dev *dev) { dev->state = I2C_STATE_DISABLED; } -/** - * @brief Turn on an I2C peripheral - * @param dev Device to enable - */ -static inline void i2c_peripheral_enable(i2c_dev *dev) { - dev->regs->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Turn off an I2C peripheral - * @param dev Device to turn off - */ -static inline void i2c_peripheral_disable(i2c_dev *dev) { - dev->regs->CR1 &= ~I2C_CR1_PE; -} - -/** - * @brief Fill transmit register - * @param dev I2C device - * @param byte Byte to write - */ -static inline void i2c_write(i2c_dev *dev, uint8 byte) { - dev->regs->DR = byte; -} - -/** - * @brief Set input clock frequency, in MHz - * @param dev I2C device - * @param freq Frequency, in MHz. This must be at least 2, and at most - * the APB frequency of dev's bus. (For example, if - * rcc_dev_clk(dev) == RCC_APB1, freq must be at most - * PCLK1, in MHz). There is an additional limit of 46 MHz. - */ -static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) { -#define I2C_MAX_FREQ_MHZ 46 - ASSERT(2 <= freq && freq <= _i2c_bus_clk(dev) && freq <= I2C_MAX_FREQ_MHZ); - uint32 cr2 = dev->regs->CR2; - cr2 &= ~I2C_CR2_FREQ; - cr2 |= freq; - dev->regs->CR2 = freq; -#undef I2C_MAX_FREQ_MHZ -} - -/** - * @brief Set I2C clock control register. - * - * See the chip reference manual for the details. - * - * @param dev I2C device - * @param val Value to use for clock control register (in - * Fast/Standard mode) - */ -static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) { - uint32 ccr = dev->regs->CCR; - ccr &= ~I2C_CCR_CCR; - ccr |= val; - dev->regs->CCR = ccr; -} - -/** - * @brief Set SCL rise time - * @param dev I2C device - * @param trise Maximum rise time in fast/standard mode (see chip - * reference manual for the relevant formulas). - */ -static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) { - dev->regs->TRISE = trise; -} - /* Start/stop conditions */ /** @@ -345,6 +274,79 @@ static inline void i2c_disable_ack(i2c_dev *dev) { dev->regs->CR1 &= ~I2C_CR1_ACK; } +/* Miscellaneous low-level routines */ + +void i2c_init(i2c_dev *dev); + +/** + * @brief Turn on an I2C peripheral + * @param dev Device to enable + */ +static inline void i2c_peripheral_enable(i2c_dev *dev) { + dev->regs->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Turn off an I2C peripheral + * @param dev Device to turn off + */ +static inline void i2c_peripheral_disable(i2c_dev *dev) { + dev->regs->CR1 &= ~I2C_CR1_PE; +} + +/** + * @brief Fill transmit register + * @param dev I2C device + * @param byte Byte to write + */ +static inline void i2c_write(i2c_dev *dev, uint8 byte) { + dev->regs->DR = byte; +} + +/** + * @brief Set input clock frequency, in MHz + * @param dev I2C device + * @param freq Frequency, in MHz. This must be at least 2, and at most + * the APB frequency of dev's bus. (For example, if + * rcc_dev_clk(dev) == RCC_APB1, freq must be at most + * PCLK1, in MHz). There is an additional limit of 46 MHz. + */ +static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) { +#define I2C_MAX_FREQ_MHZ 46 + ASSERT(2 <= freq && freq <= _i2c_bus_clk(dev) && freq <= I2C_MAX_FREQ_MHZ); + uint32 cr2 = dev->regs->CR2; + cr2 &= ~I2C_CR2_FREQ; + cr2 |= freq; + dev->regs->CR2 = freq; +#undef I2C_MAX_FREQ_MHZ +} + +/** + * @brief Set I2C clock control register. + * + * See the chip reference manual for the details. + * + * @param dev I2C device + * @param val Value to use for clock control register (in + * Fast/Standard mode) + */ +static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) { + uint32 ccr = dev->regs->CCR; + ccr &= ~I2C_CCR_CCR; + ccr |= val; + dev->regs->CCR = ccr; +} + +/** + * @brief Set SCL rise time + * @param dev I2C device + * @param trise Maximum rise time in fast/standard mode (see chip + * reference manual for the relevant formulas). + */ +static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) { + dev->regs->TRISE = trise; +} + #ifdef __cplusplus } #endif -- cgit v1.2.3 From 53b77e1ef202191fb398092ca1d5d10b2ad602bb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 16:28:24 -0400 Subject: I2C: I don't think 10-bit addressing works. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 5c0d5e4..451643e 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -105,6 +105,9 @@ enum { * @param dev I2C device */ void _i2c_irq_handler(i2c_dev *dev) { + /* WTFs: + * - Where is I2C_MSG_10BIT_ADDR handled? + */ i2c_msg *msg = dev->msg; uint8 read = msg->flags & I2C_MSG_READ; -- cgit v1.2.3 From 0262fe55fa5c87264b3e93358474a77289603d20 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 16:30:49 -0400 Subject: libmaple/i2c.c: Replace throb() with ASSERT(0). Calling throb() directly like that breaks the abstraction. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 451643e..1618586 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -193,7 +193,7 @@ void _i2c_irq_handler(i2c_dev *dev) { /* * This should be impossible... */ - throb(); + ASSERT(0); } sr1 = sr2 = 0; } -- cgit v1.2.3 From a3344f4ab3ab90b1aec05c97cb026cec9ec73e9e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Wed, 20 Jun 2012 16:34:15 -0400 Subject: libmaple/i2c.h: Better comments. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 8ea77d7..859edcd 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -28,6 +28,13 @@ /** * @file libmaple/include/libmaple/i2c.h * @brief Inter-Integrated Circuit (I2C) peripheral support + * + * Currently master-only. Usage notes: + * + * - Enable an I2C device with i2c_master_enable(). + * - Initialize an array of struct i2c_msg to suit the bus + * transactions (reads/writes) you wish to perform. + * - Call i2c_master_xfer() to do the work. */ #ifndef _LIBMAPLE_I2C_H_ @@ -72,10 +79,15 @@ typedef struct i2c_reg_map { */ typedef struct i2c_msg { uint16 addr; /**< Address */ + #define I2C_MSG_READ 0x1 #define I2C_MSG_10BIT_ADDR 0x2 - uint16 flags; /**< Bitwise OR of I2C_MSG_READ and - I2C_MSG_10BIT_ADDR */ + /** + * Bitwise OR of: + * - I2C_MSG_READ (write is default) + * - I2C_MSG_10BIT_ADDR (7-bit is default) */ + uint16 flags; + uint16 length; /**< Message length */ uint16 xferred; /**< Messages transferred */ uint8 *data; /**< Data */ @@ -165,6 +177,8 @@ typedef struct i2c_msg { * Convenience routines */ +/* Main I2C API */ + /* I2C enable options */ #define I2C_FAST_MODE 0x1 // 400 khz #define I2C_DUTY_16_9 0x2 // 16/9 duty ratio -- cgit v1.2.3 From f34ba402c9a39acc43828918313a30d2fbc4e186 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 14:45:43 -0400 Subject: : Fix Doxygen. Existing Doxygen was commenting I2C_IRQ_ERROR instead of i2c_enable_irq(), as desired. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 859edcd..9f65f13 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -243,6 +243,9 @@ static inline void i2c_stop_condition(i2c_dev *dev) { /* IRQ enable/disable */ +#define I2C_IRQ_ERROR I2C_CR2_ITERREN +#define I2C_IRQ_EVENT I2C_CR2_ITEVTEN +#define I2C_IRQ_BUFFER I2C_CR2_ITBUFEN /** * @brief Enable one or more I2C interrupts * @param dev I2C device @@ -251,9 +254,6 @@ static inline void i2c_stop_condition(i2c_dev *dev) { * I2C_IRQ_EVENT (event interrupt), and * I2C_IRQ_BUFFER (buffer interrupt). */ -#define I2C_IRQ_ERROR I2C_CR2_ITERREN -#define I2C_IRQ_EVENT I2C_CR2_ITEVTEN -#define I2C_IRQ_BUFFER I2C_CR2_ITBUFEN static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) { dev->regs->CR2 |= irqs; } -- cgit v1.2.3 From baf9dd6a8275160fdf5a4ff63efa2678f16b1cc3 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 15:04:39 -0400 Subject: I2C: Add i2c_config_gpios(), i2c_master_release_bus(). These are necessary to pull out some calls to gpio_set_mode(). Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 8 ++------ libmaple/include/libmaple/i2c.h | 25 +++++++++++++++++++++++++ libmaple/stm32f1/i2c.c | 16 ++++++++++++++++ 3 files changed, 43 insertions(+), 6 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 1618586..f54be47 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -299,10 +299,7 @@ void _i2c_irq_error_handler(i2c_dev *dev) { */ void i2c_bus_reset(const i2c_dev *dev) { /* Release both lines */ - gpio_write_bit(dev->gpio_port, dev->scl_pin, 1); - gpio_write_bit(dev->gpio_port, dev->sda_pin, 1); - gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD); - gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD); + i2c_master_release_bus(dev); /* * Make sure the bus is free by clocking it until any slaves release the @@ -376,8 +373,7 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) { /* Turn on clock and set GPIO modes */ i2c_init(dev); - gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD); - gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD); + i2c_config_gpios(dev); /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */ i2c_set_input_clk(dev, I2C_CLK); diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 9f65f13..8ce6674 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -288,6 +288,31 @@ static inline void i2c_disable_ack(i2c_dev *dev) { dev->regs->CR1 &= ~I2C_CR1_ACK; } +/* GPIO control */ + +/** + * @brief Configure device GPIOs. + * + * Configure GPIO bits dev->sda_pin and dev->scl_pin on GPIO device + * dev->gpio_port for use with I2C device dev. + * + * @param dev I2C Device + * @see i2c_release_gpios() + */ +extern void i2c_config_gpios(const i2c_dev *dev); + +/** + * @brief Release GPIOs controlling an I2C bus + * + * Releases the I2C bus controlled by dev as master, and disconnects + * GPIO bits dev->sda_pin and dev->scl_pin on GPIO device + * dev->gpio_port from I2C device dev. + * + * @param dev I2C device + * @see i2c_config_gpios() + */ +extern void i2c_master_release_bus(const i2c_dev *dev); + /* Miscellaneous low-level routines */ void i2c_init(i2c_dev *dev); diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index 9ebcb40..ed0ca97 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -39,6 +39,22 @@ i2c_dev* const I2C1 = &i2c1; /** STM32F1 I2C device 2 */ i2c_dev* const I2C2 = &i2c2; +/* + * Routines + */ + +void i2c_config_gpios(const i2c_dev *dev) { + gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD); + gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD); +} + +void i2c_master_release_bus(const i2c_dev *dev) { + gpio_write_bit(dev->gpio_port, dev->scl_pin, 1); + gpio_write_bit(dev->gpio_port, dev->sda_pin, 1); + gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD); + gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD); +} + /* * IRQ handlers */ -- cgit v1.2.3 From 11d7ba62fb30bdcc26cd5e281eaf8b267782a561 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 15:12:16 -0400 Subject: libmaple/i2c.c: Keep authorship straight. I'm going to be moving a lot of code around without changing it soon, so git blame will be unreliable. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index f54be47..15bcbe0 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -27,6 +27,7 @@ /** * @file libmaple/i2c.c + * @author Perry Hung * @brief Inter-Integrated Circuit (I2C) support. * * Currently, only master mode is supported. -- cgit v1.2.3 From 3ba9c0ecd6fd881d21292a369f8b7e45be5d2cb4 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 15:15:34 -0400 Subject: libmaple/i2c.c: Cosmetics. Move private API to bottom of file. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 378 +++++++++++++++++++++++++++++---------------------------- 1 file changed, 190 insertions(+), 188 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 15bcbe0..2e11f54 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -101,194 +101,6 @@ enum { ERROR_ENTRY = 13, }; -/** - * @brief IRQ handler for I2C master. Handles transmission/reception. - * @param dev I2C device - */ -void _i2c_irq_handler(i2c_dev *dev) { - /* WTFs: - * - Where is I2C_MSG_10BIT_ADDR handled? - */ - i2c_msg *msg = dev->msg; - - uint8 read = msg->flags & I2C_MSG_READ; - - uint32 sr1 = dev->regs->SR1; - uint32 sr2 = dev->regs->SR2; - I2C_CRUMB(IRQ_ENTRY, sr1, sr2); - - /* - * Reset timeout counter - */ - dev->timestamp = systick_uptime(); - - /* - * EV5: Start condition sent - */ - if (sr1 & I2C_SR1_SB) { - msg->xferred = 0; - i2c_enable_irq(dev, I2C_IRQ_BUFFER); - - /* - * Master receiver - */ - if (read) { - i2c_enable_ack(dev); - } - - i2c_send_slave_addr(dev, msg->addr, read); - sr1 = sr2 = 0; - } - - /* - * EV6: Slave address sent - */ - if (sr1 & I2C_SR1_ADDR) { - /* - * Special case event EV6_1 for master receiver. - * Generate NACK and restart/stop condition after ADDR - * is cleared. - */ - if (read) { - if (msg->length == 1) { - i2c_disable_ack(dev); - if (dev->msgs_left > 1) { - i2c_start_condition(dev); - I2C_CRUMB(RX_ADDR_START, 0, 0); - } else { - i2c_stop_condition(dev); - I2C_CRUMB(RX_ADDR_STOP, 0, 0); - } - } - } else { - /* - * Master transmitter: write first byte to fill shift - * register. We should get another TXE interrupt - * immediately to fill DR again. - */ - if (msg->length != 1) { - i2c_write(dev, msg->data[msg->xferred++]); - } - } - sr1 = sr2 = 0; - } - - /* - * EV8: Master transmitter - * Transmit buffer empty, but we haven't finished transmitting the last - * byte written. - */ - if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) { - I2C_CRUMB(TXE_ONLY, 0, 0); - if (dev->msgs_left) { - i2c_write(dev, msg->data[msg->xferred++]); - if (msg->xferred == msg->length) { - /* - * End of this message. Turn off TXE/RXNE and wait for - * BTF to send repeated start or stop condition. - */ - i2c_disable_irq(dev, I2C_IRQ_BUFFER); - dev->msgs_left--; - } - } else { - /* - * This should be impossible... - */ - ASSERT(0); - } - sr1 = sr2 = 0; - } - - /* - * EV8_2: Master transmitter - * Last byte sent, program repeated start/stop - */ - if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) { - I2C_CRUMB(TXE_BTF, 0, 0); - if (dev->msgs_left) { - I2C_CRUMB(TEST, 0, 0); - /* - * Repeated start insanity: We can't disable ITEVTEN or else SB - * won't interrupt, but if we don't disable ITEVTEN, BTF will - * continually interrupt us. What the fuck ST? - */ - i2c_start_condition(dev); - while (!(dev->regs->SR1 & I2C_SR1_SB)) - ; - dev->msg++; - } else { - i2c_stop_condition(dev); - - /* - * Turn off event interrupts to keep BTF from firing until - * the end of the stop condition. Why on earth they didn't - * have a start/stop condition request clear BTF is beyond - * me. - */ - i2c_disable_irq(dev, I2C_IRQ_EVENT); - I2C_CRUMB(STOP_SENT, 0, 0); - dev->state = I2C_STATE_XFER_DONE; - } - sr1 = sr2 = 0; - } - - /* - * EV7: Master Receiver - */ - if (sr1 & I2C_SR1_RXNE) { - I2C_CRUMB(RXNE_ONLY, 0, 0); - msg->data[msg->xferred++] = dev->regs->DR; - - /* - * EV7_1: Second to last byte in the reception? Set NACK and generate - * stop/restart condition in time for the last byte. We'll get one more - * RXNE interrupt before shutting things down. - */ - if (msg->xferred == (msg->length - 1)) { - i2c_disable_ack(dev); - if (dev->msgs_left > 2) { - i2c_start_condition(dev); - I2C_CRUMB(RXNE_START_SENT, 0, 0); - } else { - i2c_stop_condition(dev); - I2C_CRUMB(RXNE_STOP_SENT, 0, 0); - } - } else if (msg->xferred == msg->length) { - dev->msgs_left--; - if (dev->msgs_left == 0) { - /* - * We're done. - */ - I2C_CRUMB(RXNE_DONE, 0, 0); - dev->state = I2C_STATE_XFER_DONE; - } else { - dev->msg++; - } - } - } -} - -/** - * @brief Interrupt handler for I2C error conditions - * @param dev I2C device - * @sideeffect Aborts any pending I2C transactions - */ -void _i2c_irq_error_handler(i2c_dev *dev) { - I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2); - - dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR | - I2C_SR1_ARLO | - I2C_SR1_AF | - I2C_SR1_OVR); - /* Clear flags */ - dev->regs->SR1 = 0; - dev->regs->SR2 = 0; - - i2c_stop_condition(dev); - i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR); - dev->state = I2C_STATE_ERROR; -} - /** * @brief Reset an I2C bus. * @@ -521,3 +333,193 @@ static inline int32 wait_for_state_change(i2c_dev *dev, } } } + +/* + * Private API + */ + +/* + * IRQ handler for I2C master. Handles transmission/reception. + */ +void _i2c_irq_handler(i2c_dev *dev) { + /* WTFs: + * - Where is I2C_MSG_10BIT_ADDR handled? + */ + i2c_msg *msg = dev->msg; + + uint8 read = msg->flags & I2C_MSG_READ; + + uint32 sr1 = dev->regs->SR1; + uint32 sr2 = dev->regs->SR2; + I2C_CRUMB(IRQ_ENTRY, sr1, sr2); + + /* + * Reset timeout counter + */ + dev->timestamp = systick_uptime(); + + /* + * EV5: Start condition sent + */ + if (sr1 & I2C_SR1_SB) { + msg->xferred = 0; + i2c_enable_irq(dev, I2C_IRQ_BUFFER); + + /* + * Master receiver + */ + if (read) { + i2c_enable_ack(dev); + } + + i2c_send_slave_addr(dev, msg->addr, read); + sr1 = sr2 = 0; + } + + /* + * EV6: Slave address sent + */ + if (sr1 & I2C_SR1_ADDR) { + /* + * Special case event EV6_1 for master receiver. + * Generate NACK and restart/stop condition after ADDR + * is cleared. + */ + if (read) { + if (msg->length == 1) { + i2c_disable_ack(dev); + if (dev->msgs_left > 1) { + i2c_start_condition(dev); + I2C_CRUMB(RX_ADDR_START, 0, 0); + } else { + i2c_stop_condition(dev); + I2C_CRUMB(RX_ADDR_STOP, 0, 0); + } + } + } else { + /* + * Master transmitter: write first byte to fill shift + * register. We should get another TXE interrupt + * immediately to fill DR again. + */ + if (msg->length != 1) { + i2c_write(dev, msg->data[msg->xferred++]); + } + } + sr1 = sr2 = 0; + } + + /* + * EV8: Master transmitter + * Transmit buffer empty, but we haven't finished transmitting the last + * byte written. + */ + if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) { + I2C_CRUMB(TXE_ONLY, 0, 0); + if (dev->msgs_left) { + i2c_write(dev, msg->data[msg->xferred++]); + if (msg->xferred == msg->length) { + /* + * End of this message. Turn off TXE/RXNE and wait for + * BTF to send repeated start or stop condition. + */ + i2c_disable_irq(dev, I2C_IRQ_BUFFER); + dev->msgs_left--; + } + } else { + /* + * This should be impossible... + */ + ASSERT(0); + } + sr1 = sr2 = 0; + } + + /* + * EV8_2: Master transmitter + * Last byte sent, program repeated start/stop + */ + if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) { + I2C_CRUMB(TXE_BTF, 0, 0); + if (dev->msgs_left) { + I2C_CRUMB(TEST, 0, 0); + /* + * Repeated start insanity: We can't disable ITEVTEN or else SB + * won't interrupt, but if we don't disable ITEVTEN, BTF will + * continually interrupt us. What the fuck ST? + */ + i2c_start_condition(dev); + while (!(dev->regs->SR1 & I2C_SR1_SB)) + ; + dev->msg++; + } else { + i2c_stop_condition(dev); + + /* + * Turn off event interrupts to keep BTF from firing until + * the end of the stop condition. Why on earth they didn't + * have a start/stop condition request clear BTF is beyond + * me. + */ + i2c_disable_irq(dev, I2C_IRQ_EVENT); + I2C_CRUMB(STOP_SENT, 0, 0); + dev->state = I2C_STATE_XFER_DONE; + } + sr1 = sr2 = 0; + } + + /* + * EV7: Master Receiver + */ + if (sr1 & I2C_SR1_RXNE) { + I2C_CRUMB(RXNE_ONLY, 0, 0); + msg->data[msg->xferred++] = dev->regs->DR; + + /* + * EV7_1: Second to last byte in the reception? Set NACK and generate + * stop/restart condition in time for the last byte. We'll get one more + * RXNE interrupt before shutting things down. + */ + if (msg->xferred == (msg->length - 1)) { + i2c_disable_ack(dev); + if (dev->msgs_left > 2) { + i2c_start_condition(dev); + I2C_CRUMB(RXNE_START_SENT, 0, 0); + } else { + i2c_stop_condition(dev); + I2C_CRUMB(RXNE_STOP_SENT, 0, 0); + } + } else if (msg->xferred == msg->length) { + dev->msgs_left--; + if (dev->msgs_left == 0) { + /* + * We're done. + */ + I2C_CRUMB(RXNE_DONE, 0, 0); + dev->state = I2C_STATE_XFER_DONE; + } else { + dev->msg++; + } + } + } +} + +/* + * Interrupt handler for I2C error conditions. Aborts any pending I2C + * transactions. + */ +void _i2c_irq_error_handler(i2c_dev *dev) { + I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2); + + dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR | + I2C_SR1_ARLO | + I2C_SR1_AF | + I2C_SR1_OVR); + /* Clear flags */ + dev->regs->SR1 = 0; + dev->regs->SR2 = 0; + + i2c_stop_condition(dev); + i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR); + dev->state = I2C_STATE_ERROR; +} -- cgit v1.2.3 From 70f22b667a7d91c68d663c1bf9ef1c0bdcbdd377 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 15:45:38 -0400 Subject: I2C: Move F1-only errata workarounds out of libmaple/i2c.c. The IRQ priority hack is unnecessary on targets with properly functioning I2C IRQ handlers, so we shouldn't use it unless we have to. Add a mechanism so a series header can provide such a hack if necessary. Have the F1 series header use this mechanism. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 30 ----------------------------- libmaple/include/libmaple/i2c.h | 18 ++++++++++++++++++ libmaple/stm32f1/i2c.c | 36 +++++++++++++++++++++++++++++++++++ libmaple/stm32f1/include/series/i2c.h | 3 +++ 4 files changed, 57 insertions(+), 30 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 2e11f54..291bf16 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -223,36 +223,6 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) { nvic_irq_enable(dev->er_nvic_line); i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR); - /* - * Important STM32 Errata: - * - * See STM32F10xx8 and STM32F10xxB Errata sheet (Doc ID 14574 Rev 8), - * Section 2.11.1, 2.11.2. - * - * 2.11.1: - * When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not - * managed before the current byte is being transferred, problems may be - * encountered such as receiving an extra byte, reading the same data twice - * or missing data. - * - * 2.11.2: - * In Master Receiver mode, when closing the communication using - * method 2, the content of the last read data can be corrupted. - * - * If the user software is not able to read the data N-1 before the STOP - * condition is generated on the bus, the content of the shift register - * (data N) will be corrupted. (data N is shifted 1-bit to the left). - * - * ---------------------------------------------------------------------- - * - * In order to ensure that events are not missed, the i2c interrupt must - * not be preempted. We set the i2c interrupt priority to be the highest - * interrupt in the system (priority level 0). All other interrupts have - * been initialized to priority level 16. See nvic_init(). - */ - nvic_irq_set_priority(dev->ev_nvic_line, 0); - nvic_irq_set_priority(dev->er_nvic_line, 0); - /* Make it go! */ i2c_peripheral_enable(dev); diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 8ce6674..c66ebcb 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -50,6 +50,17 @@ extern "C" { * - uint32 _i2c_bus_clk(i2c_dev*): Clock frequency of dev's bus, in * MHz. (This is for internal use only). * + * - (optional) _I2C_HAVE_IRQ_FIXUP: Leave undefined, or define to 1. + * This is for internal use only. It's a hack to work around a + * silicon bug related to I2C IRQ pre-emption on some targets. If 1, + * the series header must also declare and implement a routine with + * this signature (it may also be provided as a macro): + * + * void _i2c_irq_priority_fixup(i2c_dev*) + * + * This will be called by i2c_enable_irq() before actually enabling + * I2C interrupts. + * * - Reg. map base pointers, device pointer declarations. */ @@ -243,6 +254,12 @@ static inline void i2c_stop_condition(i2c_dev *dev) { /* IRQ enable/disable */ +#ifndef _I2C_HAVE_IRQ_FIXUP +/* The series header provides this if _I2C_HAVE_IRQ_FIXUP is defined, + * but we need it either way. */ +#define _i2c_irq_priority_fixup(dev) ((void)0) +#endif + #define I2C_IRQ_ERROR I2C_CR2_ITERREN #define I2C_IRQ_EVENT I2C_CR2_ITEVTEN #define I2C_IRQ_BUFFER I2C_CR2_ITBUFEN @@ -255,6 +272,7 @@ static inline void i2c_stop_condition(i2c_dev *dev) { * I2C_IRQ_BUFFER (buffer interrupt). */ static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) { + _i2c_irq_priority_fixup(dev); dev->regs->CR2 |= irqs; } diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index ed0ca97..4e918ad 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -74,3 +74,39 @@ void __irq_i2c1_er(void) { void __irq_i2c2_er(void) { _i2c_irq_error_handler(I2C2); } + +/* + * Internal APIs + */ + +void _i2c_irq_priority_fixup(i2c_dev *dev) { + /* + * Important STM32 Errata: + * + * See STM32F10xx8 and STM32F10xxB Errata sheet (Doc ID 14574 Rev 8), + * Section 2.11.1, 2.11.2. + * + * 2.11.1: + * When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not + * managed before the current byte is being transferred, problems may be + * encountered such as receiving an extra byte, reading the same data twice + * or missing data. + * + * 2.11.2: + * In Master Receiver mode, when closing the communication using + * method 2, the content of the last read data can be corrupted. + * + * If the user software is not able to read the data N-1 before the STOP + * condition is generated on the bus, the content of the shift register + * (data N) will be corrupted. (data N is shifted 1-bit to the left). + * + * ---------------------------------------------------------------------- + * + * In order to ensure that events are not missed, the i2c interrupt must + * not be preempted. We set the i2c interrupt priority to be the highest + * interrupt in the system (priority level 0). All other interrupts have + * been initialized to priority level 16. See nvic_init(). + */ + nvic_irq_set_priority(dev->ev_nvic_line, 0); + nvic_irq_set_priority(dev->er_nvic_line, 0); +} diff --git a/libmaple/stm32f1/include/series/i2c.h b/libmaple/stm32f1/include/series/i2c.h index 0c89df4..315a7e3 100644 --- a/libmaple/stm32f1/include/series/i2c.h +++ b/libmaple/stm32f1/include/series/i2c.h @@ -63,4 +63,7 @@ static inline uint32 _i2c_bus_clk(i2c_dev *dev) { return STM32_PCLK1 / (1000 * 1000); } +#define _I2C_HAVE_IRQ_FIXUP 1 +void _i2c_irq_priority_fixup(i2c_dev *dev); + #endif /* _LIBMAPLE_STM32F1_I2C_H_ */ -- cgit v1.2.3 From 4d133982271fd063779174d1695e14c7821c6da6 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 16:04:18 -0400 Subject: I2C: Deprecate I2C_REMAP flag. This is ad-hoc and nonportable. If you really want I2C mapped elsewhere, then mess with the I2C device fields and call afio_remap() yourself. (This is also cleaner for F2). Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 15 +++++++++------ libmaple/include/libmaple/i2c.h | 2 +- libmaple/stm32f1/include/series/i2c.h | 16 ++++++++++++++++ 3 files changed, 26 insertions(+), 7 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 291bf16..d2447a4 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -153,6 +153,11 @@ void i2c_init(i2c_dev *dev) { rcc_clk_enable(dev->clk_id); } +/* Hack for deprecated bit of STM32F1 functionality */ +#ifndef _I2C_HAVE_DEPRECATED_I2C_REMAP +#define _i2c_handle_remap(dev, flags) ((void)0) +#endif + /** * @brief Initialize an I2C device as bus master * @param dev Device to enable @@ -163,7 +168,8 @@ void i2c_init(i2c_dev *dev) { * I2C_BUS_RESET: Reset the bus and clock out any hung slaves on * initialization, * I2C_10BIT_ADDRESSING: Enable 10-bit addressing, - * I2C_REMAP: Remap I2C1 to SCL/PB8 SDA/PB9. + * I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8 + * SDA/PB9. */ void i2c_master_enable(i2c_dev *dev, uint32 flags) { #define I2C_CLK (STM32_PCLK1/1000000) @@ -173,11 +179,8 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) { /* PE must be disabled to configure the device */ ASSERT(!(dev->regs->CR1 & I2C_CR1_PE)); - if ((dev == I2C1) && (flags & I2C_REMAP)) { - afio_remap(AFIO_REMAP_I2C1); - I2C1->sda_pin = 9; - I2C1->scl_pin = 8; - } + /* Ugh */ + _i2c_handle_remap(dev, flags); /* Reset the bus. Clock out any hung slaves. */ if (flags & I2C_BUS_RESET) { diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index c66ebcb..f7821af 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -193,7 +193,7 @@ typedef struct i2c_msg { /* I2C enable options */ #define I2C_FAST_MODE 0x1 // 400 khz #define I2C_DUTY_16_9 0x2 // 16/9 duty ratio -#define I2C_REMAP 0x4 // Use alternate pin mapping +/* Flag 0x4 is reserved; DO NOT USE. */ #define I2C_BUS_RESET 0x8 // Perform a bus reset void i2c_master_enable(i2c_dev *dev, uint32 flags); diff --git a/libmaple/stm32f1/include/series/i2c.h b/libmaple/stm32f1/include/series/i2c.h index 315a7e3..a0822e8 100644 --- a/libmaple/stm32f1/include/series/i2c.h +++ b/libmaple/stm32f1/include/series/i2c.h @@ -34,6 +34,7 @@ #define _LIBMAPLE_STM32F1_I2C_H_ #include +#include #include /* @@ -66,4 +67,19 @@ static inline uint32 _i2c_bus_clk(i2c_dev *dev) { #define _I2C_HAVE_IRQ_FIXUP 1 void _i2c_irq_priority_fixup(i2c_dev *dev); +/* + * Deprecated functionality + */ + +/* Flag to use alternate pin mapping in i2c_master_enable(). */ +#define _I2C_HAVE_DEPRECATED_I2C_REMAP 1 +#define I2C_REMAP 0x4 +static inline void _i2c_handle_remap(i2c_dev *dev, uint32 flags) { + if ((dev == I2C1) && (flags & I2C_REMAP)) { + afio_remap(AFIO_REMAP_I2C1); + I2C1->sda_pin = 9; + I2C1->scl_pin = 8; + } +} + #endif /* _LIBMAPLE_STM32F1_I2C_H_ */ -- cgit v1.2.3 From fe34ca70469f1bd88eb38feb2b0b336ef5b07ff8 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 16:29:22 -0400 Subject: I2C: Move nonportable CCR/TRISE configuration. Do this via new private _i2c_set_ccr_trise(). Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 37 ++++--------------------------------- libmaple/i2c_private.h | 4 ++++ libmaple/stm32f1/i2c.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 33 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index d2447a4..0e6a64c 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -33,6 +33,8 @@ * Currently, only master mode is supported. */ +#include "i2c_private.h" + #include #include #include @@ -172,10 +174,6 @@ void i2c_init(i2c_dev *dev) { * SDA/PB9. */ void i2c_master_enable(i2c_dev *dev, uint32 flags) { -#define I2C_CLK (STM32_PCLK1/1000000) - uint32 ccr = 0; - uint32 trise = 0; - /* PE must be disabled to configure the device */ ASSERT(!(dev->regs->CR1 & I2C_CR1_PE)); @@ -191,35 +189,8 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) { i2c_init(dev); i2c_config_gpios(dev); - /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */ - i2c_set_input_clk(dev, I2C_CLK); - - if (flags & I2C_FAST_MODE) { - ccr |= I2C_CCR_FS; - - if (flags & I2C_DUTY_16_9) { - /* Tlow/Thigh = 16/9 */ - ccr |= I2C_CCR_DUTY; - ccr |= STM32_PCLK1/(400000 * 25); - } else { - /* Tlow/Thigh = 2 */ - ccr |= STM32_PCLK1/(400000 * 3); - } - - trise = (300 * (I2C_CLK)/1000) + 1; - } else { - /* Tlow/Thigh = 1 */ - ccr = STM32_PCLK1/(100000 * 2); - trise = I2C_CLK + 1; - } - - /* Set minimum required value if CCR < 1*/ - if ((ccr & I2C_CCR_CCR) == 0) { - ccr |= 0x1; - } - - i2c_set_clk_control(dev, ccr); - i2c_set_trise(dev, trise); + /* Configure clock and rise time */ + _i2c_set_ccr_trise(dev, flags); /* Enable event and buffer interrupts */ nvic_irq_enable(dev->ev_nvic_line); diff --git a/libmaple/i2c_private.h b/libmaple/i2c_private.h index 4a0f01f..05a293c 100644 --- a/libmaple/i2c_private.h +++ b/libmaple/i2c_private.h @@ -43,4 +43,8 @@ struct i2c_dev; void _i2c_irq_handler(struct i2c_dev *dev); void _i2c_irq_error_handler(struct i2c_dev *dev); +/* Auxiliary procedure for enabling an I2C peripheral; `flags' as for + * i2c_master_enable(). */ +void _i2c_set_ccr_trise(i2c_dev *dev, uint32 flags); + #endif /* _LIBMAPLE_I2C_PRIVATE_H_ */ diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index 4e918ad..4c9af30 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -110,3 +110,39 @@ void _i2c_irq_priority_fixup(i2c_dev *dev) { nvic_irq_set_priority(dev->ev_nvic_line, 0); nvic_irq_set_priority(dev->er_nvic_line, 0); } + +void _i2c_set_ccr_trise(i2c_dev *dev, uint32 flags) { +#define I2C_CLK (STM32_PCLK1/1000000) + uint32 ccr = 0; + uint32 trise = 0; + + /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */ + i2c_set_input_clk(dev, I2C_CLK); + + if (flags & I2C_FAST_MODE) { + ccr |= I2C_CCR_FS; + + if (flags & I2C_DUTY_16_9) { + /* Tlow/Thigh = 16/9 */ + ccr |= I2C_CCR_DUTY; + ccr |= STM32_PCLK1/(400000 * 25); + } else { + /* Tlow/Thigh = 2 */ + ccr |= STM32_PCLK1/(400000 * 3); + } + + trise = (300 * (I2C_CLK)/1000) + 1; + } else { + /* Tlow/Thigh = 1 */ + ccr = STM32_PCLK1/(100000 * 2); + trise = I2C_CLK + 1; + } + + /* Set minimum required value if CCR < 1*/ + if ((ccr & I2C_CCR_CCR) == 0) { + ccr |= 0x1; + } + + i2c_set_clk_control(dev, ccr); + i2c_set_trise(dev, trise); +} -- cgit v1.2.3 From 9ba028ef647bc033e5ec078acd7de9d5c28432a9 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 16:30:16 -0400 Subject: STM32F1: i2c_config_gpios(): Do afio_remap() if we should. This should help avoid surprising some users. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/i2c.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index 4c9af30..5797940 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -44,6 +44,10 @@ i2c_dev* const I2C2 = &i2c2; */ void i2c_config_gpios(const i2c_dev *dev) { + if ((dev->clk_id == RCC_I2C1) && + (dev->sda_pin == 9) && (dev->scl_pin == 8)) { + afio_remap(AFIO_REMAP_I2C1); + } gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD); gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD); } -- cgit v1.2.3 From 001997b815e70f6a7707e765982b6f321afb961a Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 17:04:32 -0400 Subject: i2c_dev: deprecate .gpio_port. This won't work on F2, which at times has SDA and SCL on different ports (e.g. I2C3 SDA on PC9, SCL on PA8). Add .sda_port and .scl_port replacements, which are used when the now-deprecated .gpio_port is null. Use them correctly everywhere, with some new i2c_private.h helper functionality. Sigh. The F1 I2C code tries too hard to guess what you wanted; it's not porting well at all. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 16 +++++++-------- libmaple/i2c_private.h | 37 ++++++++++++++++++++++++++++++---- libmaple/include/libmaple/i2c_common.h | 19 ++++++++++++++++- libmaple/stm32f1/i2c.c | 28 ++++++++++++++++--------- 4 files changed, 77 insertions(+), 23 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 0e6a64c..3c92bef 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -120,29 +120,29 @@ void i2c_bus_reset(const i2c_dev *dev) { * Make sure the bus is free by clocking it until any slaves release the * bus. */ - while (!gpio_read_bit(dev->gpio_port, dev->sda_pin)) { + while (!gpio_read_bit(sda_port(dev), dev->sda_pin)) { /* Wait for any clock stretching to finish */ - while (!gpio_read_bit(dev->gpio_port, dev->scl_pin)) + while (!gpio_read_bit(scl_port(dev), dev->scl_pin)) ; delay_us(10); /* Pull low */ - gpio_write_bit(dev->gpio_port, dev->scl_pin, 0); + gpio_write_bit(scl_port(dev), dev->scl_pin, 0); delay_us(10); /* Release high again */ - gpio_write_bit(dev->gpio_port, dev->scl_pin, 1); + gpio_write_bit(scl_port(dev), dev->scl_pin, 1); delay_us(10); } /* Generate start then stop condition */ - gpio_write_bit(dev->gpio_port, dev->sda_pin, 0); + gpio_write_bit(sda_port(dev), dev->sda_pin, 0); delay_us(10); - gpio_write_bit(dev->gpio_port, dev->scl_pin, 0); + gpio_write_bit(scl_port(dev), dev->scl_pin, 0); delay_us(10); - gpio_write_bit(dev->gpio_port, dev->scl_pin, 1); + gpio_write_bit(scl_port(dev), dev->scl_pin, 1); delay_us(10); - gpio_write_bit(dev->gpio_port, dev->sda_pin, 1); + gpio_write_bit(sda_port(dev), dev->sda_pin, 1); } /** diff --git a/libmaple/i2c_private.h b/libmaple/i2c_private.h index 05a293c..5b79516 100644 --- a/libmaple/i2c_private.h +++ b/libmaple/i2c_private.h @@ -27,10 +27,15 @@ #ifndef _LIBMAPLE_I2C_PRIVATE_H_ #define _LIBMAPLE_I2C_PRIVATE_H_ -#define I2C_DEV(num, port, sda, scl) \ +#include + +/* For old-style definitions (SDA/SCL on same GPIO device) */ +#define I2C_DEV_OLD(num, port, sda, scl) \ { \ .regs = I2C##num##_BASE, \ .gpio_port = port, \ + .scl_port = NULL, \ + .sda_port = NULL, \ .sda_pin = sda, \ .scl_pin = scl, \ .clk_id = RCC_I2C##num, \ @@ -39,9 +44,33 @@ .state = I2C_STATE_DISABLED, \ } -struct i2c_dev; -void _i2c_irq_handler(struct i2c_dev *dev); -void _i2c_irq_error_handler(struct i2c_dev *dev); +/* For new-style definitions (SDA/SCL may be on different GPIO devices) */ +#define I2C_DEV_NEW(num, sdaport, sdabit, sclport, sclbit) \ + { \ + .regs = I2C##num##_BASE, \ + .gpio_port = NULL, \ + .scl_port = sclport, \ + .scl_pin = sclbit, \ + .sda_port = sdaport, \ + .sda_pin = sdabit, \ + .clk_id = RCC_I2C##num, \ + .ev_nvic_line = NVIC_I2C##num##_EV, \ + .er_nvic_line = NVIC_I2C##num##_ER, \ + .state = I2C_STATE_DISABLED, \ + } + +void _i2c_irq_handler(i2c_dev *dev); +void _i2c_irq_error_handler(i2c_dev *dev); + +struct gpio_dev; + +static inline struct gpio_dev* scl_port(const i2c_dev *dev) { + return (dev->gpio_port == NULL) ? dev->scl_port : dev->gpio_port; +} + +static inline struct gpio_dev* sda_port(const i2c_dev *dev) { + return (dev->gpio_port == NULL) ? dev->sda_port : dev->gpio_port; +} /* Auxiliary procedure for enabling an I2C peripheral; `flags' as for * i2c_master_enable(). */ diff --git a/libmaple/include/libmaple/i2c_common.h b/libmaple/include/libmaple/i2c_common.h index 2f36f80..5d99530 100644 --- a/libmaple/include/libmaple/i2c_common.h +++ b/libmaple/include/libmaple/i2c_common.h @@ -65,7 +65,24 @@ typedef struct i2c_dev { struct i2c_msg *msg; /**< Messages */ uint32 error_flags; /**< Error flags, set on I2C error condition */ volatile uint32 timestamp; /**< For internal use */ - struct gpio_dev *gpio_port; /**< SDA, SCL pins' GPIO port */ + + /** + * @brief Deprecated. Use .scl_port or .sda_port instead. + * If non-null, this will be used as SDA, SCL pins' GPIO port. If + * null, then .sda_port will be used for SDA, and .sda_port for + * SDA. */ + struct gpio_dev *gpio_port; + + /** + * @brief SDA GPIO device (but see .gpio_port). + */ + struct gpio_dev *sda_port; + + /** + * @brief SCL GPIO device (but see .gpio_port). + */ + struct gpio_dev *scl_port; + uint16 msgs_left; /**< Messages left */ uint8 sda_pin; /**< SDA bit on gpio_port */ uint8 scl_pin; /**< SCL bit on gpio_port */ diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index 5797940..d864464 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -31,8 +31,8 @@ * Devices */ -static i2c_dev i2c1 = I2C_DEV(1, &gpiob, 7, 6); -static i2c_dev i2c2 = I2C_DEV(2, &gpiob, 11, 10); +static i2c_dev i2c1 = I2C_DEV_OLD(1, &gpiob, 7, 6); +static i2c_dev i2c2 = I2C_DEV_OLD(2, &gpiob, 11, 10); /** STM32F1 I2C device 1 */ i2c_dev* const I2C1 = &i2c1; @@ -43,20 +43,28 @@ i2c_dev* const I2C2 = &i2c2; * Routines */ +static int i2c1_wants_remap(const i2c_dev *dev) { + /* Check if we've got I2C1 configured for SDA/SCL remap on PB9/PB8 */ + return (dev->clk_id == RCC_I2C1) && + (scl_port(dev)->clk_id == RCC_GPIOB) && + (sda_port(dev)->clk_id == RCC_GPIOB) && + (dev->sda_pin == 9) && + (dev->scl_pin == 8); +} + void i2c_config_gpios(const i2c_dev *dev) { - if ((dev->clk_id == RCC_I2C1) && - (dev->sda_pin == 9) && (dev->scl_pin == 8)) { + if (i2c1_wants_remap(dev)) { afio_remap(AFIO_REMAP_I2C1); } - gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD); - gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD); + gpio_set_mode(sda_port(dev), dev->sda_pin, GPIO_AF_OUTPUT_OD); + gpio_set_mode(scl_port(dev), dev->scl_pin, GPIO_AF_OUTPUT_OD); } void i2c_master_release_bus(const i2c_dev *dev) { - gpio_write_bit(dev->gpio_port, dev->scl_pin, 1); - gpio_write_bit(dev->gpio_port, dev->sda_pin, 1); - gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD); - gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD); + gpio_write_bit(scl_port(dev), dev->scl_pin, 1); + gpio_write_bit(sda_port(dev), dev->sda_pin, 1); + gpio_set_mode(scl_port(dev), dev->scl_pin, GPIO_OUTPUT_OD); + gpio_set_mode(sda_port(dev), dev->sda_pin, GPIO_OUTPUT_OD); } /* -- cgit v1.2.3 From c176248a4f7014bf83edf684e3a5a795efc3696e Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Thu, 21 Jun 2012 17:21:58 -0400 Subject: libmaple/stm32f1/i2c.c: Add Doxygen file header. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index d864464..3e0e146 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -24,6 +24,11 @@ * SOFTWARE. *****************************************************************************/ +/** + * @file libmaple/stm32f1/i2c.c + * @brief STM32F1 I2C support + */ + #include "i2c_private.h" #include -- cgit v1.2.3 From f94c9f659be11340b80476cec8c0f713e4bba02c Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 13:58:25 -0400 Subject: Add I2C example for MCP4725 DAC. Signed-off-by: Marti Bolivar --- examples/i2c-mcp4725-dac.cpp | 145 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 examples/i2c-mcp4725-dac.cpp diff --git a/examples/i2c-mcp4725-dac.cpp b/examples/i2c-mcp4725-dac.cpp new file mode 100644 index 0000000..e757bd1 --- /dev/null +++ b/examples/i2c-mcp4725-dac.cpp @@ -0,0 +1,145 @@ +// i2c-mcp4725-dac.cpp +// +// Written by Andrew Meyer +// Modified by Marti Bolivar +// +// Simple program showing how to control an MCP4725 DAC using the +// libmaple I2C interface. There's an MCP4725 breakout board available +// on SparkFun: +// +// http://www.sparkfun.com/products/8736 +// +// How to use: +// +// 1. Connect the DAC SDA and SCL pins to I2C2, with a pullup +// resistor (1 KOhm should work) to VCC. +// 2. Load the sketch and connect to SerialUSB. +// 3. Press the button. +// +// The program then makes sure the DAC is connected properly (during +// setup()), then has the DAC output a sawtooth wave (with loop()). + +#include +#include + +#define MCP_ADDR 0x60 +#define MCP_WRITE_DAC 0b01000000 +#define MCP_WRITE_EEPROM 0b01100000 +#define MCP_PD_NORMAL 0b00000000 +#define MCP_PD_1K 0b00000010 +#define MCP_PD_100K 0b00000100 +#define MCP_PD_500K 0b00000110 + +static uint8 write_msg_data[3]; +static i2c_msg write_msg; + +static uint8 read_msg_data[5]; +static i2c_msg read_msg; + +/* + * DAC control routines + */ + +void mcp_i2c_setup(void) { + write_msg.addr = MCP_ADDR; + write_msg.flags = 0; // write, 7 bit address + write_msg.length = sizeof(write_msg_data); + write_msg.xferred = 0; + write_msg.data = write_msg_data; + + read_msg.addr = MCP_ADDR; + read_msg.flags = I2C_MSG_READ; + read_msg.length = sizeof(read_msg_data); + read_msg.xferred = 0; + read_msg.data = read_msg_data; +} + +void mcp_write_val(uint16 val) { + write_msg_data[0] = MCP_WRITE_DAC | MCP_PD_NORMAL; + uint16 tmp = val >> 4; + write_msg_data[1] = tmp; + tmp = (val << 4) & 0x00FF; + write_msg_data[2] = tmp; + + i2c_master_xfer(I2C2, &write_msg, 1, 0); +} + +uint16 mcp_read_val() { + uint16 tmp = 0; + + i2c_master_xfer(I2C2, &read_msg, 1, 2); + + /* We don't care about the status and EEPROM bytes (0, 3, and 4). */ + tmp = (read_msg_data[1] << 4); + tmp += (read_msg_data[2] >> 4); + return tmp; +} + +int mcp_test() { + uint16 val; + uint16 test_val = 0x0101; + + SerialUSB.println("Testing the MCP4725..."); + /* Read the value of the register (should be 0x0800 if factory fresh) */ + val = mcp_read_val(); + SerialUSB.print("DAC Register = 0x"); + SerialUSB.println(val, HEX); + + mcp_write_val(test_val); + SerialUSB.print("Wrote 0x"); + SerialUSB.print(test_val, HEX); + SerialUSB.println(" to the DAC"); + + val = mcp_read_val(); + SerialUSB.print("DAC Register = 0x"); + SerialUSB.println(val, HEX); + + if (val != test_val) { + SerialUSB.println("ERROR: MCP4725 not responding correctly"); + return 0; + } + + SerialUSB.println("MCP4725 seems to be working"); + return 1; +} + +/* + * setup() and loop() + */ + +void setup() { + pinMode(BOARD_BUTTON_PIN, INPUT); + i2c_master_enable(I2C2, 0); + mcp_i2c_setup(); + + waitForButtonPress(); + ASSERT(mcp_test()); + + SerialUSB.println("Starting sawtooth wave"); +} + +void loop() { + static uint16 dout = 0; + + mcp_write_val(dout); + + dout += 50; + if (dout >= 32768) { + dout = 0; + } +} + +// -- init() and main() ------------------------------------------------------- + +__attribute__((constructor)) void premain() { + init(); +} + +int main(void) { + setup(); + + while (true) { + loop(); + } + return 0; +} -- cgit v1.2.3 From e397f7c18b775aacf40223a7cc91cba547e819e7 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 14:47:45 -0400 Subject: i2c-mcp4725-dac.cpp: Fix whitespace. Signed-off-by: Marti Bolivar --- examples/i2c-mcp4725-dac.cpp | 118 +++++++++++++++++++++---------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/examples/i2c-mcp4725-dac.cpp b/examples/i2c-mcp4725-dac.cpp index e757bd1..da9a34e 100644 --- a/examples/i2c-mcp4725-dac.cpp +++ b/examples/i2c-mcp4725-dac.cpp @@ -41,66 +41,66 @@ static i2c_msg read_msg; */ void mcp_i2c_setup(void) { - write_msg.addr = MCP_ADDR; - write_msg.flags = 0; // write, 7 bit address - write_msg.length = sizeof(write_msg_data); - write_msg.xferred = 0; - write_msg.data = write_msg_data; - - read_msg.addr = MCP_ADDR; - read_msg.flags = I2C_MSG_READ; - read_msg.length = sizeof(read_msg_data); - read_msg.xferred = 0; - read_msg.data = read_msg_data; + write_msg.addr = MCP_ADDR; + write_msg.flags = 0; // write, 7 bit address + write_msg.length = sizeof(write_msg_data); + write_msg.xferred = 0; + write_msg.data = write_msg_data; + + read_msg.addr = MCP_ADDR; + read_msg.flags = I2C_MSG_READ; + read_msg.length = sizeof(read_msg_data); + read_msg.xferred = 0; + read_msg.data = read_msg_data; } void mcp_write_val(uint16 val) { - write_msg_data[0] = MCP_WRITE_DAC | MCP_PD_NORMAL; - uint16 tmp = val >> 4; - write_msg_data[1] = tmp; - tmp = (val << 4) & 0x00FF; - write_msg_data[2] = tmp; + write_msg_data[0] = MCP_WRITE_DAC | MCP_PD_NORMAL; + uint16 tmp = val >> 4; + write_msg_data[1] = tmp; + tmp = (val << 4) & 0x00FF; + write_msg_data[2] = tmp; - i2c_master_xfer(I2C2, &write_msg, 1, 0); + i2c_master_xfer(I2C2, &write_msg, 1, 0); } uint16 mcp_read_val() { - uint16 tmp = 0; + uint16 tmp = 0; - i2c_master_xfer(I2C2, &read_msg, 1, 2); + i2c_master_xfer(I2C2, &read_msg, 1, 2); - /* We don't care about the status and EEPROM bytes (0, 3, and 4). */ - tmp = (read_msg_data[1] << 4); - tmp += (read_msg_data[2] >> 4); - return tmp; + /* We don't care about the status and EEPROM bytes (0, 3, and 4). */ + tmp = (read_msg_data[1] << 4); + tmp += (read_msg_data[2] >> 4); + return tmp; } int mcp_test() { - uint16 val; - uint16 test_val = 0x0101; - - SerialUSB.println("Testing the MCP4725..."); - /* Read the value of the register (should be 0x0800 if factory fresh) */ - val = mcp_read_val(); - SerialUSB.print("DAC Register = 0x"); - SerialUSB.println(val, HEX); - - mcp_write_val(test_val); - SerialUSB.print("Wrote 0x"); - SerialUSB.print(test_val, HEX); - SerialUSB.println(" to the DAC"); - - val = mcp_read_val(); - SerialUSB.print("DAC Register = 0x"); - SerialUSB.println(val, HEX); - - if (val != test_val) { - SerialUSB.println("ERROR: MCP4725 not responding correctly"); - return 0; - } + uint16 val; + uint16 test_val = 0x0101; + + SerialUSB.println("Testing the MCP4725..."); + /* Read the value of the register (should be 0x0800 if factory fresh) */ + val = mcp_read_val(); + SerialUSB.print("DAC Register = 0x"); + SerialUSB.println(val, HEX); + + mcp_write_val(test_val); + SerialUSB.print("Wrote 0x"); + SerialUSB.print(test_val, HEX); + SerialUSB.println(" to the DAC"); + + val = mcp_read_val(); + SerialUSB.print("DAC Register = 0x"); + SerialUSB.println(val, HEX); + + if (val != test_val) { + SerialUSB.println("ERROR: MCP4725 not responding correctly"); + return 0; + } - SerialUSB.println("MCP4725 seems to be working"); - return 1; + SerialUSB.println("MCP4725 seems to be working"); + return 1; } /* @@ -108,25 +108,25 @@ int mcp_test() { */ void setup() { - pinMode(BOARD_BUTTON_PIN, INPUT); - i2c_master_enable(I2C2, 0); - mcp_i2c_setup(); + pinMode(BOARD_BUTTON_PIN, INPUT); + i2c_master_enable(I2C2, 0); + mcp_i2c_setup(); - waitForButtonPress(); - ASSERT(mcp_test()); + waitForButtonPress(); + ASSERT(mcp_test()); - SerialUSB.println("Starting sawtooth wave"); + SerialUSB.println("Starting sawtooth wave"); } void loop() { - static uint16 dout = 0; + static uint16 dout = 0; - mcp_write_val(dout); + mcp_write_val(dout); - dout += 50; - if (dout >= 32768) { - dout = 0; - } + dout += 50; + if (dout >= 32768) { + dout = 0; + } } // -- init() and main() ------------------------------------------------------- -- cgit v1.2.3 From 929ef7192a497c7b6dc9d72c8bf455dc152dffbc Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 14:41:48 -0400 Subject: : Add I2C_CCR_DUTY bit value definitions. Signed-off-by: Marti Bolivar --- libmaple/include/libmaple/i2c.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index f7821af..ff1c313 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -181,7 +181,9 @@ typedef struct i2c_msg { /* Clock control register */ #define I2C_CCR_FS (1U << 15) // Fast mode selection -#define I2C_CCR_DUTY (1U << 14) // 16/9 duty ratio +#define I2C_CCR_DUTY (1U << 14) // Fast mode duty cycle +#define I2C_CCR_DUTY_2_1 (0U << 14) // Fast mode duty: 2/1 +#define I2C_CCR_DUTY_16_9 (1U << 14) // Fast mode duty: 16/9 #define I2C_CCR_CCR 0xFFF // Clock control bits /* -- cgit v1.2.3 From 7645bf2d485a74e11ae55fe1f281ff68fc49290f Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 14:44:15 -0400 Subject: I2C: Move CCR/TRISE config helper back to libmaple/i2c.c. We can implement it in terms of _i2c_bus_clk() instead of hard-coding STM32_PCLK1. This might be overkill, since I2C peripherals are slow and thus likely to be on APB1 for all STM32 devices (that is the case for F2/F4, for instance), but if we're going to have _i2c_bus_clk(), we might as well respect it. Signed-off-by: Marti Bolivar --- libmaple/i2c.c | 42 +++++++++++++++++++++++++++++++++++++++++- libmaple/stm32f1/i2c.c | 36 ------------------------------------ 2 files changed, 41 insertions(+), 37 deletions(-) diff --git a/libmaple/i2c.c b/libmaple/i2c.c index 3c92bef..9c93d3f 100644 --- a/libmaple/i2c.c +++ b/libmaple/i2c.c @@ -47,6 +47,7 @@ static inline int32 wait_for_state_change(i2c_dev *dev, i2c_state state, uint32 timeout); +static void set_ccr_trise(i2c_dev *dev, uint32 flags); /** * @brief Fill data register with slave address @@ -190,7 +191,7 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) { i2c_config_gpios(dev); /* Configure clock and rise time */ - _i2c_set_ccr_trise(dev, flags); + set_ccr_trise(dev, flags); /* Enable event and buffer interrupts */ nvic_irq_enable(dev->ev_nvic_line); @@ -467,3 +468,42 @@ void _i2c_irq_error_handler(i2c_dev *dev) { i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR); dev->state = I2C_STATE_ERROR; } + +/* + * CCR/TRISE configuration helper + */ +static void set_ccr_trise(i2c_dev *dev, uint32 flags) { + uint32 ccr = 0; + uint32 trise = 0; + uint32 clk_mhz = _i2c_bus_clk(dev); + uint32 clk_hz = clk_mhz * (1000 * 1000); + + i2c_set_input_clk(dev, clk_mhz); + + if (flags & I2C_FAST_MODE) { + ccr |= I2C_CCR_FS; + + if (flags & I2C_DUTY_16_9) { + /* Tlow/Thigh = 16/9 */ + ccr |= I2C_CCR_DUTY_16_9; + ccr |= clk_hz / (400000 * 25); + } else { + /* Tlow/Thigh = 2 */ + ccr |= clk_hz / (400000 * 3); + } + + trise = (300 * clk_mhz / 1000) + 1; + } else { + /* Tlow/Thigh = 1 */ + ccr = clk_hz / (100000 * 2); + trise = clk_mhz + 1; + } + + /* Set minimum required value if CCR < 1*/ + if ((ccr & I2C_CCR_CCR) == 0) { + ccr |= 0x1; + } + + i2c_set_clk_control(dev, ccr); + i2c_set_trise(dev, trise); +} diff --git a/libmaple/stm32f1/i2c.c b/libmaple/stm32f1/i2c.c index 3e0e146..8439793 100644 --- a/libmaple/stm32f1/i2c.c +++ b/libmaple/stm32f1/i2c.c @@ -127,39 +127,3 @@ void _i2c_irq_priority_fixup(i2c_dev *dev) { nvic_irq_set_priority(dev->ev_nvic_line, 0); nvic_irq_set_priority(dev->er_nvic_line, 0); } - -void _i2c_set_ccr_trise(i2c_dev *dev, uint32 flags) { -#define I2C_CLK (STM32_PCLK1/1000000) - uint32 ccr = 0; - uint32 trise = 0; - - /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */ - i2c_set_input_clk(dev, I2C_CLK); - - if (flags & I2C_FAST_MODE) { - ccr |= I2C_CCR_FS; - - if (flags & I2C_DUTY_16_9) { - /* Tlow/Thigh = 16/9 */ - ccr |= I2C_CCR_DUTY; - ccr |= STM32_PCLK1/(400000 * 25); - } else { - /* Tlow/Thigh = 2 */ - ccr |= STM32_PCLK1/(400000 * 3); - } - - trise = (300 * (I2C_CLK)/1000) + 1; - } else { - /* Tlow/Thigh = 1 */ - ccr = STM32_PCLK1/(100000 * 2); - trise = I2C_CLK + 1; - } - - /* Set minimum required value if CCR < 1*/ - if ((ccr & I2C_CCR_CCR) == 0) { - ccr |= 0x1; - } - - i2c_set_clk_control(dev, ccr); - i2c_set_trise(dev, trise); -} -- cgit v1.2.3 From 556aea4bc76da127ac2aaf2655af1fe5cbc19bd2 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 15:27:52 -0400 Subject: libmaple/util.c: Add FIXMEs. Signed-off-by: Marti Bolivar --- libmaple/util.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libmaple/util.c b/libmaple/util.c index ff100fe..0c066d6 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -37,6 +37,8 @@ #include #include +/* FIXME [0.0.13] put this stuff back in some form. Move to Wirish? */ + /* Failed ASSERT()s send out a message using this USART config. */ #ifndef ERROR_USART #define ERROR_USART USART2 -- cgit v1.2.3 From 30b2d02c01baae1bb21c8e32a2ff646b01c555cb Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 15:30:46 -0400 Subject: stm32f1: gpio.h: Add another hack mode macro. Signed-off-by: Marti Bolivar --- libmaple/stm32f1/include/series/gpio.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libmaple/stm32f1/include/series/gpio.h b/libmaple/stm32f1/include/series/gpio.h index 2f96a08..aecf911 100644 --- a/libmaple/stm32f1/include/series/gpio.h +++ b/libmaple/stm32f1/include/series/gpio.h @@ -137,6 +137,7 @@ typedef enum gpio_pin_mode { /* Hacks for F2: */ #define GPIO_MODE_ANALOG GPIO_INPUT_ANALOG +#define GPIO_MODE_OUTPUT GPIO_OUTPUT_PP /* * AFIO register map -- cgit v1.2.3 From 924505a95ca4e62b46032fdeab76abd4b860246d Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Fri, 22 Jun 2012 17:40:25 -0400 Subject: Bring back throb(). Signed-off-by: Marti Bolivar --- libmaple/util.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libmaple/util.c b/libmaple/util.c index 0c066d6..592037a 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -149,13 +149,13 @@ void abort() { * @sideeffect Sets output push-pull on ERROR_LED_PIN. */ void throb(void) { -#if 0 +#ifdef HAVE_ERROR_LED int32 slope = 1; uint32 CC = 0x0000; uint32 TOP_CNT = 0x0200; uint32 i = 0; - gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_OUTPUT_PP); + gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_MODE_OUTPUT); /* Error fade. */ while (1) { if (CC == TOP_CNT) { -- cgit v1.2.3 From 0d7471bb40f3ad048c624700dc5d1b1d776feb43 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 26 Jun 2012 16:57:11 -0400 Subject: Bring back the libraries. Signed-off-by: Marti Bolivar --- Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 9e8c796..4b82958 100644 --- a/Makefile +++ b/Makefile @@ -74,13 +74,13 @@ endif LIBMAPLE_MODULES += $(SRCROOT)/libmaple/usb # The USB module is kept separate LIBMAPLE_MODULES += $(LIBMAPLE_MODULE_SERIES) # STM32 series submodule in libmaple LIBMAPLE_MODULES += $(SRCROOT)/wirish -# Official libraries: -# LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo -# LIBMAPLE_MODULES += $(SRCROOT)/libraries/LiquidCrystal -# LIBMAPLE_MODULES += $(SRCROOT)/libraries/Wire +Official libraries: +LIBMAPLE_MODULES += $(SRCROOT)/libraries/Servo +LIBMAPLE_MODULES += $(SRCROOT)/libraries/LiquidCrystal +LIBMAPLE_MODULES += $(SRCROOT)/libraries/Wire -# Experimental libraries: -# LIBMAPLE_MODULES += $(SRCROOT)/libraries/FreeRTOS +Experimental libraries: +LIBMAPLE_MODULES += $(SRCROOT)/libraries/FreeRTOS # Call each module's rules.mk: $(foreach m,$(LIBMAPLE_MODULES),$(eval $(call LIBMAPLE_MODULE_template,$(m)))) -- cgit v1.2.3 From 1700847e991e90831ec691045464943b249abc89 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 26 Jun 2012 16:59:03 -0400 Subject: util.c: Fix Doxygen header. Signed-off-by: Marti Bolivar --- libmaple/util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libmaple/util.c b/libmaple/util.c index 592037a..88da075 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -27,7 +27,7 @@ /** * @file libmaple/util.c * @brief Utility procedures for debugging, mostly an error LED fade - * and messages dumped over a UART for failed asserts. + * and messages dumped over a UART for failed asserts. */ #include -- cgit v1.2.3 From fbbf35ee079d1c979909981c95132ba7eaca7215 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 26 Jun 2012 18:03:40 -0400 Subject: Bring back and fix up util.c functionality. Rip out the existing nonportable pieces, and shove them under wirish/stm32f1, using weak symbols so users who only want libmaple proper don't end up with build errors. Add stubbed-out (and only partially functional) definitions for F2 targets under wirish/stm32f2. The behavior on F103 targets is the same as it was before (though the assertion framework has always been broken and badly needs replacement, that awaits another commit). We additionally now skip re-enabling USB on F1 targets without USB, to make things work on value line MCUs. Signed-off-by: Marti Bolivar --- libmaple/util.c | 119 ++++++++++++++++---------------------------- wirish/rules.mk | 1 + wirish/stm32f1/util_hooks.c | 83 ++++++++++++++++++++++++++++++ wirish/stm32f2/util_hooks.c | 45 +++++++++++++++++ 4 files changed, 171 insertions(+), 77 deletions(-) create mode 100644 wirish/stm32f1/util_hooks.c create mode 100644 wirish/stm32f2/util_hooks.c diff --git a/libmaple/util.c b/libmaple/util.c index 88da075..2ee5ede 100644 --- a/libmaple/util.c +++ b/libmaple/util.c @@ -26,27 +26,17 @@ /** * @file libmaple/util.c - * @brief Utility procedures for debugging, mostly an error LED fade - * and messages dumped over a UART for failed asserts. + * @brief Utility procedures for debugging */ #include #include #include #include -#include -#include -/* FIXME [0.0.13] put this stuff back in some form. Move to Wirish? */ - -/* Failed ASSERT()s send out a message using this USART config. */ -#ifndef ERROR_USART -#define ERROR_USART USART2 -#define ERROR_USART_CLK_SPEED STM32_PCLK1 -#define ERROR_USART_BAUD 9600 -#define ERROR_TX_PORT GPIOA -#define ERROR_TX_PIN 2 -#endif +/* (Undocumented) hooks used by Wirish to direct our behavior here */ +extern __weak void __lm_error(void); +extern __weak usart_dev* __lm_enable_error_usart(void); /* If you define ERROR_LED_PORT and ERROR_LED_PIN, then a failed * ASSERT() will also throb() an LED connected to that port and pin. @@ -55,100 +45,75 @@ #define HAVE_ERROR_LED #endif -/** - * @brief Disables all peripheral interrupts except USB and fades the - * error LED. - */ /* (Called from exc.S with global interrupts disabled.) */ -void __error(void) { - /* Turn off peripheral interrupts */ - nvic_irq_disable_all(); - - /* /\* Turn off timers *\/ */ - /* timer_disable_all(); */ - - /* /\* Turn off ADC *\/ */ - /* adc_disable_all(); */ - - /* /\* Turn off all USARTs *\/ */ - /* usart_disable_all(); */ - - /* /\* Turn the USB interrupt back on so the bootloader keeps on functioning *\/ */ - /* nvic_irq_enable(NVIC_USB_HP_CAN_TX); */ - /* nvic_irq_enable(NVIC_USB_LP_CAN_RX0); */ - +__attribute__((noreturn)) void __error(void) { + if (__lm_error) { + __lm_error(); + } /* Reenable global interrupts */ nvic_globalirq_enable(); throb(); } -/** - * @brief Enable the error USART for writing. - * @sideeffect Configures ERROR_USART appropriately for writing. - */ -void _enable_error_usart() { - /* gpio_set_mode(ERROR_TX_PORT, ERROR_TX_PIN, GPIO_AF_OUTPUT_PP); */ - /* usart_init(ERROR_USART); */ - /* usart_set_baud_rate(ERROR_USART, ERROR_USART_CLK_SPEED, ERROR_USART_BAUD); */ -} - -/** - * @brief Print an error message on a UART upon a failed assertion - * and throb the error LED, if there is one defined. +/* + * Print an error message on a UART upon a failed assertion (if one is + * available), and punt to __error(). + * * @param file Source file of failed assertion * @param line Source line of failed assertion * @param exp String representation of failed assertion * @sideeffect Turns of all peripheral interrupts except USB. */ void _fail(const char* file, int line, const char* exp) { - /* Initialize the error USART */ - /* _enable_error_usart(); */ - - /* /\* Print failed assert message *\/ */ - /* usart_putstr(ERROR_USART, "ERROR: FAILED ASSERT("); */ - /* usart_putstr(ERROR_USART, exp); */ - /* usart_putstr(ERROR_USART, "): "); */ - /* usart_putstr(ERROR_USART, file); */ - /* usart_putstr(ERROR_USART, ": "); */ - /* usart_putudec(ERROR_USART, line); */ - /* usart_putc(ERROR_USART, '\n'); */ - /* usart_putc(ERROR_USART, '\r'); */ - + if (__lm_enable_error_usart) { + /* Initialize the error USART */ + usart_dev *err_usart = __lm_enable_error_usart(); + + /* Print failed assert message */ + usart_putstr(err_usart, "ERROR: FAILED ASSERT("); + usart_putstr(err_usart, exp); + usart_putstr(err_usart, "): "); + usart_putstr(err_usart, file); + usart_putstr(err_usart, ": "); + usart_putudec(err_usart, line); + usart_putc(err_usart, '\n'); + usart_putc(err_usart, '\r'); + } /* Shutdown and error fade */ __error(); } -/** - * @brief Provide an __assert_func handler to libc so that calls to assert() get - * redirected to _fail. +/* + * Provide an __assert_func handler to libc so that calls to assert() + * get redirected to _fail. */ void __assert_func(const char* file, int line, const char* method, const char* expression) { _fail(file, line, expression); } -/** - * @brief Provide an abort() implementation that aborts execution and enters an - * error state with the throbbing LED indicator. +/* + * Provide an abort() implementation that aborts execution and punts + * to __error(). */ void abort() { - /* /\* Initialize the error USART *\/ */ - /* _enable_error_usart(); */ - - /* /\* Print abort message. *\/ */ - /* usart_putstr(ERROR_USART, "ERROR: PROGRAM ABORTED VIA abort()\n\r"); */ + if (__lm_enable_error_usart) { + /* Initialize the error USART */ + usart_dev *err_usart = __lm_enable_error_usart(); + /* Print abort message. */ + usart_putstr(err_usart, "ERROR: PROGRAM ABORTED VIA abort()\r\n"); + } - /* /\* Shutdown and error fade *\/ */ - /* __error(); */ - while (1) - ; + /* Shutdown and error fade */ + __error(); } +/* This was public as of v0.0.12, so we've got to keep it public. */ /** * @brief Fades the error LED on and off * @sideeffect Sets output push-pull on ERROR_LED_PIN. */ -void throb(void) { +__attribute__((noreturn)) void throb(void) { #ifdef HAVE_ERROR_LED int32 slope = 1; uint32 CC = 0x0000; diff --git a/wirish/rules.mk b/wirish/rules.mk index 5138c82..f895213 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -21,6 +21,7 @@ CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) $(WIRISH_INCLUDES) -I$(d) sSRCS_$(d) := start.S cSRCS_$(d) := start_c.c cSRCS_$(d) += syscalls.c +cSRCS_$(d) += $(MCU_SERIES)/util_hooks.c cppSRCS_$(d) := boards.cpp cppSRCS_$(d) += cxxabi-compat.cpp cppSRCS_$(d) += ext_interrupts.cpp diff --git a/wirish/stm32f1/util_hooks.c b/wirish/stm32f1/util_hooks.c new file mode 100644 index 0000000..8f798a1 --- /dev/null +++ b/wirish/stm32f1/util_hooks.c @@ -0,0 +1,83 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung (from libmaple/util.c). + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* + * STM32F1 implementations for libmaple/util.c hooks + * + * These need more love and attention before being made public API + * (this includes being easily overridable by user code). + */ + +#include +#include +#include +#include +#include +#include + +/* Failed ASSERT()s send out a message using this USART config. */ +#ifndef ERROR_USART +#define ERROR_USART USART2 +#define ERROR_USART_BAUD 9600 +#define ERROR_TX_PORT GPIOA +#define ERROR_TX_PIN 2 +#endif + +/* + * Disables all peripheral interrupts except USB (when available), + * turns off commonly-used peripherals. Called by __error() with + * global interrupts disabled. + */ +void __lm_error(void) { + /* Turn off peripheral interrupts */ + nvic_irq_disable_all(); + + /* Turn off timers */ + timer_disable_all(); + + /* Turn off ADC */ + adc_disable_all(); + + /* Turn off all USARTs */ + usart_disable_all(); + +#if STM32_HAVE_USB + /* Turn the USB interrupt back on so the bootloader keeps on functioning */ + nvic_irq_enable(NVIC_USB_HP_CAN_TX); + nvic_irq_enable(NVIC_USB_LP_CAN_RX0); +#endif +} + +/* + * Enable the error USART for writing. + */ +usart_dev* __lm_enable_error_usart() { + gpio_set_mode(ERROR_TX_PORT, ERROR_TX_PIN, GPIO_AF_OUTPUT_PP); + usart_init(ERROR_USART); + usart_set_baud_rate(ERROR_USART, USART_USE_PCLK, ERROR_USART_BAUD); + return ERROR_USART; +} diff --git a/wirish/stm32f2/util_hooks.c b/wirish/stm32f2/util_hooks.c new file mode 100644 index 0000000..1b519ab --- /dev/null +++ b/wirish/stm32f2/util_hooks.c @@ -0,0 +1,45 @@ +/****************************************************************************** + * The MIT License + * + * Copyright (c) 2012 LeafLabs, LLC. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + *****************************************************************************/ + +/* + * STM32F2 implementations for libmaple util.c hooks + * FIXME these are just minimal stubs + */ + +#include + +/* + * Disables all peripheral interrupts. Called by __error() with global + * interrupts disabled. + */ +void __lm_error(void) { + nvic_irq_disable_all(); +} + +/* + * Enable the error USART for writing. + */ +/* usart_dev* __lm_enable_error_usart(void) { (TODO) } */ -- cgit v1.2.3 From c6073e4886da4606679bc3e9d770c9cff9390597 Mon Sep 17 00:00:00 2001 From: Marti Bolivar Date: Tue, 26 Jun 2012 18:13:12 -0400 Subject: STM32F1: Bring back HardwareSPI. We're going to merge into master without F2 support for this. Signed-off-by: Marti Bolivar --- wirish/include/wirish/wirish.h | 6 +++++- wirish/rules.mk | 3 +-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/wirish/include/wirish/wirish.h b/wirish/include/wirish/wirish.h index 360b502..4ebd66f 100644 --- a/wirish/include/wirish/wirish.h +++ b/wirish/include/wirish/wirish.h @@ -34,6 +34,8 @@ #ifndef _WIRISH_WIRISH_H_ #define _WIRISH_WIRISH_H_ +#include + #include #include #include @@ -42,7 +44,9 @@ #include #include #include -/* FIXME put this back when you can #include */ +#if STM32_MCU_SERIES == STM32_SERIES_F1 /* FIXME [0.0.13?] port to F2 */ +#include +#endif #include #include #include diff --git a/wirish/rules.mk b/wirish/rules.mk index f895213..1cac74a 100644 --- a/wirish/rules.mk +++ b/wirish/rules.mk @@ -31,6 +31,7 @@ cppSRCS_$(d) += Print.cpp cppSRCS_$(d) += pwm.cpp ifeq ($(MCU_SERIES), stm32f1) cppSRCS_$(d) += usb_serial.cpp # HACK: this is currently STM32F1 only. +cppSRCS_$(d) += HardwareSPI.cpp # FIXME: port to F2 and fix wirish.h endif cppSRCS_$(d) += wirish_analog.cpp cppSRCS_$(d) += wirish_digital.cpp @@ -41,8 +42,6 @@ cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp cppSRCS_$(d) += $(MCU_SERIES)/wirish_debug.cpp cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp -# TODO: revise these appropriately for F2 and put them back in: -# HardwareSPI.cpp sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%) cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%) -- cgit v1.2.3