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-rw-r--r--wirish/HardwareTimer.cpp11
-rw-r--r--wirish/boards.cpp476
-rw-r--r--wirish/boards.h416
-rw-r--r--wirish/comm/HardwareSerial.cpp14
-rw-r--r--wirish/comm/HardwareSerial.h4
-rw-r--r--wirish/ext_interrupts.cpp (renamed from wirish/ext_interrupts.c)67
-rw-r--r--wirish/ext_interrupts.h11
-rw-r--r--wirish/io.h27
-rw-r--r--wirish/native_sram.cpp45
-rw-r--r--wirish/native_sram.h43
-rw-r--r--wirish/pwm.cpp (renamed from wirish/pwm.c)0
-rw-r--r--wirish/pwm.h13
-rw-r--r--wirish/rules.mk33
-rw-r--r--wirish/time.cpp (renamed from wirish/time.c)0
-rw-r--r--wirish/time.h9
-rw-r--r--wirish/wirish.cpp (renamed from wirish/wirish.c)8
-rw-r--r--wirish/wirish.h16
-rw-r--r--wirish/wirish_analog.cpp (renamed from wirish/wirish_analog.c)0
-rw-r--r--wirish/wirish_digital.cpp (renamed from wirish/wirish_digital.c)29
-rw-r--r--wirish/wirish_math.h9
-rw-r--r--wirish/wirish_shift.cpp (renamed from wirish/wirish_shift.c)0
21 files changed, 705 insertions, 526 deletions
diff --git a/wirish/HardwareTimer.cpp b/wirish/HardwareTimer.cpp
index 0f8bec6..04d1c76 100644
--- a/wirish/HardwareTimer.cpp
+++ b/wirish/HardwareTimer.cpp
@@ -89,7 +89,7 @@ uint16 HardwareTimer::setPeriod(uint32 microseconds) {
return this->getOverflow();
}
-inline void HardwareTimer::setChannelMode(int channel, TimerMode mode) {
+void HardwareTimer::setChannelMode(int channel, TimerMode mode) {
timer_set_mode(this->timerNum, channel, mode);
}
@@ -109,7 +109,7 @@ void HardwareTimer::setChannel4Mode(TimerMode mode) {
this->setChannelMode(4, mode);
}
-inline uint16 HardwareTimer::getCompare(int channel) {
+uint16 HardwareTimer::getCompare(int channel) {
return timer_get_compare_value(this->timerNum, channel);
}
@@ -129,7 +129,7 @@ uint16 HardwareTimer::getCompare4() {
return this->getCompare(4);
}
-inline void HardwareTimer::setCompare(int channel, uint16 val) {
+void HardwareTimer::setCompare(int channel, uint16 val) {
uint16 ovf = this->getOverflow();
timer_set_compare_value(this->timerNum, channel, min(val, ovf));
}
@@ -150,7 +150,7 @@ void HardwareTimer::setCompare4(uint16 val) {
this->setCompare(4, val);
}
-inline void HardwareTimer::attachInterrupt(int channel, voidFuncPtr handler) {
+void HardwareTimer::attachInterrupt(int channel, voidFuncPtr handler) {
timer_attach_interrupt(this->timerNum, channel, handler);
}
@@ -170,7 +170,7 @@ void HardwareTimer::attachCompare4Interrupt(voidFuncPtr handler) {
this->attachInterrupt(4, handler);
}
-inline void HardwareTimer::detachInterrupt(int channel) {
+void HardwareTimer::detachInterrupt(int channel) {
timer_detach_interrupt(this->timerNum, channel);
}
@@ -194,7 +194,6 @@ void HardwareTimer::generateUpdate(void) {
timer_generate_update(this->timerNum);
}
-
HardwareTimer Timer1(TIMER1);
HardwareTimer Timer2(TIMER2);
HardwareTimer Timer3(TIMER3);
diff --git a/wirish/boards.cpp b/wirish/boards.cpp
new file mode 100644
index 0000000..1256ba1
--- /dev/null
+++ b/wirish/boards.cpp
@@ -0,0 +1,476 @@
+#include "boards.h"
+
+// think of the poor column numbers
+#define ADCx ADC_INVALID
+#define TIMERx TIMER_INVALID
+
+#if defined(BOARD_maple)
+
+PinMapping PIN_MAP[NR_GPIO_PINS] = {
+ /* D0/PA3 */
+ {GPIOA, 3, 3, TIMER2_CH4_CCR, TIMER2, 4, AFIO_EXTI_PA},
+ /* D1/PA2 */
+ {GPIOA, 2, 2, TIMER2_CH3_CCR, TIMER2, 3, AFIO_EXTI_PA},
+ /* D2/PA0 */
+ {GPIOA, 0, 0, TIMER2_CH1_CCR, TIMER2, 1, AFIO_EXTI_PA},
+ /* D3/PA1 */
+ {GPIOA, 1, 1, TIMER2_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA},
+ /* D4/PB5 */
+ {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D5/PB6 */
+ {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB},
+ /* D6/PA8 */
+ {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA},
+ /* D7/PA9 */
+ {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER1, 2, AFIO_EXTI_PA},
+ /* D8/PA10 */
+ {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA},
+ /* D9/PB7 */
+ {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB},
+ /* D10/PA4 */
+ {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D11/PA7 */
+ {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA},
+ /* D12/PA6 */
+ {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA},
+ /* D13/PA5 */
+ {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D14/PB8 */
+ {GPIOB, 8, ADCx, TIMER4_CH3_CCR, TIMER4, 3, AFIO_EXTI_PB},
+
+ /* Little header */
+
+ /* D15/PC0 */
+ {GPIOC, 0, 10, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D16/PC1 */
+ {GPIOC, 1, 11, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D17/PC2 */
+ {GPIOC, 2, 12, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D18/PC3 */
+ {GPIOC, 3, 13, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D19/PC4 */
+ {GPIOC, 4, 14, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D20/PC5 */
+ {GPIOC, 5, 15, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+
+ /* External header */
+
+ /* D21/PC13 */
+ {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D22/PC14 */
+ {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D23/PC15 */
+ {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D24/PB9 */
+ {GPIOB, 9, ADCx, TIMER4_CH4_CCR, TIMER4, 4, AFIO_EXTI_PB},
+ /* D25/PD2 */
+ {GPIOD, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D26/PC10 */
+ {GPIOC, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D27/PB0 */
+ {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB},
+ /* D28/PB1 */
+ {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB},
+ /* D29/PB10 */
+ {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D30/PB11 */
+ {GPIOB, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D31/PB12 */
+ {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D32/PB13 */
+ {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D33/PB14 */
+ {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D34/PB15 */
+ {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D35/PC6 */
+ {GPIOC, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D36/PC7 */
+ {GPIOC, 7, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D37/PC8 */
+ {GPIOC, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D38/PC9 (BUT) */
+ {GPIOC, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC}
+};
+
+#elif defined(BOARD_maple_native)
+
+PinMapping PIN_MAP[NR_GPIO_PINS] = {
+ /* Top header */
+
+ /* D0/PB10 */
+ {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D1/PB2 */
+ {GPIOB, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D2/PB12 */
+ {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D3/PB13 */
+ {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D4/PB14 */
+ {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D5/PB15 */
+ {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D6/PC0 */
+ {GPIOC, 0, 10, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D7/PC1 */
+ {GPIOC, 1, 11, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D8/PC2 */
+ {GPIOC, 2, 12, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D9/PC3 */
+ {GPIOC, 3, 13, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D10/PC4 */
+ {GPIOC, 4, 14, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D11/PC5 */
+ {GPIOC, 5, 15, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D12/PC6 */
+ {GPIOC, 6, ADCx, TIMER8_CH1_CCR, TIMER8, 1, AFIO_EXTI_PC},
+ /* D13/PC7 */
+ {GPIOC, 7, ADCx, TIMER8_CH2_CCR, TIMER8, 2, AFIO_EXTI_PC},
+ /* D14/PC8 */
+ {GPIOC, 8, ADCx, TIMER8_CH3_CCR, TIMER8, 3, AFIO_EXTI_PC},
+ /* D15/PC9 */
+ {GPIOC, 9, ADCx, TIMER8_CH4_CCR, TIMER8, 4, AFIO_EXTI_PC},
+ /* D16/PC10 */
+ {GPIOC, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D17/PC11 */
+ {GPIOC, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D18/PC12 */
+ {GPIOC, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D19/PC13 */
+ {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D20/PC14 */
+ {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D21/PC15 */
+ {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D22/PA8 */
+ {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA},
+ /* D23/PA9 */
+ {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER1, 2, AFIO_EXTI_PA},
+ /* D24/PA10 */
+ {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA},
+ /* D25/PB9 */
+ {GPIOB, 9, ADCx, TIMER4_CH4_CCR, TIMER4, 4, AFIO_EXTI_PB},
+
+ /* Bottom header */
+
+ /* D26/PD2 */
+ {GPIOD, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D27/PD3 */
+ {GPIOD, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D28/PD6 */
+ {GPIOD, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D29/PG11 */
+ {GPIOG, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D30/PG12 */
+ {GPIOG, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D31/PG13 */
+ {GPIOG, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D32/PG14 */
+ {GPIOG, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D33/PG8 */
+ {GPIOG, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D34/PG7 */
+ {GPIOG, 7, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D35/PG6 */
+ {GPIOG, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D36/PB5 */
+ {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D37/PB6 */
+ {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB},
+ /* D38/PB7 */
+ {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB},
+ /* D39/PF6 */
+ {GPIOF, 6, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D40/PF7 */
+ {GPIOF, 7, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D41/PF8 */
+ {GPIOF, 8, 6, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D42/PF9 */
+ {GPIOF, 9, 7, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D43/PF10 */
+ {GPIOF, 10, 8, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D44/PF11 */
+ {GPIOF, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D45/PB1 */
+ {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB},
+ /* D46/PB0 */
+ {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB},
+ /* D47/PA0 */
+ {GPIOA, 0, 0, TIMER5_CH1_CCR, TIMER5, 1, AFIO_EXTI_PA},
+ /* D48/PA1 */ /* FIXME (?)
+ What about D48--D50 also being TIMER2_CH[234]? */
+ {GPIOA, 1, 1, TIMER5_CH2_CCR, TIMER5, 2, AFIO_EXTI_PA},
+ /* D49/PA2 */
+ {GPIOA, 2, 2, TIMER5_CH3_CCR, TIMER5, 3, AFIO_EXTI_PA},
+ /* D50/PA3 */
+ {GPIOA, 3, 3, TIMER5_CH4_CCR, TIMER5, 4, AFIO_EXTI_PA},
+ /* D51/PA4 */
+ {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D52/PA5 */
+ {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D53/PA6 */
+ {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA},
+ /* D54/PA7 */
+ {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA},
+
+ /* Right (triple) header */
+
+ /* D55/PF0 */
+ {GPIOF, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D56/PD11 */
+ {GPIOD, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D57/PD14 */
+ {GPIOD, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D58/PF1 */
+ {GPIOF, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D59/PD12 */
+ {GPIOD, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D60/PD15 */
+ {GPIOD, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D61/PF2 */
+ {GPIOF, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D62/PD13 */
+ {GPIOD, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D63/PD0 */
+ {GPIOD, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D64/PF3 */
+ {GPIOF, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D65/PE3 */
+ {GPIOE, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D66/PD1 */
+ {GPIOD, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D67/PF4 */
+ {GPIOF, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D68/PE4 */
+ {GPIOE, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D69/PE7 */
+ {GPIOE, 7, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D70/PF5 */
+ {GPIOF, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D71/PE5 */
+ {GPIOE, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D72/PE8 */
+ {GPIOE, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D73/PF12 */
+ {GPIOF, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D74/PE6 */
+ {GPIOE, 6, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D75/PE9 */
+ {GPIOE, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D76/PF13 */
+ {GPIOF, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D77/PE10 */
+ {GPIOE, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D78/PF14 */
+ {GPIOF, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D79/PG9 */
+ {GPIOG, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D80/PE11 */
+ {GPIOE, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D81/PF15 */
+ {GPIOF, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PF},
+ /* D82/PG10 */
+ {GPIOG, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D83/PE12 */
+ {GPIOE, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D84/PG0 */
+ {GPIOG, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D85/PD5 */
+ {GPIOD, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D86/PE13 */
+ {GPIOE, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D87/PG1 */
+ {GPIOG, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D88/PD4 */
+ {GPIOD, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D89/PE14 */
+ {GPIOE, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D90/PG2 */
+ {GPIOG, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D91/PE1 */
+ {GPIOE, 1, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D92/PE15 */
+ {GPIOE, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D93/PG3 */
+ {GPIOG, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D94/PE0 */
+ {GPIOE, 0, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PE},
+ /* D95/PD8 */
+ {GPIOD, 8, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D96/PG4 */
+ {GPIOG, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D97/PD9 */
+ {GPIOD, 9, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D98/PG5 */
+ {GPIOG, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PG},
+ /* D99/PD10 */
+ {GPIOD, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PDD}
+};
+
+#elif defined(BOARD_maple_mini)
+
+PinMapping PIN_MAP[NR_GPIO_PINS] = {
+ /* D0/PB11 */
+ {GPIOB, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D1/PB10 */
+ {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D2/PB2 */
+ {GPIOB, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D3/PB0 */
+ {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB},
+ /* D4/PA7 */
+ {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA},
+ /* D5/PA6 */
+ {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA},
+ /* D6/PA5 */
+ {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D7/PA4 */
+ {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D8/PA3 */
+ {GPIOA, 3, 3, TIMER2_CH4_CCR, TIMER2, 4, AFIO_EXTI_PA},
+ /* D9/PA2 */
+ {GPIOA, 2, 2, TIMER2_CH3_CCR, TIMER2, 3, AFIO_EXTI_PA},
+ /* D10/PA1 */
+ {GPIOA, 1, 1, TIMER2_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA},
+ /* D11/PA0 */
+ {GPIOA, 0, 0, TIMER2_CH1_CCR, TIMER2, 1, AFIO_EXTI_PA},
+ /* D12/PC15 */
+ {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D13/PC14 */
+ {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D14/PC13 */
+ {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D15/PB7 */
+ {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB},
+ /* D16/PB6 */
+ {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB},
+ /* D17/PB5 */
+ {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D18/PB4 */
+ {GPIOB, 4, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D19/PB3 */
+ {GPIOB, 3, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D20/PA15 */
+ {GPIOA, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D21/PA14 */
+ {GPIOA, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D22/PA13 */
+ {GPIOA, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D23/PA12 */
+ {GPIOA, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D24/PA11 */
+ {GPIOA, 11, ADCx, TIMER1_CH4_CCR, TIMER1, 4, AFIO_EXTI_PA},
+ /* D25/PA10 */
+ {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA},
+ /* D26/PA9 */
+ {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA},
+ /* D27/PA8 */
+ {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA},
+ /* D28/PB15 */
+ {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D29/PB14 */
+ {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D30/PB13 */
+ {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D31/PB12 */
+ {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D32/PB8 */
+ {GPIOB, 8, ADCx, TIMER4_CH3_CCR, TIMER4, 3, AFIO_EXTI_PB},
+ /* D33/PB1 */
+ {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB},
+};
+
+#elif defined(BOARD_maple_RET6)
+
+PinMapping PIN_MAP[NR_GPIO_PINS] = {
+ /* D0/PA3 */
+ {GPIOA, 3, 3, TIMER2_CH4_CCR, TIMER2, 4, AFIO_EXTI_PA},
+ /* D1/PA2 */
+ {GPIOA, 2, 2, TIMER2_CH3_CCR, TIMER2, 3, AFIO_EXTI_PA},
+ /* D2/PA0 */
+ {GPIOA, 0, 0, TIMER2_CH1_CCR, TIMER2, 1, AFIO_EXTI_PA},
+ /* D3/PA1 */
+ {GPIOA, 1, 1, TIMER2_CH2_CCR, TIMER2, 2, AFIO_EXTI_PA},
+ /* D4/PB5 */
+ {GPIOB, 5, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D5/PB6 */
+ {GPIOB, 6, ADCx, TIMER4_CH1_CCR, TIMER4, 1, AFIO_EXTI_PB},
+ /* D6/PA8 */
+ {GPIOA, 8, ADCx, TIMER1_CH1_CCR, TIMER1, 1, AFIO_EXTI_PA},
+ /* D7/PA9 */
+ {GPIOA, 9, ADCx, TIMER1_CH2_CCR, TIMER1, 2, AFIO_EXTI_PA},
+ /* D8/PA10 */
+ {GPIOA, 10, ADCx, TIMER1_CH3_CCR, TIMER1, 3, AFIO_EXTI_PA},
+ /* D9/PB7 */
+ {GPIOB, 7, ADCx, TIMER4_CH2_CCR, TIMER4, 2, AFIO_EXTI_PB},
+ /* D10/PA4 */
+ {GPIOA, 4, 4, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D11/PA7 */
+ {GPIOA, 7, 7, TIMER3_CH2_CCR, TIMER3, 2, AFIO_EXTI_PA},
+ /* D12/PA6 */
+ {GPIOA, 6, 6, TIMER3_CH1_CCR, TIMER3, 1, AFIO_EXTI_PA},
+ /* D13/PA5 */
+ {GPIOA, 5, 5, 0, TIMERx, TIMERx, AFIO_EXTI_PA},
+ /* D14/PB8 */
+ {GPIOB, 8, ADCx, TIMER4_CH3_CCR, TIMER4, 3, AFIO_EXTI_PB},
+
+ /* Little header */
+
+ /* D15/PC0 */
+ {GPIOC, 0, 10, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D16/PC1 */
+ {GPIOC, 1, 11, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D17/PC2 */
+ {GPIOC, 2, 12, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D18/PC3 */
+ {GPIOC, 3, 13, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D19/PC4 */
+ {GPIOC, 4, 14, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D20/PC5 */
+ {GPIOC, 5, 15, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+
+ /* External header */
+
+ /* D21/PC13 */
+ {GPIOC, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D22/PC14 */
+ {GPIOC, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D23/PC15 */
+ {GPIOC, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D24/PB9 */
+ {GPIOB, 9, ADCx, TIMER4_CH4_CCR, TIMER4, 4, AFIO_EXTI_PB},
+ /* D25/PD2 */
+ {GPIOD, 2, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PD},
+ /* D26/PC10 */
+ {GPIOC, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PC},
+ /* D27/PB0 */
+ {GPIOB, 0, 8, TIMER3_CH3_CCR, TIMER3, 3, AFIO_EXTI_PB},
+ /* D28/PB1 */
+ {GPIOB, 1, 9, TIMER3_CH4_CCR, TIMER3, 4, AFIO_EXTI_PB},
+ /* D29/PB10 */
+ {GPIOB, 10, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D30/PB11 */
+ {GPIOB, 11, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D31/PB12 */
+ {GPIOB, 12, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D32/PB13 */
+ {GPIOB, 13, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D33/PB14 */
+ {GPIOB, 14, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D34/PB15 */
+ {GPIOB, 15, ADCx, 0, TIMERx, TIMERx, AFIO_EXTI_PB},
+ /* D35/PC6 */
+ {GPIOC, 6, ADCx, TIMER8_CH1_CCR, TIMER8, 1, AFIO_EXTI_PC},
+ /* D36/PC7 */
+ {GPIOC, 7, ADCx, TIMER8_CH1_CCR, TIMER8, 2, AFIO_EXTI_PC},
+ /* D37/PC8 */
+ {GPIOC, 8, ADCx, TIMER8_CH1_CCR, TIMER8, 3, AFIO_EXTI_PC},
+ /* D38/PC9 (BUT) */
+ {GPIOC, 9, ADCx, TIMER8_CH1_CCR, TIMER8, 4, AFIO_EXTI_PC}
+};
+
+#else
+
+#error "Board type has not been selected correctly."
+
+#endif
diff --git a/wirish/boards.h b/wirish/boards.h
index ee93c5a..94566fa 100644
--- a/wirish/boards.h
+++ b/wirish/boards.h
@@ -34,13 +34,11 @@
#include "libmaple.h"
#include "gpio.h"
#include "timers.h"
-#include "exti.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Set of all possible digital pin names; not all boards have all these */
+/* Set of all possible pin names; not all boards have all these (note
+ that we use the Dx convention since all of the Maple's pins are
+ "digital" pins (e.g. can be used with digitalRead() and
+ digitalWrite()), but not all of them are connected to ADCs. */
enum {
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16,
D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31,
@@ -53,17 +51,20 @@ enum {
#define ADC_INVALID 0xFFFFFFFF
-/* Types used for the tables below */
+/* Pin mapping: pin number -> STM32 info */
typedef struct PinMapping {
- GPIO_Port *port;
+ gpio_dev *gpio_device;
uint32 pin;
uint32 adc_channel;
TimerCCR timer_ccr;
- uint32 exti_port;
timer_dev_num timer_num;
uint32 timer_chan;
+ afio_exti_port ext_port;
} PinMapping;
+/* Maps every digital pin to a PinMapping */
+extern PinMapping PIN_MAP[];
+
/* LeafLabs Maple rev3, rev5 */
#ifdef BOARD_maple
@@ -77,93 +78,6 @@ typedef struct PinMapping {
intended for general use. */
#define NR_GPIO_PINS 39
- static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
- /* D0/PA3 */
- {GPIOA_BASE, 3, 3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2, 4},
- /* D1/PA2 */
- {GPIOA_BASE, 2, 2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2, 3},
- /* D2/PA0 */
- {GPIOA_BASE, 0, 0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2, 1},
- /* D3/PA1 */
- {GPIOA_BASE, 1, 1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2, 2},
- /* D4/PB5 */
- {GPIOB_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D5/PB6 */
- {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB, TIMER4, 1},
- /* D6/PA8 */
- {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA, TIMER1, 1},
- /* D7/PA9 */
- {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA, TIMER1, 2},
- /* D8/PA10 */
- {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA, TIMER1, 3},
- /* D9/PB7 */
- {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB, TIMER4, 2},
- /* D10/PA4 */
- {GPIOA_BASE, 4, 4, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D11/PA7 */
- {GPIOA_BASE, 7, 7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3, 2},
- /* D12/PA6 */
- {GPIOA_BASE, 6, 6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3, 1},
- /* D13/PA5 */
- {GPIOA_BASE, 5, 5, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D14/PB8 */
- {GPIOB_BASE, 8, ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB, TIMER4, 3},
-
- /* Little header */
-
- /* D15/PC0 */
- {GPIOC_BASE, 0, 10, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D16/PC1 */
- {GPIOC_BASE, 1, 11, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D17/PC2 */
- {GPIOC_BASE, 2, 12, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D18/PC3 */
- {GPIOC_BASE, 3, 13, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D19/PC4 */
- {GPIOC_BASE, 4, 14, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D20/PC5 */
- {GPIOC_BASE, 5, 15, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
-
- /* External header */
-
- /* D21/PC13 */
- {GPIOC_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D22/PC14 */
- {GPIOC_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D23/PC15 */
- {GPIOC_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D24/PB9 */
- {GPIOB_BASE, 9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB, TIMER4, 4},
- /* D25/PD2 */
- {GPIOD_BASE, 2, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D26/PC10 */
- {GPIOC_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D27/PB0 */
- {GPIOB_BASE, 0, 8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3, 3},
- /* D28/PB1 */
- {GPIOB_BASE, 1, 9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3, 4},
- /* D29/PB10 */
- {GPIOB_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D30/PB11 */
- {GPIOB_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D31/PB12 */
- {GPIOB_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D32/PB13 */
- {GPIOB_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D33/PB14 */
- {GPIOB_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D34/PB15 */
- {GPIOB_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D35/PC6 */
- {GPIOC_BASE, 6, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D36/PC7 */
- {GPIOC_BASE, 7, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D37/PC8 */
- {GPIOC_BASE, 8, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D38/PC9 (BUT) */
- {GPIOC_BASE, 9, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID}
- };
-
#define BOARD_INIT do { \
} while(0)
@@ -179,218 +93,6 @@ typedef struct PinMapping {
#define NR_GPIO_PINS 100
- static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
- /* Top header */
-
- /* D0/PB10 */
- {GPIOB_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D1/PB2 */
- {GPIOB_BASE, 2, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D2/PB12 */
- {GPIOB_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D3/PB13 */
- {GPIOB_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D4/PB14 */
- {GPIOB_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D5/PB15 */
- {GPIOB_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D6/PC0 */
- {GPIOC_BASE, 0, 10, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D7/PC1 */
- {GPIOC_BASE, 1, 11, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D8/PC2 */
- {GPIOC_BASE, 2, 12, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D9/PC3 */
- {GPIOC_BASE, 3, 13, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D10/PC4 */
- {GPIOC_BASE, 4, 14, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D11/PC5 */
- {GPIOC_BASE, 5, 15, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D12/PC6 */
- {GPIOC_BASE, 6, ADC_INVALID, TIMER8_CH1_CCR, EXTI_CONFIG_PORTC, TIMER8, 1},
- /* D13/PC7 */
- {GPIOC_BASE, 7, ADC_INVALID, TIMER8_CH2_CCR, EXTI_CONFIG_PORTC, TIMER8, 2},
- /* D14/PC8 */
- {GPIOC_BASE, 8, ADC_INVALID, TIMER8_CH3_CCR, EXTI_CONFIG_PORTC, TIMER8, 3},
- /* D15/PC9 */
- {GPIOC_BASE, 9, ADC_INVALID, TIMER8_CH4_CCR, EXTI_CONFIG_PORTC, TIMER8, 4},
- /* D16/PC10 */
- {GPIOC_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D17/PC11 */
- {GPIOC_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D18/PC12 */
- {GPIOC_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D19/PC13 */
- {GPIOC_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D20/PC14 */
- {GPIOC_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D21/PC15 */
- {GPIOC_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D22/PA8 */
- {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA, TIMER1, 1},
- /* D23/PA9 */
- {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA, TIMER1, 2},
- /* D24/PA10 */
- {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA, TIMER1, 3},
- /* D25/PB9 */
- {GPIOB_BASE, 9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB, TIMER4, 4},
-
- /* Bottom header */
-
- /* D26/PD2 */
- {GPIOD_BASE, 2, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D27/PD3 */
- {GPIOD_BASE, 3, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D28/PD6 */
- {GPIOD_BASE, 6, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D29/PG11 */
- {GPIOG_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D30/PG12 */
- {GPIOG_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D31/PG13 */
- {GPIOG_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D32/PG14 */
- {GPIOG_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D33/PG8 */
- {GPIOG_BASE, 8, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D34/PG7 */
- {GPIOG_BASE, 7, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D35/PG6 */
- {GPIOG_BASE, 6, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D36/PB5 */
- {GPIOB_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D37/PB6 */
- {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB, TIMER4, 1},
- /* D38/PB7 */
- {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB, TIMER4, 2},
- /* D39/PF6 */
- {GPIOF_BASE, 6, 4, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D40/PF7 */
- {GPIOF_BASE, 7, 5, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D41/PF8 */
- {GPIOF_BASE, 8, 6, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D42/PF9 */
- {GPIOF_BASE, 9, 7, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D43/PF10 */
- {GPIOF_BASE, 10, 8, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D44/PF11 */
- {GPIOF_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D45/PB1 */
- {GPIOB_BASE, 1, 9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3, 4},
- /* D46/PB0 */
- {GPIOB_BASE, 0, 8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3, 3},
- /* D47/PA0 */
- {GPIOA_BASE, 0, 0, TIMER5_CH1_CCR, EXTI_CONFIG_PORTA, TIMER5, 1},
- /* D48/PA1 */
- {GPIOA_BASE, 1, 1, TIMER5_CH2_CCR, EXTI_CONFIG_PORTA, TIMER5, 2}, /* FIXME (?) what to do about D48--D50
- also being TIMER2_CH[2,3,4]? */
- /* D49/PA2 */
- {GPIOA_BASE, 2, 2, TIMER5_CH3_CCR, EXTI_CONFIG_PORTA, TIMER5, 3},
- /* D50/PA3 */
- {GPIOA_BASE, 3, 3, TIMER5_CH4_CCR, EXTI_CONFIG_PORTA, TIMER5, 4},
- /* D51/PA4 */
- {GPIOA_BASE, 4, 4, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D52/PA5 */
- {GPIOA_BASE, 5, 5, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D53/PA6 */
- {GPIOA_BASE, 6, 6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3, 1},
- /* D54/PA7 */
- {GPIOA_BASE, 7, 7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3, 2},
-
- /* Right (triple) header */
-
- /* D55/PF0 */
- {GPIOF_BASE, 0, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D56/PD11 */
- {GPIOD_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D57/PD14 */
- {GPIOD_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D58/PF1 */
- {GPIOF_BASE, 1, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D59/PD12 */
- {GPIOD_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D60/PD15 */
- {GPIOD_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D61/PF2 */
- {GPIOF_BASE, 2, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D62/PD13 */
- {GPIOD_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D63/PD0 */
- {GPIOD_BASE, 0, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D64/PF3 */
- {GPIOF_BASE, 3, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D65/PE3 */
- {GPIOE_BASE, 3, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D66/PD1 */
- {GPIOD_BASE, 1, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D67/PF4 */
- {GPIOF_BASE, 4, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D68/PE4 */
- {GPIOE_BASE, 4, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D69/PE7 */
- {GPIOE_BASE, 7, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D70/PF5 */
- {GPIOF_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D71/PE5 */
- {GPIOE_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D72/PE8 */
- {GPIOE_BASE, 8, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D73/PF12 */
- {GPIOF_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D74/PE6 */
- {GPIOE_BASE, 6, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D75/PE9 */
- {GPIOE_BASE, 9, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D76/PF13 */
- {GPIOF_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D77/PE10 */
- {GPIOE_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D78/PF14 */
- {GPIOF_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D79/PG9 */
- {GPIOG_BASE, 9, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D80/PE11 */
- {GPIOE_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D81/PF15 */
- {GPIOF_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
- /* D82/PG10 */
- {GPIOG_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D83/PE12 */
- {GPIOE_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D84/PG0 */
- {GPIOG_BASE, 0, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D85/PD5 */
- {GPIOD_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D86/PE13 */
- {GPIOE_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D87/PG1 */
- {GPIOG_BASE, 1, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D88/PD4 */
- {GPIOD_BASE, 4, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D89/PE14 */
- {GPIOE_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D90/PG2 */
- {GPIOG_BASE, 2, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D91/PE1 */
- {GPIOE_BASE, 1, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D92/PE15 */
- {GPIOE_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D93/PG3 */
- {GPIOG_BASE, 3, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D94/PE0 */
- {GPIOE_BASE, 0, ADC_INVALID, 0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
- /* D95/PD8 */
- {GPIOD_BASE, 8, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D96/PG4 */
- {GPIOG_BASE, 4, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D97/PD9 */
- {GPIOD_BASE, 9, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
- /* D98/PG5 */
- {GPIOG_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
- /* D99/PD10 */
- {GPIOD_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID}
- };
-
#define BOARD_INIT do { \
} while(0)
@@ -404,94 +106,32 @@ typedef struct PinMapping {
#define NR_GPIO_PINS 34
- static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
- /* D0/PB11 */
- {GPIOB_BASE, 11, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D1/PB10 */
- {GPIOB_BASE, 10, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D2/PB2 */
- {GPIOB_BASE, 2, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D3/PB0 */
- {GPIOB_BASE, 0, 8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3, 3},
- /* D4/PA7 */
- {GPIOA_BASE, 7, 7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3, 2},
- /* D5/PA6 */
- {GPIOA_BASE, 6, 6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3, 1},
- /* D6/PA5 */
- {GPIOA_BASE, 5, 5, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D7/PA4 */
- {GPIOA_BASE, 4, 4, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D8/PA3 */
- {GPIOA_BASE, 3, 3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2, 4},
- /* D9/PA2 */
- {GPIOA_BASE, 2, 2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2, 3},
- /* D10/PA1 */
- {GPIOA_BASE, 1, 1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2, 2},
- /* D11/PA0 */
- {GPIOA_BASE, 0, 0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2, 1},
- /* D12/PC15 */
- {GPIOC_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D13/PC14 */
- {GPIOC_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D14/PC13 */
- {GPIOC_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
- /* D15/PB7 */
- {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB, TIMER4, 1},
- /* D16/PB6 */
- {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB, TIMER4, 1},
- /* D17/PB5 */
- {GPIOB_BASE, 5, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D18/PB4 */
- {GPIOB_BASE, 4, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D19/PB3 */
- {GPIOB_BASE, 3, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D20/PA15 */
- {GPIOA_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D21/PA14 */
- {GPIOA_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D22/PA13 */
- {GPIOA_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D23/PA12 */
- {GPIOA_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
- /* D24/PA11 */
- {GPIOA_BASE, 11, ADC_INVALID, TIMER1_CH4_CCR, EXTI_CONFIG_PORTA, TIMER1, 4},
- /* D25/PA10 */
- {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA, TIMER1, 3},
- /* D26/PA9 */
- {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2, 2},
- /* D27/PA8 */
- {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTB, TIMER1, 1},
- /* D28/PB15 */
- {GPIOB_BASE, 15, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D29/PB14 */
- {GPIOB_BASE, 14, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D30/PB13 */
- {GPIOB_BASE, 13, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D31/PB12 */
- {GPIOB_BASE, 12, ADC_INVALID, 0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
- /* D32/PB8 */
- {GPIOB_BASE, 8, ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB, TIMER4, 3},
- /* D33/PB1 */
- {GPIOB_BASE, 1, 9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3, 4},
- };
-
- /* since we want the Serial Wire/JTAG pins as GPIOs, disable both
- SW and JTAG debug support */
- /* don't use __clear_bits here! */
+ /* Since we want the Serial Wire/JTAG pins as GPIOs, disable both
+ * SW and JTAG debug support */
#define BOARD_INIT \
do { \
- *AFIO_MAPR = (*AFIO_MAPR | BIT(26)) & ~(BIT(25) | BIT(24)); \
+ afio_mapr_swj_config(AFIO_MAPR_SWJ_NO_JTAG_NO_SW); \
} while (0)
+#elif defined(BOARD_maple_RET6)
+
+ #define CYCLES_PER_MICROSECOND 72
+ #define SYSTICK_RELOAD_VAL 71999 /* takes a cycle to reload */
+
+ #define BOARD_BUTTON_PIN 38
+ #define BOARD_LED_PIN 13
+
+ /* Total number of GPIO pins that are broken out to headers and
+ intended for general use. */
+ #define NR_GPIO_PINS 39
+
+ #define BOARD_INIT do { \
+ } while(0)
+
#else
#error "Board type has not been selected correctly."
#endif
-#ifdef __cplusplus
-} // extern "C"
#endif
-
-#endif
-
diff --git a/wirish/comm/HardwareSerial.cpp b/wirish/comm/HardwareSerial.cpp
index d6c7e82..08252d8 100644
--- a/wirish/comm/HardwareSerial.cpp
+++ b/wirish/comm/HardwareSerial.cpp
@@ -34,21 +34,21 @@
#include "gpio.h"
#include "timers.h"
-HardwareSerial Serial1(USART1, 4500000UL, GPIOA_BASE, 9,10, TIMER1, 2);
-HardwareSerial Serial2(USART2, 2250000UL, GPIOA_BASE, 2, 3, TIMER2, 3);
-HardwareSerial Serial3(USART3, 2250000UL, GPIOB_BASE, 10,11, TIMER_INVALID, 0);
+HardwareSerial Serial1(USART1, 4500000UL, GPIOA, 9,10, TIMER1, 2);
+HardwareSerial Serial2(USART2, 2250000UL, GPIOA, 2, 3, TIMER2, 3);
+HardwareSerial Serial3(USART3, 2250000UL, GPIOB, 10,11, TIMER_INVALID, 0);
// TODO: High density device ports
HardwareSerial::HardwareSerial(uint8 usart_num,
uint32 max_baud,
- GPIO_Port *gpio_port,
+ gpio_dev *gpio_device,
uint8 tx_pin,
uint8 rx_pin,
timer_dev_num timer_num,
uint8 compare_num) {
this->usart_num = usart_num;
this->max_baud = max_baud;
- this->gpio_port = gpio_port;
+ this->gpio_device = gpio_device;
this->tx_pin = tx_pin;
this->rx_pin = rx_pin;
this->timer_num = timer_num;
@@ -72,8 +72,8 @@ void HardwareSerial::begin(uint32 baud) {
return;
}
- gpio_set_mode(gpio_port, tx_pin, GPIO_MODE_AF_OUTPUT_PP);
- gpio_set_mode(gpio_port, rx_pin, GPIO_MODE_INPUT_FLOATING);
+ gpio_set_mode(gpio_device, tx_pin, GPIO_AF_OUTPUT_PP);
+ gpio_set_mode(gpio_device, rx_pin, GPIO_INPUT_FLOATING);
if (timer_num != TIMER_INVALID) {
/* turn off any pwm if there's a conflict on this usart */
diff --git a/wirish/comm/HardwareSerial.h b/wirish/comm/HardwareSerial.h
index aad8aa7..ef19a56 100644
--- a/wirish/comm/HardwareSerial.h
+++ b/wirish/comm/HardwareSerial.h
@@ -46,7 +46,7 @@ class HardwareSerial : public Print {
private:
uint8 usart_num;
uint32 max_baud;
- GPIO_Port *gpio_port;
+ gpio_dev *gpio_device;
uint8 tx_pin;
uint8 rx_pin;
timer_dev_num timer_num;
@@ -54,7 +54,7 @@ class HardwareSerial : public Print {
public:
HardwareSerial(uint8 usart_num,
uint32 max_baud,
- GPIO_Port *gpio_port,
+ gpio_dev *gpio_device,
uint8 tx_pin,
uint8 rx_pin,
timer_dev_num timer_num,
diff --git a/wirish/ext_interrupts.c b/wirish/ext_interrupts.cpp
index dd7c1a8..5b32b05 100644
--- a/wirish/ext_interrupts.c
+++ b/wirish/ext_interrupts.cpp
@@ -28,52 +28,55 @@
* @brief Wiring-like interface for external interrupts
*/
-#include "wirish.h"
+#include "boards.h"
+#include "gpio.h"
#include "exti.h"
#include "ext_interrupts.h"
-/* Attach ISR handler on pin, triggering on the given mode. */
-void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) {
- uint8 outMode;
-
- /* Parameter checking */
- if (pin >= NR_GPIO_PINS) {
- return;
- }
+static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode);
- if (!handler) {
+/**
+ * @brief Attach an interrupt handler to a pin, triggering on the given mode.
+ * @param pin Pin to attach an interrupt handler onto.
+ * @param handler Function to call when the external interrupt is triggered.
+ * @param mode Trigger mode for the given interrupt.
+ * @see ExtIntTriggerMode
+ */
+void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) {
+ if (pin >= NR_GPIO_PINS || !handler) {
return;
}
- switch (mode) {
- case RISING:
- outMode = EXTI_RISING;
- break;
- case FALLING:
- outMode = EXTI_FALLING;
- break;
- case CHANGE:
- outMode = EXTI_RISING_FALLING;
- break;
- default:
- ASSERT(0);
- return;
- }
+ exti_trigger_mode outMode = exti_out_mode(mode);
- exti_attach_interrupt(PIN_MAP[pin].exti_port,
- PIN_MAP[pin].pin,
+ exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].pin),
+ PIN_MAP[pin].ext_port,
handler,
- mode);
-
- return;
+ outMode);
}
-/* Disable any interrupts */
+/**
+ * @brief Disable any external interrupt attached to a pin.
+ * @param pin Pin number to detach any interrupt from.
+ */
void detachInterrupt(uint8 pin) {
- if (!(pin < NR_GPIO_PINS)) {
+ if (pin >= NR_GPIO_PINS) {
return;
}
- exti_detach_interrupt(PIN_MAP[pin].pin);
+ exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].pin));
}
+static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) {
+ switch (mode) {
+ case RISING:
+ return EXTI_RISING;
+ case FALLING:
+ return EXTI_FALLING;
+ case CHANGE:
+ return EXTI_RISING_FALLING;
+ }
+ // Can't happen
+ ASSERT(0);
+ return (exti_trigger_mode)0;
+}
diff --git a/wirish/ext_interrupts.h b/wirish/ext_interrupts.h
index 4e22c71..364bcda 100644
--- a/wirish/ext_interrupts.h
+++ b/wirish/ext_interrupts.h
@@ -28,7 +28,7 @@
/**
* @file ext_interrupts.h
*
- * @brief External interrupt wiring prototypes and types
+ * @brief Wiring-like external interrupt prototypes and types.
*/
#ifndef _EXT_INTERRUPTS_H_
@@ -48,10 +48,6 @@ typedef enum ExtIntTriggerMode_ {
changes). */
} ExtIntTriggerMode;
-#ifdef __cplusplus
-extern "C"{
-#endif
-
/**
* @brief Registers an interrupt handler on a pin.
*
@@ -104,10 +100,5 @@ static inline void noInterrupts() {
nvic_globalirq_disable();
}
-#ifdef __cplusplus
-}
-#endif
-
-
#endif
diff --git a/wirish/io.h b/wirish/io.h
index 2d22dcd..8dad1d1 100644
--- a/wirish/io.h
+++ b/wirish/io.h
@@ -35,10 +35,6 @@
#include "adc.h"
#include "time.h"
-#ifdef __cplusplus
-extern "C"{
-#endif
-
/**
* Specifies a GPIO pin behavior.
*
@@ -68,11 +64,11 @@ typedef enum WiringPinMode {
supply through a large resistor). When the
pin is high, not much current flows through
to ground and the line stays at positive
- voltage; when the pin is low the bus
+ voltage; when the pin is low, the bus
"drains" to ground with a small amount of
current constantly flowing through the large
resistor from the external supply. In this
- mode no current is ever actually /sourced/
+ mode, no current is ever actually sourced
from the pin. */
INPUT, /**< Basic digital input. The pin voltage is sampled; when
@@ -220,8 +216,21 @@ uint8 isButtonPressed();
*/
uint8 waitForButtonPress(uint32 timeout_millis);
-#ifdef __cplusplus
-} // extern "C"
-#endif
+/**
+ * Shift out a byte of data, one bit at a time.
+ *
+ * This function starts at either the most significant or least
+ * significant bit in a byte value, and shifts out each byte in order
+ * onto a data pin. After each bit is written to the data pin, a
+ * separate clock pin is pulsed to indicate that the new bit is
+ * available.
+ *
+ * @param dataPin Pin to shift data out on
+ * @param clockPin Pin to pulse after each bit is shifted out
+ * @param bitOrder Either MSBFIRST (big-endian) or LSBFIRST (little-endian).
+ * @param val Value to shift out
+ */
+void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value);
+
#endif
diff --git a/wirish/native_sram.cpp b/wirish/native_sram.cpp
new file mode 100644
index 0000000..5e8095f
--- /dev/null
+++ b/wirish/native_sram.cpp
@@ -0,0 +1,45 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#include "native_sram.h"
+#include "libmaple.h"
+#include "fsmc.h"
+#include "rcc.h"
+
+#ifdef BOARD_maple_native
+
+void initNativeSRAM(void) {
+ fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
+
+ fsmc_sram_init_gpios();
+ rcc_clk_enable(RCC_FSMC);
+
+ regs->BCR = FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
+ fsmc_nor_psram_set_addset(regs, 0);
+ fsmc_nor_psram_set_datast(regs, 3);
+}
+
+#endif
diff --git a/wirish/native_sram.h b/wirish/native_sram.h
new file mode 100644
index 0000000..7724667
--- /dev/null
+++ b/wirish/native_sram.h
@@ -0,0 +1,43 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifdef BOARD_maple_native
+
+#ifndef _NATIVE_SRAM_H_
+#define _NATIVE_SRAM_H_
+
+/**
+ * Sets up the FSMC peripheral to use the SRAM chip on the Maple
+ * Native as an external segment of system memory space.
+ *
+ * This implementation is for the IS62WV51216BLL 8Mb chip (55ns
+ * timing, 512K x 16 bits).
+ */
+void initNativeSRAM(void);
+
+#endif
+
+#endif
diff --git a/wirish/pwm.c b/wirish/pwm.cpp
index 072e4cd..072e4cd 100644
--- a/wirish/pwm.c
+++ b/wirish/pwm.cpp
diff --git a/wirish/pwm.h b/wirish/pwm.h
index d0bc9e0..a6385e9 100644
--- a/wirish/pwm.h
+++ b/wirish/pwm.h
@@ -28,12 +28,8 @@
* @brief Arduino-compatible PWM interface.
*/
-#ifndef _PWM_H
-#define _PWM_H
-
-#ifdef __cplusplus
-extern "C"{
-#endif
+#ifndef _PWM_H_
+#define _PWM_H_
/**
* As a convenience, analogWrite is an alias of pwmWrite to ease
@@ -50,10 +46,5 @@ extern "C"{
*/
void pwmWrite(uint8 pin, uint16 duty_cycle);
-#ifdef __cplusplus
-}
-#endif
-
-
#endif
diff --git a/wirish/rules.mk b/wirish/rules.mk
index cb5a69f..3dd4b2d 100644
--- a/wirish/rules.mk
+++ b/wirish/rules.mk
@@ -11,21 +11,24 @@ WIRISH_INCLUDES := -I$(d) -I$(d)/comm
CFLAGS_$(d) := $(WIRISH_INCLUDES) $(LIBMAPLE_INCLUDES)
# Local rules and targets
-cSRCS_$(d) := wirish.c \
- wirish_shift.c \
- wirish_analog.c \
- time.c \
- pwm.c \
- ext_interrupts.c \
- wirish_digital.c
-
-cppSRCS_$(d) := wirish_math.cpp \
- Print.cpp \
- comm/HardwareSerial.cpp \
- comm/HardwareSPI.cpp \
- usb_serial.cpp \
- HardwareTimer.cpp \
- cxxabi-compat.cpp \
+cSRCS_$(d) :=
+
+cppSRCS_$(d) := wirish_math.cpp \
+ Print.cpp \
+ comm/HardwareSerial.cpp \
+ comm/HardwareSPI.cpp \
+ usb_serial.cpp \
+ HardwareTimer.cpp \
+ cxxabi-compat.cpp \
+ wirish.cpp \
+ wirish_shift.cpp \
+ wirish_analog.cpp \
+ time.cpp \
+ pwm.cpp \
+ ext_interrupts.cpp \
+ wirish_digital.cpp \
+ native_sram.cpp \
+ boards.cpp
cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%)
cppFILES_$(d) := $(cppSRCS_$(d):%=$(d)/%)
diff --git a/wirish/time.c b/wirish/time.cpp
index b5663b0..b5663b0 100644
--- a/wirish/time.c
+++ b/wirish/time.cpp
diff --git a/wirish/time.h b/wirish/time.h
index 8d3d074..a0c0c82 100644
--- a/wirish/time.h
+++ b/wirish/time.h
@@ -35,10 +35,6 @@
#include "systick.h"
#include "boards.h"
-#ifdef __cplusplus
-extern "C"{
-#endif
-
#define US_PER_MS 1000
/**
@@ -99,10 +95,5 @@ void delay(unsigned long ms);
*/
void delayMicroseconds(uint32 us);
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-
#endif
diff --git a/wirish/wirish.c b/wirish/wirish.cpp
index 4c84d26..65d0262 100644
--- a/wirish/wirish.c
+++ b/wirish/wirish.cpp
@@ -41,14 +41,15 @@
#include "fsmc.h"
#include "dac.h"
#include "flash.h"
+#include "native_sram.h"
void init(void) {
/* make sure the flash is ready before spinning the high speed clock up */
flash_enable_prefetch();
flash_set_latency(FLASH_WAIT_STATE_2);
-#ifdef STM32_HIGH_DENSITY
- fsmc_native_sram_init();
+#ifdef BOARD_maple_native
+ initNativeSRAM();
#endif
/* initialize clocks */
@@ -59,7 +60,8 @@ void init(void) {
nvic_init();
systick_init(SYSTICK_RELOAD_VAL);
- gpio_init();
+ gpio_init_all();
+ afio_init();
/* Initialize the ADC for slow conversions, to allow for high
impedance inputs. */
diff --git a/wirish/wirish.h b/wirish/wirish.h
index 311c74f..447b2b6 100644
--- a/wirish/wirish.h
+++ b/wirish/wirish.h
@@ -32,25 +32,19 @@
#define _WIRISH_H_
#include "libmaple.h"
-#include "boards.h"
-#include "time.h"
#include "timers.h"
+
+#include "boards.h"
#include "io.h"
#include "bits.h"
#include "pwm.h"
#include "ext_interrupts.h"
#include "wirish_math.h"
-
-#ifdef __cplusplus
+#include "time.h"
#include "HardwareSPI.h"
#include "HardwareSerial.h"
#include "usb_serial.h"
#include "HardwareTimer.h"
-#endif
-
-#ifdef __cplusplus
-extern "C"{
-#endif
/* Arduino wiring macros and bit defines */
#define HIGH 0x1
@@ -77,9 +71,5 @@ typedef uint8 byte;
void init(void);
void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, byte val);
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
#endif
diff --git a/wirish/wirish_analog.c b/wirish/wirish_analog.cpp
index a658184..a658184 100644
--- a/wirish/wirish_analog.c
+++ b/wirish/wirish_analog.cpp
diff --git a/wirish/wirish_digital.c b/wirish/wirish_digital.cpp
index bb28f0a..0c0bd85 100644
--- a/wirish/wirish_digital.c
+++ b/wirish/wirish_digital.cpp
@@ -30,7 +30,7 @@
#include "io.h"
void pinMode(uint8 pin, WiringPinMode mode) {
- uint8 outputMode;
+ gpio_pin_mode outputMode;
boolean pwm = false;
if (pin >= NR_GPIO_PINS) {
@@ -39,30 +39,30 @@ void pinMode(uint8 pin, WiringPinMode mode) {
switch(mode) {
case OUTPUT:
- outputMode = GPIO_MODE_OUTPUT_PP;
+ outputMode = GPIO_OUTPUT_PP;
break;
case OUTPUT_OPEN_DRAIN:
- outputMode = GPIO_MODE_OUTPUT_OD;
+ outputMode = GPIO_OUTPUT_OD;
break;
case INPUT:
case INPUT_FLOATING:
- outputMode = GPIO_MODE_INPUT_FLOATING;
+ outputMode = GPIO_INPUT_FLOATING;
break;
case INPUT_ANALOG:
- outputMode = GPIO_MODE_INPUT_ANALOG;
+ outputMode = GPIO_INPUT_ANALOG;
break;
case INPUT_PULLUP:
- outputMode = GPIO_MODE_INPUT_PU;
+ outputMode = GPIO_INPUT_PU;
break;
case INPUT_PULLDOWN:
- outputMode = GPIO_MODE_INPUT_PD;
+ outputMode = GPIO_INPUT_PD;
break;
case PWM:
- outputMode = GPIO_MODE_AF_OUTPUT_PP;
+ outputMode = GPIO_AF_OUTPUT_PP;
pwm = true;
break;
case PWM_OPEN_DRAIN:
- outputMode = GPIO_MODE_AF_OUTPUT_OD;
+ outputMode = GPIO_AF_OUTPUT_OD;
pwm = true;
break;
default:
@@ -70,7 +70,7 @@ void pinMode(uint8 pin, WiringPinMode mode) {
return;
}
- gpio_set_mode(PIN_MAP[pin].port, PIN_MAP[pin].pin, outputMode);
+ gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].pin, outputMode);
if (PIN_MAP[pin].timer_num != TIMER_INVALID) {
/* enable/disable timer channels if we're switching into or
@@ -93,7 +93,8 @@ uint32 digitalRead(uint8 pin) {
return 0;
}
- return gpio_read_bit(PIN_MAP[pin].port, PIN_MAP[pin].pin);
+ return gpio_read_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].pin) ?
+ HIGH : LOW;
}
void digitalWrite(uint8 pin, uint8 val) {
@@ -101,15 +102,15 @@ void digitalWrite(uint8 pin, uint8 val) {
return;
}
- gpio_write_bit(PIN_MAP[pin].port, PIN_MAP[pin].pin, val);
+ gpio_write_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].pin, val);
}
void togglePin(uint8 pin) {
if (pin >= NR_GPIO_PINS) {
return;
}
-
- gpio_toggle_pin(PIN_MAP[pin].port, PIN_MAP[pin].pin);
+
+ gpio_toggle_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].pin);
}
uint8 isButtonPressed() {
diff --git a/wirish/wirish_math.h b/wirish/wirish_math.h
index 14614ba..fa544a9 100644
--- a/wirish/wirish_math.h
+++ b/wirish/wirish_math.h
@@ -24,7 +24,7 @@
/**
* @file wirish_math.h
- * @brief Includes cmath; provides Arduino-compatible math routines.
+ * @brief Includes <math.h>; provides Arduino-compatible math routines.
*/
#ifndef _WIRING_MATH_H_
@@ -32,8 +32,6 @@
#include <math.h>
-#ifdef __cplusplus
-
/**
* @brief Initialize the pseudo-random number generator.
* @param seed the number used to initialize the seed; cannot be zero.
@@ -78,8 +76,7 @@ long random(long min, long max);
* @param toEnd the end of the value's mapped range.
* @return the mapped value.
*/
-/* TODO: profile code bloat due to inlining this */
-inline long map(long value, long fromStart, long fromEnd,
+static inline long map(long value, long fromStart, long fromEnd,
long toStart, long toEnd) {
return (value - fromStart) * (toEnd - toStart) / (fromEnd - fromStart) +
toStart;
@@ -105,8 +102,6 @@ inline long map(long value, long fromStart, long fromEnd,
#endif
#define abs(x) (((x) > 0) ? (x) : -(unsigned)(x))
-#endif
-
/* Following are duplicate declarations (with Doxygen comments) for
* some of the math.h functions; this is for the convenience of the
* Sphinx docs.
diff --git a/wirish/wirish_shift.c b/wirish/wirish_shift.cpp
index f67364d..f67364d 100644
--- a/wirish/wirish_shift.c
+++ b/wirish/wirish_shift.cpp
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-01 23:08:53 +0000