aboutsummaryrefslogtreecommitdiffstats
path: root/wirish/boards.h
diff options
context:
space:
mode:
Diffstat (limited to 'wirish/boards.h')
-rw-r--r--wirish/boards.h102
1 files changed, 40 insertions, 62 deletions
diff --git a/wirish/boards.h b/wirish/boards.h
index 03d0b0e..0e0d159 100644
--- a/wirish/boards.h
+++ b/wirish/boards.h
@@ -64,13 +64,9 @@ typedef struct PinMapping {
uint32 pin;
uint32 adc;
TimerCCR timer_channel;
+ uint32 exti_port;
} PinMapping;
-typedef struct ExtiInfo {
- uint8 channel;
- uint8 port;
-} ExtiInfo;
-
// LeafLabs Maple rev3, rev4
#ifdef BOARD_maple
@@ -78,65 +74,47 @@ typedef struct ExtiInfo {
#define MAPLE_RELOAD_VAL 71999 /* takes a cycle to reload */
static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
- {GPIOA_BASE, 3, ADC3, TIMER2_CH4_CCR}, // D0/PA3
- {GPIOA_BASE, 2, ADC2, TIMER2_CH3_CCR}, // D1/PA2
- {GPIOA_BASE, 0, ADC0, TIMER2_CH1_CCR}, // D2/PA0
- {GPIOA_BASE, 1, ADC1, TIMER2_CH2_CCR}, // D3/PA1
- {GPIOB_BASE, 5, ADC_INVALID, TIMER_INVALID}, // D4/PB5
- {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR}, // D5/PB6
- {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR}, // D6/PA8
- {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR}, // D7/PA9
- {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR}, // D8/PA10
- {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR}, // D9/PB7
- {GPIOA_BASE, 4, ADC4, TIMER_INVALID}, // D10/PA4
- {GPIOA_BASE, 7, ADC7, TIMER3_CH2_CCR}, // D11/PA7
- {GPIOA_BASE, 6, ADC6, TIMER3_CH1_CCR}, // D12/PA6
- {GPIOA_BASE, 5, ADC5, TIMER_INVALID}, // D13/PA5
- {GPIOB_BASE, 8, ADC_INVALID, TIMER4_CH3_CCR}, // D14/PB8
+ {GPIOA_BASE, 3, ADC3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA}, // D0/PA3
+ {GPIOA_BASE, 2, ADC2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA}, // D1/PA2
+ {GPIOA_BASE, 0, ADC0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA}, // D2/PA0
+ {GPIOA_BASE, 1, ADC1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA}, // D3/PA1
+ {GPIOB_BASE, 5, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D4/PB5
+ {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB}, // D5/PB6
+ {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA}, // D6/PA8
+ {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA}, // D7/PA9
+ {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA}, // D8/PA10
+ {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB}, // D9/PB7
+ {GPIOA_BASE, 4, ADC4, TIMER_INVALID, EXTI_CONFIG_PORTA}, // D10/PA4
+ {GPIOA_BASE, 7, ADC7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA}, // D11/PA7
+ {GPIOA_BASE, 6, ADC6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA}, // D12/PA6
+ {GPIOA_BASE, 5, ADC5, TIMER_INVALID, EXTI_CONFIG_PORTA}, // D13/PA5
+ {GPIOB_BASE, 8, ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB}, // D14/PB8
/* Little header */
- {GPIOC_BASE, 0, ADC10, TIMER_INVALID}, // D15/PC0
- {GPIOC_BASE, 1, ADC11, TIMER_INVALID}, // D16/PC1
- {GPIOC_BASE, 2, ADC12, TIMER_INVALID}, // D17/PC2
- {GPIOC_BASE, 3, ADC13, TIMER_INVALID}, // D18/PC3
- {GPIOC_BASE, 4, ADC14, TIMER_INVALID}, // D19/PC4
- {GPIOC_BASE, 5, ADC15, TIMER_INVALID}, // D20/PC5
+ {GPIOC_BASE, 0, ADC10, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D15/PC0
+ {GPIOC_BASE, 1, ADC11, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D16/PC1
+ {GPIOC_BASE, 2, ADC12, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D17/PC2
+ {GPIOC_BASE, 3, ADC13, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D18/PC3
+ {GPIOC_BASE, 4, ADC14, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D19/PC4
+ {GPIOC_BASE, 5, ADC15, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D20/PC5
/* External header */
- {GPIOC_BASE, 13, ADC_INVALID, TIMER_INVALID}, // D21/PC13
- {GPIOC_BASE, 14, ADC_INVALID, TIMER_INVALID}, // D22/PC14
- {GPIOC_BASE, 15, ADC_INVALID, TIMER_INVALID}, // D23/PC15
- {GPIOB_BASE, 9, ADC_INVALID, TIMER4_CH4_CCR}, // D24/PB9
- {GPIOD_BASE, 2, ADC_INVALID, TIMER_INVALID}, // D25/PD2
- {GPIOC_BASE, 10, ADC_INVALID, TIMER_INVALID}, // D26/PC10
- {GPIOB_BASE, 0, ADC8, TIMER3_CH3_CCR}, // D27/PB0
- {GPIOB_BASE, 1, ADC9, TIMER3_CH4_CCR}, // D28/PB1
- {GPIOB_BASE, 10, ADC_INVALID, TIMER_INVALID}, // D29/PB10
- {GPIOB_BASE, 11, ADC_INVALID, TIMER_INVALID}, // D30/PB11
- {GPIOB_BASE, 12, ADC_INVALID, TIMER_INVALID}, // D31/PB12
- {GPIOB_BASE, 13, ADC_INVALID, TIMER_INVALID}, // D32/PB13
- {GPIOB_BASE, 14, ADC_INVALID, TIMER_INVALID}, // D33/PB14
- {GPIOB_BASE, 15, ADC_INVALID, TIMER_INVALID}, // D34/PB15
- {GPIOC_BASE, 6, ADC_INVALID, TIMER_INVALID}, // D35/PC6
- {GPIOC_BASE, 7, ADC_INVALID, TIMER_INVALID}, // D36/PC7
- {GPIOC_BASE, 8, ADC_INVALID, TIMER_INVALID}, // D37/PC8
- {GPIOC_BASE, 9, ADC_INVALID, TIMER_INVALID} // D38/PC9 (BUT)
- };
-
- static __attribute__ ((unused)) ExtiInfo PIN_TO_EXTI_CHANNEL[NR_GPIO_PINS] =
- {
- {EXTI3, EXTI_CONFIG_PORTA}, // D0/PA3
- {EXTI2, EXTI_CONFIG_PORTA}, // D1/PA2
- {EXTI0, EXTI_CONFIG_PORTA}, // D2/PA0
- {EXTI1, EXTI_CONFIG_PORTA}, // D3/PA1
- {EXTI5, EXTI_CONFIG_PORTB}, // D4/PB5
- {EXTI6, EXTI_CONFIG_PORTB}, // D5/PB6
- {EXTI8, EXTI_CONFIG_PORTA}, // D6/PA8
- {EXTI9, EXTI_CONFIG_PORTA}, // D7/PA9
- {EXTI10, EXTI_CONFIG_PORTA}, // D8/PA10
- {EXTI7, EXTI_CONFIG_PORTB}, // D9/PB7
- {EXTI4, EXTI_CONFIG_PORTA}, // D10/PA4
- {EXTI7, EXTI_CONFIG_PORTA}, // D11/PA7
- {EXTI6, EXTI_CONFIG_PORTA}, // D12/PA6
- {EXTI5, EXTI_CONFIG_PORTA}, // D13/PA5
+ {GPIOC_BASE, 13, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D21/PC13
+ {GPIOC_BASE, 14, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D22/PC14
+ {GPIOC_BASE, 15, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D23/PC15
+ {GPIOB_BASE, 9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB}, // D24/PB9
+ {GPIOD_BASE, 2, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTD}, // D25/PD2
+ {GPIOC_BASE, 10, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D26/PC10
+ {GPIOB_BASE, 0, ADC8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB}, // D27/PB0
+ {GPIOB_BASE, 1, ADC9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB}, // D28/PB1
+ {GPIOB_BASE, 10, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D29/PB10
+ {GPIOB_BASE, 11, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D30/PB11
+ {GPIOB_BASE, 12, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D31/PB12
+ {GPIOB_BASE, 13, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D32/PB13
+ {GPIOB_BASE, 14, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D33/PB14
+ {GPIOB_BASE, 15, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D34/PB15
+ {GPIOC_BASE, 6, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D35/PC6
+ {GPIOC_BASE, 7, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D36/PC7
+ {GPIOC_BASE, 8, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D37/PC8
+ {GPIOC_BASE, 9, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC} // D38/PC9 (BUT)
};
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 19:30:33 +0000