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-rw-r--r--support/ld/jtag.ld4
-rw-r--r--support/ld/ram.ld4
-rw-r--r--support/openocd/flash.cfg6
3 files changed, 7 insertions, 7 deletions
diff --git a/support/ld/jtag.ld b/support/ld/jtag.ld
index 67fbe85..64d049d 100644
--- a/support/ld/jtag.ld
+++ b/support/ld/jtag.ld
@@ -8,8 +8,8 @@
/* Define memory spaces. */
MEMORY
{
- ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
- rom (rx) : ORIGIN = 0x08000000, LENGTH = 120K
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
}
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
diff --git a/support/ld/ram.ld b/support/ld/ram.ld
index 6398ea4..872d6f2 100644
--- a/support/ld/ram.ld
+++ b/support/ld/ram.ld
@@ -25,8 +25,8 @@
/* Define memory spaces. */
MEMORY
{
- ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K
- rom (rx) : ORIGIN = 0x00000000, LENGTH = 0K
+ ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
}
diff --git a/support/openocd/flash.cfg b/support/openocd/flash.cfg
index eceac32..25fe23f 100644
--- a/support/openocd/flash.cfg
+++ b/support/openocd/flash.cfg
@@ -62,15 +62,15 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME
proc flash_chip {} {
echo "Halting..."
halt
- echo "Erasing 128KB..."
- flash erase_address 0x08000000 0x20000
+ echo "Erasing..."
+ flash erase_address 0x08000000 0x80000
echo "Flashing image..."
flash write_bank 0 build/maple.bin 0
echo "Verifying image..."