diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/lib/adc.c | 16 | ||||
| -rw-r--r-- | src/lib/rcc.c | 23 | ||||
| -rw-r--r-- | src/lib/rcc.h | 24 |
3 files changed, 41 insertions, 22 deletions
diff --git a/src/lib/adc.c b/src/lib/adc.c index ee2b17a..d584dba 100644 --- a/src/lib/adc.c +++ b/src/lib/adc.c @@ -23,9 +23,9 @@ * @brief Analog to digital converter routines */ +#include "libmaple.h" +#include "rcc.h" #include "adc.h" -#include <stdio.h> -#include <inttypes.h> /* The ADC input clock is generated from PCLK2/APB2 divided by a prescaler * and it must not exceed 14MHz. @@ -58,15 +58,9 @@ * At 55.5 cycles/sample, the external input impedance < 50kOhms*/ void adc_init(void) { - /* PCLK2 is the APB2 clock */ -// RCC_ADCCLKConfig(RCC_PCLK2_Div6); - - /* Enable ADC1 clock so that we can talk to it */ -// RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); - - /* Put everything back to power-on defaults */ -// RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); -// RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + rcc_set_adc_prescaler(PCLK2_DIV_2); + rcc_enable_clk_adc1(); + rcc_reset_adc1(); ADC_CR1 = 0; ADC_CR2 = CR2_EXTSEL_SWSTART | CR2_EXTTRIG; // Software triggers conversions diff --git a/src/lib/rcc.c b/src/lib/rcc.c index c08f1cd..bf76eb0 100644 --- a/src/lib/rcc.c +++ b/src/lib/rcc.c @@ -1,3 +1,10 @@ +/** + * @file rcc.c + * + * @brief Implements pretty much only the basic clock setup on the maple, + * exposes a handful of clock enable/disable and peripheral reset commands. + */ + #include "libmaple.h" #include "rcc.h" #include "stm32f10x_flash.h" @@ -83,15 +90,6 @@ static void hse_init(void) { } } - -void rcc_enable_clock(uint32 p) { - switch(p) { - default: - ASSERT(0); - break; - } -} - void rcc_init(void) { hse_init(); @@ -105,6 +103,11 @@ void rcc_init(void) { set_ahb_prescaler(SYSCLK_DIV_1); set_apb1_prescaler(HCLK_DIV_2); set_apb2_prescaler(HCLK_DIV_1); - pll_init(); } + +void rcc_set_adc_prescaler(uint32_t divider) { + uint32_t cfgr = __read(RCC_CFGR); + cfgr &= ~ADCPRE; + __write(RCC_CFGR, cfgr | PCLK2_DIV_2); +} diff --git a/src/lib/rcc.h b/src/lib/rcc.h index e3c80bd..5c9591b 100644 --- a/src/lib/rcc.h +++ b/src/lib/rcc.h @@ -11,7 +11,7 @@ #define RCC_CR (RCC_BASE + 0x0) #define RCC_CFGR (RCC_BASE + 0x4) #define RCC_CIR (RCC_BASE + 0x8) -#define RCC_APB2STR (RCC_BASE + 0xC) +#define RCC_APB2RSTR (RCC_BASE + 0xC) #define RCC_APB1RSTR (RCC_BASE + 0x10) #define RCC_AHBENR (RCC_BASE + 0x14) #define RCC_APB2ENR (RCC_BASE + 0x18) @@ -24,6 +24,7 @@ #define HSEON BIT(16) #define HSERDY *(volatile uint32_t*)(BITBAND_PERI(RCC_CR + 2, 0)) +#define ADCPRE 0x0000C000 #define HPRE 0x000000F0 #define PPRE2 0x00003800 // apb2 high speed prescaler #define PPRE1 0x00000700 // apb1 low-speed prescaler @@ -34,6 +35,7 @@ #define SYSCLK_DIV_1 (0x0 << 4) #define HCLK_DIV_1 0 #define HCLK_DIV_2 0x00000400 +#define PCLK2_DIV_2 0x00008000 #define PLLRDY BIT(25) #define PLLON BIT(24) @@ -42,6 +44,18 @@ #define RCC_CFGR_SWS 0x00000003 #define RCC_CFGR_SWS_PLL 0x00000002 +/* APB2 reset bits */ +#define RCC_APB2RSTR_USART1RST BIT(14) +#define RCC_APB2RSTR_SPI1RST BIT(12) +#define RCC_APB2RSTR_TIM1RST BIT(11) +#define RCC_APB2RSTR_ADC2RST BIT(10) +#define RCC_APB2RSTR_ADC1RST BIT(9) +#define RCC_APB2RSTR_IOERST BIT(6) +#define RCC_APB2RSTR_IODRST BIT(5) +#define RCC_APB2RSTR_IOCRST BIT(4) +#define RCC_APB2RSTR_IOBRST BIT(3) +#define RCC_APB2RSTR_IOARST BIT(2) +#define RCC_APB2RSTR_AFIORST BIT(0) /* APB2 peripheral clock enable bits */ #define RCC_APB2ENR_USART1EN BIT(14) @@ -78,7 +92,15 @@ #define rcc_enable_clk_usart2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_USART2EN) #define rcc_enable_clk_usart3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_USART3EN) +#define rcc_enable_clk_adc1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_ADC1EN) + +#define rcc_reset_adc1() { __set_bits(RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); \ + __clear_bits(RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); \ + } + + void rcc_init(void); +void rcc_set_adc_prescaler(uint32_t divider); #endif |