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Diffstat (limited to 'src/stm32lib/examples/TIM/Cascade_Synchro/main.c')
| -rwxr-xr-x | src/stm32lib/examples/TIM/Cascade_Synchro/main.c | 272 |
1 files changed, 272 insertions, 0 deletions
diff --git a/src/stm32lib/examples/TIM/Cascade_Synchro/main.c b/src/stm32lib/examples/TIM/Cascade_Synchro/main.c new file mode 100755 index 0000000..4dfce78 --- /dev/null +++ b/src/stm32lib/examples/TIM/Cascade_Synchro/main.c @@ -0,0 +1,272 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : main.c
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Main program body
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+TIM_OCInitTypeDef TIM_OCInitStructure;
+ErrorStatus HSEStartUpStatus;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+void NVIC_Configuration(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : main
+* Description : Main program
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+int main(void)
+{
+#ifdef DEBUG
+ debug();
+#endif
+
+ /* System Clocks Configuration */
+ RCC_Configuration();
+
+ /* NVIC Configuration */
+ NVIC_Configuration();
+
+ /* GPIO Configuration */
+ GPIO_Configuration();
+
+ /* Timers synchronisation in cascade mode ----------------------------
+ 1/TIM2 is configured as Master Timer:
+ - PWM Mode is used
+ - The TIM2 Update event is used as Trigger Output
+
+ 2/TIM3 is slave for TIM2 and Master for TIM4,
+ - PWM Mode is used
+ - The ITR1(TIM2) is used as input trigger
+ - Gated mode is used, so start and stop of slave counter
+ are controlled by the Master trigger output signal(TIM2 update event).
+ - The TIM3 Update event is used as Trigger Output.
+
+ 3/TIM4 is slave for TIM3,
+ - PWM Mode is used
+ - The ITR2(TIM3) is used as input trigger
+ - Gated mode is used, so start and stop of slave counter
+ are controlled by the Master trigger output signal(TIM3 update event).
+
+ The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
+
+ The Master Timer TIM2 is running at TIM2 frequency :
+ TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz
+ and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.
+
+ The TIM3 is running:
+ - At (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle
+ equal to TIM3_CCR1/(TIM3_ARR + 1) = 25%
+
+ The TIM4 is running:
+ - At (TIM3 frequency)/ (TIM4 period + 1) = 17.578 KHz and a duty cycle
+ equal to TIM4_CCR1/(TIM4_ARR + 1) = 25%
+ -------------------------------------------------------------------- */
+
+ /* Time base configuration */
+ TIM_TimeBaseStructure.TIM_Period = 255;
+ TIM_TimeBaseStructure.TIM_Prescaler = 0;
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+
+ TIM_TimeBaseStructure.TIM_Period = 3;
+ TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
+
+ TIM_TimeBaseStructure.TIM_Period = 3;
+ TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
+
+ /* Master Configuration in PWM1 Mode */
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_Pulse = 64;
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+
+ TIM_OC1Init(TIM2, &TIM_OCInitStructure);
+
+ /* Select the Master Slave Mode */
+ TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);
+
+ /* Master Mode selection */
+ TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
+
+ /* Slaves Configuration: PWM1 Mode */
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_Pulse = 1;
+
+ TIM_OC1Init(TIM3, &TIM_OCInitStructure);
+
+ TIM_OC1Init(TIM4, &TIM_OCInitStructure);
+
+ /* Slave Mode selection: TIM3 */
+ TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
+ TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);
+
+ /* Select the Master Slave Mode */
+ TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
+
+ /* Master Mode selection: TIM3 */
+ TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update);
+
+ /* Slave Mode selection: TIM4 */
+ TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
+ TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2);
+
+ /* TIM enable counter */
+ TIM_Cmd(TIM3, ENABLE);
+ TIM_Cmd(TIM2, ENABLE);
+ TIM_Cmd(TIM4, ENABLE);
+
+ while (1)
+ {}
+}
+
+/*******************************************************************************
+* Function Name : RCC_Configuration
+* Description : Configures the different system clocks.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_Configuration(void)
+{
+ /* RCC system reset(for debug purpose) */
+ RCC_DeInit();
+
+ /* Enable HSE */
+ RCC_HSEConfig(RCC_HSE_ON);
+
+ /* Wait till HSE is ready */
+ HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+ if (HSEStartUpStatus == SUCCESS)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
+
+ /* Flash 2 wait state */
+ FLASH_SetLatency(FLASH_Latency_2);
+
+ /* HCLK = SYSCLK */
+ RCC_HCLKConfig(RCC_SYSCLK_Div1);
+
+ /* PCLK2 = HCLK */
+ RCC_PCLK2Config(RCC_HCLK_Div1);
+
+ /* PCLK1 = HCLK/2 */
+ RCC_PCLK1Config(RCC_HCLK_Div2);
+
+ /* PLLCLK = 8MHz * 9 = 72 MHz */
+ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+
+ /* Enable PLL */
+ RCC_PLLCmd(ENABLE);
+
+ /* Wait till PLL is ready */
+ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+ {}
+
+ /* Select PLL as system clock source */
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+ /* Wait till PLL is used as system clock source */
+ while (RCC_GetSYSCLKSource() != 0x08)
+ {}
+ }
+ /* TIM2, TIM3 and TIM4 clock enable */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
+ RCC_APB1Periph_TIM4, ENABLE);
+
+
+ /* GPIOA and GPIOB clock enable */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name : GPIO_Configuration
+* Description : Configure the GPIOD Pins.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_Configuration(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* GPIOA Configuration: PA0(TIM2 CH1) and PA6(TIM3 CH1) as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_6;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name : NVIC_Configuration
+* Description : Configures Vector Table base location.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x20000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+}
+
+#ifdef DEBUG
+/*******************************************************************************
+* Function Name : assert_failed
+* Description : Reports the name of the source file and the source line number
+* where the assert_param error has occurred.
+* Input : - file: pointer to the source file name
+* - line: assert_param error line source number
+* Output : None
+* Return : None
+*******************************************************************************/
+void assert_failed(u8* file, u32 line)
+{
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+ while (1)
+ {}
+}
+#endif
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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