diff options
Diffstat (limited to 'src/stm32lib/examples/DMA/FSMC/main.c')
| -rwxr-xr-x | src/stm32lib/examples/DMA/FSMC/main.c | 275 |
1 files changed, 275 insertions, 0 deletions
diff --git a/src/stm32lib/examples/DMA/FSMC/main.c b/src/stm32lib/examples/DMA/FSMC/main.c new file mode 100755 index 0000000..f5b2df7 --- /dev/null +++ b/src/stm32lib/examples/DMA/FSMC/main.c @@ -0,0 +1,275 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : main.c
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Main program body.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_sram.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
+
+/* Private define ------------------------------------------------------------*/
+#define BufferSize 32
+#define Bank1_SRAM3_ADDR ((u32)0x68000000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+DMA_InitTypeDef DMA_InitStructure;
+ErrorStatus HSEStartUpStatus;
+volatile TestStatus TransferStatus;
+uc32 SRC_Const_Buffer[BufferSize]= {0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10,
+ 0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20,
+ 0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30,
+ 0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40,
+ 0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50,
+ 0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60,
+ 0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70,
+ 0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80};
+u8 DST_Buffer[4*BufferSize], Idx = 0;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void NVIC_Configuration(void);
+void Delay(vu32 nCount);
+TestStatus Buffercmp(uc32* pBuffer, u32* pBuffer1, u16 BufferLength);
+
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : main
+* Description : Main program.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+int main(void)
+{
+#ifdef DEBUG
+ debug();
+#endif
+
+ /* System Clocks Configuration */
+ RCC_Configuration();
+
+ /* NVIC Configuration */
+ NVIC_Configuration();
+
+ /* FSMC for SRAM and SRAM pins configuration */
+ FSMC_SRAM_Init();
+
+ /* Write to FSMC -----------------------------------------------------------*/
+ /* DMA2 channel5 configuration */
+ DMA_DeInit(DMA2_Channel5);
+ DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)SRC_Const_Buffer;
+ DMA_InitStructure.DMA_MemoryBaseAddr = (u32)Bank1_SRAM3_ADDR;
+ DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+ DMA_InitStructure.DMA_BufferSize = 32;
+ DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
+ DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+ DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+ DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+ DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+ DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+ DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
+ DMA_Init(DMA2_Channel5, &DMA_InitStructure);
+
+ /* Enable DMA2 channel5 */
+ DMA_Cmd(DMA2_Channel5, ENABLE);
+
+ /* Check if DMA2 channel5 transfer is finished */
+ while(!DMA_GetFlagStatus(DMA2_FLAG_TC5));
+
+ /* Clear DMA2 channel5 transfer complete flag bit */
+ DMA_ClearFlag(DMA2_FLAG_TC5);
+
+ /* Read from FSMC ----------------------------------------------------------*/
+ /* Destination buffer initialization */
+ for(Idx=0; Idx<128; Idx++) DST_Buffer[Idx]=0;
+
+ /* DMA1 channel3 configuration */
+ DMA_DeInit(DMA1_Channel3);
+ DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)Bank1_SRAM3_ADDR;
+ DMA_InitStructure.DMA_MemoryBaseAddr = (u32)DST_Buffer;
+ DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+ DMA_InitStructure.DMA_BufferSize = 128;
+ DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
+ DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+ DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+ DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+ DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
+ DMA_Init(DMA1_Channel3, &DMA_InitStructure);
+
+ /* Enable DMA1 channel3 */
+ DMA_Cmd(DMA1_Channel3, ENABLE);
+
+ /* Check if DMA1 channel3 transfer is finished */
+ while(!DMA_GetFlagStatus(DMA1_FLAG_TC3));
+
+ /* Clear DMA1 channel3 transfer complete flag bit */
+ DMA_ClearFlag(DMA1_FLAG_TC3);
+
+ /* Check if the transmitted and received data are equal */
+ TransferStatus = Buffercmp(SRC_Const_Buffer, (u32*)DST_Buffer, BufferSize);
+ /* TransferStatus = PASSED, if the transmitted and received data
+ are the same */
+ /* TransferStatus = FAILED, if the transmitted and received data
+ are different */
+
+ while (1)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_Configuration
+* Description : Configures the different system clocks.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_Configuration(void)
+{
+ /* RCC system reset(for debug purpose) */
+ RCC_DeInit();
+
+ /* Enable HSE */
+ RCC_HSEConfig(RCC_HSE_ON);
+
+ /* Wait till HSE is ready */
+ HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+ if(HSEStartUpStatus == SUCCESS)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
+
+ /* Flash 2 wait state */
+ FLASH_SetLatency(FLASH_Latency_2);
+
+ /* HCLK = SYSCLK */
+ RCC_HCLKConfig(RCC_SYSCLK_Div1);
+
+ /* PCLK2 = HCLK */
+ RCC_PCLK2Config(RCC_HCLK_Div1);
+
+ /* PCLK1 = HCLK/2 */
+ RCC_PCLK1Config(RCC_HCLK_Div2);
+
+ /* PLLCLK = 8MHz * 9 = 72 MHz */
+ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+
+ /* Enable PLL */
+ RCC_PLLCmd(ENABLE);
+
+ /* Wait till PLL is ready */
+ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+ /* Wait till PLL is used as system clock source */
+ while(RCC_GetSYSCLKSource() != 0x08)
+ {
+ }
+ }
+
+/* Enable peripheral clocks --------------------------------------------------*/
+ /* DMA1 and DMA2 clock enable */
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_DMA2, ENABLE);
+ /* FSMC clock enable */
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name : NVIC_Configuration
+* Description : Configures Vector Table base location.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x20000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+}
+
+/*******************************************************************************
+* Function Name : Delay
+* Description : Inserts a delay time.
+* Input : nCount: specifies the delay time length.
+* Output : None
+* Return : None
+*******************************************************************************/
+void Delay(vu32 nCount)
+{
+ for(; nCount != 0; nCount--);
+}
+
+/*******************************************************************************
+* Function Name : Buffercmp
+* Description : Compares two buffers.
+* Input : - pBuffer, pBuffer1: buffers to be compared.
+* : - BufferLength: buffer's length
+* Output : None
+* Return : PASSED: pBuffer identical to pBuffer1
+* FAILED: pBuffer differs from pBuffer1
+*******************************************************************************/
+TestStatus Buffercmp(uc32* pBuffer, u32* pBuffer1, u16 BufferLength)
+{
+ while(BufferLength--)
+ {
+ if(*pBuffer != *pBuffer1)
+ {
+ return FAILED;
+ }
+
+ pBuffer++;
+ pBuffer1++;
+ }
+
+ return PASSED;
+}
+
+#ifdef DEBUG
+/*******************************************************************************
+* Function Name : assert_failed
+* Description : Reports the name of the source file and the source line number
+* where the assert_param error has occurred.
+* Input : - file: pointer to the source file name
+* - line: assert_param error line source number
+* Output : None
+* Return : None
+*******************************************************************************/
+void assert_failed(u8* file, u32 line)
+{
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+ /* Infinite loop */
+ while (1)
+ {
+ }
+}
+#endif
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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