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-rw-r--r--src/lib/gpio.c14
-rw-r--r--src/lib/rcc.c109
-rw-r--r--src/lib/rcc.h75
-rw-r--r--src/lib/timers.c9
-rw-r--r--src/lib/usart.c9
5 files changed, 126 insertions, 90 deletions
diff --git a/src/lib/gpio.c b/src/lib/gpio.c
index 0335a51..39341af 100644
--- a/src/lib/gpio.c
+++ b/src/lib/gpio.c
@@ -24,17 +24,15 @@
*/
#include "libmaple.h"
-#include "stm32f10x_rcc.h"
+#include "rcc.h"
#include "gpio.h"
void gpio_init(void) {
- /* Turn on clocks for GPIO */
-// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |
-// RCC_APB2Periph_GPIOB |
-// RCC_APB2Periph_GPIOC |
-// RCC_APB2Periph_GPIOD |
-// RCC_APB2Periph_AFIO,
-// ENABLE);
+ rcc_enable_clk_gpioa();
+ rcc_enable_clk_gpiob();
+ rcc_enable_clk_gpioc();
+ rcc_enable_clk_gpiod();
+ rcc_enable_clk_afio();
}
void gpio_set_mode(GPIO_Port* port, uint8 gpio_pin, uint8 mode) {
diff --git a/src/lib/rcc.c b/src/lib/rcc.c
index 9cefcea..c08f1cd 100644
--- a/src/lib/rcc.c
+++ b/src/lib/rcc.c
@@ -2,122 +2,100 @@
#include "rcc.h"
#include "stm32f10x_flash.h"
-#define RCC_BASE 0x40021000
-#define RCC_CR (RCC_BASE + 0x0)
-#define RCC_CFGR (RCC_BASE + 0x4)
-#define RCC_CIR (RCC_BASE + 0x8)
-#define RCC_APB2STR (RCC_BASE + 0xC)
-#define RCC_APB1RSTR (RCC_BASE + 0x10)
-#define RCC_AHBENR (RCC_BASE + 0x14)
-#define RCC_APB2ENR (RCC_BASE + 0x18)
-#define RCC_APB1ENR (RCC_BASE + 0x1C)
-#define RCC_BDCR (RCC_BASE + 0x20)
-#define RCC_CSR (RCC_BASE + 0x24)
-#define RCC_AHBSTR (RCC_BASE + 0x28)
-#define RCC_CFGR2 (RCC_BASE + 0x2C))
-
-#define HSEON BIT(16)
-
-#define HSERDY *(volatile uint32_t*)(BITBAND_PERI(RCC_CR + 2, 0))
-
-#define HPRE 0x000000F0
-#define PPRE 0x00000700
-#define PLLMUL 0x002C0000
-#define PLL_MUL_9 0x001C0000
-#define PLLSRC BIT(16)
-#define SYSCLK_DIV_1 (0x0 << 4)
-#define HCLK_DIV_1 0
-#define HCLK_DIV_2 0x00000400
-
-#define PLLRDY BIT(25)
-#define PLLON BIT(24)
-#define PLL_INPUT_CLK_HSE BIT(16)
-
-
static void set_ahb_prescaler(uint32_t divider) {
- uint32_t tmp = __read(RCC_CFGR);
+ uint32_t cfgr = __read(RCC_CFGR);
+
+ cfgr &= ~HPRE;
switch (divider) {
case SYSCLK_DIV_1:
- tmp &= ~HPRE;
- tmp |= SYSCLK_DIV_1;
+ cfgr |= SYSCLK_DIV_1;
break;
default:
ASSERT(0);
}
- __write(RCC_CFGR, tmp);
+ __write(RCC_CFGR, cfgr);
}
static void set_apb1_prescaler(uint32_t divider) {
- uint32_t tmp = __read(RCC_CFGR);
+ uint32_t cfgr = __read(RCC_CFGR);
+
+ cfgr &= ~PPRE1;
switch (divider) {
case HCLK_DIV_2:
- tmp &= ~PPRE;
- tmp |= HCLK_DIV_2;
+ cfgr |= HCLK_DIV_2;
break;
default:
ASSERT(0);
}
- __write(RCC_CFGR, tmp);
+ __write(RCC_CFGR, cfgr);
}
static void set_apb2_prescaler(uint32_t divider) {
- uint32_t tmp = __read(RCC_CFGR);
+ uint32_t cfgr = __read(RCC_CFGR);
+
+ cfgr &= ~PPRE2;
switch (divider) {
case HCLK_DIV_1:
+ cfgr |= HCLK_DIV_1;
break;
default:
ASSERT(0);
}
+
+ __write(RCC_CFGR, cfgr);
}
+/* FIXME: magic numbers */
static void pll_init(void) {
- uint32_t tmp;
+ uint32_t cfgr;
- /* set pll multiplier to 9 */
- tmp = __read(RCC_CFGR);
- tmp &= ~PLLMUL;
- tmp |= PLL_MUL_9;
+ cfgr = __read(RCC_CFGR);
+ cfgr &= (~PLLMUL | PLL_INPUT_CLK_HSE);
- /* set pll clock to be hse */
- tmp |= PLL_INPUT_CLK_HSE;
- __write(RCC_CFGR, tmp);
+ /* pll multiplier 9, input clock hse */
+ __write(RCC_CFGR, cfgr | PLL_MUL_9 | PLL_INPUT_CLK_HSE);
- /* turn on the pll */
+ /* enable pll */
__set_bits(RCC_CR, PLLON);
-
while(!__get_bits(RCC_CR, PLLRDY)) {
asm volatile("nop");
}
/* select pll for system clock source */
- tmp = __read(RCC_CFGR);
- tmp &= ~0x3;
- tmp |= 0x2;
- __write(RCC_CFGR, tmp);
+ cfgr = __read(RCC_CFGR);
+ cfgr &= ~RCC_CFGR_SWS;
+ __write(RCC_CFGR, cfgr | RCC_CFGR_SWS_PLL);
while (__get_bits(RCC_CFGR, 0x00000008) != 0x8) {
asm volatile("nop");
}
}
-
-void rcc_enable(uint32 p) {
-}
-
-void rcc_init(void) {
-
-
+static void hse_init(void) {
__set_bits(RCC_CR, HSEON);
-
while (!HSERDY) {
asm volatile("nop");
}
+}
+
+
+void rcc_enable_clock(uint32 p) {
+ switch(p) {
+ default:
+ ASSERT(0);
+ break;
+ }
+}
+void rcc_init(void) {
+ hse_init();
+
+ /* Leave this here for now... */
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd( (u32)FLASH_PrefetchBuffer_Enable);
@@ -129,9 +107,4 @@ void rcc_init(void) {
set_apb2_prescaler(HCLK_DIV_1);
pll_init();
-
- __set_bits(RCC_APB2ENR, BIT(2));
- __set_bits(RCC_APB2ENR, BIT(3));
- __set_bits(RCC_APB2ENR, BIT(4));
- __set_bits(RCC_APB2ENR, BIT(5));
}
diff --git a/src/lib/rcc.h b/src/lib/rcc.h
index f06fb5f..e3c80bd 100644
--- a/src/lib/rcc.h
+++ b/src/lib/rcc.h
@@ -7,12 +7,77 @@
#ifndef _RCC_H_
#define _RCC_H_
-#define RCC_TIMER1
-#define RCC_TIMER2
-#define RCC_TIMER3
-#define RCC_TIMER4
+#define RCC_BASE 0x40021000
+#define RCC_CR (RCC_BASE + 0x0)
+#define RCC_CFGR (RCC_BASE + 0x4)
+#define RCC_CIR (RCC_BASE + 0x8)
+#define RCC_APB2STR (RCC_BASE + 0xC)
+#define RCC_APB1RSTR (RCC_BASE + 0x10)
+#define RCC_AHBENR (RCC_BASE + 0x14)
+#define RCC_APB2ENR (RCC_BASE + 0x18)
+#define RCC_APB1ENR (RCC_BASE + 0x1C)
+#define RCC_BDCR (RCC_BASE + 0x20)
+#define RCC_CSR (RCC_BASE + 0x24)
+#define RCC_AHBSTR (RCC_BASE + 0x28)
+#define RCC_CFGR2 (RCC_BASE + 0x2C))
+
+#define HSEON BIT(16)
+#define HSERDY *(volatile uint32_t*)(BITBAND_PERI(RCC_CR + 2, 0))
+
+#define HPRE 0x000000F0
+#define PPRE2 0x00003800 // apb2 high speed prescaler
+#define PPRE1 0x00000700 // apb1 low-speed prescaler
+
+#define PLLMUL 0x002C0000
+#define PLL_MUL_9 0x001C0000
+#define PLLSRC BIT(16)
+#define SYSCLK_DIV_1 (0x0 << 4)
+#define HCLK_DIV_1 0
+#define HCLK_DIV_2 0x00000400
+
+#define PLLRDY BIT(25)
+#define PLLON BIT(24)
+#define PLL_INPUT_CLK_HSE BIT(16)
+
+#define RCC_CFGR_SWS 0x00000003
+#define RCC_CFGR_SWS_PLL 0x00000002
+
+
+/* APB2 peripheral clock enable bits */
+#define RCC_APB2ENR_USART1EN BIT(14)
+#define RCC_APB2ENR_SPI1EN BIT(12)
+#define RCC_APB2ENR_TIM1EN BIT(11)
+#define RCC_APB2ENR_ADC2EN BIT(10)
+#define RCC_APB2ENR_ADC1EN BIT(9)
+#define RCC_APB2ENR_IOEEN BIT(6)
+#define RCC_APB2ENR_IODEN BIT(5)
+#define RCC_APB2ENR_IOCEN BIT(4)
+#define RCC_APB2ENR_IOBEN BIT(3)
+#define RCC_APB2ENR_IOAEN BIT(2)
+#define RCC_APB2ENR_AFIOEN BIT(0)
+
+/* APB1 peripheral clock enable bits */
+#define RCC_APB1ENR_TIM2EN BIT(0)
+#define RCC_APB1ENR_TIM3EN BIT(1)
+#define RCC_APB1ENR_TIM4EN BIT(2)
+#define RCC_APB1ENR_USART2EN BIT(17)
+#define RCC_APB1ENR_USART3EN BIT(18)
+
+#define rcc_enable_clk_timer1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_TIM1EN)
+#define rcc_enable_clk_timer2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM2EN)
+#define rcc_enable_clk_timer3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM3EN)
+#define rcc_enable_clk_timer4() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM4EN)
+
+#define rcc_enable_clk_gpioa() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOAEN)
+#define rcc_enable_clk_gpiob() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOBEN)
+#define rcc_enable_clk_gpioc() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOCEN)
+#define rcc_enable_clk_gpiod() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IODEN)
+#define rcc_enable_clk_afio() __set_bits(RCC_APB2ENR, RCC_APB2ENR_AFIOEN)
+
+#define rcc_enable_clk_usart1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_USART1EN)
+#define rcc_enable_clk_usart2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_USART2EN)
+#define rcc_enable_clk_usart3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_USART3EN)
-void rcc_enable(uint32 p);
void rcc_init(void);
#endif
diff --git a/src/lib/timers.c b/src/lib/timers.c
index a248235..e187428 100644
--- a/src/lib/timers.c
+++ b/src/lib/timers.c
@@ -79,21 +79,20 @@ void timer_init(uint8_t timer_num, uint16_t prescale) {
switch(timer_num) {
case 1:
timer = (Timer*)TIMER1_BASE;
-// rcc_enable(RCC_TIMER1);
+ rcc_enable_clk_timer1();
is_advanced = 1;
break;
case 2:
timer = (Timer*)TIMER2_BASE;
-// rcc_enable(RCC_TIMER2);
- //RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
+ rcc_enable_clk_timer2();
break;
case 3:
timer = (Timer*)TIMER3_BASE;
-// rcc_enable(RCC_TIMER3);
+ rcc_enable_clk_timer3();
break;
case 4:
timer = (Timer*)TIMER4_BASE;
- // rcc_enable(RCC_TIMER4);
+ rcc_enable_clk_timer4();
break;
}
diff --git a/src/lib/usart.c b/src/lib/usart.c
index b7c3ea8..545f64a 100644
--- a/src/lib/usart.c
+++ b/src/lib/usart.c
@@ -24,8 +24,9 @@
*/
#include "libmaple.h"
-#include "usart.h"
+#include "rcc.h"
#include "nvic.h"
+#include "usart.h"
#define USART1_BASE 0x40013800
#define USART2_BASE 0x40004400
@@ -122,21 +123,21 @@ void usart_init(uint8 usart_num, uint32 baud) {
port = (usart_port*)USART1_BASE;
ring_buf = &ring_buf1;
clk_speed = USART1_CLK;
-// RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ rcc_enable_clk_usart1();
REG_SET(NVIC_ISER1, BIT(5));
break;
case 2:
port = (usart_port*)USART2_BASE;
ring_buf = &ring_buf2;
clk_speed = USART2_CLK;
-// RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+ rcc_enable_clk_usart2();
REG_SET(NVIC_ISER1, BIT(6));
break;
case 3:
port = (usart_port*)USART3_BASE;
ring_buf = &ring_buf3;
clk_speed = USART3_CLK;
-// RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+ rcc_enable_clk_usart3();
REG_SET(NVIC_ISER1, BIT(7));
break;
default:
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 05:04:20 +0000