diff options
Diffstat (limited to 'source/libmaple/api')
25 files changed, 2773 insertions, 102 deletions
diff --git a/source/libmaple/api/adc.rst b/source/libmaple/api/adc.rst index 8817055..fecaece 100644 --- a/source/libmaple/api/adc.rst +++ b/source/libmaple/api/adc.rst @@ -4,9 +4,212 @@ ``adc.h`` ========= -[Stub] support. +:ref:`Analog to Digital Conversion <adc>` (ADC) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: adc.h +Types +----- + +.. doxygenstruct:: adc_dev +.. doxygenstruct:: adc_reg_map +.. doxygenenum:: adc_extsel_event +.. doxygenenum:: adc_smp_rate + +Devices +------- + +.. doxygenvariable:: ADC1 +.. doxygenvariable:: ADC2 +.. doxygenvariable:: ADC3 + +Functions +--------- + +.. doxygenfunction:: adc_init +.. doxygenfunction:: adc_calibrate +.. doxygenfunction:: adc_set_extsel +.. doxygenfunction:: adc_enable +.. doxygenfunction:: adc_disable +.. doxygenfunction:: adc_disable_all +.. doxygenfunction:: adc_foreach +.. doxygenfunction:: adc_set_sample_rate +.. doxygenfunction:: adc_read +.. doxygenfunction:: adc_set_reg_seqlen +.. doxygenfunction:: adc_set_exttrig + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: ADC1_BASE +.. doxygendefine:: ADC2_BASE +.. doxygendefine:: ADC3_BASE + +Register Bit Definitions +------------------------ + +Status register +~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_SR_AWD_BIT +.. doxygendefine:: ADC_SR_EOC_BIT +.. doxygendefine:: ADC_SR_JEOC_BIT +.. doxygendefine:: ADC_SR_JSTRT_BIT +.. doxygendefine:: ADC_SR_STRT_BIT + +.. doxygendefine:: ADC_SR_AWD +.. doxygendefine:: ADC_SR_EOC +.. doxygendefine:: ADC_SR_JEOC +.. doxygendefine:: ADC_SR_JSTRT +.. doxygendefine:: ADC_SR_STRT + +Control register 1 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_CR1_EOCIE_BIT +.. doxygendefine:: ADC_CR1_AWDIE_BIT +.. doxygendefine:: ADC_CR1_JEOCIE_BIT +.. doxygendefine:: ADC_CR1_SCAN_BIT +.. doxygendefine:: ADC_CR1_AWDSGL_BIT +.. doxygendefine:: ADC_CR1_JAUTO_BIT +.. doxygendefine:: ADC_CR1_DISCEN_BIT +.. doxygendefine:: ADC_CR1_JDISCEN_BIT +.. doxygendefine:: ADC_CR1_JAWDEN_BIT +.. doxygendefine:: ADC_CR1_AWDEN_BIT + +.. doxygendefine:: ADC_CR1_AWDCH +.. doxygendefine:: ADC_CR1_EOCIE +.. doxygendefine:: ADC_CR1_AWDIE +.. doxygendefine:: ADC_CR1_JEOCIE +.. doxygendefine:: ADC_CR1_SCAN +.. doxygendefine:: ADC_CR1_AWDSGL +.. doxygendefine:: ADC_CR1_JAUTO +.. doxygendefine:: ADC_CR1_DISCEN +.. doxygendefine:: ADC_CR1_JDISCEN +.. doxygendefine:: ADC_CR1_DISCNUM +.. doxygendefine:: ADC_CR1_JAWDEN +.. doxygendefine:: ADC_CR1_AWDEN + +Control register 2 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_CR2_ADON_BIT +.. doxygendefine:: ADC_CR2_CONT_BIT +.. doxygendefine:: ADC_CR2_CAL_BIT +.. doxygendefine:: ADC_CR2_RSTCAL_BIT +.. doxygendefine:: ADC_CR2_DMA_BIT +.. doxygendefine:: ADC_CR2_ALIGN_BIT +.. doxygendefine:: ADC_CR2_JEXTTRIG_BIT +.. doxygendefine:: ADC_CR2_EXTTRIG_BIT +.. doxygendefine:: ADC_CR2_JSWSTART_BIT +.. doxygendefine:: ADC_CR2_SWSTART_BIT +.. doxygendefine:: ADC_CR2_TSEREFE_BIT + +.. doxygendefine:: ADC_CR2_ADON +.. doxygendefine:: ADC_CR2_CONT +.. doxygendefine:: ADC_CR2_CAL +.. doxygendefine:: ADC_CR2_RSTCAL +.. doxygendefine:: ADC_CR2_DMA +.. doxygendefine:: ADC_CR2_ALIGN +.. doxygendefine:: ADC_CR2_JEXTSEL +.. doxygendefine:: ADC_CR2_JEXTTRIG +.. doxygendefine:: ADC_CR2_EXTSEL +.. doxygendefine:: ADC_CR2_EXTTRIG +.. doxygendefine:: ADC_CR2_JSWSTART +.. doxygendefine:: ADC_CR2_SWSTART +.. doxygendefine:: ADC_CR2_TSEREFE + +Sample time register 1 +~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_SMPR1_SMP17 +.. doxygendefine:: ADC_SMPR1_SMP16 +.. doxygendefine:: ADC_SMPR1_SMP15 +.. doxygendefine:: ADC_SMPR1_SMP14 +.. doxygendefine:: ADC_SMPR1_SMP13 +.. doxygendefine:: ADC_SMPR1_SMP12 +.. doxygendefine:: ADC_SMPR1_SMP11 +.. doxygendefine:: ADC_SMPR1_SMP10 + +Sample time register 2 +~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_SMPR2_SMP9 +.. doxygendefine:: ADC_SMPR2_SMP8 +.. doxygendefine:: ADC_SMPR2_SMP7 +.. doxygendefine:: ADC_SMPR2_SMP6 +.. doxygendefine:: ADC_SMPR2_SMP5 +.. doxygendefine:: ADC_SMPR2_SMP4 +.. doxygendefine:: ADC_SMPR2_SMP3 +.. doxygendefine:: ADC_SMPR2_SMP2 +.. doxygendefine:: ADC_SMPR2_SMP1 +.. doxygendefine:: ADC_SMPR2_SMP0 + +Injected channel data offset register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_JOFR_JOFFSET + +Watchdog high threshold register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_HTR_HT + +Watchdog low threshold register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_LTR_LT + +Regular sequence register 1 +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_SQR1_L +.. doxygendefine:: ADC_SQR1_SQ16 +.. doxygendefine:: ADC_SQR1_SQ15 +.. doxygendefine:: ADC_SQR1_SQ14 +.. doxygendefine:: ADC_SQR1_SQ13 + +Regular sequence register 2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_SQR2_SQ12 +.. doxygendefine:: ADC_SQR2_SQ11 +.. doxygendefine:: ADC_SQR2_SQ10 +.. doxygendefine:: ADC_SQR2_SQ9 +.. doxygendefine:: ADC_SQR2_SQ8 +.. doxygendefine:: ADC_SQR2_SQ7 + +Regular sequence register 3 +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_SQR3_SQ6 +.. doxygendefine:: ADC_SQR3_SQ5 +.. doxygendefine:: ADC_SQR3_SQ4 +.. doxygendefine:: ADC_SQR3_SQ3 +.. doxygendefine:: ADC_SQR3_SQ2 +.. doxygendefine:: ADC_SQR3_SQ1 + +Injected sequence register +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_JSQR_JL +.. doxygendefine:: ADC_JSQR_JL_1CONV +.. doxygendefine:: ADC_JSQR_JL_2CONV +.. doxygendefine:: ADC_JSQR_JL_3CONV +.. doxygendefine:: ADC_JSQR_JL_4CONV +.. doxygendefine:: ADC_JSQR_JSQ4 +.. doxygendefine:: ADC_JSQR_JSQ3 +.. doxygendefine:: ADC_JSQR_JSQ2 +.. doxygendefine:: ADC_JSQR_JSQ1 + +Injected data registers +~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_JDR_JDATA + +Regular data register +~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: ADC_DR_ADC2DATA +.. doxygendefine:: ADC_DR_DATA diff --git a/source/libmaple/api/bitband.rst b/source/libmaple/api/bitband.rst index fd57944..5251015 100644 --- a/source/libmaple/api/bitband.rst +++ b/source/libmaple/api/bitband.rst @@ -4,9 +4,12 @@ ``bitband.h`` ============= -[Stub] support. +Bit-banding support. -Library Documentation ---------------------- +Functions +--------- -.. doxygenfile:: bitband.h +.. doxygenfunction:: bb_sram_get_bit +.. doxygenfunction:: bb_sram_set_bit +.. doxygenfunction:: bb_peri_get_bit +.. doxygenfunction:: bb_peri_set_bit diff --git a/source/libmaple/api/bkp.rst b/source/libmaple/api/bkp.rst index 9a697c7..4f0115b 100644 --- a/source/libmaple/api/bkp.rst +++ b/source/libmaple/api/bkp.rst @@ -4,9 +4,76 @@ ``bkp.h`` ========= -[Stub] support. +Backup register (BKP) suport. -Library Documentation +.. contents:: Contents + :local: + +Types +----- + +.. doxygenstruct:: bkp_dev +.. doxygenstruct:: bkp_reg_map + +Devices +------- + +.. doxygenvariable:: BKP + +Convenience Functions --------------------- -.. doxygenfile:: bkp.h +.. doxygenfunction:: bkp_init +.. doxygenfunction:: bkp_enable_writes +.. doxygenfunction:: bkp_disable_writes +.. doxygenfunction:: bkp_read +.. doxygenfunction:: bkp_write + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: BKP_BASE + +Register Bit Definitions +------------------------ + +Data Registers +~~~~~~~~~~~~~~ + +.. doxygendefine:: BKP_DR_D + +RTC Clock Calibration Register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: BKP_RTCCR_ASOS_BIT +.. doxygendefine:: BKP_RTCCR_ASOE_BIT +.. doxygendefine:: BKP_RTCCR_CCO_BIT + +.. doxygendefine:: BKP_RTCCR_ASOS +.. doxygendefine:: BKP_RTCCR_ASOE +.. doxygendefine:: BKP_RTCCR_CCO +.. doxygendefine:: BKP_RTCCR_CAL + +Backup control register +~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: BKP_CR_TPAL_BIT +.. doxygendefine:: BKP_CR_TPE_BIT + +.. doxygendefine:: BKP_CR_TPAL +.. doxygendefine:: BKP_CR_TPE + +Backup control/status register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: BKP_CSR_TIF_BIT +.. doxygendefine:: BKP_CSR_TEF_BIT +.. doxygendefine:: BKP_CSR_TPIE_BIT +.. doxygendefine:: BKP_CSR_CTI_BIT +.. doxygendefine:: BKP_CSR_CTE_BIT + +.. doxygendefine:: BKP_CSR_TIF +.. doxygendefine:: BKP_CSR_TEF +.. doxygendefine:: BKP_CSR_TPIE +.. doxygendefine:: BKP_CSR_CTI +.. doxygendefine:: BKP_CSR_CTE diff --git a/source/libmaple/api/dac.rst b/source/libmaple/api/dac.rst index 038753b..55c8faf 100644 --- a/source/libmaple/api/dac.rst +++ b/source/libmaple/api/dac.rst @@ -4,9 +4,120 @@ ``dac.h`` ========= -[Stub] support. +Digital to Analog Conversion (DAC) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: dac.h +Types +----- + +.. doxygenstruct:: dac_dev +.. doxygenstruct:: dac_reg_map + +Devices +------- + +.. doxygenvariable:: DAC + +Functions +--------- + +.. doxygenfunction:: dac_init +.. doxygenfunction:: dac_write_channel +.. doxygenfunction:: dac_enable_channel +.. doxygenfunction:: dac_disable_channel + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: DAC_BASE + +Register Bit Definitions +------------------------ + +Control register +~~~~~~~~~~~~~~~~ + +**Channel 1**: + +.. doxygendefine:: DAC_CR_EN1 +.. doxygendefine:: DAC_CR_BOFF1 +.. doxygendefine:: DAC_CR_TEN1 +.. doxygendefine:: DAC_CR_TSEL1 +.. doxygendefine:: DAC_CR_WAVE1 +.. doxygendefine:: DAC_CR_MAMP1 +.. doxygendefine:: DAC_CR_DMAEN1 + +**Channel 2**: + +.. doxygendefine:: DAC_CR_EN2 +.. doxygendefine:: DAC_CR_BOFF2 +.. doxygendefine:: DAC_CR_TEN2 +.. doxygendefine:: DAC_CR_TSEL2 +.. doxygendefine:: DAC_CR_WAVE2 +.. doxygendefine:: DAC_CR_MAMP2 +.. doxygendefine:: DAC_CR_DMAEN2 + +Software trigger register +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_SWTRIGR_SWTRIG1 +.. doxygendefine:: DAC_SWTRIGR_SWTRIG2 + +Channel 1 12-bit right-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR12R1_DACC1DHR + +Channel 1 12-bit left-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR12L1_DACC1DHR + +Channel 1 8-bit left-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR8R1_DACC1DHR + +Channel 2 12-bit right-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR12R2_DACC2DHR + +Channel 2 12-bit left-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR12L2_DACC2DHR + +Channel 2 8-bit left-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR8R2_DACC2DHR + +Dual DAC 12-bit right-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR12RD_DACC1DHR +.. doxygendefine:: DAC_DHR12RD_DACC2DHR + +Dual DAC 12-bit left-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR12LD_DACC1DHR +.. doxygendefine:: DAC_DHR12LD_DACC2DHR + +Dual DAC 8-bit left-aligned data holding register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DHR8RD_DACC1DHR +.. doxygendefine:: DAC_DHR8RD_DACC2DHR + +Channel 1 data output register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DAC_DOR1_DACC1DOR + +Channel 1 data output register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. doxygendefine:: DAC_DOR2_DACC2DOR diff --git a/source/libmaple/api/delay.rst b/source/libmaple/api/delay.rst index a0d013a..5d0397d 100644 --- a/source/libmaple/api/delay.rst +++ b/source/libmaple/api/delay.rst @@ -4,9 +4,9 @@ ``delay.h`` =========== -[Stub] support. +Simple busy-loop delaying. -Library Documentation ---------------------- +Functions +--------- -.. doxygenfile:: delay.h +.. doxygenfunction:: delay_us diff --git a/source/libmaple/api/dma.rst b/source/libmaple/api/dma.rst index 1512d0c..2acca41 100644 --- a/source/libmaple/api/dma.rst +++ b/source/libmaple/api/dma.rst @@ -4,9 +4,217 @@ ``dma.h`` ========= -[Stub] support. +Direct Memory Access (DMA) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: dma.h +Types +----- + +.. doxygenstruct:: dma_reg_map +.. doxygenstruct:: dma_dev +.. doxygenstruct:: dma_handler_config +.. doxygenenum:: dma_mode_flags +.. doxygenenum:: dma_xfer_size +.. doxygenenum:: dma_channel +.. doxygenenum:: dma_priority +.. doxygenenum:: dma_irq_cause +.. doxygenstruct:: dma_channel_reg_map + +Devices +------- + +.. doxygenvariable:: DMA1 +.. doxygenvariable:: DMA2 + +Functions +--------- + +.. TODO [0.0.11?] figure out the dma_attach_interrupt weirdness + +.. warning:: There currently appear to be problems with + the dma_attach_interrupt() implementation. + +.. doxygenfunction:: dma_init +.. doxygenfunction:: dma_setup_transfer +.. doxygenfunction:: dma_set_num_transfers +.. doxygenfunction:: dma_set_priority +.. doxygenfunction:: dma_attach_interrupt +.. doxygenfunction:: dma_detach_interrupt +.. doxygenfunction:: dma_get_irq_cause +.. doxygenfunction:: dma_enable +.. doxygenfunction:: dma_disable +.. doxygenfunction:: dma_set_mem_addr +.. doxygenfunction:: dma_set_per_addr +.. doxygenfunction:: dma_channel_regs +.. doxygenfunction:: dma_is_channel_enabled +.. doxygenfunction:: dma_get_isr_bits +.. doxygenfunction:: dma_clear_isr_bits + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: DMA1_BASE +.. doxygendefine:: DMA2_BASE + +Register Bit Definitions +------------------------ + +Interrupt status register +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DMA_ISR_TEIF7_BIT +.. doxygendefine:: DMA_ISR_HTIF7_BIT +.. doxygendefine:: DMA_ISR_TCIF7_BIT +.. doxygendefine:: DMA_ISR_GIF7_BIT +.. doxygendefine:: DMA_ISR_TEIF6_BIT +.. doxygendefine:: DMA_ISR_HTIF6_BIT +.. doxygendefine:: DMA_ISR_TCIF6_BIT +.. doxygendefine:: DMA_ISR_GIF6_BIT +.. doxygendefine:: DMA_ISR_TEIF5_BIT +.. doxygendefine:: DMA_ISR_HTIF5_BIT +.. doxygendefine:: DMA_ISR_TCIF5_BIT +.. doxygendefine:: DMA_ISR_GIF5_BIT +.. doxygendefine:: DMA_ISR_TEIF4_BIT +.. doxygendefine:: DMA_ISR_HTIF4_BIT +.. doxygendefine:: DMA_ISR_TCIF4_BIT +.. doxygendefine:: DMA_ISR_GIF4_BIT +.. doxygendefine:: DMA_ISR_TEIF3_BIT +.. doxygendefine:: DMA_ISR_HTIF3_BIT +.. doxygendefine:: DMA_ISR_TCIF3_BIT +.. doxygendefine:: DMA_ISR_GIF3_BIT +.. doxygendefine:: DMA_ISR_TEIF2_BIT +.. doxygendefine:: DMA_ISR_HTIF2_BIT +.. doxygendefine:: DMA_ISR_TCIF2_BIT +.. doxygendefine:: DMA_ISR_GIF2_BIT +.. doxygendefine:: DMA_ISR_TEIF1_BIT +.. doxygendefine:: DMA_ISR_HTIF1_BIT +.. doxygendefine:: DMA_ISR_TCIF1_BIT +.. doxygendefine:: DMA_ISR_GIF1_BIT + +.. doxygendefine:: DMA_ISR_TEIF7 +.. doxygendefine:: DMA_ISR_HTIF7 +.. doxygendefine:: DMA_ISR_TCIF7 +.. doxygendefine:: DMA_ISR_GIF7 +.. doxygendefine:: DMA_ISR_TEIF6 +.. doxygendefine:: DMA_ISR_HTIF6 +.. doxygendefine:: DMA_ISR_TCIF6 +.. doxygendefine:: DMA_ISR_GIF6 +.. doxygendefine:: DMA_ISR_TEIF5 +.. doxygendefine:: DMA_ISR_HTIF5 +.. doxygendefine:: DMA_ISR_TCIF5 +.. doxygendefine:: DMA_ISR_GIF5 +.. doxygendefine:: DMA_ISR_TEIF4 +.. doxygendefine:: DMA_ISR_HTIF4 +.. doxygendefine:: DMA_ISR_TCIF4 +.. doxygendefine:: DMA_ISR_GIF4 +.. doxygendefine:: DMA_ISR_TEIF3 +.. doxygendefine:: DMA_ISR_HTIF3 +.. doxygendefine:: DMA_ISR_TCIF3 +.. doxygendefine:: DMA_ISR_GIF3 +.. doxygendefine:: DMA_ISR_TEIF2 +.. doxygendefine:: DMA_ISR_HTIF2 +.. doxygendefine:: DMA_ISR_TCIF2 +.. doxygendefine:: DMA_ISR_GIF2 +.. doxygendefine:: DMA_ISR_TEIF1 +.. doxygendefine:: DMA_ISR_HTIF1 +.. doxygendefine:: DMA_ISR_TCIF1 +.. doxygendefine:: DMA_ISR_GIF1 + +Interrupt flag clear register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DMA_IFCR_CTEIF7_BIT +.. doxygendefine:: DMA_IFCR_CHTIF7_BIT +.. doxygendefine:: DMA_IFCR_CTCIF7_BIT +.. doxygendefine:: DMA_IFCR_CGIF7_BIT +.. doxygendefine:: DMA_IFCR_CTEIF6_BIT +.. doxygendefine:: DMA_IFCR_CHTIF6_BIT +.. doxygendefine:: DMA_IFCR_CTCIF6_BIT +.. doxygendefine:: DMA_IFCR_CGIF6_BIT +.. doxygendefine:: DMA_IFCR_CTEIF5_BIT +.. doxygendefine:: DMA_IFCR_CHTIF5_BIT +.. doxygendefine:: DMA_IFCR_CTCIF5_BIT +.. doxygendefine:: DMA_IFCR_CGIF5_BIT +.. doxygendefine:: DMA_IFCR_CTEIF4_BIT +.. doxygendefine:: DMA_IFCR_CHTIF4_BIT +.. doxygendefine:: DMA_IFCR_CTCIF4_BIT +.. doxygendefine:: DMA_IFCR_CGIF4_BIT +.. doxygendefine:: DMA_IFCR_CTEIF3_BIT +.. doxygendefine:: DMA_IFCR_CHTIF3_BIT +.. doxygendefine:: DMA_IFCR_CTCIF3_BIT +.. doxygendefine:: DMA_IFCR_CGIF3_BIT +.. doxygendefine:: DMA_IFCR_CTEIF2_BIT +.. doxygendefine:: DMA_IFCR_CHTIF2_BIT +.. doxygendefine:: DMA_IFCR_CTCIF2_BIT +.. doxygendefine:: DMA_IFCR_CGIF2_BIT +.. doxygendefine:: DMA_IFCR_CTEIF1_BIT +.. doxygendefine:: DMA_IFCR_CHTIF1_BIT +.. doxygendefine:: DMA_IFCR_CTCIF1_BIT +.. doxygendefine:: DMA_IFCR_CGIF1_BIT + +.. doxygendefine:: DMA_IFCR_CTEIF7 +.. doxygendefine:: DMA_IFCR_CHTIF7 +.. doxygendefine:: DMA_IFCR_CTCIF7 +.. doxygendefine:: DMA_IFCR_CGIF7 +.. doxygendefine:: DMA_IFCR_CTEIF6 +.. doxygendefine:: DMA_IFCR_CHTIF6 +.. doxygendefine:: DMA_IFCR_CTCIF6 +.. doxygendefine:: DMA_IFCR_CGIF6 +.. doxygendefine:: DMA_IFCR_CTEIF5 +.. doxygendefine:: DMA_IFCR_CHTIF5 +.. doxygendefine:: DMA_IFCR_CTCIF5 +.. doxygendefine:: DMA_IFCR_CGIF5 +.. doxygendefine:: DMA_IFCR_CTEIF4 +.. doxygendefine:: DMA_IFCR_CHTIF4 +.. doxygendefine:: DMA_IFCR_CTCIF4 +.. doxygendefine:: DMA_IFCR_CGIF4 +.. doxygendefine:: DMA_IFCR_CTEIF3 +.. doxygendefine:: DMA_IFCR_CHTIF3 +.. doxygendefine:: DMA_IFCR_CTCIF3 +.. doxygendefine:: DMA_IFCR_CGIF3 +.. doxygendefine:: DMA_IFCR_CTEIF2 +.. doxygendefine:: DMA_IFCR_CHTIF2 +.. doxygendefine:: DMA_IFCR_CTCIF2 +.. doxygendefine:: DMA_IFCR_CGIF2 +.. doxygendefine:: DMA_IFCR_CTEIF1 +.. doxygendefine:: DMA_IFCR_CHTIF1 +.. doxygendefine:: DMA_IFCR_CTCIF1 +.. doxygendefine:: DMA_IFCR_CGIF1 + +Channel configuration register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: DMA_CCR_MEM2MEM_BIT +.. doxygendefine:: DMA_CCR_MINC_BIT +.. doxygendefine:: DMA_CCR_PINC_BIT +.. doxygendefine:: DMA_CCR_CIRC_BIT +.. doxygendefine:: DMA_CCR_DIR_BIT +.. doxygendefine:: DMA_CCR_TEIE_BIT +.. doxygendefine:: DMA_CCR_HTIE_BIT +.. doxygendefine:: DMA_CCR_TCIE_BIT +.. doxygendefine:: DMA_CCR_EN_BIT + +.. doxygendefine:: DMA_CCR_MEM2MEM +.. doxygendefine:: DMA_CCR_PL +.. doxygendefine:: DMA_CCR_PL_LOW +.. doxygendefine:: DMA_CCR_PL_MEDIUM +.. doxygendefine:: DMA_CCR_PL_HIGH +.. doxygendefine:: DMA_CCR_PL_VERY_HIGH +.. doxygendefine:: DMA_CCR_MSIZE +.. doxygendefine:: DMA_CCR_MSIZE_8BITS +.. doxygendefine:: DMA_CCR_MSIZE_16BITS +.. doxygendefine:: DMA_CCR_MSIZE_32BITS +.. doxygendefine:: DMA_CCR_PSIZE +.. doxygendefine:: DMA_CCR_PSIZE_8BITS +.. doxygendefine:: DMA_CCR_PSIZE_16BITS +.. doxygendefine:: DMA_CCR_PSIZE_32BITS +.. doxygendefine:: DMA_CCR_MINC +.. doxygendefine:: DMA_CCR_PINC +.. doxygendefine:: DMA_CCR_CIRC +.. doxygendefine:: DMA_CCR_DIR +.. doxygendefine:: DMA_CCR_TEIE +.. doxygendefine:: DMA_CCR_HTIE +.. doxygendefine:: DMA_CCR_TCIE +.. doxygendefine:: DMA_CCR_EN diff --git a/source/libmaple/api/exti.rst b/source/libmaple/api/exti.rst index 2909aa7..1038fbf 100644 --- a/source/libmaple/api/exti.rst +++ b/source/libmaple/api/exti.rst @@ -4,9 +4,34 @@ ``exti.h`` ========== -[Stub] support. +:ref:`External interrupt <external-interrupts>` support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: exti.h +Types +----- + +.. doxygenstruct:: exti_reg_map +.. doxygenenum:: exti_trigger_mode + +Devices +------- + +None at this time. + +Functions +--------- + +.. doxygenfunction:: exti_attach_interrupt +.. doxygenfunction:: exti_detach_interrupt + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: EXTI_BASE + +Register Bit Definitions +------------------------ + +None at this time. diff --git a/source/libmaple/api/flash.rst b/source/libmaple/api/flash.rst index 6f2f9d3..8a7e79b 100644 --- a/source/libmaple/api/flash.rst +++ b/source/libmaple/api/flash.rst @@ -4,9 +4,94 @@ ``flash.h`` =========== -[Stub] support. +Flash support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: flash.h +Types +----- + +.. doxygenstruct:: flash_reg_map + +Functions +--------- + +.. doxygenfunction:: flash_enable_prefetch +.. doxygenfunction:: flash_set_latency + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: FLASH_BASE + +Register Bit Definitions +------------------------ + +Access control register +~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FLASH_ACR_PRFTBS_BIT +.. doxygendefine:: FLASH_ACR_PRFTBE_BIT +.. doxygendefine:: FLASH_ACR_HLFCYA_BIT + +.. doxygendefine:: FLASH_ACR_PRFTBS +.. doxygendefine:: FLASH_ACR_PRFTBE +.. doxygendefine:: FLASH_ACR_HLFCYA +.. doxygendefine:: FLASH_ACR_LATENCY + +Status register +~~~~~~~~~~~~~~~ + +.. doxygendefine:: FLASH_SR_EOP_BIT +.. doxygendefine:: FLASH_SR_WRPRTERR_BIT +.. doxygendefine:: FLASH_SR_PGERR_BIT +.. doxygendefine:: FLASH_SR_BSY_BIT + +.. doxygendefine:: FLASH_SR_EOP +.. doxygendefine:: FLASH_SR_WRPRTERR +.. doxygendefine:: FLASH_SR_PGERR +.. doxygendefine:: FLASH_SR_BSY + +Control register +~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FLASH_CR_EOPIE_BIT +.. doxygendefine:: FLASH_CR_ERRIE_BIT +.. doxygendefine:: FLASH_CR_OPTWRE_BIT +.. doxygendefine:: FLASH_CR_LOCK_BIT +.. doxygendefine:: FLASH_CR_STRT_BIT +.. doxygendefine:: FLASH_CR_OPTER_BIT +.. doxygendefine:: FLASH_CR_OPTPG_BIT +.. doxygendefine:: FLASH_CR_MER_BIT +.. doxygendefine:: FLASH_CR_PER_BIT +.. doxygendefine:: FLASH_CR_PG_BIT + +.. doxygendefine:: FLASH_CR_EOPIE +.. doxygendefine:: FLASH_CR_ERRIE +.. doxygendefine:: FLASH_CR_OPTWRE +.. doxygendefine:: FLASH_CR_LOCK +.. doxygendefine:: FLASH_CR_STRT +.. doxygendefine:: FLASH_CR_OPTER +.. doxygendefine:: FLASH_CR_OPTPG +.. doxygendefine:: FLASH_CR_MER +.. doxygendefine:: FLASH_CR_PER +.. doxygendefine:: FLASH_CR_PG + +Option byte register +~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FLASH_OBR_nRST_STDBY_BIT +.. doxygendefine:: FLASH_OBR_nRST_STOP_BIT +.. doxygendefine:: FLASH_OBR_WDG_SW_BIT +.. doxygendefine:: FLASH_OBR_RDPRT_BIT +.. doxygendefine:: FLASH_OBR_OPTERR_BIT + +.. doxygendefine:: FLASH_OBR_DATA1 +.. doxygendefine:: FLASH_OBR_DATA0 +.. doxygendefine:: FLASH_OBR_USER +.. doxygendefine:: FLASH_OBR_nRST_STDBY +.. doxygendefine:: FLASH_OBR_nRST_STOP +.. doxygendefine:: FLASH_OBR_WDG_SW +.. doxygendefine:: FLASH_OBR_RDPRT +.. doxygendefine:: FLASH_OBR_OPTERR diff --git a/source/libmaple/api/fsmc.rst b/source/libmaple/api/fsmc.rst index cecfc99..3b356cc 100644 --- a/source/libmaple/api/fsmc.rst +++ b/source/libmaple/api/fsmc.rst @@ -4,9 +4,186 @@ ``fsmc.h`` ========== -[Stub] support. +Flexible Static Memory Controller (FSMC) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: fsmc.h +Types +----- + +.. doxygenstruct:: fsmc_reg_map +.. doxygenstruct:: fsmc_nor_psram_reg_map + +Devices +------- + +None at this time. + +Functions +--------- + +.. doxygenfunction:: fsmc_sram_init_gpios +.. doxygenfunction:: fsmc_nor_psram_set_datast +.. doxygenfunction:: fsmc_nor_psram_set_addset + +Memory Bank Boundary Addresses +------------------------------ + +.. doxygendefine:: FSMC_BANK1 +.. doxygendefine:: FSMC_BANK2 +.. doxygendefine:: FSMC_BANK3 +.. doxygendefine:: FSMC_BANK4 + +.. doxygendefine:: FSMC_NOR_PSRAM_REGION1 +.. doxygendefine:: FSMC_NOR_PSRAM_REGION2 +.. doxygendefine:: FSMC_NOR_PSRAM_REGION3 +.. doxygendefine:: FSMC_NOR_PSRAM_REGION4 + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: FSMC_BASE + +.. doxygendefine:: FSMC_NOR_PSRAM1_BASE +.. doxygendefine:: FSMC_NOR_PSRAM2_BASE +.. doxygendefine:: FSMC_NOR_PSRAM3_BASE +.. doxygendefine:: FSMC_NOR_PSRAM4_BASE + +Register Bit Definitions +------------------------ + +NOR/PSRAM Chip-Select Control Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_BCR_CBURSTRW_BIT +.. doxygendefine:: FSMC_BCR_ASYNCWAIT_BIT +.. doxygendefine:: FSMC_BCR_EXTMOD_BIT +.. doxygendefine:: FSMC_BCR_WAITEN_BIT +.. doxygendefine:: FSMC_BCR_WREN_BIT +.. doxygendefine:: FSMC_BCR_WAITCFG_BIT +.. doxygendefine:: FSMC_BCR_WRAPMOD_BIT +.. doxygendefine:: FSMC_BCR_WAITPOL_BIT +.. doxygendefine:: FSMC_BCR_BURSTEN_BIT +.. doxygendefine:: FSMC_BCR_FACCEN_BIT +.. doxygendefine:: FSMC_BCR_MUXEN_BIT +.. doxygendefine:: FSMC_BCR_MBKEN_BIT + +.. doxygendefine:: FSMC_BCR_CBURSTRW +.. doxygendefine:: FSMC_BCR_ASYNCWAIT +.. doxygendefine:: FSMC_BCR_EXTMOD +.. doxygendefine:: FSMC_BCR_WAITEN +.. doxygendefine:: FSMC_BCR_WREN +.. doxygendefine:: FSMC_BCR_WAITCFG +.. doxygendefine:: FSMC_BCR_WRAPMOD +.. doxygendefine:: FSMC_BCR_WAITPOL +.. doxygendefine:: FSMC_BCR_BURSTEN +.. doxygendefine:: FSMC_BCR_FACCEN +.. doxygendefine:: FSMC_BCR_MWID +.. doxygendefine:: FSMC_BCR_MWID_8BITS +.. doxygendefine:: FSMC_BCR_MWID_16BITS +.. doxygendefine:: FSMC_BCR_MTYP +.. doxygendefine:: FSMC_BCR_MTYP_SRAM +.. doxygendefine:: FSMC_BCR_MTYP_PSRAM +.. doxygendefine:: FSMC_BCR_MTYP_NOR_FLASH +.. doxygendefine:: FSMC_BCR_MUXEN +.. doxygendefine:: FSMC_BCR_MBKEN + +SRAM/NOR-Flash Chip-Select Timing Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_BTR_ACCMOD +.. doxygendefine:: FSMC_BTR_ACCMOD_A +.. doxygendefine:: FSMC_BTR_ACCMOD_B +.. doxygendefine:: FSMC_BTR_ACCMOD_C +.. doxygendefine:: FSMC_BTR_ACCMOD_D +.. doxygendefine:: FSMC_BTR_DATLAT +.. doxygendefine:: FSMC_BTR_CLKDIV +.. doxygendefine:: FSMC_BTR_BUSTURN +.. doxygendefine:: FSMC_BTR_DATAST +.. doxygendefine:: FSMC_BTR_ADDHLD +.. doxygendefine:: FSMC_BTR_ADDSET + +SRAM/NOR-Flash Write Timing Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_BWTR_ACCMOD +.. doxygendefine:: FSMC_BWTR_ACCMOD_A +.. doxygendefine:: FSMC_BWTR_ACCMOD_B +.. doxygendefine:: FSMC_BWTR_ACCMOD_C +.. doxygendefine:: FSMC_BWTR_ACCMOD_D +.. doxygendefine:: FSMC_BWTR_DATLAT +.. doxygendefine:: FSMC_BWTR_CLKDIV +.. doxygendefine:: FSMC_BWTR_DATAST +.. doxygendefine:: FSMC_BWTR_ADDHLD +.. doxygendefine:: FSMC_BWTR_ADDSET + +NAND Flash/PC Card Controller Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_PCR_ECCEN_BIT +.. doxygendefine:: FSMC_PCR_PTYP_BIT +.. doxygendefine:: FSMC_PCR_PBKEN_BIT +.. doxygendefine:: FSMC_PCR_PWAITEN_BIT + +.. doxygendefine:: FSMC_PCR_ECCPS +.. doxygendefine:: FSMC_PCR_ECCPS_256B +.. doxygendefine:: FSMC_PCR_ECCPS_512B +.. doxygendefine:: FSMC_PCR_ECCPS_1024B +.. doxygendefine:: FSMC_PCR_ECCPS_2048B +.. doxygendefine:: FSMC_PCR_ECCPS_4096B +.. doxygendefine:: FSMC_PCR_ECCPS_8192B +.. doxygendefine:: FSMC_PCR_TAR +.. doxygendefine:: FSMC_PCR_TCLR +.. doxygendefine:: FSMC_PCR_ECCEN +.. doxygendefine:: FSMC_PCR_PWID +.. doxygendefine:: FSMC_PCR_PWID_8BITS +.. doxygendefine:: FSMC_PCR_PWID_16BITS +.. doxygendefine:: FSMC_PCR_PTYP +.. doxygendefine:: FSMC_PCR_PTYP_PC_CF_PCMCIA +.. doxygendefine:: FSMC_PCR_PTYP_NAND +.. doxygendefine:: FSMC_PCR_PBKEN +.. doxygendefine:: FSMC_PCR_PWAITEN + +FIFO Status And Interrupt Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_SR_FEMPT_BIT +.. doxygendefine:: FSMC_SR_IFEN_BIT +.. doxygendefine:: FSMC_SR_ILEN_BIT +.. doxygendefine:: FSMC_SR_IREN_BIT +.. doxygendefine:: FSMC_SR_IFS_BIT +.. doxygendefine:: FSMC_SR_ILS_BIT +.. doxygendefine:: FSMC_SR_IRS_BIT + +.. doxygendefine:: FSMC_SR_FEMPT +.. doxygendefine:: FSMC_SR_IFEN +.. doxygendefine:: FSMC_SR_ILEN +.. doxygendefine:: FSMC_SR_IREN +.. doxygendefine:: FSMC_SR_IFS +.. doxygendefine:: FSMC_SR_ILS +.. doxygendefine:: FSMC_SR_IRS + +Common Memory Space Timing Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_PMEM_MEMHIZ +.. doxygendefine:: FSMC_PMEM_MEMHOLD +.. doxygendefine:: FSMC_PMEM_MEMWAIT +.. doxygendefine:: FSMC_PMEM_MEMSET + +Attribute Memory Space Timing Registers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_PATT_ATTHIZ +.. doxygendefine:: FSMC_PATT_ATTHOLD +.. doxygendefine:: FSMC_PATT_ATTWAIT +.. doxygendefine:: FSMC_PATT_ATTSET + +I/O Space Timing Register 4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: FSMC_PIO_IOHIZ +.. doxygendefine:: FSMC_PIO_IOHOLD +.. doxygendefine:: FSMC_PIO_IOWAIT +.. doxygendefine:: FSMC_PIO_IOSET diff --git a/source/libmaple/api/gpio.rst b/source/libmaple/api/gpio.rst index 2cfec23..96058c0 100644 --- a/source/libmaple/api/gpio.rst +++ b/source/libmaple/api/gpio.rst @@ -4,9 +4,238 @@ ``gpio.h`` ========== -[Stub] support. +General Purpose Input/Output (GPIO) port and Alternate Function +Input/Output (AFIO) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: gpio.h +Types +----- + +.. doxygenstruct:: gpio_reg_map +.. doxygenstruct:: gpio_dev +.. doxygenenum:: gpio_pin_mode + +.. doxygenstruct:: afio_reg_map +.. doxygenenum:: afio_exti_port +.. doxygenenum:: afio_exti_num +.. doxygenenum:: afio_remap_peripheral +.. doxygenenum:: afio_debug_cfg + +Devices +------- + +.. doxygenvariable:: GPIOA +.. doxygenvariable:: GPIOB +.. doxygenvariable:: GPIOC +.. doxygenvariable:: GPIOD +.. doxygenvariable:: GPIOE +.. doxygenvariable:: GPIOF +.. doxygenvariable:: GPIOG + +Functions +--------- + +.. doxygenfunction:: gpio_init +.. doxygenfunction:: gpio_init_all +.. doxygenfunction:: gpio_set_mode +.. doxygenfunction:: gpio_exti_port +.. doxygenfunction:: gpio_write_bit +.. doxygenfunction:: gpio_read_bit +.. doxygenfunction:: gpio_toggle_bit + +.. doxygenfunction:: afio_init +.. doxygenfunction:: afio_exti_select +.. doxygenfunction:: afio_remap +.. doxygenfunction:: afio_cfg_debug_ports + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: GPIOA_BASE +.. doxygendefine:: GPIOB_BASE +.. doxygendefine:: GPIOC_BASE +.. doxygendefine:: GPIOD_BASE +.. doxygendefine:: GPIOE_BASE +.. doxygendefine:: GPIOF_BASE +.. doxygendefine:: GPIOG_BASE + +.. doxygendefine:: AFIO_BASE + +Register Bit Definitions +------------------------ + +GPIO Control Registers +~~~~~~~~~~~~~~~~~~~~~~ + +These values apply to both the low and high configuration registers +(ST RM0008: GPIOx_CRL and GPIOx_CRH). You can shift them right by the +appropriate number of bits for the GPIO port bit you're interested in +to obtain a bit mask. + +For example, to mask out just the value of GPIOA_CRH_CNF12, note that +GPIO port bit 12's configuration starts at bit 18 in the corresponding +CRH. Thus, an appropriate mask is ``GPIOA_BASE->CRH & (GPIO_CR_CNF << +18)``. + +.. doxygendefine:: GPIO_CR_CNF_INPUT_ANALOG +.. doxygendefine:: GPIO_CR_CNF_INPUT_FLOATING +.. doxygendefine:: GPIO_CR_CNF_INPUT_PU_PD +.. doxygendefine:: GPIO_CR_CNF_OUTPUT_PP +.. doxygendefine:: GPIO_CR_CNF_OUTPUT_OD +.. doxygendefine:: GPIO_CR_CNF_AF_OUTPUT_PP +.. doxygendefine:: GPIO_CR_CNF_AF_OUTPUT_OD +.. doxygendefine:: GPIO_CR_MODE_INPUT +.. doxygendefine:: GPIO_CR_MODE_OUTPUT_10MHZ +.. doxygendefine:: GPIO_CR_MODE_OUTPUT_2MHZ +.. doxygendefine:: GPIO_CR_MODE_OUTPUT_50MHZ + +Event Control Register +~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: AFIO_EVCR_EVOE +.. doxygendefine:: AFIO_EVCR_PORT_PA +.. doxygendefine:: AFIO_EVCR_PORT_PB +.. doxygendefine:: AFIO_EVCR_PORT_PC +.. doxygendefine:: AFIO_EVCR_PORT_PD +.. doxygendefine:: AFIO_EVCR_PORT_PE +.. doxygendefine:: AFIO_EVCR_PIN_0 +.. doxygendefine:: AFIO_EVCR_PIN_1 +.. doxygendefine:: AFIO_EVCR_PIN_2 +.. doxygendefine:: AFIO_EVCR_PIN_3 +.. doxygendefine:: AFIO_EVCR_PIN_4 +.. doxygendefine:: AFIO_EVCR_PIN_5 +.. doxygendefine:: AFIO_EVCR_PIN_6 +.. doxygendefine:: AFIO_EVCR_PIN_7 +.. doxygendefine:: AFIO_EVCR_PIN_8 +.. doxygendefine:: AFIO_EVCR_PIN_9 +.. doxygendefine:: AFIO_EVCR_PIN_10 +.. doxygendefine:: AFIO_EVCR_PIN_11 +.. doxygendefine:: AFIO_EVCR_PIN_12 +.. doxygendefine:: AFIO_EVCR_PIN_13 +.. doxygendefine:: AFIO_EVCR_PIN_14 +.. doxygendefine:: AFIO_EVCR_PIN_15 + +AF Remap and Debug I/O Configuration Register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: AFIO_MAPR_SWJ_CFG +.. doxygendefine:: AFIO_MAPR_SWJ_CFG_FULL_SWJ +.. doxygendefine:: AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST +.. doxygendefine:: AFIO_MAPR_SWJ_CFG_NO_JTAG_SW +.. doxygendefine:: AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW +.. doxygendefine:: AFIO_MAPR_ADC2_ETRGREG_REMAP +.. doxygendefine:: AFIO_MAPR_ADC2_ETRGINJ_REMAP +.. doxygendefine:: AFIO_MAPR_ADC1_ETRGREG_REMAP +.. doxygendefine:: AFIO_MAPR_ADC1_ETRGINJ_REMAP +.. doxygendefine:: AFIO_MAPR_TIM5CH4_IREMAP +.. doxygendefine:: AFIO_MAPR_PD01_REMAP +.. doxygendefine:: AFIO_MAPR_CAN_REMAP +.. doxygendefine:: AFIO_MAPR_CAN_REMAP_NONE +.. doxygendefine:: AFIO_MAPR_CAN_REMAP_PB8_PB9 +.. doxygendefine:: AFIO_MAPR_CAN_REMAP_PD0_PD1 +.. doxygendefine:: AFIO_MAPR_TIM4_REMAP +.. doxygendefine:: AFIO_MAPR_TIM3_REMAP +.. doxygendefine:: AFIO_MAPR_TIM3_REMAP_NONE +.. doxygendefine:: AFIO_MAPR_TIM3_REMAP_PARTIAL +.. doxygendefine:: AFIO_MAPR_TIM3_REMAP_FULL +.. doxygendefine:: AFIO_MAPR_TIM2_REMAP +.. doxygendefine:: AFIO_MAPR_TIM2_REMAP_NONE +.. doxygendefine:: AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 +.. doxygendefine:: AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 +.. doxygendefine:: AFIO_MAPR_TIM2_REMAP_FULL +.. doxygendefine:: AFIO_MAPR_TIM1_REMAP +.. doxygendefine:: AFIO_MAPR_TIM1_REMAP_NONE +.. doxygendefine:: AFIO_MAPR_TIM1_REMAP_PARTIAL +.. doxygendefine:: AFIO_MAPR_TIM1_REMAP_FULL +.. doxygendefine:: AFIO_MAPR_USART3_REMAP +.. doxygendefine:: AFIO_MAPR_USART3_REMAP_NONE +.. doxygendefine:: AFIO_MAPR_USART3_REMAP_PARTIAL +.. doxygendefine:: AFIO_MAPR_USART3_REMAP_FULL +.. doxygendefine:: AFIO_MAPR_USART2_REMAP +.. doxygendefine:: AFIO_MAPR_USART1_REMAP +.. doxygendefine:: AFIO_MAPR_I2C1_REMAP +.. doxygendefine:: AFIO_MAPR_SPI1_REMAP + +External Interrupt Configuration Register 1 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: AFIO_EXTICR1_EXTI3 +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PA +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PB +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PC +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PD +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PE +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PF +.. doxygendefine:: AFIO_EXTICR1_EXTI3_PG +.. doxygendefine:: AFIO_EXTICR1_EXTI2 +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PA +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PB +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PC +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PD +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PE +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PF +.. doxygendefine:: AFIO_EXTICR1_EXTI2_PG +.. doxygendefine:: AFIO_EXTICR1_EXTI1 +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PA +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PB +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PC +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PD +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PE +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PF +.. doxygendefine:: AFIO_EXTICR1_EXTI1_PG +.. doxygendefine:: AFIO_EXTICR1_EXTI0 +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PA +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PB +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PC +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PD +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PE +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PF +.. doxygendefine:: AFIO_EXTICR1_EXTI0_PG + +External Interrupt Configuration Register 2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: AFIO_EXTICR2_EXTI7 +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PA +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PB +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PC +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PD +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PE +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PF +.. doxygendefine:: AFIO_EXTICR2_EXTI7_PG +.. doxygendefine:: AFIO_EXTICR2_EXTI6 +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PA +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PB +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PC +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PD +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PE +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PF +.. doxygendefine:: AFIO_EXTICR2_EXTI6_PG +.. doxygendefine:: AFIO_EXTICR2_EXTI5 +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PA +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PB +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PC +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PD +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PE +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PF +.. doxygendefine:: AFIO_EXTICR2_EXTI5_PG +.. doxygendefine:: AFIO_EXTICR2_EXTI4 +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PA +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PB +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PC +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PD +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PE +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PF +.. doxygendefine:: AFIO_EXTICR2_EXTI4_PG + +AF Remap and Debug I/O Configuration Register 2 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: AFIO_MAPR2_FSMC_NADV +.. doxygendefine:: AFIO_MAPR2_TIM14_REMAP +.. doxygendefine:: AFIO_MAPR2_TIM13_REMAP +.. doxygendefine:: AFIO_MAPR2_TIM11_REMAP +.. doxygendefine:: AFIO_MAPR2_TIM10_REMAP +.. doxygendefine:: AFIO_MAPR2_TIM9_REMAP diff --git a/source/libmaple/api/i2c.rst b/source/libmaple/api/i2c.rst index 14dd304..ff380cc 100644 --- a/source/libmaple/api/i2c.rst +++ b/source/libmaple/api/i2c.rst @@ -4,9 +4,121 @@ ``i2c.h`` ========= -[Stub] support. +Inter-Integrated Circuit (|i2c|) peripheral support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: i2c.h +Important Note +-------------- + +There are some important known problems with the built-in I2C +peripherals. For more information, see STM32F10xx8 and STM32F10xxB +Errata sheet (ST Doc ID 14574 Rev 8), Section 2.11.1, 2.11.2. An +important consequence of these problems is that the |i2c| interrupt +must not be preempted. Consequently, (by default) Wirish uses an +|i2c| interrupt priority which is the highest in the system (priority +level 0). Other interrupt priorities are set lower. + +Types +----- + +.. doxygenstruct:: i2c_reg_map +.. doxygenenum:: i2c_state +.. doxygenstruct:: i2c_msg +.. doxygenstruct:: i2c_dev + +Devices +------- + +.. doxygenvariable:: I2C1 +.. doxygenvariable:: I2C2 + +Functions +--------- + +.. doxygenfunction:: i2c_init +.. doxygenfunction:: i2c_master_enable +.. doxygenfunction:: i2c_master_xfer +.. doxygenfunction:: i2c_bus_reset +.. doxygenfunction:: i2c_disable +.. doxygenfunction:: i2c_peripheral_enable +.. doxygenfunction:: i2c_peripheral_disable +.. doxygenfunction:: i2c_write +.. doxygenfunction:: i2c_set_input_clk +.. doxygenfunction:: i2c_set_clk_control +.. doxygenfunction:: i2c_set_trise +.. doxygenfunction:: i2c_start_condition +.. doxygenfunction:: i2c_stop_condition +.. doxygenfunction:: i2c_enable_irq +.. doxygenfunction:: i2c_disable_irq +.. doxygenfunction:: i2c_enable_ack +.. doxygenfunction:: i2c_disable_ack + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: I2C1_BASE +.. doxygendefine:: I2C2_BASE + +Register Bit Definitions +------------------------ + +Control register 1 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: I2C_CR1_SWRST +.. doxygendefine:: I2C_CR1_ALERT +.. doxygendefine:: I2C_CR1_PEC +.. doxygendefine:: I2C_CR1_POS +.. doxygendefine:: I2C_CR1_ACK +.. doxygendefine:: I2C_CR1_START +.. doxygendefine:: I2C_CR1_STOP +.. doxygendefine:: I2C_CR1_PE + +Control register 2 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: I2C_CR2_LAST +.. doxygendefine:: I2C_CR2_DMAEN +.. doxygendefine:: I2C_CR2_ITBUFEN +.. doxygendefine:: I2C_CR2_ITEVTEN +.. doxygendefine:: I2C_CR2_ITERREN +.. doxygendefine:: I2C_CR2_FREQ + +Clock control register +~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: I2C_CCR_FS +.. doxygendefine:: I2C_CCR_DUTY +.. doxygendefine:: I2C_CCR_CCR + +Status register 1 +~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: I2C_SR1_SB +.. doxygendefine:: I2C_SR1_ADDR +.. doxygendefine:: I2C_SR1_BTF +.. doxygendefine:: I2C_SR1_ADD10 +.. doxygendefine:: I2C_SR1_STOPF +.. doxygendefine:: I2C_SR1_RXNE +.. doxygendefine:: I2C_SR1_TXE +.. doxygendefine:: I2C_SR1_BERR +.. doxygendefine:: I2C_SR1_ARLO +.. doxygendefine:: I2C_SR1_AF +.. doxygendefine:: I2C_SR1_OVR +.. doxygendefine:: I2C_SR1_PECERR +.. doxygendefine:: I2C_SR1_TIMEOUT +.. doxygendefine:: I2C_SR1_SMBALERT + +Status register 2 +~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: I2C_SR2_MSL +.. doxygendefine:: I2C_SR2_BUSY +.. doxygendefine:: I2C_SR2_TRA +.. doxygendefine:: I2C_SR2_GENCALL +.. doxygendefine:: I2C_SR2_SMBDEFAULT +.. doxygendefine:: I2C_SR2_SMBHOST +.. doxygendefine:: I2C_SR2_DUALF +.. doxygendefine:: I2C_SR2_PEC diff --git a/source/libmaple/api/iwdg.rst b/source/libmaple/api/iwdg.rst index 3911ece..06691f8 100644 --- a/source/libmaple/api/iwdg.rst +++ b/source/libmaple/api/iwdg.rst @@ -4,9 +4,70 @@ ``iwdg.h`` ========== -[Stub] support. +Independent Watchdog (IWDG) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: iwdg.h +Usage Note +---------- + +To use the independent watchdog, first call :c:func:`iwdg_init()` with +the appropriate prescaler and IWDG counter reload values for your +application. Afterwards, you must periodically call +:c:func:`iwdg_feed()` before the IWDG counter reaches 0 to reset the +counter to its reload value. If you do not, the chip will reset. + +Once started, the independent watchdog cannot be turned off. + +Types +----- + +.. doxygenstruct:: iwdg_reg_map +.. doxygenenum:: iwdg_prescaler + +Devices +------- + +None at this time. + +Functions +--------- + +.. doxygenfunction:: iwdg_init +.. doxygenfunction:: iwdg_feed + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: IWDG_BASE + +Register Bit Definitions +------------------------ + +Key register +~~~~~~~~~~~~ + +.. doxygendefine:: IWDG_KR_UNLOCK +.. doxygendefine:: IWDG_KR_FEED +.. doxygendefine:: IWDG_KR_START + +Prescaler register +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: IWDG_PR_DIV_4 +.. doxygendefine:: IWDG_PR_DIV_8 +.. doxygendefine:: IWDG_PR_DIV_16 +.. doxygendefine:: IWDG_PR_DIV_32 +.. doxygendefine:: IWDG_PR_DIV_64 +.. doxygendefine:: IWDG_PR_DIV_128 +.. doxygendefine:: IWDG_PR_DIV_256 + +Status register +~~~~~~~~~~~~~~~ + +.. doxygendefine:: IWDG_SR_RVU_BIT +.. doxygendefine:: IWDG_SR_PVU_BIT + +.. doxygendefine:: IWDG_SR_RVU +.. doxygendefine:: IWDG_SR_PVU diff --git a/source/libmaple/api/libmaple.rst b/source/libmaple/api/libmaple.rst index d4f28f0..c230cef 100644 --- a/source/libmaple/api/libmaple.rst +++ b/source/libmaple/api/libmaple.rst @@ -4,9 +4,8 @@ ``libmaple.h`` ============== -[Stub] support. +Base include file for libmaple. -Library Documentation ---------------------- - -.. doxygenfile:: libmaple.h +This file includes :ref:`libmaple-libmaple_types`, +:ref:`libmaple-stm32`, and :ref:`libmaple-util`. You shouldn't rely +on it doing anything else, however. diff --git a/source/libmaple/api/libmaple_types.rst b/source/libmaple/api/libmaple_types.rst index bbea2c1..7fed5dc 100644 --- a/source/libmaple/api/libmaple_types.rst +++ b/source/libmaple/api/libmaple_types.rst @@ -4,9 +4,40 @@ ``libmaple_types.h`` ==================== -[Stub] support. +Defines the base types and type-related macros used throughout the +rest of libmaple. -Library Documentation ---------------------- +Integral Types +-------------- -.. doxygenfile:: libmaple_types.h +.. doxygentypedef:: uint8 +.. doxygentypedef:: uint16 +.. doxygentypedef:: uint32 +.. doxygentypedef:: uint64 +.. doxygentypedef:: int8 +.. doxygentypedef:: int16 +.. doxygentypedef:: int32 +.. doxygentypedef:: int64 + +Attributes and Type Qualifiers +------------------------------ + +.. c:macro:: __io + + This is a macro for ``volatile`` which is used to denote that the + variable whose type is being qualified is IO-mapped. Its most + common use is in the individual members of each :ref:`register map + <libmaple-overview-regmaps>` struct. + +.. c:macro:: __attr_flash + + This is a macro for a GCC ``__attribute__`` which (when using the + linker scripts provided with libmaple) will cause the variable + being marked to be stored in Flash, rather than SRAM. The + variable's value may be read like that of any other variable, but + it may not be written. + +Other typedefs +-------------- + +.. doxygentypedef:: voidFuncPtr diff --git a/source/libmaple/api/nvic.rst b/source/libmaple/api/nvic.rst index b94dc31..11342d2 100644 --- a/source/libmaple/api/nvic.rst +++ b/source/libmaple/api/nvic.rst @@ -4,9 +4,40 @@ ``nvic.h`` ========== -[Stub] support. +Nested Vector Interrupt Controller (NVIC) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: nvic.h +Types +----- + +.. doxygenstruct:: nvic_reg_map +.. doxygenenum:: nvic_irq_num + +Devices +------- + +None at this time. + +Functions +--------- + +.. doxygenfunction:: nvic_init +.. doxygenfunction:: nvic_set_vector_table +.. doxygenfunction:: nvic_irq_set_priority +.. doxygenfunction:: nvic_globalirq_enable +.. doxygenfunction:: nvic_globalirq_disable +.. doxygenfunction:: nvic_irq_enable +.. doxygenfunction:: nvic_irq_disable +.. doxygenfunction:: nvic_irq_disable_all + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: NVIC_BASE + +Register Bit Definitions +------------------------ + +None at this time. diff --git a/source/libmaple/api/pwr.rst b/source/libmaple/api/pwr.rst index 82e4864..6a2cf22 100644 --- a/source/libmaple/api/pwr.rst +++ b/source/libmaple/api/pwr.rst @@ -4,9 +4,48 @@ ``pwr.h`` ========= -[Stub] support. +Power control (PWR) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: pwr.h +Types +----- + +.. doxygenstruct:: pwr_reg_map + +Devices +------- + +None. + +Functions +--------- + +.. doxygenfunction:: pwr_init + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: PWR_BASE + +Register Bit Definitions +------------------------ + +Control register +~~~~~~~~~~~~~~~~ + +.. doxygendefine:: PWR_CR_DBP +.. doxygendefine:: PWR_CR_PVDE +.. doxygendefine:: PWR_CR_CSBF +.. doxygendefine:: PWR_CR_CWUF +.. doxygendefine:: PWR_CR_PDDS +.. doxygendefine:: PWR_CR_LPDS + +Control and status register +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: PWR_CSR_EWUP +.. doxygendefine:: PWR_CSR_PVDO +.. doxygendefine:: PWR_CSR_SBF +.. doxygendefine:: PWR_CSR_WUF diff --git a/source/libmaple/api/rcc.rst b/source/libmaple/api/rcc.rst index 81dc604..4b96c00 100644 --- a/source/libmaple/api/rcc.rst +++ b/source/libmaple/api/rcc.rst @@ -4,9 +4,374 @@ ``rcc.h`` ========= -[Stub] support. +Reset and Clock Control (RCC) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: rcc.h +Types +----- + +.. doxygenstruct:: rcc_reg_map +.. doxygenenum:: rcc_sysclk_src +.. doxygenenum:: rcc_pllsrc +.. doxygenenum:: rcc_pll_multiplier +.. doxygenenum:: rcc_clk_id +.. doxygenenum:: rcc_clk_domain +.. doxygenenum:: rcc_prescaler +.. doxygenenum:: rcc_adc_divider +.. doxygenenum:: rcc_apb1_divider +.. doxygenenum:: rcc_apb2_divider +.. doxygenenum:: rcc_ahb_divider + +Devices +------- + +None. + +Functions +--------- + +.. doxygenfunction:: rcc_clk_init +.. doxygenfunction:: rcc_clk_enable +.. doxygenfunction:: rcc_reset_dev +.. doxygenfunction:: rcc_dev_clk +.. doxygenfunction:: rcc_set_prescaler + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: RCC_BASE + +Register Bit Definitions +------------------------ + +Clock control register +~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_CR_PLLRDY_BIT +.. doxygendefine:: RCC_CR_PLLON_BIT +.. doxygendefine:: RCC_CR_CSSON_BIT +.. doxygendefine:: RCC_CR_HSEBYP_BIT +.. doxygendefine:: RCC_CR_HSERDY_BIT +.. doxygendefine:: RCC_CR_HSEON_BIT +.. doxygendefine:: RCC_CR_HSIRDY_BIT +.. doxygendefine:: RCC_CR_HSION_BIT + +.. doxygendefine:: RCC_CR_PLLRDY +.. doxygendefine:: RCC_CR_PLLON +.. doxygendefine:: RCC_CR_CSSON +.. doxygendefine:: RCC_CR_HSEBYP +.. doxygendefine:: RCC_CR_HSERDY +.. doxygendefine:: RCC_CR_HSEON +.. doxygendefine:: RCC_CR_HSICAL +.. doxygendefine:: RCC_CR_HSITRIM +.. doxygendefine:: RCC_CR_HSIRDY +.. doxygendefine:: RCC_CR_HSION + +Clock configuration register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_CFGR_USBPRE_BIT +.. doxygendefine:: RCC_CFGR_PLLXTPRE_BIT +.. doxygendefine:: RCC_CFGR_PLLSRC_BIT + +.. doxygendefine:: RCC_CFGR_MCO +.. doxygendefine:: RCC_CFGR_USBPRE +.. doxygendefine:: RCC_CFGR_PLLMUL +.. doxygendefine:: RCC_CFGR_PLLXTPRE +.. doxygendefine:: RCC_CFGR_PLLSRC +.. doxygendefine:: RCC_CFGR_ADCPRE +.. doxygendefine:: RCC_CFGR_PPRE2 +.. doxygendefine:: RCC_CFGR_PPRE1 +.. doxygendefine:: RCC_CFGR_HPRE +.. doxygendefine:: RCC_CFGR_SWS +.. doxygendefine:: RCC_CFGR_SWS_PLL +.. doxygendefine:: RCC_CFGR_SWS_HSE +.. doxygendefine:: RCC_CFGR_SW +.. doxygendefine:: RCC_CFGR_SW_PLL +.. doxygendefine:: RCC_CFGR_SW_HSE + +Clock interrupt register +~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_CIR_CSSC_BIT +.. doxygendefine:: RCC_CIR_PLLRDYC_BIT +.. doxygendefine:: RCC_CIR_HSERDYC_BIT +.. doxygendefine:: RCC_CIR_HSIRDYC_BIT +.. doxygendefine:: RCC_CIR_LSERDYC_BIT +.. doxygendefine:: RCC_CIR_LSIRDYC_BIT +.. doxygendefine:: RCC_CIR_PLLRDYIE_BIT +.. doxygendefine:: RCC_CIR_HSERDYIE_BIT +.. doxygendefine:: RCC_CIR_HSIRDYIE_BIT +.. doxygendefine:: RCC_CIR_LSERDYIE_BIT +.. doxygendefine:: RCC_CIR_LSIRDYIE_BIT +.. doxygendefine:: RCC_CIR_CSSF_BIT +.. doxygendefine:: RCC_CIR_PLLRDYF_BIT +.. doxygendefine:: RCC_CIR_HSERDYF_BIT +.. doxygendefine:: RCC_CIR_HSIRDYF_BIT +.. doxygendefine:: RCC_CIR_LSERDYF_BIT +.. doxygendefine:: RCC_CIR_LSIRDYF_BIT + +.. doxygendefine:: RCC_CIR_CSSC +.. doxygendefine:: RCC_CIR_PLLRDYC +.. doxygendefine:: RCC_CIR_HSERDYC +.. doxygendefine:: RCC_CIR_HSIRDYC +.. doxygendefine:: RCC_CIR_LSERDYC +.. doxygendefine:: RCC_CIR_LSIRDYC +.. doxygendefine:: RCC_CIR_PLLRDYIE +.. doxygendefine:: RCC_CIR_HSERDYIE +.. doxygendefine:: RCC_CIR_HSIRDYIE +.. doxygendefine:: RCC_CIR_LSERDYIE +.. doxygendefine:: RCC_CIR_LSIRDYIE +.. doxygendefine:: RCC_CIR_CSSF +.. doxygendefine:: RCC_CIR_PLLRDYF +.. doxygendefine:: RCC_CIR_HSERDYF +.. doxygendefine:: RCC_CIR_HSIRDYF +.. doxygendefine:: RCC_CIR_LSERDYF +.. doxygendefine:: RCC_CIR_LSIRDYF + +APB2 peripheral reset register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_APB2RSTR_TIM11RST_BIT +.. doxygendefine:: RCC_APB2RSTR_TIM10RST_BIT +.. doxygendefine:: RCC_APB2RSTR_TIM9RST_BIT +.. doxygendefine:: RCC_APB2RSTR_ADC3RST_BIT +.. doxygendefine:: RCC_APB2RSTR_USART1RST_BIT +.. doxygendefine:: RCC_APB2RSTR_TIM8RST_BIT +.. doxygendefine:: RCC_APB2RSTR_SPI1RST_BIT +.. doxygendefine:: RCC_APB2RSTR_TIM1RST_BIT +.. doxygendefine:: RCC_APB2RSTR_ADC2RST_BIT +.. doxygendefine:: RCC_APB2RSTR_ADC1RST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPGRST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPFRST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPERST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPDRST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPCRST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPBRST_BIT +.. doxygendefine:: RCC_APB2RSTR_IOPARST_BIT +.. doxygendefine:: RCC_APB2RSTR_AFIORST_BIT + +.. doxygendefine:: RCC_APB2RSTR_TIM11RST +.. doxygendefine:: RCC_APB2RSTR_TIM10RST +.. doxygendefine:: RCC_APB2RSTR_TIM9RST +.. doxygendefine:: RCC_APB2RSTR_ADC3RST +.. doxygendefine:: RCC_APB2RSTR_USART1RST +.. doxygendefine:: RCC_APB2RSTR_TIM8RST +.. doxygendefine:: RCC_APB2RSTR_SPI1RST +.. doxygendefine:: RCC_APB2RSTR_TIM1RST +.. doxygendefine:: RCC_APB2RSTR_ADC2RST +.. doxygendefine:: RCC_APB2RSTR_ADC1RST +.. doxygendefine:: RCC_APB2RSTR_IOPGRST +.. doxygendefine:: RCC_APB2RSTR_IOPFRST +.. doxygendefine:: RCC_APB2RSTR_IOPERST +.. doxygendefine:: RCC_APB2RSTR_IOPDRST +.. doxygendefine:: RCC_APB2RSTR_IOPCRST +.. doxygendefine:: RCC_APB2RSTR_IOPBRST +.. doxygendefine:: RCC_APB2RSTR_IOPARST +.. doxygendefine:: RCC_APB2RSTR_AFIORST + +APB1 peripheral reset register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_APB1RSTR_DACRST_BIT +.. doxygendefine:: RCC_APB1RSTR_PWRRST_BIT +.. doxygendefine:: RCC_APB1RSTR_BKPRST_BIT +.. doxygendefine:: RCC_APB1RSTR_CANRST_BIT +.. doxygendefine:: RCC_APB1RSTR_USBRST_BIT +.. doxygendefine:: RCC_APB1RSTR_I2C2RST_BIT +.. doxygendefine:: RCC_APB1RSTR_I2C1RST_BIT +.. doxygendefine:: RCC_APB1RSTR_UART5RST_BIT +.. doxygendefine:: RCC_APB1RSTR_UART4RST_BIT +.. doxygendefine:: RCC_APB1RSTR_USART3RST_BIT +.. doxygendefine:: RCC_APB1RSTR_USART2RST_BIT +.. doxygendefine:: RCC_APB1RSTR_SPI3RST_BIT +.. doxygendefine:: RCC_APB1RSTR_SPI2RST_BIT +.. doxygendefine:: RCC_APB1RSTR_WWDRST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM14RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM13RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM12RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM7RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM6RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM5RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM4RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM3RST_BIT +.. doxygendefine:: RCC_APB1RSTR_TIM2RST_BIT + +.. doxygendefine:: RCC_APB1RSTR_DACRST +.. doxygendefine:: RCC_APB1RSTR_PWRRST +.. doxygendefine:: RCC_APB1RSTR_BKPRST +.. doxygendefine:: RCC_APB1RSTR_CANRST +.. doxygendefine:: RCC_APB1RSTR_USBRST +.. doxygendefine:: RCC_APB1RSTR_I2C2RST +.. doxygendefine:: RCC_APB1RSTR_I2C1RST +.. doxygendefine:: RCC_APB1RSTR_UART5RST +.. doxygendefine:: RCC_APB1RSTR_UART4RST +.. doxygendefine:: RCC_APB1RSTR_USART3RST +.. doxygendefine:: RCC_APB1RSTR_USART2RST +.. doxygendefine:: RCC_APB1RSTR_SPI3RST +.. doxygendefine:: RCC_APB1RSTR_SPI2RST +.. doxygendefine:: RCC_APB1RSTR_WWDRST +.. doxygendefine:: RCC_APB1RSTR_TIM14RST +.. doxygendefine:: RCC_APB1RSTR_TIM13RST +.. doxygendefine:: RCC_APB1RSTR_TIM12RST +.. doxygendefine:: RCC_APB1RSTR_TIM7RST +.. doxygendefine:: RCC_APB1RSTR_TIM6RST +.. doxygendefine:: RCC_APB1RSTR_TIM5RST +.. doxygendefine:: RCC_APB1RSTR_TIM4RST +.. doxygendefine:: RCC_APB1RSTR_TIM3RST +.. doxygendefine:: RCC_APB1RSTR_TIM2RST + +AHB peripheral clock enable register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_AHBENR_SDIOEN_BIT +.. doxygendefine:: RCC_AHBENR_FSMCEN_BIT +.. doxygendefine:: RCC_AHBENR_CRCEN_BIT +.. doxygendefine:: RCC_AHBENR_FLITFEN_BIT +.. doxygendefine:: RCC_AHBENR_SRAMEN_BIT +.. doxygendefine:: RCC_AHBENR_DMA2EN_BIT +.. doxygendefine:: RCC_AHBENR_DMA1EN_BIT + +.. doxygendefine:: RCC_AHBENR_SDIOEN +.. doxygendefine:: RCC_AHBENR_FSMCEN +.. doxygendefine:: RCC_AHBENR_CRCEN +.. doxygendefine:: RCC_AHBENR_FLITFEN +.. doxygendefine:: RCC_AHBENR_SRAMEN +.. doxygendefine:: RCC_AHBENR_DMA2EN +.. doxygendefine:: RCC_AHBENR_DMA1EN + +APB2 peripheral clock enable register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_APB2ENR_TIM11EN_BIT +.. doxygendefine:: RCC_APB2ENR_TIM10EN_BIT +.. doxygendefine:: RCC_APB2ENR_TIM9EN_BIT +.. doxygendefine:: RCC_APB2ENR_ADC3EN_BIT +.. doxygendefine:: RCC_APB2ENR_USART1EN_BIT +.. doxygendefine:: RCC_APB2ENR_TIM8EN_BIT +.. doxygendefine:: RCC_APB2ENR_SPI1EN_BIT +.. doxygendefine:: RCC_APB2ENR_TIM1EN_BIT +.. doxygendefine:: RCC_APB2ENR_ADC2EN_BIT +.. doxygendefine:: RCC_APB2ENR_ADC1EN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPGEN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPFEN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPEEN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPDEN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPCEN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPBEN_BIT +.. doxygendefine:: RCC_APB2ENR_IOPAEN_BIT +.. doxygendefine:: RCC_APB2ENR_AFIOEN_BIT + +.. doxygendefine:: RCC_APB2ENR_TIM11EN +.. doxygendefine:: RCC_APB2ENR_TIM10EN +.. doxygendefine:: RCC_APB2ENR_TIM9EN +.. doxygendefine:: RCC_APB2ENR_ADC3EN +.. doxygendefine:: RCC_APB2ENR_USART1EN +.. doxygendefine:: RCC_APB2ENR_TIM8EN +.. doxygendefine:: RCC_APB2ENR_SPI1EN +.. doxygendefine:: RCC_APB2ENR_TIM1EN +.. doxygendefine:: RCC_APB2ENR_ADC2EN +.. doxygendefine:: RCC_APB2ENR_ADC1EN +.. doxygendefine:: RCC_APB2ENR_IOPGEN +.. doxygendefine:: RCC_APB2ENR_IOPFEN +.. doxygendefine:: RCC_APB2ENR_IOPEEN +.. doxygendefine:: RCC_APB2ENR_IOPDEN +.. doxygendefine:: RCC_APB2ENR_IOPCEN +.. doxygendefine:: RCC_APB2ENR_IOPBEN +.. doxygendefine:: RCC_APB2ENR_IOPAEN +.. doxygendefine:: RCC_APB2ENR_AFIOEN + +APB1 peripheral clock enable register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_APB1ENR_DACEN_BIT +.. doxygendefine:: RCC_APB1ENR_PWREN_BIT +.. doxygendefine:: RCC_APB1ENR_BKPEN_BIT +.. doxygendefine:: RCC_APB1ENR_CANEN_BIT +.. doxygendefine:: RCC_APB1ENR_USBEN_BIT +.. doxygendefine:: RCC_APB1ENR_I2C2EN_BIT +.. doxygendefine:: RCC_APB1ENR_I2C1EN_BIT +.. doxygendefine:: RCC_APB1ENR_UART5EN_BIT +.. doxygendefine:: RCC_APB1ENR_UART4EN_BIT +.. doxygendefine:: RCC_APB1ENR_USART3EN_BIT +.. doxygendefine:: RCC_APB1ENR_USART2EN_BIT +.. doxygendefine:: RCC_APB1ENR_SPI3EN_BIT +.. doxygendefine:: RCC_APB1ENR_SPI2EN_BIT +.. doxygendefine:: RCC_APB1ENR_WWDEN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM14EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM13EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM12EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM7EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM6EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM5EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM4EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM3EN_BIT +.. doxygendefine:: RCC_APB1ENR_TIM2EN_BIT + +.. doxygendefine:: RCC_APB1ENR_DACEN +.. doxygendefine:: RCC_APB1ENR_PWREN +.. doxygendefine:: RCC_APB1ENR_BKPEN +.. doxygendefine:: RCC_APB1ENR_CANEN +.. doxygendefine:: RCC_APB1ENR_USBEN +.. doxygendefine:: RCC_APB1ENR_I2C2EN +.. doxygendefine:: RCC_APB1ENR_I2C1EN +.. doxygendefine:: RCC_APB1ENR_UART5EN +.. doxygendefine:: RCC_APB1ENR_UART4EN +.. doxygendefine:: RCC_APB1ENR_USART3EN +.. doxygendefine:: RCC_APB1ENR_USART2EN +.. doxygendefine:: RCC_APB1ENR_SPI3EN +.. doxygendefine:: RCC_APB1ENR_SPI2EN +.. doxygendefine:: RCC_APB1ENR_WWDEN +.. doxygendefine:: RCC_APB1ENR_TIM14EN +.. doxygendefine:: RCC_APB1ENR_TIM13EN +.. doxygendefine:: RCC_APB1ENR_TIM12EN +.. doxygendefine:: RCC_APB1ENR_TIM7EN +.. doxygendefine:: RCC_APB1ENR_TIM6EN +.. doxygendefine:: RCC_APB1ENR_TIM5EN +.. doxygendefine:: RCC_APB1ENR_TIM4EN +.. doxygendefine:: RCC_APB1ENR_TIM3EN +.. doxygendefine:: RCC_APB1ENR_TIM2EN + +Backup domain control register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_BDCR_BDRST_BIT +.. doxygendefine:: RCC_BDCR_RTCEN_BIT +.. doxygendefine:: RCC_BDCR_LSEBYP_BIT +.. doxygendefine:: RCC_BDCR_LSERDY_BIT +.. doxygendefine:: RCC_BDCR_LSEON_BIT + +.. doxygendefine:: RCC_BDCR_BDRST +.. doxygendefine:: RCC_BDCR_RTCEN +.. doxygendefine:: RCC_BDCR_RTCSEL +.. doxygendefine:: RCC_BDCR_RTCSEL_NONE +.. doxygendefine:: RCC_BDCR_RTCSEL_LSE +.. doxygendefine:: RCC_BDCR_RTCSEL_HSE +.. doxygendefine:: RCC_BDCR_LSEBYP +.. doxygendefine:: RCC_BDCR_LSERDY +.. doxygendefine:: RCC_BDCR_LSEON + +Control/status register +~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: RCC_CSR_LPWRRSTF_BIT +.. doxygendefine:: RCC_CSR_WWDGRSTF_BIT +.. doxygendefine:: RCC_CSR_IWDGRSTF_BIT +.. doxygendefine:: RCC_CSR_SFTRSTF_BIT +.. doxygendefine:: RCC_CSR_PORRSTF_BIT +.. doxygendefine:: RCC_CSR_PINRSTF_BIT +.. doxygendefine:: RCC_CSR_RMVF_BIT +.. doxygendefine:: RCC_CSR_LSIRDY_BIT +.. doxygendefine:: RCC_CSR_LSION_BIT + +.. doxygendefine:: RCC_CSR_LPWRRSTF +.. doxygendefine:: RCC_CSR_WWDGRSTF +.. doxygendefine:: RCC_CSR_IWDGRSTF +.. doxygendefine:: RCC_CSR_SFTRSTF +.. doxygendefine:: RCC_CSR_PORRSTF +.. doxygendefine:: RCC_CSR_PINRSTF +.. doxygendefine:: RCC_CSR_RMVF +.. doxygendefine:: RCC_CSR_LSIRDY +.. doxygendefine:: RCC_CSR_LSION diff --git a/source/libmaple/api/ring_buffer.rst b/source/libmaple/api/ring_buffer.rst index a014fa4..e9b6637 100644 --- a/source/libmaple/api/ring_buffer.rst +++ b/source/libmaple/api/ring_buffer.rst @@ -4,9 +4,24 @@ ``ring_buffer.h`` ================= -[Stub] support. +Simple circular byte buffer. This implementation is not thread-safe. +In particular, none of these functions is guaranteed to be re-entrant. -Library Documentation ---------------------- +Ring Buffer Type +---------------- -.. doxygenfile:: ring_buffer.h +.. doxygenstruct:: ring_buffer + +Ring Buffer Operations +---------------------- + +.. doxygenfunction:: rb_init +.. doxygenfunction:: rb_full_count +.. doxygenfunction:: rb_is_full +.. doxygenfunction:: rb_is_empty +.. doxygenfunction:: rb_insert +.. doxygenfunction:: rb_remove +.. doxygenfunction:: rb_safe_remove +.. doxygenfunction:: rb_safe_insert +.. doxygenfunction:: rb_push_insert +.. doxygenfunction:: rb_reset diff --git a/source/libmaple/api/scb.rst b/source/libmaple/api/scb.rst index 78cc7eb..ff6f61b 100644 --- a/source/libmaple/api/scb.rst +++ b/source/libmaple/api/scb.rst @@ -4,9 +4,27 @@ ``scb.h`` ========= -[Stub] support. +System Control Block (SCB) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: scb.h +Types +----- + +.. doxygenstruct:: scb_reg_map + +Devices +------- + +None. + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: SCB_BASE + +Register Bit Definitions +------------------------ + +None at this time. diff --git a/source/libmaple/api/spi.rst b/source/libmaple/api/spi.rst index b0c7e86..e72696b 100644 --- a/source/libmaple/api/spi.rst +++ b/source/libmaple/api/spi.rst @@ -4,9 +4,184 @@ ``spi.h`` ========= -[Stub] support. +Serial Peripheral Interface (SPI) support. Currently, there is no I2S +support beyond register bit definitions. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: spi.h +Types +----- + +.. doxygenstruct:: spi_reg_map +.. doxygenstruct:: spi_dev +.. doxygenenum:: spi_mode +.. doxygenenum:: spi_baud_rate +.. doxygenenum:: spi_cfg_flag +.. doxygenenum:: spi_interrupt + +Devices +------- + +.. doxygenvariable:: SPI1 +.. doxygenvariable:: SPI2 +.. doxygenvariable:: SPI3 + +Functions +--------- + +.. doxygenfunction:: spi_init +.. doxygenfunction:: spi_gpio_cfg +.. doxygenfunction:: spi_master_enable +.. doxygenfunction:: spi_slave_enable +.. doxygenfunction:: spi_tx +.. doxygenfunction:: spi_foreach +.. doxygenfunction:: spi_peripheral_enable +.. doxygenfunction:: spi_peripheral_disable +.. doxygenfunction:: spi_peripheral_disable_all +.. doxygenfunction:: spi_tx_dma_enable +.. doxygenfunction:: spi_tx_dma_disable +.. doxygenfunction:: spi_rx_dma_enable +.. doxygenfunction:: spi_rx_dma_disable +.. doxygenfunction:: spi_is_enabled +.. doxygenfunction:: spi_irq_enable +.. doxygenfunction:: spi_irq_disable +.. doxygenfunction:: spi_dff +.. doxygenfunction:: spi_is_rx_nonempty +.. doxygenfunction:: spi_rx_reg +.. doxygenfunction:: spi_is_tx_empty +.. doxygenfunction:: spi_tx_reg +.. doxygenfunction:: spi_is_busy + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: SPI1_BASE +.. doxygendefine:: SPI2_BASE +.. doxygendefine:: SPI3_BASE + +Register Bit Definitions +------------------------ + +Control register 1 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: SPI_CR1_BIDIMODE_BIT +.. doxygendefine:: SPI_CR1_BIDIOE_BIT +.. doxygendefine:: SPI_CR1_CRCEN_BIT +.. doxygendefine:: SPI_CR1_CRCNEXT_BIT +.. doxygendefine:: SPI_CR1_DFF_BIT +.. doxygendefine:: SPI_CR1_RXONLY_BIT +.. doxygendefine:: SPI_CR1_SSM_BIT +.. doxygendefine:: SPI_CR1_SSI_BIT +.. doxygendefine:: SPI_CR1_LSBFIRST_BIT +.. doxygendefine:: SPI_CR1_SPE_BIT +.. doxygendefine:: SPI_CR1_MSTR_BIT +.. doxygendefine:: SPI_CR1_CPOL_BIT +.. doxygendefine:: SPI_CR1_CPHA_BIT + +.. doxygendefine:: SPI_CR1_BIDIMODE +.. doxygendefine:: SPI_CR1_BIDIMODE_2_LINE +.. doxygendefine:: SPI_CR1_BIDIMODE_1_LINE +.. doxygendefine:: SPI_CR1_BIDIOE +.. doxygendefine:: SPI_CR1_CRCEN +.. doxygendefine:: SPI_CR1_CRCNEXT +.. doxygendefine:: SPI_CR1_DFF +.. doxygendefine:: SPI_CR1_DFF_8_BIT +.. doxygendefine:: SPI_CR1_DFF_16_BIT +.. doxygendefine:: SPI_CR1_RXONLY +.. doxygendefine:: SPI_CR1_SSM +.. doxygendefine:: SPI_CR1_SSI +.. doxygendefine:: SPI_CR1_LSBFIRST +.. doxygendefine:: SPI_CR1_SPE +.. doxygendefine:: SPI_CR1_BR +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_2 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_4 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_8 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_16 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_32 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_64 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_128 +.. doxygendefine:: SPI_CR1_BR_PCLK_DIV_256 +.. doxygendefine:: SPI_CR1_MSTR +.. doxygendefine:: SPI_CR1_CPOL +.. doxygendefine:: SPI_CR1_CPOL_LOW +.. doxygendefine:: SPI_CR1_CPOL_HIGH +.. doxygendefine:: SPI_CR1_CPHA + +Control register 2 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: SPI_CR2_TXEIE_BIT +.. doxygendefine:: SPI_CR2_RXNEIE_BIT +.. doxygendefine:: SPI_CR2_ERRIE_BIT +.. doxygendefine:: SPI_CR2_SSOE_BIT +.. doxygendefine:: SPI_CR2_TXDMAEN_BIT +.. doxygendefine:: SPI_CR2_RXDMAEN_BIT + +.. doxygendefine:: SPI_CR2_TXEIE +.. doxygendefine:: SPI_CR2_RXNEIE +.. doxygendefine:: SPI_CR2_ERRIE +.. doxygendefine:: SPI_CR2_SSOE +.. doxygendefine:: SPI_CR2_TXDMAEN +.. doxygendefine:: SPI_CR2_RXDMAEN + +Status register +~~~~~~~~~~~~~~~ + +.. doxygendefine:: SPI_SR_BSY_BIT +.. doxygendefine:: SPI_SR_OVR_BIT +.. doxygendefine:: SPI_SR_MODF_BIT +.. doxygendefine:: SPI_SR_CRCERR_BIT +.. doxygendefine:: SPI_SR_UDR_BIT +.. doxygendefine:: SPI_SR_CHSIDE_BIT +.. doxygendefine:: SPI_SR_TXE_BIT +.. doxygendefine:: SPI_SR_RXNE_BIT + +.. doxygendefine:: SPI_SR_BSY +.. doxygendefine:: SPI_SR_OVR +.. doxygendefine:: SPI_SR_MODF +.. doxygendefine:: SPI_SR_CRCERR +.. doxygendefine:: SPI_SR_UDR +.. doxygendefine:: SPI_SR_CHSIDE +.. doxygendefine:: SPI_SR_CHSIDE_LEFT +.. doxygendefine:: SPI_SR_CHSIDE_RIGHT +.. doxygendefine:: SPI_SR_TXE +.. doxygendefine:: SPI_SR_RXNE + +I2S configuration register +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: SPI_I2SCFGR_I2SMOD_BIT +.. doxygendefine:: SPI_I2SCFGR_I2SE_BIT +.. doxygendefine:: SPI_I2SCFGR_PCMSYNC_BIT +.. doxygendefine:: SPI_I2SCFGR_CKPOL_BIT +.. doxygendefine:: SPI_I2SCFGR_CHLEN_BIT + +.. doxygendefine:: SPI_I2SCFGR_I2SMOD +.. doxygendefine:: SPI_I2SCFGR_I2SMOD_SPI +.. doxygendefine:: SPI_I2SCFGR_I2SMOD_I2S +.. doxygendefine:: SPI_I2SCFGR_I2SE +.. doxygendefine:: SPI_I2SCFGR_I2SCFG +.. doxygendefine:: SPI_I2SCFGR_I2SCFG_SLAVE_TX +.. doxygendefine:: SPI_I2SCFGR_I2SCFG_SLAVE_RX +.. doxygendefine:: SPI_I2SCFGR_I2SCFG_MASTER_TX +.. doxygendefine:: SPI_I2SCFGR_I2SCFG_MASTER_RX +.. doxygendefine:: SPI_I2SCFGR_PCMSYNC +.. doxygendefine:: SPI_I2SCFGR_PCMSYNC_SHORT +.. doxygendefine:: SPI_I2SCFGR_PCMSYNC_LONG +.. doxygendefine:: SPI_I2SCFGR_I2SSTD +.. doxygendefine:: SPI_I2SCFGR_I2SSTD_PHILLIPS +.. doxygendefine:: SPI_I2SCFGR_I2SSTD_MSB +.. doxygendefine:: SPI_I2SCFGR_I2SSTD_LSB +.. doxygendefine:: SPI_I2SCFGR_I2SSTD_PCM +.. doxygendefine:: SPI_I2SCFGR_CKPOL +.. doxygendefine:: SPI_I2SCFGR_CKPOL_LOW +.. doxygendefine:: SPI_I2SCFGR_CKPOL_HIGH +.. doxygendefine:: SPI_I2SCFGR_DATLEN +.. doxygendefine:: SPI_I2SCFGR_DATLEN_16_BIT +.. doxygendefine:: SPI_I2SCFGR_DATLEN_24_BIT +.. doxygendefine:: SPI_I2SCFGR_DATLEN_32_BIT +.. doxygendefine:: SPI_I2SCFGR_CHLEN +.. doxygendefine:: SPI_I2SCFGR_CHLEN_16_BIT +.. doxygendefine:: SPI_I2SCFGR_CHLEN_32_BIT diff --git a/source/libmaple/api/stm32.rst b/source/libmaple/api/stm32.rst index 2784540..82280bb 100644 --- a/source/libmaple/api/stm32.rst +++ b/source/libmaple/api/stm32.rst @@ -4,9 +4,16 @@ ``stm32.h`` =========== -[Stub] support. +General STM32-specific definitions. This file is currently somewhat +incomplete, but it will form the future basis for MCU-specific (rather +than board-specific, which belongs in :ref:`Wirish +<libmaple-vs-wirish>`) configuration. -Library Documentation ---------------------- +Defines +------- -.. doxygenfile:: stm32.h +.. doxygendefine:: PCLK1 +.. doxygendefine:: PCLK2 +.. doxygendefine:: NR_INTERRUPTS +.. doxygendefine:: NR_GPIO_PORTS +.. doxygendefine:: DELAY_US_MULT diff --git a/source/libmaple/api/systick.rst b/source/libmaple/api/systick.rst index fa959f2..8dab417 100644 --- a/source/libmaple/api/systick.rst +++ b/source/libmaple/api/systick.rst @@ -1,7 +1,6 @@ .. highlight:: c -.. FIXME [0.1.0] move these to the right places once Breathe is fast -.. enough to use for libmaple proper +.. FIXME [0.0.10] move these to the right places: .. _libmaple-systick_disable: @@ -12,9 +11,56 @@ ``systick.h`` ============= -[Stub] support. +System timer (SysTick) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: systick.h +Types +----- + +.. doxygenstruct:: systick_reg_map + +Devices +------- + +None. + +Functions +--------- + +.. doxygenfunction:: systick_init +.. doxygenfunction:: systick_enable +.. doxygenfunction:: systick_disable +.. doxygenfunction:: systick_uptime +.. doxygenfunction:: systick_get_count +.. doxygenfunction:: systick_check_underflow + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: SYSTICK_BASE + +Register Bit Definitions +------------------------ + +Control and status register +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: SYSTICK_CSR_COUNTFLAG +.. doxygendefine:: SYSTICK_CSR_CLKSOURCE +.. doxygendefine:: SYSTICK_CSR_CLKSOURCE_EXTERNAL +.. doxygendefine:: SYSTICK_CSR_CLKSOURCE_CORE +.. doxygendefine:: SYSTICK_CSR_TICKINT +.. doxygendefine:: SYSTICK_CSR_TICKINT_PEND +.. doxygendefine:: SYSTICK_CSR_TICKINT_NO_PEND +.. doxygendefine:: SYSTICK_CSR_ENABLE +.. doxygendefine:: SYSTICK_CSR_ENABLE_MULTISHOT +.. doxygendefine:: SYSTICK_CSR_ENABLE_DISABLED + +Calibration value register +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: SYSTICK_CVR_NOREF +.. doxygendefine:: SYSTICK_CVR_SKEW +.. doxygendefine:: SYSTICK_CVR_TENMS diff --git a/source/libmaple/api/timer.rst b/source/libmaple/api/timer.rst index 3acbf4f..f315cb0 100644 --- a/source/libmaple/api/timer.rst +++ b/source/libmaple/api/timer.rst @@ -4,9 +4,450 @@ ``timer.h`` =========== -[Stub] support. +Timer support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: timer.h +Types +----- + +The timer register map type, unlike that for most other peripherals in +libmaple, is a union rather than a struct. This is due to the fact +that there are advanced, general purpose, and basic timers. Thus, +each kind of timer has a register map type, and a ``union +timer_reg_map`` ties it all together. + +.. doxygenstruct:: timer_adv_reg_map +.. doxygenstruct:: timer_gen_reg_map +.. doxygenstruct:: timer_bas_reg_map +.. doxygenunion:: timer_reg_map +.. doxygenenum:: timer_type +.. doxygenstruct:: timer_dev +.. doxygenenum:: timer_mode +.. doxygenenum:: timer_channel +.. doxygenenum:: timer_interrupt_id +.. doxygenenum:: timer_dma_base_addr +.. doxygenenum:: timer_oc_mode +.. doxygenenum:: timer_oc_mode_flags + +Devices +------- + +.. doxygenvariable:: TIMER1 +.. doxygenvariable:: TIMER2 +.. doxygenvariable:: TIMER3 +.. doxygenvariable:: TIMER4 +.. doxygenvariable:: TIMER5 +.. doxygenvariable:: TIMER6 +.. doxygenvariable:: TIMER7 +.. doxygenvariable:: TIMER8 + +Functions +--------- + +Enabling and Disabling +~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygenfunction:: timer_init +.. doxygenfunction:: timer_init_all +.. doxygenfunction:: timer_disable +.. doxygenfunction:: timer_disable_all + +General Configuration +~~~~~~~~~~~~~~~~~~~~~ + +.. doxygenfunction:: timer_set_mode +.. doxygenfunction:: timer_foreach + +Count and Prescaler +~~~~~~~~~~~~~~~~~~~ + +.. doxygenfunction:: timer_get_count +.. doxygenfunction:: timer_set_count +.. doxygenfunction:: timer_pause +.. doxygenfunction:: timer_resume +.. doxygenfunction:: timer_generate_update +.. doxygenfunction:: timer_get_prescaler +.. doxygenfunction:: timer_set_prescaler +.. doxygenfunction:: timer_get_reload +.. doxygenfunction:: timer_set_reload + +Interrupts +~~~~~~~~~~ + +.. doxygenfunction:: timer_attach_interrupt +.. doxygenfunction:: timer_detach_interrupt +.. doxygenfunction:: timer_enable_irq +.. doxygenfunction:: timer_disable_irq + +Capture/Compare +~~~~~~~~~~~~~~~ + +.. doxygenfunction:: timer_get_compare +.. doxygenfunction:: timer_set_compare +.. doxygenfunction:: timer_cc_enable +.. doxygenfunction:: timer_cc_disable +.. doxygenfunction:: timer_cc_get_pol +.. doxygenfunction:: timer_cc_set_pol +.. doxygenfunction:: timer_oc_set_mode + +DMA +~~~ + +.. doxygenfunction:: timer_dma_enable_trg_req +.. doxygenfunction:: timer_dma_disable_trg_req +.. doxygenfunction:: timer_dma_enable_req +.. doxygenfunction:: timer_dma_get_burst_len +.. doxygenfunction:: timer_dma_set_burst_len +.. doxygenfunction:: timer_dma_get_base_addr +.. doxygenfunction:: timer_dma_set_base_addr + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: TIMER1_BASE +.. doxygendefine:: TIMER2_BASE +.. doxygendefine:: TIMER3_BASE +.. doxygendefine:: TIMER4_BASE +.. doxygendefine:: TIMER5_BASE +.. doxygendefine:: TIMER6_BASE +.. doxygendefine:: TIMER7_BASE +.. doxygendefine:: TIMER8_BASE + +Register Bit Definitions +------------------------ + +Control register 1 (CR1) +~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_CR1_ARPE_BIT +.. doxygendefine:: TIMER_CR1_DIR_BIT +.. doxygendefine:: TIMER_CR1_OPM_BIT +.. doxygendefine:: TIMER_CR1_URS_BIT +.. doxygendefine:: TIMER_CR1_UDIS_BIT +.. doxygendefine:: TIMER_CR1_CEN_BIT + +.. doxygendefine:: TIMER_CR1_CKD +.. doxygendefine:: TIMER_CR1_CKD_1TCKINT +.. doxygendefine:: TIMER_CR1_CKD_2TCKINT +.. doxygendefine:: TIMER_CR1_CKD_4TICKINT +.. doxygendefine:: TIMER_CR1_ARPE +.. doxygendefine:: TIMER_CR1_CKD_CMS +.. doxygendefine:: TIMER_CR1_CKD_CMS_EDGE +.. doxygendefine:: TIMER_CR1_CKD_CMS_CENTER1 +.. doxygendefine:: TIMER_CR1_CKD_CMS_CENTER2 +.. doxygendefine:: TIMER_CR1_CKD_CMS_CENTER3 +.. doxygendefine:: TIMER_CR1_DIR +.. doxygendefine:: TIMER_CR1_OPM +.. doxygendefine:: TIMER_CR1_URS +.. doxygendefine:: TIMER_CR1_UDIS +.. doxygendefine:: TIMER_CR1_CEN + +Control register 2 (CR2) +~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_CR2_OIS4_BIT +.. doxygendefine:: TIMER_CR2_OIS3N_BIT +.. doxygendefine:: TIMER_CR2_OIS3_BIT +.. doxygendefine:: TIMER_CR2_OIS2N_BIT +.. doxygendefine:: TIMER_CR2_OIS2_BIT +.. doxygendefine:: TIMER_CR2_OIS1N_BIT +.. doxygendefine:: TIMER_CR2_OIS1_BIT +.. doxygendefine:: TIMER_CR2_TI1S_BIT +.. doxygendefine:: TIMER_CR2_CCDS_BIT +.. doxygendefine:: TIMER_CR2_CCUS_BIT +.. doxygendefine:: TIMER_CR2_CCPC_BIT + +.. doxygendefine:: TIMER_CR2_OIS4 +.. doxygendefine:: TIMER_CR2_OIS3N +.. doxygendefine:: TIMER_CR2_OIS3 +.. doxygendefine:: TIMER_CR2_OIS2N +.. doxygendefine:: TIMER_CR2_OIS2 +.. doxygendefine:: TIMER_CR2_OIS1N +.. doxygendefine:: TIMER_CR2_OIS1 +.. doxygendefine:: TIMER_CR2_TI1S +.. doxygendefine:: TIMER_CR2_MMS +.. doxygendefine:: TIMER_CR2_MMS_RESET +.. doxygendefine:: TIMER_CR2_MMS_ENABLE +.. doxygendefine:: TIMER_CR2_MMS_UPDATE +.. doxygendefine:: TIMER_CR2_MMS_COMPARE_PULSE +.. doxygendefine:: TIMER_CR2_MMS_COMPARE_OC1REF +.. doxygendefine:: TIMER_CR2_MMS_COMPARE_OC2REF +.. doxygendefine:: TIMER_CR2_MMS_COMPARE_OC3REF +.. doxygendefine:: TIMER_CR2_MMS_COMPARE_OC4REF +.. doxygendefine:: TIMER_CR2_CCDS +.. doxygendefine:: TIMER_CR2_CCUS +.. doxygendefine:: TIMER_CR2_CCPC + +Slave mode control register (SMCR) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_SMCR_ETP_BIT +.. doxygendefine:: TIMER_SMCR_ECE_BIT +.. doxygendefine:: TIMER_SMCR_MSM_BIT + +.. doxygendefine:: TIMER_SMCR_ETP +.. doxygendefine:: TIMER_SMCR_ECE +.. doxygendefine:: TIMER_SMCR_ETPS +.. doxygendefine:: TIMER_SMCR_ETPS_OFF +.. doxygendefine:: TIMER_SMCR_ETPS_DIV2 +.. doxygendefine:: TIMER_SMCR_ETPS_DIV4 +.. doxygendefine:: TIMER_SMCR_ETPS_DIV8 +.. doxygendefine:: TIMER_SMCR_ETF +.. doxygendefine:: TIMER_SMCR_MSM +.. doxygendefine:: TIMER_SMCR_TS +.. doxygendefine:: TIMER_SMCR_TS_ITR0 +.. doxygendefine:: TIMER_SMCR_TS_ITR1 +.. doxygendefine:: TIMER_SMCR_TS_ITR2 +.. doxygendefine:: TIMER_SMCR_TS_ITR3 +.. doxygendefine:: TIMER_SMCR_TS_TI1F_ED +.. doxygendefine:: TIMER_SMCR_TS_TI1FP1 +.. doxygendefine:: TIMER_SMCR_TS_TI2FP2 +.. doxygendefine:: TIMER_SMCR_TS_ETRF +.. doxygendefine:: TIMER_SMCR_SMS +.. doxygendefine:: TIMER_SMCR_SMS_DISABLED +.. doxygendefine:: TIMER_SMCR_SMS_ENCODER1 +.. doxygendefine:: TIMER_SMCR_SMS_ENCODER2 +.. doxygendefine:: TIMER_SMCR_SMS_ENCODER3 +.. doxygendefine:: TIMER_SMCR_SMS_RESET +.. doxygendefine:: TIMER_SMCR_SMS_GATED +.. doxygendefine:: TIMER_SMCR_SMS_TRIGGER +.. doxygendefine:: TIMER_SMCR_SMS_EXTERNAL + +DMA/Interrupt enable register (DIER) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_DIER_TDE_BIT +.. doxygendefine:: TIMER_DIER_CC4DE_BIT +.. doxygendefine:: TIMER_DIER_CC3DE_BIT +.. doxygendefine:: TIMER_DIER_CC2DE_BIT +.. doxygendefine:: TIMER_DIER_CC1DE_BIT +.. doxygendefine:: TIMER_DIER_UDE_BIT +.. doxygendefine:: TIMER_DIER_TIE_BIT +.. doxygendefine:: TIMER_DIER_CC4IE_BIT +.. doxygendefine:: TIMER_DIER_CC3IE_BIT +.. doxygendefine:: TIMER_DIER_CC2IE_BIT +.. doxygendefine:: TIMER_DIER_CC1IE_BIT +.. doxygendefine:: TIMER_DIER_UIE_BIT + +.. doxygendefine:: TIMER_DIER_TDE +.. doxygendefine:: TIMER_DIER_CC4DE +.. doxygendefine:: TIMER_DIER_CC3DE +.. doxygendefine:: TIMER_DIER_CC2DE +.. doxygendefine:: TIMER_DIER_CC1DE +.. doxygendefine:: TIMER_DIER_UDE +.. doxygendefine:: TIMER_DIER_TIE +.. doxygendefine:: TIMER_DIER_CC4IE +.. doxygendefine:: TIMER_DIER_CC3IE +.. doxygendefine:: TIMER_DIER_CC2IE +.. doxygendefine:: TIMER_DIER_CC1IE +.. doxygendefine:: TIMER_DIER_UIE + +Status register (SR) +~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_SR_CC4OF_BIT +.. doxygendefine:: TIMER_SR_CC3OF_BIT +.. doxygendefine:: TIMER_SR_CC2OF_BIT +.. doxygendefine:: TIMER_SR_CC1OF_BIT +.. doxygendefine:: TIMER_SR_BIF_BIT +.. doxygendefine:: TIMER_SR_TIF_BIT +.. doxygendefine:: TIMER_SR_COMIF_BIT +.. doxygendefine:: TIMER_SR_CC4IF_BIT +.. doxygendefine:: TIMER_SR_CC3IF_BIT +.. doxygendefine:: TIMER_SR_CC2IF_BIT +.. doxygendefine:: TIMER_SR_CC1IF_BIT +.. doxygendefine:: TIMER_SR_UIF_BIT + +.. doxygendefine:: TIMER_SR_CC4OF +.. doxygendefine:: TIMER_SR_CC3OF +.. doxygendefine:: TIMER_SR_CC2OF +.. doxygendefine:: TIMER_SR_CC1OF +.. doxygendefine:: TIMER_SR_BIF +.. doxygendefine:: TIMER_SR_TIF +.. doxygendefine:: TIMER_SR_COMIF +.. doxygendefine:: TIMER_SR_CC4IF +.. doxygendefine:: TIMER_SR_CC3IF +.. doxygendefine:: TIMER_SR_CC2IF +.. doxygendefine:: TIMER_SR_CC1IF +.. doxygendefine:: TIMER_SR_UIF + +Event generation register (EGR) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_EGR_TG_BIT +.. doxygendefine:: TIMER_EGR_CC4G_BIT +.. doxygendefine:: TIMER_EGR_CC3G_BIT +.. doxygendefine:: TIMER_EGR_CC2G_BIT +.. doxygendefine:: TIMER_EGR_CC1G_BIT +.. doxygendefine:: TIMER_EGR_UG_BIT + +.. doxygendefine:: TIMER_EGR_TG +.. doxygendefine:: TIMER_EGR_CC4G +.. doxygendefine:: TIMER_EGR_CC3G +.. doxygendefine:: TIMER_EGR_CC2G +.. doxygendefine:: TIMER_EGR_CC1G +.. doxygendefine:: TIMER_EGR_UG + +Capture/compare mode registers, common values +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_CCMR_CCS_OUTPUT +.. doxygendefine:: TIMER_CCMR_CCS_INPUT_TI1 +.. doxygendefine:: TIMER_CCMR_CCS_INPUT_TI2 +.. doxygendefine:: TIMER_CCMR_CCS_INPUT_TRC + +Capture/compare mode register 1 (CCMR1) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_CCMR1_OC2CE_BIT +.. doxygendefine:: TIMER_CCMR1_OC2PE_BIT +.. doxygendefine:: TIMER_CCMR1_OC2FE_BIT +.. doxygendefine:: TIMER_CCMR1_OC1CE_BIT +.. doxygendefine:: TIMER_CCMR1_OC1PE_BIT +.. doxygendefine:: TIMER_CCMR1_OC1FE_BIT + +.. doxygendefine:: TIMER_CCMR1_OC2CE +.. doxygendefine:: TIMER_CCMR1_OC2M +.. doxygendefine:: TIMER_CCMR1_IC2F +.. doxygendefine:: TIMER_CCMR1_OC2PE +.. doxygendefine:: TIMER_CCMR1_OC2FE +.. doxygendefine:: TIMER_CCMR1_IC2PSC +.. doxygendefine:: TIMER_CCMR1_CC2S +.. doxygendefine:: TIMER_CCMR1_CC2S_OUTPUT +.. doxygendefine:: TIMER_CCMR1_CC2S_INPUT_TI1 +.. doxygendefine:: TIMER_CCMR1_CC2S_INPUT_TI2 +.. doxygendefine:: TIMER_CCMR1_CC2S_INPUT_TRC +.. doxygendefine:: TIMER_CCMR1_OC1CE +.. doxygendefine:: TIMER_CCMR1_OC1M +.. doxygendefine:: TIMER_CCMR1_IC1F +.. doxygendefine:: TIMER_CCMR1_OC1PE +.. doxygendefine:: TIMER_CCMR1_OC1FE +.. doxygendefine:: TIMER_CCMR1_IC1PSC +.. doxygendefine:: TIMER_CCMR1_CC1S +.. doxygendefine:: TIMER_CCMR1_CC1S_OUTPUT +.. doxygendefine:: TIMER_CCMR1_CC1S_INPUT_TI1 +.. doxygendefine:: TIMER_CCMR1_CC1S_INPUT_TI2 +.. doxygendefine:: TIMER_CCMR1_CC1S_INPUT_TRC + +Capture/compare mode register 2 (CCMR2) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_CCMR2_OC4CE_BIT +.. doxygendefine:: TIMER_CCMR2_OC4PE_BIT +.. doxygendefine:: TIMER_CCMR2_OC4FE_BIT +.. doxygendefine:: TIMER_CCMR2_OC3CE_BIT +.. doxygendefine:: TIMER_CCMR2_OC3PE_BIT +.. doxygendefine:: TIMER_CCMR2_OC3FE_BIT + +.. doxygendefine:: TIMER_CCMR2_OC4CE +.. doxygendefine:: TIMER_CCMR2_OC4M +.. doxygendefine:: TIMER_CCMR2_IC2F +.. doxygendefine:: TIMER_CCMR2_OC4PE +.. doxygendefine:: TIMER_CCMR2_OC4FE +.. doxygendefine:: TIMER_CCMR2_IC2PSC +.. doxygendefine:: TIMER_CCMR2_CC4S +.. doxygendefine:: TIMER_CCMR1_CC4S_OUTPUT +.. doxygendefine:: TIMER_CCMR1_CC4S_INPUT_TI1 +.. doxygendefine:: TIMER_CCMR1_CC4S_INPUT_TI2 +.. doxygendefine:: TIMER_CCMR1_CC4S_INPUT_TRC +.. doxygendefine:: TIMER_CCMR2_OC3CE +.. doxygendefine:: TIMER_CCMR2_OC3M +.. doxygendefine:: TIMER_CCMR2_IC1F +.. doxygendefine:: TIMER_CCMR2_OC3PE +.. doxygendefine:: TIMER_CCMR2_OC3FE +.. doxygendefine:: TIMER_CCMR2_IC1PSC +.. doxygendefine:: TIMER_CCMR2_CC3S +.. doxygendefine:: TIMER_CCMR1_CC3S_OUTPUT +.. doxygendefine:: TIMER_CCMR1_CC3S_INPUT_TI1 +.. doxygendefine:: TIMER_CCMR1_CC3S_INPUT_TI2 +.. doxygendefine:: TIMER_CCMR1_CC3S_INPUT_TRC + +Capture/compare enable register (CCER) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_CCER_CC4P_BIT +.. doxygendefine:: TIMER_CCER_CC4E_BIT +.. doxygendefine:: TIMER_CCER_CC3P_BIT +.. doxygendefine:: TIMER_CCER_CC3E_BIT +.. doxygendefine:: TIMER_CCER_CC2P_BIT +.. doxygendefine:: TIMER_CCER_CC2E_BIT +.. doxygendefine:: TIMER_CCER_CC1P_BIT +.. doxygendefine:: TIMER_CCER_CC1E_BIT + +.. doxygendefine:: TIMER_CCER_CC4P +.. doxygendefine:: TIMER_CCER_CC4E +.. doxygendefine:: TIMER_CCER_CC3P +.. doxygendefine:: TIMER_CCER_CC3E +.. doxygendefine:: TIMER_CCER_CC2P +.. doxygendefine:: TIMER_CCER_CC2E +.. doxygendefine:: TIMER_CCER_CC1P +.. doxygendefine:: TIMER_CCER_CC1E + +Break and dead-time register (BDTR) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_BDTR_MOE_BIT +.. doxygendefine:: TIMER_BDTR_AOE_BIT +.. doxygendefine:: TIMER_BDTR_BKP_BIT +.. doxygendefine:: TIMER_BDTR_BKE_BIT +.. doxygendefine:: TIMER_BDTR_OSSR_BIT +.. doxygendefine:: TIMER_BDTR_OSSI_BIT + +.. doxygendefine:: TIMER_BDTR_MOE +.. doxygendefine:: TIMER_BDTR_AOE +.. doxygendefine:: TIMER_BDTR_BKP +.. doxygendefine:: TIMER_BDTR_BKE +.. doxygendefine:: TIMER_BDTR_OSSR +.. doxygendefine:: TIMER_BDTR_OSSI +.. doxygendefine:: TIMER_BDTR_LOCK +.. doxygendefine:: TIMER_BDTR_LOCK_OFF +.. doxygendefine:: TIMER_BDTR_LOCK_LEVEL1 +.. doxygendefine:: TIMER_BDTR_LOCK_LEVEL2 +.. doxygendefine:: TIMER_BDTR_LOCK_LEVEL3 +.. doxygendefine:: TIMER_BDTR_DTG + +DMA control register (DCR) +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: TIMER_DCR_DBL +.. doxygendefine:: TIMER_DCR_DBL_1BYTE +.. doxygendefine:: TIMER_DCR_DBL_2BYTE +.. doxygendefine:: TIMER_DCR_DBL_3BYTE +.. doxygendefine:: TIMER_DCR_DBL_4BYTE +.. doxygendefine:: TIMER_DCR_DBL_5BYTE +.. doxygendefine:: TIMER_DCR_DBL_6BYTE +.. doxygendefine:: TIMER_DCR_DBL_7BYTE +.. doxygendefine:: TIMER_DCR_DBL_8BYTE +.. doxygendefine:: TIMER_DCR_DBL_9BYTE +.. doxygendefine:: TIMER_DCR_DBL_10BYTE +.. doxygendefine:: TIMER_DCR_DBL_11BYTE +.. doxygendefine:: TIMER_DCR_DBL_12BYTE +.. doxygendefine:: TIMER_DCR_DBL_13BYTE +.. doxygendefine:: TIMER_DCR_DBL_14BYTE +.. doxygendefine:: TIMER_DCR_DBL_15BYTE +.. doxygendefine:: TIMER_DCR_DBL_16BYTE +.. doxygendefine:: TIMER_DCR_DBL_17BYTE +.. doxygendefine:: TIMER_DCR_DBL_18BYTE +.. doxygendefine:: TIMER_DCR_DBA +.. doxygendefine:: TIMER_DCR_DBA_CR1 +.. doxygendefine:: TIMER_DCR_DBA_CR2 +.. doxygendefine:: TIMER_DCR_DBA_SMCR +.. doxygendefine:: TIMER_DCR_DBA_DIER +.. doxygendefine:: TIMER_DCR_DBA_SR +.. doxygendefine:: TIMER_DCR_DBA_EGR +.. doxygendefine:: TIMER_DCR_DBA_CCMR1 +.. doxygendefine:: TIMER_DCR_DBA_CCMR2 +.. doxygendefine:: TIMER_DCR_DBA_CCER +.. doxygendefine:: TIMER_DCR_DBA_CNT +.. doxygendefine:: TIMER_DCR_DBA_PSC +.. doxygendefine:: TIMER_DCR_DBA_ARR +.. doxygendefine:: TIMER_DCR_DBA_RCR +.. doxygendefine:: TIMER_DCR_DBA_CCR1 +.. doxygendefine:: TIMER_DCR_DBA_CCR2 +.. doxygendefine:: TIMER_DCR_DBA_CCR3 +.. doxygendefine:: TIMER_DCR_DBA_CCR4 +.. doxygendefine:: TIMER_DCR_DBA_BDTR +.. doxygendefine:: TIMER_DCR_DBA_DCR +.. doxygendefine:: TIMER_DCR_DBA_DMAR diff --git a/source/libmaple/api/usart.rst b/source/libmaple/api/usart.rst index 26e6b9c..1575a8f 100644 --- a/source/libmaple/api/usart.rst +++ b/source/libmaple/api/usart.rst @@ -4,9 +4,193 @@ ``usart.h`` =========== -[Stub] support. +Universal Synchronous/Asynchronous Receiver/Transmitter (USART, or +commonly *serial port*) support. -Library Documentation ---------------------- +.. contents:: Contents + :local: -.. doxygenfile:: usart.h +Types +----- + +.. doxygenstruct:: usart_reg_map +.. doxygenstruct:: usart_dev + +Devices +------- + +.. doxygenvariable:: USART1 +.. doxygenvariable:: USART2 +.. doxygenvariable:: USART3 +.. doxygenvariable:: UART4 +.. doxygenvariable:: UART5 + +Functions +--------- + +.. doxygenfunction:: usart_init +.. doxygenfunction:: usart_set_baud_rate +.. doxygenfunction:: usart_enable +.. doxygenfunction:: usart_disable +.. doxygenfunction:: usart_disable_all +.. doxygenfunction:: usart_foreach +.. doxygenfunction:: usart_tx +.. doxygenfunction:: usart_putudec +.. doxygenfunction:: usart_putc +.. doxygenfunction:: usart_putstr +.. doxygenfunction:: usart_getc +.. doxygenfunction:: usart_data_available +.. doxygenfunction:: usart_reset_rx + +Register Map Base Pointers +-------------------------- + +.. doxygendefine:: USART1_BASE +.. doxygendefine:: USART2_BASE +.. doxygendefine:: USART3_BASE +.. doxygendefine:: UART4_BASE +.. doxygendefine:: UART5_BASE + +Register Bit Definitions +------------------------ + +Status Register +~~~~~~~~~~~~~~~ + +.. doxygendefine:: USART_SR_CTS_BIT +.. doxygendefine:: USART_SR_LBD_BIT +.. doxygendefine:: USART_SR_TXE_BIT +.. doxygendefine:: USART_SR_TC_BIT +.. doxygendefine:: USART_SR_RXNE_BIT +.. doxygendefine:: USART_SR_IDLE_BIT +.. doxygendefine:: USART_SR_ORE_BIT +.. doxygendefine:: USART_SR_NE_BIT +.. doxygendefine:: USART_SR_FE_BIT +.. doxygendefine:: USART_SR_PE_BIT + +.. doxygendefine:: USART_SR_CTS +.. doxygendefine:: USART_SR_LBD +.. doxygendefine:: USART_SR_TXE +.. doxygendefine:: USART_SR_TC +.. doxygendefine:: USART_SR_RXNE +.. doxygendefine:: USART_SR_IDLE +.. doxygendefine:: USART_SR_ORE +.. doxygendefine:: USART_SR_NE +.. doxygendefine:: USART_SR_FE +.. doxygendefine:: USART_SR_PE + +Data register +~~~~~~~~~~~~~ + +.. doxygendefine:: USART_DR_DR + +Baud Rate Register +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: USART_BRR_DIV_MANTISSA +.. doxygendefine:: USART_BRR_DIV_FRACTION + +Control Register 1 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: USART_CR1_UE_BIT +.. doxygendefine:: USART_CR1_M_BIT +.. doxygendefine:: USART_CR1_WAKE_BIT +.. doxygendefine:: USART_CR1_PCE_BIT +.. doxygendefine:: USART_CR1_PS_BIT +.. doxygendefine:: USART_CR1_PEIE_BIT +.. doxygendefine:: USART_CR1_TXEIE_BIT +.. doxygendefine:: USART_CR1_TCIE_BIT +.. doxygendefine:: USART_CR1_RXNEIE_BIT +.. doxygendefine:: USART_CR1_IDLEIE_BIT +.. doxygendefine:: USART_CR1_TE_BIT +.. doxygendefine:: USART_CR1_RE_BIT +.. doxygendefine:: USART_CR1_RWU_BIT +.. doxygendefine:: USART_CR1_SBK_BIT + +.. doxygendefine:: USART_CR1_UE +.. doxygendefine:: USART_CR1_M +.. doxygendefine:: USART_CR1_WAKE +.. doxygendefine:: USART_CR1_WAKE_IDLE +.. doxygendefine:: USART_CR1_WAKE_ADDR +.. doxygendefine:: USART_CR1_PCE +.. doxygendefine:: USART_CR1_PS +.. doxygendefine:: USART_CR1_PS_EVEN +.. doxygendefine:: USART_CR1_PS_ODD +.. doxygendefine:: USART_CR1_PEIE +.. doxygendefine:: USART_CR1_TXEIE +.. doxygendefine:: USART_CR1_TCIE +.. doxygendefine:: USART_CR1_RXNEIE +.. doxygendefine:: USART_CR1_IDLEIE +.. doxygendefine:: USART_CR1_TE +.. doxygendefine:: USART_CR1_RE +.. doxygendefine:: USART_CR1_RWU +.. doxygendefine:: USART_CR1_RWU_ACTIVE +.. doxygendefine:: USART_CR1_RWU_MUTE +.. doxygendefine:: USART_CR1_SBK + +Control Register 2 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: USART_CR2_LINEN_BIT +.. doxygendefine:: USART_CR2_CLKEN_BIT +.. doxygendefine:: USART_CR2_CPOL_BIT +.. doxygendefine:: USART_CR2_CPHA_BIT +.. doxygendefine:: USART_CR2_LBCL_BIT +.. doxygendefine:: USART_CR2_LBDIE_BIT +.. doxygendefine:: USART_CR2_LBDL_BIT + +.. doxygendefine:: USART_CR2_LINEN +.. doxygendefine:: USART_CR2_STOP +.. doxygendefine:: USART_CR2_STOP_BITS_1 +.. doxygendefine:: USART_CR2_STOP_BITS_POINT_5 +.. doxygendefine:: USART_CR2_STOP_BITS_1_POINT_5 +.. doxygendefine:: USART_CR2_STOP_BITS_2 +.. doxygendefine:: USART_CR2_CLKEN +.. doxygendefine:: USART_CR2_CPOL +.. doxygendefine:: USART_CR2_CPOL_LOW +.. doxygendefine:: USART_CR2_CPOL_HIGH +.. doxygendefine:: USART_CR2_CPHA +.. doxygendefine:: USART_CR2_CPHA_FIRST +.. doxygendefine:: USART_CR2_CPHA_SECOND +.. doxygendefine:: USART_CR2_LBCL +.. doxygendefine:: USART_CR2_LBDIE +.. doxygendefine:: USART_CR2_LBDL +.. doxygendefine:: USART_CR2_LBDL_10_BIT +.. doxygendefine:: USART_CR2_LBDL_11_BIT +.. doxygendefine:: USART_CR2_ADD + +Control Register 3 +~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: USART_CR3_CTSIE_BIT +.. doxygendefine:: USART_CR3_CTSE_BIT +.. doxygendefine:: USART_CR3_RTSE_BIT +.. doxygendefine:: USART_CR3_DMAT_BIT +.. doxygendefine:: USART_CR3_DMAR_BIT +.. doxygendefine:: USART_CR3_SCEN_BIT +.. doxygendefine:: USART_CR3_NACK_BIT +.. doxygendefine:: USART_CR3_HDSEL_BIT +.. doxygendefine:: USART_CR3_IRLP_BIT +.. doxygendefine:: USART_CR3_IREN_BIT +.. doxygendefine:: USART_CR3_EIE_BIT + +.. doxygendefine:: USART_CR3_CTSIE +.. doxygendefine:: USART_CR3_CTSE +.. doxygendefine:: USART_CR3_RTSE +.. doxygendefine:: USART_CR3_DMAT +.. doxygendefine:: USART_CR3_DMAR +.. doxygendefine:: USART_CR3_SCEN +.. doxygendefine:: USART_CR3_NACK +.. doxygendefine:: USART_CR3_HDSEL +.. doxygendefine:: USART_CR3_IRLP +.. doxygendefine:: USART_CR3_IRLP_NORMAL +.. doxygendefine:: USART_CR3_IRLP_LOW_POWER +.. doxygendefine:: USART_CR3_IREN +.. doxygendefine:: USART_CR3_EIE + +Guard Time and Prescaler Register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. doxygendefine:: USART_GTPR_GT +.. doxygendefine:: USART_GTPR_PSC diff --git a/source/libmaple/api/util.rst b/source/libmaple/api/util.rst index 50ffe76..06c9246 100644 --- a/source/libmaple/api/util.rst +++ b/source/libmaple/api/util.rst @@ -4,9 +4,48 @@ ``util.h`` ========== -[Stub] support. +.. TODO [0.2.0?] clean this up. -Library Documentation ---------------------- +Miscellaneous utility macros and procedures. -.. doxygenfile:: util.h +.. contents:: Contents + :local: + +Bit Manipulation +---------------- + +:: + + #define BIT(shift) (1UL << (shift)) + #define BIT_MASK_SHIFT(mask, shift) ((mask) << (shift)) + /** Gets bits m to n of x */ + #define GET_BITS(x, m, n) ((((uint32)x) << (31 - (n))) >> ((31 - (n)) + (m))) + #define IS_POWER_OF_TWO(v) (v && !(v & (v - 1))) + +Failure Routines +---------------- + +.. doxygenfunction:: throb + +Asserts and Debug Levels +------------------------ + +The level of libmaple's assertion support is determined by +``DEBUG_LEVEL``, as follows: + +.. doxygendefine:: DEBUG_LEVEL + +The current assert macros are ``ASSERT()`` and ``ASSERT_FAULT()``. +``ASSERT()`` is checked when ``DEBUG_LEVEL >= DEBUG_ALL``. +``ASSERT_FAULT()`` is checked whenever ``DEBUG_LEVEL >= DEBUG_FAULT``. + +As explained above, an assert macro is checked when the current +``DEBUG_LEVEL`` is high enough. If the debug level is too low, the +macro expands into a no-op that gets compiled away. + +If an assertion fails, execution is halted at the point of the failed +assertion. When libmaple has been configured properly (Wirish +performs this configuration by default), the built-in LED throbs in a +smooth pattern to signal the failed assertion (using +:c:func:`throb()`), and the file and line where the assert failed are +transmitted to the user as detailed in :ref:`lang-assert`. |