diff options
Diffstat (limited to 'libmaple')
| -rw-r--r-- | libmaple/include/libmaple/scb.h | 120 |
1 files changed, 60 insertions, 60 deletions
diff --git a/libmaple/include/libmaple/scb.h b/libmaple/include/libmaple/scb.h index 9abcb13..77b9629 100644 --- a/libmaple/include/libmaple/scb.h +++ b/libmaple/include/libmaple/scb.h @@ -2,7 +2,7 @@ * The MIT License * * Copyright (c) 2010 Perry Hung. - * Copyright (c) 2011 LeafLabs, LLC. + * Copyright (c) 2011-2012 LeafLabs, LLC. * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation @@ -99,14 +99,14 @@ typedef struct scb_reg_map { /* Interrupt control state register (SCB_ICSR) */ -#define SCB_ICSR_NMIPENDSET BIT(31) -#define SCB_ICSR_PENDSVSET BIT(28) -#define SCB_ICSR_PENDSVCLR BIT(27) -#define SCB_ICSR_PENDSTSET BIT(26) -#define SCB_ICSR_PENDSTCLR BIT(25) -#define SCB_ICSR_ISRPENDING BIT(22) +#define SCB_ICSR_NMIPENDSET (1U << 31) +#define SCB_ICSR_PENDSVSET (1U << 28) +#define SCB_ICSR_PENDSVCLR (1U << 27) +#define SCB_ICSR_PENDSTSET (1U << 26) +#define SCB_ICSR_PENDSTCLR (1U << 25) +#define SCB_ICSR_ISRPENDING (1U << 22) #define SCB_ICSR_VECTPENDING (0x3FF << 12) -#define SCB_ICSR_RETOBASE BIT(11) +#define SCB_ICSR_RETOBASE (1U << 11) #define SCB_ICSR_VECTACTIVE 0xFF /* Vector table offset register (SCB_VTOR) */ @@ -117,26 +117,26 @@ typedef struct scb_reg_map { #define SCB_AIRCR_VECTKEYSTAT (0x5FA << 16) #define SCB_AIRCR_VECTKEY (0x5FA << 16) -#define SCB_AIRCR_ENDIANNESS BIT(15) +#define SCB_AIRCR_ENDIANNESS (1U << 15) #define SCB_AIRCR_PRIGROUP (0x3 << 8) -#define SCB_AIRCR_SYSRESETREQ BIT(2) -#define SCB_AIRCR_VECTCLRACTIVE BIT(1) -#define SCB_AIRCR_VECTRESET BIT(0) +#define SCB_AIRCR_SYSRESETREQ (1U << 2) +#define SCB_AIRCR_VECTCLRACTIVE (1U << 1) +#define SCB_AIRCR_VECTRESET (1U << 0) /* System control register (SCB_SCR) */ -#define SCB_SCR_SEVONPEND BIT(4) -#define SCB_SCR_SLEEPDEEP BIT(2) -#define SCB_SCR_SLEEPONEXIT BIT(1) +#define SCB_SCR_SEVONPEND (1U << 4) +#define SCB_SCR_SLEEPDEEP (1U << 2) +#define SCB_SCR_SLEEPONEXIT (1U << 1) /* Configuration and Control Register (SCB_CCR) */ -#define SCB_CCR_STKALIGN BIT(9) -#define SCB_CCR_BFHFNMIGN BIT(8) -#define SCB_CCR_DIV_0_TRP BIT(4) -#define SCB_CCR_UNALIGN_TRP BIT(3) -#define SCB_CCR_USERSETMPEND BIT(1) -#define SCB_CCR_NONBASETHRDENA BIT(0) +#define SCB_CCR_STKALIGN (1U << 9) +#define SCB_CCR_BFHFNMIGN (1U << 8) +#define SCB_CCR_DIV_0_TRP (1U << 4) +#define SCB_CCR_UNALIGN_TRP (1U << 3) +#define SCB_CCR_USERSETMPEND (1U << 1) +#define SCB_CCR_NONBASETHRDENA (1U << 0) /* System handler priority registers (SCB_SHPRx) */ @@ -151,57 +151,57 @@ typedef struct scb_reg_map { /* System Handler Control and state register (SCB_SHCSR) */ -#define SCB_SHCSR_USGFAULTENA BIT(18) -#define SCB_SHCSR_BUSFAULTENA BIT(17) -#define SCB_SHCSR_MEMFAULTENA BIT(16) -#define SCB_SHCSR_SVCALLPENDED BIT(15) -#define SCB_SHCSR_BUSFAULTPENDED BIT(14) -#define SCB_SHCSR_MEMFAULTPENDED BIT(13) -#define SCB_SHCSR_USGFAULTPENDED BIT(12) -#define SCB_SHCSR_SYSTICKACT BIT(11) -#define SCB_SHCSR_PENDSVACT BIT(10) -#define SCB_SHCSR_MONITORACT BIT(8) -#define SCB_SHCSR_SVCALLACT BIT(7) -#define SCB_SHCSR_USGFAULTACT BIT(3) -#define SCB_SHCSR_BUSFAULTACT BIT(1) -#define SCB_SHCSR_MEMFAULTACT BIT(0) +#define SCB_SHCSR_USGFAULTENA (1U << 18) +#define SCB_SHCSR_BUSFAULTENA (1U << 17) +#define SCB_SHCSR_MEMFAULTENA (1U << 16) +#define SCB_SHCSR_SVCALLPENDED (1U << 15) +#define SCB_SHCSR_BUSFAULTPENDED (1U << 14) +#define SCB_SHCSR_MEMFAULTPENDED (1U << 13) +#define SCB_SHCSR_USGFAULTPENDED (1U << 12) +#define SCB_SHCSR_SYSTICKACT (1U << 11) +#define SCB_SHCSR_PENDSVACT (1U << 10) +#define SCB_SHCSR_MONITORACT (1U << 8) +#define SCB_SHCSR_SVCALLACT (1U << 7) +#define SCB_SHCSR_USGFAULTACT (1U << 3) +#define SCB_SHCSR_BUSFAULTACT (1U << 1) +#define SCB_SHCSR_MEMFAULTACT (1U << 0) /* Configurable fault status register (SCB_CFSR) */ -#define SCB_CFSR_DIVBYZERO BIT(25) -#define SCB_CFSR_UNALIGNED BIT(24) -#define SCB_CFSR_NOCP BIT(19) -#define SCB_CFSR_INVPC BIT(18) -#define SCB_CFSR_INVSTATE BIT(17) -#define SCB_CFSR_UNDEFINSTR BIT(16) -#define SCB_CFSR_BFARVALID BIT(15) -#define SCB_CFSR_STKERR BIT(12) -#define SCB_CFSR_UNSTKERR BIT(11) -#define SCB_CFSR_IMPRECISERR BIT(10) -#define SCB_CFSR_PRECISERR BIT(9) -#define SCB_CFSR_IBUSERR BIT(8) -#define SCB_CFSR_MMARVALID BIT(7) -#define SCB_CFSR_MSTKERR BIT(4) -#define SCB_CFSR_MUNSTKERR BIT(3) -#define SCB_CFSR_DACCVIOL BIT(1) -#define SCB_CFSR_IACCVIOL BIT(0) +#define SCB_CFSR_DIVBYZERO (1U << 25) +#define SCB_CFSR_UNALIGNED (1U << 24) +#define SCB_CFSR_NOCP (1U << 19) +#define SCB_CFSR_INVPC (1U << 18) +#define SCB_CFSR_INVSTATE (1U << 17) +#define SCB_CFSR_UNDEFINSTR (1U << 16) +#define SCB_CFSR_BFARVALID (1U << 15) +#define SCB_CFSR_STKERR (1U << 12) +#define SCB_CFSR_UNSTKERR (1U << 11) +#define SCB_CFSR_IMPRECISERR (1U << 10) +#define SCB_CFSR_PRECISERR (1U << 9) +#define SCB_CFSR_IBUSERR (1U << 8) +#define SCB_CFSR_MMARVALID (1U << 7) +#define SCB_CFSR_MSTKERR (1U << 4) +#define SCB_CFSR_MUNSTKERR (1U << 3) +#define SCB_CFSR_DACCVIOL (1U << 1) +#define SCB_CFSR_IACCVIOL (1U << 0) /* Hard Fault Status Register (SCB_HFSR) */ -#define SCB_HFSR_DEBUG_VT BIT(31) -#define SCB_CFSR_FORCED BIT(30) -#define SCB_CFSR_VECTTBL BIT(1) +#define SCB_HFSR_DEBUG_VT (1U << 31) +#define SCB_CFSR_FORCED (1U << 30) +#define SCB_CFSR_VECTTBL (1U << 1) /* Debug Fault Status Register */ /* Not specified by PM0056, but required by ARM. The bit definitions * here are based on the names given in the ARM v7-M ARM. */ -#define SCB_DFSR_EXTERNAL BIT(4) -#define SCB_DFSR_VCATCH BIT(3) -#define SCB_DFSR_DWTTRAP BIT(2) -#define SCB_DFSR_BKPT BIT(1) -#define SCB_DFSR_HALTED BIT(0) +#define SCB_DFSR_EXTERNAL (1U << 4) +#define SCB_DFSR_VCATCH (1U << 3) +#define SCB_DFSR_DWTTRAP (1U << 2) +#define SCB_DFSR_BKPT (1U << 1) +#define SCB_DFSR_HALTED (1U << 0) #ifdef __cplusplus } |